arch/alpha/include/asm/io.h
161
REMAP2(u32, writel, volatile)
arch/alpha/include/asm/io.h
247
extern void writel(u32 b, volatile void __iomem *addr);
arch/alpha/include/asm/io.h
255
#define writel writel
arch/alpha/include/asm/io.h
502
IO_CONCAT(__IO_PREFIX,writel)(b, addr);
arch/alpha/include/asm/io.h
594
#define writel_relaxed writel
arch/alpha/include/asm/io_trivial.h
128
IO_CONCAT(__IO_PREFIX,writel)(u32 b, volatile void __iomem *a)
arch/alpha/kernel/io.c
155
IO_CONCAT(__IO_PREFIX,writel)(b, addr);
arch/alpha/kernel/io.c
238
EXPORT_SYMBOL(writel);
arch/arc/plat-hsdk/platform.c
209
writel(0x77777777, CREG_AXI_M_SLV0(M_DMAC_0));
arch/arc/plat-hsdk/platform.c
210
writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_DMAC_0));
arch/arc/plat-hsdk/platform.c
211
writel(axi_m_slv1, CREG_AXI_M_SLV1(M_DMAC_0));
arch/arc/plat-hsdk/platform.c
212
writel(axi_m_oft1, CREG_AXI_M_OFT1(M_DMAC_0));
arch/arc/plat-hsdk/platform.c
213
writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_DMAC_0));
arch/arc/plat-hsdk/platform.c
215
writel(0x77777777, CREG_AXI_M_SLV0(M_DMAC_1));
arch/arc/plat-hsdk/platform.c
216
writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_DMAC_1));
arch/arc/plat-hsdk/platform.c
217
writel(axi_m_slv1, CREG_AXI_M_SLV1(M_DMAC_1));
arch/arc/plat-hsdk/platform.c
218
writel(axi_m_oft1, CREG_AXI_M_OFT1(M_DMAC_1));
arch/arc/plat-hsdk/platform.c
219
writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_DMAC_1));
arch/arc/plat-hsdk/platform.c
232
writel(reg, CREG_AXI_M_HS_CORE_BOOT);
arch/arc/plat-hsdk/platform.c
233
writel(0x11111111, CREG_AXI_M_SLV0(M_HS_CORE));
arch/arc/plat-hsdk/platform.c
234
writel(0x63111111, CREG_AXI_M_SLV1(M_HS_CORE));
arch/arc/plat-hsdk/platform.c
235
writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HS_CORE));
arch/arc/plat-hsdk/platform.c
236
writel(0x0E543210, CREG_AXI_M_OFT1(M_HS_CORE));
arch/arc/plat-hsdk/platform.c
237
writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HS_CORE));
arch/arc/plat-hsdk/platform.c
239
writel(0x77777777, CREG_AXI_M_SLV0(M_HS_RTT));
arch/arc/plat-hsdk/platform.c
240
writel(0x77777777, CREG_AXI_M_SLV1(M_HS_RTT));
arch/arc/plat-hsdk/platform.c
241
writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HS_RTT));
arch/arc/plat-hsdk/platform.c
242
writel(0x76543210, CREG_AXI_M_OFT1(M_HS_RTT));
arch/arc/plat-hsdk/platform.c
243
writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HS_RTT));
arch/arc/plat-hsdk/platform.c
245
writel(0x88888888, CREG_AXI_M_SLV0(M_AXI_TUN));
arch/arc/plat-hsdk/platform.c
246
writel(0x88888888, CREG_AXI_M_SLV1(M_AXI_TUN));
arch/arc/plat-hsdk/platform.c
247
writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_AXI_TUN));
arch/arc/plat-hsdk/platform.c
248
writel(0x76543210, CREG_AXI_M_OFT1(M_AXI_TUN));
arch/arc/plat-hsdk/platform.c
249
writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_AXI_TUN));
arch/arc/plat-hsdk/platform.c
251
writel(0x77777777, CREG_AXI_M_SLV0(M_HDMI_VIDEO));
arch/arc/plat-hsdk/platform.c
252
writel(0x77777777, CREG_AXI_M_SLV1(M_HDMI_VIDEO));
arch/arc/plat-hsdk/platform.c
253
writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HDMI_VIDEO));
arch/arc/plat-hsdk/platform.c
254
writel(0x76543210, CREG_AXI_M_OFT1(M_HDMI_VIDEO));
arch/arc/plat-hsdk/platform.c
255
writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HDMI_VIDEO));
arch/arc/plat-hsdk/platform.c
257
writel(0x77777777, CREG_AXI_M_SLV0(M_HDMI_AUDIO));
arch/arc/plat-hsdk/platform.c
258
writel(0x77777777, CREG_AXI_M_SLV1(M_HDMI_AUDIO));
arch/arc/plat-hsdk/platform.c
259
writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HDMI_AUDIO));
arch/arc/plat-hsdk/platform.c
260
writel(0x76543210, CREG_AXI_M_OFT1(M_HDMI_AUDIO));
arch/arc/plat-hsdk/platform.c
261
writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HDMI_AUDIO));
arch/arc/plat-hsdk/platform.c
263
writel(0x77777777, CREG_AXI_M_SLV0(M_USB_HOST));
arch/arc/plat-hsdk/platform.c
264
writel(0x77999999, CREG_AXI_M_SLV1(M_USB_HOST));
arch/arc/plat-hsdk/platform.c
265
writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_USB_HOST));
arch/arc/plat-hsdk/platform.c
266
writel(0x76DCBA98, CREG_AXI_M_OFT1(M_USB_HOST));
arch/arc/plat-hsdk/platform.c
267
writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_USB_HOST));
arch/arc/plat-hsdk/platform.c
269
writel(0x77777777, CREG_AXI_M_SLV0(M_ETHERNET));
arch/arc/plat-hsdk/platform.c
270
writel(0x77999999, CREG_AXI_M_SLV1(M_ETHERNET));
arch/arc/plat-hsdk/platform.c
271
writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_ETHERNET));
arch/arc/plat-hsdk/platform.c
272
writel(0x76DCBA98, CREG_AXI_M_OFT1(M_ETHERNET));
arch/arc/plat-hsdk/platform.c
273
writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_ETHERNET));
arch/arc/plat-hsdk/platform.c
275
writel(0x77777777, CREG_AXI_M_SLV0(M_SDIO));
arch/arc/plat-hsdk/platform.c
276
writel(0x77999999, CREG_AXI_M_SLV1(M_SDIO));
arch/arc/plat-hsdk/platform.c
277
writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_SDIO));
arch/arc/plat-hsdk/platform.c
278
writel(0x76DCBA98, CREG_AXI_M_OFT1(M_SDIO));
arch/arc/plat-hsdk/platform.c
279
writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_SDIO));
arch/arc/plat-hsdk/platform.c
281
writel(0x77777777, CREG_AXI_M_SLV0(M_GPU));
arch/arc/plat-hsdk/platform.c
282
writel(0x77777777, CREG_AXI_M_SLV1(M_GPU));
arch/arc/plat-hsdk/platform.c
283
writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_GPU));
arch/arc/plat-hsdk/platform.c
284
writel(0x76543210, CREG_AXI_M_OFT1(M_GPU));
arch/arc/plat-hsdk/platform.c
285
writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_GPU));
arch/arc/plat-hsdk/platform.c
287
writel(0x00000000, CREG_AXI_M_SLV0(M_DVFS));
arch/arc/plat-hsdk/platform.c
288
writel(0x60000000, CREG_AXI_M_SLV1(M_DVFS));
arch/arc/plat-hsdk/platform.c
289
writel(0x00000000, CREG_AXI_M_OFT0(M_DVFS));
arch/arc/plat-hsdk/platform.c
290
writel(0x00000000, CREG_AXI_M_OFT1(M_DVFS));
arch/arc/plat-hsdk/platform.c
291
writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_DVFS));
arch/arc/plat-hsdk/platform.c
301
writel(0x00000000, CREG_PAE);
arch/arc/plat-hsdk/platform.c
302
writel(UPDATE_VAL, CREG_PAE_UPDT);
arch/arm/common/sa1111.c
264
writel(ie, mapbase + SA1111_INTEN0);
arch/arm/include/asm/cachetype.h
100
writel(cache_selector, BASEADDR_V7M_SCB + V7M_SCB_CTR);
arch/arm/kernel/io.c
36
writel(value, reg);
arch/arm/mach-actions/platsmp.c
68
writel(__pa_symbol(secondary_startup),
arch/arm/mach-actions/platsmp.c
70
writel(OWL_CPUx_FLAG_BOOT,
arch/arm/mach-actions/platsmp.c
91
writel(0, timer_base_addr + OWL_CPU1_ADDR + (cpu - 1) * 4);
arch/arm/mach-actions/platsmp.c
92
writel(0, timer_base_addr + OWL_CPU1_FLAG + (cpu - 1) * 4);
arch/arm/mach-alpine/alpine_cpu_pm.c
35
writel(phys_resume_addr,
arch/arm/mach-at91/pm.c
261
writel(mode, soc_pm.data.pmc + AT91_PMC_FSMR);
arch/arm/mach-at91/pm.c
318
writel(mode, pmc + AT91_PMC_FSMR);
arch/arm/mach-at91/pm.c
319
writel(polarity, pmc + AT91_PMC_FSPR);
arch/arm/mach-at91/pm.c
326
writel(mode, pmc + AT91_PMC_FSMR);
arch/arm/mach-at91/pm.c
636
writel(val, soc_pm.data.sfrbu + offset);
arch/arm/mach-at91/pm.c
859
writel(pwrtmg | UDDRC_PWRCTL_SELFREF_EN,
arch/arm/mach-at91/pm.c
862
writel(ratio & ~AT91_PMC_RATIO_RATIO, soc_pm.data.pmc + AT91_PMC_RATIO);
arch/arm/mach-at91/pm.c
867
writel(ratio, soc_pm.data.pmc + AT91_PMC_RATIO);
arch/arm/mach-at91/pm.c
868
writel(pwrtmg, soc_pm.data.ramc[0] + UDDRC_PWRCTL);
arch/arm/mach-at91/pm.c
971
writel(AT91_PMC_PCK, soc_pm.data.pmc + AT91_PMC_SCDR);
arch/arm/mach-at91/pm.c
976
writel(AT91_PMC_PCK, soc_pm.data.pmc + AT91_PMC_SCDR);
arch/arm/mach-axxia/platsmp.c
47
writel(0xab, syscon + SC_CRIT_WRITE_KEY);
arch/arm/mach-axxia/platsmp.c
49
writel(tmp, syscon + SC_RST_CPU_HOLD);
arch/arm/mach-bcm/bcm_kona_smc.c
130
writel(data->arg3, args);
arch/arm/mach-bcm/board_bcm281xx.c
43
writel(val, base + SECWDOG_OFFSET);
arch/arm/mach-bcm/platsmp-brcmstb.c
91
writel((readl(base) & mask) | val, base);
arch/arm/mach-bcm/platsmp-brcmstb.c
97
writel((readl(base) & mask) & ~val, base);
arch/arm/mach-bcm/platsmp.c
306
writel(virt_to_phys(secondary_startup),
arch/arm/mach-berlin/platsmp.c
113
writel(val, cpu_ctrl + CPU_RESET_NON_SC);
arch/arm/mach-berlin/platsmp.c
39
writel(val, cpu_ctrl + CPU_RESET_NON_SC);
arch/arm/mach-berlin/platsmp.c
41
writel(val, cpu_ctrl + CPU_RESET_NON_SC);
arch/arm/mach-berlin/platsmp.c
86
writel(boot_inst, vectors_base + RESET_VECT);
arch/arm/mach-berlin/platsmp.c
92
writel(__pa_symbol(secondary_startup), vectors_base + SW_RESET_ADDR);
arch/arm/mach-dove/common.c
440
writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
arch/arm/mach-dove/common.c
445
writel(SOFT_RESET, SYSTEM_SOFT_RESET);
arch/arm/mach-dove/mpp.c
111
writel(mpp_ctrl4, DOVE_MPP_CTRL4_VIRT_BASE);
arch/arm/mach-dove/mpp.c
112
writel(ssp_ctrl1, DOVE_SSP_CTRL_STATUS_1);
arch/arm/mach-dove/mpp.c
113
writel(mpp_gen_ctrl, DOVE_MPP_GENERAL_VIRT_BASE);
arch/arm/mach-dove/mpp.c
114
writel(global_cfg_2, DOVE_GLOBAL_CONFIG_2);
arch/arm/mach-dove/mpp.c
140
writel(mpp_ctrl4, DOVE_MPP_CTRL4_VIRT_BASE);
arch/arm/mach-dove/mpp.c
74
writel(mpp_gen_cfg, DOVE_MPP_GENERAL_VIRT_BASE);
arch/arm/mach-exynos/firmware.c
127
writel(0, sysram_ns_base_addr + EXYNOS_BOOT_FLAG);
arch/arm/mach-exynos/firmware.c
136
writel(EXYNOS_SLEEP_MAGIC, sysram_ns_base_addr + EXYNOS_BOOT_FLAG);
arch/arm/mach-exynos/firmware.c
137
writel(__pa_symbol(exynos_cpu_resume_ns),
arch/arm/mach-exynos/firmware.c
145
writel(0, sysram_ns_base_addr + EXYNOS_BOOT_FLAG);
arch/arm/mach-highbank/highbank.c
100
writel(val | 0xff01, sregs_base + reg);
arch/arm/mach-highbank/sysregs.h
47
writel(HB_PWR_SUSPEND, sregs_base + HB_SREG_A9_PWR_REQ);
arch/arm/mach-highbank/sysregs.h
53
writel(HB_PWR_SHUTDOWN, sregs_base + HB_SREG_A9_PWR_REQ);
arch/arm/mach-highbank/sysregs.h
59
writel(HB_PWR_SOFT_RESET, sregs_base + HB_SREG_A9_PWR_REQ);
arch/arm/mach-highbank/sysregs.h
65
writel(HB_PWR_HARD_RESET, sregs_base + HB_SREG_A9_PWR_REQ);
arch/arm/mach-highbank/sysregs.h
71
writel(~0UL, sregs_base + HB_SREG_A9_PWR_REQ);
arch/arm/mach-imx/mmdc.c
344
writel(DBG_RST, reg);
arch/arm/mach-imx/mmdc.c
351
writel(val, reg);
arch/arm/mach-imx/mmdc.c
358
writel(val, reg);
arch/arm/mach-imx/mmdc.c
390
writel(PRF_FRZ, reg);
arch/arm/mach-imx/mmdc.c
393
writel(MMDC_PRF_AXI_ID_CLEAR, reg);
arch/arm/mach-imx/pm-imx6.c
264
writel(val, ccm_base + CCR);
arch/arm/mach-lpc32xx/serial.c
89
writel(tmp, LPC32XX_UARTCTL_CLOOP);
arch/arm/mach-mediatek/mediatek.c
31
writel(GPT_ENABLE, gpt_base);
arch/arm/mach-meson/platsmp.c
124
writel(__pa_symbol(secondary_startup),
arch/arm/mach-meson/platsmp.c
147
writel(__pa_symbol(secondary_startup),
arch/arm/mach-meson/platsmp.c
57
writel(val, sram_base + MESON_SMP_SRAM_CPU_CTRL_REG);
arch/arm/mach-milbeaut/platsmp.c
40
writel(__pa_symbol(secondary_startup), m10v_smp_base + cpu * 4);
arch/arm/mach-milbeaut/platsmp.c
65
writel(KERNEL_UNBOOT_FLAG, m10v_smp_base + cpu * 4);
arch/arm/mach-milbeaut/platsmp.c
83
writel(KERNEL_UNBOOT_FLAG, m10v_smp_base + cpu * 4);
arch/arm/mach-mv78xx0/common.c
435
writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
arch/arm/mach-mv78xx0/common.c
440
writel(SOFT_RESET, SYSTEM_SOFT_RESET);
arch/arm/mach-mvebu/coherency.c
88
writel(reg, cpu_config_base);
arch/arm/mach-mvebu/cpu-reset.c
36
writel(reg, cpu_reset_base + CPU_RESET_OFFSET(cpu));
arch/arm/mach-mvebu/kirkwood.c
155
writel(readl(cpu_config) & ~CPU_CONFIG_ERROR_PROP, cpu_config);
arch/arm/mach-mvebu/platsmp.c
208
writel(0, base + MV98DX3236_CPU_RESUME_CTRL_REG);
arch/arm/mach-mvebu/platsmp.c
209
writel(__pa_symbol(boot_addr), base + MV98DX3236_CPU_RESUME_ADDR_REG);
arch/arm/mach-mvebu/pm-board.c
36
writel(reg, gpio_ctrl);
arch/arm/mach-mvebu/pm.c
121
writel(BOOT_MAGIC_WORD, store_addr++);
arch/arm/mach-mvebu/pm.c
122
writel(resume_pc, store_addr++);
arch/arm/mach-mvebu/pm.c
130
writel(MBUS_WINDOW_12_CTRL, store_addr++);
arch/arm/mach-mvebu/pm.c
131
writel(0x0, store_addr++);
arch/arm/mach-mvebu/pm.c
137
writel(MBUS_INTERNAL_REG_ADDRESS, store_addr++);
arch/arm/mach-mvebu/pm.c
138
writel(mvebu_internal_reg_base(), store_addr++);
arch/arm/mach-mvebu/pm.c
147
writel(BOOT_MAGIC_LIST_END, store_addr);
arch/arm/mach-mvebu/pm.c
52
writel(reg, sdram_ctrl + SDRAM_DLB_EVICTION_OFFS);
arch/arm/mach-mvebu/pm.c
59
writel(reg, sdram_ctrl + SDRAM_CONFIG_OFFS);
arch/arm/mach-mvebu/pmsu.c
112
writel(__pa_symbol(boot_addr), pmsu_mp_base +
arch/arm/mach-mvebu/pmsu.c
214
writel(reg, pmsu_mp_base + L2C_NFABRIC_PM_CTL);
arch/arm/mach-mvebu/pmsu.c
244
writel(reg, pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu));
arch/arm/mach-mvebu/pmsu.c
253
writel(reg, pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu));
arch/arm/mach-mvebu/pmsu.c
259
writel(reg, pmsu_mp_base + PMSU_CPU_POWER_DOWN_CONTROL(hw_cpu));
arch/arm/mach-mvebu/pmsu.c
349
writel(reg, pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu));
arch/arm/mach-mvebu/pmsu.c
357
writel(reg, pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu));
arch/arm/mach-mvebu/pmsu.c
453
writel(reg, mpsoc_base + MPCORE_RESET_CTL);
arch/arm/mach-mvebu/pmsu.c
461
writel(reg, pmsu_mp_base + PMSU_POWERDOWN_DELAY);
arch/arm/mach-mvebu/pmsu.c
548
writel(reg, pmsu_mp_base + PMSU_STATUS_AND_MASK(cpu));
arch/arm/mach-mvebu/pmsu.c
553
writel(reg, pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(cpu));
arch/arm/mach-mvebu/pmsu.c
564
writel(reg, pmsu_mp_base + PMSU_STATUS_AND_MASK(cpu));
arch/arm/mach-mvebu/pmsu.c
578
writel(reg, pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu));
arch/arm/mach-mvebu/pmsu.c
583
writel(reg, pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu));
arch/arm/mach-mvebu/pmsu.c
604
writel(reg, pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu));
arch/arm/mach-mvebu/system-controller.c
105
writel(mvebu_sc->system_soft_reset,
arch/arm/mach-mvebu/system-controller.c
153
writel(__pa_symbol(boot_addr), system_controller_base +
arch/arm/mach-mvebu/system-controller.c
99
writel(mvebu_sc->rstoutn_mask_reset_out_en,
arch/arm/mach-nomadik/cpu-8815.c
81
writel(1, srcbase + 0x18);
arch/arm/mach-omap1/time.c
103
writel(MPU_TIMER_CLOCK_ENABLE, &timer->cntl);
arch/arm/mach-omap1/time.c
105
writel(load_val, &timer->load_tim);
arch/arm/mach-omap1/time.c
107
writel(timerflags, &timer->cntl);
arch/arm/mach-omap1/time.c
114
writel(readl(&timer->cntl) & ~MPU_TIMER_ST, &timer->cntl);
arch/arm/mach-omap1/time.c
84
writel(readl(&timer->cntl) | MPU_TIMER_AR, &timer->cntl);
arch/arm/mach-omap1/time.c
91
writel(readl(&timer->cntl) & ~MPU_TIMER_AR, &timer->cntl);
arch/arm/mach-orion5x/board-mss2.c
75
writel(reg, RSTOUTn_MASK);
arch/arm/mach-orion5x/board-mss2.c
79
writel(reg, CPU_SOFT_RESET);
arch/arm/mach-orion5x/common.h
89
#define orion5x_setbits(r, mask) writel(readl(r) | (mask), (r))
arch/arm/mach-orion5x/common.h
90
#define orion5x_clrbits(r, mask) writel(readl(r) & ~(mask), (r))
arch/arm/mach-orion5x/dns323-setup.c
582
writel((3 << 21) /* phy ID reg */ |
arch/arm/mach-orion5x/dns323-setup.c
627
writel(0, MPP_DEV_CTRL); /* DEV_D[31:16] */
arch/arm/mach-orion5x/dns323-setup.c
740
writel(0x5, ORION5X_SATA_VIRT_BASE + 0x2c);
arch/arm/mach-orion5x/kurobox_pro-setup.c
213
writel(buf[i++], UART1_REG(TX));
arch/arm/mach-orion5x/kurobox_pro-setup.c
297
writel(0x83, UART1_REG(LCR));
arch/arm/mach-orion5x/kurobox_pro-setup.c
298
writel(divisor & 0xff, UART1_REG(DLL));
arch/arm/mach-orion5x/kurobox_pro-setup.c
299
writel((divisor >> 8) & 0xff, UART1_REG(DLM));
arch/arm/mach-orion5x/kurobox_pro-setup.c
300
writel(0x1b, UART1_REG(LCR));
arch/arm/mach-orion5x/kurobox_pro-setup.c
301
writel(0x00, UART1_REG(IER));
arch/arm/mach-orion5x/kurobox_pro-setup.c
302
writel(0x07, UART1_REG(FCR));
arch/arm/mach-orion5x/kurobox_pro-setup.c
303
writel(0x00, UART1_REG(MCR));
arch/arm/mach-orion5x/pci.c
279
writel(PCI_CONF_BUS(bus) |
arch/arm/mach-orion5x/pci.c
303
writel(PCI_CONF_BUS(bus) |
arch/arm/mach-orion5x/pci.c
390
writel(p2p, PCI_P2P_CONF);
arch/arm/mach-orion5x/pci.c
418
writel(win_enable, PCI_BAR_ENABLE);
arch/arm/mach-orion5x/pci.c
444
writel((cs->size - 1) & 0xfffff000,
arch/arm/mach-orion5x/pci.c
446
writel(cs->base & 0xfffff000,
arch/arm/mach-orion5x/pci.c
458
writel(win_enable, PCI_BAR_ENABLE);
arch/arm/mach-orion5x/terastation_pro2-setup.c
191
writel(buf[i++], UART1_REG(TX));
arch/arm/mach-orion5x/terastation_pro2-setup.c
275
writel(0x83, UART1_REG(LCR));
arch/arm/mach-orion5x/terastation_pro2-setup.c
276
writel(divisor & 0xff, UART1_REG(DLL));
arch/arm/mach-orion5x/terastation_pro2-setup.c
277
writel((divisor >> 8) & 0xff, UART1_REG(DLM));
arch/arm/mach-orion5x/terastation_pro2-setup.c
278
writel(0x1b, UART1_REG(LCR));
arch/arm/mach-orion5x/terastation_pro2-setup.c
279
writel(0x00, UART1_REG(IER));
arch/arm/mach-orion5x/terastation_pro2-setup.c
280
writel(0x07, UART1_REG(FCR));
arch/arm/mach-orion5x/terastation_pro2-setup.c
281
writel(0x00, UART1_REG(MCR));
arch/arm/mach-orion5x/tsx09-common.c
32
writel(0x83, UART1_REG(LCR));
arch/arm/mach-orion5x/tsx09-common.c
33
writel(divisor & 0xff, UART1_REG(DLL));
arch/arm/mach-orion5x/tsx09-common.c
34
writel((divisor >> 8) & 0xff, UART1_REG(DLM));
arch/arm/mach-orion5x/tsx09-common.c
35
writel(0x03, UART1_REG(LCR));
arch/arm/mach-orion5x/tsx09-common.c
36
writel(0x00, UART1_REG(IER));
arch/arm/mach-orion5x/tsx09-common.c
37
writel(0x00, UART1_REG(FCR));
arch/arm/mach-orion5x/tsx09-common.c
38
writel(0x00, UART1_REG(MCR));
arch/arm/mach-orion5x/tsx09-common.c
41
writel('A', UART1_REG(TX));
arch/arm/mach-pxa/gumstix.c
143
writel(readl(OSCC) | OSCC_OON, OSCC);
arch/arm/mach-qcom/platsmp.c
104
writel(reg_val, reg + APCS_CPU_PWR_CTL);
arch/arm/mach-qcom/platsmp.c
107
writel(BHS_EN | (0x10 << BHS_CNT_SHIFT), reg + APC_PWR_GATE_CTL);
arch/arm/mach-qcom/platsmp.c
112
writel(reg_val, reg + APCS_CPU_PWR_CTL);
arch/arm/mach-qcom/platsmp.c
114
writel(reg_val, reg + APCS_CPU_PWR_CTL);
arch/arm/mach-qcom/platsmp.c
118
writel(reg_val, reg + APCS_CPU_PWR_CTL);
arch/arm/mach-qcom/platsmp.c
123
writel(reg_val, reg + APCS_CPU_PWR_CTL);
arch/arm/mach-qcom/platsmp.c
125
writel(reg_val, reg + APCS_CPU_PWR_CTL);
arch/arm/mach-rockchip/platsmp.c
150
writel(__pa_symbol(secondary_startup), sram_base_addr + 8);
arch/arm/mach-rockchip/platsmp.c
151
writel(0xDEADBEAF, sram_base_addr + 4);
arch/arm/mach-rockchip/rockchip.c
34
writel(0, reg_base + 0x30);
arch/arm/mach-rockchip/rockchip.c
35
writel(0xffffffff, reg_base + 0x20);
arch/arm/mach-rockchip/rockchip.c
36
writel(0xffffffff, reg_base + 0x24);
arch/arm/mach-rockchip/rockchip.c
37
writel(1, reg_base + 0x30);
arch/arm/mach-rpc/dma.c
119
writel(idma->cur_addr, base + cur);
arch/arm/mach-rpc/dma.c
120
writel(idma->cur_len, base + end);
arch/arm/mach-s3c/pl080.c
254
writel(0xffffff, S3C64XX_SDMA_SEL);
arch/arm/mach-s3c/setup-usb-phy-s3c64xx.c
28
writel(readl(S3C64XX_OTHERS) | S3C64XX_OTHERS_USBMASK, S3C64XX_OTHERS);
arch/arm/mach-s3c/setup-usb-phy-s3c64xx.c
51
writel(phyclk | S3C_PHYCLK_CLK_FORCE, S3C_PHYCLK);
arch/arm/mach-s3c/setup-usb-phy-s3c64xx.c
54
writel((readl(S3C_PHYPWR) & ~S3C_PHYPWR_NORMAL_MASK), S3C_PHYPWR);
arch/arm/mach-s3c/setup-usb-phy-s3c64xx.c
58
writel(S3C_RSTCON_PHY | S3C_RSTCON_HCLK | S3C_RSTCON_PHYCLK,
arch/arm/mach-s3c/setup-usb-phy-s3c64xx.c
61
writel(0, S3C_RSTCON);
arch/arm/mach-s3c/setup-usb-phy-s3c64xx.c
68
writel((readl(S3C_PHYPWR) | S3C_PHYPWR_ANALOG_POWERDOWN |
arch/arm/mach-s3c/setup-usb-phy-s3c64xx.c
71
writel(readl(S3C64XX_OTHERS) & ~S3C64XX_OTHERS_USBMASK, S3C64XX_OTHERS);
arch/arm/mach-shmobile/platsmp-apmu.c
201
writel(x, apmu_cpus[cpu].iomem + DBGRCR_OFFS);
arch/arm/mach-shmobile/setup-r8a7778.c
34
writel(0x73ffffff, base + INT2NTSR0);
arch/arm/mach-shmobile/setup-r8a7778.c
35
writel(0xffffffff, base + INT2NTSR1);
arch/arm/mach-shmobile/setup-r8a7778.c
38
writel(0x08330773, base + INT2SMSKCR0);
arch/arm/mach-shmobile/setup-r8a7778.c
39
writel(0x00311110, base + INT2SMSKCR1);
arch/arm/mach-shmobile/setup-r8a7779.c
37
writel(0xffffffff, base + INT2NTSR0);
arch/arm/mach-shmobile/setup-r8a7779.c
38
writel(0x3fffffff, base + INT2NTSR1);
arch/arm/mach-shmobile/setup-r8a7779.c
41
writel(0xfffffff0, base + INT2SMSKCR0);
arch/arm/mach-shmobile/setup-r8a7779.c
42
writel(0xfff7ffff, base + INT2SMSKCR1);
arch/arm/mach-shmobile/setup-r8a7779.c
43
writel(0xfffbffdf, base + INT2SMSKCR2);
arch/arm/mach-shmobile/setup-r8a7779.c
44
writel(0xbffffffc, base + INT2SMSKCR3);
arch/arm/mach-shmobile/setup-r8a7779.c
45
writel(0x003fee3f, base + INT2SMSKCR4);
arch/arm/mach-shmobile/smp-r8a7779.c
51
writel(__pa(shmobile_boot_vector), base + AVECR);
arch/arm/mach-shmobile/smp-sh73a0.c
38
writel(1 << lcpu, cpg2 + WUPCR); /* wake up */
arch/arm/mach-shmobile/smp-sh73a0.c
40
writel(1 << lcpu, cpg2 + SRESCR); /* reset */
arch/arm/mach-shmobile/smp-sh73a0.c
57
writel(0, ap + APARMBAREA); /* 4k */
arch/arm/mach-shmobile/smp-sh73a0.c
58
writel(__pa(shmobile_boot_vector), sysc + SBAR);
arch/arm/mach-socfpga/l2_cache.c
42
writel(0x01, mapped_l2_edac_addr);
arch/arm/mach-socfpga/l2_cache.c
70
writel(A10_SYSMGR_MPU_CLEAR_L2_ECC, (sys_manager_base_addr +
arch/arm/mach-socfpga/l2_cache.c
73
writel(A10_SYSMGR_ECC_INTMASK_CLR_L2, sys_manager_base_addr +
arch/arm/mach-socfpga/l2_cache.c
75
writel(A10_MPU_CTRL_L2_ECC_EN, mapped_l2_edac_addr +
arch/arm/mach-socfpga/ocram.c
107
writel(ALTR_A10_ECC_ERRPENA_MASK,
arch/arm/mach-socfpga/ocram.c
140
writel(ALTR_A10_OCRAM_ECC_EN_CTL,
arch/arm/mach-socfpga/ocram.c
162
writel(ALTR_A10_OCRAM_ECC_EN_CTL,
arch/arm/mach-socfpga/ocram.c
35
writel(ALTR_OCRAM_CLEAR_ECC, mapped_ocr_edac_addr);
arch/arm/mach-socfpga/ocram.c
36
writel(ALTR_OCRAM_ECC_EN, mapped_ocr_edac_addr);
arch/arm/mach-socfpga/ocram.c
70
writel(value, ioaddr);
arch/arm/mach-socfpga/ocram.c
78
writel(value, ioaddr);
arch/arm/mach-socfpga/platsmp.c
27
writel(RSTMGR_MPUMODRST_CPU1,
arch/arm/mach-socfpga/platsmp.c
32
writel(__pa_symbol(secondary_startup),
arch/arm/mach-socfpga/platsmp.c
40
writel(0, rst_manager_base_addr + SOCFPGA_RSTMGR_MODMPURST);
arch/arm/mach-socfpga/platsmp.c
51
writel(RSTMGR_MPUMODRST_CPU1, rst_manager_base_addr +
arch/arm/mach-socfpga/platsmp.c
55
writel(__pa_symbol(secondary_startup),
arch/arm/mach-socfpga/platsmp.c
63
writel(0, rst_manager_base_addr + SOCFPGA_A10_RSTMGR_MODMPURST);
arch/arm/mach-socfpga/socfpga.c
78
writel(temp, rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL);
arch/arm/mach-socfpga/socfpga.c
91
writel(temp, rst_manager_base_addr + SOCFPGA_A10_RSTMGR_CTRL);
arch/arm/mach-spear/pl080.c
53
writel(val, DMA_CHN_CFG);
arch/arm/mach-sunxi/mc_smp.c
129
writel(0xff, prcm_base + PRCM_PWR_SWITCH_REG(cluster, cpu));
arch/arm/mach-sunxi/mc_smp.c
131
writel(0xfe, prcm_base + PRCM_PWR_SWITCH_REG(cluster, cpu));
arch/arm/mach-sunxi/mc_smp.c
133
writel(0xf8, prcm_base + PRCM_PWR_SWITCH_REG(cluster, cpu));
arch/arm/mach-sunxi/mc_smp.c
135
writel(0xf0, prcm_base + PRCM_PWR_SWITCH_REG(cluster, cpu));
arch/arm/mach-sunxi/mc_smp.c
137
writel(0x00, prcm_base + PRCM_PWR_SWITCH_REG(cluster, cpu));
arch/arm/mach-sunxi/mc_smp.c
140
writel(0xff, prcm_base + PRCM_PWR_SWITCH_REG(cluster, cpu));
arch/arm/mach-sunxi/mc_smp.c
150
writel(CPU0_SUPPORT_HOTPLUG_MAGIC0, sram_b_smp_base);
arch/arm/mach-sunxi/mc_smp.c
151
writel(CPU0_SUPPORT_HOTPLUG_MAGIC1, sram_b_smp_base + 0x4);
arch/arm/mach-sunxi/mc_smp.c
153
writel(0x0, sram_b_smp_base);
arch/arm/mach-sunxi/mc_smp.c
154
writel(0x0, sram_b_smp_base + 0x4);
arch/arm/mach-sunxi/mc_smp.c
173
writel(reg, prcm_base + PRCM_CPU_PO_RST_CTRL(cluster));
arch/arm/mach-sunxi/mc_smp.c
180
writel(reg, r_cpucfg_base +
arch/arm/mach-sunxi/mc_smp.c
189
writel(reg, cpucfg_base + CPUCFG_CX_CTRL_REG0(cluster));
arch/arm/mach-sunxi/mc_smp.c
203
writel(reg, cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
arch/arm/mach-sunxi/mc_smp.c
217
writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster));
arch/arm/mach-sunxi/mc_smp.c
229
writel(reg, prcm_base + PRCM_CPU_PO_RST_CTRL(cluster));
arch/arm/mach-sunxi/mc_smp.c
235
writel(reg, r_cpucfg_base +
arch/arm/mach-sunxi/mc_smp.c
248
writel(reg, cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
arch/arm/mach-sunxi/mc_smp.c
265
writel(reg, cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
arch/arm/mach-sunxi/mc_smp.c
272
writel(reg, cpucfg_base + CPUCFG_CX_CTRL_REG1(cluster));
arch/arm/mach-sunxi/mc_smp.c
277
writel(reg, prcm_base + PRCM_CPU_PO_RST_CTRL(cluster));
arch/arm/mach-sunxi/mc_smp.c
284
writel(reg, r_cpucfg_base +
arch/arm/mach-sunxi/mc_smp.c
303
writel(reg, cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
arch/arm/mach-sunxi/mc_smp.c
315
writel(reg, cpucfg_base + CPUCFG_CX_CTRL_REG0(cluster));
arch/arm/mach-sunxi/mc_smp.c
323
writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster));
arch/arm/mach-sunxi/mc_smp.c
331
writel(reg, cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
arch/arm/mach-sunxi/mc_smp.c
336
writel(reg, cpucfg_base + CPUCFG_CX_CTRL_REG1(cluster));
arch/arm/mach-sunxi/mc_smp.c
440
writel(reg, cpucfg_base + CPUCFG_CX_CTRL_REG1(cluster));
arch/arm/mach-sunxi/mc_smp.c
495
writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster));
arch/arm/mach-sunxi/mc_smp.c
518
writel(reg, cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
arch/arm/mach-sunxi/mc_smp.c
527
writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster));
arch/arm/mach-sunxi/mc_smp.c
884
writel(__pa_symbol(sunxi_mc_smp_secondary_startup), addr);
arch/arm/mach-sunxi/platsmp.c
104
writel(reg & ~BIT(cpu), prcm_membase + PRCM_CPU_PWROFF_REG);
arch/arm/mach-sunxi/platsmp.c
108
writel(3, cpucfg_membase + CPUCFG_CPU_RST_CTRL_REG(cpu));
arch/arm/mach-sunxi/platsmp.c
112
writel(reg | BIT(cpu), cpucfg_membase + CPUCFG_DBG_CTL1_REG);
arch/arm/mach-sunxi/platsmp.c
167
writel(__pa_symbol(secondary_startup),
arch/arm/mach-sunxi/platsmp.c
171
writel(0, cpucfg_membase + CPUCFG_CPU_RST_CTRL_REG(cpu));
arch/arm/mach-sunxi/platsmp.c
175
writel(reg & ~BIT(cpu), cpucfg_membase + CPUCFG_GEN_CTRL_REG);
arch/arm/mach-sunxi/platsmp.c
179
writel(reg & ~BIT(cpu), prcm_membase + PRCM_CPU_PWROFF_REG);
arch/arm/mach-sunxi/platsmp.c
183
writel(3, cpucfg_membase + CPUCFG_CPU_RST_CTRL_REG(cpu));
arch/arm/mach-sunxi/platsmp.c
83
writel(__pa_symbol(secondary_startup),
arch/arm/mach-sunxi/platsmp.c
87
writel(0, cpucfg_membase + CPUCFG_CPU_RST_CTRL_REG(cpu));
arch/arm/mach-sunxi/platsmp.c
91
writel(reg & ~BIT(cpu), cpucfg_membase + CPUCFG_GEN_CTRL_REG);
arch/arm/mach-sunxi/platsmp.c
95
writel(reg & ~BIT(cpu), cpucfg_membase + CPUCFG_DBG_CTL1_REG);
arch/arm/mach-sunxi/platsmp.c
99
writel(0xff >> i, prcm_membase + PRCM_CPU_PWR_CLAMP_REG(cpu));
arch/arm/mach-tegra/reset.c
42
writel(reset_address, evp_cpu_reset);
arch/arm/mach-tegra/reset.c
52
writel(reg, sb_ctrl);
arch/arm/mach-ux500/platsmp.c
75
writel(__pa_symbol(secondary_startup),
arch/arm/mach-ux500/platsmp.c
77
writel(0xA1FEED01,
arch/arm/mach-ux500/pm.c
149
writel(er, PRCM_ARMITMSK31TO0 + i * 4);
arch/arm/mach-ux500/pm.c
50
writel(val | PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ,
arch/arm/mach-ux500/pm.c
68
writel(val & ~PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ, PRCM_A9_MASK_REQ);
arch/arm/mach-versatile/integrator.c
54
writel(val | set, cm_base + INTEGRATOR_HDR_CTRL_OFFSET);
arch/arm/mach-versatile/integrator.c
61
writel(0xffffffffU, cm_base + INTEGRATOR_HDR_IC_OFFSET +
arch/arm/mach-versatile/integrator_ap.c
76
writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
arch/arm/mach-versatile/integrator_ap.c
77
writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
arch/arm/mach-versatile/integrator_ap.c
79
writel(ic_irq_enable, VA_IC_BASE + IRQ_ENABLE_SET);
arch/arm/mach-versatile/integrator_cp.c
70
writel(8, intcp_con_base + 8);
arch/arm/mach-versatile/spc.c
338
writel(perf, info->baseaddr + perf_cfg_reg);
arch/arm/mach-versatile/spc.c
358
writel(SYSCFG_START | func | offset >> 2, info->baseaddr + COMMS);
arch/arm/mach-versatile/v2m.c
25
writel(~0, base + SYS_FLAGSCLR);
arch/arm/mach-versatile/v2m.c
26
writel(data, base + SYS_FLAGSSET);
arch/arm/mach-versatile/versatile.c
116
writel((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) |
arch/arm/mach-versatile/versatile.c
141
writel(1, versatile_sys_base + VERSATILE_SYS_PCICTL_OFFSET);
arch/arm/mach-vt8500/vt8500.c
120
writel(readl(gpio_base + VT8500_GPIO_MUX_REG) |
arch/arm/mach-vt8500/vt8500.c
36
writel(1, pmc_base + VT8500_PMSR_REG);
arch/arm/mach-vt8500/vt8500.c
88
writel(readl(gpio_base + VT8500_GPIO_MUX_REG) | 1,
arch/arm/mach-zynq/platsmp.c
64
writel(address, zero + trampoline_size);
arch/arm/mach-zynq/pm.c
69
writel(reg, ddrc_base + DDRC_DRAM_PARAM_REG3_OFFS);
arch/arm/mach-zynq/slcr.c
184
writel(state, zynq_slcr_base + SLCR_REBOOT_STATUS_OFFSET);
arch/arm/mm/cache-feroceon-l2.c
380
writel(readl(base) | L2_WRITETHROUGH_KIRKWOOD, base);
arch/arm/mm/cache-feroceon-l2.c
382
writel(readl(base) & ~L2_WRITETHROUGH_KIRKWOOD, base);
arch/arm/plat-orion/gpio.c
106
writel(u, GPIO_IO_CONF(ochip));
arch/arm/plat-orion/gpio.c
118
writel(u, GPIO_OUT(ochip));
arch/arm/plat-orion/gpio.c
131
writel(u, GPIO_BLINK_EN(ochip));
arch/arm/plat-orion/gpio.c
384
writel(u, GPIO_IN_POL(ochip));
arch/arm/plat-orion/gpio.c
388
writel(u, GPIO_IN_POL(ochip));
arch/arm/plat-orion/gpio.c
402
writel(u, GPIO_IN_POL(ochip));
arch/arm/plat-orion/gpio.c
434
writel(polarity, GPIO_IN_POL(ochip));
arch/arm/plat-orion/gpio.c
562
writel(0, GPIO_EDGE_CAUSE(ochip));
arch/arm/plat-orion/gpio.c
563
writel(0, GPIO_EDGE_MASK(ochip));
arch/arm/plat-orion/gpio.c
564
writel(0, GPIO_LEVEL_MASK(ochip));
arch/arm/plat-orion/irq.c
30
writel(0, maskaddr);
arch/arm/plat-orion/mpp.c
78
writel(mpp_ctrl[i], mpp_ctrl_addr(i, dev_bus));
arch/arm/plat-orion/pcie.c
105
writel(reg, base + PCIE_DEBUG_CTRL);
arch/arm/plat-orion/pcie.c
115
writel(reg, base + PCIE_DEBUG_CTRL);
arch/arm/plat-orion/pcie.c
135
writel(0, base + PCIE_BAR_CTRL_OFF(i));
arch/arm/plat-orion/pcie.c
136
writel(0, base + PCIE_BAR_LO_OFF(i));
arch/arm/plat-orion/pcie.c
137
writel(0, base + PCIE_BAR_HI_OFF(i));
arch/arm/plat-orion/pcie.c
141
writel(0, base + PCIE_WIN04_CTRL_OFF(i));
arch/arm/plat-orion/pcie.c
142
writel(0, base + PCIE_WIN04_BASE_OFF(i));
arch/arm/plat-orion/pcie.c
143
writel(0, base + PCIE_WIN04_REMAP_OFF(i));
arch/arm/plat-orion/pcie.c
146
writel(0, base + PCIE_WIN5_CTRL_OFF);
arch/arm/plat-orion/pcie.c
147
writel(0, base + PCIE_WIN5_BASE_OFF);
arch/arm/plat-orion/pcie.c
148
writel(0, base + PCIE_WIN5_REMAP_OFF);
arch/arm/plat-orion/pcie.c
157
writel(cs->base & 0xffff0000, base + PCIE_WIN04_BASE_OFF(i));
arch/arm/plat-orion/pcie.c
158
writel(0, base + PCIE_WIN04_REMAP_OFF(i));
arch/arm/plat-orion/pcie.c
159
writel(((cs->size - 1) & 0xffff0000) |
arch/arm/plat-orion/pcie.c
176
writel(dram->cs[0].base, base + PCIE_BAR_LO_OFF(1));
arch/arm/plat-orion/pcie.c
177
writel(0, base + PCIE_BAR_HI_OFF(1));
arch/arm/plat-orion/pcie.c
178
writel(((size - 1) & 0xffff0000) | 1, base + PCIE_BAR_CTRL_OFF(1));
arch/arm/plat-orion/pcie.c
205
writel(mask, base + PCIE_MASK_OFF);
arch/arm/plat-orion/pcie.c
211
writel(PCIE_CONF_BUS(bus->number) |
arch/arm/plat-orion/pcie.c
230
writel(PCIE_CONF_BUS(bus->number) |
arch/arm/plat-orion/pcie.c
271
writel(PCIE_CONF_BUS(bus->number) |
arch/arm/plat-orion/pcie.c
278
writel(val, base + PCIE_CONF_DATA_OFF);
arch/arm/plat-orion/pcie.c
89
writel(stat, base + PCIE_STAT_OFF);
arch/arm/plat-orion/time.c
103
writel(u, timer_base + TIMER_CTRL_OFF);
arch/arm/plat-orion/time.c
119
writel(u & ~TIMER1_EN, timer_base + TIMER_CTRL_OFF);
arch/arm/plat-orion/time.c
123
writel(u & ~BRIDGE_INT_TIMER1, bridge_base + BRIDGE_MASK_OFF);
arch/arm/plat-orion/time.c
126
writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF);
arch/arm/plat-orion/time.c
141
writel(ticks_per_jiffy - 1, timer_base + TIMER1_RELOAD_OFF);
arch/arm/plat-orion/time.c
142
writel(ticks_per_jiffy - 1, timer_base + TIMER1_VAL_OFF);
arch/arm/plat-orion/time.c
146
writel(u | BRIDGE_INT_TIMER1, bridge_base + BRIDGE_MASK_OFF);
arch/arm/plat-orion/time.c
150
writel(u | TIMER1_EN | TIMER1_RELOAD_EN, timer_base + TIMER_CTRL_OFF);
arch/arm/plat-orion/time.c
174
writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF);
arch/arm/plat-orion/time.c
221
writel(0xffffffff, timer_base + TIMER0_VAL_OFF);
arch/arm/plat-orion/time.c
222
writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF);
arch/arm/plat-orion/time.c
224
writel(u & ~BRIDGE_INT_TIMER0, bridge_base + BRIDGE_MASK_OFF);
arch/arm/plat-orion/time.c
226
writel(u | TIMER0_EN | TIMER0_RELOAD_EN, timer_base + TIMER_CTRL_OFF);
arch/arm/plat-orion/time.c
87
writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF);
arch/arm/plat-orion/time.c
91
writel(u, bridge_base + BRIDGE_MASK_OFF);
arch/arm/plat-orion/time.c
96
writel(delta, timer_base + TIMER1_VAL_OFF);
arch/loongarch/pci/pci.c
153
writel(val, crtc_reg);
arch/m68k/coldfire/intc-5249.c
25
writel(imr, MCFSIM2_GPIOINTENABLE);
arch/m68k/coldfire/intc-5249.c
33
writel(imr, MCFSIM2_GPIOINTENABLE);
arch/m68k/coldfire/intc-5249.c
38
writel(0x1 << (d->irq - MCF_IRQ_GPIO0), MCFSIM2_GPIOINTCLEAR);
arch/m68k/coldfire/intc-525x.c
31
writel(imr, MCFSIM2_GPIOINTENABLE);
arch/m68k/coldfire/intc-525x.c
44
writel(imr, MCFSIM2_GPIOINTENABLE);
arch/m68k/coldfire/intc-525x.c
57
writel(imr, MCFSIM2_GPIOINTCLEAR);
arch/m68k/coldfire/intc-525x.c
80
writel(MCFINTC2_VECBASE, MCFINTC2_INTBASE);
arch/m68k/coldfire/intc-5272.c
101
writel(v, intc_irqmap[irq].icr);
arch/m68k/coldfire/intc-5272.c
117
writel(v, intc_irqmap[irq].icr);
arch/m68k/coldfire/intc-5272.c
135
writel(v, MCFSIM_PITR);
arch/m68k/coldfire/intc-5272.c
166
writel(0x88888888, MCFSIM_ICR1);
arch/m68k/coldfire/intc-5272.c
167
writel(0x88888888, MCFSIM_ICR2);
arch/m68k/coldfire/intc-5272.c
168
writel(0x88888888, MCFSIM_ICR3);
arch/m68k/coldfire/intc-5272.c
169
writel(0x88888888, MCFSIM_ICR4);
arch/m68k/coldfire/intc-5272.c
89
writel(v, intc_irqmap[irq].icr);
arch/m68k/coldfire/m5249.c
100
writel(r, MCFINTC2_INTPRI_REG(MCF_IRQ_I2C1));
arch/m68k/coldfire/m5249.c
114
writel(gpio | 0x40, MCFSIM2_GPIOINTENABLE);
arch/m68k/coldfire/m5249.c
117
writel(gpio | 0x04000000, MCFINTC2_INTPRI5);
arch/m68k/coldfire/m525x.c
49
writel(f, MCFSIM2_GPIOFUNC);
arch/m68k/coldfire/m525x.c
72
writel(r, MCFINTC2_INTPRI_REG(MCF_IRQ_I2C1));
arch/m68k/coldfire/m5272.c
60
writel(v, MCFSIM_PBCNT);
arch/m68k/coldfire/m5272.c
64
writel(v, MCFSIM_PDCNT);
arch/m68k/coldfire/m53xx.c
317
writel(0x77777777, MCF_SCM_MPR);
arch/m68k/coldfire/m53xx.c
321
writel(0, MCF_SCM_PACRA);
arch/m68k/coldfire/m53xx.c
322
writel(0, MCF_SCM_PACRB);
arch/m68k/coldfire/m53xx.c
323
writel(0, MCF_SCM_PACRC);
arch/m68k/coldfire/m53xx.c
324
writel(0, MCF_SCM_PACRD);
arch/m68k/coldfire/m53xx.c
325
writel(0, MCF_SCM_PACRE);
arch/m68k/coldfire/m53xx.c
326
writel(0, MCF_SCM_PACRF);
arch/m68k/coldfire/m53xx.c
329
writel(MCF_SCM_BCR_GBR | MCF_SCM_BCR_GBW, MCF_SCM_BCR);
arch/m68k/coldfire/m53xx.c
338
writel(0x10080000, MCF_FBCS1_CSAR);
arch/m68k/coldfire/m53xx.c
340
writel(0x002A3780, MCF_FBCS1_CSCR);
arch/m68k/coldfire/m53xx.c
341
writel(MCF_FBCS_CSMR_BAM_2M | MCF_FBCS_CSMR_V, MCF_FBCS1_CSMR);
arch/m68k/coldfire/m53xx.c
347
writel(EXT_SRAM_ADDRESS, MCF_FBCS1_CSAR);
arch/m68k/coldfire/m53xx.c
348
writel(MCF_FBCS_CSCR_PS_16 |
arch/m68k/coldfire/m53xx.c
353
writel(MCF_FBCS_CSMR_BAM_512K | MCF_FBCS_CSMR_V, MCF_FBCS1_CSMR);
arch/m68k/coldfire/m53xx.c
356
writel(FLASH_ADDRESS, MCF_FBCS0_CSAR);
arch/m68k/coldfire/m53xx.c
357
writel(MCF_FBCS_CSCR_PS_16 |
arch/m68k/coldfire/m53xx.c
363
writel(MCF_FBCS_CSMR_BAM_32M | MCF_FBCS_CSMR_V, MCF_FBCS0_CSMR);
arch/m68k/coldfire/m53xx.c
376
writel(MCF_SDRAMC_SDCS_BA(SDRAM_ADDRESS) |
arch/m68k/coldfire/m53xx.c
383
writel(MCF_SDRAMC_SDCFG1_SRD2RW((int)((SDRAM_CASL + 2) + 0.5)) |
arch/m68k/coldfire/m53xx.c
391
writel(MCF_SDRAMC_SDCFG2_BRD2PRE(SDRAM_BL / 2 + 1) |
arch/m68k/coldfire/m53xx.c
401
writel(MCF_SDRAMC_SDCR_MODE_EN |
arch/m68k/coldfire/m53xx.c
413
writel(MCF_SDRAMC_SDMR_BNKAD_LEMR |
arch/m68k/coldfire/m53xx.c
421
writel(MCF_SDRAMC_SDMR_BNKAD_LMR |
arch/m68k/coldfire/m53xx.c
429
writel(readl(MCF_SDRAMC_SDCR) | MCF_SDRAMC_SDCR_IPALL, MCF_SDRAMC_SDCR);
arch/m68k/coldfire/m53xx.c
434
writel(readl(MCF_SDRAMC_SDCR) | MCF_SDRAMC_SDCR_IREF, MCF_SDRAMC_SDCR);
arch/m68k/coldfire/m53xx.c
435
writel(readl(MCF_SDRAMC_SDCR) | MCF_SDRAMC_SDCR_IREF, MCF_SDRAMC_SDCR);
arch/m68k/coldfire/m53xx.c
440
writel(MCF_SDRAMC_SDMR_BNKAD_LMR |
arch/m68k/coldfire/m53xx.c
448
writel(readl(MCF_SDRAMC_SDCR) & ~MCF_SDRAMC_SDCR_MODE_EN,
arch/m68k/coldfire/m53xx.c
450
writel(MCF_SDRAMC_SDCR_REF | MCF_SDRAMC_SDCR_DQS_OE(0xC),
arch/m68k/coldfire/m53xx.c
507
writel(readl(MCF_SDRAMC_SDCR) & ~MCF_SDRAMC_SDCR_CKE,
arch/m68k/coldfire/m53xx.c
532
writel(readl(MCF_SDRAMC_SDCR) | MCF_SDRAMC_SDCR_CKE,
arch/m68k/coldfire/m53xx.c
536
writel(MCF_SDRAMC_REFRESH, MCF_SDRAMC_LIMP_FIX);
arch/m68k/coldfire/m54xx.c
72
writel(r, MCF_PAR_FECI2CIRQ);
arch/m68k/include/asm/io_mm.h
398
#define writel_relaxed(b, addr) writel(b, addr)
arch/m68k/include/asm/io_no.h
90
#define writel writel
arch/mips/include/asm/io.h
513
#define writel writel
arch/mips/include/asm/mips-cm.h
398
writel(0, mips_cm_l2sync_base);
arch/mips/loongson2ef/common/pm.c
104
writel(readl(LOONGSON_CHIPCFG) & ~0x7, LOONGSON_CHIPCFG);
arch/mips/loongson2ef/common/pm.c
109
writel(cached_cpu_freq, LOONGSON_CHIPCFG);
arch/mips/loongson2ef/common/pm.c
78
writel(readl(LOONGSON_CHIPCFG) & ~0x7, LOONGSON_CHIPCFG);
arch/mips/loongson2ef/lemote-2f/clock.c
47
writel(regval, LOONGSON_CHIPCFG);
arch/mips/loongson2ef/lemote-2f/reset.c
27
writel(readl(LOONGSON_CHIPCFG) | 0x7, LOONGSON_CHIPCFG);
arch/mips/pci/ops-bonito64.c
61
writel(cpu_to_le32(*data), addrp);
arch/mips/pci/ops-loongson2.c
93
writel(cpu_to_le32(*data), addrp);
arch/mips/pci/pci-rt2880.c
51
writel(val, rt2880_pci_base + reg);
arch/mips/pic32/pic32mzda/config.c
111
writel(-1, PIC32_CLR(pic32_conf_base + PIC32_RCON));
arch/mips/pic32/pic32mzda/config.c
45
writel(v, pic32_conf_base + offset);
arch/mips/pic32/pic32mzda/config.c
82
writel(0x00000000, syskey);
arch/mips/pic32/pic32mzda/config.c
83
writel(0xAA996655, syskey);
arch/mips/pic32/pic32mzda/config.c
84
writel(0x556699AA, syskey);
arch/mips/rb532/gpio.c
81
writel(val, ioaddr);
arch/mips/rb532/setup.c
32
writel(0x80000001, IDT434_REG_BASE + RST);
arch/nios2/boot/compressed/console.c
51
writel(ALTERA_JTAGUART_CONTROL_AC_MSK,
arch/nios2/include/asm/io.h
26
#define writel_relaxed(x, addr) writel(x, addr)
arch/parisc/lib/iomap.c
211
writel(datum, addr);
arch/powerpc/include/asm/io.h
465
#define __do_outl(val, port) writel(val,_IO_PORT(port));
arch/powerpc/include/asm/io.h
543
#define writel writel
arch/powerpc/include/asm/io.h
700
#define writel_relaxed(v, addr) writel(v, addr)
arch/powerpc/platforms/44x/pci.c
240
writel(plb_addr, reg + PCIL0_PMM0LA + (0x10 * index));
arch/powerpc/platforms/44x/pci.c
241
writel(pcila, reg + PCIL0_PMM0PCILA + (0x10 * index));
arch/powerpc/platforms/44x/pci.c
242
writel(pciha, reg + PCIL0_PMM0PCIHA + (0x10 * index));
arch/powerpc/platforms/44x/pci.c
243
writel(ma, reg + PCIL0_PMM0MA + (0x10 * index));
arch/powerpc/platforms/44x/pci.c
303
writel(0, reg + PCIL0_PTM1LA);
arch/powerpc/platforms/44x/pci.c
304
writel(sa, reg + PCIL0_PTM1MS);
arch/powerpc/platforms/44x/pci.c
371
writel(0, reg + PCIL0_PMM0MA);
arch/powerpc/platforms/44x/pci.c
372
writel(0, reg + PCIL0_PMM1MA);
arch/powerpc/platforms/44x/pci.c
373
writel(0, reg + PCIL0_PMM2MA);
arch/powerpc/platforms/44x/pci.c
374
writel(0, reg + PCIL0_PTM1MS);
arch/powerpc/platforms/44x/pci.c
375
writel(0, reg + PCIL0_PTM2MS);
arch/powerpc/platforms/44x/pci.c
431
writel(lah, reg + PCIX0_POM0LAH);
arch/powerpc/platforms/44x/pci.c
432
writel(lal, reg + PCIX0_POM0LAL);
arch/powerpc/platforms/44x/pci.c
433
writel(pciah, reg + PCIX0_POM0PCIAH);
arch/powerpc/platforms/44x/pci.c
434
writel(pcial, reg + PCIX0_POM0PCIAL);
arch/powerpc/platforms/44x/pci.c
435
writel(sa, reg + PCIX0_POM0SA);
arch/powerpc/platforms/44x/pci.c
437
writel(lah, reg + PCIX0_POM1LAH);
arch/powerpc/platforms/44x/pci.c
438
writel(lal, reg + PCIX0_POM1LAL);
arch/powerpc/platforms/44x/pci.c
439
writel(pciah, reg + PCIX0_POM1PCIAH);
arch/powerpc/platforms/44x/pci.c
440
writel(pcial, reg + PCIX0_POM1PCIAL);
arch/powerpc/platforms/44x/pci.c
441
writel(sa, reg + PCIX0_POM1SA);
arch/powerpc/platforms/44x/pci.c
500
writel(0x00000000, reg + PCIX0_PIM0LAH);
arch/powerpc/platforms/44x/pci.c
501
writel(0x00000000, reg + PCIX0_PIM0LAL);
arch/powerpc/platforms/44x/pci.c
510
writel(sa, reg + PCIX0_PIM0SA);
arch/powerpc/platforms/44x/pci.c
512
writel(0xffffffff, reg + PCIX0_PIM0SAH);
arch/powerpc/platforms/44x/pci.c
515
writel(0x00000000, reg + PCIX0_BAR0H);
arch/powerpc/platforms/44x/pci.c
516
writel(res->start, reg + PCIX0_BAR0L);
arch/powerpc/platforms/44x/pci.c
575
writel(0, reg + PCIX0_POM0SA);
arch/powerpc/platforms/44x/pci.c
576
writel(0, reg + PCIX0_POM1SA);
arch/powerpc/platforms/44x/pci.c
577
writel(0, reg + PCIX0_POM2SA);
arch/powerpc/platforms/44x/pci.c
578
writel(0, reg + PCIX0_PIM0SA);
arch/powerpc/platforms/44x/pci.c
579
writel(0, reg + PCIX0_PIM1SA);
arch/powerpc/platforms/44x/pci.c
580
writel(0, reg + PCIX0_PIM2SA);
arch/powerpc/platforms/44x/pci.c
582
writel(0, reg + PCIX0_PIM0SAH);
arch/powerpc/platforms/44x/pci.c
583
writel(0, reg + PCIX0_PIM2SAH);
arch/powerpc/platforms/chrp/pegasos_eth.c
115
#define MV_WRITE(offset,data) writel(data, mv643xx_reg_base + offset)
arch/powerpc/platforms/microwatt/smp.c
69
writel((1ul << ncpus) - 1, syscon + SYSCON_CPU_CTRL);
arch/powerpc/sysdev/mpic.c
1979
writel(mpic->save_data[i].fixup_data & ~1,
arch/powerpc/sysdev/mpic.c
385
writel(mask, fixup->applebase + soff);
arch/powerpc/sysdev/mpic.c
389
writel(fixup->data, fixup->base + 4);
arch/powerpc/sysdev/mpic.c
413
writel(tmp, fixup->base + 4);
arch/powerpc/sysdev/mpic.c
439
writel(tmp, fixup->base + 4);
arch/powerpc/sysdev/mpic.c
528
writel(tmp, base + 4);
arch/riscv/kvm/aia_imsic.c
1046
writel(iid, imsic->vsfile_va + IMSIC_MMIO_SETIPNUM_LE);
arch/sh/boards/board-sh7757lcr.c
120
writel(readl(GBECONT) & ~GBECONT_RMII0, GBECONT);
arch/sh/boards/board-sh7757lcr.c
123
writel(readl(GBECONT) & ~GBECONT_RMII1, GBECONT);
arch/sh/boards/board-sh7757lcr.c
57
writel(readl(GBECONT) | GBECONT_RMII0, GBECONT);
arch/sh/boards/board-sh7757lcr.c
59
writel(readl(GBECONT) | GBECONT_RMII1, GBECONT);
arch/sh/boards/board-sh7785lcr.c
350
writel(0x000307c2, sm501_reg + SM501_DRAM_CONTROL);
arch/sh/boards/mach-r2d/setup.c
294
writel(readl(sm501_reg) | 0x00f107c0, sm501_reg);
arch/sh/drivers/pci/fixups-se7751.c
32
#define PCIC_WRITE(x,v) writel((v), PCI_REG(x))
arch/sparc/include/asm/floppy_64.h
602
writel(readl(auxio_reg)|0x2, auxio_reg);
arch/sparc/include/asm/io_64.h
176
#define writel writel
arch/sparc/include/asm/io_64.h
177
#define writel_relaxed writel
arch/sparc/include/asm/io_64.h
229
writel(l, (volatile void __iomem *)addr);
arch/sparc/include/asm/io_64.h
447
#define iowrite32 writel
arch/sparc/kernel/auxio_64.c
48
writel((u32) newval, auxio_register);
arch/sparc/kernel/ebus.c
118
writel(csr, p->regs + EBDMA_CSR);
arch/sparc/kernel/ebus.c
138
writel(csr, p->regs + EBDMA_CSR);
arch/sparc/kernel/ebus.c
144
writel(csr, p->regs + EBDMA_CSR);
arch/sparc/kernel/ebus.c
166
writel(csr, p->regs + EBDMA_CSR);
arch/sparc/kernel/ebus.c
194
writel(len, p->regs + EBDMA_COUNT);
arch/sparc/kernel/ebus.c
195
writel(bus_addr, p->regs + EBDMA_ADDR);
arch/sparc/kernel/ebus.c
223
writel(csr, p->regs + EBDMA_CSR);
arch/sparc/kernel/ebus.c
254
writel(csr, p->regs + EBDMA_CSR);
arch/sparc/kernel/ebus.c
55
writel(EBDMA_CSR_RESET, p->regs + EBDMA_CSR);
arch/sparc/kernel/ebus.c
78
writel(csr, p->regs + EBDMA_CSR);
arch/sparc/kernel/pcic.c
190
writel(CONFIG_CMD(busno, devfn, where), pcic->pcic_config_space_addr);
arch/sparc/kernel/pcic.c
247
writel(CONFIG_CMD(busno, devfn, where), pcic->pcic_config_space_addr);
arch/sparc/kernel/pcic.c
248
writel(value, pcic->pcic_config_space_data + (where&4));
arch/sparc/kernel/pcic.c
434
writel(0xF0000000UL, pcic->pcic_regs+PCI_SIZE_0);
arch/sparc/kernel/pcic.c
435
writel(0+PCI_BASE_ADDRESS_SPACE_MEMORY,
arch/sparc/kernel/pcic.c
694
writel (TICK_TIMER_LIMIT, pcic->pcic_regs+PCI_SYS_LIMIT);
arch/sparc/kernel/pcic.c
698
writel (PCI_COUNTER_IRQ_SET(timer_irq, 0),
arch/sparc/kernel/pcic.c
750
writel(mask, pcic0.pcic_regs+PCI_SYS_INT_TARGET_MASK_SET);
arch/sparc/kernel/pcic.c
760
writel(mask, pcic0.pcic_regs+PCI_SYS_INT_TARGET_MASK_CLEAR);
arch/x86/events/intel/uncore.c
1708
writel(0, io_addr);
arch/x86/events/intel/uncore_discovery.c
657
writel(GENERIC_PMON_BOX_CTL_INT, box->io_addr);
arch/x86/events/intel/uncore_discovery.c
665
writel(GENERIC_PMON_BOX_CTL_FRZ, box->io_addr);
arch/x86/events/intel/uncore_discovery.c
673
writel(0, box->io_addr);
arch/x86/events/intel/uncore_discovery.c
684
writel(hwc->config, box->io_addr + hwc->config_base);
arch/x86/events/intel/uncore_discovery.c
695
writel(0, box->io_addr + hwc->config_base);
arch/x86/events/intel/uncore_snb.c
1664
writel(ADL_UNCORE_IMC_CTL_INT, box->io_addr + ADL_UNCORE_IMC_GLOBAL_CTL);
arch/x86/events/intel/uncore_snb.c
1672
writel(ADL_UNCORE_IMC_CTL_FRZ, box->io_addr + uncore_mmio_box_ctl(box));
arch/x86/events/intel/uncore_snb.c
1680
writel(0, box->io_addr + uncore_mmio_box_ctl(box));
arch/x86/events/intel/uncore_snb.c
1846
writel(ADL_UNCORE_IMC_CTL_INT, box->io_addr + LNL_UNCORE_GLOBAL_CTL);
arch/x86/events/intel/uncore_snb.c
1903
writel(0, box->io_addr + PTL_UNCORE_GLOBAL_CTL_OFFSET);
arch/x86/events/intel/uncore_snbep.c
5036
writel(IVBEP_PMON_BOX_CTL_INT, box->io_addr);
arch/x86/events/intel/uncore_snbep.c
5055
writel(config, box->io_addr);
arch/x86/events/intel/uncore_snbep.c
5067
writel(config, box->io_addr);
arch/x86/events/intel/uncore_snbep.c
5081
writel(hwc->config | SNBEP_PMON_CTL_EN,
arch/x86/events/intel/uncore_snbep.c
5096
writel(hwc->config, box->io_addr + hwc->config_base);
arch/x86/events/intel/uncore_snbep.c
5925
writel(SNBEP_PMON_CTL_EN, box->io_addr + hwc->config_base);
arch/x86/events/intel/uncore_snbep.c
5927
writel(hwc->config, box->io_addr + hwc->config_base);
arch/x86/include/asm/io.h
67
build_mmio_write(writel, "l", unsigned int, "r", :"memory")
arch/x86/include/asm/io.h
85
#define writel writel
arch/x86/include/asm/numachip/numachip_csr.h
52
writel(swab32(val), lcsr_address(offset));
arch/x86/include/asm/numachip/numachip_csr.h
85
writel(val, numachip2_lcsr_address(offset));
arch/x86/kernel/apic/io_apic.c
268
writel(vector, &io_apic->eoi);
arch/x86/kernel/apic/io_apic.c
275
writel(reg, &io_apic->index);
arch/x86/kernel/apic/io_apic.c
284
writel(reg, &io_apic->index);
arch/x86/kernel/apic/io_apic.c
285
writel(value, &io_apic->data);
arch/x86/kernel/cpu/microcode/intel.c
359
writel(0, mmio_base + MBOX_RDDATA_OFFSET);
arch/x86/kernel/cpu/microcode/intel.c
365
writel(dword, mmio_base + MBOX_WRDATA_OFFSET);
arch/x86/kernel/cpu/microcode/intel.c
410
writel(MASK_MBOX_CTRL_ABORT, ss->mmio_base + MBOX_CONTROL_OFFSET);
arch/x86/kernel/cpu/microcode/intel.c
521
writel(MASK_MBOX_CTRL_GO, ss->mmio_base + MBOX_CONTROL_OFFSET);
arch/x86/kernel/early_printk.c
203
writel(value, vaddr + offset);
arch/x86/kernel/hpet.c
86
writel(d, hpet_virt_address + a);
arch/x86/kernel/quirks.c
137
writel(val | 0x80, rcba_base + 0x3404);
arch/x86/kernel/quirks.c
88
writel(val | 0x80, rcba_base + 0x3404);
arch/x86/kernel/vsmp_64.c
51
writel(ctl, address + 4);
arch/x86/platform/intel-mid/pwr.c
113
writel(value, pwr->regs + PM_SSC(reg));
arch/x86/platform/intel-mid/pwr.c
118
writel(value, pwr->regs + PM_WKC(reg));
arch/x86/platform/intel-mid/pwr.c
123
writel(~PM_ICS_IE, pwr->regs + PM_ICS);
arch/x86/platform/intel-mid/pwr.c
149
writel(PM_CMD_CMD(cmd) | PM_CMD_CM_IMMEDIATE, pwr->regs + PM_CMD);
arch/x86/platform/intel-mid/pwr.c
300
writel(cmd, pwr->regs + PM_CMD);
arch/x86/platform/intel-mid/pwr.c
338
writel(ics | PM_ICS_IP, pwr->regs + PM_ICS);
arch/x86/platform/uv/uv_nmi.c
325
writel(writed, addr);
arch/x86/platform/uv/uv_nmi.c
328
writel(data, addr);
drivers/accel/amdxdna/aie2_pci.c
158
writel(0, SRAM_GET_ADDR(ndev, FW_ALIVE_OFF));
drivers/accel/amdxdna/aie2_psp.c
55
writel(reg_vals[i], PSP_REG(psp, i));
drivers/accel/amdxdna/aie2_psp.c
58
writel(0, PSP_REG(psp, PSP_INTR_REG));
drivers/accel/amdxdna/aie2_psp.c
59
writel(1, PSP_REG(psp, PSP_INTR_REG));
drivers/accel/amdxdna/aie2_smu.c
38
writel(0, SMU_REG(ndev, SMU_RESP_REG));
drivers/accel/amdxdna/aie2_smu.c
39
writel(reg_arg, SMU_REG(ndev, SMU_ARG_REG));
drivers/accel/amdxdna/aie2_smu.c
40
writel(reg_cmd, SMU_REG(ndev, SMU_CMD_REG));
drivers/accel/amdxdna/aie2_smu.c
43
writel(0, SMU_REG(ndev, SMU_INTR_REG));
drivers/accel/amdxdna/aie2_smu.c
44
writel(1, SMU_REG(ndev, SMU_INTR_REG));
drivers/accel/amdxdna/amdxdna_mailbox.c
104
writel(data, ringbuf_addr);
drivers/accel/amdxdna/amdxdna_mailbox.c
206
writel(TOMBSTONE, write_addr);
drivers/accel/ethosu/ethosu_job.c
73
writel(CMD_TRANSITION_TO_RUN, dev->regs + NPU_REG_CMD);
drivers/accel/habanalabs/common/device.c
100
writel(*val, acc_addr);
drivers/accel/habanalabs/common/device.c
2679
writel(val, hdev->rmmio + reg);
drivers/accel/ivpu/ivpu_hw_reg_io.h
111
writel(val, base + reg);
drivers/accel/ivpu/ivpu_hw_reg_io.h
130
writel(val, base + reg);
drivers/accel/qaic/qaic_data.c
1405
writel(tail, dbc->dbc_base + REQTP_OFF);
drivers/accel/qaic/qaic_data.c
1662
writel(head, dbc->dbc_base + RSPHP_OFF);
drivers/accel/rocket/rocket_core.h
18
writel(value, (core)->pc_iomem + (REG_PC_##reg))
drivers/accel/rocket/rocket_core.h
23
writel(value, (core)->cna_iomem + (REG_CNA_##reg) - REG_CNA_S_STATUS)
drivers/accel/rocket/rocket_core.h
28
writel(value, (core)->core_iomem + (REG_CORE_##reg) - REG_CORE_S_STATUS)
drivers/acpi/osl.c
797
writel(value, virt_addr);
drivers/acpi/x86/lpss.c
136
writel(val | LPSS_TX_INT_MASK, pdata->mmio_base + offset);
drivers/acpi/x86/lpss.c
143
writel(val, pdata->mmio_base + offset);
drivers/acpi/x86/lpss.c
155
writel(val, pdata->mmio_base + offset);
drivers/acpi/x86/lpss.c
197
writel(0, pdata->mmio_base + LPSS_I2C_ENABLE);
drivers/acpi/x86/lpss.c
448
writel(LPSS_CLK_DIVIDER_DEF_MASK, prv_base);
drivers/acpi/x86/lpss.c
698
writel(val, pdata->mmio_base + pdata->dev_desc->prv_offset + reg);
drivers/amba/tegra-ahb.c
133
writel(value, ahb->regs + offset);
drivers/ata/acard-ahci.c
133
writel(ctl, mmio + HOST_CTL);
drivers/ata/ahci.c
1013
writel(ctl, mmio + HOST_CTL);
drivers/ata/ahci.c
1680
writel(irq_stat, mmio + HOST_IRQ_STAT);
drivers/ata/ahci.c
853
writel(0, port_mmio + PORT_IRQ_MASK);
drivers/ata/ahci.c
859
writel(tmp, port_mmio + PORT_IRQ_STAT);
drivers/ata/ahci_brcm.c
137
writel(0xff1003fc,
drivers/ata/ahci_brcm.c
272
writel(ctl, mmio + HOST_CTL);
drivers/ata/ahci_brcm.c
309
writel(ctl, mmio + HOST_CTL);
drivers/ata/ahci_ceva.c
132
writel(tmp, mmio + HOST_CTL);
drivers/ata/ahci_ceva.c
137
writel(tmp, mmio + AHCI_VEND_PCFG);
drivers/ata/ahci_ceva.c
147
writel(tmp, mmio + AHCI_VEND_PAXIC);
drivers/ata/ahci_ceva.c
156
writel(tmp, mmio + AHCI_VEND_AXICC);
drivers/ata/ahci_ceva.c
161
writel(tmp, mmio + AHCI_VEND_PPCFG);
drivers/ata/ahci_ceva.c
164
writel(cevapriv->pp2c[i], mmio + AHCI_VEND_PP2C);
drivers/ata/ahci_ceva.c
167
writel(cevapriv->pp3c[i], mmio + AHCI_VEND_PP3C);
drivers/ata/ahci_ceva.c
170
writel(cevapriv->pp4c[i], mmio + AHCI_VEND_PP4C);
drivers/ata/ahci_ceva.c
173
writel(cevapriv->pp5c[i], mmio + AHCI_VEND_PP5C);
drivers/ata/ahci_ceva.c
177
writel(tmp, mmio + AHCI_VEND_PTC);
drivers/ata/ahci_ceva.c
183
writel(tmp, mmio + PORT_SCR_CTL + PORT_BASE + PORT_OFFSET * i);
drivers/ata/ahci_da850.c
36
writel(val, pwrdn_reg);
drivers/ata/ahci_da850.c
41
writel(val, ahci_base + SATA_P0PHYCR_REG);
drivers/ata/ahci_dm816.c
93
writel(val, hpriv->mmio + AHCI_DM816_P0PHYCR_REG);
drivers/ata/ahci_dm816.c
98
writel(val, hpriv->mmio + AHCI_DM816_P1PHYCR_REG);
drivers/ata/ahci_dwc.c
257
writel(dpriv->timv, hpriv->mmio + AHCI_DWC_HOST_TIMER1MS);
drivers/ata/ahci_dwc.c
292
writel(dmacr, port_mmio + AHCI_DWC_PORT_DMACR);
drivers/ata/ahci_dwc.c
351
writel(dpriv->timv, hpriv->mmio + AHCI_DWC_HOST_TIMER1MS);
drivers/ata/ahci_dwc.c
355
writel(dpriv->dmacr[i], port_mmio + AHCI_DWC_PORT_DMACR);
drivers/ata/ahci_imx.c
114
writel(crval, mmio + IMX_P0PHYCR);
drivers/ata/ahci_imx.c
135
writel(crval, mmio + IMX_P0PHYCR);
drivers/ata/ahci_imx.c
153
writel(crval, mmio + IMX_P0PHYCR);
drivers/ata/ahci_imx.c
477
writel(val, hpriv->mmio + IMX8QM_SATA_AHCI_PTC);
drivers/ata/ahci_imx.c
627
writel(reg_val | IMX_P0PHYCR_TEST_PDDQ, mmio + IMX_P0PHYCR);
drivers/ata/ahci_imx.c
95
writel(crval, mmio + IMX_P0PHYCR);
drivers/ata/ahci_imx.c
951
writel(reg_val, hpriv->mmio + HOST_CAP);
drivers/ata/ahci_imx.c
956
writel(reg_val, hpriv->mmio + HOST_PORTS_IMPL);
drivers/ata/ahci_imx.c
971
writel(reg_val, hpriv->mmio + IMX_TIMER1MS);
drivers/ata/ahci_mvebu.c
135
writel(tmp, port_mmio + PORT_CMD);
drivers/ata/ahci_mvebu.c
142
writel(port_fbs, port_mmio + PORT_FBS);
drivers/ata/ahci_mvebu.c
42
writel(0, hpriv->mmio + AHCI_WINDOW_CTRL(i));
drivers/ata/ahci_mvebu.c
43
writel(0, hpriv->mmio + AHCI_WINDOW_BASE(i));
drivers/ata/ahci_mvebu.c
44
writel(0, hpriv->mmio + AHCI_WINDOW_SIZE(i));
drivers/ata/ahci_mvebu.c
50
writel((cs->mbus_attr << 8) |
drivers/ata/ahci_mvebu.c
53
writel(cs->base >> 16, hpriv->mmio + AHCI_WINDOW_BASE(i));
drivers/ata/ahci_mvebu.c
54
writel(((cs->size - 1) & 0xffff0000),
drivers/ata/ahci_mvebu.c
66
writel(0x4, hpriv->mmio + AHCI_VENDOR_SPECIFIC_0_ADDR);
drivers/ata/ahci_mvebu.c
67
writel(0x80, hpriv->mmio + AHCI_VENDOR_SPECIFIC_0_DATA);
drivers/ata/ahci_mvebu.c
90
writel(0, hpriv->mmio + AHCI_VENDOR_SPECIFIC_0_ADDR);
drivers/ata/ahci_mvebu.c
94
writel(reg, hpriv->mmio + AHCI_VENDOR_SPECIFIC_0_DATA);
drivers/ata/ahci_qoriq.c
134
writel(px_cmd, port_mmio + PORT_CMD);
drivers/ata/ahci_qoriq.c
138
writel(px_is, port_mmio + PORT_IRQ_STAT);
drivers/ata/ahci_qoriq.c
174
writel(SATA_ECC_DISABLE, qpriv->ecc_addr);
drivers/ata/ahci_qoriq.c
175
writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
drivers/ata/ahci_qoriq.c
176
writel(LS1021A_PORT_PHY2, reg_base + PORT_PHY2);
drivers/ata/ahci_qoriq.c
177
writel(LS1021A_PORT_PHY3, reg_base + PORT_PHY3);
drivers/ata/ahci_qoriq.c
178
writel(LS1021A_PORT_PHY4, reg_base + PORT_PHY4);
drivers/ata/ahci_qoriq.c
179
writel(LS1021A_PORT_PHY5, reg_base + PORT_PHY5);
drivers/ata/ahci_qoriq.c
180
writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
drivers/ata/ahci_qoriq.c
182
writel(AHCI_PORT_AXICC_CFG,
drivers/ata/ahci_qoriq.c
190
writel(readl(qpriv->ecc_addr) |
drivers/ata/ahci_qoriq.c
193
writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
drivers/ata/ahci_qoriq.c
194
writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
drivers/ata/ahci_qoriq.c
195
writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
drivers/ata/ahci_qoriq.c
196
writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
drivers/ata/ahci_qoriq.c
198
writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
drivers/ata/ahci_qoriq.c
202
writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
drivers/ata/ahci_qoriq.c
203
writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
drivers/ata/ahci_qoriq.c
204
writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
drivers/ata/ahci_qoriq.c
205
writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
drivers/ata/ahci_qoriq.c
207
writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
drivers/ata/ahci_qoriq.c
214
writel(readl(qpriv->ecc_addr) |
drivers/ata/ahci_qoriq.c
217
writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
drivers/ata/ahci_qoriq.c
218
writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
drivers/ata/ahci_qoriq.c
219
writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
drivers/ata/ahci_qoriq.c
220
writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
drivers/ata/ahci_qoriq.c
222
writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
drivers/ata/ahci_qoriq.c
231
writel(readl(qpriv->ecc_addr) |
drivers/ata/ahci_qoriq.c
234
writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
drivers/ata/ahci_qoriq.c
235
writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
drivers/ata/ahci_qoriq.c
236
writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
drivers/ata/ahci_qoriq.c
237
writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
drivers/ata/ahci_qoriq.c
239
writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
drivers/ata/ahci_qoriq.c
243
writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
drivers/ata/ahci_qoriq.c
244
writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
drivers/ata/ahci_qoriq.c
245
writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
drivers/ata/ahci_qoriq.c
246
writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
drivers/ata/ahci_qoriq.c
248
writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
drivers/ata/ahci_st.c
48
writel(old_val | ST_AHCI_OOBR_WE, mmio + ST_AHCI_OOBR);
drivers/ata/ahci_st.c
49
writel(new_val | ST_AHCI_OOBR_WE, mmio + ST_AHCI_OOBR);
drivers/ata/ahci_st.c
50
writel(new_val, mmio + ST_AHCI_OOBR);
drivers/ata/ahci_sunxi.c
142
writel(0x7, reg_base + AHCI_RWCR);
drivers/ata/ahci_sunxi.c
59
writel(reg_val, reg);
drivers/ata/ahci_sunxi.c
68
writel(reg_val, reg);
drivers/ata/ahci_sunxi.c
78
writel(reg_val, reg);
drivers/ata/ahci_sunxi.c
92
writel(0, reg_base + AHCI_RWCR);
drivers/ata/ahci_tegra.c
190
writel(val, tegra->sata_aux_regs + SATA_AUX_MISC_CNTL_1_0);
drivers/ata/ahci_tegra.c
208
writel(BIT(0), tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX);
drivers/ata/ahci_tegra.c
216
writel(val, tegra->sata_regs + SCFG_OFFSET +
drivers/ata/ahci_tegra.c
225
writel(val, tegra->sata_regs + SCFG_OFFSET +
drivers/ata/ahci_tegra.c
228
writel(T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ,
drivers/ata/ahci_tegra.c
230
writel(T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1,
drivers/ata/ahci_tegra.c
233
writel(0, tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX);
drivers/ata/ahci_tegra.c
317
writel(val, tegra->sata_regs + SATA_FPCI_BAR5);
drivers/ata/ahci_tegra.c
322
writel(val, tegra->sata_regs + SATA_CONFIGURATION_0);
drivers/ata/ahci_tegra.c
326
writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL17_0);
drivers/ata/ahci_tegra.c
328
writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL18_0);
drivers/ata/ahci_tegra.c
330
writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL20_0);
drivers/ata/ahci_tegra.c
332
writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL21_0);
drivers/ata/ahci_tegra.c
339
writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA_CFG_PHY_0);
drivers/ata/ahci_tegra.c
348
writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_NVOOB);
drivers/ata/ahci_tegra.c
356
writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG2NVOOB_2);
drivers/ata/ahci_tegra.c
368
writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_1);
drivers/ata/ahci_tegra.c
370
writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_9);
drivers/ata/ahci_tegra.c
375
writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);
drivers/ata/ahci_tegra.c
382
writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_BKDOOR_CC);
drivers/ata/ahci_tegra.c
386
writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);
drivers/ata/ahci_tegra.c
394
writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_AHCI_HBA_CAP_BKDR);
drivers/ata/ahci_tegra.c
403
writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_35);
drivers/ata/ahci_tegra.c
406
writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_AHCI_IDP1);
drivers/ata/ahci_tegra.c
411
writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_PHY_1);
drivers/ata/ahci_tegra.c
416
writel(val, tegra->sata_regs + SATA_CONFIGURATION_0);
drivers/ata/ahci_tegra.c
424
writel(val, tegra->sata_regs + SATA_INTR_MASK);
drivers/ata/ahci_xgene.c
161
writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS);
drivers/ata/ahci_xgene.c
203
writel(port_fbs, port_mmio + PORT_FBS);
drivers/ata/ahci_xgene.c
273
writel(val, mmio + PORTCFG);
drivers/ata/ahci_xgene.c
276
writel(0x0001fffe, mmio + PORTPHY1CFG);
drivers/ata/ahci_xgene.c
278
writel(0x28183219, mmio + PORTPHY2CFG);
drivers/ata/ahci_xgene.c
280
writel(0x13081008, mmio + PORTPHY3CFG);
drivers/ata/ahci_xgene.c
282
writel(0x00480815, mmio + PORTPHY4CFG);
drivers/ata/ahci_xgene.c
287
writel(val, mmio + PORTPHY5CFG);
drivers/ata/ahci_xgene.c
292
writel(val, mmio + PORTAXICFG);
drivers/ata/ahci_xgene.c
297
writel(val, mmio + PORTRANSCFG);
drivers/ata/ahci_xgene.c
382
writel(val, port_mmio + PORT_SCR_ERR);
drivers/ata/ahci_xgene.c
413
writel(portcmd_saved, port_mmio + PORT_CMD);
drivers/ata/ahci_xgene.c
414
writel(portclb_saved, port_mmio + PORT_LST_ADDR);
drivers/ata/ahci_xgene.c
415
writel(portclbhi_saved, port_mmio + PORT_LST_ADDR_HI);
drivers/ata/ahci_xgene.c
416
writel(portrxfis_saved, port_mmio + PORT_FIS_ADDR);
drivers/ata/ahci_xgene.c
417
writel(portrxfishi_saved, port_mmio + PORT_FIS_ADDR_HI);
drivers/ata/ahci_xgene.c
463
writel(port_fbs, port_mmio + PORT_FBS);
drivers/ata/ahci_xgene.c
511
writel(port_fbs, port_mmio + PORT_FBS);
drivers/ata/ahci_xgene.c
524
writel(port_fbs_save, port_mmio + PORT_FBS);
drivers/ata/ahci_xgene.c
601
writel(irq_stat, mmio + HOST_IRQ_STAT);
drivers/ata/ahci_xgene.c
657
writel(0xffffffff, hpriv->mmio + HOST_IRQ_STAT);
drivers/ata/ahci_xgene.c
659
writel(0, ctx->csr_core + INTSTATUSMASK);
drivers/ata/ahci_xgene.c
664
writel(0x0, ctx->csr_core + ERRINTSTATUSMASK);
drivers/ata/ahci_xgene.c
666
writel(0x0, ctx->csr_axi + INT_SLV_TMOMASK);
drivers/ata/ahci_xgene.c
670
writel(0xffffffff, ctx->csr_core + SLVRDERRATTRIBUTES);
drivers/ata/ahci_xgene.c
671
writel(0xffffffff, ctx->csr_core + SLVWRERRATTRIBUTES);
drivers/ata/ahci_xgene.c
672
writel(0xffffffff, ctx->csr_core + MSTRDERRATTRIBUTES);
drivers/ata/ahci_xgene.c
673
writel(0xffffffff, ctx->csr_core + MSTWRERRATTRIBUTES);
drivers/ata/ahci_xgene.c
679
writel(val, ctx->csr_core + BUSCTLREG);
drivers/ata/ahci_xgene.c
684
writel(val, ctx->csr_core + IOFMSTRWAUX);
drivers/ata/ahci_xgene.c
702
writel(val, ctx->csr_mux + SATA_ENET_CONFIG_REG);
drivers/ata/ahci_xgene.c
92
writel(0x0, ctx->csr_diag + CFG_MEM_RAM_SHUTDOWN);
drivers/ata/libahci.c
1106
writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL);
drivers/ata/libahci.c
1155
writel(message[0], mmio + hpriv->em_loc);
drivers/ata/libahci.c
1156
writel(message[1], mmio + hpriv->em_loc+4);
drivers/ata/libahci.c
1161
writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
drivers/ata/libahci.c
1270
writel(tmp, port_mmio + PORT_SCR_ERR);
drivers/ata/libahci.c
1276
writel(tmp, port_mmio + PORT_IRQ_STAT);
drivers/ata/libahci.c
1278
writel(1 << ap->port_no, hpriv->mmio + HOST_IRQ_STAT);
drivers/ata/libahci.c
1316
writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
drivers/ata/libahci.c
1397
writel(tmp, port_mmio + PORT_CMD);
drivers/ata/libahci.c
1431
writel(tmp, port_mmio + PORT_FBS);
drivers/ata/libahci.c
1436
writel(1, port_mmio + PORT_CMD_ISSUE);
drivers/ata/libahci.c
1651
writel(new_tmp, port_mmio + PORT_CMD);
drivers/ata/libahci.c
1740
writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS);
drivers/ata/libahci.c
1963
writel(status, port_mmio + PORT_IRQ_STAT);
drivers/ata/libahci.c
1975
writel(status, port_mmio + PORT_IRQ_STAT);
drivers/ata/libahci.c
2041
writel(irq_stat, mmio + HOST_IRQ_STAT);
drivers/ata/libahci.c
2061
writel(1 << qc->hw_tag, port_mmio + PORT_SCR_ACT);
drivers/ata/libahci.c
2067
writel(fbs, port_mmio + PORT_FBS);
drivers/ata/libahci.c
2071
writel(1 << qc->hw_tag, port_mmio + PORT_CMD_ISSUE);
drivers/ata/libahci.c
2194
writel(0, port_mmio + PORT_IRQ_MASK);
drivers/ata/libahci.c
2207
writel(tmp, port_mmio + PORT_IRQ_STAT);
drivers/ata/libahci.c
2208
writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
drivers/ata/libahci.c
2211
writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
drivers/ata/libahci.c
2258
writel(devslp & ~PORT_DEVSLP_ADSE,
drivers/ata/libahci.c
226
writel(tmp, mmio + HOST_CTL);
drivers/ata/libahci.c
2308
writel(devslp, port_mmio + PORT_DEVSLP);
drivers/ata/libahci.c
2342
writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS);
drivers/ata/libahci.c
2375
writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS);
drivers/ata/libahci.c
2395
writel(cmd, port_mmio + PORT_CMD);
drivers/ata/libahci.c
2410
writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
drivers/ata/libahci.c
2423
writel(cmd, port_mmio + PORT_CMD);
drivers/ata/libahci.c
2429
writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
drivers/ata/libahci.c
2594
writel(1 << ap->port_no, host_mmio + HOST_IRQ_STAT);
drivers/ata/libahci.c
398
writel(msg, em_mmio + i);
drivers/ata/libahci.c
401
writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
drivers/ata/libahci.c
629
writel(hpriv->saved_cap, mmio + HOST_CAP);
drivers/ata/libahci.c
631
writel(hpriv->saved_cap2, mmio + HOST_CAP2);
drivers/ata/libahci.c
632
writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
drivers/ata/libahci.c
637
writel(hpriv->saved_port_cap[i], port_mmio + PORT_CMD);
drivers/ata/libahci.c
676
writel(val, port_mmio + offset);
drivers/ata/libahci.c
690
writel(tmp, port_mmio + PORT_CMD);
drivers/ata/libahci.c
732
writel(tmp, port_mmio + PORT_CMD);
drivers/ata/libahci.c
753
writel((pp->cmd_slot_dma >> 16) >> 16,
drivers/ata/libahci.c
755
writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
drivers/ata/libahci.c
758
writel((pp->rx_fis_dma >> 16) >> 16,
drivers/ata/libahci.c
760
writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
drivers/ata/libahci.c
765
writel(tmp, port_mmio + PORT_CMD);
drivers/ata/libahci.c
780
writel(tmp, port_mmio + PORT_CMD);
drivers/ata/libahci.c
802
writel(cmd, port_mmio + PORT_CMD);
drivers/ata/libahci.c
806
writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
drivers/ata/libahci.c
827
writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
drivers/ata/libahci.c
840
writel(cmd, port_mmio + PORT_CMD);
drivers/ata/libahci.c
856
writel(cmd, port_mmio + PORT_CMD);
drivers/ata/libahci.c
876
writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
drivers/ata/libahci.c
895
writel(scontrol, port_mmio + PORT_SCR_CTL);
drivers/ata/libahci.c
900
writel(cmd, port_mmio + PORT_CMD);
drivers/ata/libahci.c
994
writel(tmp | HOST_RESET, mmio + HOST_CTL);
drivers/ata/libahci_platform.c
821
writel(readl(mmio + HOST_CTL) & ~HOST_IRQ_EN, mmio + HOST_CTL);
drivers/ata/libahci_platform.c
823
writel(GENMASK(host->n_ports, 0), mmio + HOST_IRQ_STAT);
drivers/ata/libahci_platform.c
858
writel(ctl, mmio + HOST_CTL);
drivers/ata/pata_arasan_cf.c
248
writel(enable, acdev->vbase + GIRQ_STS_EN);
drivers/ata/pata_arasan_cf.c
249
writel(enable, acdev->vbase + GIRQ_SGN_EN);
drivers/ata/pata_arasan_cf.c
259
writel(mask, acdev->vbase + IRQ_STS);
drivers/ata/pata_arasan_cf.c
260
writel(val | mask, acdev->vbase + IRQ_EN);
drivers/ata/pata_arasan_cf.c
262
writel(val & ~mask, acdev->vbase + IRQ_EN);
drivers/ata/pata_arasan_cf.c
269
writel(val | CARD_RESET, acdev->vbase + OP_MODE);
drivers/ata/pata_arasan_cf.c
271
writel(val & ~CARD_RESET, acdev->vbase + OP_MODE);
drivers/ata/pata_arasan_cf.c
276
writel(readl(acdev->vbase + OP_MODE) & ~CFHOST_ENB,
drivers/ata/pata_arasan_cf.c
278
writel(readl(acdev->vbase + OP_MODE) | CFHOST_ENB,
drivers/ata/pata_arasan_cf.c
333
writel(if_clk, acdev->vbase + CLK_CFG);
drivers/ata/pata_arasan_cf.c
335
writel(TRUE_IDE_MODE | CFHOST_ENB, acdev->vbase + OP_MODE);
drivers/ata/pata_arasan_cf.c
351
writel(readl(acdev->vbase + OP_MODE) & ~CFHOST_ENB,
drivers/ata/pata_arasan_cf.c
460
writel(xfer_ctr | xfer_cnt | XFER_START,
drivers/ata/pata_arasan_cf.c
500
writel(readl(acdev->vbase + XFER_CTR) & ~XFER_START,
drivers/ata/pata_arasan_cf.c
606
writel(irqsts, acdev->vbase + IRQ_STS); /* clear irqs */
drivers/ata/pata_arasan_cf.c
607
writel(GIRQ_CF, acdev->vbase + GIRQ_STS); /* clear girqs */
drivers/ata/pata_arasan_cf.c
620
writel(readl(acdev->vbase + XFER_CTR) & ~XFER_START,
drivers/ata/pata_arasan_cf.c
651
writel(readl(acdev->vbase + XFER_CTR) & ~XFER_START,
drivers/ata/pata_arasan_cf.c
683
writel(xfer_ctr, acdev->vbase + XFER_CTR);
drivers/ata/pata_arasan_cf.c
741
writel(val, acdev->vbase + OP_MODE);
drivers/ata/pata_arasan_cf.c
744
writel(val, acdev->vbase + TM_CFG);
drivers/ata/pata_arasan_cf.c
777
writel(opmode, acdev->vbase + OP_MODE);
drivers/ata/pata_arasan_cf.c
778
writel(tmcfg, acdev->vbase + TM_CFG);
drivers/ata/pata_arasan_cf.c
779
writel(DMA_XFER_MODE, acdev->vbase + XFER_CTR);
drivers/ata/pata_ep93xx.c
143
writel(IDECTRL_CS0N | IDECTRL_CS1N | IDECTRL_DIORN |
drivers/ata/pata_ep93xx.c
146
writel(0, base + IDECFG);
drivers/ata/pata_ep93xx.c
147
writel(0, base + IDEMDMAOP);
drivers/ata/pata_ep93xx.c
148
writel(0, base + IDEUDMAOP);
drivers/ata/pata_ep93xx.c
149
writel(0, base + IDEDATAOUT);
drivers/ata/pata_ep93xx.c
150
writel(0, base + IDEDATAIN);
drivers/ata/pata_ep93xx.c
151
writel(0, base + IDEMDMADATAOUT);
drivers/ata/pata_ep93xx.c
152
writel(0, base + IDEMDMADATAIN);
drivers/ata/pata_ep93xx.c
153
writel(0, base + IDEUDMADATAOUT);
drivers/ata/pata_ep93xx.c
154
writel(0, base + IDEUDMADATAIN);
drivers/ata/pata_ep93xx.c
155
writel(0, base + IDEUDMADEBUG);
drivers/ata/pata_ep93xx.c
193
writel(IDECFG_IDEEN | IDECFG_PIO |
drivers/ata/pata_ep93xx.c
241
writel(IDECTRL_DIOWN | IDECTRL_DIORN | addr, base + IDECTRL);
drivers/ata/pata_ep93xx.c
254
writel(IDECTRL_DIOWN | IDECTRL_DIORN | addr, base + IDECTRL);
drivers/ata/pata_ep93xx.c
272
writel(IDECTRL_DIOWN | addr, base + IDECTRL);
drivers/ata/pata_ep93xx.c
310
writel(value, base + IDEDATAOUT);
drivers/ata/pata_ep93xx.c
311
writel(IDECTRL_DIORN | addr, base + IDECTRL);
drivers/ata/pata_ep93xx.c
730
writel(v, base + IDEUDMAOP);
drivers/ata/pata_ep93xx.c
732
writel(v | IDEUDMAOP_UEN, base + IDEUDMAOP);
drivers/ata/pata_ep93xx.c
734
writel(IDECFG_IDEEN | IDECFG_UDMA |
drivers/ata/pata_ep93xx.c
752
writel(0, base + IDEUDMAOP);
drivers/ata/pata_ep93xx.c
753
writel(readl(base + IDECTRL) | IDECTRL_DIOWN | IDECTRL_DIORN |
drivers/ata/pata_macio.c
391
writel(priv->treg[device][0], rbase + IDE_KAUAI_PIO_CONFIG);
drivers/ata/pata_macio.c
392
writel(priv->treg[device][1], rbase + IDE_KAUAI_ULTRA_CONFIG);
drivers/ata/pata_macio.c
394
writel(priv->treg[device][0], rbase + IDE_TIMING_CONFIG);
drivers/ata/pata_macio.c
601
writel((RUN|PAUSE|FLUSH|WAKE|DEAD) << 16, &dma_regs->control);
drivers/ata/pata_macio.c
620
writel(priv->dma_table_dma, &dma_regs->cmdptr);
drivers/ata/pata_macio.c
632
writel(reg, rbase + IDE_TIMING_CONFIG);
drivers/ata/pata_macio.c
647
writel((RUN << 16) | RUN, &dma_regs->control);
drivers/ata/pata_macio.c
662
writel (((RUN|WAKE|DEAD) << 16), &dma_regs->control);
drivers/ata/pata_macio.c
709
writel((FLUSH << 16) | FLUSH, &dma_regs->control);
drivers/ata/pata_macio.c
807
writel(KAUAI_FCR_UATA_MAGIC |
drivers/ata/pata_macio.c
891
writel(fcr, priv->kauai_fcr);
drivers/ata/pdc_adma.c
204
writel((u32)pp->pkt_dma, chan + ADMA_CPB_NEXT);
drivers/ata/sata_gemini.c
157
writel(val, sg->base + GEMINI_SATA0_CTRL);
drivers/ata/sata_gemini.c
163
writel(val, sg->base + GEMINI_SATA1_CTRL);
drivers/ata/sata_highbank.c
219
writel(CPHY_MAP(dev, addr), port_data[sata_port].phy_base + 0x800);
drivers/ata/sata_highbank.c
229
writel(CPHY_MAP(dev, addr), port_data[sata_port].phy_base + 0x800);
drivers/ata/sata_highbank.c
230
writel(data, port_data[sata_port].phy_base + CPHY_ADDR(addr));
drivers/ata/sata_highbank.c
588
writel(ctl, mmio + HOST_CTL);
drivers/ata/sata_inic162x.c
313
writel(val, scr_addr + scr_map[sc_reg] * 4);
drivers/ata/sata_inic162x.c
687
writel(pp->cpb_tbl_dma, port_base + PORT_CPB_CPBLAR);
drivers/ata/sata_mv.c
1091
writel(clks, mmio + IRQ_COAL_TIME_THRESHOLD);
drivers/ata/sata_mv.c
1092
writel(count, mmio + IRQ_COAL_IO_THRESHOLD);
drivers/ata/sata_mv.c
1094
writel(~ALL_PORTS_COAL_IRQ, mmio + IRQ_COAL_CAUSE);
drivers/ata/sata_mv.c
1104
writel(clks, hc_mmio + HC_IRQ_COAL_TIME_THRESHOLD);
drivers/ata/sata_mv.c
1105
writel(count, hc_mmio + HC_IRQ_COAL_IO_THRESHOLD);
drivers/ata/sata_mv.c
1106
writel(~HC_COAL_IRQ, hc_mmio + HC_IRQ_CAUSE);
drivers/ata/sata_mv.c
1111
writel(clks, hc_mmio + HC_IRQ_COAL_TIME_THRESHOLD);
drivers/ata/sata_mv.c
1112
writel(count, hc_mmio + HC_IRQ_COAL_IO_THRESHOLD);
drivers/ata/sata_mv.c
1113
writel(~HC_COAL_IRQ, hc_mmio + HC_IRQ_CAUSE);
drivers/ata/sata_mv.c
1484
writel(new, hpriv->base + GPIO_PORT_CTL);
drivers/ata/sata_mv.c
1537
writel(led_ctrl | SOC_LED_CTRL_BLINK, hc_mmio + SOC_LED_CTRL);
drivers/ata/sata_mv.c
1563
writel(led_ctrl & ~SOC_LED_CTRL_BLINK, hc_mmio + SOC_LED_CTRL);
drivers/ata/sata_mv.c
1855
writel(0, port_mmio + BMDMA_CMD);
drivers/ata/sata_mv.c
1858
writel((pp->sg_tbl_dma[qc->hw_tag] >> 16) >> 16,
drivers/ata/sata_mv.c
2206
writel(fis[i], port_mmio + VENDOR_UNIQUE_FIS);
drivers/ata/sata_mv.c
2857
writel(~ALL_PORTS_COAL_IRQ, mmio + IRQ_COAL_CAUSE);
drivers/ata/sata_mv.c
3059
writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
drivers/ata/sata_mv.c
3067
writel(0x0fcfffff, mmio + FLASH_CTL);
drivers/ata/sata_mv.c
3086
writel(0, mmio + GPIO_PORT_CTL);
drivers/ata/sata_mv.c
3092
writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
drivers/ata/sata_mv.c
3106
writel(tmp, phy_mmio + MV5_LTMODE);
drivers/ata/sata_mv.c
3111
writel(tmp, phy_mmio + MV5_PHY_CTL);
drivers/ata/sata_mv.c
3118
writel(tmp, phy_mmio + MV5_PHY_MODE);
drivers/ata/sata_mv.c
3123
#define ZERO(reg) writel(0, port_mmio + (reg))
drivers/ata/sata_mv.c
3132
writel(0x11f, port_mmio + EDMA_CFG);
drivers/ata/sata_mv.c
3143
writel(0xbc, port_mmio + EDMA_IORDY_TMOUT);
drivers/ata/sata_mv.c
3147
#define ZERO(reg) writel(0, hc_mmio + (reg))
drivers/ata/sata_mv.c
3162
writel(tmp, hc_mmio + 0x20);
drivers/ata/sata_mv.c
3184
#define ZERO(reg) writel(0, mmio + (reg))
drivers/ata/sata_mv.c
3192
writel(tmp, mmio + MV_PCI_MODE);
drivers/ata/sata_mv.c
3196
writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT);
drivers/ata/sata_mv.c
3216
writel(tmp, mmio + GPIO_PORT_CTL);
drivers/ata/sata_mv.c
3239
writel(t | STOP_PCI_MASTER, reg);
drivers/ata/sata_mv.c
3256
writel(t | GLOB_SFT_RST, reg);
drivers/ata/sata_mv.c
3270
writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg);
drivers/ata/sata_mv.c
3305
writel(0x00000060, mmio + GPIO_PORT_CTL);
drivers/ata/sata_mv.c
3324
writel(m2, port_mmio + PHY_MODE2);
drivers/ata/sata_mv.c
3330
writel(m2, port_mmio + PHY_MODE2);
drivers/ata/sata_mv.c
3357
writel(m4, port_mmio + PHY_MODE4);
drivers/ata/sata_mv.c
3365
writel(m3, port_mmio + PHY_MODE3);
drivers/ata/sata_mv.c
3381
writel(m2, port_mmio + PHY_MODE2);
drivers/ata/sata_mv.c
3406
#define ZERO(reg) writel(0, port_mmio + (reg))
drivers/ata/sata_mv.c
3415
writel(0x101f, port_mmio + EDMA_CFG);
drivers/ata/sata_mv.c
3426
writel(0x800, port_mmio + EDMA_IORDY_TMOUT);
drivers/ata/sata_mv.c
3431
#define ZERO(reg) writel(0, hc_mmio + (reg))
drivers/ata/sata_mv.c
3481
writel(reg, port_mmio + PHY_MODE3);
drivers/ata/sata_mv.c
3486
writel(reg, port_mmio + PHY_MODE4);
drivers/ata/sata_mv.c
3492
writel(reg, port_mmio + PHY_MODE9_GEN2);
drivers/ata/sata_mv.c
3498
writel(reg, port_mmio + PHY_MODE9_GEN1);
drivers/ata/sata_mv.c
3643
writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE);
drivers/ata/sata_mv.c
3988
writel(0, hpriv->base + WINDOW_CTRL(i));
drivers/ata/sata_mv.c
3989
writel(0, hpriv->base + WINDOW_BASE(i));
drivers/ata/sata_mv.c
3995
writel(((cs->size - 1) & 0xffff0000) |
drivers/ata/sata_mv.c
3999
writel(cs->base, hpriv->base + WINDOW_BASE(i));
drivers/ata/sata_mv.c
831
writel(data, addr);
drivers/ata/sata_mv.c
957
writel(new, addr); /* unaffected by the errata */
drivers/ata/sata_mv.c
974
writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI);
drivers/ata/sata_mv.c
986
writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI);
drivers/ata/sata_nv.c
1005
writel(notifier_clears[0], pp->notifier_clear_block);
drivers/ata/sata_nv.c
1007
writel(notifier_clears[1], pp->notifier_clear_block);
drivers/ata/sata_nv.c
1083
writel(notifier_clears[0], pp->notifier_clear_block);
drivers/ata/sata_nv.c
1085
writel(notifier_clears[1], pp->notifier_clear_block);
drivers/ata/sata_nv.c
1152
writel(mem_dma & 0xFFFFFFFF, mmio + NV_ADMA_CPB_BASE_LOW);
drivers/ata/sata_nv.c
1153
writel((mem_dma >> 16) >> 16, mmio + NV_ADMA_CPB_BASE_HIGH);
drivers/ata/sata_nv.c
1223
writel(pp->cpb_dma & 0xFFFFFFFF, mmio + NV_ADMA_CPB_BASE_LOW);
drivers/ata/sata_nv.c
1224
writel((pp->cpb_dma >> 16) >> 16, mmio + NV_ADMA_CPB_BASE_HIGH);
drivers/ata/sata_nv.c
1608
writel(NV_INT_ALL_MCP55 << shift, mmio_base + NV_INT_STATUS_MCP55);
drivers/ata/sata_nv.c
1612
writel(mask, mmio_base + NV_INT_ENABLE_MCP55);
drivers/ata/sata_nv.c
1621
writel(NV_INT_ALL_MCP55 << shift, mmio_base + NV_INT_STATUS_MCP55);
drivers/ata/sata_nv.c
1625
writel(mask, mmio_base + NV_INT_ENABLE_MCP55);
drivers/ata/sata_nv.c
1816
writel(~0, mmio + NV_INT_STATUS_MCP55);
drivers/ata/sata_nv.c
1819
writel(0, mmio + NV_INT_ENABLE_MCP55);
drivers/ata/sata_nv.c
1824
writel(tmp, mmio + NV_CTL_MCP55);
drivers/ata/sata_nv.c
1835
writel(~0, mmio + NV_INT_STATUS_MCP55);
drivers/ata/sata_nv.c
1838
writel(0x00fd00fd, mmio + NV_INT_ENABLE_MCP55);
drivers/ata/sata_nv.c
1842
writel(tmp | NV_CTL_PRI_SWNCQ | NV_CTL_SEC_SWNCQ, mmio + NV_CTL_MCP55);
drivers/ata/sata_nv.c
1863
writel(tmp | NV_CTL_PRI_SWNCQ | NV_CTL_SEC_SWNCQ, mmio + NV_CTL_MCP55);
drivers/ata/sata_nv.c
1868
writel(tmp | 0x00fd00fd, mmio + NV_INT_ENABLE_MCP55);
drivers/ata/sata_nv.c
1871
writel(~0x0, mmio + NV_INT_STATUS_MCP55);
drivers/ata/sata_nv.c
2009
writel((1 << qc->hw_tag), pp->sactive_block);
drivers/ata/sata_promise.c
1000
writel(pp->pkt_dma, ata_mmio + PDC_PKT_SUBMIT);
drivers/ata/sata_promise.c
1116
writel(tmp, host_mmio + PDC_FLASH_CTL);
drivers/ata/sata_promise.c
1120
writel(tmp | 0xff, host_mmio + hotplug_offset);
drivers/ata/sata_promise.c
1124
writel(tmp & ~0xff0000, host_mmio + hotplug_offset);
drivers/ata/sata_promise.c
1126
writel(tmp | 0xff0000, host_mmio + hotplug_offset);
drivers/ata/sata_promise.c
1136
writel(tmp, host_mmio + PDC_TBG_MODE);
drivers/ata/sata_promise.c
1145
writel(tmp, host_mmio + PDC_SLEW_CTL);
drivers/ata/sata_promise.c
353
writel(tmp, sata_mmio + PDC_PHYMODE4);
drivers/ata/sata_promise.c
400
writel(0, sata_mmio + PDC_INTERNAL_DEBUG_1);
drivers/ata/sata_promise.c
412
writel(0xffffffff, sata_mmio + PDC_SATA_ERROR);
drivers/ata/sata_promise.c
413
writel(0xffff0000, sata_mmio + PDC_LINK_LAYER_ERRORS);
drivers/ata/sata_promise.c
427
writel(tmp, ata_ctlstat_mmio);
drivers/ata/sata_promise.c
437
writel(tmp, ata_ctlstat_mmio);
drivers/ata/sata_promise.c
441
writel(tmp, ata_ctlstat_mmio);
drivers/ata/sata_promise.c
475
writel(val, link->ap->ioaddr.scr_addr + (sc_reg * 4));
drivers/ata/sata_promise.c
702
writel(tmp, ata_mmio + PDC_CTLSTAT);
drivers/ata/sata_promise.c
723
writel(hotplug_status, host_mmio + hotplug_offset);
drivers/ata/sata_promise.c
740
writel(tmp, ata_mmio + PDC_CTLSTAT);
drivers/ata/sata_promise.c
760
writel(hotplug_status, host_mmio + hotplug_offset);
drivers/ata/sata_promise.c
935
writel(hotplug_status | 0xff, host_mmio + hotplug_offset);
drivers/ata/sata_promise.c
950
writel(mask, host_mmio + PDC_INT_SEQMASK);
drivers/ata/sata_promise.c
995
writel(0x00000001, host_mmio + (seq * 4));
drivers/ata/sata_qstor.c
232
writel(val, link->ap->ioaddr.scr_addr + (sc_reg * 8));
drivers/ata/sata_qstor.c
304
writel(QS_CCF_RUN_PKT, chan + QS_CCT_CFF);
drivers/ata/sata_qstor.c
475
writel((u32) addr, chan + QS_CCF_CPBA);
drivers/ata/sata_qstor.c
476
writel((u32)(addr >> 32), chan + QS_CCF_CPBA + 4);
drivers/ata/sata_sil.c
372
writel(tmp, addr);
drivers/ata/sata_sil.c
413
writel(val, mmio);
drivers/ata/sata_sil.c
542
writel(0, mmio_base + sil_port[ap->port_no].sien);
drivers/ata/sata_sil.c
547
writel(tmp, mmio_base + SIL_SYSCFG);
drivers/ata/sata_sil.c
575
writel(SIL_SIEN_N, mmio_base + sil_port[ap->port_no].sien);
drivers/ata/sata_sil.c
580
writel(tmp, mmio_base + SIL_SYSCFG);
drivers/ata/sata_sil.c
681
writel(tmp & ~0x3, mmio_base + sil_port[i].sfis_cfg);
drivers/ata/sata_sil.c
690
writel(tmp | SIL_INTR_STEERING,
drivers/ata/sata_sil24.c
1081
writel(PORT_CS_PMP_RESUME, port + PORT_CTRL_STAT);
drivers/ata/sata_sil24.c
1109
writel(PORT_IRQ_COMPLETE, port + PORT_IRQ_STAT);
drivers/ata/sata_sil24.c
1224
writel(0, host_base + HOST_FLASH_CMD);
drivers/ata/sata_sil24.c
1227
writel(0, host_base + HOST_CTRL);
drivers/ata/sata_sil24.c
1236
writel(0x20c, port + PORT_PHY_CFG);
drivers/ata/sata_sil24.c
1241
writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
drivers/ata/sata_sil24.c
1255
writel(IRQ_STAT_4PORTS, host_base + HOST_CTRL);
drivers/ata/sata_sil24.c
1339
writel(HOST_CTRL_GLOBAL_RST, host_base + HOST_CTRL);
drivers/ata/sata_sil24.c
476
writel(PORT_CS_CDB16, port + PORT_CTRL_STAT);
drivers/ata/sata_sil24.c
478
writel(PORT_CS_CDB16, port + PORT_CTRL_CLR);
drivers/ata/sata_sil24.c
515
writel(val, scr_addr + sil24_scr_map[sc_reg] * 4);
drivers/ata/sata_sil24.c
527
writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_STAT);
drivers/ata/sata_sil24.c
529
writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR);
drivers/ata/sata_sil24.c
540
writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_CLR);
drivers/ata/sata_sil24.c
543
writel(PORT_CS_PMP_EN | PORT_CS_PMP_RESUME, port + PORT_CTRL_CLR);
drivers/ata/sata_sil24.c
551
writel(PORT_CS_PMP_EN, port + PORT_CTRL_STAT);
drivers/ata/sata_sil24.c
553
writel(PORT_CS_PMP_EN, port + PORT_CTRL_CLR);
drivers/ata/sata_sil24.c
561
writel(PORT_CS_PMP_RESUME, port + PORT_CTRL_CLR);
drivers/ata/sata_sil24.c
566
writel(0, pmp_base + PORT_PMP_STATUS);
drivers/ata/sata_sil24.c
567
writel(0, pmp_base + PORT_PMP_QACTIVE);
drivers/ata/sata_sil24.c
581
writel(PORT_CS_INIT, port + PORT_CTRL_STAT);
drivers/ata/sata_sil24.c
613
writel(PORT_IRQ_COMPLETE | PORT_IRQ_ERROR, port + PORT_IRQ_ENABLE_CLR);
drivers/ata/sata_sil24.c
620
writel((u32)paddr, port + PORT_CMD_ACTIVATE);
drivers/ata/sata_sil24.c
621
writel((u64)paddr >> 32, port + PORT_CMD_ACTIVATE + 4);
drivers/ata/sata_sil24.c
627
writel(irq_mask, port + PORT_IRQ_STAT); /* clear IRQs */
drivers/ata/sata_sil24.c
643
writel(irq_enabled, port + PORT_IRQ_ENABLE_SET);
drivers/ata/sata_sil24.c
708
writel(PORT_CS_PORT_RST, port + PORT_CTRL_STAT);
drivers/ata/sata_sil24.c
710
writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
drivers/ata/sata_sil24.c
729
writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT);
drivers/ata/sata_sil24.c
897
writel((u32)paddr, activate);
drivers/ata/sata_sil24.c
898
writel((u64)paddr >> 32, activate + 4);
drivers/ata/sata_sil24.c
952
writel(0xffff, port + PORT_IRQ_ENABLE_CLR);
drivers/ata/sata_sil24.c
962
writel(tmp, port + PORT_IRQ_STAT);
drivers/ata/sata_sil24.c
965
writel(DEF_PORT_IRQ, port + PORT_IRQ_ENABLE_SET);
drivers/ata/sata_sil24.c
980
writel(irq_stat, port + PORT_IRQ_STAT);
drivers/ata/sata_svw.c
121
writel(val, link->ap->ioaddr.scr_addr + (sc_reg * 4));
drivers/ata/sata_svw.c
240
writel(ap->bmdma_prd_dma, mmio + ATA_DMA_TABLE_OFS);
drivers/ata/sata_svw.c
484
writel(readl(mmio_base + K2_SATA_SICR1_OFFSET) & ~0x00040000,
drivers/ata/sata_svw.c
488
writel(0xffffffff, mmio_base + K2_SATA_SCR_ERROR_OFFSET);
drivers/ata/sata_svw.c
489
writel(0x0, mmio_base + K2_SATA_SIM_OFFSET);
drivers/ata/sata_sx4.c
1003
writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
drivers/ata/sata_sx4.c
1009
writel(0x01, mmio + PDC_GENERAL_CTLR);
drivers/ata/sata_sx4.c
1015
writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
drivers/ata/sata_sx4.c
1018
writel(0x01, mmio + PDC_GENERAL_CTLR);
drivers/ata/sata_sx4.c
1026
writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
drivers/ata/sata_sx4.c
1029
writel(0x01, mmio + PDC_GENERAL_CTLR);
drivers/ata/sata_sx4.c
1050
writel(i2creg, mmio + PDC_I2C_ADDR_DATA);
drivers/ata/sata_sx4.c
1054
writel(PDC_I2C_READ | PDC_I2C_START | PDC_I2C_MASK_INT,
drivers/ata/sata_sx4.c
1155
writel(data, mmio + PDC_DIMM0_CONTROL);
drivers/ata/sata_sx4.c
1178
writel(data, mmio + PDC_SDRAM_CONTROL);
drivers/ata/sata_sx4.c
1191
writel(data, mmio + PDC_SDRAM_CONTROL);
drivers/ata/sata_sx4.c
1199
writel(data, mmio + PDC_SDRAM_CONTROL);
drivers/ata/sata_sx4.c
1231
writel(0xffffffff, mmio + PDC_TIME_PERIOD);
drivers/ata/sata_sx4.c
1236
writel(PDC_TIMER_DEFAULT, mmio + PDC_TIME_CONTROL);
drivers/ata/sata_sx4.c
1277
writel(pci_status, mmio + PDC_CTL_STATUS);
drivers/ata/sata_sx4.c
1374
writel(tmp, mmio + PDC_20621_DIMM_WINDOW);
drivers/ata/sata_sx4.c
1381
writel(tmp, mmio + PDC_HDMA_CTLSTAT);
drivers/ata/sata_sx4.c
1388
writel(tmp, mmio + PDC_HDMA_CTLSTAT);
drivers/ata/sata_sx4.c
466
writel(0x00000001, mmio + PDC_20621_GENERAL_CTL);
drivers/ata/sata_sx4.c
500
writel(0x00000001, mmio + PDC_20621_GENERAL_CTL);
drivers/ata/sata_sx4.c
534
writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
drivers/ata/sata_sx4.c
537
writel(pkt_ofs, mmio + PDC_HDMA_PKT_SUBMIT);
drivers/ata/sata_sx4.c
620
writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
drivers/ata/sata_sx4.c
623
writel(port_ofs + PDC_DIMM_ATA_PKT,
drivers/ata/sata_sx4.c
701
writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
drivers/ata/sata_sx4.c
703
writel(port_ofs + PDC_DIMM_ATA_PKT,
drivers/ata/sata_sx4.c
803
writel(tmp, mmio + PDC_CTLSTAT);
drivers/ata/sata_sx4.c
820
writel(tmp, mmio + PDC_CTLSTAT);
drivers/ata/sata_sx4.c
840
writel(tmp, mmio);
drivers/ata/sata_sx4.c
844
writel(tmp, mmio);
drivers/ata/sata_sx4.c
953
writel(0x01, mmio + PDC_GENERAL_CTLR);
drivers/ata/sata_sx4.c
955
writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
drivers/ata/sata_sx4.c
966
writel(0x01, mmio + PDC_GENERAL_CTLR);
drivers/ata/sata_sx4.c
968
writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
drivers/ata/sata_sx4.c
977
writel(0x01, mmio + PDC_GENERAL_CTLR);
drivers/ata/sata_sx4.c
979
writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
drivers/ata/sata_vsc.c
315
writel(0, base + VSC_SATA_UP_DESCRIPTOR_OFFSET);
drivers/ata/sata_vsc.c
316
writel(0, base + VSC_SATA_UP_DATA_BUFFER_OFFSET);
drivers/ata/sata_vsc.c
99
writel(val, link->ap->ioaddr.scr_addr + (sc_reg * 4));
drivers/atm/eni.c
1151
writel((MID_SEG_TX_ID << MID_SEG_ID_SHIFT) |
drivers/atm/eni.c
1156
writel((vcc->vci << MID_SEG_VCI_SHIFT) |
drivers/atm/eni.c
1162
writel(skb->len,tx->send+
drivers/atm/eni.c
1166
writel(eni_dev->dma[i*2],eni_dev->tx_dma+dma_wr*8);
drivers/atm/eni.c
1167
writel(eni_dev->dma[i*2+1],eni_dev->tx_dma+dma_wr*8+4);
drivers/atm/eni.c
155
#define eni_out(v,r) writel((v),eni_dev->reg+(r)*4)
drivers/atm/eni.c
1752
writel(0x55555555,eni_dev->ram+i);
drivers/atm/eni.c
1755
writel(0xAAAAAAAA,eni_dev->ram+i);
drivers/atm/eni.c
1757
else writel(i,eni_dev->ram+i);
drivers/atm/eni.c
1985
writel((readl(dsc) & ~(MID_SEG_RATE | MID_SEG_PR)) |
drivers/atm/eni.c
2071
writel(value,ENI_DEV(dev)->phy+addr*4);
drivers/atm/eni.c
464
writel(dma[i*2],eni_dev->rx_dma+dma_wr*8);
drivers/atm/eni.c
465
writel(dma[i*2+1],eni_dev->rx_dma+dma_wr*8+4);
drivers/atm/eni.c
631
writel(readl(vci_dsc) & ~MID_VCI_IN_SERVICE,vci_dsc);
drivers/atm/eni.c
821
writel(0,here+4); /* descr, read = 0 */
drivers/atm/eni.c
822
writel(0,here+8); /* write, state, count = 0 */
drivers/atm/eni.c
827
writel(((vcc->qos.aal != ATM_AAL5 ? MID_MODE_RAW : MID_MODE_AAL5) <<
drivers/atm/eni.c
848
writel((readl(here) & ~MID_VCI_MODE) | (MID_MODE_TRASH <<
drivers/atm/eni.c
853
writel(readl(here) & ~MID_VCI_IN_SERVICE,here);
drivers/atm/fore200e.c
446
writel(cpu_to_le32(val), addr);
drivers/atm/fore200e.c
468
writel(PCA200E_HCR_CLRINTR, fore200e->regs.pca.hcr);
drivers/atm/fore200e.c
475
writel(PCA200E_HCR_RESET, fore200e->regs.pca.hcr);
drivers/atm/fore200e.c
477
writel(0, fore200e->regs.pca.hcr);
drivers/atm/he.c
176
#define he_writel(dev, val, reg) do { writel(val, (dev)->membase + (reg)); wmb(); } while (0)
drivers/atm/idt77252.c
1235
writel((unsigned long) card->rsq.next - (unsigned long) card->rsq.base,
drivers/atm/idt77252.c
1392
writel(card->tsq.paddr, SAR_REG_TSQB);
drivers/atm/idt77252.c
1393
writel((unsigned long) card->tsq.next - (unsigned long) card->tsq.base,
drivers/atm/idt77252.c
1524
writel((unsigned long)card->tsq.next - (unsigned long)card->tsq.base,
drivers/atm/idt77252.c
177
writel(SAR_CMD_READ_SRAM | (addr << 2), SAR_REG_CMD);
drivers/atm/idt77252.c
1834
writel(handle, card->fbq[queue]);
drivers/atm/idt77252.c
1835
writel(addr, card->fbq[queue]);
drivers/atm/idt77252.c
199
writel(value, SAR_REG_DR0);
drivers/atm/idt77252.c
200
writel(SAR_CMD_WRITE_SRAM | (addr << 2), SAR_REG_CMD);
drivers/atm/idt77252.c
2104
writel(TCMDQ_LACR|(vc->lacr << 16)|vc->index, SAR_REG_TCMDQ);
drivers/atm/idt77252.c
218
writel(SAR_CMD_READ_UTILITY + ubus_addr, SAR_REG_CMD);
drivers/atm/idt77252.c
2299
writel(TCMDQ_START | vc->index, SAR_REG_TCMDQ);
drivers/atm/idt77252.c
237
writel((u32) value, SAR_REG_DR0);
drivers/atm/idt77252.c
2376
writel(SAR_CMD_OPEN_CONNECTION | (addr << 2), SAR_REG_CMD);
drivers/atm/idt77252.c
238
writel(SAR_CMD_WRITE_UTILITY + ubus_addr, SAR_REG_CMD);
drivers/atm/idt77252.c
2515
writel(SAR_CMD_CLOSE_CONNECTION | (addr << 2), SAR_REG_CMD);
drivers/atm/idt77252.c
2553
writel(TCMDQ_HALT | vc->index, SAR_REG_TCMDQ);
drivers/atm/idt77252.c
2598
writel(TCMDQ_LACR | (vc->lacr << 16) |
drivers/atm/idt77252.c
2725
writel(stat, SAR_REG_STAT); /* reset interrupt */
drivers/atm/idt77252.c
2781
writel(readl(SAR_REG_CFG) & ~(SAR_CFG_FBIE), SAR_REG_CFG);
drivers/atm/idt77252.c
2840
writel(readl(SAR_REG_CFG) | SAR_CFG_FBIE, SAR_REG_CFG);
drivers/atm/idt77252.c
2877
writel(SAR_CMD_OPEN_CONNECTION | (addr << 2),
drivers/atm/idt77252.c
2904
writel(SAR_CMD_CLOSE_CONNECTION | (addr << 2),
drivers/atm/idt77252.c
2958
writel(TCMDQ_START | 0, SAR_REG_TCMDQ);
drivers/atm/idt77252.c
2999
writel(readl(SAR_REG_CFG) | conf, SAR_REG_CFG);
drivers/atm/idt77252.c
3035
writel(readl(SAR_REG_CFG) & ~(conf), SAR_REG_CFG);
drivers/atm/idt77252.c
3060
writel(0, SAR_REG_CFG);
drivers/atm/idt77252.c
3187
writel((SAR_FBQ0_LOW << 28) | (SAR_FB_SIZE_0 / 48), SAR_REG_FBQS0);
drivers/atm/idt77252.c
3188
writel((SAR_FBQ1_LOW << 28) | (SAR_FB_SIZE_1 / 48), SAR_REG_FBQS1);
drivers/atm/idt77252.c
3189
writel((SAR_FBQ2_LOW << 28) | (SAR_FB_SIZE_2 / 48), SAR_REG_FBQS2);
drivers/atm/idt77252.c
3190
writel((SAR_FBQ3_LOW << 28) | (SAR_FB_SIZE_3 / 48), SAR_REG_FBQS3);
drivers/atm/idt77252.c
3226
writel(card->rt_base << 2, SAR_REG_RTBL);
drivers/atm/idt77252.c
3246
writel(card->tst[0] << 2, SAR_REG_TSTB);
drivers/atm/idt77252.c
3250
writel(card->abrst_size | (card->abrst_base << 2),
drivers/atm/idt77252.c
3254
writel(card->fifo_size | (card->fifo_base << 2),
drivers/atm/idt77252.c
3319
writel(SAR_STAT_TMROF, SAR_REG_STAT);
drivers/atm/idt77252.c
3366
writel(readl(SAR_REG_CFG) | conf, SAR_REG_CFG);
drivers/atm/idt77252.c
3398
writel(0, SAR_REG_VPM);
drivers/atm/idt77252.c
3401
writel(0, SAR_REG_GP);
drivers/atm/idt77252.c
3413
writel(card->raw_cell_paddr, SAR_REG_RAWHND);
drivers/atm/idt77252.c
3524
writel(0xffff, SAR_REG_MDFCT);
drivers/atm/idt77252.c
3572
writel(SAR_CFG_SWRST, SAR_REG_CFG);
drivers/atm/idt77252.c
3574
writel(0, SAR_REG_CFG);
drivers/atm/idt77252.c
3585
writel(0, SAR_REG_DR0);
drivers/atm/idt77252.c
3586
writel(SAR_CMD_WRITE_SRAM | (0 << 2), SAR_REG_CMD);
drivers/atm/idt77252.c
3589
writel(ATM_POISON, SAR_REG_DR0);
drivers/atm/idt77252.c
3590
writel(SAR_CMD_WRITE_SRAM | (addr << 2), SAR_REG_CMD);
drivers/atm/idt77252.c
3592
writel(SAR_CMD_READ_SRAM | (0 << 2), SAR_REG_CMD);
drivers/atm/idt77252.c
374
writel(value, SAR_REG_GP);
drivers/atm/idt77252.c
735
writel(TCMDQ_LACR | (vc->lacr << 16) |
drivers/atm/idt77252.c
764
writel(TCMDQ_START_LACR | (vc->lacr << 16) | vc->index,
drivers/atm/idt77252.c
989
writel((unsigned long) card->rsq.last - (unsigned long) card->rsq.base,
drivers/atm/idt77252.c
991
writel(card->rsq.paddr, SAR_REG_RSQB);
drivers/atm/iphase.c
1204
writel(1, iadev->dma+IPHASE5575_RX_COUNTER);
drivers/atm/iphase.c
1368
writel(state & ~(RX_FREEQ_EMPT |/* RX_EXCP_RCVD |*/ RX_PKT_RCVD),
drivers/atm/iphase.c
1452
writel(iadev->rx_dle_dma & 0xfffff000,
drivers/atm/iphase.c
1936
writel(iadev->tx_dle_dma & 0xfffff000,
drivers/atm/iphase.c
2239
writel(STAT_DLERINT, iadev->reg + IPHASE5575_BUS_STATUS_REG);
drivers/atm/iphase.c
2250
writel(STAT_DLETINT, iadev->reg + IPHASE5575_BUS_STATUS_REG);
drivers/atm/iphase.c
2297
writel(0, iadev->reg+IPHASE5575_EXT_RESET);
drivers/atm/iphase.c
2444
writel(ctrl_reg, ia_dev[i]->reg+IPHASE5575_BUS_CONTROL_REG);
drivers/atm/iphase.c
2450
writel(ctrl_reg, ia_dev[i]->reg+IPHASE5575_BUS_CONTROL_REG);
drivers/atm/iphase.c
2466
writel(value, INPH_IA_DEV(dev)->phy+addr);
drivers/atm/iphase.c
2549
writel(ctrl_reg, iadev->reg+IPHASE5575_BUS_CONTROL_REG);
drivers/atm/iphase.c
2565
writel(ctrl_reg | CTRL_FE_RST, iadev->reg+IPHASE5575_BUS_CONTROL_REG);
drivers/atm/iphase.c
3039
writel(2, iadev->dma+IPHASE5575_TX_COUNTER);
drivers/atm/iphase.c
829
writel(val, ia->phy + (reg >> 2));
drivers/atm/iphase.h
1376
writel(t, iadev->reg+IPHASE5575_EEPROM_ACCESS); \
drivers/atm/iphase.h
1390
writel(t, iadev->reg+IPHASE5575_EEPROM_ACCESS); \
drivers/atm/lanai.c
489
writel(val, reg_addr(lanai, reg));
drivers/atm/lanai.c
548
writel(val, sram_addr(lanai, offset));
drivers/atm/lanai.c
666
writel(val, lvcc->vbase + offset);
drivers/atm/nicstar.c
1030
writel(addr2, card->membase + DR3);
drivers/atm/nicstar.c
1031
writel(id2, card->membase + DR2);
drivers/atm/nicstar.c
1032
writel(addr1, card->membase + DR1);
drivers/atm/nicstar.c
1033
writel(id1, card->membase + DR0);
drivers/atm/nicstar.c
1034
writel(NS_CMD_WRITE_FREEBUFQ | NS_PRV_BUFTYPE(skb),
drivers/atm/nicstar.c
1047
writel((readl(card->membase + CFG) | NS_CFG_EFBIE),
drivers/atm/nicstar.c
1076
writel(NS_STAT_TSIF, card->membase + STAT);
drivers/atm/nicstar.c
1081
writel(NS_STAT_TXICP, card->membase + STAT);
drivers/atm/nicstar.c
1088
writel(NS_STAT_TSQF, card->membase + STAT);
drivers/atm/nicstar.c
1095
writel(NS_STAT_TMROF, card->membase + STAT);
drivers/atm/nicstar.c
1101
writel(NS_STAT_PHYI, card->membase + STAT);
drivers/atm/nicstar.c
1110
writel(NS_STAT_SFBQF, card->membase + STAT);
drivers/atm/nicstar.c
1117
writel(NS_STAT_LFBQF, card->membase + STAT);
drivers/atm/nicstar.c
1124
writel(NS_STAT_RSQF, card->membase + STAT);
drivers/atm/nicstar.c
1133
writel(NS_STAT_EOPDU, card->membase + STAT);
drivers/atm/nicstar.c
1138
writel(NS_STAT_RAWCF, card->membase + STAT);
drivers/atm/nicstar.c
1170
writel(NS_STAT_SFBQE, card->membase + STAT);
drivers/atm/nicstar.c
1176
writel(readl(card->membase + CFG) &
drivers/atm/nicstar.c
1195
writel(NS_STAT_LFBQE, card->membase + STAT);
drivers/atm/nicstar.c
1201
writel(readl(card->membase + CFG) &
drivers/atm/nicstar.c
1217
writel(NS_STAT_RSQAF, card->membase + STAT);
drivers/atm/nicstar.c
1432
writel(NS_CMD_CLOSE_CONNECTION | addr << 2,
drivers/atm/nicstar.c
1911
writel(PTR_DIFF(previous, card->tsq.base),
drivers/atm/nicstar.c
1972
writel(PTR_DIFF(previous, card->rsq.base), card->membase + RSQH);
drivers/atm/nicstar.c
218
writel(0x00000000, card->membase + CFG);
drivers/atm/nicstar.c
2450
writel(NS_CMD_READ_UTILITY | 0x00000200 | i,
drivers/atm/nicstar.c
2719
writel(stat_w, card->membase + STAT);
drivers/atm/nicstar.c
2735
writel((u32) value, card->membase + DR0);
drivers/atm/nicstar.c
2736
writel(NS_CMD_WRITE_UTILITY | 0x00000200 | (addr & 0x000000FF),
drivers/atm/nicstar.c
2750
writel(NS_CMD_READ_UTILITY | 0x00000200 | (addr & 0x000000FF),
drivers/atm/nicstar.c
320
writel(sram_address, card->membase + CMD);
drivers/atm/nicstar.c
338
writel(*(value++), card->membase + i);
drivers/atm/nicstar.c
344
writel(sram_address, card->membase + CMD);
drivers/atm/nicstar.c
435
writel(NS_STAT_TMROF, card->membase + STAT);
drivers/atm/nicstar.c
438
writel(NS_CFG_SWRST, card->membase + CFG);
drivers/atm/nicstar.c
440
writel(0x00000000, card->membase + CFG);
drivers/atm/nicstar.c
443
writel(0x00000008, card->membase + GP);
drivers/atm/nicstar.c
445
writel(0x00000001, card->membase + GP);
drivers/atm/nicstar.c
448
writel(NS_CMD_WRITE_UTILITY | 0x00000100, card->membase + CMD); /* Sync UTOPIA with SAR clock */
drivers/atm/nicstar.c
453
writel(NS_CMD_READ_UTILITY | 0x00000200, card->membase + CMD);
drivers/atm/nicstar.c
461
writel(0x00000008, card->membase + DR0);
drivers/atm/nicstar.c
462
writel(NS_CMD_WRITE_UTILITY | 0x00000200, card->membase + CMD);
drivers/atm/nicstar.c
464
writel(NS_STAT_SFBQF, card->membase + STAT);
drivers/atm/nicstar.c
467
writel(0x00000022, card->membase + DR0);
drivers/atm/nicstar.c
468
writel(NS_CMD_WRITE_UTILITY | 0x00000202, card->membase + CMD);
drivers/atm/nicstar.c
477
writel(0x00000002, card->membase + DR0);
drivers/atm/nicstar.c
478
writel(NS_CMD_WRITE_UTILITY | 0x00000205, card->membase + CMD);
drivers/atm/nicstar.c
487
writel(0x00000000, card->membase + GP);
drivers/atm/nicstar.c
530
writel(0x00000000, card->membase + VPM);
drivers/atm/nicstar.c
556
writel(0x00000000, card->membase + TSQH);
drivers/atm/nicstar.c
557
writel(ALIGN(card->tsq.dma, NS_TSQ_ALIGNMENT), card->membase + TSQB);
drivers/atm/nicstar.c
575
writel(0x00000000, card->membase + RSQH);
drivers/atm/nicstar.c
576
writel(ALIGN(card->rsq.dma, NS_RSQ_ALIGNMENT), card->membase + RSQB);
drivers/atm/nicstar.c
613
writel(NS_TST0 << 2, card->membase + TSTB);
drivers/atm/nicstar.c
808
writel(NS_CFG_RXPATH | NS_CFG_SMBUFSIZE | NS_CFG_LGBUFSIZE | NS_CFG_EFBIE | NS_CFG_RSQSIZE | NS_CFG_VPIBITS | ns_cfg_rctsize | NS_CFG_RXINT_NODELAY | NS_CFG_RAWIE | /* Only enabled if RCQ_SUPPORT */
drivers/atm/nicstar.c
820
writel(0x00000000, card->membase + CFG);
drivers/atm/nicstarmac.c
106
writel((val),(base)+(reg))
drivers/auxdisplay/arm-charlcd.c
125
writel(CHAR_RAW_CLEAR, lcd->virtbase + CHAR_RAW);
drivers/auxdisplay/arm-charlcd.c
139
writel(CHAR_RAW_CLEAR, lcd->virtbase + CHAR_RAW);
drivers/auxdisplay/arm-charlcd.c
155
writel(CHAR_RAW_CLEAR, lcd->virtbase + CHAR_RAW);
drivers/auxdisplay/arm-charlcd.c
157
writel(0x01, lcd->virtbase + CHAR_MASK);
drivers/auxdisplay/arm-charlcd.c
180
writel(cmdhi, lcd->virtbase + CHAR_COM);
drivers/auxdisplay/arm-charlcd.c
182
writel(cmdlo, lcd->virtbase + CHAR_COM);
drivers/auxdisplay/arm-charlcd.c
191
writel(chhi, lcd->virtbase + CHAR_DAT);
drivers/auxdisplay/arm-charlcd.c
193
writel(chlo, lcd->virtbase + CHAR_DAT);
drivers/auxdisplay/arm-charlcd.c
225
writel(HD_FUNCSET | HD_FUNCSET_8BIT, lcd->virtbase + CHAR_COM);
drivers/auxdisplay/arm-charlcd.c
227
writel(HD_FUNCSET | HD_FUNCSET_8BIT, lcd->virtbase + CHAR_COM);
drivers/auxdisplay/arm-charlcd.c
229
writel(HD_FUNCSET | HD_FUNCSET_8BIT, lcd->virtbase + CHAR_COM);
drivers/auxdisplay/arm-charlcd.c
232
writel(HD_FUNCSET, lcd->virtbase + CHAR_COM);
drivers/auxdisplay/arm-charlcd.c
82
writel(CHAR_RAW_CLEAR, lcd->virtbase + CHAR_RAW);
drivers/auxdisplay/arm-charlcd.c
98
writel(0x00, lcd->virtbase + CHAR_MASK);
drivers/base/regmap/regmap-mmio.c
122
writel(val, ctx->regs + reg);
drivers/base/regmap/regmap-mmio.c
142
writel(swab32(val), ctx->regs + reg);
drivers/base/regmap/regmap-mmio.c
202
writel(swab32(valp[i]), ctx->regs + reg);
drivers/bcma/driver_chipcommon_b.c
38
writel(offset, mii + BCMA_CCB_MII_MNG_CTL);
drivers/bcma/driver_chipcommon_b.c
40
writel(value, mii + BCMA_CCB_MII_MNG_CMD_DATA);
drivers/bcma/driver_pci_host.c
215
writel(val, mmio);
drivers/bcma/host_soc.c
150
writel(value, core->io_wrap + offset);
drivers/bcma/host_soc.c
46
writel(value, core->io_addr + offset);
drivers/block/mtip32xx/mtip32xx.c
172
writel(HOST_RESET, dd->mmio + HOST_CTL);
drivers/block/mtip32xx/mtip32xx.c
214
writel((1 << MTIP_TAG_BIT(tag)),
drivers/block/mtip32xx/mtip32xx.c
216
writel((1 << MTIP_TAG_BIT(tag)),
drivers/block/mtip32xx/mtip32xx.c
2302
writel(hwdata |
drivers/block/mtip32xx/mtip32xx.c
237
writel(tmp | PORT_CMD_FIS_RX, port->mmio + PORT_CMD);
drivers/block/mtip32xx/mtip32xx.c
239
writel(tmp & ~PORT_CMD_FIS_RX, port->mmio + PORT_CMD);
drivers/block/mtip32xx/mtip32xx.c
263
writel(tmp | PORT_CMD_START, port->mmio + PORT_CMD);
drivers/block/mtip32xx/mtip32xx.c
265
writel(tmp & ~PORT_CMD_START, port->mmio + PORT_CMD);
drivers/block/mtip32xx/mtip32xx.c
2797
writel(readl(dd->mmio + HOST_IRQ_STAT),
drivers/block/mtip32xx/mtip32xx.c
2815
writel(readl(dd->mmio + HOST_CTL) | HOST_IRQ_EN,
drivers/block/mtip32xx/mtip32xx.c
2829
writel(readl(dd->mmio + HOST_CTL) & ~HOST_IRQ_EN,
drivers/block/mtip32xx/mtip32xx.c
2883
writel(readl(dd->mmio + HOST_CTL) & ~HOST_IRQ_EN,
drivers/block/mtip32xx/mtip32xx.c
2949
writel(readl(dd->mmio + HOST_CTL) & ~HOST_IRQ_EN,
drivers/block/mtip32xx/mtip32xx.c
298
writel(0, port->mmio + PORT_IRQ_MASK);
drivers/block/mtip32xx/mtip32xx.c
2988
writel(readl(dd->mmio + HOST_CTL) | HOST_IRQ_EN,
drivers/block/mtip32xx/mtip32xx.c
327
writel((port->command_list_dma >> 16) >> 16,
drivers/block/mtip32xx/mtip32xx.c
329
writel((port->rxfis_dma >> 16) >> 16,
drivers/block/mtip32xx/mtip32xx.c
334
writel(port->command_list_dma & 0xFFFFFFFF,
drivers/block/mtip32xx/mtip32xx.c
336
writel(port->rxfis_dma & 0xFFFFFFFF, port->mmio + PORT_FIS_ADDR);
drivers/block/mtip32xx/mtip32xx.c
339
writel(readl(port->mmio + PORT_SCR_ERR), port->mmio + PORT_SCR_ERR);
drivers/block/mtip32xx/mtip32xx.c
343
writel(0xFFFFFFFF, port->completed[i]);
drivers/block/mtip32xx/mtip32xx.c
346
writel(readl(port->mmio + PORT_IRQ_STAT), port->mmio + PORT_IRQ_STAT);
drivers/block/mtip32xx/mtip32xx.c
349
writel(readl(port->dd->mmio + HOST_IRQ_STAT),
drivers/block/mtip32xx/mtip32xx.c
353
writel(DEF_PORT_IRQ, port->mmio + PORT_IRQ_MASK);
drivers/block/mtip32xx/mtip32xx.c
399
writel(readl(port->mmio + PORT_SCR_CTL) |
drivers/block/mtip32xx/mtip32xx.c
412
writel(readl(port->mmio + PORT_SCR_CTL) & ~1,
drivers/block/mtip32xx/mtip32xx.c
449
writel(readl(dd->mmio + HOST_CTL) | HOST_IRQ_EN,
drivers/block/mtip32xx/mtip32xx.c
529
writel(completed, port->completed[group]);
drivers/block/mtip32xx/mtip32xx.c
658
writel(completed, port->completed[group]);
drivers/block/mtip32xx/mtip32xx.c
677
writel(0xffffffff, dd->mmio + HOST_IRQ_STAT);
drivers/block/mtip32xx/mtip32xx.c
705
writel((1 << 26), dd->port->mmio + PORT_SCR_ERR);
drivers/block/mtip32xx/mtip32xx.c
711
writel((1 << 16), dd->port->mmio + PORT_SCR_ERR);
drivers/block/mtip32xx/mtip32xx.c
746
writel(port_stat, port->mmio + PORT_IRQ_STAT);
drivers/block/mtip32xx/mtip32xx.c
804
writel(hba_stat, dd->mmio + HOST_IRQ_STAT);
drivers/block/mtip32xx/mtip32xx.c
828
writel(1 << MTIP_TAG_BIT(tag), port->cmd_issue[MTIP_TAG_INDEX(tag)]);
drivers/block/n64cart.c
44
writel(value, reg_base + reg);
drivers/bus/da8xx-mstpri.c
242
writel(reg, mstpri + prio_descr->reg);
drivers/bus/fsl-mc/fsl-mc-bus.c
1083
writel(readl(mc->fsl_mc_regs + FSL_MC_GCR1) &
drivers/bus/fsl-mc/fsl-mc-bus.c
1176
writel(readl(mc->fsl_mc_regs + FSL_MC_GCR1) |
drivers/bus/fsl-mc/fsl-mc-bus.c
1234
writel(readl(fsl_mc_regs + FSL_MC_GCR1) | (GCR1_P1_STOP | GCR1_P2_STOP),
drivers/bus/hisi_lpc.c
127
writel(LPC_REG_STARTUP_SIGNAL_START,
drivers/bus/hisi_lpc.c
182
writel(LPC_REG_STARTUP_SIGNAL_START,
drivers/bus/imx-aipstz.c
26
writel(data->default_cfg->mpr0, data->base + IMX_AIPSTZ_MPR0);
drivers/bus/imx-weim.c
194
writel(value[i],
drivers/bus/imx-weim.c
240
writel(reg, base + devtype->wcr_offset);
drivers/bus/mhi/ep/mmio.c
20
writel(val, mhi_cntrl->mmio + offset);
drivers/bus/mhi/host/pci_generic.c
1059
writel(val, addr);
drivers/bus/mvebu-mbus.c
1048
writel(s->mbus_bridge_ctrl,
drivers/bus/mvebu-mbus.c
1050
writel(s->mbus_bridge_base,
drivers/bus/mvebu-mbus.c
1058
writel(s->wins[win].base, addr + WIN_BASE_OFF);
drivers/bus/mvebu-mbus.c
1059
writel(s->wins[win].ctrl, addr + WIN_CTRL_OFF);
drivers/bus/mvebu-mbus.c
1067
writel(s->wins[win].remap_lo, addr_rmp + WIN_REMAP_LO_OFF);
drivers/bus/mvebu-mbus.c
1068
writel(s->wins[win].remap_hi, addr_rmp + WIN_REMAP_HI_OFF);
drivers/bus/mvebu-mbus.c
1122
writel(UNIT_SYNC_BARRIER_ALL,
drivers/bus/mvebu-mbus.c
242
writel(0, addr + WIN_BASE_OFF);
drivers/bus/mvebu-mbus.c
243
writel(0, addr + WIN_CTRL_OFF);
drivers/bus/mvebu-mbus.c
247
writel(0, addr + WIN_REMAP_LO_OFF);
drivers/bus/mvebu-mbus.c
248
writel(0, addr + WIN_REMAP_HI_OFF);
drivers/bus/mvebu-mbus.c
352
writel(base & WIN_BASE_LOW, addr + WIN_BASE_OFF);
drivers/bus/mvebu-mbus.c
353
writel(ctrl, addr + WIN_CTRL_OFF);
drivers/bus/mvebu-mbus.c
363
writel(remap_addr & WIN_REMAP_LOW, addr_rmp + WIN_REMAP_LO_OFF);
drivers/bus/mvebu-mbus.c
364
writel(0, addr_rmp + WIN_REMAP_HI_OFF);
drivers/bus/mvebu-mbus.c
714
writel(mbus->sdramwins_phys_base + DDR_BASE_CS_OFF(i),
drivers/bus/mvebu-mbus.c
716
writel(base, store_addr++);
drivers/bus/mvebu-mbus.c
717
writel(mbus->sdramwins_phys_base + DDR_SIZE_CS_OFF(i),
drivers/bus/mvebu-mbus.c
719
writel(size, store_addr++);
drivers/bus/mvebu-mbus.c
765
writel(mbus->sdramwins_phys_base + DOVE_DDR_BASE_CS_OFF(i),
drivers/bus/mvebu-mbus.c
767
writel(map, store_addr++);
drivers/bus/qcom-ebi2.c
241
writel(val, ebi2_base);
drivers/bus/qcom-ebi2.c
287
writel(slowcfg, ebi2_xmem + csd->slow_cfg);
drivers/bus/qcom-ebi2.c
289
writel(fastcfg, ebi2_xmem + csd->fast_cfg);
drivers/bus/qcom-ebi2.c
342
writel(0UL, ebi2_xmem + EBI2_XMEM_CFG);
drivers/bus/qcom-ebi2.c
347
writel(val, ebi2_base);
drivers/bus/stm32_rifsc.c
645
writel(SEMCR_MUTEX, addr);
drivers/bus/stm32_rifsc.c
663
writel(SEMCR_MUTEX, addr);
drivers/bus/sunxi-rsb.c
286
writel(int_mask, rsb->regs + RSB_INTE);
drivers/bus/sunxi-rsb.c
287
writel(RSB_CTRL_START_TRANS | RSB_CTRL_GLOBAL_INT_ENB,
drivers/bus/sunxi-rsb.c
294
writel(status, rsb->regs + RSB_INTS);
drivers/bus/sunxi-rsb.c
305
writel(RSB_CTRL_ABORT_TRANS, rsb->regs + RSB_CTRL);
drivers/bus/sunxi-rsb.c
308
writel(readl(rsb->regs + RSB_INTS), rsb->regs + RSB_INTS);
drivers/bus/sunxi-rsb.c
363
writel(addr, rsb->regs + RSB_ADDR);
drivers/bus/sunxi-rsb.c
364
writel(RSB_DAR_RTA(rtaddr), rsb->regs + RSB_DAR);
drivers/bus/sunxi-rsb.c
365
writel(cmd, rsb->regs + RSB_CMD);
drivers/bus/sunxi-rsb.c
411
writel(addr, rsb->regs + RSB_ADDR);
drivers/bus/sunxi-rsb.c
412
writel(RSB_DAR_RTA(rtaddr), rsb->regs + RSB_DAR);
drivers/bus/sunxi-rsb.c
413
writel(*buf, rsb->regs + RSB_DATA);
drivers/bus/sunxi-rsb.c
414
writel(cmd, rsb->regs + RSB_CMD);
drivers/bus/sunxi-rsb.c
517
writel(status, rsb->regs + RSB_INTS);
drivers/bus/sunxi-rsb.c
530
writel(RSB_DMCR_DEVICE_START | RSB_DMCR_MODE_DATA |
drivers/bus/sunxi-rsb.c
539
writel(readl(rsb->regs + RSB_INTS), rsb->regs + RSB_INTS);
drivers/bus/sunxi-rsb.c
614
writel(RSB_CMD_STRA, rsb->regs + RSB_CMD);
drivers/bus/sunxi-rsb.c
615
writel(RSB_DAR_RTA(rtaddr) | RSB_DAR_DA(hwaddr),
drivers/bus/sunxi-rsb.c
668
writel(RSB_CTRL_SOFT_RST, rsb->regs + RSB_CTRL);
drivers/bus/sunxi-rsb.c
691
writel(RSB_CCR_SDA_OUT_DELAY(clk_delay) | RSB_CCR_CLK_DIV(clk_div - 1),
drivers/bus/tegra-gmi.c
70
writel(gmi->snor_timing0, gmi->base + TEGRA_GMI_TIMING0);
drivers/bus/tegra-gmi.c
71
writel(gmi->snor_timing1, gmi->base + TEGRA_GMI_TIMING1);
drivers/bus/tegra-gmi.c
74
writel(gmi->snor_config, gmi->base + TEGRA_GMI_CONFIG);
drivers/bus/tegra-gmi.c
86
writel(config, gmi->base + TEGRA_GMI_CONFIG);
drivers/bus/uniphier-system-bus.c
171
writel(val, base_reg + UNIPHIER_SBC_STRIDE * i);
drivers/bus/vexpress-config.c
183
writel(*data, syscfg->base + SYS_CFGDATA);
drivers/bus/vexpress-config.c
184
writel(0, syscfg->base + SYS_CFGSTAT);
drivers/bus/vexpress-config.c
185
writel(command, syscfg->base + SYS_CFGCTRL);
drivers/cache/ax45mp_cache.c
78
writel(pa, base + AX45MP_L2C_REG_CN_ACC_OFFSET(mhartid));
drivers/cache/ax45mp_cache.c
79
writel(l2_op, base + AX45MP_L2C_REG_CN_CMD_OFFSET(mhartid));
drivers/cache/hisi_soc_hha.c
101
writel(reg, soc_hha->base + HISI_HHA_CTRL);
drivers/cache/hisi_soc_hha.c
94
writel(lower_32_bits(addr), soc_hha->base + HISI_HHA_START_L);
drivers/cache/hisi_soc_hha.c
95
writel(upper_32_bits(addr), soc_hha->base + HISI_HHA_START_H);
drivers/cache/hisi_soc_hha.c
96
writel(lower_32_bits(size), soc_hha->base + HISI_HHA_LEN_L);
drivers/cache/hisi_soc_hha.c
97
writel(upper_32_bits(size), soc_hha->base + HISI_HHA_LEN_H);
drivers/cache/sifive_ccache.c
84
writel(val, ccache_base + SIFIVE_CCACHE_ECCINJECTERR);
drivers/char/agp/amd-k7-agp.c
157
writel(virt_to_phys(amd_irongate_private.gatt_pages[i]->real) | 1,
drivers/char/agp/amd-k7-agp.c
165
writel(agp_bridge->scratch_page, cur_gatt+GET_GATT_OFF(addr));
drivers/char/agp/amd-k7-agp.c
224
writel(agp_bridge->gatt_bus_addr, amd_irongate_private.registers+AMD_ATTBASE);
drivers/char/agp/amd-k7-agp.c
245
writel(1, amd_irongate_private.registers+AMD_TLBFLUSH);
drivers/char/agp/amd-k7-agp.c
280
writel(1, amd_irongate_private.registers+AMD_TLBFLUSH);
drivers/char/agp/amd-k7-agp.c
316
writel(agp_generic_mask_memory(agp_bridge,
drivers/char/agp/amd-k7-agp.c
339
writel(agp_bridge->scratch_page, cur_gatt+GET_GATT_OFF(addr));
drivers/char/agp/amd-k7-agp.c
49
writel(agp_bridge->scratch_page, page_map->remapped+i);
drivers/char/agp/amd64-agp.c
91
writel(pte, agp_bridge->gatt_table+j);
drivers/char/agp/ati-agp.c
177
writel(1, ati_generic_private.registers+ATI_GART_CACHE_CNTRL);
drivers/char/agp/ati-agp.c
225
writel(0x60000, ati_generic_private.registers+ATI_GART_FEATURE_ID);
drivers/char/agp/ati-agp.c
233
writel(agp_bridge->gatt_bus_addr, ati_generic_private.registers+ATI_GART_BASE);
drivers/char/agp/ati-agp.c
296
writel(agp_bridge->driver->mask_memory(agp_bridge,
drivers/char/agp/ati-agp.c
324
writel(agp_bridge->scratch_page, cur_gatt+GET_GATT_OFF(addr));
drivers/char/agp/ati-agp.c
385
writel(virt_to_phys(ati_generic_private.gatt_pages[i]->real) | 1,
drivers/char/agp/ati-agp.c
393
writel(agp_bridge->scratch_page, cur_gatt+GET_GATT_OFF(addr));
drivers/char/agp/ati-agp.c
73
writel(agp_bridge->scratch_page, page_map->remapped+i);
drivers/char/agp/generic.c
1094
writel(bridge->driver->mask_memory(bridge,
drivers/char/agp/generic.c
1136
writel(bridge->scratch_page, bridge->gatt_table+i);
drivers/char/agp/generic.c
960
writel(bridge->scratch_page, bridge->gatt_table+i);
drivers/char/agp/intel-gtt.c
1145
writel(1, intel_private.i9xx_flush_page);
drivers/char/agp/intel-gtt.c
192
writel(virt_to_phys(gtt_table) | I810_PGETBL_ENABLED,
drivers/char/agp/intel-gtt.c
209
writel(0, intel_private.registers+I810_PGETBL_CTL);
drivers/char/agp/intel-gtt.c
455
writel(pgetbl_ctl2, intel_private.registers+I965_PGETBL_CTL2);
drivers/char/agp/intel-gtt.c
461
writel(pgetbl_ctl, intel_private.registers+I810_PGETBL_CTL);
drivers/char/agp/intel-gtt.c
736
writel(readl(intel_private.registers+I830_HIC) | (1<<31),
drivers/char/agp/intel-gtt.c
798
writel(0, intel_private.registers+GFX_FLSH_CNTL);
drivers/char/agp/intel-gtt.c
801
writel(intel_private.PGETBL_save, reg);
drivers/char/agp/intel-gtt.c
810
writel(0, intel_private.registers+GFX_FLSH_CNTL);
drivers/char/agp/nvidia-agp.c
228
writel(agp_bridge->driver->mask_memory(agp_bridge,
drivers/char/agp/nvidia-agp.c
255
writel(agp_bridge->scratch_page, agp_bridge->gatt_table+nvidia_private.pg_offset+i);
drivers/char/agp/parisc-agp.c
222
writel(command, info->lba_regs + info->lba_cap_offset + PCI_AGP_COMMAND);
drivers/char/agp/sworks-agp.c
157
writel(agp_bridge->scratch_page, serverworks_private.scratch_dir.remapped+i);
drivers/char/agp/sworks-agp.c
158
writel(virt_to_phys(serverworks_private.scratch_dir.real) | 1, page_dir.remapped+i);
drivers/char/agp/sworks-agp.c
182
writel(virt_to_phys(serverworks_private.gatt_pages[i]->real)|1, page_dir.remapped+i);
drivers/char/agp/sworks-agp.c
250
writel(1, serverworks_private.registers+SVWRKS_DIRFLUSH);
drivers/char/agp/sworks-agp.c
280
writel(agp_bridge->gatt_bus_addr, serverworks_private.registers+SVWRKS_GATTBASE);
drivers/char/agp/sworks-agp.c
349
writel(agp_bridge->driver->mask_memory(agp_bridge,
drivers/char/agp/sworks-agp.c
374
writel(agp_bridge->scratch_page, cur_gatt+GET_GATT_OFF(addr));
drivers/char/agp/sworks-agp.c
61
writel(agp_bridge->scratch_page, page_map->remapped+i);
drivers/char/hpet.c
153
writel(isr, &devp->hd_hpet->hpet_isr);
drivers/char/hpet.c
182
writel(v, &timer->hpet_config);
drivers/char/hpet.c
216
writel(v, &timer->hpet_config);
drivers/char/hpet.c
471
writel(readl(&timer->hpet_config) & ~Tn_TYPE_CNF_MASK,
drivers/char/hpet.c
477
writel(isr, &hpet->hpet_isr);
drivers/char/hpet.c
533
writel(isr, &hpet->hpet_isr);
drivers/char/hpet.c
60
#define write_counter(V, MC) writel(V, MC)
drivers/char/hw_random/airoha-trng.c
132
writel(val, trng->base + TRNG_NS_SEK_AND_DAT_EN);
drivers/char/hw_random/airoha-trng.c
135
writel(SW_RST, trng->base + TRNG_HEALTH_TEST_SW_RST);
drivers/char/hw_random/airoha-trng.c
200
writel(val, trng->base + TRNG_INTR_EN);
drivers/char/hw_random/airoha-trng.c
205
writel(val, trng->base + TRNG_NS_SEK_AND_DAT_EN);
drivers/char/hw_random/airoha-trng.c
208
writel(SW_RST, trng->base + TRNG_HEALTH_TEST_SW_RST);
drivers/char/hw_random/airoha-trng.c
60
writel(val, trng->base + TRNG_INTR_EN);
drivers/char/hw_random/airoha-trng.c
71
writel(val, trng->base + TRNG_INTR_EN);
drivers/char/hw_random/airoha-trng.c
84
writel(val, trng->base + TRNG_NS_SEK_AND_DAT_EN);
drivers/char/hw_random/airoha-trng.c
88
writel(0, trng->base + TRNG_HEALTH_TEST_SW_RST);
drivers/char/hw_random/atmel-rng.c
101
writel(TRNG_HALFR, trng->base + TRNG_MR);
drivers/char/hw_random/atmel-rng.c
104
writel(TRNG_KEY | 1, trng->base + TRNG_CR);
drivers/char/hw_random/atmel-rng.c
111
writel(TRNG_KEY, trng->base + TRNG_CR);
drivers/char/hw_random/bcm2835-rng.c
60
writel(val, priv->base + offset);
drivers/char/hw_random/imx-rngc.c
102
writel(ctrl, rngc->base + RNGC_CONTROL);
drivers/char/hw_random/imx-rngc.c
114
writel(cmd | RNGC_CMD_SELF_TEST, rngc->base + RNGC_COMMAND);
drivers/char/hw_random/imx-rngc.c
189
writel(cmd | RNGC_CMD_CLR_ERR, rngc->base + RNGC_COMMAND);
drivers/char/hw_random/imx-rngc.c
197
writel(cmd | RNGC_CMD_SEED, rngc->base + RNGC_COMMAND);
drivers/char/hw_random/imx-rngc.c
219
writel(ctrl, rngc->base + RNGC_CONTROL);
drivers/char/hw_random/imx-rngc.c
84
writel(ctrl, rngc->base + RNGC_CONTROL);
drivers/char/hw_random/imx-rngc.c
93
writel(cmd, rngc->base + RNGC_COMMAND);
drivers/char/hw_random/ingenic-rng.c
123
writel(0, priv->base + RNG_REG_ERNG_OFFSET);
drivers/char/hw_random/ingenic-rng.c
43
writel(ERNG_ENABLE, priv->base + RNG_REG_ERNG_OFFSET);
drivers/char/hw_random/ingenic-rng.c
52
writel(0, priv->base + RNG_REG_ERNG_OFFSET);
drivers/char/hw_random/ingenic-trng.c
42
writel(ctrl, trng->base + TRNG_REG_CFG_OFFSET);
drivers/char/hw_random/ingenic-trng.c
54
writel(ctrl, trng->base + TRNG_REG_CFG_OFFSET);
drivers/char/hw_random/jh7110-trng.c
138
writel(data, trng->base + STARFIVE_ISTAT);
drivers/char/hw_random/jh7110-trng.c
153
writel(cmd, trng->base + STARFIVE_CTRL);
drivers/char/hw_random/jh7110-trng.c
161
writel(cmd, trng->base + STARFIVE_CTRL);
drivers/char/hw_random/jh7110-trng.c
179
writel(autoage, trng->base + STARFIVE_AUTO_AGE);
drivers/char/hw_random/jh7110-trng.c
180
writel(autoreq, trng->base + STARFIVE_AUTO_RQSTS);
drivers/char/hw_random/jh7110-trng.c
186
writel(intr, trng->base + STARFIVE_IE);
drivers/char/hw_random/jh7110-trng.c
202
writel(mode, trng->base + STARFIVE_MODE);
drivers/char/hw_random/jh7110-trng.c
214
writel(STARFIVE_ISTAT_RAND_RDY, trng->base + STARFIVE_ISTAT);
drivers/char/hw_random/jh7110-trng.c
219
writel(STARFIVE_ISTAT_SEED_DONE, trng->base + STARFIVE_ISTAT);
drivers/char/hw_random/jh7110-trng.c
224
writel(STARFIVE_ISTAT_LFSR_LOCKUP, trng->base + STARFIVE_ISTAT);
drivers/char/hw_random/jh7110-trng.c
227
writel(STARFIVE_CTRL_EXEC_RANDRESEED, trng->base + STARFIVE_CTRL);
drivers/char/hw_random/jh7110-trng.c
238
writel(0, trng->base + STARFIVE_CTRL);
drivers/char/hw_random/ks-sa-rng.c
124
writel(0, &ks_sa_rng->reg_rng->control);
drivers/char/hw_random/ks-sa-rng.c
126
writel(value, &ks_sa_rng->reg_rng->control);
drivers/char/hw_random/ks-sa-rng.c
135
writel(value, &ks_sa_rng->reg_rng->config);
drivers/char/hw_random/ks-sa-rng.c
138
writel(0, &ks_sa_rng->reg_rng->intmask);
drivers/char/hw_random/ks-sa-rng.c
143
writel(value, &ks_sa_rng->reg_rng->control);
drivers/char/hw_random/ks-sa-rng.c
157
writel(0, &ks_sa_rng->reg_rng->control);
drivers/char/hw_random/ks-sa-rng.c
170
writel(TRNG_INTACK_REG_READY, &ks_sa_rng->reg_rng->intack);
drivers/char/hw_random/mtk-rng.c
54
writel(val, priv->base + RNG_CTRL);
drivers/char/hw_random/mtk-rng.c
66
writel(val, priv->base + RNG_CTRL);
drivers/char/hw_random/npcm-rng.c
115
writel(NPCM_RNG_M1ROSEL, priv->base + NPCM_RNGMODE_REG);
drivers/char/hw_random/npcm-rng.c
43
writel(priv->clkp | NPCM_RNG_ENABLE, priv->base + NPCM_RNGCS_REG);
drivers/char/hw_random/npcm-rng.c
52
writel(priv->clkp, priv->base + NPCM_RNGCS_REG);
drivers/char/hw_random/pic32-rng.c
45
writel(TRNGEN | TRNGMOD, priv->base + RNGCON);
drivers/char/hw_random/pic32-rng.c
74
writel(0, priv->base + RNGCON);
drivers/char/hw_random/rockchip-rng.c
144
writel((mask << 16) | val, rng->base + TRNG_RNG_CTL);
drivers/char/hw_random/rockchip-rng.c
149
writel(val, rng->base + offset);
drivers/char/hw_random/rockchip-rng.c
180
writel(RK_RNG_SAMPLE_CNT, rk_rng->base + TRNG_RNG_SAMPLE_CNT);
drivers/char/hw_random/xgene-rng.c
111
writel(fro_val, ctx->csr_base + RNG_FRODETUNE);
drivers/char/hw_random/xgene-rng.c
112
writel(0x00000000, ctx->csr_base + RNG_ALARMMASK);
drivers/char/hw_random/xgene-rng.c
113
writel(0x00000000, ctx->csr_base + RNG_ALARMSTOP);
drivers/char/hw_random/xgene-rng.c
114
writel(0xFFFFFFFF, ctx->csr_base + RNG_FROENABLE);
drivers/char/hw_random/xgene-rng.c
197
writel(val, ctx->csr_base + RNG_INTR_STS_ACK);
drivers/char/hw_random/xgene-rng.c
234
writel(READY_MASK, ctx->csr_base + RNG_INTR_STS_ACK);
drivers/char/hw_random/xgene-rng.c
243
writel(0x00000000, ctx->csr_base + RNG_CONTROL);
drivers/char/hw_random/xgene-rng.c
247
writel(val, ctx->csr_base + RNG_CONFIG);
drivers/char/hw_random/xgene-rng.c
250
writel(val, ctx->csr_base + RNG_ALARMCNT);
drivers/char/hw_random/xgene-rng.c
254
writel(MONOBIT_FAIL_MASK |
drivers/char/hw_random/xgene-rng.c
271
writel(val, ctx->csr_base + RNG_CONTROL);
drivers/char/hw_random/xiphera-trng.c
112
writel(HOST_TO_TRNG_ACK_ZEROIZE, trng->mem + CONTROL_REG);
drivers/char/hw_random/xiphera-trng.c
48
writel(HOST_TO_TRNG_READ, trng->mem + CONTROL_REG);
drivers/char/hw_random/xiphera-trng.c
49
writel(HOST_TO_TRNG_ENABLE, trng->mem + CONTROL_REG);
drivers/char/hw_random/xiphera-trng.c
78
writel(HOST_TO_TRNG_RESET, trng->mem + CONTROL_REG);
drivers/char/hw_random/xiphera-trng.c
97
writel(HOST_TO_TRNG_RELEASE_RESET, trng->mem + CONTROL_REG);
drivers/char/hw_random/xiphera-trng.c
98
writel(HOST_TO_TRNG_ENABLE, trng->mem + CONTROL_REG);
drivers/char/hw_random/xiphera-trng.c
99
writel(HOST_TO_TRNG_ZEROIZE, trng->mem + CONTROL_REG);
drivers/char/ipmi/bt-bmc.c
369
writel(reg, bt_bmc->base + BT_CR2);
drivers/char/ipmi/bt-bmc.c
402
writel(reg, bt_bmc->base + BT_CR1);
drivers/char/ipmi/bt-bmc.c
450
writel((BT_IO_BASE << BT_CR0_IO_BASE) |
drivers/char/ipmi/ipmi_si_ls2k.c
102
writel(readl(addr + LS2K_KCS_WR_REQ) + 1, addr + LS2K_KCS_WR_REQ);
drivers/char/ipmi/ipmi_si_ls2k.c
123
writel(readl(addr + LS2K_KCS_WR_REQ) + 1, addr + LS2K_KCS_WR_REQ);
drivers/char/ipmi/ipmi_si_mem_io.c
41
writel(b << io->regshift, (io->addr)+(offset * io->regspacing));
drivers/clk/aspeed/clk-ast2700.c
793
writel(clk, gate->reg + 0x04);
drivers/clk/aspeed/clk-ast2700.c
804
writel(clk, gate->reg);
drivers/clk/aspeed/clk-ast2700.c
859
writel(val, clk_ctrl->base + SCU1_CLK_SEL2);
drivers/clk/at91/sckc.c
151
writel((readl(sckcr) & ~osc->bits->cr_osc32en) |
drivers/clk/at91/sckc.c
193
writel(readl(sckcr) | osc->bits->cr_rcen, sckcr);
drivers/clk/at91/sckc.c
208
writel(readl(sckcr) & ~osc->bits->cr_rcen, sckcr);
drivers/clk/at91/sckc.c
297
writel(tmp, sckcr);
drivers/clk/at91/sckc.c
79
writel(tmp | osc->bits->cr_osc32en, sckcr);
drivers/clk/at91/sckc.c
98
writel(tmp & ~osc->bits->cr_osc32en, sckcr);
drivers/clk/axis/clk-artpec6.c
188
writel(muxreg, clkdata->syscon_base + 0x14);
drivers/clk/axis/clk-artpec6.c
197
writel(muxreg, clkdata->syscon_base + 0x14);
drivers/clk/bcm/clk-bcm2835.c
337
writel(CM_PASSWORD | val, cprman->regs + reg);
drivers/clk/bcm/clk-iproc-asiu.c
139
writel(val, asiu->div_base + clk->div.offset);
drivers/clk/bcm/clk-iproc-asiu.c
167
writel(val, asiu->div_base + clk->div.offset);
drivers/clk/bcm/clk-iproc-asiu.c
48
writel(val, asiu->gate_base + clk->gate.offset);
drivers/clk/bcm/clk-iproc-asiu.c
65
writel(val, asiu->gate_base + clk->gate.offset);
drivers/clk/bcm/clk-iproc-pll.c
168
writel(val, base + offset);
drivers/clk/bcm/clk-kona.c
114
writel(reg_val, ccu->base + reg_offset);
drivers/clk/clk-axi-clkgen.c
242
writel(val, axi_clkgen->base + reg);
drivers/clk/clk-bm1880.c
654
writel(val, reg_addr);
drivers/clk/clk-clps711x.c
105
writel(tmp, base + CLPS711X_SYSCON1);
drivers/clk/clk-divider.c
42
writel(val, divider->reg);
drivers/clk/clk-en7523.c
455
writel(val, np_base + REG_PCI_CONTROL);
drivers/clk/clk-en7523.c
460
writel(val, np_base + REG_PCI_CONTROL);
drivers/clk/clk-en7523.c
467
writel(val & ~mask, np_base + REG_RESET_CONTROL1);
drivers/clk/clk-en7523.c
469
writel(val | mask, np_base + REG_RESET_CONTROL1);
drivers/clk/clk-en7523.c
471
writel(val & ~mask, np_base + REG_RESET_CONTROL1);
drivers/clk/clk-en7523.c
477
writel(val & ~mask, np_base + REG_PCI_CONTROL);
drivers/clk/clk-en7523.c
479
writel(val | mask, np_base + REG_PCI_CONTROL);
drivers/clk/clk-en7523.c
493
writel(val, np_base + REG_PCI_CONTROL);
drivers/clk/clk-en7523.c
542
writel(val | mask, np_base + REG_PCI_CONTROL);
drivers/clk/clk-en7523.c
557
writel(val & ~mask, np_base + REG_PCI_CONTROL);
drivers/clk/clk-en7523.c
664
writel(val, addr);
drivers/clk/clk-en7523.c
750
writel(val, base + REG_NP_SCU_SSTR);
drivers/clk/clk-en7523.c
752
writel(val | 3, base + REG_NP_SCU_PCIC);
drivers/clk/clk-fractional-divider.c
66
writel(val, fd->reg);
drivers/clk/clk-fsl-sai.c
57
writel(CR2_BCD, base + I2S_CR2);
drivers/clk/clk-gate.c
40
writel(val, gate->reg);
drivers/clk/clk-highbank.c
159
writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg);
drivers/clk/clk-highbank.c
161
writel(reg | HB_PLL_RESET, hbclk->reg);
drivers/clk/clk-highbank.c
164
writel(reg | HB_PLL_RESET, hbclk->reg);
drivers/clk/clk-highbank.c
165
writel(reg, hbclk->reg);
drivers/clk/clk-highbank.c
174
writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg);
drivers/clk/clk-highbank.c
177
writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg);
drivers/clk/clk-highbank.c
179
writel(reg, hbclk->reg);
drivers/clk/clk-highbank.c
256
writel(div >> 1, hbclk->reg);
drivers/clk/clk-highbank.c
50
writel(reg, hbclk->reg);
drivers/clk/clk-highbank.c
67
writel(reg, hbclk->reg);
drivers/clk/clk-highbank.c
77
writel(reg, hbclk->reg);
drivers/clk/clk-highbank.c
89
writel(reg, hbclk->reg);
drivers/clk/clk-k210.c
350
writel(reg, regs + K210_SYSCTL_SEL0);
drivers/clk/clk-k210.c
374
writel(reg, pll->lock);
drivers/clk/clk-k210.c
412
writel(reg, pll->reg);
drivers/clk/clk-k210.c
419
writel(reg, pll->reg);
drivers/clk/clk-k210.c
421
writel(reg, pll->reg);
drivers/clk/clk-k210.c
425
writel(reg, pll->reg);
drivers/clk/clk-k210.c
431
writel(reg, pll->reg);
drivers/clk/clk-k210.c
467
writel(reg, pll->reg);
drivers/clk/clk-k210.c
471
writel(reg, pll->reg);
drivers/clk/clk-k210.c
519
writel(reg, pll->reg);
drivers/clk/clk-k210.c
688
writel(reg, ksc->regs + cfg->gate_reg);
drivers/clk/clk-k210.c
708
writel(reg, ksc->regs + cfg->gate_reg);
drivers/clk/clk-k210.c
726
writel(reg, ksc->regs + cfg->mux_reg);
drivers/clk/clk-lan966x.c
109
writel(val, gck->reg);
drivers/clk/clk-lan966x.c
120
writel(val, gck->reg);
drivers/clk/clk-lan966x.c
137
writel(val, gck->reg);
drivers/clk/clk-lan966x.c
191
writel(val, gck->reg);
drivers/clk/clk-loongson1.c
126
writel(val, ls1x_clk->reg);
drivers/clk/clk-loongson1.c
131
writel(val, ls1x_clk->reg);
drivers/clk/clk-loongson1.c
139
writel(val, ls1x_clk->reg);
drivers/clk/clk-milbeaut.c
309
writel(reg, mux->reg);
drivers/clk/clk-milbeaut.c
432
writel(val, divider->reg);
drivers/clk/clk-milbeaut.c
435
writel(M10V_DCHREQ, divider->write_valid_reg);
drivers/clk/clk-multiplier.c
28
writel(val, mult->reg);
drivers/clk/clk-mux.c
40
writel(val, mux->reg);
drivers/clk/clk-nomadik.c
116
writel(val, src_base + SRC_CR);
drivers/clk/clk-nomadik.c
134
writel(val, src_base + SRC_XTALCR);
drivers/clk/clk-nomadik.c
178
writel(val, src_base + SRC_PLLCR);
drivers/clk/clk-nomadik.c
182
writel(val, src_base + SRC_PLLCR);
drivers/clk/clk-nomadik.c
198
writel(val, src_base + SRC_PLLCR);
drivers/clk/clk-nomadik.c
202
writel(val, src_base + SRC_PLLCR);
drivers/clk/clk-nomadik.c
310
writel(sclk->clkbit, src_base + enreg);
drivers/clk/clk-nomadik.c
323
writel(sclk->clkbit, src_base + disreg);
drivers/clk/clk-nomadik.c
76
writel(val, src_base + SRC_XTALCR);
drivers/clk/clk-plldig.c
164
writel(val, data->regs + PLLDIG_REG_PLLDV);
drivers/clk/clk-plldig.c
210
writel(val, data->regs + PLLDIG_REG_PLLDV);
drivers/clk/clk-plldig.c
216
writel(val, data->regs + PLLDIG_REG_PLLFD);
drivers/clk/clk-plldig.c
76
writel(val, data->regs + PLLDIG_REG_PLLFM);
drivers/clk/clk-plldig.c
91
writel(val, data->regs + PLLDIG_REG_PLLFM);
drivers/clk/clk-sp7021.c
321
writel(r0, clk->reg);
drivers/clk/clk-sp7021.c
322
writel(r1, clk->reg + 4);
drivers/clk/clk-sp7021.c
323
writel(r2, clk->reg + 8);
drivers/clk/clk-sp7021.c
376
writel(0xffff0000 | pp[i], clk->reg + (i * 4));
drivers/clk/clk-sp7021.c
501
writel(reg, clk->reg);
drivers/clk/clk-sp7021.c
511
writel(BIT(clk->pd_bit + 16) | BIT(clk->pd_bit), clk->reg);
drivers/clk/clk-sp7021.c
520
writel(BIT(clk->pd_bit + 16), clk->reg);
drivers/clk/clk-sp7021.c
614
writel((sp_clken[i] << 16) | sp_clken[i], clk_base + i * 4);
drivers/clk/clk-sparx5.c
151
writel(val, pll->reg);
drivers/clk/clk-sparx5.c
162
writel(val, pll->reg);
drivers/clk/clk-sparx5.c
187
writel(val, pll->reg);
drivers/clk/clk-stm32f4.c
1047
writel(val | BIT(16), base + STM32F4_RCC_BDCR);
drivers/clk/clk-stm32f4.c
1048
writel(val & ~BIT(16), base + STM32F4_RCC_BDCR);
drivers/clk/clk-stm32f4.c
717
writel(sscgr, base + STM32F4_RCC_SSCGR);
drivers/clk/clk-stm32f4.c
740
writel(val, base + pll->offset);
drivers/clk/clk-vt8500.c
101
writel(en_val, cdev->en_reg);
drivers/clk/clk-vt8500.c
190
writel(divisor, cdev->div_reg);
drivers/clk/clk-vt8500.c
590
writel(pll_val, pll->reg);
drivers/clk/clk-vt8500.c
85
writel(en_val, cdev->en_reg);
drivers/clk/clk-xgene.c
329
writel(val, fd->reg);
drivers/clk/davinci/pll.c
186
writel(mult - 1, pll->base + PLLM);
drivers/clk/davinci/pll.c
317
writel(ctrl, pll->base + PLLCTL);
drivers/clk/davinci/pll.c
323
writel(ctrl, pll->base + PLLCTL);
drivers/clk/davinci/pll.c
329
writel(ctrl, pll->base + PLLCTL);
drivers/clk/davinci/pll.c
335
writel(ctrl, pll->base + PLLCTL);
drivers/clk/davinci/pll.c
612
writel(oscdiv, base + OSCDIV);
drivers/clk/davinci/pll.c
651
writel(pllcmd, pll->base + PLLCMD);
drivers/clk/hisilicon/clk-hisi-phase.c
81
writel(val, phase->reg);
drivers/clk/hisilicon/reset.c
57
writel(reg | BIT(bit), rstc->membase + offset);
drivers/clk/hisilicon/reset.c
78
writel(reg & ~BIT(bit), rstc->membase + offset);
drivers/clk/imx/clk-composite-7ulp.c
50
writel(val, gate->reg);
drivers/clk/imx/clk-composite-8m.c
102
writel(val, divider->reg);
drivers/clk/imx/clk-composite-8m.c
168
writel(reg, mux->reg);
drivers/clk/imx/clk-composite-8m.c
169
writel(reg, mux->reg);
drivers/clk/imx/clk-composite-8m.c
201
writel(val, gate->reg);
drivers/clk/imx/clk-composite-93.c
126
writel(val, divider->reg);
drivers/clk/imx/clk-composite-93.c
162
writel(reg, mux->reg);
drivers/clk/imx/clk-composite-93.c
62
writel(reg, gate->reg);
drivers/clk/imx/clk-divider-gate.c
119
writel(val, div->reg);
drivers/clk/imx/clk-divider-gate.c
139
writel(0, div->reg);
drivers/clk/imx/clk-divider-gate.c
93
writel(val, div->reg);
drivers/clk/imx/clk-fixup-div.c
75
writel(val, div->reg);
drivers/clk/imx/clk-fixup-mux.c
55
writel(val, mux->reg);
drivers/clk/imx/clk-gate-93.c
55
writel(val, gate->reg + LPM_CUR_OFFSET);
drivers/clk/imx/clk-gate-93.c
61
writel(val, gate->reg + DIRECT_OFFSET);
drivers/clk/imx/clk-gate2.c
50
writel(reg, gate->reg);
drivers/clk/imx/clk-imx5.c
461
writel(val, MXC_CCM_CCDR);
drivers/clk/imx/clk-imx5.c
465
writel(val, MXC_CCM_CLPCR);
drivers/clk/imx/clk-imx6q.c
568
writel(readl(base + 0x160) & ~0x3c00, base + 0x160);
drivers/clk/imx/clk-imx8mp-audiomix.c
269
writel(priv->regs_save[i], base + audiomix_regs[i]);
drivers/clk/imx/clk-imx8ulp.c
111
writel(val, pcc_reset->base + offset);
drivers/clk/imx/clk-imx8ulp.c
93
writel(val, pcc_reset->base + offset);
drivers/clk/imx/clk-imx95-blk-ctl.c
471
writel(bc->clk_reg_restore, bc->base + bc->pdata->clk_reg_offset);
drivers/clk/imx/clk-imx95-blk-ctl.c
503
writel(bc->clk_reg_restore, bc->base + bc->pdata->clk_reg_offset);
drivers/clk/imx/clk-lpcg-scu.c
180
writel(clk->state, clk->reg);
drivers/clk/imx/clk-lpcg-scu.c
49
writel(val, reg);
drivers/clk/imx/clk-pll14xx.c
329
writel(tmp, pll->base + GNRL_CTL);
drivers/clk/imx/clk-sscg-pll.c
369
writel(val, pll->base + PLL_CFG0);
drivers/clk/imx/clk-sscg-pll.c
406
writel(val, pll->base + PLL_CFG0);
drivers/clk/ingenic/cgu.c
235
writel(ctl, cgu->base + pll_info->reg);
drivers/clk/ingenic/cgu.c
268
writel(ctl, cgu->base + pll_info->bypass_reg);
drivers/clk/ingenic/cgu.c
275
writel(ctl, cgu->base + pll_info->reg);
drivers/clk/ingenic/cgu.c
300
writel(ctl, cgu->base + pll_info->reg);
drivers/clk/ingenic/cgu.c
398
writel(reg, cgu->base + clk_info->mux.reg);
drivers/clk/ingenic/cgu.c
566
writel(reg, cgu->base + clk_info->div.reg);
drivers/clk/ingenic/cgu.c
72
writel(clkgr, cgu->base + info->reg);
drivers/clk/ingenic/jz4770-cgu.c
56
writel(readl(reg_opcr) & ~OPCR_SPENDH, reg_opcr);
drivers/clk/ingenic/jz4770-cgu.c
57
writel(readl(reg_usbpcr1) | USBPCR1_UHC_POWER, reg_usbpcr1);
drivers/clk/ingenic/jz4770-cgu.c
66
writel(readl(reg_usbpcr1) & ~USBPCR1_UHC_POWER, reg_usbpcr1);
drivers/clk/ingenic/jz4770-cgu.c
67
writel(readl(reg_opcr) | OPCR_SPENDH, reg_opcr);
drivers/clk/ingenic/jz4780-cgu.c
178
writel(usbpcr1, cgu->base + CGU_REG_USBPCR1);
drivers/clk/ingenic/jz4780-cgu.c
189
writel(readl(reg_opcr) | OPCR_SPENDN0, reg_opcr);
drivers/clk/ingenic/jz4780-cgu.c
190
writel(readl(reg_usbpcr) & ~USBPCR_OTG_DISABLE & ~USBPCR_SIDDQ, reg_usbpcr);
drivers/clk/ingenic/jz4780-cgu.c
199
writel(readl(reg_opcr) & ~OPCR_SPENDN0, reg_opcr);
drivers/clk/ingenic/jz4780-cgu.c
200
writel(readl(reg_usbpcr) | USBPCR_OTG_DISABLE | USBPCR_SIDDQ, reg_usbpcr);
drivers/clk/ingenic/jz4780-cgu.c
236
writel(lcr, cgu->base + CGU_REG_LCR);
drivers/clk/ingenic/jz4780-cgu.c
240
writel(clkgr1, cgu->base + CGU_REG_CLKGR1);
drivers/clk/ingenic/pm.c
22
writel(val | LCR_LOW_POWER_MODE, ingenic_cgu_base + CGU_REG_LCR);
drivers/clk/ingenic/pm.c
31
writel(val & ~LCR_LOW_POWER_MODE, ingenic_cgu_base + CGU_REG_LCR);
drivers/clk/ingenic/x1000-cgu.c
128
writel(usbpcr1, cgu->base + CGU_REG_USBPCR1);
drivers/clk/ingenic/x1000-cgu.c
139
writel(readl(reg_opcr) | OPCR_SPENDN0, reg_opcr);
drivers/clk/ingenic/x1000-cgu.c
140
writel(readl(reg_usbpcr) & ~USBPCR_OTG_DISABLE & ~USBPCR_SIDDQ, reg_usbpcr);
drivers/clk/ingenic/x1000-cgu.c
149
writel(readl(reg_opcr) & ~OPCR_SPENDN0, reg_opcr);
drivers/clk/ingenic/x1000-cgu.c
150
writel(readl(reg_usbpcr) | USBPCR_OTG_DISABLE | USBPCR_SIDDQ, reg_usbpcr);
drivers/clk/ingenic/x1000-cgu.c
202
writel(0, cgu->base + CGU_REG_I2SCDR1);
drivers/clk/ingenic/x1830-cgu.c
62
writel((readl(reg_opcr) | OPCR_SPENDN0) & ~OPCR_GATE_USBPHYCLK, reg_opcr);
drivers/clk/ingenic/x1830-cgu.c
63
writel(readl(reg_usbpcr) & ~USBPCR_OTG_DISABLE & ~USBPCR_SIDDQ, reg_usbpcr);
drivers/clk/ingenic/x1830-cgu.c
72
writel((readl(reg_opcr) & ~OPCR_SPENDN0) | OPCR_GATE_USBPHYCLK, reg_opcr);
drivers/clk/ingenic/x1830-cgu.c
73
writel(readl(reg_usbpcr) | USBPCR_OTG_DISABLE | USBPCR_SIDDQ, reg_usbpcr);
drivers/clk/keystone/gate.c
83
writel(mdctl, control_base + MDCTL);
drivers/clk/keystone/gate.c
89
writel(pdctl, domain_base + PDCTL);
drivers/clk/keystone/gate.c
93
writel(ptcmd, domain_transition_base + PTCMD);
drivers/clk/mediatek/clk-apmixed.c
45
writel(val, tx->base_addr);
drivers/clk/mediatek/clk-apmixed.c
49
writel(val, tx->base_addr);
drivers/clk/mediatek/clk-apmixed.c
52
writel(val, tx->base_addr);
drivers/clk/mediatek/clk-apmixed.c
64
writel(val, tx->base_addr);
drivers/clk/mediatek/clk-fhctl.c
101
writel(readl(regs->reg_cfg) | data->frddsx_en, regs->reg_cfg);
drivers/clk/mediatek/clk-fhctl.c
103
writel(readl(regs->reg_cfg) | data->fhctlx_en, regs->reg_cfg);
drivers/clk/mediatek/clk-fhctl.c
107
writel(readl(regs->reg_hp_en) & ~BIT(data->fh_id),
drivers/clk/mediatek/clk-fhctl.c
128
writel((readl(pll->pcw_addr) & dds_mask) | data->tgl_org,
drivers/clk/mediatek/clk-fhctl.c
131
writel(readl(regs->reg_cfg) | data->sfstrx_en, regs->reg_cfg);
drivers/clk/mediatek/clk-fhctl.c
132
writel(readl(regs->reg_cfg) | data->fhctlx_en, regs->reg_cfg);
drivers/clk/mediatek/clk-fhctl.c
133
writel(data->slope0_value, regs->reg_slope0);
drivers/clk/mediatek/clk-fhctl.c
134
writel(data->slope1_value, regs->reg_slope1);
drivers/clk/mediatek/clk-fhctl.c
136
writel(readl(regs->reg_hp_en) | BIT(data->fh_id), regs->reg_hp_en);
drivers/clk/mediatek/clk-fhctl.c
137
writel((new_dds) | (data->dvfs_tri), regs->reg_dvfs);
drivers/clk/mediatek/clk-fhctl.c
152
writel(con_pcw_tmp, pll->pcw_addr);
drivers/clk/mediatek/clk-fhctl.c
153
writel(readl(regs->reg_hp_en) & ~BIT(data->fh_id), regs->reg_hp_en);
drivers/clk/mediatek/clk-fhctl.c
178
writel(regval, pll->pd_addr);
drivers/clk/mediatek/clk-fhctl.c
250
writel(val, regs.reg_clk_con);
drivers/clk/mediatek/clk-fhctl.c
253
writel(val, regs.reg_rst_con);
drivers/clk/mediatek/clk-fhctl.c
255
writel(val, regs.reg_rst_con);
drivers/clk/mediatek/clk-fhctl.c
257
writel(0x0, regs.reg_cfg);
drivers/clk/mediatek/clk-fhctl.c
258
writel(0x0, regs.reg_updnlmt);
drivers/clk/mediatek/clk-fhctl.c
259
writel(0x0, regs.reg_dds);
drivers/clk/mediatek/clk-fhctl.c
73
writel((readl(regs->reg_cfg) & ~(data->frddsx_en)), regs->reg_cfg);
drivers/clk/mediatek/clk-fhctl.c
74
writel((readl(regs->reg_cfg) & ~(data->sfstrx_en)), regs->reg_cfg);
drivers/clk/mediatek/clk-fhctl.c
75
writel((readl(regs->reg_cfg) & ~(data->fhctlx_en)), regs->reg_cfg);
drivers/clk/mediatek/clk-fhctl.c
82
writel(r, regs->reg_cfg);
drivers/clk/mediatek/clk-fhctl.c
87
writel(r, regs->reg_cfg);
drivers/clk/mediatek/clk-fhctl.c
89
writel((readl(pll->pcw_addr) & data->dds_mask) | data->tgl_org,
drivers/clk/mediatek/clk-fhctl.c
97
writel(updnlmt_val, regs->reg_updnlmt);
drivers/clk/mediatek/clk-fhctl.c
98
writel(readl(regs->reg_hp_en) | BIT(data->fh_id),
drivers/clk/mediatek/clk-mt6765.c
755
writel(readl(AP_PLL_CON3) & 0xFFFFFFE1, AP_PLL_CON3);
drivers/clk/mediatek/clk-mt6765.c
756
writel(readl(PLLON_CON0) & 0x01041041, PLLON_CON0);
drivers/clk/mediatek/clk-mt6765.c
757
writel(readl(PLLON_CON1) & 0x01041041, PLLON_CON1);
drivers/clk/mediatek/clk-mt6765.c
795
writel(readl(CLK_SCP_CFG_0) | 0x3EF, CLK_SCP_CFG_0);
drivers/clk/mediatek/clk-mt6765.c
797
writel(readl(CLK_SCP_CFG_1) | 0x1, CLK_SCP_CFG_1);
drivers/clk/mediatek/clk-mt6795-apmixedsys.c
118
writel(readl(reg) & ~MD1_CLK_OFF, reg);
drivers/clk/mediatek/clk-mt6795-apmixedsys.c
121
writel(readl(reg) & ~MD1_MTCMOS_OFF, reg);
drivers/clk/mediatek/clk-mt6795-apmixedsys.c
124
writel(readl(reg) & ~MD1_ISO_OFF, reg);
drivers/clk/mediatek/clk-mt6795-apmixedsys.c
127
writel(readl(reg) & ~MD1_MEM_OFF, reg);
drivers/clk/mediatek/clk-mt7988-xfipll.c
59
writel(RG_XFI_PLL_ANA_SWWA, base + XFI_PLL_ANA_GLB8);
drivers/clk/mediatek/clk-pll.c
116
writel(val, pll->pd_addr);
drivers/clk/mediatek/clk-pll.c
124
writel(val, pll->pcw_addr);
drivers/clk/mediatek/clk-pll.c
127
writel(chg, pll->pcw_chg_addr);
drivers/clk/mediatek/clk-pll.c
129
writel(val + 1, pll->tuner_addr);
drivers/clk/mediatek/clk-pll.c
232
writel(r, pll->pwr_addr);
drivers/clk/mediatek/clk-pll.c
236
writel(r, pll->pwr_addr);
drivers/clk/mediatek/clk-pll.c
240
writel(r, pll->en_addr);
drivers/clk/mediatek/clk-pll.c
244
writel(r, pll->base_addr + REG_CON0);
drivers/clk/mediatek/clk-pll.c
254
writel(r, pll->base_addr + REG_CON0);
drivers/clk/mediatek/clk-pll.c
268
writel(r, pll->base_addr + REG_CON0);
drivers/clk/mediatek/clk-pll.c
275
writel(r, pll->base_addr + REG_CON0);
drivers/clk/mediatek/clk-pll.c
279
writel(r, pll->en_addr);
drivers/clk/mediatek/clk-pll.c
282
writel(r, pll->pwr_addr);
drivers/clk/mediatek/clk-pll.c
285
writel(r, pll->pwr_addr);
drivers/clk/mediatek/clk-pll.c
292
writel(BIT(pll->data->pll_en_bit), pll->en_set_addr);
drivers/clk/mediatek/clk-pll.c
304
writel(BIT(pll->data->pll_en_bit), pll->en_clr_addr);
drivers/clk/mediatek/clk-pll.c
81
writel(r, pll->tuner_en_addr);
drivers/clk/mediatek/clk-pll.c
84
writel(r, pll->tuner_addr);
drivers/clk/mediatek/clk-pll.c
94
writel(r, pll->tuner_en_addr);
drivers/clk/mediatek/clk-pll.c
97
writel(r, pll->tuner_addr);
drivers/clk/microchip/clk-core.c
107
writel(PB_DIV_ENABLE, PIC32_SET(pb->ctrl_reg));
drivers/clk/microchip/clk-core.c
115
writel(PB_DIV_ENABLE, PIC32_CLR(pb->ctrl_reg));
drivers/clk/microchip/clk-core.c
192
writel(v, pb->ctrl_reg);
drivers/clk/microchip/clk-core.c
259
writel(REFO_ON | REFO_OE, PIC32_SET(refo->ctrl_reg));
drivers/clk/microchip/clk-core.c
267
writel(REFO_ON | REFO_OE, PIC32_CLR(refo->ctrl_reg));
drivers/clk/microchip/clk-core.c
463
writel(v, refo->ctrl_reg);
drivers/clk/microchip/clk-core.c
510
writel(v, refo->ctrl_reg);
drivers/clk/microchip/clk-core.c
516
writel(v, refo->ctrl_reg + REFO_TRIM_REG);
drivers/clk/microchip/clk-core.c
519
writel(REFO_ON | REFO_DIVSW_EN, PIC32_SET(refo->ctrl_reg));
drivers/clk/microchip/clk-core.c
525
writel(REFO_ON, PIC32_CLR(refo->ctrl_reg));
drivers/clk/microchip/clk-core.c
708
writel(v, pll->ctrl_reg);
drivers/clk/microchip/clk-core.c
800
writel(v, sclk->slew_reg);
drivers/clk/microchip/clk-core.c
846
writel(v, sclk->mux_reg);
drivers/clk/microchip/clk-core.c
849
writel(OSC_SWEN, PIC32_SET(sclk->mux_reg));
drivers/clk/microchip/clk-core.c
893
writel(v, sclk->slew_reg);
drivers/clk/microchip/clk-core.c
961
writel(sosc->enable_mask, PIC32_SET(sosc->enable_reg));
drivers/clk/microchip/clk-core.c
973
writel(sosc->enable_mask, PIC32_CLR(sosc->enable_reg));
drivers/clk/mmp/clk-audio.c
218
writel(val, priv->mmio_base + SSPA_AUD_PLL_CTRL0);
drivers/clk/mmp/clk-audio.c
222
writel(val, priv->mmio_base + SSPA_AUD_PLL_CTRL1);
drivers/clk/mmp/clk-audio.c
415
writel(priv->aud_ctrl, priv->mmio_base + SSPA_AUD_CTRL);
drivers/clk/mmp/clk-audio.c
416
writel(priv->aud_pll_ctrl0, priv->mmio_base + SSPA_AUD_PLL_CTRL0);
drivers/clk/mmp/clk-audio.c
417
writel(priv->aud_pll_ctrl1, priv->mmio_base + SSPA_AUD_PLL_CTRL1);
drivers/clk/mmp/clk-frac.c
153
writel(val, factor->base);
drivers/clk/mmp/clk-gate.c
37
writel(tmp, gate->reg);
drivers/clk/mmp/clk-gate.c
63
writel(tmp, gate->reg);
drivers/clk/mmp/clk-mix.c
167
writel(mux_div, ri->reg_clk_ctrl);
drivers/clk/mmp/clk-mix.c
170
writel(mux_div, ri->reg_clk_ctrl);
drivers/clk/mmp/clk-mix.c
188
writel(fc_req, ri->reg_clk_ctrl);
drivers/clk/mmp/clk-mix.c
189
writel(mux_div, ri->reg_clk_sel);
drivers/clk/mmp/pwr-island.c
39
writel(val, pm_domain->reg);
drivers/clk/mmp/pwr-island.c
43
writel(val, pm_domain->reg);
drivers/clk/mmp/pwr-island.c
50
writel(val, pm_domain->reg);
drivers/clk/mmp/pwr-island.c
53
writel(val, pm_domain->reg);
drivers/clk/mmp/pwr-island.c
56
writel(val, pm_domain->reg);
drivers/clk/mmp/pwr-island.c
58
writel(after_power_on, pm_domain->reg);
drivers/clk/mmp/pwr-island.c
83
writel(val, pm_domain->reg);
drivers/clk/mmp/reset.c
48
writel(val, cell->reg);
drivers/clk/mmp/reset.c
70
writel(val, cell->reg);
drivers/clk/mvebu/armada-37xx-periph.c
716
writel(data->clk_dis, data->reg + CLK_DIS);
drivers/clk/mvebu/armada-37xx-periph.c
717
writel(data->div_sel0, data->reg + DIV_SEL0);
drivers/clk/mvebu/armada-37xx-periph.c
718
writel(data->div_sel1, data->reg + DIV_SEL1);
drivers/clk/mvebu/armada-37xx-periph.c
719
writel(data->div_sel2, data->reg + DIV_SEL2);
drivers/clk/mvebu/armada-37xx-periph.c
720
writel(data->tbg_sel, data->reg + TBG_SEL);
drivers/clk/mvebu/armada-37xx-periph.c
721
writel(data->clk_sel, data->reg + CLK_SEL);
drivers/clk/mvebu/clk-corediv.c
101
writel(reg, corediv->reg);
drivers/clk/mvebu/clk-corediv.c
120
writel(reg, corediv->reg);
drivers/clk/mvebu/clk-corediv.c
172
writel(reg, corediv->reg + soc_desc->ratio_offset);
drivers/clk/mvebu/clk-corediv.c
176
writel(reg, corediv->reg);
drivers/clk/mvebu/clk-corediv.c
180
writel(reg, corediv->reg);
drivers/clk/mvebu/clk-corediv.c
188
writel(reg, corediv->reg);
drivers/clk/mvebu/clk-cpu.c
104
writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET);
drivers/clk/mvebu/clk-cpu.c
143
writel(reg, cpuclk->pmu_dfs);
drivers/clk/mvebu/clk-cpu.c
148
writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET);
drivers/clk/mvebu/clk-cpu.c
88
writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET);
drivers/clk/mvebu/clk-cpu.c
94
writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET);
drivers/clk/mvebu/clk-cpu.c
99
writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET);
drivers/clk/mvebu/common.c
225
writel(ctrl->saved_reg, ctrl->base);
drivers/clk/mxs/clk-ssp.c
48
writel(val, ssp->base + HW_SSP_TIMING(ssp));
drivers/clk/nxp/clk-lpc18xx-ccu.c
156
writel(val, gate->reg);
drivers/clk/nxp/clk-lpc18xx-ccu.c
161
writel(val, gate->reg);
drivers/clk/nxp/clk-lpc18xx-cgu.c
421
writel(ctrl, pll->reg + LPC18XX_CGU_PLL0USB_CTRL);
drivers/clk/nxp/clk-lpc18xx-cgu.c
424
writel(m, pll->reg + LPC18XX_CGU_PLL0USB_MDIV);
drivers/clk/nxp/clk-lpc18xx-cgu.c
425
writel(LPC18XX_PLL0_NP_DIVS_1, pll->reg + LPC18XX_CGU_PLL0USB_NP_DIV);
drivers/clk/nxp/clk-lpc18xx-cgu.c
429
writel(ctrl, pll->reg + LPC18XX_CGU_PLL0USB_CTRL);
drivers/clk/nxp/clk-lpc18xx-cgu.c
435
writel(ctrl, pll->reg + LPC18XX_CGU_PLL0USB_CTRL);
drivers/clk/nxp/clk-lpc32xx.c
384
writel(val, usb_clk_vbase + LPC32XX_USB_CLK_CTRL);
drivers/clk/pistachio/clk-pll.c
85
writel(val, pll->base + reg);
drivers/clk/pxa/clk-pxa.c
194
writel(freq->cccr, cccr);
drivers/clk/pxa/clk-pxa3xx.c
167
writel(accr, clk_regs + ACCR);
drivers/clk/qcom/lpass-gfm-sm8250.c
58
writel(val, clk->gfm_mux);
drivers/clk/renesas/clk-div6.c
161
writel(val | CPG_DIV6_DIV(clock->div - 1), clock->reg);
drivers/clk/renesas/clk-div6.c
195
writel((readl(clock->reg) & ~clock->src_mask) | src, clock->reg);
drivers/clk/renesas/clk-div6.c
54
writel(val, clock->reg);
drivers/clk/renesas/clk-div6.c
74
writel(val, clock->reg);
drivers/clk/renesas/clk-mstp.c
73
group->width_8bit ? writeb(val, reg) : writel(val, reg);
drivers/clk/renesas/clk-sh73a0.c
192
writel(0x108, base + CPG_SD0CKCR);
drivers/clk/renesas/clk-sh73a0.c
193
writel(0x108, base + CPG_SD1CKCR);
drivers/clk/renesas/clk-sh73a0.c
194
writel(0x108, base + CPG_SD2CKCR);
drivers/clk/renesas/r9a06g032-clocks.c
1045
writel(div | BIT(31), reg);
drivers/clk/renesas/r9a06g032-clocks.c
1284
writel(R9A06G032_SYSCTRL_SWRST, sysctrl_priv->reg + R9A06G032_SYSCTRL_RSTCTRL);
drivers/clk/renesas/r9a06g032-clocks.c
1307
writel(usb, clocks->reg + R9A06G032_SYSCTRL_USB);
drivers/clk/renesas/r9a06g032-clocks.c
1343
writel(R9A06G032_SYSCTRL_WDA7RST_0 | R9A06G032_SYSCTRL_WDA7RST_1,
drivers/clk/renesas/r9a06g032-clocks.c
1346
writel(R9A06G032_SYSCTRL_SWRST | R9A06G032_SYSCTRL_RSTEN_MRESET_EN,
drivers/clk/renesas/r9a06g032-clocks.c
700
writel(dmamux, sysctrl_priv->reg + R9A06G032_SYSCTRL_DMAMUX);
drivers/clk/renesas/r9a06g032-clocks.c
719
writel(val, reg);
drivers/clk/renesas/rcar-cpg-lib.c
36
writel(val, reg);
drivers/clk/renesas/rcar-cpg-lib.c
52
writel(csn->saved, csn->reg);
drivers/clk/renesas/rcar-gen2-cpg.c
101
writel(val, zclk->reg);
drivers/clk/renesas/rcar-gen2-cpg.c
109
writel(kick, zclk->kick_reg);
drivers/clk/renesas/rcar-gen3-cpg.c
430
writel(value, csn->reg);
drivers/clk/renesas/rcar-gen3-cpg.c
96
writel(val, pll_clk->pllcr_reg);
drivers/clk/renesas/renesas-cpg-mssr.c
1145
writel(newval, priv->pub.base0 + priv->control_regs[reg]);
drivers/clk/renesas/renesas-cpg-mssr.c
253
writel(value, base + RZT2H_MSTPCR_OFFSET(offset));
drivers/clk/renesas/renesas-cpg-mssr.c
299
writel(value, priv->pub.base0 + priv->control_regs[reg]);
drivers/clk/renesas/renesas-cpg-mssr.c
712
writel(bitmask, priv->pub.base0 + off);
drivers/clk/renesas/renesas-cpg-mssr.c
786
writel(val, reg_addr);
drivers/clk/renesas/rzg2l-cpg.c
1001
writel(CPG_SIPLL5_STBY_DOWNSPREAD_WEN | CPG_SIPLL5_STBY_SSCG_EN_WEN |
drivers/clk/renesas/rzg2l-cpg.c
1052
writel(CPG_SIPLL5_STBY_SSCG_EN_WEN | CPG_SIPLL5_STBY_RESETB_WEN |
drivers/clk/renesas/rzg2l-cpg.c
1403
writel(value, priv->base + MSTOP_OFF(mstop->conf));
drivers/clk/renesas/rzg2l-cpg.c
1466
writel(value, priv->base + CLK_ON_R(reg));
drivers/clk/renesas/rzg2l-cpg.c
1470
writel(value, priv->base + CLK_ON_R(reg));
drivers/clk/renesas/rzg2l-cpg.c
1770
writel(value, priv->base + CLK_RST_R(reg));
drivers/clk/renesas/rzg2l-cpg.c
1787
writel(value, priv->base + CLK_RST_R(info->resets[id].off));
drivers/clk/renesas/rzg2l-cpg.c
241
writel((CPG_WEN_BIT | clk_src_266) << shift, priv->base + off);
drivers/clk/renesas/rzg2l-cpg.c
288
writel((CPG_WEN_BIT | 1) << shift, priv->base + off);
drivers/clk/renesas/rzg2l-cpg.c
362
writel((CPG_WEN_BIT | val) << shift, priv->base + off);
drivers/clk/renesas/rzg2l-cpg.c
508
writel((CPG_WEN_BIT | val) << shift, priv->base + off);
drivers/clk/renesas/rzg2l-cpg.c
778
writel(CPG_PL5_SDIV_DIV_DSI_A_WEN | CPG_PL5_SDIV_DIV_DSI_B_WEN |
drivers/clk/renesas/rzg2l-cpg.c
868
writel(CPG_OTHERFUNC1_REG_RES0_ON_WEN | index,
drivers/clk/renesas/rzg2l-cpg.c
978
writel(CPG_SIPLL5_STBY_RESETB_WEN, priv->base + CPG_SIPLL5_STBY);
drivers/clk/renesas/rzg2l-cpg.c
987
writel((params.pl5_postdiv1 << 0) | (params.pl5_postdiv2 << 4) |
drivers/clk/renesas/rzg2l-cpg.c
991
writel((params.pl5_fracin << 8), priv->base + CPG_SIPLL5_CLK3);
drivers/clk/renesas/rzg2l-cpg.c
994
writel(CPG_SIPLL5_CLK4_RESV_LSB | (params.pl5_intin << 16),
drivers/clk/renesas/rzg2l-cpg.c
998
writel(params.pl5_spread, priv->base + CPG_SIPLL5_CLK5);
drivers/clk/renesas/rzv2h-cpg.c
1121
writel(val, priv->base + CPG_BUS_MSTOP(mstop_index));
drivers/clk/renesas/rzv2h-cpg.c
1142
writel(val, priv->base + CPG_BUS_MSTOP(mstop_index));
drivers/clk/renesas/rzv2h-cpg.c
1210
writel(value, priv->base + reg);
drivers/clk/renesas/rzv2h-cpg.c
1216
writel(value, priv->base + reg);
drivers/clk/renesas/rzv2h-cpg.c
1336
writel(val, priv->base + CPG_BUS_MSTOP(mstop_index));
drivers/clk/renesas/rzv2h-cpg.c
1363
writel(value, priv->base + reg);
drivers/clk/renesas/rzv2h-cpg.c
1372
writel(value, priv->base + GET_RST_OFFSET(priv->resets[id].reset_index));
drivers/clk/renesas/rzv2h-cpg.c
509
writel(val, priv->base + ddiv.offset);
drivers/clk/renesas/rzv2h-cpg.c
600
writel(CPG_PLL_STBY_RESETB_WEN, priv->base + CPG_PLL_STBY(offset));
drivers/clk/renesas/rzv2h-cpg.c
610
writel(FIELD_PREP(CPG_PLL_CLK1_KDIV, (u16)params->k) |
drivers/clk/renesas/rzv2h-cpg.c
617
writel((val & ~CPG_PLL_CLK2_SDIV) | FIELD_PREP(CPG_PLL_CLK2_SDIV, params->s),
drivers/clk/renesas/rzv2h-cpg.c
625
writel(val | CPG_PLL_STBY_RESETB_WEN | CPG_PLL_STBY_RESETB,
drivers/clk/renesas/rzv2h-cpg.c
679
writel(CPG_PLL_STBY_RESETB_WEN | CPG_PLL_STBY_RESETB,
drivers/clk/renesas/rzv2h-cpg.c
834
writel(val, divider->reg);
drivers/clk/rockchip/clk-cpu.c
112
writel(clksel->val, cpuclk->reg_base + clksel->reg);
drivers/clk/rockchip/clk-cpu.c
130
writel(clksel->val, cpuclk->reg_base + clksel->reg);
drivers/clk/rockchip/clk-cpu.c
148
writel(clksel->val, cpuclk->reg_base + clksel->reg);
drivers/clk/rockchip/clk-cpu.c
199
writel(HIWORD_UPDATE(alt_div, reg_data->div_core_mask[i],
drivers/clk/rockchip/clk-cpu.c
209
writel(HIWORD_UPDATE(reg_data->mux_core_alt,
drivers/clk/rockchip/clk-cpu.c
214
writel(HIWORD_UPDATE(reg_data->mux_core_alt,
drivers/clk/rockchip/clk-cpu.c
251
writel(HIWORD_UPDATE(reg_data->mux_core_main,
drivers/clk/rockchip/clk-cpu.c
256
writel(HIWORD_UPDATE(reg_data->mux_core_main,
drivers/clk/rockchip/clk-cpu.c
265
writel(HIWORD_UPDATE(0, reg_data->div_core_mask[i],
drivers/clk/rockchip/clk-half-divider.c
134
writel(val, divider->reg);
drivers/clk/rockchip/clk-inverter.c
49
writel(HIWORD_UPDATE(val, INVERTER_MASK, inv_clock->shift),
drivers/clk/rockchip/clk-inverter.c
60
writel(reg, inv_clock->reg);
drivers/clk/rockchip/clk-mmc-phase.c
150
writel(raw_value, mmc_clock->reg);
drivers/clk/rockchip/clk-pll.c
1012
writel(HIWORD_UPDATE(0, RK3588_PLLCON1_PWRDOWN, 0),
drivers/clk/rockchip/clk-pll.c
1023
writel(HIWORD_UPDATE(RK3588_PLLCON1_PWRDOWN, RK3588_PLLCON1_PWRDOWN, 0),
drivers/clk/rockchip/clk-pll.c
279
writel(HIWORD_UPDATE(0, RK3036_PLLCON1_PWRDOWN, 0),
drivers/clk/rockchip/clk-pll.c
290
writel(HIWORD_UPDATE(RK3036_PLLCON1_PWRDOWN,
drivers/clk/rockchip/clk-pll.c
454
writel(HIWORD_UPDATE(RK3066_PLLCON3_RESET, RK3066_PLLCON3_RESET, 0),
drivers/clk/rockchip/clk-pll.c
458
writel(HIWORD_UPDATE(rate->nr - 1, RK3066_PLLCON0_NR_MASK,
drivers/clk/rockchip/clk-pll.c
472
writel(HIWORD_UPDATE(0, RK3066_PLLCON3_RESET, 0),
drivers/clk/rockchip/clk-pll.c
514
writel(HIWORD_UPDATE(0, RK3066_PLLCON3_PWRDOWN, 0),
drivers/clk/rockchip/clk-pll.c
525
writel(HIWORD_UPDATE(RK3066_PLLCON3_PWRDOWN,
drivers/clk/rockchip/clk-pll.c
763
writel(HIWORD_UPDATE(0, RK3399_PLLCON3_PWRDOWN, 0),
drivers/clk/rockchip/clk-pll.c
774
writel(HIWORD_UPDATE(RK3399_PLLCON3_PWRDOWN,
drivers/clk/rockchip/clk-pll.c
955
writel(HIWORD_UPDATE(RK3588_PLLCON1_PWRDOWN,
drivers/clk/rockchip/clk-pll.c
971
writel(HIWORD_UPDATE(0, RK3588_PLLCON1_PWRDOWN, 0),
drivers/clk/rockchip/clk.c
772
writel(0xfdb9, rst_base + reg_restart);
drivers/clk/rockchip/softrst.c
38
writel(BIT(offset) | (BIT(offset) << 16),
drivers/clk/rockchip/softrst.c
47
writel(reg | BIT(offset), softrst->reg_base + (bank * 4));
drivers/clk/rockchip/softrst.c
70
writel((BIT(offset) << 16), softrst->reg_base + (bank * 4));
drivers/clk/rockchip/softrst.c
78
writel(reg & ~BIT(offset), softrst->reg_base + (bank * 4));
drivers/clk/samsung/clk-cpu.c
173
writel(div0, base + regs->div_cpu0);
drivers/clk/samsung/clk-cpu.c
257
writel(mux_reg | (1 << 16), base + regs->mux_sel);
drivers/clk/samsung/clk-cpu.c
261
writel(div0, base + regs->div_cpu0);
drivers/clk/samsung/clk-cpu.c
265
writel(div1, base + regs->div_cpu1);
drivers/clk/samsung/clk-cpu.c
298
writel(mux_reg & ~(1 << 16), base + regs->mux_sel);
drivers/clk/samsung/clk-cpu.c
370
writel(mux_reg | 1, base + regs->mux_sel);
drivers/clk/samsung/clk-cpu.c
374
writel(div0, base + regs->div_cpu0);
drivers/clk/samsung/clk-cpu.c
377
writel(div1, base + regs->div_cpu1);
drivers/clk/samsung/clk-cpu.c
398
writel(mux_reg & ~1, base + regs->mux_sel);
drivers/clk/samsung/clk-cpu.c
521
writel(mux_reg | 1, base + regs->mux);
drivers/clk/samsung/clk-cpu.c
531
writel(val, base + regs->divs[i]);
drivers/clk/samsung/clk-cpu.c
558
writel(mux_reg & ~1, base + regs->mux);
drivers/clk/samsung/clk-exynos-arm64.c
110
writel(CMU_OPT_GLOBAL_EN_AUTO_GATING,
drivers/clk/samsung/clk-exynos-arm64.c
119
writel(PLL_CON1_MANUAL, reg);
drivers/clk/samsung/clk-exynos-arm64.c
129
writel(val, reg);
drivers/clk/samsung/clk-exynos-audss.c
57
writel(reg_save[i][1], reg_base + reg_save[i][0]);
drivers/clk/samsung/clk-exynos-clkout.c
231
writel(clkout->pmu_debug_save, clkout->reg + EXYNOS_PMU_DEBUG_REG);
drivers/clk/samsung/clk-exynos5-subcmu.c
27
writel((rd->save & ~rd->mask) | rd->value, base + rd->offset);
drivers/clk/samsung/clk-exynos5-subcmu.c
37
writel((readl(base + rd->offset) & ~rd->mask) | rd->save,
drivers/clk/samsung/clk-s5pv210-audss.c
54
writel(reg_save[i][1], reg_base + reg_save[i][0]);
drivers/clk/samsung/clk.c
45
writel(rd->value, base + rd->offset);
drivers/clk/socfpga/clk-gate.c
65
writel(src_reg, clk_mgr_base_addr + CLKMGR_L4SRC);
drivers/clk/socfpga/clk-gate.c
70
writel(src_reg, clk_mgr_base_addr + CLKMGR_L4SRC);
drivers/clk/socfpga/clk-gate.c
84
writel(src_reg, clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
drivers/clk/socfpga/clk-pll-s10.c
148
writel(reg, socfpgaclk->hw.reg);
drivers/clk/socfpga/clk-pll-s10.c
161
writel(reg, socfpgaclk->hw.reg + 0x4);
drivers/clk/sophgo/clk-cv1800.c
1213
writel(val, base + reg);
drivers/clk/sophgo/clk-cv1800.c
1230
writel(val, base + REG_CLK_BYP_0);
drivers/clk/sophgo/clk-cv1800.c
1242
writel(val, base + REG_CLK_EN_2);
drivers/clk/sophgo/clk-cv18xx-common.c
23
writel(value | mask, common->base + field->reg);
drivers/clk/sophgo/clk-cv18xx-common.c
40
writel(value & ~mask, common->base + field->reg);
drivers/clk/sophgo/clk-cv18xx-ip.c
126
writel(reg, common->base + div->reg);
drivers/clk/sophgo/clk-cv18xx-ip.c
483
writel(reg, mux->common.base + mux->mux.reg);
drivers/clk/sophgo/clk-cv18xx-ip.c
781
writel(reg, mmux->common.base + mux->reg);
drivers/clk/sophgo/clk-cv18xx-ip.c
886
writel(m, aclk->common.base + aclk->m.reg);
drivers/clk/sophgo/clk-cv18xx-ip.c
887
writel(n, aclk->common.base + aclk->n.reg);
drivers/clk/sophgo/clk-cv18xx-pll.c
147
writel(regval, pll->common.base + pll->pll_reg);
drivers/clk/sophgo/clk-cv18xx-pll.c
371
writel(detected_ssc, pll->common.base + pll->pll_syn->set);
drivers/clk/sophgo/clk-cv18xx-pll.c
376
writel(regval, pll->common.base + pll->pll_reg);
drivers/clk/sophgo/clk-sg2042-clkgen.c
228
writel(val, divider->reg);
drivers/clk/sophgo/clk-sg2042-clkgen.c
238
writel(val, divider->reg);
drivers/clk/sophgo/clk-sg2042-clkgen.c
243
writel(val, divider->reg);
drivers/clk/sophgo/clk-sg2042-pll.c
129
writel(value | (1 << pll->shift_enable), pll->base + R_PLL_CLKEN_CONTROL);
drivers/clk/sophgo/clk-sg2042-pll.c
133
writel(value & (~(1 << pll->shift_enable)), pll->base + R_PLL_CLKEN_CONTROL);
drivers/clk/sophgo/clk-sg2042-pll.c
399
writel(value, pll->base + pll->offset_ctrl);
drivers/clk/sophgo/clk-sg2044.c
164
writel(reg, addr);
drivers/clk/sophgo/clk-sg2044.c
170
writel(reg, addr);
drivers/clk/sophgo/clk-sg2044.c
174
writel(reg, addr);
drivers/clk/sophgo/clk-sg2044.c
203
writel(value, addr);
drivers/clk/sophgo/clk-sg2044.c
218
writel(value, addr);
drivers/clk/st/clk-flexgen.c
173
writel(reg, config->reg);
drivers/clk/st/clkgen.h
31
writel((readl(base + field->offset) &
drivers/clk/stm32/clk-stm32-core.c
128
writel(reg, base + mux->offset);
drivers/clk/stm32/clk-stm32-core.c
145
writel(BIT(gate->bit_idx), addr);
drivers/clk/stm32/clk-stm32-core.c
147
writel(readl(addr) | BIT(gate->bit_idx), addr);
drivers/clk/stm32/clk-stm32-core.c
153
writel(BIT(gate->bit_idx), addr + gate->set_clr);
drivers/clk/stm32/clk-stm32-core.c
155
writel(readl(addr) & ~BIT(gate->bit_idx), addr);
drivers/clk/stm32/clk-stm32-core.c
170
writel(BIT(gate->bit_idx), addr + gate->set_clr);
drivers/clk/stm32/clk-stm32-core.c
172
writel(readl(addr) & ~BIT(gate->bit_idx), addr);
drivers/clk/stm32/clk-stm32-core.c
253
writel(val, base + divider->offset);
drivers/clk/stm32/reset-stm32.c
70
writel(BIT(ptr_line->bit_idx), addr);
drivers/clk/stm32/reset-stm32.c
85
writel(reg, data->membase + ptr_line->offset);
drivers/clk/sunxi-ng/ccu-sun20i-d1.c
1359
writel(val, reg + pll_regs[i]);
drivers/clk/sunxi-ng/ccu-sun20i-d1.c
1365
writel(val, reg + SUN20I_D1_PLL_CPUX_REG);
drivers/clk/sunxi-ng/ccu-sun20i-d1.c
1375
writel(val, reg + pll_video_regs[i]);
drivers/clk/sunxi-ng/ccu-sun20i-d1.c
1381
writel(val, reg + SUN20I_D1_PLL_AUDIO0_REG);
drivers/clk/sunxi-ng/ccu-sun20i-d1.c
1386
writel(val, reg + SUN20I_D1_FANOUT_27M_REG);
drivers/clk/sunxi-ng/ccu-sun4i-a10.c
1455
writel(val | (1 << 26), reg + SUN4I_PLL_AUDIO_REG);
drivers/clk/sunxi-ng/ccu-sun4i-a10.c
1468
writel(val | (2 << 6), reg + SUN4I_AHB_REG);
drivers/clk/sunxi-ng/ccu-sun50i-a100.c
1201
writel(val, reg + sun50i_a100_pll_regs[i]);
drivers/clk/sunxi-ng/ccu-sun50i-a100.c
1209
writel(SUN50I_A100_PLL_PERIPH1_PATTERN0,
drivers/clk/sunxi-ng/ccu-sun50i-a100.c
1214
writel(val, reg + SUN50I_A100_PLL_PERIPH1_REG);
drivers/clk/sunxi-ng/ccu-sun50i-a100.c
1224
writel(val, reg + sun50i_a100_pll_video_regs[i]);
drivers/clk/sunxi-ng/ccu-sun50i-a100.c
1235
writel(val, reg + SUN50I_A100_PLL_AUDIO_REG);
drivers/clk/sunxi-ng/ccu-sun50i-a100.c
1246
writel(val, reg + sun50i_a100_usb2_clk_regs[i]);
drivers/clk/sunxi-ng/ccu-sun50i-a64.c
958
writel(val | (0 << 16), reg + SUN50I_A64_PLL_AUDIO_REG);
drivers/clk/sunxi-ng/ccu-sun50i-a64.c
960
writel(0x515, reg + SUN50I_A64_PLL_MIPI_REG);
drivers/clk/sunxi-ng/ccu-sun50i-h6.c
1208
writel(val, reg + SUN50I_H6_PLL_GPU_REG);
drivers/clk/sunxi-ng/ccu-sun50i-h6.c
1213
writel(val, reg + gpu_clk.common.reg);
drivers/clk/sunxi-ng/ccu-sun50i-h6.c
1219
writel(val, reg + pll_regs[i]);
drivers/clk/sunxi-ng/ccu-sun50i-h6.c
1230
writel(val, reg + pll_video_regs[i]);
drivers/clk/sunxi-ng/ccu-sun50i-h6.c
1242
writel (val, reg + usb2_clk_regs[i]);
drivers/clk/sunxi-ng/ccu-sun50i-h6.c
1251
writel(val | (11 << 16) | BIT(0), reg + SUN50I_H6_PLL_AUDIO_REG);
drivers/clk/sunxi-ng/ccu-sun50i-h6.c
1260
writel(val, reg + SUN50I_H6_HDMI_CEC_CLK_REG);
drivers/clk/sunxi-ng/ccu-sun50i-h616.c
1181
writel(val, reg + pll_regs[i]);
drivers/clk/sunxi-ng/ccu-sun50i-h616.c
1192
writel(val, reg + pll_video_regs[i]);
drivers/clk/sunxi-ng/ccu-sun50i-h616.c
1204
writel(val, reg + usb2_clk_regs[i]);
drivers/clk/sunxi-ng/ccu-sun50i-h616.c
1215
writel(val, reg + SUN50I_H616_PLL_AUDIO_REG);
drivers/clk/sunxi-ng/ccu-sun50i-h616.c
1223
writel(val, reg + SUN50I_H616_GPU_CLK1_REG);
drivers/clk/sunxi-ng/ccu-sun50i-h616.c
1232
writel(val, reg + SUN50I_H616_HDMI_CEC_CLK_REG);
drivers/clk/sunxi-ng/ccu-sun55i-a523-mcu.c
443
writel(val, reg + SUN55I_A523_PLL_AUDIO1_REG);
drivers/clk/sunxi-ng/ccu-sun55i-a523.c
1669
writel(val, reg + pll_regs[i]);
drivers/clk/sunxi-ng/ccu-sun55i-a523.c
1675
writel(val, reg + SUN55I_A523_PLL_AUDIO0_REG);
drivers/clk/sunxi-ng/ccu-sun5i.c
1002
writel(val | (0 << 26), reg + SUN5I_PLL_AUDIO_REG);
drivers/clk/sunxi-ng/ccu-sun5i.c
1013
writel(val | (2 << 6), reg + SUN5I_AHB_REG);
drivers/clk/sunxi-ng/ccu-sun6i-a31.c
1243
writel(val | (0 << 16), reg + SUN6I_A31_PLL_AUDIO_REG);
drivers/clk/sunxi-ng/ccu-sun6i-a31.c
1248
writel(val, reg + SUN6I_A31_PLL_MIPI_REG);
drivers/clk/sunxi-ng/ccu-sun6i-a31.c
1258
writel(val, reg + SUN6I_A31_AHB1_REG);
drivers/clk/sunxi-ng/ccu-sun6i-rtc.c
126
writel(val | IOSC_CLK_CALI_EN | IOSC_CLK_CALI_SRC_SEL,
drivers/clk/sunxi-ng/ccu-sun6i-rtc.c
141
writel(val & ~(IOSC_CLK_CALI_EN | IOSC_CLK_CALI_SRC_SEL),
drivers/clk/sunxi-ng/ccu-sun8i-a23.c
740
writel(val | (0 << 16), reg + SUN8I_A23_PLL_AUDIO_REG);
drivers/clk/sunxi-ng/ccu-sun8i-a23.c
745
writel(val, reg + SUN8I_A23_PLL_MIPI_REG);
drivers/clk/sunxi-ng/ccu-sun8i-a33.c
801
writel(val | (0 << 16), reg + SUN8I_A33_PLL_AUDIO_REG);
drivers/clk/sunxi-ng/ccu-sun8i-a33.c
806
writel(val, reg + SUN8I_A33_PLL_MIPI_REG);
drivers/clk/sunxi-ng/ccu-sun8i-a83t.c
885
writel(val, reg);
drivers/clk/sunxi-ng/ccu-sun8i-a83t.c
901
writel(val, reg + SUN8I_A83T_PLL_AUDIO_REG);
drivers/clk/sunxi-ng/ccu-sun8i-de2.c
311
writel(0, reg + 0x24);
drivers/clk/sunxi-ng/ccu-sun8i-de2.c
312
writel(0x0000a980, reg + 0x28);
drivers/clk/sunxi-ng/ccu-sun8i-h3.c
1058
writel(val | (0 << 16), reg + SUN8I_H3_PLL_AUDIO_REG);
drivers/clk/sunxi-ng/ccu-sun8i-r40.c
1323
writel(val | (0 << 16), reg + SUN8I_R40_PLL_AUDIO_REG);
drivers/clk/sunxi-ng/ccu-sun8i-r40.c
1328
writel(val, reg + SUN8I_R40_PLL_MIPI_REG);
drivers/clk/sunxi-ng/ccu-sun8i-r40.c
1333
writel(val, reg + SUN8I_R40_USB_CLK_REG);
drivers/clk/sunxi-ng/ccu-sun8i-r40.c
1340
writel(SUN8I_R40_SYS_32K_CLK_KEY | BIT(8),
drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
756
writel(val, reg + SUN8I_V3S_PLL_AUDIO_REG);
drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
766
writel(val, reg + de_clk.common.reg);
drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
771
writel(val, reg + tcon_clk.common.reg);
drivers/clk/sunxi-ng/ccu-sun9i-a80.c
1211
writel(val, reg);
drivers/clk/sunxi-ng/ccu-sun9i-a80.c
1226
writel(val, reg + SUN9I_A80_PLL_AUDIO_REG);
drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c
548
writel(val | (3 << 16), reg + SUNIV_PLL_AUDIO_REG);
drivers/clk/sunxi-ng/ccu_div.c
111
writel(reg | (val << cd->div.shift),
drivers/clk/sunxi-ng/ccu_frac.c
108
writel(reg | sel, common->base + common->reg);
drivers/clk/sunxi-ng/ccu_frac.c
34
writel(reg & ~cf->enable, common->base + common->reg);
drivers/clk/sunxi-ng/ccu_frac.c
50
writel(reg | cf->enable, common->base + common->reg);
drivers/clk/sunxi-ng/ccu_gate.c
25
writel(reg & ~gate, common->base + common->reg);
drivers/clk/sunxi-ng/ccu_gate.c
51
writel(reg | gate, common->base + common->reg);
drivers/clk/sunxi-ng/ccu_mmc_timing.c
37
writel(val, cm->base + cm->reg);
drivers/clk/sunxi-ng/ccu_mp.c
247
writel(reg, cmp->common.base + cmp->common.reg);
drivers/clk/sunxi-ng/ccu_mult.c
138
writel(reg, cm->common.base + cm->common.reg);
drivers/clk/sunxi-ng/ccu_mux.c
215
writel(reg | (index << cm->shift), common->base + common->reg);
drivers/clk/sunxi-ng/ccu_nk.c
143
writel(reg, nk->common.base + nk->common.reg);
drivers/clk/sunxi-ng/ccu_nkm.c
236
writel(reg, nkm->common.base + nkm->common.reg);
drivers/clk/sunxi-ng/ccu_nkmp.c
216
writel(reg, nkmp->common.base + nkmp->common.reg);
drivers/clk/sunxi-ng/ccu_nm.c
186
writel(reg, nm->common.base + nm->common.reg);
drivers/clk/sunxi-ng/ccu_nm.c
222
writel(reg, nm->common.base + nm->common.reg);
drivers/clk/sunxi-ng/ccu_phase.c
113
writel(reg | (delay << phase->shift),
drivers/clk/sunxi-ng/ccu_reset.c
24
writel(reg & ~map->bit, ccu->base + map->reg);
drivers/clk/sunxi-ng/ccu_reset.c
42
writel(reg | map->bit, ccu->base + map->reg);
drivers/clk/sunxi-ng/ccu_sdm.c
39
writel(sdm->table[i].pattern,
drivers/clk/sunxi-ng/ccu_sdm.c
45
writel(reg | sdm->tuning_enable, common->base + sdm->tuning_reg);
drivers/clk/sunxi-ng/ccu_sdm.c
50
writel(reg | sdm->enable, common->base + common->reg);
drivers/clk/sunxi-ng/ccu_sdm.c
66
writel(reg & ~sdm->enable, common->base + common->reg);
drivers/clk/sunxi-ng/ccu_sdm.c
71
writel(reg & ~sdm->tuning_enable, common->base + sdm->tuning_reg);
drivers/clk/sunxi/clk-a10-pll2.c
118
writel(val, reg);
drivers/clk/sunxi/clk-a10-ve.c
45
writel(reg & ~BIT(SUN4I_VE_RESET), data->reg);
drivers/clk/sunxi/clk-a10-ve.c
64
writel(reg | BIT(SUN4I_VE_RESET), data->reg);
drivers/clk/sunxi/clk-factors.c
159
writel(reg, factors->reg);
drivers/clk/sunxi/clk-mod0.c
270
writel(value, phase->reg);
drivers/clk/sunxi/clk-sun4i-display.c
56
writel(reg & ~BIT(data->offset + id), data->reg);
drivers/clk/sunxi/clk-sun4i-display.c
73
writel(reg | BIT(data->offset + id), data->reg);
drivers/clk/sunxi/clk-sun4i-tcon-ch1.c
205
writel(reg, tclk->reg);
drivers/clk/sunxi/clk-sun4i-tcon-ch1.c
43
writel(reg, tclk->reg);
drivers/clk/sunxi/clk-sun4i-tcon-ch1.c
56
writel(reg, tclk->reg);
drivers/clk/sunxi/clk-sun4i-tcon-ch1.c
92
writel(reg, tclk->reg);
drivers/clk/sunxi/clk-sun9i-cpus.c
167
writel(reg, cpus->reg);
drivers/clk/sunxi/clk-sun9i-mmc.c
48
writel(val & ~BIT(SUN9I_MMC_RESET_BIT), reg);
drivers/clk/sunxi/clk-sun9i-mmc.c
70
writel(val | BIT(SUN9I_MMC_RESET_BIT), reg);
drivers/clk/sunxi/clk-usb.c
42
writel(reg & ~BIT(id), data->reg);
drivers/clk/sunxi/clk-usb.c
63
writel(reg | BIT(id), data->reg);
drivers/clk/tegra/clk-periph-fixed.c
37
writel(mask, fixed->base + fixed->regs->enb_set_reg);
drivers/clk/tegra/clk-periph-fixed.c
47
writel(mask, fixed->base + fixed->regs->enb_clr_reg);
drivers/clk/tegra/clk-pll.c
1010
writel(val, pll->clk_base + PLLE_SS_CTRL);
drivers/clk/tegra/clk-pll.c
240
#define pll_override_writel(val, offset, p) writel(val, p->pmc + offset)
drivers/clk/tegra/clk-pll.c
933
writel(val, pll->pmc + PMC_SATA_PWRGT);
drivers/clk/tegra/clk-pll.c
937
writel(val, pll->pmc + PMC_SATA_PWRGT);
drivers/clk/tegra/clk-pll.c
941
writel(val, pll->pmc + PMC_SATA_PWRGT);
drivers/clk/tegra/clk-sdmmc-mux.c
157
writel(val, sdmmc_mux->reg);
drivers/clk/tegra/clk-sdmmc-mux.c
82
writel(val, sdmmc_mux->reg);
drivers/clk/tegra/clk-tegra114.c
1102
writel(3 << 30, clk_base + CLK_SOURCE_CSITE);
drivers/clk/tegra/clk-tegra114.c
1112
writel(tegra114_cpu_clk_sctx.clk_csite_src,
drivers/clk/tegra/clk-tegra114.c
1115
writel(tegra114_cpu_clk_sctx.cclkg_burst,
drivers/clk/tegra/clk-tegra114.c
1117
writel(tegra114_cpu_clk_sctx.cclkg_divider,
drivers/clk/tegra/clk-tegra124-emc.c
268
writel(car_value, tegra->clk_regs + CLK_SOURCE_EMC);
drivers/clk/tegra/clk-tegra124.c
1256
writel(3 << 30, clk_base + CLK_SOURCE_CSITE);
drivers/clk/tegra/clk-tegra124.c
1266
writel(tegra124_cpu_clk_sctx.clk_csite_src,
drivers/clk/tegra/clk-tegra124.c
1269
writel(tegra124_cpu_clk_sctx.cclkg_burst,
drivers/clk/tegra/clk-tegra124.c
1271
writel(tegra124_cpu_clk_sctx.cclkg_divider,
drivers/clk/tegra/clk-tegra124.c
1502
writel(plld_base, clk_base + PLLD_BASE);
drivers/clk/tegra/clk-tegra20.c
896
writel(CPU_RESET(cpu),
drivers/clk/tegra/clk-tegra20.c
903
writel(CPU_RESET(cpu),
drivers/clk/tegra/clk-tegra20.c
913
writel(reg & ~CPU_CLOCK(cpu),
drivers/clk/tegra/clk-tegra20.c
924
writel(reg | CPU_CLOCK(cpu),
drivers/clk/tegra/clk-tegra20.c
944
writel(3<<30, clk_base + CLK_SOURCE_CSITE);
drivers/clk/tegra/clk-tegra20.c
979
writel(tegra20_cpu_clk_sctx.pllx_misc,
drivers/clk/tegra/clk-tegra20.c
981
writel(tegra20_cpu_clk_sctx.pllx_base,
drivers/clk/tegra/clk-tegra20.c
994
writel(tegra20_cpu_clk_sctx.cclk_divider,
drivers/clk/tegra/clk-tegra20.c
996
writel(tegra20_cpu_clk_sctx.cpu_burst,
drivers/clk/tegra/clk-tegra20.c
999
writel(tegra20_cpu_clk_sctx.clk_csite_src,
drivers/clk/tegra/clk-tegra210.c
2921
writel(reg, clk_base + PLLU_BASE);
drivers/clk/tegra/clk-tegra210.c
2924
writel(reg, clk_base + PLLU_BASE);
drivers/clk/tegra/clk-tegra210.c
2960
writel(reg, clk_base + PLLU_BASE);
drivers/clk/tegra/clk-tegra210.c
3516
writel(3 << 30, clk_base + CLK_SOURCE_CSITE);
drivers/clk/tegra/clk-tegra210.c
3521
writel(tegra210_cpu_clk_sctx.clk_csite_src,
drivers/clk/tegra/clk-tegra210.c
3669
writel(GENMASK(26, 21) | BIT(7),
drivers/clk/tegra/clk-tegra210.c
3682
writel(BIT(21), clk_base + CLK_RST_CONTROLLER_RST_DEV_Y_CLR);
drivers/clk/tegra/clk-tegra210.c
3689
writel(GENMASK(26, 22) | BIT(7),
drivers/clk/tegra/clk-tegra210.c
3803
writel(value, clk_base + PLLD_BASE);
drivers/clk/tegra/clk-tegra30.c
1091
writel(CPU_RESET(cpu),
drivers/clk/tegra/clk-tegra30.c
1098
writel(CPU_RESET(cpu),
drivers/clk/tegra/clk-tegra30.c
1105
writel(CPU_CLOCK(cpu),
drivers/clk/tegra/clk-tegra30.c
1115
writel(reg | CPU_CLOCK(cpu),
drivers/clk/tegra/clk-tegra30.c
1142
writel(3 << 30, clk_base + CLK_RESET_SOURCE_CSITE);
drivers/clk/tegra/clk-tegra30.c
1177
writel(tegra30_cpu_clk_sctx.pllx_misc,
drivers/clk/tegra/clk-tegra30.c
1179
writel(tegra30_cpu_clk_sctx.pllx_base,
drivers/clk/tegra/clk-tegra30.c
1192
writel(tegra30_cpu_clk_sctx.cclk_divider,
drivers/clk/tegra/clk-tegra30.c
1194
writel(tegra30_cpu_clk_sctx.cpu_burst,
drivers/clk/tegra/clk-tegra30.c
1197
writel(tegra30_cpu_clk_sctx.clk_csite_src,
drivers/clk/ux500/clk-prcc.c
39
writel(clk->cg_sel, (clk->base + PRCC_PCKEN));
drivers/clk/ux500/clk-prcc.c
51
writel(clk->cg_sel, (clk->base + PRCC_PCKDIS));
drivers/clk/ux500/clk-prcc.c
59
writel(clk->cg_sel, (clk->base + PRCC_KCKEN));
drivers/clk/ux500/clk-prcc.c
71
writel(clk->cg_sel, (clk->base + PRCC_KCKDIS));
drivers/clk/ux500/reset-prcc.c
109
writel(BIT(bit), base + PRCC_K_SOFTRST_SET);
drivers/clk/ux500/reset-prcc.c
80
writel(BIT(bit), base + PRCC_K_SOFTRST_CLEAR);
drivers/clk/ux500/reset-prcc.c
82
writel(BIT(bit), base + PRCC_K_SOFTRST_SET);
drivers/clk/ux500/reset-prcc.c
96
writel(BIT(bit), base + PRCC_K_SOFTRST_CLEAR);
drivers/clk/versatile/clk-sp810.c
58
writel(val, sp810->base + SCCTRL);
drivers/clk/visconti/pll.c
139
writel(PLL_CREATE_FRACMODE(rate_table), pll->pll_base + PLL_FRACMODE_REG);
drivers/clk/visconti/pll.c
140
writel(PLL_CREATE_OSTDIV(rate_table), pll->pll_base + PLL_POSTDIV_REG);
drivers/clk/visconti/pll.c
141
writel(rate_table->intin, pll->pll_base + PLL_INTIN_REG);
drivers/clk/visconti/pll.c
142
writel(rate_table->fracin, pll->pll_base + PLL_FRACIN_REG);
drivers/clk/visconti/pll.c
143
writel(rate_table->refdiv, pll->pll_base + PLL_REFDIV_REG);
drivers/clk/visconti/pll.c
183
writel(PLL_CONFIG_SEL, pll->pll_base + PLL_CONF_REG);
drivers/clk/visconti/pll.c
187
writel(reg, pll->pll_base + PLL_CTRL_REG);
drivers/clk/visconti/pll.c
193
writel(reg, pll->pll_base + PLL_CTRL_REG);
drivers/clk/visconti/pll.c
199
writel(reg, pll->pll_base + PLL_CTRL_REG);
drivers/clk/visconti/pll.c
205
writel(reg, pll->pll_base + PLL_CTRL_REG);
drivers/clk/visconti/pll.c
223
writel(PLL_CONFIG_SEL, pll->pll_base + PLL_CONF_REG);
drivers/clk/visconti/pll.c
227
writel(reg, pll->pll_base + PLL_CTRL_REG);
drivers/clk/visconti/pll.c
231
writel(reg, pll->pll_base + PLL_CTRL_REG);
drivers/clk/x86/clk-pmc-atom.c
90
writel(tmp, clk->reg);
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
259
writel(regval1, div_addr);
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
262
writel(regval, div_addr + 4);
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
271
writel(WZRD_DR_BEGIN_DYNA_RECONF,
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
300
writel(value, div_addr);
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
301
writel(0x00, div_addr + WZRD_DR_DIV_TO_PHASE_OFFSET);
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
311
writel(WZRD_DR_BEGIN_DYNA_RECONF_5_2,
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
313
writel(WZRD_DR_BEGIN_DYNA_RECONF1_5_2,
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
436
writel(WZRD_DR_BEGIN_DYNA_RECONF, div_addr);
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
455
writel(0, divider->base + WZRD_CLK_CFG_REG(1, WZRD_CLKFBOUT_4));
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
468
writel(regval1, divider->base + WZRD_CLK_CFG_REG(1,
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
471
writel(regval1, divider->base + WZRD_CLK_CFG_REG(1,
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
478
writel(regval1, divider->base + WZRD_CLK_CFG_REG(1,
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
481
writel(regval1, divider->base + WZRD_CLK_CFG_REG(1, WZRD_DIVCLK));
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
499
writel(regval1, divider->base + WZRD_CLK_CFG_REG(1,
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
502
writel(regval, divider->base + WZRD_CLK_CFG_REG(1,
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
524
writel(reg, divider->base + WZRD_CLK_CFG_REG(0, 2));
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
528
writel(reg, divider->base + WZRD_CLK_CFG_REG(0, 0));
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
529
writel(0, divider->base + WZRD_CLK_CFG_REG(0, 3));
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
759
writel(value, div_addr);
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
760
writel(0x0, div_addr + WZRD_DR_DIV_TO_PHASE_OFFSET);
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
770
writel(WZRD_DR_BEGIN_DYNA_RECONF_5_2,
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
772
writel(WZRD_DR_BEGIN_DYNA_RECONF1_5_2,
drivers/clk/zynq/pll.c
133
writel(reg, clk->pll_ctrl);
drivers/clk/zynq/pll.c
163
writel(reg, clk->pll_ctrl);
drivers/clk/zynq/pll.c
218
writel(reg, pll->pll_ctrl);
drivers/clocksource/arm_global_timer.c
128
writel(ctrl, gt_base + GT_CONTROL);
drivers/clocksource/arm_global_timer.c
214
writel(GT_CONTROL_TIMER_ENABLE, gt_base + GT_CONTROL);
drivers/clocksource/arm_global_timer.c
249
writel(reg, gt_base + GT_CONTROL);
drivers/clocksource/arm_global_timer.c
268
writel(0, gt_base + GT_CONTROL);
drivers/clocksource/arm_global_timer.c
269
writel(0, gt_base + GT_COUNTER0);
drivers/clocksource/arm_global_timer.c
270
writel(0, gt_base + GT_COUNTER1);
drivers/clocksource/arm_global_timer.c
272
writel(FIELD_PREP(GT_CONTROL_PRESCALER_MASK, psv - 1) |
drivers/clocksource/bcm_kona_timer.c
113
writel(lsw + clc, timers.tmr_regs + KONA_GPTIMER_STCM0_OFFSET);
drivers/clocksource/bcm_kona_timer.c
118
writel(reg, timers.tmr_regs + KONA_GPTIMER_STCS_OFFSET);
drivers/clocksource/bcm_kona_timer.c
55
writel(reg, base + KONA_GPTIMER_STCS_OFFSET);
drivers/clocksource/clksrc-dbx500-prcmu.c
64
writel(TIMER_MODE_CONTINUOUS,
drivers/clocksource/clksrc-dbx500-prcmu.c
66
writel(TIMER_DOWNCOUNT_VAL,
drivers/clocksource/dw_apb_timer.c
57
writel(val, timer->base + offs);
drivers/clocksource/ingenic-sysost.c
160
writel(val, ost_clk->ost->base + info->ostccr_reg);
drivers/clocksource/ingenic-sysost.c
176
writel(val, ost_clk->ost->base + info->ostccr_reg);
drivers/clocksource/ingenic-sysost.c
243
writel(OSTECR_OST1ENC, ost->base + OST_REG_OSTECR);
drivers/clocksource/ingenic-sysost.c
253
writel((u32)~OSTFR_FFLAG, ost->base + OST_REG_OSTFR);
drivers/clocksource/ingenic-sysost.c
254
writel(next, ost->base + OST_REG_OST1DFR);
drivers/clocksource/ingenic-sysost.c
255
writel(OSTCR_OST1CLR, ost->base + OST_REG_OSTCR);
drivers/clocksource/ingenic-sysost.c
256
writel(OSTESR_OST1ENS, ost->base + OST_REG_OSTESR);
drivers/clocksource/ingenic-sysost.c
257
writel((u32)~OSTMR_FMASK, ost->base + OST_REG_OSTMR);
drivers/clocksource/ingenic-sysost.c
267
writel(OSTECR_OST1ENC, ost->base + OST_REG_OSTECR);
drivers/clocksource/ingenic-sysost.c
294
writel(val, ost->base + info->ostccr_reg);
drivers/clocksource/ingenic-sysost.c
395
writel(OSTCR_OST2CLR, ost->base + OST_REG_OSTCR);
drivers/clocksource/ingenic-sysost.c
398
writel(OSTESR_OST2ENS, ost->base + OST_REG_OSTESR);
drivers/clocksource/jcore-pit.c
64
writel(0, pit->base + REG_PITEN);
drivers/clocksource/jcore-pit.c
71
writel(delta, pit->base + REG_THROT);
drivers/clocksource/jcore-pit.c
72
writel(pit->enable_val, pit->base + REG_PITEN);
drivers/clocksource/nomadik-mtu.c
104
writel(nmdk_cycle, mtu_base + MTU_LR(1));
drivers/clocksource/nomadik-mtu.c
105
writel(nmdk_cycle, mtu_base + MTU_BGLR(1));
drivers/clocksource/nomadik-mtu.c
107
writel(MTU_CRn_PERIODIC | clk_prescale |
drivers/clocksource/nomadik-mtu.c
110
writel(1 << 1, mtu_base + MTU_IMSC);
drivers/clocksource/nomadik-mtu.c
119
writel(0, mtu_base + MTU_IMSC);
drivers/clocksource/nomadik-mtu.c
121
writel(0, mtu_base + MTU_CR(1));
drivers/clocksource/nomadik-mtu.c
123
writel(0xffffffff, mtu_base + MTU_LR(1));
drivers/clocksource/nomadik-mtu.c
143
writel(0, mtu_base + MTU_CR(0));
drivers/clocksource/nomadik-mtu.c
146
writel(nmdk_cycle, mtu_base + MTU_LR(0));
drivers/clocksource/nomadik-mtu.c
147
writel(nmdk_cycle, mtu_base + MTU_BGLR(0));
drivers/clocksource/nomadik-mtu.c
149
writel(clk_prescale | MTU_CRn_32BITS | MTU_CRn_ENA,
drivers/clocksource/nomadik-mtu.c
179
writel(1 << 1, mtu_base + MTU_ICR); /* Interrupt clear reg */
drivers/clocksource/nomadik-mtu.c
90
writel(1 << 1, mtu_base + MTU_IMSC);
drivers/clocksource/nomadik-mtu.c
91
writel(evt, mtu_base + MTU_LR(1));
drivers/clocksource/nomadik-mtu.c
93
writel(MTU_CRn_ONESHOT | clk_prescale |
drivers/clocksource/renesas-ostm.c
114
writel(timer_of_period(to) - 1, timer_of_base(to) + OSTM_CMP);
drivers/clocksource/renesas-ostm.c
65
writel(0, timer_of_base(to) + OSTM_CMP);
drivers/clocksource/renesas-ostm.c
92
writel(delta, timer_of_base(to) + OSTM_CMP);
drivers/clocksource/samsung_pwm_timer.c
114
writel(reg, pwm.base + REG_TCFG1);
drivers/clocksource/samsung_pwm_timer.c
228
writel(mask | (mask << 5), pwm.base + REG_TINT_CSTAT);
drivers/clocksource/samsung_pwm_timer.c
252
writel(mask | (mask << 5), pwm.base + REG_TINT_CSTAT);
drivers/clocksource/samsung_pwm_timer.c
287
writel(mask | (mask << 5), pwm.base + REG_TINT_CSTAT);
drivers/clocksource/samsung_pwm_timer.c
95
writel(reg, pwm.base + REG_TCFG0);
drivers/clocksource/timer-armada-370-xp.c
109
writel(TIMER0_CLR_MASK, local_base + LCL_TIMER_EVENTS_STATUS);
drivers/clocksource/timer-armada-370-xp.c
114
writel(delta, local_base + TIMER0_VAL_OFF);
drivers/clocksource/timer-armada-370-xp.c
133
writel(TIMER0_CLR_MASK, local_base + LCL_TIMER_EVENTS_STATUS);
drivers/clocksource/timer-armada-370-xp.c
142
writel(ticks_per_jiffy - 1, local_base + TIMER0_RELOAD_OFF);
drivers/clocksource/timer-armada-370-xp.c
143
writel(ticks_per_jiffy - 1, local_base + TIMER0_VAL_OFF);
drivers/clocksource/timer-armada-370-xp.c
161
writel(TIMER0_CLR_MASK, local_base + LCL_TIMER_EVENTS_STATUS);
drivers/clocksource/timer-armada-370-xp.c
219
writel(0xffffffff, timer_base + TIMER0_VAL_OFF);
drivers/clocksource/timer-armada-370-xp.c
220
writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF);
drivers/clocksource/timer-armada-370-xp.c
221
writel(timer0_ctrl_reg, timer_base + TIMER_CTRL_OFF);
drivers/clocksource/timer-armada-370-xp.c
222
writel(timer0_local_ctrl_reg, local_base + TIMER_CTRL_OFF);
drivers/clocksource/timer-armada-370-xp.c
282
writel(0xffffffff, timer_base + TIMER0_VAL_OFF);
drivers/clocksource/timer-armada-370-xp.c
283
writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF);
drivers/clocksource/timer-armada-370-xp.c
90
writel((readl(local_base + TIMER_CTRL_OFF) & ~clr) | set,
drivers/clocksource/timer-atmel-tcb.c
101
writel(tcb_cache[i].imr, tcaddr + ATMEL_TC_REG(i, IER));
drivers/clocksource/timer-atmel-tcb.c
104
writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(i, CCR));
drivers/clocksource/timer-atmel-tcb.c
108
writel(bmr_cache, tcaddr + ATMEL_TC_BMR);
drivers/clocksource/timer-atmel-tcb.c
110
writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
drivers/clocksource/timer-atmel-tcb.c
165
writel(0xff, regs + ATMEL_TC_REG(2, IDR));
drivers/clocksource/timer-atmel-tcb.c
166
writel(ATMEL_TC_CLKDIS, regs + ATMEL_TC_REG(2, CCR));
drivers/clocksource/timer-atmel-tcb.c
184
writel(timer_clock | ATMEL_TC_CPCSTOP | ATMEL_TC_WAVE |
drivers/clocksource/timer-atmel-tcb.c
186
writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
drivers/clocksource/timer-atmel-tcb.c
206
writel(timer_clock | ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO,
drivers/clocksource/timer-atmel-tcb.c
208
writel((tcd->rate + HZ / 2) / HZ, tcaddr + ATMEL_TC_REG(2, RC));
drivers/clocksource/timer-atmel-tcb.c
211
writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
drivers/clocksource/timer-atmel-tcb.c
214
writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG, regs +
drivers/clocksource/timer-atmel-tcb.c
315
writel(mck_divisor_idx /* likely divide-by-8 */
drivers/clocksource/timer-atmel-tcb.c
322
writel(0x0000, tcaddr + ATMEL_TC_REG(0, RA));
drivers/clocksource/timer-atmel-tcb.c
323
writel(0x8000, tcaddr + ATMEL_TC_REG(0, RC));
drivers/clocksource/timer-atmel-tcb.c
324
writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR)); /* no irqs */
drivers/clocksource/timer-atmel-tcb.c
325
writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));
drivers/clocksource/timer-atmel-tcb.c
328
writel(ATMEL_TC_XC1 /* input: TIOA0 */
drivers/clocksource/timer-atmel-tcb.c
332
writel(0xff, tcaddr + ATMEL_TC_REG(1, IDR)); /* no irqs */
drivers/clocksource/timer-atmel-tcb.c
333
writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(1, CCR));
drivers/clocksource/timer-atmel-tcb.c
336
writel(ATMEL_TC_TC1XC1S_TIOA0, tcaddr + ATMEL_TC_BMR);
drivers/clocksource/timer-atmel-tcb.c
338
writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
drivers/clocksource/timer-atmel-tcb.c
344
writel(mck_divisor_idx /* likely divide-by-8 */
drivers/clocksource/timer-atmel-tcb.c
348
writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR)); /* no irqs */
drivers/clocksource/timer-atmel-tcb.c
349
writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));
drivers/clocksource/timer-atmel-tcb.c
352
writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
drivers/clocksource/timer-atmel-tcb.c
426
writel(ATMEL_TC_ALL_IRQ, tc.regs + ATMEL_TC_REG(i, IDR));
drivers/clocksource/timer-atmel-tcb.c
94
writel(tcb_cache[i].cmr, tcaddr + ATMEL_TC_REG(i, CMR));
drivers/clocksource/timer-atmel-tcb.c
95
writel(tcb_cache[i].rc, tcaddr + ATMEL_TC_REG(i, RC));
drivers/clocksource/timer-atmel-tcb.c
96
writel(0, tcaddr + ATMEL_TC_REG(i, RA));
drivers/clocksource/timer-atmel-tcb.c
97
writel(0, tcaddr + ATMEL_TC_REG(i, RB));
drivers/clocksource/timer-atmel-tcb.c
99
writel(0xff, tcaddr + ATMEL_TC_REG(i, IDR));
drivers/clocksource/timer-clint.c
51
writel(1, clint_ipi_base + cpuid_to_hartid_map(cpu));
drivers/clocksource/timer-clint.c
56
writel(0, clint_ipi_base + cpuid_to_hartid_map(smp_processor_id()));
drivers/clocksource/timer-digicolor.c
181
writel(UINT_MAX, dc_timer_dev.base + COUNT(TIMER_B));
drivers/clocksource/timer-digicolor.c
85
writel(count, dt->base + COUNT(dt->timer_id));
drivers/clocksource/timer-ep93xx.c
100
writel(tmode | EP93XX_TIMER123_CONTROL_ENABLE,
drivers/clocksource/timer-ep93xx.c
109
writel(0, tcu->base + EP93XX_TIMER3_CONTROL);
drivers/clocksource/timer-ep93xx.c
130
writel(1, tcu->base + EP93XX_TIMER3_CLEAR);
drivers/clocksource/timer-ep93xx.c
165
writel(EP93XX_TIMER4_VALUE_HIGH_ENABLE,
drivers/clocksource/timer-ep93xx.c
96
writel(tmode, tcu->base + EP93XX_TIMER3_CONTROL);
drivers/clocksource/timer-ep93xx.c
99
writel(next, tcu->base + EP93XX_TIMER3_LOAD);
drivers/clocksource/timer-fttmr010.c
156
writel(cycles, fttmr010->base + TIMER1_LOAD);
drivers/clocksource/timer-fttmr010.c
160
writel(cr + cycles, fttmr010->base + TIMER1_MATCH1);
drivers/clocksource/timer-fttmr010.c
166
writel(cr, fttmr010->base + TIMER_CR);
drivers/clocksource/timer-fttmr010.c
176
writel(fttmr010->t1_enable_val, fttmr010->base + AST2600_TIMER_CR_CLR);
drivers/clocksource/timer-fttmr010.c
189
writel(cr, fttmr010->base + TIMER_CR);
drivers/clocksource/timer-fttmr010.c
203
writel(0, fttmr010->base + TIMER1_COUNT);
drivers/clocksource/timer-fttmr010.c
205
writel(~0, fttmr010->base + TIMER1_LOAD);
drivers/clocksource/timer-fttmr010.c
207
writel(0, fttmr010->base + TIMER1_LOAD);
drivers/clocksource/timer-fttmr010.c
213
writel(cr, fttmr010->base + TIMER_INTR_MASK);
drivers/clocksource/timer-fttmr010.c
230
writel(period, fttmr010->base + TIMER1_LOAD);
drivers/clocksource/timer-fttmr010.c
233
writel(cr, fttmr010->base + TIMER1_COUNT);
drivers/clocksource/timer-fttmr010.c
234
writel(cr, fttmr010->base + TIMER1_LOAD);
drivers/clocksource/timer-fttmr010.c
240
writel(cr, fttmr010->base + TIMER_INTR_MASK);
drivers/clocksource/timer-fttmr010.c
246
writel(cr, fttmr010->base + TIMER_CR);
drivers/clocksource/timer-fttmr010.c
267
writel(0x1, fttmr010->base + TIMER_INTR_STATE);
drivers/clocksource/timer-fttmr010.c
332
writel(TIMER_INT_ALL_MASK, fttmr010->base + TIMER_INTR_MASK);
drivers/clocksource/timer-fttmr010.c
333
writel(0, fttmr010->base + TIMER_INTR_STATE);
drivers/clocksource/timer-fttmr010.c
346
writel(val, fttmr010->base + TIMER_CR);
drivers/clocksource/timer-fttmr010.c
353
writel(0, fttmr010->base + TIMER2_COUNT);
drivers/clocksource/timer-fttmr010.c
354
writel(0, fttmr010->base + TIMER2_MATCH1);
drivers/clocksource/timer-fttmr010.c
355
writel(0, fttmr010->base + TIMER2_MATCH2);
drivers/clocksource/timer-fttmr010.c
358
writel(~0, fttmr010->base + TIMER2_LOAD);
drivers/clocksource/timer-fttmr010.c
366
writel(0, fttmr010->base + TIMER2_LOAD);
drivers/clocksource/timer-fttmr010.c
378
writel(0, fttmr010->base + TIMER1_COUNT);
drivers/clocksource/timer-fttmr010.c
379
writel(0, fttmr010->base + TIMER1_LOAD);
drivers/clocksource/timer-fttmr010.c
380
writel(0, fttmr010->base + TIMER1_MATCH1);
drivers/clocksource/timer-fttmr010.c
381
writel(0, fttmr010->base + TIMER1_MATCH2);
drivers/clocksource/timer-imx-sysctr.c
39
writel(enable ? priv->cmpcr | SYS_CTR_EN : priv->cmpcr, base + CMPCR);
drivers/clocksource/timer-imx-tpm.c
221
writel(0, timer_base + TPM_SC);
drivers/clocksource/timer-imx-tpm.c
223
writel(TPM_SC_TOF_MASK, timer_base + TPM_SC);
drivers/clocksource/timer-imx-tpm.c
224
writel(0, timer_base + TPM_CNT);
drivers/clocksource/timer-imx-tpm.c
226
writel(TPM_C0SC_CHF_MASK, timer_base + TPM_C0SC);
drivers/clocksource/timer-imx-tpm.c
232
writel(TPM_SC_CMOD_INC_PER_CNT |
drivers/clocksource/timer-imx-tpm.c
238
writel(GENMASK(counter_width - 1, 0), timer_base + TPM_MOD);
drivers/clocksource/timer-imx-tpm.c
45
writel(val, timer_base + TPM_C0SC);
drivers/clocksource/timer-imx-tpm.c
56
writel(val, timer_base + TPM_C0SC);
drivers/clocksource/timer-imx-tpm.c
61
writel(TPM_STATUS_CH0F, timer_base + TPM_STATUS);
drivers/clocksource/timer-imx-tpm.c
90
writel(next, timer_base + TPM_C0V);
drivers/clocksource/timer-integrator-ap.c
107
writel(ctrl & ~TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
drivers/clocksource/timer-integrator-ap.c
108
writel(next, clkevt_base + TIMER_LOAD);
drivers/clocksource/timer-integrator-ap.c
109
writel(ctrl | TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
drivers/clocksource/timer-integrator-ap.c
143
writel(ctrl, clkevt_base + TIMER_CTRL);
drivers/clocksource/timer-integrator-ap.c
179
writel(0, base + TIMER_CTRL);
drivers/clocksource/timer-integrator-ap.c
38
writel(0xffff, base + TIMER_LOAD);
drivers/clocksource/timer-integrator-ap.c
39
writel(ctrl, base + TIMER_CTRL);
drivers/clocksource/timer-integrator-ap.c
63
writel(1, clkevt_base + TIMER_INTCLR);
drivers/clocksource/timer-integrator-ap.c
75
writel(ctrl, clkevt_base + TIMER_CTRL);
drivers/clocksource/timer-integrator-ap.c
85
writel(ctrl, clkevt_base + TIMER_CTRL);
drivers/clocksource/timer-integrator-ap.c
94
writel(ctrl, clkevt_base + TIMER_CTRL);
drivers/clocksource/timer-integrator-ap.c
97
writel(timer_reload, clkevt_base + TIMER_LOAD);
drivers/clocksource/timer-integrator-ap.c
99
writel(ctrl, clkevt_base + TIMER_CTRL);
drivers/clocksource/timer-loongson1-pwm.c
47
writel(period, timer_of_base(to) + PWM_LRC);
drivers/clocksource/timer-loongson1-pwm.c
48
writel(period, timer_of_base(to) + PWM_HRC);
drivers/clocksource/timer-loongson1-pwm.c
53
writel(0, timer_of_base(to) + PWM_CNTR);
drivers/clocksource/timer-loongson1-pwm.c
58
writel((INT_EN | PWM_OE | CNT_EN), timer_of_base(to) + PWM_CTRL);
drivers/clocksource/timer-loongson1-pwm.c
63
writel(0, timer_of_base(to) + PWM_CTRL);
drivers/clocksource/timer-loongson1-pwm.c
72
writel(val, timer_of_base(to) + PWM_CTRL);
drivers/clocksource/timer-mediatek-cpux.c
39
writel(reg_idx, timer_of_base(to) + CPUX_IDX_REG);
drivers/clocksource/timer-mediatek-cpux.c
45
writel(reg_idx, timer_of_base(to) + CPUX_IDX_REG);
drivers/clocksource/timer-mediatek-cpux.c
46
writel(val, timer_of_base(to) + CPUX_CON_REG);
drivers/clocksource/timer-mediatek.c
105
writel(ticks, SYST_VAL_REG(to));
drivers/clocksource/timer-mediatek.c
108
writel(SYST_CON_EN | SYST_CON_IRQ_EN, SYST_CON_REG(to));
drivers/clocksource/timer-mediatek.c
119
writel(0, SYST_CON_REG(to_timer_of(clkevt)));
drivers/clocksource/timer-mediatek.c
144
writel(val & ~GPT_CTRL_ENABLE, timer_of_base(to) +
drivers/clocksource/timer-mediatek.c
151
writel(delay, timer_of_base(to) + GPT_CMP_REG(timer));
drivers/clocksource/timer-mediatek.c
160
writel(GPT_IRQ_ACK(timer), timer_of_base(to) + GPT_IRQ_ACK_REG);
drivers/clocksource/timer-mediatek.c
172
writel(val | GPT_CTRL_ENABLE | GPT_CTRL_CLEAR,
drivers/clocksource/timer-mediatek.c
212
writel(GPT_IRQ_ACK(TIMER_CLK_EVT), timer_of_base(to) + GPT_IRQ_ACK_REG);
drivers/clocksource/timer-mediatek.c
221
writel(GPT_CTRL_CLEAR | GPT_CTRL_DISABLE,
drivers/clocksource/timer-mediatek.c
224
writel(GPT_CLK_SRC(GPT_CLK_SRC_SYS13M) | GPT_CLK_DIV1,
drivers/clocksource/timer-mediatek.c
227
writel(0x0, timer_of_base(to) + GPT_CMP_REG(timer));
drivers/clocksource/timer-mediatek.c
229
writel(GPT_CTRL_OP(option) | GPT_CTRL_ENABLE,
drivers/clocksource/timer-mediatek.c
238
writel(0x0, timer_of_base(to) + GPT_IRQ_EN_REG);
drivers/clocksource/timer-mediatek.c
241
writel(0x3f, timer_of_base(to) + GPT_IRQ_ACK_REG);
drivers/clocksource/timer-mediatek.c
244
writel(val | GPT_IRQ_ENABLE(timer),
drivers/clocksource/timer-mediatek.c
260
writel(0x0, timer_of_base(to) + GPT_IRQ_EN_REG);
drivers/clocksource/timer-mediatek.c
267
writel(0x3f, timer_of_base(to) + GPT_IRQ_ACK_REG);
drivers/clocksource/timer-mediatek.c
78
writel(SYST_CON_EN, SYST_CON_REG(to));
drivers/clocksource/timer-mediatek.c
79
writel(SYST_CON_IRQ_CLR | SYST_CON_EN, SYST_CON_REG(to));
drivers/clocksource/timer-mediatek.c
99
writel(SYST_CON_EN, SYST_CON_REG(to));
drivers/clocksource/timer-meson6.c
175
writel(val, timer_base + MESON_ISA_TIMER_MUX);
drivers/clocksource/timer-meson6.c
185
writel(val, timer_base + MESON_ISA_TIMER_MUX);
drivers/clocksource/timer-meson6.c
79
writel(val & ~MESON_ISA_TIMER_MUX_TIMERA_EN,
drivers/clocksource/timer-meson6.c
85
writel(delay, timer_base + MESON_ISA_TIMERA);
drivers/clocksource/timer-meson6.c
97
writel(val | MESON_ISA_TIMER_MUX_TIMERA_EN,
drivers/clocksource/timer-npcm7xx.c
103
writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0);
drivers/clocksource/timer-npcm7xx.c
114
writel(evt, timer_of_base(to) + NPCM7XX_REG_TICR0);
drivers/clocksource/timer-npcm7xx.c
117
writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0);
drivers/clocksource/timer-npcm7xx.c
127
writel(NPCM7XX_T0_CLR_INT, timer_of_base(to) + NPCM7XX_REG_TISR);
drivers/clocksource/timer-npcm7xx.c
157
writel(NPCM7XX_DEFAULT_CSR,
drivers/clocksource/timer-npcm7xx.c
160
writel(NPCM7XX_Tx_RESETINT,
drivers/clocksource/timer-npcm7xx.c
173
writel(NPCM7XX_DEFAULT_CSR,
drivers/clocksource/timer-npcm7xx.c
175
writel(NPCM7XX_Tx_MAX_CNT,
drivers/clocksource/timer-npcm7xx.c
180
writel(val, timer_of_base(&npcm7xx_to) + NPCM7XX_REG_TCSR1);
drivers/clocksource/timer-npcm7xx.c
63
writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0);
drivers/clocksource/timer-npcm7xx.c
75
writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0);
drivers/clocksource/timer-npcm7xx.c
88
writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0);
drivers/clocksource/timer-npcm7xx.c
98
writel(timer_of_period(to), timer_of_base(to) + NPCM7XX_REG_TICR0);
drivers/clocksource/timer-nxp-pit.c
100
writel(PITTFLG_TIF, PITTFLG(pit->clkevt_base));
drivers/clocksource/timer-nxp-pit.c
73
writel(0, PITMCR(base));
drivers/clocksource/timer-nxp-pit.c
78
writel(PITMCR_MDIS, PITMCR(base));
drivers/clocksource/timer-nxp-pit.c
85
writel(val, PITTCTRL(base));
drivers/clocksource/timer-nxp-pit.c
90
writel(0, PITTCTRL(base));
drivers/clocksource/timer-nxp-pit.c
95
writel(cnt, PITLDVAL(base));
drivers/clocksource/timer-nxp-stm.c
104
writel(cnt, STM_CNT(stm_timer->base));
drivers/clocksource/timer-nxp-stm.c
122
writel(reg, STM_CR(stm_timer->base));
drivers/clocksource/timer-nxp-stm.c
133
writel(reg, STM_CR(stm_timer->base));
drivers/clocksource/timer-nxp-stm.c
230
writel(0, STM_CCR0(stm_timer->base));
drivers/clocksource/timer-nxp-stm.c
235
writel(STM_CCR_CEN, STM_CCR0(stm_timer->base));
drivers/clocksource/timer-nxp-stm.c
258
writel(val, STM_CMP0(stm_timer->base));
drivers/clocksource/timer-nxp-stm.c
367
writel(STM_CIR_CIF, STM_CIR0(stm_timer->base));
drivers/clocksource/timer-nxp-stm.c
374
writel(val, STM_CMP0(stm_timer->base));
drivers/clocksource/timer-orion.c
150
writel(~0, timer_base + TIMER0_VAL);
drivers/clocksource/timer-orion.c
151
writel(~0, timer_base + TIMER0_RELOAD);
drivers/clocksource/timer-orion.c
69
writel(delta, timer_base + TIMER1_VAL);
drivers/clocksource/timer-orion.c
87
writel(ticks_per_jiffy - 1, timer_base + TIMER1_RELOAD);
drivers/clocksource/timer-orion.c
88
writel(ticks_per_jiffy - 1, timer_base + TIMER1_VAL);
drivers/clocksource/timer-owl.c
109
writel(OWL_Tx_CTL_PD, owl_clkevt_base + OWL_Tx_CTL);
drivers/clocksource/timer-owl.c
36
writel(0, base + OWL_Tx_CTL);
drivers/clocksource/timer-owl.c
37
writel(0, base + OWL_Tx_VAL);
drivers/clocksource/timer-owl.c
38
writel(0, base + OWL_Tx_CMP);
drivers/clocksource/timer-owl.c
53
writel(ctl, base + OWL_Tx_CTL);
drivers/clocksource/timer-owl.c
86
writel(OWL_Tx_CTL_INTEN, base + OWL_Tx_CTL);
drivers/clocksource/timer-owl.c
87
writel(0, base + OWL_Tx_VAL);
drivers/clocksource/timer-owl.c
88
writel(evt, base + OWL_Tx_CMP);
drivers/clocksource/timer-pistachio.c
209
writel(TIMER_ME_GLOBAL, pcs_gpt.base);
drivers/clocksource/timer-pistachio.c
64
writel(value, base + 0x20 * gpt_id + offset);
drivers/clocksource/timer-realtek.c
111
writel(TS_CMP_EN_MASK, reg_base);
drivers/clocksource/timer-realtek.c
53
writel(high, systimer_base + TS_CMP_VAL_HW_OFST);
drivers/clocksource/timer-realtek.c
54
writel(low, systimer_base + TS_CMP_VAL_LW_OFST);
drivers/clocksource/timer-realtek.c
65
writel(val, systimer_base + TS_CMP_CTRL_OFST);
drivers/clocksource/timer-realtek.c
93
writel(val | TS_CMP_EN_MASK, reg_base);
drivers/clocksource/timer-sp804.c
144
writel(0, clkevt->ctrl);
drivers/clocksource/timer-sp804.c
145
writel(0xffffffff, clkevt->load);
drivers/clocksource/timer-sp804.c
146
writel(0xffffffff, clkevt->value);
drivers/clocksource/timer-sp804.c
148
writel(0xffffffff, clkevt->load_h);
drivers/clocksource/timer-sp804.c
149
writel(0xffffffff, clkevt->value_h);
drivers/clocksource/timer-sp804.c
151
writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
drivers/clocksource/timer-sp804.c
178
writel(1, common_clkevt->intclr);
drivers/clocksource/timer-sp804.c
187
writel(0, common_clkevt->ctrl);
drivers/clocksource/timer-sp804.c
202
writel(common_clkevt->reload, common_clkevt->load);
drivers/clocksource/timer-sp804.c
203
writel(ctrl, common_clkevt->ctrl);
drivers/clocksource/timer-sp804.c
213
writel(next, common_clkevt->load);
drivers/clocksource/timer-sp804.c
214
writel(ctrl, common_clkevt->ctrl);
drivers/clocksource/timer-sp804.c
247
writel(0, common_clkevt->ctrl);
drivers/clocksource/timer-sp804.c
302
writel(0, timer1_base + timer->ctrl);
drivers/clocksource/timer-sp804.c
303
writel(0, timer2_base + timer->ctrl);
drivers/clocksource/timer-sp804.c
390
writel(0, base + arm_sp804_timer.ctrl);
drivers/clocksource/timer-sun4i.c
127
writel(TIMER_IRQ_CLEAR(0), base + TIMER_IRQ_ST_REG);
drivers/clocksource/timer-sun4i.c
177
writel(~0, timer_of_base(&to) + TIMER_INTVAL_REG(1));
drivers/clocksource/timer-sun4i.c
178
writel(TIMER_CTL_ENABLE | TIMER_CTL_RELOAD |
drivers/clocksource/timer-sun4i.c
201
writel(TIMER_CTL_CLK_SRC(TIMER_CTL_CLK_SRC_OSC24M),
drivers/clocksource/timer-sun4i.c
215
writel(val | TIMER_IRQ_EN(0), timer_of_base(&to) + TIMER_IRQ_EN_REG);
drivers/clocksource/timer-sun4i.c
59
writel(val & ~TIMER_CTL_ENABLE, base + TIMER_CTL_REG(timer));
drivers/clocksource/timer-sun4i.c
66
writel(delay, base + TIMER_INTVAL_REG(timer));
drivers/clocksource/timer-sun4i.c
79
writel(val | TIMER_CTL_ENABLE | TIMER_CTL_RELOAD,
drivers/clocksource/timer-sun5i.c
135
writel(0x1, ce->base + TIMER_IRQ_ST_REG);
drivers/clocksource/timer-sun5i.c
179
writel(~0, base + TIMER_INTVAL_LO_REG(1));
drivers/clocksource/timer-sun5i.c
180
writel(TIMER_CTL_ENABLE | TIMER_CTL_RELOAD,
drivers/clocksource/timer-sun5i.c
222
writel(val | TIMER_IRQ_EN(0), base + TIMER_IRQ_EN_REG);
drivers/clocksource/timer-sun5i.c
69
writel(val & ~TIMER_CTL_ENABLE, ce->base + TIMER_CTL_REG(timer));
drivers/clocksource/timer-sun5i.c
76
writel(delay, ce->base + TIMER_INTVAL_LO_REG(timer));
drivers/clocksource/timer-sun5i.c
88
writel(val | TIMER_CTL_ENABLE | TIMER_CTL_RELOAD,
drivers/clocksource/timer-tegra186.c
153
writel(value, tegra->regs + TKEIE(wdt->tmr->hwirq));
drivers/clocksource/timer-vt8500.c
122
writel(1, regbase + TIMER_CTRL_VAL);
drivers/clocksource/timer-vt8500.c
123
writel(0xf, regbase + TIMER_STATUS_VAL);
drivers/clocksource/timer-vt8500.c
124
writel(~0, regbase + TIMER_MATCH_VAL);
drivers/clocksource/timer-vt8500.c
46
writel(3, regbase + TIMER_CTRL_VAL);
drivers/clocksource/timer-vt8500.c
69
writel((unsigned long)alarm, regbase + TIMER_MATCH_VAL);
drivers/clocksource/timer-vt8500.c
74
writel(1, regbase + TIMER_IER_VAL);
drivers/clocksource/timer-vt8500.c
81
writel(readl(regbase + TIMER_CTRL_VAL) | 1, regbase + TIMER_CTRL_VAL);
drivers/clocksource/timer-vt8500.c
82
writel(0, regbase + TIMER_IER_VAL);
drivers/clocksource/timer-vt8500.c
98
writel(0xf, regbase + TIMER_STATUS_VAL);
drivers/clocksource/timer-zevio.c
107
writel(TIMER_INTR_MSK, timer->interrupt_regs + IO_INTR_ACK);
drivers/clocksource/timer-zevio.c
108
writel(CNTL_STOP_TIMER, timer->timer1 + IO_CONTROL);
drivers/clocksource/timer-zevio.c
164
writel(CNTL_STOP_TIMER, timer->timer1 + IO_CONTROL);
drivers/clocksource/timer-zevio.c
165
writel(0, timer->timer1 + IO_DIVIDER);
drivers/clocksource/timer-zevio.c
168
writel(0, timer->interrupt_regs + IO_INTR_MSK);
drivers/clocksource/timer-zevio.c
169
writel(TIMER_INTR_ALL, timer->interrupt_regs + IO_INTR_ACK);
drivers/clocksource/timer-zevio.c
172
writel(0, timer->base + IO_MATCH(TIMER_MATCH));
drivers/clocksource/timer-zevio.c
186
writel(CNTL_STOP_TIMER, timer->timer2 + IO_CONTROL);
drivers/clocksource/timer-zevio.c
187
writel(0, timer->timer2 + IO_CURRENT_VAL);
drivers/clocksource/timer-zevio.c
188
writel(0, timer->timer2 + IO_DIVIDER);
drivers/clocksource/timer-zevio.c
189
writel(CNTL_RUN_TIMER | CNTL_FOREVER | CNTL_INC,
drivers/clocksource/timer-zevio.c
67
writel(delta, timer->timer1 + IO_CURRENT_VAL);
drivers/clocksource/timer-zevio.c
68
writel(CNTL_RUN_TIMER | CNTL_DEC | CNTL_MATCH(TIMER_MATCH),
drivers/clocksource/timer-zevio.c
80
writel(0, timer->interrupt_regs + IO_INTR_MSK);
drivers/clocksource/timer-zevio.c
81
writel(TIMER_INTR_ALL, timer->interrupt_regs + IO_INTR_ACK);
drivers/clocksource/timer-zevio.c
83
writel(CNTL_STOP_TIMER, timer->timer1 + IO_CONTROL);
drivers/clocksource/timer-zevio.c
93
writel(TIMER_INTR_MSK, timer->interrupt_regs + IO_INTR_MSK);
drivers/clocksource/timer-zevio.c
94
writel(TIMER_INTR_ALL, timer->interrupt_regs + IO_INTR_ACK);
drivers/comedi/drivers/8255_pci.c
189
writel(main_phys_addr | WENAB, mite_base + MITE_IODWBSR);
drivers/comedi/drivers/addi_apci_3xxx.c
358
writel(status, dev->mmio + 16);
drivers/comedi/drivers/addi_apci_3xxx.c
391
writel(0x10000, dev->mmio + 12);
drivers/comedi/drivers/addi_apci_3xxx.c
398
writel(delay_mode, dev->mmio + 4);
drivers/comedi/drivers/addi_apci_3xxx.c
403
writel(val, dev->mmio + 0);
drivers/comedi/drivers/addi_apci_3xxx.c
406
writel(delay_mode | 0x100, dev->mmio + 4);
drivers/comedi/drivers/addi_apci_3xxx.c
407
writel(chan, dev->mmio + 0);
drivers/comedi/drivers/addi_apci_3xxx.c
410
writel(delay_mode, dev->mmio + 4);
drivers/comedi/drivers/addi_apci_3xxx.c
413
writel(1, dev->mmio + 48);
drivers/comedi/drivers/addi_apci_3xxx.c
445
writel(0x80000, dev->mmio + 8);
drivers/comedi/drivers/addi_apci_3xxx.c
578
writel(devpriv->ai_time_base, dev->mmio + 36);
drivers/comedi/drivers/addi_apci_3xxx.c
581
writel(devpriv->ai_timer, dev->mmio + 32);
drivers/comedi/drivers/addi_apci_3xxx.c
584
writel(0x180000, dev->mmio + 8);
drivers/comedi/drivers/addi_apci_3xxx.c
622
writel(range, dev->mmio + 96);
drivers/comedi/drivers/addi_apci_3xxx.c
625
writel((val << 8) | chan, dev->mmio + 100);
drivers/comedi/drivers/addi_apci_3xxx.c
733
writel(0, dev->mmio + 8);
drivers/comedi/drivers/addi_apci_3xxx.c
737
writel(val, dev->mmio + 16);
drivers/comedi/drivers/amplc_dio200_common.c
120
writel(val, dev->mmio + offset);
drivers/comedi/drivers/amplc_dio200_common.c
148
writel(val, dev->mmio + offset);
drivers/comedi/drivers/amplc_dio200_pci.c
334
writel(0x80, brbase + 0x50);
drivers/comedi/drivers/cb_pcidas64.c
1225
writel(devpriv->plx_intcsr_bits,
drivers/comedi/drivers/cb_pcidas64.c
1286
writel(bits, devpriv->plx9080_iobase + PLX_REG_BIGEND);
drivers/comedi/drivers/cb_pcidas64.c
1322
writel(bits, plx_iobase + PLX_REG_DMAMODE1);
drivers/comedi/drivers/cb_pcidas64.c
1324
writel(bits, plx_iobase + PLX_REG_DMAMODE0);
drivers/comedi/drivers/cb_pcidas64.c
1331
writel(devpriv->plx_intcsr_bits,
drivers/comedi/drivers/cb_pcidas64.c
1609
writel(devpriv->plx_control_bits, plx_control_addr);
drivers/comedi/drivers/cb_pcidas64.c
1613
writel(devpriv->plx_control_bits, plx_control_addr);
drivers/comedi/drivers/cb_pcidas64.c
1628
writel(devpriv->plx_control_bits, plx_control_addr);
drivers/comedi/drivers/cb_pcidas64.c
1632
writel(devpriv->plx_control_bits, plx_control_addr);
drivers/comedi/drivers/cb_pcidas64.c
2533
writel(0, devpriv->plx9080_iobase + PLX_REG_DMASIZ1);
drivers/comedi/drivers/cb_pcidas64.c
2534
writel(0, devpriv->plx9080_iobase + PLX_REG_DMAPADR1);
drivers/comedi/drivers/cb_pcidas64.c
2535
writel(0, devpriv->plx9080_iobase + PLX_REG_DMALADR1);
drivers/comedi/drivers/cb_pcidas64.c
2536
writel(descriptor_bits,
drivers/comedi/drivers/cb_pcidas64.c
2539
writel(0, devpriv->plx9080_iobase + PLX_REG_DMASIZ0);
drivers/comedi/drivers/cb_pcidas64.c
2540
writel(0, devpriv->plx9080_iobase + PLX_REG_DMAPADR0);
drivers/comedi/drivers/cb_pcidas64.c
2541
writel(0, devpriv->plx9080_iobase + PLX_REG_DMALADR0);
drivers/comedi/drivers/cb_pcidas64.c
2542
writel(descriptor_bits,
drivers/comedi/drivers/cb_pcidas64.c
3058
writel(plx_bits, devpriv->plx9080_iobase + PLX_REG_L2PDBELL);
drivers/comedi/drivers/cb_pcidas64.c
3710
writel(devpriv->plx_control_bits, plx_control_addr);
drivers/comedi/drivers/cb_pcidas64.c
3714
writel(devpriv->plx_control_bits, plx_control_addr);
drivers/comedi/drivers/cb_pcidas64.c
3724
writel(devpriv->plx_control_bits, plx_control_addr);
drivers/comedi/drivers/cb_pcidas64.c
3728
writel(devpriv->plx_control_bits, plx_control_addr);
drivers/comedi/drivers/cb_pcidas64.c
3731
writel(devpriv->plx_control_bits, plx_control_addr);
drivers/comedi/drivers/cb_pcidas64.c
3739
writel(devpriv->plx_control_bits, plx_control_addr);
drivers/comedi/drivers/cb_pcidas64.c
3742
writel(devpriv->plx_control_bits, plx_control_addr);
drivers/comedi/drivers/cb_pcidas64.c
3751
writel(devpriv->plx_control_bits, plx_control_addr);
drivers/comedi/drivers/comedi_8254.c
206
writel(val, mmiobase + reg_offset);
drivers/comedi/drivers/daqboard2000.c
335
writel(1000000, dev->mmio + DB2K_REG_ACQ_PACER_CLOCK_DIV_LOW);
drivers/comedi/drivers/daqboard2000.c
424
writel(cntrl, devpriv->plx + PLX_REG_CNTRL);
drivers/comedi/drivers/daqboard2000.c
427
writel(cntrl, devpriv->plx + PLX_REG_CNTRL);
drivers/comedi/drivers/daqboard2000.c
438
writel(cntrl, devpriv->plx + PLX_REG_CNTRL);
drivers/comedi/drivers/daqboard2000.c
441
writel(cntrl, devpriv->plx + PLX_REG_CNTRL);
drivers/comedi/drivers/daqboard2000.c
444
writel(cntrl, devpriv->plx + PLX_REG_CNTRL);
drivers/comedi/drivers/daqboard2000.c
455
writel(cntrl, devpriv->plx + PLX_REG_CNTRL);
drivers/comedi/drivers/daqboard2000.c
458
writel(cntrl, devpriv->plx + PLX_REG_CNTRL);
drivers/comedi/drivers/gsc_hpdi.c
200
writel(hpdi_intr_status, dev->mmio + INTERRUPT_STATUS_REG);
drivers/comedi/drivers/gsc_hpdi.c
229
writel(plx_bits, devpriv->plx9080_mmio + PLX_REG_L2PDBELL);
drivers/comedi/drivers/gsc_hpdi.c
266
writel(0, dev->mmio + BOARD_CONTROL_REG);
drivers/comedi/drivers/gsc_hpdi.c
267
writel(0, dev->mmio + INTERRUPT_CONTROL_REG);
drivers/comedi/drivers/gsc_hpdi.c
286
writel(RX_FIFO_RESET_BIT, dev->mmio + BOARD_CONTROL_REG);
drivers/comedi/drivers/gsc_hpdi.c
298
writel(0, devpriv->plx9080_mmio + PLX_REG_DMASIZ0);
drivers/comedi/drivers/gsc_hpdi.c
299
writel(0, devpriv->plx9080_mmio + PLX_REG_DMAPADR0);
drivers/comedi/drivers/gsc_hpdi.c
300
writel(0, devpriv->plx9080_mmio + PLX_REG_DMALADR0);
drivers/comedi/drivers/gsc_hpdi.c
305
writel(bits, devpriv->plx9080_mmio + PLX_REG_DMADPR0);
drivers/comedi/drivers/gsc_hpdi.c
319
writel(RX_UNDERRUN_BIT | RX_OVERRUN_BIT, dev->mmio + BOARD_STATUS_REG);
drivers/comedi/drivers/gsc_hpdi.c
322
writel(RX_FULL_INTR, dev->mmio + INTERRUPT_CONTROL_REG);
drivers/comedi/drivers/gsc_hpdi.c
324
writel(RX_ENABLE_BIT, dev->mmio + BOARD_CONTROL_REG);
drivers/comedi/drivers/gsc_hpdi.c
510
writel(BOARD_RESET_BIT, dev->mmio + BOARD_CONTROL_REG);
drivers/comedi/drivers/gsc_hpdi.c
513
writel(ALMOST_EMPTY_BITS(32) | ALMOST_FULL_BITS(32),
drivers/comedi/drivers/gsc_hpdi.c
515
writel(ALMOST_EMPTY_BITS(32) | ALMOST_FULL_BITS(32),
drivers/comedi/drivers/gsc_hpdi.c
523
writel(0, dev->mmio + INTERRUPT_CONTROL_REG);
drivers/comedi/drivers/gsc_hpdi.c
530
writel(plx_intcsr_bits, devpriv->plx9080_mmio + PLX_REG_INTCSR);
drivers/comedi/drivers/gsc_hpdi.c
546
writel(bits, devpriv->plx9080_mmio + PLX_REG_BIGEND);
drivers/comedi/drivers/gsc_hpdi.c
548
writel(0, devpriv->plx9080_mmio + PLX_REG_INTCSR);
drivers/comedi/drivers/gsc_hpdi.c
576
writel(bits, plx_iobase + PLX_REG_DMAMODE0);
drivers/comedi/drivers/gsc_hpdi.c
682
writel(0, devpriv->plx9080_mmio + PLX_REG_INTCSR);
drivers/comedi/drivers/jr3_pci.c
717
writel(0, &block[i].reset);
drivers/comedi/drivers/jr3_pci.h
14
writel(val, p);
drivers/comedi/drivers/jr3_pci.h
24
writel(val, p);
drivers/comedi/drivers/me_daq.c
367
writel(0x00, devpriv->plx_regbase + PLX9052_INTCSR);
drivers/comedi/drivers/me_daq.c
394
writel(0x00, devpriv->plx_regbase + PLX9052_INTCSR);
drivers/comedi/drivers/me_daq.c
403
writel(PLX9052_INTCSR_LI1ENAB |
drivers/comedi/drivers/mite.c
370
writel(CHOR_CLRDONE,
drivers/comedi/drivers/mite.c
394
writel(CHOR_CLRLC, mite->mmio + MITE_CHOR(mite_chan->channel));
drivers/comedi/drivers/mite.c
430
writel(CHOR_DMARESET | CHOR_FRESET,
drivers/comedi/drivers/mite.c
451
writel(CHOR_START, mite->mmio + MITE_CHOR(mite_chan->channel));
drivers/comedi/drivers/mite.c
465
writel(CHOR_ABORT, mite->mmio + MITE_CHOR(mite_chan->channel));
drivers/comedi/drivers/mite.c
508
writel(chcr, mite->mmio + MITE_CHCR(mite_chan->channel));
drivers/comedi/drivers/mite.c
526
writel(mcr, mite->mmio + MITE_MCR(mite_chan->channel));
drivers/comedi/drivers/mite.c
545
writel(dcr, mite->mmio + MITE_DCR(mite_chan->channel));
drivers/comedi/drivers/mite.c
548
writel(0, mite->mmio + MITE_DAR(mite_chan->channel));
drivers/comedi/drivers/mite.c
552
writel(lkcr, mite->mmio + MITE_LKCR(mite_chan->channel));
drivers/comedi/drivers/mite.c
555
writel(mite_chan->ring->dma_addr,
drivers/comedi/drivers/mite.c
625
writel(CHCR_CLR_DMA_IE | CHCR_CLR_LINKP_IE |
drivers/comedi/drivers/mite.c
804
writel(0, mite->mmio + MITE_IODWBSR);
drivers/comedi/drivers/mite.c
807
writel(daq_phys_addr | WENAB |
drivers/comedi/drivers/mite.c
810
writel(0, mite->mmio + MITE_IODWCR_1);
drivers/comedi/drivers/mite.c
812
writel(daq_phys_addr | WENAB, mite->mmio + MITE_IODWBSR);
drivers/comedi/drivers/mite.c
827
writel(unknown_dma_burst_bits, mite->mmio + MITE_UNKNOWN_DMA_BURST_REG);
drivers/comedi/drivers/mite.c
853
writel(CHOR_DMARESET, mite->mmio + MITE_CHOR(i));
drivers/comedi/drivers/mite.c
855
writel(CHCR_CLR_DMA_IE | CHCR_CLR_LINKP_IE | CHCR_CLR_SAR_IE |
drivers/comedi/drivers/ni_65xx.c
285
writel(0x00000000, dev->mmio + NI_65XX_FILTER_REG);
drivers/comedi/drivers/ni_65xx.c
376
writel(interval, dev->mmio + NI_65XX_FILTER_REG);
drivers/comedi/drivers/ni_65xx.c
621
writel(main_phys_addr | WENAB, mite_base + MITE_IODWBSR);
drivers/comedi/drivers/ni_660x.c
279
writel(bits, dev->mmio + addr);
drivers/comedi/drivers/ni_670x.c
109
writel(s->state, dev->mmio + DIO_PORT0_DATA_OFFSET);
drivers/comedi/drivers/ni_670x.c
127
writel(s->io_bits, dev->mmio + DIO_PORT0_DIR_OFFSET);
drivers/comedi/drivers/ni_670x.c
148
writel(main_phys_addr | WENAB, mite_base + MITE_IODWBSR);
drivers/comedi/drivers/ni_670x.c
229
writel(0x10, dev->mmio + MISC_CONTROL_OFFSET);
drivers/comedi/drivers/ni_670x.c
231
writel(0x00, dev->mmio + AO_CONTROL_OFFSET);
drivers/comedi/drivers/ni_670x.c
93
writel(((chan & 15) << 1) | ((chan & 16) >> 4),
drivers/comedi/drivers/ni_670x.c
96
writel(val, dev->mmio + AO_VALUE_OFFSET);
drivers/comedi/drivers/ni_labpc_pci.c
59
writel(main_phys_addr | WENAB, mite_base + MITE_IODWBSR);
drivers/comedi/drivers/ni_mio_common.c
223
writel(data, dev->mmio + reg);
drivers/comedi/drivers/ni_pcidio.c
486
writel(s->io_bits, dev->mmio + PORT_PIN_DIRECTIONS(0));
drivers/comedi/drivers/ni_pcidio.c
497
writel(s->state, dev->mmio + PORT_IO(0));
drivers/comedi/drivers/ni_pcidio.c
623
writel(0x0000, dev->mmio + PORT_PIN_DIRECTIONS(0));
drivers/comedi/drivers/ni_pcidio.c
648
writel(ni_pcidio_ns_to_timer(&cmd->scan_begin_arg,
drivers/comedi/drivers/ni_pcidio.c
675
writel(1, dev->mmio + START_DELAY);
drivers/comedi/drivers/ni_pcidio.c
686
writel(cmd->stop_arg,
drivers/comedi/drivers/ni_pcidio.c
832
writel(0, dev->mmio + FPGA_Control1_Register);
drivers/comedi/drivers/ni_pcidio.c
833
writel(0, dev->mmio + FPGA_Control2_Register);
drivers/comedi/drivers/ni_pcidio.c
834
writel(0, dev->mmio + FPGA_SCALS_Counter_Register);
drivers/comedi/drivers/ni_pcidio.c
835
writel(0, dev->mmio + FPGA_SCAMS_Counter_Register);
drivers/comedi/drivers/ni_pcidio.c
836
writel(0, dev->mmio + FPGA_SCBLS_Counter_Register);
drivers/comedi/drivers/ni_pcidio.c
837
writel(0, dev->mmio + FPGA_SCBMS_Counter_Register);
drivers/comedi/drivers/ni_pcidio.c
869
writel(0, dev->mmio + PORT_IO(0));
drivers/comedi/drivers/ni_pcidio.c
870
writel(0, dev->mmio + PORT_PIN_DIRECTIONS(0));
drivers/comedi/drivers/ni_pcidio.c
871
writel(0, dev->mmio + PORT_PIN_MASK(0));
drivers/comedi/drivers/ni_pcimio.c
1237
writel(0x0, mite->mmio + MITE_IODWBSR);
drivers/comedi/drivers/ni_pcimio.c
1238
writel(((0x80 | window_size) | daq_phys_addr),
drivers/comedi/drivers/ni_pcimio.c
1240
writel(0x1 | old_iodwcr1_bits, mite->mmio + MITE_IODWCR_1);
drivers/comedi/drivers/ni_pcimio.c
1241
writel(0xf, mite->mmio + 0x30);
drivers/comedi/drivers/ni_pcimio.c
1246
writel(old_iodwbsr1_bits, mite->mmio + MITE_IODWBSR_1);
drivers/comedi/drivers/ni_pcimio.c
1247
writel(old_iodwbsr_bits, mite->mmio + MITE_IODWBSR);
drivers/comedi/drivers/ni_pcimio.c
1248
writel(old_iodwcr1_bits, mite->mmio + MITE_IODWCR_1);
drivers/comedi/drivers/ni_pcimio.c
1249
writel(0x0, mite->mmio + 0x30);
drivers/comedi/drivers/rtd520.c
1165
writel(0, dev->mmio + LAS0_BOARD_RESET);
drivers/comedi/drivers/rtd520.c
1167
writel(0, devpriv->lcfg + PLX_REG_INTCSR);
drivers/comedi/drivers/rtd520.c
1181
writel(0, dev->mmio + LAS0_OVERRUN);
drivers/comedi/drivers/rtd520.c
1182
writel(0, dev->mmio + LAS0_CGT_CLEAR);
drivers/comedi/drivers/rtd520.c
1183
writel(0, dev->mmio + LAS0_ADC_FIFO_CLEAR);
drivers/comedi/drivers/rtd520.c
1184
writel(0, dev->mmio + LAS0_DAC_RESET(0));
drivers/comedi/drivers/rtd520.c
1185
writel(0, dev->mmio + LAS0_DAC_RESET(1));
drivers/comedi/drivers/rtd520.c
1308
writel(PLX_INTCSR_PIEN | PLX_INTCSR_PLIEN,
drivers/comedi/drivers/rtd520.c
464
writel(0, dev->mmio + LAS0_CGT_CLEAR);
drivers/comedi/drivers/rtd520.c
465
writel(1, dev->mmio + LAS0_CGT_ENABLE);
drivers/comedi/drivers/rtd520.c
467
writel(rtd_convert_chan_gain(dev, list[ii], ii),
drivers/comedi/drivers/rtd520.c
471
writel(0, dev->mmio + LAS0_CGT_ENABLE);
drivers/comedi/drivers/rtd520.c
472
writel(rtd_convert_chan_gain(dev, list[0], 0),
drivers/comedi/drivers/rtd520.c
488
writel(0, dev->mmio + LAS0_ADC_FIFO_CLEAR);
drivers/comedi/drivers/rtd520.c
491
writel(0, dev->mmio + LAS0_ADC_CONVERSION);
drivers/comedi/drivers/rtd520.c
508
writel(0, dev->mmio + LAS0_ADC_FIFO_CLEAR);
drivers/comedi/drivers/rtd520.c
541
writel(0, dev->mmio + LAS0_ADC_FIFO_CLEAR);
drivers/comedi/drivers/rtd520.c
547
writel(0, dev->mmio + LAS0_ADC_CONVERSION);
drivers/comedi/drivers/rtd520.c
836
writel(0, dev->mmio + LAS0_PACER_STOP);
drivers/comedi/drivers/rtd520.c
837
writel(0, dev->mmio + LAS0_PACER); /* stop pacer */
drivers/comedi/drivers/rtd520.c
838
writel(0, dev->mmio + LAS0_ADC_CONVERSION);
drivers/comedi/drivers/rtd520.c
840
writel(0, dev->mmio + LAS0_ADC_FIFO_CLEAR);
drivers/comedi/drivers/rtd520.c
841
writel(0, dev->mmio + LAS0_OVERRUN);
drivers/comedi/drivers/rtd520.c
850
writel(0, dev->mmio + LAS0_PACER_START);
drivers/comedi/drivers/rtd520.c
852
writel(1, dev->mmio + LAS0_BURST_START);
drivers/comedi/drivers/rtd520.c
854
writel(2, dev->mmio + LAS0_ADC_CONVERSION);
drivers/comedi/drivers/rtd520.c
857
writel(0, dev->mmio + LAS0_PACER_START);
drivers/comedi/drivers/rtd520.c
859
writel(1, dev->mmio + LAS0_ADC_CONVERSION);
drivers/comedi/drivers/rtd520.c
861
writel((devpriv->fifosz / 2 - 1) & 0xffff, dev->mmio + LAS0_ACNT);
drivers/comedi/drivers/rtd520.c
896
writel((devpriv->xfer_count - 1) & 0xffff,
drivers/comedi/drivers/rtd520.c
904
writel(1, dev->mmio + LAS0_PACER_SELECT);
drivers/comedi/drivers/rtd520.c
906
writel(1, dev->mmio + LAS0_ACNT_STOP_ENABLE);
drivers/comedi/drivers/rtd520.c
931
writel(timer & 0xffffff, dev->mmio + LAS0_PCLK);
drivers/comedi/drivers/rtd520.c
937
writel(1, dev->mmio + LAS0_PACER_START);
drivers/comedi/drivers/rtd520.c
949
writel(timer & 0x3ff, dev->mmio + LAS0_BCLK);
drivers/comedi/drivers/rtd520.c
956
writel(2, dev->mmio + LAS0_BURST_START);
drivers/comedi/drivers/rtd520.c
983
writel(0, dev->mmio + LAS0_PACER_STOP);
drivers/comedi/drivers/rtd520.c
984
writel(0, dev->mmio + LAS0_PACER); /* stop pacer */
drivers/comedi/drivers/rtd520.c
985
writel(0, dev->mmio + LAS0_ADC_CONVERSION);
drivers/comedi/drivers/rtd520.c
988
writel(0, dev->mmio + LAS0_ADC_FIFO_CLEAR);
drivers/comedi/drivers/s626.c
110
writel(val, dev->mmio + reg);
drivers/comedi/drivers/s626.c
116
writel(cmd << 16, dev->mmio + reg);
drivers/comedi/drivers/s626.c
1247
writel(0, dev->mmio + S626_P_IER);
drivers/comedi/drivers/s626.c
1250
writel(irqtype, dev->mmio + S626_P_ISR);
drivers/comedi/drivers/s626.c
1265
writel(irqstatus, dev->mmio + S626_P_IER);
drivers/comedi/drivers/s626.c
1292
writel((u32)devpriv->rps_buf.physical_base,
drivers/comedi/drivers/s626.c
1519
writel(gpio_image & ~S626_GPIO1_HI, dev->mmio + S626_P_GPIO);
drivers/comedi/drivers/s626.c
1521
writel(gpio_image & ~S626_GPIO1_HI, dev->mmio + S626_P_GPIO);
drivers/comedi/drivers/s626.c
1522
writel(gpio_image & ~S626_GPIO1_HI, dev->mmio + S626_P_GPIO);
drivers/comedi/drivers/s626.c
1524
writel(gpio_image | S626_GPIO1_HI, dev->mmio + S626_P_GPIO);
drivers/comedi/drivers/s626.c
1561
writel(gpio_image & ~S626_GPIO1_HI, dev->mmio + S626_P_GPIO);
drivers/comedi/drivers/s626.c
1563
writel(gpio_image & ~S626_GPIO1_HI, dev->mmio + S626_P_GPIO);
drivers/comedi/drivers/s626.c
1564
writel(gpio_image & ~S626_GPIO1_HI, dev->mmio + S626_P_GPIO);
drivers/comedi/drivers/s626.c
1566
writel(gpio_image | S626_GPIO1_HI, dev->mmio + S626_P_GPIO);
drivers/comedi/drivers/s626.c
1704
writel(0, dev->mmio + S626_P_IER);
drivers/comedi/drivers/s626.c
1707
writel(S626_IRQ_RPS1 | S626_IRQ_GPIO3, dev->mmio + S626_P_ISR);
drivers/comedi/drivers/s626.c
1785
writel(S626_IRQ_GPIO3 | S626_IRQ_RPS1, dev->mmio + S626_P_IER);
drivers/comedi/drivers/s626.c
181
writel(S626_DEBI_CMD_RDWORD | addr, dev->mmio + S626_P_DEBICMD);
drivers/comedi/drivers/s626.c
1912
writel(0, dev->mmio + S626_P_IER);
drivers/comedi/drivers/s626.c
196
writel(S626_DEBI_CMD_WRWORD | addr, dev->mmio + S626_P_DEBICMD);
drivers/comedi/drivers/s626.c
197
writel(wdata, dev->mmio + S626_P_DEBIAD);
drivers/comedi/drivers/s626.c
214
writel(S626_DEBI_CMD_RDWORD | addr, dev->mmio + S626_P_DEBICMD);
drivers/comedi/drivers/s626.c
217
writel(S626_DEBI_CMD_WRWORD | addr, dev->mmio + S626_P_DEBICMD);
drivers/comedi/drivers/s626.c
2187
writel(S626_DEBI_CFG_SLAVE16 |
drivers/comedi/drivers/s626.c
2192
writel(S626_DEBI_PAGE_DISABLE, dev->mmio + S626_P_DEBIPAGE);
drivers/comedi/drivers/s626.c
2195
writel(S626_GPIO_BASE | S626_GPIO1_HI, dev->mmio + S626_P_GPIO);
drivers/comedi/drivers/s626.c
2204
writel(S626_I2C_CLKSEL | S626_I2C_ABORT,
drivers/comedi/drivers/s626.c
221
writel(val & 0xffff, dev->mmio + S626_P_DEBIAD);
drivers/comedi/drivers/s626.c
2216
writel(S626_I2C_CLKSEL, dev->mmio + S626_P_I2CSTAT);
drivers/comedi/drivers/s626.c
2230
writel(S626_ACON2_INIT, dev->mmio + S626_P_ACON2);
drivers/comedi/drivers/s626.c
2238
writel(S626_RSD1 | S626_SIB_A1, dev->mmio + S626_P_TSL1);
drivers/comedi/drivers/s626.c
2239
writel(S626_RSD1 | S626_SIB_A1 | S626_EOS,
drivers/comedi/drivers/s626.c
2243
writel(S626_ACON1_ADCSTART, dev->mmio + S626_P_ACON1);
drivers/comedi/drivers/s626.c
2250
writel((u32)devpriv->rps_buf.physical_base,
drivers/comedi/drivers/s626.c
2253
writel(0, dev->mmio + S626_P_RPSPAGE1);
drivers/comedi/drivers/s626.c
2255
writel(0, dev->mmio + S626_P_RPS1_TOUT);
drivers/comedi/drivers/s626.c
2311
writel(0, dev->mmio + S626_P_PCI_BT_A);
drivers/comedi/drivers/s626.c
2321
writel((u32)phys_buf, dev->mmio + S626_P_BASEA2_OUT);
drivers/comedi/drivers/s626.c
2322
writel((u32)(phys_buf + sizeof(u32)),
drivers/comedi/drivers/s626.c
2338
writel(8, dev->mmio + S626_P_PAGEA2_OUT);
drivers/comedi/drivers/s626.c
2353
writel(S626_XSD2 | S626_RSD3 | S626_SIB_A2 | S626_EOS,
drivers/comedi/drivers/s626.c
2366
writel(S626_LF_A2, dev->mmio + S626_VECTPORT(1));
drivers/comedi/drivers/s626.c
2369
writel(S626_ACON1_DACSTART, dev->mmio + S626_P_ACON1);
drivers/comedi/drivers/s626.c
2438
writel(0, dev->mmio + S626_P_IER);
drivers/comedi/drivers/s626.c
2441
writel(S626_MC1_SOFT_RESET, dev->mmio + S626_P_MC1);
drivers/comedi/drivers/s626.c
246
writel(val, dev->mmio + S626_P_I2CCTRL);
drivers/comedi/drivers/s626.c
2552
writel(0, dev->mmio + S626_P_IER);
drivers/comedi/drivers/s626.c
2554
writel(S626_IRQ_GPIO3 | S626_IRQ_RPS1,
drivers/comedi/drivers/s626.c
2561
writel(S626_MC1_SHUTDOWN, dev->mmio + S626_P_MC1);
drivers/comedi/drivers/s626.c
2562
writel(S626_ACON1_BASE, dev->mmio + S626_P_ACON1);
drivers/comedi/drivers/s626.c
396
writel(S626_ISR_AFOU, dev->mmio + S626_P_ISR);
drivers/comedi/drivers/s626.c
420
writel(S626_XSD2 | S626_RSD3 | S626_SIB_A2,
drivers/comedi/drivers/s626.c
445
writel(S626_XSD2 | S626_XFIFO_2 | S626_RSD2 | S626_SIB_A2 | S626_EOS,
drivers/comedi/drivers/s626.c
493
writel(S626_RSD3 | S626_SIB_A2 | S626_EOS,
drivers/comedi/drivers/s626.c
551
writel(S626_XSD2 | S626_XFIFO_1 | ws_image,
drivers/comedi/drivers/s626.c
554
writel(S626_XSD2 | S626_XFIFO_0 | ws_image,
drivers/comedi/drivers/s626.c
557
writel(S626_XSD2 | S626_XFIFO_3 | S626_WS3,
drivers/comedi/drivers/s626.c
560
writel(S626_XSD2 | S626_XFIFO_2 | S626_WS3 | S626_EOS,
drivers/comedi/drivers/s626.c
605
writel(S626_XSD2 | S626_XFIFO_1 | S626_WS3,
drivers/comedi/drivers/s626.c
608
writel(S626_XSD2 | S626_XFIFO_0 | S626_WS3,
drivers/comedi/drivers/s626.c
611
writel(S626_XSD2 | S626_XFIFO_3 | S626_WS1,
drivers/comedi/drivers/s626.c
614
writel(S626_XSD2 | S626_XFIFO_2 | S626_WS1 | S626_EOS,
drivers/counter/intel-qep.c
84
writel(value, qep->regs + offset);
drivers/cpufreq/brcmstb-avs-cpufreq.c
253
writel(AVS_STATUS_CLEAR, base + AVS_MBOX_STATUS);
drivers/cpufreq/brcmstb-avs-cpufreq.c
257
writel(args[i], base + AVS_MBOX_PARAM(i));
drivers/cpufreq/brcmstb-avs-cpufreq.c
263
writel(cmd, base + AVS_MBOX_COMMAND);
drivers/cpufreq/brcmstb-avs-cpufreq.c
264
writel(AVS_CPU_L2_INT_MASK, priv->avs_intr_base + AVS_CPU_L2_SET0);
drivers/cpufreq/brcmstb-avs-cpufreq.c
289
writel(AVS_STATUS_CLEAR, base + AVS_MBOX_STATUS);
drivers/cpufreq/loongson2_cpufreq.c
127
writel(readl(LOONGSON_CHIPCFG) & ~0x7, LOONGSON_CHIPCFG);
drivers/cpufreq/loongson2_cpufreq.c
129
writel(cpu_freq, LOONGSON_CHIPCFG);
drivers/cpufreq/tegra186-cpufreq.c
220
writel(edvd_val, data->regs + edvd_offset);
drivers/cpufreq/tegra186-cpufreq.c
393
writel(edvd_val, data->regs + edvd_offset);
drivers/cpufreq/tegra194-cpufreq.c
139
writel(ndiv, data->cpu_data[cpu].freq_core_reg);
drivers/cpuidle/cpuidle-clps711x.c
21
writel(0xaa, clps711x_halt);
drivers/cpuidle/cpuidle-kirkwood.c
32
writel(0x7, ddr_operation_base);
drivers/crypto/allwinner/sun4i-ss/sun4i-ss-cipher.c
143
writel(0, ss->base + SS_CTL);
drivers/crypto/allwinner/sun4i-ss/sun4i-ss-cipher.c
263
writel(mode, ss->base + SS_CTL);
drivers/crypto/allwinner/sun4i-ss/sun4i-ss-cipher.c
390
writel(0, ss->base + SS_CTL);
drivers/crypto/allwinner/sun4i-ss/sun4i-ss-cipher.c
71
writel(mode, ss->base + SS_CTL);
drivers/crypto/allwinner/sun4i-ss/sun4i-ss-core.c
446
writel(SS_ENABLED, ss->base + SS_CTL);
drivers/crypto/allwinner/sun4i-ss/sun4i-ss-core.c
451
writel(0, ss->base + SS_CTL);
drivers/crypto/allwinner/sun4i-ss/sun4i-ss-hash.c
235
writel(op->hash[i], ss->base + SS_IV0 + i * 4);
drivers/crypto/allwinner/sun4i-ss/sun4i-ss-hash.c
238
writel(op->mode | SS_ENABLED | ivmode, ss->base + SS_CTL);
drivers/crypto/allwinner/sun4i-ss/sun4i-ss-hash.c
362
writel(op->mode | SS_ENABLED | SS_DATA_END, ss->base + SS_CTL);
drivers/crypto/allwinner/sun4i-ss/sun4i-ss-hash.c
457
writel(op->mode | SS_ENABLED | SS_DATA_END, ss->base + SS_CTL);
drivers/crypto/allwinner/sun4i-ss/sun4i-ss-hash.c
503
writel(0, ss->base + SS_CTL);
drivers/crypto/allwinner/sun4i-ss/sun4i-ss-prng.c
43
writel(mode, ss->base + SS_CTL);
drivers/crypto/allwinner/sun4i-ss/sun4i-ss-prng.c
48
writel(ss->seed[i], ss->base + SS_KEY0 + i * 4);
drivers/crypto/allwinner/sun4i-ss/sun4i-ss-prng.c
63
writel(0, ss->base + SS_CTL);
drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c
201
writel(v, ce->base + CE_ICR);
drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c
204
writel(desc_addr_val(ce, ce->chanlist[flow].t_phy), ce->base + CE_TDQ);
drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c
214
writel(v, ce->base + CE_TLR);
drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c
294
writel(BIT(flow), ce->base + CE_ISR);
drivers/crypto/allwinner/sun8i-ss/sun8i-ss-core.c
108
writel(rctx->p_key, ss->base + SS_KEY_ADR_REG);
drivers/crypto/allwinner/sun8i-ss/sun8i-ss-core.c
113
writel(rctx->p_iv[0], ss->base + SS_IV_ADR_REG);
drivers/crypto/allwinner/sun8i-ss/sun8i-ss-core.c
115
writel(rctx->t_dst[i - 1].addr + rctx->t_dst[i - 1].len * 4 - ivlen, ss->base + SS_IV_ADR_REG);
drivers/crypto/allwinner/sun8i-ss/sun8i-ss-core.c
117
writel(rctx->p_iv[i], ss->base + SS_IV_ADR_REG);
drivers/crypto/allwinner/sun8i-ss/sun8i-ss-core.c
128
writel(rctx->t_src[i].addr, ss->base + SS_SRC_ADR_REG);
drivers/crypto/allwinner/sun8i-ss/sun8i-ss-core.c
129
writel(rctx->t_dst[i].addr, ss->base + SS_DST_ADR_REG);
drivers/crypto/allwinner/sun8i-ss/sun8i-ss-core.c
130
writel(rctx->t_src[i].len, ss->base + SS_LEN_ADR_REG);
drivers/crypto/allwinner/sun8i-ss/sun8i-ss-core.c
136
writel(v, ss->base + SS_CTL_REG);
drivers/crypto/allwinner/sun8i-ss/sun8i-ss-core.c
158
writel(BIT(flow), ss->base + SS_INT_STA_REG);
drivers/crypto/allwinner/sun8i-ss/sun8i-ss-core.c
643
writel(BIT(0) | BIT(1), ss->base + SS_INT_CTL_REG);
drivers/crypto/allwinner/sun8i-ss/sun8i-ss-hash.c
313
writel(rctx->t_dst[i - 1].addr, ss->base + SS_KEY_ADR_REG);
drivers/crypto/allwinner/sun8i-ss/sun8i-ss-hash.c
314
writel(rctx->t_dst[i - 1].addr, ss->base + SS_IV_ADR_REG);
drivers/crypto/allwinner/sun8i-ss/sun8i-ss-hash.c
323
writel(rctx->t_src[i].addr, ss->base + SS_SRC_ADR_REG);
drivers/crypto/allwinner/sun8i-ss/sun8i-ss-hash.c
324
writel(rctx->t_dst[i].addr, ss->base + SS_DST_ADR_REG);
drivers/crypto/allwinner/sun8i-ss/sun8i-ss-hash.c
325
writel(rctx->t_src[i].len, ss->base + SS_LEN_ADR_REG);
drivers/crypto/allwinner/sun8i-ss/sun8i-ss-hash.c
326
writel(BIT(0) | BIT(1), ss->base + SS_INT_CTL_REG);
drivers/crypto/allwinner/sun8i-ss/sun8i-ss-hash.c
332
writel(v, ss->base + SS_CTL_REG);
drivers/crypto/allwinner/sun8i-ss/sun8i-ss-prng.c
128
writel(dma_iv, ss->base + SS_IV_ADR_REG);
drivers/crypto/allwinner/sun8i-ss/sun8i-ss-prng.c
130
writel(dma_iv, ss->base + SS_KEY_ADR_REG);
drivers/crypto/allwinner/sun8i-ss/sun8i-ss-prng.c
131
writel(dma_dst, ss->base + SS_DST_ADR_REG);
drivers/crypto/allwinner/sun8i-ss/sun8i-ss-prng.c
132
writel(todo / 4, ss->base + SS_LEN_ADR_REG);
drivers/crypto/allwinner/sun8i-ss/sun8i-ss-prng.c
139
writel(v, ss->base + SS_CTL_REG);
drivers/crypto/amcc/crypto4xx_core.c
100
writel(part_ring_size.w, dev->ce_base + CRYPTO4XX_PART_RING_SIZE);
drivers/crypto/amcc/crypto4xx_core.c
101
writel(PPC4XX_SD_BUFFER_SIZE, dev->ce_base + CRYPTO4XX_PART_RING_CFG);
drivers/crypto/amcc/crypto4xx_core.c
105
writel(io_threshold.w, dev->ce_base + CRYPTO4XX_IO_THRESHOLD);
drivers/crypto/amcc/crypto4xx_core.c
106
writel(0, dev->ce_base + CRYPTO4XX_PDR_BASE_UADDR);
drivers/crypto/amcc/crypto4xx_core.c
1062
writel(clr_val, core_dev->dev->ce_base + CRYPTO4XX_INT_CLR);
drivers/crypto/amcc/crypto4xx_core.c
107
writel(0, dev->ce_base + CRYPTO4XX_RDR_BASE_UADDR);
drivers/crypto/amcc/crypto4xx_core.c
108
writel(0, dev->ce_base + CRYPTO4XX_PKT_SRC_UADDR);
drivers/crypto/amcc/crypto4xx_core.c
1087
writel(PPC4XX_PRNG_CTRL_AUTO_EN,
drivers/crypto/amcc/crypto4xx_core.c
109
writel(0, dev->ce_base + CRYPTO4XX_PKT_DEST_UADDR);
drivers/crypto/amcc/crypto4xx_core.c
110
writel(0, dev->ce_base + CRYPTO4XX_SA_UADDR);
drivers/crypto/amcc/crypto4xx_core.c
111
writel(0, dev->ce_base + CRYPTO4XX_GATH_RING_BASE_UADDR);
drivers/crypto/amcc/crypto4xx_core.c
112
writel(0, dev->ce_base + CRYPTO4XX_SCAT_RING_BASE_UADDR);
drivers/crypto/amcc/crypto4xx_core.c
119
writel(pe_dma_cfg.w, dev->ce_base + CRYPTO4XX_PE_DMA_CFG);
drivers/crypto/amcc/crypto4xx_core.c
121
writel(PPC4XX_INTERRUPT_CLR, dev->ce_base + CRYPTO4XX_INT_CLR);
drivers/crypto/amcc/crypto4xx_core.c
122
writel(PPC4XX_INT_DESCR_CNT, dev->ce_base + CRYPTO4XX_INT_DESCR_CNT);
drivers/crypto/amcc/crypto4xx_core.c
123
writel(PPC4XX_INT_DESCR_CNT, dev->ce_base + CRYPTO4XX_INT_DESCR_CNT);
drivers/crypto/amcc/crypto4xx_core.c
124
writel(PPC4XX_INT_CFG, dev->ce_base + CRYPTO4XX_INT_CFG);
drivers/crypto/amcc/crypto4xx_core.c
126
writel(PPC4XX_INT_TIMEOUT_CNT_REVB << 10,
drivers/crypto/amcc/crypto4xx_core.c
128
writel(PPC4XX_PD_DONE_INT | PPC4XX_TMO_ERR_INT,
drivers/crypto/amcc/crypto4xx_core.c
131
writel(PPC4XX_PD_DONE_INT, dev->ce_base + CRYPTO4XX_INT_EN);
drivers/crypto/amcc/crypto4xx_core.c
60
writel(PPC4XX_BYTE_ORDER, dev->ce_base + CRYPTO4XX_BYTE_ORDER_CFG);
drivers/crypto/amcc/crypto4xx_core.c
71
writel(pe_dma_cfg.w, dev->ce_base + CRYPTO4XX_PE_DMA_CFG);
drivers/crypto/amcc/crypto4xx_core.c
78
writel(pe_dma_cfg.w, dev->ce_base + CRYPTO4XX_PE_DMA_CFG);
drivers/crypto/amcc/crypto4xx_core.c
79
writel(dev->pdr_pa, dev->ce_base + CRYPTO4XX_PDR_BASE);
drivers/crypto/amcc/crypto4xx_core.c
80
writel(dev->pdr_pa, dev->ce_base + CRYPTO4XX_RDR_BASE);
drivers/crypto/amcc/crypto4xx_core.c
81
writel(PPC4XX_PRNG_CTRL_AUTO_EN, dev->ce_base + CRYPTO4XX_PRNG_CTRL);
drivers/crypto/amcc/crypto4xx_core.c
83
writel(rand_num, dev->ce_base + CRYPTO4XX_PRNG_SEED_L);
drivers/crypto/amcc/crypto4xx_core.c
85
writel(rand_num, dev->ce_base + CRYPTO4XX_PRNG_SEED_H);
drivers/crypto/amcc/crypto4xx_core.c
889
writel(0, dev->ce_base + CRYPTO4XX_INT_DESCR_RD);
drivers/crypto/amcc/crypto4xx_core.c
89
writel(ring_size.w, dev->ce_base + CRYPTO4XX_RING_SIZE);
drivers/crypto/amcc/crypto4xx_core.c
890
writel(1, dev->ce_base + CRYPTO4XX_INT_DESCR_RD);
drivers/crypto/amcc/crypto4xx_core.c
91
writel(ring_ctrl.w, dev->ce_base + CRYPTO4XX_RING_CTRL);
drivers/crypto/amcc/crypto4xx_core.c
94
writel(device_ctrl, dev->ce_base + CRYPTO4XX_DEVICE_CTRL);
drivers/crypto/amcc/crypto4xx_core.c
95
writel(dev->gdr_pa, dev->ce_base + CRYPTO4XX_GATH_RING_BASE);
drivers/crypto/amcc/crypto4xx_core.c
96
writel(dev->sdr_pa, dev->ce_base + CRYPTO4XX_SCAT_RING_BASE);
drivers/crypto/amcc/crypto4xx_trng.c
61
writel(device_ctrl, dev->ce_base + CRYPTO4XX_DEVICE_CTRL);
drivers/crypto/amlogic/amlogic-gxl-cipher.c
228
writel(mc->chanlist[flow].t_phy | 2, mc->base + (flow << 2));
drivers/crypto/aspeed/aspeed-acry.c
76
writel((val), (acry)->regs + (offset))
drivers/crypto/aspeed/aspeed-hace.h
265
writel((val), (hace)->regs + (offset))
drivers/crypto/gemini/sl3516-ce-core.c
195
writel(v, ce->base + IPSEC_DMA_STATUS);
drivers/crypto/gemini/sl3516-ce-core.c
330
writel(ce->dtx, ce->base + IPSEC_TXDMA_CURR_DESC);
drivers/crypto/gemini/sl3516-ce-core.c
331
writel(ce->drx, ce->base + IPSEC_RXDMA_CURR_DESC);
drivers/crypto/gemini/sl3516-ce-core.c
332
writel(0, ce->base + IPSEC_DMA_STATUS);
drivers/crypto/gemini/sl3516-ce-core.c
84
writel(v, ce->base + IPSEC_TXDMA_CTRL);
drivers/crypto/gemini/sl3516-ce-core.c
96
writel(v, ce->base + IPSEC_RXDMA_CTRL);
drivers/crypto/hifn_795x.c
624
writel((__force u32)cpu_to_le32(val), dev->bar[0] + reg);
drivers/crypto/hifn_795x.c
629
writel((__force u32)cpu_to_le32(val), dev->bar[1] + reg);
drivers/crypto/hisilicon/debugfs.c
1196
writel(0x0, qm->io_base + QM_DFX_MB_CNT_VF);
drivers/crypto/hisilicon/debugfs.c
1197
writel(0x0, qm->io_base + QM_DFX_DB_CNT_VF);
drivers/crypto/hisilicon/debugfs.c
1200
writel(0x0, qm->io_base + QM_DFX_SQE_CNT_VF_SQN);
drivers/crypto/hisilicon/debugfs.c
1201
writel(0x0, qm->io_base + QM_DFX_CQE_CNT_VF_CQN);
drivers/crypto/hisilicon/debugfs.c
1207
writel(0x1, qm->io_base + QM_DFX_CNT_CLR_CE);
drivers/crypto/hisilicon/debugfs.c
1216
writel(0x0, qm->io_base + QM_DFX_CNT_CLR_CE);
drivers/crypto/hisilicon/debugfs.c
638
writel(tmp, qm->io_base + QM_DFX_SQE_CNT_VF_SQN);
drivers/crypto/hisilicon/debugfs.c
642
writel(tmp, qm->io_base + QM_DFX_CQE_CNT_VF_CQN);
drivers/crypto/hisilicon/debugfs.c
658
writel(rd_clr_ctrl, qm->io_base + QM_DFX_CNT_CLR_CE);
drivers/crypto/hisilicon/debugfs.c
701
writel(val, qm->io_base + QM_DFX_MB_CNT_VF);
drivers/crypto/hisilicon/debugfs.c
702
writel(val, qm->io_base + QM_DFX_DB_CNT_VF);
drivers/crypto/hisilicon/debugfs.c
706
writel(tmp, qm->io_base + QM_DFX_SQE_CNT_VF_SQN);
drivers/crypto/hisilicon/debugfs.c
710
writel(tmp, qm->io_base + QM_DFX_CQE_CNT_VF_CQN);
drivers/crypto/hisilicon/hpre/hpre_main.c
1392
writel(err_sts, qm->io_base + HPRE_HAC_SOURCE_INT);
drivers/crypto/hisilicon/hpre/hpre_main.c
1399
writel(nfe_mask & (~err_type), qm->io_base + HPRE_RAS_NFE_ENB);
drivers/crypto/hisilicon/hpre/hpre_main.c
1407
writel(nfe_mask, qm->io_base + HPRE_RAS_NFE_ENB);
drivers/crypto/hisilicon/hpre/hpre_main.c
1408
writel(ce_mask, qm->io_base + HPRE_RAS_CE_ENB);
drivers/crypto/hisilicon/hpre/hpre_main.c
1416
writel(value & ~HPRE_AM_OOO_SHUTDOWN_ENABLE,
drivers/crypto/hisilicon/hpre/hpre_main.c
1418
writel(value | HPRE_AM_OOO_SHUTDOWN_ENABLE,
drivers/crypto/hisilicon/hpre/hpre_main.c
1463
writel(val, qm->io_base + HPRE_INT_MASK);
drivers/crypto/hisilicon/hpre/hpre_main.c
1466
writel(dev_err->shutdown_mask & (~HPRE_AXI_ERROR_MASK),
drivers/crypto/hisilicon/hpre/hpre_main.c
1476
writel(HPRE_AXI_ERROR_MASK, qm->io_base + HPRE_HAC_SOURCE_INT);
drivers/crypto/hisilicon/hpre/hpre_main.c
1478
writel(~err_mask, qm->io_base + HPRE_INT_MASK);
drivers/crypto/hisilicon/hpre/hpre_main.c
1481
writel(dev_err->shutdown_mask, qm->io_base + HPRE_OOO_SHUTDOWN_SEL);
drivers/crypto/hisilicon/hpre/hpre_main.c
564
writel(cluster_core_mask,
drivers/crypto/hisilicon/hpre/hpre_main.c
566
writel(0x1, qm->io_base + offset + HPRE_CORE_INI_CFG);
drivers/crypto/hisilicon/hpre/hpre_main.c
595
writel(val, qm->io_base + QM_PEH_AXUSER_CFG);
drivers/crypto/hisilicon/hpre/hpre_main.c
596
writel(PEH_AXUSER_CFG_ENABLE, qm->io_base + QM_PEH_AXUSER_CFG_ENABLE);
drivers/crypto/hisilicon/hpre/hpre_main.c
609
writel(val, qm->io_base + HPRE_PREFETCH_CFG);
drivers/crypto/hisilicon/hpre/hpre_main.c
632
writel(val, qm->io_base + HPRE_PREFETCH_CFG);
drivers/crypto/hisilicon/hpre/hpre_main.c
661
writel(val, qm->io_base + HPRE_CLKGATE_CTL);
drivers/crypto/hisilicon/hpre/hpre_main.c
665
writel(val, qm->io_base + HPRE_PEH_CFG_AUTO_GATE);
drivers/crypto/hisilicon/hpre/hpre_main.c
674
writel(val, qm->io_base + offset + HPRE_CLUSTER_DYN_CTL);
drivers/crypto/hisilicon/hpre/hpre_main.c
678
writel(val, qm->io_base + offset + HPRE_CORE_SHB_CFG);
drivers/crypto/hisilicon/hpre/hpre_main.c
694
writel(val, qm->io_base + HPRE_CLKGATE_CTL);
drivers/crypto/hisilicon/hpre/hpre_main.c
698
writel(val, qm->io_base + HPRE_PEH_CFG_AUTO_GATE);
drivers/crypto/hisilicon/hpre/hpre_main.c
707
writel(val, qm->io_base + offset + HPRE_CLUSTER_DYN_CTL);
drivers/crypto/hisilicon/hpre/hpre_main.c
711
writel(val, qm->io_base + offset + HPRE_CORE_SHB_CFG);
drivers/crypto/hisilicon/hpre/hpre_main.c
724
writel(HPRE_QM_USR_CFG_MASK, qm->io_base + QM_ARUSER_M_CFG_ENABLE);
drivers/crypto/hisilicon/hpre/hpre_main.c
725
writel(HPRE_QM_USR_CFG_MASK, qm->io_base + QM_AWUSER_M_CFG_ENABLE);
drivers/crypto/hisilicon/hpre/hpre_main.c
729
writel(HPRE_RSA_ENB | HPRE_ECC_ENB,
drivers/crypto/hisilicon/hpre/hpre_main.c
732
writel(HPRE_RSA_ENB, qm->io_base + HPRE_TYPES_ENB);
drivers/crypto/hisilicon/hpre/hpre_main.c
734
writel(HPRE_QM_VFG_AX_MASK, qm->io_base + HPRE_VFG_AXCACHE);
drivers/crypto/hisilicon/hpre/hpre_main.c
735
writel(0x0, qm->io_base + HPRE_BD_ENDIAN);
drivers/crypto/hisilicon/hpre/hpre_main.c
736
writel(0x0, qm->io_base + HPRE_POISON_BYPASS);
drivers/crypto/hisilicon/hpre/hpre_main.c
737
writel(0x0, qm->io_base + HPRE_ECC_BYPASS);
drivers/crypto/hisilicon/hpre/hpre_main.c
739
writel(HPRE_BD_USR_MASK, qm->io_base + HPRE_BD_ARUSR_CFG);
drivers/crypto/hisilicon/hpre/hpre_main.c
740
writel(HPRE_BD_USR_MASK, qm->io_base + HPRE_BD_AWUSR_CFG);
drivers/crypto/hisilicon/hpre/hpre_main.c
741
writel(0x1, qm->io_base + HPRE_RDCHN_INI_CFG);
drivers/crypto/hisilicon/hpre/hpre_main.c
786
writel(0x0, qm->io_base + offset + HPRE_CLUSTER_INQURY);
drivers/crypto/hisilicon/hpre/hpre_main.c
790
writel(0x0, qm->io_base + HPRE_CTRL_CNT_CLR_CE);
drivers/crypto/hisilicon/hpre/hpre_main.c
809
writel(val2, qm->io_base + HPRE_OOO_SHUTDOWN_SEL);
drivers/crypto/hisilicon/hpre/hpre_main.c
811
writel(val1, qm->io_base + HPRE_AM_OOO_SHUTDOWN_ENB);
drivers/crypto/hisilicon/hpre/hpre_main.c
820
writel(err_mask, qm->io_base + HPRE_INT_MASK);
drivers/crypto/hisilicon/hpre/hpre_main.c
831
writel(err_mask, qm->io_base + HPRE_HAC_SOURCE_INT);
drivers/crypto/hisilicon/hpre/hpre_main.c
834
writel(dev_err->ce, qm->io_base + HPRE_RAS_CE_ENB);
drivers/crypto/hisilicon/hpre/hpre_main.c
835
writel(dev_err->nfe, qm->io_base + HPRE_RAS_NFE_ENB);
drivers/crypto/hisilicon/hpre/hpre_main.c
836
writel(dev_err->fe, qm->io_base + HPRE_RAS_FE_ENB);
drivers/crypto/hisilicon/hpre/hpre_main.c
842
writel(~err_mask, qm->io_base + HPRE_INT_MASK);
drivers/crypto/hisilicon/hpre/hpre_main.c
870
writel(tmp, qm->io_base + HPRE_CTRL_CNT_CLR_CE);
drivers/crypto/hisilicon/hpre/hpre_main.c
892
writel(val, qm->io_base + offset + HPRE_CLUSTER_INQURY);
drivers/crypto/hisilicon/qm.c
1247
writel(page_type, qm->io_base + QM_PAGE_SIZE);
drivers/crypto/hisilicon/qm.c
1366
writel(lower_32_bits(tmp), qm->io_base + QM_VFT_CFG_DATA_L);
drivers/crypto/hisilicon/qm.c
1367
writel(upper_32_bits(tmp), qm->io_base + QM_VFT_CFG_DATA_H);
drivers/crypto/hisilicon/qm.c
1386
writel(0x0, qm->io_base + QM_VFT_CFG_OP_WR);
drivers/crypto/hisilicon/qm.c
1387
writel(type, qm->io_base + QM_VFT_CFG_TYPE);
drivers/crypto/hisilicon/qm.c
1391
writel(fun_num, qm->io_base + QM_VFT_CFG);
drivers/crypto/hisilicon/qm.c
1395
writel(0x0, qm->io_base + QM_VFT_CFG_RDY);
drivers/crypto/hisilicon/qm.c
1396
writel(0x1, qm->io_base + QM_VFT_CFG_OP_ENABLE);
drivers/crypto/hisilicon/qm.c
1413
writel(qm->type_rate, qm->io_base + QM_SHAPER_CFG);
drivers/crypto/hisilicon/qm.c
1469
writel(QM_ABNORMAL_INT_MASK_VALUE, qm->io_base + QM_ABNORMAL_INT_MASK);
drivers/crypto/hisilicon/qm.c
1478
writel(qm->error_mask, qm->io_base + QM_ABNORMAL_INT_SOURCE);
drivers/crypto/hisilicon/qm.c
1481
writel(qm_err->ce, qm->io_base + QM_RAS_CE_ENABLE);
drivers/crypto/hisilicon/qm.c
1482
writel(QM_RAS_CE_TIMES_PER_IRQ, qm->io_base + QM_RAS_CE_THRESHOLD);
drivers/crypto/hisilicon/qm.c
1483
writel(qm_err->nfe, qm->io_base + QM_RAS_NFE_ENABLE);
drivers/crypto/hisilicon/qm.c
1484
writel(qm_err->fe, qm->io_base + QM_RAS_FE_ENABLE);
drivers/crypto/hisilicon/qm.c
1495
writel(irq_unmask, qm->io_base + QM_ABNORMAL_INT_MASK);
drivers/crypto/hisilicon/qm.c
1503
writel(irq_mask, qm->io_base + QM_ABNORMAL_INT_MASK);
drivers/crypto/hisilicon/qm.c
1513
writel(qm->err_info.qm_err.shutdown_mask, qm->io_base + QM_OOO_SHUTDOWN_SEL);
drivers/crypto/hisilicon/qm.c
1517
writel(irq_unmask, qm->io_base + QM_ABNORMAL_INT_MASK);
drivers/crypto/hisilicon/qm.c
1525
writel(irq_mask, qm->io_base + QM_ABNORMAL_INT_MASK);
drivers/crypto/hisilicon/qm.c
1528
writel(0x0, qm->io_base + QM_OOO_SHUTDOWN_SEL);
drivers/crypto/hisilicon/qm.c
1586
writel(qm_err->nfe & (~error_status), qm->io_base + QM_RAS_NFE_ENABLE);
drivers/crypto/hisilicon/qm.c
1591
writel(error_status, qm->io_base + QM_ABNORMAL_INT_SOURCE);
drivers/crypto/hisilicon/qm.c
1592
writel(qm_err->nfe, qm->io_base + QM_RAS_NFE_ENABLE);
drivers/crypto/hisilicon/qm.c
1593
writel(qm_err->ce, qm->io_base + QM_RAS_CE_ENABLE);
drivers/crypto/hisilicon/qm.c
1608
writel(val, qm->io_base + QM_IFC_INT_SOURCE_V);
drivers/crypto/hisilicon/qm.c
1686
writel(val, qm->io_base + QM_IFC_INT_CFG);
drivers/crypto/hisilicon/qm.c
1690
writel(val, qm->io_base + QM_IFC_INT_SET_P);
drivers/crypto/hisilicon/qm.c
1699
writel(val, qm->io_base + QM_IFC_INT_SET_V);
drivers/crypto/hisilicon/qm.c
2486
writel(0x1, qm->io_base + QM_CACHE_WB_START);
drivers/crypto/hisilicon/qm.c
3098
writel(val, qm->io_base + QM_IFC_INT_MASK);
drivers/crypto/hisilicon/qm.c
3114
writel(val, qm->io_base + QM_IFC_INT_MASK);
drivers/crypto/hisilicon/qm.c
3136
writel(val, qm->io_base + QM_MIG_REGION_SEL);
drivers/crypto/hisilicon/qm.c
3148
writel(val, qm->io_base + QM_MIG_REGION_SEL);
drivers/crypto/hisilicon/qm.c
3165
writel(state, qm->io_base + QM_VF_STATE);
drivers/crypto/hisilicon/qm.c
3288
writel(0x0, qm->io_base + QM_VF_EQ_INT_MASK);
drivers/crypto/hisilicon/qm.c
3289
writel(0x0, qm->io_base + QM_VF_AEQ_INT_MASK);
drivers/crypto/hisilicon/qm.c
3294
writel(0x1, qm->io_base + QM_VF_EQ_INT_MASK);
drivers/crypto/hisilicon/qm.c
3295
writel(0x1, qm->io_base + QM_VF_AEQ_INT_MASK);
drivers/crypto/hisilicon/qm.c
3932
writel(0x1, qm->io_base + QM_VFT_CFG_OP_WR);
drivers/crypto/hisilicon/qm.c
3933
writel(SHAPER_VFT, qm->io_base + QM_VFT_CFG_TYPE);
drivers/crypto/hisilicon/qm.c
3934
writel(fun_index, qm->io_base + QM_VFT_CFG);
drivers/crypto/hisilicon/qm.c
3936
writel(0x0, qm->io_base + QM_VFT_CFG_RDY);
drivers/crypto/hisilicon/qm.c
3937
writel(0x1, qm->io_base + QM_VFT_CFG_OP_ENABLE);
drivers/crypto/hisilicon/qm.c
4349
writel(ACC_VENDOR_ID_VALUE, qm->io_base + QM_PEH_VENDOR_ID);
drivers/crypto/hisilicon/qm.c
4358
writel(PCI_VENDOR_ID_HUAWEI, qm->io_base + QM_PEH_VENDOR_ID);
drivers/crypto/hisilicon/qm.c
4440
writel(nfe_enb & ~qm->err_info.qm_err.ecc_2bits_mask,
drivers/crypto/hisilicon/qm.c
4442
writel(qm->err_info.qm_err.ecc_2bits_mask, qm->io_base + QM_ABNORMAL_INT_SET);
drivers/crypto/hisilicon/qm.c
4554
writel(ACC_MASTER_GLOBAL_CTRL_SHUTDOWN, qm->io_base + ACC_MASTER_GLOBAL_CTRL);
drivers/crypto/hisilicon/qm.c
4717
writel(value & ~qm->err_info.msi_wr_port,
drivers/crypto/hisilicon/qm.c
4726
writel(qm->err_info.qm_err.ecc_2bits_mask, qm->io_base + QM_ABNORMAL_INT_SOURCE);
drivers/crypto/hisilicon/qm.c
4729
writel(ACC_ROB_ECC_ERR_MULTPL, qm->io_base + ACC_AM_ROB_ECC_INT_STS);
drivers/crypto/hisilicon/qm.c
4746
writel(value, qm->io_base + ACC_AM_CFG_PORT_WR_EN);
drivers/crypto/hisilicon/qm.c
4759
writel(val, qm->io_base + QM_ABNORMAL_INT_MASK);
drivers/crypto/hisilicon/qm.c
4761
writel(qm_err->shutdown_mask & (~QM_RAS_AXI_ERROR),
drivers/crypto/hisilicon/qm.c
4771
writel(QM_RAS_AXI_ERROR, qm->io_base + QM_ABNORMAL_INT_SOURCE);
drivers/crypto/hisilicon/qm.c
4773
writel(~qm->error_mask, qm->io_base + QM_ABNORMAL_INT_MASK);
drivers/crypto/hisilicon/qm.c
4775
writel(qm->err_info.qm_err.shutdown_mask, qm->io_base + QM_OOO_SHUTDOWN_SEL);
drivers/crypto/hisilicon/qm.c
5674
writel(0x0, qm->io_base + ACC_MASTER_GLOBAL_CTRL);
drivers/crypto/hisilicon/qm.c
5681
writel(0x0, qm->io_base + ACC_MASTER_GLOBAL_CTRL);
drivers/crypto/hisilicon/qm.c
5916
writel(QM_DB_TIMEOUT_SET, qm->io_base + QM_DB_TIMEOUT_CFG);
drivers/crypto/hisilicon/qm.c
6082
writel(QM_DB_TIMEOUT_SET, qm->io_base + QM_DB_TIMEOUT_CFG);
drivers/crypto/hisilicon/qm.c
844
writel(val, qm->io_base + QM_PM_CTRL);
drivers/crypto/hisilicon/qm.c
851
writel(0x1, qm->io_base + QM_MEM_START_INIT);
drivers/crypto/hisilicon/sec/sec_drv.c
716
writel(ooo_read, base + SEC_Q_OUTORDER_RD_PTR_REG);
drivers/crypto/hisilicon/sec/sec_drv.c
877
writel(write, base + SEC_Q_WR_PTR_REG);
drivers/crypto/hisilicon/sec2/sec_main.c
1116
writel(err_sts, qm->io_base + SEC_CORE_INT_SOURCE);
drivers/crypto/hisilicon/sec2/sec_main.c
1123
writel(nfe_mask & (~err_type), qm->io_base + SEC_RAS_NFE_REG);
drivers/crypto/hisilicon/sec2/sec_main.c
1131
writel(nfe_mask, qm->io_base + SEC_RAS_NFE_REG);
drivers/crypto/hisilicon/sec2/sec_main.c
1132
writel(ce_mask, qm->io_base + SEC_RAS_CE_REG);
drivers/crypto/hisilicon/sec2/sec_main.c
1140
writel(val & SEC_AXI_SHUTDOWN_DISABLE, qm->io_base + SEC_CONTROL_REG);
drivers/crypto/hisilicon/sec2/sec_main.c
1141
writel(val | SEC_AXI_SHUTDOWN_ENABLE, qm->io_base + SEC_CONTROL_REG);
drivers/crypto/hisilicon/sec2/sec_main.c
1183
writel(err_mask & ~SEC_AXI_ERROR_MASK, qm->io_base + SEC_CORE_INT_MASK);
drivers/crypto/hisilicon/sec2/sec_main.c
1186
writel(dev_err->shutdown_mask & (~SEC_AXI_ERROR_MASK),
drivers/crypto/hisilicon/sec2/sec_main.c
1196
writel(SEC_AXI_ERROR_MASK, qm->io_base + SEC_CORE_INT_SOURCE);
drivers/crypto/hisilicon/sec2/sec_main.c
1198
writel(err_mask, qm->io_base + SEC_CORE_INT_MASK);
drivers/crypto/hisilicon/sec2/sec_main.c
1201
writel(dev_err->shutdown_mask, qm->io_base + SEC_OOO_SHUTDOWN_SEL);
drivers/crypto/hisilicon/sec2/sec_main.c
527
writel(val, qm->io_base + SEC_PREFETCH_CFG);
drivers/crypto/hisilicon/sec2/sec_main.c
549
writel(val, qm->io_base + SEC_PREFETCH_CFG);
drivers/crypto/hisilicon/sec2/sec_main.c
614
writel(val, qm->io_base + SEC_DYNAMIC_GATE_REG);
drivers/crypto/hisilicon/sec2/sec_main.c
618
writel(val, qm->io_base + SEC_CORE_AUTO_GATE);
drivers/crypto/hisilicon/sec2/sec_main.c
655
writel(SEC_SINGLE_PORT_MAX_TRANS,
drivers/crypto/hisilicon/sec2/sec_main.c
659
writel(reg, qm->io_base + SEC_SAA_EN_REG);
drivers/crypto/hisilicon/sec2/sec_main.c
684
writel(AXUSER_BASE, qm->io_base + QM_ARUSER_M_CFG_1);
drivers/crypto/hisilicon/sec2/sec_main.c
685
writel(ARUSER_M_CFG_ENABLE, qm->io_base + QM_ARUSER_M_CFG_ENABLE);
drivers/crypto/hisilicon/sec2/sec_main.c
686
writel(AXUSER_BASE, qm->io_base + QM_AWUSER_M_CFG_1);
drivers/crypto/hisilicon/sec2/sec_main.c
687
writel(AWUSER_M_CFG_ENABLE, qm->io_base + QM_AWUSER_M_CFG_ENABLE);
drivers/crypto/hisilicon/sec2/sec_main.c
688
writel(WUSER_M_CFG_ENABLE, qm->io_base + QM_WUSER_M_CFG_ENABLE);
drivers/crypto/hisilicon/sec2/sec_main.c
691
writel(AXI_M_CFG, qm->io_base + QM_AXI_M_CFG);
drivers/crypto/hisilicon/sec2/sec_main.c
692
writel(AXI_M_CFG_ENABLE, qm->io_base + QM_AXI_M_CFG_ENABLE);
drivers/crypto/hisilicon/sec2/sec_main.c
695
writel(PEH_AXUSER_CFG, qm->io_base + QM_PEH_AXUSER_CFG);
drivers/crypto/hisilicon/sec2/sec_main.c
696
writel(PEH_AXUSER_CFG_ENABLE, qm->io_base + QM_PEH_AXUSER_CFG_ENABLE);
drivers/crypto/hisilicon/sec2/sec_main.c
699
writel(SQC_CACHE_ENABLE | CQC_CACHE_ENABLE | SQC_CACHE_WB_ENABLE |
drivers/crypto/hisilicon/sec2/sec_main.c
712
writel(0x1, qm->io_base + SEC_CTRL_CNT_CLR_CE);
drivers/crypto/hisilicon/sec2/sec_main.c
717
writel(0x0, qm->io_base + SEC_CTRL_CNT_CLR_CE);
drivers/crypto/hisilicon/sec2/sec_main.c
736
writel(val2, qm->io_base + SEC_OOO_SHUTDOWN_SEL);
drivers/crypto/hisilicon/sec2/sec_main.c
738
writel(val1, qm->io_base + SEC_CONTROL_REG);
drivers/crypto/hisilicon/sec2/sec_main.c
747
writel(SEC_CORE_INT_DISABLE, qm->io_base + SEC_CORE_INT_MASK);
drivers/crypto/hisilicon/sec2/sec_main.c
753
writel(err_mask, qm->io_base + SEC_CORE_INT_SOURCE);
drivers/crypto/hisilicon/sec2/sec_main.c
756
writel(dev_err->ce, qm->io_base + SEC_RAS_CE_REG);
drivers/crypto/hisilicon/sec2/sec_main.c
757
writel(dev_err->fe, qm->io_base + SEC_RAS_FE_REG);
drivers/crypto/hisilicon/sec2/sec_main.c
758
writel(dev_err->nfe, qm->io_base + SEC_RAS_NFE_REG);
drivers/crypto/hisilicon/sec2/sec_main.c
764
writel(err_mask, qm->io_base + SEC_CORE_INT_MASK);
drivers/crypto/hisilicon/sec2/sec_main.c
770
writel(SEC_CORE_INT_DISABLE, qm->io_base + SEC_CORE_INT_MASK);
drivers/crypto/hisilicon/sec2/sec_main.c
776
writel(SEC_RAS_DISABLE, qm->io_base + SEC_RAS_CE_REG);
drivers/crypto/hisilicon/sec2/sec_main.c
777
writel(SEC_RAS_DISABLE, qm->io_base + SEC_RAS_FE_REG);
drivers/crypto/hisilicon/sec2/sec_main.c
778
writel(SEC_RAS_DISABLE, qm->io_base + SEC_RAS_NFE_REG);
drivers/crypto/hisilicon/sec2/sec_main.c
796
writel(tmp, qm->io_base + SEC_CTRL_CNT_CLR_CE);
drivers/crypto/hisilicon/trng/trng.c
171
writel(0x1, trng->base + SW_DRBG_GEN);
drivers/crypto/hisilicon/trng/trng.c
76
writel(0x0, trng->base + SW_DRBG_BLOCKS);
drivers/crypto/hisilicon/trng/trng.c
86
writel(val, trng->base + SW_DRBG_SEED(seed_reg));
drivers/crypto/hisilicon/trng/trng.c
89
writel(SW_DRBG_BLOCKS_NUM | (0x1 << SW_DRBG_ENABLE_SHIFT),
drivers/crypto/hisilicon/trng/trng.c
91
writel(0x1, trng->base + SW_DRBG_INIT);
drivers/crypto/hisilicon/zip/dae_main.c
128
writel(axi_val, qm->io_base + DAE_AXI_CFG_OFFSET);
drivers/crypto/hisilicon/zip/dae_main.c
129
writel(err_val, qm->io_base + DAE_ERR_SHUTDOWN_OFFSET);
drivers/crypto/hisilicon/zip/dae_main.c
138
writel(DAE_ERR_ENABLE_MASK, qm->io_base + DAE_ERR_SOURCE_OFFSET);
drivers/crypto/hisilicon/zip/dae_main.c
141
writel(DAE_ERR_CE_MASK, qm->io_base + DAE_ERR_CE_OFFSET);
drivers/crypto/hisilicon/zip/dae_main.c
142
writel(DAE_ERR_NFE_MASK, qm->io_base + DAE_ERR_NFE_OFFSET);
drivers/crypto/hisilicon/zip/dae_main.c
143
writel(DAE_ERR_FE_MASK, qm->io_base + DAE_ERR_FE_OFFSET);
drivers/crypto/hisilicon/zip/dae_main.c
148
writel(DAE_ERR_ENABLE_MASK, qm->io_base + DAE_ERR_ENABLE_OFFSET);
drivers/crypto/hisilicon/zip/dae_main.c
156
writel(0, qm->io_base + DAE_ERR_ENABLE_OFFSET);
drivers/crypto/hisilicon/zip/dae_main.c
170
writel(err_sts, qm->io_base + DAE_ERR_SOURCE_OFFSET);
drivers/crypto/hisilicon/zip/dae_main.c
175
writel(DAE_ERR_NFE_MASK & (~err_type), qm->io_base + DAE_ERR_NFE_OFFSET);
drivers/crypto/hisilicon/zip/dae_main.c
180
writel(DAE_ERR_CE_MASK, qm->io_base + DAE_ERR_CE_OFFSET);
drivers/crypto/hisilicon/zip/dae_main.c
181
writel(DAE_ERR_NFE_MASK, qm->io_base + DAE_ERR_NFE_OFFSET);
drivers/crypto/hisilicon/zip/dae_main.c
255
writel(val, qm->io_base + DAE_AM_CTRL_GLOBAL_OFFSET);
drivers/crypto/hisilicon/zip/dae_main.c
275
writel(val & ~DAE_AXI_SHUTDOWN_EN_MASK, qm->io_base + DAE_AXI_CFG_OFFSET);
drivers/crypto/hisilicon/zip/dae_main.c
276
writel(val | DAE_AXI_SHUTDOWN_EN_MASK, qm->io_base + DAE_AXI_CFG_OFFSET);
drivers/crypto/hisilicon/zip/dae_main.c
74
writel(val, qm->io_base + DAE_MEM_START_OFFSET);
drivers/crypto/hisilicon/zip/zip_main.c
1031
writel(HZIP_RD_CNT_CLR_CE_EN, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE);
drivers/crypto/hisilicon/zip/zip_main.c
1038
writel(0x0, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE);
drivers/crypto/hisilicon/zip/zip_main.c
1181
writel(err_sts, qm->io_base + HZIP_CORE_INT_SOURCE);
drivers/crypto/hisilicon/zip/zip_main.c
1188
writel(nfe_mask & (~err_type), qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB);
drivers/crypto/hisilicon/zip/zip_main.c
1196
writel(nfe_mask, qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB);
drivers/crypto/hisilicon/zip/zip_main.c
1197
writel(ce_mask, qm->io_base + HZIP_CORE_INT_RAS_CE_ENB);
drivers/crypto/hisilicon/zip/zip_main.c
1206
writel(val & ~HZIP_AXI_SHUTDOWN_ENABLE,
drivers/crypto/hisilicon/zip/zip_main.c
1209
writel(val | HZIP_AXI_SHUTDOWN_ENABLE,
drivers/crypto/hisilicon/zip/zip_main.c
1221
writel(nfe_enb & ~HZIP_CORE_INT_STATUS_M_ECC,
drivers/crypto/hisilicon/zip/zip_main.c
1225
writel(HZIP_CORE_INT_STATUS_M_ECC,
drivers/crypto/hisilicon/zip/zip_main.c
1283
writel(val, qm->io_base + HZIP_CORE_INT_MASK_REG);
drivers/crypto/hisilicon/zip/zip_main.c
1286
writel(dev_err->shutdown_mask & (~HZIP_AXI_ERROR_MASK),
drivers/crypto/hisilicon/zip/zip_main.c
1296
writel(HZIP_AXI_ERROR_MASK, qm->io_base + HZIP_CORE_INT_SOURCE);
drivers/crypto/hisilicon/zip/zip_main.c
1298
writel(~err_mask, qm->io_base + HZIP_CORE_INT_MASK_REG);
drivers/crypto/hisilicon/zip/zip_main.c
1301
writel(dev_err->shutdown_mask, qm->io_base + HZIP_OOO_SHUTDOWN_SEL);
drivers/crypto/hisilicon/zip/zip_main.c
479
writel(val, qm->io_base + HZIP_LIT_LEN_EN_OFFSET);
drivers/crypto/hisilicon/zip/zip_main.c
493
writel(val, qm->io_base + HZIP_HIGH_PERF_OFFSET);
drivers/crypto/hisilicon/zip/zip_main.c
533
writel(val, qm->io_base + HZIP_PREFETCH_CFG);
drivers/crypto/hisilicon/zip/zip_main.c
555
writel(val, qm->io_base + HZIP_PREFETCH_CFG);
drivers/crypto/hisilicon/zip/zip_main.c
580
writel(val, qm->io_base + HZIP_CLOCK_GATE_CTRL);
drivers/crypto/hisilicon/zip/zip_main.c
584
writel(val, qm->io_base + HZIP_PEH_CFG_AUTO_GATE);
drivers/crypto/hisilicon/zip/zip_main.c
595
writel(AXUSER_BASE, base + QM_ARUSER_M_CFG_1);
drivers/crypto/hisilicon/zip/zip_main.c
596
writel(ARUSER_M_CFG_ENABLE, base + QM_ARUSER_M_CFG_ENABLE);
drivers/crypto/hisilicon/zip/zip_main.c
597
writel(AXUSER_BASE, base + QM_AWUSER_M_CFG_1);
drivers/crypto/hisilicon/zip/zip_main.c
598
writel(AWUSER_M_CFG_ENABLE, base + QM_AWUSER_M_CFG_ENABLE);
drivers/crypto/hisilicon/zip/zip_main.c
599
writel(WUSER_M_CFG_ENABLE, base + QM_WUSER_M_CFG_ENABLE);
drivers/crypto/hisilicon/zip/zip_main.c
602
writel(AXI_M_CFG, base + QM_AXI_M_CFG);
drivers/crypto/hisilicon/zip/zip_main.c
603
writel(AXI_M_CFG_ENABLE, base + QM_AXI_M_CFG_ENABLE);
drivers/crypto/hisilicon/zip/zip_main.c
606
writel(PEH_AXUSER_CFG, base + QM_PEH_AXUSER_CFG);
drivers/crypto/hisilicon/zip/zip_main.c
607
writel(PEH_AXUSER_CFG_ENABLE, base + QM_PEH_AXUSER_CFG_ENABLE);
drivers/crypto/hisilicon/zip/zip_main.c
610
writel(HZIP_CACHE_ALL_EN, base + HZIP_PORT_ARCA_CHE_0);
drivers/crypto/hisilicon/zip/zip_main.c
611
writel(HZIP_CACHE_ALL_EN, base + HZIP_PORT_ARCA_CHE_1);
drivers/crypto/hisilicon/zip/zip_main.c
612
writel(HZIP_CACHE_ALL_EN, base + HZIP_PORT_AWCA_CHE_0);
drivers/crypto/hisilicon/zip/zip_main.c
613
writel(HZIP_CACHE_ALL_EN, base + HZIP_PORT_AWCA_CHE_1);
drivers/crypto/hisilicon/zip/zip_main.c
616
writel(AXUSER_BASE, base + HZIP_BD_RUSER_32_63);
drivers/crypto/hisilicon/zip/zip_main.c
617
writel(AXUSER_BASE, base + HZIP_BD_WUSER_32_63);
drivers/crypto/hisilicon/zip/zip_main.c
620
writel(AXUSER_BASE | AXUSER_SSV, base + HZIP_DATA_RUSER_32_63);
drivers/crypto/hisilicon/zip/zip_main.c
621
writel(AXUSER_BASE | AXUSER_SSV, base + HZIP_DATA_WUSER_32_63);
drivers/crypto/hisilicon/zip/zip_main.c
622
writel(AXUSER_BASE | AXUSER_SSV, base + HZIP_SGL_RUSER_32_63);
drivers/crypto/hisilicon/zip/zip_main.c
624
writel(AXUSER_BASE, base + HZIP_DATA_RUSER_32_63);
drivers/crypto/hisilicon/zip/zip_main.c
625
writel(AXUSER_BASE, base + HZIP_DATA_WUSER_32_63);
drivers/crypto/hisilicon/zip/zip_main.c
626
writel(AXUSER_BASE, base + HZIP_SGL_RUSER_32_63);
drivers/crypto/hisilicon/zip/zip_main.c
637
writel(HZIP_DECOMP_CHECK_ENABLE | dcomp_bm | comp_bm, base + HZIP_CLOCK_GATE_CTRL);
drivers/crypto/hisilicon/zip/zip_main.c
640
writel(SQC_CACHE_ENABLE | CQC_CACHE_ENABLE | SQC_CACHE_WB_ENABLE |
drivers/crypto/hisilicon/zip/zip_main.c
673
writel(val2, qm->io_base + HZIP_OOO_SHUTDOWN_SEL);
drivers/crypto/hisilicon/zip/zip_main.c
675
writel(val1, qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL);
drivers/crypto/hisilicon/zip/zip_main.c
684
writel(HZIP_CORE_INT_MASK_ALL,
drivers/crypto/hisilicon/zip/zip_main.c
691
writel(err_mask, qm->io_base + HZIP_CORE_INT_SOURCE);
drivers/crypto/hisilicon/zip/zip_main.c
694
writel(dev_err->ce, qm->io_base + HZIP_CORE_INT_RAS_CE_ENB);
drivers/crypto/hisilicon/zip/zip_main.c
695
writel(dev_err->fe, qm->io_base + HZIP_CORE_INT_RAS_FE_ENB);
drivers/crypto/hisilicon/zip/zip_main.c
696
writel(dev_err->nfe, qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB);
drivers/crypto/hisilicon/zip/zip_main.c
701
writel(~err_mask, qm->io_base + HZIP_CORE_INT_MASK_REG);
drivers/crypto/hisilicon/zip/zip_main.c
712
writel(err_mask, qm->io_base + HZIP_CORE_INT_MASK_REG);
drivers/crypto/hisilicon/zip/zip_main.c
741
writel(tmp, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE);
drivers/crypto/inside-secure/eip93/eip93-common.c
505
writel(1, eip93->base + EIP93_REG_PE_CD_COUNT);
drivers/crypto/inside-secure/eip93/eip93-hash.c
280
writel(1, eip93->base + EIP93_REG_PE_CD_COUNT);
drivers/crypto/inside-secure/eip93/eip93-main.c
236
writel(1, eip93->base + EIP93_REG_PE_RD_COUNT);
drivers/crypto/inside-secure/eip93/eip93-main.c
308
writel(val, eip93->base + EIP93_REG_PE_CONFIG);
drivers/crypto/inside-secure/eip93/eip93-main.c
316
writel(val, eip93->base + EIP93_REG_PE_CONFIG);
drivers/crypto/inside-secure/eip93/eip93-main.c
328
writel(val, eip93->base + EIP93_REG_PE_CLOCK_CTRL);
drivers/crypto/inside-secure/eip93/eip93-main.c
333
writel(val, eip93->base + EIP93_REG_PE_BUF_THRESH);
drivers/crypto/inside-secure/eip93/eip93-main.c
346
writel(val, eip93->base + EIP93_REG_PE_RING_THRESH);
drivers/crypto/inside-secure/eip93/eip93-main.c
351
writel(0, eip93->base + EIP93_REG_PE_RING_CONFIG);
drivers/crypto/inside-secure/eip93/eip93-main.c
352
writel(0, eip93->base + EIP93_REG_PE_CDR_BASE);
drivers/crypto/inside-secure/eip93/eip93-main.c
353
writel(0, eip93->base + EIP93_REG_PE_RDR_BASE);
drivers/crypto/inside-secure/eip93/eip93-main.c
387
writel((u32 __force)cdr->base_dma, eip93->base + EIP93_REG_PE_CDR_BASE);
drivers/crypto/inside-secure/eip93/eip93-main.c
388
writel((u32 __force)rdr->base_dma, eip93->base + EIP93_REG_PE_RDR_BASE);
drivers/crypto/inside-secure/eip93/eip93-main.c
391
writel(val, eip93->base + EIP93_REG_PE_RING_CONFIG);
drivers/crypto/inside-secure/eip93/eip93-main.c
404
writel(0, eip93->base + EIP93_REG_PE_CLOCK_CTRL);
drivers/crypto/inside-secure/safexcel.c
104
writel(~marker,
drivers/crypto/inside-secure/safexcel.c
1052
writel(EIP197_xDR_PROC_xD_PKT(i) |
drivers/crypto/inside-secure/safexcel.c
1114
writel(stat & 0xff,
drivers/crypto/inside-secure/safexcel.c
1119
writel(status, EIP197_HIA_AIC_R(priv) + EIP197_HIA_AIC_R_ACK(ring));
drivers/crypto/inside-secure/safexcel.c
135
writel(EIP197_CS_RC_NEXT(EIP197_RC_NULL) |
drivers/crypto/inside-secure/safexcel.c
144
writel(val, priv->base + offset + 4);
drivers/crypto/inside-secure/safexcel.c
1446
writel(val, EIP197_HIA_AIC(priv) + EIP197_HIA_MST_CTRL);
drivers/crypto/inside-secure/safexcel.c
146
writel(0, priv->base + offset + 8);
drivers/crypto/inside-secure/safexcel.c
147
writel(0, priv->base + offset + 12);
drivers/crypto/inside-secure/safexcel.c
153
writel(GENMASK(29, 0),
drivers/crypto/inside-secure/safexcel.c
1717
writel(GENMASK(5, 0), EIP197_HIA_CDR(priv, i) + EIP197_HIA_xDR_STAT);
drivers/crypto/inside-secure/safexcel.c
1718
writel(GENMASK(7, 0), EIP197_HIA_RDR(priv, i) + EIP197_HIA_xDR_STAT);
drivers/crypto/inside-secure/safexcel.c
1721
writel(0, EIP197_HIA_CDR(priv, i) + EIP197_HIA_xDR_RING_BASE_ADDR_LO);
drivers/crypto/inside-secure/safexcel.c
1722
writel(0, EIP197_HIA_CDR(priv, i) + EIP197_HIA_xDR_RING_BASE_ADDR_HI);
drivers/crypto/inside-secure/safexcel.c
1725
writel(0, EIP197_HIA_RDR(priv, i) + EIP197_HIA_xDR_RING_BASE_ADDR_LO);
drivers/crypto/inside-secure/safexcel.c
1726
writel(0, EIP197_HIA_RDR(priv, i) + EIP197_HIA_xDR_RING_BASE_ADDR_HI);
drivers/crypto/inside-secure/safexcel.c
175
writel(val, priv->base + EIP197_CS_RAM_CTRL);
drivers/crypto/inside-secure/safexcel.c
180
writel(0, priv->base + EIP197_TRC_ECCCTRL);
drivers/crypto/inside-secure/safexcel.c
188
writel(val, priv->base + EIP197_TRC_PARAMS);
drivers/crypto/inside-secure/safexcel.c
1932
writel(EIP197_XLX_USER_VECT_LUT0_IDENT,
drivers/crypto/inside-secure/safexcel.c
1934
writel(EIP197_XLX_USER_VECT_LUT1_IDENT,
drivers/crypto/inside-secure/safexcel.c
1936
writel(EIP197_XLX_USER_VECT_LUT2_IDENT,
drivers/crypto/inside-secure/safexcel.c
1938
writel(EIP197_XLX_USER_VECT_LUT3_IDENT,
drivers/crypto/inside-secure/safexcel.c
1942
writel(GENMASK(31, 0),
drivers/crypto/inside-secure/safexcel.c
1952
writel(1, priv->base + EIP197_XLX_GPIO_BASE);
drivers/crypto/inside-secure/safexcel.c
1955
writel(0, priv->base + EIP197_XLX_GPIO_BASE);
drivers/crypto/inside-secure/safexcel.c
201
writel(val, priv->base + EIP197_TRC_PARAMS);
drivers/crypto/inside-secure/safexcel.c
207
writel(0, priv->base + EIP197_TRC_ECCCTRL);
drivers/crypto/inside-secure/safexcel.c
246
writel(val, priv->base + EIP197_CS_RAM_CTRL);
drivers/crypto/inside-secure/safexcel.c
251
writel(val, priv->base + EIP197_TRC_FREECHAIN);
drivers/crypto/inside-secure/safexcel.c
256
writel(val, priv->base + EIP197_TRC_PARAMS2);
drivers/crypto/inside-secure/safexcel.c
262
writel(val, priv->base + EIP197_TRC_PARAMS);
drivers/crypto/inside-secure/safexcel.c
276
writel(3, EIP197_PE(priv) + EIP197_PE_ICE_PUTF_CTRL(pe));
drivers/crypto/inside-secure/safexcel.c
277
writel(0, EIP197_PE(priv) + EIP197_PE_ICE_PPTF_CTRL(pe));
drivers/crypto/inside-secure/safexcel.c
285
writel(val, EIP197_PE(priv) + EIP197_PE_ICE_SCRATCH_CTRL(pe));
drivers/crypto/inside-secure/safexcel.c
289
writel(0, EIP197_PE(priv) +
drivers/crypto/inside-secure/safexcel.c
293
writel(EIP197_PE_ICE_x_CTRL_SW_RESET |
drivers/crypto/inside-secure/safexcel.c
299
writel(EIP197_PE_ICE_x_CTRL_SW_RESET |
drivers/crypto/inside-secure/safexcel.c
305
writel(EIP197_PE_ICE_RAM_CTRL_FPP_PROG_EN,
drivers/crypto/inside-secure/safexcel.c
310
writel(EIP197_DEBUG_OCE_BYPASS, EIP197_PE(priv) +
drivers/crypto/inside-secure/safexcel.c
329
writel(val,
drivers/crypto/inside-secure/safexcel.c
377
writel(0, EIP197_PE(priv) + EIP197_PE_ICE_RAM_CTRL(pe));
drivers/crypto/inside-secure/safexcel.c
386
writel(val, EIP197_PE(priv) + EIP197_PE_ICE_FPP_CTRL(pe));
drivers/crypto/inside-secure/safexcel.c
395
writel(val, EIP197_PE(priv) + EIP197_PE_ICE_PUE_CTRL(pe));
drivers/crypto/inside-secure/safexcel.c
45
writel(0, priv->base + EIP197_FLUE_IFC_LUT(i));
drivers/crypto/inside-secure/safexcel.c
453
writel(EIP197_PE_ICE_RAM_CTRL_PUE_PROG_EN,
drivers/crypto/inside-secure/safexcel.c
512
writel(lower_32_bits(priv->ring[i].cdr.base_dma),
drivers/crypto/inside-secure/safexcel.c
514
writel(upper_32_bits(priv->ring[i].cdr.base_dma),
drivers/crypto/inside-secure/safexcel.c
517
writel(EIP197_xDR_DESC_MODE_64BIT | EIP197_CDR_DESC_MODE_ADCP |
drivers/crypto/inside-secure/safexcel.c
52
writel(0, priv->base + EIP197_FLUE_CACHEBASE_LO(i));
drivers/crypto/inside-secure/safexcel.c
520
writel(((cd_fetch_cnt *
drivers/crypto/inside-secure/safexcel.c
528
writel(val, EIP197_HIA_CDR(priv, i) + EIP197_HIA_xDR_DMA_CFG);
drivers/crypto/inside-secure/safexcel.c
53
writel(0, priv->base + EIP197_FLUE_CACHEBASE_HI(i));
drivers/crypto/inside-secure/safexcel.c
531
writel(GENMASK(5, 0),
drivers/crypto/inside-secure/safexcel.c
54
writel(EIP197_FLUE_CONFIG_MAGIC,
drivers/crypto/inside-secure/safexcel.c
560
writel(lower_32_bits(priv->ring[i].rdr.base_dma),
drivers/crypto/inside-secure/safexcel.c
562
writel(upper_32_bits(priv->ring[i].rdr.base_dma),
drivers/crypto/inside-secure/safexcel.c
565
writel(EIP197_xDR_DESC_MODE_64BIT | (priv->config.rd_offset << 14) |
drivers/crypto/inside-secure/safexcel.c
569
writel(((rd_fetch_cnt *
drivers/crypto/inside-secure/safexcel.c
57
writel(0, priv->base + EIP197_FLUE_OFFSETS);
drivers/crypto/inside-secure/safexcel.c
578
writel(val,
drivers/crypto/inside-secure/safexcel.c
58
writel(0, priv->base + EIP197_FLUE_ARC4_OFFSET);
drivers/crypto/inside-secure/safexcel.c
582
writel(GENMASK(7, 0),
drivers/crypto/inside-secure/safexcel.c
588
writel(val, EIP197_HIA_AIC_R(priv) + EIP197_HIA_AIC_R_ENABLE_CTRL(i));
drivers/crypto/inside-secure/safexcel.c
609
writel(val, EIP197_HIA_AIC(priv) + EIP197_HIA_MST_CTRL);
drivers/crypto/inside-secure/safexcel.c
613
writel(EIP197_MST_CTRL_RD_CACHE(RD_CACHE_4BITS) |
drivers/crypto/inside-secure/safexcel.c
620
writel(0, EIP197_HIA_AIC_G(priv) + EIP197_HIA_AIC_G_ENABLE_CTRL);
drivers/crypto/inside-secure/safexcel.c
623
writel(GENMASK(31, 0), EIP197_HIA_AIC_G(priv) + EIP197_HIA_AIC_G_ACK);
drivers/crypto/inside-secure/safexcel.c
630
writel(EIP197_DxE_THR_CTRL_RESET_PE,
drivers/crypto/inside-secure/safexcel.c
635
writel(EIP197_HIA_RA_PE_CTRL_RESET,
drivers/crypto/inside-secure/safexcel.c
646
writel(val, EIP197_HIA_DFE(priv) + EIP197_HIA_DFE_CFG(pe));
drivers/crypto/inside-secure/safexcel.c
649
writel(0, EIP197_HIA_DFE_THR(priv) + EIP197_HIA_DFE_THR_CTRL(pe));
drivers/crypto/inside-secure/safexcel.c
652
writel(EIP197_PE_IN_xBUF_THRES_MIN(6) |
drivers/crypto/inside-secure/safexcel.c
655
writel(EIP197_PE_IN_xBUF_THRES_MIN(6) |
drivers/crypto/inside-secure/safexcel.c
661
writel(EIP197_HIA_RA_PE_CTRL_EN |
drivers/crypto/inside-secure/safexcel.c
668
writel(EIP197_DxE_THR_CTRL_RESET_PE,
drivers/crypto/inside-secure/safexcel.c
694
writel(val, EIP197_HIA_DSE(priv) + EIP197_HIA_DSE_CFG(pe));
drivers/crypto/inside-secure/safexcel.c
697
writel(0, EIP197_HIA_DSE_THR(priv) + EIP197_HIA_DSE_THR_CTRL(pe));
drivers/crypto/inside-secure/safexcel.c
700
writel(EIP197_PE_OUT_DBUF_THRES_MIN(opbuflo) |
drivers/crypto/inside-secure/safexcel.c
710
writel(val, EIP197_PE(priv) + EIP197_PE_EIP96_TOKEN_CTRL(pe));
drivers/crypto/inside-secure/safexcel.c
713
writel(EIP197_FUNCTION_ALL,
drivers/crypto/inside-secure/safexcel.c
715
writel(EIP197_FUNCTION_ALL,
drivers/crypto/inside-secure/safexcel.c
72
writel(val, priv->base + EIP197_CS_RAM_CTRL);
drivers/crypto/inside-secure/safexcel.c
722
writel(GENMASK(31, 0),
drivers/crypto/inside-secure/safexcel.c
726
writel(0, EIP197_HIA_CDR(priv, i) + EIP197_HIA_xDR_CFG);
drivers/crypto/inside-secure/safexcel.c
729
writel(EIP197_xDR_PREP_CLR_COUNT,
drivers/crypto/inside-secure/safexcel.c
733
writel(EIP197_xDR_PROC_CLR_COUNT,
drivers/crypto/inside-secure/safexcel.c
736
writel(0,
drivers/crypto/inside-secure/safexcel.c
738
writel(0,
drivers/crypto/inside-secure/safexcel.c
741
writel((EIP197_DEFAULT_RING_SIZE * priv->config.cd_offset),
drivers/crypto/inside-secure/safexcel.c
748
writel(0, EIP197_HIA_RDR(priv, i) + EIP197_HIA_xDR_CFG);
drivers/crypto/inside-secure/safexcel.c
751
writel(EIP197_xDR_PREP_CLR_COUNT,
drivers/crypto/inside-secure/safexcel.c
755
writel(EIP197_xDR_PROC_CLR_COUNT,
drivers/crypto/inside-secure/safexcel.c
758
writel(0,
drivers/crypto/inside-secure/safexcel.c
760
writel(0,
drivers/crypto/inside-secure/safexcel.c
764
writel((EIP197_DEFAULT_RING_SIZE * priv->config.rd_offset),
drivers/crypto/inside-secure/safexcel.c
770
writel(EIP197_DxE_THR_CTRL_EN | GENMASK(priv->config.rings - 1, 0),
drivers/crypto/inside-secure/safexcel.c
774
writel(EIP197_DxE_THR_CTRL_EN | GENMASK(priv->config.rings - 1, 0),
drivers/crypto/inside-secure/safexcel.c
779
writel(GENMASK(30, 20), EIP197_HIA_AIC_G(priv) + EIP197_HIA_AIC_G_ACK);
drivers/crypto/inside-secure/safexcel.c
782
writel(EIP197_STRC_CONFIG_INIT |
drivers/crypto/inside-secure/safexcel.c
786
writel(EIP197_PE_EIP96_TOKEN_CTRL2_CTX_DONE,
drivers/crypto/inside-secure/safexcel.c
815
writel(EIP197_HIA_RDR_THRESH_PKT_MODE |
drivers/crypto/inside-secure/safexcel.c
890
writel((rdesc * priv->config.rd_offset),
drivers/crypto/inside-secure/safexcel.c
894
writel((cdesc * priv->config.cd_offset),
drivers/crypto/inside-secure/safexcel.c
95
writel(marker,
drivers/crypto/intel/keembay/ocs-hcu.c
182
writel(0xFFFFFFFF, hcu_dev->io_base + OCS_HCU_ISR);
drivers/crypto/intel/keembay/ocs-hcu.c
185
writel(HCU_IRQ_HASH_DONE | HCU_IRQ_HASH_ERR_MASK,
drivers/crypto/intel/keembay/ocs-hcu.c
192
writel(0xFFFFFFFF, hcu_dev->io_base + OCS_HCU_DMA_MSI_ISR);
drivers/crypto/intel/keembay/ocs-hcu.c
195
writel(HCU_DMA_IRQ_ERR_MASK | HCU_DMA_IRQ_SRC_DONE,
drivers/crypto/intel/keembay/ocs-hcu.c
198
writel(HCU_DMA_MSI_UNMASK, hcu_dev->io_base + OCS_HCU_DMA_MSI_MASK);
drivers/crypto/intel/keembay/ocs-hcu.c
203
writel(HCU_IRQ_DISABLE, hcu_dev->io_base + OCS_HCU_IER);
drivers/crypto/intel/keembay/ocs-hcu.c
204
writel(HCU_DMA_MSI_DISABLE, hcu_dev->io_base + OCS_HCU_DMA_MSI_IER);
drivers/crypto/intel/keembay/ocs-hcu.c
301
writel(chain[i], hcu_dev->io_base + OCS_HCU_CHAIN);
drivers/crypto/intel/keembay/ocs-hcu.c
303
writel(data->msg_len_lo, hcu_dev->io_base + OCS_HCU_MSG_LEN_LO);
drivers/crypto/intel/keembay/ocs-hcu.c
304
writel(data->msg_len_hi, hcu_dev->io_base + OCS_HCU_MSG_LEN_HI);
drivers/crypto/intel/keembay/ocs-hcu.c
365
writel(cfg, hcu_dev->io_base + OCS_HCU_MODE);
drivers/crypto/intel/keembay/ocs-hcu.c
380
writel(0, hcu_dev->io_base + OCS_HCU_KEY_0 + reg_off);
drivers/crypto/intel/keembay/ocs-hcu.c
418
writel(HCU_BYTE_ORDER_SWAP,
drivers/crypto/intel/keembay/ocs-hcu.c
425
writel(key_u32[OCS_HCU_HW_KEY_LEN_U32 - 1 - i],
drivers/crypto/intel/keembay/ocs-hcu.c
471
writel(dma_list->dma_addr, hcu_dev->io_base + OCS_HCU_DMA_NEXT_SRC_DESCR);
drivers/crypto/intel/keembay/ocs-hcu.c
472
writel(0, hcu_dev->io_base + OCS_HCU_DMA_SRC_SIZE);
drivers/crypto/intel/keembay/ocs-hcu.c
473
writel(0, hcu_dev->io_base + OCS_HCU_DMA_DST_SIZE);
drivers/crypto/intel/keembay/ocs-hcu.c
475
writel(OCS_HCU_START, hcu_dev->io_base + OCS_HCU_OPERATION);
drivers/crypto/intel/keembay/ocs-hcu.c
477
writel(cfg, hcu_dev->io_base + OCS_HCU_DMA_DMA_MODE);
drivers/crypto/intel/keembay/ocs-hcu.c
480
writel(OCS_HCU_TERMINATE, hcu_dev->io_base + OCS_HCU_OPERATION);
drivers/crypto/intel/keembay/ocs-hcu.c
705
writel(OCS_HCU_TERMINATE, hcu_dev->io_base + OCS_HCU_OPERATION);
drivers/crypto/intel/keembay/ocs-hcu.c
749
writel(dma_handle, hcu_dev->io_base + OCS_HCU_DMA_SRC_ADDR);
drivers/crypto/intel/keembay/ocs-hcu.c
750
writel(data_len, hcu_dev->io_base + OCS_HCU_DMA_SRC_SIZE);
drivers/crypto/intel/keembay/ocs-hcu.c
751
writel(OCS_HCU_START, hcu_dev->io_base + OCS_HCU_OPERATION);
drivers/crypto/intel/keembay/ocs-hcu.c
752
writel(reg, hcu_dev->io_base + OCS_HCU_DMA_DMA_MODE);
drivers/crypto/intel/keembay/ocs-hcu.c
754
writel(OCS_HCU_TERMINATE, hcu_dev->io_base + OCS_HCU_OPERATION);
drivers/crypto/intel/keembay/ocs-hcu.c
816
writel(hcu_irq, hcu_dev->io_base + OCS_HCU_ISR);
drivers/crypto/intel/keembay/ocs-hcu.c
820
writel(dma_irq, hcu_dev->io_base + OCS_HCU_DMA_MSI_ISR);
drivers/crypto/marvell/cesa/cesa.c
128
writel(~status, engine->regs + CESA_SA_FPGA_INT_STATUS);
drivers/crypto/marvell/cesa/cesa.c
129
writel(~status, engine->regs + CESA_SA_INT_STATUS);
drivers/crypto/marvell/cesa/cesa.c
316
writel(0, iobase + CESA_TDMA_WINDOW_CTRL(i));
drivers/crypto/marvell/cesa/cesa.c
317
writel(0, iobase + CESA_TDMA_WINDOW_BASE(i));
drivers/crypto/marvell/cesa/cesa.c
323
writel(((cs->size - 1) & 0xffff0000) |
drivers/crypto/marvell/cesa/cesa.c
327
writel(cs->base, iobase + CESA_TDMA_WINDOW_BASE(i));
drivers/crypto/marvell/cesa/cesa.c
512
writel(0, engine->regs + CESA_SA_INT_STATUS);
drivers/crypto/marvell/cesa/cesa.c
513
writel(CESA_SA_CFG_STOP_DIG_ERR,
drivers/crypto/marvell/cesa/cesa.c
515
writel(engine->sram_dma & CESA_SA_SRAM_MSK,
drivers/crypto/marvell/cesa/cipher.c
123
writel(CESA_SA_CMD_EN_CESA_SA_ACCL0, engine->regs + CESA_SA_CMD);
drivers/crypto/marvell/cesa/hash.c
284
writel(CESA_SA_CMD_EN_CESA_SA_ACCL0, engine->regs + CESA_SA_CMD);
drivers/crypto/marvell/cesa/tdma.c
64
writel(CESA_SA_CMD_EN_CESA_SA_ACCL0, engine->regs + CESA_SA_CMD);
drivers/crypto/mxs-dcp.c
1046
writel(stat, sdcp->base + MXS_DCP_STAT_CLR);
drivers/crypto/mxs-dcp.c
1122
writel(MXS_DCP_CTRL_GATHER_RESIDUAL_WRITES |
drivers/crypto/mxs-dcp.c
1127
writel(MXS_DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK,
drivers/crypto/mxs-dcp.c
1137
writel(0xffff0000, sdcp->base + MXS_DCP_CONTEXT);
drivers/crypto/mxs-dcp.c
1139
writel(0xffffffff, sdcp->base + MXS_DCP_CH_N_STAT_CLR(i));
drivers/crypto/mxs-dcp.c
1140
writel(0xffffffff, sdcp->base + MXS_DCP_STAT_CLR);
drivers/crypto/mxs-dcp.c
194
writel(0xffffffff, sdcp->base + MXS_DCP_CH_N_STAT_CLR(chan));
drivers/crypto/mxs-dcp.c
197
writel(desc_phys, sdcp->base + MXS_DCP_CH_N_CMDPTR(chan));
drivers/crypto/mxs-dcp.c
200
writel(1, sdcp->base + MXS_DCP_CH_N_SEMA(chan));
drivers/crypto/qce/common.c
28
writel(val, qce->base + offset);
drivers/crypto/qcom-rng.c
140
writel(val, rng->base + PRNG_LFSR_CFG);
drivers/crypto/qcom-rng.c
144
writel(val, rng->base + PRNG_CONFIG);
drivers/crypto/sahara.c
224
writel(data, dev->regs_base + reg);
drivers/crypto/starfive/jh7110-aes.c
101
writel(value, cryp->base + STARFIVE_AES_CSR);
drivers/crypto/starfive/jh7110-aes.c
110
writel(upper_32_bits(cryp->assoclen), cryp->base + STARFIVE_AES_ALEN0);
drivers/crypto/starfive/jh7110-aes.c
111
writel(lower_32_bits(cryp->assoclen), cryp->base + STARFIVE_AES_ALEN1);
drivers/crypto/starfive/jh7110-aes.c
118
writel(upper_32_bits(cryp->total_in), cryp->base + STARFIVE_AES_MLEN0);
drivers/crypto/starfive/jh7110-aes.c
119
writel(lower_32_bits(cryp->total_in), cryp->base + STARFIVE_AES_MLEN1);
drivers/crypto/starfive/jh7110-aes.c
135
writel(iv[0], cryp->base + STARFIVE_AES_IV0);
drivers/crypto/starfive/jh7110-aes.c
136
writel(iv[1], cryp->base + STARFIVE_AES_IV1);
drivers/crypto/starfive/jh7110-aes.c
137
writel(iv[2], cryp->base + STARFIVE_AES_IV2);
drivers/crypto/starfive/jh7110-aes.c
146
writel(iv[3], cryp->base + STARFIVE_AES_IV3);
drivers/crypto/starfive/jh7110-aes.c
163
writel(nonce[0], cryp->base + STARFIVE_AES_NONCE0);
drivers/crypto/starfive/jh7110-aes.c
164
writel(nonce[1], cryp->base + STARFIVE_AES_NONCE1);
drivers/crypto/starfive/jh7110-aes.c
165
writel(nonce[2], cryp->base + STARFIVE_AES_NONCE2);
drivers/crypto/starfive/jh7110-aes.c
166
writel(nonce[3], cryp->base + STARFIVE_AES_NONCE3);
drivers/crypto/starfive/jh7110-aes.c
175
writel(key[0], cryp->base + STARFIVE_AES_KEY0);
drivers/crypto/starfive/jh7110-aes.c
176
writel(key[1], cryp->base + STARFIVE_AES_KEY1);
drivers/crypto/starfive/jh7110-aes.c
177
writel(key[2], cryp->base + STARFIVE_AES_KEY2);
drivers/crypto/starfive/jh7110-aes.c
178
writel(key[3], cryp->base + STARFIVE_AES_KEY3);
drivers/crypto/starfive/jh7110-aes.c
182
writel(key[4], cryp->base + STARFIVE_AES_KEY4);
drivers/crypto/starfive/jh7110-aes.c
183
writel(key[5], cryp->base + STARFIVE_AES_KEY5);
drivers/crypto/starfive/jh7110-aes.c
187
writel(key[6], cryp->base + STARFIVE_AES_KEY6);
drivers/crypto/starfive/jh7110-aes.c
188
writel(key[7], cryp->base + STARFIVE_AES_KEY7);
drivers/crypto/starfive/jh7110-aes.c
233
writel(rctx->csr.aes.v, cryp->base + STARFIVE_AES_CSR);
drivers/crypto/starfive/jh7110-aes.c
261
writel(rctx->csr.aes.v, cryp->base + STARFIVE_AES_CSR);
drivers/crypto/starfive/jh7110-aes.c
271
writel(GCM_AES_IV_SIZE, cryp->base + STARFIVE_AES_IVLEN);
drivers/crypto/starfive/jh7110-aes.c
353
writel(*buffer, cryp->base + STARFIVE_AES_NONCE0);
drivers/crypto/starfive/jh7110-aes.c
355
writel(*buffer, cryp->base + STARFIVE_AES_NONCE1);
drivers/crypto/starfive/jh7110-aes.c
357
writel(*buffer, cryp->base + STARFIVE_AES_NONCE2);
drivers/crypto/starfive/jh7110-aes.c
359
writel(*buffer, cryp->base + STARFIVE_AES_NONCE3);
drivers/crypto/starfive/jh7110-aes.c
389
writel(*buffer, cryp->base + STARFIVE_AES_AESDIO0R);
drivers/crypto/starfive/jh7110-aes.c
395
writel(*buffer, cryp->base + STARFIVE_AES_AESDIO0R);
drivers/crypto/starfive/jh7110-aes.c
449
writel(alg_cr.v, cryp->base + STARFIVE_ALG_CR_OFFSET);
drivers/crypto/starfive/jh7110-aes.c
454
writel(ALIGN(len, AES_BLOCK_SIZE), cryp->base + STARFIVE_DMA_IN_LEN_OFFSET);
drivers/crypto/starfive/jh7110-aes.c
455
writel(ALIGN(len, AES_BLOCK_SIZE), cryp->base + STARFIVE_DMA_OUT_LEN_OFFSET);
drivers/crypto/starfive/jh7110-aes.c
494
writel(alg_cr.v, cryp->base + STARFIVE_ALG_CR_OFFSET);
drivers/crypto/starfive/jh7110-aes.c
95
writel(value, cryp->base + STARFIVE_AES_CSR);
drivers/crypto/starfive/jh7110-hash.c
101
writel(csr.v, cryp->base + STARFIVE_HASH_SHACSR);
drivers/crypto/starfive/jh7110-hash.c
134
writel(alg_cr.v, cryp->base + STARFIVE_ALG_CR_OFFSET);
drivers/crypto/starfive/jh7110-hash.c
136
writel(sg_dma_len(sg), cryp->base + STARFIVE_DMA_IN_LEN_OFFSET);
drivers/crypto/starfive/jh7110-hash.c
160
writel(alg_cr.v, cryp->base + STARFIVE_ALG_CR_OFFSET);
drivers/crypto/starfive/jh7110-hash.c
205
writel(STARFIVE_HASH_RESET, cryp->base + STARFIVE_HASH_SHACSR);
drivers/crypto/starfive/jh7110-hash.c
220
writel(rctx->csr.hash.v, cryp->base + STARFIVE_HASH_SHACSR);
drivers/crypto/starfive/jh7110-hash.c
72
writel(ctx->keylen, cryp->base + STARFIVE_HASH_SHAWKLEN);
drivers/crypto/starfive/jh7110-hash.c
77
writel(rctx->csr.hash.v, cryp->base + STARFIVE_HASH_SHACSR);
drivers/crypto/starfive/jh7110-hash.c
80
writel(*key, cryp->base + STARFIVE_HASH_SHAWKR);
drivers/crypto/starfive/jh7110-rsa.c
105
writel(in[opsize - loop], cryp->base + STARFIVE_PKA_CAAR_OFFSET + loop * 4);
drivers/crypto/starfive/jh7110-rsa.c
107
writel(0x1000000, cryp->base + STARFIVE_PKA_CAER_OFFSET);
drivers/crypto/starfive/jh7110-rsa.c
110
writel(0, cryp->base + STARFIVE_PKA_CAER_OFFSET + loop * 4);
drivers/crypto/starfive/jh7110-rsa.c
120
writel(rctx->csr.pka.v, cryp->base + STARFIVE_PKA_CACR_OFFSET);
drivers/crypto/starfive/jh7110-rsa.c
134
writel(rctx->csr.pka.v, cryp->base + STARFIVE_PKA_CACR_OFFSET);
drivers/crypto/starfive/jh7110-rsa.c
140
writel(in[count - loop], cryp->base + STARFIVE_PKA_CAER_OFFSET + loop * 4);
drivers/crypto/starfive/jh7110-rsa.c
144
writel(0, cryp->base + STARFIVE_PKA_CAER_OFFSET + loop * 4);
drivers/crypto/starfive/jh7110-rsa.c
154
writel(rctx->csr.pka.v, cryp->base + STARFIVE_PKA_CACR_OFFSET);
drivers/crypto/starfive/jh7110-rsa.c
193
writel(mta[opsize - loop],
drivers/crypto/starfive/jh7110-rsa.c
207
writel(rctx->csr.pka.v, cryp->base + STARFIVE_PKA_CACR_OFFSET);
drivers/crypto/starfive/jh7110-rsa.c
222
writel(rctx->csr.pka.v, cryp->base + STARFIVE_PKA_CACR_OFFSET);
drivers/crypto/starfive/jh7110-rsa.c
255
writel(STARFIVE_RSA_RESET, cryp->base + STARFIVE_PKA_CACR_OFFSET);
drivers/crypto/starfive/jh7110-rsa.c
282
writel(STARFIVE_RSA_RESET, cryp->base + STARFIVE_PKA_CACR_OFFSET);
drivers/crypto/starfive/jh7110-rsa.c
84
writel(rctx->csr.pka.v, cryp->base + STARFIVE_PKA_CACR_OFFSET);
drivers/crypto/starfive/jh7110-rsa.c
87
writel(mod[opsize - loop], cryp->base + STARFIVE_PKA_CANR_OFFSET + loop * 4);
drivers/crypto/starfive/jh7110-rsa.c
99
writel(rctx->csr.pka.v, cryp->base + STARFIVE_PKA_CACR_OFFSET);
drivers/crypto/tegra/tegra-se-aes.c
1060
writel(0, se->base + se->hw->regs->result + (i * 4));
drivers/crypto/tegra/tegra-se-aes.c
1189
writel(0, se->base + se->hw->regs->result + (i * 4));
drivers/crypto/tegra/tegra-se-aes.c
1537
writel(rctx->result[i],
drivers/crypto/tegra/tegra-se-aes.c
1565
writel(0, se->base + se->hw->regs->result + (i * 4));
drivers/crypto/tegra/tegra-se-aes.c
1694
writel(0, se->base + se->hw->regs->result + (i * 4));
drivers/crypto/tegra/tegra-se-main.c
309
writel(se->stream_id, se->base + SE_STREAM_ID);
drivers/cxl/core/hdm.c
1062
writel(ctrl, hdm + CXL_HDM_DECODER0_CTRL_OFFSET(which));
drivers/cxl/core/hdm.c
748
writel(ctrl, hdm + CXL_HDM_DECODER0_CTRL_OFFSET(id));
drivers/cxl/core/hdm.c
772
writel(upper_32_bits(base), hdm + CXL_HDM_DECODER0_BASE_HIGH_OFFSET(id));
drivers/cxl/core/hdm.c
773
writel(lower_32_bits(base), hdm + CXL_HDM_DECODER0_BASE_LOW_OFFSET(id));
drivers/cxl/core/hdm.c
774
writel(upper_32_bits(size), hdm + CXL_HDM_DECODER0_SIZE_HIGH_OFFSET(id));
drivers/cxl/core/hdm.c
775
writel(lower_32_bits(size), hdm + CXL_HDM_DECODER0_SIZE_LOW_OFFSET(id));
drivers/cxl/core/hdm.c
785
writel(upper_32_bits(targets), tl_hi);
drivers/cxl/core/hdm.c
786
writel(lower_32_bits(targets), tl_lo);
drivers/cxl/core/hdm.c
793
writel(upper_32_bits(cxled->skip), sk_hi);
drivers/cxl/core/hdm.c
794
writel(lower_32_bits(cxled->skip), sk_lo);
drivers/cxl/core/hdm.c
797
writel(ctrl, hdm + CXL_HDM_DECODER0_CTRL_OFFSET(id));
drivers/cxl/core/hdm.c
912
writel(ctrl, hdm + CXL_HDM_DECODER0_CTRL_OFFSET(id));
drivers/cxl/core/hdm.c
914
writel(0, hdm + CXL_HDM_DECODER0_SIZE_HIGH_OFFSET(id));
drivers/cxl/core/hdm.c
915
writel(0, hdm + CXL_HDM_DECODER0_SIZE_LOW_OFFSET(id));
drivers/cxl/core/hdm.c
916
writel(0, hdm + CXL_HDM_DECODER0_BASE_HIGH_OFFSET(id));
drivers/cxl/core/hdm.c
917
writel(0, hdm + CXL_HDM_DECODER0_BASE_LOW_OFFSET(id));
drivers/cxl/core/pci.c
246
writel(global_ctrl & ~CXL_HDM_DECODER_ENABLE,
drivers/cxl/core/pci.c
256
writel(global_ctrl | CXL_HDM_DECODER_ENABLE,
drivers/cxl/core/ras.c
197
writel(status & CXL_RAS_CORRECTABLE_STATUS_MASK, addr);
drivers/cxl/core/ras.c
251
writel(status & CXL_RAS_UNCORRECTABLE_STATUS_MASK, addr);
drivers/cxl/core/ras_rch.c
47
writel(aer_cmd, aer_base + PCI_ERR_ROOT_COMMAND);
drivers/cxl/core/ras_rch.c
72
writel(aer_regs->uncor_status, aer_base + PCI_ERR_UNCOR_STATUS);
drivers/cxl/core/ras_rch.c
73
writel(aer_regs->cor_status, aer_base + PCI_ERR_COR_STATUS);
drivers/cxl/pci.c
264
writel(CXLDEV_MBOX_CTRL_DOORBELL,
drivers/cxl/pci.c
463
writel(ctrl, cxlds->regs.mbox + CXLDEV_MBOX_CTRL_OFFSET);
drivers/cxl/port.c
104
writel(val, addr);
drivers/cxl/port.c
113
writel(val, addr);
drivers/devfreq/sun8i-a33-mbus.c
164
writel(mdfscr, priv->reg_mbus + MBUS_MDFSCR);
drivers/devfreq/sun8i-a33-mbus.c
169
writel(DRAM_RFSHTMG_TREFI(tREFI_32ck) | DRAM_RFSHTMG_TRFC(tRFC_ck),
drivers/devfreq/sun8i-a33-mbus.c
175
writel(priv->odtmap, priv->reg_dram + DRAM_ODTMAP);
drivers/devfreq/sun8i-a33-mbus.c
178
writel(0, priv->reg_dram + DRAM_ODTMAP);
drivers/devfreq/sun8i-a33-mbus.c
183
writel((readl(reg) & ~DRAM_DXnGCR0_DXODT) | dxodt, reg);
drivers/devfreq/sun8i-a33-mbus.c
192
writel(mdfscr | MBUS_MDFSCR_START, priv->reg_mbus + MBUS_MDFSCR);
drivers/devfreq/sun8i-a33-mbus.c
199
writel(0, priv->reg_mbus + MBUS_MDFSCR);
drivers/dma/amba-pl08x.c
2278
writel(PL080_CONFIG_ENABLE, pl08x->base + FTDMAC020_CSR);
drivers/dma/amba-pl08x.c
2281
writel(PL080_CONFIG_ENABLE, pl08x->base + PL080_CONFIG);
drivers/dma/amba-pl08x.c
2294
writel(err, pl08x->base + PL080_ERR_CLEAR);
drivers/dma/amba-pl08x.c
2298
writel(tc, pl08x->base + PL080_TC_CLEAR);
drivers/dma/amba-pl08x.c
2844
writel(0x0000FFFF, pl08x->base + PL080_ERR_CLEAR);
drivers/dma/amba-pl08x.c
2846
writel(0x000000FF, pl08x->base + PL080_ERR_CLEAR);
drivers/dma/amba-pl08x.c
2847
writel(0x000000FF, pl08x->base + PL080_TC_CLEAR);
drivers/dma/amba-pl08x.c
518
writel(ccfg, phychan->reg_config);
drivers/dma/amba-pl08x.c
560
writel(val | FTDMAC020_CH_CSR_EN,
drivers/dma/amba-pl08x.c
568
writel(val | PL080_CONFIG_ENABLE, phychan->reg_config);
drivers/dma/amba-pl08x.c
591
writel(val, ch->reg_control);
drivers/dma/amba-pl08x.c
598
writel(val, ch->reg_config);
drivers/dma/amba-pl08x.c
618
writel(val, ch->reg_control);
drivers/dma/amba-pl08x.c
625
writel(val, ch->reg_config);
drivers/dma/amba-pl08x.c
646
writel(val, ch->reg_config);
drivers/dma/amba-pl08x.c
652
writel(val, ch->reg_control);
drivers/dma/amba-pl08x.c
655
writel(BIT(ch->id) | BIT(ch->id + 16),
drivers/dma/amba-pl08x.c
657
writel(BIT(ch->id), pl08x->base + PL080_TC_CLEAR);
drivers/dma/amba-pl08x.c
665
writel(val, ch->reg_config);
drivers/dma/amba-pl08x.c
667
writel(BIT(ch->id), pl08x->base + PL080_ERR_CLEAR);
drivers/dma/amba-pl08x.c
668
writel(BIT(ch->id), pl08x->base + PL080_TC_CLEAR);
drivers/dma/amd/ae4dma/ae4dma-dev.c
130
writel(CMD_Q_LEN, cmd_q->reg_control + AE4_MAX_IDX_OFF);
drivers/dma/amd/ae4dma/ae4dma-dev.c
133
writel(lower_32_bits(cmd_q->qdma_tail), cmd_q->reg_control + AE4_Q_BASE_L_OFF);
drivers/dma/amd/ae4dma/ae4dma-dev.c
134
writel(upper_32_bits(cmd_q->qdma_tail), cmd_q->reg_control + AE4_Q_BASE_H_OFF);
drivers/dma/amd/ae4dma/ae4dma-dev.c
65
writel(status, cmd_q->reg_control + AE4_INTR_STS_OFF);
drivers/dma/amd/ae4dma/ae4dma-dev.c
97
writel(max_hw_q, pt->io_regs);
drivers/dma/amd/ptdma/ptdma-dmaengine.c
128
writel(ae4cmd_q->tail_wi, cmd_q->reg_control + AE4_WR_IDX_OFF);
drivers/dma/arm-dma350.c
450
writel(CH_CMD_ENABLE, dch->base + CH_CMD);
drivers/dma/bcm2835-dma.c
406
writel(0, chan_base + BCM2835_DMA_CS);
drivers/dma/bcm2835-dma.c
418
writel(BCM2835_DMA_RESET, chan_base + BCM2835_DMA_CS);
drivers/dma/bcm2835-dma.c
435
writel(d->cb_list[0].paddr, c->chan_base + BCM2835_DMA_ADDR);
drivers/dma/bcm2835-dma.c
436
writel(BCM2835_DMA_ACTIVE, c->chan_base + BCM2835_DMA_CS);
drivers/dma/bcm2835-dma.c
463
writel(BCM2835_DMA_INT | BCM2835_DMA_ACTIVE,
drivers/dma/dma-axi-dmac.c
196
writel(val, axi_dmac->base + reg);
drivers/dma/dma-jz4780.c
192
writel(val, jzdma->chn_base + reg + JZ_DMA_REG_CHAN(chn));
drivers/dma/dma-jz4780.c
204
writel(val, jzdma->ctrl_base + reg);
drivers/dma/dw-edma/dw-edma-v0-core.c
119
writel(viewport_sel,
drivers/dma/dw-edma/dw-edma-v0-core.c
121
writel(value, addr);
drivers/dma/dw-edma/dw-edma-v0-core.c
125
writel(value, addr);
drivers/dma/dw-edma/dw-edma-v0-core.c
144
writel(viewport_sel,
drivers/dma/dw-edma/dw-edma-v0-core.c
294
writel(control, &lli->control);
drivers/dma/dw-edma/dw-edma-v0-core.c
295
writel(size, &lli->transfer_size);
drivers/dma/dw-edma/dw-edma-v0-core.c
314
writel(control, &llp->control);
drivers/dma/dw-edma/dw-edma-v0-core.c
34
writel(value, &(__dw_regs(dw)->name))
drivers/dma/dw-edma/dw-edma-v0-core.c
84
writel(value, &(__dw_regs(dw)->type.unroll.name))
drivers/dma/dw-edma/dw-edma-v0-debugfs.c
87
writel(viewport_sel, REGS_ADDR(dw, type.legacy.viewport_sel));
drivers/dma/dw-edma/dw-hdma-v0-core.c
170
writel(control, &lli->control);
drivers/dma/dw-edma/dw-hdma-v0-core.c
171
writel(size, &lli->transfer_size);
drivers/dma/dw-edma/dw-hdma-v0-core.c
190
writel(control, &llp->control);
drivers/dma/dw-edma/dw-hdma-v0-core.c
41
writel(value, &(__dw_ch_regs(dw, dir, ch)->name))
drivers/dma/dw-edma/dw-hdma-v0-core.c
48
writel(value, &(__dw_ch_regs(dw, EDMA_DIR_WRITE, ch)->name)); \
drivers/dma/dw-edma/dw-hdma-v0-core.c
49
writel(value, &(__dw_ch_regs(dw, EDMA_DIR_READ, ch)->name)); \
drivers/dma/dw/idma32.c
109
writel(value, misc + DMA_XBAR_SEL(dwc->chan.chan_id));
drivers/dma/dw/idma32.c
60
writel(value, misc + DMA_REGACCESS_CHID_CFG);
drivers/dma/dw/idma32.c
88
writel(value, misc + DMA_CTL_CH(dwc->chan.chan_id));
drivers/dma/dw/regs.h
306
writel((val), &(__dwc_regs(dwc)->name))
drivers/dma/dw/regs.h
351
writel((val), &(__dw_regs(dw)->name))
drivers/dma/ep93xx_dma.c
371
writel(control, edmac->regs + M2P_CONTROL);
drivers/dma/ep93xx_dma.c
383
writel(edmac->dma_cfg.port & 0xf, edmac->regs + M2P_PPALLOC);
drivers/dma/ep93xx_dma.c
439
writel(desc->size, edmac->regs + M2P_MAXCNT0);
drivers/dma/ep93xx_dma.c
440
writel(bus_addr, edmac->regs + M2P_BASE0);
drivers/dma/ep93xx_dma.c
442
writel(desc->size, edmac->regs + M2P_MAXCNT1);
drivers/dma/ep93xx_dma.c
443
writel(bus_addr, edmac->regs + M2P_BASE1);
drivers/dma/ep93xx_dma.c
473
writel(1, edmac->regs + M2P_INTERRUPT);
drivers/dma/ep93xx_dma.c
524
writel(control, edmac->regs + M2M_CONTROL);
drivers/dma/ep93xx_dma.c
574
writel(control, edmac->regs + M2M_CONTROL);
drivers/dma/ep93xx_dma.c
581
writel(0, edmac->regs + M2M_CONTROL);
drivers/dma/ep93xx_dma.c
595
writel(desc->src_addr, edmac->regs + M2M_SAR_BASE0);
drivers/dma/ep93xx_dma.c
596
writel(desc->dst_addr, edmac->regs + M2M_DAR_BASE0);
drivers/dma/ep93xx_dma.c
597
writel(desc->size, edmac->regs + M2M_BCR0);
drivers/dma/ep93xx_dma.c
599
writel(desc->src_addr, edmac->regs + M2M_SAR_BASE1);
drivers/dma/ep93xx_dma.c
600
writel(desc->dst_addr, edmac->regs + M2M_DAR_BASE1);
drivers/dma/ep93xx_dma.c
601
writel(desc->size, edmac->regs + M2M_BCR1);
drivers/dma/ep93xx_dma.c
632
writel(control, edmac->regs + M2M_CONTROL);
drivers/dma/ep93xx_dma.c
640
writel(control, edmac->regs + M2M_CONTROL);
drivers/dma/ep93xx_dma.c
670
writel(0, edmac->regs + M2M_INTERRUPT);
drivers/dma/ep93xx_dma.c
700
writel(control, edmac->regs + M2M_CONTROL);
drivers/dma/ep93xx_dma.c
719
writel(control, edmac->regs + M2M_CONTROL);
drivers/dma/hsu/hsu.h
111
writel(value, hsuc->reg + offset);
drivers/dma/idma64.h
159
writel(value, idma64c->regs + offset);
drivers/dma/idma64.h
205
writel(value, idma64->regs + offset);
drivers/dma/img-mdc-dma.c
155
writel(val, mdma->regs + reg);
drivers/dma/imx-sdma.c
742
writel(BIT(channel), sdma->regs + SDMA_H_START);
drivers/dma/ioat/dca.c
140
writel(id | IOAT_DCA_GREQID_VALID,
drivers/dma/ioat/dca.c
166
writel(0, ioatdca->iobase + global_req_table + (i * 4));
drivers/dma/ioat/dma.c
1017
writel(chanerr, ioat_chan->reg_base + IOAT_CHANERR_OFFSET);
drivers/dma/ioat/dma.c
708
writel(lower_32_bits(ioat_chan->completion_dma),
drivers/dma/ioat/dma.c
710
writel(upper_32_bits(ioat_chan->completion_dma),
drivers/dma/ioat/dma.c
867
writel(chanerr, ioat_chan->reg_base + IOAT_CHANERR_OFFSET);
drivers/dma/ioat/dma.h
351
writel(addr & 0x00000000FFFFFFFF,
drivers/dma/ioat/dma.h
353
writel(addr >> 32,
drivers/dma/ioat/init.c
1070
writel(errmask, ioat_chan->reg_base +
drivers/dma/ioat/init.c
1169
writel(IOAT_DMA_DCA_ANY_CPU,
drivers/dma/ioat/init.c
1257
writel(chanerr, ioat_chan->reg_base + IOAT_CHANERR_OFFSET);
drivers/dma/ioat/init.c
691
writel(((u64)ioat_chan->completion_dma) & 0x00000000FFFFFFFF,
drivers/dma/ioat/init.c
693
writel(((u64)ioat_chan->completion_dma) >> 32,
drivers/dma/ioat/init.c
719
writel(lat_val, ioat_chan->reg_base +
drivers/dma/ioat/init.c
725
writel(lat_val, ioat_chan->reg_base +
drivers/dma/lgm/lgm-dma.c
1008
writel(c->nr, d->base + DMA_CS);
drivers/dma/lgm/lgm-dma.c
1009
writel(DMA_CI_EOP, d->base + DMA_CIE);
drivers/dma/lgm/lgm-dma.c
1010
writel(BIT(c->nr), d->base + DMA_IRNEN);
drivers/dma/lgm/lgm-dma.c
1107
writel(c->nr, d->base + DMA_CS);
drivers/dma/lgm/lgm-dma.c
1112
writel(readl(d->base + DMA_CIE) & ~DMA_CI_ALL, d->base + DMA_CIE);
drivers/dma/lgm/lgm-dma.c
1113
writel(stat, d->base + DMA_CIS);
drivers/dma/lgm/lgm-dma.c
1132
writel(readl(d->base + DMA_IRNEN) & ~BIT(cid), d->base + DMA_IRNEN);
drivers/dma/lgm/lgm-dma.c
1134
writel(readl(d->base + DMA_IRNCR) | BIT(cid), d->base + DMA_IRNCR);
drivers/dma/lgm/lgm-dma.c
287
writel(new_val, d->base + ofs);
drivers/dma/lgm/lgm-dma.c
542
writel(val, d->base + DMA_CCTRL);
drivers/dma/lgm/lgm-dma.c
568
writel(0, d->base + DMA_CIE);
drivers/dma/lgm/lgm-dma.c
569
writel(DMA_CI_ALL, d->base + DMA_CIS);
drivers/dma/lgm/lgm-dma.c
572
writel(cn_bit, d->base + crofs);
drivers/dma/lgm/lgm-dma.c
643
writel(lower_32_bits(desc_base), d->base + DMA_CDBA);
drivers/dma/lgm/lgm-dma.c
652
writel(desc_num, d->base + DMA_CDLEN);
drivers/dma/lgm/lgm-dma.c
850
writel(p->portid, d->base + DMA_PS);
drivers/dma/lgm/lgm-dma.c
851
writel(reg, d->base + DMA_PCTRL);
drivers/dma/loongson1-apb-dma.c
106
writel(val, chan->reg_base + LS1X_DMA_CTRL);
drivers/dma/loongson1-apb-dma.c
125
writel(val, chan->reg_base + LS1X_DMA_CTRL);
drivers/dma/loongson1-apb-dma.c
140
writel(val | LS1X_DMA_STOP, chan->reg_base + LS1X_DMA_CTRL);
drivers/dma/mediatek/mtk-hsdma.c
275
writel(val, hsdma->base + reg);
drivers/dma/mediatek/mtk-uart-apdma.c
123
writel(val, c->base + reg);
drivers/dma/milbeaut-xdmac.c
221
writel(val, mc->reg_ch_base + M10V_XDDES);
drivers/dma/milbeaut-xdmac.c
298
writel(val, mdev->reg_base + M10V_XDACS);
drivers/dma/milbeaut-xdmac.c
307
writel(val, mdev->reg_base + M10V_XDACS);
drivers/dma/mmp_pdma.c
201
writel(addr, phy->base + DDADR(phy->idx));
drivers/dma/mmp_pdma.c
242
writel(lower_32_bits(addr), phy->base + DDADR(phy->idx));
drivers/dma/mmp_pdma.c
243
writel(upper_32_bits(addr), phy->base + DDADRH(phy->idx));
drivers/dma/mmp_pdma.c
305
writel(DRCMR_MAPVLD | phy->idx, phy->base + reg);
drivers/dma/mmp_pdma.c
312
writel(dalgn, phy->base + DALGN);
drivers/dma/mmp_pdma.c
315
writel(readl(phy->base + reg) | pdev->ops->run_bits,
drivers/dma/mmp_pdma.c
333
writel(dcsr & ~pdev->ops->run_bits, phy->base + reg);
drivers/dma/mmp_pdma.c
336
writel(dcsr & ~DCSR_RUN, phy->base + reg);
drivers/dma/mmp_pdma.c
351
writel(dcsr, phy->base + reg);
drivers/dma/mmp_pdma.c
441
writel(0, pchan->phy->base + reg);
drivers/dma/mmp_tdma.c
145
writel(phys, tdmac->reg_base + TDNDPR);
drivers/dma/mmp_tdma.c
146
writel(readl(tdmac->reg_base + TDCR) | TDCR_FETCHND,
drivers/dma/mmp_tdma.c
153
writel(TDIMR_COMP, tdmac->reg_base + TDIMR);
drivers/dma/mmp_tdma.c
155
writel(0, tdmac->reg_base + TDIMR);
drivers/dma/mmp_tdma.c
161
writel(readl(tdmac->reg_base + TDCR) | TDCR_CHANEN,
drivers/dma/mmp_tdma.c
174
writel(tdcr, tdmac->reg_base + TDCR);
drivers/dma/mmp_tdma.c
185
writel(readl(tdmac->reg_base + TDCR) | TDCR_CHANEN,
drivers/dma/mmp_tdma.c
196
writel(readl(tdmac->reg_base + TDCR) & ~TDCR_CHANEN,
drivers/dma/mmp_tdma.c
284
writel(tdcr, tdmac->reg_base + TDCR);
drivers/dma/mmp_tdma.c
295
writel(reg, tdmac->reg_base + TDISR);
drivers/dma/moxart-dma.c
196
writel(ctrl, ch->base + REG_OFF_CTRL);
drivers/dma/moxart-dma.c
256
writel(ctrl, ch->base + REG_OFF_CTRL);
drivers/dma/moxart-dma.c
365
writel(src_addr, ch->base + REG_OFF_ADDRESS_SOURCE);
drivers/dma/moxart-dma.c
366
writel(dst_addr, ch->base + REG_OFF_ADDRESS_DEST);
drivers/dma/moxart-dma.c
380
writel(d->dma_cycles, ch->base + REG_OFF_CYCLES);
drivers/dma/moxart-dma.c
392
writel(ctrl, ch->base + REG_OFF_CTRL);
drivers/dma/moxart-dma.c
550
writel(ctrl, ch->base + REG_OFF_CTRL);
drivers/dma/mv_xor.c
1187
writel(0, base + WINDOW_BASE(i));
drivers/dma/mv_xor.c
1188
writel(0, base + WINDOW_SIZE(i));
drivers/dma/mv_xor.c
1190
writel(0, base + WINDOW_REMAP_HIGH(i));
drivers/dma/mv_xor.c
1196
writel((cs->base & 0xffff0000) |
drivers/dma/mv_xor.c
1199
writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
drivers/dma/mv_xor.c
1209
writel(win_enable, base + WINDOW_BAR_ENABLE(0));
drivers/dma/mv_xor.c
1210
writel(win_enable, base + WINDOW_BAR_ENABLE(1));
drivers/dma/mv_xor.c
1211
writel(0, base + WINDOW_OVERRIDE_CTRL(0));
drivers/dma/mv_xor.c
1212
writel(0, base + WINDOW_OVERRIDE_CTRL(1));
drivers/dma/mv_xor.c
1223
writel(0, base + WINDOW_BASE(i));
drivers/dma/mv_xor.c
1224
writel(0, base + WINDOW_SIZE(i));
drivers/dma/mv_xor.c
1226
writel(0, base + WINDOW_REMAP_HIGH(i));
drivers/dma/mv_xor.c
1232
writel(0xffff0000, base + WINDOW_SIZE(0));
drivers/dma/mv_xor.c
1236
writel(win_enable, base + WINDOW_BAR_ENABLE(0));
drivers/dma/mv_xor.c
1237
writel(win_enable, base + WINDOW_BAR_ENABLE(1));
drivers/dma/mv_xor.c
1238
writel(0, base + WINDOW_OVERRIDE_CTRL(0));
drivers/dma/mv_xor.c
1239
writel(0, base + WINDOW_OVERRIDE_CTRL(1));
drivers/dma/mv_xor.c
161
writel(BIT(0), XOR_ACTIVATION(chan));
drivers/dma/mv_xor.c
538
writel((addr & 0xffff0000) | (attr << 8) | target,
drivers/dma/mv_xor.c
540
writel(size & 0xffff0000, base + WINDOW_SIZE(i));
drivers/dma/mv_xor.c
548
writel(win_enable, base + WINDOW_BAR_ENABLE(0));
drivers/dma/mv_xor.c
549
writel(win_enable, base + WINDOW_BAR_ENABLE(1));
drivers/dma/mv_xor_v2.c
231
writel(num_of_desc, xor_dev->dma_base + MV_XOR_V2_DMA_DESQ_ADD_OFF);
drivers/dma/mv_xor_v2.c
241
writel(num_of_desc, xor_dev->dma_base + MV_XOR_V2_DMA_DESQ_DEALLOC_OFF);
drivers/dma/mv_xor_v2.c
250
writel(MV_XOR_V2_DMA_DESQ_CTRL_128B,
drivers/dma/mv_xor_v2.c
269
writel(reg, xor_dev->dma_base + MV_XOR_V2_DMA_IMSG_THRD_OFF);
drivers/dma/mv_xor_v2.c
275
writel(reg, xor_dev->dma_base + MV_XOR_V2_DMA_IMSG_TMOT);
drivers/dma/mv_xor_v2.c
622
writel(msg->address_lo,
drivers/dma/mv_xor_v2.c
624
writel(msg->address_hi & 0xFFFF,
drivers/dma/mv_xor_v2.c
626
writel(msg->data,
drivers/dma/mv_xor_v2.c
635
writel(MV_XOR_V2_DESC_NUM,
drivers/dma/mv_xor_v2.c
639
writel(lower_32_bits(xor_dev->hw_desq),
drivers/dma/mv_xor_v2.c
641
writel(upper_32_bits(xor_dev->hw_desq),
drivers/dma/mv_xor_v2.c
657
writel(reg, xor_dev->dma_base + MV_XOR_V2_DMA_DESQ_ARATTR_OFF);
drivers/dma/mv_xor_v2.c
663
writel(reg, xor_dev->dma_base + MV_XOR_V2_DMA_DESQ_AWATTR_OFF);
drivers/dma/mv_xor_v2.c
680
writel(reg, xor_dev->glob_base + MV_XOR_V2_GLOB_BW_CTRL);
drivers/dma/mv_xor_v2.c
685
writel(reg, xor_dev->glob_base + MV_XOR_V2_GLOB_PAUSE);
drivers/dma/mv_xor_v2.c
688
writel(0, xor_dev->dma_base + MV_XOR_V2_DMA_DESQ_STOP_OFF);
drivers/dma/mv_xor_v2.c
698
writel(0x1, xor_dev->dma_base + MV_XOR_V2_DMA_DESQ_STOP_OFF);
drivers/dma/mxs-dma.c
200
writel(1 << (chan_id + BP_APBH_CTRL0_RESET_CHANNEL),
drivers/dma/mxs-dma.c
225
writel(1 << (chan_id + BP_APBHX_CHANNEL_CTRL_RESET_CHANNEL),
drivers/dma/mxs-dma.c
239
writel(mxs_chan->ccw_phys,
drivers/dma/mxs-dma.c
248
writel(2, mxs_dma->base + HW_APBHX_CHn_SEMA(mxs_dma, chan_id));
drivers/dma/mxs-dma.c
250
writel(1, mxs_dma->base + HW_APBHX_CHn_SEMA(mxs_dma, chan_id));
drivers/dma/mxs-dma.c
270
writel(1 << chan_id,
drivers/dma/mxs-dma.c
273
writel(1 << chan_id,
drivers/dma/mxs-dma.c
288
writel(1 << chan_id,
drivers/dma/mxs-dma.c
291
writel(1 << chan_id,
drivers/dma/mxs-dma.c
337
writel((1 << chan),
drivers/dma/mxs-dma.c
352
writel((1 << chan),
drivers/dma/mxs-dma.c
376
writel(1, mxs_dma->base +
drivers/dma/mxs-dma.c
686
writel(BM_APBH_CTRL0_APB_BURST_EN,
drivers/dma/mxs-dma.c
688
writel(BM_APBH_CTRL0_APB_BURST8_EN,
drivers/dma/mxs-dma.c
693
writel(MXS_DMA_CHANNELS_MASK << MXS_DMA_CHANNELS,
drivers/dma/owl-dma.c
253
writel(regval, pchan->base + reg);
drivers/dma/owl-dma.c
258
writel(data, pchan->base + reg);
drivers/dma/owl-dma.c
277
writel(regval, od->base + reg);
drivers/dma/owl-dma.c
282
writel(data, od->base + reg);
drivers/dma/pch_dma.c
113
writel((val), (pdc)->membase + PDC_##name)
drivers/dma/pch_dma.c
135
writel((val), (pd)->membase + PCH_DMA_##name)
drivers/dma/pl330.c
1049
writel(readl(regs + INTEN) | (1 << thrd->ev), regs + INTEN);
drivers/dma/pl330.c
1692
writel(1 << ev, regs + INTCLR);
drivers/dma/pl330.c
907
writel(val, regs + DBGINST0);
drivers/dma/pl330.c
910
writel(val, regs + DBGINST1);
drivers/dma/pl330.c
913
writel(0, regs + DBGCMD);
drivers/dma/pl330.c
995
writel(1 << thrd->ev, regs + INTCLR);
drivers/dma/pl330.c
997
writel(inten & ~(1 << thrd->ev), regs + INTEN);
drivers/dma/plx_dma.c
207
writel(PLX_REG_CTRL_RESET_VAL | PLX_REG_CTRL_GRACEFUL_PAUSE,
drivers/dma/plx_dma.c
222
writel(PLX_REG_CTRL_RESET_VAL | PLX_REG_CTRL_GRACEFUL_PAUSE,
drivers/dma/plx_dma.c
225
writel(0, plxdev->bar + PLX_REG_DESC_RING_COUNT);
drivers/dma/plx_dma.c
226
writel(0, plxdev->bar + PLX_REG_DESC_RING_ADDR);
drivers/dma/plx_dma.c
227
writel(0, plxdev->bar + PLX_REG_DESC_RING_ADDR_HI);
drivers/dma/plx_dma.c
228
writel(0, plxdev->bar + PLX_REG_DESC_RING_NEXT_ADDR);
drivers/dma/plx_dma.c
429
writel(PLX_REG_CTRL_RESET_VAL, plxdev->bar + PLX_REG_CTRL);
drivers/dma/plx_dma.c
430
writel(lower_32_bits(plxdev->hw_ring_dma),
drivers/dma/plx_dma.c
432
writel(upper_32_bits(plxdev->hw_ring_dma),
drivers/dma/plx_dma.c
434
writel(lower_32_bits(plxdev->hw_ring_dma),
drivers/dma/plx_dma.c
436
writel(PLX_DMA_RING_COUNT, plxdev->bar + PLX_REG_DESC_RING_COUNT);
drivers/dma/plx_dma.c
437
writel(PLX_REG_PREF_LIMIT_PREF_FOUR, plxdev->bar + PLX_REG_PREF_LIMIT);
drivers/dma/pxa_dma.c
159
writel((val), (phy)->base + _reg((phy)->idx)); \
drivers/dma/qcom/hidma.c
679
writel(msg->address_lo, dmadev->dev_evca + 0x118);
drivers/dma/qcom/hidma.c
680
writel(msg->address_hi, dmadev->dev_evca + 0x11C);
drivers/dma/qcom/hidma.c
681
writel(msg->data, dmadev->dev_evca + 0x120);
drivers/dma/qcom/hidma_ll.c
294
writel(evre_read_off, lldev->evca + HIDMA_EVCA_DOORBELL_REG);
drivers/dma/qcom/hidma_ll.c
320
writel(val, lldev->trca + HIDMA_TRCA_CTRLSTS_REG);
drivers/dma/qcom/hidma_ll.c
337
writel(val, lldev->evca + HIDMA_EVCA_CTRLSTS_REG);
drivers/dma/qcom/hidma_ll.c
395
writel(cause, lldev->evca + HIDMA_EVCA_IRQ_CLR_REG);
drivers/dma/qcom/hidma_ll.c
466
writel(val, lldev->evca + HIDMA_EVCA_CTRLSTS_REG);
drivers/dma/qcom/hidma_ll.c
479
writel(val, lldev->trca + HIDMA_TRCA_CTRLSTS_REG);
drivers/dma/qcom/hidma_ll.c
493
writel(ENABLE_IRQS, lldev->evca + HIDMA_EVCA_IRQ_EN_REG);
drivers/dma/qcom/hidma_ll.c
503
writel(lldev->tre_write_offset, lldev->trca + HIDMA_TRCA_DOORBELL_REG);
drivers/dma/qcom/hidma_ll.c
563
writel(val, lldev->trca + HIDMA_TRCA_CTRLSTS_REG);
drivers/dma/qcom/hidma_ll.c
578
writel(val, lldev->evca + HIDMA_EVCA_CTRLSTS_REG);
drivers/dma/qcom/hidma_ll.c
594
writel(0, lldev->evca + HIDMA_EVCA_IRQ_EN_REG);
drivers/dma/qcom/hidma_ll.c
646
writel(0, lldev->evca + HIDMA_EVCA_IRQ_EN_REG);
drivers/dma/qcom/hidma_ll.c
650
writel(val, lldev->evca + HIDMA_EVCA_IRQ_CLR_REG);
drivers/dma/qcom/hidma_ll.c
661
writel(val, lldev->evca + HIDMA_EVCA_IRQ_CLR_REG);
drivers/dma/qcom/hidma_ll.c
664
writel(0, lldev->evca + HIDMA_EVCA_IRQ_EN_REG);
drivers/dma/qcom/hidma_ll.c
667
writel(lower_32_bits(addr), lldev->trca + HIDMA_TRCA_RING_LOW_REG);
drivers/dma/qcom/hidma_ll.c
668
writel(upper_32_bits(addr), lldev->trca + HIDMA_TRCA_RING_HIGH_REG);
drivers/dma/qcom/hidma_ll.c
669
writel(lldev->tre_ring_size, lldev->trca + HIDMA_TRCA_RING_LEN_REG);
drivers/dma/qcom/hidma_ll.c
672
writel(lower_32_bits(addr), lldev->evca + HIDMA_EVCA_RING_LOW_REG);
drivers/dma/qcom/hidma_ll.c
673
writel(upper_32_bits(addr), lldev->evca + HIDMA_EVCA_RING_HIGH_REG);
drivers/dma/qcom/hidma_ll.c
674
writel(HIDMA_EVRE_SIZE * nr_tres,
drivers/dma/qcom/hidma_ll.c
694
writel(0, lldev->evca + HIDMA_EVCA_IRQ_CLR_REG);
drivers/dma/qcom/hidma_ll.c
695
writel(0, lldev->evca + HIDMA_EVCA_IRQ_EN_REG);
drivers/dma/qcom/hidma_ll.c
702
writel(val, lldev->evca + HIDMA_EVCA_INTCTRL_REG);
drivers/dma/qcom/hidma_ll.c
705
writel(ENABLE_IRQS, lldev->evca + HIDMA_EVCA_IRQ_CLR_REG);
drivers/dma/qcom/hidma_ll.c
706
writel(ENABLE_IRQS, lldev->evca + HIDMA_EVCA_IRQ_EN_REG);
drivers/dma/qcom/hidma_ll.c
797
writel(ENABLE_IRQS, lldev->evca + HIDMA_EVCA_IRQ_EN_REG);
drivers/dma/qcom/hidma_ll.c
829
writel(val, lldev->evca + HIDMA_EVCA_IRQ_CLR_REG);
drivers/dma/qcom/hidma_ll.c
830
writel(0, lldev->evca + HIDMA_EVCA_IRQ_EN_REG);
drivers/dma/qcom/hidma_mgmt.c
122
writel(val, mgmtdev->virtaddr + HIDMA_MAX_BUS_REQ_LEN_OFFSET);
drivers/dma/qcom/hidma_mgmt.c
129
writel(val, mgmtdev->virtaddr + HIDMA_MAX_XACTIONS_OFFSET);
drivers/dma/qcom/hidma_mgmt.c
145
writel(val, mgmtdev->virtaddr + HIDMA_QOS_N_OFFSET + (4 * i));
drivers/dma/qcom/hidma_mgmt.c
151
writel(val, mgmtdev->virtaddr + HIDMA_CHRESET_TIMEOUT_OFFSET);
drivers/dma/qcom/hidma_mgmt.c
294
writel(val, mgmtdev->virtaddr + HIDMA_CFG_OFFSET);
drivers/dma/qcom/qcom_adm.c
535
writel(ADM_CH_CONF_SHADOW_EN |
drivers/dma/qcom/qcom_adm.c
541
writel(ADM_CH_RSLT_CONF_IRQ_EN | ADM_CH_RSLT_CONF_FLUSH_EN,
drivers/dma/qcom/qcom_adm.c
549
writel(async_desc->mux | async_desc->blk_size,
drivers/dma/qcom/qcom_adm.c
557
writel(ALIGN(async_desc->dma_addr, ADM_DESC_ALIGN) >> 3,
drivers/dma/qcom/qcom_adm.c
843
writel(ADM_CRCI_CTL_RST, adev->regs +
drivers/dma/qcom/qcom_adm.c
847
writel(ADM_CI_RANGE_START(0x40) | ADM_CI_RANGE_END(0xb0) |
drivers/dma/qcom/qcom_adm.c
849
writel(ADM_CI_RANGE_START(0x2a) | ADM_CI_RANGE_END(0x2c) |
drivers/dma/qcom/qcom_adm.c
851
writel(ADM_CI_RANGE_START(0x12) | ADM_CI_RANGE_END(0x28) |
drivers/dma/qcom/qcom_adm.c
853
writel(ADM_GP_CTL_LP_EN | ADM_GP_CTL_LP_CNT(0xf),
drivers/dma/qcom/qcom_adm.c
919
writel(0, adev->regs + ADM_CH_RSLT_CONF(achan->id, adev->ee));
drivers/dma/sa11x0-dma.c
1011
writel(DCSR_RUN | DCSR_IE, p->base + DMA_DCSR_C);
drivers/dma/sa11x0-dma.c
1032
writel(DCSR_STRTA | DCSR_STRTB, p->base + DMA_DCSR_C);
drivers/dma/sa11x0-dma.c
214
writel(dcsr, base + DMA_DCSR_S);
drivers/dma/sa11x0-dma.c
712
writel(DCSR_RUN | DCSR_IE, p->base + DMA_DCSR_C);
drivers/dma/sa11x0-dma.c
738
writel(DCSR_RUN | DCSR_IE, p->base + DMA_DCSR_S);
drivers/dma/sa11x0-dma.c
767
writel(DCSR_RUN | DCSR_IE |
drivers/dma/sf-pdma/sf-pdma.c
128
writel(PDMA_CLAIM_MASK, regs->ctrl);
drivers/dma/sf-pdma/sf-pdma.c
137
writel(readl(regs->ctrl) & ~PDMA_RUN_MASK, regs->ctrl);
drivers/dma/sf-pdma/sf-pdma.c
238
writel(v, regs->ctrl);
drivers/dma/sf-pdma/sf-pdma.c
264
writel(desc->xfer_type, regs->xfer_type);
drivers/dma/sf-pdma/sf-pdma.c
351
writel((readl(regs->ctrl)) & ~PDMA_DONE_STATUS_MASK, regs->ctrl);
drivers/dma/sf-pdma/sf-pdma.c
378
writel((readl(regs->ctrl)) & ~PDMA_ERR_STATUS_MASK, regs->ctrl);
drivers/dma/sf-pdma/sf-pdma.c
40
writel(lower_32_bits(v), addr);
drivers/dma/sf-pdma/sf-pdma.c
41
writel(upper_32_bits(v), addr + 4);
drivers/dma/sf-pdma/sf-pdma.c
489
writel(PDMA_CLEAR_CTRL, chan->regs.ctrl);
drivers/dma/sf-pdma/sf-pdma.c
81
writel(PDMA_CLEAR_CTRL, regs->ctrl);
drivers/dma/sh/rcar-dmac.c
317
writel(data, dmac->dmac_base + reg);
drivers/dma/sh/rcar-dmac.c
341
writel(data, chan->iomem + reg);
drivers/dma/sh/rz-dmac.c
190
writel(val, dmac->base + offset);
drivers/dma/sh/rz-dmac.c
196
writel(val, dmac->ext_base + offset);
drivers/dma/sh/rz-dmac.c
208
writel(val, channel->ch_base + offset);
drivers/dma/sh/rz-dmac.c
210
writel(val, channel->ch_cmn_base + offset);
drivers/dma/sh/usb-dmac.c
153
writel(data, dmac->iomem + reg);
drivers/dma/sh/usb-dmac.c
168
writel(data, chan->iomem + reg);
drivers/dma/sprd-dma.c
248
writel(tmp, sdev->glb_base + reg);
drivers/dma/sprd-dma.c
258
writel(tmp, schan->chn_base + reg);
drivers/dma/sprd-dma.c
299
writel(schan->chn_num + 1, sdev->glb_base + uid_offset);
drivers/dma/sprd-dma.c
312
writel(0, sdev->glb_base + uid_offset);
drivers/dma/sprd-dma.c
516
writel(cfg->pause, schan->chn_base + SPRD_DMA_CHN_PAUSE);
drivers/dma/sprd-dma.c
517
writel(cfg->cfg, schan->chn_base + SPRD_DMA_CHN_CFG);
drivers/dma/sprd-dma.c
518
writel(cfg->intc, schan->chn_base + SPRD_DMA_CHN_INTC);
drivers/dma/sprd-dma.c
519
writel(cfg->src_addr, schan->chn_base + SPRD_DMA_CHN_SRC_ADDR);
drivers/dma/sprd-dma.c
520
writel(cfg->des_addr, schan->chn_base + SPRD_DMA_CHN_DES_ADDR);
drivers/dma/sprd-dma.c
521
writel(cfg->frg_len, schan->chn_base + SPRD_DMA_CHN_FRG_LEN);
drivers/dma/sprd-dma.c
522
writel(cfg->blk_len, schan->chn_base + SPRD_DMA_CHN_BLK_LEN);
drivers/dma/sprd-dma.c
523
writel(cfg->trsc_len, schan->chn_base + SPRD_DMA_CHN_TRSC_LEN);
drivers/dma/sprd-dma.c
524
writel(cfg->trsf_step, schan->chn_base + SPRD_DMA_CHN_TRSF_STEP);
drivers/dma/sprd-dma.c
525
writel(cfg->wrap_ptr, schan->chn_base + SPRD_DMA_CHN_WARP_PTR);
drivers/dma/sprd-dma.c
526
writel(cfg->wrap_to, schan->chn_base + SPRD_DMA_CHN_WARP_TO);
drivers/dma/sprd-dma.c
527
writel(cfg->llist_ptr, schan->chn_base + SPRD_DMA_CHN_LLIST_PTR);
drivers/dma/sprd-dma.c
528
writel(cfg->frg_step, schan->chn_base + SPRD_DMA_CHN_FRAG_STEP);
drivers/dma/sprd-dma.c
529
writel(cfg->src_blk_step, schan->chn_base + SPRD_DMA_CHN_SRC_BLK_STEP);
drivers/dma/sprd-dma.c
530
writel(cfg->des_blk_step, schan->chn_base + SPRD_DMA_CHN_DES_BLK_STEP);
drivers/dma/sprd-dma.c
531
writel(cfg->req, schan->chn_base + SPRD_DMA_CHN_REQ);
drivers/dma/st_fdma.c
92
writel(cmd,
drivers/dma/st_fdma.h
170
writel((val), (fdev)->slim_rproc->peri + name)
drivers/dma/st_fdma.h
190
writel((val), (fchan)->fdev->slim_rproc->mem[ST_SLIM_DMEM].cpu_addr \
drivers/dma/st_fdma.h
197
writel((val), (fchan)->fdev->slim_rproc->mem[ST_SLIM_DMEM].cpu_addr \
drivers/dma/st_fdma.h
212
writel((val), (fchan)->fdev->slim_rproc->mem[ST_SLIM_DMEM].cpu_addr \
drivers/dma/ste_dma40.c
1094
writel(wmask | (command << D40_CHAN_POS(d40c->phy_chan->num)),
drivers/dma/ste_dma40.c
1190
writel((D40_DEACTIVATE_EVENTLINE << D40_EVENTLINE_POS(event))
drivers/dma/ste_dma40.c
1202
writel((D40_SUSPEND_REQ_EVENTLINE << D40_EVENTLINE_POS(event))
drivers/dma/ste_dma40.c
1237
writel((D40_ACTIVATE_EVENTLINE <<
drivers/dma/ste_dma40.c
1381
writel(var, d40c->base->virtbase + D40_DREG_PRMSE + addr_base);
drivers/dma/ste_dma40.c
1386
writel(var, d40c->base->virtbase + D40_DREG_PRMOE + addr_base);
drivers/dma/ste_dma40.c
1394
writel(d40c->src_def_cfg, chanbase + D40_CHAN_REG_SSCFG);
drivers/dma/ste_dma40.c
1395
writel(d40c->dst_def_cfg, chanbase + D40_CHAN_REG_SDCFG);
drivers/dma/ste_dma40.c
1398
writel(lidx, chanbase + D40_CHAN_REG_SSELT);
drivers/dma/ste_dma40.c
1399
writel(lidx, chanbase + D40_CHAN_REG_SDELT);
drivers/dma/ste_dma40.c
1402
writel(0, chanbase + D40_CHAN_REG_SSLNK);
drivers/dma/ste_dma40.c
1403
writel(0, chanbase + D40_CHAN_REG_SDLNK);
drivers/dma/ste_dma40.c
1703
writel(BIT(idx), base->virtbase + il[row].clr);
drivers/dma/ste_dma40.c
2337
writel(bit, d40c->base->virtbase + prioreg + group * 4);
drivers/dma/ste_dma40.c
2338
writel(bit, d40c->base->virtbase + rtreg + group * 4);
drivers/dma/ste_dma40.c
3109
writel(D40_DREG_GCC_ENABLE_ALL, base->virtbase + D40_DREG_GCC);
drivers/dma/ste_dma40.c
3314
writel(dma_init_reg[i].val,
drivers/dma/ste_dma40.c
3340
writel(prmseo[1], base->virtbase + D40_DREG_PRMSE);
drivers/dma/ste_dma40.c
3341
writel(prmseo[0], base->virtbase + D40_DREG_PRMSO);
drivers/dma/ste_dma40.c
3342
writel(activeo[1], base->virtbase + D40_DREG_ACTIVE);
drivers/dma/ste_dma40.c
3343
writel(activeo[0], base->virtbase + D40_DREG_ACTIVO);
drivers/dma/ste_dma40.c
3346
writel(pcmis, base->virtbase + base->gen_dmac.interrupt_en);
drivers/dma/ste_dma40.c
3349
writel(pcicr, base->virtbase + base->gen_dmac.interrupt_clear);
drivers/dma/ste_dma40.c
3431
writel(virt_to_phys(base->lcla_pool.base),
drivers/dma/ste_dma40.c
3543
writel(base->phy_lcpa, base->virtbase + D40_DREG_LCPA);
drivers/dma/ste_dma40.c
3568
writel(res->start, base->virtbase + D40_DREG_LCLA);
drivers/dma/ste_dma40.c
835
writel(lli_src->reg_cfg, base + D40_CHAN_REG_SSCFG);
drivers/dma/ste_dma40.c
836
writel(lli_src->reg_elt, base + D40_CHAN_REG_SSELT);
drivers/dma/ste_dma40.c
837
writel(lli_src->reg_ptr, base + D40_CHAN_REG_SSPTR);
drivers/dma/ste_dma40.c
838
writel(lli_src->reg_lnk, base + D40_CHAN_REG_SSLNK);
drivers/dma/ste_dma40.c
840
writel(lli_dst->reg_cfg, base + D40_CHAN_REG_SDCFG);
drivers/dma/ste_dma40.c
841
writel(lli_dst->reg_elt, base + D40_CHAN_REG_SDELT);
drivers/dma/ste_dma40.c
842
writel(lli_dst->reg_ptr, base + D40_CHAN_REG_SDPTR);
drivers/dma/ste_dma40.c
843
writel(lli_dst->reg_lnk, base + D40_CHAN_REG_SDLNK);
drivers/dma/sun4i-dma.c
1334
writel(0, priv->base + SUN4I_DMA_IRQ_ENABLE_REG);
drivers/dma/sun4i-dma.c
1335
writel(0xFFFFFFFF, priv->base + SUN4I_DMA_IRQ_PENDING_STATUS_REG);
drivers/dma/sun4i-dma.c
992
writel(0, pchan->base + SUN4I_DDMA_CFG_REG);
drivers/dma/sun4i-dma.c
994
writel(0, pchan->base + SUN4I_NDMA_CFG_REG);
drivers/dma/sun6i-dma.c
1079
writel(0, sdev->base + DMA_IRQ_EN(0));
drivers/dma/sun6i-dma.c
1080
writel(0, sdev->base + DMA_IRQ_EN(1));
drivers/dma/sun6i-dma.c
306
writel(SUN8I_DMA_GATE_ENABLE, sdev->base + SUN8I_DMA_GATE);
drivers/dma/sun6i-dma.c
311
writel(SUNXI_H3_DMA_GATE_ENABLE, sdev->base + SUNXI_H3_DMA_GATE);
drivers/dma/sun6i-dma.c
467
writel(irq_val, sdev->base + DMA_IRQ_EN(irq_reg));
drivers/dma/sun6i-dma.c
469
writel(pchan->desc->p_lli, pchan->base + DMA_CHAN_LLI_ADDR);
drivers/dma/sun6i-dma.c
470
writel(DMA_CHAN_ENABLE_START, pchan->base + DMA_CHAN_ENABLE);
drivers/dma/sun6i-dma.c
559
writel(status, sdev->base + DMA_IRQ_STAT(i));
drivers/dma/sun6i-dma.c
898
writel(DMA_CHAN_PAUSE_PAUSE,
drivers/dma/sun6i-dma.c
921
writel(DMA_CHAN_PAUSE_RESUME,
drivers/dma/sun6i-dma.c
961
writel(DMA_CHAN_ENABLE_STOP, pchan->base + DMA_CHAN_ENABLE);
drivers/dma/sun6i-dma.c
962
writel(DMA_CHAN_PAUSE_RESUME, pchan->base + DMA_CHAN_PAUSE);
drivers/dma/tegra20-apb-dma.c
232
writel(val, tdma->base_addr + reg);
drivers/dma/tegra20-apb-dma.c
238
writel(val, tdc->chan_addr + reg);
drivers/dma/tegra210-adma.c
209
writel(val, tdma->base_addr + tdma->cdata->global_reg_offset + reg);
drivers/dma/tegra210-adma.c
219
writel(val, tdma->ch_base_addr + tdma->cdata->global_reg_offset + reg);
drivers/dma/tegra210-adma.c
224
writel(val, tdc->chan_addr + reg);
drivers/dma/ti/edma.c
2126
writel(mux, (xbar + offset));
drivers/dma/ti/k3-udma.c
340
writel(val, base + reg);
drivers/dma/ti/k3-udma.c
353
writel(tmp, base + reg);
drivers/dma/uniphier-mdmac.c
130
writel(src_mode, mc->reg_ch_base + UNIPHIER_MDMAC_CH_SRC_MODE);
drivers/dma/uniphier-mdmac.c
131
writel(dest_mode, mc->reg_ch_base + UNIPHIER_MDMAC_CH_DEST_MODE);
drivers/dma/uniphier-mdmac.c
132
writel(src_addr, mc->reg_ch_base + UNIPHIER_MDMAC_CH_SRC_ADDR);
drivers/dma/uniphier-mdmac.c
133
writel(dest_addr, mc->reg_ch_base + UNIPHIER_MDMAC_CH_DEST_ADDR);
drivers/dma/uniphier-mdmac.c
134
writel(chunk_size, mc->reg_ch_base + UNIPHIER_MDMAC_CH_SIZE);
drivers/dma/uniphier-mdmac.c
137
writel(irq_flag, mc->reg_ch_base + UNIPHIER_MDMAC_CH_IRQ_REQ);
drivers/dma/uniphier-mdmac.c
139
writel(irq_flag, mc->reg_ch_base + UNIPHIER_MDMAC_CH_IRQ_EN);
drivers/dma/uniphier-mdmac.c
141
writel(BIT(mc->chan_id), mdev->reg_base + UNIPHIER_MDMAC_CMD);
drivers/dma/uniphier-mdmac.c
162
writel(irq_flag, mc->reg_ch_base + UNIPHIER_MDMAC_CH_IRQ_REQ);
drivers/dma/uniphier-mdmac.c
164
writel(UNIPHIER_MDMAC_CMD_ABORT | BIT(mc->chan_id),
drivers/dma/uniphier-mdmac.c
196
writel(irq_stat, mc->reg_ch_base + UNIPHIER_MDMAC_CH_IRQ_REQ);
drivers/dma/uniphier-xdmac.c
170
writel(val, xc->reg_ch_base + XDMAC_TFA);
drivers/dma/uniphier-xdmac.c
173
writel(lower_32_bits(src_addr), xc->reg_ch_base + XDMAC_SAD);
drivers/dma/uniphier-xdmac.c
174
writel(upper_32_bits(src_addr), xc->reg_ch_base + XDMAC_EXSAD);
drivers/dma/uniphier-xdmac.c
176
writel(lower_32_bits(dst_addr), xc->reg_ch_base + XDMAC_DAD);
drivers/dma/uniphier-xdmac.c
177
writel(upper_32_bits(dst_addr), xc->reg_ch_base + XDMAC_EXDAD);
drivers/dma/uniphier-xdmac.c
181
writel(src_mode, xc->reg_ch_base + XDMAC_SADM);
drivers/dma/uniphier-xdmac.c
182
writel(dst_mode, xc->reg_ch_base + XDMAC_DADM);
drivers/dma/uniphier-xdmac.c
184
writel(its, xc->reg_ch_base + XDMAC_ITS);
drivers/dma/uniphier-xdmac.c
185
writel(tnum, xc->reg_ch_base + XDMAC_TNUM);
drivers/dma/uniphier-xdmac.c
188
writel(XDMAC_IEN_ENDIEN | XDMAC_IEN_ERRIEN,
drivers/dma/uniphier-xdmac.c
194
writel(val, xc->reg_ch_base + XDMAC_TSS);
drivers/dma/uniphier-xdmac.c
205
writel(val, xc->reg_ch_base + XDMAC_IEN);
drivers/dma/uniphier-xdmac.c
210
writel(0, xc->reg_ch_base + XDMAC_TSS);
drivers/dma/uniphier-xdmac.c
259
writel(stat, xc->reg_ch_base + XDMAC_IR);
drivers/dma/xilinx/xilinx_dma.c
591
writel(value_lsb, chan->xdev->regs + chan->desc_offset + reg);
drivers/dma/xilinx/xilinx_dma.c
594
writel(value_msb, chan->xdev->regs + chan->desc_offset + reg + 4);
drivers/dma/xilinx/zynqmp_dma.c
349
writel(ZYNQMP_DMA_IDS_DEFAULT_MASK, chan->regs + ZYNQMP_DMA_IDS);
drivers/dma/xilinx/zynqmp_dma.c
351
writel(val, chan->regs + ZYNQMP_DMA_ISR);
drivers/dma/xilinx/zynqmp_dma.c
357
writel(val, chan->regs + ZYNQMP_DMA_DSCR_ATTR);
drivers/dma/xilinx/zynqmp_dma.c
367
writel(val, chan->regs + ZYNQMP_DMA_DATA_ATTR);
drivers/dma/xilinx/zynqmp_dma.c
527
writel(ZYNQMP_DMA_INT_EN_DEFAULT_MASK, chan->regs + ZYNQMP_DMA_IER);
drivers/dma/xilinx/zynqmp_dma.c
528
writel(0, chan->regs + ZYNQMP_DMA_TOTAL_BYTE);
drivers/dma/xilinx/zynqmp_dma.c
530
writel(ZYNQMP_DMA_ENABLE, chan->regs + ZYNQMP_DMA_CTRL2);
drivers/dma/xilinx/zynqmp_dma.c
541
writel(0, chan->regs + ZYNQMP_DMA_TOTAL_BYTE);
drivers/dma/xilinx/zynqmp_dma.c
554
writel(val, chan->regs + ZYNQMP_DMA_CTRL0);
drivers/dma/xilinx/zynqmp_dma.c
563
writel(val, chan->regs + ZYNQMP_DMA_DATA_ATTR);
drivers/dma/xilinx/zynqmp_dma.c
708
writel(ZYNQMP_DMA_IDS_DEFAULT_MASK, chan->regs + ZYNQMP_DMA_IDS);
drivers/dma/xilinx/zynqmp_dma.c
736
writel(isr, chan->regs + ZYNQMP_DMA_ISR);
drivers/dma/xilinx/zynqmp_dma.c
804
writel(ZYNQMP_DMA_IDS_DEFAULT_MASK, chan->regs + ZYNQMP_DMA_IDS);
drivers/edac/altera_edac.c
1010
writel(ALTR_A10_ECC_SERRINTEN,
drivers/edac/altera_edac.c
1205
writel(ALTR_A10_ECC_SERRINTEN, (base + ALTR_A10_ECC_ERRINTENS_OFST));
drivers/edac/altera_edac.c
1656
writel(priv->ce_clear_mask,
drivers/edac/altera_edac.c
1661
writel(priv->ue_clear_mask,
drivers/edac/altera_edac.c
1793
writel(ECC_WORD_WRITE, drvdata->base + ECC_BLK_DBYTECTRL_OFST);
drivers/edac/altera_edac.c
1795
writel(0, drvdata->base + ECC_BLK_ADDRESS_OFST);
drivers/edac/altera_edac.c
1797
writel(ECC_READ_EDOVR, drvdata->base + ECC_BLK_ACCCTRL_OFST);
drivers/edac/altera_edac.c
1799
writel(ECC_XACT_KICK, drvdata->base + ECC_BLK_STARTACC_OFST);
drivers/edac/altera_edac.c
1801
writel(readl(drvdata->base + ECC_BLK_RDATA0_OFST) ^ 0x1,
drivers/edac/altera_edac.c
1803
writel(readl(drvdata->base + ECC_BLK_RDATA1_OFST),
drivers/edac/altera_edac.c
1805
writel(readl(drvdata->base + ECC_BLK_RDATA2_OFST),
drivers/edac/altera_edac.c
1807
writel(readl(drvdata->base + ECC_BLK_RDATA3_OFST),
drivers/edac/altera_edac.c
1811
writel(readl(drvdata->base + ECC_BLK_RECC0_OFST),
drivers/edac/altera_edac.c
1813
writel(readl(drvdata->base + ECC_BLK_RECC1_OFST),
drivers/edac/altera_edac.c
1816
writel(ECC_WRITE_EDOVR, drvdata->base + ECC_BLK_ACCCTRL_OFST);
drivers/edac/altera_edac.c
1818
writel(ECC_XACT_KICK, drvdata->base + ECC_BLK_STARTACC_OFST);
drivers/edac/altera_edac.c
1820
writel(ECC_READ_EDOVR, drvdata->base + ECC_BLK_ACCCTRL_OFST);
drivers/edac/altera_edac.c
1822
writel(ECC_XACT_KICK, drvdata->base + ECC_BLK_STARTACC_OFST);
drivers/edac/altera_edac.c
2091
writel(ALTR_A10_ECC_DERRPENA,
drivers/edac/altera_edac.c
556
writel(priv->ce_clear_mask, drvdata->base);
drivers/edac/altera_edac.c
561
writel(priv->ue_clear_mask, drvdata->base);
drivers/edac/altera_edac.c
619
writel(error_mask, (drvdata->base + priv->set_err_ofst));
drivers/edac/altera_edac.c
620
writel(priv->ecc_enable_mask, (drvdata->base +
drivers/edac/altera_edac.c
855
writel(ALTR_A10_ECC_SERRPENA,
drivers/edac/altera_edac.c
861
writel(ALTR_A10_ECC_DERRPENA,
drivers/edac/altera_edac.c
893
writel(value, ioaddr);
drivers/edac/altera_edac.c
901
writel(value, ioaddr);
drivers/edac/altera_edac.c
942
writel(clear_mask, (ioaddr + ALTR_A10_ECC_INTSTAT_OFST));
drivers/edac/altera_edac.c
983
writel(ALTR_A10_ECC_SERRINTEN,
drivers/edac/armada_xp_edac.c
147
writel(~(SDRAM_ERR_CAUSE_DBE_MASK | SDRAM_ERR_CAUSE_SBE_MASK),
drivers/edac/armada_xp_edac.c
149
writel(~(SDRAM_ERR_CAUSE_DBE_MASK | SDRAM_ERR_CAUSE_SBE_MASK),
drivers/edac/armada_xp_edac.c
154
writel(0, drvdata->base + SDRAM_ERR_SBE_COUNT_REG);
drivers/edac/armada_xp_edac.c
156
writel(0, drvdata->base + SDRAM_ERR_DBE_COUNT_REG);
drivers/edac/armada_xp_edac.c
337
writel(1 << SDRAM_ERR_CTRL_THR_OFFSET, drvdata->base + SDRAM_ERR_CTRL_REG);
drivers/edac/armada_xp_edac.c
340
writel(~(SDRAM_ERR_CAUSE_DBE_MASK | SDRAM_ERR_CAUSE_SBE_MASK), drvdata->base + SDRAM_ERR_CAUSE_ERR_REG);
drivers/edac/armada_xp_edac.c
341
writel(~(SDRAM_ERR_CAUSE_DBE_MASK | SDRAM_ERR_CAUSE_SBE_MASK), drvdata->base + SDRAM_ERR_CAUSE_MSG_REG);
drivers/edac/armada_xp_edac.c
344
writel(0, drvdata->base + SDRAM_ERR_SBE_COUNT_REG);
drivers/edac/armada_xp_edac.c
345
writel(0, drvdata->base + SDRAM_ERR_DBE_COUNT_REG);
drivers/edac/armada_xp_edac.c
394
writel(0, drvdata->base + AURORA_ERR_INJECT_CTL_REG);
drivers/edac/armada_xp_edac.c
395
writel(drvdata->inject_mask, drvdata->base + AURORA_ERR_INJECT_MASK_REG);
drivers/edac/armada_xp_edac.c
396
writel(drvdata->inject_addr | drvdata->inject_ctl, drvdata->base + AURORA_ERR_INJECT_CTL_REG);
drivers/edac/armada_xp_edac.c
418
writel(AURORA_ERR_CNT_CLR, drvdata->base + AURORA_ERR_CNT_REG);
drivers/edac/armada_xp_edac.c
467
writel(AURORA_ERR_ATTR_CAP_VALID, drvdata->base + AURORA_ERR_ATTR_CAP_REG);
drivers/edac/armada_xp_edac.c
542
writel(AURORA_ERR_CNT_CLR, drvdata->base + AURORA_ERR_CNT_REG);
drivers/edac/armada_xp_edac.c
543
writel(AURORA_ERR_ATTR_CAP_VALID, drvdata->base + AURORA_ERR_ATTR_CAP_REG);
drivers/edac/aspeed_edac.c
46
writel(ASPEED_MCR_PROT_PASSWD, regs + ASPEED_MCR_PROT);
drivers/edac/aspeed_edac.c
48
writel(val, regs + reg);
drivers/edac/aspeed_edac.c
51
writel(~ASPEED_MCR_PROT_PASSWD, regs + ASPEED_MCR_PROT);
drivers/edac/bluefield_edac.c
164
writel(data, addr);
drivers/edac/dmc520_edac.c
185
writel(val, pvt->reg_base + offset);
drivers/edac/highbank_l2_edac.c
31
writel(1, drvdata->base + SR_CLR_SB_ECC_INTR);
drivers/edac/highbank_l2_edac.c
35
writel(1, drvdata->base + SR_CLR_DB_ECC_INTR);
drivers/edac/highbank_mc_edac.c
83
writel(status, drvdata->mc_int_base + HB_DDR_ECC_INT_ACK);
drivers/edac/highbank_mc_edac.c
95
writel(reg, pdata->mc_err_base + HB_DDR_ECC_OPT);
drivers/edac/i10nm_base.c
55
writel(v, (m)->mbase + (i) * (m)->chan_mmio_sz + (offset))
drivers/edac/synopsys_edac.c
1046
writel(regval, priv->baseaddr + ECC_POISON0_OFST);
drivers/edac/synopsys_edac.c
1051
writel(regval, priv->baseaddr + ECC_POISON1_OFST);
drivers/edac/synopsys_edac.c
1102
writel(0, priv->baseaddr + DDRC_SWCTL);
drivers/edac/synopsys_edac.c
1104
writel(ECC_CEPOISON_MASK, priv->baseaddr + ECC_CFG1_OFST);
drivers/edac/synopsys_edac.c
1106
writel(ECC_UEPOISON_MASK, priv->baseaddr + ECC_CFG1_OFST);
drivers/edac/synopsys_edac.c
1107
writel(1, priv->baseaddr + DDRC_SWCTL);
drivers/edac/synopsys_edac.c
1447
writel(0x0, baseaddr + ECC_CTRL_OFST);
drivers/edac/synopsys_edac.c
410
writel(clearval, base + ECC_CTRL_OFST);
drivers/edac/synopsys_edac.c
411
writel(0x0, base + ECC_CTRL_OFST);
drivers/edac/synopsys_edac.c
494
writel(clearval, base + ECC_CLR_OFST);
drivers/edac/synopsys_edac.c
560
writel(DDR_QOSUE_MASK | DDR_QOSCE_MASK,
drivers/edac/synopsys_edac.c
568
writel(DDR_UE_MASK | DDR_CE_MASK,
drivers/edac/synopsys_edac.c
580
writel(DDR_QOSUE_MASK | DDR_QOSCE_MASK,
drivers/edac/synopsys_edac.c
588
writel(0, priv->baseaddr + ECC_CLR_OFST);
drivers/edac/synopsys_edac.c
633
writel(regval, priv->baseaddr + DDR_QOS_IRQ_STAT_OFST);
drivers/edac/synopsys_edac.c
742
writel(clearval, priv->baseaddr + ECC_CTRL_OFST);
drivers/edac/synopsys_edac.c
743
writel(0x0, priv->baseaddr + ECC_CTRL_OFST);
drivers/edac/synopsys_edac.c
757
writel(clearval, priv->baseaddr + ECC_CLR_OFST);
drivers/edac/versal_edac.c
345
writel(PCSR_UNLOCK_VAL, ddrmc_base + XDDR_PCSR_OFFSET);
drivers/edac/versal_edac.c
347
writel(0, ddrmc_base + ECCR0_CERR_STAT_OFFSET);
drivers/edac/versal_edac.c
348
writel(0, ddrmc_base + ECCR1_CERR_STAT_OFFSET);
drivers/edac/versal_edac.c
349
writel(0, ddrmc_base + ECCR0_UERR_STAT_OFFSET);
drivers/edac/versal_edac.c
350
writel(0, ddrmc_base + ECCR1_UERR_STAT_OFFSET);
drivers/edac/versal_edac.c
353
writel(1, ddrmc_base + XDDR_PCSR_OFFSET);
drivers/edac/versal_edac.c
478
writel(PCSR_UNLOCK_VAL, priv->ddrmc_baseaddr + XDDR_PCSR_OFFSET);
drivers/edac/versal_edac.c
481
writel(regval, priv->ddrmc_baseaddr + XDDR_ISR_OFFSET);
drivers/edac/versal_edac.c
484
writel(PCSR_LOCK_VAL, priv->ddrmc_baseaddr + XDDR_PCSR_OFFSET);
drivers/edac/versal_edac.c
646
writel(PCSR_UNLOCK_VAL, priv->ddrmc_baseaddr + XDDR_PCSR_OFFSET);
drivers/edac/versal_edac.c
649
writel(XDDR_IRQ_CE_MASK | XDDR_IRQ_UE_MASK,
drivers/edac/versal_edac.c
652
writel(XDDR_IRQ_UE_MASK,
drivers/edac/versal_edac.c
655
writel(PCSR_LOCK_VAL, priv->ddrmc_baseaddr + XDDR_PCSR_OFFSET);
drivers/edac/versal_edac.c
661
writel(PCSR_UNLOCK_VAL, priv->ddrmc_baseaddr + XDDR_PCSR_OFFSET);
drivers/edac/versal_edac.c
664
writel(XDDR_IRQ_CE_MASK | XDDR_IRQ_UE_MASK,
drivers/edac/versal_edac.c
668
writel(PCSR_LOCK_VAL, priv->ddrmc_baseaddr + XDDR_PCSR_OFFSET);
drivers/edac/versal_edac.c
719
writel(0xFF, priv->ddrmc_baseaddr + ECCW1_FLIP_CTRL);
drivers/edac/versal_edac.c
721
writel(0xFF, priv->ddrmc_baseaddr + ECCW0_FLIP_CTRL);
drivers/edac/versal_edac.c
723
writel(0, priv->ddrmc_noc_baseaddr + XDDR_NOC_REG_ADEC12_OFFSET);
drivers/edac/versal_edac.c
724
writel(0, priv->ddrmc_noc_baseaddr + XDDR_NOC_REG_ADEC13_OFFSET);
drivers/edac/versal_edac.c
730
writel(regval, priv->ddrmc_noc_baseaddr + XDDR_NOC_REG_ADEC14_OFFSET);
drivers/edac/versal_edac.c
736
writel(regval, priv->ddrmc_noc_baseaddr + XDDR_NOC_REG_ADEC15_OFFSET);
drivers/edac/versal_edac.c
757
writel(ecc0_flip0, priv->ddrmc_baseaddr + ECCW0_FLIP0_OFFSET);
drivers/edac/versal_edac.c
758
writel(ecc1_flip0, priv->ddrmc_baseaddr + ECCW1_FLIP0_OFFSET);
drivers/edac/versal_edac.c
759
writel(ecc0_flip1, priv->ddrmc_baseaddr + ECCW0_FLIP1_OFFSET);
drivers/edac/versal_edac.c
760
writel(ecc1_flip1, priv->ddrmc_baseaddr + ECCW1_FLIP1_OFFSET);
drivers/edac/versal_edac.c
798
writel(PCSR_UNLOCK_VAL, priv->ddrmc_baseaddr + XDDR_PCSR_OFFSET);
drivers/edac/versal_edac.c
799
writel(PCSR_UNLOCK_VAL, priv->ddrmc_noc_baseaddr + XDDR_PCSR_OFFSET);
drivers/edac/versal_edac.c
807
writel(PCSR_LOCK_VAL, priv->ddrmc_baseaddr + XDDR_PCSR_OFFSET);
drivers/edac/versal_edac.c
808
writel(PCSR_LOCK_VAL, priv->ddrmc_noc_baseaddr + XDDR_PCSR_OFFSET);
drivers/edac/versal_edac.c
823
writel(val0, priv->ddrmc_baseaddr + ECCW0_FLIP0_OFFSET);
drivers/edac/versal_edac.c
824
writel(val0, priv->ddrmc_baseaddr + ECCW0_FLIP1_OFFSET);
drivers/edac/versal_edac.c
825
writel(val1, priv->ddrmc_baseaddr + ECCW1_FLIP1_OFFSET);
drivers/edac/versal_edac.c
826
writel(val1, priv->ddrmc_baseaddr + ECCW1_FLIP1_OFFSET);
drivers/edac/versal_edac.c
894
writel(PCSR_UNLOCK_VAL, priv->ddrmc_baseaddr + XDDR_PCSR_OFFSET);
drivers/edac/versal_edac.c
895
writel(PCSR_UNLOCK_VAL, priv->ddrmc_noc_baseaddr + XDDR_PCSR_OFFSET);
drivers/edac/versal_edac.c
902
writel(PCSR_LOCK_VAL, priv->ddrmc_noc_baseaddr + XDDR_PCSR_OFFSET);
drivers/edac/versal_edac.c
903
writel(PCSR_LOCK_VAL, priv->ddrmc_baseaddr + XDDR_PCSR_OFFSET);
drivers/edac/xgene_edac.c
1101
writel(0, ctx->dev_csr + L3C_ESR);
drivers/edac/xgene_edac.c
1129
writel(val, ctx->dev_csr + L3C_ECR);
drivers/edac/xgene_edac.c
1155
writel(0xFFFFFFFF, ctx->dev_csr + L3C_ESR);
drivers/edac/xgene_edac.c
1413
writel(reg, ctx->dev_csr + XGICTRANSERRINTSTS);
drivers/edac/xgene_edac.c
1426
writel(err_addr_lo, ctx->dev_csr + GLBL_SEC_ERRL);
drivers/edac/xgene_edac.c
1427
writel(err_addr_hi, ctx->dev_csr + GLBL_SEC_ERRH);
drivers/edac/xgene_edac.c
1435
writel(err_addr_lo, ctx->dev_csr + GLBL_MSEC_ERRL);
drivers/edac/xgene_edac.c
1436
writel(err_addr_hi, ctx->dev_csr + GLBL_MSEC_ERRH);
drivers/edac/xgene_edac.c
1447
writel(err_addr_lo, ctx->dev_csr + GLBL_DED_ERRL);
drivers/edac/xgene_edac.c
1448
writel(err_addr_hi, ctx->dev_csr + GLBL_DED_ERRH);
drivers/edac/xgene_edac.c
1456
writel(err_addr_lo, ctx->dev_csr + GLBL_MDED_ERRL);
drivers/edac/xgene_edac.c
1457
writel(err_addr_hi, ctx->dev_csr + GLBL_MDED_ERRH);
drivers/edac/xgene_edac.c
150
writel(MCU_ESRR_MULTUCERR_MASK | MCU_ESRR_BACKUCERR_MASK |
drivers/edac/xgene_edac.c
1569
writel(reg, ctx->dev_csr + IOBBATRANSERRINTSTS);
drivers/edac/xgene_edac.c
1603
writel(reg, ctx->dev_csr + IOBPATRANSERRINTSTS);
drivers/edac/xgene_edac.c
1617
writel(reg, ctx->dev_csr + IOBAXIS0TRANSERRINTSTS);
drivers/edac/xgene_edac.c
1631
writel(reg, ctx->dev_csr + IOBAXIS1TRANSERRINTSTS);
drivers/edac/xgene_edac.c
1711
writel(enable ? 0x0 : 0xFFFFFFFF,
drivers/edac/xgene_edac.c
1713
writel(enable ? 0x0 : 0xFFFFFFFF,
drivers/edac/xgene_edac.c
1715
writel(enable ? 0x0 : 0xFFFFFFFF,
drivers/edac/xgene_edac.c
227
writel(0x0, ctx->mcu_csr + MCUEBLRR0 + rank * MCU_RANK_STRIDE);
drivers/edac/xgene_edac.c
228
writel(0x0, ctx->mcu_csr + MCUERCRR0 + rank * MCU_RANK_STRIDE);
drivers/edac/xgene_edac.c
229
writel(0x0, ctx->mcu_csr + MCUSBECNT0 +
drivers/edac/xgene_edac.c
231
writel(reg, ctx->mcu_csr + MCUESRR0 + rank * MCU_RANK_STRIDE);
drivers/edac/xgene_edac.c
244
writel(reg, ctx->mcu_csr + MCUGESR);
drivers/edac/xgene_edac.c
287
writel(val, ctx->mcu_csr + MCUGECR);
drivers/edac/xgene_edac.c
295
writel(val, ctx->mcu_csr + MCUGECR);
drivers/edac/xgene_edac.c
562
writel(val, pg_f + MEMERR_CPU_ICFESR_PAGE_OFFSET);
drivers/edac/xgene_edac.c
606
writel(val, pg_f + MEMERR_CPU_LSUESR_PAGE_OFFSET);
drivers/edac/xgene_edac.c
655
writel(val, pg_f + MEMERR_CPU_MMUESR_PAGE_OFFSET);
drivers/edac/xgene_edac.c
712
writel(val, pg_e + MEMERR_L2C_L2ESR_PAGE_OFFSET);
drivers/edac/xgene_edac.c
731
writel(val, pg_d + CPUX_L2C_L2RTOSR_PAGE_OFFSET);
drivers/edac/xgene_edac.c
764
writel(0x00000301, pg_f + MEMERR_CPU_ICFECR_PAGE_OFFSET);
drivers/edac/xgene_edac.c
765
writel(0x00000301, pg_f + MEMERR_CPU_LSUECR_PAGE_OFFSET);
drivers/edac/xgene_edac.c
766
writel(0x00000101, pg_f + MEMERR_CPU_MMUECR_PAGE_OFFSET);
drivers/edac/xgene_edac.c
776
writel(0x00000703, pg_e + MEMERR_L2C_L2ECR_PAGE_OFFSET);
drivers/edac/xgene_edac.c
779
writel(0x00000119, pg_d + CPUX_L2C_L2RTOCR_PAGE_OFFSET);
drivers/edac/xgene_edac.c
80
writel(val, edac->pcp_csr + reg);
drivers/edac/xgene_edac.c
820
writel(MEMERR_CPU_ICFESR_MULTCERR_MASK |
drivers/edac/xgene_edac.c
823
writel(MEMERR_CPU_LSUESR_MULTCERR_MASK |
drivers/edac/xgene_edac.c
826
writel(MEMERR_CPU_MMUESR_MULTCERR_MASK |
drivers/edac/xgene_edac.c
841
writel(MEMERR_L2C_L2ESR_MULTUCERR_MASK |
drivers/edac/xgene_edac.c
92
writel(val, edac->pcp_csr + reg);
drivers/edac/zynqmp_edac.c
140
writel(ECC_CTRL_CLR_CE_ERR, base + OCM_ISR_OFST);
drivers/edac/zynqmp_edac.c
146
writel(ECC_CTRL_CLR_UE_ERR, base + OCM_ISR_OFST);
drivers/edac/zynqmp_edac.c
240
writel(ficount, priv->baseaddr + OCM_FIC_OFST);
drivers/edac/zynqmp_edac.c
268
writel(BIT(priv->ce_bitpos), priv->baseaddr + OCM_FID0_OFST);
drivers/edac/zynqmp_edac.c
269
writel(0, priv->baseaddr + OCM_FID1_OFST);
drivers/edac/zynqmp_edac.c
271
writel(BIT(priv->ce_bitpos - UE_MIN_BITPOS_UPPER),
drivers/edac/zynqmp_edac.c
273
writel(0, priv->baseaddr + OCM_FID0_OFST);
drivers/edac/zynqmp_edac.c
335
writel((u32)ue_bitpos, priv->baseaddr + OCM_FID0_OFST);
drivers/edac/zynqmp_edac.c
336
writel((u32)(ue_bitpos >> 32), priv->baseaddr + OCM_FID1_OFST);
drivers/edac/zynqmp_edac.c
411
writel((OCM_CEINTR_MASK | OCM_UEINTR_MASK), priv->baseaddr + OCM_IEN_OFST);
drivers/edac/zynqmp_edac.c
435
writel((OCM_CEINTR_MASK | OCM_UEINTR_MASK), priv->baseaddr + OCM_IDS_OFST);
drivers/extcon/extcon-rtk-type-c.c
1211
writel(val, reg);
drivers/extcon/extcon-rtk-type-c.c
1218
writel(type_c->cc1_vref, reg);
drivers/extcon/extcon-rtk-type-c.c
1221
writel(type_c->cc2_vref, reg);
drivers/extcon/extcon-rtk-type-c.c
1427
writel(default_ctrl, type_c->reg_base + USB_TYPEC_CTRL);
drivers/extcon/extcon-rtk-type-c.c
1430
writel(PLR_EN, type_c->reg_base + USB_TYPEC_CTRL_CC1_0);
drivers/extcon/extcon-rtk-type-c.c
1431
writel(0, type_c->reg_base + USB_TYPEC_CTRL_CC2_0);
drivers/extcon/extcon-rtk-type-c.c
1733
writel(default_ctrl, type_c->reg_base + USB_TYPEC_CTRL);
drivers/extcon/extcon-rtk-type-c.c
1736
writel(PLR_EN, type_c->reg_base + USB_TYPEC_CTRL_CC1_0);
drivers/extcon/extcon-rtk-type-c.c
1737
writel(0, type_c->reg_base + USB_TYPEC_CTRL_CC2_0);
drivers/extcon/extcon-rtk-type-c.c
266
writel(val_cc, reg);
drivers/extcon/extcon-rtk-type-c.c
374
writel(ENABLE_TYPE_C_DETECT | readl(reg), reg);
drivers/extcon/extcon-rtk-type-c.c
383
writel(~ENABLE_TYPE_C_DETECT & readl(reg), reg);
drivers/extcon/extcon-rtk-type-c.c
401
writel(default_ctrl, reg_base + USB_TYPEC_CTRL);
drivers/extcon/extcon-rtk-type-c.c
408
writel(cc1_config, reg_base + USB_TYPEC_CTRL_CC1_0);
drivers/extcon/extcon-rtk-type-c.c
409
writel(cc2_config, reg_base + USB_TYPEC_CTRL_CC2_0);
drivers/extcon/extcon-rtk-type-c.c
418
writel(cc2_config, reg_base + USB_TYPEC_CTRL_CC2_0);
drivers/extcon/extcon-rtk-type-c.c
419
writel(cc1_config, reg_base + USB_TYPEC_CTRL_CC1_0);
drivers/extcon/extcon-rtk-type-c.c
431
writel(cc1_config, reg_base + USB_TYPEC_CTRL_CC1_0);
drivers/extcon/extcon-rtk-type-c.c
432
writel(cc2_config, reg_base + USB_TYPEC_CTRL_CC2_0);
drivers/extcon/extcon-rtk-type-c.c
679
writel(~ALL_CC_INT_STS & readl(reg), reg);
drivers/extcon/extcon-rtk-type-c.c
689
writel(~ALL_CC_INT_STS & readl(reg), reg);
drivers/firewire/init_ohci1394_dma.c
42
writel(data, ohci->registers + offset);
drivers/firewire/nosy.c
220
writel(data, lynx->registers + offset);
drivers/firewire/ohci.c
406
writel(data, ohci->registers + offset);
drivers/firmware/samsung/exynos-acpm.c
283
writel(rx_front, achan->rx.rear);
drivers/firmware/samsung/exynos-acpm.c
454
writel(idx, achan->tx.front);
drivers/firmware/tegra/bpmp-tegra210.c
144
writel(index << TRIGGER_ID_SHIFT | TRIGGER_CMD_GET,
drivers/fpga/altera-cvp.c
131
writel(val, conf->map);
drivers/fpga/altera-freeze-bridge.c
109
writel(FREEZE_CSR_CTRL_FREEZE_REQ, csr_ctrl_addr);
drivers/fpga/altera-freeze-bridge.c
115
writel(0, csr_ctrl_addr);
drivers/fpga/altera-freeze-bridge.c
117
writel(FREEZE_CSR_CTRL_RESET_REQ, csr_ctrl_addr);
drivers/fpga/altera-freeze-bridge.c
131
writel(0, csr_ctrl_addr);
drivers/fpga/altera-freeze-bridge.c
146
writel(FREEZE_CSR_CTRL_UNFREEZE_REQ, csr_ctrl_addr);
drivers/fpga/altera-freeze-bridge.c
155
writel(0, csr_ctrl_addr);
drivers/fpga/altera-freeze-bridge.c
55
writel(1, csr_illegal_req_addr);
drivers/fpga/altera-pr-ip-core.c
116
writel(buffer_32[i++], priv->reg_base);
drivers/fpga/altera-pr-ip-core.c
123
writel(buffer_32[i++] & 0x00ffffff, priv->reg_base);
drivers/fpga/altera-pr-ip-core.c
126
writel(buffer_32[i++] & 0x0000ffff, priv->reg_base);
drivers/fpga/altera-pr-ip-core.c
129
writel(buffer_32[i++] & 0x000000ff, priv->reg_base);
drivers/fpga/altera-pr-ip-core.c
99
writel(val | ALT_PR_CSR_PR_START, priv->reg_base + ALT_PR_CSR_OFST);
drivers/fpga/socfpga-a10.c
366
writel(buffer_32[i++], priv->fpga_data_addr);
drivers/fpga/socfpga-a10.c
373
writel(buffer_32[i++] & 0x00ffffff, priv->fpga_data_addr);
drivers/fpga/socfpga-a10.c
376
writel(buffer_32[i++] & 0x0000ffff, priv->fpga_data_addr);
drivers/fpga/socfpga-a10.c
379
writel(buffer_32[i++] & 0x000000ff, priv->fpga_data_addr);
drivers/fpga/socfpga.c
142
writel(value, priv->fpga_base_addr + reg_offset);
drivers/fpga/socfpga.c
159
writel(value, priv->fpga_data_addr);
drivers/fpga/xilinx-pr-decoupler.c
36
writel(val, d->io_base + offset);
drivers/fpga/zynq-fpga.c
140
writel(val, priv->io_base + offset);
drivers/fsi/fsi-master-aspeed.c
113
writel(0x1, base + OPB_TRIGGER);
drivers/fsi/fsi-master-aspeed.c
164
writel(0x1, base + OPB_TRIGGER);
drivers/fsi/fsi-master-aspeed.c
578
writel(0x1, aspeed->base + OPB_CLK_SYNC);
drivers/fsi/fsi-master-aspeed.c
579
writel(OPB1_XFER_ACK_EN | OPB0_XFER_ACK_EN,
drivers/fsi/fsi-master-aspeed.c
583
writel(0x10, aspeed->base + OPB_RETRY_COUNTER);
drivers/fsi/fsi-master-aspeed.c
585
writel(ctrl_base, aspeed->base + OPB_CTRL_BASE);
drivers/fsi/fsi-master-aspeed.c
586
writel(fsi_base, aspeed->base + OPB_FSI_BASE);
drivers/fsi/fsi-master-aspeed.c
589
writel(0x00030b1b, aspeed->base + OPB0_READ_ORDER1);
drivers/fsi/fsi-master-aspeed.c
592
writel(0x0011101b, aspeed->base + OPB0_WRITE_ORDER1);
drivers/fsi/fsi-master-aspeed.c
593
writel(0x0c330f3f, aspeed->base + OPB0_WRITE_ORDER2);
drivers/fsi/fsi-master-aspeed.c
600
writel(0x1, aspeed->base + OPB0_SELECT);
drivers/gpib/agilent_82350b/agilent_82350b.c
528
writel(plx_cntrl_static_bits | PLX9050_USER3_DATA_BIT,
drivers/gpib/agilent_82350b/agilent_82350b.c
531
writel(plx_cntrl_static_bits, a_priv->plx_base + PLX9050_CNTRL_REG);
drivers/gpib/agilent_82350b/agilent_82350b.c
533
writel(plx_cntrl_static_bits | PLX9050_USER3_DATA_BIT,
drivers/gpib/agilent_82350b/agilent_82350b.c
709
writel(PLX9050_LINTR1_EN_BIT | PLX9050_LINTR2_POLARITY_BIT |
drivers/gpib/agilent_82350b/agilent_82350b.c
754
writel(0, a_priv->plx_base + PLX9050_INTCSR_REG);
drivers/gpib/eastwood/fluke_gpib.c
395
writel(0x0, e_priv->write_transfer_counter);
drivers/gpib/eastwood/fluke_gpib.h
85
writel(data, nec_priv->mmiobase + register_num * nec_priv->offset);
drivers/gpib/tnt4882/mite.c
98
writel(mite->daq_phys_addr | WENAB, mite->mite_io_addr + MITE_IODWBSR);
drivers/gpio/gpio-altera.c
128
writel(data_reg, altera_gc->regs + ALTERA_GPIO_DATA);
drivers/gpio/gpio-altera.c
144
writel(gpio_ddr, altera_gc->regs + ALTERA_GPIO_DIR);
drivers/gpio/gpio-altera.c
164
writel(data_reg, altera_gc->regs + ALTERA_GPIO_DATA);
drivers/gpio/gpio-altera.c
169
writel(gpio_ddr, altera_gc->regs + ALTERA_GPIO_DIR);
drivers/gpio/gpio-altera.c
191
writel(status, altera_gc->regs + ALTERA_GPIO_EDGE_CAP);
drivers/gpio/gpio-altera.c
56
writel(intmask, altera_gc->regs + ALTERA_GPIO_IRQ_MASK);
drivers/gpio/gpio-altera.c
71
writel(intmask, altera_gc->regs + ALTERA_GPIO_IRQ_MASK);
drivers/gpio/gpio-amdpt.c
120
writel(0, pt_gpio->reg_base + PT_SYNC_REG);
drivers/gpio/gpio-amdpt.c
121
writel(0, pt_gpio->reg_base + PT_CLOCKRATE_REG);
drivers/gpio/gpio-amdpt.c
49
writel(using_pins | BIT(offset), pt_gpio->reg_base + PT_SYNC_REG);
drivers/gpio/gpio-amdpt.c
64
writel(using_pins, pt_gpio->reg_base + PT_SYNC_REG);
drivers/gpio/gpio-ath79.c
53
writel(val, ctrl->base + reg);
drivers/gpio/gpio-bcm-kona.c
174
writel(val, reg_base + reg_offset);
drivers/gpio/gpio-bcm-kona.c
233
writel(val, reg_base + GPIO_CONTROL(gpio));
drivers/gpio/gpio-bcm-kona.c
255
writel(val, reg_base + GPIO_CONTROL(gpio));
drivers/gpio/gpio-bcm-kona.c
260
writel(val, reg_base + reg_offset);
drivers/gpio/gpio-bcm-kona.c
316
writel(val, reg_base + GPIO_CONTROL(gpio));
drivers/gpio/gpio-bcm-kona.c
364
writel(val, reg_base + GPIO_INT_STATUS(bank_id));
drivers/gpio/gpio-bcm-kona.c
383
writel(val, reg_base + GPIO_INT_MASK(bank_id));
drivers/gpio/gpio-bcm-kona.c
403
writel(val, reg_base + GPIO_INT_MSKCLR(bank_id));
drivers/gpio/gpio-bcm-kona.c
444
writel(val, reg_base + GPIO_CONTROL(gpio));
drivers/gpio/gpio-bcm-kona.c
475
writel(readl(reg_base + GPIO_INT_STATUS(bank_id)) |
drivers/gpio/gpio-bcm-kona.c
571
writel(0xffffffff, reg_base + GPIO_INT_MASK(i));
drivers/gpio/gpio-bcm-kona.c
572
writel(0xffffffff, reg_base + GPIO_INT_STATUS(i));
drivers/gpio/gpio-bcm-kona.c
96
writel(BCM_GPIO_PASSWD, reg_base + GPIO_GPPWR_OFFSET);
drivers/gpio/gpio-bcm-kona.c
97
writel(lockcode, reg_base + GPIO_PWD_STATUS(bank_id));
drivers/gpio/gpio-bt8xx.c
59
#define bgwrite(dat, adr) writel((dat), bg->mmio+(adr))
drivers/gpio/gpio-creg-snps.c
48
writel(reg, hcg->regs);
drivers/gpio/gpio-ftgpio010.c
132
writel(reg_type, g->base + GPIO_INT_TYPE);
drivers/gpio/gpio-ftgpio010.c
133
writel(reg_level, g->base + GPIO_INT_LEVEL);
drivers/gpio/gpio-ftgpio010.c
134
writel(reg_both, g->base + GPIO_INT_BOTH_EDGE);
drivers/gpio/gpio-ftgpio010.c
204
writel(val, g->base + GPIO_DEBOUNCE_EN);
drivers/gpio/gpio-ftgpio010.c
218
writel(deb_div, g->base + GPIO_DEBOUNCE_PRESCALE);
drivers/gpio/gpio-ftgpio010.c
221
writel(val, g->base + GPIO_DEBOUNCE_EN);
drivers/gpio/gpio-ftgpio010.c
304
writel(0x0, g->base + GPIO_INT_EN);
drivers/gpio/gpio-ftgpio010.c
305
writel(0x0, g->base + GPIO_INT_MASK);
drivers/gpio/gpio-ftgpio010.c
306
writel(~0x0, g->base + GPIO_INT_CLR);
drivers/gpio/gpio-ftgpio010.c
309
writel(0x0, g->base + GPIO_DEBOUNCE_EN);
drivers/gpio/gpio-ftgpio010.c
61
writel(BIT(irqd_to_hwirq(d)), g->base + GPIO_INT_CLR);
drivers/gpio/gpio-ftgpio010.c
72
writel(val, g->base + GPIO_INT_EN);
drivers/gpio/gpio-ftgpio010.c
85
writel(val, g->base + GPIO_INT_EN);
drivers/gpio/gpio-graniterapids.c
189
writel(reg, addr);
drivers/gpio/gpio-graniterapids.c
207
writel(reg, addr);
drivers/gpio/gpio-graniterapids.c
390
writel(priv->pad_backup[i], gnr_gpio_get_padcfg_addr(priv, i));
drivers/gpio/gpio-graniterapids.c
90
writel(dw, addr);
drivers/gpio/gpio-hisi.c
62
writel(val, reg);
drivers/gpio/gpio-idt3243x.c
105
writel(ctrl->mask_cache, ctrl->pic + IDT_PIC_IRQ_MASK);
drivers/gpio/gpio-idt3243x.c
114
writel(ctrl->mask_cache, ctrl->pic + IDT_PIC_IRQ_MASK);
drivers/gpio/gpio-idt3243x.c
68
writel(ilevel, ctrl->gpio + IDT_GPIO_ILEVEL);
drivers/gpio/gpio-idt3243x.c
79
writel(~BIT(d->hwirq), ctrl->gpio + IDT_GPIO_ISTAT);
drivers/gpio/gpio-idt3243x.c
89
writel(ctrl->mask_cache, ctrl->pic + IDT_PIC_IRQ_MASK);
drivers/gpio/gpio-loongson-64bit.c
143
writel(u, lgpio->reg_base + lgpio->chip_data->inten_offset + (offset / 32) * 4);
drivers/gpio/gpio-lpc18xx.c
305
writel(dir, gc->base + LPC18XX_REG_DIR(port));
drivers/gpio/gpio-mb86s7x.c
104
writel(val, gchip->base + PDR(gpio));
drivers/gpio/gpio-mb86s7x.c
108
writel(val, gchip->base + DDR(gpio));
drivers/gpio/gpio-mb86s7x.c
135
writel(val, gchip->base + PDR(gpio));
drivers/gpio/gpio-mb86s7x.c
51
writel(val, gchip->base + PFR(gpio));
drivers/gpio/gpio-mb86s7x.c
68
writel(val, gchip->base + PFR(gpio));
drivers/gpio/gpio-mb86s7x.c
83
writel(val, gchip->base + DDR(gpio));
drivers/gpio/gpio-menz127.c
108
writel(od_en, priv->reg_base + MEN_Z127_ODER);
drivers/gpio/gpio-menz127.c
85
writel(db_en, priv->reg_base + MEN_Z127_DBER);
drivers/gpio/gpio-menz127.c
86
writel(db_cnt, priv->reg_base + GPIO_TO_DBCNT_REG(gpio));
drivers/gpio/gpio-mlxbf2.c
150
writel(YU_ARM_GPIO_LOCK_ACQUIRE, yu_arm_gpio_lock_param.io);
drivers/gpio/gpio-mlxbf2.c
162
writel(YU_ARM_GPIO_LOCK_RELEASE, yu_arm_gpio_lock_param.io);
drivers/gpio/gpio-mlxbf2.c
199
writel(BIT(offset), gs->gpio_io + YU_GPIO_MODE0_CLEAR);
drivers/gpio/gpio-mlxbf2.c
200
writel(BIT(offset), gs->gpio_io + YU_GPIO_MODE1_CLEAR);
drivers/gpio/gpio-mlxbf2.c
227
writel(BIT(offset), gs->gpio_io + YU_GPIO_MODE1_CLEAR);
drivers/gpio/gpio-mlxbf2.c
228
writel(BIT(offset), gs->gpio_io + YU_GPIO_MODE0_SET);
drivers/gpio/gpio-mlxbf2.c
246
writel(val, gs->gpio_io + YU_GPIO_CAUSE_OR_CLRCAUSE);
drivers/gpio/gpio-mlxbf2.c
250
writel(val, gs->gpio_io + YU_GPIO_CAUSE_OR_EVTEN0);
drivers/gpio/gpio-mlxbf2.c
263
writel(val, gs->gpio_io + YU_GPIO_CAUSE_OR_EVTEN0);
drivers/gpio/gpio-mlxbf2.c
277
writel(pending, gs->gpio_io + YU_GPIO_CAUSE_OR_CLRCAUSE);
drivers/gpio/gpio-mlxbf2.c
315
writel(val, gs->gpio_io + YU_GPIO_CAUSE_FALL_EN);
drivers/gpio/gpio-mlxbf2.c
321
writel(val, gs->gpio_io + YU_GPIO_CAUSE_RISE_EN);
drivers/gpio/gpio-mlxbf2.c
443
writel(gs->csave_regs->gpio_mode0, gs->gpio_io +
drivers/gpio/gpio-mlxbf2.c
445
writel(gs->csave_regs->gpio_mode1, gs->gpio_io +
drivers/gpio/gpio-mlxbf3.c
101
writel(pending, gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_CLRCAUSE);
drivers/gpio/gpio-mlxbf3.c
122
writel(val, gs->gpio_io + MLXBF_GPIO_CAUSE_FALL_EN);
drivers/gpio/gpio-mlxbf3.c
125
writel(val, gs->gpio_io + MLXBF_GPIO_CAUSE_RISE_EN);
drivers/gpio/gpio-mlxbf3.c
130
writel(val, gs->gpio_io + MLXBF_GPIO_CAUSE_RISE_EN);
drivers/gpio/gpio-mlxbf3.c
135
writel(val, gs->gpio_io + MLXBF_GPIO_CAUSE_FALL_EN);
drivers/gpio/gpio-mlxbf3.c
268
writel(0, gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_EVTEN0);
drivers/gpio/gpio-mlxbf3.c
269
writel(MLXBF_GPIO_CLR_ALL_INTS, gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_CLRCAUSE);
drivers/gpio/gpio-mlxbf3.c
68
writel(BIT(offset), gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_CLRCAUSE);
drivers/gpio/gpio-mlxbf3.c
72
writel(val, gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_EVTEN0);
drivers/gpio/gpio-mlxbf3.c
85
writel(val, gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_EVTEN0);
drivers/gpio/gpio-mlxbf3.c
87
writel(BIT(offset), gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_CLRCAUSE);
drivers/gpio/gpio-mmio.c
87
writel(data, reg);
drivers/gpio/gpio-mxc.c
208
writel(val | (1 << gpio_idx),
drivers/gpio/gpio-mxc.c
211
writel(val & ~(1 << gpio_idx),
drivers/gpio/gpio-mxc.c
219
writel(val | (edge << (bit << 1)), reg);
drivers/gpio/gpio-mxc.c
222
writel(1 << gpio_idx, port->base + GPIO_ISR);
drivers/gpio/gpio-mxc.c
253
writel(val | (edge << (bit << 1)), reg);
drivers/gpio/gpio-mxc.c
463
writel(0, port->base + GPIO_IMR);
drivers/gpio/gpio-mxc.c
464
writel(~0, port->base + GPIO_ISR);
drivers/gpio/gpio-mxc.c
560
writel(port->gpio_saved_reg.icr1, port->base + GPIO_ICR1);
drivers/gpio/gpio-mxc.c
561
writel(port->gpio_saved_reg.icr2, port->base + GPIO_ICR2);
drivers/gpio/gpio-mxc.c
562
writel(port->gpio_saved_reg.imr, port->base + GPIO_IMR);
drivers/gpio/gpio-mxc.c
563
writel(port->gpio_saved_reg.gdir, port->base + GPIO_GDIR);
drivers/gpio/gpio-mxc.c
564
writel(port->gpio_saved_reg.edge_sel, port->base + GPIO_EDGE_SEL);
drivers/gpio/gpio-mxc.c
565
writel(port->gpio_saved_reg.dr, port->base + GPIO_DR);
drivers/gpio/gpio-mxs.c
108
writel(pin_mask, pin_addr + MXS_SET);
drivers/gpio/gpio-mxs.c
109
writel(pin_mask, port->base + PINCTRL_IRQEN(port) + MXS_SET);
drivers/gpio/gpio-mxs.c
111
writel(pin_mask, pin_addr + MXS_CLR);
drivers/gpio/gpio-mxs.c
112
writel(pin_mask, port->base + PINCTRL_PIN2IRQ(port) + MXS_SET);
drivers/gpio/gpio-mxs.c
118
writel(pin_mask, pin_addr + MXS_SET);
drivers/gpio/gpio-mxs.c
120
writel(pin_mask, pin_addr + MXS_CLR);
drivers/gpio/gpio-mxs.c
122
writel(pin_mask, port->base + PINCTRL_IRQSTAT(port) + MXS_CLR);
drivers/gpio/gpio-mxs.c
139
writel(bit, pin_addr + MXS_CLR);
drivers/gpio/gpio-mxs.c
141
writel(bit, pin_addr + MXS_SET);
drivers/gpio/gpio-mxs.c
296
writel(0, port->base + PINCTRL_PIN2IRQ(port));
drivers/gpio/gpio-mxs.c
297
writel(0, port->base + PINCTRL_IRQEN(port));
drivers/gpio/gpio-mxs.c
300
writel(~0U, port->base + PINCTRL_IRQSTAT(port) + MXS_CLR);
drivers/gpio/gpio-nomadik.c
123
writel(*rimscval, nmk_chip->addr + rimscreg);
drivers/gpio/gpio-nomadik.c
130
writel(*fimscval, nmk_chip->addr + fimscreg);
drivers/gpio/gpio-nomadik.c
295
writel(status & ~mask, nmk_chip->addr + NMK_GPIO_IC);
drivers/gpio/gpio-nomadik.c
330
writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DIRC);
drivers/gpio/gpio-nomadik.c
57
writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC);
drivers/gpio/gpio-nomadik.c
64
writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATS);
drivers/gpio/gpio-nomadik.c
66
writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATC);
drivers/gpio/gpio-nomadik.c
72
writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DIRS);
drivers/gpio/gpio-nomadik.c
84
writel(BIT(d->hwirq), nmk_chip->addr + NMK_GPIO_IC);
drivers/gpio/gpio-rockchip.c
119
writel(data, bit >= 16 ? reg + 0x4 : reg);
drivers/gpio/gpio-rockchip.c
125
writel(data, reg);
drivers/gpio/gpio-rockchip.c
231
writel(div_reg, bank->reg_base +
drivers/gpio/gpio-rockchip.c
367
writel(polarity,
drivers/gpio/gpio-rockchip.c
73
writel((val & 0xffff) | 0xffff0000, reg);
drivers/gpio/gpio-rockchip.c
74
writel((val >> 16) | 0xffff0000, reg + 0x4);
drivers/gpio/gpio-rockchip.c
90
writel(value, reg);
drivers/gpio/gpio-sodaville.c
138
writel(0, sd->gpio_pub_base + GPIO_INT);
drivers/gpio/gpio-sodaville.c
139
writel((1 << 11) - 1, sd->gpio_pub_base + GPSTR);
drivers/gpio/gpio-sodaville.c
209
writel(mux_val, sd->gpio_pub_base + GPMUXCTL);
drivers/gpio/gpio-sodaville.c
73
writel(reg, type_reg);
drivers/gpio/gpio-spacemit-k1.c
73
writel(val, gb->base + to_spacemit_gpio_regs(gb)[reg]);
drivers/gpio/gpio-tangier.c
103
writel(BIT(shift), reg);
drivers/gpio/gpio-tangier.c
121
writel(value, gpdr);
drivers/gpio/gpio-tangier.c
140
writel(value, gpdr);
drivers/gpio/gpio-tangier.c
175
writel(value, gfbr);
drivers/gpio/gpio-tangier.c
210
writel(BIT(shift), gisr);
drivers/gpio/gpio-tangier.c
228
writel(value, gimr);
drivers/gpio/gpio-tangier.c
270
writel(value, grer);
drivers/gpio/gpio-tangier.c
277
writel(value, gfer);
drivers/gpio/gpio-tangier.c
288
writel(value, glpr);
drivers/gpio/gpio-tangier.c
293
writel(value, gitr);
drivers/gpio/gpio-tangier.c
299
writel(value, gitr);
drivers/gpio/gpio-tangier.c
322
writel(BIT(shift), gwsr);
drivers/gpio/gpio-tangier.c
329
writel(value, gwmr);
drivers/gpio/gpio-tangier.c
382
writel(0, reg);
drivers/gpio/gpio-tangier.c
386
writel(0, reg);
drivers/gpio/gpio-tangier.c
499
writel(ctx->level, gpio_reg(&priv->chip, base, GPSR));
drivers/gpio/gpio-tangier.c
501
writel(ctx->gpdr, gpio_reg(&priv->chip, base, GPDR));
drivers/gpio/gpio-tangier.c
502
writel(ctx->grer, gpio_reg(&priv->chip, base, GRER));
drivers/gpio/gpio-tangier.c
503
writel(ctx->gfer, gpio_reg(&priv->chip, base, GFER));
drivers/gpio/gpio-tangier.c
504
writel(ctx->gimr, gpio_reg(&priv->chip, base, GIMR));
drivers/gpio/gpio-tangier.c
506
writel(ctx->gwmr, gpio_reg(&priv->chip, base, priv->wake_regs.gwmr));
drivers/gpio/gpio-tegra186.c
249
writel(value, base + TEGRA186_GPIO_OUTPUT_VALUE);
drivers/gpio/gpio-tegra186.c
285
writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL);
drivers/gpio/gpio-tegra186.c
290
writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
drivers/gpio/gpio-tegra186.c
315
writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL);
drivers/gpio/gpio-tegra186.c
320
writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
drivers/gpio/gpio-tegra186.c
357
writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
drivers/gpio/gpio-tegra186.c
390
writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
drivers/gpio/gpio-tegra186.c
441
writel(value, base + TEGRA186_GPIO_DEBOUNCE_CONTROL);
drivers/gpio/gpio-tegra186.c
445
writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
drivers/gpio/gpio-tegra186.c
536
writel(1, base + TEGRA186_GPIO_INTERRUPT_CLEAR);
drivers/gpio/gpio-tegra186.c
552
writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
drivers/gpio/gpio-tegra186.c
572
writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
drivers/gpio/gpio-tegra186.c
620
writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
drivers/gpio/gpio-tegra186.c
822
writel(value, base + offset);
drivers/gpio/gpio-uniphier.c
335
writel(0xff, priv->regs + UNIPHIER_GPIO_IRQ_FLT_CYC);
drivers/gpio/gpio-uniphier.c
462
writel(*val++, priv->regs + reg + UNIPHIER_GPIO_PORT_DATA);
drivers/gpio/gpio-uniphier.c
463
writel(*val++, priv->regs + reg + UNIPHIER_GPIO_PORT_DIR);
drivers/gpio/gpio-uniphier.c
466
writel(*val++, priv->regs + UNIPHIER_GPIO_IRQ_EN);
drivers/gpio/gpio-uniphier.c
467
writel(*val++, priv->regs + UNIPHIER_GPIO_IRQ_MODE);
drivers/gpio/gpio-uniphier.c
468
writel(*val++, priv->regs + UNIPHIER_GPIO_IRQ_FLT_EN);
drivers/gpio/gpio-uniphier.c
69
writel(tmp, priv->regs + reg);
drivers/gpio/gpio-visconti.c
83
writel(odata, priv->base + GPIO_ODATA);
drivers/gpio/gpio-visconti.c
84
writel(intmode, priv->base + GPIO_INTMODE);
drivers/gpio/gpio-xilinx.c
38
# define xgpio_writereg(offset, val) writel(val, offset)
drivers/gpio/gpio-xlp.c
90
writel(value, addr + regset);
drivers/gpio/gpio-zevio.c
74
writel(val, IOMEM(c->regs + section_offset + port_offset));
drivers/gpu/drm/adp/adp-mipi.c
46
writel(hdr_val, adp->mipi + DSI_GEN_HDR);
drivers/gpu/drm/adp/adp-mipi.c
72
writel(le32_to_cpu(word), adp->mipi + DSI_GEN_PLD_DATA);
drivers/gpu/drm/adp/adp-mipi.c
76
writel(le32_to_cpu(word), adp->mipi + DSI_GEN_PLD_DATA);
drivers/gpu/drm/adp/adp_drv.c
177
writel(src_pos, adp->be + ADBE_SRC_START);
drivers/gpu/drm/adp/adp_drv.c
178
writel(src_size, adp->be + ADBE_SRC_SIZE);
drivers/gpu/drm/adp/adp_drv.c
179
writel(dst_pos, adp->be + ADBE_DST_START);
drivers/gpu/drm/adp/adp_drv.c
180
writel(dst_size, adp->be + ADBE_DST_SIZE);
drivers/gpu/drm/adp/adp_drv.c
181
writel(fb->pitches[0], adp->be + ADBE_STRIDE);
drivers/gpu/drm/adp/adp_drv.c
184
writel(obj->dma_addr + fb->offsets[0], adp->be + ADBE_FB_BASE);
drivers/gpu/drm/adp/adp_drv.c
186
writel(BIT(0), adp->be + ADBE_LAYER_EN1);
drivers/gpu/drm/adp/adp_drv.c
187
writel(BIT(0), adp->be + ADBE_LAYER_EN2);
drivers/gpu/drm/adp/adp_drv.c
188
writel(BIT(0), adp->be + ADBE_LAYER_EN3);
drivers/gpu/drm/adp/adp_drv.c
189
writel(BIT(0), adp->be + ADBE_LAYER_EN4);
drivers/gpu/drm/adp/adp_drv.c
190
writel(ADBE_SCALE_CTL_BYPASS, adp->be + ADBE_SCALE_CTL);
drivers/gpu/drm/adp/adp_drv.c
191
writel(ADBE_LAYER_CTL_ENABLE | BIT(0), adp->be + ADBE_LAYER_CTL);
drivers/gpu/drm/adp/adp_drv.c
192
writel(ADBE_PIX_FMT_XRGB32, adp->be + ADBE_PIX_FMT);
drivers/gpu/drm/adp/adp_drv.c
200
writel(0x0, adp->be + ADBE_LAYER_EN1);
drivers/gpu/drm/adp/adp_drv.c
201
writel(0x0, adp->be + ADBE_LAYER_EN2);
drivers/gpu/drm/adp/adp_drv.c
202
writel(0x0, adp->be + ADBE_LAYER_EN3);
drivers/gpu/drm/adp/adp_drv.c
203
writel(0x0, adp->be + ADBE_LAYER_EN4);
drivers/gpu/drm/adp/adp_drv.c
204
writel(ADBE_LAYER_CTL_ENABLE, adp->be + ADBE_LAYER_CTL);
drivers/gpu/drm/adp/adp_drv.c
248
writel(ADP_INT_STATUS_INT_MASK, adp->fe + ADP_INT_STATUS);
drivers/gpu/drm/adp/adp_drv.c
251
writel(cur_ctrl | ADP_CTRL_VBLANK_ON, adp->fe + ADP_CTRL);
drivers/gpu/drm/adp/adp_drv.c
269
writel(cur_ctrl & ~ADP_CTRL_VBLANK_ON, adp->fe + ADP_CTRL);
drivers/gpu/drm/adp/adp_drv.c
270
writel(ADP_INT_STATUS_INT_MASK, adp->fe + ADP_INT_STATUS);
drivers/gpu/drm/adp/adp_drv.c
286
writel(BIT(0), adp->be + ADBE_BLEND_EN2);
drivers/gpu/drm/adp/adp_drv.c
287
writel(BIT(4), adp->be + ADBE_BLEND_EN1);
drivers/gpu/drm/adp/adp_drv.c
288
writel(BIT(0), adp->be + ADBE_BLEND_EN3);
drivers/gpu/drm/adp/adp_drv.c
289
writel(BIT(0), adp->be + ADBE_BLEND_BYPASS);
drivers/gpu/drm/adp/adp_drv.c
290
writel(BIT(0), adp->be + ADBE_BLEND_EN4);
drivers/gpu/drm/adp/adp_drv.c
302
writel(0x0, adp->be + ADBE_BLEND_EN2);
drivers/gpu/drm/adp/adp_drv.c
303
writel(0x0, adp->be + ADBE_BLEND_EN1);
drivers/gpu/drm/adp/adp_drv.c
304
writel(0x0, adp->be + ADBE_BLEND_EN3);
drivers/gpu/drm/adp/adp_drv.c
305
writel(0x0, adp->be + ADBE_BLEND_BYPASS);
drivers/gpu/drm/adp/adp_drv.c
306
writel(0x0, adp->be + ADBE_BLEND_EN4);
drivers/gpu/drm/adp/adp_drv.c
329
writel(adp->mask_iova, adp->be + ADBE_MASK_BUF);
drivers/gpu/drm/adp/adp_drv.c
333
writel(ADBE_FIFO_SYNC | frame_num, adp->be + ADBE_FIFO);
drivers/gpu/drm/adp/adp_drv.c
508
writel(int_status, adp->fe + ADP_INT_STATUS);
drivers/gpu/drm/adp/adp_drv.c
520
writel(ADP_CTRL_FIFO_ON, adp->fe + ADP_CTRL);
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
1000
writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
1034
writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
1072
writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
1102
writel(reg_addr, pcie_index_offset);
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
1143
writel(reg_addr, pcie_index_offset);
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
1146
writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset);
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
1153
writel(0, pcie_index_hi_offset);
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
1186
writel(reg_addr, pcie_index_offset);
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
1190
writel(reg_addr + 4, pcie_index_offset);
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
1221
writel(reg_addr, pcie_index_offset);
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
1224
writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset);
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
1229
writel(reg_addr + 4, pcie_index_offset);
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
1232
writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset);
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
1239
writel(0, pcie_index_hi_offset);
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
1270
writel(reg_addr, pcie_index_offset);
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
1272
writel(reg_data, pcie_data_offset);
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
1299
writel(reg_addr, pcie_index_offset);
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
1302
writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset);
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
1305
writel(reg_data, pcie_data_offset);
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
1310
writel(0, pcie_index_hi_offset);
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
1340
writel(reg_addr, pcie_index_offset);
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
1342
writel((u32)(reg_data & 0xffffffffULL), pcie_data_offset);
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
1345
writel(reg_addr + 4, pcie_index_offset);
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
1347
writel((u32)(reg_data >> 32), pcie_data_offset);
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
1374
writel(reg_addr, pcie_index_offset);
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
1377
writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset);
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
1380
writel((u32)(reg_data & 0xffffffffULL), pcie_data_offset);
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
1383
writel(reg_addr + 4, pcie_index_offset);
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
1386
writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset);
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
1389
writel((u32)(reg_data >> 32), pcie_data_offset);
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
1394
writel(0, pcie_index_hi_offset);
drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell_mgr.c
65
writel(v, adev->doorbell.cpu_addr + index);
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
1417
writel(addr, vfi_addr);
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
1418
writel(data, vfi_data);
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
1419
writel(grbm_cntl_data, vfi_grbm_cntl);
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
1420
writel(grbm_idx_data, vfi_grbm_idx);
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
1422
writel(AMDGPU_RLCG_VFI_STAT__BUSY, vfi_stat);
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
1423
writel(cmd, vfi_cmd);
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
1512
writel(v, scratch_reg2);
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
1514
writel(v, ((void __iomem *)adev->rmmio) + (offset * 4));
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
1517
writel(v, scratch_reg3);
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
1519
writel(v, ((void __iomem *)adev->rmmio) + (offset * 4));
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
1527
writel(v, scratch_reg0);
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
1528
writel((offset | flag), scratch_reg1);
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
1530
writel(1, spare_int);
drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c
193
writel(value, db);
drivers/gpu/drm/arm/display/include/malidp_io.h
21
writel(v, (base + (offset >> 2)));
drivers/gpu/drm/arm/display/include/malidp_io.h
27
writel(lower_32_bits(v), (base + (offset >> 2)));
drivers/gpu/drm/arm/display/include/malidp_io.h
28
writel(upper_32_bits(v), (base + (offset >> 2) + 1));
drivers/gpu/drm/arm/hdlcd_drv.h
30
writel(value, hdlcd->mmio + reg);
drivers/gpu/drm/arm/malidp_hw.h
269
writel(value, hwdev->regs + reg);
drivers/gpu/drm/armada/armada_crtc.c
233
writel(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA);
drivers/gpu/drm/armada/armada_crtc.c
241
writel(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA);
drivers/gpu/drm/armada/armada_crtc.c
243
writel(0, dcrtc->base + LCD_SPU_IRQ_ISR);
drivers/gpu/drm/armada/armada_debugfs.c
82
writel(v, dcrtc->base + reg);
drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c
110
writel(ctrl1, priv->base + CRT_CTRL1);
drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c
113
writel(CRT_H_TOTAL(m->htotal - 1) | CRT_H_DE(m->hdisplay - 1),
drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c
115
writel(CRT_H_RS_START(m->hsync_start - 1) | CRT_H_RS_END(m->hsync_end),
drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c
120
writel(CRT_V_TOTAL(m->vtotal - 1) | CRT_V_DE(m->vdisplay - 1),
drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c
122
writel(CRT_V_RS_START(m->vsync_start) | CRT_V_RS_END(m->vsync_end),
drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c
132
writel(CRT_DISP_OFFSET(d_offset) | CRT_TERM_COUNT(t_count),
drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c
139
writel(priv->throd_val, priv->base + CRT_THROD);
drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c
190
writel(gem->dma_addr, priv->base + CRT_ADDR);
drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c
199
writel(reg | CRT_CTRL_VERTICAL_INTR_STS, priv->base + CRT_CTRL1);
drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c
202
writel(reg, priv->base + CRT_CTRL1);
drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c
213
writel(reg, priv->base + CRT_CTRL1);
drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c
216
writel(reg | CRT_CTRL_VERTICAL_INTR_STS, priv->base + CRT_CTRL1);
drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c
52
writel(ctrl1, priv->base + CRT_CTRL1);
drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c
65
writel(ctrl1 | CRT_CTRL_EN, priv->base + CRT_CTRL1);
drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c
66
writel(ctrl2 | CRT_CTRL_DAC_EN, priv->base + CRT_CTRL2);
drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c
74
writel(ctrl1 & ~CRT_CTRL_EN, priv->base + CRT_CTRL1);
drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c
75
writel(ctrl2 & ~CRT_CTRL_DAC_EN, priv->base + CRT_CTRL2);
drivers/gpu/drm/aspeed/aspeed_gfx_drv.c
134
writel(reg, priv->base + priv->int_clr_reg);
drivers/gpu/drm/aspeed/aspeed_gfx_drv.c
202
writel(0, priv->base + CRT_CTRL1);
drivers/gpu/drm/aspeed/aspeed_gfx_drv.c
203
writel(0, priv->base + CRT_CTRL2);
drivers/gpu/drm/ast/ast_cursor.c
110
writel(csum, dst);
drivers/gpu/drm/ast/ast_cursor.c
111
writel(width, dst + AST_HWC_SIGNATURE_SizeX);
drivers/gpu/drm/ast/ast_cursor.c
112
writel(height, dst + AST_HWC_SIGNATURE_SizeY);
drivers/gpu/drm/ast/ast_cursor.c
113
writel(0, dst + AST_HWC_SIGNATURE_HOTSPOTX);
drivers/gpu/drm/ast/ast_cursor.c
114
writel(0, dst + AST_HWC_SIGNATURE_HOTSPOTY);
drivers/gpu/drm/ast/ast_cursor.c
284
writel(plane_state->crtc_x, sig + AST_HWC_SIGNATURE_X);
drivers/gpu/drm/ast/ast_cursor.c
285
writel(plane_state->crtc_y, sig + AST_HWC_SIGNATURE_Y);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
1017
writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
102
writel(INT_POL1 | INT_POL0, dp->reg_base + ANALOGIX_DP_INT_CTL);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
1021
writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
1023
writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
1025
writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
1030
writel(reg, dp->reg_base + ANALOGIX_DP_BUF_DATA_0 +
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
1042
writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
105
writel(0xff, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_1);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
106
writel(0x4f, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_2);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
1061
writel(RPLY_RECEIV, dp->reg_base + ANALOGIX_DP_INT_STA);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
1069
writel(AUX_ERR, dp->reg_base + ANALOGIX_DP_INT_STA);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
107
writel(0xe0, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_3);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
108
writel(0xe7, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_4);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
109
writel(0x63, dp->reg_base + ANALOGIX_DP_INT_STA);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
112
writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_1);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
113
writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_2);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
114
writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_3);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
115
writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
116
writel(0x00, dp->reg_base + ANALOGIX_DP_INT_STA_MASK);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
134
writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
139
writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
145
writel(0x0, dp->reg_base + ANALOGIX_DP_SYS_CTL_1);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
146
writel(0x40, dp->reg_base + ANALOGIX_DP_SYS_CTL_2);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
147
writel(0x0, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
148
writel(0x0, dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
150
writel(0x0, dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
151
writel(0x0, dp->reg_base + ANALOGIX_DP_HDCP_CTL);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
153
writel(0x5e, dp->reg_base + ANALOGIX_DP_HPD_DEGLITCH_L);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
154
writel(0x1a, dp->reg_base + ANALOGIX_DP_HPD_DEGLITCH_H);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
156
writel(0x10, dp->reg_base + ANALOGIX_DP_LINK_DEBUG_CTL);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
158
writel(0x0, dp->reg_base + ANALOGIX_DP_PHY_TEST);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
160
writel(0x0, dp->reg_base + ANALOGIX_DP_VIDEO_FIFO_THRD);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
161
writel(0x20, dp->reg_base + ANALOGIX_DP_AUDIO_MARGIN);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
163
writel(0x4, dp->reg_base + ANALOGIX_DP_M_VID_GEN_FILTER_TH);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
164
writel(0x2, dp->reg_base + ANALOGIX_DP_M_AUD_GEN_FILTER_TH);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
166
writel(0x00000101, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
171
writel(RESET_DP_TX, dp->reg_base + ANALOGIX_DP_TX_SW_RESET);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
180
writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_1);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
183
writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_2);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
186
writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_3);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
189
writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
192
writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA_MASK);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
202
writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
206
writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA_MASK);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
215
writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
218
writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA_MASK);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
246
writel(reg, dp->reg_base + pd_addr);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
272
writel(reg, dp->reg_base + phy_pd_addr);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
282
writel(reg, dp->reg_base + phy_pd_addr);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
292
writel(reg, dp->reg_base + phy_pd_addr);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
302
writel(reg, dp->reg_base + phy_pd_addr);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
312
writel(reg, dp->reg_base + phy_pd_addr);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
331
writel(reg, dp->reg_base + phy_pd_addr);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
338
writel(reg, dp->reg_base + phy_pd_addr);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
34
writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
341
writel(reg, dp->reg_base + phy_pd_addr);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
344
writel(reg, dp->reg_base + phy_pd_addr);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
347
writel(0x00, dp->reg_base + phy_pd_addr);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
362
writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_1);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
366
writel(reg, dp->reg_base + ANALOGIX_DP_DEBUG_CTL);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
375
writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
38
writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
387
writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_4);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
390
writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
404
writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
413
writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
450
writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
459
writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
477
writel(reg, dp->reg_base + ANALOGIX_DP_AUX_HW_RETRY_CTL);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
48
writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
481
writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_DEFER_CTL);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
486
writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
511
writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
521
writel(reg, dp->reg_base + ANALOGIX_DP_LINK_BW_SET);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
551
writel(reg, dp->reg_base + ANALOGIX_DP_LANE_COUNT_SET);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
580
writel(dp->link_train.training_lane[lane],
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
62
writel(reg, dp->reg_base + ANALOGIX_DP_LANE_MAP);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
620
writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
624
writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
636
writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
640
writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
644
writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
648
writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
654
writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
667
writel(reg, dp->reg_base + ANALOGIX_DP_PHY_TEST);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
673
writel(reg, dp->reg_base + ANALOGIX_DP_PHY_TEST);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
681
writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_1);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
684
writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_1);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
687
writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_2);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
690
writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
693
writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_8);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
70
writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_1);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
704
writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_2);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
713
writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
721
writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_1);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
73
writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_2);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
731
writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_2);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
753
writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
755
writel(reg, dp->reg_base + ANALOGIX_DP_M_VID_0);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
757
writel(reg, dp->reg_base + ANALOGIX_DP_M_VID_1);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
759
writel(reg, dp->reg_base + ANALOGIX_DP_M_VID_2);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
762
writel(reg, dp->reg_base + ANALOGIX_DP_N_VID_0);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
764
writel(reg, dp->reg_base + ANALOGIX_DP_N_VID_1);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
766
writel(reg, dp->reg_base + ANALOGIX_DP_N_VID_2);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
770
writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
772
writel(0x00, dp->reg_base + ANALOGIX_DP_N_VID_0);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
773
writel(0x80, dp->reg_base + ANALOGIX_DP_N_VID_1);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
774
writel(0x00, dp->reg_base + ANALOGIX_DP_N_VID_2);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
785
writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
789
writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
80
writel(reg, dp->reg_base + ANALOGIX_DP_PLL_REG_1);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
801
writel(reg, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
806
writel(reg, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
81
writel(0x95, dp->reg_base + ANALOGIX_DP_PLL_REG_2);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
816
writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
82
writel(0x40, dp->reg_base + ANALOGIX_DP_PLL_REG_3);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
824
writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
83
writel(0x58, dp->reg_base + ANALOGIX_DP_PLL_REG_4);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
84
writel(0x22, dp->reg_base + ANALOGIX_DP_PLL_REG_5);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
846
writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
851
writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
856
writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
861
writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
864
writel(reg, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
873
writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
88
writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_3);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
882
writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
887
writel(PSR_VID_CRC_ENABLE, dp->reg_base + ANALOGIX_DP_CRC_CON);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
913
writel(val, dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
916
writel(PSR_FRAME_UP_TYPE_BURST | PSR_CRC_SEL_HARDWARE,
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
92
writel(reg, dp->reg_base + ANALOGIX_DP_PLL_FILTER_CTL_1);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
920
writel(vsc->sdp_header.HB0, dp->reg_base + ANALOGIX_DP_SPD_HB0);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
921
writel(vsc->sdp_header.HB1, dp->reg_base + ANALOGIX_DP_SPD_HB1);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
922
writel(vsc->sdp_header.HB2, dp->reg_base + ANALOGIX_DP_SPD_HB2);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
923
writel(vsc->sdp_header.HB3, dp->reg_base + ANALOGIX_DP_SPD_HB3);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
926
writel(0x00, dp->reg_base + ANALOGIX_DP_SPD_PB0);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
927
writel(0x16, dp->reg_base + ANALOGIX_DP_SPD_PB1);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
928
writel(0xCE, dp->reg_base + ANALOGIX_DP_SPD_PB2);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
929
writel(0x5D, dp->reg_base + ANALOGIX_DP_SPD_PB3);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
932
writel(vsc->db[0], dp->reg_base + ANALOGIX_DP_VSC_SHADOW_DB0);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
933
writel(vsc->db[1], dp->reg_base + ANALOGIX_DP_VSC_SHADOW_DB1);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
938
writel(val, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
943
writel(val, dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
948
writel(val, dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
96
writel(reg, dp->reg_base + ANALOGIX_DP_TX_AMP_TUNING_CTL);
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
989
writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL);
drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
1103
writel(ctl, dsi->regs + DIRECT_CMD_STS_CTL);
drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
1169
writel(readl(dsi->regs + MCTL_MAIN_DATA_CTL) | ctl,
drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
1172
writel(cmd, dsi->regs + DIRECT_CMD_MAIN_SETTINGS);
drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
1182
writel(val, dsi->regs + DIRECT_CMD_WRDATA);
drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
1186
writel(wait, dsi->regs + DIRECT_CMD_STS_CLR);
drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
1187
writel(wait, dsi->regs + DIRECT_CMD_STS_CTL);
drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
1189
writel(0, dsi->regs + DIRECT_CMD_SEND);
drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
1195
writel(wait, dsi->regs + DIRECT_CMD_STS_CLR);
drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
1196
writel(0, dsi->regs + DIRECT_CMD_STS_CTL);
drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
1198
writel(readl(dsi->regs + MCTL_MAIN_DATA_CTL) & ~ctl,
drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
1316
writel(0, dsi->regs + MCTL_MAIN_DATA_CTL);
drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
1317
writel(0, dsi->regs + MCTL_MAIN_EN);
drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
1318
writel(0, dsi->regs + MCTL_MAIN_PHY_CTL);
drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
1328
writel(0, dsi->regs + MCTL_MAIN_STS_CTL);
drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
1329
writel(0, dsi->regs + MCTL_DPHY_ERR_CTL1);
drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
1330
writel(0, dsi->regs + CMD_MODE_STS_CTL);
drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
1331
writel(0, dsi->regs + DIRECT_CMD_STS_CTL);
drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
1332
writel(0, dsi->regs + DIRECT_CMD_RD_STS_CTL);
drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
1333
writel(0, dsi->regs + VID_MODE_STS_CTL);
drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
1334
writel(0, dsi->regs + TVG_STS_CTL);
drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
1335
writel(0, dsi->regs + DPI_IRQ_EN);
drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
618
writel(val, dsi->regs + MCTL_MAIN_DATA_CTL);
drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
621
writel(val, dsi->regs + MCTL_MAIN_EN);
drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
645
writel(DPHY_CMN_PSO | DPHY_PLL_PSO | DPHY_ALL_D_PDN | DPHY_C_PDN |
drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
655
writel(PLL_LOCKED, dsi->regs + MCTL_MAIN_STS_CLR);
drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
656
writel(DPHY_CMN_PSO | DPHY_ALL_D_PDN | DPHY_C_PDN | DPHY_CMN_PDN,
drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
661
writel(DPHY_CMN_PSO | DPHY_ALL_D_PDN | DPHY_C_PDN | DPHY_CMN_PDN |
drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
684
writel(val, dsi->regs + MCTL_MAIN_PHY_CTL);
drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
689
writel(CLK_LANE_ULPOUT_TIME(ulpout) | DATA_LANE_ULPOUT_TIME(ulpout),
drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
692
writel(LINK_EN, dsi->regs + MCTL_MAIN_DATA_CTL);
drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
698
writel(val, dsi->regs + MCTL_MAIN_EN);
drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
771
writel(HBP_LEN(dsi_cfg.hbp) | HSA_LEN(dsi_cfg.hsa),
drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
773
writel(HFP_LEN(dsi_cfg.hfp) | HACT_LEN(dsi_cfg.hact),
drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
776
writel(VBP_LEN(mode->crtc_vtotal - mode->crtc_vsync_end - 1) |
drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
780
writel(mode->crtc_vdisplay, dsi->regs + VID_VSIZE2);
drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
785
writel(BLK_LINE_PULSE_PKT_LEN(tmp), dsi->regs + VID_BLKSIZE2);
drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
787
writel(MAX_LINE_LIMIT(tmp - DSI_NULL_FRAME_OVERHEAD),
drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
792
writel(BLK_LINE_EVENT_PKT_LEN(tmp), dsi->regs + VID_BLKSIZE1);
drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
794
writel(MAX_LINE_LIMIT(tmp - DSI_NULL_FRAME_OVERHEAD),
drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
812
writel(REG_WAKEUP_TIME(reg_wakeup) | REG_LINE_DURATION(tmp),
drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
833
writel(CLK_DIV(div) | HSTX_TIMEOUT(tmp),
drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
836
writel(LPRX_TIMEOUT(tmp), dsi->regs + MCTL_DPHY_TIMEOUT2);
drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
873
writel(tmp, dsi->regs + VID_MAIN_CTL);
drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
885
writel(tmp, dsi->regs + MCTL_MAIN_DATA_CTL);
drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
888
writel(tmp, dsi->regs + MCTL_MAIN_EN);
drivers/gpu/drm/bridge/cadence/cdns-dsi-j721e.c
38
writel(DSI_WRAP_DPI_0_EN, dsi->j721e_regs + DSI_WRAP_DPI_CONTROL);
drivers/gpu/drm/bridge/cadence/cdns-dsi-j721e.c
44
writel(0, dsi->j721e_regs + DSI_WRAP_DPI_CONTROL);
drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
103
writel(val, mhdp->regs + CDNS_MAILBOX_TX_DATA);
drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
2050
writel(~0, mhdp->regs + CDNS_APB_INT_MASK);
drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
2459
writel(rate % 1000000, mhdp->regs + CDNS_SW_CLK_L);
drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
2460
writel(rate / 1000000, mhdp->regs + CDNS_SW_CLK_H);
drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
2464
writel(~0, mhdp->regs + CDNS_APB_INT_MASK);
drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
62
writel(readl(mhdp->regs + CDNS_APB_INT_MASK) &
drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
653
writel(CDNS_CPU_STALL, mhdp->regs + CDNS_APB_CTRL);
drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
658
writel(0, mhdp->regs + CDNS_APB_CTRL);
drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
71
writel(readl(mhdp->regs + CDNS_APB_INT_MASK) |
drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-hdcp.c
46
writel(val, mhdp->sapb_regs + CDNS_MAILBOX_TX_DATA);
drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-j721e.c
58
writel(DPTX_SRC_VIF_0_EN | DPTX_SRC_VIF_0_SEL_DPI2,
drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-j721e.c
65
writel(0, mhdp->j721e_regs + DPTX_DSC_CFG);
drivers/gpu/drm/bridge/imx/imx8mp-hdmi-pvi.c
88
writel(val, pvi->regs + HTX_PVI_CTRL);
drivers/gpu/drm/bridge/imx/imx8mp-hdmi-pvi.c
96
writel(0x0, pvi->regs + HTX_PVI_CTRL);
drivers/gpu/drm/bridge/imx/imx8qxp-pixel-combiner.c
82
writel(value, pc->base + offset);
drivers/gpu/drm/bridge/samsung-dsim.c
706
writel(val, dsi->reg_base + dsi->driver_data->reg_ofs[idx]);
drivers/gpu/drm/bridge/samsung-dsim.c
821
writel(driver_data->reg_values[PLL_TIMER],
drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
309
writel(val, dsi->base + reg);
drivers/gpu/drm/etnaviv/etnaviv_gpu.h
172
writel(data, gpu->mmio + reg);
drivers/gpu/drm/etnaviv/etnaviv_gpu.h
199
writel(data, gpu->mmio + gpu_fix_power_address(gpu, reg));
drivers/gpu/drm/exynos/exynos5433_drm_decon.c
101
writel(val, ctx->addr + reg);
drivers/gpu/drm/exynos/exynos5433_drm_decon.c
115
writel(val, ctx->addr + DECON_VIDINTCON0);
drivers/gpu/drm/exynos/exynos5433_drm_decon.c
132
writel(0, ctx->addr + DECON_VIDINTCON0);
drivers/gpu/drm/exynos/exynos5433_drm_decon.c
183
writel(TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F |
drivers/gpu/drm/exynos/exynos5433_drm_decon.c
189
writel(TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F | TRIGCON_HWTRIGMASK
drivers/gpu/drm/exynos/exynos5433_drm_decon.c
225
writel(val, ctx->addr + DECON_VIDOUTCON0);
drivers/gpu/drm/exynos/exynos5433_drm_decon.c
233
writel(val, ctx->addr + DECON_VIDTCON2);
drivers/gpu/drm/exynos/exynos5433_drm_decon.c
242
writel(val, ctx->addr + DECON_VIDTCON00);
drivers/gpu/drm/exynos/exynos5433_drm_decon.c
246
writel(val, ctx->addr + DECON_VIDTCON01);
drivers/gpu/drm/exynos/exynos5433_drm_decon.c
252
writel(val, ctx->addr + DECON_VIDTCON10);
drivers/gpu/drm/exynos/exynos5433_drm_decon.c
256
writel(val, ctx->addr + DECON_VIDTCON11);
drivers/gpu/drm/exynos/exynos5433_drm_decon.c
417
writel(val, ctx->addr + DECON_VIDOSDxA(win));
drivers/gpu/drm/exynos/exynos5433_drm_decon.c
421
writel(val, ctx->addr + DECON_VIDOSDxB(win));
drivers/gpu/drm/exynos/exynos5433_drm_decon.c
424
writel(val, ctx->addr + DECON_VIDOSDxA(win));
drivers/gpu/drm/exynos/exynos5433_drm_decon.c
428
writel(val, ctx->addr + DECON_VIDOSDxB(win));
drivers/gpu/drm/exynos/exynos5433_drm_decon.c
433
writel(val, ctx->addr + DECON_VIDOSDxC(win));
drivers/gpu/drm/exynos/exynos5433_drm_decon.c
437
writel(val, ctx->addr + DECON_VIDOSDxD(win));
drivers/gpu/drm/exynos/exynos5433_drm_decon.c
439
writel(dma_addr, ctx->addr + DECON_VIDW0xADD0B0(win));
drivers/gpu/drm/exynos/exynos5433_drm_decon.c
442
writel(val, ctx->addr + DECON_VIDW0xADD1B0(win));
drivers/gpu/drm/exynos/exynos5433_drm_decon.c
450
writel(val, ctx->addr + DECON_VIDW0xADD2(win));
drivers/gpu/drm/exynos/exynos5433_drm_decon.c
491
writel(0, ctx->addr + DECON_VIDCON0);
drivers/gpu/drm/exynos/exynos5433_drm_decon.c
495
writel(VIDCON0_SWRESET, ctx->addr + DECON_VIDCON0);
drivers/gpu/drm/exynos/exynos5433_drm_decon.c
508
writel(VIDCON0_CLKVALUP | VIDCON0_VLCKFREE, ctx->addr + DECON_VIDCON0);
drivers/gpu/drm/exynos/exynos5433_drm_decon.c
511
writel(VIDCON1_VCLK_RUN_VDEN_DISABLE, ctx->addr + DECON_VIDCON1);
drivers/gpu/drm/exynos/exynos5433_drm_decon.c
512
writel(CRCCTRL_CRCEN | CRCCTRL_CRCSTART_F | CRCCTRL_CRCCLKEN,
drivers/gpu/drm/exynos/exynos5433_drm_decon.c
700
writel(val, ctx->addr + DECON_VIDINTCON1);
drivers/gpu/drm/exynos/exynos7_drm_decon.c
130
writel(val, ctx->regs + SHADOWCON);
drivers/gpu/drm/exynos/exynos7_drm_decon.c
160
writel(val, ctx->regs + WINCON(win));
drivers/gpu/drm/exynos/exynos7_drm_decon.c
169
writel(val, ctx->regs + DECON_UPDATE);
drivers/gpu/drm/exynos/exynos7_drm_decon.c
222
writel(val, ctx->regs + VIDTCON0);
drivers/gpu/drm/exynos/exynos7_drm_decon.c
225
writel(val, ctx->regs + VIDTCON1);
drivers/gpu/drm/exynos/exynos7_drm_decon.c
234
writel(val, ctx->regs + VIDTCON2);
drivers/gpu/drm/exynos/exynos7_drm_decon.c
237
writel(val, ctx->regs + VIDTCON3);
drivers/gpu/drm/exynos/exynos7_drm_decon.c
243
writel(val, ctx->regs + VIDTCON4);
drivers/gpu/drm/exynos/exynos7_drm_decon.c
245
writel(mode->vdisplay - 1, ctx->regs + LINECNT_OP_THRESHOLD);
drivers/gpu/drm/exynos/exynos7_drm_decon.c
252
writel(val, ctx->regs + VIDCON0);
drivers/gpu/drm/exynos/exynos7_drm_decon.c
257
writel(val, ctx->regs + VCLKCON1);
drivers/gpu/drm/exynos/exynos7_drm_decon.c
258
writel(val, ctx->regs + VCLKCON2);
drivers/gpu/drm/exynos/exynos7_drm_decon.c
263
writel(val, ctx->regs + DECON_UPDATE);
drivers/gpu/drm/exynos/exynos7_drm_decon.c
282
writel(val, ctx->regs + VIDINTCON0);
drivers/gpu/drm/exynos/exynos7_drm_decon.c
300
writel(val, ctx->regs + VIDINTCON0);
drivers/gpu/drm/exynos/exynos7_drm_decon.c
374
writel(val, ctx->regs + WINCON(win));
drivers/gpu/drm/exynos/exynos7_drm_decon.c
386
writel(keycon0, ctx->regs + WKEYCON0_BASE(win));
drivers/gpu/drm/exynos/exynos7_drm_decon.c
387
writel(keycon1, ctx->regs + WKEYCON1_BASE(win));
drivers/gpu/drm/exynos/exynos7_drm_decon.c
427
writel(val, ctx->regs + VIDW_BUF_START(vidw_addr0_base, win));
drivers/gpu/drm/exynos/exynos7_drm_decon.c
432
writel(fb->width + padding, ctx->regs + VIDW_WHOLE_X(win));
drivers/gpu/drm/exynos/exynos7_drm_decon.c
433
writel(fb->height, ctx->regs + VIDW_WHOLE_Y(win));
drivers/gpu/drm/exynos/exynos7_drm_decon.c
436
writel(state->src.x, ctx->regs + VIDW_OFFSET_X(win));
drivers/gpu/drm/exynos/exynos7_drm_decon.c
437
writel(state->src.y, ctx->regs + VIDW_OFFSET_Y(win));
drivers/gpu/drm/exynos/exynos7_drm_decon.c
446
writel(val, ctx->regs + VIDOSD_A(win));
drivers/gpu/drm/exynos/exynos7_drm_decon.c
457
writel(val, ctx->regs + VIDOSD_B(win));
drivers/gpu/drm/exynos/exynos7_drm_decon.c
467
writel(alpha, ctx->regs + VIDOSD_C(win));
drivers/gpu/drm/exynos/exynos7_drm_decon.c
473
writel(alpha, ctx->regs + VIDOSD_D(win));
drivers/gpu/drm/exynos/exynos7_drm_decon.c
485
writel(val, ctx->regs + WINCON(win));
drivers/gpu/drm/exynos/exynos7_drm_decon.c
492
writel(val, ctx->regs + DECON_UPDATE);
drivers/gpu/drm/exynos/exynos7_drm_decon.c
508
writel(val, ctx->regs + WINCON(win));
drivers/gpu/drm/exynos/exynos7_drm_decon.c
512
writel(val, ctx->regs + DECON_UPDATE);
drivers/gpu/drm/exynos/exynos7_drm_decon.c
529
writel(VIDCON0_SWRESET, ctx->regs + VIDCON0);
drivers/gpu/drm/exynos/exynos7_drm_decon.c
534
writel(val, ctx->regs + VIDOUTCON0);
drivers/gpu/drm/exynos/exynos7_drm_decon.c
536
writel(VCLKCON0_CLKVALUP | VCLKCON0_VCLKFREE, ctx->regs + VCLKCON0);
drivers/gpu/drm/exynos/exynos7_drm_decon.c
539
writel(VIDCON1_VCLK_HOLD, ctx->regs + VIDCON1(0));
drivers/gpu/drm/exynos/exynos7_drm_decon.c
599
writel(clear_bit, ctx->regs + VIDINTCON1);
drivers/gpu/drm/exynos/exynos_drm_fimc.c
120
writel(val, ctx->regs + reg);
drivers/gpu/drm/exynos/exynos_drm_fimc.c
127
writel(readl(r) | bits, r);
drivers/gpu/drm/exynos/exynos_drm_fimc.c
134
writel(readl(r) & ~bits, r);
drivers/gpu/drm/exynos/exynos_drm_fimd.c
1007
writel(reg, timing_base + TRIGCON);
drivers/gpu/drm/exynos/exynos_drm_fimd.c
1060
writel(val, ctx->regs + DP_MIE_CLKCON);
drivers/gpu/drm/exynos/exynos_drm_fimd.c
1088
writel(clear_bit, ctx->regs + VIDINTCON1);
drivers/gpu/drm/exynos/exynos_drm_fimd.c
260
writel(val, ctx->regs + reg);
drivers/gpu/drm/exynos/exynos_drm_fimd.c
289
writel(val, ctx->regs + VIDINTCON0);
drivers/gpu/drm/exynos/exynos_drm_fimd.c
315
writel(val, ctx->regs + VIDINTCON0);
drivers/gpu/drm/exynos/exynos_drm_fimd.c
348
writel(val, ctx->regs + WINCON(win));
drivers/gpu/drm/exynos/exynos_drm_fimd.c
362
writel(val, ctx->regs + SHADOWCON);
drivers/gpu/drm/exynos/exynos_drm_fimd.c
477
writel(val, timing_base + TRIGCON);
drivers/gpu/drm/exynos/exynos_drm_fimd.c
497
writel(val, timing_base + I80IFCONFAx(0));
drivers/gpu/drm/exynos/exynos_drm_fimd.c
500
writel(0, timing_base + I80IFCONFBx(0));
drivers/gpu/drm/exynos/exynos_drm_fimd.c
522
writel(vidcon1, ctx->regs + driver_data->timing_base + VIDCON1);
drivers/gpu/drm/exynos/exynos_drm_fimd.c
532
writel(val, ctx->regs + driver_data->timing_base + VIDTCON0);
drivers/gpu/drm/exynos/exynos_drm_fimd.c
542
writel(val, ctx->regs + driver_data->timing_base + VIDTCON1);
drivers/gpu/drm/exynos/exynos_drm_fimd.c
546
writel(ctx->vidout_con, timing_base + VIDOUT_CON);
drivers/gpu/drm/exynos/exynos_drm_fimd.c
576
writel(val, ctx->regs + driver_data->timing_base + VIDTCON2);
drivers/gpu/drm/exynos/exynos_drm_fimd.c
593
writel(val, ctx->regs + VIDCON0);
drivers/gpu/drm/exynos/exynos_drm_fimd.c
649
writel(val, ctx->regs + VIDOSD_C(win));
drivers/gpu/drm/exynos/exynos_drm_fimd.c
653
writel(val, ctx->regs + VIDWnALPHA0(win));
drivers/gpu/drm/exynos/exynos_drm_fimd.c
657
writel(val, ctx->regs + VIDWnALPHA1(win));
drivers/gpu/drm/exynos/exynos_drm_fimd.c
726
writel(WIN_RGB_ORDER_REVERSE, ctx->regs + WIN_RGB_ORDER(win));
drivers/gpu/drm/exynos/exynos_drm_fimd.c
729
writel(WIN_RGB_ORDER_FORWARD, ctx->regs + WIN_RGB_ORDER(win));
drivers/gpu/drm/exynos/exynos_drm_fimd.c
763
writel(keycon0, ctx->regs + WKEYCON0_BASE(win));
drivers/gpu/drm/exynos/exynos_drm_fimd.c
764
writel(keycon1, ctx->regs + WKEYCON1_BASE(win));
drivers/gpu/drm/exynos/exynos_drm_fimd.c
802
writel(val, ctx->regs + reg);
drivers/gpu/drm/exynos/exynos_drm_fimd.c
854
writel(val, ctx->regs + VIDWx_BUF_START(win, 0));
drivers/gpu/drm/exynos/exynos_drm_fimd.c
859
writel(val, ctx->regs + VIDWx_BUF_END(win, 0));
drivers/gpu/drm/exynos/exynos_drm_fimd.c
874
writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0));
drivers/gpu/drm/exynos/exynos_drm_fimd.c
881
writel(val, ctx->regs + VIDOSD_A(win));
drivers/gpu/drm/exynos/exynos_drm_fimd.c
893
writel(val, ctx->regs + VIDOSD_B(win));
drivers/gpu/drm/exynos/exynos_drm_fimd.c
905
writel(val, ctx->regs + offset);
drivers/gpu/drm/exynos/exynos_drm_fimd.c
982
writel(0, ctx->regs + VIDCON0);
drivers/gpu/drm/exynos/exynos_drm_g2d.c
267
writel(G2D_R | G2D_SFRCLEAR, g2d->regs + G2D_SOFT_RESET);
drivers/gpu/drm/exynos/exynos_drm_gsc.c
66
#define gsc_write(cfg, offset) writel(cfg, ctx->regs + (offset))
drivers/gpu/drm/exynos/exynos_drm_mic.c
142
writel(MIC_SW_RST, mic->reg + MIC_OP);
drivers/gpu/drm/exynos/exynos_drm_mic.c
163
writel(reg, mic->reg + MIC_V_TIMING_0);
drivers/gpu/drm/exynos/exynos_drm_mic.c
167
writel(reg, mic->reg + MIC_V_TIMING_1);
drivers/gpu/drm/exynos/exynos_drm_mic.c
172
writel(reg, mic->reg + MIC_INPUT_TIMING_0);
drivers/gpu/drm/exynos/exynos_drm_mic.c
176
writel(reg, mic->reg + MIC_INPUT_TIMING_1);
drivers/gpu/drm/exynos/exynos_drm_mic.c
187
writel(reg, mic->reg + MIC_IMG_SIZE);
drivers/gpu/drm/exynos/exynos_drm_mic.c
198
writel(reg, mic->reg + MIC_2D_OUTPUT_TIMING_2);
drivers/gpu/drm/exynos/exynos_drm_mic.c
204
writel(reg, mic->reg + MIC_2D_OUTPUT_TIMING_0);
drivers/gpu/drm/exynos/exynos_drm_mic.c
208
writel(reg, mic->reg + MIC_2D_OUTPUT_TIMING_1);
drivers/gpu/drm/exynos/exynos_drm_mic.c
228
writel(reg, mic->reg + MIC_OP);
drivers/gpu/drm/exynos/exynos_drm_rotator.c
36
#define rot_write(cfg, offset) writel(cfg, rot->regs + (offset))
drivers/gpu/drm/exynos/exynos_drm_scaler.c
28
#define scaler_write(cfg, offset) writel(cfg, scaler->regs + (offset))
drivers/gpu/drm/exynos/exynos_hdmi.c
1437
writel(v, hdata->regs_hdmiphy + HDMIPHY5433_MODE_SET_DONE);
drivers/gpu/drm/exynos/exynos_hdmi.c
692
writel(value, hdata->regs + hdmi_map_reg(hdata, reg_id));
drivers/gpu/drm/exynos/exynos_hdmi.c
701
writel(val & 0xff, hdata->regs + reg_id);
drivers/gpu/drm/exynos/exynos_hdmi.c
711
writel(*buf++, hdata->regs + reg_id);
drivers/gpu/drm/exynos/exynos_hdmi.c
722
writel(value, hdata->regs + reg_id);
drivers/gpu/drm/exynos/exynos_hdmi.c
741
writel(buf[i], hdata->regs_hdmiphy +
drivers/gpu/drm/exynos/exynos_mixer.c
193
writel(val, ctx->vp_regs + reg_id);
drivers/gpu/drm/exynos/exynos_mixer.c
202
writel(val, ctx->vp_regs + reg_id);
drivers/gpu/drm/exynos/exynos_mixer.c
213
writel(val, ctx->mixer_regs + reg_id);
drivers/gpu/drm/exynos/exynos_mixer.c
222
writel(val, ctx->mixer_regs + reg_id);
drivers/gpu/drm/gma500/oaktrail_hdmi.c
250
writel(0xff11d118, base + 0x0c);
drivers/gpu/drm/gma500/oaktrail_hdmi.c
251
writel(0x7fffffdf, base + 0x80);
drivers/gpu/drm/gma500/oaktrail_hdmi.c
252
writel(0x42005, base + 0x0);
drivers/gpu/drm/gma500/oaktrail_hdmi.c
256
writel(0xff11d118, base + 0x0c);
drivers/gpu/drm/gma500/oaktrail_hdmi.c
257
writel(0x7fffffff, base + 0x80);
drivers/gpu/drm/gma500/oaktrail_hdmi.c
258
writel(0x42005, base + 0x0);
drivers/gpu/drm/gma500/oaktrail_hdmi.c
41
#define HDMI_WRITE(reg, val) writel(val, hdmi_dev->regs + (reg))
drivers/gpu/drm/gma500/oaktrail_hdmi_i2c.c
268
writel((temp | 0x00000a00), (base + 0x44));
drivers/gpu/drm/gma500/oaktrail_hdmi_i2c.c
39
#define HDMI_WRITE(reg, val) writel(val, hdmi_dev->regs + (reg))
drivers/gpu/drm/hisilicon/hibmc/dp/dp_aux.c
134
writel(0, dp->base + HIBMC_DP_AUX_WR_DATA0);
drivers/gpu/drm/hisilicon/hibmc/dp/dp_aux.c
135
writel(0, dp->base + HIBMC_DP_AUX_WR_DATA1);
drivers/gpu/drm/hisilicon/hibmc/dp/dp_aux.c
136
writel(0, dp->base + HIBMC_DP_AUX_WR_DATA2);
drivers/gpu/drm/hisilicon/hibmc/dp/dp_aux.c
137
writel(0, dp->base + HIBMC_DP_AUX_WR_DATA3);
drivers/gpu/drm/hisilicon/hibmc/dp/dp_aux.c
142
writel(aux_cmd, dp->base + HIBMC_DP_AUX_CMD_ADDR);
drivers/gpu/drm/hisilicon/hibmc/dp/dp_aux.c
62
writel(value, dp->base + HIBMC_DP_AUX_WR_DATA0 + i * HIBMC_BYTES_IN_U32);
drivers/gpu/drm/hisilicon/hibmc/dp/dp_comm.h
63
writel(reg_value, addr); \
drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c
136
writel(HIBMC_DP_MSA1, dp->base + HIBMC_DP_VIDEO_MSA1);
drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c
137
writel(HIBMC_DP_MSA2, dp->base + HIBMC_DP_VIDEO_MSA2);
drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c
181
writel(0, dp_dev->base + HIBMC_DP_INTR_ENABLE);
drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c
182
writel(HIBMC_DP_INT_RST, dp_dev->base + HIBMC_DP_INTR_ORIGINAL_STATUS);
drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c
184
writel(0, dp_dev->base + HIBMC_DP_COLOR_BAR_CTRL);
drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c
186
writel(0, dp_dev->base + HIBMC_DP_DPTX_RST_CTRL);
drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c
189
writel(HIBMC_DP_DPTX_RST, dp_dev->base + HIBMC_DP_DPTX_RST_CTRL);
drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c
191
writel(HIBMC_DP_HDCP, dp_dev->base + HIBMC_DP_HDCP_CFG);
drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c
193
writel(HIBMC_DP_CLK_EN, dp_dev->base + HIBMC_DP_DPTX_CLK_CTRL);
drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c
202
writel(HIBMC_DP_INT_ENABLE, dp_dev->base + HIBMC_DP_INTR_ENABLE);
drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c
209
writel(0, dp_dev->base + HIBMC_DP_INTR_ENABLE);
drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c
210
writel(HIBMC_DP_INT_RST, dp_dev->base + HIBMC_DP_INTR_ORIGINAL_STATUS);
drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c
220
writel(HIBMC_DP_HDCP, dp_dev->base + HIBMC_DP_HDCP_CFG);
drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c
221
writel(0, dp_dev->base + HIBMC_DP_INTR_ENABLE);
drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c
222
writel(HIBMC_DP_INT_RST, dp_dev->base + HIBMC_DP_INTR_ORIGINAL_STATUS);
drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c
223
writel(HIBMC_DP_INT_ENABLE, dp_dev->base + HIBMC_DP_INTR_ENABLE);
drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c
224
writel(HIBMC_DP_DPTX_RST, dp_dev->base + HIBMC_DP_DPTX_RST_CTRL);
drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c
225
writel(HIBMC_DP_CLK_EN, dp_dev->base + HIBMC_DP_DPTX_CLK_CTRL);
drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c
234
writel(HIBMC_DP_SYNC_EN_MASK, dp_dev->base + HIBMC_DP_TIMING_SYNC_CTRL);
drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c
236
writel(HIBMC_DP_SYNC_EN_MASK, dp_dev->base + HIBMC_DP_TIMING_SYNC_CTRL);
drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c
239
writel(HIBMC_DP_SYNC_EN_MASK, dp_dev->base + HIBMC_DP_TIMING_SYNC_CTRL);
drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c
241
writel(HIBMC_DP_SYNC_EN_MASK, dp_dev->base + HIBMC_DP_TIMING_SYNC_CTRL);
drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c
322
writel(HIBMC_DP_SYNC_EN_MASK, dp_dev->base + HIBMC_DP_TIMING_SYNC_CTRL);
drivers/gpu/drm/hisilicon/hibmc/dp/dp_serdes.c
28
writel(FIELD_PREP(HIBMC_DP_PMA_TXDEEMPH, cfg[i]),
drivers/gpu/drm/hisilicon/hibmc/dp/dp_serdes.c
44
writel(rate, dp->serdes_base + HIBMC_DP_LANE0_RATE_OFFSET);
drivers/gpu/drm/hisilicon/hibmc/dp/dp_serdes.c
45
writel(rate, dp->serdes_base + HIBMC_DP_LANE1_RATE_OFFSET);
drivers/gpu/drm/hisilicon/hibmc/dp/dp_serdes.c
65
writel(FIELD_PREP(HIBMC_DP_PMA_TXDEEMPH, DP_SERDES_VOL0_PRE0),
drivers/gpu/drm/hisilicon/hibmc/dp/dp_serdes.c
67
writel(FIELD_PREP(HIBMC_DP_PMA_TXDEEMPH, DP_SERDES_VOL0_PRE0),
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c
121
writel(gpu_addr, priv->mmio + HIBMC_CRT_FB_ADDRESS);
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c
126
writel(HIBMC_FIELD(HIBMC_CRT_FB_WIDTH_WIDTH, reg) |
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c
135
writel(reg, priv->mmio + HIBMC_CRT_DISP_CTL);
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c
171
writel(reg, priv->mmio + HIBMC_CRT_DISP_CTL);
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c
261
writel(val, priv->mmio + CRT_PLL1_HS);
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c
264
writel(val, priv->mmio + CRT_PLL1_HS);
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c
266
writel(pll, priv->mmio + CRT_PLL1_HS);
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c
271
writel(val, priv->mmio + CRT_PLL1_HS);
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c
276
writel(val, priv->mmio + CRT_PLL1_HS);
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c
281
writel(val, priv->mmio + CRT_PLL1_HS);
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c
323
writel(pll2, priv->mmio + CRT_PLL2_HS);
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c
332
writel(HIBMC_FIELD(HIBMC_CRT_AUTO_CENTERING_TL_TOP, 0) |
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c
336
writel(HIBMC_FIELD(HIBMC_CRT_AUTO_CENTERING_BR_BOTTOM, y - 1) |
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c
355
writel(ctrl, priv->mmio + HIBMC_CRT_DISP_CTL);
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c
369
writel(format_pll_reg(), priv->mmio + HIBMC_CRT_PLL_CTRL);
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c
370
writel(HIBMC_FIELD(HIBMC_CRT_HORZ_TOTAL_TOTAL, mode->htotal - 1) |
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c
374
writel(HIBMC_FIELD(HIBMC_CRT_HORZ_SYNC_WIDTH, width) |
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c
378
writel(HIBMC_FIELD(HIBMC_CRT_VERT_TOTAL_TOTAL, mode->vtotal - 1) |
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c
382
writel(HIBMC_FIELD(HIBMC_CRT_VERT_SYNC_HEIGHT, height) |
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c
431
writel(HIBMC_RAW_INTERRUPT_EN_VBLANK(1),
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c
441
writel(HIBMC_RAW_INTERRUPT_EN_VBLANK(0),
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c
464
writel(rgb, mmio + HIBMC_CRT_PALETTE + offset);
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c
469
writel(reg, priv->mmio + HIBMC_CRT_DISP_CTL);
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c
188
writel(control_value, mmio + HIBMC_POWER_MODE_CTRL);
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c
214
writel(gate, mmio + gate_reg);
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c
242
writel(reg, priv->mmio + HIBMC_MISC_CTRL);
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c
247
writel(reg, priv->mmio + HIBMC_MISC_CTRL);
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c
46
writel(HIBMC_RAW_INTERRUPT_VBLANK(1),
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c
63
writel(status, priv->mmio + HIBMC_DP_INTCLR);
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_i2c.c
34
writel(tmp_dir, priv->mmio + GPIO_DATA_DIRECTION);
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_i2c.c
39
writel(tmp_data, priv->mmio + GPIO_DATA);
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_i2c.c
42
writel(tmp_dir, priv->mmio + GPIO_DATA_DIRECTION);
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_i2c.c
54
writel(tmp_dir, priv->mmio + GPIO_DATA_DIRECTION);
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_vdac.c
87
writel(reg, priv->mmio + HIBMC_DISPLAY_CONTROL_HISILE);
drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c
318
writel(reg_write, base + PHY_TST_CTRL1);
drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c
319
writel(0x02, base + PHY_TST_CTRL0);
drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c
320
writel(0x00, base + PHY_TST_CTRL0);
drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c
325
writel(val, base + PHY_TST_CTRL1);
drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c
326
writel(0x02, base + PHY_TST_CTRL0);
drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c
327
writel(0x00, base + PHY_TST_CTRL0);
drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c
340
writel(val, base + PHY_IF_CFG);
drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c
346
writel(val, base + CLKMGR_CFG);
drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c
377
writel(0, base + PHY_RSTZ);
drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c
378
writel(0, base + PHY_TST_CTRL0);
drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c
379
writel(1, base + PHY_TST_CTRL0);
drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c
380
writel(0, base + PHY_TST_CTRL0);
drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c
423
writel(PHY_ENABLECLK, base + PHY_RSTZ);
drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c
425
writel(PHY_ENABLECLK | PHY_UNSHUTDOWNZ, base + PHY_RSTZ);
drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c
427
writel(PHY_ENABLECLK | PHY_UNRSTZ | PHY_UNSHUTDOWNZ, base + PHY_RSTZ);
drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c
462
writel(val, base + DPI_COLOR_CODING);
drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c
466
writel(val, base + DPI_CFG_POL);
drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c
495
writel(hsa_time, base + VID_HSA_TIME);
drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c
496
writel(hbp_time, base + VID_HBP_TIME);
drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c
497
writel(hline_time, base + VID_HLINE_TIME);
drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c
499
writel(vsw, base + VID_VSA_LINES);
drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c
500
writel(vbp, base + VID_VBP_LINES);
drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c
501
writel(vfp, base + VID_VFP_LINES);
drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c
502
writel(mode->vdisplay, base + VID_VACTIVE_LINES);
drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c
503
writel(mode->hdisplay, base + VID_PKT_SIZE);
drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c
531
writel(val, base + VID_MODE_CFG);
drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c
533
writel(PHY_TXREQUESTCLKHS, base + LPCLK_CTRL);
drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c
534
writel(DSI_VIDEO_MODE, base + MODE_CFG);
drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c
553
writel(RESET, base + PWR_UP);
drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c
565
writel(POWERUP, base + PWR_UP);
drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c
580
writel(0, base + PWR_UP);
drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c
581
writel(0, base + LPCLK_CTRL);
drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c
582
writel(0, base + PHY_RSTZ);
drivers/gpu/drm/hisilicon/kirin/dw_dsi_reg.h
98
writel(tmp, addr);
drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h
223
writel(tmp, addr);
drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c
126
writel(0, base + ADE_OVLY1_TRANS_CFG);
drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c
127
writel(0, base + ADE_OVLY_CTL);
drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c
128
writel(0, base + ADE_OVLYX_CTL(OUT_OVLY));
drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c
130
writel(MASK(32), base + ADE_SOFT_RST_SEL(0));
drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c
131
writel(MASK(32), base + ADE_SOFT_RST_SEL(1));
drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c
132
writel(MASK(32), base + ADE_RELOAD_DIS(0));
drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c
133
writel(MASK(32), base + ADE_RELOAD_DIS(1));
drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c
195
writel((hbp << HBP_OFST) | hfp, base + LDI_HRZ_CTRL0);
drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c
197
writel(hsw - 1, base + LDI_HRZ_CTRL1);
drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c
198
writel((vbp << VBP_OFST) | vfp, base + LDI_VRT_CTRL0);
drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c
200
writel(vsw - 1, base + LDI_VRT_CTRL1);
drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c
202
writel(((height - 1) << VSIZE_OFST) | (width - 1),
drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c
204
writel(plr_flags, base + LDI_PLR_CTRL);
drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c
207
writel(((width - 1) << OUTPUT_XSIZE_OFST) | (height - 1),
drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c
211
writel(CTRAN_BYPASS_ON, base + ADE_CTRAN_DIS(ADE_CTRAN6));
drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c
213
writel(width * height - 1, base + ADE_CTRAN_IMAGE_SIZE(ADE_CTRAN6));
drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c
252
writel(ADE_DISABLE, base + LDI_CTRL);
drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c
254
writel(DSI_PCLK_OFF, base + LDI_HDMI_DSI_GT);
drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c
333
writel(ADE_ENABLE, base + ADE_OVLYX_CTL(OUT_OVLY));
drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c
337
writel(DISP_SRC_OVLY2, base + ADE_DISP_SRC_CFG);
drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c
340
writel(ADE_ENABLE, base + ADE_EN);
drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c
342
writel(NORMAL_MODE, base + LDI_WORK_MODE);
drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c
343
writel((out_fmt << BPP_OFST) | DATA_GATE_EN | LDI_EN,
drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c
346
writel(DSI_PCLK_ON, base + LDI_HDMI_DSI_GT);
drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c
411
writel(ADE_ENABLE, base + ADE_OVLYX_CTL(comp));
drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c
515
writel(ADE_ENABLE, base + ADE_EN);
drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c
575
writel((fmt << 16) & 0x1f0000, base + reg_ctrl);
drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c
576
writel(addr, base + reg_addr);
drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c
577
writel((in_h << 16) | stride, base + reg_size);
drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c
578
writel(stride, base + reg_stride);
drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c
579
writel(in_h * stride, base + reg_space);
drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c
580
writel(ADE_ENABLE, base + reg_en);
drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c
590
writel(0, base + reg_en);
drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c
617
writel(disable_val, base + ADE_CLIP_DISABLE(ch));
drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c
618
writel((fb_w - 1) << 16 | (in_h - 1), base + ADE_CLIP_SIZE0(ch));
drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c
619
writel(clip_left << 16 | clip_right, base + ADE_CLIP_SIZE1(ch));
drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c
625
writel(1, base + ADE_CLIP_DISABLE(ch));
drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c
682
writel(x0 << 16 | y0, base + ADE_OVLY_CH_XY0(ovly_ch));
drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c
683
writel(x1 << 16 | y1, base + ADE_OVLY_CH_XY1(ovly_ch));
drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c
689
writel(val, base + ADE_OVLY_CH_CTL(ovly_ch));
drivers/gpu/drm/i915/gt/intel_execlists_submission.c
726
writel(lower_32_bits(desc), execlists->submit_reg + port * 2);
drivers/gpu/drm/i915/gt/intel_execlists_submission.c
727
writel(upper_32_bits(desc), execlists->submit_reg + port * 2 + 1);
drivers/gpu/drm/i915/gt/intel_execlists_submission.c
729
writel(upper_32_bits(desc), execlists->submit_reg);
drivers/gpu/drm/i915/gt/intel_execlists_submission.c
730
writel(lower_32_bits(desc), execlists->submit_reg);
drivers/gpu/drm/i915/gt/intel_execlists_submission.c
938
writel(EL_CTRL_LOAD, execlists->ctrl_reg);
drivers/gpu/drm/i915/intel_uncore.c
135
#define fw_set(d, val) writel(_MASKED_BIT_ENABLE((val)), (d)->reg_set)
drivers/gpu/drm/i915/intel_uncore.c
136
#define fw_clear(d, val) writel(_MASKED_BIT_DISABLE((val)), (d)->reg_set)
drivers/gpu/drm/i915/intel_uncore.h
516
writel(value, base + i915_mmio_reg_offset(reg))
drivers/gpu/drm/imx/dcss/dcss-dev.h
19
#define dcss_writel(v, c) writel((v), (c))
drivers/gpu/drm/imx/dcss/dcss-dev.h
21
#define dcss_set(v, c) writel((v), (c) + SET)
drivers/gpu/drm/imx/dcss/dcss-dev.h
22
#define dcss_clr(v, c) writel((v), (c) + CLR)
drivers/gpu/drm/imx/dcss/dcss-dev.h
23
#define dcss_toggle(v, c) writel((v), (c) + TGL)
drivers/gpu/drm/imx/dcss/dcss-dev.h
27
writel((readl(c) & ~(m)) | (v), (c));
drivers/gpu/drm/imx/lcdc/imx-lcdc.c
152
writel(addr, lcdc->base + IMX21LCDC_LSSAR);
drivers/gpu/drm/imx/lcdc/imx-lcdc.c
164
writel(framesize, lcdc->base + IMX21LCDC_LSR);
drivers/gpu/drm/imx/lcdc/imx-lcdc.c
170
writel(lhcr, lcdc->base + IMX21LCDC_LHCR);
drivers/gpu/drm/imx/lcdc/imx-lcdc.c
176
writel(lvcr, lcdc->base + IMX21LCDC_LVCR);
drivers/gpu/drm/imx/lcdc/imx-lcdc.c
181
writel(lpcr, lcdc->base + IMX21LCDC_LPCR);
drivers/gpu/drm/imx/lcdc/imx-lcdc.c
184
writel(new_state->fb->pitches[0] / 4, lcdc->base + IMX21LCDC_LVPWR);
drivers/gpu/drm/imx/lcdc/imx-lcdc.c
212
writel(FIELD_PREP(IMX21LCDC_LPCR_PCD, clk_div - 1) |
drivers/gpu/drm/imx/lcdc/imx-lcdc.c
226
writel(0x00000000, lcdc->base + IMX21LCDC_LPOR);
drivers/gpu/drm/imx/lcdc/imx-lcdc.c
229
writel(readl(lcdc->base + IMX21LCDC_LCPR) & ~(IMX21LCDC_LCPR_CC0 | IMX21LCDC_LCPR_CC1),
drivers/gpu/drm/imx/lcdc/imx-lcdc.c
249
writel(INTR_EOF, lcdc->base + IMX21LCDC_LIER);
drivers/gpu/drm/imx/lcdc/imx-lcdc.c
273
writel(0, lcdc->base + IMX21LCDC_LIER);
drivers/gpu/drm/kmb/kmb_drv.h
79
writel(value, (dev_p->lcd_mmio + reg));
drivers/gpu/drm/kmb/kmb_dsi.h
341
writel(value, (kmb_dsi->mipi_mmio + reg));
drivers/gpu/drm/lima/lima_bcast.c
11
#define bcast_write(reg, data) writel(data, ip->iomem + reg)
drivers/gpu/drm/lima/lima_dlbu.c
12
#define dlbu_write(reg, data) writel(data, ip->iomem + reg)
drivers/gpu/drm/lima/lima_gp.c
164
writel(f[i], ip->iomem + LIMA_GP_VSCL_START_ADDR + i * 4);
drivers/gpu/drm/lima/lima_gp.c
17
#define gp_write(reg, data) writel(data, ip->iomem + reg)
drivers/gpu/drm/lima/lima_l2_cache.c
11
#define l2_cache_write(reg, data) writel(data, ip->iomem + reg)
drivers/gpu/drm/lima/lima_mmu.c
13
#define mmu_write(reg, data) writel(data, ip->iomem + reg)
drivers/gpu/drm/lima/lima_pmu.c
11
#define pmu_write(reg, data) writel(data, ip->iomem + reg)
drivers/gpu/drm/lima/lima_pp.c
163
writel(frame[i], ip->iomem + LIMA_PP_FRAME + i * 4);
drivers/gpu/drm/lima/lima_pp.c
167
writel(wb[n++], ip->iomem + LIMA_PP_WB(i) + j * 4);
drivers/gpu/drm/lima/lima_pp.c
18
#define pp_write(reg, data) writel(data, ip->iomem + reg)
drivers/gpu/drm/loongson/lsdc_drv.h
353
writel(val, ldev->reg_base + offset);
drivers/gpu/drm/loongson/lsdc_drv.h
363
writel(val | mask, addr);
drivers/gpu/drm/loongson/lsdc_drv.h
373
writel(val & ~mask, addr);
drivers/gpu/drm/loongson/lsdc_drv.h
385
writel(val, ldev->reg_base + offset + pipe * CRTC_PIPE_OFFSET);
drivers/gpu/drm/loongson/lsdc_pixpll.c
269
writel(src->w[0], this->mmio);
drivers/gpu/drm/loongson/lsdc_pixpll.c
270
writel(src->w[1], this->mmio + 4);
drivers/gpu/drm/mcde/mcde_clk_div.c
38
writel(val, mcde->regs + cdiv->cr);
drivers/gpu/drm/mcde/mcde_display.c
1028
writel(val, mcde->regs + MCDE_CONF0);
drivers/gpu/drm/mcde/mcde_display.c
1031
writel(0, mcde->regs + MCDE_TVCRA);
drivers/gpu/drm/mcde/mcde_display.c
1036
writel(val, mcde->regs + MCDE_TVBL1A);
drivers/gpu/drm/mcde/mcde_display.c
1038
writel(val, mcde->regs + MCDE_TVBL2A);
drivers/gpu/drm/mcde/mcde_display.c
1044
writel(val, mcde->regs + MCDE_TVDVOA);
drivers/gpu/drm/mcde/mcde_display.c
1047
writel((hbp - 1), mcde->regs + MCDE_TVTIM1A);
drivers/gpu/drm/mcde/mcde_display.c
1052
writel(val, mcde->regs + MCDE_TVLBALWA);
drivers/gpu/drm/mcde/mcde_display.c
1055
writel(0, mcde->regs + MCDE_TVISLA);
drivers/gpu/drm/mcde/mcde_display.c
1056
writel(0, mcde->regs + MCDE_TVBLUA);
drivers/gpu/drm/mcde/mcde_display.c
1068
writel(val, mcde->regs + MCDE_LCDTIM1A);
drivers/gpu/drm/mcde/mcde_display.c
109
writel(val, mcde->regs + MCDE_CRA0);
drivers/gpu/drm/mcde/mcde_display.c
1107
writel(val, mcde->regs + MCDE_CONF0);
drivers/gpu/drm/mcde/mcde_display.c
1183
writel(0, mcde->regs + MCDE_IMSCERR);
drivers/gpu/drm/mcde/mcde_display.c
1184
writel(0xFFFFFFFF, mcde->regs + MCDE_RISERR);
drivers/gpu/drm/mcde/mcde_display.c
1267
writel(val, mcde->regs + MCDE_VSCRC0);
drivers/gpu/drm/mcde/mcde_display.c
1271
writel(val, mcde->regs + MCDE_CRC);
drivers/gpu/drm/mcde/mcde_display.c
1296
writel(val, mcde->regs + MCDE_CR);
drivers/gpu/drm/mcde/mcde_display.c
132
writel(mispp, mcde->regs + MCDE_RISPP);
drivers/gpu/drm/mcde/mcde_display.c
1357
writel(MCDE_CHNLXSYNCHSW_SW_TRIG,
drivers/gpu/drm/mcde/mcde_display.c
1376
writel(buffer_address, mcde->regs + MCDE_EXTSRCXA0);
drivers/gpu/drm/mcde/mcde_display.c
1381
writel(buffer_address + mcde->stride, mcde->regs + MCDE_EXTSRCXA1);
drivers/gpu/drm/mcde/mcde_display.c
139
writel(misovl, mcde->regs + MCDE_RISOVL);
drivers/gpu/drm/mcde/mcde_display.c
144
writel(mischnl, mcde->regs + MCDE_RISCHNL);
drivers/gpu/drm/mcde/mcde_display.c
1460
writel(val, mcde->regs + MCDE_IMSCPP);
drivers/gpu/drm/mcde/mcde_display.c
1472
writel(0, mcde->regs + MCDE_IMSCPP);
drivers/gpu/drm/mcde/mcde_display.c
1474
writel(0xFFFFFFFF, mcde->regs + MCDE_RISPP);
drivers/gpu/drm/mcde/mcde_display.c
150
writel(0, mcde->regs + MCDE_IMSCPP);
drivers/gpu/drm/mcde/mcde_display.c
151
writel(0, mcde->regs + MCDE_IMSCOVL);
drivers/gpu/drm/mcde/mcde_display.c
152
writel(0, mcde->regs + MCDE_IMSCCHNL);
drivers/gpu/drm/mcde/mcde_display.c
155
writel(0xFFFFFFFF, mcde->regs + MCDE_RISPP);
drivers/gpu/drm/mcde/mcde_display.c
156
writel(0xFFFFFFFF, mcde->regs + MCDE_RISOVL);
drivers/gpu/drm/mcde/mcde_display.c
157
writel(0xFFFFFFFF, mcde->regs + MCDE_RISCHNL);
drivers/gpu/drm/mcde/mcde_display.c
329
writel(val, mcde->regs + conf);
drivers/gpu/drm/mcde/mcde_display.c
334
writel(val, mcde->regs + cr);
drivers/gpu/drm/mcde/mcde_display.c
409
writel(val, mcde->regs + conf1);
drivers/gpu/drm/mcde/mcde_display.c
464
writel(val, mcde->regs + conf2);
drivers/gpu/drm/mcde/mcde_display.c
467
writel(mcde->stride, mcde->regs + ljinc);
drivers/gpu/drm/mcde/mcde_display.c
469
writel(0, mcde->regs + crop);
drivers/gpu/drm/mcde/mcde_display.c
481
writel(val, mcde->regs + cr);
drivers/gpu/drm/mcde/mcde_display.c
488
writel(val, mcde->regs + comp);
drivers/gpu/drm/mcde/mcde_display.c
577
writel(val, mcde->regs + sync);
drivers/gpu/drm/mcde/mcde_display.c
582
writel(val, mcde->regs + conf);
drivers/gpu/drm/mcde/mcde_display.c
590
writel(val, mcde->regs + stat);
drivers/gpu/drm/mcde/mcde_display.c
591
writel(0, mcde->regs + bgcol);
drivers/gpu/drm/mcde/mcde_display.c
596
writel(MCDE_CHNLXMUXING_FIFO_ID_FIFO_A,
drivers/gpu/drm/mcde/mcde_display.c
600
writel(MCDE_CHNLXMUXING_FIFO_ID_FIFO_B,
drivers/gpu/drm/mcde/mcde_display.c
622
writel(val, mcde->regs + MCDE_SYNCHCONFA);
drivers/gpu/drm/mcde/mcde_display.c
625
writel(val, mcde->regs + MCDE_SYNCHCONFB);
drivers/gpu/drm/mcde/mcde_display.c
696
writel(val, mcde->regs + ctrl);
drivers/gpu/drm/mcde/mcde_display.c
701
writel(val, mcde->regs + cr0);
drivers/gpu/drm/mcde/mcde_display.c
745
writel(val, mcde->regs + cr1);
drivers/gpu/drm/mcde/mcde_display.c
825
writel(val, mcde->regs + conf0);
drivers/gpu/drm/mcde/mcde_display.c
827
writel(formatter_frame, mcde->regs + frame);
drivers/gpu/drm/mcde/mcde_display.c
828
writel(pkt_size, mcde->regs + pkt);
drivers/gpu/drm/mcde/mcde_display.c
829
writel(0, mcde->regs + sync);
drivers/gpu/drm/mcde/mcde_display.c
835
writel(val, mcde->regs + cmdw);
drivers/gpu/drm/mcde/mcde_display.c
841
writel(0, mcde->regs + delay0);
drivers/gpu/drm/mcde/mcde_display.c
842
writel(0, mcde->regs + delay1);
drivers/gpu/drm/mcde/mcde_display.c
866
writel(val, mcde->regs + cr);
drivers/gpu/drm/mcde/mcde_display.c
894
writel(val, mcde->regs + cr);
drivers/gpu/drm/mcde/mcde_display.c
953
writel(MCDE_CHNLXSYNCHSW_SW_TRIG, mcde->regs + synsw);
drivers/gpu/drm/mcde/mcde_drv.c
123
writel(val, mcde->regs + MCDE_RISERR);
drivers/gpu/drm/mcde/mcde_drv.c
384
writel(0, mcde->regs + MCDE_IMSCERR);
drivers/gpu/drm/mcde/mcde_drv.c
385
writel(0xFFFFFFFF, mcde->regs + MCDE_RISERR);
drivers/gpu/drm/mcde/mcde_dsi.c
1031
writel(val, d->regs + DSI_MCTL_MAIN_DATA_CTL);
drivers/gpu/drm/mcde/mcde_dsi.c
1045
writel(0, d->regs + DSI_VID_MODE_STS_CTL);
drivers/gpu/drm/mcde/mcde_dsi.c
108
writel(val, d->regs + DSI_CMD_MODE_STS_CLR);
drivers/gpu/drm/mcde/mcde_dsi.c
113
writel(val, d->regs + DSI_DIRECT_CMD_RD_STS_CLR);
drivers/gpu/drm/mcde/mcde_dsi.c
118
writel(val, d->regs + DSI_TG_STS_CLR);
drivers/gpu/drm/mcde/mcde_dsi.c
143
writel(val, d->regs + DSI_VID_MODE_STS_CLR);
drivers/gpu/drm/mcde/mcde_dsi.c
222
writel(~0, d->regs + DSI_DIRECT_CMD_STS_CLR);
drivers/gpu/drm/mcde/mcde_dsi.c
223
writel(~0, d->regs + DSI_CMD_MODE_STS_CLR);
drivers/gpu/drm/mcde/mcde_dsi.c
225
writel(1, d->regs + DSI_DIRECT_CMD_SEND);
drivers/gpu/drm/mcde/mcde_dsi.c
257
writel(1, d->regs + DSI_DIRECT_CMD_RD_INIT);
drivers/gpu/drm/mcde/mcde_dsi.c
339
writel(val, d->regs + DSI_DIRECT_CMD_MAIN_SETTINGS);
drivers/gpu/drm/mcde/mcde_dsi.c
347
writel(val, d->regs + DSI_DIRECT_CMD_WRDAT0);
drivers/gpu/drm/mcde/mcde_dsi.c
352
writel(val, d->regs + DSI_DIRECT_CMD_WRDAT1);
drivers/gpu/drm/mcde/mcde_dsi.c
358
writel(val, d->regs + DSI_DIRECT_CMD_WRDAT2);
drivers/gpu/drm/mcde/mcde_dsi.c
364
writel(val, d->regs + DSI_DIRECT_CMD_WRDAT3);
drivers/gpu/drm/mcde/mcde_dsi.c
377
writel(~0, d->regs + DSI_DIRECT_CMD_STS_CLR);
drivers/gpu/drm/mcde/mcde_dsi.c
378
writel(~0, d->regs + DSI_CMD_MODE_STS_CLR);
drivers/gpu/drm/mcde/mcde_dsi.c
404
writel(val, d->regs + DSI_DIRECT_CMD_MAIN_SETTINGS);
drivers/gpu/drm/mcde/mcde_dsi.c
407
writel(DSI_DIRECT_CMD_STS_CLR_TE_RECEIVED_CLR |
drivers/gpu/drm/mcde/mcde_dsi.c
413
writel(val, d->regs + DSI_DIRECT_CMD_STS_CTL);
drivers/gpu/drm/mcde/mcde_dsi.c
416
writel(DSI_CMD_MODE_STS_CLR_ERR_NO_TE_CLR |
drivers/gpu/drm/mcde/mcde_dsi.c
422
writel(val, d->regs + DSI_CMD_MODE_STS_CTL);
drivers/gpu/drm/mcde/mcde_dsi.c
425
writel(1, d->regs + DSI_DIRECT_CMD_SEND);
drivers/gpu/drm/mcde/mcde_dsi.c
494
writel(val, d->regs + DSI_VID_MAIN_CTL);
drivers/gpu/drm/mcde/mcde_dsi.c
507
writel(val, d->regs + DSI_VID_VSIZE);
drivers/gpu/drm/mcde/mcde_dsi.c
567
writel(val, d->regs + DSI_VID_HSIZE1);
drivers/gpu/drm/mcde/mcde_dsi.c
571
writel(val, d->regs + DSI_VID_HSIZE2);
drivers/gpu/drm/mcde/mcde_dsi.c
618
writel(0, d->regs + DSI_VID_BLKSIZE1);
drivers/gpu/drm/mcde/mcde_dsi.c
627
writel(val, d->regs + DSI_VID_BLKSIZE2);
drivers/gpu/drm/mcde/mcde_dsi.c
630
writel(0, d->regs + DSI_VID_BLKSIZE2);
drivers/gpu/drm/mcde/mcde_dsi.c
638
writel(val, d->regs + DSI_VID_BLKSIZE1);
drivers/gpu/drm/mcde/mcde_dsi.c
665
writel(val, d->regs + DSI_VID_DPHY_TIME);
drivers/gpu/drm/mcde/mcde_dsi.c
699
writel(val, d->regs + DSI_VID_BLKSIZE1);
drivers/gpu/drm/mcde/mcde_dsi.c
704
writel(val, d->regs + DSI_VID_VCA_SETTING2);
drivers/gpu/drm/mcde/mcde_dsi.c
730
writel(val, d->regs + DSI_VID_PCK_TIME);
drivers/gpu/drm/mcde/mcde_dsi.c
737
writel(val, d->regs + DSI_VID_VCA_SETTING1);
drivers/gpu/drm/mcde/mcde_dsi.c
745
writel(val, d->regs + DSI_VID_VCA_SETTING2);
drivers/gpu/drm/mcde/mcde_dsi.c
756
writel(0, d->regs + DSI_MCTL_INTEGRATION_MODE);
drivers/gpu/drm/mcde/mcde_dsi.c
765
writel(val, d->regs + DSI_MCTL_MAIN_DATA_CTL);
drivers/gpu/drm/mcde/mcde_dsi.c
769
writel(val, d->regs + DSI_CMD_MODE_CTL);
drivers/gpu/drm/mcde/mcde_dsi.c
782
writel(val, d->regs + DSI_MCTL_DPHY_STATIC);
drivers/gpu/drm/mcde/mcde_dsi.c
798
writel(val, d->regs + DSI_MCTL_MAIN_PHY_CTL);
drivers/gpu/drm/mcde/mcde_dsi.c
802
writel(val, d->regs + DSI_MCTL_ULPOUT_TIME);
drivers/gpu/drm/mcde/mcde_dsi.c
804
writel(DSI_DPHY_LANES_TRIM_DPHY_SPECS_90_81B_0_90,
drivers/gpu/drm/mcde/mcde_dsi.c
811
writel(val, d->regs + DSI_MCTL_DPHY_TIMEOUT);
drivers/gpu/drm/mcde/mcde_dsi.c
819
writel(val, d->regs + DSI_MCTL_MAIN_EN);
drivers/gpu/drm/mcde/mcde_dsi.c
848
writel(val, d->regs + DSI_CMD_MODE_CTL);
drivers/gpu/drm/mcde/mcde_dsi.c
91
writel(val, d->regs + DSI_DIRECT_CMD_STS_CLR);
drivers/gpu/drm/mcde/mcde_dsi.c
925
writel(val, d->regs + DSI_MCTL_MAIN_DATA_CTL);
drivers/gpu/drm/mcde/mcde_dsi.c
930
writel(val, d->regs + DSI_CMD_MODE_CTL);
drivers/gpu/drm/mcde/mcde_dsi.c
936
writel(val, d->regs + DSI_VID_MODE_STS_CTL);
drivers/gpu/drm/mcde/mcde_dsi.c
941
writel(val, d->regs + DSI_MCTL_MAIN_DATA_CTL);
drivers/gpu/drm/mcde/mcde_dsi.c
952
writel(val, d->regs + DSI_CMD_MODE_CTL);
drivers/gpu/drm/mediatek/mtk_cec.c
69
writel(tmp, reg);
drivers/gpu/drm/mediatek/mtk_cec.c
80
writel(tmp, reg);
drivers/gpu/drm/mediatek/mtk_cec.c
89
writel(tmp, cec->regs + offset);
drivers/gpu/drm/mediatek/mtk_ddp_comp.c
108
writel(tmp, regs + offset);
drivers/gpu/drm/mediatek/mtk_ddp_comp.c
171
writel(DITHER_EN, priv->regs + DISP_REG_DITHER_EN);
drivers/gpu/drm/mediatek/mtk_ddp_comp.c
235
writel(1, priv->regs + DISP_REG_OD_EN);
drivers/gpu/drm/mediatek/mtk_ddp_comp.c
254
writel(POSTMASK_EN, priv->regs + DISP_REG_POSTMASK_EN);
drivers/gpu/drm/mediatek/mtk_ddp_comp.c
268
writel(UFO_BYPASS, priv->regs + DISP_REG_UFO_START);
drivers/gpu/drm/mediatek/mtk_ddp_comp.c
79
writel(value, regs + offset);
drivers/gpu/drm/mediatek/mtk_disp_aal.c
123
writel(word, aal->regs + DISP_AAL_GAMMA_LUT + i * 4);
drivers/gpu/drm/mediatek/mtk_disp_aal.c
134
writel(cfg_val, aal->regs + DISP_AAL_CFG);
drivers/gpu/drm/mediatek/mtk_disp_aal.c
141
writel(AAL_EN, aal->regs + DISP_AAL_EN);
drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
73
writel(CCORR_EN, ccorr->regs + DISP_CCORR_EN);
drivers/gpu/drm/mediatek/mtk_disp_color.c
74
writel(COLOR_BYPASS_ALL | COLOR_SEQ_SEL,
drivers/gpu/drm/mediatek/mtk_disp_color.c
76
writel(0x1, color->regs + DISP_COLOR_START(color));
drivers/gpu/drm/mediatek/mtk_disp_gamma.c
143
writel(lbank_val, gamma->regs + DISP_GAMMA_BANK);
drivers/gpu/drm/mediatek/mtk_disp_gamma.c
184
writel(word[0], lut0_base + i * 4);
drivers/gpu/drm/mediatek/mtk_disp_gamma.c
186
writel(word[1], lut1_base + i * 4);
drivers/gpu/drm/mediatek/mtk_disp_gamma.c
206
writel(cfg_val, gamma->regs + DISP_GAMMA_CFG);
drivers/gpu/drm/mediatek/mtk_disp_gamma.c
229
writel(GAMMA_EN, gamma->regs + DISP_GAMMA_EN);
drivers/gpu/drm/mediatek/mtk_disp_ovl.c
175
writel(0x0, priv->regs + DISP_REG_OVL_INTSTA);
drivers/gpu/drm/mediatek/mtk_disp_ovl.c
207
writel(0x0, ovl->regs + DISP_REG_OVL_INTSTA);
drivers/gpu/drm/mediatek/mtk_disp_ovl.c
581
writel(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON);
drivers/gpu/drm/mediatek/mtk_disp_ovl.c
591
writel(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON);
drivers/gpu/drm/mediatek/mtk_disp_rdma.c
113
writel(tmp, rdma->regs + reg);
drivers/gpu/drm/mediatek/mtk_disp_rdma.c
349
writel(0x0, priv->regs + DISP_REG_RDMA_INT_ENABLE);
drivers/gpu/drm/mediatek/mtk_disp_rdma.c
350
writel(0x0, priv->regs + DISP_REG_RDMA_INT_STATUS);
drivers/gpu/drm/mediatek/mtk_disp_rdma.c
96
writel(0x0, priv->regs + DISP_REG_RDMA_INT_STATUS);
drivers/gpu/drm/mediatek/mtk_dpi.c
182
writel(tmp, dpi->regs + offset);
drivers/gpu/drm/mediatek/mtk_dsi.c
243
writel((temp & ~mask) | (data & mask), dsi->regs + offset);
drivers/gpu/drm/mediatek/mtk_dsi.c
287
writel(timcon0, dsi->regs + DSI_PHY_TIMECON0);
drivers/gpu/drm/mediatek/mtk_dsi.c
288
writel(timcon1, dsi->regs + DSI_PHY_TIMECON1);
drivers/gpu/drm/mediatek/mtk_dsi.c
289
writel(timcon2, dsi->regs + DSI_PHY_TIMECON2);
drivers/gpu/drm/mediatek/mtk_dsi.c
290
writel(timcon3, dsi->regs + DSI_PHY_TIMECON3);
drivers/gpu/drm/mediatek/mtk_dsi.c
367
writel(vid_mode, dsi->regs + DSI_MODE_CTRL);
drivers/gpu/drm/mediatek/mtk_dsi.c
393
writel(regval, dsi->regs + DSI_TXRX_CTRL);
drivers/gpu/drm/mediatek/mtk_dsi.c
429
writel(vact_nl, dsi->regs + DSI_VACT_NL);
drivers/gpu/drm/mediatek/mtk_dsi.c
430
writel(ps_wc, dsi->regs + DSI_HSTX_CKL_WC);
drivers/gpu/drm/mediatek/mtk_dsi.c
432
writel(ps_val, dsi->regs + DSI_PSCTRL);
drivers/gpu/drm/mediatek/mtk_dsi.c
491
writel(hstx_cklp_wc, dsi->regs + DSI_HSTX_CKL_WC);
drivers/gpu/drm/mediatek/mtk_dsi.c
498
writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC);
drivers/gpu/drm/mediatek/mtk_dsi.c
499
writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC);
drivers/gpu/drm/mediatek/mtk_dsi.c
500
writel(horizontal_frontporch_byte, dsi->regs + DSI_HFP_WC);
drivers/gpu/drm/mediatek/mtk_dsi.c
562
writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC);
drivers/gpu/drm/mediatek/mtk_dsi.c
563
writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC);
drivers/gpu/drm/mediatek/mtk_dsi.c
564
writel(horizontal_frontporch_byte, dsi->regs + DSI_HFP_WC);
drivers/gpu/drm/mediatek/mtk_dsi.c
571
writel(vm->vsync_len, dsi->regs + DSI_VSA_NL);
drivers/gpu/drm/mediatek/mtk_dsi.c
572
writel(vm->vback_porch, dsi->regs + DSI_VBP_NL);
drivers/gpu/drm/mediatek/mtk_dsi.c
573
writel(vm->vfront_porch, dsi->regs + DSI_VFP_NL);
drivers/gpu/drm/mediatek/mtk_dsi.c
574
writel(vm->vactive, dsi->regs + DSI_VACT_NL);
drivers/gpu/drm/mediatek/mtk_dsi.c
577
writel(FIELD_PREP(DSI_HEIGHT, vm->vactive) |
drivers/gpu/drm/mediatek/mtk_dsi.c
591
writel(0, dsi->regs + DSI_START);
drivers/gpu/drm/mediatek/mtk_dsi.c
592
writel(1, dsi->regs + DSI_START);
drivers/gpu/drm/mediatek/mtk_dsi.c
597
writel(0, dsi->regs + DSI_START);
drivers/gpu/drm/mediatek/mtk_dsi.c
602
writel(CMD_MODE, dsi->regs + DSI_MODE_CTRL);
drivers/gpu/drm/mediatek/mtk_dsi.c
609
writel(inten, dsi->regs + DSI_INTEN);
drivers/gpu/drm/mediatek/mtk_dsi.c
718
writel(FORCE_COMMIT | BYPASS_SHADOW,
drivers/gpu/drm/mediatek/mtk_dsi.c
761
writel(0, dsi->regs + DSI_TXRX_CTRL);
drivers/gpu/drm/mediatek/mtk_ethdr.c
124
writel(MIX_FME_CPL_INTEN, priv->ethdr_comp[ETHDR_MIXER].regs + MIX_INTEN);
drivers/gpu/drm/mediatek/mtk_ethdr.c
131
writel(0x0, priv->ethdr_comp[ETHDR_MIXER].regs + MIX_INTEN);
drivers/gpu/drm/mediatek/mtk_ethdr.c
138
writel(0x0, priv->ethdr_comp[ETHDR_MIXER].regs + MIX_INTSTA);
drivers/gpu/drm/mediatek/mtk_ethdr.c
270
writel(1, mixer->regs + MIX_EN);
drivers/gpu/drm/mediatek/mtk_ethdr.c
278
writel(0, mixer->regs + MIX_EN);
drivers/gpu/drm/mediatek/mtk_ethdr.c
279
writel(1, mixer->regs + MIX_RST);
drivers/gpu/drm/mediatek/mtk_ethdr.c
281
writel(0, mixer->regs + MIX_RST);
drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c
67
writel(readl(ddc->regs + offset) | val, ddc->regs + offset);
drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c
73
writel(readl(ddc->regs + offset) & ~val, ddc->regs + offset);
drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c
91
writel(tmp, ddc->regs + offset);
drivers/gpu/drm/mediatek/mtk_padding.c
59
writel(PADDING_ENABLE | PADDING_BYPASS,
drivers/gpu/drm/mediatek/mtk_padding.c
67
writel(0, padding->reg + PADDING_PIC_SIZE_REG);
drivers/gpu/drm/mediatek/mtk_padding.c
68
writel(0, padding->reg + PADDING_H_REG);
drivers/gpu/drm/mediatek/mtk_padding.c
69
writel(0, padding->reg + PADDING_V_REG);
drivers/gpu/drm/mediatek/mtk_padding.c
70
writel(0, padding->reg + PADDING_COLOR_REG);
drivers/gpu/drm/mediatek/mtk_padding.c
77
writel(0, padding->reg + PADDING_CONTROL_REG);
drivers/gpu/drm/meson/meson_crtc.c
103
writel(crtc_state->mode.hdisplay |
drivers/gpu/drm/meson/meson_crtc.c
135
writel(crtc_state->mode.hdisplay,
drivers/gpu/drm/meson/meson_crtc.c
139
writel(FIELD_PREP(GENMASK(11, 0), 2303),
drivers/gpu/drm/meson/meson_crtc.c
99
writel(FIELD_PREP(GENMASK(11, 0), 2303),
drivers/gpu/drm/meson/meson_dw_hdmi.c
170
writel(addr & 0xffff, dw_hdmi->hdmitx + HDMITX_TOP_ADDR_REG);
drivers/gpu/drm/meson/meson_dw_hdmi.c
171
writel(addr & 0xffff, dw_hdmi->hdmitx + HDMITX_TOP_ADDR_REG);
drivers/gpu/drm/meson/meson_dw_hdmi.c
196
writel(addr & 0xffff, dw_hdmi->hdmitx + HDMITX_TOP_ADDR_REG);
drivers/gpu/drm/meson/meson_dw_hdmi.c
197
writel(addr & 0xffff, dw_hdmi->hdmitx + HDMITX_TOP_ADDR_REG);
drivers/gpu/drm/meson/meson_dw_hdmi.c
200
writel(data, dw_hdmi->hdmitx + HDMITX_TOP_DATA_REG);
drivers/gpu/drm/meson/meson_dw_hdmi.c
208
writel(data, dw_hdmi->hdmitx + HDMITX_TOP_G12A_OFFSET + (addr << 2));
drivers/gpu/drm/meson/meson_dw_hdmi.c
234
writel(addr & 0xffff, dw_hdmi->hdmitx + HDMITX_DWC_ADDR_REG);
drivers/gpu/drm/meson/meson_dw_hdmi.c
235
writel(addr & 0xffff, dw_hdmi->hdmitx + HDMITX_DWC_ADDR_REG);
drivers/gpu/drm/meson/meson_dw_hdmi.c
260
writel(addr & 0xffff, dw_hdmi->hdmitx + HDMITX_DWC_ADDR_REG);
drivers/gpu/drm/meson/meson_dw_hdmi.c
261
writel(addr & 0xffff, dw_hdmi->hdmitx + HDMITX_DWC_ADDR_REG);
drivers/gpu/drm/meson/meson_dw_hdmi.c
264
writel(data, dw_hdmi->hdmitx + HDMITX_DWC_DATA_REG);
drivers/gpu/drm/meson/meson_rdma.c
121
writel(priv->rdma.addr_dma,
drivers/gpu/drm/meson/meson_rdma.c
125
writel(priv->rdma.addr_dma + (priv->rdma.offset * RDMA_DESC_SIZE) - 1,
drivers/gpu/drm/meson/meson_venc.c
1106
writel(vmode->enci.sch_adjust,
drivers/gpu/drm/meson/meson_venc.c
1820
writel(mode->sch_adjust, priv->io_base + _REG(ENCI_VIDEO_SCH));
drivers/gpu/drm/meson/meson_viu.c
100
writel(((m[18] & 0xfff) << 16) | (m[19] & 0xfff),
drivers/gpu/drm/meson/meson_viu.c
102
writel(m[20] & 0xfff,
drivers/gpu/drm/meson/meson_viu.c
115
writel(((m[0] & 0xfff) << 16) | (m[1] & 0xfff),
drivers/gpu/drm/meson/meson_viu.c
117
writel(m[2] & 0xfff,
drivers/gpu/drm/meson/meson_viu.c
119
writel(((m[3] & 0x1fff) << 16) | (m[4] & 0x1fff),
drivers/gpu/drm/meson/meson_viu.c
121
writel(((m[5] & 0x1fff) << 16) | (m[6] & 0x1fff),
drivers/gpu/drm/meson/meson_viu.c
123
writel(((m[7] & 0x1fff) << 16) | (m[8] & 0x1fff),
drivers/gpu/drm/meson/meson_viu.c
125
writel(((m[9] & 0x1fff) << 16) | (m[10] & 0x1fff),
drivers/gpu/drm/meson/meson_viu.c
129
writel(((m[11] & 0x1fff) << 16) | (m[12] & 0x1fff),
drivers/gpu/drm/meson/meson_viu.c
132
writel(((m[13] & 0x1fff) << 16) | (m[14] & 0x1fff),
drivers/gpu/drm/meson/meson_viu.c
135
writel(((m[15] & 0x1fff) << 16) | (m[16] & 0x1fff),
drivers/gpu/drm/meson/meson_viu.c
138
writel(m[17] & 0x1fff, priv->io_base +
drivers/gpu/drm/meson/meson_viu.c
141
writel((m[11] & 0x1fff) << 16, priv->io_base +
drivers/gpu/drm/meson/meson_viu.c
144
writel(((m[18] & 0xfff) << 16) | (m[19] & 0xfff),
drivers/gpu/drm/meson/meson_viu.c
146
writel(m[20] & 0xfff,
drivers/gpu/drm/meson/meson_viu.c
164
writel(((m[i * 2] & 0x1fff) << 16) |
drivers/gpu/drm/meson/meson_viu.c
200
writel(0, priv->io_base + _REG(addr_port));
drivers/gpu/drm/meson/meson_viu.c
203
writel(r_map[i * 2] | (r_map[i * 2 + 1] << 16),
drivers/gpu/drm/meson/meson_viu.c
206
writel(r_map[OSD_OETF_LUT_SIZE - 1] | (g_map[0] << 16),
drivers/gpu/drm/meson/meson_viu.c
210
writel(g_map[i * 2 + 1] | (g_map[i * 2 + 2] << 16),
drivers/gpu/drm/meson/meson_viu.c
214
writel(b_map[i * 2] | (b_map[i * 2 + 1] << 16),
drivers/gpu/drm/meson/meson_viu.c
217
writel(b_map[OSD_OETF_LUT_SIZE - 1],
drivers/gpu/drm/meson/meson_viu.c
227
writel(0, priv->io_base + _REG(addr_port));
drivers/gpu/drm/meson/meson_viu.c
230
writel(r_map[i * 2] | (r_map[i * 2 + 1] << 16),
drivers/gpu/drm/meson/meson_viu.c
233
writel(r_map[OSD_EOTF_LUT_SIZE - 1] | (g_map[0] << 16),
drivers/gpu/drm/meson/meson_viu.c
237
writel(g_map[i * 2 + 1] | (g_map[i * 2 + 2] << 16),
drivers/gpu/drm/meson/meson_viu.c
241
writel(b_map[i * 2] | (b_map[i * 2 + 1] << 16),
drivers/gpu/drm/meson/meson_viu.c
244
writel(b_map[OSD_EOTF_LUT_SIZE - 1],
drivers/gpu/drm/meson/meson_viu.c
85
writel(((m[0] & 0xfff) << 16) | (m[1] & 0xfff),
drivers/gpu/drm/meson/meson_viu.c
87
writel(m[2] & 0xfff,
drivers/gpu/drm/meson/meson_viu.c
89
writel(((m[3] & 0x1fff) << 16) | (m[4] & 0x1fff),
drivers/gpu/drm/meson/meson_viu.c
91
writel(((m[5] & 0x1fff) << 16) | (m[6] & 0x1fff),
drivers/gpu/drm/meson/meson_viu.c
93
writel(((m[7] & 0x1fff) << 16) | (m[8] & 0x1fff),
drivers/gpu/drm/meson/meson_viu.c
95
writel(((m[9] & 0x1fff) << 16) | (m[10] & 0x1fff),
drivers/gpu/drm/meson/meson_viu.c
97
writel((m[11] & 0x1fff),
drivers/gpu/drm/meson/meson_vpp.c
38
writel(mux, priv->io_base + _REG(VPU_VIU_VENC_MUX_CTRL));
drivers/gpu/drm/msm/adreno/a6xx_gmu.c
630
writel(value, ptr + (offset << 2));
drivers/gpu/drm/msm/adreno/a6xx_gmu.h
145
writel(value, gmu->mmio + GMU_BYTE_OFFSET(gmu, offset));
drivers/gpu/drm/msm/adreno/a6xx_gmu.h
188
writel(value, gmu->rscc + (offset << 2));
drivers/gpu/drm/msm/adreno/a6xx_gpu.h
255
writel(value, a6xx_gpu->llc_mmio + (reg << 2));
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
202
writel((val), (ptr) + ((offset) << 2))
drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h
47
writel(data, mdp4_kms->mmio + reg);
drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h
174
writel(data, mdp5_kms->mmio + reg);
drivers/gpu/drm/msm/dp/dp_audio.c
43
writel(data, audio->link_base + offset);
drivers/gpu/drm/msm/dp/dp_aux.c
61
writel(data, aux->aux_base + offset);
drivers/gpu/drm/msm/dp/dp_ctrl.c
157
writel(data, ctrl->ahb_base + offset);
drivers/gpu/drm/msm/dp/dp_ctrl.c
172
writel(data, ctrl->link_base + offset);
drivers/gpu/drm/msm/dp/dp_panel.c
44
writel(data, panel->link_base + offset);
drivers/gpu/drm/msm/dp/dp_panel.c
54
writel(data, panel->p0_base + offset);
drivers/gpu/drm/msm/dsi/dsi_host.c
198
writel(data, msm_host->ctrl_base + reg);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
191
writel(config->ssc_stepsize & 0xff,
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
193
writel(config->ssc_stepsize >> 8,
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
195
writel(config->ssc_div_per & 0xff,
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
197
writel(config->ssc_div_per >> 8,
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
199
writel(config->ssc_adj_per & 0xff,
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
201
writel(config->ssc_adj_per >> 8,
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
203
writel(SSC_EN | (config->ssc_center ? SSC_CENTER : 0),
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
212
writel(0x80, base + REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_ONE);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
213
writel(0x03, base + REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_TWO);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
214
writel(0x00, base + REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_THREE);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
215
writel(0x00, base + REG_DSI_10nm_PHY_PLL_DSM_DIVIDER);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
216
writel(0x4e, base + REG_DSI_10nm_PHY_PLL_FEEDBACK_DIVIDER);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
217
writel(0x40, base + REG_DSI_10nm_PHY_PLL_CALIBRATION_SETTINGS);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
218
writel(0xba, base + REG_DSI_10nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
219
writel(0x0c, base + REG_DSI_10nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
220
writel(0x00, base + REG_DSI_10nm_PHY_PLL_OUTDIV);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
221
writel(0x00, base + REG_DSI_10nm_PHY_PLL_CORE_OVERRIDE);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
222
writel(0x08, base + REG_DSI_10nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
223
writel(0x08, base + REG_DSI_10nm_PHY_PLL_PLL_PROP_GAIN_RATE_1);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
224
writel(0xc0, base + REG_DSI_10nm_PHY_PLL_PLL_BAND_SET_RATE_1);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
225
writel(0xfa, base + REG_DSI_10nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
226
writel(0x4c, base + REG_DSI_10nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
227
writel(0x80, base + REG_DSI_10nm_PHY_PLL_PLL_LOCK_OVERRIDE);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
228
writel(0x29, base + REG_DSI_10nm_PHY_PLL_PFILT);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
229
writel(0x3f, base + REG_DSI_10nm_PHY_PLL_IFILT);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
236
writel(0x12, base + REG_DSI_10nm_PHY_PLL_CORE_INPUT_OVERRIDE);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
237
writel(config->decimal_div_start,
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
239
writel(config->frac_div_start & 0xff,
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
241
writel((config->frac_div_start & 0xff00) >> 8,
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
243
writel((config->frac_div_start & 0x30000) >> 16,
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
245
writel(64, base + REG_DSI_10nm_PHY_PLL_PLL_LOCKDET_RATE_1);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
246
writel(0x06, base + REG_DSI_10nm_PHY_PLL_PLL_LOCK_DELAY);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
247
writel(0x10, base + REG_DSI_10nm_PHY_PLL_CMODE);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
248
writel(config->pll_clock_inverters, base + REG_DSI_10nm_PHY_PLL_CLOCK_INVERTERS);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
305
writel(0, pll->phy->pll_base + REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
306
writel(data & ~BIT(5), pll->phy->base + REG_DSI_10nm_PHY_CMN_CTRL_0);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
314
writel(data | BIT(5), pll->phy->base + REG_DSI_10nm_PHY_CMN_CTRL_0);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
315
writel(0xc0, pll->phy->pll_base + REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
324
writel(data & ~BIT(5), pll->phy->base + REG_DSI_10nm_PHY_CMN_CLK_CFG1);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
332
writel(data | BIT(5), pll->phy->base + REG_DSI_10nm_PHY_CMN_CLK_CFG1);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
352
writel(0x01, pll_10nm->phy->base + REG_DSI_10nm_PHY_CMN_PLL_CNTRL);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
373
writel(0x01, pll_10nm->phy->base + REG_DSI_10nm_PHY_CMN_RBUF_CTRL);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
375
writel(0x01, pll_10nm->slave->phy->base + REG_DSI_10nm_PHY_CMN_RBUF_CTRL);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
383
writel(0, pll->phy->base + REG_DSI_10nm_PHY_CMN_RBUF_CTRL);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
397
writel(0, pll_10nm->phy->base + REG_DSI_10nm_PHY_CMN_PLL_CNTRL);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
504
writel(val, pll_10nm->phy->pll_base + REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
506
writel(cached->bit_clk_div | (cached->pix_clk_div << 4),
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
512
writel(val, phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG1);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
550
writel(data << 2, base + REG_DSI_10nm_PHY_CMN_CLK_CFG1);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
736
writel(0x3, lane_base + REG_DSI_10nm_PHY_LN_LPRX_CTRL(phy_lane_0));
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
738
writel(0, lane_base + REG_DSI_10nm_PHY_LN_LPRX_CTRL(phy_lane_0));
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
753
writel(0x55, lane_base + REG_DSI_10nm_PHY_LN_LPTX_STR_CTRL(i));
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
759
writel(0, lane_base + REG_DSI_10nm_PHY_LN_LPRX_CTRL(i));
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
760
writel(0x0, lane_base + REG_DSI_10nm_PHY_LN_PIN_SWAP(i));
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
761
writel(0x88, lane_base + REG_DSI_10nm_PHY_LN_HSTX_STR_CTRL(i));
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
768
writel(0, lane_base + REG_DSI_10nm_PHY_LN_CFG0(i));
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
769
writel(0, lane_base + REG_DSI_10nm_PHY_LN_CFG1(i));
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
770
writel(0, lane_base + REG_DSI_10nm_PHY_LN_CFG2(i));
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
771
writel(i == 4 ? 0x80 : 0x0, lane_base + REG_DSI_10nm_PHY_LN_CFG3(i));
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
774
writel(tuning_cfg->rescode_offset_top[i],
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
776
writel(tuning_cfg->rescode_offset_bot[i],
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
779
writel(tx_dctrl[i],
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
785
writel(0x05, lane_base + REG_DSI_10nm_PHY_LN_TX_DCTRL(3));
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
786
writel(0x04, lane_base + REG_DSI_10nm_PHY_LN_TX_DCTRL(3));
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
824
writel(data, base + REG_DSI_10nm_PHY_CMN_CTRL_0);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
827
writel(0x00, base + REG_DSI_10nm_PHY_CMN_PLL_CNTRL);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
830
writel(0x00, base + REG_DSI_10nm_PHY_CMN_RBUF_CTRL);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
833
writel(0x10, base + REG_DSI_10nm_PHY_CMN_GLBL_CTRL);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
836
writel(tuning_cfg->vreg_ctrl, base + REG_DSI_10nm_PHY_CMN_VREG_CTRL);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
839
writel(0x21, base + REG_DSI_10nm_PHY_CMN_LANE_CFG0);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
840
writel(0x84, base + REG_DSI_10nm_PHY_CMN_LANE_CFG1);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
843
writel(timing->hs_halfbyte_en, base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_0);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
844
writel(timing->clk_zero, base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_1);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
845
writel(timing->clk_prepare, base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_2);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
846
writel(timing->clk_trail, base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_3);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
847
writel(timing->hs_exit, base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_4);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
848
writel(timing->hs_zero, base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_5);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
849
writel(timing->hs_prepare, base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_6);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
850
writel(timing->hs_trail, base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_7);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
851
writel(timing->hs_rqst, base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_8);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
852
writel(timing->ta_go | (timing->ta_sure << 3), base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_9);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
853
writel(timing->ta_get, base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_10);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
854
writel(0x00, base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_11);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
857
writel(0x7f, base + REG_DSI_10nm_PHY_CMN_CTRL_0);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
864
writel(data, base + REG_DSI_10nm_PHY_CMN_CTRL_0);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
865
writel(0x1F, base + REG_DSI_10nm_PHY_CMN_LANE_CTRL0);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
868
writel(0x40, base + REG_DSI_10nm_PHY_CMN_CTRL_2);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
900
writel(data, base + REG_DSI_10nm_PHY_CMN_CTRL_0);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
901
writel(0, base + REG_DSI_10nm_PHY_CMN_LANE_CTRL0);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
904
writel(0x00, base + REG_DSI_10nm_PHY_CMN_CTRL_0);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
1000
writel(glbl_test_ctrl, base + REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
1009
writel(0xff, base + REG_DSI_14nm_PHY_CMN_CTRL_0);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
1016
writel(0, phy->base + REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
1017
writel(0, phy->base + REG_DSI_14nm_PHY_CMN_CTRL_0);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
292
writel(data, base + REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER1);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
295
writel(data, base + REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER2);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
299
writel(data, base + REG_DSI_14nm_PHY_PLL_SSC_PER1);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
302
writel(data, base + REG_DSI_14nm_PHY_PLL_SSC_PER2);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
306
writel(data, base + REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE1);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
309
writel(data, base + REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE2);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
314
writel(data, base + REG_DSI_14nm_PHY_PLL_SSC_EN_CENTER);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
327
writel(data, base + REG_DSI_14nm_PHY_PLL_SYSCLK_EN_RESET);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
329
writel(1, base + REG_DSI_14nm_PHY_PLL_TXCLK_EN);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
331
writel(48, base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
333
writel(4 << 3, base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL2);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
335
writel(5, base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL5);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
338
writel(data, base + REG_DSI_14nm_PHY_PLL_VCO_DIV_REF1);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
340
writel(data, base + REG_DSI_14nm_PHY_PLL_VCO_DIV_REF2);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
343
writel(data, base + REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF1);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
345
writel(data, base + REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF2);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
347
writel(16, base + REG_DSI_14nm_PHY_PLL_PLL_MISC1);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
349
writel(4, base + REG_DSI_14nm_PHY_PLL_IE_TRIM);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
351
writel(4, base + REG_DSI_14nm_PHY_PLL_IP_TRIM);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
353
writel(1 << 3 | 1, base + REG_DSI_14nm_PHY_PLL_CP_SET_CUR);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
355
writel(0 << 3 | 0, base + REG_DSI_14nm_PHY_PLL_PLL_ICPCSET);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
357
writel(0 << 3 | 0, base + REG_DSI_14nm_PHY_PLL_PLL_ICPMSET);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
359
writel(4 << 3 | 4, base + REG_DSI_14nm_PHY_PLL_PLL_ICP_SET);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
361
writel(1 << 4 | 11, base + REG_DSI_14nm_PHY_PLL_PLL_LPF1);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
363
writel(7, base + REG_DSI_14nm_PHY_PLL_IPTAT_TRIM);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
365
writel(1 << 4 | 2, base + REG_DSI_14nm_PHY_PLL_PLL_CRCTRL);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
375
writel(0, cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
378
writel(0x20, cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_1);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
382
writel(0, cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_1);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
395
writel(0x3c, cmn_base + REG_DSI_14nm_PHY_CMN_LDO_CNTRL);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
402
writel(1, cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG1);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
405
writel(data, cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_0);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
409
writel(data, base + REG_DSI_14nm_PHY_PLL_DEC_START);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
412
writel(data, base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START1);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
414
writel(data, base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START2);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
416
writel(data, base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START3);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
419
writel(data, base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP1);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
422
writel(data, base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP2);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
425
writel(data, base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP3);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
428
writel(data, base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP_EN);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
431
writel(data, base + REG_DSI_14nm_PHY_PLL_VCO_COUNT1);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
433
writel(data, base + REG_DSI_14nm_PHY_PLL_VCO_COUNT2);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
436
writel(data, base + REG_DSI_14nm_PHY_PLL_KVCO_COUNT1);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
438
writel(data, base + REG_DSI_14nm_PHY_PLL_KVCO_COUNT2);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
449
writel(0 << 4 | 3, base + REG_DSI_14nm_PHY_PLL_PLL_LPF2_POSTDIV);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
549
writel(0x10, base + REG_DSI_14nm_PHY_PLL_VREF_CFG1);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
550
writel(1, cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
576
writel(0, cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
659
writel(val, base + REG_DSI_14nm_PHY_CMN_CLK_CFG0);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
668
writel(val, slave_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
725
writel(data, cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
732
writel(data, slave_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
760
writel(clkbuflr_en, base + REG_DSI_14nm_PHY_PLL_CLKBUFLR_EN);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
762
writel(bandgap, base + REG_DSI_14nm_PHY_PLL_PLL_BANDGAP);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
919
writel(DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT(timing->hs_exit),
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
921
writel(DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO(zero),
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
923
writel(DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE(prepare),
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
925
writel(DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL(trail),
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
927
writel(DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST(rqst),
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
929
writel(DSI_14nm_PHY_LN_CFG0_PREPARE_DLY(prep_dly),
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
931
writel(halfbyte_en ? DSI_14nm_PHY_LN_CFG1_HALFBYTECLK_EN : 0,
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
933
writel(DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO(timing->ta_go) |
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
936
writel(DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET(timing->ta_get),
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
938
writel(DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD(0xa0),
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
963
writel(data, base + REG_DSI_14nm_PHY_CMN_LDO_CNTRL);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
965
writel(0x1, base + REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
969
writel(0x1d, lane_base + REG_DSI_14nm_PHY_LN_VREG_CNTRL(i));
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
971
writel(0xff, lane_base + REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_0(i));
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
972
writel(i == PHY_14NM_CKLN_IDX ? 0x00 : 0x06,
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
975
writel(i == PHY_14NM_CKLN_IDX ? 0x8f : 0x0f,
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
977
writel(0x10, lane_base + REG_DSI_14nm_PHY_LN_CFG2(i));
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
978
writel(0, lane_base + REG_DSI_14nm_PHY_LN_TEST_DATAPATH(i));
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
979
writel(0x88, lane_base + REG_DSI_14nm_PHY_LN_TEST_STR(i));
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
985
writel(0x00, base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
990
writel(0x80, base + REG_DSI_14nm_PHY_CMN_CTRL_1);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
993
writel(0x00, base + REG_DSI_14nm_PHY_CMN_CTRL_1);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
100
writel(0xa0, base + REG_DSI_20nm_PHY_LN_CFG_1(i));
drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
101
writel(cfg_4[i], base + REG_DSI_20nm_PHY_LN_CFG_4(i));
drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
104
writel(0x80, base + REG_DSI_20nm_PHY_LNCK_CFG_3);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
105
writel(0x01, base + REG_DSI_20nm_PHY_LNCK_TEST_STR0);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
106
writel(0x46, base + REG_DSI_20nm_PHY_LNCK_TEST_STR1);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
107
writel(0x00, base + REG_DSI_20nm_PHY_LNCK_CFG_0);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
108
writel(0xa0, base + REG_DSI_20nm_PHY_LNCK_CFG_1);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
109
writel(0x00, base + REG_DSI_20nm_PHY_LNCK_CFG_2);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
110
writel(0x00, base + REG_DSI_20nm_PHY_LNCK_CFG_4);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
114
writel(0x00, base + REG_DSI_20nm_PHY_CTRL_1);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
116
writel(0x06, base + REG_DSI_20nm_PHY_STRENGTH_1);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
120
writel(0x7f, base + REG_DSI_20nm_PHY_CTRL_0);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
127
writel(0, phy->base + REG_DSI_20nm_PHY_CTRL_0);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
15
writel(DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO(timing->clk_zero),
drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
17
writel(DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL(timing->clk_trail),
drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
19
writel(DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE(timing->clk_prepare),
drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
22
writel(DSI_20nm_PHY_TIMING_CTRL_3_CLK_ZERO_8,
drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
24
writel(DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT(timing->hs_exit),
drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
26
writel(DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO(timing->hs_zero),
drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
28
writel(DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE(timing->hs_prepare),
drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
30
writel(DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL(timing->hs_trail),
drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
32
writel(DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST(timing->hs_rqst),
drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
34
writel(DSI_20nm_PHY_TIMING_CTRL_9_TA_GO(timing->ta_go) |
drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
37
writel(DSI_20nm_PHY_TIMING_CTRL_10_TA_GET(timing->ta_get),
drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
39
writel(DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD(0),
drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
48
writel(0, base + REG_DSI_20nm_PHY_REGULATOR_CAL_PWR_CFG);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
53
writel(0x1d, phy->base + REG_DSI_20nm_PHY_LDO_CNTRL);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
58
writel(0x03, base + REG_DSI_20nm_PHY_REGULATOR_CTRL_1);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
59
writel(0x03, base + REG_DSI_20nm_PHY_REGULATOR_CTRL_2);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
60
writel(0x00, base + REG_DSI_20nm_PHY_REGULATOR_CTRL_3);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
61
writel(0x20, base + REG_DSI_20nm_PHY_REGULATOR_CTRL_4);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
62
writel(0x01, base + REG_DSI_20nm_PHY_REGULATOR_CAL_PWR_CFG);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
63
writel(0x00, phy->base + REG_DSI_20nm_PHY_LDO_CNTRL);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
64
writel(0x03, base + REG_DSI_20nm_PHY_REGULATOR_CTRL_0);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
86
writel(0xff, base + REG_DSI_20nm_PHY_STRENGTH_0);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
93
writel(val, base + REG_DSI_20nm_PHY_GLBL_TEST_CTRL);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
96
writel((i >> 1) * 0x40, base + REG_DSI_20nm_PHY_LN_CFG_3(i));
drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
97
writel(0x01, base + REG_DSI_20nm_PHY_LN_TEST_STR_0(i));
drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
98
writel(0x46, base + REG_DSI_20nm_PHY_LN_TEST_STR_1(i));
drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
99
writel(0x02, base + REG_DSI_20nm_PHY_LN_CFG_0(i));
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
108
writel(DSI_28nm_PHY_PLL_TEST_CFG_PLL_SW_RESET, base + REG_DSI_28nm_PHY_PLL_TEST_CFG);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
110
writel(0, base + REG_DSI_28nm_PHY_PLL_TEST_CFG);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
133
writel(3, base + REG_DSI_28nm_PHY_PLL_POSTDIV2_CFG);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
144
writel(lpfr_lut[i].resistance, base + REG_DSI_28nm_PHY_PLL_LPFR_CFG);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
147
writel(0x70, base + REG_DSI_28nm_PHY_PLL_LPFC1_CFG);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
148
writel(0x15, base + REG_DSI_28nm_PHY_PLL_LPFC2_CFG);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
200
writel(0x02, base + REG_DSI_28nm_PHY_PLL_CHGPUMP_CFG);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
201
writel(0x2b, base + REG_DSI_28nm_PHY_PLL_CAL_CFG3);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
202
writel(0x06, base + REG_DSI_28nm_PHY_PLL_CAL_CFG4);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
203
writel(0x0d, base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
205
writel(sdm_cfg1, base + REG_DSI_28nm_PHY_PLL_SDM_CFG1);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
206
writel(DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0(sdm_cfg2),
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
208
writel(DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8(sdm_cfg3),
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
210
writel(0, base + REG_DSI_28nm_PHY_PLL_SDM_CFG4);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
218
writel(refclk_cfg, base + REG_DSI_28nm_PHY_PLL_REFCLK_CFG);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
219
writel(0x00, base + REG_DSI_28nm_PHY_PLL_PWRGEN_CFG);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
220
writel(0x31, base + REG_DSI_28nm_PHY_PLL_VCOLPF_CFG);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
221
writel(sdm_cfg0, base + REG_DSI_28nm_PHY_PLL_SDM_CFG0);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
222
writel(0x12, base + REG_DSI_28nm_PHY_PLL_CAL_CFG0);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
223
writel(0x30, base + REG_DSI_28nm_PHY_PLL_CAL_CFG6);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
224
writel(0x00, base + REG_DSI_28nm_PHY_PLL_CAL_CFG7);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
225
writel(0x60, base + REG_DSI_28nm_PHY_PLL_CAL_CFG8);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
226
writel(0x00, base + REG_DSI_28nm_PHY_PLL_CAL_CFG9);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
227
writel(cal_cfg10 & 0xff, base + REG_DSI_28nm_PHY_PLL_CAL_CFG10);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
228
writel(cal_cfg11 & 0xff, base + REG_DSI_28nm_PHY_PLL_CAL_CFG11);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
229
writel(0x20, base + REG_DSI_28nm_PHY_PLL_EFUSE_CFG);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
308
writel(val, base + REG_DSI_28nm_PHY_PLL_GLB_CFG);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
312
writel(val, base + REG_DSI_28nm_PHY_PLL_GLB_CFG);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
316
writel(val, base + REG_DSI_28nm_PHY_PLL_GLB_CFG);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
320
writel(val, base + REG_DSI_28nm_PHY_PLL_GLB_CFG);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
325
writel(0x0c, base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
327
writel(0x0d, base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
342
writel(val, base + REG_DSI_28nm_PHY_PLL_GLB_CFG);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
346
writel(val, base + REG_DSI_28nm_PHY_PLL_GLB_CFG);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
350
writel(val, base + REG_DSI_28nm_PHY_PLL_GLB_CFG);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
354
writel(val, base + REG_DSI_28nm_PHY_PLL_GLB_CFG);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
358
writel(val, base + REG_DSI_28nm_PHY_PLL_GLB_CFG);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
362
writel(val, base + REG_DSI_28nm_PHY_PLL_GLB_CFG);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
411
writel(0x34, base + REG_DSI_28nm_PHY_PLL_CAL_CFG1);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
414
writel(val, base + REG_DSI_28nm_PHY_PLL_GLB_CFG);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
418
writel(val, base + REG_DSI_28nm_PHY_PLL_GLB_CFG);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
423
writel(val, base + REG_DSI_28nm_PHY_PLL_GLB_CFG);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
428
writel(0x0d, base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
429
writel(0x0c, base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
431
writel(0x0d, base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
445
writel(0x00, base + REG_DSI_28nm_PHY_PLL_PWRGEN_CFG);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
450
writel(val, base + REG_DSI_28nm_PHY_PLL_GLB_CFG);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
455
writel(val, base + REG_DSI_28nm_PHY_PLL_GLB_CFG);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
487
writel(0x34, base + REG_DSI_28nm_PHY_PLL_CAL_CFG1);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
491
writel(val, base + REG_DSI_28nm_PHY_PLL_GLB_CFG);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
495
writel(val, base + REG_DSI_28nm_PHY_PLL_GLB_CFG);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
500
writel(val, base + REG_DSI_28nm_PHY_PLL_GLB_CFG);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
504
writel(0x04, base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
506
writel(0x05, base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
531
writel(0, pll_28nm->phy->pll_base + REG_DSI_28nm_PHY_PLL_GLB_CFG);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
611
writel(cached_state->postdiv3, base + REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
612
writel(cached_state->postdiv1, base + REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
613
writel(cached_state->byte_mux, base + REG_DSI_28nm_PHY_PLL_VREG_CFG);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
723
writel(DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO(timing->clk_zero),
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
725
writel(DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL(timing->clk_trail),
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
727
writel(DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE(timing->clk_prepare),
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
730
writel(DSI_28nm_PHY_TIMING_CTRL_3_CLK_ZERO_8,
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
732
writel(DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT(timing->hs_exit),
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
734
writel(DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO(timing->hs_zero),
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
736
writel(DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE(timing->hs_prepare),
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
738
writel(DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL(timing->hs_trail),
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
740
writel(DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST(timing->hs_rqst),
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
742
writel(DSI_28nm_PHY_TIMING_CTRL_9_TA_GO(timing->ta_go) |
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
745
writel(DSI_28nm_PHY_TIMING_CTRL_10_TA_GET(timing->ta_get),
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
747
writel(DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD(0),
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
755
writel(0x0, base + REG_DSI_28nm_PHY_REGULATOR_CTRL_0);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
756
writel(1, base + REG_DSI_28nm_PHY_REGULATOR_CAL_PWR_CFG);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
757
writel(0, base + REG_DSI_28nm_PHY_REGULATOR_CTRL_5);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
758
writel(0, base + REG_DSI_28nm_PHY_REGULATOR_CTRL_3);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
759
writel(0x3, base + REG_DSI_28nm_PHY_REGULATOR_CTRL_2);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
760
writel(0x9, base + REG_DSI_28nm_PHY_REGULATOR_CTRL_1);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
761
writel(0x7, base + REG_DSI_28nm_PHY_REGULATOR_CTRL_0);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
762
writel(0x20, base + REG_DSI_28nm_PHY_REGULATOR_CTRL_4);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
763
writel(0x00, phy->base + REG_DSI_28nm_PHY_LDO_CNTRL);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
770
writel(0x0, base + REG_DSI_28nm_PHY_REGULATOR_CTRL_0);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
771
writel(0, base + REG_DSI_28nm_PHY_REGULATOR_CAL_PWR_CFG);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
772
writel(0x7, base + REG_DSI_28nm_PHY_REGULATOR_CTRL_5);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
773
writel(0, base + REG_DSI_28nm_PHY_REGULATOR_CTRL_3);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
774
writel(0x1, base + REG_DSI_28nm_PHY_REGULATOR_CTRL_2);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
775
writel(0x1, base + REG_DSI_28nm_PHY_REGULATOR_CTRL_1);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
776
writel(0x20, base + REG_DSI_28nm_PHY_REGULATOR_CTRL_4);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
779
writel(0x05, phy->base + REG_DSI_28nm_PHY_LDO_CNTRL);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
781
writel(0x0d, phy->base + REG_DSI_28nm_PHY_LDO_CNTRL);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
787
writel(0, phy->reg_base + REG_DSI_28nm_PHY_REGULATOR_CAL_PWR_CFG);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
814
writel(0xff, base + REG_DSI_28nm_PHY_STRENGTH_0);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
820
writel(0x00, base + REG_DSI_28nm_PHY_CTRL_1);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
821
writel(0x5f, base + REG_DSI_28nm_PHY_CTRL_0);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
823
writel(0x6, base + REG_DSI_28nm_PHY_STRENGTH_1);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
826
writel(0, base + REG_DSI_28nm_PHY_LN_CFG_0(i));
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
827
writel(0, base + REG_DSI_28nm_PHY_LN_CFG_1(i));
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
828
writel(0, base + REG_DSI_28nm_PHY_LN_CFG_2(i));
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
829
writel(0, base + REG_DSI_28nm_PHY_LN_CFG_3(i));
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
830
writel(0, base + REG_DSI_28nm_PHY_LN_CFG_4(i));
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
831
writel(0, base + REG_DSI_28nm_PHY_LN_TEST_DATAPATH(i));
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
832
writel(0, base + REG_DSI_28nm_PHY_LN_DEBUG_SEL(i));
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
833
writel(0x1, base + REG_DSI_28nm_PHY_LN_TEST_STR_0(i));
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
834
writel(0x97, base + REG_DSI_28nm_PHY_LN_TEST_STR_1(i));
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
837
writel(0, base + REG_DSI_28nm_PHY_LNCK_CFG_4);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
838
writel(0xc0, base + REG_DSI_28nm_PHY_LNCK_CFG_1);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
839
writel(0x1, base + REG_DSI_28nm_PHY_LNCK_TEST_STR0);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
840
writel(0xbb, base + REG_DSI_28nm_PHY_LNCK_TEST_STR1);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
842
writel(0x5f, base + REG_DSI_28nm_PHY_CTRL_0);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
849
writel(val, base + REG_DSI_28nm_PHY_GLBL_TEST_CTRL);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
856
writel(0, phy->base + REG_DSI_28nm_PHY_CTRL_0);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
107
writel(fb_divider & 0xff, base + REG_DSI_28nm_8960_PHY_PLL_CTRL_1);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
113
writel(val, base + REG_DSI_28nm_8960_PHY_PLL_CTRL_2);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
119
writel(val, base + REG_DSI_28nm_8960_PHY_PLL_CTRL_3);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
121
writel(0xf, base + REG_DSI_28nm_8960_PHY_PLL_CTRL_6);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
125
writel(val, base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
201
writel(val, base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
204
writel(DSI_28nm_8960_PHY_PLL_CTRL_0_ENABLE,
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
229
writel(0x00, pll_28nm->phy->pll_base + REG_DSI_28nm_8960_PHY_PLL_CTRL_0);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
324
writel(val, bytediv->reg);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
370
writel(cached_state->postdiv3, base + REG_DSI_28nm_8960_PHY_PLL_CTRL_10);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
371
writel(cached_state->postdiv2, base + REG_DSI_28nm_8960_PHY_PLL_CTRL_9);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
372
writel(cached_state->postdiv1, base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
473
writel(DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO(timing->clk_zero),
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
475
writel(DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL(timing->clk_trail),
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
477
writel(DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE(timing->clk_prepare),
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
479
writel(0, base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_3);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
480
writel(DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT(timing->hs_exit),
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
482
writel(DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO(timing->hs_zero),
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
484
writel(DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE(timing->hs_prepare),
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
486
writel(DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL(timing->hs_trail),
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
488
writel(DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST(timing->hs_rqst),
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
490
writel(DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO(timing->ta_go) |
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
493
writel(DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET(timing->ta_get),
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
495
writel(DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD(0),
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
503
writel(0x3, base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_0);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
504
writel(1, base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_1);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
505
writel(1, base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_2);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
506
writel(0, base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_3);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
507
writel(0x100, base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_4);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
514
writel(0x3, base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_0);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
515
writel(0xa, base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_1);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
516
writel(0x4, base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_2);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
517
writel(0x0, base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_3);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
518
writel(0x20, base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_4);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
527
writel(0x3, base + REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CAL_PWR_CFG);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
529
writel(0x0, base + REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_2);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
530
writel(0x5a, base + REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_1);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
531
writel(0x10, base + REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_3);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
532
writel(0x1, base + REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_4);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
533
writel(0x1, base + REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_0);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
535
writel(0x1, base + REG_DSI_28nm_8960_PHY_MISC_CAL_HW_TRIGGER);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
537
writel(0x0, base + REG_DSI_28nm_8960_PHY_MISC_CAL_HW_TRIGGER);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
556
writel(0x80, base + REG_DSI_28nm_8960_PHY_LN_CFG_0(i));
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
557
writel(0x45, base + REG_DSI_28nm_8960_PHY_LN_CFG_1(i));
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
558
writel(0x00, base + REG_DSI_28nm_8960_PHY_LN_CFG_2(i));
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
559
writel(0x00, base + REG_DSI_28nm_8960_PHY_LN_TEST_DATAPATH(i));
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
560
writel(0x01, base + REG_DSI_28nm_8960_PHY_LN_TEST_STR_0(i));
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
561
writel(0x66, base + REG_DSI_28nm_8960_PHY_LN_TEST_STR_1(i));
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
564
writel(0x40, base + REG_DSI_28nm_8960_PHY_LNCK_CFG_0);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
565
writel(0x67, base + REG_DSI_28nm_8960_PHY_LNCK_CFG_1);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
566
writel(0x0, base + REG_DSI_28nm_8960_PHY_LNCK_CFG_2);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
567
writel(0x0, base + REG_DSI_28nm_8960_PHY_LNCK_TEST_DATAPATH);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
568
writel(0x1, base + REG_DSI_28nm_8960_PHY_LNCK_TEST_STR0);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
569
writel(0x88, base + REG_DSI_28nm_8960_PHY_LNCK_TEST_STR1);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
589
writel(0x04, base + REG_DSI_28nm_8960_PHY_LDO_CTRL);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
592
writel(0xff, base + REG_DSI_28nm_8960_PHY_STRENGTH_0);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
593
writel(0x00, base + REG_DSI_28nm_8960_PHY_STRENGTH_1);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
594
writel(0x06, base + REG_DSI_28nm_8960_PHY_STRENGTH_2);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
597
writel(0x5f, base + REG_DSI_28nm_8960_PHY_CTRL_0);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
598
writel(0x00, base + REG_DSI_28nm_8960_PHY_CTRL_1);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
599
writel(0x00, base + REG_DSI_28nm_8960_PHY_CTRL_2);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
600
writel(0x10, base + REG_DSI_28nm_8960_PHY_CTRL_3);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
608
writel(0x0f, base + REG_DSI_28nm_8960_PHY_BIST_CTRL_4);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
609
writel(0x03, base + REG_DSI_28nm_8960_PHY_BIST_CTRL_1);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
610
writel(0x03, base + REG_DSI_28nm_8960_PHY_BIST_CTRL_0);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
611
writel(0x0, base + REG_DSI_28nm_8960_PHY_BIST_CTRL_4);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
620
writel(0x0, phy->base + REG_DSI_28nm_8960_PHY_CTRL_0);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
1090
writel(data, base + REG_DSI_7nm_PHY_CMN_CTRL_0);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
1093
writel(0x00, base + REG_DSI_7nm_PHY_CMN_PLL_CNTRL);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
1096
writel(0x00, base + REG_DSI_7nm_PHY_CMN_RBUF_CTRL);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
1102
writel(0x04, base + REG_DSI_7nm_PHY_CMN_CTRL_4);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
1105
writel(0x21, base + REG_DSI_7nm_PHY_CMN_LANE_CFG0);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
1106
writel(0x84, base + REG_DSI_7nm_PHY_CMN_LANE_CFG1);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
1109
writel(BIT(6), base + REG_DSI_7nm_PHY_CMN_GLBL_CTRL);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
1112
writel(vreg_ctrl_0, base + REG_DSI_7nm_PHY_CMN_VREG_CTRL_0);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
1113
writel(vreg_ctrl_1, base + REG_DSI_7nm_PHY_CMN_VREG_CTRL_1);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
1115
writel(0x00, base + REG_DSI_7nm_PHY_CMN_CTRL_3);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
1116
writel(glbl_str_swi_cal_sel_ctrl,
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
1118
writel(glbl_hstx_str_ctrl_0,
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
1120
writel(glbl_pemph_ctrl_0,
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
1123
writel(0x01, base + REG_DSI_7nm_PHY_CMN_GLBL_PEMPH_CTRL_1);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
1124
writel(glbl_rescode_top_ctrl,
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
1126
writel(glbl_rescode_bot_ctrl,
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
1128
writel(0x55, base + REG_DSI_7nm_PHY_CMN_GLBL_LPTX_STR_CTRL);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
1131
writel(0x7f, base + REG_DSI_7nm_PHY_CMN_CTRL_0);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
1133
writel(lane_ctrl0, base + REG_DSI_7nm_PHY_CMN_LANE_CTRL0);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
1137
writel(0x40, base + REG_DSI_7nm_PHY_CMN_CTRL_2);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
1148
writel(0x00, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_0);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
1149
writel(timing->hs_exit, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_4);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
1150
writel(timing->shared_timings.clk_pre,
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
1152
writel(timing->clk_prepare, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_6);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
1153
writel(timing->shared_timings.clk_post,
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
1155
writel(timing->hs_rqst, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_8);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
1156
writel(0x02, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_9);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
1157
writel(0x04, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_10);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
1158
writel(0x00, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_11);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
1160
writel(0x00, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_0);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
1161
writel(timing->clk_zero, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_1);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
1162
writel(timing->clk_prepare, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_2);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
1163
writel(timing->clk_trail, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_3);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
1164
writel(timing->hs_exit, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_4);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
1165
writel(timing->hs_zero, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_5);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
1166
writel(timing->hs_prepare, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_6);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
1167
writel(timing->hs_trail, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_7);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
1168
writel(timing->hs_rqst, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_8);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
1169
writel(0x02, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_9);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
1170
writel(0x04, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_10);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
1171
writel(0x00, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_11);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
1172
writel(timing->shared_timings.clk_pre,
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
1174
writel(timing->shared_timings.clk_post,
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
1196
writel(data, base + REG_DSI_7nm_PHY_CMN_LANE_CTRL1);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
1217
writel(0x0, base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE10);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
1227
writel(data, base + REG_DSI_7nm_PHY_CMN_CTRL_0);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
1228
writel(0, base + REG_DSI_7nm_PHY_CMN_LANE_CTRL0);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
1231
writel(0x00, base + REG_DSI_7nm_PHY_CMN_CTRL_0);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
245
writel(config->ssc_stepsize & 0xff,
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
247
writel(config->ssc_stepsize >> 8,
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
249
writel(config->ssc_div_per & 0xff,
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
251
writel(config->ssc_div_per >> 8,
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
253
writel(config->ssc_adj_per & 0xff,
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
255
writel(config->ssc_adj_per >> 8,
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
257
writel(SSC_EN | (config->ssc_center ? SSC_CENTER : 0),
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
294
writel(analog_controls_five_1, base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE_1);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
295
writel(vco_config_1, base + REG_DSI_7nm_PHY_PLL_VCO_CONFIG_1);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
296
writel(0x01, base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
297
writel(0x03, base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_TWO);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
298
writel(0x00, base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_THREE);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
299
writel(0x00, base + REG_DSI_7nm_PHY_PLL_DSM_DIVIDER);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
300
writel(0x4e, base + REG_DSI_7nm_PHY_PLL_FEEDBACK_DIVIDER);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
301
writel(0x40, base + REG_DSI_7nm_PHY_PLL_CALIBRATION_SETTINGS);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
302
writel(0xba, base + REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
303
writel(0x0c, base + REG_DSI_7nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
304
writel(0x00, base + REG_DSI_7nm_PHY_PLL_OUTDIV);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
305
writel(0x00, base + REG_DSI_7nm_PHY_PLL_CORE_OVERRIDE);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
306
writel(0x08, base + REG_DSI_7nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
307
writel(0x0a, base + REG_DSI_7nm_PHY_PLL_PLL_PROP_GAIN_RATE_1);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
308
writel(0xc0, base + REG_DSI_7nm_PHY_PLL_PLL_BAND_SEL_RATE_1);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
309
writel(0x84, base + REG_DSI_7nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
310
writel(0x82, base + REG_DSI_7nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
311
writel(0x4c, base + REG_DSI_7nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
312
writel(0x80, base + REG_DSI_7nm_PHY_PLL_PLL_LOCK_OVERRIDE);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
313
writel(0x29, base + REG_DSI_7nm_PHY_PLL_PFILT);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
314
writel(0x2f, base + REG_DSI_7nm_PHY_PLL_PFILT);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
315
writel(0x2a, base + REG_DSI_7nm_PHY_PLL_IFILT);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
316
writel(!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1) ? 0x3f : 0x22,
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
320
writel(0x22, base + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
322
writel(0x22, pll->slave->phy->pll_base + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
330
writel(0x12, base + REG_DSI_7nm_PHY_PLL_CORE_INPUT_OVERRIDE);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
331
writel(config->decimal_div_start,
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
333
writel(config->frac_div_start & 0xff,
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
335
writel((config->frac_div_start & 0xff00) >> 8,
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
337
writel((config->frac_div_start & 0x30000) >> 16,
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
339
writel(0x40, base + REG_DSI_7nm_PHY_PLL_PLL_LOCKDET_RATE_1);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
340
writel(0x06, base + REG_DSI_7nm_PHY_PLL_PLL_LOCK_DELAY);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
341
writel(pll->phy->cphy_mode ? 0x00 : 0x10,
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
343
writel(config->pll_clock_inverters,
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
417
writel(0, pll->phy->pll_base + REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
418
writel(data, pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
434
writel(data, pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
436
writel(0xc0, pll->phy->pll_base + REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
446
writel(val, pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG0);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
461
writel(data, pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
474
writel(0x04, pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_3);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
485
writel(BIT(0), pll->phy->base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE4);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
487
writel(0, pll->phy->base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE4);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
501
writel(BIT(0), pll_7nm->phy->base + REG_DSI_7nm_PHY_CMN_PLL_CNTRL);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
531
writel(0x1, pll_7nm->phy->base + REG_DSI_7nm_PHY_CMN_RBUF_CTRL);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
533
writel(0x1, pll_7nm->slave->phy->base + REG_DSI_7nm_PHY_CMN_RBUF_CTRL);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
541
writel(0, pll->phy->base + REG_DSI_7nm_PHY_CMN_RBUF_CTRL);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
555
writel(0, pll_7nm->phy->base + REG_DSI_7nm_PHY_CMN_PLL_CNTRL);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
666
writel(val, pll_7nm->phy->pll_base + REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
703
writel(0x07, base + REG_DSI_7nm_PHY_CMN_CTRL_5);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
918
writel(0x3, lane_base + REG_DSI_7nm_PHY_LN_LPRX_CTRL(phy_lane_0));
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
920
writel(0, lane_base + REG_DSI_7nm_PHY_LN_LPRX_CTRL(phy_lane_0));
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
941
writel(0, lane_base + REG_DSI_7nm_PHY_LN_LPRX_CTRL(i));
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
942
writel(0x0, lane_base + REG_DSI_7nm_PHY_LN_PIN_SWAP(i));
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
949
writel(0x0, lane_base + REG_DSI_7nm_PHY_LN_CFG0(i));
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
950
writel(0x0, lane_base + REG_DSI_7nm_PHY_LN_CFG1(i));
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
951
writel(i == 4 ? 0x8a : 0xa, lane_base + REG_DSI_7nm_PHY_LN_CFG2(i));
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
952
writel(tx_dctrl[i], lane_base + REG_DSI_7nm_PHY_LN_TX_DCTRL(i));
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
991
writel(0x1, phy->base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE10);
drivers/gpu/drm/msm/hdmi/hdmi.h
107
writel(data, hdmi->mmio + reg);
drivers/gpu/drm/msm/hdmi/hdmi.h
160
writel(data, phy->mmio + reg);
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
100
writel(data, pll->mmio_qserdes_tx[channel] + offset);
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
89
writel(data, pll->mmio_qserdes_com + offset);
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
88
writel(data, pll->mmio_qserdes_com + offset);
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
99
writel(data, pll->mmio_qserdes_tx[channel] + offset);
drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c
239
writel(data, pll->mmio + reg);
drivers/gpu/drm/msm/msm_drv.h
476
writel(val | or, addr);
drivers/gpu/drm/msm/msm_gpu.h
598
writel(data, gpu->mmio + (reg << 2));
drivers/gpu/drm/msm/msm_gpu.h
643
writel(lower_32_bits(val), gpu->mmio + (reg << 2));
drivers/gpu/drm/msm/msm_gpu.h
645
writel(upper_32_bits(val), gpu->mmio + ((reg + 1) << 2));
drivers/gpu/drm/mxsfb/lcdif_drv.c
128
writel(stat, lcdif->base + LCDC_V8_INT_STATUS_D0);
drivers/gpu/drm/mxsfb/lcdif_kms.c
173
writel(DISP_PARA_LINE_PATTERN_RGB565,
drivers/gpu/drm/mxsfb/lcdif_kms.c
177
writel(DISP_PARA_LINE_PATTERN_RGB888,
drivers/gpu/drm/mxsfb/lcdif_kms.c
181
writel(DISP_PARA_LINE_PATTERN_UYVY_H,
drivers/gpu/drm/mxsfb/lcdif_kms.c
193
writel(CTRLDESCL0_5_BPP_16_RGB565,
drivers/gpu/drm/mxsfb/lcdif_kms.c
197
writel(CTRLDESCL0_5_BPP_24_RGB888,
drivers/gpu/drm/mxsfb/lcdif_kms.c
201
writel(CTRLDESCL0_5_BPP_16_ARGB1555,
drivers/gpu/drm/mxsfb/lcdif_kms.c
205
writel(CTRLDESCL0_5_BPP_16_ARGB4444,
drivers/gpu/drm/mxsfb/lcdif_kms.c
209
writel(CTRLDESCL0_5_BPP_32_ABGR8888,
drivers/gpu/drm/mxsfb/lcdif_kms.c
213
writel(CTRLDESCL0_5_BPP_32_ARGB8888,
drivers/gpu/drm/mxsfb/lcdif_kms.c
219
writel(CTRLDESCL0_5_BPP_YCbCr422 | CTRLDESCL0_5_YUV_FORMAT_VY2UY1,
drivers/gpu/drm/mxsfb/lcdif_kms.c
224
writel(CTRLDESCL0_5_BPP_YCbCr422 | CTRLDESCL0_5_YUV_FORMAT_UY2VY1,
drivers/gpu/drm/mxsfb/lcdif_kms.c
229
writel(CTRLDESCL0_5_BPP_YCbCr422 | CTRLDESCL0_5_YUV_FORMAT_Y2VY1U,
drivers/gpu/drm/mxsfb/lcdif_kms.c
234
writel(CTRLDESCL0_5_BPP_YCbCr422 | CTRLDESCL0_5_YUV_FORMAT_Y2UY1V,
drivers/gpu/drm/mxsfb/lcdif_kms.c
253
writel(CSC0_CTRL_CSC_MODE_RGB2YCbCr,
drivers/gpu/drm/mxsfb/lcdif_kms.c
263
writel(CSC0_COEF0_A2(0x081) | CSC0_COEF0_A1(0x041),
drivers/gpu/drm/mxsfb/lcdif_kms.c
265
writel(CSC0_COEF1_B1(0x7db) | CSC0_COEF1_A3(0x019),
drivers/gpu/drm/mxsfb/lcdif_kms.c
267
writel(CSC0_COEF2_B3(0x070) | CSC0_COEF2_B2(0x7b6),
drivers/gpu/drm/mxsfb/lcdif_kms.c
269
writel(CSC0_COEF3_C2(0x7a2) | CSC0_COEF3_C1(0x070),
drivers/gpu/drm/mxsfb/lcdif_kms.c
271
writel(CSC0_COEF4_D1(0x010) | CSC0_COEF4_C3(0x7ee),
drivers/gpu/drm/mxsfb/lcdif_kms.c
273
writel(CSC0_COEF5_D3(0x080) | CSC0_COEF5_D2(0x080),
drivers/gpu/drm/mxsfb/lcdif_kms.c
281
writel(CSC0_CTRL_CSC_MODE_YCbCr2RGB,
drivers/gpu/drm/mxsfb/lcdif_kms.c
284
writel(coeffs[0], lcdif->base + LCDC_V8_CSC0_COEF0);
drivers/gpu/drm/mxsfb/lcdif_kms.c
285
writel(coeffs[1], lcdif->base + LCDC_V8_CSC0_COEF1);
drivers/gpu/drm/mxsfb/lcdif_kms.c
286
writel(coeffs[2], lcdif->base + LCDC_V8_CSC0_COEF2);
drivers/gpu/drm/mxsfb/lcdif_kms.c
287
writel(coeffs[3], lcdif->base + LCDC_V8_CSC0_COEF3);
drivers/gpu/drm/mxsfb/lcdif_kms.c
288
writel(coeffs[4], lcdif->base + LCDC_V8_CSC0_COEF4);
drivers/gpu/drm/mxsfb/lcdif_kms.c
289
writel(coeffs[5], lcdif->base + LCDC_V8_CSC0_COEF5);
drivers/gpu/drm/mxsfb/lcdif_kms.c
292
writel(CSC0_CTRL_BYPASS, lcdif->base + LCDC_V8_CSC0_CTRL);
drivers/gpu/drm/mxsfb/lcdif_kms.c
310
writel(ctrl, lcdif->base + LCDC_V8_CTRL);
drivers/gpu/drm/mxsfb/lcdif_kms.c
312
writel(DISP_SIZE_DELTA_Y(m->vdisplay) |
drivers/gpu/drm/mxsfb/lcdif_kms.c
316
writel(HSYN_PARA_BP_H(m->htotal - m->hsync_end) |
drivers/gpu/drm/mxsfb/lcdif_kms.c
320
writel(VSYN_PARA_BP_V(m->vtotal - m->vsync_end) |
drivers/gpu/drm/mxsfb/lcdif_kms.c
324
writel(VSYN_HSYN_WIDTH_PW_V(m->vsync_end - m->vsync_start) |
drivers/gpu/drm/mxsfb/lcdif_kms.c
328
writel(CTRLDESCL0_1_HEIGHT(m->vdisplay) |
drivers/gpu/drm/mxsfb/lcdif_kms.c
343
writel(ctrl, lcdif->base + LCDC_V8_CTRLDESCL0_3);
drivers/gpu/drm/mxsfb/lcdif_kms.c
351
writel(FIELD_PREP(PANIC0_THRES_LOW_MASK, 1 * PANIC0_THRES_MAX / 3) |
drivers/gpu/drm/mxsfb/lcdif_kms.c
359
writel(INT_ENABLE_D1_PLANE_PANIC_EN,
drivers/gpu/drm/mxsfb/lcdif_kms.c
364
writel(reg, lcdif->base + LCDC_V8_DISP_PARA);
drivers/gpu/drm/mxsfb/lcdif_kms.c
368
writel(reg, lcdif->base + LCDC_V8_CTRLDESCL0_5);
drivers/gpu/drm/mxsfb/lcdif_kms.c
378
writel(reg, lcdif->base + LCDC_V8_CTRLDESCL0_5);
drivers/gpu/drm/mxsfb/lcdif_kms.c
388
writel(reg, lcdif->base + LCDC_V8_DISP_PARA);
drivers/gpu/drm/mxsfb/lcdif_kms.c
391
writel(0, lcdif->base + LCDC_V8_INT_ENABLE_D1);
drivers/gpu/drm/mxsfb/lcdif_kms.c
396
writel(CTRL_SW_RESET, lcdif->base + LCDC_V8_CTRL + REG_SET);
drivers/gpu/drm/mxsfb/lcdif_kms.c
398
writel(CTRL_SW_RESET, lcdif->base + LCDC_V8_CTRL + REG_CLR);
drivers/gpu/drm/mxsfb/lcdif_kms.c
514
writel(reg, lcdif->base + LCDC_V8_CTRLDESCL0_5);
drivers/gpu/drm/mxsfb/lcdif_kms.c
550
writel(lower_32_bits(paddr),
drivers/gpu/drm/mxsfb/lcdif_kms.c
552
writel(CTRLDESCL_HIGH0_4_ADDR_HIGH(upper_32_bits(paddr)),
drivers/gpu/drm/mxsfb/lcdif_kms.c
629
writel(INT_STATUS_D0_VS_BLANK, lcdif->base + LCDC_V8_INT_STATUS_D0);
drivers/gpu/drm/mxsfb/lcdif_kms.c
630
writel(INT_ENABLE_D0_VS_BLANK_EN, lcdif->base + LCDC_V8_INT_ENABLE_D0);
drivers/gpu/drm/mxsfb/lcdif_kms.c
640
writel(0, lcdif->base + LCDC_V8_INT_ENABLE_D0);
drivers/gpu/drm/mxsfb/lcdif_kms.c
641
writel(INT_STATUS_D0_VS_BLANK, lcdif->base + LCDC_V8_INT_STATUS_D0);
drivers/gpu/drm/mxsfb/lcdif_kms.c
693
writel(lower_32_bits(paddr),
drivers/gpu/drm/mxsfb/lcdif_kms.c
695
writel(CTRLDESCL_HIGH0_4_ADDR_HIGH(upper_32_bits(paddr)),
drivers/gpu/drm/mxsfb/mxsfb_drv.c
173
writel(CTRL1_CUR_FRAME_DONE_IRQ, mxsfb->base + LCDC_CTRL1 + REG_CLR);
drivers/gpu/drm/mxsfb/mxsfb_drv.c
185
writel(CTRL1_CUR_FRAME_DONE_IRQ_EN, mxsfb->base + LCDC_CTRL1 + REG_CLR);
drivers/gpu/drm/mxsfb/mxsfb_drv.c
186
writel(CTRL1_CUR_FRAME_DONE_IRQ, mxsfb->base + LCDC_CTRL1 + REG_CLR);
drivers/gpu/drm/mxsfb/mxsfb_kms.c
106
writel(TRANSFER_COUNT_SET_VCOUNT(m->crtc_vdisplay) |
drivers/gpu/drm/mxsfb/mxsfb_kms.c
132
writel(vdctrl0, mxsfb->base + LCDC_VDCTRL0);
drivers/gpu/drm/mxsfb/mxsfb_kms.c
135
writel(m->crtc_vtotal, mxsfb->base + LCDC_VDCTRL1);
drivers/gpu/drm/mxsfb/mxsfb_kms.c
139
writel(set_hsync_pulse_width(mxsfb, hsync_pulse_len) |
drivers/gpu/drm/mxsfb/mxsfb_kms.c
143
writel(SET_HOR_WAIT_CNT(m->crtc_htotal - m->crtc_hsync_start) |
drivers/gpu/drm/mxsfb/mxsfb_kms.c
147
writel(SET_DOTCLK_H_VALID_DATA_CNT(m->hdisplay),
drivers/gpu/drm/mxsfb/mxsfb_kms.c
165
writel(reg, mxsfb->base + LCDC_V4_CTRL2);
drivers/gpu/drm/mxsfb/mxsfb_kms.c
169
writel(CTRL_DOTCLK_MODE, mxsfb->base + LCDC_CTRL + REG_SET);
drivers/gpu/drm/mxsfb/mxsfb_kms.c
174
writel(reg, mxsfb->base + LCDC_VDCTRL4);
drivers/gpu/drm/mxsfb/mxsfb_kms.c
203
writel(reg, mxsfb->base + LCDC_CTRL1);
drivers/gpu/drm/mxsfb/mxsfb_kms.c
205
writel(CTRL_RUN, mxsfb->base + LCDC_CTRL + REG_SET);
drivers/gpu/drm/mxsfb/mxsfb_kms.c
216
writel(CTRL_DOTCLK_MODE, mxsfb->base + LCDC_CTRL + REG_CLR);
drivers/gpu/drm/mxsfb/mxsfb_kms.c
223
writel(reg, mxsfb->base + LCDC_VDCTRL4);
drivers/gpu/drm/mxsfb/mxsfb_kms.c
239
writel(mask, addr + REG_CLR);
drivers/gpu/drm/mxsfb/mxsfb_kms.c
257
writel(CTRL_CLKGATE, mxsfb->base + LCDC_CTRL + REG_CLR);
drivers/gpu/drm/mxsfb/mxsfb_kms.c
268
writel(CTRL1_FIFO_CLEAR, mxsfb->base + LCDC_CTRL1 + REG_SET);
drivers/gpu/drm/mxsfb/mxsfb_kms.c
270
writel(CTRL1_FIFO_CLEAR, mxsfb->base + LCDC_CTRL1 + REG_CLR);
drivers/gpu/drm/mxsfb/mxsfb_kms.c
274
writel(0, mxsfb->base + LCDC_AS_CTRL);
drivers/gpu/drm/mxsfb/mxsfb_kms.c
394
writel(dma_addr, mxsfb->base + mxsfb->devdata->cur_buf);
drivers/gpu/drm/mxsfb/mxsfb_kms.c
395
writel(dma_addr, mxsfb->base + mxsfb->devdata->next_buf);
drivers/gpu/drm/mxsfb/mxsfb_kms.c
429
writel(CTRL1_CUR_FRAME_DONE_IRQ, mxsfb->base + LCDC_CTRL1 + REG_CLR);
drivers/gpu/drm/mxsfb/mxsfb_kms.c
430
writel(CTRL1_CUR_FRAME_DONE_IRQ_EN, mxsfb->base + LCDC_CTRL1 + REG_SET);
drivers/gpu/drm/mxsfb/mxsfb_kms.c
440
writel(CTRL1_CUR_FRAME_DONE_IRQ_EN, mxsfb->base + LCDC_CTRL1 + REG_CLR);
drivers/gpu/drm/mxsfb/mxsfb_kms.c
441
writel(CTRL1_CUR_FRAME_DONE_IRQ, mxsfb->base + LCDC_CTRL1 + REG_CLR);
drivers/gpu/drm/mxsfb/mxsfb_kms.c
549
writel(dma_addr, mxsfb->base + mxsfb->devdata->next_buf);
drivers/gpu/drm/mxsfb/mxsfb_kms.c
565
writel(0, mxsfb->base + LCDC_AS_CTRL);
drivers/gpu/drm/mxsfb/mxsfb_kms.c
577
writel(dma_addr, mxsfb->base + LCDC_AS_NEXT_BUF);
drivers/gpu/drm/mxsfb/mxsfb_kms.c
584
writel(dma_addr, mxsfb->base + LCDC_AS_BUF);
drivers/gpu/drm/mxsfb/mxsfb_kms.c
612
writel(ctrl, mxsfb->base + LCDC_AS_CTRL);
drivers/gpu/drm/mxsfb/mxsfb_kms.c
620
writel(0, mxsfb->base + LCDC_AS_CTRL);
drivers/gpu/drm/mxsfb/mxsfb_kms.c
97
writel(ctrl1, mxsfb->base + LCDC_CTRL1);
drivers/gpu/drm/mxsfb/mxsfb_kms.c
98
writel(ctrl, mxsfb->base + LCDC_CTRL);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a_devfreq.c
104
writel(data, gdevfreq->regs + PWR_PMU_IDLE_CTRL_REG_OFFSET +
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a_devfreq.c
108
writel(PWM_PMU_IDLE_MASK_GR_ENABLED | PWM_PMU_IDLE_MASK_CE_2_ENABLED,
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a_devfreq.c
116
writel(data, gdevfreq->regs + PWR_PMU_IDLE_CTRL_REG_OFFSET +
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a_devfreq.c
132
writel(PWR_PMU_IDLE_COUNT_RESET_VALUE, gdevfreq->regs + PWR_PMU_IDLE_COUNT_REG_OFFSET +
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a_devfreq.c
147
writel(PWR_PMU_IDLE_INTR_STATUS_RESET_VALUE,
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a_devfreq.c
92
writel(PWR_PMU_IDLE_INTR_ENABLE_VALUE,
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a_devfreq.c
95
writel(PWR_PMU_IDLE_THRESHOLD_MAX_VALUE,
drivers/gpu/drm/omapdrm/omap_dmm_tiler.c
132
writel(val, (__iomem void *)dmm->wa_dma_data);
drivers/gpu/drm/omapdrm/omap_dmm_tiler.c
147
writel(val, dmm->base + reg);
drivers/gpu/drm/omapdrm/omap_dmm_tiler.c
176
writel(val, dmm->base + reg);
drivers/gpu/drm/panfrost/panfrost_job.c
28
#define job_write(dev, reg, data) writel(data, dev->iomem + (reg))
drivers/gpu/drm/panfrost/panfrost_mmu.c
27
#define mmu_write(dev, reg, data) writel(data, dev->iomem + reg)
drivers/gpu/drm/panfrost/panfrost_regs.h
379
#define gpu_write(dev, reg, data) writel(data, dev->iomem + reg)
drivers/gpu/drm/panthor/panthor_device.h
479
writel(data, ptdev->iomem + reg);
drivers/gpu/drm/pl111/pl111_display.c
160
writel((ppl << 2) |
drivers/gpu/drm/pl111/pl111_display.c
165
writel(lpp |
drivers/gpu/drm/pl111/pl111_display.c
232
writel(tim2, priv->regs + CLCD_TIM2);
drivers/gpu/drm/pl111/pl111_display.c
235
writel(0, priv->regs + CLCD_TIM3);
drivers/gpu/drm/pl111/pl111_display.c
339
writel(cntl, priv->regs + priv->ctrl);
drivers/gpu/drm/pl111/pl111_display.c
352
writel(cntl, priv->regs + priv->ctrl);
drivers/gpu/drm/pl111/pl111_display.c
372
writel(cntl, priv->regs + priv->ctrl);
drivers/gpu/drm/pl111/pl111_display.c
385
writel(0, priv->regs + priv->ctrl);
drivers/gpu/drm/pl111/pl111_display.c
404
writel(addr, priv->regs + CLCD_UBAS);
drivers/gpu/drm/pl111/pl111_display.c
425
writel(CLCD_IRQ_NEXTBASE_UPDATE, priv->regs + priv->ienb);
drivers/gpu/drm/pl111/pl111_display.c
436
writel(0, priv->regs + priv->ienb);
drivers/gpu/drm/pl111/pl111_display.c
46
writel(irq_stat, priv->regs + CLCD_PL111_ICR);
drivers/gpu/drm/pl111/pl111_display.c
527
writel(tim2, priv->regs + CLCD_TIM2);
drivers/gpu/drm/pl111/pl111_drv.c
293
writel(0, priv->regs + priv->ienb);
drivers/gpu/drm/radeon/cik.c
1751
writel(v, rdev->doorbell.ptr + index);
drivers/gpu/drm/radeon/r100.c
4128
writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
drivers/gpu/drm/radeon/r100.c
4139
writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
drivers/gpu/drm/radeon/r100.c
4140
writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
drivers/gpu/drm/radeon/r300.c
127
writel(entry, ((void __iomem *)ptr) + (i * 4));
drivers/gpu/drm/radeon/radeon.h
2467
writel(v, ((void __iomem *)rdev->rmmio) + reg);
drivers/gpu/drm/radeon/radeon_uvd.c
783
writel((__force u32)cpu_to_le32(0x00000de4), &msg[0]);
drivers/gpu/drm/radeon/radeon_uvd.c
784
writel(0x0, (void __iomem *)&msg[1]);
drivers/gpu/drm/radeon/radeon_uvd.c
785
writel((__force u32)cpu_to_le32(handle), &msg[2]);
drivers/gpu/drm/radeon/radeon_uvd.c
786
writel(0x0, &msg[3]);
drivers/gpu/drm/radeon/radeon_uvd.c
787
writel(0x0, &msg[4]);
drivers/gpu/drm/radeon/radeon_uvd.c
788
writel(0x0, &msg[5]);
drivers/gpu/drm/radeon/radeon_uvd.c
789
writel(0x0, &msg[6]);
drivers/gpu/drm/radeon/radeon_uvd.c
790
writel((__force u32)cpu_to_le32(0x00000780), &msg[7]);
drivers/gpu/drm/radeon/radeon_uvd.c
791
writel((__force u32)cpu_to_le32(0x00000440), &msg[8]);
drivers/gpu/drm/radeon/radeon_uvd.c
792
writel(0x0, &msg[9]);
drivers/gpu/drm/radeon/radeon_uvd.c
793
writel((__force u32)cpu_to_le32(0x01b37000), &msg[10]);
drivers/gpu/drm/radeon/radeon_uvd.c
795
writel(0x0, &msg[i]);
drivers/gpu/drm/radeon/radeon_uvd.c
819
writel((__force u32)cpu_to_le32(0x00000de4), &msg[0]);
drivers/gpu/drm/radeon/radeon_uvd.c
820
writel((__force u32)cpu_to_le32(0x00000002), &msg[1]);
drivers/gpu/drm/radeon/radeon_uvd.c
821
writel((__force u32)cpu_to_le32(handle), &msg[2]);
drivers/gpu/drm/radeon/radeon_uvd.c
822
writel(0x0, &msg[3]);
drivers/gpu/drm/radeon/radeon_uvd.c
824
writel(0x0, &msg[i]);
drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c
100
writel(DU_MCR1_PB_AUTOCLR, rcdu->mmio + DU_MCR1);
drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c
221
writel(start ? DU_MCR0_DI_EN : 0, rcdu->mmio + DU_MCR0);
drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c
92
writel(ditr0, rcdu->mmio + DU_DITR0);
drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c
93
writel(ditr1, rcdu->mmio + DU_DITR1);
drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c
94
writel(ditr2, rcdu->mmio + DU_DITR2);
drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c
95
writel(ditr3, rcdu->mmio + DU_DITR3);
drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c
96
writel(ditr4, rcdu->mmio + DU_DITR4);
drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c
97
writel(pbcr0, rcdu->mmio + DU_PBCR0);
drivers/gpu/drm/rockchip/cdn-dp-reg.c
103
writel(val, dp->regs + MAILBOX0_WR_DATA);
drivers/gpu/drm/rockchip/cdn-dp-reg.c
28
writel(clk / 1000000, dp->regs + SW_CLK_H);
drivers/gpu/drm/rockchip/cdn-dp-reg.c
290
writel(APB_IRAM_PATH | APB_DRAM_PATH | APB_XT_RESET,
drivers/gpu/drm/rockchip/cdn-dp-reg.c
294
writel(*i_mem++, dp->regs + ADDR_IMEM + i);
drivers/gpu/drm/rockchip/cdn-dp-reg.c
297
writel(*d_mem++, dp->regs + ADDR_DMEM + i);
drivers/gpu/drm/rockchip/cdn-dp-reg.c
300
writel(0, dp->regs + APB_CTRL);
drivers/gpu/drm/rockchip/cdn-dp-reg.c
47
writel(val, dp->regs + SOURCE_DPTX_CAR);
drivers/gpu/drm/rockchip/cdn-dp-reg.c
50
writel(val, dp->regs + SOURCE_PHY_CAR);
drivers/gpu/drm/rockchip/cdn-dp-reg.c
56
writel(val, dp->regs + SOURCE_PKT_CAR);
drivers/gpu/drm/rockchip/cdn-dp-reg.c
64
writel(val, dp->regs + SOURCE_AIF_CAR);
drivers/gpu/drm/rockchip/cdn-dp-reg.c
70
writel(val, dp->regs + SOURCE_CIPHER_CAR);
drivers/gpu/drm/rockchip/cdn-dp-reg.c
74
writel(val, dp->regs + SOURCE_CRYPTO_CAR);
drivers/gpu/drm/rockchip/cdn-dp-reg.c
77
writel(0, dp->regs + APB_INT_MASK);
drivers/gpu/drm/rockchip/cdn-dp-reg.c
796
writel(0, dp->regs + SPDIF_CTRL_ADDR);
drivers/gpu/drm/rockchip/cdn-dp-reg.c
799
writel(0, dp->regs + AUDIO_SRC_CNTL);
drivers/gpu/drm/rockchip/cdn-dp-reg.c
800
writel(0, dp->regs + AUDIO_SRC_CNFG);
drivers/gpu/drm/rockchip/cdn-dp-reg.c
801
writel(AUDIO_SW_RST, dp->regs + AUDIO_SRC_CNTL);
drivers/gpu/drm/rockchip/cdn-dp-reg.c
802
writel(0, dp->regs + AUDIO_SRC_CNTL);
drivers/gpu/drm/rockchip/cdn-dp-reg.c
805
writel(0, dp->regs + SMPL2PKT_CNTL);
drivers/gpu/drm/rockchip/cdn-dp-reg.c
806
writel(AUDIO_SW_RST, dp->regs + SMPL2PKT_CNTL);
drivers/gpu/drm/rockchip/cdn-dp-reg.c
807
writel(0, dp->regs + SMPL2PKT_CNTL);
drivers/gpu/drm/rockchip/cdn-dp-reg.c
810
writel(AUDIO_SW_RST, dp->regs + FIFO_CNTL);
drivers/gpu/drm/rockchip/cdn-dp-reg.c
811
writel(0, dp->regs + FIFO_CNTL);
drivers/gpu/drm/rockchip/cdn-dp-reg.c
847
writel(0x0, dp->regs + SPDIF_CTRL_ADDR);
drivers/gpu/drm/rockchip/cdn-dp-reg.c
849
writel(SYNC_WR_TO_CH_ZERO, dp->regs + FIFO_CNTL);
drivers/gpu/drm/rockchip/cdn-dp-reg.c
855
writel(val, dp->regs + SMPL2PKT_CNFG);
drivers/gpu/drm/rockchip/cdn-dp-reg.c
867
writel(val, dp->regs + AUDIO_SRC_CNFG);
drivers/gpu/drm/rockchip/cdn-dp-reg.c
876
writel(val, dp->regs + STTS_BIT_CH(i));
drivers/gpu/drm/rockchip/cdn-dp-reg.c
910
writel(val, dp->regs + COM_CH_STTS_BITS);
drivers/gpu/drm/rockchip/cdn-dp-reg.c
912
writel(SMPL2PKT_EN, dp->regs + SMPL2PKT_CNTL);
drivers/gpu/drm/rockchip/cdn-dp-reg.c
913
writel(I2S_DEC_START, dp->regs + AUDIO_SRC_CNTL);
drivers/gpu/drm/rockchip/cdn-dp-reg.c
920
writel(SYNC_WR_TO_CH_ZERO, dp->regs + FIFO_CNTL);
drivers/gpu/drm/rockchip/cdn-dp-reg.c
923
writel(val, dp->regs + SMPL2PKT_CNFG);
drivers/gpu/drm/rockchip/cdn-dp-reg.c
924
writel(SMPL2PKT_EN, dp->regs + SMPL2PKT_CNTL);
drivers/gpu/drm/rockchip/cdn-dp-reg.c
927
writel(val, dp->regs + SPDIF_CTRL_ADDR);
drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
380
writel(val, dsi->base + reg);
drivers/gpu/drm/rockchip/rockchip_drm_vop.c
1273
writel(word, vop->lut_regs + i * 4);
drivers/gpu/drm/rockchip/rockchip_drm_vop.c
229
writel(v, vop->regs + offset);
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
1463
writel(word, vop2->lut_regs + i * 4);
drivers/gpu/drm/sprd/sprd_dpu.c
409
writel(0x00, ctx->base + REG_BG_COLOR);
drivers/gpu/drm/sprd/sprd_dpu.c
410
writel(0x00, ctx->base + REG_MMU_EN);
drivers/gpu/drm/sprd/sprd_dpu.c
411
writel(0x00, ctx->base + REG_MMU_PPN1);
drivers/gpu/drm/sprd/sprd_dpu.c
412
writel(0xffff, ctx->base + REG_MMU_RANGE1);
drivers/gpu/drm/sprd/sprd_dpu.c
413
writel(0x00, ctx->base + REG_MMU_PPN2);
drivers/gpu/drm/sprd/sprd_dpu.c
414
writel(0xffff, ctx->base + REG_MMU_RANGE2);
drivers/gpu/drm/sprd/sprd_dpu.c
415
writel(0x1ffff, ctx->base + REG_MMU_VPN_RANGE);
drivers/gpu/drm/sprd/sprd_dpu.c
449
writel(int_mask, ctx->base + REG_DPU_INT_EN);
drivers/gpu/drm/sprd/sprd_dpu.c
456
writel(0x00, ctx->base + REG_DPU_INT_EN);
drivers/gpu/drm/sprd/sprd_dpu.c
457
writel(0xff, ctx->base + REG_DPU_INT_CLR);
drivers/gpu/drm/sprd/sprd_dpu.c
467
writel(size, ctx->base + REG_PANEL_SIZE);
drivers/gpu/drm/sprd/sprd_dpu.c
468
writel(size, ctx->base + REG_BLEND_SIZE);
drivers/gpu/drm/sprd/sprd_dpu.c
475
writel(reg_val, ctx->base + REG_DPI_H_TIMING);
drivers/gpu/drm/sprd/sprd_dpu.c
480
writel(reg_val, ctx->base + REG_DPI_V_TIMING);
drivers/gpu/drm/sprd/sprd_dpu.c
776
writel(reg_val, ctx->base + REG_DPU_INT_CLR);
drivers/gpu/drm/sprd/sprd_dpu.c
800
writel(0x00, ctx->base + REG_DPU_INT_EN);
drivers/gpu/drm/sprd/sprd_dpu.c
801
writel(0xff, ctx->base + REG_DPU_INT_CLR);
drivers/gpu/drm/sprd/sprd_dpu.h
103
writel(cfg_bits, ctx->base + layer_offset);
drivers/gpu/drm/sprd/sprd_dpu.h
79
writel(bits | set_bits, ctx->base + offset);
drivers/gpu/drm/sprd/sprd_dpu.h
87
writel(bits & ~clr_bits, ctx->base + offset);
drivers/gpu/drm/sprd/sprd_dsi.c
151
writel(ret, ctx->base + offset);
drivers/gpu/drm/sprd/sprd_dsi.c
160
writel((ret & ~mask) | (val & mask), ctx->base + offset);
drivers/gpu/drm/sprd/sprd_dsi.c
397
writel(0, ctx->base + SOFT_RESET);
drivers/gpu/drm/sprd/sprd_dsi.c
398
writel(0xffffffff, ctx->base + MASK_PROTOCOL_INT);
drivers/gpu/drm/sprd/sprd_dsi.c
399
writel(0xffffffff, ctx->base + MASK_INTERNAL_INT);
drivers/gpu/drm/sprd/sprd_dsi.c
400
writel(1, ctx->base + DSI_MODE_CFG);
drivers/gpu/drm/sprd/sprd_dsi.c
405
writel(1, ctx->base + TA_EN);
drivers/gpu/drm/sprd/sprd_dsi.c
410
writel(div, ctx->base + TX_ESC_CLK_CONFIG);
drivers/gpu/drm/sprd/sprd_dsi.c
413
writel(max_rd_time, ctx->base + MAX_READ_TIME);
drivers/gpu/drm/sprd/sprd_dsi.c
428
writel(1, ctx->base + SOFT_RESET);
drivers/gpu/drm/sprd/sprd_dsi.c
436
writel(0xffffffff, ctx->base + MASK_PROTOCOL_INT);
drivers/gpu/drm/sprd/sprd_dsi.c
437
writel(0xffffffff, ctx->base + MASK_INTERNAL_INT);
drivers/gpu/drm/sprd/sprd_dsi.c
438
writel(0, ctx->base + SOFT_RESET);
drivers/gpu/drm/sprd/sprd_dsi.c
477
writel(0, ctx->base + SOFT_RESET);
drivers/gpu/drm/sprd/sprd_dsi.c
484
writel(byte_cycle, ctx->base + VIDEO_LINE_TIME);
drivers/gpu/drm/sprd/sprd_dsi.c
489
writel(vm->vactive, ctx->base + VIDEO_VACTIVE_LINES);
drivers/gpu/drm/sprd/sprd_dsi.c
500
writel(div, ctx->base + TIMEOUT_CNT_CLK_CONFIG);
drivers/gpu/drm/sprd/sprd_dsi.c
501
writel(hs_to / div, ctx->base + LRX_H_TO_CONFIG);
drivers/gpu/drm/sprd/sprd_dsi.c
502
writel(hs_to / div, ctx->base + HTX_TO_CONFIG);
drivers/gpu/drm/sprd/sprd_dsi.c
509
writel(0, ctx->base + VIDEO_NULLPKT_SIZE);
drivers/gpu/drm/sprd/sprd_dsi.c
570
writel(null_pkt_size, ctx->base + VIDEO_NULLPKT_SIZE);
drivers/gpu/drm/sprd/sprd_dsi.c
574
writel(ctx->int0_mask, ctx->base + MASK_PROTOCOL_INT);
drivers/gpu/drm/sprd/sprd_dsi.c
575
writel(ctx->int1_mask, ctx->base + MASK_INTERNAL_INT);
drivers/gpu/drm/sprd/sprd_dsi.c
576
writel(1, ctx->base + SOFT_RESET);
drivers/gpu/drm/sprd/sprd_dsi.c
595
writel(0, ctx->base + SOFT_RESET);
drivers/gpu/drm/sprd/sprd_dsi.c
600
writel(hactive, ctx->base + DCS_WM_PKT_SIZE);
drivers/gpu/drm/sprd/sprd_dsi.c
602
writel(max_fifo_len, ctx->base + DCS_WM_PKT_SIZE);
drivers/gpu/drm/sprd/sprd_dsi.c
604
writel(ctx->int0_mask, ctx->base + MASK_PROTOCOL_INT);
drivers/gpu/drm/sprd/sprd_dsi.c
605
writel(ctx->int1_mask, ctx->base + MASK_INTERNAL_INT);
drivers/gpu/drm/sprd/sprd_dsi.c
606
writel(1, ctx->base + SOFT_RESET);
drivers/gpu/drm/sprd/sprd_dsi.c
643
writel(payload, ctx->base + GEN_PLD_DATA);
drivers/gpu/drm/sprd/sprd_dsi.c
659
writel(type | (vc << 6) | (wc_lsbyte << 8) | (wc_msbyte << 16),
drivers/gpu/drm/sprd/sprd_dsi.c
691
writel(type | (vc << 6) | (lsb_byte << 8) | (msb_byte << 16),
drivers/gpu/drm/sprd/sprd_dsi.c
731
writel(1, ctx->base + DSI_MODE_CFG);
drivers/gpu/drm/sprd/sprd_dsi.c
733
writel(0, ctx->base + DSI_MODE_CFG);
drivers/gpu/drm/sprd/sprd_dsi.c
738
writel(0, ctx->base + SOFT_RESET);
drivers/gpu/drm/sprd/sprd_dsi.c
740
writel(1, ctx->base + SOFT_RESET);
drivers/gpu/drm/sprd/sprd_dsi.c
761
writel(0x1C, ctx->base + PHY_MIN_STOP_TIME);
drivers/gpu/drm/sprd/sprd_dsi.c
763
writel(dsi->slave->lanes - 1, ctx->base + PHY_LANE_NUM_CONFIG);
drivers/gpu/drm/sti/sti_cursor.c
294
writel(val, cursor->regs + CUR_AWS);
drivers/gpu/drm/sti/sti_cursor.c
298
writel(val, cursor->regs + CUR_AWE);
drivers/gpu/drm/sti/sti_cursor.c
301
writel(cursor->pixmap.paddr, cursor->regs + CUR_PML);
drivers/gpu/drm/sti/sti_cursor.c
302
writel(cursor->width, cursor->regs + CUR_PMP);
drivers/gpu/drm/sti/sti_cursor.c
303
writel(cursor->height << 16 | cursor->width, cursor->regs + CUR_SIZE);
drivers/gpu/drm/sti/sti_cursor.c
307
writel((y << 16) | x, cursor->regs + CUR_VPO);
drivers/gpu/drm/sti/sti_cursor.c
310
writel(cursor->clut_paddr, cursor->regs + CUR_CML);
drivers/gpu/drm/sti/sti_cursor.c
311
writel(CUR_CTL_CLUT_UPDATE, cursor->regs + CUR_CTL);
drivers/gpu/drm/sti/sti_dvo.c
156
writel(awg_ram_code[i],
drivers/gpu/drm/sti/sti_dvo.c
159
writel(0, dvo->regs + DVO_DIGSYNC_INSTR_I + i * 4);
drivers/gpu/drm/sti/sti_dvo.c
161
writel(DVO_AWG_CTRL_EN, dvo->regs + DVO_AWG_DIGSYNC_CTRL);
drivers/gpu/drm/sti/sti_dvo.c
222
writel(0x00000000, dvo->regs + DVO_AWG_DIGSYNC_CTRL);
drivers/gpu/drm/sti/sti_dvo.c
224
writel(0x00000000, dvo->regs + DVO_DOF_CFG);
drivers/gpu/drm/sti/sti_dvo.c
247
writel(0x00000000, dvo->regs + DVO_DOF_CFG);
drivers/gpu/drm/sti/sti_dvo.c
248
writel(0x00000000, dvo->regs + DVO_AWG_DIGSYNC_CTRL);
drivers/gpu/drm/sti/sti_dvo.c
269
writel(config->lowbyte, dvo->regs + DVO_LUT_PROG_LOW);
drivers/gpu/drm/sti/sti_dvo.c
270
writel(config->midbyte, dvo->regs + DVO_LUT_PROG_MID);
drivers/gpu/drm/sti/sti_dvo.c
271
writel(config->highbyte, dvo->regs + DVO_LUT_PROG_HIGH);
drivers/gpu/drm/sti/sti_dvo.c
275
writel(val, dvo->regs + DVO_DOF_CFG);
drivers/gpu/drm/sti/sti_gdp.c
847
writel(gdp->is_curr_top ?
drivers/gpu/drm/sti/sti_gdp.c
861
writel(dma_updated_top,
drivers/gpu/drm/sti/sti_gdp.c
866
writel(dma_updated_top, gdp->regs + GAM_GDP_NVN_OFFSET);
drivers/gpu/drm/sti/sti_hda.c
278
writel(val, hda->regs + offset);
drivers/gpu/drm/sti/sti_hda.c
318
writel(val, hda->video_dacs_ctrl);
drivers/gpu/drm/sti/sti_hdmi.c
189
writel(val, hdmi->regs + offset);
drivers/gpu/drm/sti/sti_hdmi.c
410
writel(val, hdmi->regs + head_offset);
drivers/gpu/drm/sti/sti_hdmi.c
424
writel(val, hdmi->regs + pack_offset + i);
drivers/gpu/drm/sti/sti_hqvdp.c
1012
writel(SOFT_VSYNC_HW, hqvdp->regs + HQVDP_MBX_SOFT_VSYNC);
drivers/gpu/drm/sti/sti_hqvdp.c
1236
writel(hqvdp->hqvdp_cmd_paddr + cmd_offset,
drivers/gpu/drm/sti/sti_hqvdp.c
768
writel(0, hqvdp->regs + HQVDP_MBX_NEXT_CMD);
drivers/gpu/drm/sti/sti_hqvdp.c
838
writel(hqvdp->hqvdp_cmd_paddr + btm_cmd_offset,
drivers/gpu/drm/sti/sti_hqvdp.c
876
writel(PLUG_PAGE_SIZE_256, hqvdp->regs + HQVDP_RD_PLUG_PAGE_SIZE);
drivers/gpu/drm/sti/sti_hqvdp.c
877
writel(PLUG_MIN_OPC_8, hqvdp->regs + HQVDP_RD_PLUG_MIN_OPC);
drivers/gpu/drm/sti/sti_hqvdp.c
878
writel(PLUG_MAX_OPC_64, hqvdp->regs + HQVDP_RD_PLUG_MAX_OPC);
drivers/gpu/drm/sti/sti_hqvdp.c
879
writel(PLUG_MAX_CHK_2X, hqvdp->regs + HQVDP_RD_PLUG_MAX_CHK);
drivers/gpu/drm/sti/sti_hqvdp.c
880
writel(PLUG_MAX_MSG_1X, hqvdp->regs + HQVDP_RD_PLUG_MAX_MSG);
drivers/gpu/drm/sti/sti_hqvdp.c
881
writel(PLUG_MIN_SPACE_1, hqvdp->regs + HQVDP_RD_PLUG_MIN_SPACE);
drivers/gpu/drm/sti/sti_hqvdp.c
882
writel(PLUG_CONTROL_ENABLE, hqvdp->regs + HQVDP_RD_PLUG_CONTROL);
drivers/gpu/drm/sti/sti_hqvdp.c
884
writel(PLUG_PAGE_SIZE_256, hqvdp->regs + HQVDP_WR_PLUG_PAGE_SIZE);
drivers/gpu/drm/sti/sti_hqvdp.c
885
writel(PLUG_MIN_OPC_8, hqvdp->regs + HQVDP_WR_PLUG_MIN_OPC);
drivers/gpu/drm/sti/sti_hqvdp.c
886
writel(PLUG_MAX_OPC_64, hqvdp->regs + HQVDP_WR_PLUG_MAX_OPC);
drivers/gpu/drm/sti/sti_hqvdp.c
887
writel(PLUG_MAX_CHK_2X, hqvdp->regs + HQVDP_WR_PLUG_MAX_CHK);
drivers/gpu/drm/sti/sti_hqvdp.c
888
writel(PLUG_MAX_MSG_1X, hqvdp->regs + HQVDP_WR_PLUG_MAX_MSG);
drivers/gpu/drm/sti/sti_hqvdp.c
889
writel(PLUG_MIN_SPACE_1, hqvdp->regs + HQVDP_WR_PLUG_MIN_SPACE);
drivers/gpu/drm/sti/sti_hqvdp.c
890
writel(PLUG_CONTROL_ENABLE, hqvdp->regs + HQVDP_WR_PLUG_CONTROL);
drivers/gpu/drm/sti/sti_hqvdp.c
960
writel(SW_RESET_CTRL_FULL, hqvdp->regs + HQVDP_MBX_SW_RESET_CTRL);
drivers/gpu/drm/sti/sti_hqvdp.c
976
writel(fw_rd_plug[i], hqvdp->regs + HQVDP_RD_PLUG + i * 4);
drivers/gpu/drm/sti/sti_hqvdp.c
978
writel(fw_wr_plug[i], hqvdp->regs + HQVDP_WR_PLUG + i * 4);
drivers/gpu/drm/sti/sti_hqvdp.c
983
writel(STARTUP_CTRL1_AUTH_IDLE, hqvdp->regs + HQVDP_MBX_STARTUP_CTRL1);
drivers/gpu/drm/sti/sti_hqvdp.c
986
writel(SOFT_VSYNC_SW_CTRL_IRQ, hqvdp->regs + HQVDP_MBX_SOFT_VSYNC);
drivers/gpu/drm/sti/sti_hqvdp.c
987
writel(0, hqvdp->regs + HQVDP_MBX_NEXT_CMD);
drivers/gpu/drm/sti/sti_hqvdp.c
991
writel(fw_pmem[i], hqvdp->regs + HQVDP_PMEM + i * 4);
drivers/gpu/drm/sti/sti_hqvdp.c
993
writel(fw_dmem[i], hqvdp->regs + HQVDP_DMEM + i * 4);
drivers/gpu/drm/sti/sti_hqvdp.c
996
writel(STARTUP_CTRL2_FETCH_EN, hqvdp->regs + HQVDP_MBX_STARTUP_CTRL2);
drivers/gpu/drm/sti/sti_mixer.c
74
writel(val, mixer->regs + reg_id);
drivers/gpu/drm/sti/sti_tvout.c
152
writel(val, tvout->regs + offset);
drivers/gpu/drm/sti/sti_vid.c
159
writel(val, vid->regs + VID_CTL);
drivers/gpu/drm/sti/sti_vid.c
166
writel((ydo << 16) | xdo, vid->regs + VID_VPO);
drivers/gpu/drm/sti/sti_vid.c
167
writel((yds << 16) | xds, vid->regs + VID_VPS);
drivers/gpu/drm/sti/sti_vid.c
171
writel(VID_MPR0_BT709, vid->regs + VID_MPR0);
drivers/gpu/drm/sti/sti_vid.c
172
writel(VID_MPR1_BT709, vid->regs + VID_MPR1);
drivers/gpu/drm/sti/sti_vid.c
173
writel(VID_MPR2_BT709, vid->regs + VID_MPR2);
drivers/gpu/drm/sti/sti_vid.c
174
writel(VID_MPR3_BT709, vid->regs + VID_MPR3);
drivers/gpu/drm/sti/sti_vid.c
176
writel(VID_MPR0_BT601, vid->regs + VID_MPR0);
drivers/gpu/drm/sti/sti_vid.c
177
writel(VID_MPR1_BT601, vid->regs + VID_MPR1);
drivers/gpu/drm/sti/sti_vid.c
178
writel(VID_MPR2_BT601, vid->regs + VID_MPR2);
drivers/gpu/drm/sti/sti_vid.c
179
writel(VID_MPR3_BT601, vid->regs + VID_MPR3);
drivers/gpu/drm/sti/sti_vid.c
190
writel(val, vid->regs + VID_CTL);
drivers/gpu/drm/sti/sti_vid.c
196
writel(VID_CTL_PSI_ENABLE | VID_CTL_IGNORE, vid->regs + VID_CTL);
drivers/gpu/drm/sti/sti_vid.c
199
writel(VID_ALP_OPAQUE, vid->regs + VID_ALP);
drivers/gpu/drm/sti/sti_vid.c
202
writel(VID_BC_DFLT, vid->regs + VID_BC);
drivers/gpu/drm/sti/sti_vid.c
203
writel(VID_TINT_DFLT, vid->regs + VID_TINT);
drivers/gpu/drm/sti/sti_vid.c
204
writel(VID_CSAT_DFLT, vid->regs + VID_CSAT);
drivers/gpu/drm/sti/sti_vtg.c
161
writel(1, vtg->regs + VTG_DRST_AUTOC);
drivers/gpu/drm/sti/sti_vtg.c
184
writel(video_top_field_start, regs + VTG_VID_TFO);
drivers/gpu/drm/sti/sti_vtg.c
185
writel(video_top_field_stop, regs + VTG_VID_TFS);
drivers/gpu/drm/sti/sti_vtg.c
186
writel(video_bottom_field_start, regs + VTG_VID_BFO);
drivers/gpu/drm/sti/sti_vtg.c
187
writel(video_bottom_field_stop, regs + VTG_VID_BFS);
drivers/gpu/drm/sti/sti_vtg.c
251
writel(mode->htotal, vtg->regs + VTG_CLKLN);
drivers/gpu/drm/sti/sti_vtg.c
254
writel(mode->vtotal * 2, vtg->regs + VTG_HLFLN);
drivers/gpu/drm/sti/sti_vtg.c
273
writel(sync[i].hsync,
drivers/gpu/drm/sti/sti_vtg.c
275
writel(sync[i].vsync_line_top,
drivers/gpu/drm/sti/sti_vtg.c
277
writel(sync[i].vsync_line_bot,
drivers/gpu/drm/sti/sti_vtg.c
279
writel(sync[i].vsync_off_top,
drivers/gpu/drm/sti/sti_vtg.c
281
writel(sync[i].vsync_off_bot,
drivers/gpu/drm/sti/sti_vtg.c
286
writel(type, vtg->regs + VTG_MODE);
drivers/gpu/drm/sti/sti_vtg.c
292
writel(0xFFFF, vtg->regs + VTG_HOST_ITS_BCLR);
drivers/gpu/drm/sti/sti_vtg.c
293
writel(0xFFFF, vtg->regs + VTG_HOST_ITM_BCLR);
drivers/gpu/drm/sti/sti_vtg.c
294
writel(VTG_IRQ_MASK, vtg->regs + VTG_HOST_ITM_BSET);
drivers/gpu/drm/sti/sti_vtg.c
376
writel(vtg->irq_status, vtg->regs + VTG_HOST_ITS_BCLR);
drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
96
writel(val, dsi->base + reg);
drivers/gpu/drm/stm/lvds.c
291
writel(val, lvds->base + reg);
drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c
112
writel(SUN4I_HDMI_UNKNOWN_INPUT_SYNC,
drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c
128
writel(val, hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG);
drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c
132
writel(SUN4I_HDMI_VID_TIMING_X(mode->hdisplay) |
drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c
138
writel(SUN4I_HDMI_VID_TIMING_X(x) | SUN4I_HDMI_VID_TIMING_Y(y),
drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c
143
writel(SUN4I_HDMI_VID_TIMING_X(x) | SUN4I_HDMI_VID_TIMING_Y(y),
drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c
148
writel(SUN4I_HDMI_VID_TIMING_X(x) | SUN4I_HDMI_VID_TIMING_Y(y),
drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c
158
writel(val, hdmi->base + SUN4I_HDMI_VID_TIMING_POL_REG);
drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c
166
writel(val, hdmi->base + SUN4I_HDMI_PKT_CTRL_REG(0));
drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c
172
writel(val, hdmi->base + SUN4I_HDMI_VID_CTRL_REG);
drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c
312
writel(SUN4I_HDMI_CEC_ENABLE, hdmi->base + SUN4I_HDMI_CEC);
drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c
323
writel(0, hdmi->base + SUN4I_HDMI_CEC);
drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c
600
writel(SUN4I_HDMI_CTRL_ENABLE, hdmi->base + SUN4I_HDMI_CTRL_REG);
drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c
602
writel(hdmi->variant->pad_ctrl0_init_val,
drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c
608
writel(reg, hdmi->base + SUN4I_HDMI_PLL_CTRL_REG);
drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c
647
writel(readl(hdmi->base + SUN4I_HDMI_CEC) & ~SUN4I_HDMI_CEC_TX,
drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c
88
writel(val, hdmi->base + SUN4I_HDMI_VID_CTRL_REG);
drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c
82
writel(reg, hdmi->base + SUN4I_HDMI_DDC_CTRL_REG);
drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c
158
writel(reg, tmds->hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG);
drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c
162
writel(reg | SUN4I_HDMI_PLL_CTRL_DIV(div - tmds->div_offset),
drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c
188
writel(reg | SUN4I_HDMI_PLL_DBG0_TMDS_PARENT(index),
drivers/gpu/drm/sun4i/sun8i_tcon_top.c
182
writel(0, regs + TCON_TOP_PORT_SEL_REG);
drivers/gpu/drm/sun4i/sun8i_tcon_top.c
183
writel(0, regs + TCON_TOP_GATE_SRC_REG);
drivers/gpu/drm/sun4i/sun8i_tcon_top.c
49
writel(val, tcon_top->regs + TCON_TOP_GATE_SRC_REG);
drivers/gpu/drm/sun4i/sun8i_tcon_top.c
88
writel(reg, tcon_top->regs + TCON_TOP_PORT_SEL_REG);
drivers/gpu/drm/sysfb/ofdrm.c
500
writel(color, data);
drivers/gpu/drm/sysfb/ofdrm.c
522
writel(val, dac_ctl);
drivers/gpu/drm/sysfb/ofdrm.c
526
writel(color, data);
drivers/gpu/drm/sysfb/ofdrm.c
548
writel(val, dac_ctl);
drivers/gpu/drm/sysfb/ofdrm.c
552
writel(color, data);
drivers/gpu/drm/sysfb/ofdrm.c
575
writel(color, data);
drivers/gpu/drm/sysfb/ofdrm.c
602
writel(1, lutsel);
drivers/gpu/drm/sysfb/ofdrm.c
604
writel(color, data);
drivers/gpu/drm/sysfb/ofdrm.c
606
writel(0, lutsel);
drivers/gpu/drm/sysfb/ofdrm.c
608
writel(color, data);
drivers/gpu/drm/tegra/dc.h
123
writel(value, dc->regs + (offset << 2));
drivers/gpu/drm/tegra/dpaux.c
90
writel(value, dpaux->regs + (offset << 2));
drivers/gpu/drm/tegra/dsi.c
121
writel(value, dsi->regs + (offset << 2));
drivers/gpu/drm/tegra/falcon.c
22
writel(value, falcon->regs + offset);
drivers/gpu/drm/tegra/hdmi.c
129
writel(value, hdmi->regs + (offset << 2));
drivers/gpu/drm/tegra/nvdec.c
63
writel(value, nvdec->regs + offset);
drivers/gpu/drm/tegra/riscv.c
34
writel(value, riscv->regs + offset);
drivers/gpu/drm/tegra/sor.c
500
writel(value, sor->regs + (offset << 2));
drivers/gpu/drm/tegra/vic.c
52
writel(value, vic->regs + offset);
drivers/gpu/drm/tiny/bochs.c
179
writel(0xbebebebe, bochs->mmio + 0x604);
drivers/gpu/drm/tiny/bochs.c
187
writel(0x1e1e1e1e, bochs->mmio + 0x604);
drivers/gpu/drm/tve200/tve200_display.c
140
writel(TVE200_CTRL_4_RESET, priv->regs + TVE200_CTRL_4);
drivers/gpu/drm/tve200/tve200_display.c
238
writel(ctrl1, priv->regs + TVE200_CTRL);
drivers/gpu/drm/tve200/tve200_display.c
252
writel(0, priv->regs + TVE200_CTRL);
drivers/gpu/drm/tve200/tve200_display.c
253
writel(TVE200_CTRL_4_RESET, priv->regs + TVE200_CTRL_4);
drivers/gpu/drm/tve200/tve200_display.c
271
writel(drm_fb_dma_get_gem_addr(fb, pstate, 0),
drivers/gpu/drm/tve200/tve200_display.c
276
writel(drm_fb_dma_get_gem_addr(fb, pstate, 1),
drivers/gpu/drm/tve200/tve200_display.c
278
writel(drm_fb_dma_get_gem_addr(fb, pstate, 2),
drivers/gpu/drm/tve200/tve200_display.c
302
writel(0xFF, priv->regs + TVE200_INT_CLR);
drivers/gpu/drm/tve200/tve200_display.c
303
writel(TVE200_INT_V_STATUS, priv->regs + TVE200_INT_EN);
drivers/gpu/drm/tve200/tve200_display.c
313
writel(0, priv->regs + TVE200_INT_EN);
drivers/gpu/drm/tve200/tve200_display.c
62
writel(val, priv->regs + TVE200_CTRL);
drivers/gpu/drm/tve200/tve200_display.c
67
writel(stat, priv->regs + TVE200_INT_CLR);
drivers/gpu/drm/tve200/tve200_drv.c
210
writel(0, priv->regs + TVE200_INT_EN);
drivers/gpu/drm/v3d/v3d_drv.h
274
#define V3D_WRITE(offset, val) writel(val, v3d->hub_regs + offset)
drivers/gpu/drm/v3d/v3d_drv.h
277
#define V3D_BRIDGE_WRITE(offset, val) writel(val, v3d->bridge_regs + offset)
drivers/gpu/drm/v3d/v3d_drv.h
280
#define V3D_GCA_WRITE(offset, val) writel(val, v3d->gca_regs + offset)
drivers/gpu/drm/v3d/v3d_drv.h
289
#define V3D_SMS_WRITE(offset, val) writel(val, v3d->sms_regs + (offset))
drivers/gpu/drm/v3d/v3d_drv.h
292
#define V3D_CORE_WRITE(core, offset, val) writel(val, v3d->core_regs[core] + offset)
drivers/gpu/drm/vc4/vc4_crtc.c
57
writel(val, vc4_crtc->regs + (offset)); \
drivers/gpu/drm/vc4/vc4_dpi.c
113
writel(val, dpi->regs + (offset)); \
drivers/gpu/drm/vc4/vc4_drv.h
648
writel(val, vc4->v3d->regs + (offset)); \
drivers/gpu/drm/vc4/vc4_drv.h
660
writel(val, hvs->regs + (offset)); \
drivers/gpu/drm/vc4/vc4_dsi.c
625
writel(val, dsi->regs + offset);
drivers/gpu/drm/vc4/vc4_hdmi.c
694
writel(buffer[i + 0] << 0 |
drivers/gpu/drm/vc4/vc4_hdmi.c
700
writel(buffer[i + 3] << 0 |
drivers/gpu/drm/vc4/vc4_hdmi.c
713
writel(0, base + packet_reg);
drivers/gpu/drm/vc4/vc4_hdmi_regs.h
724
writel(value, base + field->offset);
drivers/gpu/drm/vc4/vc4_hvs.c
410
writel(kernel[i], &dst_kernel[i]);
drivers/gpu/drm/vc4/vc4_hvs.c
412
writel(kernel[VC4_KERNEL_DWORDS - i - 1],
drivers/gpu/drm/vc4/vc4_hvs.c
992
writel(SCALER_CTL0_END, dlist_next);
drivers/gpu/drm/vc4/vc4_plane.c
2196
writel(vc4_state->dlist[i], &dlist[i]);
drivers/gpu/drm/vc4/vc4_plane.c
2238
writel(value, &vc4_state->hw_dlist[vc4_state->ptr0_offset[0]]);
drivers/gpu/drm/vc4/vc4_plane.c
2242
writel(value, &vc4_state->hw_dlist[vc4_state->ptr0_offset[0] + 1]);
drivers/gpu/drm/vc4/vc4_plane.c
2253
writel(addr, &vc4_state->hw_dlist[vc4_state->ptr0_offset[0]]);
drivers/gpu/drm/vc4/vc4_plane.c
2329
writel(vc4_state->dlist[vc4_state->pos0_offset],
drivers/gpu/drm/vc4/vc4_plane.c
2331
writel(vc4_state->dlist[vc4_state->pos2_offset],
drivers/gpu/drm/vc4/vc4_plane.c
2333
writel(vc4_state->dlist[vc4_state->ptr0_offset[0]],
drivers/gpu/drm/vc4/vc4_txp.c
161
writel(val, txp->regs + (offset)); \
drivers/gpu/drm/vc4/vc4_vec.c
220
writel(val, vec->regs + (offset)); \
drivers/gpu/drm/xe/xe_map.h
64
writel(val, map->vaddr_iomem);
drivers/gpu/drm/xe/xe_mmio.c
141
writel(0, mmio->regs + DUMMY_REG_OFFSET);
drivers/gpu/drm/xe/xe_mmio.c
180
writel(val, mmio->regs + addr);
drivers/gpu/drm/xlnx/zynqmp_disp.c
410
writel(val, disp->avbuf + reg);
drivers/gpu/drm/xlnx/zynqmp_disp.c
646
writel(val, disp->blend + reg);
drivers/gpu/drm/xlnx/zynqmp_dp.c
418
writel(val, dp->iomem + offset);
drivers/gpu/drm/xlnx/zynqmp_dp_audio.c
97
writel(val, audio->base + reg);
drivers/gpu/host1x/dev.c
47
writel(v, host1x->common_regs + r);
drivers/gpu/host1x/dev.c
52
writel(v, host1x->hv_regs + r);
drivers/gpu/host1x/dev.c
64
writel(v, sync_regs + r);
drivers/gpu/host1x/dev.c
85
writel(v, ch->regs + r);
drivers/gpu/host1x/mipi.c
145
writel(value, mipi->regs + (offset << 2));
drivers/gpu/ipu-v3/ipu-common.c
36
writel(value, ipu->cm_reg + offset);
drivers/gpu/ipu-v3/ipu-cpmem.c
116
writel(val, &base->word[word].data[i]);
drivers/gpu/ipu-v3/ipu-cpmem.c
122
writel(val, &base->word[word].data[i + 1]);
drivers/gpu/ipu-v3/ipu-cpmem.c
235
writel(0, base + i * sizeof(u32));
drivers/gpu/ipu-v3/ipu-csi.c
185
writel(value, csi->base + offset);
drivers/gpu/ipu-v3/ipu-dc.c
116
writel(reg, dc->base + DC_RL_CH(event));
drivers/gpu/ipu-v3/ipu-dc.c
135
writel(reg1, priv->dc_tmpl_reg + word * 8);
drivers/gpu/ipu-v3/ipu-dc.c
136
writel(reg2, priv->dc_tmpl_reg + word * 8 + 4);
drivers/gpu/ipu-v3/ipu-dc.c
222
writel(reg, dc->base + DC_WR_CH_CONF);
drivers/gpu/ipu-v3/ipu-dc.c
224
writel(0x0, dc->base + DC_WR_CH_ADDR);
drivers/gpu/ipu-v3/ipu-dc.c
225
writel(width, priv->dc_reg + DC_DISP_CONF2(dc->di));
drivers/gpu/ipu-v3/ipu-dc.c
252
writel(reg, dc->base + DC_WR_CH_CONF);
drivers/gpu/ipu-v3/ipu-dc.c
262
writel(val, dc->base + DC_WR_CH_CONF);
drivers/gpu/ipu-v3/ipu-dc.c
292
writel(reg, priv->dc_reg + DC_MAP_CONF_VAL(ptr));
drivers/gpu/ipu-v3/ipu-dc.c
297
writel(reg, priv->dc_reg + DC_MAP_CONF_PTR(map));
drivers/gpu/ipu-v3/ipu-dc.c
304
writel(reg & ~(0xffff << (16 * (map & 0x1))),
drivers/gpu/ipu-v3/ipu-dc.c
371
writel(DC_WR_CH_CONF_WORD_SIZE_24 | DC_WR_CH_CONF_DISP_ID_PARALLEL(1) |
drivers/gpu/ipu-v3/ipu-dc.c
374
writel(DC_WR_CH_CONF_WORD_SIZE_24 | DC_WR_CH_CONF_DISP_ID_PARALLEL(0),
drivers/gpu/ipu-v3/ipu-dc.c
377
writel(DC_GEN_SYNC_1_6_SYNC | DC_GEN_SYNC_PRIORITY_1,
drivers/gpu/ipu-v3/ipu-di.c
130
writel(value, di->base + offset);
drivers/gpu/ipu-v3/ipu-dmfc.c
149
writel(dmfc_gen1, priv->base + DMFC_GENERAL1);
drivers/gpu/ipu-v3/ipu-dmfc.c
203
writel(0x00000050, priv->base + DMFC_WR_CHAN);
drivers/gpu/ipu-v3/ipu-dmfc.c
204
writel(0x00005654, priv->base + DMFC_DP_CHAN);
drivers/gpu/ipu-v3/ipu-dmfc.c
205
writel(0x202020f6, priv->base + DMFC_WR_CHAN_DEF);
drivers/gpu/ipu-v3/ipu-dmfc.c
206
writel(0x2020f6f6, priv->base + DMFC_DP_CHAN_DEF);
drivers/gpu/ipu-v3/ipu-dmfc.c
207
writel(0x00000003, priv->base + DMFC_GENERAL1);
drivers/gpu/ipu-v3/ipu-dp.c
101
writel(reg | DP_COM_CONF_GWAM, flow->base + DP_COM_CONF);
drivers/gpu/ipu-v3/ipu-dp.c
104
writel(reg & ~DP_COM_CONF_GWAM, flow->base + DP_COM_CONF);
drivers/gpu/ipu-v3/ipu-dp.c
120
writel((x_pos << 16) | y_pos, flow->base + DP_FG_POS);
drivers/gpu/ipu-v3/ipu-dp.c
141
writel(reg, flow->base + DP_COM_CONF);
drivers/gpu/ipu-v3/ipu-dp.c
146
writel(0x099 | (0x12d << 16), flow->base + DP_CSC_A_0);
drivers/gpu/ipu-v3/ipu-dp.c
147
writel(0x03a | (0x3a9 << 16), flow->base + DP_CSC_A_1);
drivers/gpu/ipu-v3/ipu-dp.c
148
writel(0x356 | (0x100 << 16), flow->base + DP_CSC_A_2);
drivers/gpu/ipu-v3/ipu-dp.c
149
writel(0x100 | (0x329 << 16), flow->base + DP_CSC_A_3);
drivers/gpu/ipu-v3/ipu-dp.c
150
writel(0x3d6 | (0x0000 << 16) | (2 << 30),
drivers/gpu/ipu-v3/ipu-dp.c
152
writel(0x200 | (2 << 14) | (0x200 << 16) | (2 << 30),
drivers/gpu/ipu-v3/ipu-dp.c
156
writel(0x095 | (0x000 << 16), flow->base + DP_CSC_A_0);
drivers/gpu/ipu-v3/ipu-dp.c
157
writel(0x0e5 | (0x095 << 16), flow->base + DP_CSC_A_1);
drivers/gpu/ipu-v3/ipu-dp.c
158
writel(0x3e5 | (0x3bc << 16), flow->base + DP_CSC_A_2);
drivers/gpu/ipu-v3/ipu-dp.c
159
writel(0x095 | (0x10e << 16), flow->base + DP_CSC_A_3);
drivers/gpu/ipu-v3/ipu-dp.c
160
writel(0x000 | (0x3e10 << 16) | (1 << 30),
drivers/gpu/ipu-v3/ipu-dp.c
162
writel(0x09a | (1 << 14) | (0x3dbe << 16) | (1 << 30),
drivers/gpu/ipu-v3/ipu-dp.c
166
writel(0x095 | (0x000 << 16), flow->base + DP_CSC_A_0);
drivers/gpu/ipu-v3/ipu-dp.c
167
writel(0x0cc | (0x095 << 16), flow->base + DP_CSC_A_1);
drivers/gpu/ipu-v3/ipu-dp.c
168
writel(0x3ce | (0x398 << 16), flow->base + DP_CSC_A_2);
drivers/gpu/ipu-v3/ipu-dp.c
169
writel(0x095 | (0x0ff << 16), flow->base + DP_CSC_A_3);
drivers/gpu/ipu-v3/ipu-dp.c
170
writel(0x000 | (0x3e42 << 16) | (1 << 30),
drivers/gpu/ipu-v3/ipu-dp.c
172
writel(0x10a | (1 << 14) | (0x3dd6 << 16) | (1 << 30),
drivers/gpu/ipu-v3/ipu-dp.c
178
writel(reg, flow->base + DP_COM_CONF);
drivers/gpu/ipu-v3/ipu-dp.c
259
writel(reg, flow->base + DP_COM_CONF);
drivers/gpu/ipu-v3/ipu-dp.c
289
writel(reg, flow->base + DP_COM_CONF);
drivers/gpu/ipu-v3/ipu-dp.c
291
writel(0, flow->base + DP_FG_POS);
drivers/gpu/ipu-v3/ipu-dp.c
93
writel(reg, flow->base + DP_COM_CONF);
drivers/gpu/ipu-v3/ipu-dp.c
97
writel(reg | ((u32) alpha << 24),
drivers/gpu/ipu-v3/ipu-ic.c
171
writel(value, ic->priv->base + offset);
drivers/gpu/ipu-v3/ipu-ic.c
193
writel(param, base++);
drivers/gpu/ipu-v3/ipu-ic.c
197
writel(param, base++);
drivers/gpu/ipu-v3/ipu-ic.c
201
writel(param, base++);
drivers/gpu/ipu-v3/ipu-ic.c
204
writel(param, base++);
drivers/gpu/ipu-v3/ipu-ic.c
208
writel(param, base++);
drivers/gpu/ipu-v3/ipu-ic.c
211
writel(param, base++);
drivers/gpu/ipu-v3/ipu-pre.c
150
writel(0, pre->regs + IPU_PRE_CTRL);
drivers/gpu/ipu-v3/ipu-pre.c
157
writel(val, pre->regs + IPU_PRE_CTRL);
drivers/gpu/ipu-v3/ipu-pre.c
165
writel(IPU_PRE_CTRL_SFTRST, pre->regs + IPU_PRE_CTRL);
drivers/gpu/ipu-v3/ipu-pre.c
194
writel(val, pre->regs + IPU_PRE_TPR_CTRL);
drivers/gpu/ipu-v3/ipu-pre.c
220
writel(bufaddr, pre->regs + IPU_PRE_CUR_BUF);
drivers/gpu/ipu-v3/ipu-pre.c
221
writel(bufaddr, pre->regs + IPU_PRE_NEXT_BUF);
drivers/gpu/ipu-v3/ipu-pre.c
228
writel(val, pre->regs + IPU_PRE_PREFETCH_ENG_CTRL);
drivers/gpu/ipu-v3/ipu-pre.c
232
writel(val, pre->regs + IPU_PRE_PREFETCH_ENG_INPUT_SIZE);
drivers/gpu/ipu-v3/ipu-pre.c
235
writel(val, pre->regs + IPU_PRE_PREFETCH_ENG_PITCH);
drivers/gpu/ipu-v3/ipu-pre.c
240
writel(val, pre->regs + IPU_PRE_STORE_ENG_CTRL);
drivers/gpu/ipu-v3/ipu-pre.c
244
writel(val, pre->regs + IPU_PRE_STORE_ENG_SIZE);
drivers/gpu/ipu-v3/ipu-pre.c
247
writel(val, pre->regs + IPU_PRE_STORE_ENG_PITCH);
drivers/gpu/ipu-v3/ipu-pre.c
249
writel(pre->buffer_paddr, pre->regs + IPU_PRE_STORE_ENG_ADDR);
drivers/gpu/ipu-v3/ipu-pre.c
254
writel(pre->cur.ctrl | IPU_PRE_CTRL_SDW_UPDATE,
drivers/gpu/ipu-v3/ipu-pre.c
264
writel(bufaddr, pre->regs + IPU_PRE_NEXT_BUF);
drivers/gpu/ipu-v3/ipu-pre.c
292
writel(pre->cur.ctrl | IPU_PRE_CTRL_SDW_UPDATE,
drivers/gpu/ipu-v3/ipu-prg.c
260
writel(val, prg->regs + IPU_PRG_CTL);
drivers/gpu/ipu-v3/ipu-prg.c
263
writel(val, prg->regs + IPU_PRG_REG_UPDATE);
drivers/gpu/ipu-v3/ipu-prg.c
305
writel(val, prg->regs + IPU_PRG_STRIDE(prg_chan));
drivers/gpu/ipu-v3/ipu-prg.c
311
writel(val, prg->regs + IPU_PRG_HEIGHT(prg_chan));
drivers/gpu/ipu-v3/ipu-prg.c
315
writel(val, prg->regs + IPU_PRG_BADDR(prg_chan));
drivers/gpu/ipu-v3/ipu-prg.c
324
writel(val, prg->regs + IPU_PRG_CTL);
drivers/gpu/ipu-v3/ipu-prg.c
327
writel(val, prg->regs + IPU_PRG_REG_UPDATE);
drivers/gpu/ipu-v3/ipu-prg.c
405
writel(val, prg->regs + IPU_PRG_CTL);
drivers/gpu/ipu-v3/ipu-prg.c
408
writel(0xffffffff, prg->regs + IPU_PRG_THD);
drivers/gpu/ipu-v3/ipu-prv.h
211
writel(value, ipu->idmac_reg + offset);
drivers/gpu/ipu-v3/ipu-smfc.c
48
writel(val, priv->base + SMFC_BS);
drivers/gpu/ipu-v3/ipu-smfc.c
68
writel(val, priv->base + SMFC_MAP);
drivers/gpu/ipu-v3/ipu-smfc.c
88
writel(val, priv->base + SMFC_WMC);
drivers/gpu/ipu-v3/ipu-vdi.c
53
writel(value, vdi->base + offset);
drivers/hid/amd-sfh-hid/amd_sfh_pcie.c
105
writel(0, privdata->mmio + amd_get_p2c_val(privdata, 4));
drivers/hid/amd-sfh-hid/amd_sfh_pcie.c
106
writel(0xf, privdata->mmio + amd_get_p2c_val(privdata, 5));
drivers/hid/amd-sfh-hid/amd_sfh_pcie.c
163
writel(cmd_param.ul, privdata->mmio + AMD_C2P_MSG1);
drivers/hid/amd-sfh-hid/amd_sfh_pcie.c
164
writel(cmd_base.ul, privdata->mmio + AMD_C2P_MSG0);
drivers/hid/amd-sfh-hid/amd_sfh_pcie.c
178
writel(cmd_base.ul, privdata->mmio + AMD_C2P_MSG0);
drivers/hid/amd-sfh-hid/amd_sfh_pcie.c
191
writel(cmd_base.ul, privdata->mmio + AMD_C2P_MSG0);
drivers/hid/amd-sfh-hid/amd_sfh_pcie.c
72
writel(cmd_base.ul, privdata->mmio + AMD_C2P_MSG0);
drivers/hid/amd-sfh-hid/amd_sfh_pcie.c
87
writel(cmd_base.ul, privdata->mmio + AMD_C2P_MSG0);
drivers/hid/amd-sfh-hid/amd_sfh_pcie.c
99
writel(cmd_base.ul, privdata->mmio + AMD_C2P_MSG0);
drivers/hid/amd-sfh-hid/sfh1_1/amd_sfh_init.c
142
writel(0, privdata->mmio + amd_get_p2c_val(privdata, 0));
drivers/hid/amd-sfh-hid/sfh1_1/amd_sfh_init.c
199
writel(0, privdata->mmio + amd_get_p2c_val(privdata, 0));
drivers/hid/amd-sfh-hid/sfh1_1/amd_sfh_interface.c
42
writel(cmd_base.ul, privdata->mmio + amd_get_c2p_val(privdata, 0));
drivers/hid/amd-sfh-hid/sfh1_1/amd_sfh_interface.c
56
writel(cmd_base.ul, privdata->mmio + amd_get_c2p_val(privdata, 0));
drivers/hid/amd-sfh-hid/sfh1_1/amd_sfh_interface.c
69
writel(cmd_base.ul, privdata->mmio + amd_get_c2p_val(privdata, 0));
drivers/hid/intel-ish-hid/ipc/ipc.c
52
writel(value, hw->mem_addr + offset);
drivers/hsi/controllers/omap_ssi_port.c
1006
writel(SSI_WAKE(0),
drivers/hsi/controllers/omap_ssi_port.c
145
writel(val, omap_port->sst_base + SSI_SST_DIVISOR_REG);
drivers/hsi/controllers/omap_ssi_port.c
306
writel(val, omap_ssi->sys + SSI_MPU_ENABLE_REG(port->num, 0));
drivers/hsi/controllers/omap_ssi_port.c
347
writel(1, omap_port->sst_base + SSI_SST_BREAK_REG);
drivers/hsi/controllers/omap_ssi_port.c
358
writel(tmp | SSI_BREAKDETECTED,
drivers/hsi/controllers/omap_ssi_port.c
555
writel(0xff, omap_ssi->sys + SSI_GDD_MPU_IRQ_STATUS_REG);
drivers/hsi/controllers/omap_ssi_port.c
584
writel(SSI_WAKE(0), omap_ssi->sys + SSI_SET_WAKE_REG(port->num));
drivers/hsi/controllers/omap_ssi_port.c
621
writel(SSI_WAKE(0), omap_ssi->sys + SSI_CLEAR_WAKE_REG(port->num));
drivers/hsi/controllers/omap_ssi_port.c
742
writel(val, omap_ssi->sys + SSI_GDD_MPU_IRQ_STATUS_REG);
drivers/hsi/controllers/omap_ssi_port.c
747
writel(mode, omap_port->sst_base + SSI_SST_MODE_REG);
drivers/hsi/controllers/omap_ssi_port.c
748
writel(mode, omap_port->ssr_base + SSI_SSR_MODE_REG);
drivers/hsi/controllers/omap_ssi_port.c
865
writel(SSI_BREAKDETECTED,
drivers/hsi/controllers/omap_ssi_port.c
902
writel(*buf, omap_port->sst_base +
drivers/hsi/controllers/omap_ssi_port.c
919
writel(val, omap_ssi->sys +
drivers/hsi/controllers/omap_ssi_port.c
999
writel(SSI_WAKE(0),
drivers/hte/hte-tegra194.c
360
writel(val, hte->regs + reg);
drivers/hwmon/aspeed-g6-pwm-tach.c
237
writel(val, priv->base + PWM_ASPEED_DUTY_CYCLE(hwpwm));
drivers/hwmon/aspeed-g6-pwm-tach.c
250
writel(val, priv->base + PWM_ASPEED_DUTY_CYCLE(hwpwm));
drivers/hwmon/aspeed-g6-pwm-tach.c
262
writel(val, priv->base + PWM_ASPEED_CTRL(hwpwm));
drivers/hwmon/aspeed-g6-pwm-tach.c
276
writel(readl(priv->base + TACH_ASPEED_CTRL(tach_ch)) |
drivers/hwmon/aspeed-g6-pwm-tach.c
280
writel(readl(priv->base + TACH_ASPEED_CTRL(tach_ch)) &
drivers/hwmon/aspeed-g6-pwm-tach.c
353
writel(reg_val, priv->base + TACH_ASPEED_CTRL(channel));
drivers/hwmon/aspeed-g6-pwm-tach.c
420
writel(val, priv->base + TACH_ASPEED_CTRL(ch));
drivers/hwmon/aspeed-pwm-tacho.c
354
writel(val, regs + reg);
drivers/hwmon/bt1-pvt.c
122
writel((old & ~mask) | (data & mask), reg);
drivers/hwmon/bt1-pvt.c
168
writel(tout, pvt->regs + PVT_TTIMEOUT);
drivers/hwmon/sfctemp.c
62
writel(SFCTEMP_PD, sfctemp->regs);
drivers/hwmon/sfctemp.c
65
writel(0, sfctemp->regs);
drivers/hwmon/sfctemp.c
70
writel(SFCTEMP_RSTN, sfctemp->regs);
drivers/hwmon/sfctemp.c
76
writel(SFCTEMP_PD, sfctemp->regs);
drivers/hwmon/sfctemp.c
81
writel(SFCTEMP_RSTN | SFCTEMP_RUN, sfctemp->regs);
drivers/hwmon/sfctemp.c
87
writel(SFCTEMP_RSTN, sfctemp->regs);
drivers/hwmon/sparx5-temp.c
38
writel(val, hwmon->base + TEMP_CFG);
drivers/hwspinlock/omap_hwspinlock.c
51
writel(SPINLOCK_NOTTAKEN, lock_addr);
drivers/hwspinlock/sprd_hwspinlock.c
124
writel(HWSPINLOCK_USER_BITS, sprd_hwlock->base + HWSPINLOCK_RECCTRL);
drivers/hwspinlock/sprd_hwspinlock.c
64
writel(HWSPINLOCK_NOTTAKEN, lock_addr);
drivers/hwspinlock/stm32_hwspinlock.c
33
writel(STM32_MUTEX_LOCK_BIT | STM32_MUTEX_COREID, lock_addr);
drivers/hwspinlock/stm32_hwspinlock.c
43
writel(STM32_MUTEX_COREID, lock_addr);
drivers/hwspinlock/sun6i_hwspinlock.c
74
writel(SPINLOCK_NOTTAKEN, lock_addr);
drivers/hwspinlock/u8500_hsem.c
103
writel((val & ~HSEM_PROTOCOL_1), io_base + HSEM_CTRL_REG);
drivers/hwspinlock/u8500_hsem.c
106
writel(0xFFFF, io_base + HSEM_ICRALL);
drivers/hwspinlock/u8500_hsem.c
129
writel(0xFFFF, io_base + HSEM_ICRALL);
drivers/hwspinlock/u8500_hsem.c
54
writel(HSEM_MASTER_ID, lock_addr);
drivers/hwspinlock/u8500_hsem.c
68
writel(RESET_SEMAPHORE, lock_addr);
drivers/hwtracing/coresight/coresight-tnoc.c
106
writel(0x0, drvdata->base + TRACE_NOC_CTRL);
drivers/hwtracing/coresight/coresight-tnoc.c
58
writel(TRACE_NOC_CTRL_PORTEN, drvdata->base + TRACE_NOC_CTRL);
drivers/hwtracing/coresight/coresight-tnoc.c
80
writel(val, drvdata->base + TRACE_NOC_CTRL);
drivers/hwtracing/coresight/ultrasoc-smb.c
197
writel(SMB_GLB_EN_HW_ENABLE, drvdata->base + SMB_GLB_EN_REG);
drivers/hwtracing/coresight/ultrasoc-smb.c
202
writel(0x0, drvdata->base + SMB_GLB_EN_REG);
drivers/hwtracing/coresight/ultrasoc-smb.c
457
writel(SMB_LB_CFG_LO_DEFAULT, drvdata->base + SMB_LB_CFG_LO_REG);
drivers/hwtracing/coresight/ultrasoc-smb.c
458
writel(SMB_LB_CFG_HI_DEFAULT, drvdata->base + SMB_LB_CFG_HI_REG);
drivers/hwtracing/coresight/ultrasoc-smb.c
459
writel(SMB_GLB_CFG_DEFAULT, drvdata->base + SMB_GLB_CFG_REG);
drivers/hwtracing/coresight/ultrasoc-smb.c
460
writel(SMB_GLB_INT_CFG, drvdata->base + SMB_GLB_INT_REG);
drivers/hwtracing/coresight/ultrasoc-smb.c
461
writel(SMB_LB_INT_CTRL_CFG, drvdata->base + SMB_LB_INT_CTRL_REG);
drivers/hwtracing/coresight/ultrasoc-smb.c
61
writel(sdb->buf_hw_base + sdb->buf_rdptr,
drivers/hwtracing/coresight/ultrasoc-smb.c
77
writel(SMB_LB_PURGE_PURGED, drvdata->base + SMB_LB_PURGE_REG);
drivers/hwtracing/coresight/ultrasoc-smb.c
80
writel(SMB_LB_INT_STS_RESET, drvdata->base + SMB_LB_INT_STS_REG);
drivers/hwtracing/coresight/ultrasoc-smb.c
92
writel(write_ptr, drvdata->base + SMB_LB_RD_ADDR_REG);
drivers/hwtracing/ptt/hisi_ptt.c
185
writel(0, hisi_ptt->iobase + HISI_PTT_TRACE_CTRL);
drivers/hwtracing/ptt/hisi_ptt.c
188
writel(HISI_PTT_TRACE_INT_MASK_ALL, hisi_ptt->iobase + HISI_PTT_TRACE_INT_MASK);
drivers/hwtracing/ptt/hisi_ptt.c
210
writel(val, hisi_ptt->iobase + HISI_PTT_TRACE_CTRL);
drivers/hwtracing/ptt/hisi_ptt.c
216
writel(val, hisi_ptt->iobase + HISI_PTT_TRACE_CTRL);
drivers/hwtracing/ptt/hisi_ptt.c
226
writel(HISI_PTT_TRACE_INT_STAT_MASK, hisi_ptt->iobase + HISI_PTT_TRACE_INT_STAT);
drivers/hwtracing/ptt/hisi_ptt.c
227
writel(0, hisi_ptt->iobase + HISI_PTT_TRACE_INT_MASK);
drivers/hwtracing/ptt/hisi_ptt.c
239
writel(val, hisi_ptt->iobase + HISI_PTT_TRACE_CTRL);
drivers/hwtracing/ptt/hisi_ptt.c
311
writel(status, hisi_ptt->iobase + HISI_PTT_TRACE_INT_STAT);
drivers/hwtracing/ptt/hisi_ptt.c
56
writel(reg, hisi_ptt->iobase + HISI_PTT_TUNING_CTRL);
drivers/hwtracing/ptt/hisi_ptt.c
59
writel(~0U, hisi_ptt->iobase + HISI_PTT_TUNING_DATA);
drivers/hwtracing/ptt/hisi_ptt.c
721
writel(lower_32_bits(ctrl->trace_buf[i].dma),
drivers/hwtracing/ptt/hisi_ptt.c
724
writel(upper_32_bits(ctrl->trace_buf[i].dma),
drivers/hwtracing/ptt/hisi_ptt.c
728
writel(HISI_PTT_TRACE_BUF_SIZE, hisi_ptt->iobase + HISI_PTT_TRACE_ADDR_SIZE);
drivers/hwtracing/ptt/hisi_ptt.c
96
writel(reg, hisi_ptt->iobase + HISI_PTT_TUNING_CTRL);
drivers/hwtracing/ptt/hisi_ptt.c
97
writel(FIELD_PREP(HISI_PTT_TUNING_DATA_VAL_MASK, val),
drivers/i2c/busses/i2c-altera.c
102
writel(idev->isr_mask, idev->base + ALTR_I2C_ISER);
drivers/i2c/busses/i2c-altera.c
109
writel(int_en | mask, idev->base + ALTR_I2C_ISR);
drivers/i2c/busses/i2c-altera.c
116
writel(tmp & ~ALTR_I2C_CTRL_EN, idev->base + ALTR_I2C_CTRL);
drivers/i2c/busses/i2c-altera.c
123
writel(tmp | ALTR_I2C_CTRL_EN, idev->base + ALTR_I2C_CTRL);
drivers/i2c/busses/i2c-altera.c
134
writel(ALTR_I2C_TFR_CMD_STO, idev->base + ALTR_I2C_TFR_CMD);
drivers/i2c/busses/i2c-altera.c
156
writel(tmp, idev->base + ALTR_I2C_CTRL);
drivers/i2c/busses/i2c-altera.c
165
writel(t_high, idev->base + ALTR_I2C_SCL_HIGH);
drivers/i2c/busses/i2c-altera.c
167
writel(t_low, idev->base + ALTR_I2C_SCL_LOW);
drivers/i2c/busses/i2c-altera.c
169
writel(3 * clk_mhz / 10, idev->base + ALTR_I2C_SDA_HOLD);
drivers/i2c/busses/i2c-altera.c
185
writel(data, idev->base + ALTR_I2C_TFR_CMD);
drivers/i2c/busses/i2c-altera.c
325
writel(ALTR_I2C_TFR_CMD_STA | addr, idev->base + ALTR_I2C_TFR_CMD);
drivers/i2c/busses/i2c-amd-mp2-pci.c
220
writel(0, reg);
drivers/i2c/busses/i2c-amd-mp2-pci.c
221
writel(0, privdata->mmio + AMD_P2C_MSG_INTEN);
drivers/i2c/busses/i2c-amd-mp2-pci.c
232
writel(0, privdata->mmio + AMD_P2C_MSG_INTEN);
drivers/i2c/busses/i2c-amd-mp2-pci.c
282
writel(0, privdata->mmio + reg);
drivers/i2c/busses/i2c-amd-mp2-pci.c
285
writel(0, privdata->mmio + reg);
drivers/i2c/busses/i2c-amd-mp2-pci.c
315
writel(0, privdata->mmio + AMD_P2C_MSG_INTEN);
drivers/i2c/busses/i2c-amd-mp2-pci.c
52
writel(i2c_cmd_base.ul, reg);
drivers/i2c/busses/i2c-aspeed.c
1057
writel(0, bus->base + ASPEED_I2C_INTR_CTRL_REG);
drivers/i2c/busses/i2c-aspeed.c
1058
writel(0xffffffff, bus->base + ASPEED_I2C_INTR_STS_REG);
drivers/i2c/busses/i2c-aspeed.c
1093
writel(0, bus->base + ASPEED_I2C_FUN_CTRL_REG);
drivers/i2c/busses/i2c-aspeed.c
1094
writel(0, bus->base + ASPEED_I2C_INTR_CTRL_REG);
drivers/i2c/busses/i2c-aspeed.c
177
writel(ASPEED_I2CD_M_STOP_CMD, bus->base + ASPEED_I2C_CMD_REG);
drivers/i2c/busses/i2c-aspeed.c
219
writel(ASPEED_I2CD_BUS_RECOVER_CMD,
drivers/i2c/busses/i2c-aspeed.c
323
writel(value, bus->base + ASPEED_I2C_BYTE_BUF_REG);
drivers/i2c/busses/i2c-aspeed.c
324
writel(ASPEED_I2CD_S_TX_CMD, bus->base + ASPEED_I2C_CMD_REG);
drivers/i2c/busses/i2c-aspeed.c
334
writel(value, bus->base + ASPEED_I2C_BYTE_BUF_REG);
drivers/i2c/busses/i2c-aspeed.c
335
writel(ASPEED_I2CD_S_TX_CMD, bus->base + ASPEED_I2C_CMD_REG);
drivers/i2c/busses/i2c-aspeed.c
345
writel(ASPEED_I2CD_M_S_RX_CMD_LAST, bus->base + ASPEED_I2C_CMD_REG);
drivers/i2c/busses/i2c-aspeed.c
396
writel(slave_addr, bus->base + ASPEED_I2C_BYTE_BUF_REG);
drivers/i2c/busses/i2c-aspeed.c
397
writel(command, bus->base + ASPEED_I2C_CMD_REG);
drivers/i2c/busses/i2c-aspeed.c
487
writel(readl(bus->base + ASPEED_I2C_CMD_REG) &
drivers/i2c/busses/i2c-aspeed.c
534
writel(msg->buf[bus->buf_index++],
drivers/i2c/busses/i2c-aspeed.c
536
writel(ASPEED_I2CD_M_TX_CMD,
drivers/i2c/busses/i2c-aspeed.c
573
writel(command, bus->base + ASPEED_I2C_CMD_REG);
drivers/i2c/busses/i2c-aspeed.c
627
writel(irq_received & ~ASPEED_I2CD_INTR_RX_DONE,
drivers/i2c/busses/i2c-aspeed.c
674
writel(ASPEED_I2CD_INTR_RX_DONE,
drivers/i2c/busses/i2c-aspeed.c
763
writel(addr_reg_val, bus->base + ASPEED_I2C_DEV_ADDR_REG);
drivers/i2c/busses/i2c-aspeed.c
768
writel(func_ctrl_reg_val, bus->base + ASPEED_I2C_FUN_CTRL_REG);
drivers/i2c/busses/i2c-aspeed.c
807
writel(func_ctrl_reg_val, bus->base + ASPEED_I2C_FUN_CTRL_REG);
drivers/i2c/busses/i2c-aspeed.c
921
writel(clk_reg_val, bus->base + ASPEED_I2C_AC_TIMING_REG1);
drivers/i2c/busses/i2c-aspeed.c
922
writel(ASPEED_NO_TIMEOUT_CTRL, bus->base + ASPEED_I2C_AC_TIMING_REG2);
drivers/i2c/busses/i2c-aspeed.c
935
writel(0, bus->base + ASPEED_I2C_FUN_CTRL_REG);
drivers/i2c/busses/i2c-aspeed.c
947
writel(readl(bus->base + ASPEED_I2C_FUN_CTRL_REG) | fun_ctrl_reg,
drivers/i2c/busses/i2c-aspeed.c
957
writel(ASPEED_I2CD_INTR_ALL, bus->base + ASPEED_I2C_INTR_CTRL_REG);
drivers/i2c/busses/i2c-aspeed.c
971
writel(0, bus->base + ASPEED_I2C_INTR_CTRL_REG);
drivers/i2c/busses/i2c-aspeed.c
972
writel(0xffffffff, bus->base + ASPEED_I2C_INTR_STS_REG);
drivers/i2c/busses/i2c-axxia.c
159
writel(int_en & ~mask, idev->base + MST_INT_ENABLE);
drivers/i2c/busses/i2c-axxia.c
167
writel(int_en | mask, idev->base + MST_INT_ENABLE);
drivers/i2c/busses/i2c-axxia.c
192
writel(0x01, idev->base + SOFT_RESET);
drivers/i2c/busses/i2c-axxia.c
202
writel(0x1, idev->base + GLOBAL_CONTROL);
drivers/i2c/busses/i2c-axxia.c
217
writel(t_high, idev->base + SCL_HIGH_PERIOD);
drivers/i2c/busses/i2c-axxia.c
219
writel(t_low, idev->base + SCL_LOW_PERIOD);
drivers/i2c/busses/i2c-axxia.c
221
writel(t_setup, idev->base + SDA_SETUP_TIME);
drivers/i2c/busses/i2c-axxia.c
223
writel(ns_to_clk(300, clk_mhz), idev->base + SDA_HOLD_TIME);
drivers/i2c/busses/i2c-axxia.c
225
writel(ns_to_clk(50, clk_mhz), idev->base + SPIKE_FLTR_LEN);
drivers/i2c/busses/i2c-axxia.c
240
writel(prescale, idev->base + TIMER_CLOCK_DIV);
drivers/i2c/busses/i2c-axxia.c
242
writel(WT_EN | WT_VALUE(tmo_clk), idev->base + WAIT_TIMER_CONTROL);
drivers/i2c/busses/i2c-axxia.c
248
writel(0x01, idev->base + INTERRUPT_ENABLE);
drivers/i2c/busses/i2c-axxia.c
287
writel(msg->len, idev->base + MST_RX_XFER);
drivers/i2c/busses/i2c-axxia.c
307
writel(msg->buf[idev->msg_xfrd++], idev->base + MST_DATA);
drivers/i2c/busses/i2c-axxia.c
346
writel(val, idev->base + SLV_DATA);
drivers/i2c/busses/i2c-axxia.c
350
writel(val, idev->base + SLV_DATA);
drivers/i2c/busses/i2c-axxia.c
355
writel(INT_SLV, idev->base + INTERRUPT_STATUS);
drivers/i2c/busses/i2c-axxia.c
428
writel(INT_MST, idev->base + INTERRUPT_STATUS);
drivers/i2c/busses/i2c-axxia.c
445
writel(addr_1, idev->base + MST_ADDR_1);
drivers/i2c/busses/i2c-axxia.c
446
writel(addr_2, idev->base + MST_ADDR_2);
drivers/i2c/busses/i2c-axxia.c
474
writel(msgs[0].len, idev->base + MST_TX_XFER);
drivers/i2c/busses/i2c-axxia.c
475
writel(rlen, idev->base + MST_RX_XFER);
drivers/i2c/busses/i2c-axxia.c
484
writel(CMD_SEQUENCE, idev->base + MST_COMMAND);
drivers/i2c/busses/i2c-axxia.c
538
writel(rx_xfer, idev->base + MST_RX_XFER);
drivers/i2c/busses/i2c-axxia.c
539
writel(tx_xfer, idev->base + MST_TX_XFER);
drivers/i2c/busses/i2c-axxia.c
548
writel(wt_value, idev->base + WAIT_TIMER_CONTROL);
drivers/i2c/busses/i2c-axxia.c
554
writel(CMD_MANUAL, idev->base + MST_COMMAND);
drivers/i2c/busses/i2c-axxia.c
557
writel(CMD_AUTO, idev->base + MST_COMMAND);
drivers/i2c/busses/i2c-axxia.c
561
writel(WT_EN | wt_value, idev->base + WAIT_TIMER_CONTROL);
drivers/i2c/busses/i2c-axxia.c
637
writel(tmp, idev->base + I2C_BUS_MONITOR);
drivers/i2c/busses/i2c-axxia.c
673
writel(GLOBAL_MST_EN | GLOBAL_SLV_EN, idev->base + GLOBAL_CONTROL);
drivers/i2c/busses/i2c-axxia.c
674
writel(INT_MST | INT_SLV, idev->base + INTERRUPT_ENABLE);
drivers/i2c/busses/i2c-axxia.c
681
writel(SLV_RX_ACSA1, idev->base + SLV_RX_CTL);
drivers/i2c/busses/i2c-axxia.c
682
writel(dec_ctl, idev->base + SLV_ADDR_DEC_CTL);
drivers/i2c/busses/i2c-axxia.c
683
writel(slave->addr, idev->base + SLV_ADDR_1);
drivers/i2c/busses/i2c-axxia.c
688
writel(slv_int_mask, idev->base + SLV_INT_ENABLE);
drivers/i2c/busses/i2c-axxia.c
698
writel(GLOBAL_MST_EN, idev->base + GLOBAL_CONTROL);
drivers/i2c/busses/i2c-axxia.c
699
writel(INT_MST, idev->base + INTERRUPT_ENABLE);
drivers/i2c/busses/i2c-bcm-iproc.c
235
writel(iproc_i2c->ape_addr_mask,
drivers/i2c/busses/i2c-bcm-iproc.c
253
writel(iproc_i2c->ape_addr_mask,
drivers/i2c/busses/i2c-bcm-iproc.c
255
writel(val, iproc_i2c->base + offset);
drivers/i2c/busses/i2c-bcm-iproc.c
258
writel(val, iproc_i2c->base + offset);
drivers/i2c/busses/i2c-bcm-kona.c
166
writel((CS_CMD_CMD_NO_ACTION << CS_CMD_SHIFT) |
drivers/i2c/busses/i2c-bcm-kona.c
172
writel((CS_ACK_CMD_GEN_START << CS_ACK_SHIFT) |
drivers/i2c/busses/i2c-bcm-kona.c
179
writel((CS_ACK_CMD_GEN_RESTART << CS_ACK_SHIFT) |
drivers/i2c/busses/i2c-bcm-kona.c
186
writel((CS_CMD_CMD_STOP << CS_CMD_SHIFT) |
drivers/i2c/busses/i2c-bcm-kona.c
198
writel(readl(dev->base + CLKEN_OFFSET) | CLKEN_CLKEN_MASK,
drivers/i2c/busses/i2c-bcm-kona.c
204
writel(readl(dev->base + CLKEN_OFFSET) & ~CLKEN_CLKEN_MASK,
drivers/i2c/busses/i2c-bcm-kona.c
218
writel(TXFCR_FIFO_FLUSH_MASK | TXFCR_FIFO_EN_MASK,
drivers/i2c/busses/i2c-bcm-kona.c
221
writel(status & ~ISR_RESERVED_MASK, dev->base + ISR_OFFSET);
drivers/i2c/busses/i2c-bcm-kona.c
254
writel(IER_I2C_INT_EN_MASK, dev->base + IER_OFFSET);
drivers/i2c/busses/i2c-bcm-kona.c
266
writel(0, dev->base + IER_OFFSET);
drivers/i2c/busses/i2c-bcm-kona.c
290
writel(IER_READ_COMPLETE_INT_MASK, dev->base + IER_OFFSET);
drivers/i2c/busses/i2c-bcm-kona.c
293
writel((last_byte_nak << RXFCR_NACK_EN_SHIFT) |
drivers/i2c/busses/i2c-bcm-kona.c
301
writel(0, dev->base + IER_OFFSET);
drivers/i2c/busses/i2c-bcm-kona.c
358
writel(ISR_SES_DONE_MASK, dev->base + ISR_OFFSET);
drivers/i2c/busses/i2c-bcm-kona.c
361
writel(IER_I2C_INT_EN_MASK, dev->base + IER_OFFSET);
drivers/i2c/busses/i2c-bcm-kona.c
367
writel(data, dev->base + DAT_OFFSET);
drivers/i2c/busses/i2c-bcm-kona.c
373
writel(0, dev->base + IER_OFFSET);
drivers/i2c/busses/i2c-bcm-kona.c
402
writel(IER_FIFO_INT_EN_MASK | IER_NOACK_EN_MASK,
drivers/i2c/busses/i2c-bcm-kona.c
410
writel(buf[k], (dev->base + DAT_OFFSET));
drivers/i2c/busses/i2c-bcm-kona.c
422
writel(0, dev->base + IER_OFFSET);
drivers/i2c/busses/i2c-bcm-kona.c
505
writel(readl(dev->base + CLKEN_OFFSET) & ~CLKEN_AUTOSENSE_OFF_MASK,
drivers/i2c/busses/i2c-bcm-kona.c
511
writel(readl(dev->base + HSTIM_OFFSET) & ~HSTIM_HS_MODE_MASK,
drivers/i2c/busses/i2c-bcm-kona.c
514
writel((dev->std_cfg->prescale << TIM_PRESCALE_SHIFT) |
drivers/i2c/busses/i2c-bcm-kona.c
520
writel((dev->std_cfg->time_m << CLKEN_M_SHIFT) |
drivers/i2c/busses/i2c-bcm-kona.c
528
writel((dev->hs_cfg->prescale << TIM_PRESCALE_SHIFT) |
drivers/i2c/busses/i2c-bcm-kona.c
534
writel((dev->hs_cfg->hs_hold << HSTIM_HS_HOLD_SHIFT) |
drivers/i2c/busses/i2c-bcm-kona.c
539
writel(readl(dev->base + HSTIM_OFFSET) | HSTIM_HS_MODE_MASK,
drivers/i2c/busses/i2c-bcm-kona.c
606
writel(0, dev->base + PADCTL_OFFSET);
drivers/i2c/busses/i2c-bcm-kona.c
682
writel(PADCTL_PAD_OUT_EN_MASK, dev->base + PADCTL_OFFSET);
drivers/i2c/busses/i2c-bcm-kona.c
789
writel(0, dev->base + TOUT_OFFSET);
drivers/i2c/busses/i2c-bcm-kona.c
795
writel(TXFCR_FIFO_FLUSH_MASK | TXFCR_FIFO_EN_MASK,
drivers/i2c/busses/i2c-bcm-kona.c
799
writel(0, dev->base + IER_OFFSET);
drivers/i2c/busses/i2c-bcm-kona.c
802
writel(ISR_CMDBUSY_MASK |
drivers/i2c/busses/i2c-bcm-kona.c
829
writel(PADCTL_PAD_OUT_EN_MASK, dev->base + PADCTL_OFFSET);
drivers/i2c/busses/i2c-bcm2835.c
76
writel(val, i2c_dev->regs + reg);
drivers/i2c/busses/i2c-brcmstb.c
602
writel(AUTOI2C_CTRL0_RELEASE_BSC, autoi2c + AUTOI2C_CTRL0);
drivers/i2c/busses/i2c-designware-common.c
104
writel(swab32(val), dev->base + reg);
drivers/i2c/busses/i2c-designware-common.c
235
writel((dev->sda_hold_time << 1) | MSCC_ICPU_CFG_TWI_DELAY_ENABLE,
drivers/i2c/busses/i2c-designware-common.c
86
writel(val, dev->base + reg);
drivers/i2c/busses/i2c-exynos5.c
274
writel(readl(i2c->regs + HSI2C_INT_STATUS),
drivers/i2c/busses/i2c-exynos5.c
324
writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_HS3);
drivers/i2c/busses/i2c-exynos5.c
326
writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_FS3);
drivers/i2c/busses/i2c-exynos5.c
425
writel(i2c_timing_s1, i2c->regs + HSI2C_TIMING_HS1);
drivers/i2c/busses/i2c-exynos5.c
426
writel(i2c_timing_s2, i2c->regs + HSI2C_TIMING_HS2);
drivers/i2c/busses/i2c-exynos5.c
427
writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_HS3);
drivers/i2c/busses/i2c-exynos5.c
429
writel(i2c_timing_s1, i2c->regs + HSI2C_TIMING_FS1);
drivers/i2c/busses/i2c-exynos5.c
430
writel(i2c_timing_s2, i2c->regs + HSI2C_TIMING_FS2);
drivers/i2c/busses/i2c-exynos5.c
431
writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_FS3);
drivers/i2c/busses/i2c-exynos5.c
433
writel(i2c_timing_sla, i2c->regs + HSI2C_TIMING_SLA);
drivers/i2c/busses/i2c-exynos5.c
460
writel(i2c_timeout, i2c->regs + HSI2C_TIMEOUT);
drivers/i2c/busses/i2c-exynos5.c
462
writel((HSI2C_FUNC_MODE_I2C | HSI2C_MASTER),
drivers/i2c/busses/i2c-exynos5.c
464
writel(HSI2C_TRAILING_COUNT, i2c->regs + HSI2C_TRAILIG_CTL);
drivers/i2c/busses/i2c-exynos5.c
467
writel(HSI2C_MASTER_ID(MASTER_ID(i2c->adap.nr)),
drivers/i2c/busses/i2c-exynos5.c
472
writel(i2c_conf | HSI2C_AUTO_MODE, i2c->regs + HSI2C_CONF);
drivers/i2c/busses/i2c-exynos5.c
482
writel(i2c_ctl, i2c->regs + HSI2C_CTL);
drivers/i2c/busses/i2c-exynos5.c
486
writel(i2c_ctl, i2c->regs + HSI2C_CTL);
drivers/i2c/busses/i2c-exynos5.c
513
writel(int_status, i2c->regs + HSI2C_INT_STATUS);
drivers/i2c/busses/i2c-exynos5.c
595
writel(int_en, i2c->regs + HSI2C_INT_ENABLE);
drivers/i2c/busses/i2c-exynos5.c
601
writel(byte, i2c->regs + HSI2C_TX_DATA);
drivers/i2c/busses/i2c-exynos5.c
610
writel(0, i2c->regs + HSI2C_INT_ENABLE);
drivers/i2c/busses/i2c-exynos5.c
651
writel(val, i2c->regs + HSI2C_CTL);
drivers/i2c/busses/i2c-exynos5.c
653
writel(val, i2c->regs + HSI2C_CONF);
drivers/i2c/busses/i2c-exynos5.c
660
writel(HSI2C_CMD_READ_DATA, i2c->regs + HSI2C_MANUAL_CMD);
drivers/i2c/busses/i2c-exynos5.c
662
writel(HSI2C_CMD_SEND_STOP, i2c->regs + HSI2C_MANUAL_CMD);
drivers/i2c/busses/i2c-exynos5.c
666
writel(val, i2c->regs + HSI2C_CTL);
drivers/i2c/busses/i2c-exynos5.c
668
writel(val, i2c->regs + HSI2C_CONF);
drivers/i2c/busses/i2c-exynos5.c
752
writel(i2c_addr, i2c->regs + HSI2C_ADDR);
drivers/i2c/busses/i2c-exynos5.c
754
writel(fifo_ctl, i2c->regs + HSI2C_FIFO_CTL);
drivers/i2c/busses/i2c-exynos5.c
755
writel(i2c_ctl, i2c->regs + HSI2C_CTL);
drivers/i2c/busses/i2c-exynos5.c
764
writel(int_en, i2c->regs + HSI2C_INT_ENABLE);
drivers/i2c/busses/i2c-exynos5.c
770
writel(i2c_auto_conf, i2c->regs + HSI2C_AUTO_CONF);
drivers/i2c/busses/i2c-hisi.c
164
writel(reg, ctlr->iobase + HISI_I2C_FRAME_CTRL);
drivers/i2c/busses/i2c-hisi.c
169
writel(reg, ctlr->iobase + HISI_I2C_SLV_ADDR);
drivers/i2c/busses/i2c-hisi.c
173
writel(reg, ctlr->iobase + HISI_I2C_FIFO_CTRL);
drivers/i2c/busses/i2c-hisi.c
175
writel(reg, ctlr->iobase + HISI_I2C_FIFO_CTRL);
drivers/i2c/busses/i2c-hisi.c
310
writel(cmd, ctlr->iobase + HISI_I2C_CMD_TXDATA);
drivers/i2c/busses/i2c-hisi.c
411
writel(scl_hcnt, ctlr->iobase + reg_hcnt);
drivers/i2c/busses/i2c-hisi.c
412
writel(scl_lcnt, ctlr->iobase + reg_lcnt);
drivers/i2c/busses/i2c-hisi.c
444
writel(reg, ctlr->iobase + HISI_I2C_FRAME_CTRL);
drivers/i2c/busses/i2c-hisi.c
449
writel(reg, ctlr->iobase + HISI_I2C_SDA_HOLD);
drivers/i2c/busses/i2c-hisi.c
451
writel(ctlr->spk_len, ctlr->iobase + HISI_I2C_FS_SPK_LEN);
drivers/i2c/busses/i2c-hisi.c
455
writel(reg, ctlr->iobase + HISI_I2C_FIFO_CTRL);
drivers/i2c/busses/i2c-hydra.c
35
writel(val, &hydra->CachePD);
drivers/i2c/busses/i2c-img-scb.c
416
writel(value, i2c->base + offset);
drivers/i2c/busses/i2c-imx-lpi2c.c
1000
writel(dma->tx_burst_num | (dma->rx_burst_num - 1) << 16,
drivers/i2c/busses/i2c-imx-lpi2c.c
1003
writel(MDER_TDDE | MDER_RDDE, lpi2c_imx->base + LPI2C_MDER);
drivers/i2c/busses/i2c-imx-lpi2c.c
1006
writel(dma->tx_burst_num, lpi2c_imx->base + LPI2C_MFCR);
drivers/i2c/busses/i2c-imx-lpi2c.c
1008
writel(MDER_TDDE, lpi2c_imx->base + LPI2C_MDER);
drivers/i2c/busses/i2c-imx-lpi2c.c
1096
writel(0, lpi2c_imx->base + LPI2C_MDER);
drivers/i2c/busses/i2c-imx-lpi2c.c
1193
writel(0, lpi2c_imx->base + LPI2C_SIER);
drivers/i2c/busses/i2c-imx-lpi2c.c
1203
writel(value, lpi2c_imx->base + LPI2C_STDR);
drivers/i2c/busses/i2c-imx-lpi2c.c
1218
writel(value, lpi2c_imx->base + LPI2C_STDR);
drivers/i2c/busses/i2c-imx-lpi2c.c
1229
writel(ssr & SSR_CLEAR_BITS, lpi2c_imx->base + LPI2C_SSR);
drivers/i2c/busses/i2c-imx-lpi2c.c
1283
writel(SCR_RST, lpi2c_imx->base + LPI2C_SCR);
drivers/i2c/busses/i2c-imx-lpi2c.c
1284
writel(0, lpi2c_imx->base + LPI2C_SCR);
drivers/i2c/busses/i2c-imx-lpi2c.c
1287
writel((lpi2c_imx->target->addr << 1), lpi2c_imx->base + LPI2C_SAMR);
drivers/i2c/busses/i2c-imx-lpi2c.c
1289
writel(SCFGR1_RXSTALL | SCFGR1_TXDSTALL, lpi2c_imx->base + LPI2C_SCFGR1);
drivers/i2c/busses/i2c-imx-lpi2c.c
1314
writel(temp, lpi2c_imx->base + LPI2C_SCFGR2);
drivers/i2c/busses/i2c-imx-lpi2c.c
1322
writel(SCR_SEN | SCR_FILTEN, lpi2c_imx->base + LPI2C_SCR);
drivers/i2c/busses/i2c-imx-lpi2c.c
1325
writel(SLAVE_INT_FLAG, lpi2c_imx->base + LPI2C_SIER);
drivers/i2c/busses/i2c-imx-lpi2c.c
1358
writel(0, lpi2c_imx->base + LPI2C_SAMR);
drivers/i2c/busses/i2c-imx-lpi2c.c
1360
writel(SCR_RST, lpi2c_imx->base + LPI2C_SCR);
drivers/i2c/busses/i2c-imx-lpi2c.c
1361
writel(0, lpi2c_imx->base + LPI2C_SCR);
drivers/i2c/busses/i2c-imx-lpi2c.c
223
writel(enable, lpi2c_imx->base + LPI2C_MIER);
drivers/i2c/busses/i2c-imx-lpi2c.c
236
writel(temp, lpi2c_imx->base + LPI2C_MSR);
drivers/i2c/busses/i2c-imx-lpi2c.c
282
writel(temp, lpi2c_imx->base + LPI2C_MCR);
drivers/i2c/busses/i2c-imx-lpi2c.c
283
writel(0x7f00, lpi2c_imx->base + LPI2C_MSR);
drivers/i2c/busses/i2c-imx-lpi2c.c
286
writel(temp, lpi2c_imx->base + LPI2C_MTDR);
drivers/i2c/busses/i2c-imx-lpi2c.c
296
writel(GEN_STOP << 8, lpi2c_imx->base + LPI2C_MTDR);
drivers/i2c/busses/i2c-imx-lpi2c.c
346
writel(temp, lpi2c_imx->base + LPI2C_MCFGR1);
drivers/i2c/busses/i2c-imx-lpi2c.c
350
writel(temp, lpi2c_imx->base + LPI2C_MCFGR2);
drivers/i2c/busses/i2c-imx-lpi2c.c
358
writel(temp, lpi2c_imx->base + LPI2C_MCCR1);
drivers/i2c/busses/i2c-imx-lpi2c.c
360
writel(temp, lpi2c_imx->base + LPI2C_MCCR0);
drivers/i2c/busses/i2c-imx-lpi2c.c
375
writel(temp, lpi2c_imx->base + LPI2C_MCR);
drivers/i2c/busses/i2c-imx-lpi2c.c
376
writel(0, lpi2c_imx->base + LPI2C_MCR);
drivers/i2c/busses/i2c-imx-lpi2c.c
384
writel(temp, lpi2c_imx->base + LPI2C_MCR);
drivers/i2c/busses/i2c-imx-lpi2c.c
400
writel(temp, lpi2c_imx->base + LPI2C_MCR);
drivers/i2c/busses/i2c-imx-lpi2c.c
441
writel(lpi2c_imx->txfifosize >> 1, lpi2c_imx->base + LPI2C_MFCR);
drivers/i2c/busses/i2c-imx-lpi2c.c
455
writel(temp << 16, lpi2c_imx->base + LPI2C_MFCR);
drivers/i2c/busses/i2c-imx-lpi2c.c
469
writel(data, lpi2c_imx->base + LPI2C_MTDR);
drivers/i2c/busses/i2c-imx-lpi2c.c
513
writel(temp, lpi2c_imx->base + LPI2C_MTDR);
drivers/i2c/busses/i2c-imx-lpi2c.c
572
writel(temp, lpi2c_imx->base + LPI2C_MTDR);
drivers/i2c/busses/i2c-imx-lpi2c.c
589
writel((RECV_DATA << 8) | 0x01, lpi2c_imx->base + LPI2C_MTDR);
drivers/i2c/busses/i2c-imx-lpi2c.c
612
writel((RECV_DATA << 8) | (block_len - 2), lpi2c_imx->base + LPI2C_MTDR);
drivers/i2c/busses/i2c-ismt.c
307
writel((val & ~ISMT_MCTRL_FMHP) | fmhp,
drivers/i2c/busses/i2c-ismt.c
312
writel(val | ISMT_MCTRL_SS,
drivers/i2c/busses/i2c-ismt.c
390
writel(ISMT_GCTRL_KILL, priv->smba + ISMT_GR_GCTRL);
drivers/i2c/busses/i2c-ismt.c
704
writel(val | ISMT_MSTS_MIS | ISMT_MSTS_MEIS,
drivers/i2c/busses/i2c-ismt.c
735
writel(ISMT_MCTRL_MEIE, priv->smba + ISMT_MSTR_MCTRL);
drivers/i2c/busses/i2c-ismt.c
738
writel(0, priv->smba + ISMT_MSTR_MSTS);
drivers/i2c/busses/i2c-ismt.c
742
writel((val & ~ISMT_MDS_MASK) | (ISMT_DESC_ENTRIES - 1),
drivers/i2c/busses/i2c-ismt.c
757
writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_80K),
drivers/i2c/busses/i2c-ismt.c
763
writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_100K),
drivers/i2c/busses/i2c-ismt.c
769
writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_400K),
drivers/i2c/busses/i2c-ismt.c
775
writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_1M),
drivers/i2c/busses/i2c-k1.c
139
writel(val, i2c->base + SPACEMIT_ICR);
drivers/i2c/busses/i2c-k1.c
148
writel(val, i2c->base + SPACEMIT_ICR);
drivers/i2c/busses/i2c-k1.c
153
writel(SPACEMIT_CR_UR, i2c->base + SPACEMIT_ICR);
drivers/i2c/busses/i2c-k1.c
155
writel(0, i2c->base + SPACEMIT_ICR);
drivers/i2c/busses/i2c-k1.c
194
writel(FIELD_PREP(SPACEMIT_RCR_FIELD_RST_CYC, 1),
drivers/i2c/busses/i2c-k1.c
196
writel(SPACEMIT_CR_RSTREQ, i2c->base + SPACEMIT_ICR);
drivers/i2c/busses/i2c-k1.c
236
writel(mask & SPACEMIT_I2C_INT_STATUS_MASK, i2c->base + SPACEMIT_ISR);
drivers/i2c/busses/i2c-k1.c
273
writel(val, i2c->base + SPACEMIT_ICR);
drivers/i2c/busses/i2c-k1.c
281
writel(val, i2c->base + SPACEMIT_IRCR);
drivers/i2c/busses/i2c-k1.c
299
writel(target_addr_rw, i2c->base + SPACEMIT_IDBR);
drivers/i2c/busses/i2c-k1.c
305
writel(val, i2c->base + SPACEMIT_ICR);
drivers/i2c/busses/i2c-k1.c
357
writel(*i2c->msg_buf++, i2c->base + SPACEMIT_IDBR);
drivers/i2c/busses/i2c-k1.c
414
writel(val, i2c->base + SPACEMIT_ICR);
drivers/i2c/busses/i2c-k1.c
465
writel(val, i2c->base + SPACEMIT_ICR);
drivers/i2c/busses/i2c-lpc2k.c
132
writel(data, i2c->base + LPC24XX_I2DAT);
drivers/i2c/busses/i2c-lpc2k.c
133
writel(LPC24XX_STA, i2c->base + LPC24XX_I2CONCLR);
drivers/i2c/busses/i2c-lpc2k.c
143
writel(i2c->msg->buf[i2c->msg_idx],
drivers/i2c/busses/i2c-lpc2k.c
147
writel(LPC24XX_STO_AA, i2c->base + LPC24XX_I2CONSET);
drivers/i2c/busses/i2c-lpc2k.c
148
writel(LPC24XX_SI, i2c->base + LPC24XX_I2CONCLR);
drivers/i2c/busses/i2c-lpc2k.c
163
writel(LPC24XX_AA, i2c->base + LPC24XX_I2CONCLR);
drivers/i2c/busses/i2c-lpc2k.c
166
writel(LPC24XX_AA, i2c->base + LPC24XX_I2CONSET);
drivers/i2c/busses/i2c-lpc2k.c
169
writel(LPC24XX_STA, i2c->base + LPC24XX_I2CONCLR);
drivers/i2c/busses/i2c-lpc2k.c
187
writel(LPC24XX_STO_AA, i2c->base + LPC24XX_I2CONSET);
drivers/i2c/busses/i2c-lpc2k.c
188
writel(LPC24XX_SI, i2c->base + LPC24XX_I2CONCLR);
drivers/i2c/busses/i2c-lpc2k.c
204
writel(LPC24XX_AA, i2c->base + LPC24XX_I2CONCLR);
drivers/i2c/busses/i2c-lpc2k.c
207
writel(LPC24XX_AA, i2c->base + LPC24XX_I2CONSET);
drivers/i2c/busses/i2c-lpc2k.c
210
writel(LPC24XX_STA, i2c->base + LPC24XX_I2CONCLR);
drivers/i2c/busses/i2c-lpc2k.c
218
writel(LPC24XX_STO_AA, i2c->base + LPC24XX_I2CONSET);
drivers/i2c/busses/i2c-lpc2k.c
228
writel(LPC24XX_STA | LPC24XX_STO, i2c->base + LPC24XX_I2CONCLR);
drivers/i2c/busses/i2c-lpc2k.c
248
writel(LPC24XX_SI, i2c->base + LPC24XX_I2CONCLR);
drivers/i2c/busses/i2c-lpc2k.c
255
writel(LPC24XX_STA, i2c->base + LPC24XX_I2CONSET);
drivers/i2c/busses/i2c-lpc2k.c
267
writel(i2c->msg->buf[0],
drivers/i2c/busses/i2c-lpc2k.c
273
writel(LPC24XX_STA, i2c->base + LPC24XX_I2CONSET);
drivers/i2c/busses/i2c-lpc2k.c
276
writel(LPC24XX_SI, i2c->base + LPC24XX_I2CONCLR);
drivers/i2c/busses/i2c-lpc2k.c
405
writel(scl_high, i2c->base + LPC24XX_I2SCLH);
drivers/i2c/busses/i2c-lpc2k.c
406
writel(clkrate - scl_high, i2c->base + LPC24XX_I2SCLL);
drivers/i2c/busses/i2c-lpc2k.c
86
writel(LPC24XX_CLEAR_ALL, i2c->base + LPC24XX_I2CONCLR);
drivers/i2c/busses/i2c-lpc2k.c
87
writel(0, i2c->base + LPC24XX_I2ADDR);
drivers/i2c/busses/i2c-lpc2k.c
88
writel(LPC24XX_I2EN, i2c->base + LPC24XX_I2CONSET);
drivers/i2c/busses/i2c-lpc2k.c
99
writel(LPC24XX_STO, i2c->base + LPC24XX_I2CONSET);
drivers/i2c/busses/i2c-mchp-pci1xxxx.c
1090
writel(regval, p);
drivers/i2c/busses/i2c-mchp-pci1xxxx.c
1112
writel(regval, p2);
drivers/i2c/busses/i2c-mchp-pci1xxxx.c
339
writel(SMBUS_PERI_LOCK, p);
drivers/i2c/busses/i2c-mchp-pci1xxxx.c
356
writel(0, p);
drivers/i2c/busses/i2c-mchp-pci1xxxx.c
678
writel(SMB_IDLE_SCALING_100K, p_idle_scaling);
drivers/i2c/busses/i2c-mchp-pci1xxxx.c
680
writel(CLK_SYNC_100K, p_clk_sync);
drivers/i2c/busses/i2c-mchp-pci1xxxx.c
681
writel(DATA_TIMING_100K, p_data_timing);
drivers/i2c/busses/i2c-mchp-pci1xxxx.c
682
writel(TO_SCALING_100K, p_to_scaling);
drivers/i2c/busses/i2c-mchp-pci1xxxx.c
687
writel(SMB_IDLE_SCALING_1000K, p_idle_scaling);
drivers/i2c/busses/i2c-mchp-pci1xxxx.c
689
writel(CLK_SYNC_1000K, p_clk_sync);
drivers/i2c/busses/i2c-mchp-pci1xxxx.c
690
writel(DATA_TIMING_1000K, p_data_timing);
drivers/i2c/busses/i2c-mchp-pci1xxxx.c
691
writel(TO_SCALING_1000K, p_to_scaling);
drivers/i2c/busses/i2c-mchp-pci1xxxx.c
697
writel(SMB_IDLE_SCALING_400K, p_idle_scaling);
drivers/i2c/busses/i2c-mchp-pci1xxxx.c
699
writel(CLK_SYNC_400K, p_clk_sync);
drivers/i2c/busses/i2c-mchp-pci1xxxx.c
700
writel(DATA_TIMING_400K, p_data_timing);
drivers/i2c/busses/i2c-mchp-pci1xxxx.c
701
writel(TO_SCALING_400K, p_to_scaling);
drivers/i2c/busses/i2c-meson.c
119
writel(data, i2c->regs + reg);
drivers/i2c/busses/i2c-meson.c
244
writel(wdata0, i2c->regs + REG_TOK_WDATA0);
drivers/i2c/busses/i2c-meson.c
245
writel(wdata1, i2c->regs + REG_TOK_WDATA1);
drivers/i2c/busses/i2c-meson.c
274
writel(i2c->tokens[0], i2c->regs + REG_TOK_LIST0);
drivers/i2c/busses/i2c-meson.c
275
writel(i2c->tokens[1], i2c->regs + REG_TOK_LIST1);
drivers/i2c/busses/i2c-mlxbf.c
1109
writel(timer, priv->timer->io +
drivers/i2c/busses/i2c-mlxbf.c
1120
writel(timer, priv->timer->io +
drivers/i2c/busses/i2c-mlxbf.c
1127
writel(timer, priv->timer->io + MLXBF_I2C_SMBUS_TIMER_THOLD);
drivers/i2c/busses/i2c-mlxbf.c
1133
writel(timer, priv->timer->io +
drivers/i2c/busses/i2c-mlxbf.c
1138
writel(timer, priv->timer->io + MLXBF_I2C_SMBUS_TIMER_TSETUP_DATA);
drivers/i2c/busses/i2c-mlxbf.c
1144
writel(timer, priv->timer->io + MLXBF_I2C_SMBUS_THIGH_MAX_TBUF);
drivers/i2c/busses/i2c-mlxbf.c
1148
writel(timer, priv->timer->io + MLXBF_I2C_SMBUS_SCL_LOW_TIMEOUT);
drivers/i2c/busses/i2c-mlxbf.c
1419
writel(config_reg, gpio_res->io + MLXBF_I2C_GPIO_0_FUNC_EN_0);
drivers/i2c/busses/i2c-mlxbf.c
1424
writel(config_reg, gpio_res->io + MLXBF_I2C_GPIO_0_FORCE_OE_EN);
drivers/i2c/busses/i2c-mlxbf.c
1576
writel(slave_reg, priv->slv->io +
drivers/i2c/busses/i2c-mlxbf.c
1632
writel(slave_reg, priv->slv->io +
drivers/i2c/busses/i2c-mlxbf.c
1736
writel(0, priv->slv->io + MLXBF_I2C_SMBUS_SLAVE_FSM);
drivers/i2c/busses/i2c-mlxbf.c
1745
writel(~0, priv->slv_cause->io + MLXBF_I2C_CAUSE_OR_CLEAR);
drivers/i2c/busses/i2c-mlxbf.c
1748
writel(int_reg, priv->slv_cause->io + MLXBF_I2C_CAUSE_OR_EVTEN0);
drivers/i2c/busses/i2c-mlxbf.c
1751
writel(0x1, priv->slv->io + MLXBF_I2C_SMBUS_SLAVE_READY);
drivers/i2c/busses/i2c-mlxbf.c
1791
writel(~0x0, priv->slv_cause->io + MLXBF_I2C_CAUSE_OR_CLEAR);
drivers/i2c/busses/i2c-mlxbf.c
1892
writel(control32, priv->slv->io + MLXBF_I2C_SMBUS_SLAVE_GW);
drivers/i2c/busses/i2c-mlxbf.c
1904
writel(0x0, priv->slv->io + MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES);
drivers/i2c/busses/i2c-mlxbf.c
1905
writel(0x0, priv->slv->io + MLXBF_I2C_SMBUS_SLAVE_PEC);
drivers/i2c/busses/i2c-mlxbf.c
1906
writel(0x1, priv->slv->io + MLXBF_I2C_SMBUS_SLAVE_READY);
drivers/i2c/busses/i2c-mlxbf.c
1960
writel(0x0, priv->slv->io + MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES);
drivers/i2c/busses/i2c-mlxbf.c
1961
writel(0x0, priv->slv->io + MLXBF_I2C_SMBUS_SLAVE_PEC);
drivers/i2c/busses/i2c-mlxbf.c
1962
writel(0x1, priv->slv->io + MLXBF_I2C_SMBUS_SLAVE_READY);
drivers/i2c/busses/i2c-mlxbf.c
656
writel(0x0, priv->mst->io + MLXBF_I2C_SMBUS_MASTER_STATUS);
drivers/i2c/busses/i2c-mlxbf.c
658
writel(~0x0, priv->mst_cause->io + MLXBF_I2C_CAUSE_OR_CLEAR);
drivers/i2c/busses/i2c-mlxbf.c
660
writel(0x0, priv->mst->io + MLXBF_I2C_SMBUS_MASTER_PEC);
drivers/i2c/busses/i2c-mlxbf.c
662
writel(0x0, priv->mst->io + priv->chip->smbus_master_rs_bytes_off);
drivers/i2c/busses/i2c-mlxbf.c
665
writel(command, priv->mst->io + MLXBF_I2C_SMBUS_MASTER_GW);
drivers/i2c/busses/i2c-mlxbf.c
818
writel(MLXBF_I2C_SMBUS_MASTER_FSM_PS_STATE_MASK,
drivers/i2c/busses/i2c-mlxbf.c
824
writel(0, priv->mst->io + MLXBF_I2C_SMBUS_MASTER_GW);
drivers/i2c/busses/i2c-mt65xx.c
1021
writel(I2C_DMA_HANDSHAKE_RST | I2C_DMA_WARM_RST,
drivers/i2c/busses/i2c-mt65xx.c
1033
writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST);
drivers/i2c/busses/i2c-mt65xx.c
1087
writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG);
drivers/i2c/busses/i2c-mt65xx.c
1088
writel(I2C_DMA_CON_RX | dma_sync, i2c->pdmabase + OFFSET_CON);
drivers/i2c/busses/i2c-mt65xx.c
1104
writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE);
drivers/i2c/busses/i2c-mt65xx.c
1107
writel((u32)rpaddr, i2c->pdmabase + OFFSET_RX_MEM_ADDR);
drivers/i2c/busses/i2c-mt65xx.c
1108
writel(msgs->len, i2c->pdmabase + OFFSET_RX_LEN);
drivers/i2c/busses/i2c-mt65xx.c
1110
writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG);
drivers/i2c/busses/i2c-mt65xx.c
1111
writel(I2C_DMA_CON_TX | dma_sync, i2c->pdmabase + OFFSET_CON);
drivers/i2c/busses/i2c-mt65xx.c
1127
writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE);
drivers/i2c/busses/i2c-mt65xx.c
1130
writel((u32)wpaddr, i2c->pdmabase + OFFSET_TX_MEM_ADDR);
drivers/i2c/busses/i2c-mt65xx.c
1131
writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN);
drivers/i2c/busses/i2c-mt65xx.c
1133
writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_INT_FLAG);
drivers/i2c/busses/i2c-mt65xx.c
1134
writel(I2C_DMA_CLR_FLAG | dma_sync, i2c->pdmabase + OFFSET_CON);
drivers/i2c/busses/i2c-mt65xx.c
1173
writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE);
drivers/i2c/busses/i2c-mt65xx.c
1176
writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE);
drivers/i2c/busses/i2c-mt65xx.c
1179
writel((u32)wpaddr, i2c->pdmabase + OFFSET_TX_MEM_ADDR);
drivers/i2c/busses/i2c-mt65xx.c
1180
writel((u32)rpaddr, i2c->pdmabase + OFFSET_RX_MEM_ADDR);
drivers/i2c/busses/i2c-mt65xx.c
1181
writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN);
drivers/i2c/busses/i2c-mt65xx.c
1182
writel((msgs + 1)->len, i2c->pdmabase + OFFSET_RX_LEN);
drivers/i2c/busses/i2c-mt65xx.c
1185
writel(I2C_DMA_START_EN, i2c->pdmabase + OFFSET_EN);
drivers/i2c/busses/i2c-mt65xx.c
564
writel(I2C_DMA_WARM_RST, i2c->pdmabase + OFFSET_RST);
drivers/i2c/busses/i2c-mt65xx.c
566
writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST);
drivers/i2c/busses/i2c-mt65xx.c
568
writel(I2C_DMA_HANDSHAKE_RST | I2C_DMA_HARD_RST,
drivers/i2c/busses/i2c-mt65xx.c
573
writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST);
drivers/i2c/busses/i2c-mt65xx.c
576
writel(I2C_DMA_HARD_RST, i2c->pdmabase + OFFSET_RST);
drivers/i2c/busses/i2c-mt65xx.c
578
writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST);
drivers/i2c/busses/i2c-mv64xxx.c
206
writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL);
drivers/i2c/busses/i2c-mv64xxx.c
207
writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_TIMING);
drivers/i2c/busses/i2c-mv64xxx.c
208
writel(0, drv_data->reg_base +
drivers/i2c/busses/i2c-mv64xxx.c
210
writel(0, drv_data->reg_base +
drivers/i2c/busses/i2c-mv64xxx.c
214
writel(0, drv_data->reg_base + drv_data->reg_offsets.soft_reset);
drivers/i2c/busses/i2c-mv64xxx.c
215
writel(MV64XXX_I2C_BAUD_DIV_M(drv_data->freq_m) | MV64XXX_I2C_BAUD_DIV_N(drv_data->freq_n),
drivers/i2c/busses/i2c-mv64xxx.c
217
writel(0, drv_data->reg_base + drv_data->reg_offsets.addr);
drivers/i2c/busses/i2c-mv64xxx.c
218
writel(0, drv_data->reg_base + drv_data->reg_offsets.ext_addr);
drivers/i2c/busses/i2c-mv64xxx.c
219
writel(MV64XXX_I2C_REG_CONTROL_TWSIEN | MV64XXX_I2C_REG_CONTROL_STOP,
drivers/i2c/busses/i2c-mv64xxx.c
346
writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_START,
drivers/i2c/busses/i2c-mv64xxx.c
374
writel(drv_data->cntl_bits,
drivers/i2c/busses/i2c-mv64xxx.c
379
writel(drv_data->addr1,
drivers/i2c/busses/i2c-mv64xxx.c
381
writel(drv_data->cntl_bits,
drivers/i2c/busses/i2c-mv64xxx.c
386
writel(drv_data->addr2,
drivers/i2c/busses/i2c-mv64xxx.c
388
writel(drv_data->cntl_bits,
drivers/i2c/busses/i2c-mv64xxx.c
393
writel(drv_data->msg->buf[drv_data->byte_posn++],
drivers/i2c/busses/i2c-mv64xxx.c
395
writel(drv_data->cntl_bits,
drivers/i2c/busses/i2c-mv64xxx.c
402
writel(drv_data->cntl_bits,
drivers/i2c/busses/i2c-mv64xxx.c
411
writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP,
drivers/i2c/busses/i2c-mv64xxx.c
430
writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP,
drivers/i2c/busses/i2c-mv64xxx.c
492
writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL);
drivers/i2c/busses/i2c-mv64xxx.c
493
writel(0, drv_data->reg_base +
drivers/i2c/busses/i2c-mv64xxx.c
532
writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_IFLG,
drivers/i2c/busses/i2c-mv64xxx.c
630
writel(buf[0], drv_data->reg_base + MV64XXX_I2C_REG_TX_DATA_LO);
drivers/i2c/busses/i2c-mv64xxx.c
631
writel(buf[1], drv_data->reg_base + MV64XXX_I2C_REG_TX_DATA_HI);
drivers/i2c/busses/i2c-mv64xxx.c
685
writel(ctrl_reg, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL);
drivers/i2c/busses/i2c-mxs.c
145
writel(i2c->timing0, i2c->regs + MXS_I2C_TIMING0);
drivers/i2c/busses/i2c-mxs.c
146
writel(i2c->timing1, i2c->regs + MXS_I2C_TIMING1);
drivers/i2c/busses/i2c-mxs.c
147
writel(i2c->timing2, i2c->regs + MXS_I2C_TIMING2);
drivers/i2c/busses/i2c-mxs.c
149
writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_SET);
drivers/i2c/busses/i2c-mxs.c
340
writel(cmd, i2c->regs + MXS_I2C_CTRL0);
drivers/i2c/busses/i2c-mxs.c
345
writel(reg, i2c->regs + MXS_I2C_CTRL0);
drivers/i2c/busses/i2c-mxs.c
359
writel(cmd, i2c->regs + MXS_I2C_CTRL0);
drivers/i2c/busses/i2c-mxs.c
362
writel(MXS_I2C_CTRL0_PIO_MODE, i2c->regs + MXS_I2C_CTRL0_SET);
drivers/i2c/busses/i2c-mxs.c
364
writel(data, i2c->regs + MXS_I2C_DATA(i2c));
drivers/i2c/busses/i2c-mxs.c
365
writel(MXS_I2C_CTRL0_RUN, i2c->regs + MXS_I2C_CTRL0_SET);
drivers/i2c/busses/i2c-mxs.c
378
writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_CLR);
drivers/i2c/busses/i2c-mxs.c
512
writel(MXS_I2C_DEBUG0_DMAREQ,
drivers/i2c/busses/i2c-mxs.c
546
writel(MXS_I2C_IRQ_MASK, i2c->regs + MXS_I2C_CTRL1_CLR);
drivers/i2c/busses/i2c-mxs.c
547
writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_SET);
drivers/i2c/busses/i2c-mxs.c
551
writel(MXS_I2C_CTRL0_PIO_MODE, i2c->regs + MXS_I2C_CTRL0_CLR);
drivers/i2c/busses/i2c-mxs.c
616
writel(MXS_I2C_CTRL1_CLR_GOT_A_NAK,
drivers/i2c/busses/i2c-mxs.c
684
writel(stat, i2c->regs + MXS_I2C_CTRL1_CLR);
drivers/i2c/busses/i2c-mxs.c
858
writel(MXS_I2C_CTRL0_SFTRST,
drivers/i2c/busses/i2c-mxs.c
875
writel(MXS_I2C_CTRL0_SFTRST, i2c->regs + MXS_I2C_CTRL0_SET);
drivers/i2c/busses/i2c-nomadik.c
231
writel(readl(reg) | mask, reg);
drivers/i2c/busses/i2c-nomadik.c
236
writel(readl(reg) & ~mask, reg);
drivers/i2c/busses/i2c-nomadik.c
252
writel(val, priv->virtbase + reg);
drivers/i2c/busses/i2c-nomadik.c
277
writel((I2C_CR_FTX | I2C_CR_FRX), priv->virtbase + I2C_CR);
drivers/i2c/busses/i2c-nomadik.c
302
writel(0, priv->virtbase + I2C_IMSCR);
drivers/i2c/busses/i2c-nomadik.c
311
writel(I2C_CLEAR_ALL_INTS, priv->virtbase + I2C_ICR);
drivers/i2c/busses/i2c-nomadik.c
406
writel(0x0, priv->virtbase + I2C_CR);
drivers/i2c/busses/i2c-nomadik.c
407
writel(0x0, priv->virtbase + I2C_HSMCR);
drivers/i2c/busses/i2c-nomadik.c
408
writel(0x0, priv->virtbase + I2C_TFTR);
drivers/i2c/busses/i2c-nomadik.c
409
writel(0x0, priv->virtbase + I2C_RFTR);
drivers/i2c/busses/i2c-nomadik.c
410
writel(0x0, priv->virtbase + I2C_DMAR);
drivers/i2c/busses/i2c-nomadik.c
443
writel(FIELD_PREP(I2C_SCR_SLSU, slsu), priv->virtbase + I2C_SCR);
drivers/i2c/busses/i2c-nomadik.c
470
writel(brcr, priv->virtbase + I2C_BRCR);
drivers/i2c/busses/i2c-nomadik.c
473
writel(FIELD_PREP(I2C_CR_SM, priv->sm), priv->virtbase + I2C_CR);
drivers/i2c/busses/i2c-nomadik.c
476
writel(priv->tft, priv->virtbase + I2C_TFTR);
drivers/i2c/busses/i2c-nomadik.c
477
writel(priv->rft, priv->virtbase + I2C_RFTR);
drivers/i2c/busses/i2c-nomadik.c
512
writel(mcr, priv->virtbase + I2C_MCR);
drivers/i2c/busses/i2c-nomadik.c
515
writel(readl(priv->virtbase + I2C_CR) | DEFAULT_I2C_REG_CR,
drivers/i2c/busses/i2c-nomadik.c
535
writel(readl(priv->virtbase + I2C_IMSCR) | irq_mask,
drivers/i2c/busses/i2c-nomadik.c
578
writel(mcr, priv->virtbase + I2C_MCR);
drivers/i2c/busses/i2c-nomadik.c
581
writel(readl(priv->virtbase + I2C_CR) | DEFAULT_I2C_REG_CR,
drivers/i2c/busses/i2c-nomadik.c
611
writel(readl(priv->virtbase + I2C_IMSCR) | irq_mask,
drivers/i2c/busses/i2c-nomadik.c
760
writel(readl(priv->virtbase + I2C_IMSCR) & ~irq,
drivers/i2c/busses/i2c-nvidia-gpu.c
116
writel(val, i2cd->regs + I2C_MST_CNTL);
drivers/i2c/busses/i2c-nvidia-gpu.c
144
writel(I2C_MST_CNTL_GEN_START, i2cd->regs + I2C_MST_CNTL);
drivers/i2c/busses/i2c-nvidia-gpu.c
150
writel(I2C_MST_CNTL_GEN_STOP, i2cd->regs + I2C_MST_CNTL);
drivers/i2c/busses/i2c-nvidia-gpu.c
158
writel(data, i2cd->regs + I2C_MST_DATA);
drivers/i2c/busses/i2c-nvidia-gpu.c
161
writel(val, i2cd->regs + I2C_MST_CNTL);
drivers/i2c/busses/i2c-nvidia-gpu.c
181
writel(msgs[i].addr, i2cd->regs + I2C_MST_ADDR);
drivers/i2c/busses/i2c-nvidia-gpu.c
70
writel(val, i2cd->regs + I2C_MST_HYBRID_PADCTL);
drivers/i2c/busses/i2c-nvidia-gpu.c
77
writel(val, i2cd->regs + I2C_MST_I2C0_TIMING);
drivers/i2c/busses/i2c-owl.c
118
writel(regval, reg);
drivers/i2c/busses/i2c-owl.c
130
writel(0, i2c_dev->base + OWL_I2C_REG_STAT);
drivers/i2c/busses/i2c-owl.c
165
writel(OWL_I2C_DIV_FACTOR(val), i2c_dev->base + OWL_I2C_REG_CLKDIV);
drivers/i2c/busses/i2c-owl.c
206
writel(msg->buf[i2c_dev->msg_ptr++],
drivers/i2c/busses/i2c-owl.c
292
writel(val, i2c_dev->base + OWL_I2C_REG_STAT);
drivers/i2c/busses/i2c-owl.c
319
writel(addr, i2c_dev->base + OWL_I2C_REG_TXDAT);
drivers/i2c/busses/i2c-owl.c
323
writel(msgs[0].buf[idx],
drivers/i2c/busses/i2c-owl.c
337
writel(msg->len, i2c_dev->base + OWL_I2C_REG_DATCNT);
drivers/i2c/busses/i2c-owl.c
340
writel(addr, i2c_dev->base + OWL_I2C_REG_TXDAT);
drivers/i2c/busses/i2c-owl.c
350
writel(msg->buf[idx],
drivers/i2c/busses/i2c-owl.c
366
writel(i2c_cmd, i2c_dev->base + OWL_I2C_REG_CMD);
drivers/i2c/busses/i2c-pxa.c
1022
writel(isr & VALID_INT_SOURCE, _ISR(i2c));
drivers/i2c/busses/i2c-pxa.c
1193
writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c));
drivers/i2c/busses/i2c-pxa.c
414
writel(icr, _ICR(i2c));
drivers/i2c/busses/i2c-pxa.c
422
writel(readl(_ICR(i2c)) & ~(ICR_MA | ICR_START | ICR_STOP),
drivers/i2c/busses/i2c-pxa.c
499
writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c));
drivers/i2c/busses/i2c-pxa.c
549
writel(readl(_ICR(i2c)) & ~ICR_STOP, _ICR(i2c));
drivers/i2c/busses/i2c-pxa.c
559
writel(readl(_ICR(i2c)) & ~(ICR_STOP|ICR_ACKNAK|ICR_MA), _ICR(i2c));
drivers/i2c/busses/i2c-pxa.c
560
writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
drivers/i2c/busses/i2c-pxa.c
574
writel(ICR_UR, _ICR(i2c));
drivers/i2c/busses/i2c-pxa.c
575
writel(I2C_ISR_INIT, _ISR(i2c));
drivers/i2c/busses/i2c-pxa.c
576
writel(readl(_ICR(i2c)) & ~ICR_UR, _ICR(i2c));
drivers/i2c/busses/i2c-pxa.c
579
writel(i2c->slave_addr, _ISAR(i2c));
drivers/i2c/busses/i2c-pxa.c
582
writel(I2C_ICR_INIT | (i2c->fast_mode ? i2c->fm_mask : 0), _ICR(i2c));
drivers/i2c/busses/i2c-pxa.c
583
writel(readl(_ICR(i2c)) | (i2c->high_mode ? i2c->hs_mask : 0), _ICR(i2c));
drivers/i2c/busses/i2c-pxa.c
587
writel(readl(_ICR(i2c)) | ICR_SADIE | ICR_ALDIE | ICR_SSDIE, _ICR(i2c));
drivers/i2c/busses/i2c-pxa.c
596
writel(readl(_ICR(i2c)) | ICR_IUE, _ICR(i2c));
drivers/i2c/busses/i2c-pxa.c
627
writel(byte, _IDBR(i2c));
drivers/i2c/busses/i2c-pxa.c
628
writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c)); /* allow next byte */
drivers/i2c/busses/i2c-pxa.c
639
writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
drivers/i2c/busses/i2c-pxa.c
656
writel(byte, _IDBR(i2c));
drivers/i2c/busses/i2c-pxa.c
668
writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c));
drivers/i2c/busses/i2c-pxa.c
669
writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
drivers/i2c/busses/i2c-pxa.c
685
writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
drivers/i2c/busses/i2c-pxa.c
720
writel(i2c->slave_addr, _ISAR(i2c));
drivers/i2c/busses/i2c-pxa.c
732
writel(i2c->slave_addr, _ISAR(i2c));
drivers/i2c/busses/i2c-pxa.c
744
writel(0, _IDBR(i2c));
drivers/i2c/busses/i2c-pxa.c
745
writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
drivers/i2c/busses/i2c-pxa.c
751
writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c));
drivers/i2c/busses/i2c-pxa.c
763
writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c));
drivers/i2c/busses/i2c-pxa.c
764
writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c));
drivers/i2c/busses/i2c-pxa.c
780
writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
drivers/i2c/busses/i2c-pxa.c
802
writel(i2c->req_slave_addr, _IDBR(i2c));
drivers/i2c/busses/i2c-pxa.c
808
writel(icr | ICR_START | ICR_TB, _ICR(i2c));
drivers/i2c/busses/i2c-pxa.c
818
writel(icr, _ICR(i2c));
drivers/i2c/busses/i2c-pxa.c
834
writel(i2c->master_code, _IDBR(i2c));
drivers/i2c/busses/i2c-pxa.c
838
writel(icr, _ICR(i2c));
drivers/i2c/busses/i2c-pxa.c
919
writel(i2c->msg->buf[i2c->msg_ptr++], _IDBR(i2c));
drivers/i2c/busses/i2c-pxa.c
952
writel(i2c->req_slave_addr, _IDBR(i2c));
drivers/i2c/busses/i2c-pxa.c
967
writel(icr, _ICR(i2c));
drivers/i2c/busses/i2c-pxa.c
995
writel(icr, _ICR(i2c));
drivers/i2c/busses/i2c-qcom-cci.c
143
writel(val, cci->base + CCI_IRQ_CLEAR_0);
drivers/i2c/busses/i2c-qcom-cci.c
144
writel(0x1, cci->base + CCI_IRQ_GLOBAL_CLEAR_CMD);
drivers/i2c/busses/i2c-qcom-cci.c
180
writel(reset, cci->base + CCI_RESET_CMD);
drivers/i2c/busses/i2c-qcom-cci.c
189
writel(CCI_HALT_REQ_I2C_M0_Q0Q1, cci->base + CCI_HALT_REQ);
drivers/i2c/busses/i2c-qcom-cci.c
200
writel(CCI_HALT_REQ_I2C_M1_Q0Q1, cci->base + CCI_HALT_REQ);
drivers/i2c/busses/i2c-qcom-cci.c
221
writel(val, cci->base + CCI_HALT_REQ);
drivers/i2c/busses/i2c-qcom-cci.c
238
writel(CCI_RESET_CMD_MASK, cci->base + CCI_RESET_CMD);
drivers/i2c/busses/i2c-qcom-cci.c
264
writel(val, cci->base + CCI_IRQ_MASK_0);
drivers/i2c/busses/i2c-qcom-cci.c
276
writel(val, cci->base + CCI_I2C_Mm_SCL_CTL(i));
drivers/i2c/busses/i2c-qcom-cci.c
279
writel(val, cci->base + CCI_I2C_Mm_SDA_CTL_0(i));
drivers/i2c/busses/i2c-qcom-cci.c
282
writel(val, cci->base + CCI_I2C_Mm_SDA_CTL_1(i));
drivers/i2c/busses/i2c-qcom-cci.c
285
writel(val, cci->base + CCI_I2C_Mm_SDA_CTL_2(i));
drivers/i2c/busses/i2c-qcom-cci.c
288
writel(val, cci->base + CCI_I2C_Mm_MISC_CTL(i));
drivers/i2c/busses/i2c-qcom-cci.c
299
writel(val, cci->base + CCI_I2C_Mm_Qn_EXEC_WORD_CNT(master, queue));
drivers/i2c/busses/i2c-qcom-cci.c
303
writel(val, cci->base + CCI_QUEUE_START);
drivers/i2c/busses/i2c-qcom-cci.c
329
writel(val, cci->base + CCI_I2C_Mm_Qn_LOAD_DATA(master, queue));
drivers/i2c/busses/i2c-qcom-cci.c
351
writel(val, cci->base + CCI_I2C_Mm_Qn_LOAD_DATA(master, queue));
drivers/i2c/busses/i2c-qcom-cci.c
354
writel(val, cci->base + CCI_I2C_Mm_Qn_LOAD_DATA(master, queue));
drivers/i2c/busses/i2c-qcom-cci.c
404
writel(val, cci->base + CCI_I2C_Mm_Qn_LOAD_DATA(master, queue));
drivers/i2c/busses/i2c-qcom-cci.c
416
writel(val, cci->base + CCI_I2C_Mm_Qn_LOAD_DATA(master, queue));
drivers/i2c/busses/i2c-qcom-cci.c
420
writel(val, cci->base + CCI_I2C_Mm_Qn_LOAD_DATA(master, queue));
drivers/i2c/busses/i2c-qup.c
1004
writel(0, qup->base + QUP_MX_READ_CNT);
drivers/i2c/busses/i2c-qup.c
1005
writel(blk->total_rx_len, qup->base + QUP_MX_INPUT_CNT);
drivers/i2c/busses/i2c-qup.c
1007
writel(0, qup->base + QUP_MX_INPUT_CNT);
drivers/i2c/busses/i2c-qup.c
1008
writel(blk->total_rx_len, qup->base + QUP_MX_READ_CNT);
drivers/i2c/busses/i2c-qup.c
1014
writel(qup_config, qup->base + QUP_CONFIG);
drivers/i2c/busses/i2c-qup.c
1015
writel(io_mode, qup->base + QUP_IO_MODE);
drivers/i2c/busses/i2c-qup.c
1036
writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL);
drivers/i2c/busses/i2c-qup.c
1105
writel(1, qup->base + QUP_SW_RESET);
drivers/i2c/busses/i2c-qup.c
1111
writel(I2C_MINI_CORE | I2C_N_VAL, qup->base + QUP_CONFIG);
drivers/i2c/busses/i2c-qup.c
1157
writel(qup->config_run | blk->total_tx_len,
drivers/i2c/busses/i2c-qup.c
1160
writel(qup->config_run | blk->total_tx_len,
drivers/i2c/busses/i2c-qup.c
1165
writel(qup->config_run | blk->total_rx_len,
drivers/i2c/busses/i2c-qup.c
1168
writel(qup->config_run | blk->total_rx_len,
drivers/i2c/busses/i2c-qup.c
1174
writel(qup_config, qup->base + QUP_CONFIG);
drivers/i2c/busses/i2c-qup.c
1189
writel(0, qup->base + QUP_MX_WRITE_CNT);
drivers/i2c/busses/i2c-qup.c
1191
writel(0, qup->base + QUP_MX_OUTPUT_CNT);
drivers/i2c/busses/i2c-qup.c
1196
writel(0, qup->base + QUP_MX_READ_CNT);
drivers/i2c/busses/i2c-qup.c
1198
writel(0, qup->base + QUP_MX_INPUT_CNT);
drivers/i2c/busses/i2c-qup.c
1201
writel(io_mode, qup->base + QUP_IO_MODE);
drivers/i2c/busses/i2c-qup.c
1292
writel(blk->tx_fifo_data,
drivers/i2c/busses/i2c-qup.c
1311
writel(blk->tx_fifo_data, qup->base + QUP_OUT_FIFO_BASE);
drivers/i2c/busses/i2c-qup.c
1363
writel(blk->tx_fifo_data, qup->base + QUP_OUT_FIFO_BASE);
drivers/i2c/busses/i2c-qup.c
1409
writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL);
drivers/i2c/busses/i2c-qup.c
1584
writel(1, qup->base + QUP_SW_RESET);
drivers/i2c/busses/i2c-qup.c
1590
writel(I2C_MINI_CORE | I2C_N_VAL_V2, qup->base + QUP_CONFIG);
drivers/i2c/busses/i2c-qup.c
1591
writel(QUP_V2_TAGS_EN, qup->base + QUP_I2C_MASTER_GEN);
drivers/i2c/busses/i2c-qup.c
1674
writel(config, qup->base + QUP_CONFIG);
drivers/i2c/busses/i2c-qup.c
1835
writel(1, qup->base + QUP_SW_RESET);
drivers/i2c/busses/i2c-qup.c
302
writel(QUP_RESET_STATE, qup->base + QUP_STATE);
drivers/i2c/busses/i2c-qup.c
311
writel(qup_err, qup->base + QUP_ERROR_FLAGS);
drivers/i2c/busses/i2c-qup.c
315
writel(bus_err, qup->base + QUP_I2C_STATUS);
drivers/i2c/busses/i2c-qup.c
334
writel(QUP_RESET_STATE, qup->base + QUP_STATE);
drivers/i2c/busses/i2c-qup.c
339
writel(QUP_OUT_SVC_FLAG, qup->base + QUP_OPERATIONAL);
drivers/i2c/busses/i2c-qup.c
351
writel(QUP_IN_SVC_FLAG, qup->base + QUP_OPERATIONAL);
drivers/i2c/busses/i2c-qup.c
417
writel(val, qup->base + QUP_STATE);
drivers/i2c/busses/i2c-qup.c
435
writel(state, qup->base + QUP_STATE);
drivers/i2c/busses/i2c-qup.c
514
writel(val, qup->base + QUP_OUT_FIFO_BASE);
drivers/i2c/busses/i2c-qup.c
878
writel(0, qup->base + QUP_MX_INPUT_CNT);
drivers/i2c/busses/i2c-qup.c
879
writel(0, qup->base + QUP_MX_OUTPUT_CNT);
drivers/i2c/busses/i2c-qup.c
882
writel(QUP_REPACK_EN | QUP_BAM_MODE, qup->base + QUP_IO_MODE);
drivers/i2c/busses/i2c-qup.c
885
writel((0x3 << 8), qup->base + QUP_OPERATIONAL_MASK);
drivers/i2c/busses/i2c-qup.c
892
writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL);
drivers/i2c/busses/i2c-qup.c
936
writel(1, qup->base + QUP_SW_RESET);
drivers/i2c/busses/i2c-qup.c
980
writel(val, qup->base + QUP_OUT_FIFO_BASE);
drivers/i2c/busses/i2c-qup.c
994
writel(0, qup->base + QUP_MX_WRITE_CNT);
drivers/i2c/busses/i2c-qup.c
995
writel(blk->total_tx_len, qup->base + QUP_MX_OUTPUT_CNT);
drivers/i2c/busses/i2c-qup.c
997
writel(0, qup->base + QUP_MX_OUTPUT_CNT);
drivers/i2c/busses/i2c-qup.c
998
writel(blk->total_tx_len, qup->base + QUP_MX_WRITE_CNT);
drivers/i2c/busses/i2c-rcar.c
179
writel(val, priv->io + reg);
drivers/i2c/busses/i2c-rcar.c
189
writel(~val & 0x7f, priv->io + ICMSR);
drivers/i2c/busses/i2c-rk3x.c
230
writel(value, i2c->regs + offset);
drivers/i2c/busses/i2c-rzv2m.c
162
writel(0, priv->base + IICB0CTL0);
drivers/i2c/busses/i2c-rzv2m.c
168
writel(i2c_ctl1, priv->base + IICB0CTL1);
drivers/i2c/busses/i2c-rzv2m.c
171
writel(priv->iicb0wl, priv->base + IICB0WL);
drivers/i2c/busses/i2c-rzv2m.c
172
writel(priv->iicb0wh, priv->base + IICB0WH);
drivers/i2c/busses/i2c-rzv2m.c
176
writel(i2c_ctl0, priv->base + IICB0CTL0);
drivers/i2c/busses/i2c-rzv2m.c
185
writel(data, priv->base + IICB0DAT);
drivers/i2c/busses/i2c-rzv2m.c
211
writel(IICB0WRET, priv->base + IICB0TRG);
drivers/i2c/busses/i2c-rzv2m.c
230
writel(IICB0WRET, priv->base + IICB0TRG);
drivers/i2c/busses/i2c-rzv2m.c
313
writel(IICB0SPT, priv->base + IICB0TRG);
drivers/i2c/busses/i2c-rzv2m.c
326
writel(IICB0STT, priv->base + IICB0TRG);
drivers/i2c/busses/i2c-rzv2m.c
80
writel(readl(addr) | val, addr);
drivers/i2c/busses/i2c-rzv2m.c
85
writel(readl(addr) & ~val, addr);
drivers/i2c/busses/i2c-s3c2410.c
186
writel(tmp & ~S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
drivers/i2c/busses/i2c-s3c2410.c
194
writel(tmp | S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
drivers/i2c/busses/i2c-s3c2410.c
203
writel(tmp & ~S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
drivers/i2c/busses/i2c-s3c2410.c
211
writel(tmp | S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
drivers/i2c/busses/i2c-s3c2410.c
266
writel(stat, i2c->regs + S3C2410_IICSTAT);
drivers/i2c/busses/i2c-s3c2410.c
278
writel(iiccon, i2c->regs + S3C2410_IICCON);
drivers/i2c/busses/i2c-s3c2410.c
281
writel(stat, i2c->regs + S3C2410_IICSTAT);
drivers/i2c/busses/i2c-s3c2410.c
331
writel(iicstat, i2c->regs + S3C2410_IICSTAT);
drivers/i2c/busses/i2c-s3c2410.c
543
writel(tmp, i2c->regs + S3C2410_IICCON);
drivers/i2c/busses/i2c-s3c2410.c
569
writel(tmp, i2c->regs + S3C2410_IICCON);
drivers/i2c/busses/i2c-s3c2410.c
599
writel(tmp, i2c->regs + S3C2410_IICSTAT);
drivers/i2c/busses/i2c-s3c2410.c
605
writel(tmp, i2c->regs + S3C2410_IICCON);
drivers/i2c/busses/i2c-s3c2410.c
879
writel(iiccon, i2c->regs + S3C2410_IICCON);
drivers/i2c/busses/i2c-s3c2410.c
895
writel(sda_delay, i2c->regs + S3C2440_IICLC);
drivers/i2c/busses/i2c-s3c2410.c
945
writel(0, i2c->regs + S3C2410_IICCON);
drivers/i2c/busses/i2c-s3c2410.c
946
writel(0, i2c->regs + S3C2410_IICSTAT);
drivers/i2c/busses/i2c-sprd.c
103
writel(tmp & ~STP_EN, i2c_dev->base + I2C_CTL);
drivers/i2c/busses/i2c-sprd.c
105
writel(tmp | STP_EN, i2c_dev->base + I2C_CTL);
drivers/i2c/busses/i2c-sprd.c
112
writel(tmp & ~I2C_START, i2c_dev->base + I2C_CTL);
drivers/i2c/busses/i2c-sprd.c
119
writel(tmp & ~I2C_RX_ACK, i2c_dev->base + I2C_STATUS);
drivers/i2c/busses/i2c-sprd.c
126
writel(tmp & ~I2C_INT, i2c_dev->base + I2C_STATUS);
drivers/i2c/busses/i2c-sprd.c
131
writel(I2C_RST, i2c_dev->base + ADDR_RST);
drivers/i2c/busses/i2c-sprd.c
136
writel(m->addr << 1, i2c_dev->base + I2C_ADDR_CFG);
drivers/i2c/busses/i2c-sprd.c
161
writel(tmp, i2c_dev->base + I2C_CTL);
drivers/i2c/busses/i2c-sprd.c
170
writel(tmp, i2c_dev->base + I2C_CTL);
drivers/i2c/busses/i2c-sprd.c
182
writel(tmp, i2c_dev->base + I2C_CTL);
drivers/i2c/busses/i2c-sprd.c
194
writel(tmp, i2c_dev->base + I2C_CTL);
drivers/i2c/busses/i2c-sprd.c
201
writel(tmp | I2C_START, i2c_dev->base + I2C_CTL);
drivers/i2c/busses/i2c-sprd.c
208
writel(cmd | rw << 3, i2c_dev->base + I2C_CTL);
drivers/i2c/busses/i2c-sprd.c
340
writel(div0, i2c_dev->base + ADDR_DVD0);
drivers/i2c/busses/i2c-sprd.c
341
writel(div1, i2c_dev->base + ADDR_DVD1);
drivers/i2c/busses/i2c-sprd.c
345
writel((6 * apb_clk) / 10000000, i2c_dev->base + ADDR_STA0_DVD);
drivers/i2c/busses/i2c-sprd.c
347
writel((4 * apb_clk) / 1000000, i2c_dev->base + ADDR_STA0_DVD);
drivers/i2c/busses/i2c-sprd.c
354
writel(tmp, i2c_dev->base + I2C_CTL);
drivers/i2c/busses/i2c-sprd.c
364
writel(tmp | I2C_EN | I2C_INT_EN, i2c_dev->base + I2C_CTL);
drivers/i2c/busses/i2c-sprd.c
95
writel(count, i2c_dev->base + I2C_COUNT);
drivers/i2c/busses/i2c-sun6i-p2wi.c
105
writel(status, p2wi->regs + P2WI_INTS);
drivers/i2c/busses/i2c-sun6i-p2wi.c
132
writel(command, p2wi->regs + P2WI_DADDR0);
drivers/i2c/busses/i2c-sun6i-p2wi.c
137
writel(data->byte, p2wi->regs + P2WI_DATA0);
drivers/i2c/busses/i2c-sun6i-p2wi.c
139
writel(dlen, p2wi->regs + P2WI_DLEN);
drivers/i2c/busses/i2c-sun6i-p2wi.c
148
writel(P2WI_INTS_LOAD_BSY | P2WI_INTS_TRANS_ERR | P2WI_INTS_TRANS_OVER,
drivers/i2c/busses/i2c-sun6i-p2wi.c
151
writel(P2WI_CTRL_START_TRANS | P2WI_CTRL_GLOBAL_INT_ENB,
drivers/i2c/busses/i2c-sun6i-p2wi.c
284
writel(P2WI_CTRL_SOFT_RST, p2wi->regs + P2WI_CTRL);
drivers/i2c/busses/i2c-sun6i-p2wi.c
299
writel(P2WI_CCR_SDA_OUT_DELAY(1) | P2WI_CCR_CLK_DIV(clk_div),
drivers/i2c/busses/i2c-tegra.c
421
writel(val, i2c_dev->base + reg);
drivers/i2c/busses/i2c-tegra.c
464
writel(0, i2c_dev->base + reg);
drivers/i2c/busses/i2c-uniphier-f.c
109
writel(*priv->buf++, priv->membase + UNIPHIER_FI2C_DTTX);
drivers/i2c/busses/i2c-uniphier-f.c
130
writel(priv->enabled_irqs, priv->membase + UNIPHIER_FI2C_IE);
drivers/i2c/busses/i2c-uniphier-f.c
136
writel(mask, priv->membase + UNIPHIER_FI2C_IC);
drivers/i2c/busses/i2c-uniphier-f.c
143
writel(UNIPHIER_FI2C_CR_MST | UNIPHIER_FI2C_CR_STO,
drivers/i2c/busses/i2c-uniphier-f.c
211
writel(UNIPHIER_FI2C_CR_MST |
drivers/i2c/busses/i2c-uniphier-f.c
254
writel(0, priv->membase + UNIPHIER_FI2C_TBC);
drivers/i2c/busses/i2c-uniphier-f.c
256
writel(UNIPHIER_FI2C_DTTX_CMD | addr << 1,
drivers/i2c/busses/i2c-uniphier-f.c
275
writel(priv->len, priv->membase + UNIPHIER_FI2C_RBC);
drivers/i2c/busses/i2c-uniphier-f.c
284
writel(0, priv->membase + UNIPHIER_FI2C_RBC);
drivers/i2c/busses/i2c-uniphier-f.c
292
writel(UNIPHIER_FI2C_DTTX_CMD | UNIPHIER_FI2C_DTTX_RD | addr << 1,
drivers/i2c/busses/i2c-uniphier-f.c
298
writel(UNIPHIER_FI2C_RST_RST, priv->membase + UNIPHIER_FI2C_RST);
drivers/i2c/busses/i2c-uniphier-f.c
303
writel(UNIPHIER_FI2C_BRST_FOEN | UNIPHIER_FI2C_BRST_RSCL,
drivers/i2c/busses/i2c-uniphier-f.c
331
writel(UNIPHIER_FI2C_RST_TBRST | UNIPHIER_FI2C_RST_RBRST,
drivers/i2c/busses/i2c-uniphier-f.c
347
writel(UNIPHIER_FI2C_CR_MST | UNIPHIER_FI2C_CR_STA,
drivers/i2c/busses/i2c-uniphier-f.c
451
writel(val ? UNIPHIER_FI2C_BRST_RSCL : 0,
drivers/i2c/busses/i2c-uniphier-f.c
483
writel(tmp, priv->membase + UNIPHIER_FI2C_CR);
drivers/i2c/busses/i2c-uniphier-f.c
491
writel(cyc, priv->membase + UNIPHIER_FI2C_CYC);
drivers/i2c/busses/i2c-uniphier-f.c
497
writel(cyc * 5 / 9, priv->membase + UNIPHIER_FI2C_LCTL);
drivers/i2c/busses/i2c-uniphier-f.c
502
writel(cyc / 2, priv->membase + UNIPHIER_FI2C_SSUT);
drivers/i2c/busses/i2c-uniphier-f.c
507
writel(cyc / 16, priv->membase + UNIPHIER_FI2C_DSUT);
drivers/i2c/busses/i2c-uniphier.c
250
writel(val, priv->membase + UNIPHIER_I2C_BRST);
drivers/i2c/busses/i2c-uniphier.c
265
writel(val ? UNIPHIER_I2C_BRST_RSCL : 0,
drivers/i2c/busses/i2c-uniphier.c
302
writel((cyc * 5 / 9 << 16) | cyc, priv->membase + UNIPHIER_I2C_CLK);
drivers/i2c/busses/i2c-uniphier.c
71
writel(txdata, priv->membase + UNIPHIER_I2C_DTRM);
drivers/i2c/busses/i2c-versatile.c
33
writel(SDA, i2c->base + (state ? I2C_CONTROLS : I2C_CONTROLC));
drivers/i2c/busses/i2c-versatile.c
40
writel(SCL, i2c->base + (state ? I2C_CONTROLS : I2C_CONTROLC));
drivers/i2c/busses/i2c-versatile.c
77
writel(SCL | SDA, i2c->base + I2C_CONTROLS);
drivers/i2c/busses/i2c-xlp9xx.c
104
writel(val, priv->base + reg);
drivers/i3c/master/adi-i3c-master.c
1000
writel(0x01, master->regs + REG_ENABLE);
drivers/i3c/master/adi-i3c-master.c
180
writel(0, master->regs + REG_IBI_CONFIG);
drivers/i3c/master/adi-i3c-master.c
223
writel(cmd->cmd0, master->regs + REG_CMD_FIFO);
drivers/i3c/master/adi-i3c-master.c
225
writel(cmd->cmd1, master->regs + REG_CMD_FIFO);
drivers/i3c/master/adi-i3c-master.c
309
writel(0x01, master->regs + REG_ENABLE);
drivers/i3c/master/adi-i3c-master.c
310
writel(0x00, master->regs + REG_ENABLE);
drivers/i3c/master/adi-i3c-master.c
311
writel(REG_IRQ_PENDING_CMDR, master->regs + REG_IRQ_MASK);
drivers/i3c/master/adi-i3c-master.c
441
writel(REG_DEV_CHAR_ADDR(dyn_addr), master->regs + REG_DEV_CHAR);
drivers/i3c/master/adi-i3c-master.c
442
writel((readl(master->regs + REG_DEV_CHAR) &
drivers/i3c/master/adi-i3c-master.c
446
writel(REG_DEV_CHAR_ADDR(addr), master->regs + REG_DEV_CHAR);
drivers/i3c/master/adi-i3c-master.c
447
writel(readl(master->regs + REG_DEV_CHAR) |
drivers/i3c/master/adi-i3c-master.c
478
writel(REG_DEV_CHAR_ADDR(addr), master->regs + REG_DEV_CHAR);
drivers/i3c/master/adi-i3c-master.c
479
writel(readl(master->regs + REG_DEV_CHAR) |
drivers/i3c/master/adi-i3c-master.c
496
writel(REG_DEV_CHAR_ADDR(addr), master->regs + REG_DEV_CHAR);
drivers/i3c/master/adi-i3c-master.c
498
writel(readl(master->regs + REG_DEV_CHAR) |
drivers/i3c/master/adi-i3c-master.c
513
writel(REG_DEV_CHAR_ADDR(addr), master->regs + REG_DEV_CHAR);
drivers/i3c/master/adi-i3c-master.c
514
writel((readl(master->regs + REG_DEV_CHAR) &
drivers/i3c/master/adi-i3c-master.c
542
writel(REG_DEV_CHAR_ADDR(dev->addr) |
drivers/i3c/master/adi-i3c-master.c
555
writel(REG_DEV_CHAR_ADDR(dev->addr) |
drivers/i3c/master/adi-i3c-master.c
617
writel(pp_sg, master->regs + REG_OPS);
drivers/i3c/master/adi-i3c-master.c
650
writel(irq_mask | REG_IRQ_PENDING_DAA,
drivers/i3c/master/adi-i3c-master.c
656
writel(irq_mask, master->regs + REG_IRQ_MASK);
drivers/i3c/master/adi-i3c-master.c
690
writel(REG_IBI_CONFIG_LISTEN,
drivers/i3c/master/adi-i3c-master.c
749
writel(addr, master->regs + REG_SDO_FIFO);
drivers/i3c/master/adi-i3c-master.c
758
writel(pending, master->regs + REG_IRQ_PENDING);
drivers/i3c/master/adi-i3c-master.c
832
writel(REG_IBI_CONFIG_LISTEN,
drivers/i3c/master/adi-i3c-master.c
834
writel(readl(master->regs + REG_IRQ_MASK) & ~REG_IRQ_PENDING_IBI,
drivers/i3c/master/adi-i3c-master.c
846
writel(REG_IBI_CONFIG_LISTEN | REG_IBI_CONFIG_ENABLE,
drivers/i3c/master/adi-i3c-master.c
849
writel(readl(master->regs + REG_IRQ_MASK) | REG_IRQ_PENDING_IBI,
drivers/i3c/master/adi-i3c-master.c
965
writel(0x00, master->regs + REG_ENABLE);
drivers/i3c/master/adi-i3c-master.c
966
writel(0x00, master->regs + REG_IRQ_MASK);
drivers/i3c/master/adi-i3c-master.c
977
writel(REG_IRQ_PENDING_CMDR, master->regs + REG_IRQ_MASK);
drivers/i3c/master/adi-i3c-master.c
998
writel(0xff, master->regs + REG_IRQ_PENDING);
drivers/i3c/master/adi-i3c-master.c
999
writel(0x00, master->regs + REG_IRQ_MASK);
drivers/i3c/master/dw-i3c-master.c
1015
writel(0,
drivers/i3c/master/dw-i3c-master.c
1027
writel(DEV_ADDR_TABLE_DYNAMIC_ADDR(dev->info.dyn_addr) | DEV_ADDR_TABLE_SIR_REJECT,
drivers/i3c/master/dw-i3c-master.c
1056
writel(DEV_ADDR_TABLE_DYNAMIC_ADDR(master->devs[pos].addr) | DEV_ADDR_TABLE_SIR_REJECT,
drivers/i3c/master/dw-i3c-master.c
1069
writel(0,
drivers/i3c/master/dw-i3c-master.c
1175
writel(DEV_ADDR_TABLE_LEGACY_I2C_DEV |
drivers/i3c/master/dw-i3c-master.c
1189
writel(0,
drivers/i3c/master/dw-i3c-master.c
1238
writel(reg, master->regs + INTR_STATUS_EN);
drivers/i3c/master/dw-i3c-master.c
1244
writel(reg, master->regs + INTR_SIGNAL_EN);
drivers/i3c/master/dw-i3c-master.c
1274
writel(reg, master->regs + dat_entry);
drivers/i3c/master/dw-i3c-master.c
1285
writel(master->sir_rej_mask, master->regs + IBI_SIR_REQ_REJECT);
drivers/i3c/master/dw-i3c-master.c
1305
writel(readl(master->regs + DEVICE_CTRL) & ~DEV_CTRL_HOT_JOIN_NACK,
drivers/i3c/master/dw-i3c-master.c
1315
writel(readl(master->regs + DEVICE_CTRL) | DEV_CTRL_HOT_JOIN_NACK,
drivers/i3c/master/dw-i3c-master.c
1487
writel(INTR_ALL, master->regs + INTR_STATUS);
drivers/i3c/master/dw-i3c-master.c
1494
writel(INTR_TRANSFER_ERR_STAT, master->regs + INTR_STATUS);
drivers/i3c/master/dw-i3c-master.c
1530
writel(reg, master->regs +
drivers/i3c/master/dw-i3c-master.c
1621
writel(INTR_ALL, master->regs + INTR_STATUS);
drivers/i3c/master/dw-i3c-master.c
1722
writel(DEV_ADDR_DYNAMIC_ADDR_VALID | DEV_ADDR_DYNAMIC(master->dev_addr),
drivers/i3c/master/dw-i3c-master.c
1740
writel(reg_val, master->regs + DEV_ADDR_TABLE_LOC(master->datstartaddr, pos));
drivers/i3c/master/dw-i3c-master.c
1750
writel(master->i3c_pp_timing, master->regs + SCL_I3C_PP_TIMING);
drivers/i3c/master/dw-i3c-master.c
1751
writel(master->bus_free_timing, master->regs + BUS_FREE_TIMING);
drivers/i3c/master/dw-i3c-master.c
1752
writel(master->i3c_od_timing, master->regs + SCL_I3C_OD_TIMING);
drivers/i3c/master/dw-i3c-master.c
1753
writel(master->ext_lcnt_timing, master->regs + SCL_EXT_LCNT_TIMING);
drivers/i3c/master/dw-i3c-master.c
1756
writel(master->i2c_fmp_timing, master->regs + SCL_I2C_FMP_TIMING);
drivers/i3c/master/dw-i3c-master.c
1757
writel(master->i2c_fm_timing, master->regs + SCL_I2C_FM_TIMING);
drivers/i3c/master/dw-i3c-master.c
1833
writel((u32)~INTR_ALL, master->regs + INTR_STATUS_EN);
drivers/i3c/master/dw-i3c-master.c
1834
writel((u32)~INTR_ALL, master->regs + INTR_SIGNAL_EN);
drivers/i3c/master/dw-i3c-master.c
325
writel(readl(master->regs + DEVICE_CTRL) & ~DEV_CTRL_ENABLE,
drivers/i3c/master/dw-i3c-master.c
338
writel(dev_ctrl | DEV_CTRL_ENABLE,
drivers/i3c/master/dw-i3c-master.c
419
writel(thld_ctrl, master->regs + QUEUE_THLD_CTRL);
drivers/i3c/master/dw-i3c-master.c
424
writel(cmd->cmd_hi, master->regs + COMMAND_QUEUE_PORT);
drivers/i3c/master/dw-i3c-master.c
425
writel(cmd->cmd_lo, master->regs + COMMAND_QUEUE_PORT);
drivers/i3c/master/dw-i3c-master.c
450
writel(RESET_CTRL_RX_FIFO | RESET_CTRL_TX_FIFO |
drivers/i3c/master/dw-i3c-master.c
521
writel(readl(master->regs + DEVICE_CTRL) | DEV_CTRL_RESUME,
drivers/i3c/master/dw-i3c-master.c
545
writel(thld_ctrl, master->regs + QUEUE_THLD_CTRL);
drivers/i3c/master/dw-i3c-master.c
549
writel(thld_ctrl, master->regs + DATA_BUFFER_THLD_CTRL);
drivers/i3c/master/dw-i3c-master.c
551
writel(INTR_ALL, master->regs + INTR_STATUS);
drivers/i3c/master/dw-i3c-master.c
552
writel(INTR_MASTER_MASK, master->regs + INTR_STATUS_EN);
drivers/i3c/master/dw-i3c-master.c
553
writel(INTR_MASTER_MASK, master->regs + INTR_SIGNAL_EN);
drivers/i3c/master/dw-i3c-master.c
556
writel(master->sir_rej_mask, master->regs + IBI_SIR_REQ_REJECT);
drivers/i3c/master/dw-i3c-master.c
558
writel(IBI_REQ_REJECT_ALL, master->regs + IBI_MR_REQ_REJECT);
drivers/i3c/master/dw-i3c-master.c
582
writel(scl_timing, master->regs + SCL_I3C_PP_TIMING);
drivers/i3c/master/dw-i3c-master.c
590
writel(BUS_I3C_MST_FREE(lcnt), master->regs + BUS_FREE_TIMING);
drivers/i3c/master/dw-i3c-master.c
597
writel(scl_timing, master->regs + SCL_I3C_OD_TIMING);
drivers/i3c/master/dw-i3c-master.c
608
writel(scl_timing, master->regs + SCL_EXT_LCNT_TIMING);
drivers/i3c/master/dw-i3c-master.c
630
writel(scl_timing, master->regs + SCL_I2C_FMP_TIMING);
drivers/i3c/master/dw-i3c-master.c
637
writel(scl_timing, master->regs + SCL_I2C_FM_TIMING);
drivers/i3c/master/dw-i3c-master.c
640
writel(BUS_I3C_MST_FREE(lcnt), master->regs + BUS_FREE_TIMING);
drivers/i3c/master/dw-i3c-master.c
643
writel(readl(master->regs + DEVICE_CTRL) | DEV_CTRL_I2C_SLAVE_PRESENT,
drivers/i3c/master/dw-i3c-master.c
690
writel(DEV_ADDR_DYNAMIC_ADDR_VALID | DEV_ADDR_DYNAMIC(ret),
drivers/i3c/master/dw-i3c-master.c
816
writel(master->i3c_pp_timing, master->regs + SCL_I3C_PP_TIMING);
drivers/i3c/master/dw-i3c-master.c
817
writel(master->i3c_od_timing, master->regs + SCL_I3C_OD_TIMING);
drivers/i3c/master/dw-i3c-master.c
872
writel(DEV_ADDR_TABLE_DYNAMIC_ADDR(ret),
drivers/i3c/master/i3c-master-cdns.c
1002
writel(prepare_rr0_dev_address(dev->addr),
drivers/i3c/master/i3c-master-cdns.c
1004
writel(dev->lvr, master->regs + DEV_ID_RR2(data->id));
drivers/i3c/master/i3c-master-cdns.c
1005
writel(readl(master->regs + DEVS_CTRL) |
drivers/i3c/master/i3c-master-cdns.c
1018
writel(readl(master->regs + DEVS_CTRL) |
drivers/i3c/master/i3c-master-cdns.c
1114
writel(prescl1, master->regs + PRESCL_CTRL1);
drivers/i3c/master/i3c-master-cdns.c
1139
writel(prepare_rr0_dev_address(last_addr) | DEV_ID_RR0_IS_I3C,
drivers/i3c/master/i3c-master-cdns.c
1141
writel(0, master->regs + DEV_ID_RR1(slot));
drivers/i3c/master/i3c-master-cdns.c
1142
writel(0, master->regs + DEV_ID_RR2(slot));
drivers/i3c/master/i3c-master-cdns.c
1165
writel(readl(master->regs + DEVS_CTRL) |
drivers/i3c/master/i3c-master-cdns.c
1244
writel(prescl0, master->regs + PRESCL_CTRL0);
drivers/i3c/master/i3c-master-cdns.c
1252
writel(prescl1, master->regs + PRESCL_CTRL1);
drivers/i3c/master/i3c-master-cdns.c
1259
writel(prepare_rr0_dev_address(ret) | DEV_ID_RR0_IS_I3C,
drivers/i3c/master/i3c-master-cdns.c
1286
writel(ctrl, master->regs + CTRL);
drivers/i3c/master/i3c-master-cdns.c
1346
writel(MST_INT_IBIR_THR, master->regs + MST_ICR);
drivers/i3c/master/i3c-master-cdns.c
1411
writel(sirmap, master->regs + SIR_MAP_DEV_REG(data->ibi));
drivers/i3c/master/i3c-master-cdns.c
1438
writel(sirmap, master->regs + SIR_MAP_DEV_REG(data->ibi));
drivers/i3c/master/i3c-master-cdns.c
1449
writel(sirmap, master->regs + SIR_MAP_DEV_REG(data->ibi));
drivers/i3c/master/i3c-master-cdns.c
1588
writel(0xffffffff, master->regs + MST_IDR);
drivers/i3c/master/i3c-master-cdns.c
1589
writel(0xffffffff, master->regs + SLV_IDR);
drivers/i3c/master/i3c-master-cdns.c
1618
writel(IBIR_THR(1), master->regs + CMD_IBI_THR_CTRL);
drivers/i3c/master/i3c-master-cdns.c
1619
writel(MST_INT_IBIR_THR, master->regs + MST_IER);
drivers/i3c/master/i3c-master-cdns.c
1620
writel(DEVS_CTRL_DEV_CLR_ALL, master->regs + DEVS_CTRL);
drivers/i3c/master/i3c-master-cdns.c
485
writel(readl(master->regs + CTRL) & ~CTRL_DEV_EN, master->regs + CTRL);
drivers/i3c/master/i3c-master-cdns.c
493
writel(readl(master->regs + CTRL) | CTRL_DEV_EN, master->regs + CTRL);
drivers/i3c/master/i3c-master-cdns.c
525
writel(MST_INT_CMDD_EMP, master->regs + MST_ICR);
drivers/i3c/master/i3c-master-cdns.c
536
writel(cmd->cmd1 | CMD1_FIFO_CMDID(i),
drivers/i3c/master/i3c-master-cdns.c
538
writel(cmd->cmd0, master->regs + CMD0_FIFO);
drivers/i3c/master/i3c-master-cdns.c
541
writel(readl(master->regs + CTRL) | CTRL_MCS,
drivers/i3c/master/i3c-master-cdns.c
543
writel(MST_INT_CMDD_EMP, master->regs + MST_IER);
drivers/i3c/master/i3c-master-cdns.c
559
writel(MST_INT_CMDD_EMP, master->regs + MST_IDR);
drivers/i3c/master/i3c-master-cdns.c
645
writel(readl(master->regs + CTRL) & ~CTRL_DEV_EN,
drivers/i3c/master/i3c-master-cdns.c
651
writel(FLUSH_RX_FIFO | FLUSH_TX_FIFO | FLUSH_CMD_FIFO |
drivers/i3c/master/i3c-master-cdns.c
654
writel(MST_INT_CMDD_EMP, master->regs + MST_IDR);
drivers/i3c/master/i3c-master-cdns.c
655
writel(readl(master->regs + CTRL) | CTRL_DEV_EN,
drivers/i3c/master/i3c-master-cdns.c
896
writel(DEV_ID_RR0_IS_I3C | rr, master->regs + DEV_ID_RR0(data->id));
drivers/i3c/master/i3c-master-cdns.c
960
writel(readl(master->regs + DEVS_CTRL) |
drivers/i3c/master/i3c-master-cdns.c
974
writel(readl(master->regs + DEVS_CTRL) |
drivers/i3c/master/mipi-i3c-hci/dat_v1.c
187
writel(hci->DAT[i].w0, hci->DAT_regs + i * 8);
drivers/i3c/master/mipi-i3c-hci/dat_v1.c
188
writel(hci->DAT[i].w1, hci->DAT_regs + i * 8 + 4);
drivers/i3c/master/mipi-i3c-hci/dat_v1.c
45
writel(v, hci->DAT_regs + i * 8);
drivers/i3c/master/mipi-i3c-hci/dat_v1.c
51
writel(v, hci->DAT_regs + i * 8 + 4);
drivers/i3c/master/mipi-i3c-hci/dma.c
41
#define rhs_reg_write(r, v) writel(v, hci->RHS_regs + (RHS_##r))
drivers/i3c/master/mipi-i3c-hci/dma.c
56
#define rh_reg_write(r, v) writel(v, rh->regs + (RH_##r))
drivers/i3c/master/mipi-i3c-hci/ext_caps.c
206
writel(0xdeadbeef, base + 1*4);
drivers/i3c/master/mipi-i3c-hci/hci.h
28
#define reg_write(r, v) writel(v, hci->base_regs + (r))
drivers/i3c/master/mipi-i3c-hci/mipi-i3c-hci-pci.c
106
writel(ltr, host->priv + INTEL_ACTIVELTR);
drivers/i3c/master/mipi-i3c-hci/mipi-i3c-hci-pci.c
107
writel(ltr, host->priv + INTEL_IDLELTR);
drivers/i3c/master/mipi-i3c-hci/mipi-i3c-hci-pci.c
149
writel(0, priv + INTEL_RESETS);
drivers/i3c/master/mipi-i3c-hci/mipi-i3c-hci-pci.c
153
writel(INTEL_RESETS_RESET, priv + INTEL_RESETS);
drivers/i3c/master/mipi-i3c-hci/pio.c
23
#define pio_reg_write(r, v) writel(v, hci->PIO_regs + (PIO_##r))
drivers/i3c/master/renesas-i3c.c
290
writel(data, reg);
drivers/i3c/master/renesas-i3c.c
300
writel(val, base + reg);
drivers/i3c/master/svc-i3c-master.c
1013
writel(SVC_I3C_MINT_IBIWON, master->regs + SVC_I3C_MSTATUS);
drivers/i3c/master/svc-i3c-master.c
1029
writel(SVC_I3C_MCTRL_REQUEST_PROC_DAA |
drivers/i3c/master/svc-i3c-master.c
1068
writel(dyn_addr, master->regs + SVC_I3C_MWDATAB);
drivers/i3c/master/svc-i3c-master.c
1208
writel(reg_mbyte, master->regs + SVC_I3C_IBIRULES);
drivers/i3c/master/svc-i3c-master.c
1210
writel(reg_nobyte, master->regs + SVC_I3C_IBIRULES);
drivers/i3c/master/svc-i3c-master.c
1232
writel(master->mctrl_config | SVC_I3C_MCONFIG_SKEW(1),
drivers/i3c/master/svc-i3c-master.c
1238
writel(master->mctrl_config, master->regs + SVC_I3C_MCONFIG);
drivers/i3c/master/svc-i3c-master.c
1332
writel(out[offset++], master->regs + SVC_I3C_MWDATAB);
drivers/i3c/master/svc-i3c-master.c
1334
writel(out[offset++], master->regs + SVC_I3C_MWDATABE);
drivers/i3c/master/svc-i3c-master.c
1351
writel(SVC_I3C_MINT_IBIWON, master->regs + SVC_I3C_MSTATUS);
drivers/i3c/master/svc-i3c-master.c
1355
writel(rnw_cmd, master->regs + SVC_I3C_MWDATAB);
drivers/i3c/master/svc-i3c-master.c
1365
writel(SVC_I3C_MCTRL_REQUEST_START_ADDR |
drivers/i3c/master/svc-i3c-master.c
1390
writel(out[len - 1] | end, master->regs + SVC_I3C_MWDATAB);
drivers/i3c/master/svc-i3c-master.c
1443
writel(SVC_I3C_MERRWARN_NACK, master->regs + SVC_I3C_MERRWARN);
drivers/i3c/master/svc-i3c-master.c
1475
writel(SVC_I3C_MINT_COMPLETE, master->regs + SVC_I3C_MSTATUS);
drivers/i3c/master/svc-i3c-master.c
2101
writel(master->saved_regs.mconfig,
drivers/i3c/master/svc-i3c-master.c
2103
writel(master->saved_regs.mdynaddr,
drivers/i3c/master/svc-i3c-master.c
298
writel(merrwarn, master->regs + SVC_I3C_MERRWARN);
drivers/i3c/master/svc-i3c-master.c
319
writel(mask, master->regs + SVC_I3C_MINTSET);
drivers/i3c/master/svc-i3c-master.c
326
writel(mask, master->regs + SVC_I3C_MINTCLR);
drivers/i3c/master/svc-i3c-master.c
332
writel(readl(master->regs + SVC_I3C_MERRWARN),
drivers/i3c/master/svc-i3c-master.c
339
writel(SVC_I3C_MDATACTRL_FLUSHTB | SVC_I3C_MDATACTRL_FLUSHRB,
drivers/i3c/master/svc-i3c-master.c
353
writel(reg, master->regs + SVC_I3C_MDATACTRL);
drivers/i3c/master/svc-i3c-master.c
402
writel(SVC_I3C_MCTRL_REQUEST_FORCE_EXIT, master->regs + SVC_I3C_MCTRL);
drivers/i3c/master/svc-i3c-master.c
425
writel(SVC_I3C_MCTRL_REQUEST_STOP, master->regs + SVC_I3C_MCTRL);
drivers/i3c/master/svc-i3c-master.c
460
writel(SVC_I3C_MDATACTRL_FLUSHRB, master->regs + SVC_I3C_MDATACTRL);
drivers/i3c/master/svc-i3c-master.c
493
writel(ibi_ack_nack, master->regs + SVC_I3C_MCTRL);
drivers/i3c/master/svc-i3c-master.c
505
writel(SVC_I3C_MCTRL_REQUEST_IBI_ACKNACK |
drivers/i3c/master/svc-i3c-master.c
521
writel(SVC_I3C_MINT_IBIWON, master->regs + SVC_I3C_MSTATUS);
drivers/i3c/master/svc-i3c-master.c
562
writel(SVC_I3C_MINT_IBIWON, master->regs + SVC_I3C_MSTATUS);
drivers/i3c/master/svc-i3c-master.c
577
writel(SVC_I3C_MCTRL_REQUEST_START_ADDR |
drivers/i3c/master/svc-i3c-master.c
673
writel(SVC_I3C_MINT_SLVSTART, master->regs + SVC_I3C_MSTATUS);
drivers/i3c/master/svc-i3c-master.c
724
writel(mconfig, master->regs + SVC_I3C_MCONFIG);
drivers/i3c/master/svc-i3c-master.c
727
writel(master->mctrl_config, master->regs + SVC_I3C_MCONFIG);
drivers/i3c/master/svc-i3c-master.c
828
writel(reg, master->regs + SVC_I3C_MCONFIG);
drivers/i3c/master/svc-i3c-master.c
840
writel(SVC_MDYNADDR_VALID | SVC_MDYNADDR_ADDR(info.dyn_addr),
drivers/i3c/master/svc-i3c-master.c
867
writel(0, master->regs + SVC_I3C_MCONFIG);
drivers/iio/adc/aspeed_adc.c
211
writel(trimming_val, data->base + ASPEED_REG_COMPENSATION_TRIM);
drivers/iio/adc/aspeed_adc.c
235
writel(adc_engine_control_reg_val | ASPEED_ADC_CTRL_COMPENSATION |
drivers/iio/adc/aspeed_adc.c
254
writel(adc_engine_control_reg_val,
drivers/iio/adc/aspeed_adc.c
291
writel(adc_engine_control_reg_val |
drivers/iio/adc/aspeed_adc.c
305
writel(adc_engine_control_reg_val,
drivers/iio/adc/aspeed_adc.c
402
writel(FIELD_PREP(ASPEED_ADC_OP_MODE, ASPEED_ADC_OP_MODE_PWR_DOWN),
drivers/iio/adc/aspeed_adc.c
428
writel(adc_engine_control_reg_val |
drivers/iio/adc/aspeed_adc.c
434
writel(adc_engine_control_reg_val |
drivers/iio/adc/aspeed_adc.c
452
writel(adc_engine_control_reg_val |
drivers/iio/adc/aspeed_adc.c
457
writel(adc_engine_control_reg_val |
drivers/iio/adc/aspeed_adc.c
591
writel(adc_engine_control_reg_val,
drivers/iio/adc/aspeed_adc.c
615
writel(adc_engine_control_reg_val,
drivers/iio/adc/cc10001_adc.c
69
writel(val, adc_dev->reg_base + reg);
drivers/iio/adc/exynos_adc.c
210
writel(con1, ADC_V1_CON(info->regs));
drivers/iio/adc/exynos_adc.c
213
writel(10000, ADC_V1_DLY(info->regs));
drivers/iio/adc/exynos_adc.c
225
writel(con, ADC_V1_CON(info->regs));
drivers/iio/adc/exynos_adc.c
230
writel(1, ADC_V1_INTCLR(info->regs));
drivers/iio/adc/exynos_adc.c
238
writel(addr, ADC_V1_MUX(info->regs));
drivers/iio/adc/exynos_adc.c
241
writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info->regs));
drivers/iio/adc/exynos_adc.c
287
writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info->regs));
drivers/iio/adc/exynos_adc.c
308
writel(con1, ADC_V2_CON1(info->regs));
drivers/iio/adc/exynos_adc.c
312
writel(con2, ADC_V2_CON2(info->regs));
drivers/iio/adc/exynos_adc.c
315
writel(1, ADC_V2_INT_EN(info->regs));
drivers/iio/adc/exynos_adc.c
327
writel(con, ADC_V2_CON1(info->regs));
drivers/iio/adc/exynos_adc.c
332
writel(1, ADC_V2_INT_ST(info->regs));
drivers/iio/adc/exynos_adc.c
343
writel(con2, ADC_V2_CON2(info->regs));
drivers/iio/adc/exynos_adc.c
346
writel(con1 | ADC_CON_EN_START, ADC_V2_CON1(info->regs));
drivers/iio/adc/exynos_adc.c
379
writel(con1, ADC_V2_CON1(info->regs));
drivers/iio/adc/exynos_adc.c
384
writel(con2, ADC_V2_CON2(info->regs));
drivers/iio/adc/exynos_adc.c
387
writel(1, ADC_V2_INT_EN(info->regs));
drivers/iio/adc/imx7d_adc.c
202
writel(tmp_cfg1,
drivers/iio/adc/imx7d_adc.c
211
writel(sample_rate, info->regs + IMX7D_REG_ADC_TIMER_UNIT);
drivers/iio/adc/imx7d_adc.c
223
writel(cfg, info->regs + IMX7D_REG_ADC_ADC_CFG);
drivers/iio/adc/imx7d_adc.c
226
writel(IMX7D_REG_ADC_INT_CHANNEL_INT_EN,
drivers/iio/adc/imx7d_adc.c
228
writel(IMX7D_REG_ADC_INT_CHANNEL_INT_EN,
drivers/iio/adc/imx7d_adc.c
268
writel(cfg2, info->regs + IMX7D_EACH_CHANNEL_REG_OFFSET * channel +
drivers/iio/adc/imx7d_adc.c
270
writel(cfg1, info->regs + IMX7D_EACH_CHANNEL_REG_OFFSET * channel);
drivers/iio/adc/imx7d_adc.c
377
writel(status, info->regs + IMX7D_REG_ADC_INT_STATUS);
drivers/iio/adc/imx7d_adc.c
389
writel(status, info->regs + IMX7D_REG_ADC_INT_STATUS);
drivers/iio/adc/imx7d_adc.c
428
writel(adc_cfg, info->regs + IMX7D_REG_ADC_ADC_CFG);
drivers/iio/adc/imx8qxp-adc.c
130
writel(ctrl, adc->regs + IMX8QXP_ADR_ADC_CTRL);
drivers/iio/adc/imx8qxp-adc.c
133
writel(ctrl, adc->regs + IMX8QXP_ADR_ADC_CTRL);
drivers/iio/adc/imx8qxp-adc.c
137
writel(ctrl, adc->regs + IMX8QXP_ADR_ADC_CTRL);
drivers/iio/adc/imx8qxp-adc.c
150
writel(adc_cfg, adc->regs + IMX8QXP_ADR_ADC_CFG);
drivers/iio/adc/imx8qxp-adc.c
157
writel(adc_tctrl, adc->regs + IMX8QXP_ADR_ADC_TCTRL(0));
drivers/iio/adc/imx8qxp-adc.c
165
writel(adc_cmdl, adc->regs + IMX8QXP_ADR_ADC_CMDL(0));
drivers/iio/adc/imx8qxp-adc.c
173
writel(adc_cmdh, adc->regs + IMX8QXP_ADR_ADC_CMDH(0));
drivers/iio/adc/imx8qxp-adc.c
184
writel(fifo_ctrl, adc->regs + IMX8QXP_ADR_ADC_FCTRL);
drivers/iio/adc/imx8qxp-adc.c
189
writel(interrupt_en, adc->regs + IMX8QXP_ADR_ADC_IE);
drivers/iio/adc/imx8qxp-adc.c
198
writel(ctrl, adc->regs + IMX8QXP_ADR_ADC_CTRL);
drivers/iio/adc/imx8qxp-adc.c
225
writel(ctrl, adc->regs + IMX8QXP_ADR_ADC_CTRL);
drivers/iio/adc/imx8qxp-adc.c
227
writel(1, adc->regs + IMX8QXP_ADR_ADC_SWTRIG);
drivers/iio/adc/imx93_adc.c
112
writel(mcr, adc->regs + IMX93_ADC_MCR);
drivers/iio/adc/imx93_adc.c
131
writel(mcr, adc->regs + IMX93_ADC_MCR);
drivers/iio/adc/imx93_adc.c
144
writel(mcr, adc->regs + IMX93_ADC_MCR);
drivers/iio/adc/imx93_adc.c
160
writel(mcr, adc->regs + IMX93_ADC_MCR);
drivers/iio/adc/imx93_adc.c
167
writel(calcfg, adc->regs + IMX93_ADC_CALCFG0);
drivers/iio/adc/imx93_adc.c
177
writel(mcr, adc->regs + IMX93_ADC_MCR);
drivers/iio/adc/imx93_adc.c
215
writel(channel, adc->regs + IMX93_ADC_NCMR0);
drivers/iio/adc/imx93_adc.c
221
writel(imr, adc->regs + IMX93_ADC_IMR);
drivers/iio/adc/imx93_adc.c
222
writel(channel, adc->regs + IMX93_ADC_CIMR0);
drivers/iio/adc/imx93_adc.c
227
writel(mcr, adc->regs + IMX93_ADC_MCR);
drivers/iio/adc/imx93_adc.c
232
writel(mcr, adc->regs + IMX93_ADC_MCR);
drivers/iio/adc/imx93_adc.c
295
writel(eoc, adc->regs + IMX93_ADC_ISR);
drivers/iio/adc/imx93_adc.c
301
writel(unexpected, adc->regs + IMX93_ADC_ISR);
drivers/iio/adc/ingenic-adc.c
125
writel(JZ_ADC_REG_ADCMD_XNGRU
drivers/iio/adc/ingenic-adc.c
131
writel(JZ_ADC_REG_ADCMD_YNGRU
drivers/iio/adc/ingenic-adc.c
139
writel(JZ_ADC_REG_ADCMD_XNGRU
drivers/iio/adc/ingenic-adc.c
145
writel(JZ_ADC_REG_ADCMD_YNGRU
drivers/iio/adc/ingenic-adc.c
153
writel(JZ_ADC_REG_ADCMD_VREFNYN | JZ_ADC_REG_ADCMD_VREFPVDD33
drivers/iio/adc/ingenic-adc.c
158
writel(JZ_ADC_REG_ADCMD_VREFNXN | JZ_ADC_REG_ADCMD_VREFPVDD33
drivers/iio/adc/ingenic-adc.c
164
writel(0, adc->base + JZ_ADC_REG_ADCMD);
drivers/iio/adc/ingenic-adc.c
179
writel(cfg, adc->base + JZ_ADC_REG_CFG);
drivers/iio/adc/ingenic-adc.c
223
writel(cfg & ~JZ_ADC_REG_CFG_CMD_SEL, adc->base + JZ_ADC_REG_CFG);
drivers/iio/adc/ingenic-adc.c
231
writel(cfg, adc->base + JZ_ADC_REG_CFG);
drivers/iio/adc/ingenic-adc.c
343
writel(((div_10us - 1) << JZ4725B_ADC_REG_ADCLK_CLKDIV10US_LSB) |
drivers/iio/adc/ingenic-adc.c
380
writel(((div_ms - 1) << JZ4770_ADC_REG_ADCLK_CLKDIVMS_LSB) |
drivers/iio/adc/ingenic-adc.c
765
writel(0, adc->base + JZ_ADC_REG_ADTCH);
drivers/iio/adc/lpc18xx_adc.c
121
writel(0, adc->base + LPC18XX_ADC_CR);
drivers/iio/adc/lpc18xx_adc.c
180
writel(adc->cr_reg, adc->base + LPC18XX_ADC_CR);
drivers/iio/adc/lpc18xx_adc.c
75
writel(reg, adc->base + LPC18XX_ADC_CR);
drivers/iio/adc/men_z188_adc.c
90
writel(ctl, addr + Z188_CTRL_REG);
drivers/iio/adc/men_z188_adc.c
96
writel(cfg, addr + i);
drivers/iio/adc/mt6577_auxadc.c
107
writel(val, reg);
drivers/iio/adc/mxs-lradc-adc.c
155
writel(LRADC_CTRL1_LRADC_IRQ_EN(0),
drivers/iio/adc/mxs-lradc-adc.c
157
writel(0x1, adc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR);
drivers/iio/adc/mxs-lradc-adc.c
161
writel(1 << LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET,
drivers/iio/adc/mxs-lradc-adc.c
164
writel(1 << LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET,
drivers/iio/adc/mxs-lradc-adc.c
168
writel(LRADC_CTRL4_LRADCSELECT_MASK(0),
drivers/iio/adc/mxs-lradc-adc.c
170
writel(chan, adc->base + LRADC_CTRL4 + STMP_OFFSET_REG_SET);
drivers/iio/adc/mxs-lradc-adc.c
172
writel(0, adc->base + LRADC_CH(0));
drivers/iio/adc/mxs-lradc-adc.c
175
writel(LRADC_CTRL1_LRADC_IRQ_EN(0),
drivers/iio/adc/mxs-lradc-adc.c
177
writel(BIT(0), adc->base + LRADC_CTRL0 + STMP_OFFSET_REG_SET);
drivers/iio/adc/mxs-lradc-adc.c
191
writel(LRADC_CTRL1_LRADC_IRQ_EN(0),
drivers/iio/adc/mxs-lradc-adc.c
403
writel(reg & mxs_lradc_irq_mask(lradc),
drivers/iio/adc/mxs-lradc-adc.c
422
writel(chan_value, adc->base + LRADC_CH(j));
drivers/iio/adc/mxs-lradc-adc.c
442
writel(LRADC_DELAY_KICK, adc->base + (LRADC_DELAY(0) + st));
drivers/iio/adc/mxs-lradc-adc.c
495
writel(lradc->buffer_vchans << LRADC_CTRL1_LRADC_IRQ_EN_OFFSET,
drivers/iio/adc/mxs-lradc-adc.c
497
writel(lradc->buffer_vchans,
drivers/iio/adc/mxs-lradc-adc.c
504
writel(chan_value, adc->base + LRADC_CH(ofs));
drivers/iio/adc/mxs-lradc-adc.c
509
writel(LRADC_DELAY_TRIGGER_LRADCS_MASK | LRADC_DELAY_KICK,
drivers/iio/adc/mxs-lradc-adc.c
511
writel(ctrl4_clr, adc->base + LRADC_CTRL4 + STMP_OFFSET_REG_CLR);
drivers/iio/adc/mxs-lradc-adc.c
512
writel(ctrl4_set, adc->base + LRADC_CTRL4 + STMP_OFFSET_REG_SET);
drivers/iio/adc/mxs-lradc-adc.c
513
writel(ctrl1_irq, adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_SET);
drivers/iio/adc/mxs-lradc-adc.c
514
writel(enable << LRADC_DELAY_TRIGGER_LRADCS_OFFSET,
drivers/iio/adc/mxs-lradc-adc.c
525
writel(LRADC_DELAY_TRIGGER_LRADCS_MASK | LRADC_DELAY_KICK,
drivers/iio/adc/mxs-lradc-adc.c
528
writel(lradc->buffer_vchans,
drivers/iio/adc/mxs-lradc-adc.c
531
writel(lradc->buffer_vchans << LRADC_CTRL1_LRADC_IRQ_EN_OFFSET,
drivers/iio/adc/mxs-lradc-adc.c
672
writel(adc_cfg, adc->base + LRADC_DELAY(0));
drivers/iio/adc/mxs-lradc-adc.c
679
writel(0, adc->base + LRADC_CTRL2);
drivers/iio/adc/mxs-lradc-adc.c
684
writel(0, adc->base + LRADC_DELAY(0));
drivers/iio/adc/nxp-sar-adc.c
196
writel(NXP_SAR_ADC_ISR_ECH, NXP_SAR_ADC_IMR(info->regs));
drivers/iio/adc/nxp-sar-adc.c
198
writel(0, NXP_SAR_ADC_IMR(info->regs));
drivers/iio/adc/nxp-sar-adc.c
217
writel(mcr, NXP_SAR_ADC_MCR(info->regs));
drivers/iio/adc/nxp-sar-adc.c
245
writel(mcr, NXP_SAR_ADC_MCR(base));
drivers/iio/adc/nxp-sar-adc.c
265
writel(msr, NXP_SAR_ADC_MSR(base));
drivers/iio/adc/nxp-sar-adc.c
299
writel(inpsamp, NXP_SAR_ADC_CTR0(info->regs));
drivers/iio/adc/nxp-sar-adc.c
309
writel(NXP_SAR_ADC_CH_MASK, NXP_SAR_ADC_CEOCFR0(info->regs));
drivers/iio/adc/nxp-sar-adc.c
310
writel(NXP_SAR_ADC_CH_MASK, NXP_SAR_ADC_CEOCFR1(info->regs));
drivers/iio/adc/nxp-sar-adc.c
386
writel(NXP_SAR_ADC_ISR_ECH, NXP_SAR_ADC_ISR(info->regs));
drivers/iio/adc/nxp-sar-adc.c
402
writel(ncmr, NXP_SAR_ADC_NCMR0(info->regs));
drivers/iio/adc/nxp-sar-adc.c
403
writel(cimr, NXP_SAR_ADC_CIMR0(info->regs));
drivers/iio/adc/nxp-sar-adc.c
416
writel(ncmr, NXP_SAR_ADC_NCMR0(info->regs));
drivers/iio/adc/nxp-sar-adc.c
417
writel(cimr, NXP_SAR_ADC_CIMR0(info->regs));
drivers/iio/adc/nxp-sar-adc.c
428
writel(dmar, NXP_SAR_ADC_DMAR0(info->regs));
drivers/iio/adc/nxp-sar-adc.c
439
writel(dmar, NXP_SAR_ADC_DMAR0(info->regs));
drivers/iio/adc/nxp-sar-adc.c
450
writel(dmae, NXP_SAR_ADC_DMAE(info->regs));
drivers/iio/adc/nxp-sar-adc.c
461
writel(mcr, NXP_SAR_ADC_MCR(info->regs));
drivers/iio/adc/nxp-sar-adc.c
483
writel(mcr, NXP_SAR_ADC_MCR(info->regs));
drivers/iio/adc/nxp-sar-adc.c
881
writel(0x00003901, NXP_SAR_ADC_MCR(info->regs));
drivers/iio/adc/nxp-sar-adc.c
882
writel(0x00000001, NXP_SAR_ADC_MSR(info->regs));
drivers/iio/adc/nxp-sar-adc.c
883
writel(0x00000014, NXP_SAR_ADC_CTR0(info->regs));
drivers/iio/adc/nxp-sar-adc.c
884
writel(0x00000014, NXP_SAR_ADC_CTR1(info->regs));
drivers/iio/adc/nxp-sar-adc.c
885
writel(0x00000000, NXP_SAR_ADC_CIMR0(info->regs));
drivers/iio/adc/nxp-sar-adc.c
886
writel(0x00000000, NXP_SAR_ADC_CIMR1(info->regs));
drivers/iio/adc/nxp-sar-adc.c
887
writel(0x00000000, NXP_SAR_ADC_NCMR0(info->regs));
drivers/iio/adc/nxp-sar-adc.c
888
writel(0x00000000, NXP_SAR_ADC_NCMR1(info->regs));
drivers/iio/adc/rcar-gyroadc.c
100
writel(clk_mhz * 1250, priv->regs + RCAR_GYROADC_1_25MS_LENGTH);
drivers/iio/adc/rcar-gyroadc.c
106
writel(RCAR_GYROADC_START_STOP_START,
drivers/iio/adc/rcar-gyroadc.c
121
writel(0, priv->regs + RCAR_GYROADC_START_STOP);
drivers/iio/adc/rcar-gyroadc.c
91
writel(0, priv->regs + RCAR_GYROADC_START_STOP);
drivers/iio/adc/rcar-gyroadc.c
95
writel(0, priv->regs + RCAR_GYROADC_INTENR);
drivers/iio/adc/rcar-gyroadc.c
98
writel(priv->mode, priv->regs + RCAR_GYROADC_MODE_SELECT);
drivers/iio/adc/rcar-gyroadc.c
99
writel(clk_len, priv->regs + RCAR_GYROADC_CLOCK_LENGTH);
drivers/iio/adc/rockchip_saradc.c
111
writel(val, info->regs + SARADC2_CONV_CON);
drivers/iio/adc/rockchip_saradc.c
91
writel(SARADC_CTRL_POWER_CTRL | (chn & SARADC_CTRL_CHN_MASK) |
drivers/iio/adc/rzg2l_adc.c
123
writel(val, adc->base + reg);
drivers/iio/adc/rzn1-adc.c
134
writel(power ? 0 : RZN1_ADC_CONFIG_ADC_POWER_DOWN,
drivers/iio/adc/rzn1-adc.c
156
writel(vc, rzn1_adc->regs + RZN1_ADC_VC_REG(ch));
drivers/iio/adc/rzn1-adc.c
167
writel(RZN1_ADC_FORCE_VC(ch), rzn1_adc->regs + RZN1_ADC_SET_FORCE_REG);
drivers/iio/adc/rzn1-adc.c
174
writel(RZN1_ADC_FORCE_VC(ch), rzn1_adc->regs + RZN1_ADC_CLEAR_FORCE_REG);
drivers/iio/adc/sophgo-cv1800b-adc.c
149
writel(CV1800B_ADC_INTR_CLR_BIT, saradc->regs + CV1800B_ADC_INTR_CLR_REG);
drivers/iio/adc/sophgo-cv1800b-adc.c
194
writel(1, saradc->regs + CV1800B_ADC_INTR_EN_REG);
drivers/iio/adc/sophgo-cv1800b-adc.c
201
writel(FIELD_PREP(CV1800B_MASK_STARTUP_CYCLE, 15) |
drivers/iio/adc/sophgo-cv1800b-adc.c
75
writel(0, saradc->regs + CV1800B_ADC_CTRL_REG);
drivers/iio/adc/sophgo-cv1800b-adc.c
76
writel(CV1800B_ADC_SEL(channel) | CV1800B_ADC_EN,
drivers/iio/adc/sun20i-gpadc-iio.c
135
writel(GENMASK(31, 0), info->regs + SUN20I_GPADC_DATA_INTS);
drivers/iio/adc/sun20i-gpadc-iio.c
233
writel(FIELD_PREP(SUN20I_GPADC_CTRL_ADC_AUTOCALI_EN_MASK, 1) |
drivers/iio/adc/sun20i-gpadc-iio.c
77
writel(SUN20I_GPADC_CS_EN_ADC_CH(chan->channel),
drivers/iio/adc/sun20i-gpadc-iio.c
81
writel(SUN20I_GPADC_DATA_INTC_CH_DATA_IRQ_EN(chan->channel),
drivers/iio/adc/sun20i-gpadc-iio.c
88
writel(ctrl, info->regs + SUN20I_GPADC_CTRL);
drivers/iio/adc/ti_am335x_adc.c
62
writel(val, adc->mfd_tscadc->tscadc_base + reg);
drivers/iio/adc/vf610_adc.c
295
writel(cfg_data, info->regs + VF610_REG_ADC_CFG);
drivers/iio/adc/vf610_adc.c
296
writel(gc_data, info->regs + VF610_REG_ADC_GC);
drivers/iio/adc/vf610_adc.c
308
writel(hc_cfg, info->regs + VF610_REG_ADC_HC0);
drivers/iio/adc/vf610_adc.c
311
writel(adc_gc | VF610_ADC_CAL, info->regs + VF610_REG_ADC_GC);
drivers/iio/adc/vf610_adc.c
338
writel(cfg_data, info->regs + VF610_REG_ADC_CFG);
drivers/iio/adc/vf610_adc.c
453
writel(cfg_data, info->regs + VF610_REG_ADC_CFG);
drivers/iio/adc/vf610_adc.c
454
writel(gc_data, info->regs + VF610_REG_ADC_GC);
drivers/iio/adc/vf610_adc.c
641
writel(hc_cfg, info->regs + VF610_REG_ADC_HC0);
drivers/iio/adc/vf610_adc.c
743
writel(val, info->regs + VF610_REG_ADC_GC);
drivers/iio/adc/vf610_adc.c
751
writel(val, info->regs + VF610_REG_ADC_HC0);
drivers/iio/adc/vf610_adc.c
764
writel(val, info->regs + VF610_REG_ADC_GC);
drivers/iio/adc/vf610_adc.c
769
writel(hc_cfg, info->regs + VF610_REG_ADC_HC0);
drivers/iio/adc/vf610_adc.c
915
writel(hc_cfg, info->regs + VF610_REG_ADC_HC0);
drivers/iio/adc/xilinx-ams.c
1001
writel(val, ams->pl_base + offset);
drivers/iio/adc/xilinx-ams.c
1003
writel(val, ams->ps_base + offset);
drivers/iio/adc/xilinx-ams.c
1091
writel(isr0, ams->base + AMS_ISR_0);
drivers/iio/adc/xilinx-ams.c
1324
writel(AMS_ALARM_THR_MIN,
drivers/iio/adc/xilinx-ams.c
1326
writel(AMS_ALARM_THR_MAX,
drivers/iio/adc/xilinx-ams.c
1329
writel(AMS_ALARM_THR_MIN,
drivers/iio/adc/xilinx-ams.c
1331
writel(AMS_ALARM_THR_MAX,
drivers/iio/adc/xilinx-ams.c
302
writel(regval, ams->ps_base + offset);
drivers/iio/adc/xilinx-ams.c
312
writel(regval, ams->pl_base + offset);
drivers/iio/adc/xilinx-ams.c
322
writel(regval, ams->base + AMS_IER_0);
drivers/iio/adc/xilinx-ams.c
325
writel(regval, ams->base + AMS_IER_1);
drivers/iio/adc/xilinx-ams.c
328
writel(regval, ams->base + AMS_IDR_0);
drivers/iio/adc/xilinx-ams.c
331
writel(regval, ams->base + AMS_IDR_1);
drivers/iio/adc/xilinx-ams.c
410
writel(unmask, ams->base + AMS_ISR_0);
drivers/iio/adc/xilinx-ams.c
459
writel(regval, ams->ps_base + AMS_REG_SEQ_CH0);
drivers/iio/adc/xilinx-ams.c
462
writel(regval, ams->ps_base + AMS_REG_SEQ_CH2);
drivers/iio/adc/xilinx-ams.c
478
writel(regval, ams->pl_base + AMS_REG_SEQ_CH0);
drivers/iio/adc/xilinx-ams.c
481
writel(regval, ams->pl_base + AMS_REG_SEQ_CH1);
drivers/iio/adc/xilinx-ams.c
484
writel(regval, ams->pl_base + AMS_REG_SEQ_CH2);
drivers/iio/adc/xilinx-ams.c
500
writel(AMS_PS_RESET_VALUE, ams->ps_base + AMS_VP_VN);
drivers/iio/adc/xilinx-ams.c
517
writel(AMS_PL_RESET_VALUE, ams->pl_base + AMS_VP_VN);
drivers/iio/adc/xilinx-ams.c
530
writel(AMS_ISR0_ALARM_MASK, ams->base + AMS_ISR_0);
drivers/iio/adc/xilinx-ams.c
531
writel(AMS_ISR1_ALARM_MASK, ams->base + AMS_ISR_1);
drivers/iio/adc/xilinx-ams.c
598
writel(expect, ams->base + AMS_ISR_1);
drivers/iio/adc/xilinx-xadc-core.c
126
writel(val, xadc->base + reg);
drivers/iio/dac/lpc18xx_dac.c
150
writel(0, dac->base + LPC18XX_DAC_CTRL);
drivers/iio/dac/lpc18xx_dac.c
151
writel(0, dac->base + LPC18XX_DAC_CR);
drivers/iio/dac/lpc18xx_dac.c
175
writel(0, dac->base + LPC18XX_DAC_CTRL);
drivers/iio/dac/lpc18xx_dac.c
89
writel(reg, dac->base + LPC18XX_DAC_CR);
drivers/iio/dac/lpc18xx_dac.c
90
writel(LPC18XX_DAC_CTRL_DMA_ENA, dac->base + LPC18XX_DAC_CTRL);
drivers/iio/dac/vf610_dac.c
153
writel(VF610_DAC_DAT0(val), info->regs);
drivers/iio/dac/vf610_dac.c
50
writel(val, info->regs + VF610_DACx_STATCTRL);
drivers/iio/dac/vf610_dac.c
59
writel(val, info->regs + VF610_DACx_STATCTRL);
drivers/iio/dac/vf610_dac.c
76
writel(val, info->regs + VF610_DACx_STATCTRL);
drivers/infiniband/hw/bng_re/bng_fw.c
383
writel(cmdq_prod, cmdq->cmdq_mbox.prod);
drivers/infiniband/hw/bng_re/bng_fw.c
384
writel(BNG_FW_CMDQ_TRIG_VAL, cmdq->cmdq_mbox.db);
drivers/infiniband/hw/bnxt_re/main.c
879
writel(rdev->chip_ctx->dbr_stat_db_fifo & BNXT_GRC_BASE_MASK,
drivers/infiniband/hw/bnxt_re/qplib_rcfw.c
279
writel(cmdq_prod, cmdq->cmdq_mbox.prod);
drivers/infiniband/hw/bnxt_re/qplib_rcfw.c
280
writel(RCFW_CMDQ_TRIG_VAL, cmdq->cmdq_mbox.db);
drivers/infiniband/hw/bnxt_re/qplib_rcfw.c
367
writel(cmdq_prod, cmdq->cmdq_mbox.prod);
drivers/infiniband/hw/bnxt_re/qplib_rcfw.c
368
writel(RCFW_CMDQ_TRIG_VAL, cmdq->cmdq_mbox.db);
drivers/infiniband/hw/bnxt_re/qplib_res.h
482
writel(key, info->db);
drivers/infiniband/hw/cxgb4/t4.h
594
writel(PIDX_T5_V(inc) | QID_V(srq->bar2_qid),
drivers/infiniband/hw/cxgb4/t4.h
614
writel(PIDX_T5_V(inc) | QID_V(wq->sq.bar2_qid),
drivers/infiniband/hw/cxgb4/t4.h
622
writel(QID_V(wq->sq.qid) | PIDX_V(inc), wq->db);
drivers/infiniband/hw/cxgb4/t4.h
639
writel(PIDX_T5_V(inc) | QID_V(wq->rq.bar2_qid),
drivers/infiniband/hw/cxgb4/t4.h
647
writel(QID_V(wq->rq.qid) | PIDX_V(inc), wq->db);
drivers/infiniband/hw/cxgb4/t4.h
706
writel(val | INGRESSQID_V(cq->bar2_qid),
drivers/infiniband/hw/cxgb4/t4.h
709
writel(val | INGRESSQID_V(cq->cqid), cq->gts);
drivers/infiniband/hw/efa/efa_com.c
1075
writel(reset_val, edev->reg_bar + EFA_REGS_DEV_CTL_OFF);
drivers/infiniband/hw/efa/efa_com.c
1087
writel(0, edev->reg_bar + EFA_REGS_DEV_CTL_OFF);
drivers/infiniband/hw/efa/efa_com.c
1168
writel(val, edev->reg_bar + EFA_REGS_EQ_DB_OFF);
drivers/infiniband/hw/efa/efa_com.c
153
writel(addr_low, edev->reg_bar + EFA_REGS_AQ_BASE_LO_OFF);
drivers/infiniband/hw/efa/efa_com.c
154
writel(addr_high, edev->reg_bar + EFA_REGS_AQ_BASE_HI_OFF);
drivers/infiniband/hw/efa/efa_com.c
160
writel(aq_caps, edev->reg_bar + EFA_REGS_AQ_CAPS_OFF);
drivers/infiniband/hw/efa/efa_com.c
187
writel(addr_low, edev->reg_bar + EFA_REGS_ACQ_BASE_LO_OFF);
drivers/infiniband/hw/efa/efa_com.c
188
writel(addr_high, edev->reg_bar + EFA_REGS_ACQ_BASE_HI_OFF);
drivers/infiniband/hw/efa/efa_com.c
196
writel(acq_caps, edev->reg_bar + EFA_REGS_ACQ_CAPS_OFF);
drivers/infiniband/hw/efa/efa_com.c
228
writel(addr_low, edev->reg_bar + EFA_REGS_AENQ_BASE_LO_OFF);
drivers/infiniband/hw/efa/efa_com.c
229
writel(addr_high, edev->reg_bar + EFA_REGS_AENQ_BASE_HI_OFF);
drivers/infiniband/hw/efa/efa_com.c
236
writel(aenq_caps, edev->reg_bar + EFA_REGS_AENQ_CAPS_OFF);
drivers/infiniband/hw/efa/efa_com.c
242
writel(edev->aenq.cc, edev->reg_bar + EFA_REGS_AENQ_CONS_DB_OFF);
drivers/infiniband/hw/efa/efa_com.c
358
writel(aq->sq.pc, aq->sq.db_addr);
drivers/infiniband/hw/efa/efa_com.c
707
writel(mask_value, edev->reg_bar + EFA_REGS_INTR_MASK_OFF);
drivers/infiniband/hw/efa/efa_com.c
892
writel(aenq->cc, edev->reg_bar + EFA_REGS_AENQ_CONS_DB_OFF);
drivers/infiniband/hw/efa/efa_com.c
905
writel(addr_high, edev->reg_bar + EFA_REGS_MMIO_RESP_HI_OFF);
drivers/infiniband/hw/efa/efa_com.c
906
writel(addr_low, edev->reg_bar + EFA_REGS_MMIO_RESP_LO_OFF);
drivers/infiniband/hw/efa/efa_com.c
95
writel(mmio_read_reg, edev->reg_bar + EFA_REGS_MMIO_REG_READ_OFF);
drivers/infiniband/hw/erdma/erdma.h
244
writel(value, dev->func_bar + reg);
drivers/infiniband/hw/hns/hns_roce_common.h
37
#define roce_write(dev, reg, val) writel((val), (dev)->reg_base + (reg))
drivers/infiniband/hw/irdma/ctrl.c
3652
writel(0, cqp->dev->hw_regs[IRDMA_CQPTAIL]);
drivers/infiniband/hw/irdma/ctrl.c
3654
writel(0, cqp->dev->hw_regs[IRDMA_CQPDB]);
drivers/infiniband/hw/irdma/ctrl.c
3655
writel(0, cqp->dev->hw_regs[IRDMA_CCQPSTATUS]);
drivers/infiniband/hw/irdma/ctrl.c
3753
writel(p1, cqp->dev->hw_regs[IRDMA_CCQPHIGH]);
drivers/infiniband/hw/irdma/ctrl.c
3754
writel(p2, cqp->dev->hw_regs[IRDMA_CCQPLOW]);
drivers/infiniband/hw/irdma/ctrl.c
3789
writel(IRDMA_RING_CURRENT_HEAD(cqp->sq_ring), cqp->dev->cqp_db);
drivers/infiniband/hw/irdma/ctrl.c
3839
writel(0, cqp->dev->hw_regs[IRDMA_CCQPHIGH]);
drivers/infiniband/hw/irdma/ctrl.c
3840
writel(0, cqp->dev->hw_regs[IRDMA_CCQPLOW]);
drivers/infiniband/hw/irdma/ctrl.c
3881
writel(ccq->cq_uk.cq_id, ccq->dev->cq_arm_db);
drivers/infiniband/hw/irdma/ctrl.c
4621
writel(0, dev->hw_regs[IRDMA_PFINT_AEQCTL]);
drivers/infiniband/hw/irdma/ctrl.c
4845
writel(count, dev->hw_regs[IRDMA_AEQALLOC]);
drivers/infiniband/hw/irdma/ctrl.c
6363
writel(reg_val, dev->hw_regs[IRDMA_PFINT_AEQCTL]);
drivers/infiniband/hw/irdma/hmc.c
112
writel(val, dev->hw_regs[IRDMA_PFHMC_PDINV]);
drivers/infiniband/hw/irdma/hw.c
131
writel(cq->cq_uk.cq_id, cq->cq_uk.cq_ack_db);
drivers/infiniband/hw/irdma/hw.c
151
writel(cq->cq_uk.cq_id, cq->cq_uk.cq_ack_db);
drivers/infiniband/hw/irdma/hw.c
163
writel(cq->cq_uk.cq_id, cq->cq_uk.cq_ack_db);
drivers/infiniband/hw/irdma/icrdma_hw.c
106
writel(reg_val, dev->hw_regs[IRDMA_GLINT_CEQCTL] + ceq_id);
drivers/infiniband/hw/irdma/icrdma_hw.c
72
writel(val, dev->hw_regs[IRDMA_GLINT_DYN_CTL] + idx);
drivers/infiniband/hw/irdma/icrdma_hw.c
74
writel(val, dev->hw_regs[IRDMA_GLINT_DYN_CTL] + (idx - 1));
drivers/infiniband/hw/irdma/icrdma_hw.c
85
writel(0, dev->hw_regs[IRDMA_GLINT_DYN_CTL] + idx);
drivers/infiniband/hw/irdma/icrdma_hw.c
87
writel(0, dev->hw_regs[IRDMA_GLINT_DYN_CTL] + (idx - 1));
drivers/infiniband/hw/irdma/ig3rdma_hw.c
26
writel(val, dev->hw_regs[IRDMA_GLINT_DYN_CTL] + (idx * int_stride));
drivers/infiniband/hw/irdma/ig3rdma_hw.c
43
writel(0, dev->hw_regs[IRDMA_GLINT_DYN_CTL] + (idx * int_stride));
drivers/infiniband/hw/irdma/uk.c
1109
writel(cq->cq_id, cq->cqe_alloc_db);
drivers/infiniband/hw/irdma/uk.c
117
writel(qp->qp_id, qp->wqe_alloc_db);
drivers/infiniband/hw/irdma/utils.c
106
writel(val, hw->hw_addr + reg);
drivers/infiniband/hw/mthca/mthca_eq.c
216
writel(eqn_mask, dev->eq_regs.arbel.eq_arm);
drivers/infiniband/hw/mthca/mthca_eq.c
398
writel(dev->eq_table.clr_mask, dev->eq_table.clr_int);
drivers/infiniband/hw/mthca/mthca_eq.c
404
writel(ecr, dev->eq_regs.tavor.ecr_base +
drivers/infiniband/hw/mthca/mthca_eq.c
438
writel(dev->eq_table.clr_mask, dev->eq_table.clr_int);
drivers/infiniband/hw/mthca/mthca_reset.c
154
writel(MTHCA_RESET_VALUE, reset);
drivers/infiniband/hw/qedr/verbs.c
2389
writel(qp->rq.db_data.raw, qp->rq.db);
drivers/infiniband/hw/qedr/verbs.c
3814
writel(qp->sq.db_data.raw, qp->sq.db);
drivers/infiniband/hw/qedr/verbs.c
3996
writel(qp->rq.db_data.raw, qp->rq.db);
drivers/infiniband/hw/qedr/verbs.c
3999
writel(qp->rq.iwarp_db2_data.raw, qp->rq.iwarp_db2);
drivers/infiniband/hw/vmw_pvrdma/pvrdma.h
301
writel(cpu_to_le32(val), dev->regs + reg);
drivers/infiniband/hw/vmw_pvrdma/pvrdma.h
311
writel(cpu_to_le32(val), dev->driver_uar.map + PVRDMA_UAR_CQ_OFFSET);
drivers/infiniband/hw/vmw_pvrdma/pvrdma.h
316
writel(cpu_to_le32(val), dev->driver_uar.map + PVRDMA_UAR_QP_OFFSET);
drivers/input/joystick/n64joy.c
87
writel(value, reg_base + reg);
drivers/input/keyboard/bcm-keypad.c
102
writel(0xFFFFFFFF, kp->base + KPICRN_OFFSET(reg_num));
drivers/input/keyboard/bcm-keypad.c
143
writel(kp->kpior, kp->base + KPIOR_OFFSET);
drivers/input/keyboard/bcm-keypad.c
145
writel(kp->imr0_val, kp->base + KPIMR0_OFFSET);
drivers/input/keyboard/bcm-keypad.c
146
writel(kp->imr1_val, kp->base + KPIMR1_OFFSET);
drivers/input/keyboard/bcm-keypad.c
148
writel(kp->kpemr, kp->base + KPEMR0_OFFSET);
drivers/input/keyboard/bcm-keypad.c
149
writel(kp->kpemr, kp->base + KPEMR1_OFFSET);
drivers/input/keyboard/bcm-keypad.c
150
writel(kp->kpemr, kp->base + KPEMR2_OFFSET);
drivers/input/keyboard/bcm-keypad.c
151
writel(kp->kpemr, kp->base + KPEMR3_OFFSET);
drivers/input/keyboard/bcm-keypad.c
153
writel(0xFFFFFFFF, kp->base + KPICR0_OFFSET);
drivers/input/keyboard/bcm-keypad.c
154
writel(0xFFFFFFFF, kp->base + KPICR1_OFFSET);
drivers/input/keyboard/bcm-keypad.c
159
writel(kp->kpcr | KPCR_ENABLE, kp->base + KPCR_OFFSET);
drivers/input/keyboard/bcm-keypad.c
170
writel(0, kp->base + KPCR_OFFSET);
drivers/input/keyboard/bcm-keypad.c
171
writel(0, kp->base + KPIMR0_OFFSET);
drivers/input/keyboard/bcm-keypad.c
172
writel(0, kp->base + KPIMR1_OFFSET);
drivers/input/keyboard/bcm-keypad.c
173
writel(0xFFFFFFFF, kp->base + KPICR0_OFFSET);
drivers/input/keyboard/bcm-keypad.c
174
writel(0xFFFFFFFF, kp->base + KPICR1_OFFSET);
drivers/input/keyboard/lpc32xx-keys.c
101
writel(1, LPC32XX_KS_IRQ(kscandat->kscan_base));
drivers/input/keyboard/lpc32xx-keys.c
117
writel(1, LPC32XX_KS_IRQ(kscandat->kscan_base));
drivers/input/keyboard/lpc32xx-keys.c
126
writel(1, LPC32XX_KS_IRQ(kscandat->kscan_base));
drivers/input/keyboard/lpc32xx-keys.c
232
writel(kscandat->deb_clks, LPC32XX_KS_DEB(kscandat->kscan_base));
drivers/input/keyboard/lpc32xx-keys.c
233
writel(kscandat->scan_delay, LPC32XX_KS_SCAN_CTL(kscandat->kscan_base));
drivers/input/keyboard/lpc32xx-keys.c
234
writel(LPC32XX_KSCAN_FTST_USE32K_CLK,
drivers/input/keyboard/lpc32xx-keys.c
236
writel(kscandat->matrix_sz,
drivers/input/keyboard/lpc32xx-keys.c
238
writel(1, LPC32XX_KS_IRQ(kscandat->kscan_base));
drivers/input/keyboard/lpc32xx-keys.c
269
writel(1, LPC32XX_KS_IRQ(kscandat->kscan_base));
drivers/input/keyboard/lpc32xx-keys.c
291
writel(1, LPC32XX_KS_IRQ(kscandat->kscan_base));
drivers/input/keyboard/nspire-keypad.c
121
writel(val, keypad->reg_base + KEYPAD_SCAN_MODE);
drivers/input/keyboard/nspire-keypad.c
124
writel(val, keypad->reg_base + KEYPAD_CNTL);
drivers/input/keyboard/nspire-keypad.c
128
writel(keypad->int_mask, keypad->reg_base + KEYPAD_INTMSK);
drivers/input/keyboard/nspire-keypad.c
138
writel(0, keypad->reg_base + KEYPAD_INTMSK);
drivers/input/keyboard/nspire-keypad.c
140
writel(~0, keypad->reg_base + KEYPAD_INT);
drivers/input/keyboard/nspire-keypad.c
206
writel(0, keypad->reg_base + KEYPAD_INTMSK);
drivers/input/keyboard/nspire-keypad.c
208
writel(~0, keypad->reg_base + KEYPAD_INT);
drivers/input/keyboard/nspire-keypad.c
212
writel(0, keypad->reg_base + KEYPAD_UNKNOWN_INT);
drivers/input/keyboard/nspire-keypad.c
214
writel(~0, keypad->reg_base + KEYPAD_UNKNOWN_INT_STS);
drivers/input/keyboard/nspire-keypad.c
91
writel(0x3, keypad->reg_base + KEYPAD_INT);
drivers/input/keyboard/samsung-keypad.c
150
writel(~0x0, keypad->base + SAMSUNG_KEYIFSTSCLR);
drivers/input/keyboard/samsung-keypad.c
180
writel(val, keypad->base + SAMSUNG_KEYIFCON);
drivers/input/keyboard/samsung-keypad.c
183
writel(0, keypad->base + SAMSUNG_KEYIFCOL);
drivers/input/keyboard/samsung-keypad.c
200
writel(~0x0, keypad->base + SAMSUNG_KEYIFSTSCLR);
drivers/input/keyboard/samsung-keypad.c
205
writel(val, keypad->base + SAMSUNG_KEYIFCON);
drivers/input/keyboard/samsung-keypad.c
458
writel(val, keypad->base + SAMSUNG_KEYIFCON);
drivers/input/keyboard/samsung-keypad.c
478
writel(val, keypad->base + SAMSUNG_KEYIFCON);
drivers/input/keyboard/samsung-keypad.c
503
writel(val, keypad->base + SAMSUNG_KEYIFCON);
drivers/input/keyboard/samsung-keypad.c
88
writel(val, keypad->base + SAMSUNG_KEYIFCOL);
drivers/input/keyboard/samsung-keypad.c
96
writel(0, keypad->base + SAMSUNG_KEYIFCOL);
drivers/input/keyboard/st-keyscan.c
69
writel(keypad->debounce_us * (clk_get_rate(keypad->clk) / 1000000),
drivers/input/keyboard/st-keyscan.c
72
writel(((keypad->n_cols - 1) << KEYSCAN_MATRIX_DIM_X_SHIFT) |
drivers/input/keyboard/st-keyscan.c
76
writel(KEYSCAN_CONFIG_ENABLE, keypad->base + KEYSCAN_CONFIG_OFF);
drivers/input/keyboard/st-keyscan.c
83
writel(0, keypad->base + KEYSCAN_CONFIG_OFF);
drivers/input/keyboard/sun4i-lradc-keys.c
143
writel(ints, lradc->base + LRADC_INTS);
drivers/input/keyboard/sun4i-lradc-keys.c
172
writel(FIRST_CONVERT_DLY(2) | LEVELA_B_CNT(1) | HOLD_EN(1) |
drivers/input/keyboard/sun4i-lradc-keys.c
175
writel(CHAN0_KEYUP_IRQ | CHAN0_KEYDOWN_IRQ, lradc->base + LRADC_INTC);
drivers/input/keyboard/sun4i-lradc-keys.c
192
writel(FIRST_CONVERT_DLY(2) | LEVELA_B_CNT(1) | HOLD_EN(1) |
drivers/input/keyboard/sun4i-lradc-keys.c
194
writel(0, lradc->base + LRADC_INTC);
drivers/input/keyboard/tegra-kbc.c
238
writel(val, kbc->mmio + KBC_CONTROL_0);
drivers/input/keyboard/tegra-kbc.c
286
writel(val, kbc->mmio + KBC_INT_0);
drivers/input/keyboard/tegra-kbc.c
312
writel(rst_val, kbc->mmio + KBC_ROW0_MASK_0 + i * 4);
drivers/input/keyboard/tegra-kbc.c
345
writel(row_cfg, kbc->mmio + r_offs);
drivers/input/keyboard/tegra-kbc.c
346
writel(col_cfg, kbc->mmio + c_offs);
drivers/input/keyboard/tegra-kbc.c
369
writel(kbc->repeat_cnt, kbc->mmio + KBC_RPT_DLY_0);
drivers/input/keyboard/tegra-kbc.c
377
writel(val, kbc->mmio + KBC_CONTROL_0);
drivers/input/keyboard/tegra-kbc.c
401
writel(0x7, kbc->mmio + KBC_INT_0);
drivers/input/keyboard/tegra-kbc.c
415
writel(val, kbc->mmio + KBC_CONTROL_0);
drivers/input/keyboard/tegra-kbc.c
694
writel(val, kbc->mmio + KBC_CONTROL_0);
drivers/input/keyboard/tegra-kbc.c
710
writel(0x7, kbc->mmio + KBC_INT_0);
drivers/input/keyboard/tegra-kbc.c
716
writel(0, kbc->mmio + KBC_TO_CNT_0);
drivers/input/keyboard/tegra-kbc.c
748
writel(kbc->cp_to_wkup_dly, kbc->mmio + KBC_TO_CNT_0);
drivers/input/serio/altera_ps2.c
52
writel(val, ps2if->base);
drivers/input/serio/altera_ps2.c
64
writel(1, ps2if->base + 4); /* enable rx irq */
drivers/input/serio/altera_ps2.c
72
writel(0, ps2if->base + 4); /* disable rx irq */
drivers/input/serio/ioc3kbd.c
188
writel(KM_CSR_K_CLAMP_3 | KM_CSR_M_CLAMP_3, ®s->km_csr);
drivers/input/serio/ioc3kbd.c
47
writel(val, &d->regs->k_wd);
drivers/input/serio/ioc3kbd.c
76
writel(val, &d->regs->m_wd);
drivers/input/serio/olpc_apsp.c
128
writel(tmp | SP_COMMAND_COMPLETE_RESET, priv->base + PJ_RST_INTERRUPT);
drivers/input/serio/olpc_apsp.c
129
writel(PORT_MASK, priv->base + SECURE_PROCESSOR_COMMAND);
drivers/input/serio/olpc_apsp.c
150
writel(tmp & ~INT_0, priv->base + PJ_INTERRUPT_MASK);
drivers/input/serio/olpc_apsp.c
164
writel(tmp | INT_0, priv->base + PJ_INTERRUPT_MASK);
drivers/input/serio/olpc_apsp.c
87
writel(which | val,
drivers/input/serio/sun4i-ps2.c
118
writel(rval, drvdata->reg_base + PS2_REG_LSTS);
drivers/input/serio/sun4i-ps2.c
125
writel(rval, drvdata->reg_base + PS2_REG_FSTS);
drivers/input/serio/sun4i-ps2.c
134
writel(intr_status, drvdata->reg_base + PS2_REG_LSTS);
drivers/input/serio/sun4i-ps2.c
135
writel(fifo_status, drvdata->reg_base + PS2_REG_FSTS);
drivers/input/serio/sun4i-ps2.c
151
writel(rval, drvdata->reg_base + PS2_REG_LCTL);
drivers/input/serio/sun4i-ps2.c
158
writel(rval, drvdata->reg_base + PS2_REG_FCTL);
drivers/input/serio/sun4i-ps2.c
165
writel(rval, drvdata->reg_base + PS2_REG_CLKDR);
drivers/input/serio/sun4i-ps2.c
172
writel(rval, drvdata->reg_base + PS2_REG_GCTL);
drivers/input/serio/sun4i-ps2.c
184
writel(rval & ~(PS2_GCTL_INTEN), drvdata->reg_base + PS2_REG_GCTL);
drivers/input/serio/sun4i-ps2.c
196
writel(val, drvdata->reg_base + PS2_REG_DATA);
drivers/input/serio/sun4i-ps2.c
259
writel(0, drvdata->reg_base + PS2_REG_GCTL);
drivers/input/touchscreen/imx6ul_tsc.c
131
writel(adc_cfg, tsc->adc_regs + REG_ADC_CFG);
drivers/input/touchscreen/imx6ul_tsc.c
136
writel(adc_hc, tsc->adc_regs + REG_ADC_HC0);
drivers/input/touchscreen/imx6ul_tsc.c
143
writel(adc_gc, tsc->adc_regs + REG_ADC_GC);
drivers/input/touchscreen/imx6ul_tsc.c
161
writel(adc_cfg, tsc->adc_regs + REG_ADC_CFG);
drivers/input/touchscreen/imx6ul_tsc.c
176
writel(adc_hc0, tsc->adc_regs + REG_ADC_HC0);
drivers/input/touchscreen/imx6ul_tsc.c
180
writel(adc_hc1, tsc->adc_regs + REG_ADC_HC1);
drivers/input/touchscreen/imx6ul_tsc.c
183
writel(adc_hc2, tsc->adc_regs + REG_ADC_HC2);
drivers/input/touchscreen/imx6ul_tsc.c
187
writel(adc_hc3, tsc->adc_regs + REG_ADC_HC3);
drivers/input/touchscreen/imx6ul_tsc.c
190
writel(adc_hc4, tsc->adc_regs + REG_ADC_HC4);
drivers/input/touchscreen/imx6ul_tsc.c
207
writel(basic_setting, tsc->tsc_regs + REG_TSC_BASIC_SETTING);
drivers/input/touchscreen/imx6ul_tsc.c
210
writel(debug_mode2, tsc->tsc_regs + REG_TSC_DEBUG_MODE2);
drivers/input/touchscreen/imx6ul_tsc.c
212
writel(tsc->pre_charge_time, tsc->tsc_regs + REG_TSC_PRE_CHARGE_TIME);
drivers/input/touchscreen/imx6ul_tsc.c
213
writel(MEASURE_INT_EN, tsc->tsc_regs + REG_TSC_INT_EN);
drivers/input/touchscreen/imx6ul_tsc.c
214
writel(MEASURE_SIG_EN | VALID_SIG_EN,
drivers/input/touchscreen/imx6ul_tsc.c
221
writel(start, tsc->tsc_regs + REG_TSC_FLOW_CONTROL);
drivers/input/touchscreen/imx6ul_tsc.c
245
writel(tsc_flow, tsc->tsc_regs + REG_TSC_FLOW_CONTROL);
drivers/input/touchscreen/imx6ul_tsc.c
250
writel(adc_cfg, tsc->adc_regs + REG_ADC_HC0);
drivers/input/touchscreen/imx6ul_tsc.c
284
writel(MEASURE_SIGNAL | DETECT_SIGNAL,
drivers/input/touchscreen/imx6ul_tsc.c
290
writel(start, tsc->tsc_regs + REG_TSC_FLOW_CONTROL);
drivers/input/touchscreen/mxs-lradc-ts.c
100
writel(LRADC_CTRL4_LRADCSELECT_MASK(vch),
drivers/input/touchscreen/mxs-lradc-ts.c
102
writel(LRADC_CTRL4_LRADCSELECT(vch, ch),
drivers/input/touchscreen/mxs-lradc-ts.c
116
writel(LRADC_CH_ACCUMULATE |
drivers/input/touchscreen/mxs-lradc-ts.c
124
writel(LRADC_CH_VALUE_MASK,
drivers/input/touchscreen/mxs-lradc-ts.c
135
writel(LRADC_DELAY_TRIGGER(1 << ch) | LRADC_DELAY_TRIGGER_DELAYS(0) |
drivers/input/touchscreen/mxs-lradc-ts.c
140
writel(LRADC_CTRL1_LRADC_IRQ(ch),
drivers/input/touchscreen/mxs-lradc-ts.c
149
writel(LRADC_DELAY_TRIGGER(0) | LRADC_DELAY_TRIGGER_DELAYS(BIT(3)) |
drivers/input/touchscreen/mxs-lradc-ts.c
175
writel(reg, ts->base + LRADC_CH(ch1));
drivers/input/touchscreen/mxs-lradc-ts.c
176
writel(reg, ts->base + LRADC_CH(ch2));
drivers/input/touchscreen/mxs-lradc-ts.c
182
writel(LRADC_CH_VALUE_MASK,
drivers/input/touchscreen/mxs-lradc-ts.c
184
writel(LRADC_CH_VALUE_MASK,
drivers/input/touchscreen/mxs-lradc-ts.c
188
writel(LRADC_DELAY_TRIGGER(1 << ch1) | LRADC_DELAY_TRIGGER(1 << ch2) |
drivers/input/touchscreen/mxs-lradc-ts.c
194
writel(LRADC_CTRL1_LRADC_IRQ(ch2),
drivers/input/touchscreen/mxs-lradc-ts.c
203
writel(LRADC_DELAY_TRIGGER(0) | LRADC_DELAY_TRIGGER_DELAYS(BIT(3)) |
drivers/input/touchscreen/mxs-lradc-ts.c
282
writel(info[lradc->soc].mask,
drivers/input/touchscreen/mxs-lradc-ts.c
284
writel(info[lradc->soc].bit,
drivers/input/touchscreen/mxs-lradc-ts.c
304
writel(info[lradc->soc].mask,
drivers/input/touchscreen/mxs-lradc-ts.c
306
writel(info[lradc->soc].x_plate,
drivers/input/touchscreen/mxs-lradc-ts.c
330
writel(info[lradc->soc].mask,
drivers/input/touchscreen/mxs-lradc-ts.c
332
writel(info[lradc->soc].y_plate,
drivers/input/touchscreen/mxs-lradc-ts.c
356
writel(info[lradc->soc].mask,
drivers/input/touchscreen/mxs-lradc-ts.c
358
writel(info[lradc->soc].pressure,
drivers/input/touchscreen/mxs-lradc-ts.c
373
writel(LRADC_CTRL1_TOUCH_DETECT_IRQ | LRADC_CTRL1_TOUCH_DETECT_IRQ_EN,
drivers/input/touchscreen/mxs-lradc-ts.c
375
writel(LRADC_CTRL1_TOUCH_DETECT_IRQ_EN,
drivers/input/touchscreen/mxs-lradc-ts.c
381
writel(LRADC_CTRL1_TOUCH_DETECT_IRQ_EN,
drivers/input/touchscreen/mxs-lradc-ts.c
383
writel(LRADC_CTRL1_LRADC_IRQ_EN(TOUCHSCREEN_VCHANNEL1),
drivers/input/touchscreen/mxs-lradc-ts.c
409
writel(0, ts->base + LRADC_CH(TOUCHSCREEN_VCHANNEL1));
drivers/input/touchscreen/mxs-lradc-ts.c
410
writel(LRADC_CTRL1_LRADC_IRQ(TOUCHSCREEN_VCHANNEL1) |
drivers/input/touchscreen/mxs-lradc-ts.c
413
writel(LRADC_DELAY_TRIGGER(1 << TOUCHSCREEN_VCHANNEL1) |
drivers/input/touchscreen/mxs-lradc-ts.c
445
writel(0, ts->base + LRADC_DELAY(2));
drivers/input/touchscreen/mxs-lradc-ts.c
446
writel(0, ts->base + LRADC_DELAY(3));
drivers/input/touchscreen/mxs-lradc-ts.c
447
writel(LRADC_CTRL1_TOUCH_DETECT_IRQ |
drivers/input/touchscreen/mxs-lradc-ts.c
451
writel(LRADC_CTRL1_TOUCH_DETECT_IRQ_EN,
drivers/input/touchscreen/mxs-lradc-ts.c
462
writel(LRADC_CTRL1_TOUCH_DETECT_IRQ,
drivers/input/touchscreen/mxs-lradc-ts.c
515
writel(reg & clr_irq,
drivers/input/touchscreen/mxs-lradc-ts.c
538
writel(LRADC_CTRL1_TOUCH_DETECT_IRQ_EN |
drivers/input/touchscreen/mxs-lradc-ts.c
544
writel(info[lradc->soc].mask,
drivers/input/touchscreen/mxs-lradc-ts.c
547
writel(lradc->buffer_vchans << LRADC_CTRL1_LRADC_IRQ_EN_OFFSET,
drivers/input/touchscreen/mxs-lradc-ts.c
551
writel(0, ts->base + LRADC_DELAY(i));
drivers/input/touchscreen/mxs-lradc-ts.c
567
writel(LRADC_CTRL0_MX28_TOUCH_SCREEN_TYPE,
drivers/input/touchscreen/mxs-lradc-ts.c
571
writel(LRADC_CTRL0_MX28_TOUCH_SCREEN_TYPE,
drivers/input/touchscreen/sun4i-ts.c
160
writel(reg_val, ts->base + TP_INT_FIFOS);
drivers/input/touchscreen/sun4i-ts.c
170
writel(TEMP_IRQ_EN(1) | DATA_IRQ_EN(1) | FIFO_TRIG(1) | FIFO_FLUSH(1) |
drivers/input/touchscreen/sun4i-ts.c
181
writel(TEMP_IRQ_EN(1), ts->base + TP_INT_FIFOC);
drivers/input/touchscreen/sun4i-ts.c
317
writel(ADC_CLK_SEL(0) | ADC_CLK_DIV(2) | FS_DIV(7) | T_ACQ(63),
drivers/input/touchscreen/sun4i-ts.c
326
writel(TP_SENSITIVE_ADJUST(tp_sensitive_adjust) | TP_MODE_SELECT(0),
drivers/input/touchscreen/sun4i-ts.c
334
writel(FILTER_EN(1) | FILTER_TYPE(filter_type), ts->base + TP_CTRL3);
drivers/input/touchscreen/sun4i-ts.c
337
writel(TEMP_ENABLE(1) | TEMP_PERIOD(1953), ts->base + TP_TPR);
drivers/input/touchscreen/sun4i-ts.c
348
writel(reg, ts->base + TP_CTRL1);
drivers/input/touchscreen/sun4i-ts.c
364
writel(TEMP_IRQ_EN(1), ts->base + TP_INT_FIFOC);
drivers/input/touchscreen/sun4i-ts.c
369
writel(0, ts->base + TP_INT_FIFOC);
drivers/input/touchscreen/sun4i-ts.c
387
writel(0, ts->base + TP_INT_FIFOC);
drivers/input/touchscreen/ti_am335x_tsc.c
70
writel(val, tsc->mfd_tscadc->tscadc_base + reg);
drivers/interconnect/imx/imx.c
52
writel(prio, base + IMX_NOC_PRIO_REG);
drivers/interconnect/imx/imx.c
53
writel(node_data->setting->mode, base + IMX_NOC_MODE_REG);
drivers/interconnect/imx/imx.c
54
writel(node_data->setting->ext_control, base + IMX_NOC_EXT_CTL_REG);
drivers/iommu/amd/init.c
3944
writel((u32)val, iommu->mmio_base + offset);
drivers/iommu/amd/init.c
3945
writel((val >> 32), iommu->mmio_base + offset + 4);
drivers/iommu/amd/init.c
767
writel(status_overflow_mask, iommu->mmio_base + MMIO_STATUS_OFFSET);
drivers/iommu/amd/init.c
803
writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
drivers/iommu/amd/init.c
804
writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
drivers/iommu/amd/init.c
892
writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
drivers/iommu/amd/init.c
893
writel(0x00, iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
drivers/iommu/amd/init.c
935
writel(0x00, iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
drivers/iommu/amd/init.c
936
writel(0x00, iommu->mmio_base + MMIO_GA_TAIL_OFFSET);
drivers/iommu/amd/iommu.c
1013
writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
drivers/iommu/amd/iommu.c
1058
writel(head, iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
drivers/iommu/amd/iommu.c
1105
writel(mask, iommu->mmio_base + MMIO_STATUS_OFFSET);
drivers/iommu/amd/iommu.c
1240
writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
drivers/iommu/amd/ppr.c
205
writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
drivers/iommu/amd/ppr.c
42
writel(0x00, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
drivers/iommu/amd/ppr.c
43
writel(0x00, iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
drivers/iommu/apple-dart.c
1059
writel(error, dart->regs + DART_T8020_ERROR);
drivers/iommu/apple-dart.c
1098
writel(error, dart->regs + DART_T8110_ERROR);
drivers/iommu/apple-dart.c
1100
writel(U32_MAX, dart->regs + DART_T8110_ERROR_STREAMS + 4 * i);
drivers/iommu/apple-dart.c
1356
writel(dart->save_ttbr[sid][idx],
drivers/iommu/apple-dart.c
1358
writel(dart->save_tcr[sid], dart->regs + DART_TCR(dart, sid));
drivers/iommu/apple-dart.c
325
writel(tcr, dart->regs + DART_TCR(dart, sid));
drivers/iommu/apple-dart.c
334
writel(dart->hw->tcr_disabled, dart->regs + DART_TCR(dart, sid));
drivers/iommu/apple-dart.c
345
writel(dart->hw->tcr_bypass,
drivers/iommu/apple-dart.c
357
writel(dart->hw->ttbr_valid |
drivers/iommu/apple-dart.c
369
writel(0, dart->regs + DART_TTBR(dart, sid, idx));
drivers/iommu/apple-dart.c
392
writel(stream_map->sidmap[i],
drivers/iommu/apple-dart.c
394
writel(command, stream_map->dart->regs + DART_T8020_STREAM_COMMAND);
drivers/iommu/apple-dart.c
427
writel(val, dart->regs + DART_T8110_TLB_CMD);
drivers/iommu/apple-dart.c
486
writel(U32_MAX, dart->regs + dart->hw->enable_streams + 4 * i);
drivers/iommu/apple-dart.c
489
writel(readl(dart->regs + dart->hw->error), dart->regs + dart->hw->error);
drivers/iommu/apple-dart.c
492
writel(0, dart->regs + DART_T8110_ERROR_MASK);
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
2137
writel(gerror, smmu->base + ARM_SMMU_GERRORN);
drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c
1162
writel(0, REG_VINTF(vintf, SID_MATCH(vsid->idx)));
drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c
1163
writel(0, REG_VINTF(vintf, SID_REPLACE(vsid->idx)));
drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c
1191
writel(stream->id, REG_VINTF(vintf, SID_REPLACE(sidx)));
drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c
1192
writel(virt_sid << 1 | 0x1, REG_VINTF(vintf, SID_MATCH(sidx)));
drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c
242
writel(regval, addr_config);
drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c
325
writel(gerror, REG_VCMDQ_PAGE0(vcmdq, GERRORN));
drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c
467
writel(gerror, REG_VCMDQ_PAGE0(vcmdq, GERRORN));
drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c
505
writel(regval & ~CMDQV_CMDQ_ALLOCATED,
drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c
524
writel(0, REG_VINTF(vintf, SID_MATCH(sidx)));
drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c
525
writel(0, REG_VINTF(vintf, SID_REPLACE(sidx)));
drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c
535
writel(regval | CMDQV_CMDQ_ALLOCATED,
drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c
557
writel(regval, REG_VINTF(vintf, CONFIG));
drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c
917
writel(regval & ~CMDQV_EN, base + TEGRA241_CMDQV_CONFIG);
drivers/iommu/exynos-iommu.c
430
writel(CTRL_ENABLE, data->sfrbase + REG_MMU_CTRL);
drivers/iommu/exynos-iommu.c
437
writel(CTRL_BLOCK, data->sfrbase + REG_MMU_CTRL);
drivers/iommu/exynos-iommu.c
451
writel(0x1, SYSMMU_REG(data, flush_all));
drivers/iommu/exynos-iommu.c
461
writel((iova & SPAGE_MASK) | 1,
drivers/iommu/exynos-iommu.c
466
writel(iova & SPAGE_MASK, SYSMMU_REG(data, flush_start));
drivers/iommu/exynos-iommu.c
467
writel((iova & SPAGE_MASK) + (num_inv - 1) * SPAGE_SIZE,
drivers/iommu/exynos-iommu.c
469
writel(0x1, SYSMMU_REG(data, flush_range));
drivers/iommu/exynos-iommu.c
482
writel(pt_base, SYSMMU_REG(data, pt_base));
drivers/iommu/exynos-iommu.c
595
writel(1 << itype, SYSMMU_REG(data, int_clear));
drivers/iommu/exynos-iommu.c
612
writel(CTRL_DISABLE, data->sfrbase + REG_MMU_CTRL);
drivers/iommu/exynos-iommu.c
613
writel(0, data->sfrbase + REG_MMU_CFG);
drivers/iommu/exynos-iommu.c
633
writel(cfg, data->sfrbase + REG_MMU_CFG);
drivers/iommu/exynos-iommu.c
645
writel(ctrl, data->sfrbase + REG_V7_CTRL_VM);
drivers/iommu/exynos-iommu.c
655
writel(CTRL_BLOCK, data->sfrbase + REG_MMU_CTRL);
drivers/iommu/exynos-iommu.c
659
writel(CTRL_ENABLE, data->sfrbase + REG_MMU_CTRL);
drivers/iommu/intel/dmar.c
1304
writel(DMA_FSTS_IQE, iommu->reg + DMAR_FSTS_REG);
drivers/iommu/intel/dmar.c
1327
writel(DMA_FSTS_ITE, iommu->reg + DMAR_FSTS_REG);
drivers/iommu/intel/dmar.c
1354
writel(DMA_FSTS_ICE, iommu->reg + DMAR_FSTS_REG);
drivers/iommu/intel/dmar.c
1445
writel(qi->free_head << shift, iommu->reg + DMAR_IQT_REG);
drivers/iommu/intel/dmar.c
1631
writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
drivers/iommu/intel/dmar.c
1662
writel(0, iommu->reg + DMAR_IQT_REG);
drivers/iommu/intel/dmar.c
1667
writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
drivers/iommu/intel/dmar.c
1865
writel(0, iommu->reg + reg);
drivers/iommu/intel/dmar.c
1879
writel(DMA_FECTL_IM, iommu->reg + reg);
drivers/iommu/intel/dmar.c
1892
writel(msg->data, iommu->reg + reg + 4);
drivers/iommu/intel/dmar.c
1893
writel(msg->address_lo, iommu->reg + reg + 8);
drivers/iommu/intel/dmar.c
1894
writel(msg->address_hi, iommu->reg + reg + 12);
drivers/iommu/intel/dmar.c
1989
writel(DMA_FRCD_F, iommu->reg + reg +
drivers/iommu/intel/dmar.c
2006
writel(DMA_FSTS_PFO | DMA_FSTS_PPF | DMA_FSTS_PRO,
drivers/iommu/intel/dmar.c
2067
writel(fault_status, iommu->reg + DMAR_FSTS_REG);
drivers/iommu/intel/iommu.c
1870
writel(iommu->iommu_state[SR_DMAR_FECTL_REG],
drivers/iommu/intel/iommu.c
1872
writel(iommu->iommu_state[SR_DMAR_FEDATA_REG],
drivers/iommu/intel/iommu.c
1874
writel(iommu->iommu_state[SR_DMAR_FEADDR_REG],
drivers/iommu/intel/iommu.c
1876
writel(iommu->iommu_state[SR_DMAR_FEUADDR_REG],
drivers/iommu/intel/iommu.c
702
writel(iommu->gcmd | DMA_GCMD_SRTP, iommu->reg + DMAR_GCMD_REG);
drivers/iommu/intel/iommu.c
732
writel(iommu->gcmd | DMA_GCMD_WBF, iommu->reg + DMAR_GCMD_REG);
drivers/iommu/intel/iommu.c
936
writel(pmen, iommu->reg + DMAR_PMEN_REG);
drivers/iommu/intel/iommu.c
952
writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
drivers/iommu/intel/iommu.c
972
writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
drivers/iommu/intel/iommu.h
154
#define dmar_writel(a, v) writel(v, a)
drivers/iommu/intel/irq_remapping.c
472
writel(iommu->gcmd | DMA_GCMD_SIRTP, iommu->reg + DMAR_GCMD_REG);
drivers/iommu/intel/irq_remapping.c
495
writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
drivers/iommu/intel/irq_remapping.c
502
writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
drivers/iommu/intel/irq_remapping.c
666
writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
drivers/iommu/intel/prq.c
209
writel(DMA_PRS_PPR, iommu->reg + DMAR_PRS_REG);
drivers/iommu/intel/prq.c
275
writel(DMA_PRS_PRO, iommu->reg + DMAR_PRS_REG);
drivers/iommu/msm_iommu_hw-8xxx.h
14
#define SET_GLOBAL_REG(reg, base, val) writel((val), ((base) + (reg)))
drivers/iommu/msm_iommu_hw-8xxx.h
17
writel((val), ((base) + (reg) + ((ctx) << CTX_SHIFT)))
drivers/iommu/msm_iommu_hw-8xxx.h
38
writel((t & ~((mask) << (shift))) + (((v) & (mask)) << (shift)), addr);\
drivers/iommu/mtk_iommu.c
1549
writel(m4u_dom->cfg.arm_v7s_cfg.ttbr, base + REG_MMU_PT_BASE_ADDR);
drivers/iommu/mtk_iommu.c
768
writel(dom->cfg.arm_v7s_cfg.ttbr, bank->base + REG_MMU_PT_BASE_ADDR);
drivers/iommu/mtk_iommu_v1.c
276
writel(dom->pgt_pa, data->base + REG_MMU_PT_BASE_ADDR);
drivers/iommu/rockchip-iommu.c
344
writel(value, base + offset);
drivers/iommu/rockchip-iommu.c
352
writel(command, iommu->bases[i] + RK_MMU_COMMAND);
drivers/iommu/rockchip-iommu.c
357
writel(command, base + RK_MMU_COMMAND);
drivers/iommu/sun50i-iommu.c
145
writel(value, iommu->base + offset);
drivers/iommu/tegra-smmu.c
78
writel(value, smmu->regs + offset);
drivers/irqchip/irq-aclint-sswi.c
24
writel(0x1, per_cpu(sswi_cpu_regs, cpu));
drivers/irqchip/irq-armada-370-xp.c
218
writel(hwirq, mpic->base + MPIC_INT_CLEAR_ENABLE);
drivers/irqchip/irq-armada-370-xp.c
220
writel(hwirq, mpic->per_cpu + MPIC_INT_SET_MASK);
drivers/irqchip/irq-armada-370-xp.c
229
writel(hwirq, mpic->base + MPIC_INT_SET_ENABLE);
drivers/irqchip/irq-armada-370-xp.c
231
writel(hwirq, mpic->per_cpu + MPIC_INT_CLEAR_MASK);
drivers/irqchip/irq-armada-370-xp.c
316
writel(reg, mpic->per_cpu + MPIC_IN_DRBEL_MASK);
drivers/irqchip/irq-armada-370-xp.c
319
writel(1, mpic->per_cpu + MPIC_INT_CLEAR_MASK);
drivers/irqchip/irq-armada-370-xp.c
369
writel(0, mpic->per_cpu + MPIC_INT_CLEAR_MASK);
drivers/irqchip/irq-armada-370-xp.c
397
writel(MPIC_INT_CAUSE_PERF(cpuid), mpic->per_cpu + MPIC_INT_FABRIC_MASK);
drivers/irqchip/irq-armada-370-xp.c
408
writel(reg, mpic->per_cpu + MPIC_IN_DRBEL_MASK);
drivers/irqchip/irq-armada-370-xp.c
418
writel(reg, mpic->per_cpu + MPIC_IN_DRBEL_MASK);
drivers/irqchip/irq-armada-370-xp.c
438
writel((map << 8) | d->hwirq, mpic->base + MPIC_SW_TRIG_INT);
drivers/irqchip/irq-armada-370-xp.c
445
writel(~BIT(d->hwirq), mpic->per_cpu + MPIC_IN_DRBEL_CAUSE);
drivers/irqchip/irq-armada-370-xp.c
532
writel(i, mpic->per_cpu + MPIC_INT_SET_MASK);
drivers/irqchip/irq-armada-370-xp.c
538
writel(0, mpic->per_cpu + MPIC_IN_DRBEL_MASK);
drivers/irqchip/irq-armada-370-xp.c
541
writel(0, mpic->per_cpu + MPIC_IN_DRBEL_CAUSE);
drivers/irqchip/irq-armada-370-xp.c
544
writel(0, mpic->per_cpu + MPIC_INT_CLEAR_MASK);
drivers/irqchip/irq-armada-370-xp.c
616
writel(hwirq, mpic->per_cpu + MPIC_INT_CLEAR_MASK);
drivers/irqchip/irq-armada-370-xp.c
618
writel(hwirq, mpic->base + MPIC_INT_SET_ENABLE);
drivers/irqchip/irq-armada-370-xp.c
645
writel(~cause, mpic->per_cpu + MPIC_IN_DRBEL_CAUSE);
drivers/irqchip/irq-armada-370-xp.c
755
writel(i, mpic->per_cpu + MPIC_INT_CLEAR_MASK);
drivers/irqchip/irq-armada-370-xp.c
760
writel(i, mpic->base + MPIC_INT_SET_ENABLE);
drivers/irqchip/irq-armada-370-xp.c
772
writel(mpic->doorbell_mask, mpic->per_cpu + MPIC_IN_DRBEL_MASK);
drivers/irqchip/irq-armada-370-xp.c
783
writel(0, mpic->per_cpu + MPIC_INT_CLEAR_MASK);
drivers/irqchip/irq-armada-370-xp.c
785
writel(1, mpic->per_cpu + MPIC_INT_CLEAR_MASK);
drivers/irqchip/irq-armada-370-xp.c
855
writel(i, mpic->base + MPIC_INT_CLEAR_ENABLE);
drivers/irqchip/irq-aspeed-intc.c
102
writel(0xffffffff, intc_ic->base + INTC_INT_STATUS_REG);
drivers/irqchip/irq-aspeed-intc.c
103
writel(0x0, intc_ic->base + INTC_INT_ENABLE_REG);
drivers/irqchip/irq-aspeed-intc.c
42
writel(BIT(bit), intc_ic->base + INTC_INT_STATUS_REG);
drivers/irqchip/irq-aspeed-intc.c
55
writel(mask, intc_ic->base + INTC_INT_ENABLE_REG);
drivers/irqchip/irq-aspeed-intc.c
64
writel(unmask, intc_ic->base + INTC_INT_ENABLE_REG);
drivers/irqchip/irq-aspeed-scu-ic.c
122
writel(BIT(bit), scu_ic->base + scu_ic->isr);
drivers/irqchip/irq-aspeed-scu-ic.c
139
writel(readl(scu_ic->base) & ~mask, scu_ic->base);
drivers/irqchip/irq-aspeed-scu-ic.c
153
writel((readl(scu_ic->base) & ~mask) | bit, scu_ic->base);
drivers/irqchip/irq-aspeed-scu-ic.c
161
writel(readl(scu_ic->base) & ~mask, scu_ic->base + scu_ic->ier);
drivers/irqchip/irq-aspeed-scu-ic.c
169
writel(readl(scu_ic->base) | bit, scu_ic->base + scu_ic->ier);
drivers/irqchip/irq-aspeed-scu-ic.c
223
writel(AST2700_SCU_IC_STATUS, scu_ic->base + scu_ic->isr);
drivers/irqchip/irq-aspeed-scu-ic.c
224
writel(0, scu_ic->base + scu_ic->ier);
drivers/irqchip/irq-aspeed-scu-ic.c
226
writel(ASPEED_SCU_IC_STATUS, scu_ic->base);
drivers/irqchip/irq-aspeed-scu-ic.c
227
writel(0, scu_ic->base);
drivers/irqchip/irq-aspeed-scu-ic.c
95
writel((readl(scu_ic->base) & ~mask) | BIT(bit + ASPEED_SCU_IC_STATUS_SHIFT),
drivers/irqchip/irq-aspeed-vic.c
115
writel(sbit, vic->base + AVIC_EDGE_CLR + sidx * 4);
drivers/irqchip/irq-aspeed-vic.c
124
writel(sbit, vic->base + AVIC_INT_ENABLE_CLR + sidx * 4);
drivers/irqchip/irq-aspeed-vic.c
133
writel(sbit, vic->base + AVIC_INT_ENABLE + sidx * 4);
drivers/irqchip/irq-aspeed-vic.c
144
writel(sbit, vic->base + AVIC_INT_ENABLE_CLR + sidx * 4);
drivers/irqchip/irq-aspeed-vic.c
148
writel(sbit, vic->base + AVIC_EDGE_CLR + sidx * 4);
drivers/irqchip/irq-aspeed-vic.c
63
writel(0xffffffff, vic->base + AVIC_INT_ENABLE_CLR);
drivers/irqchip/irq-aspeed-vic.c
64
writel(0xffffffff, vic->base + AVIC_INT_ENABLE_CLR + 4);
drivers/irqchip/irq-aspeed-vic.c
67
writel(0xffffffff, vic->base + AVIC_INT_TRIGGER_CLR);
drivers/irqchip/irq-aspeed-vic.c
68
writel(0xffffffff, vic->base + AVIC_INT_TRIGGER_CLR + 4);
drivers/irqchip/irq-aspeed-vic.c
71
writel(0, vic->base + AVIC_INT_SELECT);
drivers/irqchip/irq-aspeed-vic.c
72
writel(0, vic->base + AVIC_INT_SELECT + 4);
drivers/irqchip/irq-aspeed-vic.c
84
writel(0xffffffff, vic->base + AVIC_EDGE_CLR);
drivers/irqchip/irq-aspeed-vic.c
85
writel(0xffffffff, vic->base + AVIC_EDGE_CLR + 4);
drivers/irqchip/irq-atmel-aic-common.c
157
writel(AT91_RTC_IRQ_MASK, regs + AT91_RTC_IDR);
drivers/irqchip/irq-atmel-aic-common.c
180
writel(readl(regs + AT91_RTT_MR) &
drivers/irqchip/irq-bcm2712-mip.c
190
writel(0, mip->base + MIP_INT_MASKL_HOST);
drivers/irqchip/irq-bcm2712-mip.c
191
writel(0, mip->base + MIP_INT_MASKH_HOST);
drivers/irqchip/irq-bcm2712-mip.c
192
writel(~0, mip->base + MIP_INT_MASKL_VPU);
drivers/irqchip/irq-bcm2712-mip.c
193
writel(~0, mip->base + MIP_INT_MASKH_VPU);
drivers/irqchip/irq-bcm2712-mip.c
194
writel(~0, mip->base + MIP_INT_CFGL_HOST);
drivers/irqchip/irq-bcm2712-mip.c
195
writel(~0, mip->base + MIP_INT_CFGH_HOST);
drivers/irqchip/irq-bcm2836.c
309
writel(0, intc.base + LOCAL_CONTROL);
drivers/irqchip/irq-bcm2836.c
31
writel(readl(reg) & ~BIT(bit), reg);
drivers/irqchip/irq-bcm2836.c
315
writel(0x80000000, intc.base + LOCAL_PRESCALER);
drivers/irqchip/irq-bcm2836.c
40
writel(readl(reg) | BIT(bit), reg);
drivers/irqchip/irq-bcm2836.c
66
writel(1 << smp_processor_id(), intc.base + LOCAL_PM_ROUTING_CLR);
drivers/irqchip/irq-bcm2836.c
71
writel(1 << smp_processor_id(), intc.base + LOCAL_PM_ROUTING_SET);
drivers/irqchip/irq-bcm7038-l1.c
110
writel(val, reg);
drivers/irqchip/irq-brcmstb-l2.c
166
writel(0xffffffff, base + init_params->cpu_mask_set);
drivers/irqchip/irq-brcmstb-l2.c
171
writel(0xffffffff, base + init_params->cpu_clear);
drivers/irqchip/irq-crossbar.c
47
writel(cb_no, cb->crossbar_base + cb->register_offsets[irq_no]);
drivers/irqchip/irq-csky-apb-intc.c
174
writel(0x0, reg_base + GX_INTC_NEN31_00);
drivers/irqchip/irq-csky-apb-intc.c
175
writel(0x0, reg_base + GX_INTC_NEN63_32);
drivers/irqchip/irq-csky-apb-intc.c
180
writel(0x0, reg_base + GX_INTC_NMASK31_00);
drivers/irqchip/irq-csky-apb-intc.c
181
writel(0x0, reg_base + GX_INTC_NMASK63_32);
drivers/irqchip/irq-csky-apb-intc.c
239
writel(0, reg_base + CK_INTC_NEN31_00);
drivers/irqchip/irq-csky-apb-intc.c
240
writel(0, reg_base + CK_INTC_NEN63_32);
drivers/irqchip/irq-csky-apb-intc.c
243
writel(BIT(31), reg_base + CK_INTC_ICR);
drivers/irqchip/irq-csky-apb-intc.c
269
writel(0, reg_base + CK_INTC_NEN31_00 + CK_INTC_DUAL_BASE);
drivers/irqchip/irq-csky-apb-intc.c
270
writel(0, reg_base + CK_INTC_NEN63_32 + CK_INTC_DUAL_BASE);
drivers/irqchip/irq-csky-apb-intc.c
97
writel(build_channel_val(i, magic), reg_addr + i);
drivers/irqchip/irq-digicolor.c
86
writel(0, reg_base + IC_INT0ENABLE_LO);
drivers/irqchip/irq-digicolor.c
87
writel(0, reg_base + IC_INT0ENABLE_XLO);
drivers/irqchip/irq-ftintc010.c
111
writel(mode, FT010_IRQ_MODE(f->base));
drivers/irqchip/irq-ftintc010.c
112
writel(polarity, FT010_IRQ_POLARITY(f->base));
drivers/irqchip/irq-ftintc010.c
180
writel(0, FT010_IRQ_MASK(f->base));
drivers/irqchip/irq-ftintc010.c
181
writel(0, FT010_FIQ_MASK(f->base));
drivers/irqchip/irq-ftintc010.c
60
writel(mask, FT010_IRQ_MASK(f->base));
drivers/irqchip/irq-ftintc010.c
70
writel(mask, FT010_IRQ_MASK(f->base));
drivers/irqchip/irq-ftintc010.c
77
writel(BIT(irqd_to_hwirq(d)), FT010_IRQ_CLEAR(f->base));
drivers/irqchip/irq-goldfish-pic.c
85
writel(1, gfpic->base + GFPIC_REG_IRQ_DISABLE_ALL);
drivers/irqchip/irq-idt3243x.c
101
writel(0xffffffff, idtpic->base + IDT_PIC_IRQ_MASK);
drivers/irqchip/irq-loongson-htpic.c
38
writel(pending, priv->base);
drivers/irqchip/irq-loongson-htpic.c
63
writel(0x0, htpic->base + HTINT_EN_OFF + i * 0x4);
drivers/irqchip/irq-loongson-htpic.c
67
writel(GENMASK(31, 0), htpic->base + i * 0x4);
drivers/irqchip/irq-loongson-htpic.c
71
writel(0xffff, htpic->base + HTINT_EN_OFF);
drivers/irqchip/irq-loongson-htvec.c
101
writel(reg, addr);
drivers/irqchip/irq-loongson-htvec.c
177
writel(htvec_priv->saved_vec_en[i], htvec_priv->base + HTVEC_EN_OFF + 4 * i);
drivers/irqchip/irq-loongson-htvec.c
71
writel(BIT(VEC_REG_BIT(d->hwirq)),
drivers/irqchip/irq-loongson-htvec.c
86
writel(reg, addr);
drivers/irqchip/irq-loongson-liointc.c
108
writel(readl(gc->reg_base + offset) | mask,
drivers/irqchip/irq-loongson-liointc.c
111
writel(readl(gc->reg_base + offset) & ~mask,
drivers/irqchip/irq-loongson-liointc.c
161
writel(0xffffffff, gc->reg_base + LIOINTC_REG_INTC_DISABLE);
drivers/irqchip/irq-loongson-liointc.c
165
writel(priv->int_pol, gc->reg_base + LIOINTC_REG_INTC_POL);
drivers/irqchip/irq-loongson-liointc.c
166
writel(priv->int_edge, gc->reg_base + LIOINTC_REG_INTC_EDGE);
drivers/irqchip/irq-loongson-liointc.c
168
writel(gc->mask_cache, gc->reg_base + LIOINTC_REG_INTC_ENABLE);
drivers/irqchip/irq-loongson-liointc.c
259
writel(0xffffffff, base + LIOINTC_REG_INTC_DISABLE);
drivers/irqchip/irq-loongson-liointc.c
261
writel(0x0, base + LIOINTC_REG_INTC_EDGE);
drivers/irqchip/irq-loongson-pch-lpc.c
142
writel(LPC_INT_CTL_EN, priv->base + LPC_INT_CTL);
drivers/irqchip/irq-loongson-pch-lpc.c
143
writel(0, priv->base + LPC_INT_ENA);
drivers/irqchip/irq-loongson-pch-lpc.c
145
writel(GENMASK(17, 0), priv->base + LPC_INT_CLR);
drivers/irqchip/irq-loongson-pch-lpc.c
164
writel(pch_lpc_priv->saved_reg_ctl, pch_lpc_priv->base + LPC_INT_CTL);
drivers/irqchip/irq-loongson-pch-lpc.c
165
writel(pch_lpc_priv->saved_reg_ena, pch_lpc_priv->base + LPC_INT_ENA);
drivers/irqchip/irq-loongson-pch-lpc.c
166
writel(pch_lpc_priv->saved_reg_pol, pch_lpc_priv->base + LPC_INT_POL);
drivers/irqchip/irq-loongson-pch-lpc.c
49
writel(0x1 << d->hwirq, priv->base + LPC_INT_CLR);
drivers/irqchip/irq-loongson-pch-lpc.c
59
writel(readl(priv->base + LPC_INT_ENA) & (~(0x1 << (d->hwirq))),
drivers/irqchip/irq-loongson-pch-lpc.c
70
writel(readl(priv->base + LPC_INT_ENA) | (0x1 << (d->hwirq)),
drivers/irqchip/irq-loongson-pch-lpc.c
91
writel(val, priv->base + LPC_INT_POL);
drivers/irqchip/irq-loongson-pch-pic.c
102
writel(BIT(PIC_REG_BIT(bit)),
drivers/irqchip/irq-loongson-pch-pic.c
152
writel(BIT(PIC_REG_BIT(bit)),
drivers/irqchip/irq-loongson-pch-pic.c
306
writel(pch_pic_priv[i]->saved_vec_pol[j],
drivers/irqchip/irq-loongson-pch-pic.c
308
writel(pch_pic_priv[i]->saved_vec_edge[j],
drivers/irqchip/irq-loongson-pch-pic.c
310
writel(pch_pic_priv[i]->saved_vec_en[j],
drivers/irqchip/irq-loongson-pch-pic.c
73
writel(reg, addr);
drivers/irqchip/irq-loongson-pch-pic.c
85
writel(reg, addr);
drivers/irqchip/irq-ls1x.c
147
writel(0x0, priv->intc_base + LS_REG_INTC_EN);
drivers/irqchip/irq-ls1x.c
150
writel(0xffffffff, priv->intc_base + LS_REG_INTC_CLR);
drivers/irqchip/irq-ls1x.c
153
writel(0xffffffff, priv->intc_base + LS_REG_INTC_POL);
drivers/irqchip/irq-ls1x.c
65
writel(readl(gc->reg_base + offset) | mask,
drivers/irqchip/irq-ls1x.c
68
writel(readl(gc->reg_base + offset) & ~mask,
drivers/irqchip/irq-mvebu-gicp.c
245
writel(i, base + GICP_CLRSPI_NSR_OFFSET);
drivers/irqchip/irq-mvebu-pic.c
39
writel(0, pic->base + PIC_MASK);
drivers/irqchip/irq-mvebu-pic.c
40
writel(PIC_MAX_IRQ_MASK, pic->base + PIC_CAUSE);
drivers/irqchip/irq-mvebu-pic.c
47
writel(1 << d->hwirq, pic->base + PIC_CAUSE);
drivers/irqchip/irq-mvebu-pic.c
57
writel(reg, pic->base + PIC_MASK);
drivers/irqchip/irq-mvebu-pic.c
67
writel(reg, pic->base + PIC_MASK);
drivers/irqchip/irq-mxs.c
233
writel(0, icoll_priv.intr + i);
drivers/irqchip/irq-orion.c
196
writel(0, gc->reg_base + ORION_BRIDGE_IRQ_MASK);
drivers/irqchip/irq-orion.c
197
writel(0, gc->reg_base + ORION_BRIDGE_IRQ_CAUSE);
drivers/irqchip/irq-orion.c
94
writel(0, gc->reg_base + ORION_IRQ_MASK);
drivers/irqchip/irq-pic32-evic.c
102
writel(set, evic_base + REG_OFF_OFFSET + irq * 4);
drivers/irqchip/irq-pic32-evic.c
112
writel(PRIORITY_MASK << shift,
drivers/irqchip/irq-pic32-evic.c
114
writel(priority << shift,
drivers/irqchip/irq-pic32-evic.c
155
writel(mask, evic_base + iecclr);
drivers/irqchip/irq-pic32-evic.c
156
writel(mask, evic_base + ifsclr);
drivers/irqchip/irq-pic32-evic.c
64
writel(BIT(bit), evic_base + PIC32_SET(REG_INTCON));
drivers/irqchip/irq-pic32-evic.c
67
writel(BIT(bit), evic_base + PIC32_CLR(REG_INTCON));
drivers/irqchip/irq-realtek-rtl.c
138
writel(0, REG(RTL_ICTL_GIMR));
drivers/irqchip/irq-realtek-rtl.c
48
writel(irr, irr0 + offset);
drivers/irqchip/irq-realtek-rtl.c
60
writel(value, REG(RTL_ICTL_GIMR));
drivers/irqchip/irq-realtek-rtl.c
74
writel(value, REG(RTL_ICTL_GIMR));
drivers/irqchip/irq-renesas-rzt2h.c
77
writel(val, priv->base_ns + RZT2H_ICU_DMACn_RSSELi(dmac_index, y));
drivers/irqchip/irq-renesas-rzv2h.c
161
writel(icu_dmksely, priv->base + ICU_DMkSELy(dmac_index, y));
drivers/irqchip/irq-riscv-aplic-direct.c
169
writel(th, idc->regs + APLIC_IDC_ITHRESHOLD);
drivers/irqchip/irq-riscv-aplic-direct.c
172
writel(de, idc->regs + APLIC_IDC_IDELIVERY);
drivers/irqchip/irq-riscv-aplic-direct.c
296
writel(v, priv->regs + APLIC_TARGET_BASE + (j - 1) * sizeof(u32));
drivers/irqchip/irq-riscv-aplic-direct.c
73
writel(val, target);
drivers/irqchip/irq-riscv-aplic-main.c
192
writel(d->hwirq, priv->regs + APLIC_SETIENUM);
drivers/irqchip/irq-riscv-aplic-main.c
199
writel(d->hwirq, priv->regs + APLIC_CLRIENUM);
drivers/irqchip/irq-riscv-aplic-main.c
230
writel(val, sourcecfg);
drivers/irqchip/irq-riscv-aplic-main.c
268
writel(val, priv->regs + APLIC_xMSICFGADDR);
drivers/irqchip/irq-riscv-aplic-main.c
269
writel(valh, priv->regs + APLIC_xMSICFGADDRH);
drivers/irqchip/irq-riscv-aplic-main.c
280
writel(val, priv->regs + APLIC_DOMAINCFG);
drivers/irqchip/irq-riscv-aplic-main.c
293
writel(-1U, priv->regs + APLIC_CLRIE_BASE + (i / 32) * sizeof(u32));
drivers/irqchip/irq-riscv-aplic-main.c
297
writel(0, priv->regs + APLIC_SOURCECFG_BASE + (i - 1) * sizeof(u32));
drivers/irqchip/irq-riscv-aplic-main.c
298
writel(APLIC_DEFAULT_PRIORITY,
drivers/irqchip/irq-riscv-aplic-main.c
303
writel(0, priv->regs + APLIC_DOMAINCFG);
drivers/irqchip/irq-riscv-aplic-main.c
32
writel(saved_regs->domaincfg, regs + APLIC_DOMAINCFG);
drivers/irqchip/irq-riscv-aplic-main.c
34
writel(saved_regs->msiaddr, regs + APLIC_xMSICFGADDR);
drivers/irqchip/irq-riscv-aplic-main.c
35
writel(saved_regs->msiaddrh, regs + APLIC_xMSICFGADDRH);
drivers/irqchip/irq-riscv-aplic-main.c
47
writel(srcs->sourcecfg, regs + APLIC_SOURCECFG_BASE + i * sizeof(u32));
drivers/irqchip/irq-riscv-aplic-main.c
48
writel(srcs->target, regs + APLIC_TARGET_BASE + i * sizeof(u32));
drivers/irqchip/irq-riscv-aplic-main.c
53
writel(-1U, regs + APLIC_CLRIE_BASE + (i / 32) * sizeof(u32));
drivers/irqchip/irq-riscv-aplic-main.c
54
writel(srcs->ie, regs + APLIC_SETIE_BASE + (i / 32) * sizeof(u32));
drivers/irqchip/irq-riscv-aplic-main.c
58
writel(readl(regs + APLIC_CLRIP_BASE + (i / 32) * sizeof(u32)),
drivers/irqchip/irq-riscv-aplic-msi.c
128
writel(val, target);
drivers/irqchip/irq-riscv-aplic-msi.c
52
writel(d->hwirq, priv->regs + APLIC_SETIPNUM_LE);
drivers/irqchip/irq-riscv-aplic-msi.c
92
writel(0, target);
drivers/irqchip/irq-riscv-imsic-early.c
41
writel(IMSIC_IPI_ID, local->msi_va);
drivers/irqchip/irq-sg2042-msi.c
105
writel(0, (u32 __iomem *)data->reg_clr + d->hwirq);
drivers/irqchip/irq-sg2042-msi.c
74
writel(1 << bit_off, data->reg_clr);
drivers/irqchip/irq-sifive-plic.c
123
writel(value, base + group);
drivers/irqchip/irq-sifive-plic.c
151
writel(1, priv->regs + PRIORITY_BASE + d->hwirq * PRIORITY_PER_ID);
drivers/irqchip/irq-sifive-plic.c
158
writel(0, priv->regs + PRIORITY_BASE + d->hwirq * PRIORITY_PER_ID);
drivers/irqchip/irq-sifive-plic.c
183
writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM);
drivers/irqchip/irq-sifive-plic.c
186
writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM);
drivers/irqchip/irq-sifive-plic.c
292
writel((priv->prio_save[index] & BIT_MASK(irq)) ? 1 : 0,
drivers/irqchip/irq-sifive-plic.c
305
writel(handler->enable_save[i], reg);
drivers/irqchip/irq-sifive-plic.c
500
writel(threshold, handler->hart_base + CONTEXT_THRESHOLD);
drivers/irqchip/irq-sifive-plic.c
705
writel(0, enable_base + j);
drivers/irqchip/irq-sifive-plic.c
745
writel(1, priv->regs + PRIORITY_BASE + hwirq * PRIORITY_PER_ID);
drivers/irqchip/irq-sni-exiu.c
44
writel(BIT(d->hwirq), data->base + EIREQCLR);
drivers/irqchip/irq-sni-exiu.c
58
writel(BIT(d->hwirq), data->base + EIREQCLR);
drivers/irqchip/irq-sun4i.c
116
writel(0, irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(irq_ic_data, 0));
drivers/irqchip/irq-sun4i.c
117
writel(0, irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(irq_ic_data, 1));
drivers/irqchip/irq-sun4i.c
118
writel(0, irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(irq_ic_data, 2));
drivers/irqchip/irq-sun4i.c
121
writel(0, irq_ic_data->irq_base + SUN4I_IRQ_MASK_REG(irq_ic_data, 0));
drivers/irqchip/irq-sun4i.c
122
writel(0, irq_ic_data->irq_base + SUN4I_IRQ_MASK_REG(irq_ic_data, 1));
drivers/irqchip/irq-sun4i.c
123
writel(0, irq_ic_data->irq_base + SUN4I_IRQ_MASK_REG(irq_ic_data, 2));
drivers/irqchip/irq-sun4i.c
126
writel(0xffffffff, irq_ic_data->irq_base + SUN4I_IRQ_PENDING_REG(0));
drivers/irqchip/irq-sun4i.c
127
writel(0xffffffff, irq_ic_data->irq_base + SUN4I_IRQ_PENDING_REG(1));
drivers/irqchip/irq-sun4i.c
128
writel(0xffffffff, irq_ic_data->irq_base + SUN4I_IRQ_PENDING_REG(2));
drivers/irqchip/irq-sun4i.c
131
writel(0x01, irq_ic_data->irq_base + SUN4I_IRQ_PROTECTION_REG);
drivers/irqchip/irq-sun4i.c
134
writel(0x00, irq_ic_data->irq_base + SUN4I_IRQ_NMI_CTRL_REG);
drivers/irqchip/irq-sun4i.c
56
writel(BIT(0), irq_ic_data->irq_base + SUN4I_IRQ_PENDING_REG(0));
drivers/irqchip/irq-sun4i.c
68
writel(val & ~(1 << irq_off),
drivers/irqchip/irq-sun4i.c
81
writel(val | (1 << irq_off),
drivers/irqchip/irq-versatile-fpga.c
221
writel(clear_mask, base + IRQ_ENABLE_CLEAR);
drivers/irqchip/irq-versatile-fpga.c
222
writel(clear_mask, base + FIQ_ENABLE_CLEAR);
drivers/irqchip/irq-versatile-fpga.c
239
writel(0xffd00000, base + PIC_ENABLES);
drivers/irqchip/irq-versatile-fpga.c
57
writel(mask, f->base + IRQ_ENABLE_CLEAR);
drivers/irqchip/irq-versatile-fpga.c
65
writel(mask, f->base + IRQ_ENABLE_SET);
drivers/irqchip/irq-vic.c
110
writel(vic->int_select, base + VIC_INT_SELECT);
drivers/irqchip/irq-vic.c
111
writel(vic->protect, base + VIC_PROTECT);
drivers/irqchip/irq-vic.c
114
writel(vic->int_enable, base + VIC_INT_ENABLE);
drivers/irqchip/irq-vic.c
115
writel(~vic->int_enable, base + VIC_INT_ENABLE_CLEAR);
drivers/irqchip/irq-vic.c
119
writel(vic->soft_int, base + VIC_INT_SOFT);
drivers/irqchip/irq-vic.c
120
writel(~vic->soft_int, base + VIC_INT_SOFT_CLEAR);
drivers/irqchip/irq-vic.c
145
writel(vic->resume_irqs, base + VIC_INT_ENABLE);
drivers/irqchip/irq-vic.c
146
writel(~vic->resume_irqs, base + VIC_INT_ENABLE_CLEAR);
drivers/irqchip/irq-vic.c
314
writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
drivers/irqchip/irq-vic.c
316
writel(1 << irq, base + VIC_INT_SOFT_CLEAR);
drivers/irqchip/irq-vic.c
323
writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
drivers/irqchip/irq-vic.c
330
writel(1 << irq, base + VIC_INT_ENABLE);
drivers/irqchip/irq-vic.c
381
writel(0, base + VIC_INT_SELECT);
drivers/irqchip/irq-vic.c
382
writel(0, base + VIC_INT_ENABLE);
drivers/irqchip/irq-vic.c
383
writel(~0, base + VIC_INT_ENABLE_CLEAR);
drivers/irqchip/irq-vic.c
384
writel(0, base + VIC_ITCR);
drivers/irqchip/irq-vic.c
385
writel(~0, base + VIC_INT_SOFT_CLEAR);
drivers/irqchip/irq-vic.c
392
writel(0, base + VIC_PL190_VECT_ADDR);
drivers/irqchip/irq-vic.c
397
writel(value, base + VIC_PL190_VECT_ADDR);
drivers/irqchip/irq-vic.c
429
writel(0, reg);
drivers/irqchip/irq-vic.c
432
writel(32, base + VIC_PL190_DEF_VECT_ADDR);
drivers/irqchip/irq-vic.c
94
writel(VIC_VECT_CNTL_ENABLE | i, reg);
drivers/irqchip/irq-vic.c
97
writel(32, base + VIC_PL190_DEF_VECT_ADDR);
drivers/irqchip/irq-vt8500.c
145
writel(ICPC_ROTATE, base + VT8500_ICPC_IRQ);
drivers/irqchip/irq-vt8500.c
146
writel(0x00, base + VT8500_ICPC_FIQ);
drivers/irqchip/irq-vt8500.c
77
writel(status, stat_reg);
drivers/irqchip/irq-wpcm450-aic.c
48
writel(0xffffffff, aic->regs + AIC_MDCR);
drivers/irqchip/irq-wpcm450-aic.c
56
writel(0, aic->regs + AIC_EOSCR);
drivers/irqchip/irq-wpcm450-aic.c
60
writel(AIC_SCR_SRCTYPE_HIGH_LEVEL | AIC_SCR_PRIORITY(7),
drivers/irqchip/irq-wpcm450-aic.c
78
writel(0, aic->regs + AIC_EOSCR);
drivers/irqchip/irq-wpcm450-aic.c
86
writel(mask, aic->regs + AIC_MDCR);
drivers/irqchip/irq-wpcm450-aic.c
94
writel(mask, aic->regs + AIC_MECR);
drivers/irqchip/irq-zevio.c
60
writel(~0, base + IO_DISABLE);
drivers/irqchip/irq-zevio.c
63
writel(0xF, base + IO_MAX_PRIOTY);
drivers/irqchip/irq-zevio.c
83
writel(~0, zevio_irq_io + IO_INVERT_SEL);
drivers/irqchip/irq-zevio.c
86
writel(0, zevio_irq_io + IO_STICKY_SEL);
drivers/irqchip/spear-shirq.c
66
writel(val, reg);
drivers/irqchip/spear-shirq.c
78
writel(val, reg);
drivers/isdn/hardware/mISDN/hfcmulti.c
1034
writel(PLX_GPIOC_INIT, plx_acc_32);
drivers/isdn/hardware/mISDN/hfcmulti.c
1044
writel(pv, plx_acc_32);
drivers/isdn/hardware/mISDN/hfcmulti.c
1167
writel(PLX_GPIOC_INIT, plx_acc_32);
drivers/isdn/hardware/mISDN/hfcmulti.c
1177
writel(pv, plx_acc_32);
drivers/isdn/hardware/mISDN/hfcmulti.c
1205
writel(pv, plx_acc_32);
drivers/isdn/hardware/mISDN/hfcmulti.c
1280
writel(pv, plx_acc_32);
drivers/isdn/hardware/mISDN/hfcmulti.c
1386
writel(pv, plx_acc_32);
drivers/isdn/hardware/mISDN/hfcmulti.c
1421
writel(pv, plx_acc_32);
drivers/isdn/hardware/mISDN/hfcmulti.c
473
writel(cpu_to_le32(*(u32 *)data),
drivers/isdn/hardware/mISDN/hfcmulti.c
917
writel(pv, plx_acc_32);
drivers/isdn/hardware/mISDN/hfcmulti.c
939
writel(pv, plx_acc_32);
drivers/isdn/hardware/mISDN/hfcmulti.c
970
writel(pv, plx_acc_32);
drivers/isdn/hardware/mISDN/mISDNinfineon.c
396
writel(PITA_INT0_ENABLE, hw->cfg.p);
drivers/isdn/hardware/mISDN/mISDNinfineon.c
440
writel(0, hw->cfg.p);
drivers/isdn/hardware/mISDN/mISDNinfineon.c
503
writel(PITA_PARA_SOFTRESET | PITA_PARA_MPX_MODE,
drivers/isdn/hardware/mISDN/mISDNinfineon.c
506
writel(PITA_PARA_MPX_MODE, hw->cfg.p + PITA_MISC_REG);
drivers/isdn/hardware/mISDN/mISDNinfineon.c
510
writel(PITA_PARA_SOFTRESET | PITA_PARA_MPX_MODE,
drivers/isdn/hardware/mISDN/mISDNinfineon.c
513
writel(PITA_PARA_MPX_MODE | PITA_SER_SOFTRESET,
drivers/leds/blink/leds-bcm63138.c
72
writel(data, leds->base + reg);
drivers/leds/leds-bcm6328.c
83
writel(data, reg);
drivers/leds/leds-bcm6358.c
51
writel(data, reg);
drivers/leds/leds-ip30.c
25
writel(value, led->reg);
drivers/leds/leds-sun50i-a100.c
135
writel(control, priv->base + LEDC_INT_CTRL_REG);
drivers/leds/leds-sun50i-a100.c
141
writel(control, priv->base + LEDC_INT_CTRL_REG);
drivers/leds/leds-sun50i-a100.c
163
writel(control, priv->base + LEDC_DMA_CTRL_REG);
drivers/leds/leds-sun50i-a100.c
168
writel(control, priv->base + LEDC_CTRL_REG);
drivers/leds/leds-sun50i-a100.c
210
writel(status, priv->base + LEDC_INT_STS_REG);
drivers/leds/leds-sun50i-a100.c
274
writel(control, priv->base + LEDC_CTRL_REG);
drivers/leds/leds-sun50i-a100.c
316
writel(control, priv->base + LEDC_T01_TIMING_CTRL_REG);
drivers/leds/leds-sun50i-a100.c
320
writel(control, priv->base + LEDC_RESET_TIMING_CTRL_REG);
drivers/leds/leds-sun50i-a100.c
343
writel(LEDC_INT_CTRL_REG_GLOBAL_INT_EN | LEDC_INT_CTRL_REG_TRANS_FINISH_INT_EN,
drivers/macintosh/smu.c
155
writel(smu->cmd_buf_abs, smu->db_buf);
drivers/mailbox/armada-37xx-rwtm-mailbox.c
119
writel(reg, mbox->base + RWTM_HOST_INT_MASK);
drivers/mailbox/armada-37xx-rwtm-mailbox.c
132
writel(reg, mbox->base + RWTM_HOST_INT_MASK);
drivers/mailbox/armada-37xx-rwtm-mailbox.c
70
writel(reg, mbox->base + RWTM_HOST_INT_RESET);
drivers/mailbox/armada-37xx-rwtm-mailbox.c
97
writel(msg->args[i], mbox->base + RWTM_MBOX_PARAM(i));
drivers/mailbox/armada-37xx-rwtm-mailbox.c
98
writel(msg->command, mbox->base + RWTM_MBOX_COMMAND);
drivers/mailbox/ast2700-mailbox.c
105
writel(word_data[i], data_reg + i * sizeof(u32));
drivers/mailbox/ast2700-mailbox.c
107
writel(BIT(idx), mb->tx_regs + IPCR_TX_TRIG);
drivers/mailbox/ast2700-mailbox.c
121
writel(readl(reg) | BIT(idx), reg);
drivers/mailbox/ast2700-mailbox.c
135
writel(readl(reg) & ~BIT(idx), reg);
drivers/mailbox/ast2700-mailbox.c
78
writel(RX_IRQ(n), mb->rx_regs + IPCR_STATUS);
drivers/mailbox/bcm2835-mailbox.c
106
writel(0, mbox->regs + MAIL0_CNF);
drivers/mailbox/bcm2835-mailbox.c
86
writel(msg, mbox->regs + MAIL1_WRT);
drivers/mailbox/bcm2835-mailbox.c
97
writel(ARM_MC_IHAVEDATAIRQEN, mbox->regs + MAIL0_CNF);
drivers/mailbox/exynos-mailbox.c
140
writel(EXYNOS_MBOX_INTMR0_MASK, exynos_mbox->regs + EXYNOS_MBOX_INTMR0);
drivers/mailbox/exynos-mailbox.c
60
writel(BIT(msg->chan_id), exynos_mbox->regs + EXYNOS_MBOX_INTGR1);
drivers/mailbox/hi3660-mailbox.c
107
writel(BIT(mchan->ack_irq), base + MBOX_ICLR_REG);
drivers/mailbox/hi3660-mailbox.c
118
writel(MBOX_IPC_UNLOCK, mbox->base + MBOX_IPC_LOCK_REG);
drivers/mailbox/hi3660-mailbox.c
144
writel(BIT(mchan->ack_irq), base + MBOX_SRC_REG);
drivers/mailbox/hi3660-mailbox.c
202
writel(BIT(mchan->ack_irq), base + MBOX_SEND_REG);
drivers/mailbox/hi6220-mailbox.c
107
writel(mode, mbox->base + MBOX_MODE_REG(slot));
drivers/mailbox/hi6220-mailbox.c
142
writel(buf[i], mbox->base + MBOX_DATA_REG(slot) + i * 4);
drivers/mailbox/hi6220-mailbox.c
145
writel(BIT(mchan->dst_irq), DST_INT_RAW_REG(mbox->ipc));
drivers/mailbox/hi6220-mailbox.c
187
writel(BIT(mchan->ack_irq), ACK_INT_CLR_REG(mbox->ipc));
drivers/mailbox/hi6220-mailbox.c
202
writel(BIT(mchan->ack_irq), ACK_INT_ENA_REG(mbox->ipc));
drivers/mailbox/hi6220-mailbox.c
212
writel(BIT(mchan->ack_irq), ACK_INT_DIS_REG(mbox->ipc));
drivers/mailbox/hi6220-mailbox.c
325
writel(0x0, ACK_INT_MSK_REG(mbox->ipc));
drivers/mailbox/hi6220-mailbox.c
326
writel(~0x0, ACK_INT_CLR_REG(mbox->ipc));
drivers/mailbox/hi6220-mailbox.c
97
writel(status, mbox->base + MBOX_MODE_REG(slot));
drivers/mailbox/mailbox-xgene-slimpro.c
141
writel(MBOX_STATUS_ACK_MASK | MBOX_STATUS_AVAIL_MASK,
drivers/mailbox/mailbox-xgene-slimpro.c
146
writel(val, mb_chan->reg + REG_DB_STATMASK);
drivers/mailbox/mailbox-xgene-slimpro.c
159
writel(val, mb_chan->reg + REG_DB_STATMASK);
drivers/mailbox/mailbox-xgene-slimpro.c
70
writel(msg[1], mb_chan->reg + REG_DB_DOUT0);
drivers/mailbox/mailbox-xgene-slimpro.c
71
writel(msg[2], mb_chan->reg + REG_DB_DOUT1);
drivers/mailbox/mailbox-xgene-slimpro.c
72
writel(msg[0], mb_chan->reg + REG_DB_OUT);
drivers/mailbox/mailbox-xgene-slimpro.c
87
writel(MBOX_STATUS_ACK_MASK, mb_chan->reg + REG_DB_STAT);
drivers/mailbox/mailbox-xgene-slimpro.c
99
writel(MBOX_STATUS_AVAIL_MASK, mb_chan->reg + REG_DB_STAT);
drivers/mailbox/mtk-adsp-mailbox.c
42
writel(op, priv->va_mboxreg + priv->cfg->clr_out);
drivers/mailbox/mtk-adsp-mailbox.c
67
writel(0xFFFFFFFF, priv->va_mboxreg + priv->cfg->clr_in);
drivers/mailbox/mtk-adsp-mailbox.c
68
writel(0xFFFFFFFF, priv->va_mboxreg + priv->cfg->clr_out);
drivers/mailbox/mtk-adsp-mailbox.c
78
writel(0xFFFFFFFF, priv->va_mboxreg + priv->cfg->clr_in);
drivers/mailbox/mtk-adsp-mailbox.c
79
writel(0xFFFFFFFF, priv->va_mboxreg + priv->cfg->clr_out);
drivers/mailbox/mtk-adsp-mailbox.c
87
writel(*msg, priv->va_mboxreg + priv->cfg->set_in);
drivers/mailbox/mtk-cmdq-mailbox.c
155
writel(vm_cpr_gsize, cmdq->base + GCE_VM_CPR_GSIZE);
drivers/mailbox/mtk-cmdq-mailbox.c
162
writel(vm_id_map, cmdq->base + GCE_VM_ID_MAP(i));
drivers/mailbox/mtk-cmdq-mailbox.c
168
writel(vm_id_map, cmdq->base + GCE_VM_ID_MAP(cmdq->pdata->thread_nr - 1));
drivers/mailbox/mtk-cmdq-mailbox.c
183
writel(val, cmdq->base + GCE_GCTL_VALUE);
drivers/mailbox/mtk-cmdq-mailbox.c
190
writel(CMDQ_THR_SUSPEND, thread->base + CMDQ_THR_SUSPEND_TASK);
drivers/mailbox/mtk-cmdq-mailbox.c
208
writel(CMDQ_THR_RESUME, thread->base + CMDQ_THR_SUSPEND_TASK);
drivers/mailbox/mtk-cmdq-mailbox.c
220
writel(CMDQ_THR_ACTIVE_SLOT_CYCLES, cmdq->base + CMDQ_THR_SLOT_CYCLES);
drivers/mailbox/mtk-cmdq-mailbox.c
222
writel(i, cmdq->base + CMDQ_SYNC_TOKEN_UPDATE);
drivers/mailbox/mtk-cmdq-mailbox.c
230
writel(CMDQ_THR_DO_WARM_RESET, thread->base + CMDQ_THR_WARM_RESET);
drivers/mailbox/mtk-cmdq-mailbox.c
245
writel(CMDQ_THR_DISABLED, thread->base + CMDQ_THR_ENABLE_TASK);
drivers/mailbox/mtk-cmdq-mailbox.c
251
writel(readl(thread->base + CMDQ_THR_CURR_ADDR),
drivers/mailbox/mtk-cmdq-mailbox.c
301
writel(next_task->pa_base >> cmdq->pdata->shift,
drivers/mailbox/mtk-cmdq-mailbox.c
315
writel(~irq_flag, thread->base + CMDQ_THR_IRQ_STATUS);
drivers/mailbox/mtk-cmdq-mailbox.c
479
writel(gce_addr, thread->base + CMDQ_THR_CURR_ADDR);
drivers/mailbox/mtk-cmdq-mailbox.c
481
writel(gce_addr, thread->base + CMDQ_THR_END_ADDR);
drivers/mailbox/mtk-cmdq-mailbox.c
483
writel(thread->priority, thread->base + CMDQ_THR_PRIORITY);
drivers/mailbox/mtk-cmdq-mailbox.c
484
writel(CMDQ_THR_IRQ_EN, thread->base + CMDQ_THR_IRQ_ENABLE);
drivers/mailbox/mtk-cmdq-mailbox.c
485
writel(CMDQ_THR_ENABLED, thread->base + CMDQ_THR_ENABLE_TASK);
drivers/mailbox/mtk-cmdq-mailbox.c
496
writel(task->pa_base >> cmdq->pdata->shift,
drivers/mailbox/mtk-cmdq-mailbox.c
502
writel((task->pa_base + pkt->cmd_buf_size) >> cmdq->pdata->shift,
drivers/mailbox/mtk-gpueb-mailbox.c
118
writel(BIT(ch->num), ch->ebm->mbox_ctl + GPUEB_MBOX_CTL_IRQ_CLR);
drivers/mailbox/mtk-gpueb-mailbox.c
143
writel(values[i / 4], ch->ebm->mbox_mmio + ch->c->tx_offset + i);
drivers/mailbox/mtk-gpueb-mailbox.c
145
writel(BIT(ch->num), ch->ebm->mbox_ctl + GPUEB_MBOX_CTL_IRQ_SET);
drivers/mailbox/mtk-gpueb-mailbox.c
164
writel(BIT(ch->num), ch->ebm->mbox_ctl + GPUEB_MBOX_CTL_IRQ_CLR);
drivers/mailbox/mtk-vcp-mailbox.c
44
writel(priv->ipi_recv.irq_status, priv->base + priv->cfg->clr_out);
drivers/mailbox/mtk-vcp-mailbox.c
80
writel(BIT(ipi_info->index), priv->base + priv->cfg->set_in);
drivers/mailbox/pcc.c
156
writel(val, vaddr);
drivers/mailbox/qcom-cpucp-mbox.c
102
writel(*val, cpucp->tx_base + APSS_CPUCP_TX_MBOX_CMD(chan_id) + APSS_CPUCP_MBOX_CMD_OFF);
drivers/mailbox/qcom-ipcc.c
106
writel(hwirq, ipcc->base + IPCC_REG_RECV_SIGNAL_ENABLE);
drivers/mailbox/qcom-ipcc.c
155
writel(hwirq, ipcc->base + IPCC_REG_SEND_ID);
drivers/mailbox/qcom-ipcc.c
304
writel(config_value, ipcc->base + IPCC_REG_CONFIG);
drivers/mailbox/qcom-ipcc.c
86
writel(hwirq, ipcc->base + IPCC_REG_RECV_SIGNAL_CLEAR);
drivers/mailbox/qcom-ipcc.c
98
writel(hwirq, ipcc->base + IPCC_REG_RECV_SIGNAL_DISABLE);
drivers/mailbox/sprd-mailbox.c
153
writel(0x1, base + SPRD_MBOX_TRIGGER);
drivers/mailbox/sprd-mailbox.c
157
writel(SPRD_MBOX_IRQ_CLR, base + SPRD_MBOX_IRQ_STS);
drivers/mailbox/sprd-mailbox.c
202
writel(SPRD_INBOX_R2_FIFO_OVERFLOW_DELIVER_RST,
drivers/mailbox/sprd-mailbox.c
205
writel(fifo_sts & (SPRD_INBOX_FIFO_DELIVER_MASK | SPRD_INBOX_FIFO_OVERLOW_MASK),
drivers/mailbox/sprd-mailbox.c
229
writel(SPRD_MBOX_IRQ_CLR, priv->inbox_base + SPRD_MBOX_IRQ_STS);
drivers/mailbox/sprd-mailbox.c
241
writel(data[0], priv->inbox_base + SPRD_MBOX_MSG_LOW);
drivers/mailbox/sprd-mailbox.c
242
writel(data[1], priv->inbox_base + SPRD_MBOX_MSG_HIGH);
drivers/mailbox/sprd-mailbox.c
245
writel(id, priv->inbox_base + SPRD_MBOX_ID);
drivers/mailbox/sprd-mailbox.c
248
writel(0x1, priv->inbox_base + SPRD_MBOX_TRIGGER);
drivers/mailbox/sprd-mailbox.c
283
writel(0x0, priv->outbox_base + SPRD_MBOX_FIFO_RST);
drivers/mailbox/sprd-mailbox.c
288
writel(val, priv->inbox_base + SPRD_MBOX_IRQ_MSK);
drivers/mailbox/sprd-mailbox.c
293
writel(val, priv->outbox_base + SPRD_MBOX_IRQ_MSK);
drivers/mailbox/sprd-mailbox.c
297
writel(0x0, priv->supp_base + SPRD_MBOX_FIFO_RST);
drivers/mailbox/sprd-mailbox.c
298
writel(val, priv->supp_base + SPRD_MBOX_IRQ_MSK);
drivers/mailbox/sprd-mailbox.c
313
writel(SPRD_INBOX_FIFO_IRQ_MASK, priv->inbox_base + SPRD_MBOX_IRQ_MSK);
drivers/mailbox/sprd-mailbox.c
314
writel(SPRD_OUTBOX_FIFO_IRQ_MASK, priv->outbox_base + SPRD_MBOX_IRQ_MSK);
drivers/mailbox/sprd-mailbox.c
317
writel(SPRD_OUTBOX_FIFO_IRQ_MASK,
drivers/mailbox/sun6i-msgbox.c
109
writel(msg, mbox->regs + MSG_DATA_REG(n));
drivers/mailbox/sun6i-msgbox.c
125
writel(RX_IRQ(n), mbox->regs + LOCAL_IRQ_STAT_REG);
drivers/mailbox/sun6i-msgbox.c
129
writel(readl(mbox->regs + LOCAL_IRQ_EN_REG) | RX_IRQ(n),
drivers/mailbox/sun6i-msgbox.c
147
writel(readl(mbox->regs + LOCAL_IRQ_EN_REG) & ~RX_IRQ(n),
drivers/mailbox/sun6i-msgbox.c
155
writel(RX_IRQ(n), mbox->regs + LOCAL_IRQ_STAT_REG);
drivers/mailbox/sun6i-msgbox.c
256
writel(0, mbox->regs + LOCAL_IRQ_EN_REG);
drivers/mailbox/sun6i-msgbox.c
93
writel(RX_IRQ(n), mbox->regs + LOCAL_IRQ_STAT_REG);
drivers/mailbox/tegra-hsp.c
142
writel(value, hsp->regs + offset);
drivers/mailbox/tegra-hsp.c
154
writel(value, channel->regs + offset);
drivers/mailbox/ti-msgmgr.c
424
writel(*word_data, data_reg);
drivers/mailbox/ti-msgmgr.c
432
writel(data_trail, data_reg);
drivers/mailbox/ti-msgmgr.c
444
writel(0, data_reg);
drivers/media/cec/platform/sti/stih-cec.c
142
writel(cec_clk_div, cec->regs + CEC_CLK_DIV);
drivers/media/cec/platform/sti/stih-cec.c
145
writel(CEC_SBIT_TOUT_47MS | (CEC_DBIT_TOUT_28MS << 4),
drivers/media/cec/platform/sti/stih-cec.c
149
writel(CEC_BIT_LPULSE_03MS | CEC_BIT_HPULSE_03MS,
drivers/media/cec/platform/sti/stih-cec.c
153
writel(BIT(5) | BIT(7), cec->regs + CEC_TX_CTRL);
drivers/media/cec/platform/sti/stih-cec.c
156
writel(CEC_TX_ARRAY_EN | CEC_RX_ARRAY_EN | CEC_TX_STOP_ON_NACK,
drivers/media/cec/platform/sti/stih-cec.c
160
writel(CEC_IN_FILTER_EN | CEC_EN | CEC_RX_RESET_EN,
drivers/media/cec/platform/sti/stih-cec.c
164
writel(0, cec->regs + CEC_ADDR_TABLE);
drivers/media/cec/platform/sti/stih-cec.c
167
writel(0x0, cec->regs + CEC_STATUS);
drivers/media/cec/platform/sti/stih-cec.c
170
writel(CEC_TX_DONE_IRQ_EN | CEC_RX_DONE_IRQ_EN |
drivers/media/cec/platform/sti/stih-cec.c
177
writel(0, cec->regs + CEC_ADDR_TABLE);
drivers/media/cec/platform/sti/stih-cec.c
180
writel(0x0, cec->regs + CEC_STATUS);
drivers/media/cec/platform/sti/stih-cec.c
183
writel(0, cec->regs + CEC_IRQ_CTRL);
drivers/media/cec/platform/sti/stih-cec.c
199
writel(reg, cec->regs + CEC_ADDR_TABLE);
drivers/media/cec/platform/sti/stih-cec.c
218
writel(CEC_TX_AUTO_SOM_EN | CEC_TX_AUTO_EOM_EN | CEC_TX_START |
drivers/media/cec/platform/sti/stih-cec.c
289
writel(cec->irq_status, cec->regs + CEC_STATUS);
drivers/media/cec/platform/tegra/tegra_cec.c
59
writel(val, cec->cec_base + reg);
drivers/media/pci/b2c2/flexcop-pci.c
101
writel(v.raw, fc_pci->io_mem + r);
drivers/media/pci/bt8xx/bt878.h
134
#define bmtwrite(dat,adr) writel((dat), (adr))
drivers/media/pci/bt8xx/bttvp.h
491
#define btwrite(dat,adr) writel((dat), btv->bt848_mmio+(adr))
drivers/media/pci/cx18/cx18-io.h
54
writel(val, addr);
drivers/media/pci/cx23885/cx23885.h
498
#define cx_write(reg, value) writel((value), dev->lmmio + ((reg)>>2))
drivers/media/pci/cx23885/cx23885.h
501
writel((readl(dev->lmmio+((reg)>>2)) & ~(mask)) |\
drivers/media/pci/cx25821/cx25821.h
351
#define cx_write(reg, value) writel((value), dev->lmmio + ((reg)>>2))
drivers/media/pci/cx25821/cx25821.h
354
writel((readl(dev->lmmio+((reg)>>2)) & ~(mask)) |\
drivers/media/pci/cx88/cx88.h
585
#define cx_write(reg, value) writel((value), core->lmmio + ((reg) >> 2))
drivers/media/pci/cx88/cx88.h
589
writel((readl(core->lmmio + ((reg) >> 2)) & ~(mask)) |\
drivers/media/pci/cx88/cx88.h
600
writel(core->shadow[sreg], core->lmmio + ((reg) >> 2)))
drivers/media/pci/cx88/cx88.h
604
writel(core->shadow[sreg], \
drivers/media/pci/ddbridge/ddbridge-io.h
26
writel(val, link->dev->regs + adr);
drivers/media/pci/ddbridge/ddbridge-io.h
36
writel(val, dev->regs + adr);
drivers/media/pci/intel/ipu3/ipu3-cio2.c
1795
writel(CIO2_D0I3C_I3, base + CIO2_REG_D0I3C);
drivers/media/pci/intel/ipu3/ipu3-cio2.c
1807
writel(CIO2_D0I3C_RR, base + CIO2_REG_D0I3C);
drivers/media/pci/intel/ipu3/ipu3-cio2.c
386
writel(timing.clk_termen, q->csi_rx_base +
drivers/media/pci/intel/ipu3/ipu3-cio2.c
388
writel(timing.clk_settle, q->csi_rx_base +
drivers/media/pci/intel/ipu3/ipu3-cio2.c
392
writel(timing.dat_termen, q->csi_rx_base +
drivers/media/pci/intel/ipu3/ipu3-cio2.c
394
writel(timing.dat_settle, q->csi_rx_base +
drivers/media/pci/intel/ipu3/ipu3-cio2.c
398
writel(CIO2_PBM_WMCTRL1_MIN_2CK |
drivers/media/pci/intel/ipu3/ipu3-cio2.c
401
writel(CIO2_PBM_WMCTRL2_HWM_2CK << CIO2_PBM_WMCTRL2_HWM_2CK_SHIFT |
drivers/media/pci/intel/ipu3/ipu3-cio2.c
407
writel(CIO2_PBM_ARB_CTRL_LANES_DIV <<
drivers/media/pci/intel/ipu3/ipu3-cio2.c
415
writel(CIO2_CSIRX_STATUS_DLANE_HS_MASK,
drivers/media/pci/intel/ipu3/ipu3-cio2.c
417
writel(CIO2_CSIRX_STATUS_DLANE_LP_MASK,
drivers/media/pci/intel/ipu3/ipu3-cio2.c
420
writel(CIO2_FB_HPLL_FREQ, base + CIO2_REG_FB_HPLL_FREQ);
drivers/media/pci/intel/ipu3/ipu3-cio2.c
421
writel(CIO2_ISCLK_RATIO, base + CIO2_REG_ISCLK_RATIO);
drivers/media/pci/intel/ipu3/ipu3-cio2.c
425
writel(1, q->csi_rx_base + CIO2_REG_MIPIBE_SP_LUT_ENTRY(i));
drivers/media/pci/intel/ipu3/ipu3-cio2.c
429
writel(CIO2_MIPIBE_LP_LUT_ENTRY_DISREGARD,
drivers/media/pci/intel/ipu3/ipu3-cio2.c
431
writel(CIO2_MIPIBE_GLOBAL_LUT_DISREGARD,
drivers/media/pci/intel/ipu3/ipu3-cio2.c
434
writel(CIO2_INT_EN_EXT_IE_MASK, base + CIO2_REG_INT_EN_EXT_IE);
drivers/media/pci/intel/ipu3/ipu3-cio2.c
435
writel(CIO2_IRQCTRL_MASK, q->csi_rx_base + CIO2_REG_IRQCTRL_MASK);
drivers/media/pci/intel/ipu3/ipu3-cio2.c
436
writel(CIO2_IRQCTRL_MASK, q->csi_rx_base + CIO2_REG_IRQCTRL_ENABLE);
drivers/media/pci/intel/ipu3/ipu3-cio2.c
437
writel(0, q->csi_rx_base + CIO2_REG_IRQCTRL_EDGE);
drivers/media/pci/intel/ipu3/ipu3-cio2.c
438
writel(0, q->csi_rx_base + CIO2_REG_IRQCTRL_LEVEL_NOT_PULSE);
drivers/media/pci/intel/ipu3/ipu3-cio2.c
439
writel(CIO2_INT_EN_EXT_OE_MASK, base + CIO2_REG_INT_EN_EXT_OE);
drivers/media/pci/intel/ipu3/ipu3-cio2.c
441
writel(CIO2_REG_INT_EN_IRQ | CIO2_INT_IOC(CIO2_DMA_CHAN) |
drivers/media/pci/intel/ipu3/ipu3-cio2.c
445
writel((CIO2_PXM_PXF_FMT_CFG_BPP_10 | CIO2_PXM_PXF_FMT_CFG_PCK_64B)
drivers/media/pci/intel/ipu3/ipu3-cio2.c
448
writel(SID << CIO2_MIPIBE_LP_LUT_ENTRY_SID_SHIFT |
drivers/media/pci/intel/ipu3/ipu3-cio2.c
452
writel(0, q->csi_rx_base + CIO2_REG_MIPIBE_COMP_FORMAT(sensor_vc));
drivers/media/pci/intel/ipu3/ipu3-cio2.c
453
writel(0, q->csi_rx_base + CIO2_REG_MIPIBE_FORCE_RAW8);
drivers/media/pci/intel/ipu3/ipu3-cio2.c
454
writel(0, base + CIO2_REG_PXM_SID2BID0(csi2bus));
drivers/media/pci/intel/ipu3/ipu3-cio2.c
456
writel(lanes, q->csi_rx_base + CIO2_REG_CSIRX_NOF_ENABLED_LANES);
drivers/media/pci/intel/ipu3/ipu3-cio2.c
457
writel(CIO2_CGC_PRIM_TGE |
drivers/media/pci/intel/ipu3/ipu3-cio2.c
470
writel(CIO2_LTRCTRL_LTRDYNEN, base + CIO2_REG_LTRCTRL);
drivers/media/pci/intel/ipu3/ipu3-cio2.c
471
writel(CIO2_LTRVAL0_VAL << CIO2_LTRVAL02_VAL_SHIFT |
drivers/media/pci/intel/ipu3/ipu3-cio2.c
476
writel(CIO2_LTRVAL2_VAL << CIO2_LTRVAL02_VAL_SHIFT |
drivers/media/pci/intel/ipu3/ipu3-cio2.c
483
writel(0, base + CIO2_REG_CDMABA(i));
drivers/media/pci/intel/ipu3/ipu3-cio2.c
484
writel(0, base + CIO2_REG_CDMAC0(i));
drivers/media/pci/intel/ipu3/ipu3-cio2.c
485
writel(0, base + CIO2_REG_CDMAC1(i));
drivers/media/pci/intel/ipu3/ipu3-cio2.c
489
writel(PFN_DOWN(q->fbpt_bus_addr), base + CIO2_REG_CDMABA(CIO2_DMA_CHAN));
drivers/media/pci/intel/ipu3/ipu3-cio2.c
491
writel(num_buffers1 << CIO2_CDMAC0_FBPT_LEN_SHIFT |
drivers/media/pci/intel/ipu3/ipu3-cio2.c
499
writel(1 << CIO2_CDMAC1_LINENUMUPDATE_SHIFT,
drivers/media/pci/intel/ipu3/ipu3-cio2.c
502
writel(0, base + CIO2_REG_PBM_FOPN_ABORT);
drivers/media/pci/intel/ipu3/ipu3-cio2.c
504
writel(CIO2_PXM_FRF_CFG_CRC_TH << CIO2_PXM_FRF_CFG_CRC_TH_SHIFT |
drivers/media/pci/intel/ipu3/ipu3-cio2.c
511
writel(CIO2_IRQCTRL_MASK, q->csi_rx_base + CIO2_REG_IRQCTRL_CLEAR);
drivers/media/pci/intel/ipu3/ipu3-cio2.c
512
writel(~0, base + CIO2_REG_INT_STS_EXT_OE);
drivers/media/pci/intel/ipu3/ipu3-cio2.c
513
writel(~0, base + CIO2_REG_INT_STS_EXT_IE);
drivers/media/pci/intel/ipu3/ipu3-cio2.c
514
writel(~0, base + CIO2_REG_INT_STS);
drivers/media/pci/intel/ipu3/ipu3-cio2.c
517
writel(1, q->csi_rx_base + CIO2_REG_MIPIBE_ENABLE);
drivers/media/pci/intel/ipu3/ipu3-cio2.c
518
writel(1, q->csi_rx_base + CIO2_REG_CSIRX_ENABLE);
drivers/media/pci/intel/ipu3/ipu3-cio2.c
532
writel(0, q->csi_rx_base + CIO2_REG_IRQCTRL_MASK);
drivers/media/pci/intel/ipu3/ipu3-cio2.c
533
writel(0, q->csi_rx_base + CIO2_REG_IRQCTRL_ENABLE);
drivers/media/pci/intel/ipu3/ipu3-cio2.c
534
writel(0, q->csi_rx_base + CIO2_REG_CSIRX_ENABLE);
drivers/media/pci/intel/ipu3/ipu3-cio2.c
535
writel(0, q->csi_rx_base + CIO2_REG_MIPIBE_ENABLE);
drivers/media/pci/intel/ipu3/ipu3-cio2.c
538
writel(0, base + CIO2_REG_CDMAC0(CIO2_DMA_CHAN));
drivers/media/pci/intel/ipu3/ipu3-cio2.c
546
writel(readl(base + CIO2_REG_PXM_FRF_CFG(i)) |
drivers/media/pci/intel/ipu3/ipu3-cio2.c
548
writel(readl(base + CIO2_REG_PBM_FOPN_ABORT) |
drivers/media/pci/intel/ipu3/ipu3-cio2.c
699
writel(oe_clear, base + CIO2_REG_INT_STS_EXT_OE);
drivers/media/pci/intel/ipu3/ipu3-cio2.c
756
writel(csi2_status,
drivers/media/pci/intel/ipu3/ipu3-cio2.c
761
writel(ie_status, base + CIO2_REG_INT_STS_EXT_IE);
drivers/media/pci/intel/ipu3/ipu3-cio2.c
783
writel(int_status, base + CIO2_REG_INT_STS);
drivers/media/pci/intel/ipu6/ipu6-buttress.c
108
writel(ENTRY | EXIT, isp->base + ipc->csr_in);
drivers/media/pci/intel/ipu6/ipu6-buttress.c
109
writel(QUERY, isp->base + ipc->csr_out);
drivers/media/pci/intel/ipu6/ipu6-buttress.c
120
writel(ENTRY | QUERY, isp->base + ipc->csr_in);
drivers/media/pci/intel/ipu6/ipu6-buttress.c
121
writel(ENTRY, isp->base + ipc->csr_out);
drivers/media/pci/intel/ipu6/ipu6-buttress.c
138
writel(EXIT, isp->base + ipc->csr_in);
drivers/media/pci/intel/ipu6/ipu6-buttress.c
139
writel(0, isp->base + ipc->db0_in);
drivers/media/pci/intel/ipu6/ipu6-buttress.c
140
writel(csr_in_clr, isp->base + ipc->csr_in);
drivers/media/pci/intel/ipu6/ipu6-buttress.c
141
writel(EXIT, isp->base + ipc->csr_out);
drivers/media/pci/intel/ipu6/ipu6-buttress.c
163
writel(QUERY, isp->base + ipc->csr_in);
drivers/media/pci/intel/ipu6/ipu6-buttress.c
164
writel(ENTRY, isp->base + ipc->csr_out);
drivers/media/pci/intel/ipu6/ipu6-buttress.c
182
writel(BUTTRESS_IU2CSECSR_IPC_PEER_DEASSERTED_REG_VALID_REQ,
drivers/media/pci/intel/ipu6/ipu6-buttress.c
195
writel(BUTTRESS_IU2CSECSR_IPC_PEER_ASSERTED_REG_VALID_REQ,
drivers/media/pci/intel/ipu6/ipu6-buttress.c
214
writel(0, isp->base + ipc->db0_in);
drivers/media/pci/intel/ipu6/ipu6-buttress.c
247
writel(msgs[i].cmd, isp->base + ipc->data0_out);
drivers/media/pci/intel/ipu6/ipu6-buttress.c
249
writel(val, isp->base + ipc->db0_out);
drivers/media/pci/intel/ipu6/ipu6-buttress.c
261
writel(0, isp->base + ipc->db0_out);
drivers/media/pci/intel/ipu6/ipu6-buttress.c
359
writel(irq_status, isp->base + BUTTRESS_REG_ISR_CLEAR);
drivers/media/pci/intel/ipu6/ipu6-buttress.c
414
writel(BUTTRESS_IRQS & ~disable_irqs,
drivers/media/pci/intel/ipu6/ipu6-buttress.c
441
writel(BUTTRESS_IRQS, isp->base + BUTTRESS_REG_ISR_ENABLE);
drivers/media/pci/intel/ipu6/ipu6-buttress.c
472
writel(val, isp->base + ctrl->freq_ctl);
drivers/media/pci/intel/ipu6/ipu6-buttress.c
519
writel(BUTTRESS_FW_RESET_CTL_START, isp->base +
drivers/media/pci/intel/ipu6/ipu6-buttress.c
532
writel(0, isp->base + BUTTRESS_REG_FW_RESET_CTL);
drivers/media/pci/intel/ipu6/ipu6-buttress.c
638
writel(data, isp->base + BUTTRESS_REG_FW_SOURCE_BASE_LO);
drivers/media/pci/intel/ipu6/ipu6-buttress.c
641
writel(data, isp->base + BUTTRESS_REG_FW_SOURCE_BASE_HI);
drivers/media/pci/intel/ipu6/ipu6-buttress.c
732
writel(BUTTRESS_FABRIC_CMD_START_TSC_SYNC,
drivers/media/pci/intel/ipu6/ipu6-buttress.c
766
writel(val, isp->base + BUTTRESS_REG_TSW_CTL);
drivers/media/pci/intel/ipu6/ipu6-buttress.c
768
writel(val, isp->base + BUTTRESS_REG_TSW_CTL);
drivers/media/pci/intel/ipu6/ipu6-buttress.c
79
writel(val, isp->base + ipc->csr_in);
drivers/media/pci/intel/ipu6/ipu6-buttress.c
818
writel(BUTTRESS_IRQS, isp->base + BUTTRESS_REG_ISR_CLEAR);
drivers/media/pci/intel/ipu6/ipu6-buttress.c
819
writel(BUTTRESS_IRQS, isp->base + BUTTRESS_REG_ISR_ENABLE);
drivers/media/pci/intel/ipu6/ipu6-buttress.c
82
writel(ENTRY, isp->base + ipc->csr_out);
drivers/media/pci/intel/ipu6/ipu6-buttress.c
820
writel(b->wdt_cached_value, isp->base + BUTTRESS_REG_WDT);
drivers/media/pci/intel/ipu6/ipu6-buttress.c
854
writel(BUTTRESS_IRQS, isp->base + BUTTRESS_REG_ISR_CLEAR);
drivers/media/pci/intel/ipu6/ipu6-buttress.c
855
writel(BUTTRESS_IRQS, isp->base + BUTTRESS_REG_ISR_ENABLE);
drivers/media/pci/intel/ipu6/ipu6-buttress.c
904
writel(0, isp->base + BUTTRESS_REG_ISR_ENABLE);
drivers/media/pci/intel/ipu6/ipu6-fw-com.c
269
writel(TUNIT_MAGIC_PATTERN, ctx->dmem_addr + TUNIT_CFG_DWR_REG * 4);
drivers/media/pci/intel/ipu6/ipu6-fw-com.c
275
writel(SYSCOM_COMMAND_UNINIT, ctx->dmem_addr + SYSCOM_COMMAND_REG * 4);
drivers/media/pci/intel/ipu6/ipu6-fw-com.c
278
writel(SYSCOM_STATE_UNINIT,
drivers/media/pci/intel/ipu6/ipu6-fw-com.c
284
writel(ctx->config_vied_addr,
drivers/media/pci/intel/ipu6/ipu6-fw-com.c
305
writel(SYSCOM_COMMAND_INACTIVE, ctx->dmem_addr +
drivers/media/pci/intel/ipu6/ipu6-fw-com.c
374
writel(wr, q_dmem + FW_COM_WR_REG);
drivers/media/pci/intel/ipu6/ipu6-fw-com.c
411
writel(rd, q_dmem + FW_COM_RD_REG);
drivers/media/pci/intel/ipu6/ipu6-fw-isys.c
197
writel(val, spc_regs_base + IPU6_ISYS_REG_SPC_STATUS_CTRL);
drivers/media/pci/intel/ipu6/ipu6-isys-csi2.c
206
writel(irq & mask, csi2->base + CSI_PORT_REG_BASE_IRQ_CSI +
drivers/media/pci/intel/ipu6/ipu6-isys-csi2.c
255
writel(0, csi2->base + CSI_REG_CSI_FE_ENABLE);
drivers/media/pci/intel/ipu6/ipu6-isys-csi2.c
256
writel(0, csi2->base + CSI_REG_PPI2CSI_ENABLE);
drivers/media/pci/intel/ipu6/ipu6-isys-csi2.c
258
writel(0,
drivers/media/pci/intel/ipu6/ipu6-isys-csi2.c
261
writel(mask,
drivers/media/pci/intel/ipu6/ipu6-isys-csi2.c
264
writel(0,
drivers/media/pci/intel/ipu6/ipu6-isys-csi2.c
267
writel(0xffffffff,
drivers/media/pci/intel/ipu6/ipu6-isys-csi2.c
273
writel(0, isys->pdata->base + CSI_REG_HUB_FW_ACCESS_PORT
drivers/media/pci/intel/ipu6/ipu6-isys-csi2.c
276
writel(0, isys->pdata->base +
drivers/media/pci/intel/ipu6/ipu6-isys-csi2.c
283
writel(0x1, csi2->base + CSI_REG_PORT_GPREG_SRST);
drivers/media/pci/intel/ipu6/ipu6-isys-csi2.c
285
writel(0x0, csi2->base + CSI_REG_PORT_GPREG_SRST);
drivers/media/pci/intel/ipu6/ipu6-isys-csi2.c
289
writel(1, isys->pdata->base + CSI_REG_HUB_DRV_ACCESS_PORT(i));
drivers/media/pci/intel/ipu6/ipu6-isys-csi2.c
290
writel(1, isys->pdata->base + CSI_REG_HUB_FW_ACCESS_PORT
drivers/media/pci/intel/ipu6/ipu6-isys-csi2.c
295
writel(mask,
drivers/media/pci/intel/ipu6/ipu6-isys-csi2.c
298
writel(mask,
drivers/media/pci/intel/ipu6/ipu6-isys-csi2.c
301
writel(mask,
drivers/media/pci/intel/ipu6/ipu6-isys-csi2.c
304
writel(mask,
drivers/media/pci/intel/ipu6/ipu6-isys-csi2.c
307
writel(mask,
drivers/media/pci/intel/ipu6/ipu6-isys-csi2.c
316
writel(0xffffffff, csi2->base + CSI_PORT_REG_BASE_IRQ_CSI_SYNC +
drivers/media/pci/intel/ipu6/ipu6-isys-csi2.c
318
writel(0, csi2->base + CSI_PORT_REG_BASE_IRQ_CSI_SYNC +
drivers/media/pci/intel/ipu6/ipu6-isys-csi2.c
320
writel(0xffffffff, csi2->base + CSI_PORT_REG_BASE_IRQ_CSI_SYNC +
drivers/media/pci/intel/ipu6/ipu6-isys-csi2.c
322
writel(0, csi2->base + CSI_PORT_REG_BASE_IRQ_CSI_SYNC +
drivers/media/pci/intel/ipu6/ipu6-isys-csi2.c
324
writel(0xffffffff, csi2->base + CSI_PORT_REG_BASE_IRQ_CSI_SYNC +
drivers/media/pci/intel/ipu6/ipu6-isys-csi2.c
328
writel(0, csi2->base + CSI_REG_CSI_FE_MODE);
drivers/media/pci/intel/ipu6/ipu6-isys-csi2.c
329
writel(CSI_SENSOR_INPUT, csi2->base + CSI_REG_CSI_FE_MUX_CTRL);
drivers/media/pci/intel/ipu6/ipu6-isys-csi2.c
330
writel(CSI_CNTR_SENSOR_LINE_ID | CSI_CNTR_SENSOR_FRAME_ID,
drivers/media/pci/intel/ipu6/ipu6-isys-csi2.c
332
writel(FIELD_PREP(PPI_INTF_CONFIG_NOF_ENABLED_DLANES_MASK, nlanes - 1),
drivers/media/pci/intel/ipu6/ipu6-isys-csi2.c
335
writel(1, csi2->base + CSI_REG_PPI2CSI_ENABLE);
drivers/media/pci/intel/ipu6/ipu6-isys-csi2.c
336
writel(1, csi2->base + CSI_REG_CSI_FE_ENABLE);
drivers/media/pci/intel/ipu6/ipu6-isys-dwc-phy.c
72
writel(data, base + addr);
drivers/media/pci/intel/ipu6/ipu6-isys-jsl-phy.c
108
writel(val, base + reg);
drivers/media/pci/intel/ipu6/ipu6-isys-jsl-phy.c
121
writel(val, base + CSI2_HUB_GPREG_SIP0_CSI_RX_A_CONTROL);
drivers/media/pci/intel/ipu6/ipu6-isys-jsl-phy.c
126
writel(val, base + CSI2_HUB_GPREG_SIP0_CSI_RX_B_CONTROL);
drivers/media/pci/intel/ipu6/ipu6-isys-jsl-phy.c
131
writel(val, base + CSI2_HUB_GPREG_SIP1_CSI_RX_A_CONTROL);
drivers/media/pci/intel/ipu6/ipu6-isys-jsl-phy.c
136
writel(val, base + CSI2_HUB_GPREG_SIP1_CSI_RX_B_CONTROL);
drivers/media/pci/intel/ipu6/ipu6-isys-jsl-phy.c
163
writel(csi2_port_cfg[index][2],
drivers/media/pci/intel/ipu6/ipu6-isys-jsl-phy.c
187
writel(timing->ctermen, reg);
drivers/media/pci/intel/ipu6/ipu6-isys-jsl-phy.c
191
writel(timing->csettle, reg);
drivers/media/pci/intel/ipu6/ipu6-isys-jsl-phy.c
196
writel(timing->dtermen, reg);
drivers/media/pci/intel/ipu6/ipu6-isys-jsl-phy.c
200
writel(timing->dsettle, reg);
drivers/media/pci/intel/ipu6/ipu6-isys-jsl-phy.c
229
writel(DPHY_TIMER_INCR,
drivers/media/pci/intel/ipu6/ipu6-isys-jsl-phy.c
79
writel(val, base + reg);
drivers/media/pci/intel/ipu6/ipu6-isys-jsl-phy.c
85
writel(val, base + reg);
drivers/media/pci/intel/ipu6/ipu6-isys-jsl-phy.c
91
writel(val, base + reg);
drivers/media/pci/intel/ipu6/ipu6-isys-jsl-phy.c
97
writel(val, base + reg);
drivers/media/pci/intel/ipu6/ipu6-isys-mcd-phy.c
512
writel(val, isys_base + CSI_REG_HUB_GPREG_PHY_CTL(id));
drivers/media/pci/intel/ipu6/ipu6-isys-mcd-phy.c
530
writel(0, isys_base + CSI_REG_HUB_GPREG_PHY_CTL(id));
drivers/media/pci/intel/ipu6/ipu6-isys-mcd-phy.c
551
writel(val, isys_base + CSI_REG_HUB_GPREG_PHY_CTL(id));
drivers/media/pci/intel/ipu6/ipu6-isys-mcd-phy.c
587
writel(common_init_regs[i].val,
drivers/media/pci/intel/ipu6/ipu6-isys-mcd-phy.c
655
writel(phy_config_regs[cfg.port][i].val,
drivers/media/pci/intel/ipu6/ipu6-isys.c
285
writel(irqs, base + isys->pdata->ipdata->csi2.ctrl0_irq_edge);
drivers/media/pci/intel/ipu6/ipu6-isys.c
286
writel(irqs, base + isys->pdata->ipdata->csi2.ctrl0_irq_lnp);
drivers/media/pci/intel/ipu6/ipu6-isys.c
287
writel(irqs, base + isys->pdata->ipdata->csi2.ctrl0_irq_mask);
drivers/media/pci/intel/ipu6/ipu6-isys.c
288
writel(irqs, base + isys->pdata->ipdata->csi2.ctrl0_irq_enable);
drivers/media/pci/intel/ipu6/ipu6-isys.c
289
writel(GENMASK(19, 0),
drivers/media/pci/intel/ipu6/ipu6-isys.c
293
writel(irqs, base + IPU6_REG_ISYS_UNISPART_IRQ_EDGE);
drivers/media/pci/intel/ipu6/ipu6-isys.c
294
writel(irqs, base + IPU6_REG_ISYS_UNISPART_IRQ_LEVEL_NOT_PULSE);
drivers/media/pci/intel/ipu6/ipu6-isys.c
295
writel(GENMASK(28, 0), base + IPU6_REG_ISYS_UNISPART_IRQ_CLEAR);
drivers/media/pci/intel/ipu6/ipu6-isys.c
296
writel(irqs, base + IPU6_REG_ISYS_UNISPART_IRQ_MASK);
drivers/media/pci/intel/ipu6/ipu6-isys.c
297
writel(irqs, base + IPU6_REG_ISYS_UNISPART_IRQ_ENABLE);
drivers/media/pci/intel/ipu6/ipu6-isys.c
299
writel(0, base + IPU6_REG_ISYS_UNISPART_SW_IRQ_REG);
drivers/media/pci/intel/ipu6/ipu6-isys.c
300
writel(0, base + IPU6_REG_ISYS_UNISPART_SW_IRQ_MUX_REG);
drivers/media/pci/intel/ipu6/ipu6-isys.c
304
writel(thd[i], base + IPU6_REG_ISYS_CDC_THRESHOLD(i));
drivers/media/pci/intel/ipu6/ipu6-isys.c
319
writel(status, csi2->base + CSI_PORT_REG_BASE_IRQ_CSI_SYNC +
drivers/media/pci/intel/ipu6/ipu6-isys.c
364
writel(ISYS_UNISPART_IRQS & ~IPU6_ISYS_UNISPART_IRQ_SW,
drivers/media/pci/intel/ipu6/ipu6-isys.c
368
writel(status_csi, isys->pdata->base + ctrl0_clear);
drivers/media/pci/intel/ipu6/ipu6-isys.c
370
writel(status_sw, isys->pdata->base +
drivers/media/pci/intel/ipu6/ipu6-isys.c
385
writel(0, base + IPU6_REG_ISYS_UNISPART_SW_IRQ_REG);
drivers/media/pci/intel/ipu6/ipu6-isys.c
398
writel(ISYS_UNISPART_IRQS, base + IPU6_REG_ISYS_UNISPART_IRQ_MASK);
drivers/media/pci/intel/ipu6/ipu6-isys.c
505
writel(fc.value, isp->base + IPU6_BUTTRESS_FABIC_CONTROL);
drivers/media/pci/intel/ipu6/ipu6-isys.c
639
writel(VAL_PKGC_PMON_CFG_RESET,
drivers/media/pci/intel/ipu6/ipu6-isys.c
641
writel(VAL_PKGC_PMON_CFG_START,
drivers/media/pci/intel/ipu6/ipu6-mmu.c
488
writel((phys_addr_t)mmu_info->l1_pt_dma,
drivers/media/pci/intel/ipu6/ipu6-mmu.c
492
writel(mmu->mmu_hw[i].info_bits,
drivers/media/pci/intel/ipu6/ipu6-mmu.c
504
writel(block_addr, mmu_hw->base +
drivers/media/pci/intel/ipu6/ipu6-mmu.c
516
writel(block_addr, mmu_hw->base +
drivers/media/pci/intel/ipu6/ipu6-mmu.c
77
writel(0xffffffff, mmu->mmu_hw[i].base +
drivers/media/pci/intel/ipu6/ipu6.c
257
writel(server_fw_addr + prog->blob_offset +
drivers/media/pci/intel/ipu6/ipu6.c
259
writel(IPU6_INFO_REQUEST_DESTINATION_IOSF,
drivers/media/pci/intel/ipu6/ipu6.c
261
writel(prog->start[1], spc_base + IPU6_PSYS_REG_SPC_START_PC);
drivers/media/pci/intel/ipu6/ipu6.c
262
writel(pkg_dir_vied_address, base + hw_variant->dmem_offset);
drivers/media/pci/intel/ipu6/ipu6.c
276
writel(val, spc_regs_base + IPU6_PSYS_REG_SPC_STATUS_CTRL);
drivers/media/pci/intel/ipu6/ipu6.c
279
writel(IPU6_PKG_DIR_IMR_OFFSET, dmem_base);
drivers/media/pci/intel/ipu6/ipu6.c
495
writel(val, isp->base + BUTTRESS_REG_BTRS_CTRL);
drivers/media/pci/ivtv/ivtv-driver.h
797
do { writel(val, reg); readl(reg); } while (0)
drivers/media/pci/ivtv/ivtv-driver.h
800
#define write_reg(val, reg) writel(val, itv->reg_mem + (reg))
drivers/media/pci/ivtv/ivtv-driver.h
805
#define write_enc(val, addr) writel(val, itv->enc_mem + (u32)(addr))
drivers/media/pci/ivtv/ivtv-driver.h
810
#define write_dec(val, addr) writel(val, itv->dec_mem + (u32)(addr))
drivers/media/pci/ivtv/ivtv-ioctl.c
707
writel(*val, reg + reg_start);
drivers/media/pci/ivtv/ivtv-streams.c
735
writel(0, &itv->dec_mbox.mbox[IVTV_MBOX_DMA_END].data[0]);
drivers/media/pci/ivtv/ivtv-streams.c
736
writel(0, &itv->dec_mbox.mbox[IVTV_MBOX_DMA_END].data[1]);
drivers/media/pci/ivtv/ivtv-streams.c
737
writel(0, &itv->dec_mbox.mbox[IVTV_MBOX_DMA_END].data[2]);
drivers/media/pci/ivtv/ivtv-streams.c
738
writel(0, &itv->dec_mbox.mbox[IVTV_MBOX_DMA_END].data[3]);
drivers/media/pci/ivtv/ivtv-streams.c
739
writel(0, &itv->dec_mbox.mbox[IVTV_MBOX_DMA].data[0]);
drivers/media/pci/ivtv/ivtv-streams.c
740
writel(0, &itv->dec_mbox.mbox[IVTV_MBOX_DMA].data[1]);
drivers/media/pci/ivtv/ivtv-streams.c
741
writel(0, &itv->dec_mbox.mbox[IVTV_MBOX_DMA].data[2]);
drivers/media/pci/ivtv/ivtv-streams.c
742
writel(0, &itv->dec_mbox.mbox[IVTV_MBOX_DMA].data[3]);
drivers/media/pci/mantis/mantis_common.h
45
#define mwrite(dat, addr) writel((dat), addr)
drivers/media/pci/netup_unidvb/netup_unidvb_core.c
173
writel(AVL_IRQ_ENABLE, ndev->bmmio0 + AVL_PCIE_IENR);
drivers/media/pci/netup_unidvb/netup_unidvb_core.c
197
writel(BIT_DMA_RUN, &dma->regs->ctrlstat_set);
drivers/media/pci/netup_unidvb/netup_unidvb_core.c
200
writel(BIT_DMA_RUN, &dma->regs->ctrlstat_clear);
drivers/media/pci/netup_unidvb/netup_unidvb_core.c
216
writel(BIT_DMA_IRQ, &dma->regs->ctrlstat_clear);
drivers/media/pci/netup_unidvb/netup_unidvb_core.c
255
writel(0, ndev->bmmio0 + AVL_PCIE_IENR);
drivers/media/pci/netup_unidvb/netup_unidvb_core.c
285
writel(AVL_IRQ_ENABLE, ndev->bmmio0 + AVL_PCIE_IENR);
drivers/media/pci/netup_unidvb/netup_unidvb_core.c
679
writel((NETUP_DMA_BLOCKS_COUNT << 24) |
drivers/media/pci/netup_unidvb/netup_unidvb_core.c
681
writel((u32)(dma->addr_phys & 0x3FFFFFFF), &dma->regs->start_addr_lo);
drivers/media/pci/netup_unidvb/netup_unidvb_core.c
682
writel(0, &dma->regs->start_addr_hi);
drivers/media/pci/netup_unidvb/netup_unidvb_core.c
683
writel(dma->high_addr, ndev->bmmio0 + 0x1000);
drivers/media/pci/netup_unidvb/netup_unidvb_core.c
684
writel(375000000, &dma->regs->timeout);
drivers/media/pci/netup_unidvb/netup_unidvb_core.c
686
writel(BIT_DMA_IRQ, &dma->regs->ctrlstat_clear);
drivers/media/pci/ngene/ngene-core.c
42
#define ngwritel(dat, adr) writel((dat), dev->iomem + (adr))
drivers/media/pci/pluto2/pluto2.c
132
writel(val, &pluto->io_mem[reg]);
drivers/media/pci/pluto2/pluto2.c
140
writel(val, &pluto->io_mem[reg]);
drivers/media/pci/pt1/pt1.c
290
writel(data, pt1->regs + reg * 4);
drivers/media/pci/saa7134/saa7134.h
680
#define saa_writel(reg,value) writel((value), dev->lmmio + (reg));
drivers/media/pci/saa7134/saa7134.h
682
writel((readl(dev->lmmio+(reg)) & ~(mask)) |\
drivers/media/pci/saa7164/saa7164.h
625
#define saa7164_writel(reg, value) writel((value), dev->lmmio + ((reg) >> 2))
drivers/media/pci/saa7164/saa7164.h
628
#define saa7164_writeb(reg, value) writel((value), dev->bmmio + (reg))
drivers/media/pci/smipcie/smipcie.h
296
#define smi_write(reg, value) writel((value), dev->lmmio + ((reg)>>2))
drivers/media/pci/smipcie/smipcie.h
299
writel((readl(dev->lmmio+((reg)>>2)) & ~(mask)) |\
drivers/media/pci/solo6x10/solo6x10.h
285
writel(data, solo_dev->reg_base + reg);
drivers/media/pci/tw5864/tw5864.h
173
#define tw_writel(reg, value) writel((value), dev->mmio + reg)
drivers/media/pci/tw68/tw68.h
169
#define tw_writel(reg, value) writel((value), dev->lmmio + ((reg) >> 2))
drivers/media/pci/tw68/tw68.h
173
writel((readl(dev->lmmio+((reg)>>2)) & ~(mask)) |\
drivers/media/pci/tw68/tw68.h
181
writel((readl(dev->lmmio + ((reg) >> 2)) & ~(bit)), \
drivers/media/pci/tw686x/tw686x.h
153
writel(value, dev->mmio + reg);
drivers/media/pci/zoran/zoran.h
299
#define btwrite(dat, adr) writel((dat), zr->zr36057_mem + (adr))
drivers/media/platform/amlogic/c3/isp/c3-isp-dev.c
28
writel(val, isp->base + reg);
drivers/media/platform/amlogic/c3/mipi-adapter/c3-mipi-adap.c
275
writel(tmp, addr);
drivers/media/platform/amlogic/c3/mipi-csi2/c3-mipi-csi2.c
294
writel(val, addr);
drivers/media/platform/amphion/vpu_core.c
30
writel(val, core->base + reg);
drivers/media/platform/amphion/vpu_drv.c
34
writel(val, vpu->base + reg);
drivers/media/platform/amphion/vpu_malone.c
508
writel(buf->phys, &str_buf->start);
drivers/media/platform/amphion/vpu_malone.c
509
writel(buf->phys, &str_buf->rptr);
drivers/media/platform/amphion/vpu_malone.c
510
writel(buf->phys, &str_buf->wptr);
drivers/media/platform/amphion/vpu_malone.c
511
writel(buf->phys + buf->length, &str_buf->end);
drivers/media/platform/amphion/vpu_malone.c
512
writel(0x1, &str_buf->lwm);
drivers/media/platform/amphion/vpu_malone.c
540
writel(wptr, &str_buf->wptr);
drivers/media/platform/amphion/vpu_malone.c
547
writel(rptr, &str_buf->rptr);
drivers/media/platform/arm/mali-c55/mali-c55-core.c
103
writel(val, mali_c55->base + addr);
drivers/media/platform/aspeed/aspeed-video.c
579
writel(t, video->base + reg);
drivers/media/platform/aspeed/aspeed-video.c
594
writel(val, video->base + reg);
drivers/media/platform/atmel/atmel-isi.c
137
writel(val, isi->regs + reg);
drivers/media/platform/broadcom/bcm2835-unicam.c
604
writel(val | 0x5a000000, unicam->clk_gate_base);
drivers/media/platform/broadcom/bcm2835-unicam.c
614
writel(val, unicam->base + offset);
drivers/media/platform/cadence/cdns-csi2rx.c
205
writel(error_irq_mask, base + CSI2RX_ERROR_IRQS_MASK_REG);
drivers/media/platform/cadence/cdns-csi2rx.c
222
writel(error_status, csi2rx->base + CSI2RX_ERROR_IRQS_REG);
drivers/media/platform/cadence/cdns-csi2rx.c
249
writel(CSI2RX_SOFT_RESET_PROTOCOL | CSI2RX_SOFT_RESET_FRONT,
drivers/media/platform/cadence/cdns-csi2rx.c
253
writel(CSI2RX_STREAM_CTRL_SOFT_RST,
drivers/media/platform/cadence/cdns-csi2rx.c
260
writel(0, csi2rx->base + CSI2RX_SOFT_RESET_REG);
drivers/media/platform/cadence/cdns-csi2rx.c
262
writel(0, csi2rx->base + CSI2RX_STREAM_CTRL_REG(i));
drivers/media/platform/cadence/cdns-csi2rx.c
345
writel(reg, csi2rx->base + CSI2RX_STATIC_CFG_REG);
drivers/media/platform/cadence/cdns-csi2rx.c
355
writel(reg, csi2rx->base + CSI2RX_DPHY_LANE_CTRL_REG);
drivers/media/platform/cadence/cdns-csi2rx.c
382
writel(CSI2RX_STREAM_CFG_FIFO_MODE_LARGE_BUF |
drivers/media/platform/cadence/cdns-csi2rx.c
391
writel(CSI2RX_STREAM_DATA_CFG_VC_SELECT(0),
drivers/media/platform/cadence/cdns-csi2rx.c
394
writel(CSI2RX_STREAM_CTRL_START,
drivers/media/platform/cadence/cdns-csi2rx.c
421
writel(0, csi2rx->base + CSI2RX_DPHY_LANE_CTRL_REG);
drivers/media/platform/cadence/cdns-csi2rx.c
440
writel(0, csi2rx->base + CSI2RX_ERROR_IRQS_MASK_REG);
drivers/media/platform/cadence/cdns-csi2rx.c
443
writel(CSI2RX_STREAM_CTRL_STOP,
drivers/media/platform/cadence/cdns-csi2rx.c
466
writel(0, csi2rx->base + CSI2RX_DPHY_LANE_CTRL_REG);
drivers/media/platform/cadence/cdns-csi2tx.c
235
writel(CSI2TX_DPHY_CLK_WAKEUP_ULPS_CYCLES(32),
drivers/media/platform/cadence/cdns-csi2tx.c
253
writel(reg, csi2tx->base + CSI2TX_DPHY_CFG_REG);
drivers/media/platform/cadence/cdns-csi2tx.c
259
writel(reg | CSI2TX_DPHY_CFG_MODE_HS,
drivers/media/platform/cadence/cdns-csi2tx.c
275
writel(reg, csi2tx->base + CSI2TX_DPHY_CFG_REG);
drivers/media/platform/cadence/cdns-csi2tx.c
289
writel(reg, csi2tx->base + CSI2TX_V2_DPHY_CFG_REG);
drivers/media/platform/cadence/cdns-csi2tx.c
296
writel(CSI2TX_CONFIG_SRST_REQ, csi2tx->base + CSI2TX_CONFIG_REG);
drivers/media/platform/cadence/cdns-csi2tx.c
309
writel(CSI2TX_CONFIG_CFG_REQ, csi2tx->base + CSI2TX_CONFIG_REG);
drivers/media/platform/cadence/cdns-csi2tx.c
363
writel(CSI2TX_DT_CFG_DT(fmt->dt),
drivers/media/platform/cadence/cdns-csi2tx.c
366
writel(CSI2TX_DT_FORMAT_BYTES_PER_LINE(mfmt->width * fmt->bpp) |
drivers/media/platform/cadence/cdns-csi2tx.c
374
writel(CSI2TX_STREAM_IF_CFG_FILL_LEVEL(4),
drivers/media/platform/cadence/cdns-csi2tx.c
379
writel(0, csi2tx->base + CSI2TX_CONFIG_REG);
drivers/media/platform/cadence/cdns-csi2tx.c
386
writel(CSI2TX_CONFIG_CFG_REQ | CSI2TX_CONFIG_SRST_REQ,
drivers/media/platform/chips-media/coda/coda-common.c
84
writel(data, dev->regs_base + reg);
drivers/media/platform/chips-media/coda/imx-vdoa.c
107
writel(0, vdoa->regs + VDOAIE);
drivers/media/platform/chips-media/coda/imx-vdoa.c
117
writel(val, vdoa->regs + VDOAIST);
drivers/media/platform/chips-media/coda/imx-vdoa.c
170
writel(val, vdoa->regs + VDOAC);
drivers/media/platform/chips-media/coda/imx-vdoa.c
172
writel(dst_q_data->height << 16 | dst_q_data->width,
drivers/media/platform/chips-media/coda/imx-vdoa.c
176
writel(val, vdoa->regs + VDOAIEBA00);
drivers/media/platform/chips-media/coda/imx-vdoa.c
178
writel(src_q_data->bytesperline << 16 | dst_q_data->bytesperline,
drivers/media/platform/chips-media/coda/imx-vdoa.c
186
writel(val, vdoa->regs + VDOAIUBO);
drivers/media/platform/chips-media/coda/imx-vdoa.c
189
writel(val, vdoa->regs + VDOAVEBA0);
drivers/media/platform/chips-media/coda/imx-vdoa.c
191
writel(val, vdoa->regs + VDOAVUBO);
drivers/media/platform/chips-media/coda/imx-vdoa.c
194
writel(VDOAIE_EITERR | VDOAIE_EIEOT, vdoa->regs + VDOAIE);
drivers/media/platform/chips-media/coda/imx-vdoa.c
195
writel(VDOASRR_START, vdoa->regs + VDOASRR);
drivers/media/platform/chips-media/wave5/wave5-vdi.c
80
writel(data, vpu_dev->vdb_register + addr);
drivers/media/platform/imagination/e5010-jpeg-enc-hw.c
26
writel(value, (base + offset));
drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
1804
writel(0, jpeg->reg_base + JPEG_ENC_INT_STS);
drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
225
writel(ret, base + JPGDEC_REG_INTERRUPT_STATUS);
drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
250
writel(0, base + JPGDEC_REG_TRIG);
drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
256
writel(0x0000FFFF, base + JPGDEC_REG_INTERRUPT_STATUS);
drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
257
writel(0x00, base + JPGDEC_REG_RESET);
drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
258
writel(0x01, base + JPGDEC_REG_RESET);
drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
263
writel(0x00, base + JPGDEC_REG_RESET);
drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
264
writel(0x10, base + JPGDEC_REG_RESET);
drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
281
writel(val, base + JPGDEC_REG_BRZ_FACTOR);
drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
290
writel(lower_32_bits(addr_y), base + JPGDEC_REG_DEST_ADDR0_Y);
drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
292
writel(lower_32_bits(addr_u), base + JPGDEC_REG_DEST_ADDR0_U);
drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
294
writel(lower_32_bits(addr_v), base + JPGDEC_REG_DEST_ADDR0_V);
drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
297
writel(val, base + JPGDEC_REG_DEST_ADDR0_Y_EXT);
drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
299
writel(val, base + JPGDEC_REG_DEST_ADDR0_U_EXT);
drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
301
writel(val, base + JPGDEC_REG_DEST_ADDR0_V_EXT);
drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
310
writel(lower_32_bits(addr_y), base + JPGDEC_REG_DEST_ADDR1_Y);
drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
311
writel(lower_32_bits(addr_u), base + JPGDEC_REG_DEST_ADDR1_U);
drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
312
writel(lower_32_bits(addr_v), base + JPGDEC_REG_DEST_ADDR1_V);
drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
315
writel(val, base + JPGDEC_REG_DEST_ADDR1_Y_EXT);
drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
317
writel(val, base + JPGDEC_REG_DEST_ADDR1_U_EXT);
drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
319
writel(val, base + JPGDEC_REG_DEST_ADDR1_V_EXT);
drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
326
writel((stride_y & 0xFFFF), base + JPGDEC_REG_STRIDE_Y);
drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
327
writel((stride_uv & 0xFFFF), base + JPGDEC_REG_STRIDE_UV);
drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
333
writel((stride_y & 0xFFFF), base + JPGDEC_REG_IMG_STRIDE_Y);
drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
334
writel((stride_uv & 0xFFFF), base + JPGDEC_REG_IMG_STRIDE_UV);
drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
339
writel(idx & 0x0003FFFFFF, base + JPGDEC_REG_PAUSE_MCU_NUM);
drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
344
writel(mode & 0x03, base + JPGDEC_REG_OPERATION_MODE);
drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
352
writel(lower_32_bits(ptr), base + JPGDEC_REG_FILE_BRP);
drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
355
writel(val, base + JPGDEC_REG_FILE_BRP_EXT);
drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
366
writel(lower_32_bits(addr), base + JPGDEC_REG_FILE_ADDR);
drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
369
writel(val, base + JPGDEC_REG_FILE_ADDR_EXT);
drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
371
writel(size, base + JPGDEC_REG_FILE_TOTAL_SIZE);
drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
372
writel(bitstream_size, base + JPGDEC_REG_BIT_STREAM_SIZE);
drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
382
writel(val, base + JPGDEC_REG_COMP_ID);
drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
387
writel(num - 1, base + JPGDEC_REG_TOTAL_MCU_NUM);
drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
392
writel(num - 1, base + JPGDEC_REG_COMP0_DATA_UNIT_NUM);
drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
401
writel(member, base + JPGDEC_REG_DU_CTRL);
drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
410
writel(val, base + JPGDEC_REG_QT_ID);
drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
421
writel(val, base + JPGDEC_REG_WDMA_CTRL);
drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c
437
writel(val, base + JPGDEC_REG_DU_NUM);
drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c
103
writel(addr_ext, base + JPEG_ENC_SRC_LUMA_ADDR_EXT);
drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c
105
writel(addr_ext, base + JPEG_ENC_SRC_CHRO_ADDR_EXT);
drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c
126
writel(dma_addr_offset & ~0xf, base + JPEG_ENC_OFFSET_ADDR);
drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c
127
writel(dma_addr_offsetmask & 0xf, base + JPEG_ENC_BYTE_OFFSET_MASK);
drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c
128
writel(dma_addr & ~0xf, base + JPEG_ENC_DST_ADDR0);
drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c
129
writel((dma_addr + size) & ~0xf, base + JPEG_ENC_STALL_ADDR0);
drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c
133
writel(addr_ext, base + JPEG_ENC_DEST_ADDR0_EXT);
drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c
134
writel(addr_ext + size, base + JPEG_ENC_STALL_ADDR0_EXT);
drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c
153
writel(value, base + JPEG_ENC_IMG_SIZE);
drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c
166
writel(blk_num, base + JPEG_ENC_BLK_NUM);
drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c
178
writel(img_stride, base + JPEG_ENC_IMG_STRIDE);
drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c
179
writel(mem_stride, base + JPEG_ENC_STRIDE);
drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c
188
writel(enc_quality, base + JPEG_ENC_QUALITY);
drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c
201
writel(value, base + JPEG_ENC_CTRL);
drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c
203
writel(ctx->restart_interval, base + JPEG_ENC_RST_MCU_NUM);
drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c
297
writel(0, jpeg->reg_base + JPEG_ENC_INT_STS);
drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c
61
writel(0, base + JPEG_ENC_RSTB);
drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c
62
writel(JPEG_ENC_RESET_BIT, base + JPEG_ENC_RSTB);
drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c
63
writel(0, base + JPEG_ENC_CODEC_SEL);
drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c
80
writel(value, base + JPEG_ENC_CTRL);
drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c
96
writel(lower_32_bits(dma_addr), base + JPEG_ENC_SRC_LUMA_ADDR);
drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c
98
writel(lower_32_bits(dma_addr), base + JPEG_ENC_SRC_CHROMA_ADDR);
drivers/media/platform/mediatek/vcodec/common/mtk_vcodec_util.c
42
writel(val, dev->reg_base[VDEC_SYS] + reg);
drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.c
76
writel((readl(vdec_misc_addr) | VDEC_IRQ_CFG),
drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.c
78
writel((readl(vdec_misc_addr) & ~VDEC_IRQ_CLR),
drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_hw.c
88
writel(dec_done_status | VDEC_IRQ_CFG, vdec_misc_addr);
drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_hw.c
89
writel(dec_done_status & ~VDEC_IRQ_CLR, vdec_misc_addr);
drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_pm.c
149
writel(ctx->dev->vdec_racing_info[j], vdec_racing_addr + j * 4);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
190
writel(val, cm + VP8_HW_VLD_ADDR);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
193
writel(val, cm + VP8_HW_VLD_VALUE);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
211
writel(val, cm + VP8_HW_VLD_ADDR);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
229
writel(0x101, ld + VP8_WO_VLD_SRST);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
230
writel(0x101, hwb + VP8_WO_VLD_SRST);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
234
writel((val & 0xFFFFFFFE), misc + VP8_RW_MISC_SRST);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
236
writel(0x1, misc + VP8_RW_MISC_SYS_SEL);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
237
writel(0x17F, misc + VP8_RW_MISC_SPEC_CON);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
238
writel(0x71201100, misc + VP8_RW_MISC_FUNC_CON);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
239
writel(0x0, ld + VP8_WO_VLD_SRST);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
240
writel(0x0, hwb + VP8_WO_VLD_SRST);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
242
writel(0x1, misc + VP8_RW_MISC_DCM_CON);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
243
writel(0x1, hwd + VP8_RW_VP8_CTRL);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
254
writel(addr, hwd + VP8_BSASET);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
257
writel(val, hwd + VP8_BSDSET);
drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp8_if.c
271
writel(addr, hwd + VP8_BSASET);
drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_drv.c
65
writel(MTK_VENC_IRQ_STATUS_PAUSE, addr);
drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_drv.c
68
writel(MTK_VENC_IRQ_STATUS_SWITCH, addr);
drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_drv.c
71
writel(MTK_VENC_IRQ_STATUS_DRAM, addr);
drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_drv.c
74
writel(MTK_VENC_IRQ_STATUS_SPS, addr);
drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_drv.c
77
writel(MTK_VENC_IRQ_STATUS_PPS, addr);
drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_drv.c
80
writel(MTK_VENC_IRQ_STATUS_FRM, addr);
drivers/media/platform/mediatek/vpu/mtk_vpu.c
229
writel(val, vpu->reg.cfg + offset);
drivers/media/platform/mediatek/vpu/mtk_vpu.c
353
writel(len, &send_obj->len);
drivers/media/platform/mediatek/vpu/mtk_vpu.c
354
writel(id, &send_obj->id);
drivers/media/platform/nxp/dw100/dw100.c
210
writel(val, dw_dev->mmio + reg);
drivers/media/platform/nxp/imx-jpeg/mxc-jpeg-hw.c
107
writel(0xb0, reg + CAST_MODE);
drivers/media/platform/nxp/imx-jpeg/mxc-jpeg-hw.c
109
writel(0xa0, reg + CAST_MODE);
drivers/media/platform/nxp/imx-jpeg/mxc-jpeg-hw.c
112
writel(0x3ff, reg + CAST_CFG_MODE);
drivers/media/platform/nxp/imx-jpeg/mxc-jpeg-hw.c
122
writel(0x150, reg + CAST_MODE);
drivers/media/platform/nxp/imx-jpeg/mxc-jpeg-hw.c
124
writel(0x140, reg + CAST_MODE);
drivers/media/platform/nxp/imx-jpeg/mxc-jpeg-hw.c
132
writel(quality, reg + CAST_QUALITY);
drivers/media/platform/nxp/imx-jpeg/mxc-jpeg-hw.c
138
writel(MXC_DEC_EXIT_IDLE_MODE, reg + CAST_CTRL);
drivers/media/platform/nxp/imx-jpeg/mxc-jpeg-hw.c
145
writel(GLB_CTRL_JPG_EN, reg + GLB_CTRL);
drivers/media/platform/nxp/imx-jpeg/mxc-jpeg-hw.c
155
writel(GLB_CTRL_SLOT_EN(slot) | regval, reg + GLB_CTRL);
drivers/media/platform/nxp/imx-jpeg/mxc-jpeg-hw.c
164
writel(GLB_CTRL_L_ENDIAN(le) | regval, reg + GLB_CTRL); /* set */
drivers/media/platform/nxp/imx-jpeg/mxc-jpeg-hw.c
184
writel(desc | MXC_NXT_DESCPT_EN,
drivers/media/platform/nxp/imx-jpeg/mxc-jpeg-hw.c
190
writel(0, reg + MXC_SLOT_OFFSET(slot, SLOT_NXT_DESCPT_PTR));
drivers/media/platform/nxp/imx-jpeg/mxc-jpeg-hw.c
79
writel(0xFFFFFFFF, reg + MXC_SLOT_OFFSET(slot, SLOT_STATUS));
drivers/media/platform/nxp/imx-jpeg/mxc-jpeg-hw.c
80
writel(0xF0C, reg + MXC_SLOT_OFFSET(slot, SLOT_IRQ_EN));
drivers/media/platform/nxp/imx-jpeg/mxc-jpeg-hw.c
85
writel(0x0, reg + MXC_SLOT_OFFSET(slot, SLOT_IRQ_EN));
drivers/media/platform/nxp/imx-jpeg/mxc-jpeg-hw.c
86
writel(0xFFFFFFFF, reg + MXC_SLOT_OFFSET(slot, SLOT_STATUS));
drivers/media/platform/nxp/imx-jpeg/mxc-jpeg-hw.c
97
writel(GLB_CTRL_SFT_RST, reg + GLB_CTRL);
drivers/media/platform/nxp/imx-jpeg/mxc-jpeg.c
1007
writel(dec_ret, reg + MXC_SLOT_OFFSET(slot, SLOT_STATUS)); /* w1c */
drivers/media/platform/nxp/imx-mipi-csis.c
547
writel(val, csis->regs + reg);
drivers/media/platform/nxp/imx7-media-csi.c
292
writel(value, csi->regbase + offset);
drivers/media/platform/nxp/imx8-isi/imx8-isi-hw.c
23
writel(val, pipe->regs + reg);
drivers/media/platform/nxp/imx8mq-mipi-csi2.c
348
writel(val, state->regs + reg);
drivers/media/platform/nxp/mx2_emmaprp.c
304
writel(p_in, pcdev->base_emma + PRP_SOURCE_Y_PTR);
drivers/media/platform/nxp/mx2_emmaprp.c
305
writel(PRP_SIZE_WIDTH(s_width) | PRP_SIZE_HEIGHT(s_height),
drivers/media/platform/nxp/mx2_emmaprp.c
309
writel(p_out, pcdev->base_emma + PRP_DEST_Y_PTR);
drivers/media/platform/nxp/mx2_emmaprp.c
310
writel(p_out + d_size, pcdev->base_emma + PRP_DEST_CB_PTR);
drivers/media/platform/nxp/mx2_emmaprp.c
311
writel(p_out + d_size + (d_size >> 2),
drivers/media/platform/nxp/mx2_emmaprp.c
313
writel(PRP_SIZE_WIDTH(d_width) | PRP_SIZE_HEIGHT(d_height),
drivers/media/platform/nxp/mx2_emmaprp.c
318
writel(tmp | PRP_INTR_RDERR |
drivers/media/platform/nxp/mx2_emmaprp.c
327
writel(tmp | PRP_CNTL_CH2_OUT_YUV420 |
drivers/media/platform/nxp/mx2_emmaprp.c
343
writel(irqst, pcdev->base_emma + PRP_INTRSTATUS);
drivers/media/platform/nxp/mx2_emmaprp.c
356
writel(PRP_CNTL_SWRST, pcdev->base_emma + PRP_CNTL);
drivers/media/platform/qcom/camss/camss-csid-340.c
139
writel(CSID_RST_IRQ | CSID_RST_IFE_CLK | CSID_RST_PHY_CLK | CSID_RST_CSID_CLK,
drivers/media/platform/qcom/camss/camss-csid-680.c
174
writel(csid->reg_update, csid->base + CSID_REG_UPDATE_CMD);
drivers/media/platform/qcom/camss/camss-csid-680.c
181
writel(csid->reg_update, csid->base + CSID_REG_UPDATE_CMD);
drivers/media/platform/qcom/camss/camss-csid-680.c
193
writel(val, csid->base + CSID_CSI2_RX_CFG0);
drivers/media/platform/qcom/camss/camss-csid-680.c
198
writel(val, csid->base + CSID_CSI2_RX_CFG1);
drivers/media/platform/qcom/camss/camss-csid-680.c
210
writel(val, csid->base + CSID_RDI_CTRL(rdi));
drivers/media/platform/qcom/camss/camss-csid-680.c
218
writel(val, csid->camss->csid_wrapper_base +
drivers/media/platform/qcom/camss/camss-csid-680.c
236
writel(val, csid->base + CSID_RDI_FRM_DROP_PERIOD(vc));
drivers/media/platform/qcom/camss/camss-csid-680.c
257
writel(val, csid->base + CSID_RDI_CFG0(vc));
drivers/media/platform/qcom/camss/camss-csid-680.c
268
writel(val, csid->base + CSID_RDI_CFG1(vc));
drivers/media/platform/qcom/camss/camss-csid-680.c
271
writel(val, csid->base + CSID_RDI_IRQ_SUBSAMPLE_PERIOD(vc));
drivers/media/platform/qcom/camss/camss-csid-680.c
274
writel(val, csid->base + CSID_RDI_IRQ_SUBSAMPLE_PATTERN(vc));
drivers/media/platform/qcom/camss/camss-csid-680.c
277
writel(val, csid->base + CSID_RDI_CTRL(vc));
drivers/media/platform/qcom/camss/camss-csid-680.c
284
writel(val, csid->base + CSID_RDI_CFG0(vc));
drivers/media/platform/qcom/camss/camss-csid-680.c
317
writel(CSID_IRQ_CMD_CLEAR, csid->base + CSID_IRQ_CMD);
drivers/media/platform/qcom/camss/camss-csid-680.c
321
writel(val, csid->base + CSID_RESET_CFG);
drivers/media/platform/qcom/camss/camss-csid-680.c
324
writel(val, csid->base + CSID_RESET_CMD);
drivers/media/platform/qcom/camss/camss-csid-680.c
335
writel(CSID_CSI2_RDIN_RUP_DONE, csid->base + CSID_CSI2_RDIN_IRQ_MASK(i));
drivers/media/platform/qcom/camss/camss-csid-680.c
339
writel(~0u, csid->base + CSID_BUF_DONE_IRQ_CLEAR);
drivers/media/platform/qcom/camss/camss-csid-680.c
342
writel(~0u, csid->base + CSID_BUF_DONE_IRQ_MASK);
drivers/media/platform/qcom/camss/camss-csid-680.c
345
writel(~0u, csid->base + CSID_TOP_IRQ_MASK);
drivers/media/platform/qcom/camss/camss-csid-680.c
370
writel(val_top, csid->base + CSID_TOP_IRQ_CLEAR);
drivers/media/platform/qcom/camss/camss-csid-680.c
374
writel(val, csid->base + CSID_CSI2_RX_IRQ_CLEAR);
drivers/media/platform/qcom/camss/camss-csid-680.c
378
writel(buf_done_val, csid->base + CSID_BUF_DONE_IRQ_CLEAR);
drivers/media/platform/qcom/camss/camss-csid-680.c
384
writel(val, csid->base + CSID_CSI2_RDIN_IRQ_CLEAR(i));
drivers/media/platform/qcom/camss/camss-csid-680.c
394
writel(CSID_IRQ_CMD_CLEAR, csid->base + CSID_IRQ_CMD);
drivers/media/platform/qcom/camss/camss-csid-gen3.c
117
writel(val, csid->base + CSID_CSI2_RX_CFG0);
drivers/media/platform/qcom/camss/camss-csid-gen3.c
123
writel(val, csid->base + CSID_CSI2_RX_CFG1);
drivers/media/platform/qcom/camss/camss-csid-gen3.c
133
writel(val, csid->base + CSID_RDI_CTRL(rdi));
drivers/media/platform/qcom/camss/camss-csid-gen3.c
145
writel(val, csid->camss->csid_wrapper_base + CSID_IO_PATH_CFG0(csid->id));
drivers/media/platform/qcom/camss/camss-csid-gen3.c
183
writel(val, csid->base + CSID_RDI_CFG0(vc));
drivers/media/platform/qcom/camss/camss-csid-gen3.c
192
writel(val, csid->base + CSID_RDI_CFG1(vc));
drivers/media/platform/qcom/camss/camss-csid-gen3.c
195
writel(val, csid->base + CSID_RDI_IRQ_SUBSAMPLE_PERIOD(vc));
drivers/media/platform/qcom/camss/camss-csid-gen3.c
198
writel(val, csid->base + CSID_RDI_IRQ_SUBSAMPLE_PATTERN(vc));
drivers/media/platform/qcom/camss/camss-csid-gen3.c
201
writel(val, csid->base + CSID_RDI_CTRL(vc));
drivers/media/platform/qcom/camss/camss-csid-gen3.c
207
writel(val, csid->base + CSID_RDI_CFG0(vc));
drivers/media/platform/qcom/camss/camss-csid-gen3.c
236
writel(csid->reg_update, csid->base + CSID_RUP_AUP_CMD);
drivers/media/platform/qcom/camss/camss-csid-gen3.c
255
writel(val, csid->base + CSID_TOP_IRQ_CLEAR);
drivers/media/platform/qcom/camss/camss-csid-gen3.c
259
writel(val, csid->base + CSID_CSI2_RX_IRQ_CLEAR);
drivers/media/platform/qcom/camss/camss-csid-gen3.c
262
writel(buf_done_val, csid->base + CSID_BUF_DONE_IRQ_CLEAR);
drivers/media/platform/qcom/camss/camss-csid-gen3.c
268
writel(val, csid->base + CSID_CSI2_RDIN_IRQ_CLEAR(i));
drivers/media/platform/qcom/camss/camss-csid-gen3.c
285
writel(val, csid->base + CSID_IRQ_CMD);
drivers/media/platform/qcom/camss/camss-csid-gen3.c
307
writel(1, csid->base + CSID_TOP_IRQ_CLEAR);
drivers/media/platform/qcom/camss/camss-csid-gen3.c
308
writel(1, csid->base + CSID_IRQ_CMD);
drivers/media/platform/qcom/camss/camss-csid-gen3.c
309
writel(1, csid->base + CSID_TOP_IRQ_MASK);
drivers/media/platform/qcom/camss/camss-csid-gen3.c
313
writel(BIT(BUF_DONE_IRQ_STATUS_RDI_OFFSET + i),
drivers/media/platform/qcom/camss/camss-csid-gen3.c
315
writel(IRQ_CMD_CLEAR, csid->base + CSID_IRQ_CMD);
drivers/media/platform/qcom/camss/camss-csid-gen3.c
316
writel(BIT(BUF_DONE_IRQ_STATUS_RDI_OFFSET + i),
drivers/media/platform/qcom/camss/camss-csid-gen3.c
322
writel(val, csid->base + CSID_RST_CFG);
drivers/media/platform/qcom/camss/camss-csid-gen3.c
325
writel(val, csid->base + CSID_RST_CMD);
drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
810
writel(CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_SHOW_REV_ID, csiphy->base +
drivers/media/platform/qcom/camss/camss-ispif.c
181
writel(0x1, ispif->base + ISPIF_IRQ_GLOBAL_CLEAR_CMD);
drivers/media/platform/qcom/camss/camss-ispif.c
243
writel(0x1, ispif->base + ISPIF_IRQ_GLOBAL_CLEAR_CMD);
drivers/media/platform/qcom/camss/camss-ispif.c
606
writel(val, ispif->base + ISPIF_VFE_m_INTF_INPUT_SEL(vfe));
drivers/media/platform/qcom/camss/camss-ispif.c
648
writel(val, ispif->base + addr);
drivers/media/platform/qcom/camss/camss-ispif.c
711
writel(0x1, ispif->base + ISPIF_IRQ_GLOBAL_CLEAR_CMD);
drivers/media/platform/qcom/camss/camss-vfe-340.c
161
writel(TFE_IRQ_MASK_0_RST_DONE, vfe->base + TFE_IRQ_MASK_0);
drivers/media/platform/qcom/camss/camss-vfe-340.c
162
writel(TFE_GLOBAL_RESET_CMD_CORE, vfe->base + TFE_GLOBAL_RESET_CMD);
drivers/media/platform/qcom/camss/camss-vfe-340.c
231
writel(TFE_IRQ_MASK_0_RST_DONE | TFE_IRQ_MASK_0_BUS_WR,
drivers/media/platform/qcom/camss/camss-vfe-340.c
233
writel(TFE_BUS_IRQ_MASK_RUP_DONE_MASK | TFE_BUS_IRQ_MASK_BUF_DONE_MASK |
drivers/media/platform/qcom/camss/camss-vfe-340.c
267
writel(TFE_BUS_CLIENT_CFG_EN | TFE_BUS_CLIENT_CFG_MODE_FRAME,
drivers/media/platform/qcom/camss/camss-vfe-340.c
278
writel(0, vfe->base + TFE_BUS_CLIENT_CFG(wm));
drivers/media/platform/qcom/camss/camss-vfe-480.c
162
writel(IRQ_MASK_0_RESET_ACK | IRQ_MASK_0_BUS_TOP_IRQ,
drivers/media/platform/qcom/camss/camss-vfe-480.c
174
writel(bus_irq_mask, vfe->base + VFE_BUS_IRQ_MASK(0));
drivers/media/platform/qcom/camss/camss-vfe-680.c
141
writel(0u, vfe->base + VFE_TOP_IRQn_MASK(vfe, 0));
drivers/media/platform/qcom/camss/camss-vfe-680.c
142
writel(0u, vfe->base + VFE_TOP_IRQn_MASK(vfe, 1));
drivers/media/platform/qcom/camss/camss-vfe-680.c
143
writel(0u, vfe->base + VFE_BUS_IRQn_MASK(vfe, 0));
drivers/media/platform/qcom/camss/camss-vfe-680.c
144
writel(0u, vfe->base + VFE_BUS_IRQn_MASK(vfe, 1));
drivers/media/platform/qcom/camss/camss-vfe-680.c
152
writel(addr, vfe->base + VFE_BUS_IMAGE_ADDR(vfe, wm));
drivers/media/platform/qcom/camss/camss-vfe-680.c
166
writel(cfg, vfe->base + VFE_BUS_IMAGE_CFG0(vfe, wm));
drivers/media/platform/qcom/camss/camss-vfe-680.c
167
writel(0, vfe->base + VFE_BUS_IMAGE_CFG1(vfe, wm));
drivers/media/platform/qcom/camss/camss-vfe-680.c
168
writel(stride, vfe->base + VFE_BUS_IMAGE_CFG2(vfe, wm));
drivers/media/platform/qcom/camss/camss-vfe-680.c
169
writel(0, vfe->base + VFE_BUS_PACKER_CFG(vfe, wm));
drivers/media/platform/qcom/camss/camss-vfe-680.c
172
writel(pix->plane_fmt[0].bytesperline * pix->height,
drivers/media/platform/qcom/camss/camss-vfe-680.c
176
writel(VFE_BUS_MMU_PREFETCH_CFG_EN, vfe->base + VFE_BUS_MMU_PREFETCH_CFG(vfe, wm));
drivers/media/platform/qcom/camss/camss-vfe-680.c
177
writel(~0u, vfe->base + VFE_BUS_MMU_PREFETCH_MAX_OFFSET(vfe, wm));
drivers/media/platform/qcom/camss/camss-vfe-680.c
180
writel(1, vfe->base + VFE_BUS_FRAMEDROP_PATTERN(vfe, wm));
drivers/media/platform/qcom/camss/camss-vfe-680.c
181
writel(0, vfe->base + VFE_BUS_FRAMEDROP_PERIOD(vfe, wm));
drivers/media/platform/qcom/camss/camss-vfe-680.c
182
writel(1, vfe->base + VFE_BUS_IRQ_SUBSAMPLE_PATTERN(vfe, wm));
drivers/media/platform/qcom/camss/camss-vfe-680.c
183
writel(0, vfe->base + VFE_BUS_IRQ_SUBSAMPLE_PERIOD(vfe, wm));
drivers/media/platform/qcom/camss/camss-vfe-680.c
189
writel(VFE_BUS_WRITE_CLIENT_CFG_EN,
drivers/media/platform/qcom/camss/camss-vfe-680.c
200
writel(0, vfe->base + VFE_BUS_WRITE_CLIENT_CFG(vfe, wm));
drivers/media/platform/qcom/camss/camss-vfe-gen3.c
100
writel(VFE_DISABLE_DSCALING_DS4 | VFE_DISABLE_DSCALING_DS16,
drivers/media/platform/qcom/camss/camss-vfe-gen3.c
104
writel(0, vfe->base + VFE_BUS_WM_FRAMEDROP_PERIOD(wm));
drivers/media/platform/qcom/camss/camss-vfe-gen3.c
105
writel(1, vfe->base + VFE_BUS_WM_FRAMEDROP_PATTERN(wm));
drivers/media/platform/qcom/camss/camss-vfe-gen3.c
106
writel(0, vfe->base + VFE_BUS_WM_IRQ_SUBSAMPLE_PERIOD(wm));
drivers/media/platform/qcom/camss/camss-vfe-gen3.c
107
writel(1, vfe->base + VFE_BUS_WM_IRQ_SUBSAMPLE_PATTERN(wm));
drivers/media/platform/qcom/camss/camss-vfe-gen3.c
109
writel(1, vfe->base + VFE_BUS_WM_MMU_PREFETCH_CFG(wm));
drivers/media/platform/qcom/camss/camss-vfe-gen3.c
110
writel(0xFFFFFFFF, vfe->base + VFE_BUS_WM_MMU_PREFETCH_MAX_OFFSET(wm));
drivers/media/platform/qcom/camss/camss-vfe-gen3.c
112
writel(WM_CFG_EN | WM_CFG_MODE, vfe->base + VFE_BUS_WM_CFG(wm));
drivers/media/platform/qcom/camss/camss-vfe-gen3.c
118
writel(0, vfe->base + VFE_BUS_WM_CFG(wm));
drivers/media/platform/qcom/camss/camss-vfe-gen3.c
127
writel(addr, vfe->base + VFE_BUS_WM_IMAGE_ADDR(wm));
drivers/media/platform/qcom/camss/camss-vfe-gen3.c
129
writel((addr >> 8), vfe->base + VFE_BUS_WM_IMAGE_ADDR(wm));
drivers/media/platform/qcom/camss/camss-vfe-gen3.c
81
writel(WM_CGC_OVERRIDE_ALL, vfe->base + VFE_BUS_WM_CGC_OVERRIDE);
drivers/media/platform/qcom/camss/camss-vfe-gen3.c
83
writel(0x0, vfe->base + VFE_BUS_WM_TEST_BUS_CTRL);
drivers/media/platform/qcom/camss/camss-vfe-gen3.c
86
writel(ALIGN(pix->plane_fmt[0].bytesperline, 16) * pix->height,
drivers/media/platform/qcom/camss/camss-vfe-gen3.c
89
writel(ALIGN(pix->plane_fmt[0].bytesperline, 16) * pix->height >> 8,
drivers/media/platform/qcom/camss/camss-vfe-gen3.c
92
writel((WM_IMAGE_CFG_0_DEFAULT_WIDTH & 0xFFFF),
drivers/media/platform/qcom/camss/camss-vfe-gen3.c
94
writel(WM_IMAGE_CFG_2_DEFAULT_STRIDE,
drivers/media/platform/qcom/camss/camss-vfe-gen3.c
96
writel(0, vfe->base + VFE_BUS_WM_PACKER_CFG(wm));
drivers/media/platform/qcom/iris/iris_platform_gen1.c
265
writel(0x0, core->reg_base + 0xB0088);
drivers/media/platform/qcom/iris/iris_platform_gen2.c
761
writel(0x0, core->reg_base + 0xB0088);
drivers/media/platform/qcom/iris/iris_vpu3x.c
100
writel(REQ_POWER_DOWN_PREP, core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL);
drivers/media/platform/qcom/iris/iris_vpu3x.c
112
writel(0, core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL);
drivers/media/platform/qcom/iris/iris_vpu3x.c
126
writel(0, core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL);
drivers/media/platform/qcom/iris/iris_vpu3x.c
128
writel(CORE_BRIDGE_SW_RESET | CORE_BRIDGE_HW_RESET_DISABLE,
drivers/media/platform/qcom/iris/iris_vpu3x.c
130
writel(CORE_BRIDGE_HW_RESET_DISABLE, core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET);
drivers/media/platform/qcom/iris/iris_vpu3x.c
131
writel(0x0, core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET);
drivers/media/platform/qcom/iris/iris_vpu3x.c
144
writel(MSK_SIGNAL_FROM_TENSILICA | MSK_CORE_POWER_ON, core->reg_base + CPU_CS_X2RPMH);
drivers/media/platform/qcom/iris/iris_vpu3x.c
146
writel(REQ_POWER_DOWN_PREP, core->reg_base + WRAPPER_IRIS_CPU_NOC_LPI_CONTROL);
drivers/media/platform/qcom/iris/iris_vpu3x.c
153
writel(0x0, core->reg_base + WRAPPER_DEBUG_BRIDGE_LPI_CONTROL);
drivers/media/platform/qcom/iris/iris_vpu3x.c
160
writel(CTL_AXI_CLK_HALT | CTL_CLK_HALT,
drivers/media/platform/qcom/iris/iris_vpu3x.c
162
writel(RESET_HIGH, core->reg_base + WRAPPER_TZ_QNS4PDXFIFO_RESET);
drivers/media/platform/qcom/iris/iris_vpu3x.c
163
writel(0x0, core->reg_base + WRAPPER_TZ_QNS4PDXFIFO_RESET);
drivers/media/platform/qcom/iris/iris_vpu3x.c
164
writel(0x0, core->reg_base + WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG);
drivers/media/platform/qcom/iris/iris_vpu3x.c
171
writel(val, core->reg_base + AON_WRAPPER_MVP_NOC_CORE_CLK_CONTROL);
drivers/media/platform/qcom/iris/iris_vpu3x.c
176
writel(val, core->reg_base + AON_WRAPPER_MVP_NOC_CORE_SW_RESET);
drivers/media/platform/qcom/iris/iris_vpu3x.c
187
writel(val, core->reg_base + AON_WRAPPER_SPARE);
drivers/media/platform/qcom/iris/iris_vpu3x.c
194
writel(val, core->reg_base + AON_WRAPPER_MVP_NOC_CORE_SW_RESET);
drivers/media/platform/qcom/iris/iris_vpu3x.c
201
writel(0, core->reg_base + AON_WRAPPER_SPARE);
drivers/media/platform/qcom/iris/iris_vpu3x.c
206
writel(val, core->reg_base + AON_WRAPPER_MVP_NOC_CORE_CLK_CONTROL);
drivers/media/platform/qcom/iris/iris_vpu3x.c
42
writel(CORE_CLK_RUN, core->reg_base + WRAPPER_CORE_CLOCK_CONFIG);
drivers/media/platform/qcom/iris/iris_vpu3x.c
51
writel(VIDEO_NOC_RESET_REQ, core->reg_base + AON_WRAPPER_MVP_NOC_RESET_REQ);
drivers/media/platform/qcom/iris/iris_vpu3x.c
58
writel(0x0, core->reg_base + AON_WRAPPER_MVP_NOC_RESET_REQ);
drivers/media/platform/qcom/iris/iris_vpu3x.c
65
writel(CORE_BRIDGE_SW_RESET | CORE_BRIDGE_HW_RESET_DISABLE,
drivers/media/platform/qcom/iris/iris_vpu3x.c
67
writel(CORE_BRIDGE_HW_RESET_DISABLE, core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET);
drivers/media/platform/qcom/iris/iris_vpu3x.c
68
writel(0x0, core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET);
drivers/media/platform/qcom/iris/iris_vpu3x.c
88
writel(CORE_CLK_RUN, core->reg_base + WRAPPER_CORE_CLOCK_CONFIG);
drivers/media/platform/qcom/iris/iris_vpu4x.c
101
writel(0x0, core->reg_base + WRAPPER_CORE_CLOCK_CONFIG);
drivers/media/platform/qcom/iris/iris_vpu4x.c
104
writel(REQ_POWER_DOWN_PREP, core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL);
drivers/media/platform/qcom/iris/iris_vpu4x.c
114
writel(0x0, core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL);
drivers/media/platform/qcom/iris/iris_vpu4x.c
122
writel(0x080200, core->reg_base + AON_WRAPPER_MVP_NOC_RESET_REQ);
drivers/media/platform/qcom/iris/iris_vpu4x.c
128
writel(0x0, core->reg_base + AON_WRAPPER_MVP_NOC_RESET_SYNCRST);
drivers/media/platform/qcom/iris/iris_vpu4x.c
129
writel(0x0, core->reg_base + AON_WRAPPER_MVP_NOC_RESET_REQ);
drivers/media/platform/qcom/iris/iris_vpu4x.c
135
writel(CORE_BRIDGE_SW_RESET | CORE_BRIDGE_HW_RESET_DISABLE, core->reg_base +
drivers/media/platform/qcom/iris/iris_vpu4x.c
137
writel(CORE_BRIDGE_HW_RESET_DISABLE, core->reg_base + CPU_CS_APV_BRIDGE_SYNC_RESET);
drivers/media/platform/qcom/iris/iris_vpu4x.c
138
writel(0x0, core->reg_base + CPU_CS_APV_BRIDGE_SYNC_RESET);
drivers/media/platform/qcom/iris/iris_vpu4x.c
147
writel(CORE_BRIDGE_SW_RESET | CORE_BRIDGE_HW_RESET_DISABLE, core->reg_base +
drivers/media/platform/qcom/iris/iris_vpu4x.c
149
writel(CORE_BRIDGE_HW_RESET_DISABLE, core->reg_base + CPU_CS_APV_BRIDGE_SYNC_RESET);
drivers/media/platform/qcom/iris/iris_vpu4x.c
150
writel(0x0, core->reg_base + CPU_CS_APV_BRIDGE_SYNC_RESET);
drivers/media/platform/qcom/iris/iris_vpu4x.c
155
writel(CORE_BRIDGE_SW_RESET | CORE_BRIDGE_HW_RESET_DISABLE, core->reg_base +
drivers/media/platform/qcom/iris/iris_vpu4x.c
157
writel(CORE_BRIDGE_HW_RESET_DISABLE, core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET);
drivers/media/platform/qcom/iris/iris_vpu4x.c
158
writel(0x0, core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET);
drivers/media/platform/qcom/iris/iris_vpu4x.c
306
writel(0x0, core->reg_base + WRAPPER_CORE_CLOCK_CONFIG);
drivers/media/platform/qcom/iris/iris_vpu4x.c
312
writel(REQ_POWER_DOWN_PREP, core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL);
drivers/media/platform/qcom/iris/iris_vpu4x.c
322
writel(0x0, core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL);
drivers/media/platform/qcom/iris/iris_vpu4x.c
330
writel(MVP_NOC_RESET_REQ_MASK, core->reg_base + AON_WRAPPER_MVP_NOC_RESET_REQ);
drivers/media/platform/qcom/iris/iris_vpu4x.c
336
writel(0x0, core->reg_base + AON_WRAPPER_MVP_NOC_RESET_SYNCRST);
drivers/media/platform/qcom/iris/iris_vpu4x.c
337
writel(0x0, core->reg_base + AON_WRAPPER_MVP_NOC_RESET_REQ);
drivers/media/platform/qcom/iris/iris_vpu4x.c
343
writel(CORE_BRIDGE_SW_RESET | CORE_BRIDGE_HW_RESET_DISABLE, core->reg_base +
drivers/media/platform/qcom/iris/iris_vpu4x.c
345
writel(CORE_BRIDGE_HW_RESET_DISABLE, core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET);
drivers/media/platform/qcom/iris/iris_vpu4x.c
346
writel(0x0, core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET);
drivers/media/platform/qcom/iris/iris_vpu_common.c
100
writel(0x0, core->reg_base + CPU_CS_X2RPMH);
drivers/media/platform/qcom/iris/iris_vpu_common.c
107
writel(1 << CPU_IC_SOFTINT_H2A_SHFT, core->reg_base + CPU_IC_SOFTINT);
drivers/media/platform/qcom/iris/iris_vpu_common.c
122
writel(CLEAR_XTENSA2HOST_INTR, core->reg_base + CPU_CS_A2HSOFTINTCLR);
drivers/media/platform/qcom/iris/iris_vpu_common.c
183
writel(MSK_SIGNAL_FROM_TENSILICA | MSK_CORE_POWER_ON, core->reg_base + CPU_CS_X2RPMH);
drivers/media/platform/qcom/iris/iris_vpu_common.c
186
writel(REQ_POWER_DOWN_PREP, core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL);
drivers/media/platform/qcom/iris/iris_vpu_common.c
194
writel(REQ_POWER_DOWN_PREP, core->reg_base + WRAPPER_IRIS_CPU_NOC_LPI_CONTROL);
drivers/media/platform/qcom/iris/iris_vpu_common.c
201
writel(0x0, core->reg_base + WRAPPER_DEBUG_BRIDGE_LPI_CONTROL);
drivers/media/platform/qcom/iris/iris_vpu_common.c
208
writel(CTL_AXI_CLK_HALT | CTL_CLK_HALT,
drivers/media/platform/qcom/iris/iris_vpu_common.c
210
writel(RESET_HIGH, core->reg_base + WRAPPER_TZ_QNS4PDXFIFO_RESET);
drivers/media/platform/qcom/iris/iris_vpu_common.c
211
writel(0x0, core->reg_base + WRAPPER_TZ_QNS4PDXFIFO_RESET);
drivers/media/platform/qcom/iris/iris_vpu_common.c
212
writel(0x0, core->reg_base + WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG);
drivers/media/platform/qcom/iris/iris_vpu_common.c
318
writel(MSK_SIGNAL_FROM_TENSILICA | MSK_CORE_POWER_ON, core->reg_base + CPU_CS_X2RPMH);
drivers/media/platform/qcom/iris/iris_vpu_common.c
320
writel(REQ_POWER_DOWN_PREP, core->reg_base + WRAPPER_IRIS_CPU_NOC_LPI_CONTROL);
drivers/media/platform/qcom/iris/iris_vpu_common.c
327
writel(0, core->reg_base + WRAPPER_IRIS_CPU_NOC_LPI_CONTROL);
drivers/media/platform/qcom/iris/iris_vpu_common.c
332
writel(REQ_POWER_DOWN_PREP, core->reg_base +
drivers/media/platform/qcom/iris/iris_vpu_common.c
343
writel(0, core->reg_base + AON_WRAPPER_MVP_VIDEO_CTL_NOC_LPI_CONTROL);
drivers/media/platform/qcom/iris/iris_vpu_common.c
356
writel(0, core->reg_base + AON_WRAPPER_MVP_VIDEO_CTL_NOC_LPI_CONTROL);
drivers/media/platform/qcom/iris/iris_vpu_common.c
358
writel(0, core->reg_base + WRAPPER_DEBUG_BRIDGE_LPI_CONTROL);
drivers/media/platform/qcom/iris/iris_vpu_common.c
409
writel(0x1, core->reg_base + WRAPPER_IRIS_VCODEC_VPU_WRAPPER_SPARE_0);
drivers/media/platform/qcom/iris/iris_vpu_common.c
41
writel(mask_val, core->reg_base + WRAPPER_INTR_MASK);
drivers/media/platform/qcom/iris/iris_vpu_common.c
54
writel(value, core->reg_base + UC_REGION_ADDR);
drivers/media/platform/qcom/iris/iris_vpu_common.c
58
writel(value, core->reg_base + UC_REGION_SIZE);
drivers/media/platform/qcom/iris/iris_vpu_common.c
61
writel(value, core->reg_base + QTBL_ADDR);
drivers/media/platform/qcom/iris/iris_vpu_common.c
63
writel(QTBL_ENABLE, core->reg_base + QTBL_INFO);
drivers/media/platform/qcom/iris/iris_vpu_common.c
67
writel(value, core->reg_base + SFR_ADDR);
drivers/media/platform/qcom/iris/iris_vpu_common.c
80
writel(ctrl_init, core->reg_base + CTRL_INIT);
drivers/media/platform/qcom/iris/iris_vpu_common.c
81
writel(0x1, core->reg_base + CPU_CS_SCIACMDARG3);
drivers/media/platform/qcom/iris/iris_vpu_common.c
99
writel(HOST2XTENSA_INTR_ENABLE, core->reg_base + CPU_CS_H2XSOFTINTEN);
drivers/media/platform/qcom/venus/firmware.c
179
writel(reg, wrapper_tz_base + WRAPPER_TZ_XTSS_SW_RESET);
drivers/media/platform/qcom/venus/firmware.c
184
writel(reg, wrapper_base + WRAPPER_A9SS_SW_RESET);
drivers/media/platform/qcom/venus/firmware.c
206
writel(CPU_CS_VCICMD_ARP_OFF, cpu_cs_base + CPU_CS_VCICMD);
drivers/media/platform/qcom/venus/firmware.c
37
writel(0, wrapper_base + WRAPPER_FW_START_ADDR);
drivers/media/platform/qcom/venus/firmware.c
38
writel(fw_size, wrapper_base + WRAPPER_FW_END_ADDR);
drivers/media/platform/qcom/venus/firmware.c
39
writel(0, wrapper_base + WRAPPER_CPA_START_ADDR);
drivers/media/platform/qcom/venus/firmware.c
40
writel(fw_size, wrapper_base + WRAPPER_CPA_END_ADDR);
drivers/media/platform/qcom/venus/firmware.c
41
writel(fw_size, wrapper_base + WRAPPER_NONPIX_START_ADDR);
drivers/media/platform/qcom/venus/firmware.c
42
writel(fw_size, wrapper_base + WRAPPER_NONPIX_END_ADDR);
drivers/media/platform/qcom/venus/firmware.c
46
writel(0, wrapper_base + WRAPPER_TZ_XTSS_SW_RESET);
drivers/media/platform/qcom/venus/firmware.c
48
writel(0x0, wrapper_base + WRAPPER_CPU_CGC_DIS);
drivers/media/platform/qcom/venus/firmware.c
49
writel(0x0, wrapper_base + WRAPPER_CPU_CLOCK_CONFIG);
drivers/media/platform/qcom/venus/firmware.c
52
writel(0, wrapper_base + WRAPPER_A9SS_SW_RESET);
drivers/media/platform/qcom/venus/firmware.c
71
writel(WRAPPER_XTSS_SW_RESET_BIT,
drivers/media/platform/qcom/venus/firmware.c
74
writel(WRAPPER_A9SS_SW_RESET_BIT,
drivers/media/platform/qcom/venus/hfi_venus.c
1163
writel(1, cpu_cs_base + CPU_CS_A2HSOFTINTCLR);
drivers/media/platform/qcom/venus/hfi_venus.c
1165
writel(status, wrapper_base + WRAPPER_INTR_CLEAR);
drivers/media/platform/qcom/venus/hfi_venus.c
375
writel(tbl[i].value, hdev->core->base + tbl[i].reg);
drivers/media/platform/qcom/venus/hfi_venus.c
388
writel(clear_bit, cpu_ic_base + CPU_IC_SOFTINT);
drivers/media/platform/qcom/venus/hfi_venus.c
484
writel(mask_val, wrapper_base + WRAPPER_INTR_MASK);
drivers/media/platform/qcom/venus/hfi_venus.c
486
writel(1, cpu_cs_base + CPU_CS_SCIACMDARG3);
drivers/media/platform/qcom/venus/hfi_venus.c
488
writel(BIT(VIDC_CTRL_INIT_CTRL_SHIFT), cpu_cs_base + VIDC_CTRL_INIT);
drivers/media/platform/qcom/venus/hfi_venus.c
505
writel(0x1, cpu_cs_base + CPU_CS_H2XSOFTINTEN_V6);
drivers/media/platform/qcom/venus/hfi_venus.c
508
writel(0x0, cpu_cs_base + CPU_CS_X2RPMH_V6);
drivers/media/platform/qcom/venus/hfi_venus.c
545
writel(hdev->ifaceq_table.da, cpu_cs_base + UC_REGION_ADDR);
drivers/media/platform/qcom/venus/hfi_venus.c
546
writel(SHARED_QSIZE, cpu_cs_base + UC_REGION_SIZE);
drivers/media/platform/qcom/venus/hfi_venus.c
547
writel(hdev->ifaceq_table.da, cpu_cs_base + CPU_CS_SCIACMDARG2);
drivers/media/platform/qcom/venus/hfi_venus.c
548
writel(0x01, cpu_cs_base + CPU_CS_SCIACMDARG1);
drivers/media/platform/qcom/venus/hfi_venus.c
550
writel(hdev->sfr.da, cpu_cs_base + SFR_ADDR);
drivers/media/platform/qcom/venus/hfi_venus.c
578
writel(0x3, cpu_cs_base + CPU_CS_X2RPMH_V6);
drivers/media/platform/qcom/venus/hfi_venus.c
583
writel(0x1, aon_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL);
drivers/media/platform/qcom/venus/hfi_venus.c
594
writel(mask_val, wrapper_base + WRAPPER_DEBUG_BRIDGE_LPI_CONTROL_V6);
drivers/media/platform/qcom/venus/hfi_venus.c
596
writel(0x00, wrapper_base + WRAPPER_DEBUG_BRIDGE_LPI_CONTROL_V6);
drivers/media/platform/qcom/venus/hfi_venus.c
613
writel(val, wrapper_base + WRAPPER_CPU_AXI_HALT);
drivers/media/platform/qcom/venus/hfi_venus.c
631
writel(val, vbif_base + VBIF_AXI_HALT_CTRL0);
drivers/media/platform/qcom/venus/pm_helpers.c
349
writel(0, ctrl);
drivers/media/platform/qcom/venus/pm_helpers.c
351
writel(1, ctrl);
drivers/media/platform/qcom/venus/pm_helpers.c
440
writel(0, ctrl);
drivers/media/platform/qcom/venus/pm_helpers.c
446
writel(1, ctrl);
drivers/media/platform/raspberrypi/pisp_be/pisp_be.c
236
writel(val, pispbe->be_reg_base + offset);
drivers/media/platform/raspberrypi/rp1-cfe/cfe.c
328
writel(val, cfe->mipi_cfg_base + offset);
drivers/media/platform/raspberrypi/rp1-cfe/csi2.c
116
writel(val, csi2->base + offset);
drivers/media/platform/raspberrypi/rp1-cfe/dphy.c
43
writel(data, dphy->base + offset);
drivers/media/platform/raspberrypi/rp1-cfe/pisp-fe.c
154
writel(val, fe->base + offset);
drivers/media/platform/renesas/rcar_drif.c
243
writel(data, ch->base + offset);
drivers/media/platform/renesas/rzv2h-ivc/rzv2h-ivc-dev.c
19
writel(val, ivc->base + addr);
drivers/media/platform/renesas/rzv2h-ivc/rzv2h-ivc-dev.c
33
writel(new, ivc->base + addr);
drivers/media/platform/rockchip/rga/rga.h
131
writel(value, rga->regs + reg);
drivers/media/platform/rockchip/rkcif/rkcif-capture-dvp.c
628
writel(val, rkcif->base_addr + addr);
drivers/media/platform/rockchip/rkcif/rkcif-capture-mipi.c
534
writel(val, interface->rkcif->base_addr + addr);
drivers/media/platform/rockchip/rkcif/rkcif-capture-mipi.c
546
writel(val, stream->rkcif->base_addr + addr);
drivers/media/platform/rockchip/rkisp1/rkisp1-common.h
563
writel(val, rkisp1->base_addr + addr);
drivers/media/platform/rockchip/rkvdec/rkvdec-h264.c
439
writel(1, rkvdec->regs + RKVDEC_REG_PREF_LUMA_CACHE_COMMAND);
drivers/media/platform/rockchip/rkvdec/rkvdec-h264.c
440
writel(1, rkvdec->regs + RKVDEC_REG_PREF_CHR_CACHE_COMMAND);
drivers/media/platform/rockchip/rkvdec/rkvdec-h264.c
443
writel(RKVDEC_INTERRUPT_DEC_E | RKVDEC_CONFIG_DEC_CLK_GATE_E |
drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c
581
writel(1, rkvdec->regs + RKVDEC_REG_PREF_LUMA_CACHE_COMMAND);
drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c
582
writel(1, rkvdec->regs + RKVDEC_REG_PREF_CHR_CACHE_COMMAND);
drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c
590
writel(RKVDEC_INTERRUPT_DEC_E | RKVDEC_CONFIG_DEC_CLK_GATE_E |
drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-h264.c
449
writel(VDPU381_DEC_E_BIT, rkvdec->regs + VDPU381_REG_DEC_E);
drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-hevc.c
619
writel(VDPU381_DEC_E_BIT, rkvdec->regs + VDPU381_REG_DEC_E);
drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-h264.c
520
writel(timeout_threshold, rkvdec->link + VDPU383_LINK_TIMEOUT_THRESHOLD);
drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-h264.c
521
writel(0, rkvdec->link + VDPU383_LINK_IP_ENABLE);
drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-h264.c
522
writel(VDPU383_DEC_E_BIT, rkvdec->link + VDPU383_LINK_DEC_ENABLE);
drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-hevc.c
630
writel(timeout_threshold, rkvdec->link + VDPU383_LINK_TIMEOUT_THRESHOLD);
drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-hevc.c
631
writel(VDPU383_IP_CRU_MODE, rkvdec->link + VDPU383_LINK_IP_ENABLE);
drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-hevc.c
632
writel(VDPU383_DEC_E_BIT, rkvdec->link + VDPU383_LINK_DEC_ENABLE);
drivers/media/platform/rockchip/rkvdec/rkvdec-vp9.c
791
writel(1, rkvdec->regs + RKVDEC_REG_PREF_LUMA_CACHE_COMMAND);
drivers/media/platform/rockchip/rkvdec/rkvdec-vp9.c
792
writel(1, rkvdec->regs + RKVDEC_REG_PREF_CHR_CACHE_COMMAND);
drivers/media/platform/rockchip/rkvdec/rkvdec-vp9.c
798
writel(RKVDEC_INTERRUPT_DEC_E | RKVDEC_CONFIG_DEC_CLK_GATE_E |
drivers/media/platform/rockchip/rkvdec/rkvdec.c
1135
writel(reg, rkvdec->regs + RKVDEC_REG_QOS_CTRL);
drivers/media/platform/rockchip/rkvdec/rkvdec.c
1444
writel(0, rkvdec->regs + RKVDEC_REG_INTERRUPT);
drivers/media/platform/rockchip/rkvdec/rkvdec.c
1468
writel(0, rkvdec->regs + VDPU381_REG_STA_INT);
drivers/media/platform/rockchip/rkvdec/rkvdec.c
1497
writel(FIELD_PREP_WM16(VDPU383_STA_INT_ALL, 0), rkvdec->link + VDPU383_LINK_STA_INT);
drivers/media/platform/rockchip/rkvdec/rkvdec.c
1499
writel(FIELD_PREP_WM16(VDPU383_INT_EN_IRQ | VDPU383_INT_EN_LINE_IRQ, 0),
drivers/media/platform/rockchip/rkvdec/rkvdec.c
1609
writel(RKVDEC_IRQ_DIS, rkvdec->regs + RKVDEC_REG_INTERRUPT);
drivers/media/platform/samsung/exynos-gsc/gsc-core.h
448
writel(cfg, dev->regs + GSC_ENABLE);
drivers/media/platform/samsung/exynos-gsc/gsc-core.h
468
writel(cfg, dev->regs + GSC_IRQ);
drivers/media/platform/samsung/exynos-gsc/gsc-regs.c
102
writel(addr->y, dev->regs + GSC_OUT_BASE_ADDR_Y(index));
drivers/media/platform/samsung/exynos-gsc/gsc-regs.c
103
writel(addr->cb, dev->regs + GSC_OUT_BASE_ADDR_CB(index));
drivers/media/platform/samsung/exynos-gsc/gsc-regs.c
104
writel(addr->cr, dev->regs + GSC_OUT_BASE_ADDR_CR(index));
drivers/media/platform/samsung/exynos-gsc/gsc-regs.c
117
writel(cfg, dev->regs + GSC_IN_CON);
drivers/media/platform/samsung/exynos-gsc/gsc-regs.c
129
writel(cfg, dev->regs + GSC_SRCIMG_OFFSET);
drivers/media/platform/samsung/exynos-gsc/gsc-regs.c
134
writel(cfg, dev->regs + GSC_SRCIMG_SIZE);
drivers/media/platform/samsung/exynos-gsc/gsc-regs.c
139
writel(cfg, dev->regs + GSC_CROPPED_SIZE);
drivers/media/platform/samsung/exynos-gsc/gsc-regs.c
159
writel(cfg, dev->regs + GSC_IN_CON);
drivers/media/platform/samsung/exynos-gsc/gsc-regs.c
16
writel(GSC_SW_RESET_SRESET, dev->regs + GSC_SW_RESET);
drivers/media/platform/samsung/exynos-gsc/gsc-regs.c
173
writel(cfg, dev->regs + GSC_IN_CON);
drivers/media/platform/samsung/exynos-gsc/gsc-regs.c
215
writel(cfg, dev->regs + GSC_IN_CON);
drivers/media/platform/samsung/exynos-gsc/gsc-regs.c
230
writel(cfg, dev->regs + GSC_OUT_CON);
drivers/media/platform/samsung/exynos-gsc/gsc-regs.c
243
writel(cfg, dev->regs + GSC_DSTIMG_OFFSET);
drivers/media/platform/samsung/exynos-gsc/gsc-regs.c
247
writel(cfg, dev->regs + GSC_DSTIMG_SIZE);
drivers/media/platform/samsung/exynos-gsc/gsc-regs.c
259
writel(cfg, dev->regs + GSC_SCALED_SIZE);
drivers/media/platform/samsung/exynos-gsc/gsc-regs.c
279
writel(cfg, dev->regs + GSC_OUT_CON);
drivers/media/platform/samsung/exynos-gsc/gsc-regs.c
293
writel(cfg, dev->regs + GSC_OUT_CON);
drivers/media/platform/samsung/exynos-gsc/gsc-regs.c
339
writel(cfg, dev->regs + GSC_OUT_CON);
drivers/media/platform/samsung/exynos-gsc/gsc-regs.c
351
writel(cfg, dev->regs + GSC_PRE_SCALE_RATIO);
drivers/media/platform/samsung/exynos-gsc/gsc-regs.c
361
writel(cfg, dev->regs + GSC_MAIN_H_RATIO);
drivers/media/platform/samsung/exynos-gsc/gsc-regs.c
364
writel(cfg, dev->regs + GSC_MAIN_V_RATIO);
drivers/media/platform/samsung/exynos-gsc/gsc-regs.c
397
writel(cfg, dev->regs + GSC_IN_CON);
drivers/media/platform/samsung/exynos-gsc/gsc-regs.c
415
writel(cfg, dev->regs + GSC_OUT_CON);
drivers/media/platform/samsung/exynos-gsc/gsc-regs.c
425
writel(cfg, dev->regs + GSC_ENABLE);
drivers/media/platform/samsung/exynos-gsc/gsc-regs.c
43
writel(cfg, dev->regs + GSC_IRQ);
drivers/media/platform/samsung/exynos-gsc/gsc-regs.c
55
writel(cfg, dev->regs + GSC_IRQ);
drivers/media/platform/samsung/exynos-gsc/gsc-regs.c
67
writel(cfg, dev->regs + GSC_IN_BASE_ADDR_Y_MASK);
drivers/media/platform/samsung/exynos-gsc/gsc-regs.c
68
writel(cfg, dev->regs + GSC_IN_BASE_ADDR_CB_MASK);
drivers/media/platform/samsung/exynos-gsc/gsc-regs.c
69
writel(cfg, dev->regs + GSC_IN_BASE_ADDR_CR_MASK);
drivers/media/platform/samsung/exynos-gsc/gsc-regs.c
81
writel(cfg, dev->regs + GSC_OUT_BASE_ADDR_Y_MASK);
drivers/media/platform/samsung/exynos-gsc/gsc-regs.c
82
writel(cfg, dev->regs + GSC_OUT_BASE_ADDR_CB_MASK);
drivers/media/platform/samsung/exynos-gsc/gsc-regs.c
83
writel(cfg, dev->regs + GSC_OUT_BASE_ADDR_CR_MASK);
drivers/media/platform/samsung/exynos-gsc/gsc-regs.c
91
writel(addr->y, dev->regs + GSC_IN_BASE_ADDR_Y(index));
drivers/media/platform/samsung/exynos-gsc/gsc-regs.c
92
writel(addr->cb, dev->regs + GSC_IN_BASE_ADDR_CB(index));
drivers/media/platform/samsung/exynos-gsc/gsc-regs.c
93
writel(addr->cr, dev->regs + GSC_IN_BASE_ADDR_CR(index));
drivers/media/platform/samsung/exynos4-is/fimc-is.h
331
writel(v, is->regs + offset);
drivers/media/platform/samsung/exynos4-is/fimc-is.h
341
writel(v, is->pmu_regs + offset);
drivers/media/platform/samsung/exynos4-is/fimc-lite-reg.c
108
writel(cfg, dev->regs + FLITE_REG_CIGCTRL);
drivers/media/platform/samsung/exynos4-is/fimc-lite-reg.c
147
writel(cfg, dev->regs + FLITE_REG_CIGCTRL);
drivers/media/platform/samsung/exynos4-is/fimc-lite-reg.c
154
writel(cfg, dev->regs + FLITE_REG_CISRCSIZE);
drivers/media/platform/samsung/exynos4-is/fimc-lite-reg.c
167
writel(cfg, dev->regs + FLITE_REG_CIWDOFST);
drivers/media/platform/samsung/exynos4-is/fimc-lite-reg.c
173
writel(cfg, dev->regs + FLITE_REG_CIWDOFST2);
drivers/media/platform/samsung/exynos4-is/fimc-lite-reg.c
184
writel(cfg, dev->regs + FLITE_REG_CIGENERAL);
drivers/media/platform/samsung/exynos4-is/fimc-lite-reg.c
212
writel(cfg, dev->regs + FLITE_REG_CIGCTRL);
drivers/media/platform/samsung/exynos4-is/fimc-lite-reg.c
226
writel(cfg, dev->regs + FLITE_REG_CIODMAFMT);
drivers/media/platform/samsung/exynos4-is/fimc-lite-reg.c
245
writel(cfg | pixcode[i][1], dev->regs + FLITE_REG_CIODMAFMT);
drivers/media/platform/samsung/exynos4-is/fimc-lite-reg.c
256
writel(cfg, dev->regs + FLITE_REG_CIOCAN);
drivers/media/platform/samsung/exynos4-is/fimc-lite-reg.c
262
writel(cfg, dev->regs + FLITE_REG_CIOOFF);
drivers/media/platform/samsung/exynos4-is/fimc-lite-reg.c
27
writel(cfg, dev->regs + FLITE_REG_CIGCTRL);
drivers/media/platform/samsung/exynos4-is/fimc-lite-reg.c
276
writel(buf->addr, dev->regs + FLITE_REG_CIOSA);
drivers/media/platform/samsung/exynos4-is/fimc-lite-reg.c
278
writel(buf->addr, dev->regs + FLITE_REG_CIOSAN(index - 1));
drivers/media/platform/samsung/exynos4-is/fimc-lite-reg.c
282
writel(cfg, dev->regs + FLITE_REG_CIFCNTSEQ);
drivers/media/platform/samsung/exynos4-is/fimc-lite-reg.c
294
writel(cfg, dev->regs + FLITE_REG_CIFCNTSEQ);
drivers/media/platform/samsung/exynos4-is/fimc-lite-reg.c
305
writel(cfg, dev->regs + FLITE_REG_CIGCTRL);
drivers/media/platform/samsung/exynos4-is/fimc-lite-reg.c
310
writel(cfg, dev->regs + FLITE_REG_CIGCTRL);
drivers/media/platform/samsung/exynos4-is/fimc-lite-reg.c
37
writel(cfg, dev->regs + FLITE_REG_CIGCTRL);
drivers/media/platform/samsung/exynos4-is/fimc-lite-reg.c
44
writel(cfg, dev->regs + FLITE_REG_CISTATUS);
drivers/media/platform/samsung/exynos4-is/fimc-lite-reg.c
58
writel(cfg, dev->regs + FLITE_REG_CISTATUS2);
drivers/media/platform/samsung/exynos4-is/fimc-lite-reg.c
80
writel(cfg, dev->regs + FLITE_REG_CIGCTRL);
drivers/media/platform/samsung/exynos4-is/fimc-lite-reg.c
87
writel(cfg, dev->regs + FLITE_REG_CIIMGCPT);
drivers/media/platform/samsung/exynos4-is/fimc-lite-reg.c
94
writel(cfg, dev->regs + FLITE_REG_CIIMGCPT);
drivers/media/platform/samsung/exynos4-is/fimc-lite-reg.h
150
writel(mask, dev->regs + FLITE_REG_CIFCNTSEQ);
drivers/media/platform/samsung/exynos4-is/fimc-reg.c
100
writel(flip, dev->regs + FIMC_REG_MSCTRL);
drivers/media/platform/samsung/exynos4-is/fimc-reg.c
139
writel(cfg, dev->regs + FIMC_REG_CITRGFMT);
drivers/media/platform/samsung/exynos4-is/fimc-reg.c
144
writel(cfg, dev->regs + FIMC_REG_CITAREA);
drivers/media/platform/samsung/exynos4-is/fimc-reg.c
154
writel(cfg, dev->regs + FIMC_REG_ORGOSIZE);
drivers/media/platform/samsung/exynos4-is/fimc-reg.c
162
writel(cfg, dev->regs + FIMC_REG_CIGCTRL);
drivers/media/platform/samsung/exynos4-is/fimc-reg.c
176
writel(cfg, dev->regs + FIMC_REG_CIOYOFF);
drivers/media/platform/samsung/exynos4-is/fimc-reg.c
179
writel(cfg, dev->regs + FIMC_REG_CIOCBOFF);
drivers/media/platform/samsung/exynos4-is/fimc-reg.c
182
writel(cfg, dev->regs + FIMC_REG_CIOCROFF);
drivers/media/platform/samsung/exynos4-is/fimc-reg.c
208
writel(cfg, dev->regs + FIMC_REG_CIOCTRL);
drivers/media/platform/samsung/exynos4-is/fimc-reg.c
218
writel(cfg, dev->regs + FIMC_REG_ORGISIZE);
drivers/media/platform/samsung/exynos4-is/fimc-reg.c
228
writel(cfg, dev->regs + FIMC_REG_CIOCTRL);
drivers/media/platform/samsung/exynos4-is/fimc-reg.c
241
writel(cfg, dev->regs + FIMC_REG_CISCPRERATIO);
drivers/media/platform/samsung/exynos4-is/fimc-reg.c
244
writel(cfg, dev->regs + FIMC_REG_CISCPREDST);
drivers/media/platform/samsung/exynos4-is/fimc-reg.c
25
writel(cfg, dev->regs + FIMC_REG_CISRCFMT);
drivers/media/platform/samsung/exynos4-is/fimc-reg.c
30
writel(cfg, dev->regs + FIMC_REG_CIGCTRL);
drivers/media/platform/samsung/exynos4-is/fimc-reg.c
308
writel(cfg, dev->regs + FIMC_REG_CISCCTRL);
drivers/media/platform/samsung/exynos4-is/fimc-reg.c
330
writel(cfg, dev->regs + FIMC_REG_CISCCTRL);
drivers/media/platform/samsung/exynos4-is/fimc-reg.c
338
writel(cfg, dev->regs + FIMC_REG_CIEXTEN);
drivers/media/platform/samsung/exynos4-is/fimc-reg.c
342
writel(cfg, dev->regs + FIMC_REG_CISCCTRL);
drivers/media/platform/samsung/exynos4-is/fimc-reg.c
35
writel(cfg, dev->regs + FIMC_REG_CIGCTRL);
drivers/media/platform/samsung/exynos4-is/fimc-reg.c
360
writel(cfg, dev->regs + FIMC_REG_CIIMGCPT);
drivers/media/platform/samsung/exynos4-is/fimc-reg.c
368
writel(cfg, dev->regs + FIMC_REG_CIIMGCPT);
drivers/media/platform/samsung/exynos4-is/fimc-reg.c
385
writel(cfg, dev->regs + FIMC_REG_CIIMGEFF);
drivers/media/platform/samsung/exynos4-is/fimc-reg.c
400
writel(cfg, dev->regs + FIMC_REG_CIOCTRL);
drivers/media/platform/samsung/exynos4-is/fimc-reg.c
416
writel(cfg_o, dev->regs + FIMC_REG_ORGISIZE);
drivers/media/platform/samsung/exynos4-is/fimc-reg.c
417
writel(cfg_r, dev->regs + FIMC_REG_CIREAL_ISIZE);
drivers/media/platform/samsung/exynos4-is/fimc-reg.c
429
writel(cfg, dev->regs + FIMC_REG_CIIYOFF);
drivers/media/platform/samsung/exynos4-is/fimc-reg.c
432
writel(cfg, dev->regs + FIMC_REG_CIICBOFF);
drivers/media/platform/samsung/exynos4-is/fimc-reg.c
435
writel(cfg, dev->regs + FIMC_REG_CIICROFF);
drivers/media/platform/samsung/exynos4-is/fimc-reg.c
487
writel(cfg, dev->regs + FIMC_REG_MSCTRL);
drivers/media/platform/samsung/exynos4-is/fimc-reg.c
499
writel(cfg, dev->regs + FIMC_REG_CIDMAPARAM);
drivers/media/platform/samsung/exynos4-is/fimc-reg.c
515
writel(cfg, dev->regs + FIMC_REG_MSCTRL);
drivers/media/platform/samsung/exynos4-is/fimc-reg.c
526
writel(cfg, dev->regs + FIMC_REG_CISCCTRL);
drivers/media/platform/samsung/exynos4-is/fimc-reg.c
533
writel(cfg, dev->regs + FIMC_REG_CIREAL_ISIZE);
drivers/media/platform/samsung/exynos4-is/fimc-reg.c
535
writel(addr->y, dev->regs + FIMC_REG_CIIYSA(0));
drivers/media/platform/samsung/exynos4-is/fimc-reg.c
536
writel(addr->cb, dev->regs + FIMC_REG_CIICBSA(0));
drivers/media/platform/samsung/exynos4-is/fimc-reg.c
537
writel(addr->cr, dev->regs + FIMC_REG_CIICRSA(0));
drivers/media/platform/samsung/exynos4-is/fimc-reg.c
540
writel(cfg, dev->regs + FIMC_REG_CIREAL_ISIZE);
drivers/media/platform/samsung/exynos4-is/fimc-reg.c
548
writel(addr->y, dev->regs + FIMC_REG_CIOYSA(i));
drivers/media/platform/samsung/exynos4-is/fimc-reg.c
549
writel(addr->cb, dev->regs + FIMC_REG_CIOCBSA(i));
drivers/media/platform/samsung/exynos4-is/fimc-reg.c
550
writel(addr->cr, dev->regs + FIMC_REG_CIOCRSA(i));
drivers/media/platform/samsung/exynos4-is/fimc-reg.c
580
writel(cfg, fimc->regs + FIMC_REG_CIGCTRL);
drivers/media/platform/samsung/exynos4-is/fimc-reg.c
647
writel(cfg, fimc->regs + FIMC_REG_CISRCFMT);
drivers/media/platform/samsung/exynos4-is/fimc-reg.c
661
writel(cfg, fimc->regs + FIMC_REG_CIWDOFST);
drivers/media/platform/samsung/exynos4-is/fimc-reg.c
667
writel(cfg, fimc->regs + FIMC_REG_CIWDOFST2);
drivers/media/platform/samsung/exynos4-is/fimc-reg.c
710
writel(tmp, fimc->regs + FIMC_REG_CSIIMGFMT);
drivers/media/platform/samsung/exynos4-is/fimc-reg.c
733
writel(cfg, fimc->regs + FIMC_REG_CIGCTRL);
drivers/media/platform/samsung/exynos4-is/fimc-reg.c
742
writel(cfg, dev->regs + FIMC_REG_CIGCTRL);
drivers/media/platform/samsung/exynos4-is/fimc-reg.c
752
writel(cfg, dev->regs + FIMC_REG_CISCCTRL);
drivers/media/platform/samsung/exynos4-is/fimc-reg.c
762
writel(cfg, dev->regs + FIMC_REG_MSCTRL);
drivers/media/platform/samsung/exynos4-is/fimc-reg.c
94
writel(cfg, dev->regs + FIMC_REG_CITRGFMT);
drivers/media/platform/samsung/exynos4-is/fimc-reg.h
335
writel(mask, dev->regs + FIMC_REG_CIFCNTSEQ);
drivers/media/platform/samsung/exynos4-is/mipi-csis.c
271
#define s5pcsis_write(__csis, __r, __v) writel(__v, __csis->regs + __r)
drivers/media/platform/samsung/s3c-camif/camif-regs.c
13
#define camif_write(_camif, _off, _val) writel(_val, (_camif)->io_base + (_off))
drivers/media/platform/samsung/s5p-g2d/g2d-hw.c
14
#define w(x, a) writel((x), d->regs + (a))
drivers/media/platform/samsung/s5p-jpeg/jpeg-core.c
622
writel((unsigned int)qtbl[i], regs + tab + (i * 0x04));
drivers/media/platform/samsung/s5p-jpeg/jpeg-core.c
648
writel((unsigned int)htbl[i], regs + tab + (i * 0x04));
drivers/media/platform/samsung/s5p-jpeg/jpeg-core.c
691
writel(dword, regs + tab + i);
drivers/media/platform/samsung/s5p-jpeg/jpeg-core.c
835
writel(word, jpeg->regs +
drivers/media/platform/samsung/s5p-jpeg/jpeg-core.c
849
writel(word, jpeg->regs +
drivers/media/platform/samsung/s5p-jpeg/jpeg-core.c
856
writel(word, jpeg->regs +
drivers/media/platform/samsung/s5p-jpeg/jpeg-core.c
926
writel(word, jpeg->regs +
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-exynos3250.c
117
writel(reg, regs + EXYNOS3250_JPGCMOD);
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-exynos3250.c
129
writel(reg, regs + EXYNOS3250_JPGCMOD);
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-exynos3250.c
143
writel(reg, regs + EXYNOS3250_JPGMOD);
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-exynos3250.c
165
writel(reg, regs + EXYNOS3250_JPGMOD);
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-exynos3250.c
179
writel(reg, regs + EXYNOS3250_JPGDRI);
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-exynos3250.c
190
writel(reg, regs + EXYNOS3250_QHTBL);
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-exynos3250.c
202
writel(reg, regs + EXYNOS3250_QHTBL);
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-exynos3250.c
214
writel(reg, regs + EXYNOS3250_QHTBL);
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-exynos3250.c
222
writel(reg, regs + EXYNOS3250_JPGY);
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-exynos3250.c
23
writel(1, regs + EXYNOS3250_SW_RESET);
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-exynos3250.c
230
writel(reg, regs + EXYNOS3250_JPGX);
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-exynos3250.c
257
writel(reg, regs + EXYNOS3250_JPGINTSE);
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-exynos3250.c
265
writel(reg, regs + EXYNOS3250_ENC_STREAM_BOUND);
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-exynos3250.c
313
writel(reg, regs + EXYNOS3250_OUTFORM);
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-exynos3250.c
318
writel(addr, regs + EXYNOS3250_JPG_JPGADR);
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-exynos3250.c
323
writel(img_addr->y, regs + EXYNOS3250_LUMA_BASE);
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-exynos3250.c
324
writel(img_addr->cb, regs + EXYNOS3250_CHROMA_BASE);
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-exynos3250.c
325
writel(img_addr->cr, regs + EXYNOS3250_CHROMA_CR_BASE);
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-exynos3250.c
35
writel(1, regs + EXYNOS3250_JPGDRI);
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-exynos3250.c
358
writel(reg_luma, regs + EXYNOS3250_LUMA_STRIDE);
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-exynos3250.c
359
writel(reg_cb, regs + EXYNOS3250_CHROMA_STRIDE);
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-exynos3250.c
360
writel(reg_cr, regs + EXYNOS3250_CHROMA_CR_STRIDE);
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-exynos3250.c
373
writel(reg, regs + EXYNOS3250_LUMA_XY_OFFSET);
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-exynos3250.c
380
writel(reg, regs + EXYNOS3250_CHROMA_XY_OFFSET);
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-exynos3250.c
387
writel(reg, regs + EXYNOS3250_CHROMA_CR_XY_OFFSET);
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-exynos3250.c
393
writel(EXYNOS3250_JPEG_ENC_COEF1,
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-exynos3250.c
395
writel(EXYNOS3250_JPEG_ENC_COEF2,
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-exynos3250.c
397
writel(EXYNOS3250_JPEG_ENC_COEF3,
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-exynos3250.c
400
writel(EXYNOS3250_JPEG_DEC_COEF1,
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-exynos3250.c
402
writel(EXYNOS3250_JPEG_DEC_COEF2,
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-exynos3250.c
404
writel(EXYNOS3250_JPEG_DEC_COEF3,
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-exynos3250.c
41
writel(0, regs + EXYNOS3250_JPGDRI);
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-exynos3250.c
411
writel(1, regs + EXYNOS3250_JSTART);
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-exynos3250.c
416
writel(1, regs + EXYNOS3250_JRSTART);
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-exynos3250.c
427
writel(value, regs + EXYNOS3250_JPGINTST);
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-exynos3250.c
438
writel(size & EXYNOS3250_DEC_STREAM_MASK,
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-exynos3250.c
46
writel(EXYNOS3250_POWER_ON, regs + EXYNOS3250_JPGCLKCON);
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-exynos3250.c
461
writel(sratio & EXYNOS3250_DEC_SCALE_FACTOR_MASK,
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-exynos3250.c
469
writel(EXYNOS3250_TIMER_INT_STAT | time_value,
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-exynos3250.c
480
writel(EXYNOS3250_TIMER_INT_STAT, regs + EXYNOS3250_TIMER_ST);
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-exynos3250.c
51
writel(((EXYNOS3250_DMA_MO_COUNT << EXYNOS3250_WDMA_ISSUE_NUM_SHIFT) &
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-exynos3250.c
66
writel(reg | EXYNOS3250_HALF_EN, base + EXYNOS3250_JPGCMOD);
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-exynos4.c
133
writel(reg, base + EXYNOS4_IMG_FMT_REG);
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-exynos4.c
166
writel(reg, base + EXYNOS4_IMG_FMT_REG);
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-exynos4.c
175
writel(reg | EXYNOS4_INT_EN_ALL, base + EXYNOS4_INT_EN_REG);
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-exynos4.c
179
writel(reg | EXYNOS5433_INT_EN_ALL, base + EXYNOS4_INT_EN_REG);
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-exynos4.c
195
writel(reg | EXYNOS4_HUF_TBL_EN,
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-exynos4.c
198
writel(reg & ~EXYNOS4_HUF_TBL_EN,
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-exynos4.c
209
writel(reg | EXYNOS4_SYS_INT_EN, base + EXYNOS4_JPEG_CNTL_REG);
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-exynos4.c
21
writel(reg & ~(EXYNOS4_DEC_MODE | EXYNOS4_ENC_MODE),
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-exynos4.c
211
writel(reg & ~EXYNOS4_SYS_INT_EN, base + EXYNOS4_JPEG_CNTL_REG);
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-exynos4.c
217
writel(address, base + EXYNOS4_OUT_MEM_BASE_REG);
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-exynos4.c
223
writel(0x0, base + EXYNOS4_JPEG_IMG_SIZE_REG); /* clear */
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-exynos4.c
224
writel(EXYNOS4_X_SIZE(x_value) | EXYNOS4_Y_SIZE(y_value),
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-exynos4.c
231
writel(exynos4_jpeg_addr->y, base + EXYNOS4_IMG_BA_PLANE_1_REG);
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-exynos4.c
232
writel(exynos4_jpeg_addr->cb, base + EXYNOS4_IMG_BA_PLANE_2_REG);
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-exynos4.c
233
writel(exynos4_jpeg_addr->cr, base + EXYNOS4_IMG_BA_PLANE_3_REG);
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-exynos4.c
247
writel(reg, base + EXYNOS4_TBL_SEL_REG);
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-exynos4.c
25
writel(reg & ~EXYNOS4_SOFT_RESET_HI, base + EXYNOS4_JPEG_CNTL_REG);
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-exynos4.c
257
writel(reg, base + EXYNOS4_TBL_SEL_REG);
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-exynos4.c
267
writel(reg, base + EXYNOS4_TBL_SEL_REG);
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-exynos4.c
277
writel(reg, base + EXYNOS4_TBL_SEL_REG);
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-exynos4.c
283
writel(0xd2, base + EXYNOS4_HUFF_CNT_REG);
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-exynos4.c
285
writel(0x1a2, base + EXYNOS4_HUFF_CNT_REG);
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-exynos4.c
29
writel(reg | EXYNOS4_SOFT_RESET_HI, base + EXYNOS4_JPEG_CNTL_REG);
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-exynos4.c
295
writel(size, base + EXYNOS4_BITSTREAM_SIZE_REG);
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-exynos4.c
39
writel((reg & EXYNOS4_ENC_DEC_MODE_MASK) |
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-exynos4.c
43
writel((reg & EXYNOS4_ENC_DEC_MODE_MASK) |
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-exynos4.c
47
writel(reg & EXYNOS4_ENC_DEC_MODE_MASK,
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-s5p.c
107
writel(reg, regs + S5P_JPG_QTBL);
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-s5p.c
118
writel(reg, regs + S5P_JPG_HTBL);
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-s5p.c
129
writel(reg, regs + S5P_JPG_HTBL);
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-s5p.c
139
writel(reg, regs + S5P_JPGY_U);
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-s5p.c
144
writel(reg, regs + S5P_JPGY_L);
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-s5p.c
154
writel(reg, regs + S5P_JPGX_U);
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-s5p.c
159
writel(reg, regs + S5P_JPGX_L);
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-s5p.c
170
writel(reg, regs + S5P_JPGINTSE);
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-s5p.c
181
writel(reg, regs + S5P_JPGINTSE);
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-s5p.c
192
writel(reg, regs + S5P_JPGINTSE);
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-s5p.c
207
writel(reg, regs + S5P_JPG_TIMER_SE);
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-s5p.c
21
writel(1, regs + S5P_JPG_SW_RESET);
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-s5p.c
218
writel(reg, regs + S5P_JPG_ENC_STREAM_INTSE);
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-s5p.c
233
writel(reg, regs + S5P_JPG_ENC_STREAM_INTSE);
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-s5p.c
248
writel(reg, regs + S5P_JPG_OUTFORM);
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-s5p.c
253
writel(addr, regs + S5P_JPG_JPGADR);
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-s5p.c
258
writel(addr, regs + S5P_JPG_IMGADR);
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-s5p.c
269
writel(reg, regs + S5P_JPG_COEF(i));
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-s5p.c
274
writel(1, regs + S5P_JSTART);
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-s5p.c
292
writel(S5P_INT_RELEASE, regs + S5P_JPGCOM);
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-s5p.c
32
writel(S5P_POWER_ON, regs + S5P_JPGCLKCON);
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-s5p.c
48
writel(reg, regs + S5P_JPGCMOD);
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-s5p.c
62
writel(reg, regs + S5P_JPGMOD);
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-s5p.c
77
writel(reg, regs + S5P_JPGMOD);
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-s5p.c
92
writel(reg, regs + S5P_JPGDRI_U);
drivers/media/platform/samsung/s5p-jpeg/jpeg-hw-s5p.c
97
writel(reg, regs + S5P_JPGDRI_L);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_common.h
103
#define mfc_write(dev, data, offset) writel((data), dev->regs_base + \
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1002
writel(0, mfc_regs->e_rc_mode);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1005
writel(2, mfc_regs->e_rc_mode);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1009
writel(1, mfc_regs->e_rc_mode);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1012
writel(2, mfc_regs->e_rc_mode);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1024
writel(reg, mfc_regs->e_enc_options);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1029
writel(reg, mfc_regs->e_rc_config);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1033
writel(reg, mfc_regs->e_mv_hor_range);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1036
writel(reg, mfc_regs->e_mv_ver_range);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1038
writel(0x0, mfc_regs->e_frame_insertion);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1039
writel(0x0, mfc_regs->e_roi_buffer_addr);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1040
writel(0x0, mfc_regs->e_param_change);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1041
writel(0x0, mfc_regs->e_rc_roi_ctrl);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1042
writel(0x0, mfc_regs->e_picture_tag);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1044
writel(0x0, mfc_regs->e_bit_count_enable);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1045
writel(0x0, mfc_regs->e_max_bit_count);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1046
writel(0x0, mfc_regs->e_min_bit_count);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1048
writel(0x0, mfc_regs->e_metadata_buffer_addr);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1049
writel(0x0, mfc_regs->e_metadata_buffer_size);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1073
writel(reg, mfc_regs->e_gop_config);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1093
writel(reg, mfc_regs->e_picture_profile);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1100
writel(reg, mfc_regs->e_rc_config);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1105
writel(reg, mfc_regs->e_rc_config);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1113
writel(reg, mfc_regs->e_rc_qp_bound);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1116
writel(0x0, mfc_regs->e_fixed_picture_qp);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1122
writel(reg, mfc_regs->e_fixed_picture_qp);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1130
writel(reg, mfc_regs->e_rc_frame_rate);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1136
writel(p_h264->cpb_size & 0xFFFF,
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1140
writel(p->vbv_delay, mfc_regs->e_vbv_init_delay);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1146
writel(reg, mfc_regs->e_h264_options);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1150
writel(ctx->img_height >> 1,
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1153
writel(ctx->img_height >> 1,
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1161
writel(reg, mfc_regs->e_h264_options);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1171
writel(reg, mfc_regs->e_h264_lf_alpha_offset);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1181
writel(reg, mfc_regs->e_h264_lf_beta_offset);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1187
writel(reg, mfc_regs->e_h264_options);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1193
writel(reg, mfc_regs->e_h264_options);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1199
writel(reg, mfc_regs->e_h264_options);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1202
writel(0x0, mfc_regs->e_mb_rc_config);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1213
writel(reg, mfc_regs->e_mb_rc_config);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1220
writel(reg, mfc_regs->e_h264_options);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1222
writel(0x0, mfc_regs->e_aspect_ratio);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1223
writel(0x0, mfc_regs->e_extended_sar);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1228
writel(reg, mfc_regs->e_aspect_ratio);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1234
writel(reg, mfc_regs->e_extended_sar);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1243
writel(reg, mfc_regs->e_h264_options);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1246
writel(0x0, mfc_regs->e_h264_i_period);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1250
writel(reg, mfc_regs->e_h264_i_period);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1256
writel(reg, mfc_regs->e_h264_options);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1261
writel(reg, mfc_regs->e_h264_options);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1267
writel(reg, mfc_regs->e_h264_options);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1273
writel(reg, mfc_regs->e_h264_options);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1278
writel(reg, mfc_regs->e_h264_num_t_layer);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1282
writel(p_h264->hier_qp_layer_qp[i],
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1288
writel(reg, mfc_regs->e_h264_num_t_layer);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1294
writel(reg, mfc_regs->e_h264_options);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1301
writel(reg, mfc_regs->e_h264_frame_packing_sei_info);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1310
writel(p_h264->fmo_run_len[i] - 1,
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1322
writel(p_h264->fmo_chg_dir & 0x1,
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1325
writel(p_h264->fmo_chg_rate,
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1336
writel(p_h264->fmo_map_type,
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1338
writel(p_h264->fmo_slice_grp - 1,
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1341
writel(0, mfc_regs->e_h264_fmo_num_slice_grp_minus1);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1365
writel(reg, mfc_regs->e_gop_config);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1373
writel(reg, mfc_regs->e_picture_profile);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1380
writel(reg, mfc_regs->e_rc_config);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1385
writel(reg, mfc_regs->e_rc_config);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1393
writel(reg, mfc_regs->e_rc_qp_bound);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1396
writel(0x0, mfc_regs->e_fixed_picture_qp);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1402
writel(reg, mfc_regs->e_fixed_picture_qp);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1410
writel(reg, mfc_regs->e_rc_frame_rate);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1416
writel(p->vbv_size & 0xFFFF, mfc_regs->e_vbv_buffer_size);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1419
writel(p->vbv_delay, mfc_regs->e_vbv_init_delay);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1423
writel(0x0, mfc_regs->e_mpeg4_options);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1424
writel(0x0, mfc_regs->e_mpeg4_hec_period);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1447
writel(reg, mfc_regs->e_picture_profile);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1454
writel(reg, mfc_regs->e_rc_config);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1459
writel(reg, mfc_regs->e_rc_config);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1467
writel(reg, mfc_regs->e_rc_qp_bound);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1470
writel(0x0, mfc_regs->e_fixed_picture_qp);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1476
writel(reg, mfc_regs->e_fixed_picture_qp);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1484
writel(reg, mfc_regs->e_rc_frame_rate);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1490
writel(p->vbv_size & 0xFFFF, mfc_regs->e_vbv_buffer_size);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1493
writel(p->vbv_delay, mfc_regs->e_vbv_init_delay);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1518
writel(reg, mfc_regs->e_gop_config);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1522
writel(reg, mfc_regs->e_picture_profile);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1529
writel(reg, mfc_regs->e_rc_config);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1536
writel(reg, mfc_regs->e_rc_frame_rate);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1542
writel(reg, mfc_regs->e_rc_config);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1545
writel(0x0, mfc_regs->e_fixed_picture_qp);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1550
writel(reg, mfc_regs->e_fixed_picture_qp);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1557
writel(reg, mfc_regs->e_rc_qp_bound);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1562
writel(p->vbv_size & 0xFFFF, mfc_regs->e_vbv_buffer_size);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1565
writel(p->vbv_delay, mfc_regs->e_vbv_init_delay);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1587
writel(reg, mfc_regs->e_vp8_options);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1612
writel(reg, mfc_regs->e_gop_config);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1630
writel(reg, mfc_regs->e_picture_profile);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1667
writel(reg, mfc_regs->e_hevc_options);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1672
writel(reg, mfc_regs->e_hevc_refresh_period);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1678
writel(reg, mfc_regs->e_hevc_lf_beta_offset_div2);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1681
writel(reg, mfc_regs->e_hevc_lf_tc_offset_div2);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1688
writel(reg, mfc_regs->e_num_t_layer);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1692
writel(p_hevc->hier_qp_layer[i],
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1697
writel(p_hevc->hier_bit_layer[i],
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1708
writel(reg, mfc_regs->e_rc_config);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1712
writel(reg, mfc_regs->e_rc_config);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1721
writel(reg, mfc_regs->e_rc_frame_rate);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1732
writel(reg, mfc_regs->e_rc_qp_bound);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1734
writel(0x0, mfc_regs->e_fixed_picture_qp);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1743
writel(reg, mfc_regs->e_fixed_picture_qp);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1771
writel(ctx->display_delay, mfc_regs->d_display_delay);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1775
writel(reg, mfc_regs->d_dec_options);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1790
writel(reg, mfc_regs->d_init_buffer_options);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1792
writel(reg, mfc_regs->d_dec_options);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1796
writel(0x3, mfc_regs->pixel_format);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1798
writel(0x2, mfc_regs->pixel_format);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1800
writel(0x1, mfc_regs->pixel_format);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1802
writel(0x0, mfc_regs->pixel_format);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1806
writel(ctx->sei_fp_parse & 0x1, mfc_regs->d_sei_enable);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1808
writel(ctx->inst_no, mfc_regs->instance_id);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1823
writel(ctx->inst_no, mfc_regs->instance_id);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1836
writel(ctx->dec_dst_flag, mfc_regs->d_available_dpb_flag_lower);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1837
writel(ctx->slice_interface & 0x1, mfc_regs->d_slice_if_enable);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1839
writel(ctx->inst_no, mfc_regs->instance_id);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1883
writel(ctx->stride[0], mfc_regs->e_source_first_plane_stride);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1884
writel(ctx->stride[1], mfc_regs->e_source_second_plane_stride);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1887
writel(ctx->stride[2], mfc_regs->e_source_third_plane_stride);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1890
writel(ctx->inst_no, mfc_regs->instance_id);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1907
writel(p_h264->aso_slice_order[i],
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
1935
writel(ctx->inst_no, mfc_regs->instance_id);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
2261
writel(0, mfc_regs->risc2host_command);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
2262
writel(0, mfc_regs->risc2host_int);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
597
writel(strm_size, mfc_regs->d_stream_data_size);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
598
writel(buf_addr, mfc_regs->d_cpb_buffer_addr);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
599
writel(buf_size->cpb, mfc_regs->d_cpb_buffer_size);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
600
writel(start_num_byte, mfc_regs->d_cpb_buffer_offset);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
624
writel(ctx->total_dpb_count, mfc_regs->d_num_dpb);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
625
writel(ctx->luma_size, mfc_regs->d_first_plane_dpb_size);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
626
writel(ctx->chroma_size, mfc_regs->d_second_plane_dpb_size);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
629
writel(ctx->chroma_size_1, mfc_regs->d_third_plane_dpb_size);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
630
writel(buf_addr1, mfc_regs->d_scratch_buffer_addr);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
631
writel(ctx->scratch_buf_size, mfc_regs->d_scratch_buffer_size);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
634
writel(ctx->stride[0], mfc_regs->d_first_plane_dpb_stride_size);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
635
writel(ctx->stride[1], mfc_regs->d_second_plane_dpb_stride_size);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
638
writel(ctx->stride[2], mfc_regs->d_third_plane_dpb_stride_size);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
647
writel(ctx->mv_size, mfc_regs->d_mv_buffer_size);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
648
writel(ctx->mv_count, mfc_regs->d_num_mv);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
661
writel(ctx->dst_bufs[i].cookie.raw.luma,
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
665
writel(ctx->dst_bufs[i].cookie.raw.chroma,
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
671
writel(ctx->dst_bufs[i].cookie.raw.chroma_1, mfc_regs->d_third_plane_dpb +
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
687
writel(buf_addr1, mfc_regs->d_mv_buffer + i * 4);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
693
writel(buf_addr1, mfc_regs->d_static_buffer_addr);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
694
writel(DEC_VP9_STATIC_BUFFER_SIZE,
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
707
writel(ctx->inst_no, mfc_regs->instance_id);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
722
writel(addr, mfc_regs->e_stream_buffer_addr); /* 16B align */
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
723
writel(size, mfc_regs->e_stream_buffer_size);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
738
writel(y_addr, mfc_regs->e_source_first_plane_addr);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
739
writel(c_addr, mfc_regs->e_source_second_plane_addr);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
740
writel(c_1_addr, mfc_regs->e_source_third_plane_addr);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
788
writel(buf_addr1, mfc_regs->e_luma_dpb + (4 * i));
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
793
writel(buf_addr1, mfc_regs->e_chroma_dpb + (4 * i));
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
798
writel(buf_addr1, mfc_regs->e_me_buffer + (4 * i));
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
804
writel(buf_addr1, mfc_regs->e_luma_dpb + (4 * i));
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
806
writel(buf_addr1, mfc_regs->e_chroma_dpb + (4 * i));
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
808
writel(buf_addr1, mfc_regs->e_me_buffer + (4 * i));
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
815
writel(buf_addr1, mfc_regs->e_scratch_buffer_addr);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
816
writel(ctx->scratch_buf_size, mfc_regs->e_scratch_buffer_size);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
820
writel(buf_addr1, mfc_regs->e_tmv_buffer0);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
822
writel(buf_addr1, mfc_regs->e_tmv_buffer1);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
833
writel(ctx->inst_no, mfc_regs->instance_id);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
849
writel(ctx->slice_mode, mfc_regs->e_mslice_mode);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
851
writel(ctx->slice_size.mb, mfc_regs->e_mslice_size_mb);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
854
writel(ctx->slice_size.bits, mfc_regs->e_mslice_size_bits);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
856
writel(0x0, mfc_regs->e_mslice_size_mb);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
857
writel(0x0, mfc_regs->e_mslice_size_bits);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
873
writel(ctx->img_width, mfc_regs->e_frame_width); /* 16 align */
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
875
writel(ctx->img_height, mfc_regs->e_frame_height); /* 16 align */
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
878
writel(ctx->img_width, mfc_regs->e_cropped_frame_width);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
880
writel(ctx->img_height, mfc_regs->e_cropped_frame_height);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
882
writel(0x0, mfc_regs->e_frame_crop_offset);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
887
writel(reg, mfc_regs->e_gop_config);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
895
writel(reg, mfc_regs->e_enc_options);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
899
writel(reg, mfc_regs->e_enc_options);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
903
writel(reg, mfc_regs->e_enc_options);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
909
writel(p->intra_refresh_mb, mfc_regs->e_ir_size);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
915
writel(reg, mfc_regs->e_enc_options);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
920
writel(reg, mfc_regs->e_enc_options);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
927
writel(reg, mfc_regs->e_enc_options);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
929
writel(0x0, mfc_regs->pixel_format);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
934
writel(reg, mfc_regs->e_enc_options);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
936
writel(0x1, mfc_regs->pixel_format);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
941
writel(reg, mfc_regs->e_enc_options);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
943
writel(0x0, mfc_regs->pixel_format);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
948
writel(reg, mfc_regs->e_enc_options);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
950
writel(0x2, mfc_regs->pixel_format);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
955
writel(reg, mfc_regs->e_enc_options);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
957
writel(0x3, mfc_regs->pixel_format);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
964
writel(reg, mfc_regs->e_enc_options);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
967
writel(0x0, mfc_regs->e_padding_ctrl);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
978
writel(reg, mfc_regs->e_padding_ctrl);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
985
writel(reg, mfc_regs->e_rc_config);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
989
writel(p->rc_bitrate,
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
992
writel(1, mfc_regs->e_rc_bit_rate);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
999
writel(1, mfc_regs->e_rc_mode);
drivers/media/platform/st/sti/bdisp/bdisp-hw.c
1104
writel(BLT_AQ1_CTL_CFG, bdisp->regs + BLT_AQ1_CTL);
drivers/media/platform/st/sti/bdisp/bdisp-hw.c
1105
writel(BLT_ITS_AQ1_LNA, bdisp->regs + BLT_ITM0);
drivers/media/platform/st/sti/bdisp/bdisp-hw.c
1108
writel(ctx->node_paddr[0], bdisp->regs + BLT_AQ1_IP);
drivers/media/platform/st/sti/bdisp/bdisp-hw.c
1115
writel(ctx->node_paddr[node_id], bdisp->regs + BLT_AQ1_LNA);
drivers/media/platform/st/sti/bdisp/bdisp-hw.c
374
writel(0, bdisp->regs + BLT_ITM0);
drivers/media/platform/st/sti/bdisp/bdisp-hw.c
377
writel(readl(bdisp->regs + BLT_CTL) | BLT_CTL_RESET,
drivers/media/platform/st/sti/bdisp/bdisp-hw.c
379
writel(0, bdisp->regs + BLT_CTL);
drivers/media/platform/st/sti/bdisp/bdisp-hw.c
411
writel(its, bdisp->regs + BLT_ITS);
drivers/media/platform/st/sti/bdisp/bdisp-hw.c
416
writel(its, bdisp->regs + BLT_ITS);
drivers/media/platform/st/sti/bdisp/bdisp-hw.c
417
writel(0, bdisp->regs + BLT_ITM0);
drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.c
317
writel(1, csi->regs + CSI_EN_REG);
drivers/media/platform/sunxi/sun4i-csi/sun4i_dma.c
103
writel(addr, csi->regs + CSI_BUF_ADDR_REG(plane, slot));
drivers/media/platform/sunxi/sun4i-csi/sun4i_dma.c
138
writel(buf_addr, csi->regs + CSI_BUF_ADDR_REG(plane, slot));
drivers/media/platform/sunxi/sun4i-csi/sun4i_dma.c
276
writel(CSI_WIN_CTRL_W_ACTIVE(csi->fmt.width * 2),
drivers/media/platform/sunxi/sun4i-csi/sun4i_dma.c
278
writel(CSI_WIN_CTRL_H_ACTIVE(csi->fmt.height),
drivers/media/platform/sunxi/sun4i-csi/sun4i_dma.c
292
writel(CSI_CFG_INPUT_FMT(csi_fmt->input) |
drivers/media/platform/sunxi/sun4i-csi/sun4i_dma.c
300
writel(csi->fmt.plane_fmt[0].bytesperline,
drivers/media/platform/sunxi/sun4i-csi/sun4i_dma.c
311
writel(CSI_BUF_CTRL_DBE, csi->regs + CSI_BUF_CTRL_REG);
drivers/media/platform/sunxi/sun4i-csi/sun4i_dma.c
314
writel(CSI_INT_FRM_DONE, csi->regs + CSI_INT_STA_REG);
drivers/media/platform/sunxi/sun4i-csi/sun4i_dma.c
317
writel(CSI_INT_FRM_DONE, csi->regs + CSI_INT_EN_REG);
drivers/media/platform/sunxi/sun4i-csi/sun4i_dma.c
38
writel(CSI_CPT_CTRL_VIDEO_START, csi->regs + CSI_CPT_CTRL_REG);
drivers/media/platform/sunxi/sun4i-csi/sun4i_dma.c
384
writel(reg, csi->regs + CSI_INT_STA_REG);
drivers/media/platform/sunxi/sun4i-csi/sun4i_dma.c
43
writel(0, csi->regs + CSI_CPT_CTRL_REG);
drivers/media/platform/sunxi/sun8i-di/sun8i-di.c
41
writel(value, dev->base + reg);
drivers/media/platform/sunxi/sun8i-di/sun8i-di.c
47
writel(readl(dev->base + reg) | bits, dev->base + reg);
drivers/media/platform/sunxi/sun8i-di/sun8i-di.c
58
writel(val, dev->base + reg);
drivers/media/platform/sunxi/sun8i-rotate/sun8i_rotate.c
33
writel(value, dev->base + reg);
drivers/media/platform/sunxi/sun8i-rotate/sun8i_rotate.c
38
writel(readl(dev->base + reg) | bits, dev->base + reg);
drivers/media/platform/synopsys/dw-mipi-csi2rx.c
192
writel(val, csi2->base_addr + addr);
drivers/media/platform/synopsys/hdmirx/snps_hdmirx.c
183
writel(val, hdmirx_dev->regs + reg);
drivers/media/platform/synopsys/hdmirx/snps_hdmirx.c
209
writel(val, hdmirx_dev->regs + reg);
drivers/media/platform/ti/davinci/vpif.h
25
#define regw(value, reg) writel(value, (reg + vpif_base))
drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c
521
writel(reg, csi->shim + SHIM_CNTL);
drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c
566
writel(reg, csi->shim + SHIM_DMACNTX);
drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c
570
writel(reg, csi->shim + SHIM_PSI_CFG0);
drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c
884
writel(0, csi->shim + SHIM_CNTL);
drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c
885
writel(0, csi->shim + SHIM_DMACNTX);
drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c
898
writel(0, csi->shim + SHIM_CNTL);
drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c
899
writel(0, csi->shim + SHIM_DMACNTX);
drivers/media/platform/verisilicon/hantro.h
403
writel(val, vpu->enc_base + reg);
drivers/media/platform/verisilicon/hantro.h
424
writel(val, vpu->dec_base + reg);
drivers/media/platform/verisilicon/imx8m_vpu_hw.c
35
writel(val, vpu->ctrl_base + CTRL_SOFT_RESET);
drivers/media/platform/verisilicon/imx8m_vpu_hw.c
42
writel(val, vpu->ctrl_base + CTRL_SOFT_RESET);
drivers/media/platform/verisilicon/imx8m_vpu_hw.c
51
writel(val, vpu->ctrl_base + CTRL_CLOCK_ENABLE);
drivers/media/platform/verisilicon/imx8m_vpu_hw.c
68
writel(0xffffffff, vpu->ctrl_base + CTRL_G1_DEC_FUSE);
drivers/media/platform/verisilicon/imx8m_vpu_hw.c
69
writel(0xffffffff, vpu->ctrl_base + CTRL_G1_PP_FUSE);
drivers/media/platform/verisilicon/imx8m_vpu_hw.c
70
writel(0xffffffff, vpu->ctrl_base + CTRL_G2_DEC_FUSE);
drivers/media/rc/meson-ir-tx.c
101
writel(~IRB_ENABLE & (IRB_MOD_CLK(clk_nr) | IRB_INIT_HIGH),
drivers/media/rc/meson-ir-tx.c
104
writel(readl(ir->reg_base + IRB_ADDR0) & ~IRB_INIT_HIGH,
drivers/media/rc/meson-ir-tx.c
106
writel(IRB_FIFO_IRQ_ENABLE | MIRTX_FIFO_THD,
drivers/media/rc/meson-ir-tx.c
108
writel(readl(ir->reg_base + IRB_ADDR0) | IRB_ENABLE,
drivers/media/rc/meson-ir-tx.c
151
writel(ir->buf[ir->buf_head], ir->reg_base + IRB_ADDR2);
drivers/media/rc/meson-ir-tx.c
199
writel(readl(ir->reg_base + IRB_ADDR3) & ~IRB_FIFO_THD_PENDING,
drivers/media/rc/meson-ir-tx.c
89
writel(IRB_MOD_COUNT(pulse_cnt, space_cnt),
drivers/media/rc/st_rc.c
117
writel(IRB_RX_OVERRUN_INT,
drivers/media/rc/st_rc.c
154
writel(IRB_RX_INTS, dev->rx_base + IRB_RX_INT_CLEAR);
drivers/media/rc/st_rc.c
180
writel(1, dev->rx_base + IRB_RX_POLARITY_INV);
drivers/media/rc/st_rc.c
183
writel(rx_sampling_freq_div, dev->base + IRB_SAMPLE_RATE_COMM);
drivers/media/rc/st_rc.c
193
writel(rx_max_symbol_per, dev->rx_base + IRB_MAX_SYM_PERIOD);
drivers/media/rc/st_rc.c
214
writel(IRB_RX_INTS, dev->rx_base + IRB_RX_INT_EN);
drivers/media/rc/st_rc.c
215
writel(0x01, dev->rx_base + IRB_RX_EN);
drivers/media/rc/st_rc.c
225
writel(0x00, dev->rx_base + IRB_RX_EN);
drivers/media/rc/st_rc.c
226
writel(0x00, dev->rx_base + IRB_RX_INT_EN);
drivers/media/rc/st_rc.c
358
writel(0x00, rc_dev->rx_base + IRB_RX_EN);
drivers/media/rc/st_rc.c
359
writel(0x00, rc_dev->rx_base + IRB_RX_INT_EN);
drivers/media/rc/st_rc.c
383
writel(IRB_RX_INTS, rc_dev->rx_base + IRB_RX_INT_EN);
drivers/media/rc/st_rc.c
384
writel(0x01, rc_dev->rx_base + IRB_RX_EN);
drivers/media/rc/sunxi-cir.c
112
writel(status | REG_RXSTA_CLEARALL, ir->base + SUNXI_IR_RXSTA_REG);
drivers/media/rc/sunxi-cir.c
166
writel(REG_CIR_NTHR(SUNXI_IR_RXNOISE) | REG_CIR_ITHR(ithr),
drivers/media/rc/sunxi-cir.c
197
writel(REG_CTL_MD, ir->base + SUNXI_IR_CTL_REG);
drivers/media/rc/sunxi-cir.c
203
writel(REG_RXCTL_RPPI, ir->base + SUNXI_IR_RXCTL_REG);
drivers/media/rc/sunxi-cir.c
206
writel(REG_RXSTA_CLEARALL, ir->base + SUNXI_IR_RXSTA_REG);
drivers/media/rc/sunxi-cir.c
212
writel(REG_RXINT_ROI_EN | REG_RXINT_RPEI_EN |
drivers/media/rc/sunxi-cir.c
218
writel(tmp | REG_CTL_GEN | REG_CTL_RXEN, ir->base + SUNXI_IR_CTL_REG);
drivers/memory/da8xx-ddrctl.c
144
writel(reg, ddrctl + knob->reg);
drivers/memory/emif.c
221
writel(temp, base + EMIF_POWER_MANAGEMENT_CONTROL);
drivers/memory/emif.c
461
writel(DDR_MR4, base + EMIF_LPDDR2_MODE_REG_CONFIG);
drivers/memory/emif.c
467
writel(DDR_MR4 | CS_MASK, base + EMIF_LPDDR2_MODE_REG_CONFIG);
drivers/memory/emif.c
518
writel(tim1, base + EMIF_SDRAM_TIMING_1_SHDW);
drivers/memory/emif.c
519
writel(tim3, base + EMIF_SDRAM_TIMING_3_SHDW);
drivers/memory/emif.c
520
writel(ref_ctrl, base + EMIF_SDRAM_REFRESH_CTRL_SHDW);
drivers/memory/emif.c
589
writel(interrupts, base + EMIF_SYSTEM_OCP_INTERRUPT_STATUS);
drivers/memory/emif.c
605
writel(interrupts, base + EMIF_LL_OCP_INTERRUPT_STATUS);
drivers/memory/emif.c
651
writel(readl(base + EMIF_SYSTEM_OCP_INTERRUPT_STATUS),
drivers/memory/emif.c
654
writel(readl(base + EMIF_LL_OCP_INTERRUPT_STATUS),
drivers/memory/emif.c
663
writel(readl(base + EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_SET),
drivers/memory/emif.c
666
writel(readl(base + EMIF_LL_OCP_INTERRUPT_ENABLE_SET),
drivers/memory/emif.c
686
writel(interrupts, base + EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_SET);
drivers/memory/emif.c
692
writel(interrupts, base + EMIF_LL_OCP_INTERRUPT_ENABLE_SET);
drivers/memory/emif.c
722
writel(pwr_mgmt_ctrl, base + EMIF_POWER_MANAGEMENT_CONTROL);
drivers/memory/emif.c
727
writel(zq, base + EMIF_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG);
drivers/memory/emif.c
738
writel(temp_alert_cfg, base + EMIF_TEMPERATURE_ALERT_CONFIG);
drivers/memory/emif.c
746
writel(EMIF_EXT_PHY_CTRL_1_VAL, base + EMIF_EXT_PHY_CTRL_1_SHDW);
drivers/memory/emif.c
747
writel(EMIF_EXT_PHY_CTRL_5_VAL, base + EMIF_EXT_PHY_CTRL_5_SHDW);
drivers/memory/emif.c
748
writel(EMIF_EXT_PHY_CTRL_6_VAL, base + EMIF_EXT_PHY_CTRL_6_SHDW);
drivers/memory/emif.c
749
writel(EMIF_EXT_PHY_CTRL_7_VAL, base + EMIF_EXT_PHY_CTRL_7_SHDW);
drivers/memory/emif.c
750
writel(EMIF_EXT_PHY_CTRL_8_VAL, base + EMIF_EXT_PHY_CTRL_8_SHDW);
drivers/memory/emif.c
751
writel(EMIF_EXT_PHY_CTRL_9_VAL, base + EMIF_EXT_PHY_CTRL_9_SHDW);
drivers/memory/emif.c
752
writel(EMIF_EXT_PHY_CTRL_10_VAL, base + EMIF_EXT_PHY_CTRL_10_SHDW);
drivers/memory/emif.c
753
writel(EMIF_EXT_PHY_CTRL_11_VAL, base + EMIF_EXT_PHY_CTRL_11_SHDW);
drivers/memory/emif.c
754
writel(EMIF_EXT_PHY_CTRL_12_VAL, base + EMIF_EXT_PHY_CTRL_12_SHDW);
drivers/memory/emif.c
755
writel(EMIF_EXT_PHY_CTRL_13_VAL, base + EMIF_EXT_PHY_CTRL_13_SHDW);
drivers/memory/emif.c
756
writel(EMIF_EXT_PHY_CTRL_14_VAL, base + EMIF_EXT_PHY_CTRL_14_SHDW);
drivers/memory/emif.c
757
writel(EMIF_EXT_PHY_CTRL_15_VAL, base + EMIF_EXT_PHY_CTRL_15_SHDW);
drivers/memory/emif.c
758
writel(EMIF_EXT_PHY_CTRL_16_VAL, base + EMIF_EXT_PHY_CTRL_16_SHDW);
drivers/memory/emif.c
759
writel(EMIF_EXT_PHY_CTRL_17_VAL, base + EMIF_EXT_PHY_CTRL_17_SHDW);
drivers/memory/emif.c
760
writel(EMIF_EXT_PHY_CTRL_18_VAL, base + EMIF_EXT_PHY_CTRL_18_SHDW);
drivers/memory/emif.c
761
writel(EMIF_EXT_PHY_CTRL_19_VAL, base + EMIF_EXT_PHY_CTRL_19_SHDW);
drivers/memory/emif.c
762
writel(EMIF_EXT_PHY_CTRL_20_VAL, base + EMIF_EXT_PHY_CTRL_20_SHDW);
drivers/memory/emif.c
763
writel(EMIF_EXT_PHY_CTRL_21_VAL, base + EMIF_EXT_PHY_CTRL_21_SHDW);
drivers/memory/emif.c
764
writel(EMIF_EXT_PHY_CTRL_22_VAL, base + EMIF_EXT_PHY_CTRL_22_SHDW);
drivers/memory/emif.c
765
writel(EMIF_EXT_PHY_CTRL_23_VAL, base + EMIF_EXT_PHY_CTRL_23_SHDW);
drivers/memory/emif.c
766
writel(EMIF_EXT_PHY_CTRL_24_VAL, base + EMIF_EXT_PHY_CTRL_24_SHDW);
drivers/memory/jz4780-nemc.c
112
writel(nfcsr, nemc->base + NEMC_NFCSR);
drivers/memory/jz4780-nemc.c
137
writel(nfcsr, nemc->base + NEMC_NFCSR);
drivers/memory/jz4780-nemc.c
266
writel(smcr, nemc->base + NEMC_SMCRn(bank));
drivers/memory/jz4780-nemc.c
313
writel(0, nemc->base + NEMC_NFCSR);
drivers/memory/mtk-smi.c
216
writel(reg_val,
drivers/memory/mtk-smi.c
227
writel(*larb->mmu, larb->base + MT8167_SMI_LARB_MMU_EN);
drivers/memory/mtk-smi.c
235
writel(*larb->mmu, larb->base + MT8173_SMI_LARB_MMU_EN);
drivers/memory/mtk-smi.c
281
writel(reg, larb->base + SMI_LARB_NONSEC_CON(i));
drivers/memory/mtk-smi.c
945
writel(bus_sel, common->base + SMI_BUS_SEL);
drivers/memory/mvebu-devbus.c
225
writel(value, devbus->base);
drivers/memory/mvebu-devbus.c
248
writel(value, devbus->base + ARMADA_READ_PARAM_OFFSET);
drivers/memory/mvebu-devbus.c
260
writel(value, devbus->base + ARMADA_WRITE_PARAM_OFFSET);
drivers/memory/pl172.c
125
writel(cfg, pl172->base + MPMC_STATIC_CFG(cs));
drivers/memory/pl172.c
73
writel(cycles, pl172->base + reg_offset);
drivers/memory/renesas-rpc-if.c
148
writel(val, rpc->base + reg);
drivers/memory/renesas-rpc-if.c
165
writel(val, rpc->base + reg);
drivers/memory/renesas-rpc-if.c
192
writel(val, xspi->base + reg);
drivers/memory/samsung/exynos-srom.c
170
writel(rd->value, base + rd->offset);
drivers/memory/samsung/exynos5422-dmc.c
388
writel(EXYNOS5_AREF_NORMAL,
drivers/memory/samsung/exynos5422-dmc.c
391
writel(dmc->bypass_timing_row,
drivers/memory/samsung/exynos5422-dmc.c
393
writel(dmc->bypass_timing_row,
drivers/memory/samsung/exynos5422-dmc.c
395
writel(dmc->bypass_timing_data,
drivers/memory/samsung/exynos5422-dmc.c
397
writel(dmc->bypass_timing_data,
drivers/memory/samsung/exynos5422-dmc.c
399
writel(dmc->bypass_timing_power,
drivers/memory/samsung/exynos5422-dmc.c
401
writel(dmc->bypass_timing_power,
drivers/memory/samsung/exynos5422-dmc.c
428
writel(EXYNOS5_AREF_NORMAL,
drivers/memory/samsung/exynos5422-dmc.c
431
writel(dmc->timing_row[idx],
drivers/memory/samsung/exynos5422-dmc.c
433
writel(dmc->timing_row[idx],
drivers/memory/samsung/exynos5422-dmc.c
435
writel(dmc->timing_data[idx],
drivers/memory/samsung/exynos5422-dmc.c
437
writel(dmc->timing_data[idx],
drivers/memory/samsung/exynos5422-dmc.c
439
writel(dmc->timing_power[idx],
drivers/memory/samsung/exynos5422-dmc.c
441
writel(dmc->timing_power[idx],
drivers/memory/samsung/exynos5422-dmc.c
768
writel(PERF_CNT2, dmc->base_drexi0 + DREX_INTENS_PPC);
drivers/memory/samsung/exynos5422-dmc.c
769
writel(PERF_CNT2, dmc->base_drexi1 + DREX_INTENS_PPC);
drivers/memory/samsung/exynos5422-dmc.c
772
writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi0 + DREX_CNTENS_PPC);
drivers/memory/samsung/exynos5422-dmc.c
773
writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi1 + DREX_CNTENS_PPC);
drivers/memory/samsung/exynos5422-dmc.c
776
writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi0 + DREX_FLAG_PPC);
drivers/memory/samsung/exynos5422-dmc.c
777
writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi1 + DREX_FLAG_PPC);
drivers/memory/samsung/exynos5422-dmc.c
780
writel(CC_RESET | PPC_COUNTER_RESET, dmc->base_drexi0 + DREX_PMNC_PPC);
drivers/memory/samsung/exynos5422-dmc.c
781
writel(CC_RESET | PPC_COUNTER_RESET, dmc->base_drexi1 + DREX_PMNC_PPC);
drivers/memory/samsung/exynos5422-dmc.c
787
writel(beg_value, dmc->base_drexi0 + DREX_PMCNT2_PPC);
drivers/memory/samsung/exynos5422-dmc.c
788
writel(beg_value, dmc->base_drexi1 + DREX_PMCNT2_PPC);
drivers/memory/samsung/exynos5422-dmc.c
791
writel(PPC_ENABLE, dmc->base_drexi0 + DREX_PMNC_PPC);
drivers/memory/samsung/exynos5422-dmc.c
792
writel(PPC_ENABLE, dmc->base_drexi1 + DREX_PMNC_PPC);
drivers/memory/samsung/exynos5422-dmc.c
850
writel(0, dmc->base_drexi0 + DREX_PMNC_PPC);
drivers/memory/samsung/exynos5422-dmc.c
851
writel(0, dmc->base_drexi1 + DREX_PMNC_PPC);
drivers/memory/samsung/exynos5422-dmc.c
882
writel(PEREV_CLK_EN, dmc->base_drexi0 + DREX_PPCCLKCON);
drivers/memory/samsung/exynos5422-dmc.c
883
writel(PEREV_CLK_EN, dmc->base_drexi1 + DREX_PPCCLKCON);
drivers/memory/samsung/exynos5422-dmc.c
886
writel(READ_TRANSFER_CH0, dmc->base_drexi0 + DREX_PEREV2CONFIG);
drivers/memory/samsung/exynos5422-dmc.c
887
writel(READ_TRANSFER_CH1, dmc->base_drexi1 + DREX_PEREV2CONFIG);
drivers/memory/samsung/exynos5422-dmc.c
907
writel(0, dmc->base_drexi0 + DREX_PMNC_PPC);
drivers/memory/samsung/exynos5422-dmc.c
908
writel(0, dmc->base_drexi1 + DREX_PMNC_PPC);
drivers/memory/samsung/exynos5422-dmc.c
911
writel(PERF_CNT2, dmc->base_drexi0 + DREX_INTENC_PPC);
drivers/memory/samsung/exynos5422-dmc.c
912
writel(PERF_CNT2, dmc->base_drexi1 + DREX_INTENC_PPC);
drivers/memory/samsung/exynos5422-dmc.c
915
writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi0 + DREX_CNTENC_PPC);
drivers/memory/samsung/exynos5422-dmc.c
916
writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi1 + DREX_CNTENC_PPC);
drivers/memory/samsung/exynos5422-dmc.c
919
writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi0 + DREX_FLAG_PPC);
drivers/memory/samsung/exynos5422-dmc.c
920
writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi1 + DREX_FLAG_PPC);
drivers/memory/tegra/tegra124-emc.c
521
writel(value, emc->regs + EMC_CCFIFO_DATA);
drivers/memory/tegra/tegra124-emc.c
522
writel(offset, emc->regs + EMC_CCFIFO_ADDR);
drivers/memory/tegra/tegra124-emc.c
530
writel(1, emc->regs + EMC_TIMING_CONTROL);
drivers/memory/tegra/tegra124-emc.c
547
writel(0, emc->regs + EMC_AUTO_CAL_INTERVAL);
drivers/memory/tegra/tegra124-emc.c
617
writel(EMC_INTSTATUS_CLKCHANGE_COMPLETE, emc->regs + EMC_INTSTATUS);
drivers/memory/tegra/tegra124-emc.c
623
writel(val, emc->regs + EMC_CFG);
drivers/memory/tegra/tegra124-emc.c
637
writel(val, emc->regs + EMC_SEL_DPD_CTRL);
drivers/memory/tegra/tegra124-emc.c
656
writel(val2, emc->regs + EMC_BGBIAS_CTL0);
drivers/memory/tegra/tegra124-emc.c
676
writel(val, emc->regs + EMC_XM2DQSPADCTRL2);
drivers/memory/tegra/tegra124-emc.c
690
writel(timing->emc_ctt_term_ctrl,
drivers/memory/tegra/tegra124-emc.c
697
writel(timing->emc_burst_data[i],
drivers/memory/tegra/tegra124-emc.c
700
writel(timing->emc_xm2dqspadctrl2, emc->regs + EMC_XM2DQSPADCTRL2);
drivers/memory/tegra/tegra124-emc.c
701
writel(timing->emc_zcal_interval, emc->regs + EMC_ZCAL_INTERVAL);
drivers/memory/tegra/tegra124-emc.c
743
writel(val, emc->regs + EMC_MRS_WAIT_CNT);
drivers/memory/tegra/tegra124-emc.c
838
writel(timing->emc_auto_cal_interval,
drivers/memory/tegra/tegra124-emc.c
843
writel(timing->emc_cfg, emc->regs + EMC_CFG);
drivers/memory/tegra/tegra124-emc.c
846
writel(timing->emc_zcal_cnt_long, emc->regs + EMC_ZCAL_WAIT_CNT);
drivers/memory/tegra/tegra124-emc.c
855
writel(val, emc->regs + EMC_BGBIAS_CTL0);
drivers/memory/tegra/tegra124-emc.c
860
writel(timing->emc_bgbias_ctl0,
drivers/memory/tegra/tegra124-emc.c
864
writel(timing->emc_auto_cal_interval,
drivers/memory/tegra/tegra124-emc.c
872
writel(timing->emc_sel_dpd_ctrl, emc->regs + EMC_SEL_DPD_CTRL);
drivers/memory/tegra/tegra186.c
113
writel(value, mc->regs + client->regs.sid.security);
drivers/memory/tegra/tegra186.c
122
writel(sid, mc->regs + client->regs.sid.override);
drivers/memory/ti-aemif.c
188
writel(val, aemif->base + offset);
drivers/memory/ti-aemif.c
253
writel(val, aemif->base + offset);
drivers/memory/ti-emif-pm.c
185
writel(EMIF_POWER_MGMT_WAIT_SELF_REFRESH_8192_CYCLES,
drivers/memory/ti-emif-pm.c
189
writel(EMIF_POWER_MGMT_WAIT_SELF_REFRESH_8192_CYCLES,
drivers/memstick/host/jmb38x_ms.c
234
writel(host->io_word[0], host->addr + DATA);
drivers/memstick/host/jmb38x_ms.c
355
writel(host->io_word[0], host->addr + TPC_P0);
drivers/memstick/host/jmb38x_ms.c
356
writel(host->io_word[1], host->addr + TPC_P1);
drivers/memstick/host/jmb38x_ms.c
358
writel(host->io_word[0], host->addr + DATA);
drivers/memstick/host/jmb38x_ms.c
425
writel(sg_dma_address(&host->req->sg),
drivers/memstick/host/jmb38x_ms.c
427
writel(((1 << 16) & BLOCK_COUNT_MASK)
drivers/memstick/host/jmb38x_ms.c
430
writel(DMA_CONTROL_ENABLE, host->addr + DMA_CONTROL);
drivers/memstick/host/jmb38x_ms.c
432
writel(((1 << 16) & BLOCK_COUNT_MASK)
drivers/memstick/host/jmb38x_ms.c
440
writel(t_val, host->addr + INT_STATUS_ENABLE);
drivers/memstick/host/jmb38x_ms.c
441
writel(t_val, host->addr + INT_SIGNAL_ENABLE);
drivers/memstick/host/jmb38x_ms.c
449
writel(host->io_word[0], host->addr + TPC_P0);
drivers/memstick/host/jmb38x_ms.c
450
writel(host->io_word[1], host->addr + TPC_P1);
drivers/memstick/host/jmb38x_ms.c
455
writel(HOST_CONTROL_LED | readl(host->addr + HOST_CONTROL),
drivers/memstick/host/jmb38x_ms.c
459
writel(cmd, host->addr + TPC);
drivers/memstick/host/jmb38x_ms.c
481
writel(0, host->addr + BLOCK);
drivers/memstick/host/jmb38x_ms.c
482
writel(0, host->addr + DMA_CONTROL);
drivers/memstick/host/jmb38x_ms.c
495
writel(t_val, host->addr + INT_STATUS_ENABLE);
drivers/memstick/host/jmb38x_ms.c
496
writel(t_val, host->addr + INT_SIGNAL_ENABLE);
drivers/memstick/host/jmb38x_ms.c
499
writel((~HOST_CONTROL_LED) & readl(host->addr + HOST_CONTROL),
drivers/memstick/host/jmb38x_ms.c
578
writel(irq_status, host->addr + INT_STATUS);
drivers/memstick/host/jmb38x_ms.c
638
writel(HOST_CONTROL_RESET_REQ | HOST_CONTROL_CLOCK_EN
drivers/memstick/host/jmb38x_ms.c
652
writel(HOST_CONTROL_RESET | HOST_CONTROL_CLOCK_EN
drivers/memstick/host/jmb38x_ms.c
667
writel(INT_STATUS_ALL, host->addr + INT_SIGNAL_ENABLE);
drivers/memstick/host/jmb38x_ms.c
668
writel(INT_STATUS_ALL, host->addr + INT_STATUS_ENABLE);
drivers/memstick/host/jmb38x_ms.c
691
writel(host_ctl, host->addr + HOST_CONTROL);
drivers/memstick/host/jmb38x_ms.c
693
writel(host->id ? PAD_PU_PD_ON_MS_SOCK1
drivers/memstick/host/jmb38x_ms.c
697
writel(PAD_OUTPUT_ENABLE_MS,
drivers/memstick/host/jmb38x_ms.c
705
writel(host_ctl, host->addr + HOST_CONTROL);
drivers/memstick/host/jmb38x_ms.c
706
writel(0, host->addr + PAD_OUTPUT_ENABLE);
drivers/memstick/host/jmb38x_ms.c
707
writel(PAD_PU_PD_OFF, host->addr + PAD_PU_PD);
drivers/memstick/host/jmb38x_ms.c
742
writel(host_ctl, host->addr + HOST_CONTROL);
drivers/memstick/host/jmb38x_ms.c
743
writel(CLOCK_CONTROL_OFF, host->addr + CLOCK_CONTROL);
drivers/memstick/host/jmb38x_ms.c
744
writel(clock_ctl, host->addr + CLOCK_CONTROL);
drivers/memstick/host/jmb38x_ms.c
983
writel(0, host->addr + INT_SIGNAL_ENABLE);
drivers/memstick/host/jmb38x_ms.c
984
writel(0, host->addr + INT_STATUS_ENABLE);
drivers/memstick/host/r592.c
100
writel(reg & ~mask, dev->mmio + address);
drivers/memstick/host/r592.c
65
writel(value, dev->mmio + address);
drivers/memstick/host/r592.c
90
writel(reg | mask , dev->mmio + address);
drivers/memstick/host/tifm_ms.c
138
writel(TIFM_MS_SYS_FDIR | readl(sock->addr + SOCK_MS_SYSTEM),
drivers/memstick/host/tifm_ms.c
140
writel(host->io_word, sock->addr + SOCK_MS_DATA);
drivers/memstick/host/tifm_ms.c
153
writel(TIFM_MS_SYS_FDIR | readl(sock->addr + SOCK_MS_SYSTEM),
drivers/memstick/host/tifm_ms.c
235
writel(TIFM_MS_SYS_FDIR
drivers/memstick/host/tifm_ms.c
238
writel(host->io_word, sock->addr + SOCK_MS_DATA);
drivers/memstick/host/tifm_ms.c
240
writel(TIFM_MS_SYS_FDIR
drivers/memstick/host/tifm_ms.c
243
writel(0, sock->addr + SOCK_MS_DATA);
drivers/memstick/host/tifm_ms.c
273
writel(TIFM_FIFO_INT_SETALL,
drivers/memstick/host/tifm_ms.c
275
writel(TIFM_FIFO_ENABLE,
drivers/memstick/host/tifm_ms.c
288
writel(ilog2(data_len) - 2,
drivers/memstick/host/tifm_ms.c
290
writel(TIFM_FIFO_INTMASK,
drivers/memstick/host/tifm_ms.c
296
writel(TIFM_FIFO_INTMASK,
drivers/memstick/host/tifm_ms.c
299
writel(sg_dma_address(&host->req->sg),
drivers/memstick/host/tifm_ms.c
301
writel(sys_param, sock->addr + SOCK_DMA_CONTROL);
drivers/memstick/host/tifm_ms.c
303
writel(host->mode_mask | TIFM_MS_SYS_FIFO,
drivers/memstick/host/tifm_ms.c
306
writel(TIFM_FIFO_MORE,
drivers/memstick/host/tifm_ms.c
311
writel(TIFM_CTRL_LED | readl(sock->addr + SOCK_CONTROL),
drivers/memstick/host/tifm_ms.c
323
writel(sys_param, sock->addr + SOCK_MS_SYSTEM);
drivers/memstick/host/tifm_ms.c
327
writel(cmd, sock->addr + SOCK_MS_COMMAND);
drivers/memstick/host/tifm_ms.c
345
writel(TIFM_FIFO_INT_SETALL,
drivers/memstick/host/tifm_ms.c
347
writel(TIFM_DMA_RESET, sock->addr + SOCK_DMA_CONTROL);
drivers/memstick/host/tifm_ms.c
356
writel((~TIFM_CTRL_LED) & readl(sock->addr + SOCK_CONTROL),
drivers/memstick/host/tifm_ms.c
407
writel(fifo_status, sock->addr + SOCK_DMA_FIFO_STATUS);
drivers/memstick/host/tifm_ms.c
444
writel(TIFM_MS_SYS_INTCLR | readl(sock->addr + SOCK_MS_SYSTEM),
drivers/memstick/host/tifm_ms.c
505
writel(TIFM_MS_SYS_RESET, sock->addr + SOCK_MS_SYSTEM);
drivers/memstick/host/tifm_ms.c
506
writel(TIFM_MS_SYS_FCLR | TIFM_MS_SYS_INTCLR,
drivers/memstick/host/tifm_ms.c
508
writel(0xffffffff, sock->addr + SOCK_MS_STATUS);
drivers/memstick/host/tifm_ms.c
510
writel(TIFM_MS_SYS_FCLR | TIFM_MS_SYS_INTCLR,
drivers/memstick/host/tifm_ms.c
512
writel(0xffffffff, sock->addr + SOCK_MS_STATUS);
drivers/memstick/host/tifm_ms.c
519
writel((~TIFM_CTRL_FAST_CLK)
drivers/memstick/host/tifm_ms.c
524
writel(TIFM_CTRL_FAST_CLK
drivers/memstick/host/tifm_ms.c
603
writel(TIFM_FIFO_INT_SETALL,
drivers/memstick/host/tifm_ms.c
605
writel(TIFM_DMA_RESET, sock->addr + SOCK_DMA_CONTROL);
drivers/message/fusion/mptbase.c
221
#define CHIPREG_WRITE32(addr,val) writel(val, addr)
drivers/mfd/atmel-flexcom.c
75
writel(FLEX_MR_OPMODE(ddata->opmode), ddata->base + FLEX_MR);
drivers/mfd/atmel-flexcom.c
99
writel(val, ddata->base + FLEX_MR);
drivers/mfd/atmel-hlcdc.c
56
writel(val, hregmap->regs + reg);
drivers/mfd/db8500-prcmu.c
1021
writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
drivers/mfd/db8500-prcmu.c
1052
writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
drivers/mfd/db8500-prcmu.c
1108
writel(MBOX_BIT(2), PRCM_MBOX_CPU_SET);
drivers/mfd/db8500-prcmu.c
1166
writel(sleep_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_SLEEP));
drivers/mfd/db8500-prcmu.c
1167
writel(idle_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_IDLE));
drivers/mfd/db8500-prcmu.c
1201
writel(MBOX_BIT(3), PRCM_MBOX_CPU_SET);
drivers/mfd/db8500-prcmu.c
1240
writel(val, PRCM_TCR);
drivers/mfd/db8500-prcmu.c
1263
writel(val, prcmu_base + clk_mgt[clock].offset);
drivers/mfd/db8500-prcmu.c
1266
writel(0, PRCM_SEM);
drivers/mfd/db8500-prcmu.c
1280
writel(val | PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS);
drivers/mfd/db8500-prcmu.c
1287
writel(val & ~PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS);
drivers/mfd/db8500-prcmu.c
1307
writel((PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP |
drivers/mfd/db8500-prcmu.c
1316
writel(val, PRCM_PLLDSI_ENABLE);
drivers/mfd/db8500-prcmu.c
1327
writel(PRCM_APE_RESETN_DSIPLL_RESETN,
drivers/mfd/db8500-prcmu.c
1330
writel((PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP |
drivers/mfd/db8500-prcmu.c
1334
writel(val, PRCM_PLLDSI_ENABLE);
drivers/mfd/db8500-prcmu.c
1338
writel(PRCM_APE_RESETN_DSIPLL_RESETN, PRCM_APE_RESETN_CLR);
drivers/mfd/db8500-prcmu.c
1351
writel(val, PRCM_DSI_PLLOUT_SEL);
drivers/mfd/db8500-prcmu.c
1361
writel(val, PRCM_DSITVCLK_DIV);
drivers/mfd/db8500-prcmu.c
1788
writel(val, prcmu_base + clk_mgt[clock].offset);
drivers/mfd/db8500-prcmu.c
1791
writel(0, PRCM_SEM);
drivers/mfd/db8500-prcmu.c
1868
writel(pll_freq, PRCM_PLLDSI_FREQ);
drivers/mfd/db8500-prcmu.c
1888
writel(val, PRCM_DSI_PLLOUT_SEL);
drivers/mfd/db8500-prcmu.c
1900
writel(val, PRCM_DSITVCLK_DIV);
drivers/mfd/db8500-prcmu.c
1936
writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
drivers/mfd/db8500-prcmu.c
1954
writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
drivers/mfd/db8500-prcmu.c
1975
writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
drivers/mfd/db8500-prcmu.c
1994
writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
drivers/mfd/db8500-prcmu.c
2032
writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
drivers/mfd/db8500-prcmu.c
2114
writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);
drivers/mfd/db8500-prcmu.c
2164
writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);
drivers/mfd/db8500-prcmu.c
2219
writel(val, PRCM_HOSTACCESS_REQ);
drivers/mfd/db8500-prcmu.c
2224
writel(val, PRCM_HOSTACCESS_REQ);
drivers/mfd/db8500-prcmu.c
2251
writel((val & ~PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ),
drivers/mfd/db8500-prcmu.c
2282
writel(1, PRCM_APE_SOFTRST);
drivers/mfd/db8500-prcmu.c
2307
writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
drivers/mfd/db8500-prcmu.c
2328
writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);
drivers/mfd/db8500-prcmu.c
2373
writel(MBOX_BIT(0), PRCM_ARM_IT1_CLR);
drivers/mfd/db8500-prcmu.c
2386
writel(MBOX_BIT(1), PRCM_ARM_IT1_CLR);
drivers/mfd/db8500-prcmu.c
2394
writel(MBOX_BIT(2), PRCM_ARM_IT1_CLR);
drivers/mfd/db8500-prcmu.c
2401
writel(MBOX_BIT(3), PRCM_ARM_IT1_CLR);
drivers/mfd/db8500-prcmu.c
2428
writel(MBOX_BIT(4), PRCM_ARM_IT1_CLR);
drivers/mfd/db8500-prcmu.c
2440
writel(MBOX_BIT(5), PRCM_ARM_IT1_CLR);
drivers/mfd/db8500-prcmu.c
2447
writel(MBOX_BIT(6), PRCM_ARM_IT1_CLR);
drivers/mfd/db8500-prcmu.c
2453
writel(MBOX_BIT(7), PRCM_ARM_IT1_CLR);
drivers/mfd/db8500-prcmu.c
2704
writel(val, (PRCM_A9PL_FORCE_CLKEN));
drivers/mfd/db8500-prcmu.c
3029
writel(ALL_MBOX_BITS, PRCM_ARM_IT1_CLR);
drivers/mfd/db8500-prcmu.c
554
writel(value, (prcmu_base + reg));
drivers/mfd/db8500-prcmu.c
566
writel(val, (prcmu_base + reg));
drivers/mfd/db8500-prcmu.c
684
writel((bits | (val & ~mask)), PRCM_CLKOCR);
drivers/mfd/db8500-prcmu.c
710
writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);
drivers/mfd/db8500-prcmu.c
746
writel(dbb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_8500));
drivers/mfd/db8500-prcmu.c
747
writel(abb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_4500));
drivers/mfd/db8500-prcmu.c
749
writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);
drivers/mfd/db8500-prcmu.c
821
writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
drivers/mfd/db8500-prcmu.c
889
writel(val, prcmu_base + clock_reg[i]);
drivers/mfd/db8500-prcmu.c
894
writel(0, PRCM_SEM);
drivers/mfd/db8500-prcmu.c
929
writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
drivers/mfd/db8500-prcmu.c
991
writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
drivers/mfd/intel-lpss.c
197
writel(ltr, lpss->priv + LPSS_PRIV_ACTIVELTR);
drivers/mfd/intel-lpss.c
198
writel(ltr, lpss->priv + LPSS_PRIV_IDLELTR);
drivers/mfd/intel-lpss.c
264
writel(value, lpss->priv + LPSS_PRIV_RESETS);
drivers/mfd/intel-lpss.c
272
writel(0, lpss->priv + LPSS_PRIV_RESETS);
drivers/mfd/intel-lpss.c
283
writel(value, lpss->priv + LPSS_PRIV_SSP_REG);
drivers/mfd/intel-lpss.c
514
writel(0, lpss->priv + LPSS_PRIV_RESETS);
drivers/mfd/intel-lpss.c
528
writel(lpss->priv_ctx[i], lpss->priv + i * 4);
drivers/mfd/intel-m10-bmc-pmci.c
104
writel(val, ctx->base + INDIRECT_WR_OFF);
drivers/mfd/intel-m10-bmc-pmci.c
105
writel(reg, ctx->base + INDIRECT_ADDR_OFF);
drivers/mfd/intel-m10-bmc-pmci.c
106
writel(INDIRECT_CMD_WR, ctx->base + INDIRECT_CMD_OFF);
drivers/mfd/intel-m10-bmc-pmci.c
124
writel(*buf++, base);
drivers/mfd/intel-m10-bmc-pmci.c
197
writel(addr + offset, pmci->base + M10BMC_N6000_FLASH_ADDR);
drivers/mfd/intel-m10-bmc-pmci.c
198
writel(FIELD_PREP(M10BMC_N6000_FLASH_READ_COUNT, read_count) |
drivers/mfd/intel-m10-bmc-pmci.c
219
writel(0, pmci->base + M10BMC_N6000_FLASH_CTRL);
drivers/mfd/intel-m10-bmc-pmci.c
229
writel(0, pmci->base + M10BMC_N6000_FLASH_CTRL);
drivers/mfd/intel-m10-bmc-pmci.c
51
writel(INDIRECT_CMD_CLR, ctx->base + INDIRECT_CMD_OFF);
drivers/mfd/intel-m10-bmc-pmci.c
72
writel(reg, ctx->base + INDIRECT_ADDR_OFF);
drivers/mfd/intel-m10-bmc-pmci.c
73
writel(INDIRECT_CMD_RD, ctx->base + INDIRECT_CMD_OFF);
drivers/mfd/intel_pmc_bxt.c
118
writel(new_val, pmc->gcr_mem_base + offset);
drivers/mfd/ioc3.c
188
writel(GPCR_UARTA_MODESEL | GPCR_UARTB_MODESEL,
drivers/mfd/ioc3.c
191
writel(0, &ipd->regs->gppr[6]);
drivers/mfd/ioc3.c
193
writel(0, &ipd->regs->gppr[7]);
drivers/mfd/ioc3.c
196
writel(readl(&ipd->regs->port_a.sscr) & ~SSCR_DMA_EN,
drivers/mfd/ioc3.c
198
writel(readl(&ipd->regs->port_b.sscr) & ~SSCR_DMA_EN,
drivers/mfd/ioc3.c
276
writel(GPCR_MLAN_EN, &ipd->regs->gpcr_s);
drivers/mfd/ioc3.c
52
writel(BIT(hwirq), &ipd->regs->sio_ir);
drivers/mfd/ioc3.c
546
writel(~0, &ipd->regs->sio_iec);
drivers/mfd/ioc3.c
547
writel(~0, &ipd->regs->sio_ir);
drivers/mfd/ioc3.c
548
writel(0, &ipd->regs->eth.eier);
drivers/mfd/ioc3.c
549
writel(~0, &ipd->regs->eth.eisr);
drivers/mfd/ioc3.c
60
writel(BIT(hwirq), &ipd->regs->sio_iec);
drivers/mfd/ioc3.c
640
writel(~0, &ipd->regs->sio_iec);
drivers/mfd/ioc3.c
641
writel(~0, &ipd->regs->sio_ir);
drivers/mfd/ioc3.c
68
writel(BIT(hwirq), &ipd->regs->sio_ies);
drivers/mfd/ipaq-micro.c
285
writel(tx->buf[tx->index], micro->base + UTDR);
drivers/mfd/ipaq-micro.c
292
writel(val, micro->base + UTCR3);
drivers/mfd/ipaq-micro.c
307
writel(0x01, micro->sdlc + 0x0); /* Select UART mode */
drivers/mfd/ipaq-micro.c
310
writel(0x0, micro->base + UTCR3);
drivers/mfd/ipaq-micro.c
313
writel(UTCR0_8BitData | UTCR0_1StpBit, micro->base + UTCR0);
drivers/mfd/ipaq-micro.c
316
writel(0x0, micro->base + UTCR1);
drivers/mfd/ipaq-micro.c
317
writel(0x1, micro->base + UTCR2);
drivers/mfd/ipaq-micro.c
320
writel(0xff, micro->base + UTSR0);
drivers/mfd/ipaq-micro.c
323
writel(UTCR3_TXE | UTCR3_RXE | UTCR3_RIE, micro->base + UTCR3);
drivers/mfd/ipaq-micro.c
326
writel(val, micro->base + UTCR3);
drivers/mfd/ipaq-micro.c
340
writel(UTSR0_RID, micro->base + UTSR0);
drivers/mfd/ipaq-micro.c
346
writel(status & (UTSR0_RBB | UTSR0_REB),
drivers/mfd/ipaq-micro.c
58
writel(val, micro->base + UTCR3);
drivers/mfd/loongson-se.c
147
writel(SE_INT_CONTROLLER, se->base + SE_S2LINT_CL);
drivers/mfd/loongson-se.c
155
writel(BIT(id), se->base + SE_S2LINT_CL);
drivers/mfd/loongson-se.c
214
writel(SE_INT_ALL, se->base + SE_S2LINT_EN);
drivers/mfd/loongson-se.c
48
writel(int_bit, se->base + SE_L2SINT_SET);
drivers/mfd/loongson-se.c
67
writel(send_cmd[i], se->base + SE_SEND_CMD_REG + i * 4);
drivers/mfd/lpc_ich.c
1273
writel(val, base + BYT_BCR);
drivers/mfd/ls2k-bmc-core.c
200
writel(val | LS2K_BMC_PCIE_LTSSM_ENABLE, base + LS7A_PCIE_PORT_CTL0);
drivers/mfd/ls2k-bmc-core.c
389
writel(val | BIT(LS2K_BMC_RESET_GPIO), gpio_base + LOONGSON_GPIO_OEN);
drivers/mfd/ls2k-bmc-core.c
393
writel(val & ~BIT(LS2K_BMC_RESET_GPIO), gpio_base + LOONGSON_GPIO_FUNC);
drivers/mfd/ls2k-bmc-core.c
397
writel(val & ~BIT(LS2K_BMC_RESET_GPIO), gpio_base + LOONGSON_GPIO_INTPOL);
drivers/mfd/ls2k-bmc-core.c
401
writel(val | BIT(LS2K_BMC_RESET_GPIO), gpio_base + LOONGSON_GPIO_INTEN);
drivers/mfd/mcp-sa11x0.c
128
writel(-1, MCSR(m));
drivers/mfd/mcp-sa11x0.c
263
writel(m->mccr0 & ~MCCR0_MCE, MCCR0(m));
drivers/mfd/qcom_rpm.c
504
writel(0, RPM_CTRL_REG(rpm, rpm->data->ack_ctx_off));
drivers/mfd/qcom_rpm.c
624
writel(fw_version[0], RPM_CTRL_REG(rpm, 0));
drivers/mfd/qcom_rpm.c
625
writel(fw_version[1], RPM_CTRL_REG(rpm, 1));
drivers/mfd/qcom_rpm.c
626
writel(fw_version[2], RPM_CTRL_REG(rpm, 2));
drivers/mfd/rz-mtu3.c
156
writel(val, priv->mmio + ch_offs);
drivers/mfd/ssbi.c
81
writel(val, ssbi->base + reg);
drivers/misc/bcm-vk/bcm_vk.h
459
writel(value, vk->bar[bar] + offset);
drivers/misc/bcm-vk/bcm_vk_msg.c
662
writel(wr_idx, &msgq->wr_idx);
drivers/misc/bcm-vk/bcm_vk_msg.c
860
writel(rd_idx, &msgq->rd_idx);
drivers/misc/cardreader/alcor_pci.c
68
writel(val, priv->iobase + addr);
drivers/misc/dw-xdata-pcie.c
106
writel(0x0, &(__dw_regs(dw)->status));
drivers/misc/dw-xdata-pcie.c
109
writel(BURST_REPEAT | BURST_VALUE, &(__dw_regs(dw)->burst_cnt));
drivers/misc/dw-xdata-pcie.c
112
writel(PATTERN_VALUE, &(__dw_regs(dw)->pattern));
drivers/misc/dw-xdata-pcie.c
122
writel(control, &(__dw_regs(dw)->control));
drivers/misc/dw-xdata-pcie.c
171
writel(0x0, &(__dw_regs(dw)->perf_control));
drivers/misc/dw-xdata-pcie.c
174
writel((u32)XPERF_CONTROL_ENABLE, &(__dw_regs(dw)->perf_control));
drivers/misc/dw-xdata-pcie.c
183
writel(0x0, &(__dw_regs(dw)->perf_control));
drivers/misc/dw-xdata-pcie.c
186
writel((u32)XPERF_CONTROL_ENABLE, &(__dw_regs(dw)->perf_control));
drivers/misc/dw-xdata-pcie.c
354
writel(0x0, &(__dw_regs(dw)->RAM_addr));
drivers/misc/dw-xdata-pcie.c
355
writel(0x0, &(__dw_regs(dw)->RAM_port));
drivers/misc/dw-xdata-pcie.c
358
writel(lower_32_bits(addr), &(__dw_regs(dw)->addr_lsb));
drivers/misc/dw-xdata-pcie.c
359
writel(upper_32_bits(addr), &(__dw_regs(dw)->addr_msb));
drivers/misc/dw-xdata-pcie.c
89
writel(burst, &(__dw_regs(dw)->burst_cnt));
drivers/misc/ibmasm/ibmasmfs.c
533
writel(value, address);
drivers/misc/ibmasm/lowlevel.h
100
writel(mfa, base_address + OUTBOUND_QUEUE_PORT);
drivers/misc/ibmasm/lowlevel.h
115
writel(mfa, base_address + INBOUND_QUEUE_PORT);
drivers/misc/ibmasm/lowlevel.h
54
writel( readl(ctrl_reg) & ~mask, ctrl_reg);
drivers/misc/ibmasm/lowlevel.h
60
writel( readl(ctrl_reg) | mask, ctrl_reg);
drivers/misc/ibmasm/remote.h
84
#define clear_mouse_interrupt(sp) writel(0, mouse_addr(sp) + CONDOR_MOUSE_ISR_STATUS)
drivers/misc/ibmasm/remote.h
85
#define enable_mouse_interrupts(sp) writel(1, mouse_addr(sp) + CONDOR_MOUSE_ISR_CONTROL)
drivers/misc/ibmasm/remote.h
86
#define disable_mouse_interrupts(sp) writel(0, mouse_addr(sp) + CONDOR_MOUSE_ISR_CONTROL)
drivers/misc/ibmasm/remote.h
93
#define set_queue_reader(sp, reader) writel(reader, mouse_addr(sp) + CONDOR_MOUSE_Q_READER)
drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_gpio.c
132
writel(data, priv->reg_base + OUT_OFFSET(nr));
drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_gpio.c
192
writel(BIT(gpio % 32), priv->reg_base + INTR_STAT_OFFSET(gpio));
drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_gpio.c
319
writel(BIT(bit), priv->reg_base + INTR_STATUS_OFFSET(gpiobank));
drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_gpio.c
363
writel(~wake_mask, priv->reg_base +
drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_gpio.c
402
writel(wake_mask, priv->reg_base +
drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_gpio.c
406
writel(0xffffffff, priv->reg_base +
drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_gpio.c
497
writel(0x0264, (priv->reg_base + 0x400 + 0xF0));
drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_gpio.c
94
writel(data, base_addr + reg_offset);
drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_otpe2p.c
103
writel(EEPROM_CMD_EPC_TIMEOUT_BIT,
drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_otpe2p.c
105
writel(EEPROM_CMD_EPC_BUSY_BIT,
drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_otpe2p.c
141
writel(EEPROM_CMD_EPC_BUSY_BIT | (off + byte), rb +
drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_otpe2p.c
182
writel(*(value + byte), rb + MMAP_EEPROM_OFFSET(EEPROM_DATA_REG));
drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_otpe2p.c
185
writel(regval, rb + MMAP_EEPROM_OFFSET(EEPROM_CMD_REG));
drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_otpe2p.c
186
writel(EEPROM_CMD_EPC_BUSY_BIT | regval,
drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_otpe2p.c
239
writel(data | OTP_FUNC_RD_BIT,
drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_otpe2p.c
242
writel(data | OTP_CMD_GO_BIT,
drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_otpe2p.c
293
writel(data | OTP_PGM_MODE_BYTE_BIT,
drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_otpe2p.c
295
writel(*(value + byte), rb + MMAP_OTP_OFFSET(OTP_PRGM_DATA_OFFSET));
drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_otpe2p.c
297
writel(data | OTP_FUNC_PGM_BIT,
drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_otpe2p.c
300
writel(data | OTP_CMD_GO_BIT,
drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_otpe2p.c
359
writel(data & ~OTP_PWR_DN_BIT,
drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_otpe2p.c
412
writel(CFG_SYS_LOCK_PF3, sys_lock);
drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_otpe2p.c
415
writel(OTP_PWR_DN_BIT,
drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_otpe2p.c
418
writel(0, sys_lock);
drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_otpe2p.c
82
writel(CFG_SYS_LOCK_PF3, sys_lock);
drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_otpe2p.c
94
writel(0, sys_lock);
drivers/misc/ocxl/mmio.c
132
writel(tmp, (char *)afu->global_mmio_ptr + offset);
drivers/misc/ocxl/mmio.c
194
writel(tmp, (char *)afu->global_mmio_ptr + offset);
drivers/misc/ocxl/mmio.c
74
writel(val, (char *)afu->global_mmio_ptr + offset);
drivers/misc/pci_endpoint_test.c
1093
writel(data, test->bar[bar] + addr);
drivers/misc/pci_endpoint_test.c
158
writel(value, test->base + offset);
drivers/misc/tifm_7xx1.c
105
writel((s_state & TIFM_CTRL_POWER_MASK) | 0x0c00,
drivers/misc/tifm_7xx1.c
117
writel(readl(sock_addr + SOCK_CONTROL) & (~TIFM_CTRL_LED),
drivers/misc/tifm_7xx1.c
125
writel((~TIFM_CTRL_POWER_MASK) & readl(sock_addr + SOCK_CONTROL),
drivers/misc/tifm_7xx1.c
171
writel(0x0e00, sock_addr + SOCK_CONTROL);
drivers/misc/tifm_7xx1.c
198
writel(TIFM_IRQ_FIFOMASK(socket_change_set)
drivers/misc/tifm_7xx1.c
202
writel(TIFM_IRQ_FIFOMASK(socket_change_set)
drivers/misc/tifm_7xx1.c
206
writel(TIFM_IRQ_ENABLE, fm->addr + FM_SET_INTERRUPT_ENABLE);
drivers/misc/tifm_7xx1.c
259
writel(TIFM_IRQ_ENABLE | TIFM_IRQ_SOCKMASK((1 << fm->num_sockets) - 1),
drivers/misc/tifm_7xx1.c
270
writel(TIFM_IRQ_FIFOMASK(good_sockets)
drivers/misc/tifm_7xx1.c
273
writel(TIFM_IRQ_FIFOMASK(good_sockets)
drivers/misc/tifm_7xx1.c
286
writel(TIFM_IRQ_ENABLE,
drivers/misc/tifm_7xx1.c
358
writel(TIFM_IRQ_ENABLE | TIFM_IRQ_SOCKMASK((1 << fm->num_sockets) - 1),
drivers/misc/tifm_7xx1.c
360
writel(TIFM_IRQ_ENABLE | TIFM_IRQ_SOCKMASK((1 << fm->num_sockets) - 1),
drivers/misc/tifm_7xx1.c
386
writel(TIFM_IRQ_SETALL, fm->addr + FM_CLEAR_INTERRUPT_ENABLE);
drivers/misc/tifm_7xx1.c
50
writel(TIFM_IRQ_ENABLE, fm->addr + FM_CLEAR_INTERRUPT_ENABLE);
drivers/misc/tifm_7xx1.c
65
writel(irq_status, fm->addr + FM_INTERRUPT_STATUS);
drivers/misc/tifm_7xx1.c
70
writel(TIFM_IRQ_ENABLE, fm->addr + FM_SET_INTERRUPT_ENABLE);
drivers/misc/tifm_7xx1.c
83
writel(0x0e00, sock_addr + SOCK_CONTROL);
drivers/misc/tifm_7xx1.c
97
writel(readl(sock_addr + SOCK_CONTROL) | TIFM_CTRL_LED,
drivers/misc/vmw_vmci/vmci_guest.c
112
writel(val, dev->mmio_base + reg);
drivers/mmc/host/bcm2835.c
1125
writel(host->cdiv, host->ioaddr + SDCDIV);
drivers/mmc/host/bcm2835.c
1148
writel(host->cdiv, host->ioaddr + SDCDIV);
drivers/mmc/host/bcm2835.c
1151
writel(mmc->actual_clock / 2, host->ioaddr + SDTOUT);
drivers/mmc/host/bcm2835.c
1248
writel(host->hcfg, host->ioaddr + SDHCFG);
drivers/mmc/host/bcm2835.c
1465
writel(SDVDD_POWER_OFF, host->ioaddr + SDVDD);
drivers/mmc/host/bcm2835.c
248
writel(SDVDD_POWER_OFF, host->ioaddr + SDVDD);
drivers/mmc/host/bcm2835.c
249
writel(0, host->ioaddr + SDCMD);
drivers/mmc/host/bcm2835.c
250
writel(0, host->ioaddr + SDARG);
drivers/mmc/host/bcm2835.c
251
writel(0xf00000, host->ioaddr + SDTOUT);
drivers/mmc/host/bcm2835.c
252
writel(0, host->ioaddr + SDCDIV);
drivers/mmc/host/bcm2835.c
253
writel(0x7f8, host->ioaddr + SDHSTS); /* Write 1s to clear */
drivers/mmc/host/bcm2835.c
254
writel(0, host->ioaddr + SDHCFG);
drivers/mmc/host/bcm2835.c
255
writel(0, host->ioaddr + SDHBCT);
drivers/mmc/host/bcm2835.c
256
writel(0, host->ioaddr + SDHBLC);
drivers/mmc/host/bcm2835.c
264
writel(temp, host->ioaddr + SDEDM);
drivers/mmc/host/bcm2835.c
266
writel(SDVDD_POWER_ON, host->ioaddr + SDVDD);
drivers/mmc/host/bcm2835.c
269
writel(host->hcfg, host->ioaddr + SDHCFG);
drivers/mmc/host/bcm2835.c
270
writel(host->cdiv, host->ioaddr + SDCDIV);
drivers/mmc/host/bcm2835.c
305
writel(edm | SDEDM_FORCE_DATA_MODE,
drivers/mmc/host/bcm2835.c
412
writel(*(buf++), host->ioaddr + SDDATA);
drivers/mmc/host/bcm2835.c
538
writel(host->hcfg, host->ioaddr + SDHCFG);
drivers/mmc/host/bcm2835.c
569
writel(data->blksz, host->ioaddr + SDHBCT);
drivers/mmc/host/bcm2835.c
570
writel(data->blocks, host->ioaddr + SDHBLC);
drivers/mmc/host/bcm2835.c
649
writel(sdhsts, host->ioaddr + SDHSTS);
drivers/mmc/host/bcm2835.c
660
writel(cmd->arg, host->ioaddr + SDARG);
drivers/mmc/host/bcm2835.c
683
writel(sdcmd | SDCMD_NEW_FLAG, host->ioaddr + SDCMD);
drivers/mmc/host/bcm2835.c
721
writel(host->hcfg, host->ioaddr + SDHCFG);
drivers/mmc/host/bcm2835.c
758
writel(SDHSTS_ERROR_MASK, host->ioaddr + SDHSTS);
drivers/mmc/host/bcm2835.c
777
writel(edm | SDEDM_FORCE_DATA_MODE,
drivers/mmc/host/bcm2835.c
930
writel(host->hcfg, host->ioaddr + SDHCFG);
drivers/mmc/host/bcm2835.c
942
writel(host->hcfg, host->ioaddr + SDHCFG);
drivers/mmc/host/bcm2835.c
981
writel(SDHSTS_BUSY_IRPT |
drivers/mmc/host/davinci_mmc.c
1031
writel(SDIOIST_IOINT, host->base + DAVINCI_SDIOIST);
drivers/mmc/host/davinci_mmc.c
1035
writel(readl(host->base + DAVINCI_SDIOIEN) |
drivers/mmc/host/davinci_mmc.c
1040
writel(readl(host->base + DAVINCI_SDIOIEN) & ~SDIOIEN_IOINTEN,
drivers/mmc/host/davinci_mmc.c
1106
writel(0, host->base + DAVINCI_MMCCLK);
drivers/mmc/host/davinci_mmc.c
1107
writel(MMCCLK_CLKEN, host->base + DAVINCI_MMCCLK);
drivers/mmc/host/davinci_mmc.c
1109
writel(0x1FFF, host->base + DAVINCI_MMCTOR);
drivers/mmc/host/davinci_mmc.c
1110
writel(0xFFFF, host->base + DAVINCI_MMCTOD);
drivers/mmc/host/davinci_mmc.c
1354
writel(0, host->base + DAVINCI_MMCIM);
drivers/mmc/host/davinci_mmc.c
235
writel(*((u32 *)p), host->base + DAVINCI_MMCDXR);
drivers/mmc/host/davinci_mmc.c
332
writel(0x1FFF, host->base + DAVINCI_MMCTOR);
drivers/mmc/host/davinci_mmc.c
355
writel(cmd->arg, host->base + DAVINCI_MMCARGHL);
drivers/mmc/host/davinci_mmc.c
356
writel(cmd_reg, host->base + DAVINCI_MMCCMD);
drivers/mmc/host/davinci_mmc.c
370
writel(im_val, host->base + DAVINCI_MMCIM);
drivers/mmc/host/davinci_mmc.c
518
writel(0, host->base + DAVINCI_MMCBLEN);
drivers/mmc/host/davinci_mmc.c
519
writel(0, host->base + DAVINCI_MMCNBLK);
drivers/mmc/host/davinci_mmc.c
533
writel(timeout, host->base + DAVINCI_MMCTOD);
drivers/mmc/host/davinci_mmc.c
534
writel(data->blocks, host->base + DAVINCI_MMCNBLK);
drivers/mmc/host/davinci_mmc.c
535
writel(data->blksz, host->base + DAVINCI_MMCBLEN);
drivers/mmc/host/davinci_mmc.c
541
writel(fifo_lev | MMCFIFOCTL_FIFODIR_WR | MMCFIFOCTL_FIFORST,
drivers/mmc/host/davinci_mmc.c
543
writel(fifo_lev | MMCFIFOCTL_FIFODIR_WR,
drivers/mmc/host/davinci_mmc.c
548
writel(fifo_lev | MMCFIFOCTL_FIFODIR_RD | MMCFIFOCTL_FIFORST,
drivers/mmc/host/davinci_mmc.c
550
writel(fifo_lev | MMCFIFOCTL_FIFODIR_RD,
drivers/mmc/host/davinci_mmc.c
650
writel(temp, host->base + DAVINCI_MMCCLK);
drivers/mmc/host/davinci_mmc.c
662
writel(temp, host->base + DAVINCI_MMCCLK);
drivers/mmc/host/davinci_mmc.c
668
writel(temp, host->base + DAVINCI_MMCCLK);
drivers/mmc/host/davinci_mmc.c
670
writel(temp | MMCCLK_CLKEN, host->base + DAVINCI_MMCCLK);
drivers/mmc/host/davinci_mmc.c
701
writel((readl(host->base + DAVINCI_MMCCTL) &
drivers/mmc/host/davinci_mmc.c
708
writel((readl(host->base + DAVINCI_MMCCTL) &
drivers/mmc/host/davinci_mmc.c
712
writel(readl(host->base + DAVINCI_MMCCTL) |
drivers/mmc/host/davinci_mmc.c
719
writel(readl(host->base + DAVINCI_MMCCTL) &
drivers/mmc/host/davinci_mmc.c
723
writel(readl(host->base + DAVINCI_MMCCTL) &
drivers/mmc/host/davinci_mmc.c
737
writel(0, host->base + DAVINCI_MMCARGHL);
drivers/mmc/host/davinci_mmc.c
738
writel(MMCCMD_INITCK, host->base + DAVINCI_MMCCMD);
drivers/mmc/host/davinci_mmc.c
768
writel(SDIOIST_IOINT, host->base + DAVINCI_SDIOIST);
drivers/mmc/host/davinci_mmc.c
784
writel(0, host->base + DAVINCI_MMCIM);
drivers/mmc/host/davinci_mmc.c
812
writel(0, host->base + DAVINCI_MMCIM);
drivers/mmc/host/davinci_mmc.c
828
writel(temp, host->base + DAVINCI_MMCCTL);
drivers/mmc/host/davinci_mmc.c
850
writel(status | SDIOIST_IOINT, host->base + DAVINCI_SDIOIST);
drivers/mmc/host/davinci_mmc.c
869
writel(0, host->base + DAVINCI_MMCIM);
drivers/mmc/host/davinci_mmc.c
894
writel(0, host->base + DAVINCI_MMCIM);
drivers/mmc/host/davinci_mmc.c
909
writel(im_val, host->base + DAVINCI_MMCIM);
drivers/mmc/host/jz4740_mmc.c
193
return writel(val, host->base + JZ_REG_MMC_IMASK);
drivers/mmc/host/jz4740_mmc.c
202
writel(val, host->base + JZ_REG_MMC_IREG);
drivers/mmc/host/jz4740_mmc.c
535
writel(buf[0], fifo_addr);
drivers/mmc/host/jz4740_mmc.c
536
writel(buf[1], fifo_addr);
drivers/mmc/host/jz4740_mmc.c
537
writel(buf[2], fifo_addr);
drivers/mmc/host/jz4740_mmc.c
538
writel(buf[3], fifo_addr);
drivers/mmc/host/jz4740_mmc.c
539
writel(buf[4], fifo_addr);
drivers/mmc/host/jz4740_mmc.c
540
writel(buf[5], fifo_addr);
drivers/mmc/host/jz4740_mmc.c
541
writel(buf[6], fifo_addr);
drivers/mmc/host/jz4740_mmc.c
542
writel(buf[7], fifo_addr);
drivers/mmc/host/jz4740_mmc.c
552
writel(*buf, fifo_addr);
drivers/mmc/host/jz4740_mmc.c
722
writel(JZ_MMC_DMAC_DMA_EN | JZ_MMC_DMAC_DMA_SEL,
drivers/mmc/host/jz4740_mmc.c
728
writel(0, host->base + JZ_REG_MMC_DMAC);
drivers/mmc/host/jz4740_mmc.c
736
writel(cmd->arg, host->base + JZ_REG_MMC_ARG);
drivers/mmc/host/jz4740_mmc.c
737
writel(cmdat, host->base + JZ_REG_MMC_CMDAT);
drivers/mmc/host/jz4740_mmc.c
908
writel(JZ_MMC_LPM_DRV_RISING_QTR_PHASE_DLY |
drivers/mmc/host/jz4740_mmc.c
913
writel(JZ_MMC_LPM_DRV_RISING |
drivers/mmc/host/jz4740_mmc.c
917
writel(JZ_MMC_LPM_LOW_POWER_MODE_EN,
drivers/mmc/host/loongson2-mmc.c
694
writel(val, regs);
drivers/mmc/host/loongson2-mmc.c
726
writel(val, regs);
drivers/mmc/host/meson-gx-mmc.c
1000
writel(start, host->regs + SD_EMMC_START);
drivers/mmc/host/meson-gx-mmc.c
1072
writel(cfg, host->regs + SD_EMMC_CFG);
drivers/mmc/host/meson-gx-mmc.c
1215
writel(0, host->regs + SD_EMMC_START);
drivers/mmc/host/meson-gx-mmc.c
1218
writel(0, host->regs + SD_EMMC_IRQ_EN);
drivers/mmc/host/meson-gx-mmc.c
1219
writel(IRQ_EN_MASK, host->regs + SD_EMMC_STATUS);
drivers/mmc/host/meson-gx-mmc.c
1220
writel(IRQ_EN_MASK, host->regs + SD_EMMC_IRQ_EN);
drivers/mmc/host/meson-gx-mmc.c
1303
writel(0, host->regs + SD_EMMC_IRQ_EN);
drivers/mmc/host/meson-gx-mmc.c
336
writel(cfg, host->regs + SD_EMMC_CFG);
drivers/mmc/host/meson-gx-mmc.c
350
writel(cfg, host->regs + SD_EMMC_CFG);
drivers/mmc/host/meson-gx-mmc.c
376
writel(cfg, host->regs + SD_EMMC_CFG);
drivers/mmc/host/meson-gx-mmc.c
385
writel(cfg, host->regs + SD_EMMC_CFG);
drivers/mmc/host/meson-gx-mmc.c
438
writel(clk_reg, host->regs + SD_EMMC_CLOCK);
drivers/mmc/host/meson-gx-mmc.c
512
writel(val, host->regs + host->data->adjust);
drivers/mmc/host/meson-gx-mmc.c
523
writel(val, host->regs + host->data->adjust);
drivers/mmc/host/meson-gx-mmc.c
538
writel(val, host->regs + host->data->adjust);
drivers/mmc/host/meson-gx-mmc.c
548
writel(val, host->regs + host->data->adjust);
drivers/mmc/host/meson-gx-mmc.c
642
writel(val, host->regs + SD_EMMC_CFG);
drivers/mmc/host/meson-gx-mmc.c
685
writel(cfg, host->regs + SD_EMMC_CFG);
drivers/mmc/host/meson-gx-mmc.c
740
writel(start, host->regs + SD_EMMC_START);
drivers/mmc/host/meson-gx-mmc.c
770
writel(*buf++, host->bounce_iomem_buf + offset + buf_offset);
drivers/mmc/host/meson-gx-mmc.c
848
writel(cmd_cfg, host->regs + SD_EMMC_CMD_CFG);
drivers/mmc/host/meson-gx-mmc.c
849
writel(cmd_data, host->regs + SD_EMMC_CMD_DAT);
drivers/mmc/host/meson-gx-mmc.c
850
writel(0, host->regs + SD_EMMC_CMD_RSP);
drivers/mmc/host/meson-gx-mmc.c
852
writel(cmd->arg, host->regs + SD_EMMC_CMD_ARG);
drivers/mmc/host/meson-gx-mmc.c
902
writel(0, host->regs + SD_EMMC_START);
drivers/mmc/host/meson-gx-mmc.c
928
writel(reg_irqen, host->regs + SD_EMMC_IRQ_EN);
drivers/mmc/host/meson-gx-mmc.c
951
writel(status, host->regs + SD_EMMC_STATUS);
drivers/mmc/host/mmci.c
1256
writel(timeout, base + MMCIDATATIMER);
drivers/mmc/host/mmci.c
1257
writel(host->size, base + MMCIDATALENGTH);
drivers/mmc/host/mmci.c
1316
writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0);
drivers/mmc/host/mmci.c
1331
writel(0, base + MMCICOMMAND);
drivers/mmc/host/mmci.c
1377
writel(cmd->arg, base + MMCIARGUMENT);
drivers/mmc/host/mmci.c
1378
writel(c, base + MMCICOMMAND);
drivers/mmc/host/mmci.c
1763
writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0);
drivers/mmc/host/mmci.c
1817
writel(status & ~host->variant->busy_detect_mask,
drivers/mmc/host/mmci.c
1820
writel(status, host->base + MMCICLEAR);
drivers/mmc/host/mmci.c
1867
writel(host->clk_reg, host->base + MMCICLOCK);
drivers/mmc/host/mmci.c
1868
writel(host->pwr_reg, host->base + MMCIPOWER);
drivers/mmc/host/mmci.c
1869
writel(MCI_IRQENABLE | host->variant->start_err,
drivers/mmc/host/mmci.c
2421
writel(0, host->base + MMCIMASK0);
drivers/mmc/host/mmci.c
2424
writel(0, host->base + MMCIMASK1);
drivers/mmc/host/mmci.c
2426
writel(0xfff, host->base + MMCICLEAR);
drivers/mmc/host/mmci.c
2464
writel(MCI_IRQENABLE | variant->start_err, host->base + MMCIMASK0);
drivers/mmc/host/mmci.c
2506
writel(0, host->base + MMCIMASK0);
drivers/mmc/host/mmci.c
2509
writel(0, host->base + MMCIMASK1);
drivers/mmc/host/mmci.c
2511
writel(0, host->base + MMCICOMMAND);
drivers/mmc/host/mmci.c
2512
writel(0, host->base + MMCIDATACTRL);
drivers/mmc/host/mmci.c
2525
writel(0, host->base + MMCIMASK0);
drivers/mmc/host/mmci.c
2527
writel(0, host->base + MMCIDATACTRL);
drivers/mmc/host/mmci.c
2528
writel(0, host->base + MMCIPOWER);
drivers/mmc/host/mmci.c
2529
writel(0, host->base + MMCICLOCK);
drivers/mmc/host/mmci.c
2543
writel(host->clk_reg, host->base + MMCICLOCK);
drivers/mmc/host/mmci.c
2544
writel(host->datactrl_reg, host->base + MMCIDATACTRL);
drivers/mmc/host/mmci.c
2545
writel(host->pwr_reg, host->base + MMCIPOWER);
drivers/mmc/host/mmci.c
2547
writel(MCI_IRQENABLE | host->variant->start_err,
drivers/mmc/host/mmci.c
407
writel(clk, host->base + MMCICLOCK);
drivers/mmc/host/mmci.c
418
writel(pwr, host->base + MMCIPOWER);
drivers/mmc/host/mmci.c
433
writel(datactrl, host->base + MMCIDATACTRL);
drivers/mmc/host/mmci.c
608
writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK,
drivers/mmc/host/mmci.c
634
writel(0, host->base + MMCICOMMAND);
drivers/mmc/host/mmci.c
655
writel(mask0, base + MMCIMASK0);
drivers/mmc/host/mmci.c
659
writel(mask, base + MMCIMASK1);
drivers/mmc/host/mmci.c
697
writel(host->variant->busy_detect_mask, base + MMCICLEAR);
drivers/mmc/host/mmci.c
698
writel(readl(base + MMCIMASK0) &
drivers/mmc/host/mmci.c
762
writel(readl(base + MMCIMASK0) |
drivers/mmc/host/mmci.c
791
writel(host->variant->busy_detect_mask, base + MMCICLEAR);
drivers/mmc/host/mmci.c
805
writel(host->variant->busy_detect_mask, base + MMCICLEAR);
drivers/mmc/host/mmci_stm32_sdmmc.c
390
writel(MCI_IRQENABLE | host->variant->start_err,
drivers/mmc/host/moxart-mmc.c
192
writel(*status & mask, host->base + REG_CLEAR);
drivers/mmc/host/moxart-mmc.c
209
writel(RSP_TIMEOUT | RSP_CRC_OK |
drivers/mmc/host/moxart-mmc.c
211
writel(cmd->arg, host->base + REG_ARGUMENT);
drivers/mmc/host/moxart-mmc.c
225
writel(cmdctrl | CMD_EN, host->base + REG_COMMAND);
drivers/mmc/host/moxart-mmc.c
386
writel(DCR_DATA_FIFO_RESET, host->base + REG_DATA_CONTROL);
drivers/mmc/host/moxart-mmc.c
387
writel(MASK_DATA | FIFO_URUN | FIFO_ORUN, host->base + REG_CLEAR);
drivers/mmc/host/moxart-mmc.c
388
writel(host->rate, host->base + REG_DATA_TIMER);
drivers/mmc/host/moxart-mmc.c
389
writel(host->data_len, host->base + REG_DATA_LENGTH);
drivers/mmc/host/moxart-mmc.c
390
writel(datactrl, host->base + REG_DATA_CONTROL);
drivers/mmc/host/moxart-mmc.c
417
writel(CARD_CHANGE, host->base + REG_INTERRUPT_MASK);
drivers/mmc/host/moxart-mmc.c
426
writel(MASK_INTR_PIO, host->base + REG_INTERRUPT_MASK);
drivers/mmc/host/moxart-mmc.c
476
writel(MASK_INTR_PIO, host->base + REG_CLEAR);
drivers/mmc/host/moxart-mmc.c
477
writel(CARD_CHANGE, host->base + REG_INTERRUPT_MASK);
drivers/mmc/host/moxart-mmc.c
506
writel(ctrl, host->base + REG_CLOCK_CONTROL);
drivers/mmc/host/moxart-mmc.c
510
writel(readl(host->base + REG_POWER_CONTROL) & ~SD_POWER_ON,
drivers/mmc/host/moxart-mmc.c
518
writel(SD_POWER_ON | (u32) power,
drivers/mmc/host/moxart-mmc.c
524
writel(BUS_WIDTH_4, host->base + REG_BUS_WIDTH);
drivers/mmc/host/moxart-mmc.c
527
writel(BUS_WIDTH_1, host->base + REG_BUS_WIDTH);
drivers/mmc/host/moxart-mmc.c
654
writel(0, host->base + REG_INTERRUPT_MASK);
drivers/mmc/host/moxart-mmc.c
656
writel(CMD_SDC_RESET, host->base + REG_COMMAND);
drivers/mmc/host/moxart-mmc.c
695
writel(0, host->base + REG_INTERRUPT_MASK);
drivers/mmc/host/moxart-mmc.c
696
writel(0, host->base + REG_POWER_CONTROL);
drivers/mmc/host/moxart-mmc.c
697
writel(readl(host->base + REG_CLOCK_CONTROL) | CLK_OFF,
drivers/mmc/host/mtk-sd.c
1087
writel(host->def_tune_para.iocon, host->base + MSDC_IOCON);
drivers/mmc/host/mtk-sd.c
1089
writel(host->def_tune_para.emmc_top_control,
drivers/mmc/host/mtk-sd.c
1091
writel(host->def_tune_para.emmc_top_cmd,
drivers/mmc/host/mtk-sd.c
1094
writel(host->def_tune_para.pad_tune,
drivers/mmc/host/mtk-sd.c
1098
writel(host->saved_tune_para.iocon, host->base + MSDC_IOCON);
drivers/mmc/host/mtk-sd.c
1099
writel(host->saved_tune_para.pad_cmd_tune,
drivers/mmc/host/mtk-sd.c
1102
writel(host->saved_tune_para.emmc_top_control,
drivers/mmc/host/mtk-sd.c
1104
writel(host->saved_tune_para.emmc_top_cmd,
drivers/mmc/host/mtk-sd.c
1107
writel(host->saved_tune_para.pad_tune,
drivers/mmc/host/mtk-sd.c
1203
writel(data->blocks, host->base + SDC_BLK_NUM);
drivers/mmc/host/mtk-sd.c
1464
writel(cmd->arg, host->base + SDC_ARG);
drivers/mmc/host/mtk-sd.c
1465
writel(rawcmd, host->base + SDC_CMD);
drivers/mmc/host/mtk-sd.c
1637
writel(val, host->base + SDC_CFG);
drivers/mmc/host/mtk-sd.c
1806
writel(events & event_mask, host->base + MSDC_INT);
drivers/mmc/host/mtk-sd.c
1829
writel(events, host->base + MSDC_INT);
drivers/mmc/host/mtk-sd.c
1882
writel(0, host->base + MSDC_INTEN);
drivers/mmc/host/mtk-sd.c
1884
writel(val, host->base + MSDC_INT);
drivers/mmc/host/mtk-sd.c
1900
writel(0, host->top_base + EMMC_TOP_CONTROL);
drivers/mmc/host/mtk-sd.c
1901
writel(0, host->top_base + EMMC_TOP_CMD);
drivers/mmc/host/mtk-sd.c
1903
writel(0, host->base + tune_reg);
drivers/mmc/host/mtk-sd.c
1905
writel(0, host->base + MSDC_IOCON);
drivers/mmc/host/mtk-sd.c
1934
writel(val, host->base + MSDC_PATCH_BIT);
drivers/mmc/host/mtk-sd.c
1997
writel(pb1_val, host->base + MSDC_PATCH_BIT1);
drivers/mmc/host/mtk-sd.c
1998
writel(pb2_val, host->base + MSDC_PATCH_BIT2);
drivers/mmc/host/mtk-sd.c
2014
writel(top_ctl_val, host->top_base + EMMC_TOP_CONTROL);
drivers/mmc/host/mtk-sd.c
2015
writel(top_cmd_val, host->top_base + EMMC_TOP_CMD);
drivers/mmc/host/mtk-sd.c
2080
writel(0, host->base + MSDC_INTEN);
drivers/mmc/host/mtk-sd.c
2083
writel(val, host->base + MSDC_INT);
drivers/mmc/host/mtk-sd.c
2235
writel(regval, host->top_base + EMMC_TOP_CMD);
drivers/mmc/host/mtk-sd.c
2266
writel(regval, host->top_base + EMMC_TOP_CONTROL);
drivers/mmc/host/mtk-sd.c
2599
writel(host->hs400_ds_delay,
drivers/mmc/host/mtk-sd.c
2606
writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE);
drivers/mmc/host/mtk-sd.c
2783
writel(MSDC_INT_CMDQ, host->base + MSDC_INTEN);
drivers/mmc/host/mtk-sd.c
2806
writel(val, host->base + MSDC_INT);
drivers/mmc/host/mtk-sd.c
3253
writel(host->save_para.msdc_cfg, host->base + MSDC_CFG);
drivers/mmc/host/mtk-sd.c
3254
writel(host->save_para.iocon, host->base + MSDC_IOCON);
drivers/mmc/host/mtk-sd.c
3255
writel(host->save_para.sdc_cfg, host->base + SDC_CFG);
drivers/mmc/host/mtk-sd.c
3256
writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT);
drivers/mmc/host/mtk-sd.c
3257
writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1);
drivers/mmc/host/mtk-sd.c
3258
writel(host->save_para.patch_bit2, host->base + MSDC_PATCH_BIT2);
drivers/mmc/host/mtk-sd.c
3259
writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE);
drivers/mmc/host/mtk-sd.c
3260
writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE);
drivers/mmc/host/mtk-sd.c
3261
writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0);
drivers/mmc/host/mtk-sd.c
3262
writel(host->save_para.emmc50_cfg3, host->base + EMMC50_CFG3);
drivers/mmc/host/mtk-sd.c
3263
writel(host->save_para.sdc_fifo_cfg, host->base + SDC_FIFO_CFG);
drivers/mmc/host/mtk-sd.c
3265
writel(host->save_para.emmc_top_control,
drivers/mmc/host/mtk-sd.c
3267
writel(host->save_para.emmc_top_cmd,
drivers/mmc/host/mtk-sd.c
3269
writel(host->save_para.emmc50_pad_ds_tune,
drivers/mmc/host/mtk-sd.c
3271
writel(host->save_para.loop_test_control,
drivers/mmc/host/mtk-sd.c
3274
writel(host->save_para.pad_tune, host->base + tune_reg);
drivers/mmc/host/mtk-sd.c
3338
writel(val, host->base + MSDC_INT);
drivers/mmc/host/mtk-sd.c
718
writel(val, reg);
drivers/mmc/host/mtk-sd.c
726
writel(val, reg);
drivers/mmc/host/mtk-sd.c
735
writel(tv, reg);
drivers/mmc/host/mtk-sd.c
757
writel(val, host->base + MSDC_INT);
drivers/mmc/host/mtk-sd.c
843
writel(lower_32_bits(dma->gpd_addr), host->base + MSDC_DMA_SA);
drivers/mmc/host/mtk-sd.c
984
writel(val, host->top_base + LOOP_TEST_CONTROL);
drivers/mmc/host/mvsdio.c
53
#define mvsd_write(offs, val) writel(val, iobase + (offs))
drivers/mmc/host/mvsdio.c
679
writel(0, iobase + MVSD_WINDOW_CTRL(i));
drivers/mmc/host/mvsdio.c
680
writel(0, iobase + MVSD_WINDOW_BASE(i));
drivers/mmc/host/mvsdio.c
685
writel(((cs->size - 1) & 0xffff0000) |
drivers/mmc/host/mvsdio.c
689
writel(cs->base, iobase + MVSD_WINDOW_BASE(i));
drivers/mmc/host/mxcmmc.c
198
writel(val, host->base + reg);
drivers/mmc/host/mxs-mmc.c
105
writel(BF_SSP(0xffff, TIMING_TIMEOUT) |
drivers/mmc/host/mxs-mmc.c
115
writel(ctrl0, ssp->base + HW_SSP_CTRL0);
drivers/mmc/host/mxs-mmc.c
116
writel(ctrl1, ssp->base + HW_SSP_CTRL1(ssp));
drivers/mmc/host/mxs-mmc.c
186
writel(stat & MXS_MMC_IRQ_BITS,
drivers/mmc/host/mxs-mmc.c
406
writel(data_size, ssp->base + HW_SSP_XFER_SIZE);
drivers/mmc/host/mxs-mmc.c
407
writel(BF_SSP(log2_blksz, BLOCK_SIZE_BLOCK_SIZE) |
drivers/mmc/host/mxs-mmc.c
427
writel(val, ssp->base + HW_SSP_TIMING(ssp));
drivers/mmc/host/mxs-mmc.c
520
writel(BM_SSP_CTRL0_SDIO_IRQ_CHECK,
drivers/mmc/host/mxs-mmc.c
522
writel(BM_SSP_CTRL1_SDIO_IRQ_EN,
drivers/mmc/host/mxs-mmc.c
525
writel(BM_SSP_CTRL0_SDIO_IRQ_CHECK,
drivers/mmc/host/mxs-mmc.c
527
writel(BM_SSP_CTRL1_SDIO_IRQ_EN,
drivers/mmc/host/owl-mmc.c
132
writel(regval, reg);
drivers/mmc/host/owl-mmc.c
146
writel(state, owl_host->base + OWL_REG_SD_STATE);
drivers/mmc/host/owl-mmc.c
226
writel(cmd->arg, owl_host->base + OWL_REG_SD_ARG);
drivers/mmc/host/owl-mmc.c
227
writel(cmd->opcode, owl_host->base + OWL_REG_SD_CMD);
drivers/mmc/host/owl-mmc.c
240
writel(mode, owl_host->base + OWL_REG_SD_CTL);
drivers/mmc/host/owl-mmc.c
300
writel(data->blocks, owl_host->base + OWL_REG_SD_BLK_NUM);
drivers/mmc/host/owl-mmc.c
301
writel(data->blksz, owl_host->base + OWL_REG_SD_BLK_SIZE);
drivers/mmc/host/owl-mmc.c
305
writel(total, owl_host->base + OWL_REG_SD_BUF_SIZE);
drivers/mmc/host/owl-mmc.c
307
writel(512, owl_host->base + OWL_REG_SD_BUF_SIZE);
drivers/mmc/host/owl-mmc.c
400
writel(reg | OWL_SD_CTL_RDELAY(OWL_SD_DELAY_LOW_CLK) |
drivers/mmc/host/owl-mmc.c
404
writel(reg | OWL_SD_CTL_RDELAY(OWL_SD_DELAY_MID_CLK) |
drivers/mmc/host/owl-mmc.c
408
writel(reg | OWL_SD_CTL_RDELAY(OWL_SD_DELAY_HIGH_CLK) |
drivers/mmc/host/owl-mmc.c
413
writel(reg | OWL_SD_CTL_RDELAY(OWL_SD_RDELAY_DDR50) |
drivers/mmc/host/owl-mmc.c
454
writel(reg, owl_host->base + OWL_REG_SD_EN);
drivers/mmc/host/owl-mmc.c
477
writel(mode, owl_host->base + OWL_REG_SD_CTL);
drivers/mmc/host/owl-mmc.c
496
writel(OWL_SD_ENABLE | OWL_SD_EN_RESE,
drivers/mmc/host/pxamci.c
122
writel(STOP_CLOCK, host->base + MMC_STRPCL);
drivers/mmc/host/pxamci.c
142
writel(host->imask, host->base + MMC_I_MASK);
drivers/mmc/host/pxamci.c
152
writel(host->imask, host->base + MMC_I_MASK);
drivers/mmc/host/pxamci.c
171
writel(nob, host->base + MMC_NOB);
drivers/mmc/host/pxamci.c
172
writel(data->blksz, host->base + MMC_BLKLEN);
drivers/mmc/host/pxamci.c
177
writel((timeout + 255) / 256, host->base + MMC_RDTO);
drivers/mmc/host/pxamci.c
255
writel(cmd->opcode, host->base + MMC_CMD);
drivers/mmc/host/pxamci.c
256
writel(cmd->arg >> 16, host->base + MMC_ARGH);
drivers/mmc/host/pxamci.c
257
writel(cmd->arg & 0xffff, host->base + MMC_ARGL);
drivers/mmc/host/pxamci.c
258
writel(cmdat, host->base + MMC_CMDAT);
drivers/mmc/host/pxamci.c
259
writel(host->clkrt, host->base + MMC_CLKRT);
drivers/mmc/host/pxamci.c
261
writel(START_CLOCK, host->base + MMC_STRPCL);
drivers/mmc/host/pxamci.c
549
writel(BUF_PART_FULL, host->base + MMC_PRTBUF);
drivers/mmc/host/pxamci.c
694
writel(0, host->base + MMC_SPI);
drivers/mmc/host/pxamci.c
695
writel(64, host->base + MMC_RESTO);
drivers/mmc/host/pxamci.c
696
writel(host->imask, host->base + MMC_I_MASK);
drivers/mmc/host/pxamci.c
770
writel(TXFIFO_WR_REQ|RXFIFO_RD_REQ|CLK_IS_OFF|STOP_CMD|
drivers/mmc/host/renesas_sdhi_core.c
349
writel(val, priv->scc_ctl + (addr << host->bus_shift));
drivers/mmc/host/renesas_sdhi_internal_dmac.c
308
writel(enable ? ~dma_irqs : INFO1_MASK_CLEAR, host->ctl + DM_CM_INFO1_MASK);
drivers/mmc/host/renesas_sdhi_internal_dmac.c
321
writel(RST_RESERVED_BITS & ~val, host->ctl + DM_CM_RST);
drivers/mmc/host/renesas_sdhi_internal_dmac.c
322
writel(RST_RESERVED_BITS | val, host->ctl + DM_CM_RST);
drivers/mmc/host/renesas_sdhi_internal_dmac.c
340
writel(status ^ dma_irqs, host->ctl + DM_CM_INFO1);
drivers/mmc/host/renesas_sdhi_internal_dmac.c
432
writel(dtran_mode, host->ctl + DM_CM_DTRAN_MODE);
drivers/mmc/host/renesas_sdhi_internal_dmac.c
433
writel(sg_dma_address(sg), host->ctl + DM_DTRAN_ADDR);
drivers/mmc/host/renesas_sdhi_internal_dmac.c
455
writel(DTRAN_CTRL_DM_START, host->ctl + DM_CM_DTRAN_CTRL);
drivers/mmc/host/renesas_sdhi_internal_dmac.c
544
writel(INFO1_MASK_CLEAR, host->ctl + DM_CM_INFO1_MASK);
drivers/mmc/host/renesas_sdhi_internal_dmac.c
545
writel(INFO2_MASK_CLEAR, host->ctl + DM_CM_INFO2_MASK);
drivers/mmc/host/renesas_sdhi_internal_dmac.c
546
writel(0, host->ctl + DM_CM_INFO1);
drivers/mmc/host/renesas_sdhi_internal_dmac.c
547
writel(0, host->ctl + DM_CM_INFO2);
drivers/mmc/host/sdhci-brcmstb.c
116
writel(sr->boot_main_ctl, priv->boot_regs + SDIO_BOOT_MAIN_CTL);
drivers/mmc/host/sdhci-brcmstb.c
119
writel(sr->sd_pin_sel, cr + SDIO_CFG_V1_SD_PIN_SEL);
drivers/mmc/host/sdhci-brcmstb.c
123
writel(sr->sd_pin_sel, cr + SDIO_CFG_SD_PIN_SEL);
drivers/mmc/host/sdhci-brcmstb.c
124
writel(sr->phy_sw_mode0_rxctrl, cr + SDIO_CFG_PHY_SW_MODE_0_RX_CTRL);
drivers/mmc/host/sdhci-brcmstb.c
125
writel(sr->max_50mhz_mode, cr + SDIO_CFG_MAX_50MHZ_MODE);
drivers/mmc/host/sdhci-brcmstb.c
222
writel(reg, host->ioaddr + SDHCI_VENDOR);
drivers/mmc/host/sdhci-brcmstb.c
283
writel(reg, brcmstb_priv->cfg_regs + SDIO_CFG_MAX_50MHZ_MODE);
drivers/mmc/host/sdhci-brcmstb.c
292
writel(reg, brcmstb_priv->cfg_regs + SDIO_CFG_CTRL);
drivers/mmc/host/sdhci-brcmstb.c
307
writel(reg, priv->cfg_regs + SDIO_CFG_OP_DLY);
drivers/mmc/host/sdhci-cadence.c
124
writel(val, reg);
drivers/mmc/host/sdhci-cadence.c
296
writel(SDHCI_CDNS_HRS37_MODE_MMC_HS200, hrs37_reg);
drivers/mmc/host/sdhci-cadence.c
299
writel(gap, hrs38_reg);
drivers/mmc/host/sdhci-cadence.c
403
writel(GENMASK(7, 3), priv->ctl_addr);
drivers/mmc/host/sdhci-cadence.c
404
writel(val, reg);
drivers/mmc/host/sdhci-cadence.c
422
writel(ELBA_BYTE_ENABLE_MASK(byte_enables), priv->ctl_addr);
drivers/mmc/host/sdhci-cadence.c
436
writel(ELBA_BYTE_ENABLE_MASK(byte_enables), priv->ctl_addr);
drivers/mmc/host/sdhci-cadence.c
468
writel(ELBA_BYTE_ENABLE_MASK(0xf), priv->ctl_addr);
drivers/mmc/host/sdhci-esdhc-imx.c
1035
writel(val | ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
drivers/mmc/host/sdhci-esdhc-imx.c
1093
writel(ctrl, host->ioaddr + ESDHC_MIX_CTRL);
drivers/mmc/host/sdhci-esdhc-imx.c
1094
writel(0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
drivers/mmc/host/sdhci-esdhc-imx.c
1096
writel(ctrl, host->ioaddr + ESDHC_MIX_CTRL);
drivers/mmc/host/sdhci-esdhc-imx.c
1104
writel(tuning_ctrl, host->ioaddr + ESDHC_TUNING_CTRL);
drivers/mmc/host/sdhci-esdhc-imx.c
1110
writel(sys_ctrl, host->ioaddr + ESDHC_SYSTEM_CONTROL);
drivers/mmc/host/sdhci-esdhc-imx.c
1115
writel(ctrl, host->ioaddr + SDHCI_AUTO_CMD_STATUS);
drivers/mmc/host/sdhci-esdhc-imx.c
1129
writel(ctrl, host->ioaddr + SDHCI_INT_STATUS);
drivers/mmc/host/sdhci-esdhc-imx.c
1188
writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
drivers/mmc/host/sdhci-esdhc-imx.c
1189
writel(FIELD_PREP(ESDHC_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK, val),
drivers/mmc/host/sdhci-esdhc-imx.c
1198
writel(sys_ctrl, host->ioaddr + ESDHC_SYSTEM_CONTROL);
drivers/mmc/host/sdhci-esdhc-imx.c
1212
writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
drivers/mmc/host/sdhci-esdhc-imx.c
1278
writel(clk_tune_ctrl_status, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
drivers/mmc/host/sdhci-esdhc-imx.c
1306
writel(m, host->ioaddr + ESDHC_MIX_CTRL);
drivers/mmc/host/sdhci-esdhc-imx.c
1359
writel(readl(host->ioaddr + ESDHC_VENDOR_SPEC) &
drivers/mmc/host/sdhci-esdhc-imx.c
1365
writel(ESDHC_STROBE_DLL_CTRL_RESET,
drivers/mmc/host/sdhci-esdhc-imx.c
1368
writel(0, host->ioaddr + ESDHC_STROBE_DLL_CTRL);
drivers/mmc/host/sdhci-esdhc-imx.c
1381
writel(v, host->ioaddr + ESDHC_STROBE_DLL_CTRL);
drivers/mmc/host/sdhci-esdhc-imx.c
1410
writel(m, host->ioaddr + ESDHC_MIX_CTRL);
drivers/mmc/host/sdhci-esdhc-imx.c
1415
writel(m, host->ioaddr + ESDHC_MIX_CTRL);
drivers/mmc/host/sdhci-esdhc-imx.c
1424
writel(v, host->ioaddr + ESDHC_DLL_CTRL);
drivers/mmc/host/sdhci-esdhc-imx.c
1429
writel(m, host->ioaddr + ESDHC_MIX_CTRL);
drivers/mmc/host/sdhci-esdhc-imx.c
1449
writel(m, host->ioaddr + ESDHC_MIX_CTRL);
drivers/mmc/host/sdhci-esdhc-imx.c
1535
writel(ESDHC_WTMK_DEFAULT_VAL, host->ioaddr + ESDHC_WTMK_LVL);
drivers/mmc/host/sdhci-esdhc-imx.c
1548
writel(readl(host->ioaddr + SDHCI_HOST_CONTROL)
drivers/mmc/host/sdhci-esdhc-imx.c
1557
writel(readl(host->ioaddr + 0x6c) & ~BIT(7),
drivers/mmc/host/sdhci-esdhc-imx.c
1562
writel(0x0, host->ioaddr + ESDHC_DLL_CTRL);
drivers/mmc/host/sdhci-esdhc-imx.c
1576
writel(tmp, host->ioaddr + ESDHC_VEND_SPEC2);
drivers/mmc/host/sdhci-esdhc-imx.c
1624
writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL);
drivers/mmc/host/sdhci-esdhc-imx.c
1633
writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL);
drivers/mmc/host/sdhci-esdhc-imx.c
1692
writel(reg, host->ioaddr + ESDHC_TUNING_CTRL);
drivers/mmc/host/sdhci-esdhc-imx.c
1698
writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
drivers/mmc/host/sdhci-esdhc-imx.c
1700
writel(FIELD_PREP(ESDHC_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK,
drivers/mmc/host/sdhci-esdhc-imx.c
1903
writel(0x0, host->ioaddr + ESDHC_MIX_CTRL);
drivers/mmc/host/sdhci-esdhc-imx.c
1904
writel(0x0, host->ioaddr + SDHCI_AUTO_CMD_STATUS);
drivers/mmc/host/sdhci-esdhc-imx.c
1905
writel(0x0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
drivers/mmc/host/sdhci-esdhc-imx.c
435
writel(((readl(base) & ~(mask << shift)) | (val << shift)), base);
drivers/mmc/host/sdhci-esdhc-imx.c
519
writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
drivers/mmc/host/sdhci-esdhc-imx.c
599
writel(SDHCI_INT_RESPONSE, host->ioaddr +
drivers/mmc/host/sdhci-esdhc-imx.c
627
writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
drivers/mmc/host/sdhci-esdhc-imx.c
629
writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
drivers/mmc/host/sdhci-esdhc-imx.c
644
writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
drivers/mmc/host/sdhci-esdhc-imx.c
651
writel(data, host->ioaddr + SDHCI_TRANSFER_MODE);
drivers/mmc/host/sdhci-esdhc-imx.c
656
writel(val, host->ioaddr + reg);
drivers/mmc/host/sdhci-esdhc-imx.c
732
writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
drivers/mmc/host/sdhci-esdhc-imx.c
742
writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
drivers/mmc/host/sdhci-esdhc-imx.c
755
writel(v, host->ioaddr + SDHCI_AUTO_CMD_STATUS);
drivers/mmc/host/sdhci-esdhc-imx.c
766
writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
drivers/mmc/host/sdhci-esdhc-imx.c
778
writel(m, host->ioaddr + ESDHC_MIX_CTRL);
drivers/mmc/host/sdhci-esdhc-imx.c
807
writel(m, host->ioaddr + ESDHC_WTMK_LVL);
drivers/mmc/host/sdhci-esdhc-imx.c
825
writel(val << 16,
drivers/mmc/host/sdhci-esdhc-imx.c
828
writel(val << 16 | imx_data->scratchpad,
drivers/mmc/host/sdhci-esdhc-imx.c
925
writel(new_val & ESDHC_MIX_CTRL_TUNING_MASK,
drivers/mmc/host/sdhci-esdhc-imx.c
969
writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
drivers/mmc/host/sdhci-esdhc-imx.c
986
writel(val | BIT(10), host->ioaddr + ESDHC_DLL_CTRL);
drivers/mmc/host/sdhci-esdhc-imx.c
988
writel(val, host->ioaddr + ESDHC_DLL_CTRL);
drivers/mmc/host/sdhci-esdhc-mcf.c
113
writel(val << 16 | mcf_data->aside,
drivers/mmc/host/sdhci-esdhc-mcf.c
118
writel((readl(base) & mask) | (val << shift), base);
drivers/mmc/host/sdhci-esdhc-mcf.c
123
writel(val, host->ioaddr + reg);
drivers/mmc/host/sdhci-esdhc-mcf.c
58
writel((readl(base) & ~mask) | val, base);
drivers/mmc/host/sdhci-esdhc-mcf.c
85
writel(host_ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
drivers/mmc/host/sdhci-esdhc-mcf.c
90
writel((readl(base) & mask) | (val << shift), base);
drivers/mmc/host/sdhci-iproc.c
76
writel(val, host->ioaddr + reg);
drivers/mmc/host/sdhci-of-arasan.c
258
writel(reg, host->ioaddr + PHY_CTRL_REG2);
drivers/mmc/host/sdhci-of-arasan.c
271
writel(reg, host->ioaddr + PHY_CTRL_REG2);
drivers/mmc/host/sdhci-of-arasan.c
300
writel(reg, host->ioaddr + PHY_CTRL_REG2);
drivers/mmc/host/sdhci-of-aspeed.c
108
writel(cap_val, sdc->regs + mirror_reg_offset);
drivers/mmc/host/sdhci-of-aspeed.c
124
writel(info, sdc->regs + ASPEED_SDC_INFO);
drivers/mmc/host/sdhci-of-aspeed.c
154
writel(reg, sdc->regs + ASPEED_SDC_PHASE);
drivers/mmc/host/sdhci-of-at91.c
195
writel(SDMMC_CACR_KEY | SDMMC_CACR_CAPWREN, host->ioaddr + SDMMC_CACR);
drivers/mmc/host/sdhci-of-at91.c
196
writel(caps0, host->ioaddr + SDHCI_CAPABILITIES);
drivers/mmc/host/sdhci-of-at91.c
197
writel(caps1, host->ioaddr + SDHCI_CAPABILITIES_1);
drivers/mmc/host/sdhci-of-at91.c
199
writel(0, host->ioaddr + SDMMC_CACR);
drivers/mmc/host/sdhci-omap.c
148
writel(data, host->base + host->omap_offset + offset);
drivers/mmc/host/sdhci-pci-core.c
797
writel(ltr, host->ioaddr + INTEL_ACTIVELTR);
drivers/mmc/host/sdhci-pci-core.c
798
writel(ltr, host->ioaddr + INTEL_IDLELTR);
drivers/mmc/host/sdhci-pic32.c
121
writel(bus, host->ioaddr + SDH_SHARED_BUS_CTRL);
drivers/mmc/host/sdhci-pxav3.c
102
writel(0, regs + SDHCI_WINDOW_CTRL(i));
drivers/mmc/host/sdhci-pxav3.c
103
writel(0, regs + SDHCI_WINDOW_BASE(i));
drivers/mmc/host/sdhci-pxav3.c
110
writel(((cs->size - 1) & 0xffff0000) |
drivers/mmc/host/sdhci-pxav3.c
115
writel(cs->base, regs + SDHCI_WINDOW_BASE(i));
drivers/mmc/host/sdhci-s3c.c
273
writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2);
drivers/mmc/host/sdhci-s3c.c
276
writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA,
drivers/mmc/host/sdhci-s3c.c
285
writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2);
drivers/mmc/host/sdhci-s3c.c
291
writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL3);
drivers/mmc/host/sdhci-tegra.c
1204
writel(val, cq_host->mmio + reg);
drivers/mmc/host/sdhci-tegra.c
1217
writel(val, cq_host->mmio + reg);
drivers/mmc/host/sdhci-tegra.c
1219
writel(val, cq_host->mmio + reg);
drivers/mmc/host/sdhci-tegra.c
216
writel((val << 16) | pltfm_host->xfer_mode_shadow,
drivers/mmc/host/sdhci-tegra.c
237
writel(val, host->ioaddr + reg);
drivers/mmc/host/sdhci-xenon-phy.c
317
writel(ARMADA_3700_SOC_PAD_1_8V, params->pad_ctrl.reg);
drivers/mmc/host/sdhci-xenon-phy.c
320
writel(ARMADA_3700_SOC_PAD_1_8V, params->pad_ctrl.reg);
drivers/mmc/host/sdhci-xenon-phy.c
322
writel(ARMADA_3700_SOC_PAD_3_3V, params->pad_ctrl.reg);
drivers/mmc/host/sdhci.h
736
writel(val, host->ioaddr + reg);
drivers/mmc/host/sdhci.h
783
writel(val, host->ioaddr + reg);
drivers/mmc/host/sdricoh_cs.c
99
writel(value, host->iobase + reg);
drivers/mmc/host/sh_mmcif.c
260
writel(val | readl(host->addr + reg), host->addr + reg);
drivers/mmc/host/sh_mmcif.c
266
writel(~val & readl(host->addr + reg), host->addr + reg);
drivers/mmc/host/sunplus-mmc.c
248
writel(value, host->base + SPMMC_SD_CONFIG0_REG);
drivers/mmc/host/sunplus-mmc.c
282
writel(value, host->base + SPMMC_SD_CONFIG1_REG);
drivers/mmc/host/sunplus-mmc.c
288
writel(value, host->base + SPMMC_SD_TIMING_CONFIG0_REG);
drivers/mmc/host/sunplus-mmc.c
291
writel(value, host->base + SPMMC_SD_CONFIG1_REG);
drivers/mmc/host/sunplus-mmc.c
296
writel(value, host->base + SPMMC_SD_CONFIG0_REG);
drivers/mmc/host/sunplus-mmc.c
300
writel(value, host->base + SPMMC_SD_CONFIG0_REG);
drivers/mmc/host/sunplus-mmc.c
322
writel(value, host->base + SPMMC_SD_CONFIG0_REG);
drivers/mmc/host/sunplus-mmc.c
334
writel(value, host->base + SPMMC_SD_CONFIG0_REG);
drivers/mmc/host/sunplus-mmc.c
348
writel(value, host->base + SPMMC_HW_DMA_CTRL_REG);
drivers/mmc/host/sunplus-mmc.c
350
writel(value, host->base + SPMMC_HW_DMA_CTRL_REG);
drivers/mmc/host/sunplus-mmc.c
353
writel(value, host->base + SPMMC_HW_DMA_CTRL_REG);
drivers/mmc/host/sunplus-mmc.c
354
writel(0x7, host->base + SPMMC_SD_RST_REG);
drivers/mmc/host/sunplus-mmc.c
365
writel(value, host->base + SPMMC_SD_CMDBUF0_3_REG);
drivers/mmc/host/sunplus-mmc.c
372
writel(value, host->base + SPMMC_SD_INT_REG);
drivers/mmc/host/sunplus-mmc.c
381
writel(value, host->base + SPMMC_SD_CONFIG0_REG);
drivers/mmc/host/sunplus-mmc.c
398
writel(value, host->base + SPMMC_SD_CONFIG0_REG);
drivers/mmc/host/sunplus-mmc.c
405
writel(data->blocks - 1, host->base + SPMMC_SD_PAGE_NUM_REG);
drivers/mmc/host/sunplus-mmc.c
406
writel(data->blksz - 1, host->base + SPMMC_SD_BLOCKSIZE_REG);
drivers/mmc/host/sunplus-mmc.c
418
writel(srcdst, host->base + SPMMC_CARD_MEDIATYPE_SRCDST_REG);
drivers/mmc/host/sunplus-mmc.c
427
writel(srcdst, host->base + SPMMC_CARD_MEDIATYPE_SRCDST_REG);
drivers/mmc/host/sunplus-mmc.c
448
writel(dma_addr, host->base + SPMMC_DMA_BASE_ADDR_REG);
drivers/mmc/host/sunplus-mmc.c
449
writel(dma_size, host->base + SPMMC_SDRAM_SECTOR_0_SIZE_REG);
drivers/mmc/host/sunplus-mmc.c
451
writel(dma_addr, host->base + SPMMC_SDRAM_SECTOR_1_ADDR_REG);
drivers/mmc/host/sunplus-mmc.c
452
writel(dma_size, host->base + SPMMC_SDRAM_SECTOR_1_LENG_REG);
drivers/mmc/host/sunplus-mmc.c
454
writel(dma_addr, host->base + SPMMC_SDRAM_SECTOR_2_ADDR_REG);
drivers/mmc/host/sunplus-mmc.c
455
writel(dma_size, host->base + SPMMC_SDRAM_SECTOR_2_LENG_REG);
drivers/mmc/host/sunplus-mmc.c
457
writel(dma_addr, host->base + SPMMC_SDRAM_SECTOR_3_ADDR_REG);
drivers/mmc/host/sunplus-mmc.c
458
writel(dma_size, host->base + SPMMC_SDRAM_SECTOR_3_LENG_REG);
drivers/mmc/host/sunplus-mmc.c
460
writel(dma_addr, host->base + SPMMC_SDRAM_SECTOR_4_ADDR_REG);
drivers/mmc/host/sunplus-mmc.c
461
writel(dma_size, host->base + SPMMC_SDRAM_SECTOR_4_LENG_REG);
drivers/mmc/host/sunplus-mmc.c
463
writel(dma_addr, host->base + SPMMC_SDRAM_SECTOR_5_ADDR_REG);
drivers/mmc/host/sunplus-mmc.c
464
writel(dma_size, host->base + SPMMC_SDRAM_SECTOR_5_LENG_REG);
drivers/mmc/host/sunplus-mmc.c
466
writel(dma_addr, host->base + SPMMC_SDRAM_SECTOR_6_ADDR_REG);
drivers/mmc/host/sunplus-mmc.c
467
writel(dma_size, host->base + SPMMC_SDRAM_SECTOR_6_LENG_REG);
drivers/mmc/host/sunplus-mmc.c
469
writel(dma_addr, host->base + SPMMC_SDRAM_SECTOR_7_ADDR_REG);
drivers/mmc/host/sunplus-mmc.c
470
writel(dma_size, host->base + SPMMC_SDRAM_SECTOR_7_LENG_REG);
drivers/mmc/host/sunplus-mmc.c
474
writel(value, host->base + SPMMC_SD_CONFIG0_REG);
drivers/mmc/host/sunplus-mmc.c
481
writel(value, host->base + SPMMC_SD_INT_REG);
drivers/mmc/host/sunplus-mmc.c
486
writel(value, host->base + SPMMC_SD_CONFIG0_REG);
drivers/mmc/host/sunplus-mmc.c
495
writel(value, host->base + SPMMC_SD_CTRL_REG);
drivers/mmc/host/sunplus-mmc.c
510
writel(value, host->base + SPMMC_SD_INT_REG);
drivers/mmc/host/sunplus-mmc.c
593
writel(timing_cfg0, host->base + SPMMC_SD_TIMING_CONFIG0_REG);
drivers/mmc/host/sunplus-mmc.c
648
writel(*buf, host->base + SPMMC_SD_PIODATATX_REG);
drivers/mmc/host/sunplus-mmc.c
679
writel(value, host->base + SPMMC_CARD_MEDIATYPE_SRCDST_REG);
drivers/mmc/host/sunplus-mmc.c
721
writel(value, host->base + SPMMC_SD_INT_REG);
drivers/mmc/host/sunplus-mmc.c
755
writel(value, host->base + SPMMC_SD_INT_REG);
drivers/mmc/host/sunplus-mmc.c
818
writel(value, host->base + SPMMC_SD_TIMING_CONFIG0_REG);
drivers/mmc/host/sunplus-mmc.c
836
writel(value, host->base + SPMMC_SD_TIMING_CONFIG0_REG);
drivers/mmc/host/sunxi-mmc.c
717
writel(SDXC_CAL_DL_SW_EN, host->reg_base + reg_off);
drivers/mmc/host/sunxi-mmc.c
80
writel((value), (host)->reg_base + SDXC_##reg)
drivers/mmc/host/tifm_sd.c
1004
writel(TIFM_FIFO_INT_SETALL,
drivers/mmc/host/tifm_sd.c
1006
writel(0, sock->addr + SOCK_DMA_FIFO_INT_ENABLE_SET);
drivers/mmc/host/tifm_sd.c
149
writel(val, sock->addr + SOCK_MMCSD_DATA);
drivers/mmc/host/tifm_sd.c
161
writel(val, sock->addr + SOCK_MMCSD_DATA);
drivers/mmc/host/tifm_sd.c
184
writel(host->bounce_buf_data[0],
drivers/mmc/host/tifm_sd.c
313
writel(sg_dma_address(sg) + dma_off, sock->addr + SOCK_DMA_ADDRESS);
drivers/mmc/host/tifm_sd.c
315
writel((dma_blk_cnt << 8) | TIFM_DMA_TX | TIFM_DMA_EN,
drivers/mmc/host/tifm_sd.c
318
writel((dma_blk_cnt << 8) | TIFM_DMA_EN,
drivers/mmc/host/tifm_sd.c
381
writel((cmd->arg >> 16) & 0xffff, sock->addr + SOCK_MMCSD_ARG_HIGH);
drivers/mmc/host/tifm_sd.c
382
writel(cmd->arg & 0xffff, sock->addr + SOCK_MMCSD_ARG_LOW);
drivers/mmc/host/tifm_sd.c
383
writel(cmd->opcode | cmd_mask, sock->addr + SOCK_MMCSD_COMMAND);
drivers/mmc/host/tifm_sd.c
428
writel(TIFM_MMCSD_EOFB
drivers/mmc/host/tifm_sd.c
439
writel((~TIFM_MMCSD_EOFB)
drivers/mmc/host/tifm_sd.c
448
writel((~TIFM_MMCSD_EOFB)
drivers/mmc/host/tifm_sd.c
494
writel(fifo_status, sock->addr + SOCK_DMA_FIFO_STATUS);
drivers/mmc/host/tifm_sd.c
516
writel(host_status & TIFM_MMCSD_ERRMASK,
drivers/mmc/host/tifm_sd.c
530
writel(TIFM_FIFO_INT_SETALL,
drivers/mmc/host/tifm_sd.c
532
writel(TIFM_DMA_RESET, sock->addr + SOCK_DMA_CONTROL);
drivers/mmc/host/tifm_sd.c
563
writel(host_status & TIFM_MMCSD_AE,
drivers/mmc/host/tifm_sd.c
581
writel(host_status, sock->addr + SOCK_MMCSD_STATUS);
drivers/mmc/host/tifm_sd.c
598
writel(data_timeout, sock->addr + SOCK_MMCSD_DATA_TO);
drivers/mmc/host/tifm_sd.c
599
writel((~TIFM_MMCSD_DPE)
drivers/mmc/host/tifm_sd.c
606
writel(data_timeout, sock->addr + SOCK_MMCSD_DATA_TO);
drivers/mmc/host/tifm_sd.c
607
writel(TIFM_MMCSD_DPE
drivers/mmc/host/tifm_sd.c
646
writel(TIFM_MMCSD_EOFB
drivers/mmc/host/tifm_sd.c
651
writel(TIFM_MMCSD_BUFINT
drivers/mmc/host/tifm_sd.c
654
writel(((TIFM_MMCSD_FIFO_SIZE - 1) << 8)
drivers/mmc/host/tifm_sd.c
689
writel(TIFM_FIFO_INT_SETALL,
drivers/mmc/host/tifm_sd.c
691
writel(ilog2(r_data->blksz) - 2,
drivers/mmc/host/tifm_sd.c
693
writel(TIFM_FIFO_ENABLE,
drivers/mmc/host/tifm_sd.c
695
writel(TIFM_FIFO_INTMASK,
drivers/mmc/host/tifm_sd.c
699
writel(TIFM_MMCSD_TXDE,
drivers/mmc/host/tifm_sd.c
702
writel(TIFM_MMCSD_RXDE,
drivers/mmc/host/tifm_sd.c
708
writel(r_data->blocks - 1,
drivers/mmc/host/tifm_sd.c
710
writel(r_data->blksz - 1,
drivers/mmc/host/tifm_sd.c
716
writel(TIFM_CTRL_LED | readl(sock->addr + SOCK_CONTROL),
drivers/mmc/host/tifm_sd.c
752
writel((~TIFM_MMCSD_BUFINT)
drivers/mmc/host/tifm_sd.c
771
writel((~TIFM_CTRL_LED) & readl(sock->addr + SOCK_CONTROL),
drivers/mmc/host/tifm_sd.c
804
writel(TIFM_MMCSD_4BBUS | readl(sock->addr + SOCK_MMCSD_CONFIG),
drivers/mmc/host/tifm_sd.c
807
writel((~TIFM_MMCSD_4BBUS)
drivers/mmc/host/tifm_sd.c
828
writel((~TIFM_CTRL_FAST_CLK)
drivers/mmc/host/tifm_sd.c
834
writel(TIFM_CTRL_FAST_CLK
drivers/mmc/host/tifm_sd.c
842
writel(host->clk_div
drivers/mmc/host/tifm_sd.c
882
writel(0, sock->addr + SOCK_MMCSD_INT_ENABLE);
drivers/mmc/host/tifm_sd.c
885
writel(TIFM_MMCSD_RESET, sock->addr + SOCK_MMCSD_SYSTEM_CONTROL);
drivers/mmc/host/tifm_sd.c
886
writel(host->clk_div | TIFM_MMCSD_POWER,
drivers/mmc/host/tifm_sd.c
904
writel(0, sock->addr + SOCK_MMCSD_NUM_BLOCKS);
drivers/mmc/host/tifm_sd.c
905
writel(host->clk_div | TIFM_MMCSD_POWER,
drivers/mmc/host/tifm_sd.c
907
writel(TIFM_MMCSD_RXDE, sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
drivers/mmc/host/tifm_sd.c
910
writel(64, sock->addr + SOCK_MMCSD_COMMAND_TO);
drivers/mmc/host/tifm_sd.c
911
writel(TIFM_MMCSD_INAB, sock->addr + SOCK_MMCSD_COMMAND);
drivers/mmc/host/tifm_sd.c
915
writel(host_status, sock->addr + SOCK_MMCSD_STATUS);
drivers/mmc/host/tifm_sd.c
930
writel(TIFM_MMCSD_CERR | TIFM_MMCSD_BRS | TIFM_MMCSD_EOC
drivers/mmc/host/tifm_sd.c
997
writel(0, sock->addr + SOCK_MMCSD_INT_ENABLE);
drivers/mmc/host/uniphier-sd.c
249
writel(UNIPHIER_SD_DMA_CTL_START, host->ctl + UNIPHIER_SD_DMA_CTL);
drivers/mmc/host/uniphier-sd.c
288
writel(dma_mode, host->ctl + UNIPHIER_SD_DMA_MODE);
drivers/mmc/host/uniphier-sd.c
291
writel(lower_32_bits(dma_addr), host->ctl + UNIPHIER_SD_DMA_ADDR_L);
drivers/mmc/host/uniphier-sd.c
292
writel(upper_32_bits(dma_addr), host->ctl + UNIPHIER_SD_DMA_ADDR_H);
drivers/mmc/host/uniphier-sd.c
338
writel(tmp, host->ctl + UNIPHIER_SD_DMA_RST);
drivers/mmc/host/uniphier-sd.c
341
writel(tmp, host->ctl + UNIPHIER_SD_DMA_RST);
drivers/mmc/host/uniphier-sd.c
479
writel(tmp, host->ctl + (CTL_SD_CARD_CLK_CTL << 1));
drivers/mmc/host/uniphier-sd.c
507
writel(tmp, host->ctl + (CTL_SD_CARD_CLK_CTL << 1));
drivers/mmc/host/uniphier-sd.c
510
writel(tmp, host->ctl + (CTL_SD_CARD_CLK_CTL << 1));
drivers/mmc/host/uniphier-sd.c
530
writel(val, host->ctl + UNIPHIER_SD_HOST_MODE);
drivers/mmc/host/uniphier-sd.c
540
writel(val, host->ctl + (CTL_SD_CARD_CLK_CTL << 1));
drivers/mmc/host/uniphier-sd.c
569
writel(tmp, host->ctl + UNIPHIER_SD_VOLT);
drivers/mmc/host/via-sdmmc.c
1058
writel(0x0, addrbase + VIA_CRDR_SDINTMASK);
drivers/mmc/host/via-sdmmc.c
1062
writel(lenreg, addrbase + VIA_CRDR_SDBLKLEN);
drivers/mmc/host/via-sdmmc.c
1074
writel(VIA_CRDR_SDACTIVE_INTMASK, addrbase + VIA_CRDR_SDINTMASK);
drivers/mmc/host/via-sdmmc.c
1190
writel(VIA_CRDR_DMACTRL_SFTRST,
drivers/mmc/host/via-sdmmc.c
1231
writel(0x0, addrbase + VIA_CRDR_SDINTMASK);
drivers/mmc/host/via-sdmmc.c
1234
writel(lenreg, addrbase + VIA_CRDR_SDBLKLEN);
drivers/mmc/host/via-sdmmc.c
1244
writel(pm_sdhcreg->sdcontrol_reg, addrbase + VIA_CRDR_SDCTRL);
drivers/mmc/host/via-sdmmc.c
1245
writel(pm_sdhcreg->sdcmdarg_reg, addrbase + VIA_CRDR_SDCARG);
drivers/mmc/host/via-sdmmc.c
1246
writel(pm_sdhcreg->sdintmask_reg, addrbase + VIA_CRDR_SDINTMASK);
drivers/mmc/host/via-sdmmc.c
1247
writel(pm_sdhcreg->sdrsptmo_reg, addrbase + VIA_CRDR_SDRSPTMO);
drivers/mmc/host/via-sdmmc.c
1248
writel(pm_sdhcreg->sdclksel_reg, addrbase + VIA_CRDR_SDCLKSEL);
drivers/mmc/host/via-sdmmc.c
1249
writel(pm_sdhcreg->sdextctrl_reg, addrbase + VIA_CRDR_SDEXTCTRL);
drivers/mmc/host/via-sdmmc.c
430
writel(pm_sdhc_reg->sdcontrol_reg, addrbase + VIA_CRDR_SDCTRL);
drivers/mmc/host/via-sdmmc.c
431
writel(pm_sdhc_reg->sdcmdarg_reg, addrbase + VIA_CRDR_SDCARG);
drivers/mmc/host/via-sdmmc.c
432
writel(pm_sdhc_reg->sdbusmode_reg, addrbase + VIA_CRDR_SDBUSMODE);
drivers/mmc/host/via-sdmmc.c
433
writel(pm_sdhc_reg->sdblklen_reg, addrbase + VIA_CRDR_SDBLKLEN);
drivers/mmc/host/via-sdmmc.c
434
writel(pm_sdhc_reg->sdcurblkcnt_reg, addrbase + VIA_CRDR_SDCURBLKCNT);
drivers/mmc/host/via-sdmmc.c
435
writel(pm_sdhc_reg->sdintmask_reg, addrbase + VIA_CRDR_SDINTMASK);
drivers/mmc/host/via-sdmmc.c
436
writel(pm_sdhc_reg->sdstatus_reg, addrbase + VIA_CRDR_SDSTATUS);
drivers/mmc/host/via-sdmmc.c
437
writel(pm_sdhc_reg->sdrsptmo_reg, addrbase + VIA_CRDR_SDRSPTMO);
drivers/mmc/host/via-sdmmc.c
438
writel(pm_sdhc_reg->sdclksel_reg, addrbase + VIA_CRDR_SDCLKSEL);
drivers/mmc/host/via-sdmmc.c
439
writel(pm_sdhc_reg->sdextctrl_reg, addrbase + VIA_CRDR_SDEXTCTRL);
drivers/mmc/host/via-sdmmc.c
464
writel(dmaaddr, addrbase + VIA_CRDR_DMABASEADD);
drivers/mmc/host/via-sdmmc.c
465
writel(count, addrbase + VIA_CRDR_DMACOUNTER);
drivers/mmc/host/via-sdmmc.c
466
writel(ctrl_data, addrbase + VIA_CRDR_DMACTRL);
drivers/mmc/host/via-sdmmc.c
467
writel(0x01, addrbase + VIA_CRDR_DMASTART);
drivers/mmc/host/via-sdmmc.c
507
writel(blk_reg, addrbase + VIA_CRDR_SDBLKLEN);
drivers/mmc/host/via-sdmmc.c
622
writel(cmd->arg, addrbase + VIA_CRDR_SDCARG);
drivers/mmc/host/via-sdmmc.c
623
writel(cmdctrl, addrbase + VIA_CRDR_SDCTRL);
drivers/mmc/host/via-sdmmc.c
751
writel(org_data, addrbase + VIA_CRDR_SDBUSMODE);
drivers/mmc/host/via-sdmmc.c
752
writel(sdextctrl, addrbase + VIA_CRDR_SDEXTCTRL);
drivers/mmc/host/via-sdmmc.c
950
writel(VIA_CRDR_DMACTRL_SFTRST,
drivers/mmc/host/via-sdmmc.c
995
writel(VIA_CRDR_DMACTRL_SFTRST, addrbase + VIA_CRDR_DMACTRL);
drivers/mmc/host/wmt-sdmmc.c
263
writel(arg, priv->sdmmc_base + SDMMC_ARG);
drivers/mmc/host/wmt-sdmmc.c
289
writel(DMA_ISR_INT_STS, priv->sdmmc_base + SDDMA_ISR);
drivers/mmc/host/wmt-sdmmc.c
290
writel(0, priv->sdmmc_base + SDDMA_IER);
drivers/mmc/host/wmt-sdmmc.c
506
writel(DMA_GCR_SOFT_RESET, priv->sdmmc_base + SDDMA_GCR);
drivers/mmc/host/wmt-sdmmc.c
507
writel(DMA_GCR_DMA_EN, priv->sdmmc_base + SDDMA_GCR);
drivers/mmc/host/wmt-sdmmc.c
532
writel(DMA_IER_INT_EN, priv->sdmmc_base + SDDMA_IER);
drivers/mmc/host/wmt-sdmmc.c
535
writel(descaddr, priv->sdmmc_base + SDDMA_DESPR);
drivers/mmc/host/wmt-sdmmc.c
537
writel(0x00, priv->sdmmc_base + SDDMA_CCR);
drivers/mmc/host/wmt-sdmmc.c
541
writel(reg_tmp & DMA_CCR_IF_TO_PERIPHERAL, priv->sdmmc_base +
drivers/mmc/host/wmt-sdmmc.c
545
writel(reg_tmp | DMA_CCR_PERIPHERAL_TO_IF, priv->sdmmc_base +
drivers/mmc/host/wmt-sdmmc.c
555
writel(reg_tmp | DMA_CCR_RUN, priv->sdmmc_base + SDDMA_CCR);
drivers/mmc/host/wmt-sdmmc.c
891
writel(reg_tmp | BM_SOFT_RESET, priv->sdmmc_base + SDMMC_BUSMODE);
drivers/mtd/devices/spear_smi.c
231
writel(ctrlreg1 & ~(SW_MODE | WB_MODE), dev->io_base + SMI_CR1);
drivers/mtd/devices/spear_smi.c
234
writel((bank << BANK_SHIFT) | RD_STATUS_REG | TFIE,
drivers/mtd/devices/spear_smi.c
248
writel(ctrlreg1, dev->io_base + SMI_CR1);
drivers/mtd/devices/spear_smi.c
249
writel(0, dev->io_base + SMI_CR2);
drivers/mtd/devices/spear_smi.c
307
writel(0, dev->io_base + SMI_SR);
drivers/mtd/devices/spear_smi.c
343
writel(0, dev->io_base + SMI_SR);
drivers/mtd/devices/spear_smi.c
345
writel(val, dev->io_base + SMI_CR1);
drivers/mtd/devices/spear_smi.c
389
writel(ctrlreg1 & ~SW_MODE, dev->io_base + SMI_CR1);
drivers/mtd/devices/spear_smi.c
392
writel((bank << BANK_SHIFT) | WE | TFIE, dev->io_base + SMI_CR2);
drivers/mtd/devices/spear_smi.c
398
writel(ctrlreg1, dev->io_base + SMI_CR1);
drivers/mtd/devices/spear_smi.c
399
writel(0, dev->io_base + SMI_CR2);
drivers/mtd/devices/spear_smi.c
461
writel((ctrlreg1 | SW_MODE) & ~WB_MODE, dev->io_base + SMI_CR1);
drivers/mtd/devices/spear_smi.c
464
writel(command, dev->io_base + SMI_TR);
drivers/mtd/devices/spear_smi.c
466
writel((bank << BANK_SHIFT) | SEND | TFIE | (bytes << TX_LEN_SHIFT),
drivers/mtd/devices/spear_smi.c
479
writel(ctrlreg1, dev->io_base + SMI_CR1);
drivers/mtd/devices/spear_smi.c
480
writel(0, dev->io_base + SMI_CR2);
drivers/mtd/devices/spear_smi.c
581
writel(val, dev->io_base + SMI_CR1);
drivers/mtd/devices/spear_smi.c
586
writel(ctrlreg1, dev->io_base + SMI_CR1);
drivers/mtd/devices/spear_smi.c
635
writel((ctrlreg1 | WB_MODE) & ~SW_MODE, dev->io_base + SMI_CR1);
drivers/mtd/devices/spear_smi.c
655
writel(ctrlreg1, dev->io_base + SMI_CR1);
drivers/mtd/devices/spear_smi.c
759
writel(val | SW_MODE, dev->io_base + SMI_CR1);
drivers/mtd/devices/spear_smi.c
762
writel(OPCODE_RDID, dev->io_base + SMI_TR);
drivers/mtd/devices/spear_smi.c
766
writel(val, dev->io_base + SMI_CR2);
drivers/mtd/devices/spear_smi.c
784
writel(val & ~SW_MODE, dev->io_base + SMI_CR1);
drivers/mtd/devices/st_spi_fsm.c
1620
writel(0x00040000, fsm->base + SPI_FAST_SEQ_CFG);
drivers/mtd/devices/st_spi_fsm.c
1891
writel(mode, fsm->base + SPI_MODESELECT);
drivers/mtd/devices/st_spi_fsm.c
1929
writel(clk_div, fsm->base + SPI_CLOCKDIV);
drivers/mtd/devices/st_spi_fsm.c
1937
writel(SEQ_CFG_SWRESET, fsm->base + SPI_FAST_SEQ_CFG);
drivers/mtd/devices/st_spi_fsm.c
1939
writel(0, fsm->base + SPI_FAST_SEQ_CFG);
drivers/mtd/devices/st_spi_fsm.c
1950
writel(SPI_CFG_DEVICE_ST |
drivers/mtd/devices/st_spi_fsm.c
1955
writel(STFSM_DEFAULT_WR_TIME, fsm->base + SPI_STATUS_WR_TIME_REG);
drivers/mtd/devices/st_spi_fsm.c
1962
writel(0x00000001, fsm->base + SPI_PROGRAM_ERASE_TIME);
drivers/mtd/devices/st_spi_fsm.c
722
writel(*src, dst);
drivers/mtd/devices/st_spi_fsm.c
903
writel(seq->seq_cfg, fsm->base + SPI_FAST_SEQ_CFG);
drivers/mtd/maps/pci.c
133
writel(0x00000008, map->base + 0x1558);
drivers/mtd/maps/pci.c
134
writel(0x00000000, map->base + 0x1550);
drivers/mtd/maps/pci.c
136
writel(0x00000007, map->base + 0x1558);
drivers/mtd/maps/pci.c
137
writel(0x00800000, map->base + 0x1550);
drivers/mtd/maps/pci.c
68
writel(val.x[0], map->base + map->translate(map, ofs));
drivers/mtd/maps/physmap-versatile.c
108
writel(INTEGRATOR_EBI_LOCK_VAL, ebi_base + INTEGRATOR_EBI_LOCK_OFFSET);
drivers/mtd/maps/physmap-versatile.c
113
writel(val, ebi_base + INTEGRATOR_EBI_CSR1_OFFSET);
drivers/mtd/maps/physmap-versatile.c
116
writel(0, ebi_base + INTEGRATOR_EBI_LOCK_OFFSET);
drivers/mtd/maps/sc520cdp.c
196
writel(par_table[i].new_par, &mmcr[SC520_PAR(j)]);
drivers/mtd/nand/ecc-mtk.c
197
writel(reg, ecc->regs + ECC_ENCCNFG);
drivers/mtd/nand/ecc-mtk.c
200
writel(lower_32_bits(config->addr),
drivers/mtd/nand/ecc-mtk.c
211
writel(reg, ecc->regs + ECC_DECCNFG);
drivers/mtd/nand/ecc-mtk.c
261
writel(ECC_OP_DISABLE, ecc->regs + ECC_DECCON);
drivers/mtd/nand/ecc-mxic.c
180
writel(reg, mxic->regs + DP_CONFIG);
drivers/mtd/nand/ecc-mxic.c
189
writel(reg, mxic->regs + DP_CONFIG);
drivers/mtd/nand/ecc-mxic.c
194
writel(0, mxic->regs + INTRPT_SIG_EN);
drivers/mtd/nand/ecc-mxic.c
199
writel(TRANS_CMPLT, mxic->regs + INTRPT_SIG_EN);
drivers/mtd/nand/ecc-mxic.c
214
writel(sts, mxic->regs + INTRPT_STS);
drivers/mtd/nand/ecc-mxic.c
248
writel(TRANS_CMPLT | SDMA_MAIN | SDMA_SPARE | ECC_ERR |
drivers/mtd/nand/ecc-mxic.c
298
writel(ECC_TYP(idx), mxic->regs + DP_CONFIG);
drivers/mtd/nand/ecc-mxic.c
373
writel(1, mxic->regs + CHUNK_CNT);
drivers/mtd/nand/ecc-mxic.c
374
writel(BURST_TYP_INCREASING | ECC_PACKED | MEM2MEM,
drivers/mtd/nand/ecc-mxic.c
400
writel(ctx->steps, mxic->regs + CHUNK_CNT);
drivers/mtd/nand/ecc-mxic.c
406
writel(BURST_TYP_INCREASING | ECC_PACKED | MAPPING,
drivers/mtd/nand/ecc-mxic.c
437
writel(val, mxic->regs + INTRPT_STS);
drivers/mtd/nand/ecc-mxic.c
458
writel(SDMA_STRT | dir, mxic->regs + SDMA_CTRL);
drivers/mtd/nand/ecc-mxic.c
474
writel(dirmap, mxic->regs + HC_SLV_ADDR);
drivers/mtd/nand/ecc-mxic.c
583
writel(sg_dma_address(&ctx->sg[0]) + (step * ctx->data_step_sz),
drivers/mtd/nand/ecc-mxic.c
585
writel(sg_dma_address(&ctx->sg[1]) + (step * (ctx->oob_step_sz + STAT_BYTES)),
drivers/mtd/nand/ecc-mxic.c
640
writel(sg_dma_address(&ctx->sg[0]) + (step * ctx->data_step_sz),
drivers/mtd/nand/ecc-mxic.c
642
writel(sg_dma_address(&ctx->sg[1]) + (step * (ctx->oob_step_sz + STAT_BYTES)),
drivers/mtd/nand/ecc-mxic.c
694
writel(sg_dma_address(&ctx->sg[0]), mxic->regs + SDMA_MAIN_ADDR);
drivers/mtd/nand/ecc-mxic.c
695
writel(sg_dma_address(&ctx->sg[1]), mxic->regs + SDMA_SPARE_ADDR);
drivers/mtd/nand/onenand/onenand_samsung.c
152
writel(value, onenand->base + offset);
drivers/mtd/nand/onenand/onenand_samsung.c
162
writel(value, onenand->ahb_addr + cmd);
drivers/mtd/nand/onenand/onenand_samsung.c
524
writel(src, base + S5PC110_DMA_SRC_ADDR);
drivers/mtd/nand/onenand/onenand_samsung.c
525
writel(dst, base + S5PC110_DMA_DST_ADDR);
drivers/mtd/nand/onenand/onenand_samsung.c
528
writel(S5PC110_DMA_SRC_CFG_READ, base + S5PC110_DMA_SRC_CFG);
drivers/mtd/nand/onenand/onenand_samsung.c
529
writel(S5PC110_DMA_DST_CFG_READ, base + S5PC110_DMA_DST_CFG);
drivers/mtd/nand/onenand/onenand_samsung.c
531
writel(S5PC110_DMA_SRC_CFG_WRITE, base + S5PC110_DMA_SRC_CFG);
drivers/mtd/nand/onenand/onenand_samsung.c
532
writel(S5PC110_DMA_DST_CFG_WRITE, base + S5PC110_DMA_DST_CFG);
drivers/mtd/nand/onenand/onenand_samsung.c
535
writel(count, base + S5PC110_DMA_TRANS_SIZE);
drivers/mtd/nand/onenand/onenand_samsung.c
536
writel(direction, base + S5PC110_DMA_TRANS_DIR);
drivers/mtd/nand/onenand/onenand_samsung.c
538
writel(S5PC110_DMA_TRANS_CMD_TR, base + S5PC110_DMA_TRANS_CMD);
drivers/mtd/nand/onenand/onenand_samsung.c
550
writel(S5PC110_DMA_TRANS_CMD_TEC,
drivers/mtd/nand/onenand/onenand_samsung.c
557
writel(S5PC110_DMA_TRANS_CMD_TDC, base + S5PC110_DMA_TRANS_CMD);
drivers/mtd/nand/onenand/onenand_samsung.c
575
writel(cmd, base + S5PC110_DMA_TRANS_CMD);
drivers/mtd/nand/onenand/onenand_samsung.c
576
writel(status, base + S5PC110_INTC_DMA_CLR);
drivers/mtd/nand/onenand/onenand_samsung.c
592
writel(status, base + S5PC110_INTC_DMA_MASK);
drivers/mtd/nand/onenand/onenand_samsung.c
595
writel(src, base + S5PC110_DMA_SRC_ADDR);
drivers/mtd/nand/onenand/onenand_samsung.c
596
writel(dst, base + S5PC110_DMA_DST_ADDR);
drivers/mtd/nand/onenand/onenand_samsung.c
599
writel(S5PC110_DMA_SRC_CFG_READ, base + S5PC110_DMA_SRC_CFG);
drivers/mtd/nand/onenand/onenand_samsung.c
600
writel(S5PC110_DMA_DST_CFG_READ, base + S5PC110_DMA_DST_CFG);
drivers/mtd/nand/onenand/onenand_samsung.c
602
writel(S5PC110_DMA_SRC_CFG_WRITE, base + S5PC110_DMA_SRC_CFG);
drivers/mtd/nand/onenand/onenand_samsung.c
603
writel(S5PC110_DMA_DST_CFG_WRITE, base + S5PC110_DMA_DST_CFG);
drivers/mtd/nand/onenand/onenand_samsung.c
606
writel(count, base + S5PC110_DMA_TRANS_SIZE);
drivers/mtd/nand/onenand/onenand_samsung.c
607
writel(direction, base + S5PC110_DMA_TRANS_DIR);
drivers/mtd/nand/onenand/onenand_samsung.c
609
writel(S5PC110_DMA_TRANS_CMD_TR, base + S5PC110_DMA_TRANS_CMD);
drivers/mtd/nand/raw/atmel/pmecc.c
645
writel(PMERRLOC_DISABLE, pmecc->regs.errloc + ATMEL_PMERRLOC_ELDIS);
drivers/mtd/nand/raw/atmel/pmecc.c
657
writel(val, pmecc->regs.errloc + ATMEL_PMERRLOC_ELCFG);
drivers/mtd/nand/raw/atmel/pmecc.c
658
writel((sector_size * 8) + (degree * strength),
drivers/mtd/nand/raw/atmel/pmecc.c
760
writel(PMECC_CTRL_RST, pmecc->regs.base + ATMEL_PMECC_CTRL);
drivers/mtd/nand/raw/atmel/pmecc.c
761
writel(PMECC_CTRL_DISABLE, pmecc->regs.base + ATMEL_PMECC_CTRL);
drivers/mtd/nand/raw/atmel/pmecc.c
783
writel(cfg, pmecc->regs.base + ATMEL_PMECC_CFG);
drivers/mtd/nand/raw/atmel/pmecc.c
784
writel(user->cache.sarea, pmecc->regs.base + ATMEL_PMECC_SAREA);
drivers/mtd/nand/raw/atmel/pmecc.c
785
writel(user->cache.saddr, pmecc->regs.base + ATMEL_PMECC_SADDR);
drivers/mtd/nand/raw/atmel/pmecc.c
786
writel(user->cache.eaddr, pmecc->regs.base + ATMEL_PMECC_EADDR);
drivers/mtd/nand/raw/atmel/pmecc.c
788
writel(PMECC_CTRL_ENABLE, pmecc->regs.base + ATMEL_PMECC_CTRL);
drivers/mtd/nand/raw/atmel/pmecc.c
789
writel(PMECC_CTRL_DATA, pmecc->regs.base + ATMEL_PMECC_CTRL);
drivers/mtd/nand/raw/atmel/pmecc.c
849
writel(PMECC_CLK_133MHZ, pmecc->regs.base + ATMEL_PMECC_CLK);
drivers/mtd/nand/raw/atmel/pmecc.c
852
writel(0xffffffff, pmecc->regs.base + ATMEL_PMECC_IDR);
drivers/mtd/nand/raw/cafe_nand.c
102
#define cafe_writel(cafe, datum, addr) writel(datum, (cafe)->mmio + CAFE_##addr)
drivers/mtd/nand/raw/fsmc_nand.c
1020
writel(val, host->regs_va + FSMC_PC);
drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c
1009
writel(BM_BCH_CTRL_COMPLETE_IRQ, r->bch_regs + HW_BCH_CTRL_CLR);
drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c
173
writel(BM_GPMI_CTRL1_GPMI_MODE, r->gpmi_regs + HW_GPMI_CTRL1_CLR);
drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c
176
writel(BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY,
drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c
180
writel(BM_GPMI_CTRL1_DEV_RESET, r->gpmi_regs + HW_GPMI_CTRL1_SET);
drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c
183
writel(BM_GPMI_CTRL1_BCH_MODE, r->gpmi_regs + HW_GPMI_CTRL1_SET);
drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c
190
writel(BM_GPMI_CTRL1_DECOUPLE_CS | BM_GPMI_CTRL1_GANGED_RDYBUSY,
drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c
2605
writel(this->bch_flashlayout0,
drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c
2607
writel(this->bch_flashlayout1,
drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c
2619
writel(BM_BCH_CTRL_COMPLETE_IRQ_EN,
drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c
2646
writel(BM_BCH_CTRL_COMPLETE_IRQ_EN,
drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c
45
writel(mask, addr + MXS_CLR_ADDR);
drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c
759
writel(0, r->bch_regs + HW_BCH_LAYOUTSELECT);
drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c
90
writel(MODULE_CLKGATE, reset_addr + MXS_CLR_ADDR);
drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c
94
writel(MODULE_SFTRST, reset_addr + MXS_SET_ADDR);
drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c
954
writel(hw->timing0, gpmi_regs + HW_GPMI_TIMING0);
drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c
955
writel(hw->timing1, gpmi_regs + HW_GPMI_TIMING1);
drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c
961
writel(BM_GPMI_CTRL1_CLEAR_MASK, gpmi_regs + HW_GPMI_CTRL1_CLR);
drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c
962
writel(hw->ctrl1n, gpmi_regs + HW_GPMI_CTRL1_SET);
drivers/mtd/nand/raw/hisi504_nand.c
152
writel(value, host->iobase + reg);
drivers/mtd/nand/raw/ingenic/jz4725b_bch.c
107
writel(reg, bch->base + BCH_BHCNT);
drivers/mtd/nand/raw/ingenic/jz4725b_bch.c
115
writel(readl(bch->base + BCH_BHINT), bch->base + BCH_BHINT);
drivers/mtd/nand/raw/ingenic/jz4725b_bch.c
178
writel(reg, bch->base + BCH_BHINT);
drivers/mtd/nand/raw/ingenic/jz4725b_bch.c
64
writel(cfg, bch->base + BCH_BHCSR);
drivers/mtd/nand/raw/ingenic/jz4725b_bch.c
69
writel(cfg, bch->base + BCH_BHCCR);
drivers/mtd/nand/raw/ingenic/jz4725b_bch.c
78
writel(readl(bch->base + BCH_BHINT), bch->base + BCH_BHINT);
drivers/mtd/nand/raw/ingenic/jz4740_ecc.c
132
writel(reg, ecc->base + JZ_REG_NAND_ECC_CTRL);
drivers/mtd/nand/raw/ingenic/jz4740_ecc.c
143
writel(reg, ecc->base + JZ_REG_NAND_ECC_CTRL);
drivers/mtd/nand/raw/ingenic/jz4740_ecc.c
168
writel(0, ecc->base + JZ_REG_NAND_IRQ_STAT);
drivers/mtd/nand/raw/ingenic/jz4740_ecc.c
171
writel(reg, ecc->base + JZ_REG_NAND_ECC_CTRL);
drivers/mtd/nand/raw/ingenic/jz4740_ecc.c
50
writel(0, ecc->base + JZ_REG_NAND_IRQ_STAT);
drivers/mtd/nand/raw/ingenic/jz4740_ecc.c
62
writel(reg, ecc->base + JZ_REG_NAND_ECC_CTRL);
drivers/mtd/nand/raw/ingenic/jz4740_ecc.c
84
writel(reg, ecc->base + JZ_REG_NAND_ECC_CTRL);
drivers/mtd/nand/raw/ingenic/jz4780_bch.c
156
writel(reg, bch->base + BCH_BHINT);
drivers/mtd/nand/raw/ingenic/jz4780_bch.c
68
writel(readl(bch->base + BCH_BHINT), bch->base + BCH_BHINT);
drivers/mtd/nand/raw/ingenic/jz4780_bch.c
73
writel(reg, bch->base + BCH_BHCNT);
drivers/mtd/nand/raw/ingenic/jz4780_bch.c
80
writel(reg, bch->base + BCH_BHCR);
drivers/mtd/nand/raw/ingenic/jz4780_bch.c
85
writel(readl(bch->base + BCH_BHINT), bch->base + BCH_BHINT);
drivers/mtd/nand/raw/ingenic/jz4780_bch.c
86
writel(BCH_BHCR_BCHE, bch->base + BCH_BHCCR);
drivers/mtd/nand/raw/ingenic/jz4780_bch.c
99
writel(*src32++, bch->base + BCH_BHDR);
drivers/mtd/nand/raw/intel-nand-controller.c
182
writel(0, ebu_host->ebu + EBU_CON);
drivers/mtd/nand/raw/intel-nand-controller.c
191
writel(EBU_CON_NANDM_EN | EBU_CON_CSMUX_E_EN | EBU_CON_CS_P_LOW |
drivers/mtd/nand/raw/intel-nand-controller.c
231
writel(reg, ctrl->ebu + EBU_BUSCON(ctrl->cs_num));
drivers/mtd/nand/raw/intel-nand-controller.c
361
writel(val, ebu_host->hsnand + HSNAND_CTL1);
drivers/mtd/nand/raw/intel-nand-controller.c
363
writel(val, ebu_host->hsnand + HSNAND_CTL2);
drivers/mtd/nand/raw/intel-nand-controller.c
365
writel(ebu_host->nd_para0, ebu_host->hsnand + HSNAND_PARA0);
drivers/mtd/nand/raw/intel-nand-controller.c
368
writel(0xFFFFFFFF, ebu_host->hsnand + HSNAND_CMSG_0);
drivers/mtd/nand/raw/intel-nand-controller.c
369
writel(0xFFFFFFFF, ebu_host->hsnand + HSNAND_CMSG_1);
drivers/mtd/nand/raw/intel-nand-controller.c
371
writel(HSNAND_INT_MSK_CTL_WR_C,
drivers/mtd/nand/raw/intel-nand-controller.c
379
writel(HSNAND_CTL_MSG_EN | HSNAND_CTL_CKFF_EN |
drivers/mtd/nand/raw/intel-nand-controller.c
403
writel(reg_data, ebu_host->hsnand + HSNAND_CTL);
drivers/mtd/nand/raw/intel-nand-controller.c
425
writel(reg, ebu_host->hsnand + HSNAND_CMSG_0);
drivers/mtd/nand/raw/intel-nand-controller.c
428
writel(reg, ebu_host->hsnand + HSNAND_CMSG_1);
drivers/mtd/nand/raw/intel-nand-controller.c
438
writel(reg_data, ebu_host->hsnand + HSNAND_CTL);
drivers/mtd/nand/raw/intel-nand-controller.c
668
writel(ebu_host->cs[cs].addr_sel | EBU_ADDR_MASK(5) | EBU_ADDR_SEL_REGEN,
drivers/mtd/nand/raw/loongson-nand-controller.c
345
writel(op->len, host->reg_base + LOONGSON_NAND_OP_NUM);
drivers/mtd/nand/raw/loongson-nand-controller.c
366
writel(op->cmd_reg, host->reg_base + LOONGSON_NAND_CMD);
drivers/mtd/nand/raw/loongson-nand-controller.c
783
writel(val, regs);
drivers/mtd/nand/raw/lpc32xx_mlc.c
236
writel(MLCCMD_RESET, MLC_CMD(host->io_base));
drivers/mtd/nand/raw/lpc32xx_mlc.c
250
writel(tmp, MLC_ICR(host->io_base));
drivers/mtd/nand/raw/lpc32xx_mlc.c
265
writel(tmp, MLC_TIME_REG(host->io_base));
drivers/mtd/nand/raw/lpc32xx_mlc.c
272
writel(MLCCEH_NORMAL, MLC_CEH(host->io_base));
drivers/mtd/nand/raw/lpc32xx_mlc.c
285
writel(cmd, MLC_CMD(host->io_base));
drivers/mtd/nand/raw/lpc32xx_mlc.c
287
writel(cmd, MLC_ADDR(host->io_base));
drivers/mtd/nand/raw/lpc32xx_mlc.c
530
writel(*((uint32_t *)(buf)),
drivers/mtd/nand/raw/lpc32xx_mlc.c
535
writel(*((uint32_t *)(oobbuf)), MLC_BUFF(host->io_base));
drivers/mtd/nand/raw/lpc32xx_slc.c
241
writel(SLCCTRL_SW_RESET, SLC_CTRL(host->io_base));
drivers/mtd/nand/raw/lpc32xx_slc.c
245
writel(0, SLC_CFG(host->io_base));
drivers/mtd/nand/raw/lpc32xx_slc.c
246
writel(0, SLC_IEN(host->io_base));
drivers/mtd/nand/raw/lpc32xx_slc.c
247
writel((SLCSTAT_INT_TC | SLCSTAT_INT_RDY_EN),
drivers/mtd/nand/raw/lpc32xx_slc.c
264
writel(tmp, SLC_TAC(host->io_base));
drivers/mtd/nand/raw/lpc32xx_slc.c
282
writel(tmp, SLC_CFG(host->io_base));
drivers/mtd/nand/raw/lpc32xx_slc.c
286
writel(cmd, SLC_CMD(host->io_base));
drivers/mtd/nand/raw/lpc32xx_slc.c
288
writel(cmd, SLC_ADDR(host->io_base));
drivers/mtd/nand/raw/lpc32xx_slc.c
378
writel((uint32_t)*buf++, SLC_DATA(host->io_base));
drivers/mtd/nand/raw/lpc32xx_slc.c
509
writel(readl(SLC_CFG(host->io_base)) |
drivers/mtd/nand/raw/lpc32xx_slc.c
513
writel((readl(SLC_CFG(host->io_base)) |
drivers/mtd/nand/raw/lpc32xx_slc.c
520
writel(SLCCTRL_ECC_CLEAR, SLC_CTRL(host->io_base));
drivers/mtd/nand/raw/lpc32xx_slc.c
523
writel(mtd->writesize, SLC_TC(host->io_base));
drivers/mtd/nand/raw/lpc32xx_slc.c
526
writel(readl(SLC_CTRL(host->io_base)) | SLCCTRL_DMA_START,
drivers/mtd/nand/raw/lpc32xx_slc.c
584
writel(readl(SLC_CTRL(host->io_base)) & ~SLCCTRL_DMA_START,
drivers/mtd/nand/raw/lpc32xx_slc.c
586
writel(readl(SLC_CFG(host->io_base)) &
drivers/mtd/nand/raw/lpc32xx_slc.c
962
writel(tmp, SLC_CTRL(host->io_base));
drivers/mtd/nand/raw/lpc32xx_slc.c
994
writel(tmp, SLC_CTRL(host->io_base));
drivers/mtd/nand/raw/marvell_nand.c
656
writel(nfc_op->ndcb[2], nfc->regs + NDCB0);
drivers/mtd/nand/raw/marvell_nand.c
665
writel(nfc_op->ndcb[3], nfc->regs + NDCB0);
drivers/mtd/nand/raw/meson_nand.c
1055
writel(cmd, nfc->reg_base + NFC_REG_CMD);
drivers/mtd/nand/raw/meson_nand.c
1063
writel(cmd, nfc->reg_base + NFC_REG_CMD);
drivers/mtd/nand/raw/meson_nand.c
1171
writel(CLK_ALWAYS_ON_NAND | CLK_SELECT_NAND | CLK_SELECT_FIX_PLL2,
drivers/mtd/nand/raw/meson_nand.c
1521
writel(cfg, nfc->reg_base + NFC_REG_CFG);
drivers/mtd/nand/raw/meson_nand.c
1585
writel(0, nfc->reg_base + NFC_REG_CFG);
drivers/mtd/nand/raw/meson_nand.c
288
writel(value, nfc->reg_base + NFC_REG_CFG);
drivers/mtd/nand/raw/meson_nand.c
289
writel((1 << 31), nfc->reg_base + NFC_REG_CMD);
drivers/mtd/nand/raw/meson_nand.c
296
writel(nfc->param.chip_select | NFC_CMD_IDLE | (time & 0x3ff),
drivers/mtd/nand/raw/meson_nand.c
302
writel(NFC_CMD_SEED | (0xc2 + (seed & 0x7fff)),
drivers/mtd/nand/raw/meson_nand.c
350
writel(cmd, nfc->reg_base + NFC_REG_CMD);
drivers/mtd/nand/raw/meson_nand.c
464
writel(cfg, nfc->reg_base + NFC_REG_CFG);
drivers/mtd/nand/raw/meson_nand.c
471
writel(cmd, nfc->reg_base + NFC_REG_CMD);
drivers/mtd/nand/raw/meson_nand.c
494
writel(cfg, nfc->reg_base + NFC_REG_CFG);
drivers/mtd/nand/raw/meson_nand.c
501
writel(cmd, nfc->reg_base + NFC_REG_CMD);
drivers/mtd/nand/raw/meson_nand.c
604
writel(cmd, nfc->reg_base + NFC_REG_CMD);
drivers/mtd/nand/raw/meson_nand.c
607
writel(cmd, nfc->reg_base + NFC_REG_CMD);
drivers/mtd/nand/raw/meson_nand.c
620
writel(cmd, nfc->reg_base + NFC_REG_CMD);
drivers/mtd/nand/raw/meson_nand.c
623
writel(cmd, nfc->reg_base + NFC_REG_CMD);
drivers/mtd/nand/raw/meson_nand.c
659
writel(cmd, nfc->reg_base + NFC_REG_CMD);
drivers/mtd/nand/raw/meson_nand.c
683
writel(cmd, nfc->reg_base + NFC_REG_CMD);
drivers/mtd/nand/raw/meson_nand.c
736
writel(nfc->cmdfifo.rw.cmd1, nfc->reg_base + NFC_REG_CMD);
drivers/mtd/nand/raw/meson_nand.c
775
writel(cmd, nfc->reg_base + NFC_REG_CMD);
drivers/mtd/nand/raw/mtk_nand.c
230
writel(val, nfc->regs + reg);
drivers/mtd/nand/raw/mxc_nand.c
1156
writel(NFC_V3_CONFIG1_RBA(0), NFC_V3_CONFIG1);
drivers/mtd/nand/raw/mxc_nand.c
1157
writel(NFC_V3_IPC_CREQ, NFC_V3_IPC);
drivers/mtd/nand/raw/mxc_nand.c
1160
writel(NFC_V3_WRPROT_BLS_UNLOCK | NFC_V3_WRPROT_UNLOCK,
drivers/mtd/nand/raw/mxc_nand.c
1165
writel(0xffff << 16, NFC_V3_WRPROT_UNLOCK_BLK_ADD0 + (i << 2));
drivers/mtd/nand/raw/mxc_nand.c
1167
writel(0, NFC_V3_IPC);
drivers/mtd/nand/raw/mxc_nand.c
1201
writel(config2, NFC_V3_CONFIG2);
drivers/mtd/nand/raw/mxc_nand.c
1212
writel(config3, NFC_V3_CONFIG3);
drivers/mtd/nand/raw/mxc_nand.c
1214
writel(0, NFC_V3_DELAY_LINE);
drivers/mtd/nand/raw/mxc_nand.c
295
writel(tmp, NFC_V3_IPC);
drivers/mtd/nand/raw/mxc_nand.c
339
writel(tmp, NFC_V3_CONFIG2);
drivers/mtd/nand/raw/mxc_nand.c
498
writel(cmd, NFC_V3_FLASH_CMD);
drivers/mtd/nand/raw/mxc_nand.c
501
writel(NFC_CMD, NFC_V3_LAUNCH);
drivers/mtd/nand/raw/mxc_nand.c
537
writel(addr, NFC_V3_FLASH_ADDR0);
drivers/mtd/nand/raw/mxc_nand.c
540
writel(NFC_ADDR, NFC_V3_LAUNCH);
drivers/mtd/nand/raw/mxc_nand.c
567
writel(tmp, NFC_V3_CONFIG1);
drivers/mtd/nand/raw/mxc_nand.c
570
writel(ops, NFC_V3_LAUNCH);
drivers/mtd/nand/raw/mxc_nand.c
615
writel(NFC_ID, NFC_V3_LAUNCH);
drivers/mtd/nand/raw/mxc_nand.c
666
writel(store, main_buf);
drivers/mtd/nand/raw/mxc_nand.c
704
writel(config2, NFC_V3_CONFIG2);
drivers/mtd/nand/raw/mxic_nand.c
219
writel(IDLY_CODE_VAL(0, idly_code) |
drivers/mtd/nand/raw/mxic_nand.c
224
writel(IDLY_CODE_VAL(4, idly_code) |
drivers/mtd/nand/raw/mxic_nand.c
299
writel(HC_CFG_NIO(8) | HC_CFG_TYPE(1, HC_CFG_TYPE_RAW_NAND) |
drivers/mtd/nand/raw/mxic_nand.c
302
writel(INT_STS_ALL, nfc->regs + INT_STS_EN);
drivers/mtd/nand/raw/mxic_nand.c
303
writel(INT_RDY_PIN, nfc->regs + INT_SIG_EN);
drivers/mtd/nand/raw/mxic_nand.c
304
writel(0x0, nfc->regs + ONFI_DIN_CNT(0));
drivers/mtd/nand/raw/mxic_nand.c
305
writel(0, nfc->regs + LRD_CFG);
drivers/mtd/nand/raw/mxic_nand.c
306
writel(0, nfc->regs + LRD_CTRL);
drivers/mtd/nand/raw/mxic_nand.c
307
writel(0x0, nfc->regs + HC_EN);
drivers/mtd/nand/raw/mxic_nand.c
312
writel(readl(nfc->regs + HC_CFG) | HC_CFG_MAN_CS_EN,
drivers/mtd/nand/raw/mxic_nand.c
314
writel(HC_CFG_MAN_CS_ASSERT | readl(nfc->regs + HC_CFG),
drivers/mtd/nand/raw/mxic_nand.c
320
writel(~HC_CFG_MAN_CS_ASSERT & readl(nfc->regs + HC_CFG),
drivers/mtd/nand/raw/mxic_nand.c
361
writel(data, nfc->regs + TXD(nbytes % 4));
drivers/mtd/nand/raw/mxic_nand.c
406
writel(0, nfc->regs + HC_EN);
drivers/mtd/nand/raw/mxic_nand.c
407
writel(HC_EN_BIT, nfc->regs + HC_EN);
drivers/mtd/nand/raw/mxic_nand.c
408
writel(OP_CMD_BUSW(OP_BUSW_8) | OP_DUMMY_CYC(0x3F) |
drivers/mtd/nand/raw/mxic_nand.c
417
writel(OP_ADDR_BUSW(OP_BUSW_8) | OP_DUMMY_CYC(0x3F) |
drivers/mtd/nand/raw/mxic_nand.c
426
writel(0x0, nfc->regs + ONFI_DIN_CNT(0));
drivers/mtd/nand/raw/mxic_nand.c
427
writel(OP_DATA_BUSW(OP_BUSW_8) | OP_DUMMY_CYC(0x3F) |
drivers/mtd/nand/raw/mxic_nand.c
435
writel(instr->ctx.data.len,
drivers/mtd/nand/raw/mxic_nand.c
437
writel(OP_DATA_BUSW(OP_BUSW_8) | OP_DUMMY_CYC(0x3F),
drivers/mtd/nand/raw/mxic_nand.c
476
writel(DATA_STROB_EDO_EN, nfc->regs + DATA_STROB);
drivers/mtd/nand/raw/ndfc.c
64
writel(cmd & 0xFF, ndfc->ndfcbase + NDFC_CMD);
drivers/mtd/nand/raw/ndfc.c
66
writel(cmd & 0xFF, ndfc->ndfcbase + NDFC_ALE);
drivers/mtd/nand/raw/nuvoton-ma35d1-nand-controller.c
152
writel(0xff, nand->regs + MA35_NFI_REG_NANDRA0);
drivers/mtd/nand/raw/nuvoton-ma35d1-nand-controller.c
195
writel(*buf++, nand->regs + MA35_NFI_REG_NANDRA0 + j);
drivers/mtd/nand/raw/nuvoton-ma35d1-nand-controller.c
200
writel(*ptr, nand->regs + MA35_NFI_REG_NANDRA0 + j);
drivers/mtd/nand/raw/nuvoton-ma35d1-nand-controller.c
204
writel(value, nand->regs + MA35_NFI_REG_NANDRA0 + j);
drivers/mtd/nand/raw/nuvoton-ma35d1-nand-controller.c
208
writel(value, nand->regs + MA35_NFI_REG_NANDRA0 + j);
drivers/mtd/nand/raw/nuvoton-ma35d1-nand-controller.c
223
writel(reg & ~DISABLE_CS0, nand->regs + MA35_NFI_REG_NANDCTL);
drivers/mtd/nand/raw/nuvoton-ma35d1-nand-controller.c
227
writel(reg, nand->regs + MA35_NFI_REG_NANDINTSTS);
drivers/mtd/nand/raw/nuvoton-ma35d1-nand-controller.c
246
writel(mtd->oobsize, nand->regs + MA35_NFI_REG_NANDRACTL);
drivers/mtd/nand/raw/nuvoton-ma35d1-nand-controller.c
278
writel(reg, nand->regs + MA35_NFI_REG_NANDCTL);
drivers/mtd/nand/raw/nuvoton-ma35d1-nand-controller.c
357
writel(value, nand->regs + MA35_NFI_REG_NANDRA0);
drivers/mtd/nand/raw/nuvoton-ma35d1-nand-controller.c
382
writel(value, nand->regs + MA35_NFI_REG_NANDRA0 + offset - remain);
drivers/mtd/nand/raw/nuvoton-ma35d1-nand-controller.c
424
writel(DMA_RST | DMA_EN, nand->regs + MA35_NFI_REG_DMACTL);
drivers/mtd/nand/raw/nuvoton-ma35d1-nand-controller.c
425
writel(DMA_EN, nand->regs + MA35_NFI_REG_DMACTL);
drivers/mtd/nand/raw/nuvoton-ma35d1-nand-controller.c
428
writel(INT_DMA | INT_ECC, nand->regs + MA35_NFI_REG_NANDINTSTS);
drivers/mtd/nand/raw/nuvoton-ma35d1-nand-controller.c
429
writel(INT_DMA, nand->regs + MA35_NFI_REG_NANDINTEN);
drivers/mtd/nand/raw/nuvoton-ma35d1-nand-controller.c
442
writel(addr[i], nand->regs + MA35_NFI_REG_NANDDATA);
drivers/mtd/nand/raw/nuvoton-ma35d1-nand-controller.c
451
writel(reg & 0xffff, nand->regs + MA35_NFI_REG_NANDRA0);
drivers/mtd/nand/raw/nuvoton-ma35d1-nand-controller.c
462
writel(dma_addr, nand->regs + MA35_NFI_REG_DMASA);
drivers/mtd/nand/raw/nuvoton-ma35d1-nand-controller.c
463
writel(readl(nand->regs + MA35_NFI_REG_NANDCTL) | DMA_W_EN,
drivers/mtd/nand/raw/nuvoton-ma35d1-nand-controller.c
501
writel(dma_addr, nand->regs + MA35_NFI_REG_DMASA);
drivers/mtd/nand/raw/nuvoton-ma35d1-nand-controller.c
502
writel(readl(nand->regs + MA35_NFI_REG_NANDCTL) | DMA_R_EN,
drivers/mtd/nand/raw/nuvoton-ma35d1-nand-controller.c
516
writel(DMA_RST | DMA_EN, nand->regs + MA35_NFI_REG_DMACTL);
drivers/mtd/nand/raw/nuvoton-ma35d1-nand-controller.c
517
writel(readl(nand->regs + MA35_NFI_REG_NANDCTL) | SWRST,
drivers/mtd/nand/raw/nuvoton-ma35d1-nand-controller.c
520
writel(INT_ECC, nand->regs + MA35_NFI_REG_NANDINTSTS);
drivers/mtd/nand/raw/nuvoton-ma35d1-nand-controller.c
545
writel(reg, nand->regs + MA35_NFI_REG_NANDRACTL);
drivers/mtd/nand/raw/nuvoton-ma35d1-nand-controller.c
561
writel(reg | ECC_EN, nand->regs + MA35_NFI_REG_NANDCTL);
drivers/mtd/nand/raw/nuvoton-ma35d1-nand-controller.c
585
writel(mtd->oobsize, nand->regs + MA35_NFI_REG_NANDRACTL);
drivers/mtd/nand/raw/nuvoton-ma35d1-nand-controller.c
588
writel(reg & ~ECC_EN, nand->regs + MA35_NFI_REG_NANDCTL);
drivers/mtd/nand/raw/nuvoton-ma35d1-nand-controller.c
602
writel(reg | ECC_EN, nand->regs + MA35_NFI_REG_NANDCTL);
drivers/mtd/nand/raw/nuvoton-ma35d1-nand-controller.c
619
writel(reg & ~ECC_EN, nand->regs + MA35_NFI_REG_NANDCTL);
drivers/mtd/nand/raw/nuvoton-ma35d1-nand-controller.c
634
writel(reg | ECC_EN, nand->regs + MA35_NFI_REG_NANDCTL);
drivers/mtd/nand/raw/nuvoton-ma35d1-nand-controller.c
651
writel(reg & ~ECC_EN, nand->regs + MA35_NFI_REG_NANDCTL);
drivers/mtd/nand/raw/nuvoton-ma35d1-nand-controller.c
666
writel(reg | ECC_EN, nand->regs + MA35_NFI_REG_NANDCTL);
drivers/mtd/nand/raw/nuvoton-ma35d1-nand-controller.c
683
writel(reg & ~ECC_EN, nand->regs + MA35_NFI_REG_NANDCTL);
drivers/mtd/nand/raw/nuvoton-ma35d1-nand-controller.c
712
writel(DISABLE_WP, nand->regs + MA35_NFI_REG_NANDECTL);
drivers/mtd/nand/raw/nuvoton-ma35d1-nand-controller.c
717
writel(reg, nand->regs + MA35_NFI_REG_NANDCTL);
drivers/mtd/nand/raw/nuvoton-ma35d1-nand-controller.c
727
writel(INT_DMA, nand->regs + MA35_NFI_REG_NANDINTSTS);
drivers/mtd/nand/raw/nuvoton-ma35d1-nand-controller.c
750
writel(reg | PSIZE_2K, nand->regs + MA35_NFI_REG_NANDCTL);
drivers/mtd/nand/raw/nuvoton-ma35d1-nand-controller.c
753
writel(reg | PSIZE_4K, nand->regs + MA35_NFI_REG_NANDCTL);
drivers/mtd/nand/raw/nuvoton-ma35d1-nand-controller.c
756
writel(reg | PSIZE_8K, nand->regs + MA35_NFI_REG_NANDCTL);
drivers/mtd/nand/raw/nuvoton-ma35d1-nand-controller.c
796
writel(instr->ctx.cmd.opcode, nand->regs + MA35_NFI_REG_NANDCMD);
drivers/mtd/nand/raw/nuvoton-ma35d1-nand-controller.c
801
writel(instr->ctx.addr.addrs[i] | ENDADDR,
drivers/mtd/nand/raw/nuvoton-ma35d1-nand-controller.c
804
writel(instr->ctx.addr.addrs[i],
drivers/mtd/nand/raw/nuvoton-ma35d1-nand-controller.c
991
writel(GRST | NAND_EN, nand->regs + MA35_NFI_REG_GCTL);
drivers/mtd/nand/raw/omap2.c
1000
writel(ECCCLEAR | ECC1, info->reg.gpmc_ecc_control);
drivers/mtd/nand/raw/omap2.c
218
writel(u32_count, info->reg.gpmc_prefetch_config2);
drivers/mtd/nand/raw/omap2.c
226
writel(val, info->reg.gpmc_prefetch_config1);
drivers/mtd/nand/raw/omap2.c
229
writel(0x1, info->reg.gpmc_prefetch_control);
drivers/mtd/nand/raw/omap2.c
247
writel(0x0, info->reg.gpmc_prefetch_control);
drivers/mtd/nand/raw/omap2.c
250
writel(0x0, info->reg.gpmc_prefetch_config1);
drivers/mtd/nand/raw/omap2.c
874
writel(val, info->reg.gpmc_ecc_control);
drivers/mtd/nand/raw/omap2.c
879
writel(val, info->reg.gpmc_ecc_size_config);
drivers/mtd/nand/raw/omap2.c
884
writel(ECCCLEAR | ECC1, info->reg.gpmc_ecc_control);
drivers/mtd/nand/raw/omap2.c
887
writel(ECCCLEAR, info->reg.gpmc_ecc_control);
drivers/mtd/nand/raw/omap2.c
897
writel(val, info->reg.gpmc_ecc_config);
drivers/mtd/nand/raw/omap2.c
980
writel(ECC1, info->reg.gpmc_ecc_control);
drivers/mtd/nand/raw/omap2.c
984
writel(val, info->reg.gpmc_ecc_size_config);
drivers/mtd/nand/raw/omap2.c
997
writel(val, info->reg.gpmc_ecc_config);
drivers/mtd/nand/raw/omap_elm.c
87
writel(val, info->elm_base + offset);
drivers/mtd/nand/raw/pl35x-nand-controller.c
1012
writel(PL35X_SMC_MEMC_CFG_CLR_INT_CLR_1 |
drivers/mtd/nand/raw/pl35x-nand-controller.c
1031
writel(PL35X_SMC_ECC_CMD1_WRITE(NAND_CMD_SEQIN) |
drivers/mtd/nand/raw/pl35x-nand-controller.c
1036
writel(PL35X_SMC_ECC_CMD2_WRITE_COL_CHG(NAND_CMD_RNDIN) |
drivers/mtd/nand/raw/pl35x-nand-controller.c
216
writel(PL35X_SMC_DIRECT_CMD_NAND_CS |
drivers/mtd/nand/raw/pl35x-nand-controller.c
226
writel(bw, nfc->conf_regs + PL35X_SMC_OPMODE);
drivers/mtd/nand/raw/pl35x-nand-controller.c
234
writel(PL35X_SMC_MEMC_CFG_CLR_INT_CLR_1,
drivers/mtd/nand/raw/pl35x-nand-controller.c
281
writel(ecc_cfg, nfc->conf_regs + PL35X_SMC_ECC_CFG);
drivers/mtd/nand/raw/pl35x-nand-controller.c
322
writel(plnand->timings, nfc->conf_regs + PL35X_SMC_CYCLES);
drivers/mtd/nand/raw/pl35x-nand-controller.c
326
writel(plnand->ecc_cfg, nfc->conf_regs + PL35X_SMC_ECC_CFG);
drivers/mtd/nand/raw/pl35x-nand-controller.c
383
writel(buf32[i], nfc->io_regs + data_phase_addr);
drivers/mtd/nand/raw/pl35x-nand-controller.c
534
writel(addr1, nfc->io_regs + cmd_addr);
drivers/mtd/nand/raw/pl35x-nand-controller.c
536
writel(addr2, nfc->io_regs + cmd_addr);
drivers/mtd/nand/raw/pl35x-nand-controller.c
626
writel(addr1, nfc->io_regs + cmd_addr);
drivers/mtd/nand/raw/pl35x-nand-controller.c
628
writel(addr2, nfc->io_regs + cmd_addr);
drivers/mtd/nand/raw/pl35x-nand-controller.c
722
writel(addr1, nfc->io_regs + cmd_addr);
drivers/mtd/nand/raw/pl35x-nand-controller.c
724
writel(addr2, nfc->io_regs + cmd_addr);
drivers/mtd/nand/raw/pl35x-nand-controller.c
865
writel(plnand->timings, nfc->conf_regs + PL35X_SMC_CYCLES);
drivers/mtd/nand/raw/pl35x-nand-controller.c
896
writel(plnand->ecc_cfg, nfc->conf_regs + PL35X_SMC_ECC_CFG);
drivers/mtd/nand/raw/r852.c
59
writel(cpu_to_le32(value), dev->mmio + address);
drivers/mtd/nand/raw/renesas-nand-controller.c
432
writel(dma_addr, rnandc->regs + DMA_ADDR_LOW_REG);
drivers/mtd/nand/raw/renesas-nand-controller.c
433
writel(mtd->writesize, rnandc->regs + DMA_CNT_REG);
drivers/mtd/nand/raw/renesas-nand-controller.c
434
writel(DMA_TLVL_MAX, rnandc->regs + DMA_TLVL_REG);
drivers/mtd/nand/raw/renesas-nand-controller.c
615
writel(dma_addr, rnandc->regs + DMA_ADDR_LOW_REG);
drivers/mtd/nand/raw/renesas-nand-controller.c
616
writel(mtd->writesize, rnandc->regs + DMA_CNT_REG);
drivers/mtd/nand/raw/renesas-nand-controller.c
617
writel(DMA_TLVL_MAX, rnandc->regs + DMA_TLVL_REG);
drivers/mtd/nand/raw/rockchip-nand-controller.c
1426
writel(0, nfc->regs + nfc->cfg->int_en_off);
drivers/mtd/nand/raw/rockchip-nand-controller.c
253
writel(reg, nfc->regs + nfc->cfg->bchctl_off);
drivers/mtd/nand/raw/rockchip-nand-controller.c
273
writel(val, nfc->regs + NFC_FMCTL);
drivers/mtd/nand/raw/rockchip-nand-controller.c
284
writel(val, nfc->regs + NFC_FMCTL);
drivers/mtd/nand/raw/rockchip-nand-controller.c
291
writel(rknand->timing, nfc->regs + NFC_FMWAIT);
drivers/mtd/nand/raw/rockchip-nand-controller.c
483
writel(bch_reg, nfc->regs + nfc->cfg->bchctl_off);
drivers/mtd/nand/raw/rockchip-nand-controller.c
486
writel(dma_reg, nfc->regs + nfc->cfg->dma_cfg_off);
drivers/mtd/nand/raw/rockchip-nand-controller.c
487
writel((u32)dma_data, nfc->regs + nfc->cfg->dma_data_buf_off);
drivers/mtd/nand/raw/rockchip-nand-controller.c
488
writel((u32)dma_oob, nfc->regs + nfc->cfg->dma_oob_buf_off);
drivers/mtd/nand/raw/rockchip-nand-controller.c
489
writel(fl_reg, nfc->regs + nfc->cfg->flctl_off);
drivers/mtd/nand/raw/rockchip-nand-controller.c
491
writel(fl_reg, nfc->regs + nfc->cfg->flctl_off);
drivers/mtd/nand/raw/rockchip-nand-controller.c
671
writel(INT_DMA, nfc->regs + nfc->cfg->int_en_off);
drivers/mtd/nand/raw/rockchip-nand-controller.c
807
writel(INT_DMA, nfc->regs + nfc->cfg->int_en_off);
drivers/mtd/nand/raw/rockchip-nand-controller.c
893
writel(FMCTL_WP, nfc->regs + NFC_FMCTL);
drivers/mtd/nand/raw/rockchip-nand-controller.c
895
writel(0x1081, nfc->regs + NFC_FMWAIT);
drivers/mtd/nand/raw/rockchip-nand-controller.c
898
writel(0, nfc->regs + nfc->cfg->randmz_off);
drivers/mtd/nand/raw/rockchip-nand-controller.c
899
writel(0, nfc->regs + nfc->cfg->dma_cfg_off);
drivers/mtd/nand/raw/rockchip-nand-controller.c
900
writel(FLCTL_RST, nfc->regs + nfc->cfg->flctl_off);
drivers/mtd/nand/raw/rockchip-nand-controller.c
914
writel(sta, nfc->regs + nfc->cfg->int_clr_off);
drivers/mtd/nand/raw/rockchip-nand-controller.c
915
writel(~sta & ien, nfc->regs + nfc->cfg->int_en_off);
drivers/mtd/nand/raw/sh_flctl.c
1064
writel(flctl->flintdmacr_base, FLINTDMACR(flctl));
drivers/mtd/nand/raw/sh_flctl.c
116
writel(flctl->flintdmacr_base | AC1CLR | AC0CLR, FLINTDMACR(flctl));
drivers/mtd/nand/raw/sh_flctl.c
117
writel(flctl->flintdmacr_base, FLINTDMACR(flctl));
drivers/mtd/nand/raw/sh_flctl.c
241
writel(addr2, FLADR2(flctl));
drivers/mtd/nand/raw/sh_flctl.c
250
writel(addr, FLADR(flctl));
drivers/mtd/nand/raw/sh_flctl.c
329
writel(0, FL4ECCCR(flctl));
drivers/mtd/nand/raw/sh_flctl.c
355
writel(0, FL4ECCCR(flctl));
drivers/mtd/nand/raw/sh_flctl.c
406
writel(reg, FLINTDMACR(flctl));
drivers/mtd/nand/raw/sh_flctl.c
441
writel(reg, FLINTDMACR(flctl));
drivers/mtd/nand/raw/sh_flctl.c
511
writel(cpu_to_be32(buf[i]), FLDTFIFO(flctl));
drivers/mtd/nand/raw/sh_flctl.c
534
writel(buf[i], FLECFIFO(flctl));
drivers/mtd/nand/raw/sh_flctl.c
595
writel(flcmncr_val, FLCMNCR(flctl));
drivers/mtd/nand/raw/sh_flctl.c
596
writel(flcmdcr_val, FLCMDCR(flctl));
drivers/mtd/nand/raw/sh_flctl.c
597
writel(flcmcdr_val, FLCMCDR(flctl));
drivers/mtd/nand/raw/sh_flctl.c
632
writel(readl(FLCMNCR(flctl)) | ACM_SACCES_MODE | _4ECCCORRECT,
drivers/mtd/nand/raw/sh_flctl.c
634
writel(readl(FLCMDCR(flctl)) | page_sectors, FLCMDCR(flctl));
drivers/mtd/nand/raw/sh_flctl.c
635
writel(page_addr << 2, FLADR(flctl));
drivers/mtd/nand/raw/sh_flctl.c
666
writel(readl(FLCMNCR(flctl)) & ~(ACM_SACCES_MODE | _4ECCCORRECT),
drivers/mtd/nand/raw/sh_flctl.c
683
writel(16, FLDTCNTR(flctl));
drivers/mtd/nand/raw/sh_flctl.c
703
writel(readl(FLCMNCR(flctl)) | ACM_SACCES_MODE, FLCMNCR(flctl));
drivers/mtd/nand/raw/sh_flctl.c
704
writel(readl(FLCMDCR(flctl)) | page_sectors, FLCMDCR(flctl));
drivers/mtd/nand/raw/sh_flctl.c
705
writel(page_addr << 2, FLADR(flctl));
drivers/mtd/nand/raw/sh_flctl.c
714
writel(readl(FLCMNCR(flctl)) & ~ACM_SACCES_MODE, FLCMNCR(flctl));
drivers/mtd/nand/raw/sh_flctl.c
731
writel(16, FLDTCNTR(flctl)); /* set read size */
drivers/mtd/nand/raw/sh_flctl.c
816
writel(flctl->read_bytes, FLDTCNTR(flctl)); /* set read size */
drivers/mtd/nand/raw/sh_flctl.c
859
writel(0, FLDTCNTR(flctl)); /* set 0 size */
drivers/mtd/nand/raw/sh_flctl.c
875
writel(flctl->index, FLDTCNTR(flctl)); /* set write size */
drivers/mtd/nand/raw/sh_flctl.c
886
writel(flctl->read_bytes, FLDTCNTR(flctl)); /* set read size */
drivers/mtd/nand/raw/sh_flctl.c
895
writel(0, FLDTCNTR(flctl)); /* set 0 size */
drivers/mtd/nand/raw/sh_flctl.c
906
writel(flctl->read_bytes, FLDTCNTR(flctl)); /* set read size */
drivers/mtd/nand/raw/sh_flctl.c
926
writel(flctl->flcmncr_base, FLCMNCR(flctl));
drivers/mtd/nand/raw/sh_flctl.c
951
writel(HOLDEN, FLHOLDCR(flctl));
drivers/mtd/nand/raw/sunxi_nand.c
1093
writel((NAND_CMD_RNDOUTSTART << 16) | (NAND_CMD_RNDOUT << 8) |
drivers/mtd/nand/raw/sunxi_nand.c
1103
writel(NFC_PAGE_OP | NFC_DATA_SWAP_METHOD | NFC_DATA_TRANS,
drivers/mtd/nand/raw/sunxi_nand.c
1226
writel(NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD |
drivers/mtd/nand/raw/sunxi_nand.c
1482
writel((NAND_CMD_RNDIN << 8) | NAND_CMD_PAGEPROG,
drivers/mtd/nand/raw/sunxi_nand.c
1492
writel(NFC_PAGE_OP | NFC_DATA_SWAP_METHOD |
drivers/mtd/nand/raw/sunxi_nand.c
2012
writel(addrs[0], nfc->regs + NFC_REG_ADDR_LOW);
drivers/mtd/nand/raw/sunxi_nand.c
2013
writel(addrs[1], nfc->regs + NFC_REG_ADDR_HIGH);
drivers/mtd/nand/raw/sunxi_nand.c
2017
writel(extcmd,
drivers/mtd/nand/raw/sunxi_nand.c
2023
writel(cnt, nfc->regs + NFC_REG_CNT);
drivers/mtd/nand/raw/sunxi_nand.c
2025
writel(cmd, nfc->regs + NFC_REG_CMD);
drivers/mtd/nand/raw/sunxi_nand.c
2320
writel(0, nfc->regs + NFC_REG_INT);
drivers/mtd/nand/raw/sunxi_nand.c
381
writel(st & NFC_INT_MASK, nfc->regs + NFC_REG_ST);
drivers/mtd/nand/raw/sunxi_nand.c
382
writel(~st & ien & NFC_INT_MASK, nfc->regs + NFC_REG_INT);
drivers/mtd/nand/raw/sunxi_nand.c
401
writel(events, nfc->regs + NFC_REG_INT);
drivers/mtd/nand/raw/sunxi_nand.c
410
writel(0, nfc->regs + NFC_REG_INT);
drivers/mtd/nand/raw/sunxi_nand.c
419
writel(events & NFC_INT_MASK, nfc->regs + NFC_REG_ST);
drivers/mtd/nand/raw/sunxi_nand.c
446
writel(0, nfc->regs + NFC_REG_ECC_CTL);
drivers/mtd/nand/raw/sunxi_nand.c
447
writel(NFC_RESET, nfc->regs + NFC_REG_CTL);
drivers/mtd/nand/raw/sunxi_nand.c
486
writel(readl(nfc->regs + NFC_REG_CTL) | NFC_RAM_METHOD,
drivers/mtd/nand/raw/sunxi_nand.c
488
writel(nchunks, nfc->regs + NFC_REG_SECTOR_NUM);
drivers/mtd/nand/raw/sunxi_nand.c
489
writel(chunksize, nfc->regs + NFC_REG_CNT);
drivers/mtd/nand/raw/sunxi_nand.c
492
writel(readl(nfc->regs + NFC_REG_CTL) & ~NFC_DMA_TYPE_NORMAL,
drivers/mtd/nand/raw/sunxi_nand.c
494
writel(chunksize * nchunks, nfc->regs + NFC_REG_MDMA_CNT);
drivers/mtd/nand/raw/sunxi_nand.c
495
writel(sg_dma_address(sg), nfc->regs + NFC_REG_MDMA_ADDR);
drivers/mtd/nand/raw/sunxi_nand.c
507
writel(readl(nfc->regs + NFC_REG_CTL) & ~NFC_RAM_METHOD,
drivers/mtd/nand/raw/sunxi_nand.c
520
writel(readl(nfc->regs + NFC_REG_CTL) & ~NFC_RAM_METHOD,
drivers/mtd/nand/raw/sunxi_nand.c
543
writel(mtd->writesize, nfc->regs + NFC_REG_SPARE_AREA(nfc));
drivers/mtd/nand/raw/sunxi_nand.c
550
writel(sunxi_nand->timing_ctl, nfc->regs + NFC_REG_TIMING_CTL);
drivers/mtd/nand/raw/sunxi_nand.c
551
writel(sunxi_nand->timing_cfg, nfc->regs + NFC_REG_TIMING_CFG);
drivers/mtd/nand/raw/sunxi_nand.c
552
writel(ctl, nfc->regs + NFC_REG_CTL);
drivers/mtd/nand/raw/sunxi_nand.c
573
writel(cnt, nfc->regs + NFC_REG_CNT);
drivers/mtd/nand/raw/sunxi_nand.c
575
writel(tmp, nfc->regs + NFC_REG_CMD);
drivers/mtd/nand/raw/sunxi_nand.c
611
writel(cnt, nfc->regs + NFC_REG_CNT);
drivers/mtd/nand/raw/sunxi_nand.c
615
writel(tmp, nfc->regs + NFC_REG_CMD);
drivers/mtd/nand/raw/sunxi_nand.c
743
writel(ecc_ctl | NFC_RANDOM_SEED(state), nfc->regs + NFC_REG_ECC_CTL);
drivers/mtd/nand/raw/sunxi_nand.c
753
writel(readl(nfc->regs + NFC_REG_ECC_CTL) | NFC_RANDOM_EN(nfc),
drivers/mtd/nand/raw/sunxi_nand.c
764
writel(readl(nfc->regs + NFC_REG_ECC_CTL) & ~NFC_RANDOM_EN(nfc),
drivers/mtd/nand/raw/sunxi_nand.c
800
writel(sunxi_nand->ecc.ecc_ctl, nfc->regs + NFC_REG_ECC_CTL);
drivers/mtd/nand/raw/sunxi_nand.c
807
writel(0, nfc->regs + NFC_REG_ECC_CTL);
drivers/mtd/nand/raw/sunxi_nand.c
848
writel(0, nfc->regs + NFC_REG_USER_DATA_LEN(nfc, i));
drivers/mtd/nand/raw/sunxi_nand.c
879
writel(val, nfc->regs + NFC_REG_USER_DATA_LEN(nfc, step));
drivers/mtd/nand/raw/sunxi_nand.c
896
writel(sunxi_nfc_buf_to_user_data(oob),
drivers/mtd/nand/raw/sunxi_nand.c
980
writel(NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD | NFC_ECC_OP,
drivers/mtd/nand/raw/vf610_nfc.c
181
writel(val, nfc->regs + reg);
drivers/mtd/spi-nor/controllers/hisi-sfc.c
144
writel(reg, host->regbase + FMC_SPI_TIMING_CFG);
drivers/mtd/spi-nor/controllers/hisi-sfc.c
187
writel(reg, host->regbase + FMC_CMD);
drivers/mtd/spi-nor/controllers/hisi-sfc.c
190
writel(reg, host->regbase + FMC_DATA_NUM);
drivers/mtd/spi-nor/controllers/hisi-sfc.c
193
writel(reg, host->regbase + FMC_OP_CFG);
drivers/mtd/spi-nor/controllers/hisi-sfc.c
195
writel(0xff, host->regbase + FMC_INT_CLR);
drivers/mtd/spi-nor/controllers/hisi-sfc.c
197
writel(reg, host->regbase + FMC_OP);
drivers/mtd/spi-nor/controllers/hisi-sfc.c
242
writel(reg, host->regbase + FMC_CFG);
drivers/mtd/spi-nor/controllers/hisi-sfc.c
244
writel(start_off, host->regbase + FMC_ADDRL);
drivers/mtd/spi-nor/controllers/hisi-sfc.c
245
writel(dma_buf, host->regbase + FMC_DMA_SADDR_D0);
drivers/mtd/spi-nor/controllers/hisi-sfc.c
246
writel(FMC_DMA_LEN_SET(len), host->regbase + FMC_DMA_LEN);
drivers/mtd/spi-nor/controllers/hisi-sfc.c
256
writel(reg, host->regbase + FMC_OP_CFG);
drivers/mtd/spi-nor/controllers/hisi-sfc.c
258
writel(0xff, host->regbase + FMC_INT_CLR);
drivers/mtd/spi-nor/controllers/hisi-sfc.c
263
writel(reg, host->regbase + FMC_OP_DMA);
drivers/mtd/spi-nor/controllers/nxp-spifi.c
114
writel(spifi->mcmd, spifi->io_base + SPIFI_MCMD);
drivers/mtd/spi-nor/controllers/nxp-spifi.c
140
writel(cmd, spifi->io_base + SPIFI_CMD);
drivers/mtd/spi-nor/controllers/nxp-spifi.c
164
writel(cmd, spifi->io_base + SPIFI_CMD);
drivers/mtd/spi-nor/controllers/nxp-spifi.c
199
writel(to, spifi->io_base + SPIFI_ADDR);
drivers/mtd/spi-nor/controllers/nxp-spifi.c
206
writel(cmd, spifi->io_base + SPIFI_CMD);
drivers/mtd/spi-nor/controllers/nxp-spifi.c
228
writel(offs, spifi->io_base + SPIFI_ADDR);
drivers/mtd/spi-nor/controllers/nxp-spifi.c
233
writel(cmd, spifi->io_base + SPIFI_CMD);
drivers/mtd/spi-nor/controllers/nxp-spifi.c
340
writel(ctrl, spifi->io_base + SPIFI_CTRL);
drivers/mtd/spi-nor/controllers/nxp-spifi.c
414
writel(0, spifi->io_base + SPIFI_IDATA);
drivers/mtd/spi-nor/controllers/nxp-spifi.c
415
writel(0, spifi->io_base + SPIFI_MCMD);
drivers/mtd/spi-nor/controllers/nxp-spifi.c
81
writel(SPIFI_STAT_RESET, spifi->io_base + SPIFI_STAT);
drivers/net/can/bxcan.c
205
writel(val, addr);
drivers/net/can/bxcan.c
408
writel(rf0r, ®s->rf0r);
drivers/net/can/bxcan.c
453
writel(tsr, ®s->tsr);
drivers/net/can/bxcan.c
620
writel(msr, ®s->msr);
drivers/net/can/bxcan.c
867
writel(*(u32 *)(cf->data + i), &mb_regs->data[j]);
drivers/net/can/bxcan.c
870
writel(FIELD_PREP(BXCAN_TDTxR_DLC_MASK, cf->len), &mb_regs->dlc);
drivers/net/can/bxcan.c
875
writel(id | BXCAN_TIxR_TXRQ, &mb_regs->id);
drivers/net/can/c_can/c_can_platform.c
169
writel(val, priv->base + priv->regs[index]);
drivers/net/can/ifi_canfd/ifi_canfd.c
241
writel(IFI_CANFD_IRQMASK_SET_ERR |
drivers/net/can/ifi_canfd/ifi_canfd.c
318
writel(IFI_CANFD_RXSTCMD_REMOVE_MSG, priv->base + IFI_CANFD_RXSTCMD);
drivers/net/can/ifi_canfd/ifi_canfd.c
319
writel(rx_irq_mask, priv->base + IFI_CANFD_INTERRUPT);
drivers/net/can/ifi_canfd/ifi_canfd.c
444
writel(IFI_CANFD_ERROR_CTR_ER_RESET, priv->base + IFI_CANFD_ERROR_CTR);
drivers/net/can/ifi_canfd/ifi_canfd.c
445
writel(IFI_CANFD_INTERRUPT_ERROR_COUNTER,
drivers/net/can/ifi_canfd/ifi_canfd.c
447
writel(IFI_CANFD_ERROR_CTR_ER_ENABLE, priv->base + IFI_CANFD_ERROR_CTR);
drivers/net/can/ifi_canfd/ifi_canfd.c
636
writel(clr_irq_mask, priv->base + IFI_CANFD_INTERRUPT);
drivers/net/can/ifi_canfd/ifi_canfd.c
680
writel((tseg2 << IFI_CANFD_TIME_TIMEB_OFF) |
drivers/net/can/ifi_canfd/ifi_canfd.c
691
writel((tseg2 << IFI_CANFD_TIME_TIMEB_OFF) |
drivers/net/can/ifi_canfd/ifi_canfd.c
700
writel(IFI_CANFD_TDELAY_EN | tdc, priv->base + IFI_CANFD_TDELAY);
drivers/net/can/ifi_canfd/ifi_canfd.c
708
writel(mask, priv->base + IFI_CANFD_FILTER_MASK(id));
drivers/net/can/ifi_canfd/ifi_canfd.c
709
writel(ident, priv->base + IFI_CANFD_FILTER_IDENT(id));
drivers/net/can/ifi_canfd/ifi_canfd.c
743
writel(IFI_CANFD_STCMD_HARDRESET, priv->base + IFI_CANFD_STCMD);
drivers/net/can/ifi_canfd/ifi_canfd.c
744
writel(IFI_CANFD_STCMD_ENABLE_7_9_8_8_TIMING,
drivers/net/can/ifi_canfd/ifi_canfd.c
751
writel(IFI_CANFD_RXSTCMD_RESET, priv->base + IFI_CANFD_RXSTCMD);
drivers/net/can/ifi_canfd/ifi_canfd.c
752
writel(0, priv->base + IFI_CANFD_RXSTCMD);
drivers/net/can/ifi_canfd/ifi_canfd.c
753
writel(IFI_CANFD_TXSTCMD_RESET, priv->base + IFI_CANFD_TXSTCMD);
drivers/net/can/ifi_canfd/ifi_canfd.c
754
writel(0, priv->base + IFI_CANFD_TXSTCMD);
drivers/net/can/ifi_canfd/ifi_canfd.c
757
writel(0, priv->base + IFI_CANFD_REPEAT);
drivers/net/can/ifi_canfd/ifi_canfd.c
758
writel(0, priv->base + IFI_CANFD_SUSPEND);
drivers/net/can/ifi_canfd/ifi_canfd.c
761
writel((u32)(~IFI_CANFD_INTERRUPT_SET_IRQ),
drivers/net/can/ifi_canfd/ifi_canfd.c
785
writel(IFI_CANFD_ERROR_CTR_UNLOCK_MAGIC,
drivers/net/can/ifi_canfd/ifi_canfd.c
787
writel(IFI_CANFD_ERROR_CTR_ER_RESET, priv->base + IFI_CANFD_ERROR_CTR);
drivers/net/can/ifi_canfd/ifi_canfd.c
788
writel(IFI_CANFD_ERROR_CTR_ER_ENABLE, priv->base + IFI_CANFD_ERROR_CTR);
drivers/net/can/ifi_canfd/ifi_canfd.c
791
writel(stcmd, priv->base + IFI_CANFD_STCMD);
drivers/net/can/ifi_canfd/ifi_canfd.c
799
writel(IFI_CANFD_ERROR_CTR_ER_RESET, priv->base + IFI_CANFD_ERROR_CTR);
drivers/net/can/ifi_canfd/ifi_canfd.c
800
writel(0, priv->base + IFI_CANFD_ERROR_CTR);
drivers/net/can/ifi_canfd/ifi_canfd.c
803
writel(IFI_CANFD_STCMD_HARDRESET, priv->base + IFI_CANFD_STCMD);
drivers/net/can/ifi_canfd/ifi_canfd.c
806
writel(~0, priv->base + IFI_CANFD_IRQMASK);
drivers/net/can/ifi_canfd/ifi_canfd.c
809
writel((u32)(~IFI_CANFD_INTERRUPT_SET_IRQ),
drivers/net/can/ifi_canfd/ifi_canfd.c
924
writel(txid, priv->base + IFI_CANFD_TXFIFO_ID);
drivers/net/can/ifi_canfd/ifi_canfd.c
925
writel(txdlc, priv->base + IFI_CANFD_TXFIFO_DLC);
drivers/net/can/ifi_canfd/ifi_canfd.c
928
writel(*(u32 *)(cf->data + i),
drivers/net/can/ifi_canfd/ifi_canfd.c
932
writel(0, priv->base + IFI_CANFD_TXFIFO_REPEATCOUNT);
drivers/net/can/ifi_canfd/ifi_canfd.c
933
writel(0, priv->base + IFI_CANFD_TXFIFO_SUSPEND_US);
drivers/net/can/ifi_canfd/ifi_canfd.c
938
writel(IFI_CANFD_TXSTCMD_ADD_MSG, priv->base + IFI_CANFD_TXSTCMD);
drivers/net/can/m_can/m_can_pci.c
140
writel(0x1, base + CTL_CSR_INT_CTL_OFFSET);
drivers/net/can/m_can/m_can_pci.c
165
writel(0x0, priv->base + CTL_CSR_INT_CTL_OFFSET);
drivers/net/can/m_can/m_can_pci.c
60
writel(val, priv->base + reg);
drivers/net/can/m_can/m_can_platform.c
51
writel(val, priv->base + reg);
drivers/net/can/peak_canfd/peak_pciefd_main.c
220
writel(val, priv->reg_base + reg);
drivers/net/can/peak_canfd/peak_pciefd_main.c
233
writel(val, priv->reg_base + reg);
drivers/net/can/rcar/rcar_can.c
440
writel((bcr << 8) | priv->clock_select, &priv->regs->bcr);
drivers/net/can/rcar/rcar_can.c
475
writel(0, &priv->regs->mkr_2_9[6]);
drivers/net/can/rcar/rcar_can.c
476
writel(0, &priv->regs->mkr_2_9[7]);
drivers/net/can/rcar/rcar_can.c
478
writel(0, &priv->regs->mkivlr1);
drivers/net/can/rcar/rcar_can.c
480
writel(0, &priv->regs->fidcr[0]);
drivers/net/can/rcar/rcar_can.c
481
writel(RCAR_CAN_FIDCR_IDE | RCAR_CAN_FIDCR_RTR, &priv->regs->fidcr[1]);
drivers/net/can/rcar/rcar_can.c
483
writel(RCAR_CAN_MIER1_RXFIE | RCAR_CAN_MIER1_TXFIE, &priv->regs->mier1);
drivers/net/can/rcar/rcar_can.c
568
writel(0, &priv->regs->mier0);
drivers/net/can/rcar/rcar_can.c
569
writel(0, &priv->regs->mier1);
drivers/net/can/rcar/rcar_can.c
616
writel(data, &priv->regs->mb[RCAR_CAN_TX_FIFO_MBX].id);
drivers/net/can/rcar/rcar_canfd.c
1476
writel(cfg, &gpriv->fcbase[ch].dcfg);
drivers/net/can/rcar/rcar_canfd.c
697
writel(data, reg);
drivers/net/can/rcar/rcar_canfd.c
707
writel(val, base + offset);
drivers/net/can/rockchip/rockchip_canfd.h
503
writel(val, priv->regs + reg);
drivers/net/can/sja1000/ems_pci.c
149
writel(PITA2_ICR_INT0_EN | PITA2_ICR_INT0,
drivers/net/can/sja1000/ems_pci.c
168
writel(PLX_ICSR_ENA_CLR, card->conf_addr + PLX_ICSR);
drivers/net/can/sja1000/ems_pci.c
186
writel(ASIX_LINTSR_INT0AC, card->conf_addr + ASIX_LINTSR);
drivers/net/can/sja1000/ems_pci.c
310
writel(PITA2_MISC_CONFIG, card->conf_addr + PITA2_MISC);
drivers/net/can/sja1000/ems_pci.c
329
writel(readl(card->conf_addr + ASIX_LIEMR) & ~ASIX_LIEMR_LRST,
drivers/net/can/sja1000/ems_pci.c
381
writel(PITA2_ICR_INT0_EN | PITA2_ICR_INT0,
drivers/net/can/sja1000/ems_pci.c
385
writel(PLX_ICSR_ENA_CLR,
drivers/net/can/sja1000/ems_pci.c
389
writel(ASIX_LINTSR_INT0AC, card->conf_addr + ASIX_LINTSR);
drivers/net/can/sja1000/ems_pci.c
391
writel(readl(card->conf_addr + ASIX_LIEMR) | ASIX_LIEMR_L0EINTEN,
drivers/net/can/sun4i_can.c
242
writel(val, priv->base + SUN4I_REG_CMD_ADDR);
drivers/net/can/sun4i_can.c
255
writel(mod_reg_val, priv->base + SUN4I_REG_MSEL_ADDR);
drivers/net/can/sun4i_can.c
276
writel(mod_reg_val, priv->base + SUN4I_REG_MSEL_ADDR);
drivers/net/can/sun4i_can.c
303
writel(cfg, priv->base + SUN4I_REG_BTIME_ADDR);
drivers/net/can/sun4i_can.c
345
writel(0x00000000, priv->base + SUN4I_REG_ACPC_ADDR + priv->acp_offset);
drivers/net/can/sun4i_can.c
346
writel(0xFFFFFFFF, priv->base + SUN4I_REG_ACPM_ADDR + priv->acp_offset);
drivers/net/can/sun4i_can.c
349
writel(0, priv->base + SUN4I_REG_ERRC_ADDR);
drivers/net/can/sun4i_can.c
353
writel(0xFF, priv->base + SUN4I_REG_INTEN_ADDR);
drivers/net/can/sun4i_can.c
355
writel(0xFF & ~SUN4I_INTEN_BERR,
drivers/net/can/sun4i_can.c
364
writel(mod_reg_val, priv->base + SUN4I_REG_MSEL_ADDR);
drivers/net/can/sun4i_can.c
396
writel(0, priv->base + SUN4I_REG_INTEN_ADDR);
drivers/net/can/sun4i_can.c
451
writel((id >> 21) & 0xFF, priv->base + SUN4I_REG_BUF1_ADDR);
drivers/net/can/sun4i_can.c
452
writel((id >> 13) & 0xFF, priv->base + SUN4I_REG_BUF2_ADDR);
drivers/net/can/sun4i_can.c
453
writel((id >> 5) & 0xFF, priv->base + SUN4I_REG_BUF3_ADDR);
drivers/net/can/sun4i_can.c
454
writel((id << 3) & 0xF8, priv->base + SUN4I_REG_BUF4_ADDR);
drivers/net/can/sun4i_can.c
457
writel((id >> 3) & 0xFF, priv->base + SUN4I_REG_BUF1_ADDR);
drivers/net/can/sun4i_can.c
458
writel((id << 5) & 0xE0, priv->base + SUN4I_REG_BUF2_ADDR);
drivers/net/can/sun4i_can.c
462
writel(cf->data[i], priv->base + (dreg + i * 4));
drivers/net/can/sun4i_can.c
464
writel(msg_flag_n, priv->base + SUN4I_REG_BUF0_ADDR);
drivers/net/can/sun4i_can.c
691
writel(isrc, priv->base + SUN4I_REG_INT_ADDR);
drivers/net/dsa/b53/b53_mmap.c
222
writel(value, regs + (page << 8) + reg);
drivers/net/dsa/b53/b53_srab.c
100
writel(ctrls, regs + B53_SRAB_CTRLS);
drivers/net/dsa/b53/b53_srab.c
122
writel(ctrls, regs + B53_SRAB_CTRLS);
drivers/net/dsa/b53/b53_srab.c
137
writel(cmdstat, regs + B53_SRAB_CMDSTAT);
drivers/net/dsa/b53/b53_srab.c
275
writel(value, regs + B53_SRAB_WD_L);
drivers/net/dsa/b53/b53_srab.c
296
writel(value, regs + B53_SRAB_WD_L);
drivers/net/dsa/b53/b53_srab.c
317
writel(value, regs + B53_SRAB_WD_L);
drivers/net/dsa/b53/b53_srab.c
338
writel((u32)value, regs + B53_SRAB_WD_L);
drivers/net/dsa/b53/b53_srab.c
339
writel((u16)(value >> 32), regs + B53_SRAB_WD_H);
drivers/net/dsa/b53/b53_srab.c
360
writel((u32)value, regs + B53_SRAB_WD_L);
drivers/net/dsa/b53/b53_srab.c
361
writel((u32)(value >> 32), regs + B53_SRAB_WD_H);
drivers/net/dsa/b53/b53_srab.c
389
writel(BIT(port->num), priv->regs + B53_SRAB_INTR);
drivers/net/dsa/b53/b53_srab.c
531
writel(reg, priv->regs + B53_SRAB_CTRLS);
drivers/net/dsa/b53/b53_srab.c
543
writel(0xffffffff, priv->regs + B53_SRAB_INTR);
drivers/net/dsa/rzn1_a5psw.c
73
writel(value, a5psw->base + offset);
drivers/net/ethernet/actions/owl-emac.c
32
writel(data, priv->base + reg);
drivers/net/ethernet/adaptec/starfire.c
1029
writel(be32_to_cpup(&fw_rx_data[i]), ioaddr + RxGfpMem + i * 4);
drivers/net/ethernet/adaptec/starfire.c
1031
writel(be32_to_cpup(&fw_tx_data[i]), ioaddr + TxGfpMem + i * 4);
drivers/net/ethernet/adaptec/starfire.c
1034
writel(TxEnable|TxGFPEnable|RxEnable|RxGFPEnable, ioaddr + GenCtrl);
drivers/net/ethernet/adaptec/starfire.c
1037
writel(TxEnable|RxEnable, ioaddr + GenCtrl);
drivers/net/ethernet/adaptec/starfire.c
1261
writel(entry * (sizeof(starfire_tx_desc) / 8), np->base + TxProducerIdx);
drivers/net/ethernet/adaptec/starfire.c
1322
writel(enable, ioaddr + IntrEnable);
drivers/net/ethernet/adaptec/starfire.c
1333
writel(enable, ioaddr + IntrEnable);
drivers/net/ethernet/adaptec/starfire.c
1553
writel(IntrRxDone | IntrRxEmpty, ioaddr + IntrClear);
drivers/net/ethernet/adaptec/starfire.c
1564
writel(intr_status, ioaddr + IntrEnable);
drivers/net/ethernet/adaptec/starfire.c
1664
writel(np->tx_mode | MiiSoftReset, ioaddr + TxMode);
drivers/net/ethernet/adaptec/starfire.c
1666
writel(np->tx_mode, ioaddr + TxMode);
drivers/net/ethernet/adaptec/starfire.c
1674
writel(new_intr_timer_ctrl, ioaddr + IntrTimerCtrl);
drivers/net/ethernet/adaptec/starfire.c
1690
writel(++np->tx_threshold, np->base + TxThreshold);
drivers/net/ethernet/adaptec/starfire.c
1826
writel(rx_mode, ioaddr + RxFilterMode);
drivers/net/ethernet/adaptec/starfire.c
1936
writel(0, ioaddr + IntrEnable);
drivers/net/ethernet/adaptec/starfire.c
1939
writel(0, ioaddr + GenCtrl);
drivers/net/ethernet/adaptec/starfire.c
704
writel(MiiSoftReset, base + TxMode);
drivers/net/ethernet/adaptec/starfire.c
706
writel(0, base + TxMode);
drivers/net/ethernet/adaptec/starfire.c
709
writel(1, base + PCIDeviceConfig);
drivers/net/ethernet/adaptec/starfire.c
847
writel(value, mdio_addr);
drivers/net/ethernet/adaptec/starfire.c
870
writel(0, ioaddr + GenCtrl);
drivers/net/ethernet/adaptec/starfire.c
871
writel(1, ioaddr + PCIDeviceConfig);
drivers/net/ethernet/adaptec/starfire.c
905
writel((np->rx_buf_sz << RxBufferLenShift) |
drivers/net/ethernet/adaptec/starfire.c
914
writel(RxChecksumIgnore |
drivers/net/ethernet/adaptec/starfire.c
921
writel((2 << TxHiPriFIFOThreshShift) |
drivers/net/ethernet/adaptec/starfire.c
928
writel( (np->queue_mem_dma >> 16) >> 16, ioaddr + RxDescQHiAddr);
drivers/net/ethernet/adaptec/starfire.c
929
writel( (np->queue_mem_dma >> 16) >> 16, ioaddr + TxRingHiAddr);
drivers/net/ethernet/adaptec/starfire.c
930
writel( (np->queue_mem_dma >> 16) >> 16, ioaddr + CompletionHiAddr);
drivers/net/ethernet/adaptec/starfire.c
931
writel(np->rx_ring_dma, ioaddr + RxDescQAddr);
drivers/net/ethernet/adaptec/starfire.c
932
writel(np->tx_ring_dma, ioaddr + TxRingPtr);
drivers/net/ethernet/adaptec/starfire.c
934
writel(np->tx_done_q_dma, ioaddr + TxCompletionAddr);
drivers/net/ethernet/adaptec/starfire.c
935
writel(np->rx_done_q_dma |
drivers/net/ethernet/adaptec/starfire.c
962
writel(MiiSoftReset | np->tx_mode, ioaddr + TxMode);
drivers/net/ethernet/adaptec/starfire.c
964
writel(np->tx_mode, ioaddr + TxMode);
drivers/net/ethernet/adaptec/starfire.c
966
writel(np->tx_threshold, ioaddr + TxThreshold);
drivers/net/ethernet/adaptec/starfire.c
968
writel(np->intr_timer_ctrl, ioaddr + IntrTimerCtrl);
drivers/net/ethernet/adaptec/starfire.c
982
writel(0x0f00ff00, ioaddr + GPIOCtrl);
drivers/net/ethernet/adaptec/starfire.c
985
writel(IntrRxDone | IntrRxEmpty | IntrDMAErr |
drivers/net/ethernet/adaptec/starfire.c
990
writel(0x00800000 | readl(ioaddr + PCIDeviceConfig),
drivers/net/ethernet/adaptec/starfire.c
995
writel(ETH_P_8021Q, ioaddr + VlanType);
drivers/net/ethernet/agere/et131x.c
1026
writel(uni_pf1, &rxmac->uni_pf_addr1);
drivers/net/ethernet/agere/et131x.c
1027
writel(uni_pf2, &rxmac->uni_pf_addr2);
drivers/net/ethernet/agere/et131x.c
1028
writel(uni_pf3, &rxmac->uni_pf_addr3);
drivers/net/ethernet/agere/et131x.c
1042
writel(0x8, &rxmac->ctrl);
drivers/net/ethernet/agere/et131x.c
1045
writel(0, &rxmac->crc0);
drivers/net/ethernet/agere/et131x.c
1046
writel(0, &rxmac->crc12);
drivers/net/ethernet/agere/et131x.c
1047
writel(0, &rxmac->crc34);
drivers/net/ethernet/agere/et131x.c
1054
writel(0, wolw);
drivers/net/ethernet/agere/et131x.c
1061
writel(sa_lo, &rxmac->sa_lo);
drivers/net/ethernet/agere/et131x.c
1065
writel(sa_hi, &rxmac->sa_hi);
drivers/net/ethernet/agere/et131x.c
1068
writel(0, &rxmac->pf_ctrl);
drivers/net/ethernet/agere/et131x.c
1075
writel(0, &rxmac->uni_pf_addr1);
drivers/net/ethernet/agere/et131x.c
1076
writel(0, &rxmac->uni_pf_addr2);
drivers/net/ethernet/agere/et131x.c
1077
writel(0, &rxmac->uni_pf_addr3);
drivers/net/ethernet/agere/et131x.c
1101
writel(0x41, &rxmac->mcif_ctrl_max_seg);
drivers/net/ethernet/agere/et131x.c
1103
writel(0, &rxmac->mcif_ctrl_max_seg);
drivers/net/ethernet/agere/et131x.c
1105
writel(0, &rxmac->mcif_water_mark);
drivers/net/ethernet/agere/et131x.c
1106
writel(0, &rxmac->mif_ctrl);
drivers/net/ethernet/agere/et131x.c
1107
writel(0, &rxmac->space_avail);
drivers/net/ethernet/agere/et131x.c
1123
writel(0x30038, &rxmac->mif_ctrl);
drivers/net/ethernet/agere/et131x.c
1125
writel(0x30030, &rxmac->mif_ctrl);
drivers/net/ethernet/agere/et131x.c
1133
writel(pf_ctrl, &rxmac->pf_ctrl);
drivers/net/ethernet/agere/et131x.c
1134
writel(ET_RX_CTRL_RXMAC_ENABLE | ET_RX_CTRL_WOL_DISABLE, &rxmac->ctrl);
drivers/net/ethernet/agere/et131x.c
1146
writel(0, &txmac->cf_param);
drivers/net/ethernet/agere/et131x.c
1148
writel(0x40, &txmac->cf_param);
drivers/net/ethernet/agere/et131x.c
1159
writel(0, reg);
drivers/net/ethernet/agere/et131x.c
1165
writel(0xFFFFBE32, &macstat->carry_reg1_mask);
drivers/net/ethernet/agere/et131x.c
1166
writel(0xFFFE7E8B, &macstat->carry_reg2_mask);
drivers/net/ethernet/agere/et131x.c
1186
writel(0, &mac->mii_mgmt_cmd);
drivers/net/ethernet/agere/et131x.c
1189
writel(ET_MAC_MII_ADDR(addr, reg), &mac->mii_mgmt_addr);
drivers/net/ethernet/agere/et131x.c
1191
writel(0x1, &mac->mii_mgmt_cmd);
drivers/net/ethernet/agere/et131x.c
1217
writel(0, &mac->mii_mgmt_cmd);
drivers/net/ethernet/agere/et131x.c
1222
writel(mii_addr, &mac->mii_mgmt_addr);
drivers/net/ethernet/agere/et131x.c
1223
writel(mii_cmd, &mac->mii_mgmt_cmd);
drivers/net/ethernet/agere/et131x.c
1255
writel(0, &mac->mii_mgmt_cmd);
drivers/net/ethernet/agere/et131x.c
1258
writel(ET_MAC_MII_ADDR(addr, reg), &mac->mii_mgmt_addr);
drivers/net/ethernet/agere/et131x.c
1261
writel(value, &mac->mii_mgmt_ctrl);
drivers/net/ethernet/agere/et131x.c
1285
writel(0, &mac->mii_mgmt_cmd);
drivers/net/ethernet/agere/et131x.c
1290
writel(mii_addr, &mac->mii_mgmt_addr);
drivers/net/ethernet/agere/et131x.c
1291
writel(mii_cmd, &mac->mii_mgmt_cmd);
drivers/net/ethernet/agere/et131x.c
1381
writel(carry_reg1, &adapter->regs->macstat.carry_reg1);
drivers/net/ethernet/agere/et131x.c
1382
writel(carry_reg2, &adapter->regs->macstat.carry_reg2);
drivers/net/ethernet/agere/et131x.c
1499
writel(0, ®s->rxq_start_addr);
drivers/net/ethernet/agere/et131x.c
1500
writel(INTERNAL_MEM_SIZE - 1, ®s->txq_end_addr);
drivers/net/ethernet/agere/et131x.c
1508
writel(PARM_RX_MEM_END_DEF, ®s->rxq_end_addr);
drivers/net/ethernet/agere/et131x.c
1509
writel(PARM_RX_MEM_END_DEF + 1, ®s->txq_start_addr);
drivers/net/ethernet/agere/et131x.c
1512
writel(INTERNAL_MEM_RX_OFFSET, ®s->rxq_end_addr);
drivers/net/ethernet/agere/et131x.c
1513
writel(INTERNAL_MEM_RX_OFFSET + 1, ®s->txq_start_addr);
drivers/net/ethernet/agere/et131x.c
1520
writel(0x01b3, ®s->rxq_end_addr);
drivers/net/ethernet/agere/et131x.c
1521
writel(0x01b4, ®s->txq_start_addr);
drivers/net/ethernet/agere/et131x.c
1525
writel(0, ®s->loopback);
drivers/net/ethernet/agere/et131x.c
1527
writel(0, ®s->msi_config);
drivers/net/ethernet/agere/et131x.c
1532
writel(0, ®s->watchdog_timer);
drivers/net/ethernet/agere/et131x.c
1549
writel(upper_32_bits(rx_local->rx_status_bus), &rx_dma->dma_wb_base_hi);
drivers/net/ethernet/agere/et131x.c
1550
writel(lower_32_bits(rx_local->rx_status_bus), &rx_dma->dma_wb_base_lo);
drivers/net/ethernet/agere/et131x.c
1555
writel(upper_32_bits(rx_local->ps_ring_physaddr), &rx_dma->psr_base_hi);
drivers/net/ethernet/agere/et131x.c
1556
writel(lower_32_bits(rx_local->ps_ring_physaddr), &rx_dma->psr_base_lo);
drivers/net/ethernet/agere/et131x.c
1557
writel(rx_local->psr_entries - 1, &rx_dma->psr_num_des);
drivers/net/ethernet/agere/et131x.c
1558
writel(0, &rx_dma->psr_full_offset);
drivers/net/ethernet/agere/et131x.c
1561
writel((psr_num_des * LO_MARK_PERCENT_FOR_PSR) / 100,
drivers/net/ethernet/agere/et131x.c
1601
writel(upper_32_bits(fbr->ring_physaddr), base_hi);
drivers/net/ethernet/agere/et131x.c
1602
writel(lower_32_bits(fbr->ring_physaddr), base_lo);
drivers/net/ethernet/agere/et131x.c
1603
writel(fbr->num_entries - 1, num_des);
drivers/net/ethernet/agere/et131x.c
1604
writel(ET_DMA10_WRAP, full_offset);
drivers/net/ethernet/agere/et131x.c
1610
writel(((fbr->num_entries * LO_MARK_PERCENT_FOR_RX) / 100) - 1,
drivers/net/ethernet/agere/et131x.c
1619
writel(PARM_RX_NUM_BUFS_DEF, &rx_dma->num_pkt_done);
drivers/net/ethernet/agere/et131x.c
1626
writel(PARM_RX_TIME_INT_DEF, &rx_dma->max_pkt_time);
drivers/net/ethernet/agere/et131x.c
1642
writel(upper_32_bits(tx_ring->tx_desc_ring_pa), &txdma->pr_base_hi);
drivers/net/ethernet/agere/et131x.c
1643
writel(lower_32_bits(tx_ring->tx_desc_ring_pa), &txdma->pr_base_lo);
drivers/net/ethernet/agere/et131x.c
1646
writel(NUM_DESC_PER_RING_TX - 1, &txdma->pr_num_des);
drivers/net/ethernet/agere/et131x.c
1649
writel(upper_32_bits(tx_ring->tx_status_pa), &txdma->dma_wb_base_hi);
drivers/net/ethernet/agere/et131x.c
1650
writel(lower_32_bits(tx_ring->tx_status_pa), &txdma->dma_wb_base_lo);
drivers/net/ethernet/agere/et131x.c
1654
writel(0, &txdma->service_request);
drivers/net/ethernet/agere/et131x.c
1666
writel(ET_MMC_ENABLE, &adapter->regs->mmc.mmc_ctrl);
drivers/net/ethernet/agere/et131x.c
1689
writel(reg, &adapter->regs->mac.cfg1);
drivers/net/ethernet/agere/et131x.c
1692
writel(reg, &adapter->regs->global.sw_reset);
drivers/net/ethernet/agere/et131x.c
1696
writel(reg, &adapter->regs->mac.cfg1);
drivers/net/ethernet/agere/et131x.c
1697
writel(0, &adapter->regs->mac.cfg1);
drivers/net/ethernet/agere/et131x.c
1709
writel(mask, &adapter->regs->global.int_mask);
drivers/net/ethernet/agere/et131x.c
1714
writel(INT_MASK_DISABLE, &adapter->regs->global.int_mask);
drivers/net/ethernet/agere/et131x.c
1720
writel(ET_TXDMA_CSR_HALT | ET_TXDMA_SNGL_EPKT,
drivers/net/ethernet/agere/et131x.c
1794
writel(pmcsr, &adapter->regs->global.pm_csr);
drivers/net/ethernet/agere/et131x.c
1798
writel(pmcsr, &adapter->regs->global.pm_csr);
drivers/net/ethernet/agere/et131x.c
1810
writel(pmcsr, &adapter->regs->global.pm_csr);
drivers/net/ethernet/agere/et131x.c
2117
writel(0, &adapter->regs->rxdma.max_pkt_time);
drivers/net/ethernet/agere/et131x.c
2118
writel(1, &adapter->regs->rxdma.num_pkt_done);
drivers/net/ethernet/agere/et131x.c
2158
writel(free_buff_ring, offset);
drivers/net/ethernet/agere/et131x.c
2231
writel(rx_local->local_psr_full, &adapter->regs->rxdma.psr_full_offset);
drivers/net/ethernet/agere/et131x.c
2336
writel(PARM_TX_TIME_INT_DEF * NANO_IN_A_MICRO,
drivers/net/ethernet/agere/et131x.c
2586
writel(tx_ring->send_idx, &adapter->regs->txdma.service_request);
drivers/net/ethernet/agere/et131x.c
2592
writel(PARM_TX_TIME_INT_DEF * NANO_IN_A_MICRO,
drivers/net/ethernet/agere/et131x.c
3437
writel(0, &adapter->regs->global.watchdog_timer);
drivers/net/ethernet/agere/et131x.c
3482
writel(3, &iomem->txmac.bp_ctrl);
drivers/net/ethernet/agere/et131x.c
3732
writel(pf_ctrl, &adapter->regs->rxmac.pf_ctrl);
drivers/net/ethernet/agere/et131x.c
3733
writel(ctrl, &adapter->regs->rxmac.ctrl);
drivers/net/ethernet/agere/et131x.c
3996
writel(ET_PMCSR_INIT, &adapter->regs->global.pm_csr);
drivers/net/ethernet/agere/et131x.c
756
writel(csr, &adapter->regs->rxdma.csr);
drivers/net/ethernet/agere/et131x.c
774
writel(ET_RXDMA_CSR_HALT | ET_RXDMA_CSR_FBR1_ENABLE,
drivers/net/ethernet/agere/et131x.c
792
writel(ET_TXDMA_SNGL_EPKT | (PARM_DMA_CACHE_DEF << ET_TXDMA_CACHE_SHIFT),
drivers/net/ethernet/agere/et131x.c
816
writel(ET_MAC_CFG1_SOFT_RESET | ET_MAC_CFG1_SIM_RESET |
drivers/net/ethernet/agere/et131x.c
824
writel(ipg, ¯egs->ipg);
drivers/net/ethernet/agere/et131x.c
828
writel(0x00A1F037, ¯egs->hfdp);
drivers/net/ethernet/agere/et131x.c
831
writel(0, ¯egs->if_ctrl);
drivers/net/ethernet/agere/et131x.c
833
writel(ET_MAC_MIIMGMT_CLK_RST, ¯egs->mii_mgmt_cfg);
drivers/net/ethernet/agere/et131x.c
848
writel(station1, ¯egs->station_addr_1);
drivers/net/ethernet/agere/et131x.c
849
writel(station2, ¯egs->station_addr_2);
drivers/net/ethernet/agere/et131x.c
858
writel(adapter->registry_jumbo_packet + 4, ¯egs->max_fm_len);
drivers/net/ethernet/agere/et131x.c
861
writel(0, ¯egs->cfg1);
drivers/net/ethernet/agere/et131x.c
895
writel(cfg1, &mac->cfg1);
drivers/net/ethernet/agere/et131x.c
915
writel(ifctrl, &mac->if_ctrl);
drivers/net/ethernet/agere/et131x.c
916
writel(cfg2, &mac->cfg2);
drivers/net/ethernet/agere/et131x.c
931
writel(ctl, &adapter->regs->txmac.ctl);
drivers/net/ethernet/agere/et131x.c
987
writel(hash1, &rxmac->multi_hash1);
drivers/net/ethernet/agere/et131x.c
988
writel(hash2, &rxmac->multi_hash2);
drivers/net/ethernet/agere/et131x.c
989
writel(hash3, &rxmac->multi_hash3);
drivers/net/ethernet/agere/et131x.c
990
writel(hash4, &rxmac->multi_hash4);
drivers/net/ethernet/airoha/airoha_eth.c
27
writel(val, base + offset);
drivers/net/ethernet/allwinner/sun4i-emac.c
112
writel(reg_val, db->membase + EMAC_MAC_SUPP_REG);
drivers/net/ethernet/allwinner/sun4i-emac.c
125
writel(reg_val, db->membase + EMAC_MAC_CTL1_REG);
drivers/net/ethernet/allwinner/sun4i-emac.c
203
writel(0, db->membase + EMAC_CTL_REG);
drivers/net/ethernet/allwinner/sun4i-emac.c
205
writel(EMAC_CTL_RESET, db->membase + EMAC_CTL_REG);
drivers/net/ethernet/allwinner/sun4i-emac.c
263
writel(reg_val, db->membase + EMAC_RX_CTL_REG);
drivers/net/ethernet/allwinner/sun4i-emac.c
268
writel(reg_val, db->membase + EMAC_INT_CTL_REG);
drivers/net/ethernet/allwinner/sun4i-emac.c
369
writel(reg_val | EMAC_TX_MODE_ABORTED_FRAME_EN,
drivers/net/ethernet/allwinner/sun4i-emac.c
375
writel(reg_val | EMAC_MAC_CTL0_RX_FLOW_CTL_EN |
drivers/net/ethernet/allwinner/sun4i-emac.c
384
writel(reg_val, db->membase + EMAC_MAC_CTL1_REG);
drivers/net/ethernet/allwinner/sun4i-emac.c
387
writel(EMAC_MAC_IPGT_FULL_DUPLEX, db->membase + EMAC_MAC_IPGT_REG);
drivers/net/ethernet/allwinner/sun4i-emac.c
390
writel((EMAC_MAC_IPGR_IPG1 << 8) | EMAC_MAC_IPGR_IPG2,
drivers/net/ethernet/allwinner/sun4i-emac.c
394
writel((EMAC_MAC_CLRT_COLLISION_WINDOW << 8) | EMAC_MAC_CLRT_RM,
drivers/net/ethernet/allwinner/sun4i-emac.c
398
writel(EMAC_MAX_FRAME_LEN,
drivers/net/ethernet/allwinner/sun4i-emac.c
417
writel(reg_val | EMAC_RX_CTL_PASS_LEN_OOR_EN |
drivers/net/ethernet/allwinner/sun4i-emac.c
433
writel(reg_val, db->membase + EMAC_RX_CTL_REG);
drivers/net/ethernet/allwinner/sun4i-emac.c
440
writel(reg_val, db->membase + EMAC_MAC_CTL0_REG);
drivers/net/ethernet/allwinner/sun4i-emac.c
446
writel(reg_val, db->membase + EMAC_MAC_MCFG_REG);
drivers/net/ethernet/allwinner/sun4i-emac.c
449
writel(0x0, db->membase + EMAC_RX_FBC_REG);
drivers/net/ethernet/allwinner/sun4i-emac.c
452
writel(0, db->membase + EMAC_INT_CTL_REG);
drivers/net/ethernet/allwinner/sun4i-emac.c
454
writel(reg_val, db->membase + EMAC_INT_STA_REG);
drivers/net/ethernet/allwinner/sun4i-emac.c
462
writel(ndev->dev_addr[0] << 16 | ndev->dev_addr[1] << 8 | ndev->
drivers/net/ethernet/allwinner/sun4i-emac.c
464
writel(ndev->dev_addr[3] << 16 | ndev->dev_addr[4] << 8 | ndev->
drivers/net/ethernet/allwinner/sun4i-emac.c
482
writel(dev->dev_addr[0] << 16 | dev->dev_addr[1] << 8 | dev->
drivers/net/ethernet/allwinner/sun4i-emac.c
484
writel(dev->dev_addr[3] << 16 | dev->dev_addr[4] << 8 | dev->
drivers/net/ethernet/allwinner/sun4i-emac.c
504
writel(reg_val | EMAC_CTL_RESET | EMAC_CTL_TX_EN | EMAC_CTL_RX_EN,
drivers/net/ethernet/allwinner/sun4i-emac.c
510
writel(reg_val, db->membase + EMAC_INT_CTL_REG);
drivers/net/ethernet/allwinner/sun4i-emac.c
555
writel(channel, db->membase + EMAC_TX_INS_REG);
drivers/net/ethernet/allwinner/sun4i-emac.c
565
writel(skb->len, db->membase + EMAC_TX_PL0_REG);
drivers/net/ethernet/allwinner/sun4i-emac.c
567
writel(readl(db->membase + EMAC_TX_CTL0_REG) | 1,
drivers/net/ethernet/allwinner/sun4i-emac.c
574
writel(skb->len, db->membase + EMAC_TX_PL1_REG);
drivers/net/ethernet/allwinner/sun4i-emac.c
576
writel(readl(db->membase + EMAC_TX_CTL1_REG) | 1,
drivers/net/ethernet/allwinner/sun4i-emac.c
643
writel(reg_val, db->membase + EMAC_INT_CTL_REG);
drivers/net/ethernet/allwinner/sun4i-emac.c
657
writel(reg_val & ~EMAC_CTL_RX_EN,
drivers/net/ethernet/allwinner/sun4i-emac.c
662
writel(reg_val | (1 << 3),
drivers/net/ethernet/allwinner/sun4i-emac.c
671
writel(reg_val | EMAC_CTL_RX_EN,
drivers/net/ethernet/allwinner/sun4i-emac.c
677
writel(reg_val, db->membase + EMAC_INT_CTL_REG);
drivers/net/ethernet/allwinner/sun4i-emac.c
737
writel(reg_val, db->membase + EMAC_RX_CTL_REG);
drivers/net/ethernet/allwinner/sun4i-emac.c
744
writel(reg_val, db->membase + EMAC_RX_CTL_REG);
drivers/net/ethernet/allwinner/sun4i-emac.c
771
writel(0, db->membase + EMAC_INT_CTL_REG);
drivers/net/ethernet/allwinner/sun4i-emac.c
777
writel(int_status, db->membase + EMAC_INT_STA_REG);
drivers/net/ethernet/allwinner/sun4i-emac.c
800
writel(reg_val, db->membase + EMAC_INT_CTL_REG);
drivers/net/ethernet/allwinner/sun4i-emac.c
804
writel(reg_val, db->membase + EMAC_INT_CTL_REG);
drivers/net/ethernet/allwinner/sun4i-emac.c
861
writel(0, db->membase + EMAC_INT_CTL_REG);
drivers/net/ethernet/allwinner/sun4i-emac.c
865
writel(reg_val, db->membase + EMAC_INT_STA_REG);
drivers/net/ethernet/allwinner/sun4i-emac.c
870
writel(reg_val, db->membase + EMAC_CTL_REG);
drivers/net/ethernet/alteon/acenic.c
1108
writel(tmp, ®s->PciState);
drivers/net/ethernet/alteon/acenic.c
1180
writel(tmp_ptr >> 32, ®s->InfoPtrHi);
drivers/net/ethernet/alteon/acenic.c
1181
writel(tmp_ptr & 0xffffffff, ®s->InfoPtrLo);
drivers/net/ethernet/alteon/acenic.c
1191
writel(0, ®s->EvtCsm);
drivers/net/ethernet/alteon/acenic.c
1198
writel(0, ®s->CmdRng[i]);
drivers/net/ethernet/alteon/acenic.c
1200
writel(0, ®s->CmdPrd);
drivers/net/ethernet/alteon/acenic.c
1201
writel(0, ®s->CmdCsm);
drivers/net/ethernet/alteon/acenic.c
1277
writel(TX_RING_BASE, ®s->WinBase);
drivers/net/ethernet/alteon/acenic.c
1283
writel(0, (__force void __iomem *)ap->tx_ring + i * 4);
drivers/net/ethernet/alteon/acenic.c
1312
writel(DMA_THRESH_16W, ®s->DmaReadCfg);
drivers/net/ethernet/alteon/acenic.c
1313
writel(DMA_THRESH_16W, ®s->DmaWriteCfg);
drivers/net/ethernet/alteon/acenic.c
1315
writel(DMA_THRESH_8W, ®s->DmaReadCfg);
drivers/net/ethernet/alteon/acenic.c
1316
writel(DMA_THRESH_8W, ®s->DmaWriteCfg);
drivers/net/ethernet/alteon/acenic.c
1319
writel(0, ®s->MaskInt);
drivers/net/ethernet/alteon/acenic.c
1320
writel(1, ®s->IfIdx);
drivers/net/ethernet/alteon/acenic.c
1326
writel(1, ®s->AssistState);
drivers/net/ethernet/alteon/acenic.c
1329
writel(DEF_STAT, ®s->TuneStatTicks);
drivers/net/ethernet/alteon/acenic.c
1330
writel(DEF_TRACE, ®s->TuneTrace);
drivers/net/ethernet/alteon/acenic.c
1340
writel(tx_coal_tick[board_idx],
drivers/net/ethernet/alteon/acenic.c
1343
writel(max_tx_desc[board_idx], ®s->TuneMaxTxDesc);
drivers/net/ethernet/alteon/acenic.c
1346
writel(rx_coal_tick[board_idx],
drivers/net/ethernet/alteon/acenic.c
1349
writel(max_rx_desc[board_idx], ®s->TuneMaxRxDesc);
drivers/net/ethernet/alteon/acenic.c
1352
writel(trace[board_idx], ®s->TuneTrace);
drivers/net/ethernet/alteon/acenic.c
1355
writel(tx_ratio[board_idx], ®s->TxBufRat);
drivers/net/ethernet/alteon/acenic.c
1408
writel(tmp, ®s->TuneLink);
drivers/net/ethernet/alteon/acenic.c
1410
writel(tmp, ®s->TuneFastLink);
drivers/net/ethernet/alteon/acenic.c
1412
writel(ap->firmware_start, ®s->Pc);
drivers/net/ethernet/alteon/acenic.c
1414
writel(0, ®s->Mb0Lo);
drivers/net/ethernet/alteon/acenic.c
1427
writel(0, ®s->RxRetCsm);
drivers/net/ethernet/alteon/acenic.c
1435
writel(1, ®s->AssistState); /* enable DMA */
drivers/net/ethernet/alteon/acenic.c
1440
writel(readl(®s->CpuCtrl) & ~(CPU_HALT|CPU_TRACE), ®s->CpuCtrl);
drivers/net/ethernet/alteon/acenic.c
1454
writel(readl(®s->CpuCtrl) | CPU_HALT, ®s->CpuCtrl);
drivers/net/ethernet/alteon/acenic.c
1467
writel(readl(®s->CpuBCtrl) | CPU_HALT,
drivers/net/ethernet/alteon/acenic.c
1469
writel(0, ®s->Mb0Lo);
drivers/net/ethernet/alteon/acenic.c
1509
writel(DEF_TX_COAL, ®s->TuneTxCoalTicks);
drivers/net/ethernet/alteon/acenic.c
1511
writel(DEF_TX_MAX_DESC, ®s->TuneMaxTxDesc);
drivers/net/ethernet/alteon/acenic.c
1513
writel(DEF_RX_COAL, ®s->TuneRxCoalTicks);
drivers/net/ethernet/alteon/acenic.c
1515
writel(DEF_RX_MAX_DESC, ®s->TuneMaxRxDesc);
drivers/net/ethernet/alteon/acenic.c
1517
writel(DEF_TX_RATIO, ®s->TxBufRat);
drivers/net/ethernet/alteon/acenic.c
1520
writel(DEF_JUMBO_TX_COAL,
drivers/net/ethernet/alteon/acenic.c
1523
writel(DEF_JUMBO_TX_MAX_DESC,
drivers/net/ethernet/alteon/acenic.c
1526
writel(DEF_JUMBO_RX_COAL,
drivers/net/ethernet/alteon/acenic.c
1529
writel(DEF_JUMBO_RX_MAX_DESC,
drivers/net/ethernet/alteon/acenic.c
1532
writel(DEF_JUMBO_TX_RATIO, ®s->TxBufRat);
drivers/net/ethernet/alteon/acenic.c
1670
writel(idx, ®s->RxStdPrd);
drivers/net/ethernet/alteon/acenic.c
1725
writel(idx, ®s->RxMiniPrd);
drivers/net/ethernet/alteon/acenic.c
1787
writel(idx, ®s->RxJumboPrd);
drivers/net/ethernet/alteon/acenic.c
1890
writel(0, &((ap->regs)->RxJumboPrd));
drivers/net/ethernet/alteon/acenic.c
2016
writel(idx, &ap->regs->RxRetCsm);
drivers/net/ethernet/alteon/acenic.c
2118
writel(0, ®s->Mb0Lo);
drivers/net/ethernet/alteon/acenic.c
2154
writel(evtcsm, ®s->EvtCsm);
drivers/net/ethernet/alteon/acenic.c
2231
writel(dev->mtu + ETH_HLEN + 4, ®s->IfMtu);
drivers/net/ethernet/alteon/acenic.c
2326
writel(0, &tx->addr.addrhi);
drivers/net/ethernet/alteon/acenic.c
2327
writel(0, &tx->addr.addrlo);
drivers/net/ethernet/alteon/acenic.c
2328
writel(0, &tx->flagsize);
drivers/net/ethernet/alteon/acenic.c
2387
writel(addr >> 32, &io->addr.addrhi);
drivers/net/ethernet/alteon/acenic.c
2388
writel(addr & 0xffffffff, &io->addr.addrlo);
drivers/net/ethernet/alteon/acenic.c
2389
writel(flagsize, &io->flagsize);
drivers/net/ethernet/alteon/acenic.c
2390
writel(vlan_tag, &io->vlanres);
drivers/net/ethernet/alteon/acenic.c
2541
writel(new_mtu + ETH_HLEN + 4, ®s->IfMtu);
drivers/net/ethernet/alteon/acenic.c
2675
writel(link, ®s->TuneLink);
drivers/net/ethernet/alteon/acenic.c
2677
writel(link, ®s->TuneFastLink);
drivers/net/ethernet/alteon/acenic.c
2721
writel(da[0] << 8 | da[1], ®s->MacAddrHi);
drivers/net/ethernet/alteon/acenic.c
2722
writel((da[2] << 24) | (da[3] << 16) | (da[4] << 8) | da[5],
drivers/net/ethernet/alteon/acenic.c
2816
writel(dest & ~(ACE_WINDOW_SIZE - 1), ®s->WinBase);
drivers/net/ethernet/alteon/acenic.c
2819
writel(be32_to_cpup(src), tdest);
drivers/net/ethernet/alteon/acenic.c
2842
writel(dest & ~(ACE_WINDOW_SIZE - 1), ®s->WinBase);
drivers/net/ethernet/alteon/acenic.c
2845
writel(0, tdest + i*4);
drivers/net/ethernet/alteon/acenic.c
2948
writel(local, ®s->LocalCtrl);
drivers/net/ethernet/alteon/acenic.c
2953
writel(local, ®s->LocalCtrl);
drivers/net/ethernet/alteon/acenic.c
2958
writel(local, ®s->LocalCtrl);
drivers/net/ethernet/alteon/acenic.c
2963
writel(local, ®s->LocalCtrl);
drivers/net/ethernet/alteon/acenic.c
2978
writel(local, ®s->LocalCtrl);
drivers/net/ethernet/alteon/acenic.c
2988
writel(local, ®s->LocalCtrl);
drivers/net/ethernet/alteon/acenic.c
2994
writel(local, ®s->LocalCtrl);
drivers/net/ethernet/alteon/acenic.c
2999
writel(local, ®s->LocalCtrl);
drivers/net/ethernet/alteon/acenic.c
3013
writel(local, ®s->LocalCtrl);
drivers/net/ethernet/alteon/acenic.c
3018
writel(local, ®s->LocalCtrl);
drivers/net/ethernet/alteon/acenic.c
3026
writel(readl(®s->LocalCtrl) & ~EEPROM_CLK_OUT, ®s->LocalCtrl);
drivers/net/ethernet/alteon/acenic.c
3041
writel(local, ®s->LocalCtrl);
drivers/net/ethernet/alteon/acenic.c
3046
writel(local, ®s->LocalCtrl);
drivers/net/ethernet/alteon/acenic.c
3051
writel(local, ®s->LocalCtrl);
drivers/net/ethernet/alteon/acenic.c
3056
writel(local, ®s->LocalCtrl);
drivers/net/ethernet/alteon/acenic.c
3061
writel(local, ®s->LocalCtrl);
drivers/net/ethernet/alteon/acenic.c
3125
writel(local, ®s->LocalCtrl);
drivers/net/ethernet/alteon/acenic.c
3130
writel(local, ®s->LocalCtrl);
drivers/net/ethernet/alteon/acenic.c
3141
writel(local, ®s->LocalCtrl);
drivers/net/ethernet/alteon/acenic.c
3147
writel(local, ®s->LocalCtrl);
drivers/net/ethernet/alteon/acenic.c
3155
writel(local, ®s->LocalCtrl);
drivers/net/ethernet/alteon/acenic.c
3159
writel(readl(®s->LocalCtrl) | EEPROM_CLK_OUT, ®s->LocalCtrl);
drivers/net/ethernet/alteon/acenic.c
3162
writel(readl(®s->LocalCtrl) & ~EEPROM_CLK_OUT, ®s->LocalCtrl);
drivers/net/ethernet/alteon/acenic.c
615
writel(readl(®s->CpuCtrl) | CPU_HALT, ®s->CpuCtrl);
drivers/net/ethernet/alteon/acenic.c
617
writel(readl(®s->CpuBCtrl) | CPU_HALT, ®s->CpuBCtrl);
drivers/net/ethernet/alteon/acenic.c
622
writel(1, ®s->Mb0Lo);
drivers/net/ethernet/alteon/acenic.c
852
writel(*(u32 *)(cmd), ®s->CmdRng[idx]);
drivers/net/ethernet/alteon/acenic.c
855
writel(idx, ®s->CmdPrd);
drivers/net/ethernet/alteon/acenic.c
883
writel(HW_RESET | (HW_RESET << 24), ®s->HostCtrl);
drivers/net/ethernet/alteon/acenic.c
895
writel((WORD_SWAP | CLR_INT | ((WORD_SWAP | CLR_INT) << 24)),
drivers/net/ethernet/alteon/acenic.c
898
writel((CLR_INT | WORD_SWAP | ((CLR_INT | WORD_SWAP) << 24)),
drivers/net/ethernet/alteon/acenic.c
906
writel(readl(®s->CpuCtrl) | CPU_HALT, ®s->CpuCtrl);
drivers/net/ethernet/alteon/acenic.c
908
writel(0, ®s->Mb0Lo);
drivers/net/ethernet/alteon/acenic.c
919
writel(0, ®s->LocalCtrl);
drivers/net/ethernet/alteon/acenic.c
928
writel(readl(®s->CpuBCtrl) | CPU_HALT, ®s->CpuBCtrl);
drivers/net/ethernet/alteon/acenic.c
935
writel(SRAM_BANK_512K, ®s->LocalCtrl);
drivers/net/ethernet/alteon/acenic.c
936
writel(SYNC_SRAM_TIMING, ®s->MiscCfg);
drivers/net/ethernet/alteon/acenic.c
955
writel(ACE_BYTE_SWAP_DMA | ACE_WARN | ACE_FATAL | ACE_BYTE_SWAP_BD |
drivers/net/ethernet/alteon/acenic.c
958
writel(ACE_BYTE_SWAP_DMA | ACE_WARN | ACE_FATAL |
drivers/net/ethernet/alteon/acenic.c
988
writel(mac1, ®s->MacAddrHi);
drivers/net/ethernet/alteon/acenic.c
989
writel(mac2, ®s->MacAddrLo);
drivers/net/ethernet/alteon/acenic.h
727
writel(value, ®s->TxPrd);
drivers/net/ethernet/alteon/acenic.h
734
writel(value, ®s->TxPrd);
drivers/net/ethernet/alteon/acenic.h
746
writel(1, ®s->MaskInt);
drivers/net/ethernet/alteon/acenic.h
748
writel(readl(®s->HostCtrl) | MASK_INTS, ®s->HostCtrl);
drivers/net/ethernet/alteon/acenic.h
760
writel(0, ®s->MaskInt);
drivers/net/ethernet/alteon/acenic.h
762
writel(readl(®s->HostCtrl) & ~MASK_INTS, ®s->HostCtrl);
drivers/net/ethernet/altera/altera_tse.h
509
writel(val, paddr);
drivers/net/ethernet/amazon/ena/ena_com.c
1485
writel(depth, ena_dev->reg_bar + ENA_REGS_AENQ_HEAD_DB_OFF);
drivers/net/ethernet/amazon/ena/ena_com.c
156
writel(addr_low, ena_dev->reg_bar + ENA_REGS_AENQ_BASE_LO_OFF);
drivers/net/ethernet/amazon/ena/ena_com.c
157
writel(addr_high, ena_dev->reg_bar + ENA_REGS_AENQ_BASE_HI_OFF);
drivers/net/ethernet/amazon/ena/ena_com.c
164
writel(aenq_caps, ena_dev->reg_bar + ENA_REGS_AENQ_CAPS_OFF);
drivers/net/ethernet/amazon/ena/ena_com.c
1646
writel(mask_value, ena_dev->reg_bar + ENA_REGS_INTR_MASK_OFF);
drivers/net/ethernet/amazon/ena/ena_com.c
1858
writel(phc->req_id, ena_dev->reg_bar + phc->doorbell_offset);
drivers/net/ethernet/amazon/ena/ena_com.c
1945
writel(0x0, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_LO_OFF);
drivers/net/ethernet/amazon/ena/ena_com.c
1946
writel(0x0, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_HI_OFF);
drivers/net/ethernet/amazon/ena/ena_com.c
1962
writel(addr_low, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_LO_OFF);
drivers/net/ethernet/amazon/ena/ena_com.c
1963
writel(addr_high, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_HI_OFF);
drivers/net/ethernet/amazon/ena/ena_com.c
2013
writel(addr_low, ena_dev->reg_bar + ENA_REGS_AQ_BASE_LO_OFF);
drivers/net/ethernet/amazon/ena/ena_com.c
2014
writel(addr_high, ena_dev->reg_bar + ENA_REGS_AQ_BASE_HI_OFF);
drivers/net/ethernet/amazon/ena/ena_com.c
2019
writel(addr_low, ena_dev->reg_bar + ENA_REGS_ACQ_BASE_LO_OFF);
drivers/net/ethernet/amazon/ena/ena_com.c
2020
writel(addr_high, ena_dev->reg_bar + ENA_REGS_ACQ_BASE_HI_OFF);
drivers/net/ethernet/amazon/ena/ena_com.c
2034
writel(aq_caps, ena_dev->reg_bar + ENA_REGS_AQ_CAPS_OFF);
drivers/net/ethernet/amazon/ena/ena_com.c
2035
writel(acq_caps, ena_dev->reg_bar + ENA_REGS_ACQ_CAPS_OFF);
drivers/net/ethernet/amazon/ena/ena_com.c
2380
writel(reset_val, ena_dev->reg_bar + ENA_REGS_DEV_CTL_OFF);
drivers/net/ethernet/amazon/ena/ena_com.c
2393
writel(0, ena_dev->reg_bar + ENA_REGS_DEV_CTL_OFF);
drivers/net/ethernet/amazon/ena/ena_com.c
264
writel(admin_queue->sq.tail, admin_queue->sq.db_addr);
drivers/net/ethernet/amazon/ena/ena_com.c
821
writel(mmio_read_reg, ena_dev->reg_bar + ENA_REGS_MMIO_REG_READ_OFF);
drivers/net/ethernet/amazon/ena/ena_eth_com.h
160
writel(tail, io_sq->db_addr);
drivers/net/ethernet/amazon/ena/ena_eth_com.h
183
writel(numa_cfg.numa_cfg, io_cq->numa_node_cfg_reg);
drivers/net/ethernet/amazon/ena/ena_eth_com.h
71
writel(intr_reg->intr_control, io_cq->unmask_reg);
drivers/net/ethernet/amd/amd8111e.c
109
writel(PHY_RD_CMD | ((phy_id & 0x1f) << 21) |
drivers/net/ethernet/amd/amd8111e.c
1092
writel(INTREN, mmio + CMD0);
drivers/net/ethernet/amd/amd8111e.c
1106
writel(intr0, mmio + INT0);
drivers/net/ethernet/amd/amd8111e.c
1112
writel(RINTEN0, mmio + INTEN0);
drivers/net/ethernet/amd/amd8111e.c
1118
writel(RINTEN0, mmio + INTEN0);
drivers/net/ethernet/amd/amd8111e.c
1135
writel(VAL0 | INTREN, mmio + CMD0);
drivers/net/ethernet/amd/amd8111e.c
1284
writel(VAL1 | TDMD0, lp->mmio + CMD0);
drivers/net/ethernet/amd/amd8111e.c
1285
writel(VAL2 | RDMD0, lp->mmio + CMD0);
drivers/net/ethernet/amd/amd8111e.c
1325
writel(VAL2 | PROM, lp->mmio + CMD2);
drivers/net/ethernet/amd/amd8111e.c
1329
writel(PROM, lp->mmio + CMD2);
drivers/net/ethernet/amd/amd8111e.c
1344
writel(PROM, lp->mmio + CMD2);
drivers/net/ethernet/amd/amd8111e.c
138
writel(PHY_WR_CMD | ((phy_id & 0x1f) << 21) |
drivers/net/ethernet/amd/amd8111e.c
1532
writel(RUN, lp->mmio + CMD0);
drivers/net/ethernet/amd/amd8111e.c
1545
writel(VAL1 | MPPLBA, lp->mmio + CMD3);
drivers/net/ethernet/amd/amd8111e.c
1546
writel(VAL0 | MPEN_SW, lp->mmio + CMD7);
drivers/net/ethernet/amd/amd8111e.c
1557
writel(VAL0 | LCMODE_SW, lp->mmio + CMD7);
drivers/net/ethernet/amd/amd8111e.c
382
writel(VAL0|STINTEN, mmio+INTEN0);
drivers/net/ethernet/amd/amd8111e.c
383
writel((u32)DLY_INT_A_R0 | (event_count << 16) |
drivers/net/ethernet/amd/amd8111e.c
396
writel(VAL0 | STINTEN, mmio + INTEN0);
drivers/net/ethernet/amd/amd8111e.c
397
writel((u32)DLY_INT_B_T0 | (event_count << 16) |
drivers/net/ethernet/amd/amd8111e.c
402
writel(0, mmio + STVAL);
drivers/net/ethernet/amd/amd8111e.c
403
writel(STINTEN, mmio + INTEN0);
drivers/net/ethernet/amd/amd8111e.c
404
writel(0, mmio + DLY_INT_B);
drivers/net/ethernet/amd/amd8111e.c
405
writel(0, mmio + DLY_INT_A);
drivers/net/ethernet/amd/amd8111e.c
409
writel((u32)SOFT_TIMER_FREQ, mmio + STVAL); /* 0.5 sec */
drivers/net/ethernet/amd/amd8111e.c
410
writel(VAL0 | STINTEN, mmio + INTEN0);
drivers/net/ethernet/amd/amd8111e.c
428
writel(RUN, mmio + CMD0);
drivers/net/ethernet/amd/amd8111e.c
434
writel((u32)VAL1 | EN_PMGR, mmio + CMD3);
drivers/net/ethernet/amd/amd8111e.c
435
writel((u32)XPHYANE | XPHYRST, mmio + CTRL2);
drivers/net/ethernet/amd/amd8111e.c
442
writel(reg_val | XMTSP_128 | CACHE_ALIGN, mmio + CTRL1);
drivers/net/ethernet/amd/amd8111e.c
445
writel(APINT5EN | APINT4EN | APINT3EN | APINT2EN | APINT1EN |
drivers/net/ethernet/amd/amd8111e.c
449
writel(VAL3 | LCINTEN | VAL1 | TINTEN0 | VAL0 | RINTEN0, mmio + INTEN0);
drivers/net/ethernet/amd/amd8111e.c
452
writel((u32)lp->tx_ring_dma_addr, mmio + XMT_RING_BASE_ADDR0);
drivers/net/ethernet/amd/amd8111e.c
453
writel((u32)lp->rx_ring_dma_addr, mmio + RCV_RING_BASE_ADDR0);
drivers/net/ethernet/amd/amd8111e.c
463
writel((u32)VAL2|JUMBO, mmio + CMD3);
drivers/net/ethernet/amd/amd8111e.c
465
writel(REX_UFLO, mmio + CMD2);
drivers/net/ethernet/amd/amd8111e.c
467
writel(VAL0 | APAD_XMT | REX_RTRY, mmio + CMD2);
drivers/net/ethernet/amd/amd8111e.c
469
writel(VAL0 | APAD_XMT | REX_RTRY | REX_UFLO, mmio + CMD2);
drivers/net/ethernet/amd/amd8111e.c
470
writel((u32)JUMBO, mmio + CMD3);
drivers/net/ethernet/amd/amd8111e.c
474
writel((u32)VAL2 | VSIZE | VL_TAG_DEL, mmio + CMD3);
drivers/net/ethernet/amd/amd8111e.c
476
writel(VAL0 | APAD_XMT | REX_RTRY, mmio + CMD2);
drivers/net/ethernet/amd/amd8111e.c
489
writel(VAL2 | RDMD0, mmio + CMD0);
drivers/net/ethernet/amd/amd8111e.c
490
writel(VAL0 | INTREN | RUN, mmio + CMD0);
drivers/net/ethernet/amd/amd8111e.c
506
writel(RUN, mmio + CMD0);
drivers/net/ethernet/amd/amd8111e.c
512
writel(0, mmio + RCV_RING_BASE_ADDR0);
drivers/net/ethernet/amd/amd8111e.c
515
writel(0, mmio + XMT_RING_BASE_ADDR0);
drivers/net/ethernet/amd/amd8111e.c
516
writel(0, mmio + XMT_RING_BASE_ADDR1);
drivers/net/ethernet/amd/amd8111e.c
517
writel(0, mmio + XMT_RING_BASE_ADDR2);
drivers/net/ethernet/amd/amd8111e.c
518
writel(0, mmio + XMT_RING_BASE_ADDR3);
drivers/net/ethernet/amd/amd8111e.c
521
writel(CMD0_CLEAR, mmio + CMD0);
drivers/net/ethernet/amd/amd8111e.c
524
writel(CMD2_CLEAR, mmio + CMD2);
drivers/net/ethernet/amd/amd8111e.c
527
writel(CMD7_CLEAR, mmio + CMD7);
drivers/net/ethernet/amd/amd8111e.c
530
writel(0x0, mmio + DLY_INT_A);
drivers/net/ethernet/amd/amd8111e.c
531
writel(0x0, mmio + DLY_INT_B);
drivers/net/ethernet/amd/amd8111e.c
534
writel(0x0, mmio + FLOW_CONTROL);
drivers/net/ethernet/amd/amd8111e.c
538
writel(reg_val, mmio + INT0);
drivers/net/ethernet/amd/amd8111e.c
541
writel(0x0, mmio + STVAL);
drivers/net/ethernet/amd/amd8111e.c
544
writel(INTEN0_CLEAR, mmio + INTEN0);
drivers/net/ethernet/amd/amd8111e.c
547
writel(0x0, mmio + LADRF);
drivers/net/ethernet/amd/amd8111e.c
550
writel(0x80010, mmio + SRAM_SIZE);
drivers/net/ethernet/amd/amd8111e.c
553
writel(0x0, mmio + RCV_RING_LEN0);
drivers/net/ethernet/amd/amd8111e.c
556
writel(0x0, mmio + XMT_RING_LEN0);
drivers/net/ethernet/amd/amd8111e.c
557
writel(0x0, mmio + XMT_RING_LEN1);
drivers/net/ethernet/amd/amd8111e.c
558
writel(0x0, mmio + XMT_RING_LEN2);
drivers/net/ethernet/amd/amd8111e.c
559
writel(0x0, mmio + XMT_RING_LEN3);
drivers/net/ethernet/amd/amd8111e.c
562
writel(0x0, mmio + XMT_RING_LIMIT);
drivers/net/ethernet/amd/amd8111e.c
574
writel(VAL2 | JUMBO, mmio + CMD3);
drivers/net/ethernet/amd/amd8111e.c
576
writel(VAL2 | VSIZE | VL_TAG_DEL, mmio + CMD3);
drivers/net/ethernet/amd/amd8111e.c
579
writel(CTRL1_DEFAULT, mmio + CTRL1);
drivers/net/ethernet/amd/amd8111e.c
594
writel(INTREN, lp->mmio + CMD0);
drivers/net/ethernet/amd/amd8111e.c
598
writel(intr0, lp->mmio + INT0);
drivers/net/ethernet/amd/amd8111e.c
608
writel(RUN, lp->mmio + CMD0);
drivers/net/ethernet/amd/amd8111e.c
783
writel(VAL0|RINTEN0, mmio + INTEN0);
drivers/net/ethernet/amd/amd8111e.c
784
writel(VAL2 | RDMD0, mmio + CMD0);
drivers/net/ethernet/amd/amd8111e.h
781
writel(*(u32*)(&_UlData), _memMap); \
drivers/net/ethernet/amd/amd8111e.h
782
writel(*(u32*)((u8*)(&_UlData)+4), _memMap+4)
drivers/net/ethernet/amd/au1000_eth.c
1041
writel(mc_filter[1], &aup->mac->multi_hash_high);
drivers/net/ethernet/amd/au1000_eth.c
1042
writel(mc_filter[0], &aup->mac->multi_hash_low);
drivers/net/ethernet/amd/au1000_eth.c
1046
writel(reg, &aup->mac->control);
drivers/net/ethernet/amd/au1000_eth.c
1171
writel(0, aup->enable);
drivers/net/ethernet/amd/au1000_eth.c
252
writel(MAC_EN_CLOCK_ENABLE, aup->enable);
drivers/net/ethernet/amd/au1000_eth.c
255
writel((MAC_EN_RESET0 | MAC_EN_RESET1 | MAC_EN_RESET2
drivers/net/ethernet/amd/au1000_eth.c
288
writel(mii_control, mii_control_reg);
drivers/net/ethernet/amd/au1000_eth.c
321
writel(value, mii_data_reg);
drivers/net/ethernet/amd/au1000_eth.c
322
writel(mii_control, mii_control_reg);
drivers/net/ethernet/amd/au1000_eth.c
372
writel(reg, &aup->mac->control);
drivers/net/ethernet/amd/au1000_eth.c
386
writel(reg, &aup->mac->control);
drivers/net/ethernet/amd/au1000_eth.c
437
writel(reg, &aup->mac->control);
drivers/net/ethernet/amd/au1000_eth.c
589
writel(MAC_EN_CLOCK_ENABLE, aup->enable);
drivers/net/ethernet/amd/au1000_eth.c
592
writel(0, aup->enable);
drivers/net/ethernet/amd/au1000_eth.c
702
writel(0, &aup->mac->control);
drivers/net/ethernet/amd/au1000_eth.c
707
writel(dev->dev_addr[5]<<8 | dev->dev_addr[4],
drivers/net/ethernet/amd/au1000_eth.c
709
writel(dev->dev_addr[3]<<24 | dev->dev_addr[2]<<16 |
drivers/net/ethernet/amd/au1000_eth.c
732
writel(control, &aup->mac->control);
drivers/net/ethernet/amd/au1000_eth.c
733
writel(0x8100, &aup->mac->vlan1_tag); /* activate vlan support */
drivers/net/ethernet/apm/xgene/xgene_enet_cle.c
745
writel(val, base + RSS_CTRL0 + offset);
drivers/net/ethernet/aquantia/atlantic/aq_hw_utils.c
54
writel(value, hw->mmio + reg);
drivers/net/ethernet/atheros/alx/hw.h
533
writel(val, hw->hw_addr + reg);
drivers/net/ethernet/atheros/atl1c/atl1c.h
550
writel((value), ((a)->hw_addr + reg)))
drivers/net/ethernet/atheros/atl1c/atl1c.h
583
writel((value), (((a)->hw_addr + reg) + ((offset) << 2))))
drivers/net/ethernet/atheros/atl1e/atl1e.h
458
writel((value), ((a)->hw_addr + reg)))
drivers/net/ethernet/atheros/atl1e/atl1e.h
479
writel((value), (((a)->hw_addr + reg) + ((offset) << 2))))
drivers/net/ethernet/broadcom/bcm4908_enet.c
100
writel(value, enet->base + offset);
drivers/net/ethernet/broadcom/bgmac-platform.c
127
writel(NICPM_PADRING_CFG_INIT_VAL,
drivers/net/ethernet/broadcom/bgmac-platform.c
146
writel(val, bgmac->plat.nicpm_base + NICPM_IOMUX_CTRL);
drivers/net/ethernet/broadcom/bgmac-platform.c
43
writel(value, bgmac->plat.base + offset);
drivers/net/ethernet/broadcom/bgmac-platform.c
53
writel(value, bgmac->plat.idm_base + offset);
drivers/net/ethernet/broadcom/bnge/bnge_hwrm.c
330
writel(0, bd->bar0 + bar_offset + i);
drivers/net/ethernet/broadcom/bnge/bnge_hwrm.c
333
writel(1, bd->bar0 + doorbell_offset);
drivers/net/ethernet/broadcom/bnx2.c
5684
writel(0, bp->regview + offset);
drivers/net/ethernet/broadcom/bnx2.c
5695
writel(0xffffffff, bp->regview + offset);
drivers/net/ethernet/broadcom/bnx2.c
5706
writel(save_val, bp->regview + offset);
drivers/net/ethernet/broadcom/bnx2.c
5710
writel(save_val, bp->regview + offset);
drivers/net/ethernet/broadcom/bnx2.h
7010
writel(val, bp->regview + offset)
drivers/net/ethernet/broadcom/bnx2x/bnx2x.h
181
#define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset))
drivers/net/ethernet/broadcom/bnx2x/bnx2x_vfpf.c
164
writel(U64_LO(msg_mapping),
drivers/net/ethernet/broadcom/bnx2x/bnx2x_vfpf.c
166
writel(U64_HI(msg_mapping),
drivers/net/ethernet/broadcom/bnxt/bnxt.c
15052
writel(reg_off & BNXT_GRC_BASE_MASK,
drivers/net/ethernet/broadcom/bnxt/bnxt.c
15057
writel(val, bp->bar0 + reg_off);
drivers/net/ethernet/broadcom/bnxt/bnxt.c
15060
writel(val, bp->bar1 + reg_off);
drivers/net/ethernet/broadcom/bnxt/bnxt.c
330
writel(DB_CP_FLAGS | DB_RING_IDX(db, idx), (db)->doorbell)
drivers/net/ethernet/broadcom/bnxt/bnxt.c
341
writel(DB_CP_REARM_FLAGS | DB_RING_IDX(db, idx), (db)->doorbell)
drivers/net/ethernet/broadcom/bnxt/bnxt.c
9977
writel(reg & BNXT_GRC_BASE_MASK, bp->bar0 +
drivers/net/ethernet/broadcom/bnxt/bnxt.h
2887
writel(db_val, db->doorbell);
drivers/net/ethernet/broadcom/bnxt/bnxt.h
2889
writel(db_val, db->doorbell);
drivers/net/ethernet/broadcom/bnxt/bnxt_hwrm.c
534
writel(0, bp->bar0 + bar_offset + i);
drivers/net/ethernet/broadcom/bnxt/bnxt_hwrm.c
537
writel(1, bp->bar0 + doorbell_offset);
drivers/net/ethernet/broadcom/bnxt/bnxt_ptp.c
665
writel(reg_base, bp->bar0 + win_off);
drivers/net/ethernet/broadcom/bnxt/bnxt_ptp.c
698
writel(0, bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT +
drivers/net/ethernet/broadcom/cnic_if.h
354
#define CNIC_WR(dev, off, val) writel(val, dev->regview + off)
drivers/net/ethernet/broadcom/tg3.c
16908
writel(0x00000000, sram_base);
drivers/net/ethernet/broadcom/tg3.c
16909
writel(0x00000000, sram_base + 4);
drivers/net/ethernet/broadcom/tg3.c
16910
writel(0xffffffff, sram_base + 4);
drivers/net/ethernet/broadcom/tg3.c
473
writel(val, tp->regs + off);
drivers/net/ethernet/broadcom/tg3.c
483
writel(val, tp->aperegs + off);
drivers/net/ethernet/broadcom/tg3.c
503
writel(val, tp->regs + off);
drivers/net/ethernet/broadcom/tg3.c
597
writel(val, mbox);
drivers/net/ethernet/broadcom/tg3.c
599
writel(val, mbox);
drivers/net/ethernet/broadcom/tg3.c
612
writel(val, tp->regs + off + GRCMBOX_BASE);
drivers/net/ethernet/brocade/bna/bfa_ioc.c
1121
writel(1, sem_reg);
drivers/net/ethernet/brocade/bna/bfa_ioc.c
1132
writel(pgnum, ioc->ioc_regs.host_page_num_fn);
drivers/net/ethernet/brocade/bna/bfa_ioc.c
1135
writel(0, ioc->ioc_regs.smem_page_start + loff);
drivers/net/ethernet/brocade/bna/bfa_ioc.c
1156
writel(1, ioc->ioc_regs.ioc_init_sem_reg);
drivers/net/ethernet/brocade/bna/bfa_ioc.c
1163
writel(1, ioc->ioc_regs.ioc_init_sem_reg);
drivers/net/ethernet/brocade/bna/bfa_ioc.c
1175
writel(1, ioc->ioc_regs.ioc_sem_reg);
drivers/net/ethernet/brocade/bna/bfa_ioc.c
1178
writel(1, ioc->ioc_regs.ioc_init_sem_reg);
drivers/net/ethernet/brocade/bna/bfa_ioc.c
1207
writel(1, ioc->ioc_regs.ioc_sem_reg);
drivers/net/ethernet/brocade/bna/bfa_ioc.c
1232
writel(pss_ctl, ioc->ioc_regs.pss_ctl_reg);
drivers/net/ethernet/brocade/bna/bfa_ioc.c
1250
writel(pss_ctl, ioc->ioc_regs.pss_ctl_reg);
drivers/net/ethernet/brocade/bna/bfa_ioc.c
1264
writel(pss_ctl, ioc->ioc_regs.pss_ctl_reg);
drivers/net/ethernet/brocade/bna/bfa_ioc.c
1278
writel(pss_ctl, ioc->ioc_regs.pss_ctl_reg);
drivers/net/ethernet/brocade/bna/bfa_ioc.c
1291
writel(pgnum, ioc->ioc_regs.host_page_num_fn);
drivers/net/ethernet/brocade/bna/bfa_ioc.c
1508
writel(cmd.i, (pci_bar + FLI_CMD_REG));
drivers/net/ethernet/brocade/bna/bfa_ioc.c
1518
writel(addr.i, (pci_bar + FLI_ADDR_REG));
drivers/net/ethernet/brocade/bna/bfa_ioc.c
1687
writel(0, (bar + FLASH_SEM_LOCK_REG));
drivers/net/ethernet/brocade/bna/bfa_ioc.c
1824
writel(1, ioc->ioc_regs.lpu_mbox_cmd);
drivers/net/ethernet/brocade/bna/bfa_ioc.c
1904
writel(cpu_to_le32(msgp[i]),
drivers/net/ethernet/brocade/bna/bfa_ioc.c
1908
writel(0, ioc->ioc_regs.hfn_mbox + i * sizeof(u32));
drivers/net/ethernet/brocade/bna/bfa_ioc.c
1913
writel(1, ioc->ioc_regs.hfn_mbox_cmd);
drivers/net/ethernet/brocade/bna/bfa_ioc.c
2021
writel(pgnum, ioc->ioc_regs.host_page_num_fn);
drivers/net/ethernet/brocade/bna/bfa_ioc.c
2045
writel(swab32(fwimg[BFA_IOC_FLASH_OFFSET_IN_CHUNK(i)]),
drivers/net/ethernet/brocade/bna/bfa_ioc.c
2056
writel(pgnum,
drivers/net/ethernet/brocade/bna/bfa_ioc.c
2061
writel(bfa_ioc_smem_pgnum(ioc, 0),
drivers/net/ethernet/brocade/bna/bfa_ioc.c
2073
writel(asicmode, ((ioc->ioc_regs.smem_page_start)
drivers/net/ethernet/brocade/bna/bfa_ioc.c
2075
writel(boot_type, ((ioc->ioc_regs.smem_page_start)
drivers/net/ethernet/brocade/bna/bfa_ioc.c
2077
writel(boot_env, ((ioc->ioc_regs.smem_page_start)
drivers/net/ethernet/brocade/bna/bfa_ioc.c
2205
writel(pgnum, ioc->ioc_regs.host_page_num_fn);
drivers/net/ethernet/brocade/bna/bfa_ioc.c
2219
writel(pgnum, ioc->ioc_regs.host_page_num_fn);
drivers/net/ethernet/brocade/bna/bfa_ioc.c
2223
writel(PSS_SMEM_PGNUM(ioc->ioc_regs.smem_pg0, 0),
drivers/net/ethernet/brocade/bna/bfa_ioc.c
2230
writel(1, ioc->ioc_regs.ioc_init_sem_reg);
drivers/net/ethernet/brocade/bna/bfa_ioc.c
2429
writel(1, ioc->ioc_regs.lpu_mbox_cmd);
drivers/net/ethernet/brocade/bna/bfa_ioc_ct.c
131
writel(1, ioc->ioc_regs.ioc_usage_reg);
drivers/net/ethernet/brocade/bna/bfa_ioc_ct.c
133
writel(0, ioc->ioc_regs.ioc_fail_sync);
drivers/net/ethernet/brocade/bna/bfa_ioc_ct.c
157
writel(usecnt, ioc->ioc_regs.ioc_usage_reg);
drivers/net/ethernet/brocade/bna/bfa_ioc_ct.c
182
writel(usecnt, ioc->ioc_regs.ioc_usage_reg);
drivers/net/ethernet/brocade/bna/bfa_ioc_ct.c
191
writel(__FW_INIT_HALT_P, ioc->ioc_regs.ll_halt);
drivers/net/ethernet/brocade/bna/bfa_ioc_ct.c
192
writel(__FW_INIT_HALT_P, ioc->ioc_regs.alt_ll_halt);
drivers/net/ethernet/brocade/bna/bfa_ioc_ct.c
419
writel(r32, rb + FNC_PERS_REG);
drivers/net/ethernet/brocade/bna/bfa_ioc_ct.c
429
writel(1, ioc->ioc_regs.lpu_read_stat);
drivers/net/ethernet/brocade/bna/bfa_ioc_ct.c
452
writel(r32 & __MSIX_VT_OFST_,
drivers/net/ethernet/brocade/bna/bfa_ioc_ct.c
457
writel(__MSIX_VT_NUMVT_(HOSTFN_MSIX_DEFAULT - 1) |
drivers/net/ethernet/brocade/bna/bfa_ioc_ct.c
460
writel(HOSTFN_MSIX_DEFAULT * bfa_ioc_pcifn(ioc),
drivers/net/ethernet/brocade/bna/bfa_ioc_ct.c
469
writel(0, ioc->ioc_regs.ioc_usage_reg);
drivers/net/ethernet/brocade/bna/bfa_ioc_ct.c
496
writel(0, ioc->ioc_regs.ioc_fail_sync);
drivers/net/ethernet/brocade/bna/bfa_ioc_ct.c
497
writel(1, ioc->ioc_regs.ioc_usage_reg);
drivers/net/ethernet/brocade/bna/bfa_ioc_ct.c
498
writel(BFI_IOC_UNINIT, ioc->ioc_regs.ioc_fwstate);
drivers/net/ethernet/brocade/bna/bfa_ioc_ct.c
499
writel(BFI_IOC_UNINIT, ioc->ioc_regs.alt_ioc_fwstate);
drivers/net/ethernet/brocade/bna/bfa_ioc_ct.c
512
writel((r32 | sync_pos), ioc->ioc_regs.ioc_fail_sync);
drivers/net/ethernet/brocade/bna/bfa_ioc_ct.c
522
writel((r32 & ~sync_msk), ioc->ioc_regs.ioc_fail_sync);
drivers/net/ethernet/brocade/bna/bfa_ioc_ct.c
530
writel(r32 | bfa_ioc_ct_sync_pos(ioc), ioc->ioc_regs.ioc_fail_sync);
drivers/net/ethernet/brocade/bna/bfa_ioc_ct.c
556
writel(bfa_ioc_ct_clear_sync_ackd(r32),
drivers/net/ethernet/brocade/bna/bfa_ioc_ct.c
558
writel(BFI_IOC_FAIL, ioc->ioc_regs.ioc_fwstate);
drivers/net/ethernet/brocade/bna/bfa_ioc_ct.c
559
writel(BFI_IOC_FAIL, ioc->ioc_regs.alt_ioc_fwstate);
drivers/net/ethernet/brocade/bna/bfa_ioc_ct.c
569
writel((r32 | sync_ackd), ioc->ioc_regs.ioc_fail_sync);
drivers/net/ethernet/brocade/bna/bfa_ioc_ct.c
578
writel(fwstate, ioc->ioc_regs.ioc_fwstate);
drivers/net/ethernet/brocade/bna/bfa_ioc_ct.c
591
writel(fwstate, ioc->ioc_regs.alt_ioc_fwstate);
drivers/net/ethernet/brocade/bna/bfa_ioc_ct.c
616
writel(0, (rb + OP_MODE));
drivers/net/ethernet/brocade/bna/bfa_ioc_ct.c
617
writel(__APP_EMS_CMLCKSEL |
drivers/net/ethernet/brocade/bna/bfa_ioc_ct.c
622
writel(__GLOBAL_FCOE_MODE, (rb + OP_MODE));
drivers/net/ethernet/brocade/bna/bfa_ioc_ct.c
623
writel(__APP_EMS_REFCKBUFEN1,
drivers/net/ethernet/brocade/bna/bfa_ioc_ct.c
626
writel(BFI_IOC_UNINIT, (rb + BFA_IOC0_STATE_REG));
drivers/net/ethernet/brocade/bna/bfa_ioc_ct.c
627
writel(BFI_IOC_UNINIT, (rb + BFA_IOC1_STATE_REG));
drivers/net/ethernet/brocade/bna/bfa_ioc_ct.c
628
writel(0xffffffffU, (rb + HOSTFN0_INT_MSK));
drivers/net/ethernet/brocade/bna/bfa_ioc_ct.c
629
writel(0xffffffffU, (rb + HOSTFN1_INT_MSK));
drivers/net/ethernet/brocade/bna/bfa_ioc_ct.c
630
writel(0xffffffffU, (rb + HOSTFN0_INT_STATUS));
drivers/net/ethernet/brocade/bna/bfa_ioc_ct.c
631
writel(0xffffffffU, (rb + HOSTFN1_INT_STATUS));
drivers/net/ethernet/brocade/bna/bfa_ioc_ct.c
632
writel(0xffffffffU, (rb + HOSTFN0_INT_MSK));
drivers/net/ethernet/brocade/bna/bfa_ioc_ct.c
633
writel(0xffffffffU, (rb + HOSTFN1_INT_MSK));
drivers/net/ethernet/brocade/bna/bfa_ioc_ct.c
634
writel(pll_sclk |
drivers/net/ethernet/brocade/bna/bfa_ioc_ct.c
637
writel(pll_fclk |
drivers/net/ethernet/brocade/bna/bfa_ioc_ct.c
640
writel(pll_sclk |
drivers/net/ethernet/brocade/bna/bfa_ioc_ct.c
643
writel(pll_fclk |
drivers/net/ethernet/brocade/bna/bfa_ioc_ct.c
648
writel(0xffffffffU, (rb + HOSTFN0_INT_STATUS));
drivers/net/ethernet/brocade/bna/bfa_ioc_ct.c
649
writel(0xffffffffU, (rb + HOSTFN1_INT_STATUS));
drivers/net/ethernet/brocade/bna/bfa_ioc_ct.c
650
writel(pll_sclk |
drivers/net/ethernet/brocade/bna/bfa_ioc_ct.c
653
writel(pll_fclk |
drivers/net/ethernet/brocade/bna/bfa_ioc_ct.c
658
writel(__PMM_1T_RESET_P, (rb + PMM_1T_RESET_REG_P0));
drivers/net/ethernet/brocade/bna/bfa_ioc_ct.c
659
writel(__PMM_1T_RESET_P, (rb + PMM_1T_RESET_REG_P1));
drivers/net/ethernet/brocade/bna/bfa_ioc_ct.c
663
writel(r32, (rb + PSS_CTL_REG));
drivers/net/ethernet/brocade/bna/bfa_ioc_ct.c
666
writel(0, (rb + PMM_1T_RESET_REG_P0));
drivers/net/ethernet/brocade/bna/bfa_ioc_ct.c
667
writel(0, (rb + PMM_1T_RESET_REG_P1));
drivers/net/ethernet/brocade/bna/bfa_ioc_ct.c
670
writel(__EDRAM_BISTR_START, (rb + MBIST_CTL_REG));
drivers/net/ethernet/brocade/bna/bfa_ioc_ct.c
673
writel(0, (rb + MBIST_CTL_REG));
drivers/net/ethernet/brocade/bna/bfa_ioc_ct.c
689
writel(r32, (rb + CT2_APP_PLL_SCLK_CTL_REG));
drivers/net/ethernet/brocade/bna/bfa_ioc_ct.c
697
writel(r32, (rb + CT2_APP_PLL_SCLK_CTL_REG));
drivers/net/ethernet/brocade/bna/bfa_ioc_ct.c
703
writel(r32 | __ETH_CLK_ENABLE_PORT0,
drivers/net/ethernet/brocade/bna/bfa_ioc_ct.c
707
writel(r32 | __ETH_CLK_ENABLE_PORT1,
drivers/net/ethernet/brocade/bna/bfa_ioc_ct.c
716
writel(r32 | 0x1061731b, rb + CT2_APP_PLL_SCLK_CTL_REG);
drivers/net/ethernet/brocade/bna/bfa_ioc_ct.c
741
writel(r32, rb + CT2_APP_PLL_LCLK_CTL_REG);
drivers/net/ethernet/brocade/bna/bfa_ioc_ct.c
747
writel(r32, (rb + CT2_CHIP_MISC_PRG));
drivers/net/ethernet/brocade/bna/bfa_ioc_ct.c
753
writel(r32, rb + CT2_APP_PLL_LCLK_CTL_REG);
drivers/net/ethernet/brocade/bna/bfa_ioc_ct.c
761
writel(r32, (rb + CT2_APP_PLL_LCLK_CTL_REG));
drivers/net/ethernet/brocade/bna/bfa_ioc_ct.c
776
writel(r32, rb + PSS_CTL_REG);
drivers/net/ethernet/brocade/bna/bfa_ioc_ct.c
779
writel(__EDRAM_BISTR_START, rb + CT2_MBIST_CTL_REG);
drivers/net/ethernet/brocade/bna/bfa_ioc_ct.c
781
writel(0, rb + CT2_MBIST_CTL_REG);
drivers/net/ethernet/brocade/bna/bfa_ioc_ct.c
796
writel(r32 & ~__APP_PLL_SCLK_LOGIC_SOFT_RESET,
drivers/net/ethernet/brocade/bna/bfa_ioc_ct.c
803
writel(r32 & ~__APP_PLL_LCLK_LOGIC_SOFT_RESET,
drivers/net/ethernet/brocade/bna/bfa_ioc_ct.c
807
writel(__CSI_MAC_RESET | __CSI_MAC_AHB_RESET,
drivers/net/ethernet/brocade/bna/bfa_ioc_ct.c
809
writel(__CSI_MAC_RESET | __CSI_MAC_AHB_RESET,
drivers/net/ethernet/brocade/bna/bfa_ioc_ct.c
835
writel(__HALT_NFC_CONTROLLER, rb + CT2_NFC_CSR_CLR_REG);
drivers/net/ethernet/brocade/bna/bfa_ioc_ct.c
859
writel(__RESET_AND_START_SCLK_LCLK_PLLS,
drivers/net/ethernet/brocade/bna/bfa_ioc_ct.c
880
writel(__HALT_NFC_CONTROLLER, (rb + CT2_NFC_CSR_SET_REG));
drivers/net/ethernet/brocade/bna/bfa_ioc_ct.c
894
writel(r32 & ~__APP_PLL_SCLK_LOGIC_SOFT_RESET,
drivers/net/ethernet/brocade/bna/bfa_ioc_ct.c
897
writel(r32 & ~__APP_PLL_LCLK_LOGIC_SOFT_RESET,
drivers/net/ethernet/brocade/bna/bfa_ioc_ct.c
904
writel(r32 & ~1, rb + PSS_GPIO_OUT_REG);
drivers/net/ethernet/brocade/bna/bfa_ioc_ct.c
906
writel(r32 | 1, rb + PSS_GPIO_OE_REG);
drivers/net/ethernet/brocade/bna/bfa_ioc_ct.c
913
writel(1, rb + CT2_LPU0_HOSTFN_MBOX0_MSK);
drivers/net/ethernet/brocade/bna/bfa_ioc_ct.c
914
writel(1, rb + CT2_LPU1_HOSTFN_MBOX0_MSK);
drivers/net/ethernet/brocade/bna/bfa_ioc_ct.c
921
writel(1, rb + CT2_LPU0_HOSTFN_CMD_STAT);
drivers/net/ethernet/brocade/bna/bfa_ioc_ct.c
926
writel(1, rb + CT2_LPU1_HOSTFN_CMD_STAT);
drivers/net/ethernet/brocade/bna/bfa_ioc_ct.c
933
writel(BFI_IOC_UNINIT, rb + CT2_BFA_IOC0_STATE_REG);
drivers/net/ethernet/brocade/bna/bfa_ioc_ct.c
934
writel(BFI_IOC_UNINIT, rb + CT2_BFA_IOC1_STATE_REG);
drivers/net/ethernet/brocade/bna/bna_hw_defs.h
159
writel(init_halt, (_bna)->ioceth.ioc.ioc_regs.ll_halt); \
drivers/net/ethernet/brocade/bna/bna_hw_defs.h
166
writel(0xffffffff, (_bna)->regs.fn_int_mask); \
drivers/net/ethernet/brocade/bna/bna_hw_defs.h
170
writel((new_mask), (bna)->regs.fn_int_mask)
drivers/net/ethernet/brocade/bna/bna_hw_defs.h
175
writel((mask | (bna)->bits.mbox_mask_bits | \
drivers/net/ethernet/brocade/bna/bna_hw_defs.h
184
writel((mask & ~((bna)->bits.mbox_mask_bits | \
drivers/net/ethernet/brocade/bna/bna_hw_defs.h
193
writel(((_status) & ~(_bna)->bits.mbox_status_bits), \
drivers/net/ethernet/brocade/bna/bna_hw_defs.h
225
(writel(BNA_DOORBELL_IB_INT_ACK(0, (_events)), \
drivers/net/ethernet/brocade/bna/bna_hw_defs.h
230
(writel(((_i_dbell)->doorbell_ack | (_events)), \
drivers/net/ethernet/brocade/bna/bna_hw_defs.h
252
writel(BNA_DOORBELL_IB_INT_DISABLE, \
drivers/net/ethernet/brocade/bna/bna_hw_defs.h
262
(writel(BNA_DOORBELL_Q_PRD_IDX((_tcb)->producer_index), \
drivers/net/ethernet/brocade/bna/bna_hw_defs.h
266
(writel(BNA_DOORBELL_Q_PRD_IDX((_rcb)->producer_index), \
drivers/net/ethernet/brocade/bna/bnad_debugfs.c
398
writel(val, reg_addr);
drivers/net/ethernet/calxeda/xgmac.c
1034
writel(DMA_INTR_DEFAULT_MASK, ioaddr + XGMAC_DMA_STATUS);
drivers/net/ethernet/calxeda/xgmac.c
1035
writel(DMA_INTR_DEFAULT_MASK, ioaddr + XGMAC_DMA_INTR_ENA);
drivers/net/ethernet/calxeda/xgmac.c
1053
writel(0, priv->base + XGMAC_DMA_INTR_ENA);
drivers/net/ethernet/calxeda/xgmac.c
1132
writel(1, priv->base + XGMAC_DMA_TX_POLL);
drivers/net/ethernet/calxeda/xgmac.c
1335
writel(hash_filter[i], ioaddr + XGMAC_HASH(i));
drivers/net/ethernet/calxeda/xgmac.c
1337
writel(value, ioaddr + XGMAC_FRAME_FILTER);
drivers/net/ethernet/calxeda/xgmac.c
1448
writel(XGMAC_MMC_CTRL_CNT_FRZ, base + XGMAC_MMC_CTRL);
drivers/net/ethernet/calxeda/xgmac.c
1467
writel(0, base + XGMAC_MMC_CTRL);
drivers/net/ethernet/calxeda/xgmac.c
1502
writel(ctrl, ioaddr + XGMAC_CONTROL);
drivers/net/ethernet/calxeda/xgmac.c
1734
writel(1, priv->base + XGMAC_ADDR_HIGH(31));
drivers/net/ethernet/calxeda/xgmac.c
1740
writel(0, priv->base + XGMAC_DMA_INTR_ENA);
drivers/net/ethernet/calxeda/xgmac.c
1853
writel(pmt, ioaddr + XGMAC_PMT);
drivers/net/ethernet/calxeda/xgmac.c
1867
writel(0, priv->base + XGMAC_DMA_INTR_ENA);
drivers/net/ethernet/calxeda/xgmac.c
1873
writel(value, priv->base + XGMAC_DMA_CONTROL);
drivers/net/ethernet/calxeda/xgmac.c
1895
writel(DMA_INTR_DEFAULT_MASK, ioaddr + XGMAC_DMA_STATUS);
drivers/net/ethernet/calxeda/xgmac.c
1896
writel(DMA_INTR_DEFAULT_MASK, ioaddr + XGMAC_DMA_INTR_ENA);
drivers/net/ethernet/calxeda/xgmac.c
509
writel(reg | XGMAC_OMR_FTF, ioaddr + XGMAC_OMR);
drivers/net/ethernet/calxeda/xgmac.c
592
writel(value, ioaddr + XGMAC_CONTROL);
drivers/net/ethernet/calxeda/xgmac.c
596
writel(value, ioaddr + XGMAC_DMA_CONTROL);
drivers/net/ethernet/calxeda/xgmac.c
603
writel(value, ioaddr + XGMAC_DMA_CONTROL);
drivers/net/ethernet/calxeda/xgmac.c
607
writel(value, ioaddr + XGMAC_CONTROL);
drivers/net/ethernet/calxeda/xgmac.c
617
writel(data, ioaddr + XGMAC_ADDR_HIGH(num));
drivers/net/ethernet/calxeda/xgmac.c
619
writel(data, ioaddr + XGMAC_ADDR_LOW(num));
drivers/net/ethernet/calxeda/xgmac.c
621
writel(0, ioaddr + XGMAC_ADDR_HIGH(num));
drivers/net/ethernet/calxeda/xgmac.c
622
writel(0, ioaddr + XGMAC_ADDR_LOW(num));
drivers/net/ethernet/calxeda/xgmac.c
661
writel(flow, priv->base + XGMAC_FLOW_CTRL);
drivers/net/ethernet/calxeda/xgmac.c
665
writel(reg, priv->base + XGMAC_OMR);
drivers/net/ethernet/calxeda/xgmac.c
667
writel(0, priv->base + XGMAC_FLOW_CTRL);
drivers/net/ethernet/calxeda/xgmac.c
671
writel(reg, priv->base + XGMAC_OMR);
drivers/net/ethernet/calxeda/xgmac.c
771
writel(priv->dma_tx_phy, priv->base + XGMAC_DMA_TX_BASE_ADDR);
drivers/net/ethernet/calxeda/xgmac.c
772
writel(priv->dma_rx_phy, priv->base + XGMAC_DMA_RX_BASE_ADDR);
drivers/net/ethernet/calxeda/xgmac.c
910
writel(0, priv->base + XGMAC_DMA_INTR_ENA);
drivers/net/ethernet/calxeda/xgmac.c
915
writel(reg & ~DMA_CONTROL_ST, priv->base + XGMAC_DMA_CONTROL);
drivers/net/ethernet/calxeda/xgmac.c
924
writel(priv->dma_tx_phy, priv->base + XGMAC_DMA_TX_BASE_ADDR);
drivers/net/ethernet/calxeda/xgmac.c
925
writel(reg | DMA_CONTROL_ST, priv->base + XGMAC_DMA_CONTROL);
drivers/net/ethernet/calxeda/xgmac.c
927
writel(DMA_STATUS_TU | DMA_STATUS_TPS | DMA_STATUS_NIS | DMA_STATUS_AIS,
drivers/net/ethernet/calxeda/xgmac.c
936
writel(DMA_INTR_DEFAULT_MASK, priv->base + XGMAC_DMA_STATUS);
drivers/net/ethernet/calxeda/xgmac.c
937
writel(DMA_INTR_DEFAULT_MASK, priv->base + XGMAC_DMA_INTR_ENA);
drivers/net/ethernet/calxeda/xgmac.c
952
writel(value, ioaddr + XGMAC_DMA_BUS_MODE);
drivers/net/ethernet/calxeda/xgmac.c
963
writel(value, ioaddr + XGMAC_DMA_BUS_MODE);
drivers/net/ethernet/calxeda/xgmac.c
965
writel(0, ioaddr + XGMAC_DMA_INTR_ENA);
drivers/net/ethernet/calxeda/xgmac.c
968
writel(XGMAC_INT_STAT_PMTIM, ioaddr + XGMAC_INT_STAT);
drivers/net/ethernet/calxeda/xgmac.c
971
writel(0x0077000E, ioaddr + XGMAC_DMA_AXI_BUS);
drivers/net/ethernet/calxeda/xgmac.c
977
writel(ctrl, ioaddr + XGMAC_CONTROL);
drivers/net/ethernet/calxeda/xgmac.c
979
writel(DMA_CONTROL_OSF, ioaddr + XGMAC_DMA_CONTROL);
drivers/net/ethernet/calxeda/xgmac.c
982
writel(XGMAC_OMR_TSF | XGMAC_OMR_RFD | XGMAC_OMR_RFA |
drivers/net/ethernet/calxeda/xgmac.c
987
writel(1, ioaddr + XGMAC_MMC_CTRL);
drivers/net/ethernet/cavium/liquidio/lio_core.c
562
writel(oct->droq[q_no]->max_count, oct->droq[q_no]->pkts_credit_reg);
drivers/net/ethernet/cavium/liquidio/lio_ethtool.c
1218
writel(oct->droq[i]->max_count,
drivers/net/ethernet/cavium/liquidio/lio_main.c
4224
writel(octeon_dev->droq[j]->max_count,
drivers/net/ethernet/cavium/liquidio/lio_vf_main.c
2399
writel(oct->droq[j]->max_count, oct->droq[j]->pkts_credit_reg);
drivers/net/ethernet/cavium/liquidio/octeon_device.c
1358
writel(addrhi, oct->reg_list.pci_win_rd_addr_hi);
drivers/net/ethernet/cavium/liquidio/octeon_device.c
1363
writel(addr & 0xffffffff, oct->reg_list.pci_win_rd_addr_lo);
drivers/net/ethernet/cavium/liquidio/octeon_device.c
1385
writel(val >> 32, oct->reg_list.pci_win_wr_data_hi);
drivers/net/ethernet/cavium/liquidio/octeon_device.c
1389
writel(val & 0xffffffff, oct->reg_list.pci_win_wr_data_lo);
drivers/net/ethernet/cavium/liquidio/octeon_device.c
1445
writel(droq->pkt_count - pkts_pend, droq->pkts_sent_reg);
drivers/net/ethernet/cavium/liquidio/octeon_device.c
1451
writel(iq->pkts_processed, iq->inst_cnt_reg);
drivers/net/ethernet/cavium/liquidio/octeon_device.h
734
writel(value, (oct_dev)->mmio[0].hw_addr + (reg_off))
drivers/net/ethernet/cavium/liquidio/octeon_droq.c
509
writel(desc_refilled, droq->pkts_credit_reg);
drivers/net/ethernet/cavium/liquidio/octeon_droq.c
706
writel(desc_refilled, droq->pkts_credit_reg);
drivers/net/ethernet/cavium/liquidio/request_manager.c
268
writel(iq->fill_cnt, iq->doorbell_reg);
drivers/net/ethernet/chelsio/cxgb/espi.c
102
writel(F_ESPI_RX_CORE_RST | F_ESPI_RX_LNK_RST,
drivers/net/ethernet/chelsio/cxgb/espi.c
120
writel(enable, espi->adapter->regs + A_ESPI_INTR_ENABLE);
drivers/net/ethernet/chelsio/cxgb/espi.c
121
writel(pl_intr | F_PL_INTR_ESPI, espi->adapter->regs + A_PL_ENABLE);
drivers/net/ethernet/chelsio/cxgb/espi.c
127
writel(0xffffffff, espi->adapter->regs + A_ESPI_INTR_STATUS);
drivers/net/ethernet/chelsio/cxgb/espi.c
128
writel(F_PL_INTR_ESPI, espi->adapter->regs + A_PL_CAUSE);
drivers/net/ethernet/chelsio/cxgb/espi.c
135
writel(0, espi->adapter->regs + A_ESPI_INTR_ENABLE);
drivers/net/ethernet/chelsio/cxgb/espi.c
136
writel(pl_intr & ~F_PL_INTR_ESPI, espi->adapter->regs + A_PL_ENABLE);
drivers/net/ethernet/chelsio/cxgb/espi.c
169
writel(status, espi->adapter->regs + A_ESPI_INTR_STATUS);
drivers/net/ethernet/chelsio/cxgb/espi.c
182
writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN0);
drivers/net/ethernet/chelsio/cxgb/espi.c
183
writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN1);
drivers/net/ethernet/chelsio/cxgb/espi.c
184
writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN2);
drivers/net/ethernet/chelsio/cxgb/espi.c
185
writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN3);
drivers/net/ethernet/chelsio/cxgb/espi.c
186
writel(0x100, adapter->regs + A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK);
drivers/net/ethernet/chelsio/cxgb/espi.c
187
writel(wmark, adapter->regs + A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK);
drivers/net/ethernet/chelsio/cxgb/espi.c
188
writel(3, adapter->regs + A_ESPI_CALENDAR_LENGTH);
drivers/net/ethernet/chelsio/cxgb/espi.c
189
writel(0x08000008, adapter->regs + A_ESPI_TRAIN);
drivers/net/ethernet/chelsio/cxgb/espi.c
190
writel(V_RX_NPORTS(1) | V_TX_NPORTS(1), adapter->regs + A_PORT_CONFIG);
drivers/net/ethernet/chelsio/cxgb/espi.c
195
writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN0);
drivers/net/ethernet/chelsio/cxgb/espi.c
196
writel(0x1f401f4, adapter->regs + A_ESPI_SCH_TOKEN1);
drivers/net/ethernet/chelsio/cxgb/espi.c
197
writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN2);
drivers/net/ethernet/chelsio/cxgb/espi.c
198
writel(0xa00, adapter->regs + A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK);
drivers/net/ethernet/chelsio/cxgb/espi.c
199
writel(0x1ff, adapter->regs + A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK);
drivers/net/ethernet/chelsio/cxgb/espi.c
200
writel(1, adapter->regs + A_ESPI_CALENDAR_LENGTH);
drivers/net/ethernet/chelsio/cxgb/espi.c
201
writel(V_RX_NPORTS(4) | V_TX_NPORTS(4), adapter->regs + A_PORT_CONFIG);
drivers/net/ethernet/chelsio/cxgb/espi.c
203
writel(0x08000008, adapter->regs + A_ESPI_TRAIN);
drivers/net/ethernet/chelsio/cxgb/espi.c
211
writel(1, adapter->regs + A_ESPI_CALENDAR_LENGTH);
drivers/net/ethernet/chelsio/cxgb/espi.c
214
writel(0xf00, adapter->regs + A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK);
drivers/net/ethernet/chelsio/cxgb/espi.c
215
writel(0x3c0, adapter->regs + A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK);
drivers/net/ethernet/chelsio/cxgb/espi.c
217
writel(0x7ff, adapter->regs + A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK);
drivers/net/ethernet/chelsio/cxgb/espi.c
218
writel(0x1ff, adapter->regs + A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK);
drivers/net/ethernet/chelsio/cxgb/espi.c
221
writel(0x1fff, adapter->regs + A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK);
drivers/net/ethernet/chelsio/cxgb/espi.c
222
writel(0x7ff, adapter->regs + A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK);
drivers/net/ethernet/chelsio/cxgb/espi.c
224
writel(V_RX_NPORTS(nports) | V_TX_NPORTS(nports), adapter->regs + A_PORT_CONFIG);
drivers/net/ethernet/chelsio/cxgb/espi.c
234
writel(0, adapter->regs + A_ESPI_TRAIN);
drivers/net/ethernet/chelsio/cxgb/espi.c
237
writel(V_OUT_OF_SYNC_COUNT(4) |
drivers/net/ethernet/chelsio/cxgb/espi.c
240
writel(nports == 4 ? 0x200040 : 0x1000080,
drivers/net/ethernet/chelsio/cxgb/espi.c
243
writel(0x800100, adapter->regs + A_ESPI_MAXBURST1_MAXBURST2);
drivers/net/ethernet/chelsio/cxgb/espi.c
255
writel(status_enable_extra | F_RXSTATUSENABLE,
drivers/net/ethernet/chelsio/cxgb/espi.c
269
writel(espi->misc_ctrl, adapter->regs + A_ESPI_MISC_CONTROL);
drivers/net/ethernet/chelsio/cxgb/espi.c
300
writel(espi->misc_ctrl, adapter->regs + A_ESPI_MISC_CONTROL);
drivers/net/ethernet/chelsio/cxgb/espi.c
321
writel(((espi->misc_ctrl & ~MON_MASK) | sel),
drivers/net/ethernet/chelsio/cxgb/espi.c
324
writel(espi->misc_ctrl, adapter->regs + A_ESPI_MISC_CONTROL);
drivers/net/ethernet/chelsio/cxgb/espi.c
350
writel(espi->misc_ctrl, adapter->regs + A_ESPI_MISC_CONTROL);
drivers/net/ethernet/chelsio/cxgb/espi.c
354
writel(espi->misc_ctrl | V_MONITORED_PORT_NUM(i),
drivers/net/ethernet/chelsio/cxgb/espi.c
360
writel(espi->misc_ctrl, adapter->regs + A_ESPI_MISC_CONTROL);
drivers/net/ethernet/chelsio/cxgb/espi.c
56
writel(V_WRITE_DATA(wr_data) |
drivers/net/ethernet/chelsio/cxgb/espi.c
62
writel(0, adapter->regs + A_ESPI_GOSTAT);
drivers/net/ethernet/chelsio/cxgb/espi.c
83
writel(F_ESPI_RX_CORE_RST, adapter->regs + A_ESPI_RX_RESET);
drivers/net/ethernet/chelsio/cxgb/pm3393.c
147
writel(pl_intr, cmac->adapter->regs + A_PL_ENABLE);
drivers/net/ethernet/chelsio/cxgb/pm3393.c
229
writel(pl_intr, cmac->adapter->regs + A_PL_CAUSE);
drivers/net/ethernet/chelsio/cxgb/sge.c
1341
writel(F_CMDQ0_ENABLE, adapter->regs + A_SG_DOORBELL);
drivers/net/ethernet/chelsio/cxgb/sge.c
1451
writel(F_CMDQ0_ENABLE, adapter->regs + A_SG_DOORBELL);
drivers/net/ethernet/chelsio/cxgb/sge.c
1532
writel(q->credits, adapter->regs + A_SG_RSPQUEUECREDIT);
drivers/net/ethernet/chelsio/cxgb/sge.c
1587
writel(q->credits, adapter->regs + A_SG_RSPQUEUECREDIT);
drivers/net/ethernet/chelsio/cxgb/sge.c
1611
writel(adapter->sge->respQ.cidx,
drivers/net/ethernet/chelsio/cxgb/sge.c
1644
writel(F_PL_INTR_EXT, adapter->regs + A_PL_CAUSE);
drivers/net/ethernet/chelsio/cxgb/sge.c
1645
writel(adapter->slow_intr_mask | F_PL_INTR_SGE_DATA,
drivers/net/ethernet/chelsio/cxgb/sge.c
1659
writel(F_PL_INTR_SGE_DATA, adapter->regs + A_PL_CAUSE);
drivers/net/ethernet/chelsio/cxgb/sge.c
1666
writel(sge->respQ.cidx, adapter->regs + A_SG_SLEEPING);
drivers/net/ethernet/chelsio/cxgb/sge.c
1776
writel(F_CMDQ0_ENABLE, adapter->regs + A_SG_DOORBELL);
drivers/net/ethernet/chelsio/cxgb/sge.c
1935
writel(F_CMDQ0_ENABLE, sge->adapter->regs + A_SG_DOORBELL);
drivers/net/ethernet/chelsio/cxgb/sge.c
1949
writel(sge->fixed_intrtimer, sge->adapter->regs + A_SG_INTRTIMER);
drivers/net/ethernet/chelsio/cxgb/sge.c
1983
writel(0, sge->adapter->regs + A_SG_CONTROL);
drivers/net/ethernet/chelsio/cxgb/sge.c
2005
writel(sge->sge_control, sge->adapter->regs + A_SG_CONTROL);
drivers/net/ethernet/chelsio/cxgb/sge.c
478
writel(F_CMDQ0_ENABLE, sge->adapter->regs + A_SG_DOORBELL);
drivers/net/ethernet/chelsio/cxgb/sge.c
492
writel(val, adapter->regs + A_SG_DOORBELL);
drivers/net/ethernet/chelsio/cxgb/sge.c
719
writel((u32)addr, adapter->regs + base_reg_lo);
drivers/net/ethernet/chelsio/cxgb/sge.c
720
writel(addr >> 32, adapter->regs + base_reg_hi);
drivers/net/ethernet/chelsio/cxgb/sge.c
721
writel(size, adapter->regs + size_reg);
drivers/net/ethernet/chelsio/cxgb/sge.c
736
writel(sge->sge_control, adapter->regs + A_SG_CONTROL);
drivers/net/ethernet/chelsio/cxgb/sge.c
749
writel(0, ap->regs + A_SG_CONTROL);
drivers/net/ethernet/chelsio/cxgb/sge.c
762
writel(SGE_RX_SM_BUF_SIZE + 1, ap->regs + A_SG_FLTHRESHOLD);
drivers/net/ethernet/chelsio/cxgb/sge.c
766
writel((u32)sge->respQ.size - 1, ap->regs + A_SG_RSPQUEUECREDIT);
drivers/net/ethernet/chelsio/cxgb/sge.c
885
writel(irqholdoff_reg, adapter->regs + A_SG_INTRTIMER);
drivers/net/ethernet/chelsio/cxgb/sge.c
886
writel(irq_reg, adapter->regs + A_SG_INT_ENABLE);
drivers/net/ethernet/chelsio/cxgb/sge.c
904
writel(val & ~SGE_PL_INTR_MASK, sge->adapter->regs + A_PL_ENABLE);
drivers/net/ethernet/chelsio/cxgb/sge.c
905
writel(0, sge->adapter->regs + A_SG_INT_ENABLE);
drivers/net/ethernet/chelsio/cxgb/sge.c
918
writel(en, sge->adapter->regs + A_SG_INT_ENABLE);
drivers/net/ethernet/chelsio/cxgb/sge.c
919
writel(val | SGE_PL_INTR_MASK, sge->adapter->regs + A_PL_ENABLE);
drivers/net/ethernet/chelsio/cxgb/sge.c
927
writel(SGE_PL_INTR_MASK, sge->adapter->regs + A_PL_CAUSE);
drivers/net/ethernet/chelsio/cxgb/sge.c
928
writel(0xffffffff, sge->adapter->regs + A_SG_INT_CAUSE);
drivers/net/ethernet/chelsio/cxgb/sge.c
968
writel(cause, adapter->regs + A_SG_INT_CAUSE);
drivers/net/ethernet/chelsio/cxgb/subr.c
105
writel(addr, adapter->regs + A_TPI_ADDR);
drivers/net/ethernet/chelsio/cxgb/subr.c
106
writel(0, adapter->regs + A_TPI_CSR);
drivers/net/ethernet/chelsio/cxgb/subr.c
133
writel(V_TPIPAR(value), adapter->regs + A_TPI_PAR);
drivers/net/ethernet/chelsio/cxgb/subr.c
201
writel(cause, adapter->regs + FPGA_GMAC_ADDR_INTERRUPT_CAUSE);
drivers/net/ethernet/chelsio/cxgb/subr.c
230
writel(tp_cause, adapter->regs + FPGA_TP_ADDR_INTERRUPT_CAUSE);
drivers/net/ethernet/chelsio/cxgb/subr.c
239
writel(cause, adapter->regs + A_PL_CAUSE);
drivers/net/ethernet/chelsio/cxgb/subr.c
76
writel(addr, adapter->regs + A_TPI_ADDR);
drivers/net/ethernet/chelsio/cxgb/subr.c
77
writel(value, adapter->regs + A_TPI_WR_DATA);
drivers/net/ethernet/chelsio/cxgb/subr.c
78
writel(F_TPIWR, adapter->regs + A_TPI_CSR);
drivers/net/ethernet/chelsio/cxgb/subr.c
787
writel(pl_intr, adapter->regs + A_PL_ENABLE);
drivers/net/ethernet/chelsio/cxgb/subr.c
809
writel(0, adapter->regs + A_PL_ENABLE);
drivers/net/ethernet/chelsio/cxgb/subr.c
837
writel(pl_intr | F_PL_INTR_EXT | F_PL_INTR_PCIX,
drivers/net/ethernet/chelsio/cxgb/subr.c
875
writel(adapter->slow_intr_mask | F_PL_INTR_SGE_DATA,
drivers/net/ethernet/chelsio/cxgb/subr.c
881
writel(cause, adapter->regs + A_PL_CAUSE);
drivers/net/ethernet/chelsio/cxgb/subr.c
987
writel(val | F_READY | F_MC4_SLOW, adapter->regs + A_MC4_CFG);
drivers/net/ethernet/chelsio/cxgb/subr.c
988
writel(F_M_BUS_ENABLE | F_TCAM_RESET,
drivers/net/ethernet/chelsio/cxgb/tp.c
100
writel(tp_intr & ~FPGA_PCIX_INTERRUPT_TP,
drivers/net/ethernet/chelsio/cxgb/tp.c
105
writel(0, tp->adapter->regs + A_TP_INT_ENABLE);
drivers/net/ethernet/chelsio/cxgb/tp.c
106
writel(tp_intr & ~F_PL_INTR_TP,
drivers/net/ethernet/chelsio/cxgb/tp.c
115
writel(0xffffffff,
drivers/net/ethernet/chelsio/cxgb/tp.c
117
writel(FPGA_PCIX_INTERRUPT_TP, tp->adapter->regs + A_PL_CAUSE);
drivers/net/ethernet/chelsio/cxgb/tp.c
121
writel(0xffffffff, tp->adapter->regs + A_TP_INT_CAUSE);
drivers/net/ethernet/chelsio/cxgb/tp.c
122
writel(F_PL_INTR_TP, tp->adapter->regs + A_PL_CAUSE);
drivers/net/ethernet/chelsio/cxgb/tp.c
136
writel(cause, tp->adapter->regs + A_TP_INT_CAUSE);
drivers/net/ethernet/chelsio/cxgb/tp.c
148
writel(val, tp->adapter->regs + A_TP_GLOBAL_CONFIG);
drivers/net/ethernet/chelsio/cxgb/tp.c
170
writel(F_TP_RESET, adapter->regs + A_TP_RESET);
drivers/net/ethernet/chelsio/cxgb/tp.c
32
writel(val, ap->regs + A_TP_IN_CONFIG);
drivers/net/ethernet/chelsio/cxgb/tp.c
33
writel(F_TP_OUT_CSPI_CPL |
drivers/net/ethernet/chelsio/cxgb/tp.c
37
writel(V_IP_TTL(64) |
drivers/net/ethernet/chelsio/cxgb/tp.c
47
writel(F_ENABLE_TX_DROP | F_ENABLE_TX_ERROR |
drivers/net/ethernet/chelsio/cxgb/tp.c
78
writel(0xffffffff,
drivers/net/ethernet/chelsio/cxgb/tp.c
80
writel(tp_intr | FPGA_PCIX_INTERRUPT_TP,
drivers/net/ethernet/chelsio/cxgb/tp.c
86
writel(0, tp->adapter->regs + A_TP_INT_ENABLE);
drivers/net/ethernet/chelsio/cxgb/tp.c
87
writel(tp_intr | F_PL_INTR_TP,
drivers/net/ethernet/chelsio/cxgb/tp.c
99
writel(0, tp->adapter->regs + FPGA_TP_ADDR_INTERRUPT_ENABLE);
drivers/net/ethernet/chelsio/cxgb3/adapter.h
281
writel(val, adapter->regs + reg_addr);
drivers/net/ethernet/chelsio/cxgb4/cxgb4.h
1509
writel(val, adap->regs + reg_addr);
drivers/net/ethernet/chelsio/cxgb4/cxgb4.h
1520
writel(val, addr);
drivers/net/ethernet/chelsio/cxgb4/cxgb4.h
1521
writel(val >> 32, addr + 4);
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
1313
writel(MBMSGVALID_F | MBOWNER_V(X_MBOWNER_FW), ctrl);
drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
2593
writel(PIDX_T5_V(pidx_inc) | QID_V(bar2_qid),
drivers/net/ethernet/chelsio/cxgb4/sge.c
1061
writel(val | QID_V(q->bar2_qid),
drivers/net/ethernet/chelsio/cxgb4/sge.c
4017
writel(val | INGRESSQID_V(q->bar2_qid),
drivers/net/ethernet/chelsio/cxgb4/sge.c
4179
writel(val | INGRESSQID_V(q->bar2_qid),
drivers/net/ethernet/chelsio/cxgb4/sge.c
502
writel(val | QID_V(q->bar2_qid),
drivers/net/ethernet/chelsio/cxgb4vf/adapter.h
445
writel(val, adapter->regs + reg_addr);
drivers/net/ethernet/chelsio/cxgb4vf/adapter.h
456
writel(val, addr);
drivers/net/ethernet/chelsio/cxgb4vf/adapter.h
457
writel(val >> 32, addr + 4);
drivers/net/ethernet/chelsio/cxgb4vf/sge.c
1024
writel(val | QID_V(tq->bar2_qid),
drivers/net/ethernet/chelsio/cxgb4vf/sge.c
1911
writel(val | INGRESSQID_V(rspq->bar2_qid),
drivers/net/ethernet/chelsio/cxgb4vf/sge.c
2013
writel(val | INGRESSQID_V(intrq->bar2_qid),
drivers/net/ethernet/chelsio/cxgb4vf/sge.c
553
writel(val | QID_V(fl->bar2_qid),
drivers/net/ethernet/cisco/enic/vnic_dev.h
26
writel(val & 0xffffffff, reg);
drivers/net/ethernet/cisco/enic/vnic_dev.h
27
writel(val >> 32, reg + 0x4UL);
drivers/net/ethernet/cortina/gemini.c
1003
writel(0, geth->base + GLOBAL_SW_FREEQ_BASE_SIZE_REG);
drivers/net/ethernet/cortina/gemini.c
1078
writel(en, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
drivers/net/ethernet/cortina/gemini.c
1095
writel(en, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
drivers/net/ethernet/cortina/gemini.c
1116
writel(mask, geth->base + GLOBAL_INTERRUPT_STATUS_0_REG);
drivers/net/ethernet/cortina/gemini.c
1120
writel(val, geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG);
drivers/net/ethernet/cortina/gemini.c
1365
writel(val, geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG);
drivers/net/ethernet/cortina/gemini.c
1370
writel(val, geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG);
drivers/net/ethernet/cortina/gemini.c
1375
writel(val, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
drivers/net/ethernet/cortina/gemini.c
1394
writel(val, geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG);
drivers/net/ethernet/cortina/gemini.c
1463
writel(DEFAULT_Q0_INT_BIT << netdev->dev_id,
drivers/net/ethernet/cortina/gemini.c
1679
writel(GMAC0_MIB_INT_BIT << (netdev->dev_id * 8),
drivers/net/ethernet/cortina/gemini.c
1770
writel(GMAC0_RXDERR_INT_BIT << (netdev->dev_id * 8),
drivers/net/ethernet/cortina/gemini.c
1799
writel(dma_ctrl.bits32, dma_ctrl_reg);
drivers/net/ethernet/cortina/gemini.c
1810
writel(dma_ctrl.bits32, dma_ctrl_reg);
drivers/net/ethernet/cortina/gemini.c
1921
writel(mc_filter[0], port->gmac_base + GMAC_MCAST_FIL0);
drivers/net/ethernet/cortina/gemini.c
1922
writel(mc_filter[1], port->gmac_base + GMAC_MCAST_FIL1);
drivers/net/ethernet/cortina/gemini.c
1923
writel(filter.bits32, port->gmac_base + GMAC_RX_FLTR);
drivers/net/ethernet/cortina/gemini.c
1934
writel(le32_to_cpu(addr[0]), port->gmac_base + GMAC_STA_ADD0);
drivers/net/ethernet/cortina/gemini.c
1935
writel(le32_to_cpu(addr[1]), port->gmac_base + GMAC_STA_ADD1);
drivers/net/ethernet/cortina/gemini.c
1936
writel(le32_to_cpu(addr[2]), port->gmac_base + GMAC_STA_ADD2);
drivers/net/ethernet/cortina/gemini.c
2042
writel(reg, port->gmac_base + GMAC_CONFIG0);
drivers/net/ethernet/cortina/gemini.c
2305
writel(irqmask, geth->base + GLOBAL_INTERRUPT_STATUS_4_REG);
drivers/net/ethernet/cortina/gemini.c
2308
writel(irqmask, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
drivers/net/ethernet/cortina/gemini.c
2334
writel(en, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
drivers/net/ethernet/cortina/gemini.c
236
writel(reg, port->gmac_base + GMAC_CONFIG0);
drivers/net/ethernet/cortina/gemini.c
2363
writel(0, geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG);
drivers/net/ethernet/cortina/gemini.c
2364
writel(0, geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG);
drivers/net/ethernet/cortina/gemini.c
2365
writel(0, geth->base + GLOBAL_INTERRUPT_ENABLE_2_REG);
drivers/net/ethernet/cortina/gemini.c
2366
writel(0, geth->base + GLOBAL_INTERRUPT_ENABLE_3_REG);
drivers/net/ethernet/cortina/gemini.c
2367
writel(0, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
drivers/net/ethernet/cortina/gemini.c
2379
writel(0xCCFC0FC0, geth->base + GLOBAL_INTERRUPT_SELECT_0_REG);
drivers/net/ethernet/cortina/gemini.c
2380
writel(0x00F00002, geth->base + GLOBAL_INTERRUPT_SELECT_1_REG);
drivers/net/ethernet/cortina/gemini.c
2381
writel(0xFFFFFFFF, geth->base + GLOBAL_INTERRUPT_SELECT_2_REG);
drivers/net/ethernet/cortina/gemini.c
2382
writel(0xFFFFFFFF, geth->base + GLOBAL_INTERRUPT_SELECT_3_REG);
drivers/net/ethernet/cortina/gemini.c
2383
writel(0xFF000003, geth->base + GLOBAL_INTERRUPT_SELECT_4_REG);
drivers/net/ethernet/cortina/gemini.c
2386
writel(~0, geth->base + GLOBAL_INTERRUPT_STATUS_0_REG);
drivers/net/ethernet/cortina/gemini.c
2387
writel(~0, geth->base + GLOBAL_INTERRUPT_STATUS_1_REG);
drivers/net/ethernet/cortina/gemini.c
2388
writel(~0, geth->base + GLOBAL_INTERRUPT_STATUS_2_REG);
drivers/net/ethernet/cortina/gemini.c
2389
writel(~0, geth->base + GLOBAL_INTERRUPT_STATUS_3_REG);
drivers/net/ethernet/cortina/gemini.c
2390
writel(~0, geth->base + GLOBAL_INTERRUPT_STATUS_4_REG);
drivers/net/ethernet/cortina/gemini.c
2393
writel(0, geth->base + GLOBAL_SW_FREEQ_BASE_SIZE_REG);
drivers/net/ethernet/cortina/gemini.c
2394
writel(0, geth->base + GLOBAL_HW_FREEQ_BASE_SIZE_REG);
drivers/net/ethernet/cortina/gemini.c
2395
writel(0, geth->base + GLOBAL_SWFQ_RWPTR_REG);
drivers/net/ethernet/cortina/gemini.c
2396
writel(0, geth->base + GLOBAL_HWFQ_RWPTR_REG);
drivers/net/ethernet/cortina/gemini.c
251
writel(reg, port->gmac_base + GMAC_CONFIG0);
drivers/net/ethernet/cortina/gemini.c
266
writel(val, port->gmac_base + GMAC_CONFIG0);
drivers/net/ethernet/cortina/gemini.c
287
writel(val, port->gmac_base + GMAC_CONFIG0);
drivers/net/ethernet/cortina/gemini.c
353
writel(status.bits32, port->gmac_base + GMAC_STATUS);
drivers/net/ethernet/cortina/gemini.c
400
writel(status.bits32, port->gmac_base + GMAC_STATUS);
drivers/net/ethernet/cortina/gemini.c
516
writel(config0.bits32, port->gmac_base + GMAC_CONFIG0);
drivers/net/ethernet/cortina/gemini.c
517
writel(config1.bits32, port->gmac_base + GMAC_CONFIG1);
drivers/net/ethernet/cortina/gemini.c
518
writel(config2.bits32, port->gmac_base + GMAC_CONFIG2);
drivers/net/ethernet/cortina/gemini.c
519
writel(config3.bits32, port->gmac_base + GMAC_CONFIG3);
drivers/net/ethernet/cortina/gemini.c
522
writel(ahb_weight.bits32, port->dma_base + GMAC_AHB_WEIGHT_REG);
drivers/net/ethernet/cortina/gemini.c
524
writel(hw_weigh.bits32,
drivers/net/ethernet/cortina/gemini.c
526
writel(sw_weigh.bits32,
drivers/net/ethernet/cortina/gemini.c
577
writel(port->txq_dma_base | port->txq_order,
drivers/net/ethernet/cortina/gemini.c
689
writel(0, port->dma_base + GMAC_SW_TX_QUEUE_BASE_REG);
drivers/net/ethernet/cortina/gemini.c
717
writel(port->rxq_dma_base | port->rxq_order, &qhdr->word0);
drivers/net/ethernet/cortina/gemini.c
718
writel(0, port->rxq_rwptr);
drivers/net/ethernet/cortina/gemini.c
772
writel(0, dma_reg);
drivers/net/ethernet/cortina/gemini.c
959
writel(qt.bits32, geth->base + GLOBAL_QUEUE_THRESHOLD_REG);
drivers/net/ethernet/cortina/gemini.c
962
writel(skbsz.bits32, geth->base + GLOBAL_DMA_SKB_SIZE_REG);
drivers/net/ethernet/cortina/gemini.c
963
writel(geth->freeq_dma_base | geth->freeq_order,
drivers/net/ethernet/dec/tulip/de2104x.c
1772
writel(EE_ENB & ~EE_CS, ee_addr);
drivers/net/ethernet/dec/tulip/de2104x.c
1773
writel(EE_ENB, ee_addr);
drivers/net/ethernet/dec/tulip/de2104x.c
1778
writel(EE_ENB | dataval, ee_addr);
drivers/net/ethernet/dec/tulip/de2104x.c
1780
writel(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
drivers/net/ethernet/dec/tulip/de2104x.c
1784
writel(EE_ENB, ee_addr);
drivers/net/ethernet/dec/tulip/de2104x.c
1788
writel(EE_ENB | EE_SHIFT_CLK, ee_addr);
drivers/net/ethernet/dec/tulip/de2104x.c
1791
writel(EE_ENB, ee_addr);
drivers/net/ethernet/dec/tulip/de2104x.c
1796
writel(EE_ENB & ~EE_CS, ee_addr);
drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.c
73
writel(val, priv->onestep_reg_base);
drivers/net/ethernet/freescale/fec_main.c
1072
writel(0, fep->rx_queue[i]->bd.reg_desc_active);
drivers/net/ethernet/freescale/fec_main.c
1084
writel(rxq->bd.dma, fep->hwp + FEC_R_DES_START(i));
drivers/net/ethernet/freescale/fec_main.c
1085
writel(fep->max_buf_size, fep->hwp + FEC_R_BUFF_SIZE(i));
drivers/net/ethernet/freescale/fec_main.c
1089
writel(RCMR_MATCHEN | RCMR_CMP(i),
drivers/net/ethernet/freescale/fec_main.c
1095
writel(txq->bd.dma, fep->hwp + FEC_X_DES_START(i));
drivers/net/ethernet/freescale/fec_main.c
1099
writel(DMA_CLASS_EN | IDLE_SLOPE(i),
drivers/net/ethernet/freescale/fec_main.c
1115
writel(0, fep->hwp + FEC_ECNTRL);
drivers/net/ethernet/freescale/fec_main.c
1117
writel(FEC_ECR_RESET, fep->hwp + FEC_ECNTRL);
drivers/net/ethernet/freescale/fec_main.c
1123
writel(val, fep->hwp + FEC_ECNTRL);
drivers/net/ethernet/freescale/fec_main.c
1131
writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
drivers/net/ethernet/freescale/fec_main.c
1134
writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
drivers/net/ethernet/freescale/fec_main.c
1165
writel((0xffffffff & ~FEC_ENET_MII), fep->hwp + FEC_IEVENT);
drivers/net/ethernet/freescale/fec_main.c
1174
writel(0x04, fep->hwp + FEC_X_CNTRL);
drivers/net/ethernet/freescale/fec_main.c
1178
writel(0x0, fep->hwp + FEC_X_CNTRL);
drivers/net/ethernet/freescale/fec_main.c
1182
writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
drivers/net/ethernet/freescale/fec_main.c
1195
writel(val, fep->hwp + FEC_RACC);
drivers/net/ethernet/freescale/fec_main.c
1196
writel(min(fep->rx_frame_size, fep->max_buf_size), fep->hwp + FEC_FTRL);
drivers/net/ethernet/freescale/fec_main.c
1230
writel(0, fep->hwp + FEC_MIIGSK_ENR);
drivers/net/ethernet/freescale/fec_main.c
1243
writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR);
drivers/net/ethernet/freescale/fec_main.c
1246
writel(2, fep->hwp + FEC_MIIGSK_ENR);
drivers/net/ethernet/freescale/fec_main.c
1259
writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM);
drivers/net/ethernet/freescale/fec_main.c
1260
writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL);
drivers/net/ethernet/freescale/fec_main.c
1261
writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM);
drivers/net/ethernet/freescale/fec_main.c
1262
writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL);
drivers/net/ethernet/freescale/fec_main.c
1265
writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD);
drivers/net/ethernet/freescale/fec_main.c
1271
writel(rcntl, fep->hwp + FEC_R_CNTRL);
drivers/net/ethernet/freescale/fec_main.c
1276
writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
drivers/net/ethernet/freescale/fec_main.c
1277
writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
drivers/net/ethernet/freescale/fec_main.c
1293
writel(0xF, fep->hwp + FEC_X_WMRK);
drivers/net/ethernet/freescale/fec_main.c
1295
writel(FEC_TXWMRK_STRFWD, fep->hwp + FEC_X_WMRK);
drivers/net/ethernet/freescale/fec_main.c
1310
writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT);
drivers/net/ethernet/freescale/fec_main.c
1314
writel(ecntl, fep->hwp + FEC_ECNTRL);
drivers/net/ethernet/freescale/fec_main.c
1324
writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
drivers/net/ethernet/freescale/fec_main.c
1326
writel(0, fep->hwp + FEC_IMASK);
drivers/net/ethernet/freescale/fec_main.c
1387
writel(0, fep->hwp + FEC_IMASK);
drivers/net/ethernet/freescale/fec_main.c
1394
writel(0, fep->hwp + FEC_IMASK);
drivers/net/ethernet/freescale/fec_main.c
1395
writel(FEC_ENET_WAKEUP, fep->hwp + FEC_IMASK);
drivers/net/ethernet/freescale/fec_main.c
1407
writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
drivers/net/ethernet/freescale/fec_main.c
1417
writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
drivers/net/ethernet/freescale/fec_main.c
1418
writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
drivers/net/ethernet/freescale/fec_main.c
1423
writel(FEC_ECR_ETHEREN, fep->hwp + FEC_ECNTRL);
drivers/net/ethernet/freescale/fec_main.c
1424
writel(rmii_mode, fep->hwp + FEC_R_CNTRL);
drivers/net/ethernet/freescale/fec_main.c
1430
writel(val, fep->hwp + FEC_ECNTRL);
drivers/net/ethernet/freescale/fec_main.c
1717
writel(0, txq->bd.reg_desc_active);
drivers/net/ethernet/freescale/fec_main.c
1926
writel(FEC_ENET_RXF_GET(queue), fep->hwp + FEC_IEVENT);
drivers/net/ethernet/freescale/fec_main.c
1994
writel(0, rxq->bd.reg_desc_active);
drivers/net/ethernet/freescale/fec_main.c
2056
writel(FEC_ENET_RXF_GET(queue), fep->hwp + FEC_IEVENT);
drivers/net/ethernet/freescale/fec_main.c
2169
writel(0, rxq->bd.reg_desc_active);
drivers/net/ethernet/freescale/fec_main.c
2299
writel(FEC_ENET_RXF_GET(queue), fep->hwp + FEC_IEVENT);
drivers/net/ethernet/freescale/fec_main.c
2431
writel(0, rxq->bd.reg_desc_active);
drivers/net/ethernet/freescale/fec_main.c
2483
writel(int_events, fep->hwp + FEC_IEVENT);
drivers/net/ethernet/freescale/fec_main.c
2500
writel(0, fep->hwp + FEC_IMASK);
drivers/net/ethernet/freescale/fec_main.c
2523
writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
drivers/net/ethernet/freescale/fec_main.c
2633
writel(sleep_cycle, fep->hwp + FEC_LPI_SLEEP);
drivers/net/ethernet/freescale/fec_main.c
2634
writel(wake_cycle, fep->hwp + FEC_LPI_WAKE);
drivers/net/ethernet/freescale/fec_main.c
2708
writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT);
drivers/net/ethernet/freescale/fec_main.c
2729
writel(frame_start | frame_op |
drivers/net/ethernet/freescale/fec_main.c
2762
writel(frame_start | FEC_MMFR_OP_ADDR_WRITE |
drivers/net/ethernet/freescale/fec_main.c
2777
writel(frame_start | frame_op |
drivers/net/ethernet/freescale/fec_main.c
2812
writel(frame_start | FEC_MMFR_OP_WRITE |
drivers/net/ethernet/freescale/fec_main.c
2841
writel(frame_start | FEC_MMFR_OP_ADDR_WRITE |
drivers/net/ethernet/freescale/fec_main.c
2854
writel(frame_start | FEC_MMFR_OP_WRITE |
drivers/net/ethernet/freescale/fec_main.c
3135
writel(0, fep->hwp + FEC_MII_DATA);
drivers/net/ethernet/freescale/fec_main.c
3138
writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
drivers/net/ethernet/freescale/fec_main.c
3141
writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT);
drivers/net/ethernet/freescale/fec_main.c
3591
writel(FEC_MIB_CTRLSTAT_DISABLE, fep->hwp + FEC_MIB_CTRLSTAT);
drivers/net/ethernet/freescale/fec_main.c
3594
writel(0, fep->hwp + fec_stats[i].offset);
drivers/net/ethernet/freescale/fec_main.c
3603
writel(0, fep->hwp + FEC_MIB_CTRLSTAT);
drivers/net/ethernet/freescale/fec_main.c
3652
writel(tx_itr, fep->hwp + FEC_TXIC0);
drivers/net/ethernet/freescale/fec_main.c
3653
writel(rx_itr, fep->hwp + FEC_RXIC0);
drivers/net/ethernet/freescale/fec_main.c
3655
writel(tx_itr, fep->hwp + FEC_TXIC1);
drivers/net/ethernet/freescale/fec_main.c
3656
writel(rx_itr, fep->hwp + FEC_RXIC1);
drivers/net/ethernet/freescale/fec_main.c
3657
writel(tx_itr, fep->hwp + FEC_TXIC2);
drivers/net/ethernet/freescale/fec_main.c
3658
writel(rx_itr, fep->hwp + FEC_RXIC2);
drivers/net/ethernet/freescale/fec_main.c
4286
writel(tmp, fep->hwp + FEC_R_CNTRL);
drivers/net/ethernet/freescale/fec_main.c
4292
writel(tmp, fep->hwp + FEC_R_CNTRL);
drivers/net/ethernet/freescale/fec_main.c
4298
writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
drivers/net/ethernet/freescale/fec_main.c
4299
writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
drivers/net/ethernet/freescale/fec_main.c
4320
writel(hash_high, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
drivers/net/ethernet/freescale/fec_main.c
4321
writel(hash_low, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
drivers/net/ethernet/freescale/fec_main.c
5006
writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK);
drivers/net/ethernet/freescale/fec_main.c
504
writel(0, txq->bd.reg_desc_active);
drivers/net/ethernet/freescale/fec_main.c
5611
writel(val, fep->hwp + FEC_ECNTRL);
drivers/net/ethernet/freescale/fec_ptp.c
107
writel(tempval, fep->hwp + FEC_ATIME_CTRL);
drivers/net/ethernet/freescale/fec_ptp.c
145
writel(FEC_T_TF_MASK, fep->hwp + FEC_TCSR(fep->pps_channel));
drivers/net/ethernet/freescale/fec_ptp.c
154
writel(val, fep->hwp + FEC_TCSR(fep->pps_channel));
drivers/net/ethernet/freescale/fec_ptp.c
197
writel(val, fep->hwp + FEC_TCCR(fep->pps_channel));
drivers/net/ethernet/freescale/fec_ptp.c
205
writel(val, fep->hwp + FEC_ATIME_CTRL);
drivers/net/ethernet/freescale/fec_ptp.c
213
writel(val, fep->hwp + FEC_TCSR(fep->pps_channel));
drivers/net/ethernet/freescale/fec_ptp.c
218
writel(fep->next_counter, fep->hwp + FEC_TCCR(fep->pps_channel));
drivers/net/ethernet/freescale/fec_ptp.c
221
writel(0, fep->hwp + FEC_TCSR(fep->pps_channel));
drivers/net/ethernet/freescale/fec_ptp.c
261
writel(compare_val, fep->hwp + FEC_TCCR(fep->pps_channel));
drivers/net/ethernet/freescale/fec_ptp.c
267
writel(temp_val, fep->hwp + FEC_ATIME_CTRL);
drivers/net/ethernet/freescale/fec_ptp.c
275
writel(temp_val, fep->hwp + FEC_TCSR(fep->pps_channel));
drivers/net/ethernet/freescale/fec_ptp.c
280
writel(fep->next_counter, fep->hwp + FEC_TCCR(fep->pps_channel));
drivers/net/ethernet/freescale/fec_ptp.c
317
writel(inc << FEC_T_INC_OFFSET, fep->hwp + FEC_ATIME_INC);
drivers/net/ethernet/freescale/fec_ptp.c
320
writel(FEC_COUNTER_PERIOD, fep->hwp + FEC_ATIME_EVT_PERIOD);
drivers/net/ethernet/freescale/fec_ptp.c
322
writel(FEC_T_CTRL_ENABLE | FEC_T_CTRL_PERIOD_RST,
drivers/net/ethernet/freescale/fec_ptp.c
402
writel(tmp, fep->hwp + FEC_ATIME_INC);
drivers/net/ethernet/freescale/fec_ptp.c
404
writel(corr_period, fep->hwp + FEC_ATIME_CORR);
drivers/net/ethernet/freescale/fec_ptp.c
496
writel(counter, fep->hwp + FEC_ATIME);
drivers/net/ethernet/freescale/fec_ptp.c
511
writel(0, fep->hwp + FEC_TCSR(channel));
drivers/net/ethernet/freescale/fec_ptp.c
709
writel(fep->next_counter, fep->hwp + FEC_TCCR(channel));
drivers/net/ethernet/freescale/fec_ptp.c
711
writel(val, fep->hwp + FEC_TCSR(channel));
drivers/net/ethernet/freescale/fec_ptp.c
836
writel(fep->ptp_saved_state.at_corr, fep->hwp + FEC_ATIME_CORR);
drivers/net/ethernet/freescale/fec_ptp.c
838
writel(atime_inc, fep->hwp + FEC_ATIME_INC);
drivers/net/ethernet/freescale/fec_ptp.c
842
writel(counter, fep->hwp + FEC_ATIME);
drivers/net/ethernet/fungible/funcore/fun_dev.c
102
writel(fdev->cc_reg, fdev->bar + NVME_REG_CC);
drivers/net/ethernet/fungible/funcore/fun_dev.c
269
writel((funq->sq_depth - 1) << AQA_ASQS_SHIFT |
drivers/net/ethernet/fungible/funcore/fun_dev.c
403
writel(funq->sq_tail, funq->sq_db);
drivers/net/ethernet/fungible/funcore/fun_queue.c
346
writel(funq->rq_tail, funq->rq_db);
drivers/net/ethernet/fungible/funcore/fun_queue.c
350
writel(db, funq->cq_db);
drivers/net/ethernet/fungible/funcore/fun_queue.h
100
writel(tail, funq->sq_db);
drivers/net/ethernet/fungible/funcore/fun_queue.h
111
writel(funq->rq_tail, funq->rq_db);
drivers/net/ethernet/fungible/funeth/funeth_rx.c
528
writel((q->rq_cons - 1) & q->rq_mask, q->rq_db);
drivers/net/ethernet/fungible/funeth/funeth_rx.c
531
writel(cq_db_val, q->cq_db);
drivers/net/ethernet/fungible/funeth/funeth_rx.c
745
writel(q->rq_mask, q->rq_db);
drivers/net/ethernet/fungible/funeth/funeth_tx.c
479
writel(db_val, q->db);
drivers/net/ethernet/fungible/funeth/funeth_tx.c
712
writel(q->irq_db_val, q->db);
drivers/net/ethernet/fungible/funeth/funeth_txrx.h
239
writel(tail, q->db);
drivers/net/ethernet/hisilicon/hibmcge/hbg_hw.h
17
writel(value, priv->io_base + addr);
drivers/net/ethernet/hisilicon/hip04_eth.c
413
writel(val, priv->base + PPE_CFG_CPU_ADD_ADDR);
drivers/net/ethernet/hisilicon/hisi_femac.c
131
writel(val | irqs, priv->glb_base + GLB_IRQ_ENA);
drivers/net/ethernet/hisilicon/hisi_femac.c
139
writel(val & (~irqs), priv->glb_base + GLB_IRQ_ENA);
drivers/net/ethernet/hisilicon/hisi_femac.c
204
writel(status, priv->port_base + MAC_PORTSET);
drivers/net/ethernet/hisilicon/hisi_femac.c
239
writel(addr, priv->port_base + IQ_ADDR);
drivers/net/ethernet/hisilicon/hisi_femac.c
260
writel(IRQ_INT_RX_RDY, priv->glb_base + GLB_IRQ_RAW);
drivers/net/ethernet/hisilicon/hisi_femac.c
316
writel(ints & DEF_INT_MASK,
drivers/net/ethernet/hisilicon/hisi_femac.c
338
writel(ints & DEF_INT_MASK,
drivers/net/ethernet/hisilicon/hisi_femac.c
435
writel(reg, priv->glb_base + GLB_HOSTMAC_H16);
drivers/net/ethernet/hisilicon/hisi_femac.c
438
writel(reg, priv->glb_base + GLB_HOSTMAC_L32);
drivers/net/ethernet/hisilicon/hisi_femac.c
449
writel(val, priv->glb_base + GLB_SOFT_RESET);
drivers/net/ethernet/hisilicon/hisi_femac.c
454
writel(val, priv->glb_base + GLB_SOFT_RESET);
drivers/net/ethernet/hisilicon/hisi_femac.c
476
writel(IRQ_ENA_PORT0_MASK, priv->glb_base + GLB_IRQ_RAW);
drivers/net/ethernet/hisilicon/hisi_femac.c
538
writel(addr, priv->port_base + EQ_ADDR);
drivers/net/ethernet/hisilicon/hisi_femac.c
539
writel(skb->len + ETH_FCS_LEN, priv->port_base + EQFRM_LEN);
drivers/net/ethernet/hisilicon/hisi_femac.c
576
writel(val, priv->glb_base + GLB_MAC_H16(reg_n));
drivers/net/ethernet/hisilicon/hisi_femac.c
590
writel(val, priv->glb_base + low);
drivers/net/ethernet/hisilicon/hisi_femac.c
596
writel(val, priv->glb_base + high);
drivers/net/ethernet/hisilicon/hisi_femac.c
609
writel(val, priv->glb_base + GLB_FWCTRL);
drivers/net/ethernet/hisilicon/hisi_femac.c
636
writel(val, priv->glb_base + GLB_MACTCTRL);
drivers/net/ethernet/hisilicon/hisi_femac.c
662
writel(val, priv->glb_base + GLB_MACTCTRL);
drivers/net/ethernet/hisilicon/hisi_femac.c
740
writel(val, priv->port_base + MAC_PORTSEL);
drivers/net/ethernet/hisilicon/hisi_femac.c
743
writel(IRQ_ENA_PORT0_MASK, priv->glb_base + GLB_IRQ_RAW);
drivers/net/ethernet/hisilicon/hisi_femac.c
749
writel(val, priv->glb_base + GLB_FWCTRL);
drivers/net/ethernet/hisilicon/hisi_femac.c
753
writel(val, priv->glb_base + GLB_MACTCTRL);
drivers/net/ethernet/hisilicon/hisi_femac.c
758
writel(val, priv->port_base + MAC_SET);
drivers/net/ethernet/hisilicon/hisi_femac.c
762
writel(val, priv->port_base + RX_COALESCE_SET);
drivers/net/ethernet/hisilicon/hisi_femac.c
765
writel(val, priv->port_base + QLEN_SET);
drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h
1019
writel(value, base + reg);
drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h
463
writel(value, base + reg);
drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
2145
writel(ring->pending_buf,
drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
3750
writel(i, ring->tqp->io_base +
drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
3762
writel(i, ring->tqp->io_base + HNS3_RING_RX_RING_HEAD_REG);
drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
475
writel(mask_en, tqp_vector->mask_addr);
drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
508
writel(rl_reg, tqp_vector->mask_addr + HNS3_VECTOR_RL_OFFSET);
drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
521
writel(new_val, tqp_vector->mask_addr + HNS3_VECTOR_GL0_OFFSET);
drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
5321
writel(new_mode, handle->kinfo.io_base + reg);
drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
534
writel(new_val, tqp_vector->mask_addr + HNS3_VECTOR_GL1_OFFSET);
drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
540
writel(ql_value, tqp_vector->mask_addr + HNS3_VECTOR_TX_QL_OFFSET);
drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
546
writel(ql_value, tqp_vector->mask_addr + HNS3_VECTOR_RX_QL_OFFSET);
drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
652
writel(value, reg_addr + reg);
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
3683
writel(enable ? 1 : 0, vector->addr);
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.c
159
writel(ts->tv_nsec, hdev->ptp->io_base + HCLGE_PTP_TIME_NSEC_REG);
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.c
160
writel(ts->tv_sec >> HCLGE_PTP_SEC_H_OFFSET,
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.c
162
writel(ts->tv_sec & HCLGE_PTP_SEC_L_MASK,
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.c
165
writel(HCLGE_PTP_TIME_SYNC_EN,
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.c
199
writel(adj_val, hdev->ptp->io_base + HCLGE_PTP_TIME_NSEC_REG);
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.c
200
writel(HCLGE_PTP_TIME_ADJ_EN,
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.c
45
writel(quo & HCLGE_PTP_CYCLE_QUO_MASK,
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.c
47
writel(numerator, hdev->ptp->io_base + HCLGE_PTP_CYCLE_NUM_REG);
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.c
48
writel(cycle->den, hdev->ptp->io_base + HCLGE_PTP_CYCLE_DEN_REG);
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.c
49
writel(HCLGE_PTP_CYCLE_ADJ_EN,
drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
1737
writel(en ? 1 : 0, vector->addr);
drivers/net/ethernet/huawei/hinic/hinic_hw_cmdq.c
332
writel(db_info, CMDQ_DB_ADDR(cmdq->db_base, prod_idx));
drivers/net/ethernet/huawei/hinic/hinic_hw_if.c
149
writel(mask_bits, hwif->intr_regs_base + offset);
drivers/net/ethernet/huawei/hinic/hinic_hw_if.h
260
writel(*(u32 *)&in, hwif->cfg_regs_bar + reg);
drivers/net/ethernet/huawei/hinic/hinic_hw_qp.c
646
writel(sq_prepare_db(sq, prod_idx, cos), SQ_DB_ADDR(sq, prod_idx));
drivers/net/ethernet/i825xx/sni_82596.c
48
writel(0, lp->ca);
drivers/net/ethernet/i825xx/sni_82596.c
64
writel(v, lp->mpu_port);
drivers/net/ethernet/i825xx/sni_82596.c
67
writel(v, lp->mpu_port);
drivers/net/ethernet/intel/e1000/e1000_ethtool.c
665
writel(write & test[i], address);
drivers/net/ethernet/intel/e1000/e1000_ethtool.c
685
writel(write & mask, address);
drivers/net/ethernet/intel/e1000/e1000_hw.c
2831
writel(mdic, E1000_MDIO_CMD);
drivers/net/ethernet/intel/e1000/e1000_hw.c
2971
writel(mdic, E1000_MDIO_CMD);
drivers/net/ethernet/intel/e1000/e1000_main.c
2010
writel(0, hw->hw_addr + tx_ring->tdh);
drivers/net/ethernet/intel/e1000/e1000_main.c
2011
writel(0, hw->hw_addr + tx_ring->tdt);
drivers/net/ethernet/intel/e1000/e1000_main.c
2133
writel(0, hw->hw_addr + rx_ring->rdh);
drivers/net/ethernet/intel/e1000/e1000_main.c
2134
writel(0, hw->hw_addr + rx_ring->rdt);
drivers/net/ethernet/intel/e1000/e1000_main.c
3273
writel(tx_ring->next_to_use, hw->hw_addr + tx_ring->tdt);
drivers/net/ethernet/intel/e1000/e1000_main.c
4559
writel(i, adapter->hw.hw_addr + rx_ring->rdt);
drivers/net/ethernet/intel/e1000/e1000_main.c
4676
writel(i, hw->hw_addr + rx_ring->rdt);
drivers/net/ethernet/intel/e1000/e1000_osdep.h
33
(writel((value), (hw->hw_addr + ((hw->mac_type >= e1000_82543) \
drivers/net/ethernet/intel/e1000/e1000_osdep.h
37
writel((value), ((a)->hw_addr + \
drivers/net/ethernet/intel/e1000/e1000_osdep.h
72
writel((value), ((a)->flash_address + reg)))
drivers/net/ethernet/intel/e1000e/ich8lan.c
158
writel(val, hw->flash_address + reg);
drivers/net/ethernet/intel/e1000e/netdev.c
137
writel(val, hw->hw_addr + reg);
drivers/net/ethernet/intel/e1000e/netdev.c
1947
writel(itr, rx_ring->itr_register);
drivers/net/ethernet/intel/e1000e/netdev.c
1988
writel(1000000000 / (rx_ring->itr_val * 256),
drivers/net/ethernet/intel/e1000e/netdev.c
1991
writel(1, rx_ring->itr_register);
drivers/net/ethernet/intel/e1000e/netdev.c
1998
writel(1000000000 / (tx_ring->itr_val * 256),
drivers/net/ethernet/intel/e1000e/netdev.c
2001
writel(1, tx_ring->itr_register);
drivers/net/ethernet/intel/e1000e/netdev.c
2009
writel(1000000000 / (rx_ring->itr_val * 256),
drivers/net/ethernet/intel/e1000e/netdev.c
2012
writel(1, hw->hw_addr + E1000_EITR_82574(vector));
drivers/net/ethernet/intel/e1000e/netdev.c
2617
writel(new_itr, hw->hw_addr + E1000_EITR_82574(vector));
drivers/net/ethernet/intel/e1000e/netdev.c
5942
writel(tx_ring->next_to_use, tx_ring->tail);
drivers/net/ethernet/intel/e1000e/netdev.c
613
writel(i, rx_ring->tail);
drivers/net/ethernet/intel/e1000e/netdev.c
630
writel(i, tx_ring->tail);
drivers/net/ethernet/intel/e1000e/netdev.c
700
writel(i, rx_ring->tail);
drivers/net/ethernet/intel/e1000e/netdev.c
802
writel(i << 1, rx_ring->tail);
drivers/net/ethernet/intel/e1000e/netdev.c
895
writel(i, rx_ring->tail);
drivers/net/ethernet/intel/fm10k/fm10k_common.h
22
writel((val), &hw_addr[(reg)]); \
drivers/net/ethernet/intel/fm10k/fm10k_common.h
30
writel((val), &sw_addr[(reg)]); \
drivers/net/ethernet/intel/fm10k/fm10k_main.c
1030
writel(i, tx_ring->tail);
drivers/net/ethernet/intel/fm10k/fm10k_main.c
1417
writel(itr, q_vector->itr);
drivers/net/ethernet/intel/fm10k/fm10k_main.c
171
writel(i, rx_ring->tail);
drivers/net/ethernet/intel/fm10k/fm10k_pci.c
1741
writel(FM10K_ITR_MASK_SET, q_vector->itr);
drivers/net/ethernet/intel/fm10k/fm10k_pci.c
1802
writel(FM10K_ITR_ENABLE, q_vector->itr);
drivers/net/ethernet/intel/fm10k/fm10k_pci.c
1825
writel(FM10K_ITR_MASK_SET, q_vector->itr);
drivers/net/ethernet/intel/fm10k/fm10k_pci.c
724
writel(FM10K_ITR_ENABLE | FM10K_ITR_PENDING2, qv->itr);
drivers/net/ethernet/intel/i40e/i40e_io.h
10
#define wr32(a, reg, value) writel((value), ((a)->hw_addr + (reg)))
drivers/net/ethernet/intel/i40e/i40e_main.c
3687
writel(0, ring->tail);
drivers/net/ethernet/intel/i40e/i40e_txrx.c
150
writel(tx_ring->next_to_use, tx_ring->tail);
drivers/net/ethernet/intel/i40e/i40e_txrx.c
1601
writel(val, rx_ring->tail);
drivers/net/ethernet/intel/i40e/i40e_txrx.c
3697
writel(i, tx_ring->tail);
drivers/net/ethernet/intel/iavf/iavf_osdep.h
16
#define wr32(a, reg, value) writel((value), ((a)->hw_addr + (reg)))
drivers/net/ethernet/intel/iavf/iavf_txrx.c
2262
writel(i, tx_ring->tail);
drivers/net/ethernet/intel/iavf/iavf_txrx.c
828
writel(val, rx_ring->tail);
drivers/net/ethernet/intel/ice/ice_base.c
602
writel(0, ring->tail);
drivers/net/ethernet/intel/ice/ice_osdep.h
22
#define wr32(a, reg, value) writel((value), ((a)->hw_addr + (reg)))
drivers/net/ethernet/intel/ice/ice_txrx.c
103
writel(tx_ring->next_to_use, tx_ring->tail);
drivers/net/ethernet/intel/ice/ice_txrx_lib.c
36
writel(val, rx_ring->tail);
drivers/net/ethernet/intel/idpf/idpf_dev.c
161
writel(reset_reg | PFGEN_CTRL_PFSWR,
drivers/net/ethernet/intel/idpf/idpf_lib.c
121
writel(val, intr->dyn_ctl);
drivers/net/ethernet/intel/idpf/idpf_lib.c
122
writel(intr->icr_ena_ctlq_m, intr->icr_ena);
drivers/net/ethernet/intel/idpf/idpf_lib.c
1474
writel(q->next_to_alloc, q->tail);
drivers/net/ethernet/intel/idpf/idpf_lib.c
1481
writel(q->next_to_alloc, q->tail);
drivers/net/ethernet/intel/idpf/idpf_main.c
38
writel(IDPF_VF_TEST_VAL, addr);
drivers/net/ethernet/intel/idpf/idpf_mem.h
15
#define idpf_mbx_wr32(a, reg, value) writel((value), ((a)->mbx.vaddr + (reg)))
drivers/net/ethernet/intel/idpf/idpf_ptp.c
87
writel(shtime_enable, adapter->ptp->dev_clk_regs.cmd_sync);
drivers/net/ethernet/intel/idpf/idpf_ptp.c
88
writel(exec_cmd | shtime_enable, adapter->ptp->dev_clk_regs.cmd_sync);
drivers/net/ethernet/intel/idpf/idpf_singleq_txrx.c
881
writel(val, rxq->tail);
drivers/net/ethernet/intel/idpf/idpf_txrx.c
1062
writel(q->txq->next_to_use, q->txq->tail);
drivers/net/ethernet/intel/idpf/idpf_txrx.c
1258
writel(0, q_vector->intr_reg.dyn_ctl);
drivers/net/ethernet/intel/idpf/idpf_txrx.c
2491
writel(val, tx_q->tail);
drivers/net/ethernet/intel/idpf/idpf_txrx.c
3889
writel(0, rsrc->noirq_dyn_ctl);
drivers/net/ethernet/intel/idpf/idpf_txrx.c
3892
writel(0, q_vector[q_idx].intr_reg.dyn_ctl);
drivers/net/ethernet/intel/idpf/idpf_txrx.c
4031
writel(intval, q_vector->intr_reg.dyn_ctl);
drivers/net/ethernet/intel/idpf/idpf_txrx.c
4109
writel(ITR_REG_ALIGN(itr) >> IDPF_ITR_GRAN_S,
drivers/net/ethernet/intel/idpf/idpf_txrx.c
4148
writel(rsrc->noirq_dyn_ctl_ena, rsrc->noirq_dyn_ctl);
drivers/net/ethernet/intel/idpf/idpf_txrx.c
544
writel(val, bufq->tail);
drivers/net/ethernet/intel/idpf/idpf_txrx.h
1061
writel(reg->dyn_ctl_wb_on_itr_m | reg->dyn_ctl_intena_msk_m |
drivers/net/ethernet/intel/idpf/xsk.c
367
writel(fq.ntu, bufq->tail);
drivers/net/ethernet/intel/igb/e1000_regs.h
359
writel((val), &hw_addr[(reg)]); \
drivers/net/ethernet/intel/igb/igb.h
831
writel(ring->next_to_use, ring->tail);
drivers/net/ethernet/intel/igb/igb_ethtool.c
1341
writel(test->write,
drivers/net/ethernet/intel/igb/igb_main.c
4401
writel(0, ring->tail);
drivers/net/ethernet/intel/igb/igb_main.c
4816
writel(0, ring->tail);
drivers/net/ethernet/intel/igb/igb_main.c
6382
writel(i, tx_ring->tail);
drivers/net/ethernet/intel/igb/igb_main.c
6503
writel(index, tx_ring->tail);
drivers/net/ethernet/intel/igb/igb_main.c
7150
writel(itr_val, q_vector->itr_register);
drivers/net/ethernet/intel/igb/igb_main.c
9267
writel(i, rx_ring->tail);
drivers/net/ethernet/intel/igb/igb_xsk.c
244
writel(ntu, rx_ring->tail);
drivers/net/ethernet/intel/igbvf/ethtool.c
368
writel(adapter->current_itr,
drivers/net/ethernet/intel/igbvf/netdev.c
2264
writel(i, adapter->hw.hw_addr + tx_ring->tail);
drivers/net/ethernet/intel/igbvf/netdev.c
231
writel(i, adapter->hw.hw_addr + rx_ring->tail);
drivers/net/ethernet/intel/igbvf/netdev.c
521
writel(0, adapter->hw.hw_addr + tx_ring->head);
drivers/net/ethernet/intel/igbvf/netdev.c
522
writel(0, adapter->hw.hw_addr + tx_ring->tail);
drivers/net/ethernet/intel/igbvf/netdev.c
604
writel(0, adapter->hw.hw_addr + rx_ring->head);
drivers/net/ethernet/intel/igbvf/netdev.c
605
writel(0, adapter->hw.hw_addr + rx_ring->tail);
drivers/net/ethernet/intel/igbvf/netdev.c
875
writel(tx_ring->itr_val,
drivers/net/ethernet/intel/igbvf/netdev.c
904
writel(adapter->rx_ring->itr_val,
drivers/net/ethernet/intel/igbvf/netdev.c
982
writel(tx_ring->itr_val, hw->hw_addr + tx_ring->itr_register);
drivers/net/ethernet/intel/igbvf/netdev.c
985
writel(rx_ring->itr_val, hw->hw_addr + rx_ring->itr_register);
drivers/net/ethernet/intel/igbvf/regs.h
77
#define ew32(reg, val) writel((val), hw->hw_addr + E1000_##reg)
drivers/net/ethernet/intel/igbvf/regs.h
81
writel((val), hw->hw_addr + E1000_##reg + (offset << 2))
drivers/net/ethernet/intel/igc/igc_main.c
1422
writel(i, tx_ring->tail);
drivers/net/ethernet/intel/igc/igc_main.c
2317
writel(i, rx_ring->tail);
drivers/net/ethernet/intel/igc/igc_main.c
2374
writel(i, ring->tail);
drivers/net/ethernet/intel/igc/igc_main.c
2569
writel(ring->next_to_use, ring->tail);
drivers/net/ethernet/intel/igc/igc_main.c
5680
writel(itr_val, q_vector->itr_register);
drivers/net/ethernet/intel/igc/igc_main.c
671
writel(0, ring->tail);
drivers/net/ethernet/intel/igc/igc_main.c
757
writel(0, ring->tail);
drivers/net/ethernet/intel/igc/igc_regs.h
353
writel((val), &hw_addr[(reg)]); \
drivers/net/ethernet/intel/ixgbe/ixgbe_common.h
149
writel(value, reg_addr + reg);
drivers/net/ethernet/intel/ixgbe/ixgbe_common.h
157
writel((u32)val, addr);
drivers/net/ethernet/intel/ixgbe/ixgbe_common.h
158
writel((u32)(val >> 32), addr + 4);
drivers/net/ethernet/intel/ixgbe/ixgbe_main.c
10979
writel(ring->next_to_use, ring->tail);
drivers/net/ethernet/intel/ixgbe/ixgbe_main.c
1848
writel(i, rx_ring->tail);
drivers/net/ethernet/intel/ixgbe/ixgbe_main.c
9057
writel(i, tx_ring->tail);
drivers/net/ethernet/intel/ixgbe/ixgbe_xsk.c
207
writel(i, rx_ring->tail);
drivers/net/ethernet/intel/ixgbevf/ixgbevf.h
280
writel(value, ring->tail);
drivers/net/ethernet/intel/ixgbevf/vf.h
166
writel(value, reg_addr + reg);
drivers/net/ethernet/jme.h
1208
writel(val, jme->regs + reg);
drivers/net/ethernet/jme.h
1218
writel(val, jme->regs + reg);
drivers/net/ethernet/korina.c
1075
writel(0, &lp->eth_regs->ethintfc);
drivers/net/ethernet/korina.c
1080
writel(ETH_INT_FC_EN, &lp->eth_regs->ethintfc);
drivers/net/ethernet/korina.c
1089
writel(0, &lp->rx_dma_regs->dmas);
drivers/net/ethernet/korina.c
1091
writel(0, &lp->rx_dma_regs->dmandptr);
drivers/net/ethernet/korina.c
1092
writel(korina_rx_dma(lp, 0), &lp->rx_dma_regs->dmadptr);
drivers/net/ethernet/korina.c
1094
writel(readl(&lp->tx_dma_regs->dmasm) &
drivers/net/ethernet/korina.c
1097
writel(readl(&lp->rx_dma_regs->dmasm) &
drivers/net/ethernet/korina.c
1102
writel(ETH_ARC_AB, &lp->eth_regs->etharc);
drivers/net/ethernet/korina.c
1105
writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal0);
drivers/net/ethernet/korina.c
1106
writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah0);
drivers/net/ethernet/korina.c
1108
writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal1);
drivers/net/ethernet/korina.c
1109
writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah1);
drivers/net/ethernet/korina.c
1111
writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal2);
drivers/net/ethernet/korina.c
1112
writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah2);
drivers/net/ethernet/korina.c
1114
writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal3);
drivers/net/ethernet/korina.c
1115
writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah3);
drivers/net/ethernet/korina.c
1119
writel(ETH_MAC2_PE | ETH_MAC2_CEN | ETH_MAC2_FD,
drivers/net/ethernet/korina.c
1123
writel(0x15, &lp->eth_regs->ethipgt);
drivers/net/ethernet/korina.c
1125
writel(0x12, &lp->eth_regs->ethipgr);
drivers/net/ethernet/korina.c
1129
writel(((lp->mii_clock_freq) / MII_CLOCK + 1) & ~1,
drivers/net/ethernet/korina.c
1131
writel(0, &lp->eth_regs->miimcfg);
drivers/net/ethernet/korina.c
1134
writel(48, &lp->eth_regs->ethfifott);
drivers/net/ethernet/korina.c
1136
writel(ETH_MAC1_RE, &lp->eth_regs->ethmac1);
drivers/net/ethernet/korina.c
1161
writel(readl(&lp->tx_dma_regs->dmasm) |
drivers/net/ethernet/korina.c
1164
writel(readl(&lp->rx_dma_regs->dmasm) |
drivers/net/ethernet/korina.c
1252
writel(tmp, &lp->tx_dma_regs->dmasm);
drivers/net/ethernet/korina.c
1257
writel(tmp, &lp->rx_dma_regs->dmasm);
drivers/net/ethernet/korina.c
392
writel(0x10, &ch->dmac);
drivers/net/ethernet/korina.c
397
writel(0, &ch->dmas);
drivers/net/ethernet/korina.c
400
writel(0, &ch->dmadptr);
drivers/net/ethernet/korina.c
401
writel(0, &ch->dmandptr);
drivers/net/ethernet/korina.c
470
writel(korina_tx_dma(lp, lp->tx_chain_head),
drivers/net/ethernet/korina.c
486
writel(korina_tx_dma(lp, lp->tx_chain_head),
drivers/net/ethernet/korina.c
542
writel(phy << 8 | reg, &lp->eth_regs->miimaddr);
drivers/net/ethernet/korina.c
543
writel(1, &lp->eth_regs->miimcmd);
drivers/net/ethernet/korina.c
553
writel(0, &lp->eth_regs->miimcmd);
drivers/net/ethernet/korina.c
564
writel(0, &lp->eth_regs->miimcmd);
drivers/net/ethernet/korina.c
565
writel(phy << 8 | reg, &lp->eth_regs->miimaddr);
drivers/net/ethernet/korina.c
566
writel(val, &lp->eth_regs->miimwtd);
drivers/net/ethernet/korina.c
580
writel(dmasm | (DMA_STAT_DONE |
drivers/net/ethernet/korina.c
684
writel((u32)~DMA_STAT_DONE, &lp->rx_dma_regs->dmas);
drivers/net/ethernet/korina.c
690
writel((u32)~(DMA_STAT_HALT | DMA_STAT_ERR),
drivers/net/ethernet/korina.c
696
writel(korina_rx_dma(lp, rd - lp->rd_ring),
drivers/net/ethernet/korina.c
714
writel(readl(&lp->rx_dma_regs->dmasm) &
drivers/net/ethernet/korina.c
753
writel((u32)(hash_table[1] << 16 | hash_table[0]),
drivers/net/ethernet/korina.c
755
writel((u32)(hash_table[3] << 16 | hash_table[2]),
drivers/net/ethernet/korina.c
760
writel(recognise, &lp->eth_regs->etharc);
drivers/net/ethernet/korina.c
842
writel(~dmas, &lp->tx_dma_regs->dmas);
drivers/net/ethernet/korina.c
844
writel(readl(&lp->tx_dma_regs->dmasm) &
drivers/net/ethernet/korina.c
863
writel(dmasm | (DMA_STAT_FINI | DMA_STAT_ERR),
drivers/net/ethernet/korina.c
870
writel(korina_tx_dma(lp, lp->tx_chain_head),
drivers/net/ethernet/korina.c
894
writel(readl(&lp->eth_regs->ethmac2) | ETH_MAC2_FD,
drivers/net/ethernet/korina.c
897
writel(readl(&lp->eth_regs->ethmac2) & ~ETH_MAC2_FD,
drivers/net/ethernet/marvell/mv643xx_eth.c
2631
writel(0, base + WINDOW_BASE(i));
drivers/net/ethernet/marvell/mv643xx_eth.c
2632
writel(0, base + WINDOW_SIZE(i));
drivers/net/ethernet/marvell/mv643xx_eth.c
2634
writel(0, base + WINDOW_REMAP_HIGH(i));
drivers/net/ethernet/marvell/mv643xx_eth.c
2643
writel((cs->base & 0xffff0000) |
drivers/net/ethernet/marvell/mv643xx_eth.c
2646
writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
drivers/net/ethernet/marvell/mv643xx_eth.c
2652
writel(win_enable, base + WINDOW_BAR_ENABLE);
drivers/net/ethernet/marvell/mv643xx_eth.c
2663
writel(0x02000000, msp->base + 0x0400 + SDMA_CONFIG);
drivers/net/ethernet/marvell/mv643xx_eth.c
2674
writel(1, msp->base + 0x0400 + TX_BW_MTU_MOVED);
drivers/net/ethernet/marvell/mv643xx_eth.c
2678
writel(7, msp->base + 0x0400 + TX_BW_RATE);
drivers/net/ethernet/marvell/mv643xx_eth.c
431
writel(data, mp->shared->base + offset);
drivers/net/ethernet/marvell/mv643xx_eth.c
436
writel(data, mp->base + offset);
drivers/net/ethernet/marvell/mvmdio.c
141
writel(((mii_id << MVMDIO_SMI_PHY_ADDR_SHIFT) |
drivers/net/ethernet/marvell/mvmdio.c
169
writel(((mii_id << MVMDIO_SMI_PHY_ADDR_SHIFT) |
drivers/net/ethernet/marvell/mvmdio.c
197
writel(regnum, dev->regs + MVMDIO_XSMI_ADDR_REG);
drivers/net/ethernet/marvell/mvmdio.c
198
writel((mii_id << MVMDIO_XSMI_PHYADDR_SHIFT) |
drivers/net/ethernet/marvell/mvmdio.c
226
writel(regnum, dev->regs + MVMDIO_XSMI_ADDR_REG);
drivers/net/ethernet/marvell/mvmdio.c
227
writel((mii_id << MVMDIO_XSMI_PHYADDR_SHIFT) |
drivers/net/ethernet/marvell/mvmdio.c
266
writel(cfg, dev->regs + MVMDIO_XSMI_CFG_REG);
drivers/net/ethernet/marvell/mvmdio.c
275
writel(~MVMDIO_ERR_INT_SMI_DONE,
drivers/net/ethernet/marvell/mvmdio.c
374
writel(MVMDIO_ERR_INT_SMI_DONE,
drivers/net/ethernet/marvell/mvmdio.c
400
writel(0, dev->regs + MVMDIO_ERR_INT_MASK);
drivers/net/ethernet/marvell/mvmdio.c
420
writel(0, dev->regs + MVMDIO_ERR_INT_MASK);
drivers/net/ethernet/marvell/mvneta.c
764
writel(data, pp->base + offset);
drivers/net/ethernet/marvell/mvneta_bm.c
32
writel(data, priv->reg_base + offset);
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
1528
writel(val, ptr);
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
1590
writel(val, xpcs + MVPP22_XPCS_CFG0);
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
1594
writel(val, mpcs + MVPP22_MPCS_CTRL);
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
1599
writel(val, mpcs + MVPP22_MPCS_CLK_RESET);
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
161
writel(data, priv->swth_base[thread] + offset);
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
1612
writel(val, fca + MVPP22_FCA_CONTROL_REG);
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
1624
writel(lsb, fca + MVPP22_PERIODIC_COUNTER_LSB_REG);
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
1625
writel(msb, fca + MVPP22_PERIODIC_COUNTER_MSB_REG);
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
1711
writel(val, port->base + MVPP22_GMAC_INT_SUM_MASK);
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
1721
writel(val, port->base + MVPP22_XLG_EXT_INT_MASK);
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
1733
writel(val, port->base + MVPP22_XLG_EXT_INT_MASK);
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
1741
writel(val, port->base + MVPP22_GMAC_INT_SUM_MASK);
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
1759
writel(val, port->base + MVPP22_GMAC_INT_MASK);
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
1765
writel(val, port->base + MVPP22_XLG_INT_MASK);
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
1809
writel(val, port->base + MVPP22_XLG_CTRL0_REG);
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
1814
writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
1826
writel(val, port->base + MVPP22_XLG_CTRL0_REG);
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
1831
writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
1841
writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
1863
writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
2171
writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
2176
writel(val, port->base + MVPP22_XLG_CTRL0_REG);
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
2195
writel(val, mpcs + MVPP22_MPCS_CLK_RESET);
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
2198
writel(val & ~MVPP22_XPCS_CFG0_RESET_DIS, xpcs + MVPP22_XPCS_CFG0);
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
2221
writel(val, mpcs + MVPP22_MPCS_CLK_RESET);
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
2226
writel(val | MVPP22_XPCS_CFG0_RESET_DIS, xpcs + MVPP22_XPCS_CFG0);
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
2242
writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
2254
writel(val, port->base + MVPP22_XLG_CTRL1_REG);
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
2268
writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
4596
writel(ctrl3, port->base + MVPP22_XLG_CTRL3_REG);
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
6007
writel(val, port->base + MVPP22_XLG_CTRL0_REG);
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
6012
writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
6384
writel(an, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
6395
writel(val | MVPP2_GMAC_IN_BAND_RESTART_AN,
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
6397
writel(val & ~MVPP2_GMAC_IN_BAND_RESTART_AN,
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
6480
writel(ctrl0, port->base + MVPP2_GMAC_CTRL_0_REG);
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
6482
writel(ctrl2, port->base + MVPP2_GMAC_CTRL_2_REG);
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
6484
writel(ctrl4, port->base + MVPP22_GMAC_CTRL_4_REG);
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
6708
writel(val, port->base + MVPP22_XLG_CTRL0_REG);
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
6713
writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
6767
writel(lpi1 | MVPP2_GMAC_LPI_CTRL1_REQ_EN,
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
7485
writel(val, priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
7489
writel(val, priv->iface_base + MVPP22_SMI_MISC_CFG_REG);
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
7518
writel(MVPP2_EXT_GLOBAL_CTRL_DEFAULT,
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
76
writel(data, priv->swth_base[0] + offset);
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
96
writel(data, priv->cm3_base + offset);
drivers/net/ethernet/marvell/mvpp2/mvpp2_tai.c
72
writel(val, reg);
drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c
302
writel(reset_instr_cnt, iq->inst_cnt_reg);
drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c
679
writel(oct->oq[i]->max_count, oct->oq[i]->pkts_credit_reg);
drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c
323
writel(reset_instr_cnt, iq->inst_cnt_reg);
drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c
720
writel(oct->oq[i]->max_count, oct->oq[i]->pkts_credit_reg);
drivers/net/ethernet/marvell/octeon_ep/octep_ctrl_mbox.c
191
writel(pi, q->hw_prod);
drivers/net/ethernet/marvell/octeon_ep/octep_ctrl_mbox.c
254
writel(ci, q->hw_cons);
drivers/net/ethernet/marvell/octeon_ep/octep_main.c
571
writel(pkts_processed, iq->inst_cnt_reg);
drivers/net/ethernet/marvell/octeon_ep/octep_main.c
577
writel(last_pkt_count - pkts_pend, oq->pkts_sent_reg);
drivers/net/ethernet/marvell/octeon_ep/octep_main.c
977
writel(iq->fill_cnt, iq->doorbell_reg);
drivers/net/ethernet/marvell/octeon_ep/octep_main.h
344
writel(value, (octep_dev)->mmio[0].hw_addr + (reg_off))
drivers/net/ethernet/marvell/octeon_ep/octep_rx.c
294
writel(oct->oq[i]->max_count, oct->oq[i]->pkts_credit_reg);
drivers/net/ethernet/marvell/octeon_ep/octep_rx.c
343
writel(pkt_count, oq->pkts_sent_reg);
drivers/net/ethernet/marvell/octeon_ep/octep_rx.c
560
writel(desc_refilled, oq->pkts_credit_reg);
drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c
191
writel(reset_instr_cnt, iq->inst_cnt_reg);
drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cn9k.c
306
writel(oct->oq[i]->max_count, oct->oq[i]->pkts_credit_reg);
drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c
194
writel(reset_instr_cnt, iq->inst_cnt_reg);
drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_cnxk.c
349
writel(oct->oq[i]->max_count, oct->oq[i]->pkts_credit_reg);
drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_main.c
304
writel(pkts_processed, iq->inst_cnt_reg);
drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_main.c
310
writel(last_pkt_count - pkts_pend, oq->pkts_sent_reg);
drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_main.c
749
writel(iq->fill_cnt, iq->doorbell_reg);
drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_main.h
312
writel(value, (octep_vf_dev)->mmio.hw_addr + (reg_off))
drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_rx.c
295
writel(oct->oq[i]->max_count, oct->oq[i]->pkts_credit_reg);
drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_rx.c
345
writel(pkt_count, oq->pkts_sent_reg);
drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_rx.c
525
writel(desc_refilled, oq->pkts_credit_reg);
drivers/net/ethernet/marvell/prestera/prestera.h
342
writel(val, sw->dev->pp_regs + reg);
drivers/net/ethernet/marvell/prestera/prestera_pci.c
234
writel(val, PRESTERA_FW_REG_ADDR(fw, reg));
drivers/net/ethernet/marvell/prestera/prestera_pci.c
527
writel(val, PRESTERA_LDR_REG_ADDR(fw, reg));
drivers/net/ethernet/marvell/skge.h
2493
writel(val, hw->regs + reg);
drivers/net/ethernet/marvell/sky2.h
2332
writel(val, hw->regs + reg);
drivers/net/ethernet/mediatek/mtk_ppe.c
31
writel(val, ppe->base + reg);
drivers/net/ethernet/mediatek/mtk_wed.c
144
writel(val, dev->wlan.base + reg);
drivers/net/ethernet/mediatek/mtk_wed.c
429
writel(val, reg);
drivers/net/ethernet/mediatek/mtk_wed.c
431
writel(val, reg);
drivers/net/ethernet/mediatek/mtk_wed.c
435
writel(val, reg);
drivers/net/ethernet/mediatek/mtk_wed.c
437
writel(val, reg);
drivers/net/ethernet/mediatek/mtk_wed.h
104
writel(val, dev->hw->wdma + reg);
drivers/net/ethernet/mediatek/mtk_wed.h
128
writel(val, dev->tx_ring[ring].wpdma + reg);
drivers/net/ethernet/mediatek/mtk_wed.h
146
writel(val, dev->rx_ring[ring].wpdma + reg);
drivers/net/ethernet/mediatek/mtk_wed.h
164
writel(val, dev->txfree_ring.wpdma + reg);
drivers/net/ethernet/mediatek/mtk_wed_mcu.c
42
writel(val, mem_region[MTK_WED_WO_REGION_BOOT].addr + reg);
drivers/net/ethernet/mellanox/mlx4/crdump.c
69
writel(readl(cr_space + CR_ENABLE_BIT_OFFSET) & ~CR_ENABLE_BIT,
drivers/net/ethernet/mellanox/mlx4/crdump.c
73
writel(swab32(1), cr_space + dev->caps.health_buffer_addrs +
drivers/net/ethernet/mellanox/mlx4/crdump.c
81
writel(0, cr_space + dev->caps.health_buffer_addrs +
drivers/net/ethernet/mellanox/mlx4/crdump.c
86
writel(readl(cr_space + CR_ENABLE_BIT_OFFSET) | CR_ENABLE_BIT,
drivers/net/ethernet/mellanox/mlx4/eq.c
856
writel(priv->eq_table.clr_mask, priv->eq_table.clr_int);
drivers/net/ethernet/mellanox/mlx4/main.c
3264
writel(0, owner);
drivers/net/ethernet/mellanox/mlx4/reset.c
119
writel(MLX4_RESET_VALUE, reset + MLX4_RESET_OFFSET);
drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_main.c
329
writel(val, priv->plu_base + MLXBF_GIGE_PLU_TX_REG0);
drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_main.c
334
writel(val, priv->plu_base + MLXBF_GIGE_PLU_RX_REG0);
drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_mdio.c
220
writel(cmd, priv->mdio_io + priv->mdio_gw->gw_address);
drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_mdio.c
227
writel(0, priv->mdio_io + priv->mdio_gw->gw_address);
drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_mdio.c
236
writel(0, priv->mdio_io + priv->mdio_gw->gw_address);
drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_mdio.c
252
writel(cmd, priv->mdio_io + priv->mdio_gw->gw_address);
drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_mdio.c
260
writel(0, priv->mdio_io + priv->mdio_gw->gw_address);
drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_mdio.c
275
writel(val, priv->mdio_io + MLXBF2_GIGE_MDIO_CFG_OFFSET);
drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_mdio.c
279
writel(val, priv->mdio_io + MLXBF3_GIGE_MDIO_CFG_REG0);
drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_mdio.c
281
writel(val, priv->mdio_io + MLXBF3_GIGE_MDIO_CFG_REG1);
drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_mdio.c
284
writel(val, priv->mdio_io + MLXBF3_GIGE_MDIO_CFG_REG2);
drivers/net/ethernet/meta/fbnic/fbnic.h
124
writel(val, csr + reg);
drivers/net/ethernet/meta/fbnic/fbnic_pci.c
80
writel(val, csr + reg);
drivers/net/ethernet/meta/fbnic/fbnic_txrx.c
1144
writel(pkt_tail, ring->doorbell);
drivers/net/ethernet/meta/fbnic/fbnic_txrx.c
1348
writel(head & rcq->size_mask, rcq->doorbell);
drivers/net/ethernet/meta/fbnic/fbnic_txrx.c
386
writel(tail, ring->doorbell);
drivers/net/ethernet/meta/fbnic/fbnic_txrx.c
62
writel(val, csr_base + csr);
drivers/net/ethernet/meta/fbnic/fbnic_txrx.c
848
writel(head & cmpl->size_mask, cmpl->doorbell);
drivers/net/ethernet/meta/fbnic/fbnic_txrx.c
930
writel(i * FBNIC_BD_FRAG_COUNT, bdq->doorbell);
drivers/net/ethernet/micrel/ksz884x.c
1427
writel(interrupt, hw->io + KS884X_INTERRUPTS_STATUS);
drivers/net/ethernet/micrel/ksz884x.c
1433
writel(0, hw->io + KS884X_INTERRUPTS_ENABLE);
drivers/net/ethernet/micrel/ksz884x.c
1440
writel(interrupt, hw->io + KS884X_INTERRUPTS_ENABLE);
drivers/net/ethernet/micrel/ksz884x.c
1460
writel(hw->intr_set, hw->io + KS884X_INTERRUPTS_ENABLE);
drivers/net/ethernet/micrel/ksz884x.c
1628
writel(data_hi, hw->io + KS884X_ACC_DATA_4_OFFSET);
drivers/net/ethernet/micrel/ksz884x.c
1629
writel(data_lo, hw->io + KS884X_ACC_DATA_0_OFFSET);
drivers/net/ethernet/micrel/ksz884x.c
2096
writel(0, hw->io + addr);
drivers/net/ethernet/micrel/ksz884x.c
2853
writel(hw->rx_cfg, hw->io + KS_DMA_RX_CTRL);
drivers/net/ethernet/micrel/ksz884x.c
2855
writel(hw->tx_cfg, hw->io + KS_DMA_TX_CTRL);
drivers/net/ethernet/micrel/ksz884x.c
2900
writel(hw->tx_cfg, hw->io + KS_DMA_TX_CTRL);
drivers/net/ethernet/micrel/ksz884x.c
3201
writel(0, hw->io + KS8841_WOL_FRAME_BYTE0_OFFSET + i);
drivers/net/ethernet/micrel/ksz884x.c
3202
writel(0, hw->io + KS8841_WOL_FRAME_BYTE2_OFFSET + i);
drivers/net/ethernet/micrel/ksz884x.c
3231
writel(crc, hw->io + KS8841_WOL_FRAME_CRC_OFFSET + i);
drivers/net/ethernet/micrel/ksz884x.c
3491
writel(tx_addr, hw->io + KS_DMA_TX_ADDR);
drivers/net/ethernet/micrel/ksz884x.c
3492
writel(rx_addr, hw->io + KS_DMA_RX_ADDR);
drivers/net/ethernet/micrel/ksz884x.c
3504
writel(DMA_START, hw->io + KS_DMA_RX_START);
drivers/net/ethernet/micrel/ksz884x.c
3515
writel(hw->rx_cfg, hw->io + KS_DMA_RX_CTRL);
drivers/net/ethernet/micrel/ksz884x.c
3520
writel(DMA_START, hw->io + KS_DMA_RX_START);
drivers/net/ethernet/micrel/ksz884x.c
3539
writel((hw->rx_cfg & ~DMA_RX_ENABLE), hw->io + KS_DMA_RX_CTRL);
drivers/net/ethernet/micrel/ksz884x.c
3550
writel(hw->tx_cfg, hw->io + KS_DMA_TX_CTRL);
drivers/net/ethernet/micrel/ksz884x.c
3561
writel((hw->tx_cfg & ~DMA_TX_ENABLE), hw->io + KS_DMA_TX_CTRL);
drivers/net/ethernet/micrel/ksz884x.c
3648
writel(0, hw->io + KS_DMA_TX_START);
drivers/net/ethernet/micrel/ksz884x.c
3722
writel(mac_addr_lo, hw->io + index + KS_ADD_ADDR_0_LO);
drivers/net/ethernet/micrel/ksz884x.c
3723
writel(mac_addr_hi, hw->io + index + KS_ADD_ADDR_0_HI);
drivers/net/ethernet/micrel/ksz884x.c
3732
writel(0, hw->io + ADD_ADDR_INCR * i +
drivers/net/ethernet/micrel/ksz884x.c
3767
writel(0, hw->io + ADD_ADDR_INCR * i +
drivers/net/ethernet/micrel/ksz884x.c
6217
writel(hw->rx_cfg, hw->io + KS_DMA_RX_CTRL);
drivers/net/ethernet/microchip/lan966x/lan966x_main.h
727
writel(val, lan_addr(lan966x->regs, id, tinst, tcnt,
drivers/net/ethernet/microchip/lan966x/lan966x_main.h
742
writel(nval, lan_addr(lan966x->regs, id, tinst, tcnt, gbase, ginst,
drivers/net/ethernet/microchip/sparx5/sparx5_main.c
425
writel(cfg->init_val, cfg->init_reg);
drivers/net/ethernet/microchip/sparx5/sparx5_main.h
809
writel(val, spx5_addr(sparx5->regs, id, tinst, tcnt,
drivers/net/ethernet/microchip/sparx5/sparx5_main.h
819
writel(val, spx5_inst_addr(iomem,
drivers/net/ethernet/microchip/sparx5/sparx5_main.h
834
writel(nval, spx5_addr(sparx5->regs, id, tinst, tcnt, gbase, ginst,
drivers/net/ethernet/microchip/sparx5/sparx5_main.h
848
writel(nval, spx5_inst_addr(iomem, gbase, ginst, gcnt, gwidth, raddr,
drivers/net/ethernet/microsoft/mana/shm_channel.c
239
writel(*dword++, sc->base + i * SMC_BASIC_UNIT);
drivers/net/ethernet/microsoft/mana/shm_channel.c
277
writel(hdr.as_uint32, sc->base + SMC_LAST_DWORD * SMC_BASIC_UNIT);
drivers/net/ethernet/moxa/moxart_ether.c
106
writel(0x00001010, priv->base + REG_INT_TIMER_CTRL);
drivers/net/ethernet/moxa/moxart_ether.c
107
writel(0x00000001, priv->base + REG_APOLL_TIMER_CTRL);
drivers/net/ethernet/moxa/moxart_ether.c
108
writel(0x00000390, priv->base + REG_DMA_BLEN_CTRL);
drivers/net/ethernet/moxa/moxart_ether.c
111
writel(priv->reg_imr, priv->base + REG_INTERRUPT_MASK);
drivers/net/ethernet/moxa/moxart_ether.c
114
writel(priv->reg_maccr, priv->base + REG_MAC_CTRL);
drivers/net/ethernet/moxa/moxart_ether.c
159
writel(priv->tx_base, priv->base + REG_TXR_BASE_ADDRESS);
drivers/net/ethernet/moxa/moxart_ether.c
160
writel(priv->rx_base, priv->base + REG_RXR_BASE_ADDRESS);
drivers/net/ethernet/moxa/moxart_ether.c
192
writel(0, priv->base + REG_INTERRUPT_MASK);
drivers/net/ethernet/moxa/moxart_ether.c
195
writel(0, priv->base + REG_MAC_CTRL);
drivers/net/ethernet/moxa/moxart_ether.c
273
writel(priv->reg_imr, priv->base + REG_INTERRUPT_MASK);
drivers/net/ethernet/moxa/moxart_ether.c
321
writel(priv->reg_imr, priv->base + REG_INTERRUPT_MASK);
drivers/net/ethernet/moxa/moxart_ether.c
388
writel(0xffffffff, priv->base + REG_TX_POLL_DEMAND);
drivers/net/ethernet/moxa/moxart_ether.c
410
writel(readl(priv->base + REG_MCAST_HASH_TABLE1) |
drivers/net/ethernet/moxa/moxart_ether.c
414
writel(readl(priv->base + REG_MCAST_HASH_TABLE0) |
drivers/net/ethernet/moxa/moxart_ether.c
440
writel(priv->reg_maccr, priv->base + REG_MAC_CTRL);
drivers/net/ethernet/moxa/moxart_ether.c
47
writel(value, priv->base + reg);
drivers/net/ethernet/moxa/moxart_ether.c
93
writel(SW_RST, priv->base + REG_MAC_CTRL);
drivers/net/ethernet/moxa/moxart_ether.c
97
writel(0, priv->base + REG_INTERRUPT_MASK);
drivers/net/ethernet/mucse/rnpgbe/rnpgbe.h
70
writel((val), (hw)->hw_addr + (reg))
drivers/net/ethernet/mucse/rnpgbe/rnpgbe_mbx.c
35
writel(value, hw->hw_addr + mbx->fwpf_shm_base + reg);
drivers/net/ethernet/mucse/rnpgbe/rnpgbe_mbx.c
63
writel(value, hw->hw_addr + mbx->fwpf_ctrl_base + reg);
drivers/net/ethernet/myricom/myri10ge/myri10ge.c
1902
writel(swab32(pattern), mgp->sram + pattern_off);
drivers/net/ethernet/natsemi/natsemi.c
1010
writel(EE_Write0, ee_addr);
drivers/net/ethernet/natsemi/natsemi.c
1015
writel(dataval, ee_addr);
drivers/net/ethernet/natsemi/natsemi.c
1017
writel(dataval | EE_ShiftClk, ee_addr);
drivers/net/ethernet/natsemi/natsemi.c
1020
writel(EE_ChipSelect, ee_addr);
drivers/net/ethernet/natsemi/natsemi.c
1024
writel(EE_ChipSelect | EE_ShiftClk, ee_addr);
drivers/net/ethernet/natsemi/natsemi.c
1027
writel(EE_ChipSelect, ee_addr);
drivers/net/ethernet/natsemi/natsemi.c
1032
writel(EE_Write0, ee_addr);
drivers/net/ethernet/natsemi/natsemi.c
1033
writel(0, ee_addr);
drivers/net/ethernet/natsemi/natsemi.c
1053
writel(MII_ShiftClk, ioaddr + EECtrl);
drivers/net/ethernet/natsemi/natsemi.c
1055
writel(0, ioaddr + EECtrl);
drivers/net/ethernet/natsemi/natsemi.c
1068
writel(mdio_val, ioaddr + EECtrl);
drivers/net/ethernet/natsemi/natsemi.c
1070
writel(mdio_val | MII_ShiftClk, ioaddr + EECtrl);
drivers/net/ethernet/natsemi/natsemi.c
1073
writel(0, ioaddr + EECtrl);
drivers/net/ethernet/natsemi/natsemi.c
1272
writel(cfg | (CfgExtPhy | CfgPhyDis), ioaddr + ChipConfig);
drivers/net/ethernet/natsemi/natsemi.c
1307
writel(cfg, ioaddr + ChipConfig);
drivers/net/ethernet/natsemi/natsemi.c
1313
writel(bmcr | BMCR_RESET, ioaddr+BasicControl+(MII_BMCR<<2));
drivers/net/ethernet/natsemi/natsemi.c
1411
writel(i*2, ioaddr + RxFilterAddr);
drivers/net/ethernet/natsemi/natsemi.c
1416
writel(0xa+(i*2), ioaddr + RxFilterAddr);
drivers/net/ethernet/natsemi/natsemi.c
1421
writel(ChipReset, ioaddr + ChipCmd);
drivers/net/ethernet/natsemi/natsemi.c
1442
writel(cfg, ioaddr + ChipConfig);
drivers/net/ethernet/natsemi/natsemi.c
1445
writel(wcsr, ioaddr + WOLCmd);
drivers/net/ethernet/natsemi/natsemi.c
1450
writel(i*2, ioaddr + RxFilterAddr);
drivers/net/ethernet/natsemi/natsemi.c
1454
writel(0xa+(i*2), ioaddr + RxFilterAddr);
drivers/net/ethernet/natsemi/natsemi.c
1458
writel(rfcr, ioaddr + RxFilterAddr);
drivers/net/ethernet/natsemi/natsemi.c
1469
writel(RxReset, ioaddr + ChipCmd);
drivers/net/ethernet/natsemi/natsemi.c
1492
writel(EepromReload, ioaddr + PCIBusCfg);
drivers/net/ethernet/natsemi/natsemi.c
1513
writel(RxOff | TxOff, ioaddr + ChipCmd);
drivers/net/ethernet/natsemi/natsemi.c
1558
writel(i*2, ioaddr + RxFilterAddr);
drivers/net/ethernet/natsemi/natsemi.c
1561
writel(np->cur_rx_mode, ioaddr + RxFilterAddr);
drivers/net/ethernet/natsemi/natsemi.c
1703
writel(np->tx_config, ioaddr + TxConfig);
drivers/net/ethernet/natsemi/natsemi.c
1704
writel(np->rx_config, ioaddr + RxConfig);
drivers/net/ethernet/natsemi/natsemi.c
1718
writel(np->ring_dma, ioaddr + RxRingPtr);
drivers/net/ethernet/natsemi/natsemi.c
1719
writel(np->ring_dma + RX_RING_SIZE * sizeof(struct netdev_desc),
drivers/net/ethernet/natsemi/natsemi.c
1738
writel(np->tx_config, ioaddr + TxConfig);
drivers/net/ethernet/natsemi/natsemi.c
1748
writel(np->rx_config, ioaddr + RxConfig);
drivers/net/ethernet/natsemi/natsemi.c
1757
writel(np->SavedClkRun & ~PMEEnable, ioaddr + ClkRun);
drivers/net/ethernet/natsemi/natsemi.c
1767
writel(DEFAULT_INTR, ioaddr + IntrMask);
drivers/net/ethernet/natsemi/natsemi.c
1770
writel(RxOn | TxOn, ioaddr + ChipCmd);
drivers/net/ethernet/natsemi/natsemi.c
1771
writel(StatsClear, ioaddr + StatsCtrl); /* Clear Stats */
drivers/net/ethernet/natsemi/natsemi.c
1846
writel(RxOn, ioaddr + ChipCmd);
drivers/net/ethernet/natsemi/natsemi.c
2125
writel(TxOn, ioaddr + ChipCmd);
drivers/net/ethernet/natsemi/natsemi.c
2323
writel(np->ring_dma, ioaddr + RxRingPtr);
drivers/net/ethernet/natsemi/natsemi.c
2391
writel(RxOn, ioaddr + ChipCmd);
drivers/net/ethernet/natsemi/natsemi.c
2430
writel(np->tx_config, ioaddr + TxConfig);
drivers/net/ethernet/natsemi/natsemi.c
2518
writel(HASH_TABLE + i, ioaddr + RxFilterAddr);
drivers/net/ethernet/natsemi/natsemi.c
2519
writel((mc_filter[i + 1] << 8) + mc_filter[i],
drivers/net/ethernet/natsemi/natsemi.c
2523
writel(rx_mode, ioaddr + RxFilterAddr);
drivers/net/ethernet/natsemi/natsemi.c
2546
writel(np->ring_dma, ioaddr + RxRingPtr);
drivers/net/ethernet/natsemi/natsemi.c
2548
writel(RxOn | TxOn, ioaddr + ChipCmd);
drivers/net/ethernet/natsemi/natsemi.c
2727
writel(data, ioaddr + WOLCmd);
drivers/net/ethernet/natsemi/natsemi.c
2782
writel(addr, ioaddr + RxFilterAddr);
drivers/net/ethernet/natsemi/natsemi.c
2785
writel(addr | 0xa, ioaddr + RxFilterAddr);
drivers/net/ethernet/natsemi/natsemi.c
2788
writel(addr | 0xc, ioaddr + RxFilterAddr);
drivers/net/ethernet/natsemi/natsemi.c
2791
writel(addr | 0xe, ioaddr + RxFilterAddr);
drivers/net/ethernet/natsemi/natsemi.c
2795
writel(addr | RxFilterEnable, ioaddr + RxFilterAddr);
drivers/net/ethernet/natsemi/natsemi.c
2815
writel(addr | 0xa, ioaddr + RxFilterAddr);
drivers/net/ethernet/natsemi/natsemi.c
2818
writel(addr | 0xc, ioaddr + RxFilterAddr);
drivers/net/ethernet/natsemi/natsemi.c
2821
writel(addr | 0xe, ioaddr + RxFilterAddr);
drivers/net/ethernet/natsemi/natsemi.c
2824
writel(addr, ioaddr + RxFilterAddr);
drivers/net/ethernet/natsemi/natsemi.c
3030
writel(j*2, ioaddr + RxFilterAddr);
drivers/net/ethernet/natsemi/natsemi.c
3033
writel(rfcr, ioaddr + RxFilterAddr);
drivers/net/ethernet/natsemi/natsemi.c
3137
writel(0, ioaddr + RxRingPtr);
drivers/net/ethernet/natsemi/natsemi.c
3143
writel(np->SavedClkRun | PMEEnable | PMEStatus, ioaddr + ClkRun);
drivers/net/ethernet/natsemi/natsemi.c
3146
writel(RxOn, ioaddr + ChipCmd);
drivers/net/ethernet/natsemi/natsemi.c
3152
writel(WOLPkt | LinkChange, ioaddr + IntrMask);
drivers/net/ethernet/natsemi/natsemi.c
3202
writel(StatsFreeze, ioaddr + StatsCtrl);
drivers/net/ethernet/natsemi/natsemi.c
3227
writel(np->SavedClkRun, ioaddr + ClkRun);
drivers/net/ethernet/natsemi/natsemi.c
3312
writel(np->SavedClkRun, ioaddr + ClkRun);
drivers/net/ethernet/natsemi/natsemi.c
712
writel(1, ns_ioaddr(dev) + IntrEnable);
drivers/net/ethernet/natsemi/natsemi.c
718
writel(0, ns_ioaddr(dev) + IntrEnable);
drivers/net/ethernet/natsemi/ns83820.c
1302
writel(readl(dev->base + TXCFG)
drivers/net/ethernet/natsemi/ns83820.c
1305
writel(readl(dev->base + RXCFG) | RXCFG_RX_FD,
drivers/net/ethernet/natsemi/ns83820.c
1308
writel(readl(dev->base + GPIOR) | GPIOR_GP1_OUT,
drivers/net/ethernet/natsemi/ns83820.c
1326
writel(TBICR_MR_AN_ENABLE | TBICR_MR_RESTART_AN,
drivers/net/ethernet/natsemi/ns83820.c
1328
writel(TBICR_MR_AN_ENABLE, dev->base + TBICR);
drivers/net/ethernet/natsemi/ns83820.c
1335
writel(0x00000000, dev->base + TBICR);
drivers/net/ethernet/natsemi/ns83820.c
1374
writel(0, dev->base + IMR);
drivers/net/ethernet/natsemi/ns83820.c
1375
writel(0, dev->base + IER);
drivers/net/ethernet/natsemi/ns83820.c
1425
writel(dev->IMR_cache, dev->base + IMR);
drivers/net/ethernet/natsemi/ns83820.c
1447
writel(CR_RXE, dev->base + CR);
drivers/net/ethernet/natsemi/ns83820.c
1482
writel(dev->IMR_cache, dev->base + IMR);
drivers/net/ethernet/natsemi/ns83820.c
1496
writel(dev->IMR_cache, dev->base + IMR);
drivers/net/ethernet/natsemi/ns83820.c
1510
writel(dev->ihr, dev->base + IHR);
drivers/net/ethernet/natsemi/ns83820.c
1517
writel(which, dev->base + CR);
drivers/net/ethernet/natsemi/ns83820.c
1619
writel(0, dev->base + PQCR);
drivers/net/ethernet/natsemi/ns83820.c
1636
writel(0, dev->base + TXDP_HI);
drivers/net/ethernet/natsemi/ns83820.c
1637
writel(desc, dev->base + TXDP);
drivers/net/ethernet/natsemi/ns83820.c
1662
writel(i*2, dev->base + RFCR);
drivers/net/ethernet/natsemi/ns83820.c
1692
writel(val & ~RFCR_RFEN, rfcr);
drivers/net/ethernet/natsemi/ns83820.c
1693
writel(val, rfcr);
drivers/net/ethernet/natsemi/ns83820.c
1709
writel(enable, dev->base + PTSCR);
drivers/net/ethernet/natsemi/ns83820.c
1741
writel(dev->MEAR_cache, dev->base + MEAR);
drivers/net/ethernet/natsemi/ns83820.c
1752
writel(dev->MEAR_cache, dev->base + MEAR);
drivers/net/ethernet/natsemi/ns83820.c
1760
writel(dev->MEAR_cache, dev->base + MEAR);
drivers/net/ethernet/natsemi/ns83820.c
1774
writel(dev->MEAR_cache, dev->base + MEAR);
drivers/net/ethernet/natsemi/ns83820.c
1783
writel(dev->MEAR_cache, dev->base + MEAR);
drivers/net/ethernet/natsemi/ns83820.c
1994
writel(PTSCR_RBIST_RST, dev->base + PTSCR);
drivers/net/ethernet/natsemi/ns83820.c
2038
writel(readl(dev->base + GPIOR) | 0x3e8, dev->base + GPIOR);
drivers/net/ethernet/natsemi/ns83820.c
2041
writel(readl(dev->base + TANAR)
drivers/net/ethernet/natsemi/ns83820.c
2046
writel(TBICR_MR_AN_ENABLE | TBICR_MR_RESTART_AN,
drivers/net/ethernet/natsemi/ns83820.c
2048
writel(TBICR_MR_AN_ENABLE, dev->base + TBICR);
drivers/net/ethernet/natsemi/ns83820.c
2054
writel(dev->CFG_cache, dev->base + CFG);
drivers/net/ethernet/natsemi/ns83820.c
2059
writel(dev->CFG_cache | CFG_PHY_RST, dev->base + CFG);
drivers/net/ethernet/natsemi/ns83820.c
2061
writel(dev->CFG_cache, dev->base + CFG);
drivers/net/ethernet/natsemi/ns83820.c
2068
writel(readl(dev->base+0x20c) | 0xfe00, dev->base + 0x20c);
drivers/net/ethernet/natsemi/ns83820.c
2078
writel(TXCFG_CSI | TXCFG_HBI | TXCFG_ATP | TXCFG_MXDMA512
drivers/net/ethernet/natsemi/ns83820.c
2083
writel(0x000, dev->base + IHR);
drivers/net/ethernet/natsemi/ns83820.c
2084
writel(0x100, dev->base + IHR);
drivers/net/ethernet/natsemi/ns83820.c
2085
writel(0x000, dev->base + IHR);
drivers/net/ethernet/natsemi/ns83820.c
2093
writel(RXCFG_AEP | RXCFG_ARP | RXCFG_AIRL | RXCFG_RX_FD
drivers/net/ethernet/natsemi/ns83820.c
2099
writel(0, dev->base + PQCR);
drivers/net/ethernet/natsemi/ns83820.c
2119
writel(VRCR_INIT_VALUE, dev->base + VRCR);
drivers/net/ethernet/natsemi/ns83820.c
2130
writel(VTCR_INIT_VALUE, dev->base + VTCR);
drivers/net/ethernet/natsemi/ns83820.c
2134
writel((PCR_PS_MCAST | PCR_PS_DA | PCR_PSEN | PCR_FFLO_4K |
drivers/net/ethernet/natsemi/ns83820.c
2139
writel(0, dev->base + WCSR);
drivers/net/ethernet/natsemi/ns83820.c
455
#define __kick_rx(dev) writel(CR_RXE, dev->base + CR)
drivers/net/ethernet/natsemi/ns83820.c
463
writel(dev->rx_info.phy_descs +
drivers/net/ethernet/natsemi/ns83820.c
622
writel(readl(dev->base + TXCFG)
drivers/net/ethernet/natsemi/ns83820.c
625
writel(readl(dev->base + RXCFG) | RXCFG_RX_FD,
drivers/net/ethernet/natsemi/ns83820.c
628
writel(readl(dev->base + GPIOR) | GPIOR_GP1_OUT,
drivers/net/ethernet/natsemi/ns83820.c
639
writel((readl(dev->base + TXCFG)
drivers/net/ethernet/natsemi/ns83820.c
642
writel(readl(dev->base + RXCFG) & ~RXCFG_RX_FD,
drivers/net/ethernet/natsemi/ns83820.c
645
writel(readl(dev->base + GPIOR) & ~GPIOR_GP1_OUT,
drivers/net/ethernet/natsemi/ns83820.c
665
writel(readl(dev->base + TXCFG)
drivers/net/ethernet/natsemi/ns83820.c
668
writel(readl(dev->base + RXCFG) | RXCFG_RX_FD,
drivers/net/ethernet/natsemi/ns83820.c
671
writel(readl(dev->base + TXCFG)
drivers/net/ethernet/natsemi/ns83820.c
674
writel(readl(dev->base + RXCFG) & ~(RXCFG_RX_FD),
drivers/net/ethernet/natsemi/ns83820.c
680
writel(new_cfg, dev->base + CFG);
drivers/net/ethernet/natsemi/ns83820.c
723
writel(0, dev->base + RXDP_HI);
drivers/net/ethernet/natsemi/ns83820.c
724
writel(dev->rx_info.phy_descs, dev->base + RXDP);
drivers/net/ethernet/natsemi/ns83820.c
732
writel(0x0001, dev->base + CCSR);
drivers/net/ethernet/natsemi/ns83820.c
733
writel(0, dev->base + RFCR);
drivers/net/ethernet/natsemi/ns83820.c
734
writel(0x7fc00000, dev->base + RFCR);
drivers/net/ethernet/natsemi/ns83820.c
735
writel(0xffc00000, dev->base + RFCR);
drivers/net/ethernet/natsemi/ns83820.c
754
writel(dev->IMR_cache, dev->base + IMR);
drivers/net/ethernet/natsemi/ns83820.c
755
writel(1, dev->base + IER);
drivers/net/ethernet/natsemi/ns83820.c
775
writel(dev->IMR_cache, dev->base + IMR);
drivers/net/ethernet/natsemi/ns83820.c
786
writel(0, dev->base + RXDP_HI);
drivers/net/ethernet/natsemi/ns83820.c
787
writel(0, dev->base + RXDP);
drivers/net/ethernet/natsemi/ns83820.c
932
writel(ihr, dev->base + IHR);
drivers/net/ethernet/natsemi/ns83820.c
936
writel(dev->IMR_cache, dev->base + IMR);
drivers/net/ethernet/natsemi/ns83820.c
949
writel(CR_TXE, dev->base + CR);
drivers/net/ethernet/netronome/nfp/nfp_net.h
807
writel(val, nn->dp.ctrl_bar + off);
drivers/net/ethernet/netronome/nfp/nfp_net.h
858
writel(val, q + NFP_QCP_QUEUE_ADD_RPTR);
drivers/net/ethernet/netronome/nfp/nfp_net.h
869
writel(val, q + NFP_QCP_QUEUE_ADD_WPTR);
drivers/net/ethernet/netronome/nfp/nfp_net_ethtool.c
1507
writel(new_rss_cfg, nn->dp.ctrl_bar + NFP_NET_CFG_RSS_CTRL);
drivers/net/ethernet/netronome/nfp/nfp_net_sriov.c
142
writel(vlan_tag, app->pf->vfcfg_tbl2 + vf_offset + NFP_NET_VF_CFG_VLAN);
drivers/net/ethernet/netronome/nfp/nfp_net_sriov.c
171
writel(ratevalue,
drivers/net/ethernet/netronome/nfp/nfp_net_sriov.c
83
writel(get_unaligned_be32(mac), app->pf->vfcfg_tbl2 + vf_offset);
drivers/net/ethernet/netronome/nfp/nfpcore/nfp6000_pcie.c
1116
writel(*(src++), priv->data + i);
drivers/net/ethernet/netronome/nfp/nfpcore/nfp6000_pcie.c
1173
writel(csr[0], nfp->iomem.csr +
drivers/net/ethernet/netronome/nfp/nfpcore/nfp6000_pcie.c
1176
writel(csr[1], nfp->iomem.csr +
drivers/net/ethernet/netronome/nfp/nfpcore/nfp6000_pcie.c
1179
writel(csr[2], nfp->iomem.csr +
drivers/net/ethernet/netronome/nfp/nfpcore/nfp6000_pcie.c
275
writel(newcfg, nfp->iomem.csr + xbar);
drivers/net/ethernet/netronome/nfp/nic/dcb.c
203
writel(enable, dcb->dcbcfg_tbl + dcb->cfg_offset +
drivers/net/ethernet/ni/nixge.c
209
writel(val, priv->dma_regs + offset);
drivers/net/ethernet/ni/nixge.c
215
writel(lower_32_bits(addr), priv->dma_regs + offset);
drivers/net/ethernet/ni/nixge.c
217
writel(upper_32_bits(addr), priv->dma_regs + offset + 4);
drivers/net/ethernet/ni/nixge.c
228
writel(val, priv->ctrl_regs + offset);
drivers/net/ethernet/nvidia/forcedeth.c
1003
writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
drivers/net/ethernet/nvidia/forcedeth.c
1005
writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
drivers/net/ethernet/nvidia/forcedeth.c
1008
writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
drivers/net/ethernet/nvidia/forcedeth.c
1009
writel(dma_high(np->ring_addr), base + NvRegRxRingPhysAddrHigh);
drivers/net/ethernet/nvidia/forcedeth.c
1012
writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
drivers/net/ethernet/nvidia/forcedeth.c
1013
writel(dma_high(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddrHigh);
drivers/net/ethernet/nvidia/forcedeth.c
1065
writel(powerstate, base + NvRegPowerState2);
drivers/net/ethernet/nvidia/forcedeth.c
1106
writel(mask, base + NvRegIrqMask);
drivers/net/ethernet/nvidia/forcedeth.c
1115
writel(mask, base + NvRegIrqMask);
drivers/net/ethernet/nvidia/forcedeth.c
1118
writel(0, base + NvRegMSIIrqMask);
drivers/net/ethernet/nvidia/forcedeth.c
1119
writel(0, base + NvRegIrqMask);
drivers/net/ethernet/nvidia/forcedeth.c
1134
writel(NVREG_MIISTAT_MASK_RW, base + NvRegMIIStatus);
drivers/net/ethernet/nvidia/forcedeth.c
1138
writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
drivers/net/ethernet/nvidia/forcedeth.c
1144
writel(value, base + NvRegMIIData);
drivers/net/ethernet/nvidia/forcedeth.c
1147
writel(reg, base + NvRegMIIControl);
drivers/net/ethernet/nvidia/forcedeth.c
1220
writel(powerstate, base + NvRegPowerState2);
drivers/net/ethernet/nvidia/forcedeth.c
1224
writel(powerstate, base + NvRegPowerState2);
drivers/net/ethernet/nvidia/forcedeth.c
1526
writel(rx_ctrl, base + NvRegReceiverControl);
drivers/net/ethernet/nvidia/forcedeth.c
1529
writel(np->linkspeed, base + NvRegLinkSpeed);
drivers/net/ethernet/nvidia/forcedeth.c
1534
writel(rx_ctrl, base + NvRegReceiverControl);
drivers/net/ethernet/nvidia/forcedeth.c
1548
writel(rx_ctrl, base + NvRegReceiverControl);
drivers/net/ethernet/nvidia/forcedeth.c
1556
writel(0, base + NvRegLinkSpeed);
drivers/net/ethernet/nvidia/forcedeth.c
1568
writel(tx_ctrl, base + NvRegTransmitterControl);
drivers/net/ethernet/nvidia/forcedeth.c
1582
writel(tx_ctrl, base + NvRegTransmitterControl);
drivers/net/ethernet/nvidia/forcedeth.c
1590
writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV,
drivers/net/ethernet/nvidia/forcedeth.c
1611
writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
drivers/net/ethernet/nvidia/forcedeth.c
1614
writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
drivers/net/ethernet/nvidia/forcedeth.c
1624
writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
drivers/net/ethernet/nvidia/forcedeth.c
1632
writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset);
drivers/net/ethernet/nvidia/forcedeth.c
1635
writel(0, base + NvRegMacReset);
drivers/net/ethernet/nvidia/forcedeth.c
1640
writel(temp1, base + NvRegMacAddrA);
drivers/net/ethernet/nvidia/forcedeth.c
1641
writel(temp2, base + NvRegMacAddrB);
drivers/net/ethernet/nvidia/forcedeth.c
1642
writel(temp3, base + NvRegTransmitPoll);
drivers/net/ethernet/nvidia/forcedeth.c
1644
writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
drivers/net/ethernet/nvidia/forcedeth.c
2097
writel(reg, base + NvRegSlotTime);
drivers/net/ethernet/nvidia/forcedeth.c
2174
writel(temp, base + NvRegBackOffControl);
drivers/net/ethernet/nvidia/forcedeth.c
2183
writel(temp, base + NvRegBackOffControl);
drivers/net/ethernet/nvidia/forcedeth.c
2358
writel(txrxctl_kick, get_hwbase(dev) + NvRegTxRxControl);
drivers/net/ethernet/nvidia/forcedeth.c
2563
writel(txrxctl_kick, get_hwbase(dev) + NvRegTxRxControl);
drivers/net/ethernet/nvidia/forcedeth.c
2583
writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
drivers/net/ethernet/nvidia/forcedeth.c
3119
writel(np->rx_buf_sz, base + NvRegOffloadConfig);
drivers/net/ethernet/nvidia/forcedeth.c
3121
writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
drivers/net/ethernet/nvidia/forcedeth.c
3124
writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
drivers/net/ethernet/nvidia/forcedeth.c
3147
writel(mac[0], base + NvRegMacAddrA);
drivers/net/ethernet/nvidia/forcedeth.c
3148
writel(mac[1], base + NvRegMacAddrB);
drivers/net/ethernet/nvidia/forcedeth.c
3243
writel(addr[0], base + NvRegMulticastAddrA);
drivers/net/ethernet/nvidia/forcedeth.c
3244
writel(addr[1], base + NvRegMulticastAddrB);
drivers/net/ethernet/nvidia/forcedeth.c
3245
writel(mask[0], base + NvRegMulticastMaskA);
drivers/net/ethernet/nvidia/forcedeth.c
3246
writel(mask[1], base + NvRegMulticastMaskB);
drivers/net/ethernet/nvidia/forcedeth.c
3247
writel(pff, base + NvRegPacketFilterFlags);
drivers/net/ethernet/nvidia/forcedeth.c
3262
writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags);
drivers/net/ethernet/nvidia/forcedeth.c
3265
writel(pff, base + NvRegPacketFilterFlags);
drivers/net/ethernet/nvidia/forcedeth.c
3277
writel(readl(base + NvRegTxPauseFrameLimit)|NVREG_TX_PAUSEFRAMELIMIT_ENABLE, base + NvRegTxPauseFrameLimit);
drivers/net/ethernet/nvidia/forcedeth.c
3279
writel(pause_enable, base + NvRegTxPauseFrame);
drivers/net/ethernet/nvidia/forcedeth.c
3280
writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1);
drivers/net/ethernet/nvidia/forcedeth.c
3283
writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame);
drivers/net/ethernet/nvidia/forcedeth.c
3284
writel(regmisc, base + NvRegMisc1);
drivers/net/ethernet/nvidia/forcedeth.c
3311
writel(phyreg, base + NvRegSlotTime);
drivers/net/ethernet/nvidia/forcedeth.c
3323
writel(phyreg, base + NvRegPhyInterface);
drivers/net/ethernet/nvidia/forcedeth.c
3334
writel(txreg, base + NvRegTxDeferral);
drivers/net/ethernet/nvidia/forcedeth.c
3345
writel(txreg, base + NvRegTxWatermark);
drivers/net/ethernet/nvidia/forcedeth.c
3347
writel(NVREG_MISC1_FORCE | (np->duplex ? 0 : NVREG_MISC1_HD),
drivers/net/ethernet/nvidia/forcedeth.c
3350
writel(np->linkspeed, base + NvRegLinkSpeed);
drivers/net/ethernet/nvidia/forcedeth.c
3493
writel(phyreg, base + NvRegSlotTime);
drivers/net/ethernet/nvidia/forcedeth.c
3504
writel(phyreg, base + NvRegPhyInterface);
drivers/net/ethernet/nvidia/forcedeth.c
3526
writel(txreg, base + NvRegTxDeferral);
drivers/net/ethernet/nvidia/forcedeth.c
3536
writel(txreg, base + NvRegTxWatermark);
drivers/net/ethernet/nvidia/forcedeth.c
3538
writel(NVREG_MISC1_FORCE | (np->duplex ? 0 : NVREG_MISC1_HD),
drivers/net/ethernet/nvidia/forcedeth.c
3541
writel(np->linkspeed, base + NvRegLinkSpeed);
drivers/net/ethernet/nvidia/forcedeth.c
3612
writel(NVREG_MIISTAT_LINKCHANGE, base + NvRegMIIStatus);
drivers/net/ethernet/nvidia/forcedeth.c
3627
writel(0, base + NvRegMSIIrqMask);
drivers/net/ethernet/nvidia/forcedeth.c
3628
writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
drivers/net/ethernet/nvidia/forcedeth.c
3668
writel(np->events, base + NvRegIrqStatus);
drivers/net/ethernet/nvidia/forcedeth.c
3671
writel(np->events, base + NvRegMSIXIrqStatus);
drivers/net/ethernet/nvidia/forcedeth.c
3682
writel(0, base + NvRegIrqMask);
drivers/net/ethernet/nvidia/forcedeth.c
3701
writel(np->events, base + NvRegIrqStatus);
drivers/net/ethernet/nvidia/forcedeth.c
3704
writel(np->events, base + NvRegMSIXIrqStatus);
drivers/net/ethernet/nvidia/forcedeth.c
3715
writel(0, base + NvRegIrqMask);
drivers/net/ethernet/nvidia/forcedeth.c
3733
writel(events, base + NvRegMSIXIrqStatus);
drivers/net/ethernet/nvidia/forcedeth.c
3745
writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask);
drivers/net/ethernet/nvidia/forcedeth.c
3829
writel(np->irqmask, base + NvRegIrqMask);
drivers/net/ethernet/nvidia/forcedeth.c
3845
writel(events, base + NvRegMSIXIrqStatus);
drivers/net/ethernet/nvidia/forcedeth.c
3862
writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
drivers/net/ethernet/nvidia/forcedeth.c
3890
writel(events, base + NvRegMSIXIrqStatus);
drivers/net/ethernet/nvidia/forcedeth.c
3914
writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
drivers/net/ethernet/nvidia/forcedeth.c
3928
writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
drivers/net/ethernet/nvidia/forcedeth.c
3955
writel(events & NVREG_IRQ_TIMER, base + NvRegIrqStatus);
drivers/net/ethernet/nvidia/forcedeth.c
3958
writel(events & NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus);
drivers/net/ethernet/nvidia/forcedeth.c
3987
writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0);
drivers/net/ethernet/nvidia/forcedeth.c
3994
writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);
drivers/net/ethernet/nvidia/forcedeth.c
4061
writel(0, base + NvRegMSIXMap0);
drivers/net/ethernet/nvidia/forcedeth.c
4062
writel(0, base + NvRegMSIXMap1);
drivers/net/ethernet/nvidia/forcedeth.c
4080
writel(0, base + NvRegMSIXMap0);
drivers/net/ethernet/nvidia/forcedeth.c
4081
writel(0, base + NvRegMSIXMap1);
drivers/net/ethernet/nvidia/forcedeth.c
4101
writel(0, base + NvRegMSIMap0);
drivers/net/ethernet/nvidia/forcedeth.c
4102
writel(0, base + NvRegMSIMap1);
drivers/net/ethernet/nvidia/forcedeth.c
4104
writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
drivers/net/ethernet/nvidia/forcedeth.c
4201
writel(np->rx_buf_sz, base + NvRegOffloadConfig);
drivers/net/ethernet/nvidia/forcedeth.c
4203
writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
drivers/net/ethernet/nvidia/forcedeth.c
4206
writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
drivers/net/ethernet/nvidia/forcedeth.c
4210
writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
drivers/net/ethernet/nvidia/forcedeth.c
4212
writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
drivers/net/ethernet/nvidia/forcedeth.c
4222
writel(mask, base + NvRegIrqMask);
drivers/net/ethernet/nvidia/forcedeth.c
4310
writel(flags, base + NvRegWakeUpFlags);
drivers/net/ethernet/nvidia/forcedeth.c
4760
writel(np->rx_buf_sz, base + NvRegOffloadConfig);
drivers/net/ethernet/nvidia/forcedeth.c
4762
writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
drivers/net/ethernet/nvidia/forcedeth.c
4765
writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
drivers/net/ethernet/nvidia/forcedeth.c
4941
writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
drivers/net/ethernet/nvidia/forcedeth.c
4968
writel(np->txrxctl_bits, base + NvRegTxRxControl);
drivers/net/ethernet/nvidia/forcedeth.c
5044
writel(orig_read, base + nv_registers_test[i].reg);
drivers/net/ethernet/nvidia/forcedeth.c
5053
writel(orig_read, base + nv_registers_test[i].reg);
drivers/net/ethernet/nvidia/forcedeth.c
5085
writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
drivers/net/ethernet/nvidia/forcedeth.c
5086
writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
drivers/net/ethernet/nvidia/forcedeth.c
5102
writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
drivers/net/ethernet/nvidia/forcedeth.c
5104
writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
drivers/net/ethernet/nvidia/forcedeth.c
5113
writel(save_poll_interval, base + NvRegPollingInterval);
drivers/net/ethernet/nvidia/forcedeth.c
5114
writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
drivers/net/ethernet/nvidia/forcedeth.c
5150
writel(NVREG_MISC1_FORCE, base + NvRegMisc1);
drivers/net/ethernet/nvidia/forcedeth.c
5151
writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags);
drivers/net/ethernet/nvidia/forcedeth.c
5154
writel(np->rx_buf_sz, base + NvRegOffloadConfig);
drivers/net/ethernet/nvidia/forcedeth.c
5156
writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
drivers/net/ethernet/nvidia/forcedeth.c
5190
writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
drivers/net/ethernet/nvidia/forcedeth.c
5241
writel(misc1_flags, base + NvRegMisc1);
drivers/net/ethernet/nvidia/forcedeth.c
5242
writel(filter_flags, base + NvRegPacketFilterFlags);
drivers/net/ethernet/nvidia/forcedeth.c
5272
writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
drivers/net/ethernet/nvidia/forcedeth.c
5274
writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
drivers/net/ethernet/nvidia/forcedeth.c
5313
writel(np->rx_buf_sz, base + NvRegOffloadConfig);
drivers/net/ethernet/nvidia/forcedeth.c
5315
writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
drivers/net/ethernet/nvidia/forcedeth.c
5318
writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
drivers/net/ethernet/nvidia/forcedeth.c
5383
writel(tx_ctrl, base + NvRegTransmitterControl);
drivers/net/ethernet/nvidia/forcedeth.c
5408
writel(tx_ctrl, base + NvRegTransmitterControl);
drivers/net/ethernet/nvidia/forcedeth.c
5423
writel(NVREG_MGMTUNITGETVERSION, base + NvRegMgmtUnitGetVersion);
drivers/net/ethernet/nvidia/forcedeth.c
5424
writel(data_ready ^ NVREG_XMITCTL_DATA_START, base + NvRegTransmitterControl);
drivers/net/ethernet/nvidia/forcedeth.c
5459
writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
drivers/net/ethernet/nvidia/forcedeth.c
5460
writel(0, base + NvRegMulticastAddrB);
drivers/net/ethernet/nvidia/forcedeth.c
5461
writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
drivers/net/ethernet/nvidia/forcedeth.c
5462
writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
drivers/net/ethernet/nvidia/forcedeth.c
5463
writel(0, base + NvRegPacketFilterFlags);
drivers/net/ethernet/nvidia/forcedeth.c
5465
writel(0, base + NvRegTransmitterControl);
drivers/net/ethernet/nvidia/forcedeth.c
5466
writel(0, base + NvRegReceiverControl);
drivers/net/ethernet/nvidia/forcedeth.c
5468
writel(0, base + NvRegAdapterControl);
drivers/net/ethernet/nvidia/forcedeth.c
5471
writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame);
drivers/net/ethernet/nvidia/forcedeth.c
5477
writel(0, base + NvRegLinkSpeed);
drivers/net/ethernet/nvidia/forcedeth.c
5478
writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
drivers/net/ethernet/nvidia/forcedeth.c
5480
writel(0, base + NvRegUnknownSetupReg6);
drivers/net/ethernet/nvidia/forcedeth.c
5486
writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
drivers/net/ethernet/nvidia/forcedeth.c
5489
writel(np->linkspeed, base + NvRegLinkSpeed);
drivers/net/ethernet/nvidia/forcedeth.c
5491
writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark);
drivers/net/ethernet/nvidia/forcedeth.c
5493
writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark);
drivers/net/ethernet/nvidia/forcedeth.c
5494
writel(np->txrxctl_bits, base + NvRegTxRxControl);
drivers/net/ethernet/nvidia/forcedeth.c
5495
writel(np->vlanctl_bits, base + NvRegVlanControl);
drivers/net/ethernet/nvidia/forcedeth.c
5497
writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
drivers/net/ethernet/nvidia/forcedeth.c
5504
writel(0, base + NvRegMIIMask);
drivers/net/ethernet/nvidia/forcedeth.c
5505
writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
drivers/net/ethernet/nvidia/forcedeth.c
5506
writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
drivers/net/ethernet/nvidia/forcedeth.c
5508
writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
drivers/net/ethernet/nvidia/forcedeth.c
5509
writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
drivers/net/ethernet/nvidia/forcedeth.c
5510
writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
drivers/net/ethernet/nvidia/forcedeth.c
5511
writel(np->rx_buf_sz, base + NvRegOffloadConfig);
drivers/net/ethernet/nvidia/forcedeth.c
5513
writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
drivers/net/ethernet/nvidia/forcedeth.c
5518
writel(low|NVREG_SLOTTIME_DEFAULT, base + NvRegSlotTime);
drivers/net/ethernet/nvidia/forcedeth.c
5522
writel(NVREG_SLOTTIME_LEGBF_ENABLED|NVREG_SLOTTIME_10_100_FULL|low, base + NvRegSlotTime);
drivers/net/ethernet/nvidia/forcedeth.c
5524
writel(NVREG_SLOTTIME_10_100_FULL, base + NvRegSlotTime);
drivers/net/ethernet/nvidia/forcedeth.c
5528
writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral);
drivers/net/ethernet/nvidia/forcedeth.c
5529
writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral);
drivers/net/ethernet/nvidia/forcedeth.c
5532
writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
drivers/net/ethernet/nvidia/forcedeth.c
5534
writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
drivers/net/ethernet/nvidia/forcedeth.c
5536
writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
drivers/net/ethernet/nvidia/forcedeth.c
5537
writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
drivers/net/ethernet/nvidia/forcedeth.c
5538
writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
drivers/net/ethernet/nvidia/forcedeth.c
5540
writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
drivers/net/ethernet/nvidia/forcedeth.c
5541
writel(NVREG_MII_LINKCHANGE, base + NvRegMIIMask);
drivers/net/ethernet/nvidia/forcedeth.c
5543
writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags);
drivers/net/ethernet/nvidia/forcedeth.c
5547
writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
drivers/net/ethernet/nvidia/forcedeth.c
5551
writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
drivers/net/ethernet/nvidia/forcedeth.c
5555
writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
drivers/net/ethernet/nvidia/forcedeth.c
5556
writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
drivers/net/ethernet/nvidia/forcedeth.c
5567
writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
drivers/net/ethernet/nvidia/forcedeth.c
5568
writel(0, base + NvRegMulticastAddrB);
drivers/net/ethernet/nvidia/forcedeth.c
5569
writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
drivers/net/ethernet/nvidia/forcedeth.c
5570
writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
drivers/net/ethernet/nvidia/forcedeth.c
5571
writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
drivers/net/ethernet/nvidia/forcedeth.c
5576
writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
drivers/net/ethernet/nvidia/forcedeth.c
5649
writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
drivers/net/ethernet/nvidia/forcedeth.c
5912
writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
drivers/net/ethernet/nvidia/forcedeth.c
5937
writel(0, base + NvRegWakeUpFlags);
drivers/net/ethernet/nvidia/forcedeth.c
5949
writel(powerstate, base + NvRegPowerState2);
drivers/net/ethernet/nvidia/forcedeth.c
6005
writel(0, base + NvRegMIIMask);
drivers/net/ethernet/nvidia/forcedeth.c
6010
writel(phystate, base + NvRegAdapterControl);
drivers/net/ethernet/nvidia/forcedeth.c
6012
writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
drivers/net/ethernet/nvidia/forcedeth.c
6131
writel(phystate|NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl);
drivers/net/ethernet/nvidia/forcedeth.c
6179
writel(np->orig_mac[0], base + NvRegMacAddrA);
drivers/net/ethernet/nvidia/forcedeth.c
6180
writel(np->orig_mac[1], base + NvRegMacAddrB);
drivers/net/ethernet/nvidia/forcedeth.c
6181
writel(readl(base + NvRegTransmitPoll) & ~NVREG_TRANSMITPOLL_MAC_ADDR_REV,
drivers/net/ethernet/nvidia/forcedeth.c
6240
writel(np->saved_config_space[i], base+i*sizeof(u32));
drivers/net/ethernet/nxp/lpc_eth.c
1021
writel(0, LPC_ENET_MAC1(pldat->net_base));
drivers/net/ethernet/nxp/lpc_eth.c
1022
writel(0, LPC_ENET_MAC2(pldat->net_base));
drivers/net/ethernet/nxp/lpc_eth.c
1075
writel(txidx, LPC_ENET_TXPRODUCEINDEX(pldat->net_base));
drivers/net/ethernet/nxp/lpc_eth.c
1131
writel(tmp32, LPC_ENET_RXFILTER_CTRL(pldat->net_base));
drivers/net/ethernet/nxp/lpc_eth.c
1148
writel(hashlo, LPC_ENET_HASHFILTERL(pldat->net_base));
drivers/net/ethernet/nxp/lpc_eth.c
1149
writel(hashhi, LPC_ENET_HASHFILTERH(pldat->net_base));
drivers/net/ethernet/nxp/lpc_eth.c
428
writel(tmp, LPC_ENET_SA2(pldat->net_base));
drivers/net/ethernet/nxp/lpc_eth.c
430
writel(tmp, LPC_ENET_SA1(pldat->net_base));
drivers/net/ethernet/nxp/lpc_eth.c
432
writel(tmp, LPC_ENET_SA0(pldat->net_base));
drivers/net/ethernet/nxp/lpc_eth.c
460
writel(tmp, LPC_ENET_MAC2(pldat->net_base));
drivers/net/ethernet/nxp/lpc_eth.c
463
writel(tmp, LPC_ENET_COMMAND(pldat->net_base));
drivers/net/ethernet/nxp/lpc_eth.c
464
writel(LPC_IPGT_LOAD(0x15), LPC_ENET_IPGT(pldat->net_base));
drivers/net/ethernet/nxp/lpc_eth.c
468
writel(tmp, LPC_ENET_MAC2(pldat->net_base));
drivers/net/ethernet/nxp/lpc_eth.c
471
writel(tmp, LPC_ENET_COMMAND(pldat->net_base));
drivers/net/ethernet/nxp/lpc_eth.c
472
writel(LPC_IPGT_LOAD(0x12), LPC_ENET_IPGT(pldat->net_base));
drivers/net/ethernet/nxp/lpc_eth.c
476
writel(LPC_SUPP_SPEED, LPC_ENET_SUPP(pldat->net_base));
drivers/net/ethernet/nxp/lpc_eth.c
478
writel(0, LPC_ENET_SUPP(pldat->net_base));
drivers/net/ethernet/nxp/lpc_eth.c
484
writel((LPC_MAC1_RESET_TX | LPC_MAC1_RESET_MCS_TX | LPC_MAC1_RESET_RX |
drivers/net/ethernet/nxp/lpc_eth.c
487
writel((LPC_COMMAND_REG_RESET | LPC_COMMAND_TXRESET |
drivers/net/ethernet/nxp/lpc_eth.c
494
writel(LPC_MCFG_RESET_MII_MGMT, LPC_ENET_MCFG(pldat->net_base));
drivers/net/ethernet/nxp/lpc_eth.c
497
writel(LPC_MCFG_CLOCK_SELECT(LPC_MCFG_CLOCK_HOST_DIV_28),
drivers/net/ethernet/nxp/lpc_eth.c
515
writel((LPC_MACINT_RXDONEINTEN | LPC_MACINT_TXDONEINTEN),
drivers/net/ethernet/nxp/lpc_eth.c
521
writel(0, LPC_ENET_INTENABLE(regbase));
drivers/net/ethernet/nxp/lpc_eth.c
584
writel((ENET_TX_DESC - 1),
drivers/net/ethernet/nxp/lpc_eth.c
586
writel(__va_to_pa(pldat->tx_desc_v, pldat),
drivers/net/ethernet/nxp/lpc_eth.c
588
writel(__va_to_pa(pldat->tx_stat_v, pldat),
drivers/net/ethernet/nxp/lpc_eth.c
590
writel((ENET_RX_DESC - 1),
drivers/net/ethernet/nxp/lpc_eth.c
592
writel(__va_to_pa(pldat->rx_desc_v, pldat),
drivers/net/ethernet/nxp/lpc_eth.c
594
writel(__va_to_pa(pldat->rx_stat_v, pldat),
drivers/net/ethernet/nxp/lpc_eth.c
605
writel(tmp, LPC_ENET_COMMAND(pldat->net_base));
drivers/net/ethernet/nxp/lpc_eth.c
608
writel(tmp, LPC_ENET_MAC1(pldat->net_base));
drivers/net/ethernet/nxp/lpc_eth.c
611
writel(LPC_MAC1_PASS_ALL_RX_FRAMES, LPC_ENET_MAC1(pldat->net_base));
drivers/net/ethernet/nxp/lpc_eth.c
612
writel((LPC_MAC2_PAD_CRC_ENABLE | LPC_MAC2_CRC_ENABLE),
drivers/net/ethernet/nxp/lpc_eth.c
614
writel(ENET_MAXF_SIZE, LPC_ENET_MAXF(pldat->net_base));
drivers/net/ethernet/nxp/lpc_eth.c
617
writel((LPC_CLRT_LOAD_RETRY_MAX(0xF) |
drivers/net/ethernet/nxp/lpc_eth.c
620
writel(LPC_IPGR_LOAD_PART2(0x12), LPC_ENET_IPGR(pldat->net_base));
drivers/net/ethernet/nxp/lpc_eth.c
623
writel(LPC_COMMAND_PASSRUNTFRAME,
drivers/net/ethernet/nxp/lpc_eth.c
626
writel((LPC_COMMAND_PASSRUNTFRAME | LPC_COMMAND_RMII),
drivers/net/ethernet/nxp/lpc_eth.c
628
writel(LPC_SUPP_RESET_RMII, LPC_ENET_SUPP(pldat->net_base));
drivers/net/ethernet/nxp/lpc_eth.c
637
writel((LPC_RXFLTRW_ACCEPTUBROADCAST | LPC_RXFLTRW_ACCEPTPERFECT),
drivers/net/ethernet/nxp/lpc_eth.c
646
writel(0xFFFF, LPC_ENET_INTCLEAR(pldat->net_base));
drivers/net/ethernet/nxp/lpc_eth.c
653
writel(tmp, LPC_ENET_COMMAND(pldat->net_base));
drivers/net/ethernet/nxp/lpc_eth.c
656
writel(tmp, LPC_ENET_MAC1(pldat->net_base));
drivers/net/ethernet/nxp/lpc_eth.c
663
writel(0, LPC_ENET_MAC1(pldat->net_base));
drivers/net/ethernet/nxp/lpc_eth.c
664
writel(0, LPC_ENET_MAC2(pldat->net_base));
drivers/net/ethernet/nxp/lpc_eth.c
676
writel(((phy_id << 8) | phyreg), LPC_ENET_MADR(pldat->net_base));
drivers/net/ethernet/nxp/lpc_eth.c
677
writel(LPC_MCMD_READ, LPC_ENET_MCMD(pldat->net_base));
drivers/net/ethernet/nxp/lpc_eth.c
687
writel(0, LPC_ENET_MCMD(pldat->net_base));
drivers/net/ethernet/nxp/lpc_eth.c
698
writel(((phy_id << 8) | phyreg), LPC_ENET_MADR(pldat->net_base));
drivers/net/ethernet/nxp/lpc_eth.c
699
writel(phydata, LPC_ENET_MWTD(pldat->net_base));
drivers/net/ethernet/nxp/lpc_eth.c
803
writel(LPC_COMMAND_PASSRUNTFRAME,
drivers/net/ethernet/nxp/lpc_eth.c
806
writel((LPC_COMMAND_PASSRUNTFRAME | LPC_COMMAND_RMII),
drivers/net/ethernet/nxp/lpc_eth.c
808
writel(LPC_SUPP_RESET_RMII, LPC_ENET_SUPP(pldat->net_base));
drivers/net/ethernet/nxp/lpc_eth.c
957
writel(rxconsidx,
drivers/net/ethernet/nxp/lpc_eth.c
996
writel(tmp, LPC_ENET_INTCLEAR(pldat->net_base));
drivers/net/ethernet/packetengines/hamachi.c
1678
writel(0x0000, ioaddr + InterruptEnable);
drivers/net/ethernet/packetengines/hamachi.c
1681
writel(2, ioaddr + RxCmd);
drivers/net/ethernet/packetengines/hamachi.c
1797
writel(*(u32 *)(ha->addr), ioaddr + 0x100 + i*8);
drivers/net/ethernet/packetengines/hamachi.c
1798
writel(0x20000 | (*(u16 *)&ha->addr[4]),
drivers/net/ethernet/packetengines/hamachi.c
1804
writel(0, ioaddr + 0x104 + i*8);
drivers/net/ethernet/packetengines/hamachi.c
1894
writel(d[0], np->base + TxIntrCtrl);
drivers/net/ethernet/packetengines/hamachi.c
1895
writel(d[1], np->base + RxIntrCtrl);
drivers/net/ethernet/packetengines/hamachi.c
872
writel(hmp->rx_ring_dma, ioaddr + RxPtr);
drivers/net/ethernet/packetengines/hamachi.c
873
writel(hmp->rx_ring_dma >> 32, ioaddr + RxPtr + 4);
drivers/net/ethernet/packetengines/hamachi.c
874
writel(hmp->tx_ring_dma, ioaddr + TxPtr);
drivers/net/ethernet/packetengines/hamachi.c
875
writel(hmp->tx_ring_dma >> 32, ioaddr + TxPtr + 4);
drivers/net/ethernet/packetengines/hamachi.c
877
writel(hmp->rx_ring_dma, ioaddr + RxPtr);
drivers/net/ethernet/packetengines/hamachi.c
878
writel(hmp->tx_ring_dma, ioaddr + TxPtr);
drivers/net/ethernet/packetengines/hamachi.c
937
writel(0x0030FFFF, ioaddr + FlowCtrl);
drivers/net/ethernet/packetengines/hamachi.c
961
writel(tx_int_var, ioaddr + TxIntrCtrl);
drivers/net/ethernet/packetengines/hamachi.c
962
writel(rx_int_var, ioaddr + RxIntrCtrl);
drivers/net/ethernet/packetengines/hamachi.c
969
writel(0x80878787, ioaddr + InterruptEnable);
drivers/net/ethernet/qlogic/netxen/netxen_nic.h
1203
writel((addr & 0xFFFF0000), (void __iomem *) (bar0 + \
drivers/net/ethernet/qlogic/netxen/netxen_nic.h
1211
writel((addr & 0xFFFF0000), (void __iomem *) (bar0 + \
drivers/net/ethernet/qlogic/netxen/netxen_nic.h
1214
writel(data, (void __iomem *) (bar0 + NX_FW_DUMP_REG2 + LSW(addr)));\
drivers/net/ethernet/qlogic/netxen/netxen_nic.h
1280
#define NX_PCI_WRITE_32(DATA, ADDR) writel(DATA, (ADDR))
drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c
1059
writel(window, offset);
drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c
1129
writel(window, addr);
drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c
1179
writel(data, addr);
drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c
1229
writel(data, addr);
drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c
1238
writel(data, addr);
drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c
1285
writel(data, addr);
drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c
1304
writel(data, addr);
drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c
1356
writel(window, adapter->ahw.ocm_win_crb);
drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c
1485
writel(off_lo, (mem_crb + MIU_TEST_AGT_ADDR_LO));
drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c
1486
writel(off_hi, (mem_crb + addr_hi));
drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c
1487
writel(data & 0xffffffff, (mem_crb + data_lo));
drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c
1488
writel((data >> 32) & 0xffffffff, (mem_crb + data_hi));
drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c
1489
writel((TA_CTL_ENABLE | TA_CTL_WRITE), (mem_crb + TEST_AGT_CTRL));
drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c
1490
writel((TA_CTL_START | TA_CTL_ENABLE | TA_CTL_WRITE),
drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c
1563
writel(off_lo, (mem_crb + MIU_TEST_AGT_ADDR_LO));
drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c
1564
writel(off_hi, (mem_crb + addr_hi));
drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c
1565
writel(TA_CTL_ENABLE, (mem_crb + TEST_AGT_CTRL));
drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c
1566
writel((TA_CTL_START|TA_CTL_ENABLE), (mem_crb + TEST_AGT_CTRL));
drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c
1630
writel(off8, (mem_crb + MIU_TEST_AGT_ADDR_LO));
drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c
1631
writel(0, (mem_crb + MIU_TEST_AGT_ADDR_HI));
drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c
1633
writel(data & 0xffffffff,
drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c
1635
writel((data >> 32) & 0xffffffff,
drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c
1638
writel((TA_CTL_ENABLE | TA_CTL_WRITE), (mem_crb + TEST_AGT_CTRL));
drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c
1639
writel((TA_CTL_START | TA_CTL_ENABLE | TA_CTL_WRITE),
drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c
1700
writel(off8, (mem_crb + MIU_TEST_AGT_ADDR_LO));
drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c
1701
writel(0, (mem_crb + MIU_TEST_AGT_ADDR_HI));
drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c
1702
writel(TA_CTL_ENABLE, (mem_crb + TEST_AGT_CTRL));
drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c
1703
writel((TA_CTL_START | TA_CTL_ENABLE), (mem_crb + TEST_AGT_CTRL));
drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c
2129
writel(adapter->ahw.pci_func, (void __iomem *)(adapter->ahw.pci_base0 +
drivers/net/ethernet/qlogic/netxen/netxen_nic_main.c
2300
writel((our_int & 0xffffffff), adapter->crb_int_state_reg);
drivers/net/ethernet/qlogic/netxen/netxen_nic_main.c
2306
writel(0xffffffff, adapter->tgt_status_reg);
drivers/net/ethernet/qlogic/netxen/netxen_nic_main.c
2322
writel(0xffffffff, adapter->tgt_status_reg);
drivers/net/ethernet/qlogic/qed/qed.h
959
#define REG_WR(cdev, offset, val) writel((u32)val, REG_ADDR(cdev, offset))
drivers/net/ethernet/qlogic/qed/qed.h
963
writel((u32)val, (void __iomem *)((u8 __iomem *)\
drivers/net/ethernet/qlogic/qede/qede_ethtool.c
1524
writel(txq->tx_db.raw, txq->doorbell_addr);
drivers/net/ethernet/qlogic/qede/qede_fp.c
296
writel(txq->tx_db.raw, txq->doorbell_addr);
drivers/net/ethernet/qlogic/qla3xxx.c
112
writel((sem_mask | sem_bits),
drivers/net/ethernet/qlogic/qla3xxx.c
126
writel(sem_mask, &port_regs->CommonRegs.semaphoreReg);
drivers/net/ethernet/qlogic/qla3xxx.c
136
writel((sem_mask | sem_bits), &port_regs->CommonRegs.semaphoreReg);
drivers/net/ethernet/qlogic/qla3xxx.c
169
writel(((ISP_CONTROL_NP_MASK << 16) | page),
drivers/net/ethernet/qlogic/qla3xxx.c
1911
writel(qdev->lrg_buf_q_producer_index,
drivers/net/ethernet/qlogic/qla3xxx.c
2190
writel(qdev->rsp_consumer_index,
drivers/net/ethernet/qlogic/qla3xxx.c
220
writel(value, reg);
drivers/net/ethernet/qlogic/qla3xxx.c
228
writel(value, reg);
drivers/net/ethernet/qlogic/qla3xxx.c
235
writel(value, reg);
drivers/net/ethernet/qlogic/qla3xxx.c
245
writel(value, reg);
drivers/net/ethernet/qlogic/qla3xxx.c
257
writel(value, reg);
drivers/net/ethernet/qlogic/qla3xxx.c
269
writel(value, reg);
drivers/net/ethernet/qlogic/qlcnic/qlcnic.h
2168
writel(0x0, tx_ring->crb_intr_mask);
drivers/net/ethernet/qlogic/qlcnic/qlcnic.h
2177
writel(1, tx_ring->crb_intr_mask);
drivers/net/ethernet/qlogic/qlcnic/qlcnic.h
2184
writel(0, tx_ring->crb_intr_mask);
drivers/net/ethernet/qlogic/qlcnic/qlcnic.h
2191
writel(1, tx_ring->crb_intr_mask);
drivers/net/ethernet/qlogic/qlcnic/qlcnic.h
2199
writel(0, sds_ring->crb_intr_mask);
drivers/net/ethernet/qlogic/qlcnic/qlcnic.h
2207
writel(1, sds_ring->crb_intr_mask);
drivers/net/ethernet/qlogic/qlcnic/qlcnic.h
2226
writel(0x1, sds_ring->crb_intr_mask);
drivers/net/ethernet/qlogic/qlcnic/qlcnic.h
2228
writel(0, sds_ring->crb_intr_mask);
drivers/net/ethernet/qlogic/qlcnic/qlcnic.h
2270
writel(0, sds_ring->crb_intr_mask);
drivers/net/ethernet/qlogic/qlcnic/qlcnic.h
2272
writel(0x1, sds_ring->crb_intr_mask);
drivers/net/ethernet/qlogic/qlcnic/qlcnic.h
2275
writel(0xfbff, adapter->tgt_mask_reg);
drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c
2372
writel(0, adapter->ahw->pci_base0 + mask);
drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c
290
writel(addr, base);
drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c
3966
writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 0));
drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c
3968
writel(cmd->req.arg[i], QLCNIC_MBX_HOST(ahw, i));
drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c
3975
writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 0));
drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c
3983
writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 1));
drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c
3986
writel(*(cmd->hdr++), QLCNIC_MBX_HOST(ahw, i));
drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c
3988
writel(*(cmd->pay++), QLCNIC_MBX_HOST(ahw, i));
drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c
417
writel(0, adapter->tgt_mask_reg);
drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c
423
writel(1, adapter->tgt_mask_reg);
drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c
437
writel(0, adapter->ahw->pci_base0 + mask);
drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c
445
writel(1, adapter->ahw->pci_base0 + mask);
drivers/net/ethernet/qlogic/qlcnic/qlcnic_hw.c
1161
writel(window, addr);
drivers/net/ethernet/qlogic/qlcnic/qlcnic_hw.c
1182
writel(data, addr);
drivers/net/ethernet/qlogic/qlcnic/qlcnic_hw.c
1192
writel(data, addr);
drivers/net/ethernet/qlogic/qlcnic/qlcnic_hw.c
1252
writel(window, adapter->ahw->ocm_win_crb);
drivers/net/ethernet/qlogic/qlcnic/qlcnic_hw.c
1265
writel(0, adapter->ahw->ocm_win_crb);
drivers/net/ethernet/qlogic/qlcnic/qlcnic_hw.c
289
writel(dest, val);
drivers/net/ethernet/qlogic/qlcnic/qlcnic_hw.c
302
writel(dest, val);
drivers/net/ethernet/qlogic/qlcnic/qlcnic_hw.c
305
writel(data, val);
drivers/net/ethernet/qlogic/qlcnic/qlcnic_hw.c
45
writel(((u32) (val)), (addr));
drivers/net/ethernet/qlogic/qlcnic/qlcnic_hw.c
46
writel(((u32) (val >> 32)), (addr + 4));
drivers/net/ethernet/qlogic/qlcnic/qlcnic_hw.h
43
writel(value, ((a)->ahw->pci_base0) + ((a)->ahw->reg_tbl[addr]))
drivers/net/ethernet/qlogic/qlcnic/qlcnic_hw.h
51
writel(value, (((ahw)->pci_base0) + ((ahw)->ext_reg_tbl[addr])))
drivers/net/ethernet/qlogic/qlcnic/qlcnic_io.c
1431
writel(consumer, sds_ring->crb_sts_consumer);
drivers/net/ethernet/qlogic/qlcnic/qlcnic_io.c
1473
writel((producer-1) & (rds_ring->num_desc-1),
drivers/net/ethernet/qlogic/qlcnic/qlcnic_io.c
1570
writel(consumer, sds_ring->crb_sts_consumer);
drivers/net/ethernet/qlogic/qlcnic/qlcnic_io.c
1943
writel(consumer, sds_ring->crb_sts_consumer);
drivers/net/ethernet/qlogic/qlcnic/qlcnic_io.c
2225
writel(consumer, sds_ring->crb_sts_consumer);
drivers/net/ethernet/qlogic/qlcnic/qlcnic_io.c
879
writel((producer - 1) & (rds_ring->num_desc - 1),
drivers/net/ethernet/qlogic/qlcnic/qlcnic_main.c
119
writel(tx_ring->producer, tx_ring->crb_cmd_producer);
drivers/net/ethernet/qlogic/qlcnic/qlcnic_main.c
3065
writel(0xffffffff, adapter->tgt_status_reg);
drivers/net/ethernet/qlogic/qlcnic/qlcnic_main.c
3081
writel(0xffffffff, adapter->tgt_status_reg);
drivers/net/ethernet/qlogic/qlcnic/qlcnic_main.c
3113
writel(0xffffffff, adapter->tgt_status_reg);
drivers/net/ethernet/qualcomm/emac/emac-mac.c
265
writel(mta, adpt->base + EMAC_HASH_TAB_REG0 + (reg << 2));
drivers/net/ethernet/qualcomm/emac/emac-mac.c
270
writel(0, adpt->base + EMAC_HASH_TAB_REG0);
drivers/net/ethernet/qualcomm/emac/emac-mac.c
271
writel(0, adpt->base + EMAC_HASH_TAB_REG1);
drivers/net/ethernet/qualcomm/emac/emac-mac.c
298
writel(mac, adpt->base + EMAC_MAC_CTRL);
drivers/net/ethernet/qualcomm/emac/emac-mac.c
305
writel(upper_32_bits(adpt->tx_q.tpd.dma_addr),
drivers/net/ethernet/qualcomm/emac/emac-mac.c
308
writel(lower_32_bits(adpt->tx_q.tpd.dma_addr),
drivers/net/ethernet/qualcomm/emac/emac-mac.c
311
writel(adpt->tx_q.tpd.count & TPD_RING_SIZE_BMSK,
drivers/net/ethernet/qualcomm/emac/emac-mac.c
315
writel(upper_32_bits(adpt->rx_q.rfd.dma_addr),
drivers/net/ethernet/qualcomm/emac/emac-mac.c
318
writel(lower_32_bits(adpt->rx_q.rfd.dma_addr),
drivers/net/ethernet/qualcomm/emac/emac-mac.c
320
writel(lower_32_bits(adpt->rx_q.rrd.dma_addr),
drivers/net/ethernet/qualcomm/emac/emac-mac.c
323
writel(adpt->rx_q.rfd.count & RFD_RING_SIZE_BMSK,
drivers/net/ethernet/qualcomm/emac/emac-mac.c
325
writel(adpt->rx_q.rrd.count & RRD_RING_SIZE_BMSK,
drivers/net/ethernet/qualcomm/emac/emac-mac.c
328
writel(adpt->rxbuf_size & RX_BUFFER_SIZE_BMSK,
drivers/net/ethernet/qualcomm/emac/emac-mac.c
331
writel(0, adpt->base + EMAC_DESC_CTRL_11);
drivers/net/ethernet/qualcomm/emac/emac-mac.c
336
writel(1, adpt->base + EMAC_INTER_SRAM_PART9);
drivers/net/ethernet/qualcomm/emac/emac-mac.c
344
writel((EMAC_MAX_TX_OFFLOAD_THRESH >> 3) &
drivers/net/ethernet/qualcomm/emac/emac-mac.c
354
writel(val, adpt->base + EMAC_TXQ_CTRL_0);
drivers/net/ethernet/qualcomm/emac/emac-mac.c
368
writel(val, adpt->base + EMAC_RXQ_CTRL_0);
drivers/net/ethernet/qualcomm/emac/emac-mac.c
376
writel(val, adpt->base + EMAC_RXQ_CTRL_1);
drivers/net/ethernet/qualcomm/emac/emac-mac.c
382
writel(val, adpt->base + EMAC_RXQ_CTRL_2);
drivers/net/ethernet/qualcomm/emac/emac-mac.c
387
writel(val, adpt->base + EMAC_RXQ_CTRL_3);
drivers/net/ethernet/qualcomm/emac/emac-mac.c
419
writel(dma_ctrl, adpt->base + EMAC_DMA_CTRL);
drivers/net/ethernet/qualcomm/emac/emac-mac.c
434
writel(sta, adpt->base + EMAC_MAC_STA_ADDR0);
drivers/net/ethernet/qualcomm/emac/emac-mac.c
438
writel(sta, adpt->base + EMAC_MAC_STA_ADDR1);
drivers/net/ethernet/qualcomm/emac/emac-mac.c
455
writel(netdev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
drivers/net/ethernet/qualcomm/emac/emac-mac.c
465
writel(val, adpt->base + EMAC_AXI_MAST_CTRL);
drivers/net/ethernet/qualcomm/emac/emac-mac.c
466
writel(0, adpt->base + EMAC_CLK_GATE_CTRL);
drivers/net/ethernet/qualcomm/emac/emac-mac.c
467
writel(RX_UNCPL_INT_EN, adpt->base + EMAC_MISC_CTRL);
drivers/net/ethernet/qualcomm/emac/emac-mac.c
951
writel((u32)~DIS_INT, adpt->base + EMAC_INT_STATUS);
drivers/net/ethernet/qualcomm/emac/emac-mac.c
952
writel(adpt->irq.mask, adpt->base + EMAC_INT_MASK);
drivers/net/ethernet/qualcomm/emac/emac-mac.c
976
writel(DIS_INT, adpt->base + EMAC_INT_STATUS);
drivers/net/ethernet/qualcomm/emac/emac-mac.c
977
writel(0, adpt->base + EMAC_INT_MASK);
drivers/net/ethernet/qualcomm/emac/emac-phy.c
57
writel(reg, adpt->base + EMAC_MDIO_CTRL);
drivers/net/ethernet/qualcomm/emac/emac-phy.c
81
writel(reg, adpt->base + EMAC_MDIO_CTRL);
drivers/net/ethernet/qualcomm/emac/emac-sgmii-fsm9900.c
145
writel(itr->val, base + itr->offset);
drivers/net/ethernet/qualcomm/emac/emac-sgmii-fsm9900.c
221
writel(SERDES_START, phy->base + EMAC_SGMII_PHY_SERDES_START);
drivers/net/ethernet/qualcomm/emac/emac-sgmii-fsm9900.c
234
writel(0, phy->base + EMAC_SGMII_PHY_INTERRUPT_MASK);
drivers/net/ethernet/qualcomm/emac/emac-sgmii-qdf2400.c
122
writel(itr->val, base + itr->offset);
drivers/net/ethernet/qualcomm/emac/emac-sgmii-qdf2400.c
190
writel(0, phy_regs + EMAC_SGMII_PHY_RESET_CTRL);
drivers/net/ethernet/qualcomm/emac/emac-sgmii-qdf2400.c
191
writel(1, laned + SGMII_LN_RSM_START);
drivers/net/ethernet/qualcomm/emac/emac-sgmii-qdf2400.c
207
writel(0, phy_regs + SGMII_PHY_LN_BIST_GEN0);
drivers/net/ethernet/qualcomm/emac/emac-sgmii-qdf2400.c
208
writel(0, phy_regs + SGMII_PHY_LN_BIST_GEN2);
drivers/net/ethernet/qualcomm/emac/emac-sgmii-qdf2400.c
209
writel(0, phy_regs + SGMII_PHY_LN_CDR_CTRL1);
drivers/net/ethernet/qualcomm/emac/emac-sgmii-qdf2400.c
212
writel(0, phy_regs + EMAC_SGMII_PHY_INTERRUPT_MASK);
drivers/net/ethernet/qualcomm/emac/emac-sgmii-qdf2432.c
112
writel(itr->val, base + itr->offset);
drivers/net/ethernet/qualcomm/emac/emac-sgmii-qdf2432.c
177
writel(0, phy_regs + EMAC_SGMII_PHY_RESET_CTRL);
drivers/net/ethernet/qualcomm/emac/emac-sgmii-qdf2432.c
178
writel(1, laned + SGMII_LN_RSM_START);
drivers/net/ethernet/qualcomm/emac/emac-sgmii-qdf2432.c
194
writel(0, phy_regs + SGMII_PHY_LN_BIST_GEN0);
drivers/net/ethernet/qualcomm/emac/emac-sgmii-qdf2432.c
195
writel(0, phy_regs + SGMII_PHY_LN_BIST_GEN2);
drivers/net/ethernet/qualcomm/emac/emac-sgmii-qdf2432.c
196
writel(0, phy_regs + SGMII_PHY_LN_CDR_CTRL1);
drivers/net/ethernet/qualcomm/emac/emac-sgmii-qdf2432.c
199
writel(0, phy_regs + EMAC_SGMII_PHY_INTERRUPT_MASK);
drivers/net/ethernet/qualcomm/emac/emac-sgmii.c
102
writel(val, phy->base + EMAC_SGMII_PHY_AUTONEG_CFG2);
drivers/net/ethernet/qualcomm/emac/emac-sgmii.c
188
writel(((val & ~PHY_RESET) | PHY_RESET), phy->base +
drivers/net/ethernet/qualcomm/emac/emac-sgmii.c
193
writel((val & ~PHY_RESET), phy->base + EMAC_EMAC_WRAPPER_CSR2);
drivers/net/ethernet/qualcomm/emac/emac-sgmii.c
224
writel(0, sgmii->base + EMAC_SGMII_PHY_INTERRUPT_MASK);
drivers/net/ethernet/qualcomm/emac/emac-sgmii.c
243
writel(0, sgmii->base + EMAC_SGMII_PHY_INTERRUPT_MASK);
drivers/net/ethernet/qualcomm/emac/emac-sgmii.c
259
writel(SGMII_ISR_MASK,
drivers/net/ethernet/qualcomm/emac/emac-sgmii.c
263
writel(0, sgmii->base + EMAC_SGMII_PHY_INTERRUPT_MASK);
drivers/net/ethernet/qualcomm/emac/emac.c
110
writel(irq->mask, adpt->base + EMAC_INT_MASK);
drivers/net/ethernet/qualcomm/emac/emac.c
134
writel(0, adpt->base + EMAC_INT_MASK);
drivers/net/ethernet/qualcomm/emac/emac.c
168
writel(irq->mask, adpt->base + EMAC_INT_MASK);
drivers/net/ethernet/qualcomm/emac/emac.c
76
writel(((data & ~mask) | val), addr);
drivers/net/ethernet/realtek/8139cp.c
360
#define cpw32(reg,val) writel((val), cp->regs + (reg))
drivers/net/ethernet/realtek/8139cp.c
370
writel((val), cp->regs + (reg)); \
drivers/net/ethernet/realtek/r8169_main.c
87
#define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
drivers/net/ethernet/realtek/rtase/rtase_main.c
116
writel(val32, tp->mmio_addr + reg);
drivers/net/ethernet/rocker/rocker_main.c
113
writel((val), (rocker)->hw_addr + (ROCKER_ ## reg))
drivers/net/ethernet/samsung/sxgbe/sxgbe_core.c
127
writel(tx_config, ioaddr + SXGBE_CORE_TX_CONFIG_REG);
drivers/net/ethernet/samsung/sxgbe/sxgbe_core.c
139
writel(rx_config, ioaddr + SXGBE_CORE_RX_CONFIG_REG);
drivers/net/ethernet/samsung/sxgbe/sxgbe_core.c
163
writel(tx_cfg, ioaddr + SXGBE_CORE_TX_CONFIG_REG);
drivers/net/ethernet/samsung/sxgbe/sxgbe_core.c
173
writel(reg_val, ioaddr + SXGBE_CORE_RX_CTL0_REG);
drivers/net/ethernet/samsung/sxgbe/sxgbe_core.c
183
writel(reg_val, ioaddr + SXGBE_CORE_RX_CTL0_REG);
drivers/net/ethernet/samsung/sxgbe/sxgbe_core.c
197
writel(ctrl, ioaddr + SXGBE_CORE_LPI_CTRL_STATUS);
drivers/net/ethernet/samsung/sxgbe/sxgbe_core.c
206
writel(ctrl, ioaddr + SXGBE_CORE_LPI_CTRL_STATUS);
drivers/net/ethernet/samsung/sxgbe/sxgbe_core.c
221
writel(ctrl, ioaddr + SXGBE_CORE_LPI_CTRL_STATUS);
drivers/net/ethernet/samsung/sxgbe/sxgbe_core.c
236
writel(value, ioaddr + SXGBE_CORE_LPI_TIMER_CTRL);
drivers/net/ethernet/samsung/sxgbe/sxgbe_core.c
245
writel(ctrl, ioaddr + SXGBE_CORE_RX_CONFIG_REG);
drivers/net/ethernet/samsung/sxgbe/sxgbe_core.c
254
writel(ctrl, ioaddr + SXGBE_CORE_RX_CONFIG_REG);
drivers/net/ethernet/samsung/sxgbe/sxgbe_core.c
31
writel(regval, ioaddr + SXGBE_CORE_TX_CONFIG_REG);
drivers/net/ethernet/samsung/sxgbe/sxgbe_core.c
40
writel(regval, ioaddr + SXGBE_CORE_RX_CONFIG_REG);
drivers/net/ethernet/samsung/sxgbe/sxgbe_core.c
97
writel(high_word, ioaddr + SXGBE_CORE_ADD_HIGHOFFSET(reg_n));
drivers/net/ethernet/samsung/sxgbe/sxgbe_core.c
98
writel(low_word, ioaddr + SXGBE_CORE_ADD_LOWOFFSET(reg_n));
drivers/net/ethernet/samsung/sxgbe/sxgbe_dma.c
102
writel(tx_config, ioaddr + SXGBE_DMA_CHA_TXCTL_REG(cha_num));
drivers/net/ethernet/samsung/sxgbe/sxgbe_dma.c
108
writel(SXGBE_DMA_ENA_INT,
drivers/net/ethernet/samsung/sxgbe/sxgbe_dma.c
115
writel(0, ioaddr + SXGBE_DMA_CHA_INT_ENABLE_REG(dma_cnum));
drivers/net/ethernet/samsung/sxgbe/sxgbe_dma.c
126
writel(tx_ctl_reg,
drivers/net/ethernet/samsung/sxgbe/sxgbe_dma.c
137
writel(tx_ctl_reg, ioaddr + SXGBE_DMA_CHA_TXCTL_REG(dma_cnum));
drivers/net/ethernet/samsung/sxgbe/sxgbe_dma.c
146
writel(tx_ctl_reg, ioaddr + SXGBE_DMA_CHA_TXCTL_REG(dma_cnum));
drivers/net/ethernet/samsung/sxgbe/sxgbe_dma.c
157
writel(tx_ctl_reg, ioaddr + SXGBE_DMA_CHA_TXCTL_REG(cnum));
drivers/net/ethernet/samsung/sxgbe/sxgbe_dma.c
169
writel(rx_ctl_reg,
drivers/net/ethernet/samsung/sxgbe/sxgbe_dma.c
182
writel(rx_ctl_reg, ioaddr + SXGBE_DMA_CHA_RXCTL_REG(cnum));
drivers/net/ethernet/samsung/sxgbe/sxgbe_dma.c
253
writel(clear_val, ioaddr + SXGBE_DMA_CHA_STATUS_REG(channel_no));
drivers/net/ethernet/samsung/sxgbe/sxgbe_dma.c
319
writel(clear_val, ioaddr + SXGBE_DMA_CHA_STATUS_REG(channel_no));
drivers/net/ethernet/samsung/sxgbe/sxgbe_dma.c
330
writel(riwt,
drivers/net/ethernet/samsung/sxgbe/sxgbe_dma.c
341
writel(ctrl, ioaddr + SXGBE_DMA_CHA_TXCTL_REG(chan_num));
drivers/net/ethernet/samsung/sxgbe/sxgbe_dma.c
38
writel(reg_val, ioaddr + SXGBE_DMA_SYSBUS_MODE_REG);
drivers/net/ethernet/samsung/sxgbe/sxgbe_dma.c
54
writel(reg_val, ioaddr + SXGBE_DMA_CHA_CTL_REG(cha_num));
drivers/net/ethernet/samsung/sxgbe/sxgbe_dma.c
58
writel(reg_val, ioaddr + SXGBE_DMA_CHA_TXCTL_REG(cha_num));
drivers/net/ethernet/samsung/sxgbe/sxgbe_dma.c
62
writel(reg_val, ioaddr + SXGBE_DMA_CHA_RXCTL_REG(cha_num));
drivers/net/ethernet/samsung/sxgbe/sxgbe_dma.c
66
writel(upper_32_bits(dma_tx),
drivers/net/ethernet/samsung/sxgbe/sxgbe_dma.c
68
writel(lower_32_bits(dma_tx),
drivers/net/ethernet/samsung/sxgbe/sxgbe_dma.c
71
writel(upper_32_bits(dma_rx),
drivers/net/ethernet/samsung/sxgbe/sxgbe_dma.c
73
writel(lower_32_bits(dma_rx),
drivers/net/ethernet/samsung/sxgbe/sxgbe_dma.c
81
writel(lower_32_bits(dma_addr),
drivers/net/ethernet/samsung/sxgbe/sxgbe_dma.c
85
writel(lower_32_bits(dma_addr),
drivers/net/ethernet/samsung/sxgbe/sxgbe_dma.c
88
writel(t_rsize - 1, ioaddr + SXGBE_DMA_CHA_TXDESC_RINGLEN_REG(cha_num));
drivers/net/ethernet/samsung/sxgbe/sxgbe_dma.c
89
writel(r_rsize - 1, ioaddr + SXGBE_DMA_CHA_RXDESC_RINGLEN_REG(cha_num));
drivers/net/ethernet/samsung/sxgbe/sxgbe_dma.c
92
writel(SXGBE_DMA_ENA_INT,
drivers/net/ethernet/samsung/sxgbe/sxgbe_ethtool.c
403
writel(reg_val, priv->ioaddr + SXGBE_CORE_RSS_CTL_REG);
drivers/net/ethernet/samsung/sxgbe/sxgbe_main.c
1725
writel(SXGBE_MMC_CTRL_CNT_FRZ, ioaddr + SXGBE_MMC_CTL_REG);
drivers/net/ethernet/samsung/sxgbe/sxgbe_main.c
1764
writel(0, ioaddr + SXGBE_MMC_CTL_REG);
drivers/net/ethernet/samsung/sxgbe/sxgbe_main.c
1831
writel(data | SXGBE_HI_REG_AE, ioaddr + SXGBE_ADDR_HIGH(reg_n));
drivers/net/ethernet/samsung/sxgbe/sxgbe_main.c
1833
writel(data, ioaddr + SXGBE_ADDR_LOW(reg_n));
drivers/net/ethernet/samsung/sxgbe/sxgbe_main.c
1865
writel(0xffffffff, ioaddr + SXGBE_HASH_HIGH);
drivers/net/ethernet/samsung/sxgbe/sxgbe_main.c
1866
writel(0xffffffff, ioaddr + SXGBE_HASH_LOW);
drivers/net/ethernet/samsung/sxgbe/sxgbe_main.c
1885
writel(mc_filter[0], ioaddr + SXGBE_HASH_LOW);
drivers/net/ethernet/samsung/sxgbe/sxgbe_main.c
1886
writel(mc_filter[1], ioaddr + SXGBE_HASH_HIGH);
drivers/net/ethernet/samsung/sxgbe/sxgbe_main.c
1905
writel(value, ioaddr + SXGBE_FRAME_FILTER);
drivers/net/ethernet/samsung/sxgbe/sxgbe_main.c
2039
writel(SXGBE_DMA_SOFT_RESET, addr + SXGBE_DMA_MODE_REG);
drivers/net/ethernet/samsung/sxgbe/sxgbe_mdio.c
49
writel(reg, sp->ioaddr + sp->hw->mii.data);
drivers/net/ethernet/samsung/sxgbe/sxgbe_mdio.c
60
writel(reg, sp->ioaddr + sp->hw->mii.addr);
drivers/net/ethernet/samsung/sxgbe/sxgbe_mdio.c
70
writel(1 << phyaddr, sp->ioaddr + SXGBE_MDIO_CLAUSE22_PORT_REG);
drivers/net/ethernet/samsung/sxgbe/sxgbe_mdio.c
74
writel(reg, sp->ioaddr + sp->hw->mii.addr);
drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c
100
writel(reg_val, ioaddr + SXGBE_MTL_TXQ_OPMODE_REG(queue_num));
drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c
112
writel(reg_val, ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));
drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c
121
writel(reg_val, ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));
drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c
133
writel(reg_val, ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));
drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c
143
writel(reg_val, ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));
drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c
153
writel(reg_val, ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));
drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c
163
writel(reg_val, ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));
drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c
173
writel(reg_val, ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));
drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c
205
writel(reg_val, ioaddr + SXGBE_MTL_TXQ_OPMODE_REG(queue_num));
drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c
227
writel(reg_val, ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));
drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c
40
writel(reg_val, ioaddr + SXGBE_MTL_OP_MODE_REG);
drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c
50
writel(reg_val, ioaddr + SXGBE_MTL_OP_MODE_REG);
drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c
56
writel(RX_QUEUE_DYNAMIC, ioaddr + SXGBE_MTL_RXQ_DMAMAP0_REG);
drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c
57
writel(RX_QUEUE_DYNAMIC, ioaddr + SXGBE_MTL_RXQ_DMAMAP1_REG);
drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c
58
writel(RX_QUEUE_DYNAMIC, ioaddr + SXGBE_MTL_RXQ_DMAMAP2_REG);
drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c
70
writel(reg_val, ioaddr + SXGBE_MTL_TXQ_OPMODE_REG(queue_num));
drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c
82
writel(reg_val, ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));
drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c
91
writel(reg_val, ioaddr + SXGBE_MTL_TXQ_OPMODE_REG(queue_num));
drivers/net/ethernet/sgi/ioc3-eth.c
1088
writel(produce << 7, &ip->regs->etpir); /* Fire ... */
drivers/net/ethernet/sgi/ioc3-eth.c
1245
writel(ip->emcr, ®s->emcr);
drivers/net/ethernet/sgi/ioc3-eth.c
1249
writel(ip->emcr, ®s->emcr); /* Clear promiscuous. */
drivers/net/ethernet/sgi/ioc3-eth.c
1267
writel(ip->ehar_h, ®s->ehar_h);
drivers/net/ethernet/sgi/ioc3-eth.c
1268
writel(ip->ehar_l, ®s->ehar_l);
drivers/net/ethernet/sgi/ioc3-eth.c
231
writel((dev->dev_addr[5] << 8) |
drivers/net/ethernet/sgi/ioc3-eth.c
234
writel((dev->dev_addr[3] << 24) |
drivers/net/ethernet/sgi/ioc3-eth.c
265
writel((phy << MICR_PHYADDR_SHIFT) | reg | MICR_READTRIG,
drivers/net/ethernet/sgi/ioc3-eth.c
280
writel(data, ®s->midr_w);
drivers/net/ethernet/sgi/ioc3-eth.c
281
writel((phy << MICR_PHYADDR_SHIFT) | reg, ®s->micr);
drivers/net/ethernet/sgi/ioc3-eth.c
440
writel((n_entry << 3) | ERPIR_ARM, &ip->regs->erpir);
drivers/net/ethernet/sgi/ioc3-eth.c
539
writel(eisr, ®s->eisr);
drivers/net/ethernet/sgi/ioc3-eth.c
560
writel(ETCSR_FD, ®s->etcsr);
drivers/net/ethernet/sgi/ioc3-eth.c
563
writel(ETCSR_HD, ®s->etcsr);
drivers/net/ethernet/sgi/ioc3-eth.c
566
writel(ip->emcr, ®s->emcr);
drivers/net/ethernet/sgi/ioc3-eth.c
700
writel(readl(®s->emcr) | (EMCR_BUFSIZ | EMCR_RAMPAR), ®s->emcr);
drivers/net/ethernet/sgi/ioc3-eth.c
703
writel(pattern, ssram0);
drivers/net/ethernet/sgi/ioc3-eth.c
704
writel(~pattern & IOC3_SSRAM_DM, ssram1);
drivers/net/ethernet/sgi/ioc3-eth.c
710
writel(readl(®s->emcr) & ~EMCR_BUFSIZ, ®s->emcr);
drivers/net/ethernet/sgi/ioc3-eth.c
723
writel(EMCR_RST, ®s->emcr); /* Reset */
drivers/net/ethernet/sgi/ioc3-eth.c
726
writel(0, ®s->emcr);
drivers/net/ethernet/sgi/ioc3-eth.c
730
writel(ERBAR_VAL, ®s->erbar);
drivers/net/ethernet/sgi/ioc3-eth.c
732
writel(15, ®s->ercsr); /* RX low watermark */
drivers/net/ethernet/sgi/ioc3-eth.c
733
writel(0, ®s->ertr); /* Interrupt immediately */
drivers/net/ethernet/sgi/ioc3-eth.c
735
writel(ip->ehar_h, ®s->ehar_h);
drivers/net/ethernet/sgi/ioc3-eth.c
736
writel(ip->ehar_l, ®s->ehar_l);
drivers/net/ethernet/sgi/ioc3-eth.c
737
writel(42, ®s->ersr); /* XXX should be random */
drivers/net/ethernet/sgi/ioc3-eth.c
747
writel(ring >> 32, ®s->erbr_h);
drivers/net/ethernet/sgi/ioc3-eth.c
748
writel(ring & 0xffffffff, ®s->erbr_l);
drivers/net/ethernet/sgi/ioc3-eth.c
749
writel(ip->rx_ci << 3, ®s->ercir);
drivers/net/ethernet/sgi/ioc3-eth.c
750
writel((ip->rx_pi << 3) | ERPIR_ARM, ®s->erpir);
drivers/net/ethernet/sgi/ioc3-eth.c
757
writel(ring >> 32, ®s->etbr_h);
drivers/net/ethernet/sgi/ioc3-eth.c
758
writel(ring & 0xffffffff, ®s->etbr_l);
drivers/net/ethernet/sgi/ioc3-eth.c
759
writel(ip->tx_pi << 7, ®s->etpir);
drivers/net/ethernet/sgi/ioc3-eth.c
760
writel(ip->tx_ci << 7, ®s->etcir);
drivers/net/ethernet/sgi/ioc3-eth.c
765
writel(ip->emcr, ®s->emcr);
drivers/net/ethernet/sgi/ioc3-eth.c
766
writel(EISR_RXTIMERINT | EISR_RXOFLO | EISR_RXBUFOFLO |
drivers/net/ethernet/sgi/ioc3-eth.c
776
writel(0, ®s->emcr); /* Shutup */
drivers/net/ethernet/sgi/ioc3-eth.c
777
writel(0, ®s->eier); /* Disable interrupts */
drivers/net/ethernet/sis/sis190.c
76
#define SIS_W32(reg, val) writel ((val), ioaddr + (reg))
drivers/net/ethernet/smsc/smc91x.h
105
writel(v, ioaddr + (reg & ~2));
drivers/net/ethernet/smsc/smc91x.h
129
#define SMC_outl(v, a, r) writel(v, (a) + (r))
drivers/net/ethernet/smsc/smc91x.h
89
#define SMC_outl(v, a, r) writel(v, (a) + (r))
drivers/net/ethernet/smsc/smsc911x.c
192
writel(val, pdata->ioaddr + reg);
drivers/net/ethernet/smsc/smsc911x.c
209
writel(val, pdata->ioaddr + __smsc_shift(pdata, reg));
drivers/net/ethernet/socionext/netsec.c
333
writel(val, priv->ioaddr + reg_addr);
drivers/net/ethernet/socionext/sni_ave.c
1003
writel(val & ~BIT(entry), priv->base + AVE_PFEN);
drivers/net/ethernet/socionext/sni_ave.c
1027
writel(GENMASK(31, set_size) & AVE_PFMBYTE_MASK0,
drivers/net/ethernet/socionext/sni_ave.c
1029
writel(AVE_PFMBYTE_MASK1, priv->base + AVE_PFMBYTE(entry) + 4);
drivers/net/ethernet/socionext/sni_ave.c
1032
writel(AVE_PFMBIT_MASK, priv->base + AVE_PFMBIT(entry));
drivers/net/ethernet/socionext/sni_ave.c
1035
writel(0, priv->base + AVE_PFSEL(entry));
drivers/net/ethernet/socionext/sni_ave.c
1054
writel(AVE_PFMBYTE_MASK0, priv->base + AVE_PFMBYTE(entry));
drivers/net/ethernet/socionext/sni_ave.c
1055
writel(AVE_PFMBYTE_MASK1, priv->base + AVE_PFMBYTE(entry) + 4);
drivers/net/ethernet/socionext/sni_ave.c
1058
writel(AVE_PFMBIT_MASK, priv->base + AVE_PFMBIT(entry));
drivers/net/ethernet/socionext/sni_ave.c
1061
writel(rxring, priv->base + AVE_PFSEL(entry));
drivers/net/ethernet/socionext/sni_ave.c
1103
writel(val, priv->base + AVE_TXCR);
drivers/net/ethernet/socionext/sni_ave.c
1112
writel(val, priv->base + AVE_LINKSEL);
drivers/net/ethernet/socionext/sni_ave.c
1146
writel(rxcr & ~AVE_RXCR_RXEN, priv->base + AVE_RXCR);
drivers/net/ethernet/socionext/sni_ave.c
1148
writel(txcr, priv->base + AVE_TXCR);
drivers/net/ethernet/socionext/sni_ave.c
1149
writel(rxcr, priv->base + AVE_RXCR);
drivers/net/ethernet/socionext/sni_ave.c
1296
writel(AVE_TXDC_ADDR_START |
drivers/net/ethernet/socionext/sni_ave.c
1307
writel(AVE_RXDC0_ADDR_START |
drivers/net/ethernet/socionext/sni_ave.c
1320
writel(val, priv->base + AVE_RXCR);
drivers/net/ethernet/socionext/sni_ave.c
1324
writel(AVE_TXCR_FLOCTR, priv->base + AVE_TXCR);
drivers/net/ethernet/socionext/sni_ave.c
1329
writel(val, priv->base + AVE_IIRQC);
drivers/net/ethernet/socionext/sni_ave.c
1476
writel(val, priv->base + AVE_RXCR);
drivers/net/ethernet/socionext/sni_ave.c
324
writel(val, priv->base + addr);
drivers/net/ethernet/socionext/sni_ave.c
352
writel(0, priv->base + AVE_GIMR);
drivers/net/ethernet/socionext/sni_ave.c
361
writel(val, priv->base + AVE_GIMR);
drivers/net/ethernet/socionext/sni_ave.c
368
writel(readl(priv->base + AVE_GIMR) | bitflag, priv->base + AVE_GIMR);
drivers/net/ethernet/socionext/sni_ave.c
369
writel(bitflag, priv->base + AVE_GISR);
drivers/net/ethernet/socionext/sni_ave.c
378
writel(mac_addr[0] | mac_addr[1] << 8 |
drivers/net/ethernet/socionext/sni_ave.c
380
writel(mac_addr[4] | mac_addr[5] << 8, priv->base + reg2);
drivers/net/ethernet/socionext/sni_ave.c
502
writel((phyid << 8) | regnum, priv->base + AVE_MDIOAR);
drivers/net/ethernet/socionext/sni_ave.c
506
writel((mdioctl | AVE_MDIOCTR_RREQ) & ~AVE_MDIOCTR_WREQ,
drivers/net/ethernet/socionext/sni_ave.c
531
writel((phyid << 8) | regnum, priv->base + AVE_MDIOAR);
drivers/net/ethernet/socionext/sni_ave.c
534
writel(val, priv->base + AVE_MDIOWDR);
drivers/net/ethernet/socionext/sni_ave.c
538
writel((mdioctl | AVE_MDIOCTR_WREQ) & ~AVE_MDIOCTR_RREQ,
drivers/net/ethernet/socionext/sni_ave.c
638
writel(AVE_DESCC_TD | AVE_DESCC_RD0, priv->base + AVE_DESCC);
drivers/net/ethernet/socionext/sni_ave.c
642
writel(0, priv->base + AVE_DESCC);
drivers/net/ethernet/socionext/sni_ave.c
654
writel(val, priv->base + AVE_DESCC);
drivers/net/ethernet/socionext/sni_ave.c
667
writel(val, priv->base + AVE_DESCC);
drivers/net/ethernet/socionext/sni_ave.c
862
writel(val, priv->base + AVE_CFGR);
drivers/net/ethernet/socionext/sni_ave.c
867
writel(val, priv->base + AVE_RSTCTRL);
drivers/net/ethernet/socionext/sni_ave.c
870
writel(AVE_GRR_GRST | AVE_GRR_PHYRST, priv->base + AVE_GRR);
drivers/net/ethernet/socionext/sni_ave.c
874
writel(AVE_GRR_GRST, priv->base + AVE_GRR);
drivers/net/ethernet/socionext/sni_ave.c
878
writel(0, priv->base + AVE_GRR);
drivers/net/ethernet/socionext/sni_ave.c
884
writel(val, priv->base + AVE_RSTCTRL);
drivers/net/ethernet/socionext/sni_ave.c
896
writel(rxcr_org & (~AVE_RXCR_RXEN), priv->base + AVE_RXCR);
drivers/net/ethernet/socionext/sni_ave.c
905
writel(AVE_GRR_RXFFR, priv->base + AVE_GRR);
drivers/net/ethernet/socionext/sni_ave.c
909
writel(0, priv->base + AVE_GRR);
drivers/net/ethernet/socionext/sni_ave.c
913
writel(AVE_GI_RXOVF, priv->base + AVE_GISR);
drivers/net/ethernet/socionext/sni_ave.c
919
writel(rxcr_org, priv->base + AVE_RXCR);
drivers/net/ethernet/socionext/sni_ave.c
935
writel(AVE_GI_PHY, priv->base + AVE_GISR);
drivers/net/ethernet/socionext/sni_ave.c
939
writel(AVE_GI_RXERR, priv->base + AVE_GISR);
drivers/net/ethernet/socionext/sni_ave.c
957
writel(AVE_GI_RXDROP, priv->base + AVE_GISR);
drivers/net/ethernet/socionext/sni_ave.c
989
writel(val | BIT(entry), priv->base + AVE_PFEN);
drivers/net/ethernet/spacemit/k1_emac.c
140
writel(val, priv->iobase + reg);
drivers/net/ethernet/stmicro/stmmac/dwmac-anarion.c
34
writel(val, gmac->ctl_block + reg);
drivers/net/ethernet/stmicro/stmmac/dwmac-dwc-qos-eth.c
146
writel(value, eqos->regs + SDMEMCOMPPADCTRL);
drivers/net/ethernet/stmicro/stmmac/dwmac-dwc-qos-eth.c
152
writel(value, eqos->regs + AUTO_CAL_CONFIG);
drivers/net/ethernet/stmicro/stmmac/dwmac-dwc-qos-eth.c
175
writel(value, eqos->regs + SDMEMCOMPPADCTRL);
drivers/net/ethernet/stmicro/stmmac/dwmac-dwc-qos-eth.c
181
writel(value, eqos->regs + AUTO_CAL_CONFIG);
drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c
211
writel(ctrl, dwmac->base_addr + MAC_CTRL_REG);
drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c
223
writel(old_ctrl, dwmac->base_addr + MAC_CTRL_REG);
drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c
235
writel(value, ioaddr + DMA_BUS_MODE);
drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c
239
writel(RMII_RESET_SPEED, ioaddr + MAC_CTRL_REG);
drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c
333
writel(gpio_value, priv->ioaddr + GMAC_GPIO_STATUS);
drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c
406
writel(acr_value, ptpaddr + PTP_ACR);
drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c
411
writel(acr_value, ptpaddr + PTP_ACR);
drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c
421
writel(gpio_value, ioaddr + GMAC_GPIO_STATUS);
drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c
423
writel(gpio_value, ioaddr + GMAC_GPIO_STATUS);
drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c
212
writel(value, ioaddr + DMA_CHAN_BUS_MODE(chan));
drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c
215
writel(DMA_INTR_DEFAULT_MASK_LOONGSON, ioaddr +
drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c
300
writel((intr_status & 0x7ffff), ioaddr + DMA_CHAN_STATUS(chan));
drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c
493
writel(value, ioaddr + DMA_BUS_MODE);
drivers/net/ethernet/stmicro/stmmac/dwmac-meson.c
42
writel(val, dwmac->reg);
drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
114
writel(data, dwmac->regs + reg);
drivers/net/ethernet/stmicro/stmmac/dwmac-motorcomm.c
156
writel(reg, priv->base + EPHY_CTRL);
drivers/net/ethernet/stmicro/stmmac/dwmac-motorcomm.c
164
writel(reg, priv->base + SYS_RESET);
drivers/net/ethernet/stmicro/stmmac/dwmac-motorcomm.c
167
writel(reg, priv->base + SYS_RESET);
drivers/net/ethernet/stmicro/stmmac/dwmac-motorcomm.c
174
writel(0x0, priv->base + MGMT_INT_CTRL0);
drivers/net/ethernet/stmicro/stmmac/dwmac-motorcomm.c
176
writel(FIELD_PREP(INT_MODERATION_RX, 200) |
drivers/net/ethernet/stmicro/stmmac/dwmac-motorcomm.c
184
writel(OOB_WOL_CTRL_DIS, priv->base + OOB_WOL_CTRL);
drivers/net/ethernet/stmicro/stmmac/dwmac-motorcomm.c
69
writel(FIELD_PREP(EFUSE_OP_MODE, EFUSE_OP_ROW_READ) |
drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
126
writel(value, ethqos->rgmii_base + offset);
drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c
50
writel(S32_PHY_INTF_SEL_RGMII, gmac->ctrl_sts);
drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
105
writel(val, splitter_base + EMAC_SPLITTER_CTRL_REG);
drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
337
writel(acr_value, ptpaddr + PTP_ACR);
drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
342
writel(acr_value, ptpaddr + PTP_ACR);
drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
351
writel(gpio_value, ioaddr + XGMAC_GPIO_STATUS);
drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
353
writel(gpio_value, ioaddr + XGMAC_GPIO_STATUS);
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
1028
writel(value, ioaddr + EMAC_BASIC_CTL0);
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
277
writel(0, ioaddr + EMAC_RX_CTL1);
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
278
writel(0, ioaddr + EMAC_TX_CTL1);
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
279
writel(0, ioaddr + EMAC_RX_FRM_FLT);
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
280
writel(0, ioaddr + EMAC_RX_DESC_LIST);
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
281
writel(0, ioaddr + EMAC_TX_DESC_LIST);
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
282
writel(0, ioaddr + EMAC_INT_EN);
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
283
writel(0x1FFFFFF, ioaddr + EMAC_INT_STA);
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
293
writel(EMAC_RX_INT | EMAC_TX_INT, ioaddr + EMAC_INT_EN);
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
294
writel(0x1FFFFFF, ioaddr + EMAC_INT_STA);
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
303
writel(lower_32_bits(dma_rx_phy), ioaddr + EMAC_RX_DESC_LIST);
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
312
writel(lower_32_bits(dma_tx_phy), ioaddr + EMAC_TX_DESC_LIST);
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
359
writel(value, ioaddr + EMAC_INT_EN);
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
373
writel(value, ioaddr + EMAC_INT_EN);
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
384
writel(v, ioaddr + EMAC_TX_CTL1);
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
394
writel(v, ioaddr + EMAC_TX_CTL1);
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
404
writel(v, ioaddr + EMAC_TX_CTL1);
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
415
writel(v, ioaddr + EMAC_RX_CTL1);
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
425
writel(v, ioaddr + EMAC_RX_CTL1);
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
495
writel(v, ioaddr + EMAC_INT_STA);
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
521
writel(v, ioaddr + EMAC_RX_CTL1);
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
551
writel(v, ioaddr + EMAC_TX_CTL1);
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
610
writel(v, ioaddr + EMAC_BASIC_CTL1);
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
626
writel(t, ioaddr + EMAC_TX_CTL0);
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
627
writel(r, ioaddr + EMAC_RX_CTL0);
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
642
writel(0, ioaddr + EMAC_MACADDR_HI(reg_n));
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
651
writel(v, ioaddr + EMAC_MACADDR_HI(reg_n));
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
673
writel(v, ioaddr + EMAC_RX_CTL0);
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
716
writel(v, ioaddr + EMAC_RX_FRM_FLT);
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
731
writel(v, ioaddr + EMAC_RX_CTL0);
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
738
writel(v, ioaddr + EMAC_TX_FLOW_CTL);
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
747
writel(v | 0x01, priv->ioaddr + EMAC_BASIC_CTL1);
drivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c
122
writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
drivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c
126
writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
drivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c
130
writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
drivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c
135
writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
drivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c
140
writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
drivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c
153
writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
drivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c
157
writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
drivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c
162
writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
drivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c
167
writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
drivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c
172
writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
drivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c
183
writel(value, mgbe->xpcs + XPCS_WRAP_IRQ_STATUS);
drivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c
195
writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
drivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c
199
writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
drivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c
203
writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
drivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c
207
writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
drivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c
211
writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
drivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c
334
writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_HW_INIT_CTRL);
drivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c
354
writel(MAC_SBD_INTR, mgbe->regs + MGBE_WRAP_COMMON_INTR_ENABLE);
drivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c
357
writel(mgbe->iommu_sid, mgbe->hv + MGBE_WRAP_AXI_ASID0_CTRL);
drivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c
86
writel(MAC_SBD_INTR, mgbe->regs + MGBE_WRAP_COMMON_INTR_ENABLE);
drivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c
89
writel(mgbe->iommu_sid, mgbe->hv + MGBE_WRAP_AXI_ASID0_CTRL);
drivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c
95
writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_HW_INIT_CTRL);
drivers/net/ethernet/stmicro/stmmac/dwmac-thead.c
100
writel(txclk_dir, dwmac->apb_base + GMAC_TXCLK_OEN);
drivers/net/ethernet/stmicro/stmmac/dwmac-thead.c
126
writel(0, dwmac->apb_base + GMAC_PLLCLK_DIV);
drivers/net/ethernet/stmicro/stmmac/dwmac-thead.c
142
writel(reg, dwmac->apb_base + GMAC_PLLCLK_DIV);
drivers/net/ethernet/stmicro/stmmac/dwmac-thead.c
171
writel(0, dwmac->apb_base + GMAC_PLLCLK_DIV);
drivers/net/ethernet/stmicro/stmmac/dwmac-thead.c
172
writel(reg, dwmac->apb_base + GMAC_PLLCLK_DIV);
drivers/net/ethernet/stmicro/stmmac/dwmac-thead.c
174
writel(GMAC_GTXCLK_SEL_PLL, dwmac->apb_base + GMAC_GTXCLK_SEL);
drivers/net/ethernet/stmicro/stmmac/dwmac-thead.c
185
writel(reg, dwmac->apb_base + GMAC_CLK_EN);
drivers/net/ethernet/stmicro/stmmac/dwmac-thead.c
206
writel(reg, dwmac->apb_base + GMAC_RXCLK_DELAY_CTRL);
drivers/net/ethernet/stmicro/stmmac/dwmac-thead.c
211
writel(reg, dwmac->apb_base + GMAC_TXCLK_DELAY_CTRL);
drivers/net/ethernet/stmicro/stmmac/dwmac-thead.c
75
writel(phyif, dwmac->apb_base + GMAC_INTF_CTRL);
drivers/net/ethernet/stmicro/stmmac/dwmac-visconti.c
110
writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);
drivers/net/ethernet/stmicro/stmmac/dwmac-visconti.c
117
writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);
drivers/net/ethernet/stmicro/stmmac/dwmac-visconti.c
120
writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);
drivers/net/ethernet/stmicro/stmmac/dwmac-visconti.c
123
writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);
drivers/net/ethernet/stmicro/stmmac/dwmac-visconti.c
130
writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);
drivers/net/ethernet/stmicro/stmmac/dwmac-visconti.c
136
writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);
drivers/net/ethernet/stmicro/stmmac/dwmac-visconti.c
139
writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);
drivers/net/ethernet/stmicro/stmmac/dwmac-visconti.c
159
writel(phy_intf_sel, dwmac->reg + REG_ETHER_CONTROL);
drivers/net/ethernet/stmicro/stmmac/dwmac-visconti.c
163
writel(clk_sel_val, dwmac->reg + REG_ETHER_CLOCK_SEL);
drivers/net/ethernet/stmicro/stmmac/dwmac-visconti.c
165
writel((clk_sel_val | ETHER_CLK_SEL_RMII_CLK_EN | ETHER_CLK_SEL_RX_TX_CLK_EN),
drivers/net/ethernet/stmicro/stmmac/dwmac-visconti.c
170
writel(phy_intf_sel, dwmac->reg + REG_ETHER_CONTROL);
drivers/net/ethernet/stmicro/stmmac/dwmac-visconti.c
80
writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);
drivers/net/ethernet/stmicro/stmmac/dwmac-visconti.c
84
writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);
drivers/net/ethernet/stmicro/stmmac/dwmac-visconti.c
87
writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);
drivers/net/ethernet/stmicro/stmmac/dwmac-visconti.c
90
writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);
drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
126
writel(mcfilterbits[0], ioaddr + GMAC_HASH_LOW);
drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
127
writel(mcfilterbits[1], ioaddr + GMAC_HASH_HIGH);
drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
140
writel(mcfilterbits[regs],
drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
209
writel(0, ioaddr + GMAC_ADDR_HIGH(reg));
drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
210
writel(0, ioaddr + GMAC_ADDR_LOW(reg));
drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
219
writel(value, ioaddr + GMAC_FRAME_FILTER);
drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
248
writel(flow, ioaddr + GMAC_FLOW_CTRL);
drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
265
writel(pmt, ioaddr + GMAC_PMT);
drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
328
writel(value, ioaddr + LPI_CTRL_STATUS);
drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
345
writel(value, ioaddr + LPI_CTRL_STATUS);
drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
360
writel(value, ioaddr + LPI_TIMER_CTRL);
drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
451
writel(value, ioaddr + GMAC_CONTROL);
drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
50
writel(value | GMAC_CORE_INIT, ioaddr + GMAC_CONTROL);
drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
53
writel(GMAC_INT_DEFAULT_MASK, ioaddr + GMAC_INT_MASK);
drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
562
writel(intr_mask, ioaddr + GMAC_INT_MASK);
drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
57
writel(0x0, ioaddr + GMAC_VLAN_TAG);
drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
590
writel(tcr_val, ptpaddr + PTP_TCR);
drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
71
writel(value, int_mask);
drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
85
writel(value, ioaddr + GMAC_CONTROL);
drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c
102
writel(lower_32_bits(dma_tx_phy), ioaddr + DMA_CHAN_TX_BASE_ADDR(chan));
drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c
152
writel(csr6, ioaddr + DMA_CHAN_CONTROL(channel));
drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c
186
writel(csr6, ioaddr + DMA_CHAN_CONTROL(channel));
drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c
250
writel(riwt, ioaddr + DMA_CHAN_RX_WATCHDOG(queue));
drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c
43
writel(value, ioaddr + DMA_AXI_BUS_MODE);
drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c
81
writel(value, ioaddr + DMA_CHAN_BUS_MODE(chan));
drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c
84
writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_CHAN_INTR_ENA(chan));
drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c
93
writel(lower_32_bits(dma_rx_phy), ioaddr + DMA_CHAN_RCV_BASE_ADDR(chan));
drivers/net/ethernet/stmicro/stmmac/dwmac100_core.c
120
writel(mc_filter[0], ioaddr + MAC_HASH_LOW);
drivers/net/ethernet/stmicro/stmmac/dwmac100_core.c
121
writel(mc_filter[1], ioaddr + MAC_HASH_HIGH);
drivers/net/ethernet/stmicro/stmmac/dwmac100_core.c
124
writel(value, ioaddr + MAC_CONTROL);
drivers/net/ethernet/stmicro/stmmac/dwmac100_core.c
136
writel(flow, ioaddr + MAC_FLOW_CTRL);
drivers/net/ethernet/stmicro/stmmac/dwmac100_core.c
154
writel(value, ioaddr + MAC_CONTROL);
drivers/net/ethernet/stmicro/stmmac/dwmac100_core.c
30
writel(value, ioaddr + MAC_CONTROL);
drivers/net/ethernet/stmicro/stmmac/dwmac100_core.c
33
writel(ETH_P_8021Q, ioaddr + MAC_VLAN1);
drivers/net/ethernet/stmicro/stmmac/dwmac100_core.c
92
writel(0xffffffff, ioaddr + MAC_HASH_HIGH);
drivers/net/ethernet/stmicro/stmmac/dwmac100_core.c
93
writel(0xffffffff, ioaddr + MAC_HASH_LOW);
drivers/net/ethernet/stmicro/stmmac/dwmac100_dma.c
25
writel(DMA_BUS_MODE_DEFAULT |
drivers/net/ethernet/stmicro/stmmac/dwmac100_dma.c
30
writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_INTR_ENA);
drivers/net/ethernet/stmicro/stmmac/dwmac100_dma.c
38
writel(lower_32_bits(dma_rx_phy), ioaddr + DMA_RCV_BASE_ADDR);
drivers/net/ethernet/stmicro/stmmac/dwmac100_dma.c
46
writel(lower_32_bits(dma_tx_phy), ioaddr + DMA_TX_BASE_ADDR);
drivers/net/ethernet/stmicro/stmmac/dwmac100_dma.c
67
writel(csr6, ioaddr + DMA_CONTROL);
drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
121
writel(ctrl2, ioaddr + GMAC_RXQ_CTRL2);
drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
122
writel(ctrl3, ioaddr + GMAC_RXQ_CTRL3);
drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
129
writel(ctrl3, ioaddr + GMAC_RXQ_CTRL3);
drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
130
writel(ctrl2, ioaddr + GMAC_RXQ_CTRL2);
drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
151
writel(value, ioaddr + base_register);
drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
184
writel(value, ioaddr + GMAC_RXQ_CTRL1);
drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
205
writel(value, ioaddr + MTL_OPERATION_MODE);
drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
232
writel(value, ioaddr + MTL_OPERATION_MODE);
drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
246
writel(value, ioaddr + mtl_txqx_weight_base_addr(dwmac4_addrs, queue));
drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
258
writel(value, ioaddr + MTL_RXQ_DMA_MAP0);
drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
263
writel(value, ioaddr + MTL_RXQ_DMA_MAP1);
drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
286
writel(value, ioaddr + mtl_etsx_ctrl_base_addr(dwmac4_addrs, queue));
drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
293
writel(value, ioaddr + mtl_send_slp_credx_base_addr(dwmac4_addrs,
drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
303
writel(value, ioaddr + mtl_high_credx_base_addr(dwmac4_addrs, queue));
drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
309
writel(value, ioaddr + mtl_low_credx_base_addr(dwmac4_addrs, queue));
drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
331
writel(value, ioaddr + GMAC_CONFIG);
drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
357
writel(config, ioaddr + GMAC_CONFIG);
drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
359
writel(pmt, ioaddr + GMAC_PMT);
drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
400
writel(et, ioaddr + GMAC4_LPI_ENTRY_TIMER);
drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
417
writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
43
writel(value | GMAC_CORE_INIT, ioaddr + GMAC_CONFIG);
drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
434
writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
449
writel(value, ioaddr + GMAC4_LPI_TIMER_CTRL);
drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
47
writel((clk_rate / 1000000) - 1, ioaddr + GMAC4_MAC_ONEUS_TIC_COUNTER);
drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
478
writel(value, ioaddr + GMAC_RXQ_CTRL4);
drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
50
writel(GMAC_INT_DEFAULT_ENABLE, ioaddr + GMAC_INT_EN);
drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
513
writel(mc_filter[i], ioaddr + GMAC_HASH_TAB(i));
drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
533
writel(0, ioaddr + GMAC_ADDR_HIGH(reg));
drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
534
writel(0, ioaddr + GMAC_ADDR_LOW(reg));
drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
545
writel(value, ioaddr + GMAC_PACKET_FILTER);
drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
563
writel(flow, ioaddr + GMAC_RX_FLOW_CTRL);
drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
578
writel(flow, ioaddr + GMAC_QX_TX_FLOW_CTRL(queue));
drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
582
writel(0, ioaddr + GMAC_QX_TX_FLOW_CTRL(queue));
drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
609
writel(status | MTL_RX_OVERFLOW_INT,
drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
66
writel(value, int_mask);
drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
764
writel(value, ioaddr + GMAC_CONFIG);
drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
773
writel(value, ioaddr + GMAC_CONFIG);
drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
782
writel(addr, ioaddr + GMAC_ARP_ADDR);
drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
789
writel(value, ioaddr + GMAC_CONFIG);
drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
801
writel(value, ioaddr + GMAC_PACKET_FILTER);
drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
832
writel(value, ioaddr + GMAC_L3L4_CTRL(filter_no));
drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
835
writel(match, ioaddr + GMAC_L3_ADDR0(filter_no));
drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
837
writel(match, ioaddr + GMAC_L3_ADDR1(filter_no));
drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
841
writel(0, ioaddr + GMAC_L3L4_CTRL(filter_no));
drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
855
writel(value, ioaddr + GMAC_PACKET_FILTER);
drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
876
writel(value, ioaddr + GMAC_L3L4_CTRL(filter_no));
drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
884
writel(value, ioaddr + GMAC_L4_ADDR(filter_no));
drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
887
writel(0, ioaddr + GMAC_L3L4_CTRL(filter_no));
drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
90
writel(value, ioaddr + GMAC_RXQ_CTRL0);
drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
102
writel(value, ioaddr + DMA_CHAN_CONTROL(dwmac4_addrs, chan));
drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
105
writel(DMA_CHAN_INTR_DEFAULT_MASK,
drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
121
writel(value, ioaddr + DMA_CHAN_CONTROL(dwmac4_addrs, chan));
drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
124
writel(DMA_CHAN_INTR_DEFAULT_MASK_4_10,
drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
147
writel(value, ioaddr + DMA_SYS_BUS_MODE);
drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
158
writel(value, ioaddr + DMA_BUS_MODE);
drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
230
writel(riwt, ioaddr + DMA_CHAN_RX_WATCHDOG(dwmac4_addrs, queue));
drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
300
writel(mtl_rx_op, ioaddr + MTL_CHAN_RX_OP_MODE(dwmac4_addrs, channel));
drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
355
writel(mtl_tx_op, ioaddr + MTL_CHAN_TX_OP_MODE(dwmac4_addrs, channel));
drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
42
writel(value, ioaddr + DMA_SYS_BUS_MODE);
drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
464
writel(value | DMA_CONTROL_TSE,
drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
469
writel(value & ~DMA_CONTROL_TSE,
drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
487
writel(mtl_tx_op, ioaddr + MTL_CHAN_TX_OP_MODE(dwmac4_addrs, channel));
drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
498
writel(value, ioaddr + DMA_CHAN_RX_CONTROL(dwmac4_addrs, chan));
drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
509
writel(value, ioaddr + GMAC_EXT_CONFIG);
drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
514
writel(value, ioaddr + GMAC_EXT_CFG1);
drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
521
writel(value, ioaddr + DMA_CHAN_CONTROL(dwmac4_addrs, chan));
drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
535
writel(value, ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs, chan));
drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
542
writel(DMA_TBS_DEF_FTOS, ioaddr + DMA_TBS_CTRL);
drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
56
writel(value, ioaddr + DMA_CHAN_RX_CONTROL(dwmac4_addrs, chan));
drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
59
writel(upper_32_bits(dma_rx_phy),
drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
62
writel(lower_32_bits(dma_rx_phy),
drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
81
writel(value, ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs, chan));
drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
84
writel(upper_32_bits(dma_tx_phy),
drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
87
writel(lower_32_bits(dma_tx_phy),
drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c
101
writel(len, ioaddr + DMA_CHAN_TX_RING_LEN(dwmac4_addrs, chan));
drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c
109
writel(len, ioaddr + DMA_CHAN_RX_RING_LEN(dwmac4_addrs, chan));
drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c
123
writel(value, ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));
drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c
137
writel(value, ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));
drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c
151
writel(value, ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));
drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c
165
writel(value, ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));
drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c
22
writel(value, ioaddr + DMA_BUS_MODE);
drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c
222
writel(intr_status & intr_en,
drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c
238
writel(data | GMAC_HI_REG_AE, ioaddr + high);
drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c
240
writel(data, ioaddr + low);
drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c
255
writel(value, ioaddr + GMAC_CONFIG);
drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c
34
writel(tail_ptr, ioaddr + DMA_CHAN_RX_END_ADDR(dwmac4_addrs, chan));
drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c
42
writel(tail_ptr, ioaddr + DMA_CHAN_TX_END_ADDR(dwmac4_addrs, chan));
drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c
52
writel(value, ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs, chan));
drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c
56
writel(value, ioaddr + GMAC_CONFIG);
drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c
67
writel(value, ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs, chan));
drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c
79
writel(value, ioaddr + DMA_CHAN_RX_CONTROL(dwmac4_addrs, chan));
drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c
83
writel(value, ioaddr + GMAC_CONFIG);
drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c
93
writel(value, ioaddr + DMA_CHAN_RX_CONTROL(dwmac4_addrs, chan));
drivers/net/ethernet/stmicro/stmmac/dwmac5.c
132
writel(value, ioaddr + MTL_ECC_INT_STATUS);
drivers/net/ethernet/stmicro/stmmac/dwmac5.c
180
writel(value, ioaddr + DMA_ECC_INT_STATUS);
drivers/net/ethernet/stmicro/stmmac/dwmac5.c
221
writel(value, ioaddr + MTL_ECC_CONTROL);
drivers/net/ethernet/stmicro/stmmac/dwmac5.c
229
writel(value, ioaddr + MTL_ECC_INT_ENABLE);
drivers/net/ethernet/stmicro/stmmac/dwmac5.c
234
writel(value, ioaddr + DMA_ECC_INT_ENABLE);
drivers/net/ethernet/stmicro/stmmac/dwmac5.c
246
writel(value, ioaddr + MAC_FSM_CONTROL);
drivers/net/ethernet/stmicro/stmmac/dwmac5.c
252
writel(value, ioaddr + MTL_DPP_CONTROL);
drivers/net/ethernet/stmicro/stmmac/dwmac5.c
263
writel(value, ioaddr + MTL_DPP_CONTROL);
drivers/net/ethernet/stmicro/stmmac/dwmac5.c
336
writel(val, ioaddr + MTL_OPERATION_MODE);
drivers/net/ethernet/stmicro/stmmac/dwmac5.c
348
writel(val, ioaddr + MTL_OPERATION_MODE);
drivers/net/ethernet/stmicro/stmmac/dwmac5.c
369
writel(val, ioaddr + MTL_RXP_IACC_DATA);
drivers/net/ethernet/stmicro/stmmac/dwmac5.c
373
writel(val, ioaddr + MTL_RXP_IACC_CTRL_STATUS);
drivers/net/ethernet/stmicro/stmmac/dwmac5.c
377
writel(val, ioaddr + MTL_RXP_IACC_CTRL_STATUS);
drivers/net/ethernet/stmicro/stmmac/dwmac5.c
381
writel(val, ioaddr + MTL_RXP_IACC_CTRL_STATUS);
drivers/net/ethernet/stmicro/stmmac/dwmac5.c
444
writel(val, ioaddr + GMAC_CONFIG);
drivers/net/ethernet/stmicro/stmmac/dwmac5.c
509
writel(val, ioaddr + MTL_RXP_CONTROL_STATUS);
drivers/net/ethernet/stmicro/stmmac/dwmac5.c
516
writel(old_val, ioaddr + GMAC_CONFIG);
drivers/net/ethernet/stmicro/stmmac/dwmac5.c
540
writel(val, ioaddr + MAC_PPS_CONTROL);
drivers/net/ethernet/stmicro/stmmac/dwmac5.c
546
writel(val, ioaddr + MAC_PPS_CONTROL);
drivers/net/ethernet/stmicro/stmmac/dwmac5.c
548
writel(cfg->start.tv_sec, ioaddr + MAC_PPSx_TARGET_TIME_SEC(index));
drivers/net/ethernet/stmicro/stmmac/dwmac5.c
552
writel(cfg->start.tv_nsec, ioaddr + MAC_PPSx_TARGET_TIME_NSEC(index));
drivers/net/ethernet/stmicro/stmmac/dwmac5.c
562
writel(period - 1, ioaddr + MAC_PPSx_INTERVAL(index));
drivers/net/ethernet/stmicro/stmmac/dwmac5.c
568
writel(period - 1, ioaddr + MAC_PPSx_WIDTH(index));
drivers/net/ethernet/stmicro/stmmac/dwmac5.c
572
writel(val, ioaddr + MAC_PPS_CONTROL);
drivers/net/ethernet/stmicro/stmmac/dwmac5.c
84
writel(value, ioaddr + MAC_DPP_FSM_INT_STATUS);
drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c
23
writel(value, ioaddr + DMA_BUS_MODE);
drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c
237
writel((intr_status & 0x1ffff), ioaddr + DMA_STATUS);
drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c
245
writel((csr6 | DMA_CONTROL_FTF), ioaddr + DMA_CONTROL);
drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c
260
writel(data | GMAC_HI_REG_AE, ioaddr + high);
drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c
262
writel(data, ioaddr + low);
drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c
280
writel(value, ioaddr + MAC_CTRL_REG);
drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c
33
writel(1, ioaddr + DMA_CHAN_XMT_POLL_DEMAND(chan));
drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c
38
writel(1, ioaddr + DMA_CHAN_RCV_POLL_DEMAND(chan));
drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c
51
writel(value, ioaddr + DMA_CHAN_INTR_ENA(chan));
drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c
64
writel(value, ioaddr + DMA_CHAN_INTR_ENA(chan));
drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c
72
writel(value, ioaddr + DMA_CHAN_CONTROL(chan));
drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c
79
writel(value, ioaddr + DMA_CHAN_CONTROL(chan));
drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c
87
writel(value, ioaddr + DMA_CHAN_CONTROL(chan));
drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c
94
writel(value, ioaddr + DMA_CHAN_CONTROL(chan));
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
1003
writel(val, ioaddr + XGMAC_MTL_RXP_IACC_CTRL_ST);
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
1067
writel(val, ioaddr + XGMAC_RX_CONFIG);
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
1132
writel(val, ioaddr + XGMAC_MTL_RXP_CONTROL_STATUS);
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
1139
writel(old_val, ioaddr + XGMAC_RX_CONFIG);
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
1176
writel(val, ioaddr + XGMAC_PPS_CONTROL);
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
1196
writel(cfg->start.tv_sec, ioaddr + XGMAC_PPSx_TARGET_TIME_SEC(index));
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
1200
writel(cfg->start.tv_nsec, ioaddr + XGMAC_PPSx_TARGET_TIME_NSEC(index));
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
1210
writel(period - 1, ioaddr + XGMAC_PPSx_INTERVAL(index));
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
1216
writel(period - 1, ioaddr + XGMAC_PPSx_WIDTH(index));
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
1219
writel(val, ioaddr + XGMAC_PPS_CONTROL);
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
1229
writel(value, ioaddr + XGMAC_TX_CONFIG);
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
125
writel(ctrl2, ioaddr + XGMAC_RXQ_CTRL2);
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
1258
writel(value, ioaddr + XGMAC_L3L4_ADDR_CTRL);
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
126
writel(ctrl3, ioaddr + XGMAC_RXQ_CTRL3);
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
1279
writel(data, ioaddr + XGMAC_L3L4_DATA);
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
1285
writel(value, ioaddr + XGMAC_L3L4_ADDR_CTRL);
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
1300
writel(value, ioaddr + XGMAC_PACKET_FILTER);
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
133
writel(ctrl3, ioaddr + XGMAC_RXQ_CTRL3);
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
134
writel(ctrl2, ioaddr + XGMAC_RXQ_CTRL2);
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
1363
writel(value, ioaddr + XGMAC_PACKET_FILTER);
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
1417
writel(addr, ioaddr + XGMAC_ARP_ADDR);
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
1424
writel(value, ioaddr + XGMAC_RX_CONFIG);
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
1480
writel(value, ioaddr + XLGMAC_RXQ_ENABLE_CTRL0);
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
152
writel(value, ioaddr + reg);
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
182
writel(value, ioaddr + XGMAC_RXQ_CTRL1);
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
204
writel(value, ioaddr + XGMAC_MTL_OPMODE);
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
233
writel(value, ioaddr + XGMAC_MTL_OPMODE);
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
241
writel(value, ioaddr + XGMAC_MTL_TCx_ETS_CONTROL(i));
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
251
writel(weight, ioaddr + XGMAC_MTL_TCx_QUANTUM_WEIGHT(queue));
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
26
writel(tx | XGMAC_CORE_INIT_TX, ioaddr + XGMAC_TX_CONFIG);
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
268
writel(value, ioaddr + reg);
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
27
writel(rx | XGMAC_CORE_INIT_RX, ioaddr + XGMAC_RX_CONFIG);
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
279
writel(send_slope, ioaddr + XGMAC_MTL_TCx_SENDSLOPE(queue));
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
28
writel(XGMAC_INT_DEFAULT_EN, ioaddr + XGMAC_INT_EN);
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
280
writel(idle_slope, ioaddr + XGMAC_MTL_TCx_QUANTUM_WEIGHT(queue));
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
281
writel(high_credit, ioaddr + XGMAC_MTL_TCx_HICREDIT(queue));
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
282
writel(low_credit, ioaddr + XGMAC_MTL_TCx_LOCREDIT(queue));
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
287
writel(value, ioaddr + XGMAC_MTL_TCx_ETS_CONTROL(queue));
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
350
writel(~0x0, ioaddr + XGMAC_MTL_QINT_STATUS(chan));
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
364
writel(XGMAC_RFE, ioaddr + XGMAC_RX_FLOW_CTRL);
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
372
writel(value, ioaddr + XGMAC_Qx_TX_FLOW_CTRL(i));
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
389
writel(cfg, ioaddr + XGMAC_RX_CONFIG);
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
392
writel(val, ioaddr + XGMAC_PMT);
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
403
writel(value | XGMAC_AE, ioaddr + XGMAC_ADDRx_HIGH(reg_n));
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
406
writel(value, ioaddr + XGMAC_ADDRx_LOW(reg_n));
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
41
writel(value, int_mask);
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
447
writel(value, ioaddr + XGMAC_LPI_CTRL);
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
462
writel(value, ioaddr + XGMAC_LPI_CTRL);
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
471
writel(value, ioaddr + XGMAC_LPI_TIMER_CTRL);
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
494
writel(mcfilterbits[regs], ioaddr + XGMAC_HASH_TABLE(regs));
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
519
writel(~0x0, ioaddr + XGMAC_HASH_TABLE(i));
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
547
writel(0, ioaddr + XGMAC_ADDRx_HIGH(reg));
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
548
writel(0, ioaddr + XGMAC_ADDRx_LOW(reg));
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
552
writel(value, ioaddr + XGMAC_PACKET_FILTER);
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
564
writel(value, ioaddr + XGMAC_RX_CONFIG);
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
572
writel(val, ioaddr + XGMAC_RSS_DATA);
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
576
writel(ctrl, ioaddr + XGMAC_RSS_ADDR);
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
592
writel(value, ioaddr + XGMAC_RSS_CTRL);
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
613
writel(value, ioaddr + XGMAC_RSS_CTRL);
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
64
writel(tx, ioaddr + XGMAC_TX_CONFIG);
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
65
writel(rx, ioaddr + XGMAC_RX_CONFIG);
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
690
writel(value, ioaddr + XGMAC_MAC_DPP_FSM_INT_STATUS);
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
738
writel(value, ioaddr + XGMAC_MTL_ECC_INT_STATUS);
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
78
writel(value, ioaddr + XGMAC_RX_CONFIG);
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
823
writel(value, ioaddr + XGMAC_DMA_ECC_INT_STATUS);
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
829
writel(value, ioaddr + XGMAC_DMA_DPP_INT_STATUS);
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
846
writel(0x0, ioaddr + XGMAC_MTL_ECC_CONTROL);
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
854
writel(value, ioaddr + XGMAC_MTL_ECC_INT_ENABLE);
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
860
writel(value, ioaddr + XGMAC_DMA_ECC_INT_ENABLE);
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
872
writel(value, ioaddr + XGMAC_MAC_FSM_CONTROL);
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
878
writel(value, ioaddr + XGMAC_MTL_DPP_CONTROL);
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
94
writel(value, ioaddr + XGMAC_RXQ_CTRL0);
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
959
writel(val, ioaddr + XGMAC_MTL_OPMODE);
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
970
writel(val, ioaddr + XGMAC_MTL_OPMODE);
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
991
writel(val, ioaddr + XGMAC_MTL_RXP_IACC_DATA);
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
995
writel(val, ioaddr + XGMAC_MTL_RXP_IACC_CTRL_ST);
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
999
writel(val, ioaddr + XGMAC_MTL_RXP_IACC_CTRL_ST);
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
103
writel(value, ioaddr + XGMAC_DMA_SYSBUS_MODE);
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
104
writel(XGMAC_TDPS, ioaddr + XGMAC_TX_EDMA_CTRL);
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
105
writel(XGMAC_RDPS, ioaddr + XGMAC_RX_EDMA_CTRL);
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
16
writel(value | XGMAC_SWR, ioaddr + XGMAC_DMA_MODE);
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
171
writel(flow, ioaddr + XGMAC_MTL_RXQ_FLOW_CONTROL(channel));
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
174
writel(value, ioaddr + XGMAC_MTL_RXQ_OPMODE(channel));
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
218
writel(value, ioaddr + XGMAC_MTL_TXQ_OPMODE(channel));
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
232
writel(value, ioaddr + XGMAC_DMA_CH_INT_EN(chan));
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
246
writel(value, ioaddr + XGMAC_DMA_CH_INT_EN(chan));
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
256
writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
260
writel(value, ioaddr + XGMAC_TX_CONFIG);
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
270
writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
274
writel(value, ioaddr + XGMAC_TX_CONFIG);
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
284
writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
288
writel(value, ioaddr + XGMAC_RX_CONFIG);
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
298
writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
33
writel(value, ioaddr + XGMAC_DMA_SYSBUS_MODE);
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
347
writel(intr_en & intr_status, ioaddr + XGMAC_DMA_CH_STATUS(chan));
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
45
writel(value, ioaddr + XGMAC_DMA_CH_CONTROL(chan));
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
46
writel(XGMAC_DMA_INT_DEFAULT_EN, ioaddr + XGMAC_DMA_CH_INT_EN(chan));
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
476
writel(riwt & XGMAC_RWT, ioaddr + XGMAC_DMA_CH_Rx_WATCHDOG(queue));
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
482
writel(len, ioaddr + XGMAC_DMA_CH_RxDESC_RING_LEN(chan));
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
488
writel(len, ioaddr + XGMAC_DMA_CH_TxDESC_RING_LEN(chan));
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
494
writel(ptr, ioaddr + XGMAC_DMA_CH_RxDESC_TAIL_LPTR(chan));
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
500
writel(ptr, ioaddr + XGMAC_DMA_CH_TxDESC_TAIL_LPTR(chan));
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
513
writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
525
writel(0, ioaddr + XGMAC_MTL_TCx_ETS_CONTROL(channel));
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
528
writel(flow & (~XGMAC_RFE), ioaddr + XGMAC_RX_FLOW_CTRL);
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
532
writel(value, ioaddr + XGMAC_MTL_TXQ_OPMODE(channel));
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
542
writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
552
writel(value, ioaddr + XGMAC_RX_CONFIG);
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
559
writel(value, ioaddr + XGMAC_DMA_CH_CONTROL(chan));
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
572
writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
578
writel(XGMAC_DEF_FTOS, ioaddr + XGMAC_DMA_TBS_CTRL0);
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
579
writel(XGMAC_DEF_FTOS, ioaddr + XGMAC_DMA_TBS_CTRL1);
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
580
writel(XGMAC_DEF_FTOS, ioaddr + XGMAC_DMA_TBS_CTRL2);
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
581
writel(XGMAC_DEF_FTOS, ioaddr + XGMAC_DMA_TBS_CTRL3);
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
59
writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
61
writel(upper_32_bits(phy), ioaddr + XGMAC_DMA_CH_RxDESC_HADDR(chan));
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
62
writel(lower_32_bits(phy), ioaddr + XGMAC_DMA_CH_RxDESC_LADDR(chan));
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
75
writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
77
writel(upper_32_bits(phy), ioaddr + XGMAC_DMA_CH_TxDESC_HADDR(chan));
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
78
writel(lower_32_bits(phy), ioaddr + XGMAC_DMA_CH_TxDESC_LADDR(chan));
drivers/net/ethernet/stmicro/stmmac/mmc_core.c
241
writel(value, mmcaddr + MMC_CNTRL);
drivers/net/ethernet/stmicro/stmmac/mmc_core.c
250
writel(MMC_DEFAULT_MASK, mmcaddr + MMC_RX_INTR_MASK);
drivers/net/ethernet/stmicro/stmmac/mmc_core.c
251
writel(MMC_DEFAULT_MASK, mmcaddr + MMC_TX_INTR_MASK);
drivers/net/ethernet/stmicro/stmmac/mmc_core.c
252
writel(MMC_DEFAULT_MASK, mmcaddr + MMC_RX_IPC_INTR_MASK);
drivers/net/ethernet/stmicro/stmmac/mmc_core.c
399
writel(value, mmcaddr + MMC_CNTRL);
drivers/net/ethernet/stmicro/stmmac/mmc_core.c
404
writel(0x0, mmcaddr + MMC_RX_INTR_MASK);
drivers/net/ethernet/stmicro/stmmac/mmc_core.c
405
writel(0x0, mmcaddr + MMC_TX_INTR_MASK);
drivers/net/ethernet/stmicro/stmmac/mmc_core.c
406
writel(MMC_DEFAULT_MASK, mmcaddr + MMC_XGMAC_TX_FPE_INTR_MASK);
drivers/net/ethernet/stmicro/stmmac/mmc_core.c
407
writel(MMC_DEFAULT_MASK, mmcaddr + MMC_XGMAC_RX_FPE_INTR_MASK);
drivers/net/ethernet/stmicro/stmmac/mmc_core.c
408
writel(MMC_DEFAULT_MASK, mmcaddr + MMC_XGMAC_RX_IPC_INTR_MASK);
drivers/net/ethernet/stmicro/stmmac/stmmac_est.c
101
writel(EST_CGCE, est_addr + EST_STATUS);
drivers/net/ethernet/stmicro/stmmac/stmmac_est.c
117
writel(value, est_addr + EST_SCH_ERR);
drivers/net/ethernet/stmicro/stmmac/stmmac_est.c
143
writel(feqn, est_addr + EST_FRM_SZ_ERR);
drivers/net/ethernet/stmicro/stmmac/stmmac_est.c
15
writel(val, est_addr + EST_GCL_DATA);
drivers/net/ethernet/stmicro/stmmac/stmmac_est.c
167
writel(EST_BTRE, est_addr + EST_STATUS);
drivers/net/ethernet/stmicro/stmmac/stmmac_est.c
171
writel(EST_SWLC, est_addr + EST_STATUS);
drivers/net/ethernet/stmicro/stmmac/stmmac_est.c
19
writel(ctrl, est_addr + EST_GCL_CONTROL);
drivers/net/ethernet/stmicro/stmmac/stmmac_est.c
22
writel(ctrl, est_addr + EST_GCL_CONTROL);
drivers/net/ethernet/stmicro/stmmac/stmmac_est.c
70
writel(ctrl, est_addr + EST_CONTROL);
drivers/net/ethernet/stmicro/stmmac/stmmac_est.c
78
writel(ctrl, est_addr + EST_INT_EN);
drivers/net/ethernet/stmicro/stmmac/stmmac_fpe.c
108
writel(value, ioaddr + reg->mac_fpe_reg);
drivers/net/ethernet/stmicro/stmmac/stmmac_fpe.c
196
writel(u32_replace_bits(value, add_frag_size, FPE_MTL_ADD_FRAG_SZ),
drivers/net/ethernet/stmicro/stmmac/stmmac_fpe.c
249
writel(u32_replace_bits(val, preemptible_txqs, FPE_MTL_PREEMPTION_CLASS),
drivers/net/ethernet/stmicro/stmmac/stmmac_fpe.c
266
writel(u32_replace_bits(val, i, XGMAC_Q2TCMAP),
drivers/net/ethernet/stmicro/stmmac/stmmac_fpe.c
286
writel(u32_replace_bits(val, tc, XGMAC_Q2TCMAP),
drivers/net/ethernet/stmicro/stmmac/stmmac_fpe.c
292
writel(u32_replace_bits(val, preemptible_txqs, FPE_MTL_PREEMPTION_CLASS),
drivers/net/ethernet/stmicro/stmmac/stmmac_fpe.c
60
writel(value, ioaddr + reg->rxq_ctrl1_reg);
drivers/net/ethernet/stmicro/stmmac/stmmac_fpe.c
64
writel(cfg->fpe_csr, ioaddr + reg->mac_fpe_reg);
drivers/net/ethernet/stmicro/stmmac/stmmac_fpe.c
90
writel(value, ioaddr + reg->int_en_reg);
drivers/net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c
105
writel(reg_tsic, ioaddr + PTP_TS_INGR_CORR_NS);
drivers/net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c
106
writel(reg_tsicsns, ioaddr + PTP_TS_INGR_CORR_SNS);
drivers/net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c
114
writel(reg_tsec, ioaddr + PTP_TS_EGR_CORR_NS);
drivers/net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c
115
writel(reg_tsecsns, ioaddr + PTP_TS_EGR_CORR_SNS);
drivers/net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c
122
writel(sec, ioaddr + PTP_STSUR);
drivers/net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c
123
writel(nsec, ioaddr + PTP_STNSUR);
drivers/net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c
127
writel(value, ioaddr + PTP_TCR);
drivers/net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c
139
writel(addend, ioaddr + PTP_TAR);
drivers/net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c
143
writel(value, ioaddr + PTP_TCR);
drivers/net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c
171
writel(sec, ioaddr + PTP_STSUR);
drivers/net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c
173
writel(value, ioaddr + PTP_STNSUR);
drivers/net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c
178
writel(value, ioaddr + PTP_TCR);
drivers/net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c
36
writel(regval, ioaddr + PTP_TCR);
drivers/net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c
70
writel(reg_value, ioaddr + PTP_SSIR);
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
1096
writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
115
writel(addr, priv->ioaddr + mii_address);
drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
116
writel(value, priv->ioaddr + mii_data);
drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
183
writel(addr, priv->ioaddr + mii_address);
drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
184
writel(value, priv->ioaddr + mii_data);
drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
261
writel(data, mii_data);
drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
262
writel(addr, mii_address);
drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
421
writel(0, priv->ioaddr + mii_address);
drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
66
writel(tmp, priv->ioaddr + XGMAC_MDIO_C22P);
drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
86
writel(tmp, priv->ioaddr + XGMAC_MDIO_C22P);
drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h
77
writel(value, ioaddr + GMAC_AN_CTRL(reg));
drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.c
252
writel(acr_value, ptpaddr + PTP_ACR);
drivers/net/ethernet/stmicro/stmmac/stmmac_vlan.c
170
writel(hash, ioaddr + VLAN_HASH_TABLE);
drivers/net/ethernet/stmicro/stmmac/stmmac_vlan.c
186
writel(value, ioaddr + VLAN_TAG);
drivers/net/ethernet/stmicro/stmmac/stmmac_vlan.c
19
writel(val, ioaddr + VLAN_TAG);
drivers/net/ethernet/stmicro/stmmac/stmmac_vlan.c
200
writel(value | perfect_match, ioaddr + VLAN_TAG);
drivers/net/ethernet/stmicro/stmmac/stmmac_vlan.c
207
writel(value, ioaddr + VLAN_TAG);
drivers/net/ethernet/stmicro/stmmac/stmmac_vlan.c
221
writel(value, ioaddr + VLAN_INCL);
drivers/net/ethernet/stmicro/stmmac/stmmac_vlan.c
250
writel(value, ioaddr + VLAN_TAG);
drivers/net/ethernet/stmicro/stmmac/stmmac_vlan.c
258
writel(hash, ioaddr + VLAN_HASH_TABLE);
drivers/net/ethernet/stmicro/stmmac/stmmac_vlan.c
265
writel(value, ioaddr + XGMAC_PACKET_FILTER);
drivers/net/ethernet/stmicro/stmmac/stmmac_vlan.c
281
writel(value, ioaddr + VLAN_TAG);
drivers/net/ethernet/stmicro/stmmac/stmmac_vlan.c
287
writel(value, ioaddr + XGMAC_PACKET_FILTER);
drivers/net/ethernet/stmicro/stmmac/stmmac_vlan.c
304
writel(value | perfect_match, ioaddr + VLAN_TAG);
drivers/net/ethernet/stmicro/stmmac/stmmac_vlan.c
310
writel(value, ioaddr + XGMAC_PACKET_FILTER);
drivers/net/ethernet/stmicro/stmmac/stmmac_vlan.c
319
writel(value, ioaddr + VLAN_TAG);
drivers/net/ethernet/stmicro/stmmac/stmmac_vlan.c
33
writel(data, ioaddr + VLAN_TAG_DATA);
drivers/net/ethernet/stmicro/stmmac/stmmac_vlan.c
41
writel(val, ioaddr + VLAN_TAG);
drivers/net/ethernet/sun/cassini.c
1154
writel(i, cp->regs + REG_HP_INSTR_RAM_ADDR);
drivers/net/ethernet/sun/cassini.c
1158
writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_HI);
drivers/net/ethernet/sun/cassini.c
1167
writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_MID);
drivers/net/ethernet/sun/cassini.c
1173
writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_LOW);
drivers/net/ethernet/sun/cassini.c
1192
writel(val, cp->regs + REG_RX_CFG);
drivers/net/ethernet/sun/cassini.c
1196
writel((desc_dma + val) >> 32, cp->regs + REG_RX_DB_HI);
drivers/net/ethernet/sun/cassini.c
1197
writel((desc_dma + val) & 0xffffffff, cp->regs + REG_RX_DB_LOW);
drivers/net/ethernet/sun/cassini.c
1198
writel(RX_DESC_RINGN_SIZE(0) - 4, cp->regs + REG_RX_KICK);
drivers/net/ethernet/sun/cassini.c
1206
writel((desc_dma + val) >> 32, cp->regs + REG_PLUS_RX_DB1_HI);
drivers/net/ethernet/sun/cassini.c
1207
writel((desc_dma + val) & 0xffffffff, cp->regs +
drivers/net/ethernet/sun/cassini.c
1209
writel(RX_DESC_RINGN_SIZE(1) - 4, cp->regs +
drivers/net/ethernet/sun/cassini.c
1216
writel((desc_dma + val) >> 32, cp->regs + REG_RX_CB_HI);
drivers/net/ethernet/sun/cassini.c
1217
writel((desc_dma + val) & 0xffffffff, cp->regs + REG_RX_CB_LOW);
drivers/net/ethernet/sun/cassini.c
1224
writel((desc_dma + val) >> 32, cp->regs +
drivers/net/ethernet/sun/cassini.c
1226
writel((desc_dma + val) & 0xffffffff, cp->regs +
drivers/net/ethernet/sun/cassini.c
1236
writel(INTR_RX_DONE | INTR_RX_BUF_UNAVAIL, cp->regs + REG_ALIAS_CLEAR);
drivers/net/ethernet/sun/cassini.c
1243
writel(val, cp->regs + REG_RX_PAUSE_THRESH);
drivers/net/ethernet/sun/cassini.c
1247
writel(i, cp->regs + REG_RX_TABLE_ADDR);
drivers/net/ethernet/sun/cassini.c
1248
writel(0x0, cp->regs + REG_RX_TABLE_DATA_LOW);
drivers/net/ethernet/sun/cassini.c
1249
writel(0x0, cp->regs + REG_RX_TABLE_DATA_MID);
drivers/net/ethernet/sun/cassini.c
1250
writel(0x0, cp->regs + REG_RX_TABLE_DATA_HI);
drivers/net/ethernet/sun/cassini.c
1254
writel(0x0, cp->regs + REG_RX_CTRL_FIFO_ADDR);
drivers/net/ethernet/sun/cassini.c
1255
writel(0x0, cp->regs + REG_RX_IPP_FIFO_ADDR);
drivers/net/ethernet/sun/cassini.c
1261
writel(val, cp->regs + REG_RX_BLANK);
drivers/net/ethernet/sun/cassini.c
1263
writel(0x0, cp->regs + REG_RX_BLANK);
drivers/net/ethernet/sun/cassini.c
1273
writel(val, cp->regs + REG_RX_AE_THRESH);
drivers/net/ethernet/sun/cassini.c
1276
writel(val, cp->regs + REG_PLUS_RX_AE1_THRESH);
drivers/net/ethernet/sun/cassini.c
1282
writel(0x0, cp->regs + REG_RX_RED);
drivers/net/ethernet/sun/cassini.c
1312
writel(val, cp->regs + REG_RX_PAGE_SIZE);
drivers/net/ethernet/sun/cassini.c
1321
writel(val, cp->regs + REG_HP_CFG);
drivers/net/ethernet/sun/cassini.c
1427
writel(cp->mac_rx_cfg & ~MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
drivers/net/ethernet/sun/cassini.c
1439
writel(0, cp->regs + REG_RX_CFG);
drivers/net/ethernet/sun/cassini.c
1453
writel(SW_RESET_RX, cp->regs + REG_SW_RESET);
drivers/net/ethernet/sun/cassini.c
1473
writel(val | RX_CFG_DMA_EN, cp->regs + REG_RX_CFG);
drivers/net/ethernet/sun/cassini.c
1474
writel(MAC_RX_FRAME_RECV, cp->regs + REG_MAC_RX_MASK);
drivers/net/ethernet/sun/cassini.c
1476
writel(val | MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
drivers/net/ethernet/sun/cassini.c
2157
writel(entry, cp->regs + REG_RX_KICK);
drivers/net/ethernet/sun/cassini.c
2160
writel(entry, cp->regs + REG_PLUS_RX_KICK1);
drivers/net/ethernet/sun/cassini.c
2218
writel(cluster, cp->regs + REG_RX_KICK);
drivers/net/ethernet/sun/cassini.c
2221
writel(cluster, cp->regs + REG_PLUS_RX_KICK1);
drivers/net/ethernet/sun/cassini.c
2374
writel(last, cp->regs + REG_RX_COMP_TAIL);
drivers/net/ethernet/sun/cassini.c
2376
writel(last, cp->regs + REG_PLUS_RX_COMPN_TAIL(ring));
drivers/net/ethernet/sun/cassini.c
274
writel(0xFFFFFFFF, cp->regs + REG_INTR_MASK);
drivers/net/ethernet/sun/cassini.c
2803
writel(entry, cp->regs + REG_TX_KICKN(ring));
drivers/net/ethernet/sun/cassini.c
2838
writel((desc_dma + off) >> 32, cp->regs + REG_TX_COMPWB_DB_HI);
drivers/net/ethernet/sun/cassini.c
2839
writel((desc_dma + off) & 0xffffffff, cp->regs + REG_TX_COMPWB_DB_LOW);
drivers/net/ethernet/sun/cassini.c
2856
writel((desc_dma + off) >> 32, cp->regs + REG_TX_DBN_HI(i));
drivers/net/ethernet/sun/cassini.c
2857
writel((desc_dma + off) & 0xffffffff, cp->regs +
drivers/net/ethernet/sun/cassini.c
2863
writel(val, cp->regs + REG_TX_CFG);
drivers/net/ethernet/sun/cassini.c
2869
writel(0x800, cp->regs + REG_TX_MAXBURST_0);
drivers/net/ethernet/sun/cassini.c
2870
writel(0x1600, cp->regs + REG_TX_MAXBURST_1);
drivers/net/ethernet/sun/cassini.c
2871
writel(0x2400, cp->regs + REG_TX_MAXBURST_2);
drivers/net/ethernet/sun/cassini.c
2872
writel(0x4800, cp->regs + REG_TX_MAXBURST_3);
drivers/net/ethernet/sun/cassini.c
2874
writel(0x800, cp->regs + REG_TX_MAXBURST_0);
drivers/net/ethernet/sun/cassini.c
2875
writel(0x800, cp->regs + REG_TX_MAXBURST_1);
drivers/net/ethernet/sun/cassini.c
2876
writel(0x800, cp->regs + REG_TX_MAXBURST_2);
drivers/net/ethernet/sun/cassini.c
2877
writel(0x800, cp->regs + REG_TX_MAXBURST_3);
drivers/net/ethernet/sun/cassini.c
2901
writel((ha->addr[4] << 8) | ha->addr[5],
drivers/net/ethernet/sun/cassini.c
2903
writel((ha->addr[2] << 8) | ha->addr[3],
drivers/net/ethernet/sun/cassini.c
2905
writel((ha->addr[0] << 8) | ha->addr[1],
drivers/net/ethernet/sun/cassini.c
291
writel(INTRN_MASK_CLEAR_ALL | INTRN_MASK_RX_EN,
drivers/net/ethernet/sun/cassini.c
2919
writel(hash_table[i], cp->regs + REG_MAC_HASH_TABLEN(i));
drivers/net/ethernet/sun/cassini.c
2933
writel(0xFFFF, cp->regs + REG_MAC_HASH_TABLEN(i));
drivers/net/ethernet/sun/cassini.c
2947
writel(0, cp->regs + REG_MAC_COLL_NORMAL);
drivers/net/ethernet/sun/cassini.c
2948
writel(0, cp->regs + REG_MAC_COLL_FIRST);
drivers/net/ethernet/sun/cassini.c
2949
writel(0, cp->regs + REG_MAC_COLL_EXCESS);
drivers/net/ethernet/sun/cassini.c
2950
writel(0, cp->regs + REG_MAC_COLL_LATE);
drivers/net/ethernet/sun/cassini.c
2951
writel(0, cp->regs + REG_MAC_TIMER_DEFER);
drivers/net/ethernet/sun/cassini.c
2952
writel(0, cp->regs + REG_MAC_ATTEMPTS_PEAK);
drivers/net/ethernet/sun/cassini.c
2953
writel(0, cp->regs + REG_MAC_RECV_FRAME);
drivers/net/ethernet/sun/cassini.c
2954
writel(0, cp->regs + REG_MAC_LEN_ERR);
drivers/net/ethernet/sun/cassini.c
2955
writel(0, cp->regs + REG_MAC_ALIGN_ERR);
drivers/net/ethernet/sun/cassini.c
2956
writel(0, cp->regs + REG_MAC_FCS_ERR);
drivers/net/ethernet/sun/cassini.c
2957
writel(0, cp->regs + REG_MAC_RX_CODE_ERR);
drivers/net/ethernet/sun/cassini.c
296
writel(INTRN_MASK_CLEAR_ALL, cp->regs +
drivers/net/ethernet/sun/cassini.c
2966
writel(0x1, cp->regs + REG_MAC_TX_RESET);
drivers/net/ethernet/sun/cassini.c
2967
writel(0x1, cp->regs + REG_MAC_RX_RESET);
drivers/net/ethernet/sun/cassini.c
3002
writel(CAWR_RR_DIS, cp->regs + REG_CAWR);
drivers/net/ethernet/sun/cassini.c
3009
writel(INF_BURST_EN, cp->regs + REG_INF_BURST);
drivers/net/ethernet/sun/cassini.c
3012
writel(0x1BF0, cp->regs + REG_MAC_SEND_PAUSE);
drivers/net/ethernet/sun/cassini.c
3014
writel(0x00, cp->regs + REG_MAC_IPG0);
drivers/net/ethernet/sun/cassini.c
3015
writel(0x08, cp->regs + REG_MAC_IPG1);
drivers/net/ethernet/sun/cassini.c
3016
writel(0x04, cp->regs + REG_MAC_IPG2);
drivers/net/ethernet/sun/cassini.c
3019
writel(0x40, cp->regs + REG_MAC_SLOT_TIME);
drivers/net/ethernet/sun/cassini.c
3022
writel(ETH_ZLEN + 4, cp->regs + REG_MAC_FRAMESIZE_MIN);
drivers/net/ethernet/sun/cassini.c
3028
writel(CAS_BASE(MAC_FRAMESIZE_MAX_BURST, 0x2000) |
drivers/net/ethernet/sun/cassini.c
3038
writel(0x41, cp->regs + REG_MAC_PA_SIZE);
drivers/net/ethernet/sun/cassini.c
3040
writel(0x07, cp->regs + REG_MAC_PA_SIZE);
drivers/net/ethernet/sun/cassini.c
3041
writel(0x04, cp->regs + REG_MAC_JAM_SIZE);
drivers/net/ethernet/sun/cassini.c
3042
writel(0x10, cp->regs + REG_MAC_ATTEMPT_LIMIT);
drivers/net/ethernet/sun/cassini.c
3043
writel(0x8808, cp->regs + REG_MAC_CTRL_TYPE);
drivers/net/ethernet/sun/cassini.c
3045
writel((e[5] | (e[4] << 8)) & 0x3ff, cp->regs + REG_MAC_RANDOM_SEED);
drivers/net/ethernet/sun/cassini.c
3047
writel(0, cp->regs + REG_MAC_ADDR_FILTER0);
drivers/net/ethernet/sun/cassini.c
3048
writel(0, cp->regs + REG_MAC_ADDR_FILTER1);
drivers/net/ethernet/sun/cassini.c
3049
writel(0, cp->regs + REG_MAC_ADDR_FILTER2);
drivers/net/ethernet/sun/cassini.c
3050
writel(0, cp->regs + REG_MAC_ADDR_FILTER2_1_MASK);
drivers/net/ethernet/sun/cassini.c
3051
writel(0, cp->regs + REG_MAC_ADDR_FILTER0_MASK);
drivers/net/ethernet/sun/cassini.c
3055
writel(0x0, cp->regs + REG_MAC_ADDRN(i));
drivers/net/ethernet/sun/cassini.c
3057
writel((e[4] << 8) | e[5], cp->regs + REG_MAC_ADDRN(0));
drivers/net/ethernet/sun/cassini.c
3058
writel((e[2] << 8) | e[3], cp->regs + REG_MAC_ADDRN(1));
drivers/net/ethernet/sun/cassini.c
3059
writel((e[0] << 8) | e[1], cp->regs + REG_MAC_ADDRN(2));
drivers/net/ethernet/sun/cassini.c
3061
writel(0x0001, cp->regs + REG_MAC_ADDRN(42));
drivers/net/ethernet/sun/cassini.c
3062
writel(0xc200, cp->regs + REG_MAC_ADDRN(43));
drivers/net/ethernet/sun/cassini.c
3063
writel(0x0180, cp->regs + REG_MAC_ADDRN(44));
drivers/net/ethernet/sun/cassini.c
3075
writel(MAC_TX_FRAME_XMIT, cp->regs + REG_MAC_TX_MASK);
drivers/net/ethernet/sun/cassini.c
3076
writel(MAC_RX_FRAME_RECV, cp->regs + REG_MAC_RX_MASK);
drivers/net/ethernet/sun/cassini.c
3081
writel(0xffffffff, cp->regs + REG_MAC_CTRL_MASK);
drivers/net/ethernet/sun/cassini.c
314
writel(INTR_TX_DONE, cp->regs + REG_INTR_MASK);
drivers/net/ethernet/sun/cassini.c
3148
writel(BIM_LOCAL_DEV_PROM | BIM_LOCAL_DEV_PAD,
drivers/net/ethernet/sun/cassini.c
330
writel(INTRN_MASK_RX_EN, cp->regs +
drivers/net/ethernet/sun/cassini.c
3310
writel(0, cp->regs + REG_BIM_LOCAL_DEV_EN);
drivers/net/ethernet/sun/cassini.c
3394
writel(PCS_DATAPATH_MODE_MII, cp->regs + REG_PCS_DATAPATH_MODE);
drivers/net/ethernet/sun/cassini.c
3432
writel(val, cp->regs + REG_TX_CFG);
drivers/net/ethernet/sun/cassini.c
3434
writel(val, cp->regs + REG_RX_CFG);
drivers/net/ethernet/sun/cassini.c
3438
writel(val, cp->regs + REG_MAC_TX_CFG);
drivers/net/ethernet/sun/cassini.c
3440
writel(val, cp->regs + REG_MAC_RX_CFG);
drivers/net/ethernet/sun/cassini.c
3471
writel(RX_DESC_RINGN_SIZE(0) - 4, cp->regs + REG_RX_KICK);
drivers/net/ethernet/sun/cassini.c
3472
writel(0, cp->regs + REG_RX_COMP_TAIL);
drivers/net/ethernet/sun/cassini.c
3476
writel(RX_DESC_RINGN_SIZE(1) - 4,
drivers/net/ethernet/sun/cassini.c
3579
writel(val, cp->regs + REG_MAC_XIF_CFG);
drivers/net/ethernet/sun/cassini.c
3600
writel(val | MAC_TX_CFG_CARRIER_EXTEND,
drivers/net/ethernet/sun/cassini.c
3605
writel(val | MAC_RX_CFG_CARRIER_EXTEND,
drivers/net/ethernet/sun/cassini.c
3608
writel(0x200, cp->regs + REG_MAC_SLOT_TIME);
drivers/net/ethernet/sun/cassini.c
3615
writel(val, cp->regs + REG_MAC_TX_CFG);
drivers/net/ethernet/sun/cassini.c
3630
writel(val & ~MAC_RX_CFG_CARRIER_EXTEND,
drivers/net/ethernet/sun/cassini.c
3632
writel(0x40, cp->regs + REG_MAC_SLOT_TIME);
drivers/net/ethernet/sun/cassini.c
3656
writel(val, cp->regs + REG_MAC_CTRL_CFG);
drivers/net/ethernet/sun/cassini.c
366
writel(BIM_LOCAL_DEV_PAD | BIM_LOCAL_DEV_PROM | BIM_LOCAL_DEV_EXT,
drivers/net/ethernet/sun/cassini.c
3686
writel(BIM_LOCAL_DEV_SOFT_0, cp->regs + REG_BIM_LOCAL_DEV_EN);
drivers/net/ethernet/sun/cassini.c
3704
writel((SW_RESET_TX | SW_RESET_RX | SW_RESET_BLOCK_PCS_SLINK),
drivers/net/ethernet/sun/cassini.c
3707
writel(SW_RESET_TX | SW_RESET_RX, cp->regs + REG_SW_RESET);
drivers/net/ethernet/sun/cassini.c
3724
writel(BIM_CFG_DPAR_INTR_ENABLE | BIM_CFG_RMA_INTR_ENABLE |
drivers/net/ethernet/sun/cassini.c
3731
writel(0xFFFFFFFFU & ~(PCI_ERR_BADACK | PCI_ERR_DTRTO |
drivers/net/ethernet/sun/cassini.c
3739
writel(PCS_DATAPATH_MODE_MII, cp->regs + REG_PCS_DATAPATH_MODE);
drivers/net/ethernet/sun/cassini.c
3754
writel(val, cp->regs + REG_TX_CFG);
drivers/net/ethernet/sun/cassini.c
3758
writel(val, cp->regs + REG_RX_CFG);
drivers/net/ethernet/sun/cassini.c
389
writel(cmd, cp->regs + REG_MIF_FRAME);
drivers/net/ethernet/sun/cassini.c
411
writel(cmd, cp->regs + REG_MIF_FRAME);
drivers/net/ethernet/sun/cassini.c
4439
writel(rxcfg & ~MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
drivers/net/ethernet/sun/cassini.c
4449
writel(rxcfg & ~MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
drivers/net/ethernet/sun/cassini.c
4459
writel(rxcfg, cp->regs + REG_MAC_RX_CFG);
drivers/net/ethernet/sun/cassini.c
664
writel((enable) ? ~(BMSR_LSTATUS | BMSR_ANEGCOMPLETE) : 0xFFFF,
drivers/net/ethernet/sun/cassini.c
666
writel(cfg, cp->regs + REG_MIF_CFG);
drivers/net/ethernet/sun/cassini.c
746
writel(val, cp->regs + REG_PCS_MII_CTRL);
drivers/net/ethernet/sun/cassini.c
857
writel(PCS_DATAPATH_MODE_MII,
drivers/net/ethernet/sun/cassini.c
893
writel((cp->phy_type & CAS_PHY_MII_MDIO0) ?
drivers/net/ethernet/sun/cassini.c
935
writel(PCS_DATAPATH_MODE_SERDES,
drivers/net/ethernet/sun/cassini.c
940
writel(0, cp->regs + REG_SATURN_PCFG);
drivers/net/ethernet/sun/cassini.c
945
writel(val, cp->regs + REG_PCS_MII_CTRL);
drivers/net/ethernet/sun/cassini.c
961
writel(0x0, cp->regs + REG_PCS_CFG);
drivers/net/ethernet/sun/cassini.c
968
writel(val, cp->regs + REG_PCS_MII_ADVERT);
drivers/net/ethernet/sun/cassini.c
971
writel(PCS_CFG_EN, cp->regs + REG_PCS_CFG);
drivers/net/ethernet/sun/cassini.c
974
writel(PCS_SERDES_CTRL_SYNCD_EN,
drivers/net/ethernet/sun/niu.c
77
writel(val & 0xffffffff, reg);
drivers/net/ethernet/sun/niu.c
78
writel(val >> 32, reg + 0x4UL);
drivers/net/ethernet/sun/sungem.c
1093
writel(gp->tx_new, gp->regs + TXDMA_KICK);
drivers/net/ethernet/sun/sungem.c
1106
writel(val, gp->regs + PCS_MIICTRL);
drivers/net/ethernet/sun/sungem.c
1127
writel(val, gp->regs + PCS_CFG);
drivers/net/ethernet/sun/sungem.c
1135
writel(val, gp->regs + PCS_MIIADV);
drivers/net/ethernet/sun/sungem.c
1143
writel(val, gp->regs + PCS_MIICTRL);
drivers/net/ethernet/sun/sungem.c
1147
writel(val, gp->regs + PCS_CFG);
drivers/net/ethernet/sun/sungem.c
1158
writel(val, gp->regs + PCS_SCTRL);
drivers/net/ethernet/sun/sungem.c
1169
writel(0xffffffff, gp->regs + GREG_IMASK);
drivers/net/ethernet/sun/sungem.c
1172
writel(gp->swrst_base | GREG_SWRST_TXRST | GREG_SWRST_RXRST,
drivers/net/ethernet/sun/sungem.c
1197
writel(val | TXDMA_CFG_ENABLE, gp->regs + TXDMA_CFG);
drivers/net/ethernet/sun/sungem.c
1199
writel(val | RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG);
drivers/net/ethernet/sun/sungem.c
1201
writel(val | MAC_TXCFG_ENAB, gp->regs + MAC_TXCFG);
drivers/net/ethernet/sun/sungem.c
1203
writel(val | MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
drivers/net/ethernet/sun/sungem.c
1210
writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);
drivers/net/ethernet/sun/sungem.c
1221
writel(val & ~TXDMA_CFG_ENABLE, gp->regs + TXDMA_CFG);
drivers/net/ethernet/sun/sungem.c
1223
writel(val & ~RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG);
drivers/net/ethernet/sun/sungem.c
1225
writel(val & ~MAC_TXCFG_ENAB, gp->regs + MAC_TXCFG);
drivers/net/ethernet/sun/sungem.c
1227
writel(val & ~MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
drivers/net/ethernet/sun/sungem.c
127
writel(cmd, gp->regs + MIF_FRAME);
drivers/net/ethernet/sun/sungem.c
1367
writel(val, gp->regs + MAC_TXCFG);
drivers/net/ethernet/sun/sungem.c
1381
writel(val, gp->regs + MAC_XIFCFG);
drivers/net/ethernet/sun/sungem.c
1388
writel(val | MAC_TXCFG_TCE, gp->regs + MAC_TXCFG);
drivers/net/ethernet/sun/sungem.c
1391
writel(val | MAC_RXCFG_RCE, gp->regs + MAC_RXCFG);
drivers/net/ethernet/sun/sungem.c
1394
writel(val & ~MAC_TXCFG_TCE, gp->regs + MAC_TXCFG);
drivers/net/ethernet/sun/sungem.c
1397
writel(val & ~MAC_RXCFG_RCE, gp->regs + MAC_RXCFG);
drivers/net/ethernet/sun/sungem.c
1409
writel(512, gp->regs + MAC_STIME);
drivers/net/ethernet/sun/sungem.c
1411
writel(64, gp->regs + MAC_STIME);
drivers/net/ethernet/sun/sungem.c
1417
writel(val, gp->regs + MAC_MCCFG);
drivers/net/ethernet/sun/sungem.c
165
writel(cmd, gp->regs + MIF_FRAME);
drivers/net/ethernet/sun/sungem.c
1661
writel(mifcfg, gp->regs + MIF_CFG);
drivers/net/ethernet/sun/sungem.c
1701
writel(val, gp->regs + PCS_DMODE);
drivers/net/ethernet/sun/sungem.c
1737
writel(val, gp->regs + TXDMA_CFG);
drivers/net/ethernet/sun/sungem.c
1739
writel(desc_dma >> 32, gp->regs + TXDMA_DBHI);
drivers/net/ethernet/sun/sungem.c
1740
writel(desc_dma & 0xffffffff, gp->regs + TXDMA_DBLOW);
drivers/net/ethernet/sun/sungem.c
1743
writel(0, gp->regs + TXDMA_KICK);
drivers/net/ethernet/sun/sungem.c
1747
writel(val, gp->regs + RXDMA_CFG);
drivers/net/ethernet/sun/sungem.c
1749
writel(desc_dma >> 32, gp->regs + RXDMA_DBHI);
drivers/net/ethernet/sun/sungem.c
1750
writel(desc_dma & 0xffffffff, gp->regs + RXDMA_DBLOW);
drivers/net/ethernet/sun/sungem.c
1752
writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);
drivers/net/ethernet/sun/sungem.c
1756
writel(val, gp->regs + RXDMA_PTHRESH);
drivers/net/ethernet/sun/sungem.c
1759
writel(((5 & RXDMA_BLANK_IPKTS) |
drivers/net/ethernet/sun/sungem.c
1763
writel(((5 & RXDMA_BLANK_IPKTS) |
drivers/net/ethernet/sun/sungem.c
1776
writel(0xffff, gp->regs + MAC_HASH0 + (i << 2));
drivers/net/ethernet/sun/sungem.c
1793
writel(hash_table[i], gp->regs + MAC_HASH0 + (i << 2));
drivers/net/ethernet/sun/sungem.c
1804
writel(0x1bf0, gp->regs + MAC_SNDPAUSE);
drivers/net/ethernet/sun/sungem.c
1806
writel(0x00, gp->regs + MAC_IPG0);
drivers/net/ethernet/sun/sungem.c
1807
writel(0x08, gp->regs + MAC_IPG1);
drivers/net/ethernet/sun/sungem.c
1808
writel(0x04, gp->regs + MAC_IPG2);
drivers/net/ethernet/sun/sungem.c
1809
writel(0x40, gp->regs + MAC_STIME);
drivers/net/ethernet/sun/sungem.c
1810
writel(0x40, gp->regs + MAC_MINFSZ);
drivers/net/ethernet/sun/sungem.c
1813
writel(0x20000000 | (gp->rx_buf_sz + 4), gp->regs + MAC_MAXFSZ);
drivers/net/ethernet/sun/sungem.c
1815
writel(0x07, gp->regs + MAC_PASIZE);
drivers/net/ethernet/sun/sungem.c
1816
writel(0x04, gp->regs + MAC_JAMSIZE);
drivers/net/ethernet/sun/sungem.c
1817
writel(0x10, gp->regs + MAC_ATTLIM);
drivers/net/ethernet/sun/sungem.c
1818
writel(0x8808, gp->regs + MAC_MCTYPE);
drivers/net/ethernet/sun/sungem.c
1820
writel((e[5] | (e[4] << 8)) & 0x3ff, gp->regs + MAC_RANDSEED);
drivers/net/ethernet/sun/sungem.c
1822
writel((e[4] << 8) | e[5], gp->regs + MAC_ADDR0);
drivers/net/ethernet/sun/sungem.c
1823
writel((e[2] << 8) | e[3], gp->regs + MAC_ADDR1);
drivers/net/ethernet/sun/sungem.c
1824
writel((e[0] << 8) | e[1], gp->regs + MAC_ADDR2);
drivers/net/ethernet/sun/sungem.c
1826
writel(0, gp->regs + MAC_ADDR3);
drivers/net/ethernet/sun/sungem.c
1827
writel(0, gp->regs + MAC_ADDR4);
drivers/net/ethernet/sun/sungem.c
1828
writel(0, gp->regs + MAC_ADDR5);
drivers/net/ethernet/sun/sungem.c
1830
writel(0x0001, gp->regs + MAC_ADDR6);
drivers/net/ethernet/sun/sungem.c
1831
writel(0xc200, gp->regs + MAC_ADDR7);
drivers/net/ethernet/sun/sungem.c
1832
writel(0x0180, gp->regs + MAC_ADDR8);
drivers/net/ethernet/sun/sungem.c
1834
writel(0, gp->regs + MAC_AFILT0);
drivers/net/ethernet/sun/sungem.c
1835
writel(0, gp->regs + MAC_AFILT1);
drivers/net/ethernet/sun/sungem.c
1836
writel(0, gp->regs + MAC_AFILT2);
drivers/net/ethernet/sun/sungem.c
1837
writel(0, gp->regs + MAC_AF21MSK);
drivers/net/ethernet/sun/sungem.c
1838
writel(0, gp->regs + MAC_AF0MSK);
drivers/net/ethernet/sun/sungem.c
1844
writel(0, gp->regs + MAC_NCOLL);
drivers/net/ethernet/sun/sungem.c
1845
writel(0, gp->regs + MAC_FASUCC);
drivers/net/ethernet/sun/sungem.c
1846
writel(0, gp->regs + MAC_ECOLL);
drivers/net/ethernet/sun/sungem.c
1847
writel(0, gp->regs + MAC_LCOLL);
drivers/net/ethernet/sun/sungem.c
1848
writel(0, gp->regs + MAC_DTIMER);
drivers/net/ethernet/sun/sungem.c
1849
writel(0, gp->regs + MAC_PATMPS);
drivers/net/ethernet/sun/sungem.c
1850
writel(0, gp->regs + MAC_RFCTR);
drivers/net/ethernet/sun/sungem.c
1851
writel(0, gp->regs + MAC_LERR);
drivers/net/ethernet/sun/sungem.c
1852
writel(0, gp->regs + MAC_AERR);
drivers/net/ethernet/sun/sungem.c
1853
writel(0, gp->regs + MAC_FCSERR);
drivers/net/ethernet/sun/sungem.c
1854
writel(0, gp->regs + MAC_RXCVERR);
drivers/net/ethernet/sun/sungem.c
1859
writel(0, gp->regs + MAC_TXCFG);
drivers/net/ethernet/sun/sungem.c
1860
writel(gp->mac_rx_cfg, gp->regs + MAC_RXCFG);
drivers/net/ethernet/sun/sungem.c
1861
writel(0, gp->regs + MAC_MCCFG);
drivers/net/ethernet/sun/sungem.c
1862
writel(0, gp->regs + MAC_XIFCFG);
drivers/net/ethernet/sun/sungem.c
1868
writel(MAC_TXSTAT_XMIT, gp->regs + MAC_TXMASK);
drivers/net/ethernet/sun/sungem.c
1869
writel(MAC_RXSTAT_RCV, gp->regs + MAC_RXMASK);
drivers/net/ethernet/sun/sungem.c
1874
writel(0xffffffff, gp->regs + MAC_MCMASK);
drivers/net/ethernet/sun/sungem.c
1879
writel(0, gp->regs + WOL_WAKECSR);
drivers/net/ethernet/sun/sungem.c
190
writel(GREG_STAT_TXDONE, gp->regs + GREG_IMASK);
drivers/net/ethernet/sun/sungem.c
1914
writel(cfg, gp->regs + GREG_CFG);
drivers/net/ethernet/sun/sungem.c
1922
writel(cfg, gp->regs + GREG_CFG);
drivers/net/ethernet/sun/sungem.c
1944
writel(mif_cfg, gp->regs + MIF_CFG);
drivers/net/ethernet/sun/sungem.c
1945
writel(PCS_DMODE_MGM, gp->regs + PCS_DMODE);
drivers/net/ethernet/sun/sungem.c
1946
writel(MAC_XIFCFG_OE, gp->regs + MAC_XIFCFG);
drivers/net/ethernet/sun/sungem.c
196
writel(GREG_STAT_NAPI | GREG_STAT_TXDONE, gp->regs + GREG_IMASK);
drivers/net/ethernet/sun/sungem.c
1981
writel(mif_cfg, gp->regs + MIF_CFG);
drivers/net/ethernet/sun/sungem.c
1985
writel(mif_cfg, gp->regs + MIF_CFG);
drivers/net/ethernet/sun/sungem.c
2076
writel(mifcfg, gp->regs + MIF_CFG);
drivers/net/ethernet/sun/sungem.c
2083
writel(MAC_RXCFG_HFE | MAC_RXCFG_SFCS | MAC_RXCFG_ENAB,
drivers/net/ethernet/sun/sungem.c
2085
writel((e[4] << 8) | e[5], gp->regs + WOL_MATCH0);
drivers/net/ethernet/sun/sungem.c
2086
writel((e[2] << 8) | e[3], gp->regs + WOL_MATCH1);
drivers/net/ethernet/sun/sungem.c
2087
writel((e[0] << 8) | e[1], gp->regs + WOL_MATCH2);
drivers/net/ethernet/sun/sungem.c
2089
writel(WOL_MCOUNT_N | WOL_MCOUNT_M, gp->regs + WOL_MCOUNT);
drivers/net/ethernet/sun/sungem.c
2093
writel(csr, gp->regs + WOL_WAKECSR);
drivers/net/ethernet/sun/sungem.c
2095
writel(0, gp->regs + MAC_RXCFG);
drivers/net/ethernet/sun/sungem.c
2104
writel(0, gp->regs + MAC_TXCFG);
drivers/net/ethernet/sun/sungem.c
2105
writel(0, gp->regs + MAC_XIFCFG);
drivers/net/ethernet/sun/sungem.c
2106
writel(0, gp->regs + TXDMA_CFG);
drivers/net/ethernet/sun/sungem.c
2107
writel(0, gp->regs + RXDMA_CFG);
drivers/net/ethernet/sun/sungem.c
2111
writel(MAC_TXRST_CMD, gp->regs + MAC_TXRST);
drivers/net/ethernet/sun/sungem.c
2112
writel(MAC_RXRST_CMD, gp->regs + MAC_RXRST);
drivers/net/ethernet/sun/sungem.c
2120
writel(mifcfg | MIF_CFG_BBMODE, gp->regs + MIF_CFG);
drivers/net/ethernet/sun/sungem.c
2121
writel(0, gp->regs + MIF_BBCLK);
drivers/net/ethernet/sun/sungem.c
2122
writel(0, gp->regs + MIF_BBDATA);
drivers/net/ethernet/sun/sungem.c
2123
writel(0, gp->regs + MIF_BBOENAB);
drivers/net/ethernet/sun/sungem.c
2124
writel(MAC_XIFCFG_GMII | MAC_XIFCFG_LBCK, gp->regs + MAC_XIFCFG);
drivers/net/ethernet/sun/sungem.c
2403
writel(0, gp->regs + MAC_FCSERR);
drivers/net/ethernet/sun/sungem.c
2406
writel(0, gp->regs + MAC_AERR);
drivers/net/ethernet/sun/sungem.c
2409
writel(0, gp->regs + MAC_LERR);
drivers/net/ethernet/sun/sungem.c
2414
writel(0, gp->regs + MAC_ECOLL);
drivers/net/ethernet/sun/sungem.c
2415
writel(0, gp->regs + MAC_LCOLL);
drivers/net/ethernet/sun/sungem.c
2439
writel((e[4] << 8) | e[5], gp->regs + MAC_ADDR0);
drivers/net/ethernet/sun/sungem.c
2440
writel((e[2] << 8) | e[3], gp->regs + MAC_ADDR1);
drivers/net/ethernet/sun/sungem.c
2441
writel((e[0] << 8) | e[1], gp->regs + MAC_ADDR2);
drivers/net/ethernet/sun/sungem.c
2466
writel(rxcfg & ~MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
drivers/net/ethernet/sun/sungem.c
2476
writel(rxcfg, gp->regs + MAC_RXCFG);
drivers/net/ethernet/sun/sungem.c
367
writel(MAC_RXRST_CMD, gp->regs + MAC_RXRST);
drivers/net/ethernet/sun/sungem.c
378
writel(gp->mac_rx_cfg & ~MAC_RXCFG_ENAB,
drivers/net/ethernet/sun/sungem.c
391
writel(0, gp->regs + RXDMA_CFG);
drivers/net/ethernet/sun/sungem.c
405
writel(gp->swrst_base | GREG_SWRST_RXRST,
drivers/net/ethernet/sun/sungem.c
433
writel(desc_dma >> 32, gp->regs + RXDMA_DBHI);
drivers/net/ethernet/sun/sungem.c
434
writel(desc_dma & 0xffffffff, gp->regs + RXDMA_DBLOW);
drivers/net/ethernet/sun/sungem.c
435
writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);
drivers/net/ethernet/sun/sungem.c
438
writel(val, gp->regs + RXDMA_CFG);
drivers/net/ethernet/sun/sungem.c
440
writel(((5 & RXDMA_BLANK_IPKTS) |
drivers/net/ethernet/sun/sungem.c
444
writel(((5 & RXDMA_BLANK_IPKTS) |
drivers/net/ethernet/sun/sungem.c
449
writel(val, gp->regs + RXDMA_PTHRESH);
drivers/net/ethernet/sun/sungem.c
451
writel(val | RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG);
drivers/net/ethernet/sun/sungem.c
452
writel(MAC_RXSTAT_RCV, gp->regs + MAC_RXMASK);
drivers/net/ethernet/sun/sungem.c
454
writel(val | MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
drivers/net/ethernet/sun/sungem.c
728
writel(kick, gp->regs + RXDMA_KICK);
drivers/net/ethernet/sun/sunhme.c
181
writel(val, reg);
drivers/net/ethernet/sun/sunhme.c
239
writel((__val), (__reg))
drivers/net/ethernet/sunplus/spl2sw_driver.c
133
writel(MAC_TRIG_L_SOC0, comm->l2sw_reg_base + L2SW_CPU_TX_TRIG);
drivers/net/ethernet/sunplus/spl2sw_driver.c
40
writel(mask, comm->l2sw_reg_base + L2SW_SW_INT_MASK_0);
drivers/net/ethernet/sunplus/spl2sw_int.c
131
writel(mask, comm->l2sw_reg_base + L2SW_SW_INT_MASK_0);
drivers/net/ethernet/sunplus/spl2sw_int.c
204
writel(mask, comm->l2sw_reg_base + L2SW_SW_INT_MASK_0);
drivers/net/ethernet/sunplus/spl2sw_int.c
223
writel(status, comm->l2sw_reg_base + L2SW_SW_INT_STATUS_0);
drivers/net/ethernet/sunplus/spl2sw_int.c
230
writel(mask, comm->l2sw_reg_base + L2SW_SW_INT_MASK_0);
drivers/net/ethernet/sunplus/spl2sw_int.c
250
writel(mask, comm->l2sw_reg_base + L2SW_SW_INT_MASK_0);
drivers/net/ethernet/sunplus/spl2sw_int.c
264
writel(mask, comm->l2sw_reg_base + L2SW_SW_INT_MASK_0);
drivers/net/ethernet/sunplus/spl2sw_mac.c
105
writel(reg, comm->l2sw_reg_base + L2SW_WT_MAC_AD0);
drivers/net/ethernet/sunplus/spl2sw_mac.c
131
writel(reg, comm->l2sw_reg_base + L2SW_CPU_CNTL);
drivers/net/ethernet/sunplus/spl2sw_mac.c
134
writel(comm->desc_dma, comm->l2sw_reg_base + L2SW_TX_LBASE_ADDR_0);
drivers/net/ethernet/sunplus/spl2sw_mac.c
135
writel(comm->desc_dma + sizeof(struct spl2sw_mac_desc) * TX_DESC_NUM,
drivers/net/ethernet/sunplus/spl2sw_mac.c
137
writel(comm->desc_dma + sizeof(struct spl2sw_mac_desc) * (TX_DESC_NUM +
drivers/net/ethernet/sunplus/spl2sw_mac.c
139
writel(comm->desc_dma + sizeof(struct spl2sw_mac_desc) * (TX_DESC_NUM +
drivers/net/ethernet/sunplus/spl2sw_mac.c
144
writel(0x4a3a2d1d, comm->l2sw_reg_base + L2SW_FL_CNTL_TH);
drivers/net/ethernet/sunplus/spl2sw_mac.c
147
writel(0x4a3a1212, comm->l2sw_reg_base + L2SW_CPU_FL_CNTL_TH);
drivers/net/ethernet/sunplus/spl2sw_mac.c
150
writel(0xf6680000, comm->l2sw_reg_base + L2SW_PRI_FL_CNTL);
drivers/net/ethernet/sunplus/spl2sw_mac.c
155
writel(reg, comm->l2sw_reg_base + L2SW_LED_PORT0);
drivers/net/ethernet/sunplus/spl2sw_mac.c
166
writel(reg, comm->l2sw_reg_base + L2SW_CPU_CNTL);
drivers/net/ethernet/sunplus/spl2sw_mac.c
176
writel(reg, comm->l2sw_reg_base + L2SW_PORT_CNTL0);
drivers/net/ethernet/sunplus/spl2sw_mac.c
181
writel(reg, comm->l2sw_reg_base + L2SW_PORT_CNTL1);
drivers/net/ethernet/sunplus/spl2sw_mac.c
190
writel(reg, comm->l2sw_reg_base + L2SW_MAC_FORCE_MODE);
drivers/net/ethernet/sunplus/spl2sw_mac.c
196
writel(reg, comm->l2sw_reg_base + L2SW_PVID_CONFIG0);
drivers/net/ethernet/sunplus/spl2sw_mac.c
202
writel(reg, comm->l2sw_reg_base + L2SW_VLAN_MEMSET_CONFIG0);
drivers/net/ethernet/sunplus/spl2sw_mac.c
213
writel(reg, comm->l2sw_reg_base + L2SW_SW_GLB_CNTL);
drivers/net/ethernet/sunplus/spl2sw_mac.c
215
writel(MAC_INT_MASK_DEF, comm->l2sw_reg_base + L2SW_SW_INT_MASK_0);
drivers/net/ethernet/sunplus/spl2sw_mac.c
22
writel(0xffffffff, comm->l2sw_reg_base + L2SW_SW_INT_MASK_0);
drivers/net/ethernet/sunplus/spl2sw_mac.c
23
writel(0xffffffff, comm->l2sw_reg_base + L2SW_SW_INT_STATUS_0);
drivers/net/ethernet/sunplus/spl2sw_mac.c
242
writel((reg & (~mask)) | ((~rx_mode) & mask), comm->l2sw_reg_base + L2SW_CPU_CNTL);
drivers/net/ethernet/sunplus/spl2sw_mac.c
28
writel(reg, comm->l2sw_reg_base + L2SW_CPU_CNTL);
drivers/net/ethernet/sunplus/spl2sw_mac.c
34
writel(reg, comm->l2sw_reg_base + L2SW_PORT_CNTL0);
drivers/net/ethernet/sunplus/spl2sw_mac.c
45
writel(reg, comm->l2sw_reg_base + L2SW_CPU_CNTL);
drivers/net/ethernet/sunplus/spl2sw_mac.c
50
writel(reg, comm->l2sw_reg_base + L2SW_PORT_CNTL0);
drivers/net/ethernet/sunplus/spl2sw_mac.c
60
writel((mac->mac_addr[0] << 0) + (mac->mac_addr[1] << 8),
drivers/net/ethernet/sunplus/spl2sw_mac.c
62
writel((mac->mac_addr[2] << 0) + (mac->mac_addr[3] << 8) +
drivers/net/ethernet/sunplus/spl2sw_mac.c
69
writel(reg, comm->l2sw_reg_base + L2SW_WT_MAC_AD0);
drivers/net/ethernet/sunplus/spl2sw_mac.c
95
writel((mac->mac_addr[0] << 0) + (mac->mac_addr[1] << 8),
drivers/net/ethernet/sunplus/spl2sw_mac.c
97
writel((mac->mac_addr[2] << 0) + (mac->mac_addr[3] << 8) +
drivers/net/ethernet/sunplus/spl2sw_mdio.c
38
writel(reg, comm->l2sw_reg_base + L2SW_MAC_FORCE_MODE);
drivers/net/ethernet/sunplus/spl2sw_mdio.c
39
writel(reg2, comm->l2sw_reg_base + L2SW_PHY_CNTL_REG0);
drivers/net/ethernet/sunplus/spl2sw_mdio.c
52
writel(reg, comm->l2sw_reg_base + L2SW_MAC_FORCE_MODE);
drivers/net/ethernet/sunplus/spl2sw_phy.c
51
writel(reg, comm->l2sw_reg_base + L2SW_MAC_FORCE_MODE);
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
104
writel(mac_addr_hi, pdata->mac_regs + *mac_reg);
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
106
writel(mac_addr_lo, pdata->mac_regs + *mac_reg);
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
1072
writel(ring->dma_desc_count - 1, XLGMAC_DMA_REG(channel, DMA_CH_TDRLR));
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
1076
writel(upper_32_bits(desc_data->dma_desc_addr),
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
1078
writel(lower_32_bits(desc_data->dma_desc_addr),
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
1156
writel(ring->dma_desc_count - 1, XLGMAC_DMA_REG(channel, DMA_CH_RDRLR));
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
1160
writel(upper_32_bits(desc_data->dma_desc_addr),
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
1162
writel(lower_32_bits(desc_data->dma_desc_addr),
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
1168
writel(lower_32_bits(desc_data->dma_desc_addr),
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
1199
writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR));
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
1212
writel(regval, pdata->mac_regs + reg);
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
1231
writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR));
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
1248
writel(regval, pdata->mac_regs + reg);
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
1263
writel(regval, pdata->mac_regs + MAC_RFCR);
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
1275
writel(regval, pdata->mac_regs + MAC_RFCR);
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
130
writel(regval, pdata->mac_regs + MAC_VLANTR);
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
1315
writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_RIWT));
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
1336
writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR));
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
1349
writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR));
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
1373
writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_RCR));
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
1392
writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_TCR));
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
1411
writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_CR));
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
1418
writel(regval, pdata->mac_regs + MAC_RCR);
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
142
writel(regval, pdata->mac_regs + MAC_VLANTR);
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
1467
writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR));
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
1482
writel(regval, pdata->mac_regs + MTL_OMR);
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
1489
writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_TC_ETSCR));
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
1494
writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_TC_QWR));
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
1501
writel(regval, pdata->mac_regs + MTL_OMR);
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
1528
writel(regval, XLGMAC_MTL_REG(pdata, queue,
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
1542
writel(regval, XLGMAC_MTL_REG(pdata, queue,
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
155
writel(regval, pdata->mac_regs + MAC_PFR);
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
1577
writel(regval, pdata->mac_regs + reg);
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
1589
writel(regval, pdata->mac_regs + reg);
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
1595
writel(regval, pdata->mac_regs + reg);
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
1601
writel(regval, pdata->mac_regs + reg);
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
1644
writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR));
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
1666
writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR));
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
1687
writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_RQFCR));
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
1701
writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR));
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
1717
writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR));
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
1733
writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR));
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
175
writel(regval, pdata->mac_regs + MAC_VLANTR);
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
1754
writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_TCR));
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
1772
writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_CR));
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
1803
writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_TCR));
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
1834
writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_RCR));
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
188
writel(regval, pdata->mac_regs + MAC_PFR);
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
2133
writel(regval, pdata->mac_regs + MMC_CR);
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
2262
writel(regval, pdata->mac_regs + MMC_CR);
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
2276
writel(regval, pdata->mac_regs + MMC_CR);
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
2295
writel(val, pdata->mac_regs + MAC_RSSDR);
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
2306
writel(regval, pdata->mac_regs + MAC_RSSAR);
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
238
writel(regval, pdata->mac_regs + MAC_VLANHTR);
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
2403
writel(pdata->rss_options, pdata->mac_regs + MAC_RSSCR);
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
2409
writel(regval, pdata->mac_regs + MAC_RSSCR);
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
2424
writel(regval, pdata->mac_regs + MAC_RSSCR);
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
2456
writel(dma_ch_isr, XLGMAC_DMA_REG(channel, DMA_CH_SR));
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
2507
writel(dma_ch_isr, XLGMAC_DMA_REG(channel, DMA_CH_IER));
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
2520
writel(mtl_q_isr, XLGMAC_MTL_REG(pdata, i, MTL_Q_ISR));
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
2523
writel(0, XLGMAC_MTL_REG(pdata, i, MTL_Q_IER));
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
2536
writel(mac_ier, pdata->mac_regs + MAC_IER);
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
2542
writel(regval, pdata->mac_regs + MMC_RIER);
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
2546
writel(regval, pdata->mac_regs + MMC_TIER);
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
2561
writel(regval, pdata->mac_regs + MAC_TCR);
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
2578
writel(regval, pdata->mac_regs + MAC_TCR);
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
2595
writel(regval, pdata->mac_regs + MAC_TCR);
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
260
writel(regval, pdata->mac_regs + MAC_PFR);
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
2612
writel(regval, pdata->mac_regs + MAC_TCR);
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
2874
writel(dma_ch_ier, XLGMAC_DMA_REG(channel, DMA_CH_IER));
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
290
writel(regval, pdata->mac_regs + MAC_PFR);
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
2938
writel(dma_ch_ier, XLGMAC_DMA_REG(channel, DMA_CH_IER));
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
2952
writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR));
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
2984
writel(regval, pdata->mac_regs + DMA_SBMR);
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
3050
writel(regval, pdata->mac_regs + DMA_MR);
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
358
writel(hash_table[i], pdata->mac_regs + hash_reg);
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
388
writel(regval, pdata->mac_regs + MAC_PFR);
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
402
writel(regval, pdata->mac_regs + MAC_RCR);
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
423
writel(regval, pdata->mac_regs + MAC_VLANIR);
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
43
writel(regval, pdata->mac_regs + MAC_RCR);
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
512
writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_TCR));
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
521
writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR));
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
528
writel(regval, pdata->mac_regs + MAC_TCR);
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
55
writel(regval, pdata->mac_regs + MAC_RCR);
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
550
writel(regval, pdata->mac_regs + MAC_TCR);
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
557
writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR));
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
569
writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_TCR));
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
616
writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_RCR));
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
623
writel(regval, pdata->mac_regs + MAC_RQC0R);
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
635
writel(regval, pdata->mac_regs + MAC_RCR);
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
654
writel(regval, pdata->mac_regs + MAC_RCR);
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
661
writel(0, pdata->mac_regs + MAC_RQC0R);
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
672
writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_RCR));
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
68
writel(mac_addr_hi, pdata->mac_regs + MAC_MACA0HR);
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
689
writel(lower_32_bits(desc_data->dma_desc_addr),
drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c
69
writel(mac_addr_lo, pdata->mac_regs + MAC_MACA0LR);
drivers/net/ethernet/synopsys/dwc-xlgmac-net.c
324
writel(dma_ch_isr, XLGMAC_DMA_REG(channel, DMA_CH_SR));
drivers/net/ethernet/synopsys/dwc-xlgmac-net.c
983
writel(lower_32_bits(desc_data->dma_desc_addr),
drivers/net/ethernet/tehuti/tehuti.c
459
writel((val | CLKPLL_SFTRST) + 0x8, regs + regCLKPLL);
drivers/net/ethernet/tehuti/tehuti.c
462
writel(val & ~CLKPLL_SFTRST, regs + regCLKPLL);
drivers/net/ethernet/tehuti/tehuti.h
98
#define WRITE_REG(pp, reg, val) writel(val, pp->pBdxRegs + reg)
drivers/net/ethernet/tehuti/tn40.h
255
writel(val, priv->regs + reg);
drivers/net/ethernet/tehuti/tn40_mdio.c
29
writel(mdio_cfg, regs + TN40_REG_MDIO_CMD_STAT);
drivers/net/ethernet/tehuti/tn40_mdio.c
64
writel(i, regs + TN40_REG_MDIO_CMD);
drivers/net/ethernet/tehuti/tn40_mdio.c
65
writel((u32)regnum, regs + TN40_REG_MDIO_ADDR);
drivers/net/ethernet/tehuti/tn40_mdio.c
69
writel(TN40_MDIO_CMD_READ | i, regs + TN40_REG_MDIO_CMD);
drivers/net/ethernet/tehuti/tn40_mdio.c
87
writel(TN40_MDIO_CMD_VAL(device, port), regs + TN40_REG_MDIO_CMD);
drivers/net/ethernet/tehuti/tn40_mdio.c
88
writel((u32)regnum, regs + TN40_REG_MDIO_ADDR);
drivers/net/ethernet/tehuti/tn40_mdio.c
91
writel((u32)data, regs + TN40_REG_MDIO_DATA);
drivers/net/ethernet/ti/am65-cpsw-ethtool.c
765
writel(val, port->port_base + AM65_CPSW_PN_REG_CTL);
drivers/net/ethernet/ti/am65-cpsw-ethtool.c
779
writel(val, port->port_base + AM65_CPSW_PN_REG_IET_CTRL);
drivers/net/ethernet/ti/am65-cpsw-ethtool.c
858
writel(AM65_CPSW_PN_TX_RX_MAX_BLKS_IET,
drivers/net/ethernet/ti/am65-cpsw-ethtool.c
862
writel(iet->original_max_blks,
drivers/net/ethernet/ti/am65-cpsw-ethtool.c
884
writel(val, port->port_base + AM65_CPSW_PN_REG_IET_CTRL);
drivers/net/ethernet/ti/am65-cpsw-nuss.c
1058
writel(reg, common->cpsw_base + AM65_CPSW_REG_CTL);
drivers/net/ethernet/ti/am65-cpsw-nuss.c
183
writel(mac_hi, slave->port_base + AM65_CPSW_PORTN_REG_SA_H);
drivers/net/ethernet/ti/am65-cpsw-nuss.c
184
writel(mac_lo, slave->port_base + AM65_CPSW_PORTN_REG_SA_L);
drivers/net/ethernet/ti/am65-cpsw-nuss.c
1873
writel(seq_id, port->port_base + AM65_CPSW_PORTN_REG_TS_SEQ_LTYPE_REG);
drivers/net/ethernet/ti/am65-cpsw-nuss.c
1874
writel(ts_vlan_ltype, port->port_base +
drivers/net/ethernet/ti/am65-cpsw-nuss.c
1876
writel(ts_ctrl_ltype2, port->port_base +
drivers/net/ethernet/ti/am65-cpsw-nuss.c
1878
writel(ts_ctrl, port->port_base + AM65_CPSW_PORTN_REG_TS_CTL);
drivers/net/ethernet/ti/am65-cpsw-nuss.c
2066
writel(ADVERTISE_SGMII,
drivers/net/ethernet/ti/am65-cpsw-nuss.c
2081
writel(AM65_CPSW_SGMII_CONTROL_MR_AN_ENABLE,
drivers/net/ethernet/ti/am65-cpsw-nuss.c
211
writel(val, slave->port_base + AM65_CPSW_PORTN_REG_DSCP_MAP + reg_ofs);
drivers/net/ethernet/ti/am65-cpsw-nuss.c
2717
writel(0, port->port_base + AM65_CPSW_PN_REG_TX_PRI_MAP);
drivers/net/ethernet/ti/am65-cpsw-nuss.c
277
writel(val, slave->port_base + AM65_CPSW_PORTN_REG_CTL);
drivers/net/ethernet/ti/am65-cpsw-nuss.c
284
writel(AM65_CPSW_MAX_PACKET_SIZE,
drivers/net/ethernet/ti/am65-cpsw-nuss.c
3050
writel(common->default_vlan, host->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET);
drivers/net/ethernet/ti/am65-cpsw-nuss.c
3063
writel(0, host->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET);
drivers/net/ethernet/ti/am65-cpsw-nuss.c
3095
writel(slave->port_vlan, port->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET);
drivers/net/ethernet/ti/am65-cpsw-nuss.c
3131
writel(slave->port_vlan, port->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET);
drivers/net/ethernet/ti/am65-cpsw-nuss.c
3791
writel(port->vid_context, port->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET);
drivers/net/ethernet/ti/am65-cpsw-nuss.c
3794
writel(host_p->vid_context, host_p->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET);
drivers/net/ethernet/ti/am65-cpsw-nuss.c
494
writel(pri_map, host_p->port_base + AM65_CPSW_PORT_REG_RX_PRI_MAP);
drivers/net/ethernet/ti/am65-cpsw-nuss.c
495
writel(val, host_p->port_base + AM65_CPSW_PORT_REG_PRI_CTL);
drivers/net/ethernet/ti/am65-cpsw-nuss.c
879
writel(AM65_CPSW_CTL_P0_ENABLE | AM65_CPSW_CTL_P0_TX_CRC_REMOVE |
drivers/net/ethernet/ti/am65-cpsw-nuss.c
883
writel(AM65_CPSW_MAX_PACKET_SIZE,
drivers/net/ethernet/ti/am65-cpsw-nuss.c
886
writel(common->rx_flow_id_base,
drivers/net/ethernet/ti/am65-cpsw-nuss.c
888
writel(AM65_CPSW_P0_REG_CTL_RX_CHECKSUM_EN | AM65_CPSW_P0_REG_CTL_RX_REMAP_VLAN,
drivers/net/ethernet/ti/am65-cpsw-nuss.c
901
writel(val, common->cpsw_base + AM65_CPSW_REG_STAT_PORT_EN);
drivers/net/ethernet/ti/am65-cpsw-nuss.c
904
writel(0, common->cpsw_base + AM65_CPSW_REG_PTYPE);
drivers/net/ethernet/ti/am65-cpsw-nuss.c
962
writel(0, common->cpsw_base + AM65_CPSW_REG_CTL);
drivers/net/ethernet/ti/am65-cpsw-nuss.c
963
writel(0, common->cpsw_base + AM65_CPSW_REG_STAT_PORT_EN);
drivers/net/ethernet/ti/am65-cpsw-qos.c
1211
writel(ch_cir, host->port_base + AM65_CPSW_PN_REG_PRI_CIR(tx_ch));
drivers/net/ethernet/ti/am65-cpsw-qos.c
1299
writel(ch_cir,
drivers/net/ethernet/ti/am65-cpsw-qos.c
198
writel(0, port->port_base + AM65_CPSW_PN_REG_TX_PRI_MAP);
drivers/net/ethernet/ti/am65-cpsw-qos.c
260
writel(tx_prio_map, port->port_base + AM65_CPSW_PN_REG_TX_PRI_MAP);
drivers/net/ethernet/ti/am65-cpsw-qos.c
310
writel(val, port->port_base + AM65_CPSW_PN_REG_IET_VERIFY);
drivers/net/ethernet/ti/am65-cpsw-qos.c
327
writel(ctrl, port->port_base + AM65_CPSW_PN_REG_IET_CTRL);
drivers/net/ethernet/ti/am65-cpsw-qos.c
332
writel(ctrl, port->port_base + AM65_CPSW_PN_REG_IET_CTRL);
drivers/net/ethernet/ti/am65-cpsw-qos.c
369
writel(val, port->port_base + AM65_CPSW_PN_REG_IET_CTRL);
drivers/net/ethernet/ti/am65-cpsw-qos.c
397
writel(val, common->cpsw_base + AM65_CPSW_REG_CTL);
drivers/net/ethernet/ti/am65-cpsw-qos.c
47
writel(0, port->port_base + AM65_CPSW_PN_REG_PRI_CIR(prio));
drivers/net/ethernet/ti/am65-cpsw-qos.c
475
writel(val, common->cpsw_base + AM65_CPSW_REG_CTL);
drivers/net/ethernet/ti/am65-cpsw-qos.c
48
writel(0, port->port_base + AM65_CPSW_PN_REG_PRI_EIR(prio));
drivers/net/ethernet/ti/am65-cpsw-qos.c
489
writel(val, port->port_base + AM65_CPSW_PN_REG_CTL);
drivers/net/ethernet/ti/am65-cpsw-qos.c
505
writel(val, port->port_base + AM65_CPSW_PN_REG_EST_CTL);
drivers/net/ethernet/ti/am65-cpsw-qos.c
584
writel(val, port->port_base + AM65_CPSW_PN_REG_EST_CTL);
drivers/net/ethernet/ti/am65-cpsw-qos.c
665
writel(cmd, addr);
drivers/net/ethernet/ti/am65-cpsw-qos.c
758
writel(~all_fetch_allow & AM65_CPSW_FETCH_ALLOW_MSK, ram_addr);
drivers/net/ethernet/ti/am65-cpsw-qos.c
86
writel(rate_mbps,
drivers/net/ethernet/ti/am65-cpsw-qos.c
98
writel(rate_mbps,
drivers/net/ethernet/ti/am65-cpsw-switchdev.c
144
writel(pvid, port->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET);
drivers/net/ethernet/ti/am65-cpsw-switchdev.c
146
writel(pvid, host_p->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET);
drivers/net/ethernet/ti/am65-cpts.c
203
#define am65_cpts_write32(c, v, r) writel(v, &(c)->reg->r)
drivers/net/ethernet/ti/cpsw-phy-sel.c
149
writel(reg, priv->gmii_sel);
drivers/net/ethernet/ti/cpsw-phy-sel.c
96
writel(reg, priv->gmii_sel);
drivers/net/ethernet/ti/cpsw.c
687
writel(vlan, &cpsw->host_port_regs->port_vlan);
drivers/net/ethernet/ti/cpsw.c
717
writel(control_reg, &cpsw->regs->control);
drivers/net/ethernet/ti/cpsw.c
720
writel(fifo_mode, &cpsw->host_port_regs->tx_in_ctl);
drivers/net/ethernet/ti/cpsw.c
832
writel(0x7, &cpsw->regs->flow_control);
drivers/net/ethernet/ti/cpsw.c
862
writel(0x10, &cpsw->wr_regs->misc_en);
drivers/net/ethernet/ti/cpsw_ale.c
1251
writel(aging_timer, ale->params.ale_regs + ALE_AGING_TIMER);
drivers/net/ethernet/ti/cpsw_ale.c
1256
writel(0, ale->params.ale_regs + ALE_AGING_TIMER);
drivers/net/ethernet/ti/cpsw_ale.c
1302
writel((u32)ale_prescale, ale->params.ale_regs + ALE_PRESCALE);
drivers/net/ethernet/ti/cpsw_ale.c
620
writel(reg_mcast, ale->params.ale_regs + ALE_VLAN_MASK_MUX(idx));
drivers/net/ethernet/ti/cpsw_ale.c
625
writel(unreg_mcast, ale->params.ale_regs + ALE_VLAN_MASK_MUX(idx));
drivers/net/ethernet/ti/cpsw_ale.c
870
writel(unreg_mcast, ale->params.ale_regs + ALE_VLAN_MASK_MUX(idx));
drivers/net/ethernet/ti/cpsw_ethtool.c
208
writel(num_interrupts, &cpsw->wr_regs->rx_imax);
drivers/net/ethernet/ti/cpsw_ethtool.c
209
writel(num_interrupts, &cpsw->wr_regs->tx_imax);
drivers/net/ethernet/ti/cpsw_ethtool.c
216
writel(int_ctrl, &cpsw->wr_regs->int_control);
drivers/net/ethernet/ti/cpsw_new.c
539
writel(CPSW_FIFO_NORMAL_MODE, &cpsw->host_port_regs->tx_in_ctl);
drivers/net/ethernet/ti/cpsw_new.c
541
writel(vlan, &cpsw->host_port_regs->port_vlan);
drivers/net/ethernet/ti/cpsw_new.c
558
writel(CPSW_FIFO_DUAL_MAC_MODE, &cpsw->host_port_regs->tx_in_ctl);
drivers/net/ethernet/ti/cpsw_new.c
563
writel(vlan, &cpsw->host_port_regs->port_vlan);
drivers/net/ethernet/ti/cpsw_new.c
584
writel(control_reg, &cpsw->regs->control);
drivers/net/ethernet/ti/cpsw_new.c
598
writel(0x7, &cpsw->regs->flow_control);
drivers/net/ethernet/ti/cpsw_new.c
899
writel(0x10, &cpsw->wr_regs->misc_en);
drivers/net/ethernet/ti/cpsw_priv.c
106
writel(0, &cpsw->wr_regs->rx_en);
drivers/net/ethernet/ti/cpsw_priv.c
122
writel(0, &cpsw->wr_regs->misc_en);
drivers/net/ethernet/ti/cpsw_priv.c
125
writel(0x10, &cpsw->wr_regs->misc_en);
drivers/net/ethernet/ti/cpsw_priv.c
156
writel(0xff, &cpsw->wr_regs->tx_en);
drivers/net/ethernet/ti/cpsw_priv.c
170
writel(0xff, &cpsw->wr_regs->tx_en);
drivers/net/ethernet/ti/cpsw_priv.c
206
writel(0xff, &cpsw->wr_regs->rx_en);
drivers/net/ethernet/ti/cpsw_priv.c
220
writel(0xff, &cpsw->wr_regs->rx_en);
drivers/net/ethernet/ti/cpsw_priv.c
90
writel(0, &cpsw->wr_regs->tx_en);
drivers/net/ethernet/ti/cpsw_sl.c
213
writel(val, sl->sl_base + sl->regs[reg]);
drivers/net/ethernet/ti/cpsw_switchdev.c
161
writel(pvid, port_vlan_reg);
drivers/net/ethernet/ti/davinci_cpdma.c
176
#define dma_reg_write(ctlr, ofs, v) writel(v, (ctlr)->dmaregs + (ofs))
drivers/net/ethernet/ti/davinci_cpdma.c
177
#define chan_write(chan, fld, v) writel(v, (chan)->fld)
drivers/net/ethernet/ti/davinci_cpdma.c
178
#define desc_write(desc, fld, v) writel((u32)(v), &(desc)->fld)
drivers/net/ethernet/ti/davinci_cpdma.c
561
writel(0, ctlr->params.txhdp + 4 * i);
drivers/net/ethernet/ti/davinci_cpdma.c
562
writel(0, ctlr->params.rxhdp + 4 * i);
drivers/net/ethernet/ti/davinci_cpdma.c
563
writel(0, ctlr->params.txcp + 4 * i);
drivers/net/ethernet/ti/davinci_cpdma.c
564
writel(0, ctlr->params.rxcp + 4 * i);
drivers/net/ethernet/ti/davinci_mdio.c
143
writel(data->clk_div | CONTROL_ENABLE, &data->regs->control);
drivers/net/ethernet/ti/davinci_mdio.c
157
writel(reg, &data->regs->control);
drivers/net/ethernet/ti/davinci_mdio.c
166
writel(reg, &data->regs->poll);
drivers/net/ethernet/ti/davinci_mdio.c
182
writel(reg, &data->regs->manualif);
drivers/net/ethernet/ti/davinci_mdio.c
198
writel(reg, &data->regs->manualif);
drivers/net/ethernet/ti/davinci_mdio.c
214
writel(reg, &data->regs->manualif);
drivers/net/ethernet/ti/davinci_mdio.c
426
writel(reg, &data->regs->user[0].access);
drivers/net/ethernet/ti/davinci_mdio.c
467
writel(reg, &data->regs->user[0].access);
drivers/net/ethernet/ti/davinci_mdio.c
685
writel(ctrl, &data->regs->control);
drivers/net/ethernet/ti/icssg/icss_iep.c
107
writel(upper_32_bits(ns), iep->base +
drivers/net/ethernet/ti/icssg/icss_iep.c
109
writel(lower_32_bits(ns), iep->base + iep->plat_data->reg_offs[ICSS_IEP_COUNT_REG0]);
drivers/net/ethernet/ti/icssg/icss_iep.c
130
writel(0, iep->base + iep->plat_data->reg_offs[ICSS_IEP_SYNC_CTRL_REG]);
drivers/net/ethernet/ti/icssg/icss_iep.c
136
writel(IEP_SYNC_CTRL_SYNC_N_EN(0) | IEP_SYNC_CTRL_SYNC_EN,
drivers/net/ethernet/ti/icssg/icss_iep.c
544
writel(lower_32_bits(ns_next),
drivers/net/ethernet/ti/icssg/icss_iep.c
547
writel(upper_32_bits(ns_next),
drivers/net/ethernet/ti/icssg/icss_iep.c
569
writel(BIT(1), iep->base + reg_offs[ICSS_IEP_CMP_STAT_REG]);
drivers/net/ethernet/ti/icssg/icss_iep.c
921
writel(val, iep->base + iep->plat_data->reg_offs[reg]);
drivers/net/ethernet/ti/icssg/icssg_config.c
264
writel(EMAC_NONE, &p->cmd[i]);
drivers/net/ethernet/ti/icssg/icssg_config.c
313
writel(addr, &bpool_cfg[i].addr);
drivers/net/ethernet/ti/icssg/icssg_config.c
314
writel(PRUETH_SW_FWD_BUF_POOL_SIZE, &bpool_cfg[i].len);
drivers/net/ethernet/ti/icssg/icssg_config.c
330
writel(addr, &bpool_cfg[cfg_idx].addr);
drivers/net/ethernet/ti/icssg/icssg_config.c
331
writel(PRUETH_SW_LI_BUF_POOL_SIZE,
drivers/net/ethernet/ti/icssg/icssg_config.c
335
writel(0, &bpool_cfg[cfg_idx].addr);
drivers/net/ethernet/ti/icssg/icssg_config.c
336
writel(0, &bpool_cfg[cfg_idx].len);
drivers/net/ethernet/ti/icssg/icssg_config.c
346
writel(addr, &rxq_ctx->start[i]);
drivers/net/ethernet/ti/icssg/icssg_config.c
349
writel(addr, &rxq_ctx->end);
drivers/net/ethernet/ti/icssg/icssg_config.c
357
writel(addr, &rxq_ctx->start[i]);
drivers/net/ethernet/ti/icssg/icssg_config.c
360
writel(addr, &rxq_ctx->end);
drivers/net/ethernet/ti/icssg/icssg_config.c
366
writel(addr, &rxq_ctx->start[0]);
drivers/net/ethernet/ti/icssg/icssg_config.c
400
writel(0, &bpool_cfg[i].addr);
drivers/net/ethernet/ti/icssg/icssg_config.c
401
writel(0, &bpool_cfg[i].len);
drivers/net/ethernet/ti/icssg/icssg_config.c
416
writel(addr, &bpool_cfg[cfg_idx].addr);
drivers/net/ethernet/ti/icssg/icssg_config.c
417
writel(PRUETH_EMAC_LI_BUF_POOL_SIZE,
drivers/net/ethernet/ti/icssg/icssg_config.c
421
writel(0, &bpool_cfg[cfg_idx].addr);
drivers/net/ethernet/ti/icssg/icssg_config.c
422
writel(0, &bpool_cfg[cfg_idx].len);
drivers/net/ethernet/ti/icssg/icssg_config.c
432
writel(addr, &rxq_ctx->start[i]);
drivers/net/ethernet/ti/icssg/icssg_config.c
435
writel(addr, &rxq_ctx->end);
drivers/net/ethernet/ti/icssg/icssg_config.c
443
writel(addr, &rxq_ctx->start[i]);
drivers/net/ethernet/ti/icssg/icssg_config.c
446
writel(addr, &rxq_ctx->end);
drivers/net/ethernet/ti/icssg/icssg_config.c
452
writel(addr, &rxq_ctx->start[0]);
drivers/net/ethernet/ti/icssg/icssg_config.c
610
writel(emac_r32_bitmask[cmd].cmd[i], &p->cmd[i]);
drivers/net/ethernet/ti/icssg/icssg_config.c
633
writel(val, emac->dram.va + HD_RAND_SEED_OFFSET);
drivers/net/ethernet/ti/icssg/icssg_config.c
834
writel(pvid, prueth->shram.va + EMAC_ICSSG_SWITCH_PORT1_DEFAULT_VLAN_OFFSET);
drivers/net/ethernet/ti/icssg/icssg_config.c
836
writel(pvid, prueth->shram.va + EMAC_ICSSG_SWITCH_PORT2_DEFAULT_VLAN_OFFSET);
drivers/net/ethernet/ti/icssg/icssg_config.c
838
writel(pvid, prueth->shram.va + EMAC_ICSSG_SWITCH_PORT0_DEFAULT_VLAN_OFFSET);
drivers/net/ethernet/ti/icssg/icssg_prueth.c
563
writel(reduction_factor, emac->prueth->shram.va +
drivers/net/ethernet/ti/icssm/icssm_prueth.c
1403
writel(reg, sram + EMAC_PROMISCUOUS_MODE_OFFSET);
drivers/net/ethernet/ti/icssm/icssm_prueth.c
614
writel(wr_buf_desc, sram + readw(&queue_desc->wr_ptr));
drivers/net/ethernet/ti/icssm/icssm_prueth.c
616
writel(wr_buf_desc, dram + readw(&queue_desc->wr_ptr));
drivers/net/ethernet/ti/icssm/icssm_prueth.c
839
writel(0, shared_ram + bd_rd_ptr);
drivers/net/ethernet/ti/icssm/icssm_prueth.c
931
writel(1 * 1024, sram + TIMESYNC_TC_RCF_OFFSET);
drivers/net/ethernet/ti/icssm/icssm_prueth.c
937
writel(200000000 / 50, sram + TIMESYNC_SYNC0_WIDTH_OFFSET);
drivers/net/ethernet/ti/icssm/icssm_prueth.c
948
writel(1000000, sram + TIMESYNC_CMP1_PERIOD_OFFSET);
drivers/net/ethernet/ti/netcp_ethss.c
1880
writel(val, GBE_REG_ADDR(gbe_dev, switch_regs, stat_port_en));
drivers/net/ethernet/ti/netcp_ethss.c
2056
writel(mac_hi(ndev->dev_addr), GBE_REG_ADDR(slave, port_regs, sa_hi));
drivers/net/ethernet/ti/netcp_ethss.c
2057
writel(mac_lo(ndev->dev_addr), GBE_REG_ADDR(slave, port_regs, sa_lo));
drivers/net/ethernet/ti/netcp_ethss.c
2086
writel(mac_control, GBE_REG_ADDR(slave, emac_regs,
drivers/net/ethernet/ti/netcp_ethss.c
2099
writel(mac_control, GBE_REG_ADDR(slave, emac_regs,
drivers/net/ethernet/ti/netcp_ethss.c
2198
writel(SOFT_RESET, GBE_REG_ADDR(slave, emac_regs, soft_reset));
drivers/net/ethernet/ti/netcp_ethss.c
2226
writel(xgmii_mode, GBE_REG_ADDR(gbe_dev, ss_regs, control));
drivers/net/ethernet/ti/netcp_ethss.c
2234
writel(max_rx_len, rx_maxlen_reg);
drivers/net/ethernet/ti/netcp_ethss.c
2235
writel(slave->mac_control, GBE_REG_ADDR(slave, emac_regs, mac_control));
drivers/net/ethernet/ti/netcp_ethss.c
2301
writel(HOST_TX_PRI_MAP_DEFAULT,
drivers/net/ethernet/ti/netcp_ethss.c
2361
writel(HOST_TX_PRI_MAP_DEFAULT,
drivers/net/ethernet/ti/netcp_ethss.c
2365
writel(NETCP_MAX_FRAME_SIZE, GBE_REG_ADDR(priv, host_port_regs,
drivers/net/ethernet/ti/netcp_ethss.c
2624
writel(0, GBE_REG_ADDR(slave, port_regs, ts_ctl));
drivers/net/ethernet/ti/netcp_ethss.c
2641
writel(ts_en, GBE_REG_ADDR(slave, port_regs, ts_ctl));
drivers/net/ethernet/ti/netcp_ethss.c
2642
writel(seq_id, GBE_REG_ADDR(slave, port_regs, ts_seq_ltype));
drivers/net/ethernet/ti/netcp_ethss.c
2643
writel(ctl, GBE_REG_ADDR(slave, port_regs, ts_ctl_ltype2));
drivers/net/ethernet/ti/netcp_ethss.c
2921
writel(0, GBE_REG_ADDR(gbe_dev, switch_regs, ptype));
drivers/net/ethernet/ti/netcp_ethss.c
2929
writel(val, GBE_REG_ADDR(gbe_dev, switch_regs, control));
drivers/net/ethernet/ti/netcp_ethss.c
2932
writel(gbe_dev->stats_en_mask, GBE_REG_ADDR(gbe_dev, switch_regs,
drivers/net/ethernet/ti/netcp_sgmii.c
33
writel(val, base + reg);
drivers/net/ethernet/ti/netcp_sgmii.c
43
writel((readl(base + reg) | val), base + reg);
drivers/net/ethernet/ti/netcp_xgbepcsr.c
185
writel(0xe0e9e038, serdes_regs + 0x1fe0 + (4 * lane));
drivers/net/ethernet/ti/netcp_xgbepcsr.c
195
writel(0x88000000, serdes_regs + 0x1ff4);
drivers/net/ethernet/ti/netcp_xgbepcsr.c
201
writel(0xee000000, serdes_regs + 0x1ff4);
drivers/net/ethernet/ti/netcp_xgbepcsr.c
22
writel(((readl(addr) & (~(mask))) | \
drivers/net/ethernet/ti/netcp_xgbepcsr.c
232
writel(0x03, sw_regs + XGBE_CTRL_OFFSET);
drivers/net/ethernet/via/via-velocity.c
1063
writel(CR0_FDXRFCEN, ®s->CR0Set);
drivers/net/ethernet/via/via-velocity.c
1065
writel(CR0_FDXRFCEN, ®s->CR0Clr);
drivers/net/ethernet/via/via-velocity.c
1068
writel(CR0_FDXTFCEN, ®s->CR0Set);
drivers/net/ethernet/via/via-velocity.c
1070
writel(CR0_FDXTFCEN, ®s->CR0Clr);
drivers/net/ethernet/via/via-velocity.c
1074
writel(CR0_FDXTFCEN, ®s->CR0Set);
drivers/net/ethernet/via/via-velocity.c
1075
writel(CR0_FDXRFCEN, ®s->CR0Clr);
drivers/net/ethernet/via/via-velocity.c
1079
writel(CR0_FDXRFCEN, ®s->CR0Set);
drivers/net/ethernet/via/via-velocity.c
1080
writel(CR0_FDXTFCEN, ®s->CR0Clr);
drivers/net/ethernet/via/via-velocity.c
1084
writel(CR0_FDXTFCEN, ®s->CR0Set);
drivers/net/ethernet/via/via-velocity.c
1085
writel(CR0_FDXRFCEN, ®s->CR0Set);
drivers/net/ethernet/via/via-velocity.c
1089
writel(CR0_FDXRFCEN, ®s->CR0Clr);
drivers/net/ethernet/via/via-velocity.c
1090
writel(CR0_FDXTFCEN, ®s->CR0Clr);
drivers/net/ethernet/via/via-velocity.c
1111
writel(CR0_SFRST, ®s->CR0Set);
drivers/net/ethernet/via/via-velocity.c
1120
writel(CR0_FORSRST, ®s->CR0Set);
drivers/net/ethernet/via/via-velocity.c
1145
writel(0xffffffff, ®s->MARCAM[0]);
drivers/net/ethernet/via/via-velocity.c
1146
writel(0xffffffff, ®s->MARCAM[4]);
drivers/net/ethernet/via/via-velocity.c
1150
writel(0xffffffff, ®s->MARCAM[0]);
drivers/net/ethernet/via/via-velocity.c
1151
writel(0xffffffff, ®s->MARCAM[4]);
drivers/net/ethernet/via/via-velocity.c
1360
writel(CR0_STOP, ®s->CR0Clr);
drivers/net/ethernet/via/via-velocity.c
1361
writel((CR0_DPOLL | CR0_TXON | CR0_RXON | CR0_STRT),
drivers/net/ethernet/via/via-velocity.c
1410
writel(vptr->rx.pool_dma, ®s->RDBaseLo);
drivers/net/ethernet/via/via-velocity.c
1418
writel(vptr->tx.pool_dma[i], ®s->TDBaseLo[i]);
drivers/net/ethernet/via/via-velocity.c
1424
writel(CR0_STOP, ®s->CR0Clr);
drivers/net/ethernet/via/via-velocity.c
1425
writel((CR0_DPOLL | CR0_TXON | CR0_RXON | CR0_STRT), ®s->CR0Set);
drivers/net/ethernet/via/via-velocity.c
2274
writel(CR0_STOP, ®s->CR0Set);
drivers/net/ethernet/via/via-velocity.c
3042
writel(mask_pattern[0][i], ®s->ByteMask[0][i]);
drivers/net/ethernet/via/via-velocity.c
3174
writel(*((u32 *) (context->mac_reg + i)), ptr + i);
drivers/net/ethernet/via/via-velocity.c
3185
writel(*((u32 *) (context->mac_reg + i)), ptr + i);
drivers/net/ethernet/via/via-velocity.c
3188
writel(*((u32 *) (context->mac_reg + i)), ptr + i);
drivers/net/ethernet/via/via-velocity.c
580
writel(vptr->rx.pool_dma, ®s->RDBaseLo);
drivers/net/ethernet/via/via-velocity.h
1148
#define mac_write_isr(regs, x) writel((x),&((regs)->ISR))
drivers/net/ethernet/via/via-velocity.h
1149
#define mac_clear_isr(regs) writel(0xffffffffL,&((regs)->ISR))
drivers/net/ethernet/via/via-velocity.h
1151
#define mac_write_int_mask(mask, regs) writel((mask),&((regs)->IMR));
drivers/net/ethernet/via/via-velocity.h
1152
#define mac_disable_int(regs) writel(CR0_GINTMSK1,&((regs)->CR0Clr))
drivers/net/ethernet/via/via-velocity.h
1153
#define mac_enable_int(regs) writel(CR0_GINTMSK1,&((regs)->CR0Set))
drivers/net/ethernet/via/via-velocity.h
1517
writel((CR0_XONEN | CR0_XHITH1 | CR0_XLTH1 | CR0_XLTH0), ®s->CR0Set);
drivers/net/ethernet/via/via-velocity.h
1518
writel((CR0_FDXTFCEN | CR0_FDXRFCEN | CR0_HDXFCEN | CR0_XHITH0), ®s->CR0Clr);
drivers/net/ethernet/via/via-velocity.h
36
#define DWORD_REG_BITS_ON(x,p) do { writel(readl((p))|(x),(p));} while (0)
drivers/net/ethernet/via/via-velocity.h
44
#define DWORD_REG_BITS_OFF(x,p) do { writel(readl((p)) & (~(x)),(p));} while (0)
drivers/net/ethernet/via/via-velocity.h
48
#define DWORD_REG_BITS_SET(x,m,p) do { writel( (readl((p)) & (~(m)))|(x),(p));} while (0)
drivers/net/ethernet/wangxun/libwx/wx_lib.c
1144
writel(i, tx_ring->tail);
drivers/net/ethernet/wangxun/libwx/wx_lib.c
372
writel(i, rx_ring->tail);
drivers/net/ethernet/wangxun/libwx/wx_type.h
1409
#define wr32(a, reg, value) writel((value), ((a)->hw_addr + (reg)))
drivers/net/ethernet/wangxun/libwx/wx_vf.c
96
writel(b4_buf[i], wx->b4_addr + i * 4);
drivers/net/fddi/defxx.c
366
writel(data, bp->base.mem + offset);
drivers/net/fjes/fjes_regs.h
122
writel((val), &base[(reg)]); \
drivers/net/mdio/mdio-bcm-iproc.c
113
writel(cmd, priv->base + MII_DATA_OFFSET);
drivers/net/mdio/mdio-bcm-iproc.c
63
writel(val, base + MII_CTRL_OFFSET);
drivers/net/mdio/mdio-bcm-iproc.c
83
writel(cmd, priv->base + MII_DATA_OFFSET);
drivers/net/mdio/mdio-hisi-femac.c
45
writel((mii_id << BIT_PHY_ADDR_OFFSET) | regnum,
drivers/net/mdio/mdio-hisi-femac.c
65
writel(MDIO_WRITE | (value << BIT_WR_DATA_OFFSET) |
drivers/net/mdio/mdio-ipq4019.c
101
writel(cmd, priv->membase + MDIO_CMD_REG);
drivers/net/mdio/mdio-ipq4019.c
123
writel(data, priv->membase + MDIO_MODE_REG);
drivers/net/mdio/mdio-ipq4019.c
126
writel((mii_id << 8) | regnum, priv->membase + MDIO_ADDR_REG);
drivers/net/mdio/mdio-ipq4019.c
131
writel(cmd, priv->membase + MDIO_CMD_REG);
drivers/net/mdio/mdio-ipq4019.c
155
writel(data, priv->membase + MDIO_MODE_REG);
drivers/net/mdio/mdio-ipq4019.c
158
writel((mii_id << 8) | mmd, priv->membase + MDIO_ADDR_REG);
drivers/net/mdio/mdio-ipq4019.c
161
writel(reg, priv->membase + MDIO_DATA_WRITE_REG);
drivers/net/mdio/mdio-ipq4019.c
165
writel(cmd, priv->membase + MDIO_CMD_REG);
drivers/net/mdio/mdio-ipq4019.c
171
writel(value, priv->membase + MDIO_DATA_WRITE_REG);
drivers/net/mdio/mdio-ipq4019.c
174
writel(cmd, priv->membase + MDIO_CMD_REG);
drivers/net/mdio/mdio-ipq4019.c
198
writel(data, priv->membase + MDIO_MODE_REG);
drivers/net/mdio/mdio-ipq4019.c
201
writel((mii_id << 8) | regnum, priv->membase + MDIO_ADDR_REG);
drivers/net/mdio/mdio-ipq4019.c
204
writel(value, priv->membase + MDIO_DATA_WRITE_REG);
drivers/net/mdio/mdio-ipq4019.c
209
writel(cmd, priv->membase + MDIO_CMD_REG);
drivers/net/mdio/mdio-ipq4019.c
240
writel(val, priv->membase + MDIO_MODE_REG);
drivers/net/mdio/mdio-ipq4019.c
262
writel(val, priv->eth_ldo_rdy);
drivers/net/mdio/mdio-ipq4019.c
82
writel(data, priv->membase + MDIO_MODE_REG);
drivers/net/mdio/mdio-ipq4019.c
85
writel((mii_id << 8) | mmd, priv->membase + MDIO_ADDR_REG);
drivers/net/mdio/mdio-ipq4019.c
88
writel(reg, priv->membase + MDIO_DATA_WRITE_REG);
drivers/net/mdio/mdio-ipq4019.c
93
writel(cmd, priv->membase + MDIO_CMD_REG);
drivers/net/mdio/mdio-moxart.c
44
writel(ctrl, data->base + REG_PHY_CTRL);
drivers/net/mdio/mdio-moxart.c
75
writel(value, data->base + REG_PHY_WRITE_DATA);
drivers/net/mdio/mdio-moxart.c
76
writel(ctrl, data->base + REG_PHY_CTRL);
drivers/net/mdio/mdio-mux-bcm-iproc.c
109
writel(0, base + MDIO_CTRL_OFFSET);
drivers/net/mdio/mdio-mux-bcm-iproc.c
120
writel(param, base + MDIO_PARAM_OFFSET);
drivers/net/mdio/mdio-mux-bcm-iproc.c
122
writel(reg, base + MDIO_ADDR_OFFSET);
drivers/net/mdio/mdio-mux-bcm-iproc.c
124
writel(op, base + MDIO_CTRL_OFFSET);
drivers/net/mdio/mdio-mux-bcm-iproc.c
206
writel(param, md->base + MDIO_PARAM_OFFSET);
drivers/net/mdio/mdio-mux-bcm-iproc.c
67
writel(val, md->base + MDIO_SCAN_CTRL_OFFSET);
drivers/net/mdio/mdio-mux-bcm-iproc.c
77
writel(val, md->base + MDIO_RATE_ADJ_EXT_OFFSET);
drivers/net/mdio/mdio-mux-bcm-iproc.c
78
writel(val, md->base + MDIO_RATE_ADJ_INT_OFFSET);
drivers/net/mdio/mdio-mux-meson-g12a.c
112
writel(val, pll->base + ETH_PLL_CTL0);
drivers/net/mdio/mdio-mux-meson-g12a.c
130
writel(0x29c0040a, pll->base + ETH_PLL_CTL0);
drivers/net/mdio/mdio-mux-meson-g12a.c
131
writel(0x927e0000, pll->base + ETH_PLL_CTL1);
drivers/net/mdio/mdio-mux-meson-g12a.c
132
writel(0xac5f49e5, pll->base + ETH_PLL_CTL2);
drivers/net/mdio/mdio-mux-meson-g12a.c
133
writel(0x00000000, pll->base + ETH_PLL_CTL3);
drivers/net/mdio/mdio-mux-meson-g12a.c
134
writel(0x00000000, pll->base + ETH_PLL_CTL4);
drivers/net/mdio/mdio-mux-meson-g12a.c
135
writel(0x20200000, pll->base + ETH_PLL_CTL5);
drivers/net/mdio/mdio-mux-meson-g12a.c
136
writel(0x0000c002, pll->base + ETH_PLL_CTL6);
drivers/net/mdio/mdio-mux-meson-g12a.c
137
writel(0x00000023, pll->base + ETH_PLL_CTL7);
drivers/net/mdio/mdio-mux-meson-g12a.c
163
writel(EPHY_G12A_ID, priv->regs + ETH_PHY_CNTL0);
drivers/net/mdio/mdio-mux-meson-g12a.c
171
writel(value, priv->regs + ETH_PHY_CNTL1);
drivers/net/mdio/mdio-mux-meson-g12a.c
172
writel(PHY_CNTL2_USE_INTERNAL |
drivers/net/mdio/mdio-mux-meson-g12a.c
178
writel(value, priv->regs + ETH_PHY_CNTL1);
drivers/net/mdio/mdio-mux-meson-g12a.c
89
writel(val, pll->base + ETH_PLL_CTL0);
drivers/net/mdio/mdio-mux-meson-g12a.c
93
writel(val, pll->base + ETH_PLL_CTL0);
drivers/net/mdio/mdio-mux-meson-gxl.c
60
writel(REG4_PWRUPRSTSIG, priv->regs + ETH_REG4);
drivers/net/mdio/mdio-mux-meson-gxl.c
61
writel(val, priv->regs + ETH_REG3);
drivers/net/mdio/mdio-mux-meson-gxl.c
69
writel(REG2_REVERSED | FIELD_PREP(REG2_PHYID, EPHY_GXL_ID),
drivers/net/mdio/mdio-mux-meson-gxl.c
74
writel(val, priv->regs + ETH_REG3);
drivers/net/mdio/mdio-mux-meson-gxl.c
75
writel(0, priv->regs + ETH_REG4);
drivers/net/mdio/mdio-mux-meson-gxl.c
84
writel(0, priv->regs + ETH_REG3);
drivers/net/mdio/mdio-sun4i.c
43
writel((mii_id << 8) | regnum, data->membase + EMAC_MAC_MADR_REG);
drivers/net/mdio/mdio-sun4i.c
45
writel(0x1, data->membase + EMAC_MAC_MCMD_REG);
drivers/net/mdio/mdio-sun4i.c
56
writel(0x0, data->membase + EMAC_MAC_MCMD_REG);
drivers/net/mdio/mdio-sun4i.c
70
writel((mii_id << 8) | regnum, data->membase + EMAC_MAC_MADR_REG);
drivers/net/mdio/mdio-sun4i.c
72
writel(0x1, data->membase + EMAC_MAC_MCMD_REG);
drivers/net/mdio/mdio-sun4i.c
83
writel(0x0, data->membase + EMAC_MAC_MCMD_REG);
drivers/net/mdio/mdio-sun4i.c
85
writel(value, data->membase + EMAC_MAC_MWTD_REG);
drivers/net/pcs/pcs-rzn1-miic.c
274
writel(0x00A5, miic->base + MIIC_PRCMD);
drivers/net/pcs/pcs-rzn1-miic.c
275
writel(0x0001, miic->base + MIIC_PRCMD);
drivers/net/pcs/pcs-rzn1-miic.c
276
writel(0xFFFE, miic->base + MIIC_PRCMD);
drivers/net/pcs/pcs-rzn1-miic.c
277
writel(0x0001, miic->base + MIIC_PRCMD);
drivers/net/pcs/pcs-rzn1-miic.c
283
writel(0x0000, miic->base + MIIC_PRCMD);
drivers/net/pcs/pcs-rzn1-miic.c
288
writel(value, miic->base + offset);
drivers/net/pcs/pcs-rzn1-miic.c
294
writel(value, miic->base + offset);
drivers/net/pcs/pcs-xpcs-plat.c
100
writel(val, pxpcs->reg_base + (ofs << 2));
drivers/net/pcs/pcs-xpcs-plat.c
153
writel(val, pxpcs->reg_base + (csr << 2));
drivers/net/pcs/pcs-xpcs-plat.c
68
writel(page, pxpcs->reg_base + (DW_VR_CSR_VIEWPORT << 2));
drivers/net/pcs/pcs-xpcs-plat.c
99
writel(page, pxpcs->reg_base + (DW_VR_CSR_VIEWPORT << 2));
drivers/net/phy/mediatek/mtk-2p5ge.c
92
writel(*((uint32_t *)(fw->data + i)), pmb_addr + i);
drivers/net/vmxnet3/vmxnet3_int.h
461
writel((val), (adapter)->hw_addr0 + (reg))
drivers/net/vmxnet3/vmxnet3_int.h
466
writel((val), (adapter)->hw_addr1 + (reg))
drivers/net/wan/farsync.c
498
#define FST_WRL(C, E, L) (writel((L), (C)->mem + WIN_OFFSET(E)))
drivers/net/wan/hd64570.c
170
writel(buff_off, &desc->bp);
drivers/net/wan/hd64570.c
696
writel(i ^ 0x12345678, rambase + i % size);
drivers/net/wan/hd64572.c
139
writel(chain_off, &desc->cp);
drivers/net/wan/hd64572.c
140
writel(buff_off, &desc->bp);
drivers/net/wan/hd64572.c
53
#define sca_outl(value, reg, card) writel(value, (card)->scabase + (reg))
drivers/net/wan/hd64572.c
612
writel(i ^ 0x12345678, rambase + i);
drivers/net/wan/pc300too.c
149
writel(card->init_ctrl_value |
drivers/net/wan/pc300too.c
152
writel(card->init_ctrl_value &
drivers/net/wan/pc300too.c
364
writel(card->init_ctrl_value | 0x40000000, p);
drivers/net/wan/pc300too.c
368
writel(card->init_ctrl_value, p);
drivers/net/wan/pc300too.c
373
writel(card->init_ctrl_value | 0x20000000, p);
drivers/net/wan/pc300too.c
377
writel(card->init_ctrl_value, p);
drivers/net/wan/pc300too.c
389
writel(card->init_ctrl_value, &card->plxbase->init_ctrl);
drivers/net/wan/pci200syn.c
324
writel(readl(p) | 0x40000000, p);
drivers/net/wan/pci200syn.c
328
writel(readl(p) & ~0x40000000, p);
drivers/net/wan/wanxl.c
266
writel(stat, card->plx + PLX_DOORBELL_FROM_CARD);
drivers/net/wan/wanxl.c
309
writel(1 << (DOORBELL_TO_CARD_TX_0 + port->node),
drivers/net/wan/wanxl.c
413
writel(1 << (DOORBELL_TO_CARD_OPEN_0 + port->node), dbr);
drivers/net/wan/wanxl.c
425
writel(1 << (DOORBELL_TO_CARD_CLOSE_0 + port->node), dbr);
drivers/net/wan/wanxl.c
437
writel(1 << (DOORBELL_TO_CARD_CLOSE_0 + port->node),
drivers/net/wan/wanxl.c
480
writel(cmd, card->plx + PLX_MAILBOX_1);
drivers/net/wan/wanxl.c
495
writel(0x80, card->plx + PLX_MAILBOX_0);
drivers/net/wan/wanxl.c
496
writel(old_value | PLX_CTL_RESET, card->plx + PLX_CONTROL);
drivers/net/wan/wanxl.c
499
writel(old_value, card->plx + PLX_CONTROL);
drivers/net/wan/wanxl.c
715
writel(ntohl(*(__be32 *)(firmware + i)), mem + PDM_OFFSET + i);
drivers/net/wan/wanxl.c
718
writel(card->status_address +
drivers/net/wan/wanxl.c
721
writel(card->status_address, mem + PDM_OFFSET + 20);
drivers/net/wan/wanxl.c
722
writel(PDM_OFFSET, mem);
drivers/net/wan/wanxl.c
725
writel(0, card->plx + PLX_MAILBOX_5);
drivers/net/wireless/ath/ath11k/mhi.c
309
writel(val, addr);
drivers/net/wireless/ath/ath12k/mhi.c
184
writel(val, addr);
drivers/net/wireless/ath/wcn36xx/dxe.c
36
writel(data, wcn->ccu_base + addr);
drivers/net/wireless/ath/wcn36xx/dxe.c
45
writel(data, wcn->dxe_base + addr);
drivers/net/wireless/ath/wil6210/fw_inc.c
386
writel(y, dst);
drivers/net/wireless/ath/wil6210/fw_inc.c
399
writel(a, gwa_addr);
drivers/net/wireless/ath/wil6210/fw_inc.c
400
writel(gw_cmd, gwa_cmd);
drivers/net/wireless/ath/wil6210/fw_inc.c
403
writel(WIL_FW_GW_CTL_RUN, gwa_ctl); /* activate gw */
drivers/net/wireless/ath/wil6210/fw_inc.c
470
writel(v, gwa_val);
drivers/net/wireless/ath/wil6210/fw_inc.c
544
writel(v[k], gwa_val[k]);
drivers/net/wireless/ath/wil6210/interrupt.c
62
writel(x, addr);
drivers/net/wireless/ath/wil6210/interrupt.c
843
writel(x, addr);
drivers/net/wireless/ath/wil6210/wil6210.h
1133
writel(val, wil->csr + HOSTADDR(reg));
drivers/net/wireless/intel/ipw2x00/ipw2200.c
357
writel(val, ipw->hw_base + ofs);
drivers/net/wireless/intel/iwlegacy/common.h
2002
writel(val, il->hw_base + ofs);
drivers/net/wireless/intel/iwlwifi/pcie/gen1_2/trans.c
1873
writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
drivers/net/wireless/marvell/mwl8k.c
4733
writel(~MWL8K_A2H_INT_TX_DONE,
drivers/net/wireless/marvell/mwl8k.c
4751
writel(~MWL8K_A2H_INT_RX_READY,
drivers/net/wireless/mediatek/mt76/dma.c
198
writel(q->desc_dma, &q->regs->desc_base);
drivers/net/wireless/mediatek/mt76/dma.c
199
writel(q->ndesc, &q->regs->ring_size);
drivers/net/wireless/mediatek/mt76/dma.h
105
writel(_val, &(_q)->regs->_field); \
drivers/net/wireless/mediatek/mt76/dma.h
112
#define Q_WRITE(_q, _field, _val) writel(_val, &(_q)->regs->_field)
drivers/net/wireless/mediatek/mt76/dma.h
70
writel(_val, &(_q)->regs->_field); \
drivers/net/wireless/mediatek/mt76/mmio.c
23
writel(val, dev->mmio.regs + offset);
drivers/net/wireless/mediatek/mt76/mmio.c
39
writel(get_unaligned_le32(data + i),
drivers/net/wireless/mediatek/mt76/mt7915/pci.c
78
writel(hif_idx | MT_PCIE_RECOG_ID_SEM,
drivers/net/wireless/mediatek/mt76/mt7915/soc.c
166
writel(val, base + offset);
drivers/net/wireless/mediatek/mt76/mt7996/npu.c
126
writel(val, &dev->mt76.q_rx[MT_RXQ_RRO_BAND0].regs->desc_base);
drivers/net/wireless/mediatek/mt76/mt7996/npu.c
135
writel(val, &dev->mt76.q_rx[MT_RXQ_RRO_BAND1].regs->desc_base);
drivers/net/wireless/mediatek/mt76/mt7996/npu.c
144
writel(val, &dev->mt76.q_rx[MT_RXQ_RRO_RXDMAD_C].regs->desc_base);
drivers/net/wireless/mediatek/mt76/mt7996/npu.c
165
writel(val, &dev->mt76.phys[i]->q_tx[0]->regs->desc_base);
drivers/net/wireless/mediatek/mt76/mt7996/pci.c
73
writel(hif_idx | MT_PCIE_RECOG_ID_SEM,
drivers/net/wireless/quantenna/qtnfmac/pcie/pcie_priv.h
84
writel(val, basereg);
drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c
1125
writel(ps->base.msi_enabled, &ps->bda->bda_rc_msi_enabled);
drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c
114
writel(ps->pcie_irq_mask, PCIE_HDP_INT_EN(ps->pcie_reg_base));
drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c
123
writel(0x0, PCIE_HDP_INT_EN(ps->pcie_reg_base));
drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c
133
writel(ps->pcie_irq_mask, PCIE_HDP_INT_EN(ps->pcie_reg_base));
drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c
143
writel(ps->pcie_irq_mask, PCIE_HDP_INT_EN(ps->pcie_reg_base));
drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c
153
writel(ps->pcie_irq_mask, PCIE_HDP_INT_EN(ps->pcie_reg_base));
drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c
163
writel(ps->pcie_irq_mask, PCIE_HDP_INT_EN(ps->pcie_reg_base));
drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c
269
writel(QTN_HOST_HI32(paddr),
drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c
272
writel(QTN_HOST_LO32(paddr),
drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c
274
writel(priv->rx_bd_num | (sizeof(struct qtnf_pearl_rx_bd)) << 16,
drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c
316
writel(QTN_HOST_HI32(paddr),
drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c
319
writel(QTN_HOST_LO32(paddr),
drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c
322
writel(index, PCIE_HDP_TX_HOST_Q_WR_PTR(ps->pcie_reg_base));
drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c
388
writel(val, PCIE_HHBM_CONFIG(ps->pcie_reg_base));
drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c
394
writel(val, PCIE_HHBM_CONFIG(ps->pcie_reg_base));
drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c
395
writel(ps->base.rx_bd_num, PCIE_HHBM_Q_LIMIT_REG(ps->pcie_reg_base));
drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c
584
writel(QTN_HOST_HI32(txbd_paddr),
drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c
587
writel(QTN_HOST_LO32(txbd_paddr),
drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c
1187
writel((u32 __force)PCI_D3hot, ts->ep_pmstate);
drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c
1189
writel(TOPAZ_IPC_IRQ_WORD(TOPAZ_RC_PM_EP_IRQ),
drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c
1208
writel((u32 __force)PCI_D0, ts->ep_pmstate);
drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c
1210
writel(TOPAZ_IPC_IRQ_WORD(TOPAZ_RC_PM_EP_IRQ),
drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c
123
writel(TOPAZ_IPC_IRQ_WORD(TOPAZ_RC_RST_EP_IRQ),
drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c
154
writel(TOPAZ_IPC_IRQ_WORD(TOPAZ_RC_CTRL_IRQ),
drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c
408
writel(TOPAZ_IPC_IRQ_WORD(TOPAZ_RC_TX_DONE_IRQ),
drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c
454
writel(0x0, ts->txqueue_wake);
drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c
460
writel(TOPAZ_IPC_IRQ_WORD(TOPAZ_RC_TX_STOP_IRQ),
drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c
477
writel(TOPAZ_IPC_IRQ_WORD(TOPAZ_RC_TX_STOP_IRQ),
drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c
535
writel(QTN_HOST_LO32(skb_paddr), &bda->request[i].addr);
drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c
536
writel(len | QTN_PCIE_TX_VALID_PKT, &bda->request[i].info);
drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c
542
writel(TOPAZ_IPC_IRQ_WORD(TOPAZ_RC_TX_DONE_IRQ),
drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c
682
writel(TOPAZ_IPC_IRQ_WORD(TOPAZ_RC_RX_DONE_IRQ),
drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c
808
writel(0x0, &bda->bda_dma_offset);
drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c
818
writel(QTN_PCI_ENDIAN_DETECT_DATA, &bda->bda_pci_endian);
drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c
823
writel(QTN_PCI_ENDIAN_VALID_STATUS, &bda->bda_pci_pre_status);
drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c
843
writel(0, &bda->bda_pci_pre_status);
drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c
844
writel(0, &bda->bda_pci_post_status);
drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c
845
writel(0, &bda->bda_pci_endian);
drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c
874
writel(flags, &bda->bda_flags);
drivers/net/wireless/quantenna/qtnfmac/shm_ipc.c
146
writel(QTNF_SHM_IPC_NEW_DATA, &shm_reg_hdr->flags);
drivers/net/wireless/quantenna/qtnfmac/shm_ipc.c
40
writel(QTNF_SHM_IPC_ACK, &shm_reg_hdr->flags);
drivers/net/wireless/ralink/rt2x00/rt2x00mmio.h
38
writel(value, rt2x00dev->csr.base + offset);
drivers/net/wireless/realtek/rtlwifi/pci.h
272
writel(val, (u8 __iomem *)rtlpriv->io.pci_mem_start + addr);
drivers/net/wireless/realtek/rtw88/pci.c
90
writel(val, rtwpci->mmap + addr);
drivers/net/wireless/realtek/rtw89/pci.c
2074
writel(data, rtwpci->mmap + addr);
drivers/ntb/hw/amd/ntb_hw_amd.c
1021
writel(reg, mmio + AMD_SIDEINFO_OFFSET);
drivers/ntb/hw/amd/ntb_hw_amd.c
1038
writel(reg, mmio + AMD_SIDEINFO_OFFSET);
drivers/ntb/hw/amd/ntb_hw_amd.c
1052
writel(ntb_ctl, mmio + AMD_CNTL_OFFSET);
drivers/ntb/hw/amd/ntb_hw_amd.c
1064
writel(ntb_ctl, mmio + AMD_CNTL_OFFSET);
drivers/ntb/hw/amd/ntb_hw_amd.c
1098
writel(ndev->int_mask, mmio + AMD_INTMASK_OFFSET);
drivers/ntb/hw/amd/ntb_hw_amd.c
1156
writel(ndev->int_mask, mmio + AMD_INTMASK_OFFSET);
drivers/ntb/hw/amd/ntb_hw_amd.c
186
writel(limit, peer_mmio + limit_reg);
drivers/ntb/hw/amd/ntb_hw_amd.c
189
writel(base_addr, mmio + limit_reg);
drivers/ntb/hw/amd/ntb_hw_amd.c
190
writel(0, peer_mmio + xlat_reg);
drivers/ntb/hw/amd/ntb_hw_amd.c
359
writel(ndev->int_mask, mmio + AMD_INTMASK_OFFSET);
drivers/ntb/hw/amd/ntb_hw_amd.c
375
writel(ndev->int_mask, mmio + AMD_INTMASK_OFFSET);
drivers/ntb/hw/amd/ntb_hw_amd.c
520
writel(val, mmio + AMD_SPAD_OFFSET + offset);
drivers/ntb/hw/amd/ntb_hw_amd.c
549
writel(val, mmio + AMD_SPAD_OFFSET + offset);
drivers/ntb/hw/amd/ntb_hw_amd.c
585
writel(reg, mmio + AMD_SMUACK_OFFSET);
drivers/ntb/hw/amd/ntb_hw_amd.c
656
writel(status, mmio + AMD_INTSTAT_OFFSET);
drivers/ntb/hw/amd/ntb_hw_amd.c
829
writel(ndev->db_mask, mmio + AMD_DBMASK_OFFSET);
drivers/ntb/hw/amd/ntb_hw_amd.h
84
writel(val, mmio);
drivers/ntb/hw/amd/ntb_hw_amd.h
85
writel(val >> 32, mmio + sizeof(u32));
drivers/ntb/hw/epf/ntb_hw_epf.c
108
writel(argument, ndev->ctrl_reg + NTB_EPF_ARGUMENT);
drivers/ntb/hw/epf/ntb_hw_epf.c
109
writel(command, ndev->ctrl_reg + NTB_EPF_COMMAND);
drivers/ntb/hw/epf/ntb_hw_epf.c
236
writel(val, ndev->ctrl_reg + offset);
drivers/ntb/hw/epf/ntb_hw_epf.c
279
writel(val, ndev->peer_spad_reg + offset);
drivers/ntb/hw/epf/ntb_hw_epf.c
428
writel(lower_32_bits(addr), ndev->ctrl_reg + NTB_EPF_LOWER_ADDR);
drivers/ntb/hw/epf/ntb_hw_epf.c
429
writel(upper_32_bits(addr), ndev->ctrl_reg + NTB_EPF_UPPER_ADDR);
drivers/ntb/hw/epf/ntb_hw_epf.c
430
writel(lower_32_bits(size), ndev->ctrl_reg + NTB_EPF_LOWER_SIZE);
drivers/ntb/hw/epf/ntb_hw_epf.c
431
writel(upper_32_bits(size), ndev->ctrl_reg + NTB_EPF_UPPER_SIZE);
drivers/ntb/hw/epf/ntb_hw_epf.c
492
writel(db_data, ndev->db_reg + (db_entry_size * interrupt_num) +
drivers/nvme/host/apple.c
1055
writel(0, anv->mmio_coproc + APPLE_ANS_COPROC_CPU_CONTROL);
drivers/nvme/host/apple.c
1077
writel(APPLE_ANS_COPROC_CPU_CONTROL_RUN,
drivers/nvme/host/apple.c
1116
writel(APPLE_ANS_LINEAR_SQ_EN,
drivers/nvme/host/apple.c
1120
writel(anv->hw->max_queue_depth
drivers/nvme/host/apple.c
1125
writel(anv->hw->max_queue_depth - 1,
drivers/nvme/host/apple.c
1135
writel(readl(anv->mmio_nvme + APPLE_ANS_UNKNOWN_CTRL) &
drivers/nvme/host/apple.c
1146
writel(aqa, anv->mmio_nvme + NVME_REG_AQA);
drivers/nvme/host/apple.c
1251
writel(val, ctrl_to_apple_nvme(ctrl)->mmio_nvme + off);
drivers/nvme/host/apple.c
1651
writel(0, anv->mmio_coproc + APPLE_ANS_COPROC_CPU_CONTROL);
drivers/nvme/host/apple.c
1665
writel(0, anv->mmio_coproc + APPLE_ANS_COPROC_CPU_CONTROL);
drivers/nvme/host/apple.c
1686
writel(0, anv->mmio_coproc + APPLE_ANS_COPROC_CPU_CONTROL);
drivers/nvme/host/apple.c
287
writel(tag, anv->mmio_nvme + APPLE_NVMMU_TCB_INVAL);
drivers/nvme/host/apple.c
309
writel(q->sq_tail, q->sq_db);
drivers/nvme/host/apple.c
345
writel(tag, q->sq_db);
drivers/nvme/host/apple.c
670
writel(q->cq_head, q->cq_db);
drivers/nvme/host/pci.c
1521
writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
drivers/nvme/host/pci.c
1693
writel(NVME_SUBSYS_RESET, dev->bar + NVME_REG_NSSR);
drivers/nvme/host/pci.c
2315
writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
drivers/nvme/host/pci.c
2358
writel(aqa, dev->bar + NVME_REG_AQA);
drivers/nvme/host/pci.c
2438
writel(NVME_CMBMSC_CRE, dev->bar + NVME_REG_CMBMSC);
drivers/nvme/host/pci.c
3470
writel(val, to_nvme_dev(ctrl)->bar + off);
drivers/nvme/host/pci.c
726
writel(nvmeq->sq_tail, nvmeq->q_db);
drivers/nvmem/bcm-ocotp.c
202
writel(*buf, priv->base + priv->map->data_w_offset[i]);
drivers/nvmem/bcm-ocotp.c
267
writel(readl(priv->base + OTPC_MODE_REG_OFFSET) |
drivers/nvmem/bcm-ocotp.c
79
writel(command & OTPC_CMD_MASK, base + OTPC_COMMAND_OFFSET);
drivers/nvmem/bcm-ocotp.c
84
writel(addr & OTPC_ADDR_MASK, base + OTPC_CPUADDR_REG_OFFSET);
drivers/nvmem/bcm-ocotp.c
89
writel(1 << OTPC_CMD_START_START, base + OTPC_CMD_START_OFFSET);
drivers/nvmem/bcm-ocotp.c
94
writel(0, base + OTPC_CMD_START_OFFSET);
drivers/nvmem/bcm-ocotp.c
99
writel(value, base + OTPC_CPU_WRITE_REG_OFFSET);
drivers/nvmem/imx-ocotp.c
155
writel(bm_ctrl_error, base + IMX_OCOTP_ADDR_CTRL_CLR);
drivers/nvmem/imx-ocotp.c
289
writel(timing, priv->base + IMX_OCOTP_ADDR_TIMING);
drivers/nvmem/imx-ocotp.c
310
writel(timing, priv->base + IMX_OCOTP_ADDR_TIMING);
drivers/nvmem/imx-ocotp.c
383
writel(ctrl, priv->base + IMX_OCOTP_ADDR_CTRL);
drivers/nvmem/imx-ocotp.c
411
writel(0, priv->base + IMX_OCOTP_ADDR_DATA1);
drivers/nvmem/imx-ocotp.c
412
writel(0, priv->base + IMX_OCOTP_ADDR_DATA2);
drivers/nvmem/imx-ocotp.c
413
writel(0, priv->base + IMX_OCOTP_ADDR_DATA3);
drivers/nvmem/imx-ocotp.c
414
writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA0);
drivers/nvmem/imx-ocotp.c
417
writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA1);
drivers/nvmem/imx-ocotp.c
418
writel(0, priv->base + IMX_OCOTP_ADDR_DATA2);
drivers/nvmem/imx-ocotp.c
419
writel(0, priv->base + IMX_OCOTP_ADDR_DATA3);
drivers/nvmem/imx-ocotp.c
420
writel(0, priv->base + IMX_OCOTP_ADDR_DATA0);
drivers/nvmem/imx-ocotp.c
423
writel(0, priv->base + IMX_OCOTP_ADDR_DATA1);
drivers/nvmem/imx-ocotp.c
424
writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA2);
drivers/nvmem/imx-ocotp.c
425
writel(0, priv->base + IMX_OCOTP_ADDR_DATA3);
drivers/nvmem/imx-ocotp.c
426
writel(0, priv->base + IMX_OCOTP_ADDR_DATA0);
drivers/nvmem/imx-ocotp.c
429
writel(0, priv->base + IMX_OCOTP_ADDR_DATA1);
drivers/nvmem/imx-ocotp.c
430
writel(0, priv->base + IMX_OCOTP_ADDR_DATA2);
drivers/nvmem/imx-ocotp.c
431
writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA3);
drivers/nvmem/imx-ocotp.c
432
writel(0, priv->base + IMX_OCOTP_ADDR_DATA0);
drivers/nvmem/imx-ocotp.c
437
writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA0);
drivers/nvmem/imx-ocotp.c
467
writel(priv->params->ctrl.bm_rel_shadows,
drivers/nvmem/lan9662-otpc.c
106
writel(OTP_OTP_PRGM_MODE_OTP_PGM_MODE_BYTE, OTP_OTP_PRGM_MODE(otp->base));
drivers/nvmem/lan9662-otpc.c
107
writel(data, OTP_OTP_PRGM_DATA(otp->base));
drivers/nvmem/lan9662-otpc.c
108
writel(OTP_OTP_FUNC_CMD_OTP_PROGRAM, OTP_OTP_FUNC_CMD(otp->base));
drivers/nvmem/lan9662-otpc.c
109
writel(OTP_OTP_CMD_GO_OTP_GO, OTP_OTP_CMD_GO(otp->base));
drivers/nvmem/lan9662-otpc.c
52
writel(readl(pwrdn) & ~OTP_OTP_PWR_DN_OTP_PWRDN_N, pwrdn);
drivers/nvmem/lan9662-otpc.c
57
writel(readl(pwrdn) | OTP_OTP_PWR_DN_OTP_PWRDN_N, pwrdn);
drivers/nvmem/lan9662-otpc.c
78
writel(0xff & (offset >> 8), OTP_OTP_ADDR_HI(otp->base));
drivers/nvmem/lan9662-otpc.c
79
writel(0xff & offset, OTP_OTP_ADDR_LO(otp->base));
drivers/nvmem/lan9662-otpc.c
88
writel(OTP_OTP_FUNC_CMD_OTP_READ, OTP_OTP_FUNC_CMD(otp->base));
drivers/nvmem/lan9662-otpc.c
89
writel(OTP_OTP_CMD_GO_OTP_GO, OTP_OTP_CMD_GO(otp->base));
drivers/nvmem/lpc18xx_eeprom.c
113
writel(*(u32 *)val, eeprom->mem_base + offset);
drivers/nvmem/lpc18xx_eeprom.c
57
writel(val, eeprom->reg_base + reg);
drivers/nvmem/meson-mx-efuse.c
58
writel(data, efuse->base + reg);
drivers/nvmem/mxs-ocotp.c
100
writel(BM_OCOTP_CTRL_RD_BANK_OPEN, otp->base + STMP_OFFSET_REG_CLR);
drivers/nvmem/mxs-ocotp.c
70
writel(BM_OCOTP_CTRL_ERROR, otp->base + STMP_OFFSET_REG_CLR);
drivers/nvmem/mxs-ocotp.c
77
writel(BM_OCOTP_CTRL_RD_BANK_OPEN, otp->base + STMP_OFFSET_REG_SET);
drivers/nvmem/qfprom.c
144
writel(old->timer_val, priv->qfpconf + QFPROM_BLOW_TIMER_OFFSET);
drivers/nvmem/qfprom.c
145
writel(old->accel_val, priv->qfpconf + QFPROM_ACCEL_OFFSET);
drivers/nvmem/qfprom.c
229
writel(priv->soc_data->qfprom_blow_timer_value,
drivers/nvmem/qfprom.c
231
writel(priv->soc_data->accel_value,
drivers/nvmem/qfprom.c
303
writel(value[i], priv->qfpraw + reg + (i * 4));
drivers/nvmem/rockchip-efuse.c
125
writel(RK3328_AUTO_RD | RK3328_AUTO_ENB |
drivers/nvmem/rockchip-efuse.c
135
writel(RK3328_INT_FINISH, efuse->base + RK3328_INT_STATUS);
drivers/nvmem/rockchip-efuse.c
177
writel(RK3399_LOAD | RK3399_PGENB | RK3399_STROBSFTSEL | RK3399_RSB,
drivers/nvmem/rockchip-efuse.c
181
writel(readl(efuse->base + REG_EFUSE_CTRL) | RK3399_STROBE |
drivers/nvmem/rockchip-efuse.c
186
writel(readl(efuse->base + REG_EFUSE_CTRL) & (~RK3399_STROBE),
drivers/nvmem/rockchip-efuse.c
195
writel(RK3399_PD | RK3399_CSB, efuse->base + REG_EFUSE_CTRL);
drivers/nvmem/rockchip-efuse.c
68
writel(RK3288_LOAD | RK3288_PGENB, efuse->base + REG_EFUSE_CTRL);
drivers/nvmem/rockchip-efuse.c
71
writel(readl(efuse->base + REG_EFUSE_CTRL) &
drivers/nvmem/rockchip-efuse.c
74
writel(readl(efuse->base + REG_EFUSE_CTRL) |
drivers/nvmem/rockchip-efuse.c
78
writel(readl(efuse->base + REG_EFUSE_CTRL) |
drivers/nvmem/rockchip-efuse.c
82
writel(readl(efuse->base + REG_EFUSE_CTRL) &
drivers/nvmem/rockchip-efuse.c
88
writel(RK3288_PGENB | RK3288_CSB, efuse->base + REG_EFUSE_CTRL);
drivers/nvmem/rockchip-otp.c
118
writel(flag, otp->base + reg);
drivers/nvmem/rockchip-otp.c
127
writel(SBPI_DAP_ADDR_MASK | (SBPI_DAP_ADDR << SBPI_DAP_ADDR_SHIFT),
drivers/nvmem/rockchip-otp.c
130
writel(SBPI_CMD_VALID_MASK | 0x1, otp->base + OTPC_SBPI_CMD_VALID_PRE);
drivers/nvmem/rockchip-otp.c
131
writel(SBPI_DAP_CMD_WRF | SBPI_DAP_REG_ECC,
drivers/nvmem/rockchip-otp.c
134
writel(SBPI_ECC_ENABLE, otp->base + OTPC_SBPI_CMD1_OFFSET);
drivers/nvmem/rockchip-otp.c
136
writel(SBPI_ECC_DISABLE, otp->base + OTPC_SBPI_CMD1_OFFSET);
drivers/nvmem/rockchip-otp.c
138
writel(SBPI_ENABLE_MASK | SBPI_ENABLE, otp->base + OTPC_SBPI_CTRL);
drivers/nvmem/rockchip-otp.c
166
writel(OTPC_USE_USER | OTPC_USE_USER_MASK, otp->base + OTPC_USER_CTRL);
drivers/nvmem/rockchip-otp.c
169
writel(offset++ | OTPC_USER_ADDR_MASK,
drivers/nvmem/rockchip-otp.c
171
writel(OTPC_USER_FSM_ENABLE | OTPC_USER_FSM_ENABLE_MASK,
drivers/nvmem/rockchip-otp.c
182
writel(0x0 | OTPC_USE_USER_MASK, otp->base + OTPC_USER_CTRL);
drivers/nvmem/rockchip-otp.c
206
writel((addr_start << RK3588_ADDR_SHIFT) |
drivers/nvmem/rockchip-otp.c
209
writel(RK3588_AUTO_EN, otp->base + RK3588_OTPC_AUTO_EN);
drivers/nvmem/sprd-efuse.c
115
writel(val, efuse->base + SPRD_EFUSE_PW_SWT);
drivers/nvmem/sprd-efuse.c
125
writel(val, efuse->base + SPRD_EFUSE_PW_SWT);
drivers/nvmem/sprd-efuse.c
140
writel(val, efuse->base + SPRD_EFUSE_ENABLE);
drivers/nvmem/sprd-efuse.c
155
writel(val, efuse->base + SPRD_EFUSE_ENABLE);
drivers/nvmem/sprd-efuse.c
167
writel(val, efuse->base + SPRD_EFUSE_ENABLE);
drivers/nvmem/sprd-efuse.c
179
writel(val, efuse->base + SPRD_EFUSE_ENABLE);
drivers/nvmem/sprd-efuse.c
191
writel(val, efuse->base + SPRD_EFUSE_PW_SWT);
drivers/nvmem/sprd-efuse.c
205
writel(SPRD_EFUSE_MAGIC_NUMBER,
drivers/nvmem/sprd-efuse.c
223
writel(*data, efuse->base + SPRD_EFUSE_MEM(blk));
drivers/nvmem/sprd-efuse.c
239
writel(SPRD_EFUSE_ERR_CLR_MASK,
drivers/nvmem/sprd-efuse.c
244
writel(0, efuse->base + SPRD_EFUSE_MEM(blk));
drivers/nvmem/sprd-efuse.c
249
writel(0, efuse->base + SPRD_EFUSE_MAGIC_NUM);
drivers/nvmem/sprd-efuse.c
286
writel(SPRD_EFUSE_ERR_CLR_MASK,
drivers/nvmem/sunplus-ocotp.c
102
writel((readl(otp->base[OTPRX] + OTP_CONTROL_2) & OTP_RD_PERIOD_MASK) | CPU_CLOCK,
drivers/nvmem/sunplus-ocotp.c
94
writel(readl(otp->base[OTPRX] + OTP_STATUS) & OTP_READ_DONE_MASK &
drivers/nvmem/sunplus-ocotp.c
96
writel(addr, otp->base[OTPRX] + OTP_READ_ADDRESS);
drivers/nvmem/sunplus-ocotp.c
97
writel(readl(otp->base[OTPRX] + OTP_CONTROL_2) | OTP_READ,
drivers/nvmem/sunplus-ocotp.c
99
writel(readl(otp->base[OTPRX] + OTP_CONTROL_2) & SEL_BAK_KEY2_MASK & SW_TRIM_EN_MASK
drivers/nvmem/sunxi_sid.c
73
writel(reg_val, sid->base + SUN8I_SID_PRCTL);
drivers/nvmem/sunxi_sid.c
83
writel(0, sid->base + SUN8I_SID_PRCTL);
drivers/nvmem/vf610-ocotp.c
105
writel(OCOTP_CTRL_ERR, base + OCOTP_CTRL_CLR);
drivers/nvmem/vf610-ocotp.c
158
writel(ocotp->timing, base + OCOTP_TIMING);
drivers/nvmem/vf610-ocotp.c
167
writel(reg, base + OCOTP_CTRL_REG);
drivers/nvmem/vf610-ocotp.c
169
writel(OCOTP_READ_CTRL_READ_FUSE,
drivers/nvmem/vf610-ocotp.c
178
writel(OCOTP_CTRL_ERR, base + OCOTP_CTRL_CLR);
drivers/parisc/dino.c
231
writel(val, base_addr + DINO_CONFIG_DATA);
drivers/parisc/iosapic.c
175
writel(reg, iosapic + IOSAPIC_REG_SELECT);
drivers/parisc/iosapic.c
181
writel(reg, iosapic + IOSAPIC_REG_SELECT);
drivers/parisc/iosapic.c
182
writel(val, iosapic + IOSAPIC_REG_WINDOW);
drivers/parisc/lba_pci.c
141
#define WRITE_REG32(value, addr) writel(value, addr)
drivers/parisc/sba_iommu.c
135
#define WRITE_REG32(val, addr) writel((val), (addr))
drivers/pci/access.c
122
writel(val, addr);
drivers/pci/access.c
157
writel(val, addr);
drivers/pci/access.c
180
writel(tmp, addr);
drivers/pci/controller/cadence/pci-j721e.c
102
writel(value, pcie->intd_cfg_base + offset);
drivers/pci/controller/cadence/pci-j721e.c
91
writel(value, pcie->user_cfg_base + offset);
drivers/pci/controller/cadence/pci-sky1.c
103
writel(val, pcie->strap_base + STRAP_REG(1));
drivers/pci/controller/cadence/pci-sky1.c
115
writel(val, pcie->strap_base + STRAP_REG(1));
drivers/pci/controller/cadence/pcie-cadence-ep.c
364
writel(0, ep->irq_cpu_addr + offset);
drivers/pci/controller/cadence/pcie-cadence-ep.c
430
writel(data, ep->irq_cpu_addr + (pci_addr & pci_addr_mask));
drivers/pci/controller/cadence/pcie-cadence-ep.c
533
writel(msg_data, ep->irq_cpu_addr + (msg_addr & pci_addr_mask));
drivers/pci/controller/cadence/pcie-cadence.h
223
writel(value, pcie->reg_base + reg);
drivers/pci/controller/cadence/pcie-cadence.h
239
writel(value, pcie->reg_base + reg);
drivers/pci/controller/cadence/pcie-cadence.h
313
writel(value, addr);
drivers/pci/controller/cadence/pcie-cadence.h
320
writel(val, aligned_addr);
drivers/pci/controller/cadence/pcie-cadence.h
390
writel(value, pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg);
drivers/pci/controller/dwc/pci-dra7xx.c
113
writel(value, pcie->base + offset);
drivers/pci/controller/dwc/pci-exynos.c
63
writel(val, base + reg);
drivers/pci/controller/dwc/pci-imx6.c
848
writel(PCIE_PHY_CMN_REG4_DCC_FB_EN, imx_pcie->phy_base + PCIE_PHY_CMN_REG4);
drivers/pci/controller/dwc/pci-imx6.c
850
writel(PCIE_PHY_CMN_REG24_RX_EQ_SEL | PCIE_PHY_CMN_REG24_RX_EQ,
drivers/pci/controller/dwc/pci-imx6.c
853
writel(PCIE_PHY_CMN_REG26_ATT_MODE, imx_pcie->phy_base + PCIE_PHY_CMN_REG26);
drivers/pci/controller/dwc/pci-keystone.c
151
writel(val, ks_pcie->va_app_base + offset);
drivers/pci/controller/dwc/pci-meson.c
239
writel(val, mp->cfg_base + reg);
drivers/pci/controller/dwc/pcie-bt1.c
203
writel(val, addr);
drivers/pci/controller/dwc/pcie-bt1.c
209
writel(tmp, addr - ofs);
drivers/pci/controller/dwc/pcie-designware-ep.c
1015
writel(msg_data, ep->msi_mem + offset);
drivers/pci/controller/dwc/pcie-designware-ep.c
933
writel(msg_data | (interrupt_num - 1), ep->msi_mem + offset);
drivers/pci/controller/dwc/pcie-designware-host.c
1212
writel(0, mem);
drivers/pci/controller/dwc/pcie-designware.c
372
writel(val, addr);
drivers/pci/controller/dwc/pcie-histb.c
74
writel(val, histb_pcie->ctrl + reg);
drivers/pci/controller/dwc/pcie-intel-gw.c
80
writel(val, base + ofs);
drivers/pci/controller/dwc/pcie-intel-gw.c
85
writel(val, pcie->app_base + ofs);
drivers/pci/controller/dwc/pcie-keembay.c
101
writel(val, pcie->apb_base + PCIE_REGS_PCIE_APP_CNTRL);
drivers/pci/controller/dwc/pcie-keembay.c
216
writel(val, pcie->apb_base + PCIE_REGS_LJPLL_CNTRL_2);
drivers/pci/controller/dwc/pcie-keembay.c
220
writel(val, pcie->apb_base + PCIE_REGS_LJPLL_CNTRL_3);
drivers/pci/controller/dwc/pcie-keembay.c
223
writel(val, pcie->apb_base + PCIE_REGS_LJPLL_CNTRL_0);
drivers/pci/controller/dwc/pcie-keembay.c
260
writel(status, pcie->apb_base + PCIE_REGS_INTERRUPT_STATUS);
drivers/pci/controller/dwc/pcie-keembay.c
288
writel(EDMA_INT_EN, pcie->apb_base + PCIE_REGS_INTERRUPT_ENABLE);
drivers/pci/controller/dwc/pcie-keembay.c
365
writel(val, pcie->apb_base + PCIE_REGS_PCIE_PHY_CNTL);
drivers/pci/controller/dwc/pcie-keembay.c
367
writel(PCIE_DEVICE_TYPE, pcie->apb_base + PCIE_REGS_PCIE_CFG);
drivers/pci/controller/dwc/pcie-keembay.c
374
writel(val | PCIE_RSTN, pcie->apb_base + PCIE_REGS_PCIE_CFG);
drivers/pci/controller/dwc/pcie-keembay.c
387
writel(val, pcie->apb_base + PCIE_REGS_INTERRUPT_ENABLE);
drivers/pci/controller/dwc/pcie-kirin.c
140
writel(val, hi3660_pcie_phy->base + reg);
drivers/pci/controller/dwc/pcie-nxp-s32g.c
56
writel(val, s32g_pp->ctrl_base + reg);
drivers/pci/controller/dwc/pcie-qcom-ep.c
298
writel(1, pci->elbi_base + ELBI_CS2_ENABLE);
drivers/pci/controller/dwc/pcie-qcom-ep.c
304
writel(0, pci->elbi_base + ELBI_CS2_ENABLE);
drivers/pci/controller/dwc/pcie-qcom.c
1006
writel(val, pcie->parf + PARF_SYS_CTRL);
drivers/pci/controller/dwc/pcie-qcom.c
1010
writel(val, pcie->parf + PARF_MHI_CLOCK_RESET_CTRL);
drivers/pci/controller/dwc/pcie-qcom.c
1015
writel(val, pcie->parf + PARF_PM_CTRL);
drivers/pci/controller/dwc/pcie-qcom.c
1021
writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2);
drivers/pci/controller/dwc/pcie-qcom.c
1037
writel(WR_NO_SNOOP_OVERRIDE_EN | RD_NO_SNOOP_OVERRIDE_EN,
drivers/pci/controller/dwc/pcie-qcom.c
1096
writel(val, pcie->parf + PARF_BDF_TO_SID_CFG);
drivers/pci/controller/dwc/pcie-qcom.c
1133
writel(val, bdf_to_sid_base + current_hash * sizeof(u32));
drivers/pci/controller/dwc/pcie-qcom.c
1141
writel(val, bdf_to_sid_base + hash * sizeof(u32));
drivers/pci/controller/dwc/pcie-qcom.c
1213
writel(val, pcie->parf + PARF_PHY_CTRL);
drivers/pci/controller/dwc/pcie-qcom.c
1217
writel(DEVICE_TYPE_RC, pcie->parf + PARF_DEVICE_TYPE);
drivers/pci/controller/dwc/pcie-qcom.c
1218
writel(BYPASS | MSTR_AXI_CLK_EN | AHB_CLK_EN,
drivers/pci/controller/dwc/pcie-qcom.c
1220
writel(GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS |
drivers/pci/controller/dwc/pcie-qcom.c
1224
writel(MST_WAKEUP_EN | SLV_WAKEUP_EN | MSTR_ACLK_CGC_DIS |
drivers/pci/controller/dwc/pcie-qcom.c
1229
writel(0, pcie->parf + PARF_Q2A_FLUSH);
drivers/pci/controller/dwc/pcie-qcom.c
1233
writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP);
drivers/pci/controller/dwc/pcie-qcom.c
1237
writel(val, pci->dbi_base + offset + PCI_EXP_LNKCAP);
drivers/pci/controller/dwc/pcie-qcom.c
1239
writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + offset +
drivers/pci/controller/dwc/pcie-qcom.c
1245
writel(0, pcie->parf + PARF_BDF_TO_SID_TABLE_N + (4 * i));
drivers/pci/controller/dwc/pcie-qcom.c
348
writel(val, pci->dbi_base + offset + PCI_EXP_LNKCAP);
drivers/pci/controller/dwc/pcie-qcom.c
362
writel(val, pci->dbi_base + offset + PCI_EXP_SLTCAP);
drivers/pci/controller/dwc/pcie-qcom.c
376
writel(lower_32_bits(pci->dbi_phys_addr), pcie->parf +
drivers/pci/controller/dwc/pcie-qcom.c
378
writel(SLV_ADDR_SPACE_SZ, pcie->parf +
drivers/pci/controller/dwc/pcie-qcom.c
393
writel(lower_32_bits(pci->dbi_phys_addr), pcie->parf +
drivers/pci/controller/dwc/pcie-qcom.c
395
writel(upper_32_bits(pci->dbi_phys_addr), pcie->parf +
drivers/pci/controller/dwc/pcie-qcom.c
399
writel(lower_32_bits(pci->atu_phys_addr), pcie->parf +
drivers/pci/controller/dwc/pcie-qcom.c
401
writel(upper_32_bits(pci->atu_phys_addr), pcie->parf +
drivers/pci/controller/dwc/pcie-qcom.c
405
writel(0x0, pcie->parf + PARF_SLV_ADDR_SPACE_SIZE_V2);
drivers/pci/controller/dwc/pcie-qcom.c
406
writel(SLV_ADDR_SPACE_SZ, pcie->parf +
drivers/pci/controller/dwc/pcie-qcom.c
423
writel(val, pci->elbi_base + ELBI_SYS_CTRL);
drivers/pci/controller/dwc/pcie-qcom.c
471
writel(1, pcie->parf + PARF_PHY_CTRL);
drivers/pci/controller/dwc/pcie-qcom.c
518
writel(val, pcie->parf + PARF_PHY_CTRL);
drivers/pci/controller/dwc/pcie-qcom.c
526
writel(PCS_DEEMPH_TX_DEEMPH_GEN1(24) |
drivers/pci/controller/dwc/pcie-qcom.c
530
writel(PCS_SWING_TX_SWING_FULL(120) |
drivers/pci/controller/dwc/pcie-qcom.c
533
writel(PHY_RX0_EQ(4), pcie->parf + PARF_CONFIG_BITS);
drivers/pci/controller/dwc/pcie-qcom.c
541
writel(val, pcie->parf + PARF_PHY_CTRL);
drivers/pci/controller/dwc/pcie-qcom.c
550
writel(val, pcie->parf + PARF_PHY_REFCLK);
drivers/pci/controller/dwc/pcie-qcom.c
556
writel(CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K,
drivers/pci/controller/dwc/pcie-qcom.c
558
writel(CFG_BRIDGE_SB_INIT,
drivers/pci/controller/dwc/pcie-qcom.c
638
writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT);
drivers/pci/controller/dwc/pcie-qcom.c
653
writel(val, pcie->parf + PARF_LTSSM);
drivers/pci/controller/dwc/pcie-qcom.c
717
writel(val, pcie->parf + PARF_PHY_CTRL);
drivers/pci/controller/dwc/pcie-qcom.c
724
writel(val, pcie->parf + PARF_SYS_CTRL);
drivers/pci/controller/dwc/pcie-qcom.c
728
writel(val, pcie->parf + PARF_MHI_CLOCK_RESET_CTRL);
drivers/pci/controller/dwc/pcie-qcom.c
732
writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2);
drivers/pci/controller/dwc/pcie-qcom.c
903
writel(val, pcie->parf + PARF_PHY_CTRL);
drivers/pci/controller/dwc/pcie-qcom.c
907
writel(MST_WAKEUP_EN | SLV_WAKEUP_EN | MSTR_ACLK_CGC_DIS
drivers/pci/controller/dwc/pcie-qcom.c
911
writel(0, pcie->parf + PARF_Q2A_FLUSH);
drivers/pci/controller/dwc/pcie-qcom.c
913
writel(PCI_COMMAND_MASTER, pci->dbi_base + PCI_COMMAND);
drivers/pci/controller/dwc/pcie-qcom.c
917
writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP);
drivers/pci/controller/dwc/pcie-qcom.c
921
writel(val, pci->dbi_base + offset + PCI_EXP_LNKCAP);
drivers/pci/controller/dwc/pcie-qcom.c
923
writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + offset +
drivers/pci/controller/dwc/pcie-qcom.c
994
writel(DEVICE_TYPE_RC, pcie->parf + PARF_DEVICE_TYPE);
drivers/pci/controller/dwc/pcie-qcom.c
999
writel(val, pcie->parf + PARF_PHY_CTRL);
drivers/pci/controller/dwc/pcie-rcar-gen4.c
210
writel(val, rcar->base + PCIEMSR0);
drivers/pci/controller/dwc/pcie-rcar-gen4.c
334
writel(val, rcar->base + PCIEINTSTS0EN);
drivers/pci/controller/dwc/pcie-rcar-gen4.c
386
writel(PCIEDMAINTSTSEN_INIT, rcar->base + PCIEDMAINTSTSEN);
drivers/pci/controller/dwc/pcie-rcar-gen4.c
400
writel(0, rcar->base + PCIEDMAINTSTSEN);
drivers/pci/controller/dwc/pcie-rcar-gen4.c
579
writel(val, rcar->base + PCIERSTCTRL1);
drivers/pci/controller/dwc/pcie-rcar-gen4.c
597
writel(val, rcar->base + PCIEPWRMNGCTRL);
drivers/pci/controller/dwc/pcie-rcar-gen4.c
608
writel(tmp, rcar->phy_base + offset);
drivers/pci/controller/dwc/pcie-rcar-gen4.c
699
writel(val, rcar->base + PCIERSTCTRL1);
drivers/pci/controller/dwc/pcie-rcar-gen4.c
710
writel(val, rcar->base + PCIEMSR0);
drivers/pci/controller/dwc/pcie-rcar-gen4.c
733
writel(val, rcar->base + PCIERSTCTRL1);
drivers/pci/controller/dwc/pcie-rcar-gen4.c
745
writel(val, rcar->base + PCIERSTCTRL1);
drivers/pci/controller/dwc/pcie-spear13xx.c
109
writel(readl(&app_reg->int_mask) |
drivers/pci/controller/dwc/pcie-spear13xx.c
75
writel(DEVICE_TYPE_RC | (1 << MISCTRL_EN_ID)
drivers/pci/controller/dwc/pcie-spear13xx.c
98
writel(status, &app_reg->int_clr);
drivers/pci/controller/dwc/pcie-tegra194-acpi.c
45
writel(val, pcie_ecam->iatu_base + offset + reg);
drivers/pci/controller/dwc/pcie-tegra194.c
1599
writel(data, pcie->appl_base + APPL_CTRL);
drivers/pci/controller/dwc/pcie-tegra194.c
1961
writel(irq, ep->msi_mem);
drivers/pci/controller/dwc/pcie-uniphier-ep.c
100
writel(val, priv->base + PCL_APP_READY_CTRL);
drivers/pci/controller/dwc/pcie-uniphier-ep.c
113
writel(val, priv->base + PCL_RSTCTRL2);
drivers/pci/controller/dwc/pcie-uniphier-ep.c
123
writel(val, priv->base + PCL_MODE);
drivers/pci/controller/dwc/pcie-uniphier-ep.c
128
writel(val, priv->base + PCL_APP_CLK_CTRL);
drivers/pci/controller/dwc/pcie-uniphier-ep.c
134
writel(val, priv->base + PCL_RSTCTRL0);
drivers/pci/controller/dwc/pcie-uniphier-ep.c
148
writel(val, priv->base + PCL_MODE);
drivers/pci/controller/dwc/pcie-uniphier-ep.c
153
writel(val, priv->base + PCL_APP_PM0);
drivers/pci/controller/dwc/pcie-uniphier-ep.c
161
writel(val, priv->base + PCL_PINCTRL0);
drivers/pci/controller/dwc/pcie-uniphier-ep.c
170
writel(val, priv->base + PCL_PINCTRL0);
drivers/pci/controller/dwc/pcie-uniphier-ep.c
229
writel(val, priv->base + PCL_APP_INTX);
drivers/pci/controller/dwc/pcie-uniphier-ep.c
235
writel(val, priv->base + PCL_APP_INTX);
drivers/pci/controller/dwc/pcie-uniphier-ep.c
249
writel(val, priv->base + PCL_APP_MSI0);
drivers/pci/controller/dwc/pcie-uniphier-ep.c
253
writel(val, priv->base + PCL_APP_MSI1);
drivers/pci/controller/dwc/pcie-uniphier.c
101
writel(val, pcie->base + PCL_APP_PM0);
drivers/pci/controller/dwc/pcie-uniphier.c
109
writel(val, pcie->base + PCL_PINCTRL0);
drivers/pci/controller/dwc/pcie-uniphier.c
118
writel(val, pcie->base + PCL_PINCTRL0);
drivers/pci/controller/dwc/pcie-uniphier.c
167
writel(PCL_RCV_INT_ALL_ENABLE, pcie->base + PCL_RCV_INT);
drivers/pci/controller/dwc/pcie-uniphier.c
168
writel(PCL_RCV_INTX_ALL_ENABLE, pcie->base + PCL_RCV_INTX);
drivers/pci/controller/dwc/pcie-uniphier.c
184
writel(val, pcie->base + PCL_RCV_INTX);
drivers/pci/controller/dwc/pcie-uniphier.c
201
writel(val, pcie->base + PCL_RCV_INTX);
drivers/pci/controller/dwc/pcie-uniphier.c
247
writel(val, pcie->base + PCL_RCV_INT);
drivers/pci/controller/dwc/pcie-uniphier.c
85
writel(val, pcie->base + PCL_APP_READY_CTRL);
drivers/pci/controller/dwc/pcie-uniphier.c
96
writel(val, pcie->base + PCL_MODE);
drivers/pci/controller/mobiveil/pcie-mobiveil.c
36
writel(val, pcie->csr_axi_slave_base + PAB_CTRL);
drivers/pci/controller/mobiveil/pcie-mobiveil.c
84
writel(val, addr);
drivers/pci/controller/pci-aardvark.c
294
writel(val, pcie->base + reg);
drivers/pci/controller/pci-ftpci100.c
185
writel(PCI_CONF1_ADDRESS(bus_number, PCI_SLOT(fn),
drivers/pci/controller/pci-ftpci100.c
217
writel(PCI_CONF1_ADDRESS(bus_number, PCI_SLOT(fn),
drivers/pci/controller/pci-ftpci100.c
223
writel(value, p->base + FTPCI_DATA);
drivers/pci/controller/pci-ftpci100.c
448
writel(val, p->base + FTPCI_IOSIZE);
drivers/pci/controller/pci-ftpci100.c
460
writel(val, p->base + FTPCI_CTRL);
drivers/pci/controller/pci-hyperv.c
1221
writel(hpdev->desc.win_slot.slot, hbus->cfg_addr);
drivers/pci/controller/pci-hyperv.c
1270
writel(hpdev->desc.win_slot.slot, hbus->cfg_addr);
drivers/pci/controller/pci-hyperv.c
1317
writel(hpdev->desc.win_slot.slot, hbus->cfg_addr);
drivers/pci/controller/pci-hyperv.c
1329
writel(val, addr);
drivers/pci/controller/pci-mvebu.c
130
writel(val, port->base + reg);
drivers/pci/controller/pci-mvebu.c
411
writel(val, conf_data);
drivers/pci/controller/pci-tegra.c
2198
writel(value, port->base + RP_PRIV_MISC);
drivers/pci/controller/pci-tegra.c
2252
writel(value, port->base + RP_LINK_CONTROL_STATUS_2);
drivers/pci/controller/pci-tegra.c
2275
writel(value, port->base + RP_LINK_CONTROL_STATUS);
drivers/pci/controller/pci-tegra.c
380
writel(value, pcie->afi + offset);
drivers/pci/controller/pci-tegra.c
391
writel(value, pcie->pads + offset);
drivers/pci/controller/pci-tegra.c
542
writel(value, port->base + RP_VEND_CTL1);
drivers/pci/controller/pci-tegra.c
548
writel(value, port->base + RP_VEND_XP);
drivers/pci/controller/pci-tegra.c
556
writel(value, port->base + RP_VEND_XP_BIST);
drivers/pci/controller/pci-tegra.c
569
writel(value, port->base + RP_PRIV_MISC);
drivers/pci/controller/pci-tegra.c
580
writel(value, port->base + RP_ECTL_2_R1);
drivers/pci/controller/pci-tegra.c
586
writel(value, port->base + RP_ECTL_4_R1);
drivers/pci/controller/pci-tegra.c
591
writel(value, port->base + RP_ECTL_5_R1);
drivers/pci/controller/pci-tegra.c
596
writel(value, port->base + RP_ECTL_6_R1);
drivers/pci/controller/pci-tegra.c
601
writel(value, port->base + RP_ECTL_2_R2);
drivers/pci/controller/pci-tegra.c
607
writel(value, port->base + RP_ECTL_4_R2);
drivers/pci/controller/pci-tegra.c
612
writel(value, port->base + RP_ECTL_5_R2);
drivers/pci/controller/pci-tegra.c
617
writel(value, port->base + RP_ECTL_6_R2);
drivers/pci/controller/pci-tegra.c
634
writel(value, port->base + RP_VEND_CTL0);
drivers/pci/controller/pci-tegra.c
641
writel(value, port->base + RP_VEND_XP);
drivers/pci/controller/pci-tegra.c
653
writel(value, port->base + RP_LINK_CONTROL_STATUS_2);
drivers/pci/controller/pci-tegra.c
678
writel(value, port->base + RP_VEND_CTL2);
drivers/pci/controller/pci-thunder-ecam.c
64
writel(0xffffffff, addr + 0);
drivers/pci/controller/pci-thunder-ecam.c
66
writel(barl_orig, addr + 0);
drivers/pci/controller/pci-v3-semi.c
365
writel(v3_addr_to_lb_base(v3->non_pre_mem) |
drivers/pci/controller/pci-v3-semi.c
373
writel(v3_addr_to_lb_base(v3->config_mem) |
drivers/pci/controller/pci-v3-semi.c
386
writel(v3_addr_to_lb_base(v3->pre_mem) |
drivers/pci/controller/pci-v3-semi.c
397
writel(v3_addr_to_lb_base(v3->non_pre_mem) |
drivers/pci/controller/pci-v3-semi.c
502
writel(0x6200, v3->base + V3_LB_IO_BASE);
drivers/pci/controller/pci-v3-semi.c
530
writel(v3_addr_to_lb_base2(pci_pio_to_address(io->start)) |
drivers/pci/controller/pci-v3-semi.c
555
writel(v3_addr_to_lb_base(v3->pre_mem) |
drivers/pci/controller/pci-v3-semi.c
575
writel(v3_addr_to_lb_base(v3->non_pre_mem) |
drivers/pci/controller/pci-v3-semi.c
690
writel(pci_base, v3->base + V3_PCI_BASE0);
drivers/pci/controller/pci-v3-semi.c
691
writel(pci_map, v3->base + V3_PCI_MAP0);
drivers/pci/controller/pci-v3-semi.c
693
writel(pci_base, v3->base + V3_PCI_BASE1);
drivers/pci/controller/pci-v3-semi.c
694
writel(pci_map, v3->base + V3_PCI_MAP1);
drivers/pci/controller/pci-v3-semi.c
826
writel(0x00000000, v3->base + V3_PCI_IO_BASE);
drivers/pci/controller/pci-versatile.c
121
writel(myslot, PCI_SELFID);
drivers/pci/controller/pci-versatile.c
126
writel(val, local_pci_cfg_base + PCI_COMMAND);
drivers/pci/controller/pci-versatile.c
131
writel(__pa(PAGE_OFFSET), local_pci_cfg_base + PCI_BASE_ADDRESS_0);
drivers/pci/controller/pci-versatile.c
132
writel(__pa(PAGE_OFFSET), local_pci_cfg_base + PCI_BASE_ADDRESS_1);
drivers/pci/controller/pci-versatile.c
133
writel(__pa(PAGE_OFFSET), local_pci_cfg_base + PCI_BASE_ADDRESS_2);
drivers/pci/controller/pci-versatile.c
146
writel(0, versatile_cfg_base[0] + PCI_INTERRUPT_LINE);
drivers/pci/controller/pci-versatile.c
93
writel(entry->res->start >> 28, PCI_IMAP(mem));
drivers/pci/controller/pci-versatile.c
94
writel(__pa(PAGE_OFFSET) >> 28, PCI_SMAP(mem));
drivers/pci/controller/pci-xgene.c
506
writel(bar_low, bar_addr);
drivers/pci/controller/pci-xgene.c
507
writel(upper_32_bits(cpu_addr), bar_addr + 0x4);
drivers/pci/controller/pci-xgene.c
78
writel(val, port->csr_base + reg);
drivers/pci/controller/pcie-altera.c
1031
writel(CFG_AER,
drivers/pci/controller/pcie-altera.c
470
writel(value, addr);
drivers/pci/controller/pcie-altera.c
842
writel(CFG_AER, (pcie->hip_base + pcie->pcie_data->port_conf_offset +
drivers/pci/controller/pcie-aspeed.c
238
writel(en, pcie->reg + intx_en);
drivers/pci/controller/pcie-aspeed.c
249
writel(en, pcie->reg + intx_en);
drivers/pci/controller/pcie-aspeed.c
260
writel(en, pcie->reg + intx_en);
drivers/pci/controller/pcie-aspeed.c
302
writel(status, pcie->reg + msi_sts_reg);
drivers/pci/controller/pcie-aspeed.c
309
writel(status, pcie->reg + msi_sts_reg);
drivers/pci/controller/pcie-aspeed.c
339
writel(ASPEED_PCIE_UNLOCK_RX_BUFF | cfg_val,
drivers/pci/controller/pcie-aspeed.c
343
writel(cfg_val, pcie->reg + ASPEED_H2X_TX_DESC0);
drivers/pci/controller/pcie-aspeed.c
348
writel(cfg_val, pcie->reg + ASPEED_H2X_TX_DESC1);
drivers/pci/controller/pcie-aspeed.c
350
writel(bdf_offset, pcie->reg + ASPEED_H2X_TX_DESC2);
drivers/pci/controller/pcie-aspeed.c
351
writel(0, pcie->reg + ASPEED_H2X_TX_DESC3);
drivers/pci/controller/pcie-aspeed.c
353
writel(TLP_SET_VALUE(*val, size, where),
drivers/pci/controller/pcie-aspeed.c
358
writel(cfg_val, pcie->reg + ASPEED_H2X_STS);
drivers/pci/controller/pcie-aspeed.c
373
writel(cfg_val, pcie->reg + ASPEED_H2X_INT_STS);
drivers/pci/controller/pcie-aspeed.c
413
writel(cfg_val, pcie->reg + ASPEED_H2X_DEV_CTRL);
drivers/pci/controller/pcie-aspeed.c
420
writel(cfg_val, pcie->reg + ASPEED_H2X_DEV_STS);
drivers/pci/controller/pcie-aspeed.c
475
writel(cfg_val, pcie->reg + ASPEED_H2X_CFGI_TLP);
drivers/pci/controller/pcie-aspeed.c
477
writel(TLP_SET_VALUE(*val, size, where),
drivers/pci/controller/pcie-aspeed.c
479
writel(ASPEED_CFGI_TLP_FIRE, pcie->reg + ASPEED_H2X_CFGI_CTRL);
drivers/pci/controller/pcie-aspeed.c
505
writel(cfg_val, pcie->reg + ASPEED_H2X_CFGE_TLP_1ST);
drivers/pci/controller/pcie-aspeed.c
510
writel(cfg_val, pcie->reg + ASPEED_H2X_CFGE_TLP_NEXT);
drivers/pci/controller/pcie-aspeed.c
512
writel(bdf_offset, pcie->reg + ASPEED_H2X_CFGE_TLP_NEXT);
drivers/pci/controller/pcie-aspeed.c
514
writel(TLP_SET_VALUE(*val, size, where),
drivers/pci/controller/pcie-aspeed.c
516
writel(ASPEED_CFGE_TX_IDLE | ASPEED_CFGE_RX_BUSY,
drivers/pci/controller/pcie-aspeed.c
518
writel(ASPEED_CFGE_TLP_FIRE, pcie->reg + ASPEED_H2X_CFGE_CTRL);
drivers/pci/controller/pcie-aspeed.c
546
writel(status, pcie->reg + ASPEED_H2X_CFGE_INT_STS);
drivers/pci/controller/pcie-aspeed.c
684
writel(~0, pcie->reg + pcie->platform->reg_msi_en);
drivers/pci/controller/pcie-aspeed.c
685
writel(~0, pcie->reg + pcie->platform->reg_msi_en + 0x04);
drivers/pci/controller/pcie-aspeed.c
686
writel(~0, pcie->reg + pcie->platform->reg_msi_sts);
drivers/pci/controller/pcie-aspeed.c
687
writel(~0, pcie->reg + pcie->platform->reg_msi_sts + 0x04);
drivers/pci/controller/pcie-aspeed.c
738
writel(0, pcie->reg + pcie->platform->reg_intx_en);
drivers/pci/controller/pcie-aspeed.c
739
writel(~0, pcie->reg + pcie->platform->reg_intx_sts);
drivers/pci/controller/pcie-aspeed.c
812
writel(ASPEED_AHB_REMAP_LO_ADDR(pci_addr_lo) |
drivers/pci/controller/pcie-aspeed.c
815
writel(ASPEED_AHB_REMAP_HI_ADDR(pci_addr_hi),
drivers/pci/controller/pcie-aspeed.c
817
writel(ASPEED_AHB_MASK_HI_ADDR(~0),
drivers/pci/controller/pcie-aspeed.c
839
writel(ASPEED_H2X_BRIDGE_EN, pcie->reg + ASPEED_H2X_CTRL);
drivers/pci/controller/pcie-aspeed.c
841
writel(ASPEED_PCIE_RX_DMA_EN | ASPEED_PCIE_RX_LINEAR |
drivers/pci/controller/pcie-aspeed.c
847
writel(ASPEED_RC_TLP_TX_TAG_NUM, pcie->reg + ASPEED_H2X_DEV_TX_TAG);
drivers/pci/controller/pcie-aspeed.c
858
writel(ASPEED_REMAP_PCI_ADDR_31_12(pci_addr),
drivers/pci/controller/pcie-aspeed.c
860
writel(ASPEED_REMAP_PCI_ADDR_63_32(pci_addr),
drivers/pci/controller/pcie-aspeed.c
891
writel(0, pcie->reg + ASPEED_H2X_CTRL);
drivers/pci/controller/pcie-aspeed.c
892
writel(ASPEED_H2X_BRIDGE_EN | ASPEED_H2X_BRIDGE_DIRECT_EN,
drivers/pci/controller/pcie-aspeed.c
896
writel(ASPEED_REMAP_PREF_ADDR_63_32(0x3),
drivers/pci/controller/pcie-brcmstb.c
1168
writel(tmp, base + HARD_DEBUG(pcie));
drivers/pci/controller/pcie-brcmstb.c
1196
writel(tmp, base + PCIE_MISC_MISC_CTRL);
drivers/pci/controller/pcie-brcmstb.c
1220
writel(tmp, base + PCIE_MISC_MISC_CTRL);
drivers/pci/controller/pcie-brcmstb.c
1240
writel(tmp, base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY);
drivers/pci/controller/pcie-brcmstb.c
1256
writel(tmp, base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY);
drivers/pci/controller/pcie-brcmstb.c
1260
writel(tmp, base + PCIE_RC_PL_REG_PHY_CTL_1);
drivers/pci/controller/pcie-brcmstb.c
1270
writel(tmp, base + PCIE_RC_CFG_PRIV1_ID_VAL3);
drivers/pci/controller/pcie-brcmstb.c
1307
writel(tmp, base + PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1);
drivers/pci/controller/pcie-brcmstb.c
1334
writel(216 * timeout_us, pcie->base + REG_OFFSET);
drivers/pci/controller/pcie-brcmstb.c
1371
writel(tmp, pcie->base + PCIE_RC_CFG_PRIV1_ROOT_CAP);
drivers/pci/controller/pcie-brcmstb.c
1394
writel(clkreq_cntl, pcie->base + HARD_DEBUG(pcie));
drivers/pci/controller/pcie-brcmstb.c
1538
writel(tmp, base + PCIE_MISC_PCIE_CTRL);
drivers/pci/controller/pcie-brcmstb.c
1575
writel(tmp, base + PCIE_DVT_PMU_PCIE_PHY_CTRL);
drivers/pci/controller/pcie-brcmstb.c
1615
writel(tmp, base + PCIE_MISC_PCIE_CTRL);
drivers/pci/controller/pcie-brcmstb.c
1620
writel(tmp, base + HARD_DEBUG(pcie));
drivers/pci/controller/pcie-brcmstb.c
1719
writel(tmp, base + HARD_DEBUG(pcie));
drivers/pci/controller/pcie-brcmstb.c
1801
writel(1, base + PCIE_OUTB_ERR_CLEAR);
drivers/pci/controller/pcie-brcmstb.c
408
writel(brcm_pcie_mdio_form_pkt(port, regad, MDIO_CMD_READ),
drivers/pci/controller/pcie-brcmstb.c
425
writel(brcm_pcie_mdio_form_pkt(port, regad, MDIO_CMD_WRITE),
drivers/pci/controller/pcie-brcmstb.c
428
writel(MDIO_DATA_DONE_MASK | wrdata, base + PCIE_RC_DL_MDIO_WR_DATA);
drivers/pci/controller/pcie-brcmstb.c
481
writel(lnkcap, pcie->base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY);
drivers/pci/controller/pcie-brcmstb.c
497
writel(lower_32_bits(pcie_addr), pcie->base + PCIE_MEM_WIN0_LO(win));
drivers/pci/controller/pcie-brcmstb.c
498
writel(upper_32_bits(pcie_addr), pcie->base + PCIE_MEM_WIN0_HI(win));
drivers/pci/controller/pcie-brcmstb.c
509
writel(tmp, pcie->base + PCIE_MEM_WIN0_BASE_LIMIT(win));
drivers/pci/controller/pcie-brcmstb.c
522
writel(tmp, pcie->base + PCIE_MEM_WIN0_BASE_HI(win));
drivers/pci/controller/pcie-brcmstb.c
528
writel(tmp, pcie->base + PCIE_MEM_WIN0_LIMIT_HI(win));
drivers/pci/controller/pcie-brcmstb.c
586
writel(1 << shift_amt, msi->intr_base + MSI_INT_CLR);
drivers/pci/controller/pcie-brcmstb.c
688
writel(val, msi->intr_base + MSI_INT_MASK_CLR);
drivers/pci/controller/pcie-brcmstb.c
689
writel(val, msi->intr_base + MSI_INT_CLR);
drivers/pci/controller/pcie-brcmstb.c
695
writel(lower_32_bits(msi->target_addr) | 0x1,
drivers/pci/controller/pcie-brcmstb.c
697
writel(upper_32_bits(msi->target_addr),
drivers/pci/controller/pcie-brcmstb.c
701
writel(val, msi->base + PCIE_MISC_MSI_DATA_CONFIG);
drivers/pci/controller/pcie-brcmstb.c
791
writel(idx, base + IDX_ADDR(pcie));
drivers/pci/controller/pcie-brcmstb.c
812
writel(idx, base + IDX_ADDR(pcie));
drivers/pci/controller/pcie-brcmstb.c
837
writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
drivers/pci/controller/pcie-brcmstb.c
849
writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
drivers/pci/controller/pcie-brcmstb.c
879
writel(tmp, pcie->base + PCIE_MISC_PCIE_CTRL);
drivers/pci/controller/pcie-brcmstb.c
890
writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
drivers/pci/controller/pcie-brcmstb.c
923
writel(tmp, pcie->base + PCIE_RC_PL_PHY_CTL_15);
drivers/pci/controller/pcie-iproc.c
1081
writel(lower_32_bits(pci_addr) | BIT(size_idx),
drivers/pci/controller/pcie-iproc.c
1083
writel(upper_32_bits(pci_addr), pcie->base + iarr_offset + 4);
drivers/pci/controller/pcie-iproc.c
1097
writel(val, pcie->base + imap_offset);
drivers/pci/controller/pcie-iproc.c
1098
writel(upper_32_bits(axi_addr),
drivers/pci/controller/pcie-iproc.c
435
writel(val, pcie->base + offset);
drivers/pci/controller/pcie-iproc.c
685
writel(val, addr);
drivers/pci/controller/pcie-iproc.c
692
writel(tmp, addr);
drivers/pci/controller/pcie-iproc.c
875
writel(lower_32_bits(axi_addr) | (size_idx << OARR_SIZE_CFG_SHIFT) |
drivers/pci/controller/pcie-iproc.c
877
writel(upper_32_bits(axi_addr), pcie->base + oarr_offset + 4);
drivers/pci/controller/pcie-iproc.c
880
writel(lower_32_bits(pci_addr), pcie->base + omap_offset);
drivers/pci/controller/pcie-iproc.c
881
writel(upper_32_bits(pci_addr), pcie->base + omap_offset + 4);
drivers/pci/controller/pcie-mediatek.c
298
writel(CFG_HEADER_DW0(CFG_WRRD_TYPE_0, CFG_RD_FMT),
drivers/pci/controller/pcie-mediatek.c
300
writel(CFG_HEADER_DW1(where, size), port->base + PCIE_CFG_HEADER1);
drivers/pci/controller/pcie-mediatek.c
301
writel(CFG_HEADER_DW2(where, PCI_FUNC(devfn), PCI_SLOT(devfn), bus),
drivers/pci/controller/pcie-mediatek.c
307
writel(tmp, port->base + PCIE_APP_TLP_REQ);
drivers/pci/controller/pcie-mediatek.c
328
writel(CFG_HEADER_DW0(CFG_WRRD_TYPE_0, CFG_WR_FMT),
drivers/pci/controller/pcie-mediatek.c
330
writel(CFG_HEADER_DW1(where, size), port->base + PCIE_CFG_HEADER1);
drivers/pci/controller/pcie-mediatek.c
331
writel(CFG_HEADER_DW2(where, PCI_FUNC(devfn), PCI_SLOT(devfn), bus),
drivers/pci/controller/pcie-mediatek.c
336
writel(val, port->base + PCIE_CFG_WDATA);
drivers/pci/controller/pcie-mediatek.c
341
writel(val, port->base + PCIE_APP_TLP_REQ);
drivers/pci/controller/pcie-mediatek.c
423
writel(1 << hwirq, port->base + PCIE_IMSI_STATUS);
drivers/pci/controller/pcie-mediatek.c
525
writel(val, port->base + PCIE_IMSI_ADDR);
drivers/pci/controller/pcie-mediatek.c
529
writel(val, port->base + PCIE_INT_MASK);
drivers/pci/controller/pcie-mediatek.c
610
writel(1 << bit, port->base + PCIE_INT_STATUS);
drivers/pci/controller/pcie-mediatek.c
627
writel(MSI_STATUS, port->base + PCIE_INT_STATUS);
drivers/pci/controller/pcie-mediatek.c
687
writel(val, pcie->base + PCIE_SYS_CFG_V2);
drivers/pci/controller/pcie-mediatek.c
696
writel(0, port->base + PCIE_RST_CTRL);
drivers/pci/controller/pcie-mediatek.c
703
writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL);
drivers/pci/controller/pcie-mediatek.c
711
writel(val, port->base + PCIE_RST_CTRL);
drivers/pci/controller/pcie-mediatek.c
736
writel(val, port->base + PCIE_INT_MASK);
drivers/pci/controller/pcie-mediatek.c
744
writel(val, port->base + PCIE_AHB_TRANS_BASE0_L);
drivers/pci/controller/pcie-mediatek.c
747
writel(val, port->base + PCIE_AHB_TRANS_BASE0_H);
drivers/pci/controller/pcie-mediatek.c
751
writel(val, port->base + PCIE_AXI_WINDOW0);
drivers/pci/controller/pcie-mediatek.c
761
writel(PCIE_CONF_ADDR(where, PCI_FUNC(devfn), PCI_SLOT(devfn),
drivers/pci/controller/pcie-mediatek.c
784
writel(val, pcie->base + PCIE_SYS_CFG);
drivers/pci/controller/pcie-mediatek.c
789
writel(val, pcie->base + PCIE_SYS_CFG);
drivers/pci/controller/pcie-mediatek.c
801
writel(val, pcie->base + PCIE_INT_ENABLE);
drivers/pci/controller/pcie-mediatek.c
804
writel(PCIE_BAR_MAP_MAX | PCIE_BAR_ENABLE,
drivers/pci/controller/pcie-mediatek.c
808
writel(PCIE_CLASS_CODE | PCIE_REVISION_ID, port->base + PCIE_CLASS);
drivers/pci/controller/pcie-mediatek.c
811
writel(PCIE_CONF_ADDR(PCIE_FC_CREDIT, func, slot, 0),
drivers/pci/controller/pcie-mediatek.c
816
writel(PCIE_CONF_ADDR(PCIE_FC_CREDIT, func, slot, 0),
drivers/pci/controller/pcie-mediatek.c
818
writel(val, pcie->base + PCIE_CFG_DATA);
drivers/pci/controller/pcie-mediatek.c
821
writel(PCIE_CONF_ADDR(PCIE_FTS_NUM, func, slot, 0),
drivers/pci/controller/pcie-mediatek.c
826
writel(PCIE_CONF_ADDR(PCIE_FTS_NUM, func, slot, 0),
drivers/pci/controller/pcie-mediatek.c
828
writel(val, pcie->base + PCIE_CFG_DATA);
drivers/pci/controller/pcie-rcar-host.c
73
writel(L1IATN, pcie_base + PMCTLR);
drivers/pci/controller/pcie-rcar-host.c
81
writel(L1FAEG | PMEL1RX, pcie_base + PMSR);
drivers/pci/controller/pcie-rcar.c
16
writel(val, pcie->base + reg);
drivers/pci/controller/pcie-rockchip-host.c
127
writel(val, addr);
drivers/pci/controller/pcie-rockchip-host.c
140
writel(tmp, addr);
drivers/pci/controller/pcie-rockchip-host.c
197
writel(val, addr);
drivers/pci/controller/pcie-rockchip-host.c
849
writel(0x0, rockchip->msg_region + PCIE_RC_SEND_PME_OFF);
drivers/pci/controller/pcie-rockchip.h
341
writel(val, rockchip->apb_base + reg);
drivers/pci/controller/pcie-xilinx-cpm.c
501
writel(variant->ir_misc_value,
drivers/pci/controller/pcie-xilinx-cpm.c
505
writel(XILINX_CPM_PCIE_IR_LOCAL,
drivers/pci/controller/pcie-xilinx-dma-pl.c
144
writel(val, port->reg_base + reg + QDMA_BRIDGE_BASE_OFF);
drivers/pci/controller/pcie-xilinx-dma-pl.c
146
writel(val, port->reg_base + reg);
drivers/pci/controller/pcie-xilinx-nwl.c
183
writel(val, pcie->breg_base + off);
drivers/pci/controller/pcie-xilinx.c
121
writel(val, pcie->reg_base + reg);
drivers/pci/controller/plda/pcie-microchip-host.c
632
writel(val, table_addr + ATR0_PCIE_WIN0_SRCADDR_PARAM);
drivers/pci/controller/plda/pcie-microchip-host.c
634
writel(upper_32_bits(pcie_addr), table_addr + ATR0_PCIE_WIN0_SRC_ADDR);
drivers/pci/controller/plda/pcie-microchip-host.c
636
writel(lower_32_bits(axi_addr), table_addr + ATR0_PCIE_WIN0_TRSL_ADDR_LSB);
drivers/pci/controller/plda/pcie-microchip-host.c
637
writel(upper_32_bits(axi_addr), table_addr + ATR0_PCIE_WIN0_TRSL_ADDR_UDW);
drivers/pci/controller/plda/pcie-microchip-host.c
639
writel(TRSL_ID_AXI4_MASTER_0, table_addr + ATR0_PCIE_WIN0_TRSL_PARAM);
drivers/pci/controller/plda/pcie-microchip-host.c
782
writel(val, port->bridge_base_addr + PCIE_PCI_IRQ_DW0);
drivers/pci/controller/plda/pcie-plda-host.c
503
writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) +
drivers/pci/controller/plda/pcie-plda-host.c
509
writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) +
drivers/pci/controller/plda/pcie-plda-host.c
513
writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) +
drivers/pci/controller/plda/pcie-plda-host.c
517
writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) +
drivers/pci/controller/plda/pcie-plda-host.c
521
writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) +
drivers/pci/controller/plda/pcie-plda-host.c
533
writel(val, bridge_base_addr + ATR0_PCIE_WIN0_SRCADDR_PARAM);
drivers/pci/controller/plda/pcie-plda-host.c
534
writel(0, bridge_base_addr + ATR0_PCIE_WIN0_SRC_ADDR);
drivers/pci/controller/vmd.c
458
writel(value, addr);
drivers/pci/controller/vmd.c
551
writel(0x0000ffff, base + PCI_IO_BASE_UPPER16);
drivers/pci/controller/vmd.c
555
writel(0, base + PCI_IO_BASE_UPPER16);
drivers/pci/controller/vmd.c
558
writel(0x0000fff0, base + PCI_MEMORY_BASE);
drivers/pci/controller/vmd.c
561
writel(0, base + PCI_PREF_LIMIT_UPPER32);
drivers/pci/controller/vmd.c
562
writel(0x0000fff0, base + PCI_PREF_MEMORY_BASE);
drivers/pci/controller/vmd.c
563
writel(0xffffffff, base + PCI_PREF_BASE_UPPER32);
drivers/pci/endpoint/functions/pci-epf-vntb.c
1341
writel(val, base + off + ct + idx * sizeof(u32));
drivers/pci/endpoint/functions/pci-epf-vntb.c
1364
writel(val, base + off + idx * sizeof(u32));
drivers/pci/hotplug/cpqphp.h
486
writel(led_control, ctrl->hpc_reg + LED_CONTROL);
drivers/pci/hotplug/cpqphp.h
496
writel(led_control, ctrl->hpc_reg + LED_CONTROL);
drivers/pci/hotplug/cpqphp.h
517
writel(led_control, ctrl->hpc_reg + LED_CONTROL);
drivers/pci/hotplug/cpqphp.h
526
writel(led_control, ctrl->hpc_reg + LED_CONTROL);
drivers/pci/hotplug/cpqphp.h
537
writel(led_control, ctrl->hpc_reg + LED_CONTROL);
drivers/pci/hotplug/cpqphp_core.c
1138
writel(0xFFFFFFFFL, ctrl->hpc_reg + INT_MASK);
drivers/pci/hotplug/cpqphp_core.c
1158
writel(0xFFFFFFFFL, ctrl->hpc_reg + INT_INPUT_CLEAR);
drivers/pci/hotplug/cpqphp_core.c
1162
writel(0x0L, ctrl->hpc_reg + INT_MASK);
drivers/pci/hotplug/cpqphp_core.c
1267
writel(0xFFFFFFC0L | ~rc, ctrl->hpc_reg + INT_MASK);
drivers/pci/hotplug/cpqphp_ctrl.c
1163
writel(0x0L, ctrl->hpc_reg + LED_CONTROL);
drivers/pci/hotplug/cpqphp_ctrl.c
1205
writel(0, ctrl->hpc_reg + INT_MASK);
drivers/pci/hotplug/cpqphp_ctrl.c
1223
writel(leds, ctrl->hpc_reg + LED_CONTROL);
drivers/pci/hotplug/cpqphp_ctrl.c
2106
writel(*work_LED, ctrl->hpc_reg + LED_CONTROL);
drivers/pci/hotplug/cpqphp_ctrl.c
2148
writel(work_LED, ctrl->hpc_reg + LED_CONTROL);
drivers/pci/hotplug/cpqphp_ctrl.c
2152
writel(work_LED, ctrl->hpc_reg + LED_CONTROL);
drivers/pci/hotplug/cpqphp_ctrl.c
2157
writel(work_LED, ctrl->hpc_reg + LED_CONTROL);
drivers/pci/hotplug/cpqphp_ctrl.c
2167
writel(work_LED, ctrl->hpc_reg + LED_CONTROL);
drivers/pci/hotplug/cpqphp_ctrl.c
2177
writel(work_LED, ctrl->hpc_reg + LED_CONTROL);
drivers/pci/hotplug/cpqphp_ctrl.c
2179
writel(work_LED, ctrl->hpc_reg + LED_CONTROL);
drivers/pci/hotplug/cpqphp_ctrl.c
2183
writel(save_LED, ctrl->hpc_reg + LED_CONTROL);
drivers/pci/hotplug/cpqphp_ctrl.c
916
writel(Diff, ctrl->hpc_reg + INT_INPUT_CLEAR);
drivers/pci/hotplug/cpqphp_ctrl.c
923
writel(0xFFFFFFFF, ctrl->hpc_reg + INT_INPUT_CLEAR);
drivers/pci/hotplug/ibmphp_hpc.c
156
writel(wpg_data, wpg_addr);
drivers/pci/hotplug/ibmphp_hpc.c
163
writel(wpg_data, wpg_addr);
drivers/pci/hotplug/ibmphp_hpc.c
171
writel(wpg_data, wpg_addr);
drivers/pci/hotplug/ibmphp_hpc.c
267
writel(wpg_data, wpg_addr);
drivers/pci/hotplug/ibmphp_hpc.c
274
writel(wpg_data, wpg_addr);
drivers/pci/hotplug/ibmphp_hpc.c
282
writel(wpg_data, wpg_addr);
drivers/pci/hotplug/shpchp_hpc.c
193
writel(val, ctrl->creg + reg);
drivers/pci/msi/msi.c
228
writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR);
drivers/pci/msi/msi.c
229
writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR);
drivers/pci/msi/msi.c
230
writel(msg->data, base + PCI_MSIX_ENTRY_DATA);
drivers/pci/msi/msi.c
619
writel(0, addr + PCI_MSIX_ENTRY_DATA);
drivers/pci/msi/msi.c
665
writel(ctrl, base + PCI_MSIX_ENTRY_VECTOR_CTRL);
drivers/pci/msi/msi.h
40
writel(ctrl, desc_addr + PCI_MSIX_ENTRY_VECTOR_CTRL);
drivers/pci/quirks.c
1720
writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418);
drivers/pci/quirks.c
3573
writel(0, regs + I915_DEIER_REG);
drivers/pci/quirks.c
4126
writel(cfg, bar + NVME_REG_CC);
drivers/pci/quirks.c
5349
writel(updcr, rcba_mem + INTEL_UPDCR_REG);
drivers/pcmcia/yenta_socket.c
94
writel(val, socket->base + reg);
drivers/peci/controller/peci-aspeed.c
149
writel(val, priv->base + ASPEED_PECI_CTRL);
drivers/peci/controller/peci-aspeed.c
157
writel(ASPEED_PECI_INT_MASK, priv->base + ASPEED_PECI_INT_STS);
drivers/peci/controller/peci-aspeed.c
162
writel(val, priv->base + ASPEED_PECI_INT_CTRL);
drivers/peci/controller/peci-aspeed.c
165
writel(val, priv->base + ASPEED_PECI_CTRL);
drivers/peci/controller/peci-aspeed.c
234
writel(peci_head, priv->base + ASPEED_PECI_RW_LENGTH);
drivers/peci/controller/peci-aspeed.c
239
writel(get_unaligned_le32(&req->tx.buf[i]), priv->base + reg);
drivers/peci/controller/peci-aspeed.c
248
writel(ASPEED_PECI_CMD_FIRE, priv->base + ASPEED_PECI_CMD);
drivers/peci/controller/peci-aspeed.c
296
writel(status, priv->base + ASPEED_PECI_INT_STS);
drivers/peci/controller/peci-aspeed.c
306
writel(0, priv->base + ASPEED_PECI_CMD);
drivers/peci/controller/peci-aspeed.c
356
writel(val, aspeed_peci->base + ASPEED_PECI_CTRL);
drivers/peci/controller/peci-aspeed.c
360
writel(val, aspeed_peci->base + ASPEED_PECI_TIMING_NEGOTIATION);
drivers/perf/alibaba_uncore_drw_pmu.c
322
writel(ALI_DRW_PMU_TEST_SEL_COMMON_COUNTER_BASE + event->hw.idx,
drivers/perf/alibaba_uncore_drw_pmu.c
327
writel(pre_val, drw_pmu->cfg_base + ALI_DRW_PMU_CNT_PRELOAD);
drivers/perf/alibaba_uncore_drw_pmu.c
331
writel(0x0, drw_pmu->cfg_base + ALI_DRW_PMU_TEST_CTRL);
drivers/perf/alibaba_uncore_drw_pmu.c
349
writel(val, drw_pmu->cfg_base + reg);
drivers/perf/alibaba_uncore_drw_pmu.c
367
writel(val, drw_pmu->cfg_base + reg);
drivers/perf/alibaba_uncore_drw_pmu.c
404
writel(clr_status,
drivers/perf/alibaba_uncore_drw_pmu.c
565
writel(ALI_DRW_PMU_CNT_RST, drw_pmu->cfg_base + ALI_DRW_PMU_CNT_CTRL);
drivers/perf/alibaba_uncore_drw_pmu.c
579
writel(ALI_DRW_PMU_CNT_START,
drivers/perf/alibaba_uncore_drw_pmu.c
588
writel(prev_raw_count,
drivers/perf/alibaba_uncore_drw_pmu.c
594
writel(ALI_DRW_PMU_CNT_START, drw_pmu->cfg_base + ALI_DRW_PMU_CNT_CTRL);
drivers/perf/alibaba_uncore_drw_pmu.c
607
writel(ALI_DRW_PMU_CNT_STOP, drw_pmu->cfg_base + ALI_DRW_PMU_CNT_CTRL);
drivers/perf/alibaba_uncore_drw_pmu.c
687
writel(ALI_DRW_PMU_CNT_RST, drw_pmu->cfg_base + ALI_DRW_PMU_CNT_CTRL);
drivers/perf/alibaba_uncore_drw_pmu.c
690
writel(ALI_DRW_PMCOM_CNT_OV_INTR_MASK,
drivers/perf/alibaba_uncore_drw_pmu.c
694
writel(0xffffff, drw_pmu->cfg_base + ALI_DRW_PMU_OV_INTR_CLR);
drivers/perf/alibaba_uncore_drw_pmu.c
730
writel(ALI_DRW_PMCOM_CNT_OV_INTR_MASK,
drivers/perf/amlogic/meson_g12_ddr_pmu.c
204
writel(clock_count, info->ddr_reg[0] + DMC_MON_G12_TIMER);
drivers/perf/amlogic/meson_g12_ddr_pmu.c
213
writel(val, info->ddr_reg[0] + DMC_MON_G12_CTRL0);
drivers/perf/amlogic/meson_g12_ddr_pmu.c
232
writel(0, info->ddr_reg[0] + rp[channel]);
drivers/perf/amlogic/meson_g12_ddr_pmu.c
233
writel(0, info->ddr_reg[0] + rs[channel]);
drivers/perf/amlogic/meson_g12_ddr_pmu.c
243
writel(val, info->ddr_reg[0] + rp[channel]);
drivers/perf/amlogic/meson_g12_ddr_pmu.c
245
writel(val, info->ddr_reg[0] + rs[channel]);
drivers/perf/amlogic/meson_g12_ddr_pmu.c
248
writel(val, info->ddr_reg[0] + rp[channel]);
drivers/perf/amlogic/meson_g12_ddr_pmu.c
251
writel(val, info->ddr_reg[0] + rs[channel]);
drivers/perf/amlogic/meson_g12_ddr_pmu.c
268
writel(0, info->ddr_reg[0] + DMC_MON_G12_CTRL0);
drivers/perf/amlogic/meson_g12_ddr_pmu.c
269
writel(0, info->ddr_reg[0] + DMC_MON_G12_TIMER);
drivers/perf/amlogic/meson_g12_ddr_pmu.c
271
writel(0, info->ddr_reg[0] + DMC_MON_G12_ALL_REQ_CNT);
drivers/perf/amlogic/meson_g12_ddr_pmu.c
272
writel(0, info->ddr_reg[0] + DMC_MON_G12_ALL_GRANT_CNT);
drivers/perf/amlogic/meson_g12_ddr_pmu.c
273
writel(0, info->ddr_reg[0] + DMC_MON_G12_ONE_GRANT_CNT);
drivers/perf/amlogic/meson_g12_ddr_pmu.c
274
writel(0, info->ddr_reg[0] + DMC_MON_G12_SEC_GRANT_CNT);
drivers/perf/amlogic/meson_g12_ddr_pmu.c
275
writel(0, info->ddr_reg[0] + DMC_MON_G12_THD_GRANT_CNT);
drivers/perf/amlogic/meson_g12_ddr_pmu.c
276
writel(0, info->ddr_reg[0] + DMC_MON_G12_FOR_GRANT_CNT);
drivers/perf/amlogic/meson_g12_ddr_pmu.c
308
writel(val, info->ddr_reg[0] + DMC_MON_G12_CTRL0);
drivers/perf/arm-cci.c
669
writel(val, cci_pmu->ctrl_base + CCI_PMCR);
drivers/perf/arm-cci.c
686
writel(val, cci_pmu->ctrl_base + CCI_PMCR);
drivers/perf/arm-ccn.c
1000
writel(val, source->base + CCN_XP_PMU_EVENT_SEL);
drivers/perf/arm-ccn.c
1037
writel(val, source->base + CCN_HNF_PMU_EVENT_SEL);
drivers/perf/arm-ccn.c
1063
writel(val, ccn->dt.base + CCN_DT_ACTIVE_DSM + offset);
drivers/perf/arm-ccn.c
1136
writel(val, ccn->dt.base + CCN_DT_PMCR);
drivers/perf/arm-ccn.c
1145
writel(val, ccn->dt.base + CCN_DT_PMCR);
drivers/perf/arm-ccn.c
1156
writel(pmovsr, dt->base + CCN_DT_PMOVSR_CLR);
drivers/perf/arm-ccn.c
1220
writel(CCN_DT_PMOVSR_CLR__MASK, ccn->dt.base + CCN_DT_PMOVSR_CLR);
drivers/perf/arm-ccn.c
1221
writel(CCN_DT_CTL__DT_EN, ccn->dt.base + CCN_DT_CTL);
drivers/perf/arm-ccn.c
1222
writel(CCN_DT_PMCR__OVFL_INTR_EN | CCN_DT_PMCR__PMU_EN,
drivers/perf/arm-ccn.c
1224
writel(0x1, ccn->dt.base + CCN_DT_PMSR_CLR);
drivers/perf/arm-ccn.c
1226
writel(0, ccn->xp[i].base + CCN_XP_DT_CONFIG);
drivers/perf/arm-ccn.c
1227
writel((CCN_XP_DT_CONTROL__WP_ARM_SEL__ALWAYS <<
drivers/perf/arm-ccn.c
1308
writel(0, ccn->xp[i].base + CCN_XP_DT_CONTROL);
drivers/perf/arm-ccn.c
1309
writel(0, ccn->dt.base + CCN_DT_PMCR);
drivers/perf/arm-ccn.c
1320
writel(0, ccn->xp[i].base + CCN_XP_DT_CONTROL);
drivers/perf/arm-ccn.c
1321
writel(0, ccn->dt.base + CCN_DT_PMCR);
drivers/perf/arm-ccn.c
1412
writel(CCN_MN_ERRINT_STATUS__ALL_ERRORS__DISABLE,
drivers/perf/arm-ccn.c
1444
writel(CCN_MN_ERRINT_STATUS__INTREQ__DESSERT,
drivers/perf/arm-ccn.c
1472
writel(CCN_MN_ERRINT_STATUS__PMU_EVENTS__DISABLE,
drivers/perf/arm-ccn.c
1477
writel(CCN_MN_ERRINT_STATUS__PMU_EVENTS__ENABLE,
drivers/perf/arm-ccn.c
844
writel(0x1, ccn->dt.base + CCN_DT_PMSR_REQ);
drivers/perf/arm-ccn.c
847
writel(0x1, ccn->dt.base + CCN_DT_PMSR_CLR);
drivers/perf/arm-ccn.c
903
writel(val, xp->base + CCN_XP_DT_CONFIG);
drivers/perf/arm-ccn.c
963
writel(val, source->base + CCN_XP_DT_INTERFACE_SEL);
drivers/perf/arm-ccn.c
966
writel(cmp_l & 0xffffffff, source->base + CCN_XP_DT_CMP_VAL_L(wp));
drivers/perf/arm-ccn.c
967
writel((cmp_l >> 32) & 0x7fffffff,
drivers/perf/arm-ccn.c
969
writel(cmp_h & 0xffffffff, source->base + CCN_XP_DT_CMP_VAL_H(wp));
drivers/perf/arm-ccn.c
970
writel((cmp_h >> 32) & 0x0fffffff,
drivers/perf/arm-ccn.c
974
writel(mask_l & 0xffffffff, source->base + CCN_XP_DT_CMP_MASK_L(wp));
drivers/perf/arm-ccn.c
975
writel((mask_l >> 32) & 0x7fffffff,
drivers/perf/arm-ccn.c
977
writel(mask_h & 0xffffffff, source->base + CCN_XP_DT_CMP_MASK_H(wp));
drivers/perf/arm-ccn.c
978
writel((mask_h >> 32) & 0x0fffffff,
drivers/perf/arm_cspmu/ampere_cspmu.c
153
writel(threshold, cspmu->base0 + PMAUXR0);
drivers/perf/arm_cspmu/ampere_cspmu.c
154
writel(rank, cspmu->base0 + PMAUXR1);
drivers/perf/arm_cspmu/ampere_cspmu.c
155
writel(bank, cspmu->base0 + PMAUXR2);
drivers/perf/arm_cspmu/arm_cspmu.c
1014
writel(pmovs[i], cspmu->base1 + pmovclr_offset);
drivers/perf/arm_cspmu/arm_cspmu.c
516
writel(PMCR_C | PMCR_P, cspmu->base0 + PMCR);
drivers/perf/arm_cspmu/arm_cspmu.c
521
writel(PMCR_E, cspmu->base0 + PMCR);
drivers/perf/arm_cspmu/arm_cspmu.c
526
writel(0, cspmu->base0 + PMCR);
drivers/perf/arm_cspmu/arm_cspmu.c
716
writel(lower_32_bits(val), cspmu->base1 + offset);
drivers/perf/arm_cspmu/arm_cspmu.c
764
writel(BIT(reg_bit), cspmu->base0 + inten_off);
drivers/perf/arm_cspmu/arm_cspmu.c
765
writel(BIT(reg_bit), cspmu->base0 + cnten_off);
drivers/perf/arm_cspmu/arm_cspmu.c
778
writel(BIT(reg_bit), cspmu->base0 + cnten_off);
drivers/perf/arm_cspmu/arm_cspmu.c
779
writel(BIT(reg_bit), cspmu->base0 + inten_off);
drivers/perf/arm_cspmu/arm_cspmu.c
802
writel(hwc->config, cspmu->base0 + offset);
drivers/perf/arm_cspmu/arm_cspmu.c
812
writel(filter, cspmu->base0 + PMEVFILTR + offset);
drivers/perf/arm_cspmu/arm_cspmu.c
813
writel(filter2, cspmu->base0 + PMEVFILT2R + offset);
drivers/perf/arm_cspmu/arm_cspmu.c
821
writel(filter, cspmu->base0 + PMCCFILTR);
drivers/perf/arm_cspmu/nvidia_cspmu.c
222
writel(filter, cspmu->base0 + PMEVFILTR + offset);
drivers/perf/arm_cspmu/nvidia_cspmu.c
227
writel(filter, cspmu->base0 + PMEVFILT2R + offset);
drivers/perf/arm_cspmu/nvidia_cspmu.c
236
writel(filter, cspmu->base0 + PMCCFILTR);
drivers/perf/arm_dmc620_pmu.c
274
writel(val, dmc620_pmu->base + DMC620_PMU_COUNTERn_OFFSET(idx) + reg);
drivers/perf/arm_dmc620_pmu.c
404
writel(0, dmc620_pmu->base + DMC620_PMU_OVERFLOW_STATUS_CLKDIV2);
drivers/perf/arm_dmc620_pmu.c
408
writel(0, dmc620_pmu->base + DMC620_PMU_OVERFLOW_STATUS_CLK);
drivers/perf/arm_dmc620_pmu.c
698
writel(0, dmc620_pmu->base + DMC620_PMU_OVERFLOW_STATUS_CLKDIV2);
drivers/perf/arm_dmc620_pmu.c
699
writel(0, dmc620_pmu->base + DMC620_PMU_OVERFLOW_STATUS_CLK);
drivers/perf/arm_smmuv3_pmu.c
158
writel(SMMU_PMCG_IRQ_CTRL_IRQEN,
drivers/perf/arm_smmuv3_pmu.c
160
writel(SMMU_PMCG_CR_ENABLE, smmu_pmu->reg_base + SMMU_PMCG_CR);
drivers/perf/arm_smmuv3_pmu.c
181
writel(0, smmu_pmu->reg_base + SMMU_PMCG_CR);
drivers/perf/arm_smmuv3_pmu.c
182
writel(0, smmu_pmu->reg_base + SMMU_PMCG_IRQ_CTRL);
drivers/perf/arm_smmuv3_pmu.c
196
writel(0xffff, smmu_pmu->reg_base + SMMU_PMCG_EVTYPER(idx));
drivers/perf/arm_smmuv3_pmu.c
207
writel(value, smmu_pmu->reloc_base + SMMU_PMCG_EVCNTR(idx, 4));
drivers/perf/arm_smmuv3_pmu.c
246
writel(val, smmu_pmu->reg_base + SMMU_PMCG_EVTYPER(idx));
drivers/perf/arm_smmuv3_pmu.c
251
writel(val, smmu_pmu->reg_base + SMMU_PMCG_SMR(idx));
drivers/perf/fsl_imx8_ddr_perf.c
500
writel(0, pmu->base + reg);
drivers/perf/fsl_imx8_ddr_perf.c
514
writel(val, pmu->base + reg);
drivers/perf/fsl_imx8_ddr_perf.c
518
writel(val, pmu->base + reg);
drivers/perf/fsl_imx8_ddr_perf.c
538
writel(val, pmu->base + reg);
drivers/perf/fsl_imx8_ddr_perf.c
541
writel(val, pmu->base + reg);
drivers/perf/fsl_imx8_ddr_perf.c
616
writel(cfg1, pmu->base + COUNTER_DPCR1);
drivers/perf/fsl_imx8_ddr_perf.c
630
writel(cfg1, pmu->base + COUNTER_MASK_COMP + ((counter - 1) << 4));
drivers/perf/fsl_imx8_ddr_perf.c
642
writel(cfg2, pmu->base + COUNTER_MUX_CNTL + ((counter - 1) << 4));
drivers/perf/fsl_imx9_ddr_perf.c
374
writel(0, pmu->base + PMC(counter) + 0x4);
drivers/perf/fsl_imx9_ddr_perf.c
375
writel(0, pmu->base + PMC(counter));
drivers/perf/fsl_imx9_ddr_perf.c
377
writel(0, pmu->base + PMC(counter));
drivers/perf/fsl_imx9_ddr_perf.c
422
writel(ctrl, pmu->base + PMGC0);
drivers/perf/fsl_imx9_ddr_perf.c
430
writel(ctrl, pmu->base + PMGC0);
drivers/perf/fsl_imx9_ddr_perf.c
434
writel(ctrl, pmu->base + PMGC0);
drivers/perf/fsl_imx9_ddr_perf.c
449
writel(ctrl_a, pmu->base + PMLCA(counter));
drivers/perf/fsl_imx9_ddr_perf.c
458
writel(ctrl_a, pmu->base + PMLCA(counter));
drivers/perf/fsl_imx9_ddr_perf.c
462
writel(ctrl_a, pmu->base + PMLCA(counter));
drivers/perf/hisilicon/hisi_pcie_pmu.c
624
writel(HISI_PCIE_GLOBAL_EN, pcie_pmu->base + HISI_PCIE_GLOBAL_CTRL);
drivers/perf/hisilicon/hisi_pcie_pmu.c
631
writel(HISI_PCIE_GLOBAL_NONE, pcie_pmu->base + HISI_PCIE_GLOBAL_CTRL);
drivers/perf/hisilicon/hisi_uncore_cpa_pmu.c
108
writel(val, cpa_pmu->base + CPA_CFG_REG);
drivers/perf/hisilicon/hisi_uncore_cpa_pmu.c
117
writel(val, cpa_pmu->base + CPA_CFG_REG);
drivers/perf/hisilicon/hisi_uncore_cpa_pmu.c
128
writel(val, cpa_pmu->base + CPA_EVENT_CTRL);
drivers/perf/hisilicon/hisi_uncore_cpa_pmu.c
139
writel(val, cpa_pmu->base + CPA_EVENT_CTRL);
drivers/perf/hisilicon/hisi_uncore_cpa_pmu.c
150
writel(val, cpa_pmu->base + CPA_INT_MASK);
drivers/perf/hisilicon/hisi_uncore_cpa_pmu.c
161
writel(val, cpa_pmu->base + CPA_INT_MASK);
drivers/perf/hisilicon/hisi_uncore_cpa_pmu.c
171
writel(1 << idx, cpa_pmu->base + CPA_INT_CLEAR);
drivers/perf/hisilicon/hisi_uncore_cpa_pmu.c
81
writel(val, cpa_pmu->base + reg);
drivers/perf/hisilicon/hisi_uncore_cpa_pmu.c
90
writel(val, cpa_pmu->base + CPA_PERF_CTRL);
drivers/perf/hisilicon/hisi_uncore_cpa_pmu.c
99
writel(val, cpa_pmu->base + CPA_PERF_CTRL);
drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c
103
writel((u32)val, ddrc_pmu->base + ddrc_reg_off[hwc->idx]);
drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c
121
writel(type, ddrc_pmu->base + DDRC_EVENT_TYPEn(regs->event_type, idx));
drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c
158
writel(val, ddrc_pmu->base + regs->perf_ctrl);
drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c
168
writel(val, ddrc_pmu->base + regs->perf_ctrl);
drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c
179
writel(val, ddrc_pmu->base + regs->event_ctrl);
drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c
190
writel(val, ddrc_pmu->base + regs->event_ctrl);
drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c
201
writel(val, ddrc_pmu->base + regs->int_mask);
drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c
212
writel(val, ddrc_pmu->base + regs->int_mask);
drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c
227
writel(1 << idx, ddrc_pmu->base + regs->int_clear);
drivers/perf/hisilicon/hisi_uncore_hha_pmu.c
107
writel(val, hha_pmu->base + HHA_DATSRC_CTRL);
drivers/perf/hisilicon/hisi_uncore_hha_pmu.c
123
writel(val, hha_pmu->base + HHA_SRCID_CTRL);
drivers/perf/hisilicon/hisi_uncore_hha_pmu.c
137
writel(val, hha_pmu->base + HHA_SRCID_CTRL);
drivers/perf/hisilicon/hisi_uncore_hha_pmu.c
202
writel(val, hha_pmu->base + reg);
drivers/perf/hisilicon/hisi_uncore_hha_pmu.c
215
writel(val, hha_pmu->base + HHA_PERF_CTRL);
drivers/perf/hisilicon/hisi_uncore_hha_pmu.c
228
writel(val, hha_pmu->base + HHA_PERF_CTRL);
drivers/perf/hisilicon/hisi_uncore_hha_pmu.c
239
writel(val, hha_pmu->base + HHA_EVENT_CTRL);
drivers/perf/hisilicon/hisi_uncore_hha_pmu.c
250
writel(val, hha_pmu->base + HHA_EVENT_CTRL);
drivers/perf/hisilicon/hisi_uncore_hha_pmu.c
261
writel(val, hha_pmu->base + HHA_INT_MASK);
drivers/perf/hisilicon/hisi_uncore_hha_pmu.c
272
writel(val, hha_pmu->base + HHA_INT_MASK);
drivers/perf/hisilicon/hisi_uncore_hha_pmu.c
282
writel(1 << idx, hha_pmu->base + HHA_INT_CLEAR);
drivers/perf/hisilicon/hisi_uncore_hha_pmu.c
69
writel(val, hha_pmu->base + HHA_SRCID_CTRL);
drivers/perf/hisilicon/hisi_uncore_hha_pmu.c
80
writel(val, hha_pmu->base + HHA_SRCID_CTRL);
drivers/perf/hisilicon/hisi_uncore_hha_pmu.c
93
writel(val, hha_pmu->base + HHA_DATSRC_CTRL);
drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c
165
writel(val, (void __iomem *)hwc->event_base + reg);
drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c
421
writel(val, l3c_pmu->base + L3C_PERF_CTRL);
drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c
433
writel(val, hisi_l3c_pmu->ext_base[i] + L3C_PERF_CTRL);
drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c
452
writel(val, l3c_pmu->base + L3C_PERF_CTRL);
drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c
464
writel(val, hisi_l3c_pmu->ext_base[i] + L3C_PERF_CTRL);
drivers/perf/hisilicon/hisi_uncore_mn_pmu.c
102
writel(val, mn_pmu->base + HISI_MN_EVTYPE_REGn(reg_info->event_type0, idx / 4));
drivers/perf/hisilicon/hisi_uncore_mn_pmu.c
112
writel(val, mn_pmu->base + reg_info->perf_ctrl);
drivers/perf/hisilicon/hisi_uncore_mn_pmu.c
122
writel(val, mn_pmu->base + reg_info->perf_ctrl);
drivers/perf/hisilicon/hisi_uncore_mn_pmu.c
135
writel(val, mn_pmu->base + reg_info->event_ctrl);
drivers/perf/hisilicon/hisi_uncore_mn_pmu.c
146
writel(val, mn_pmu->base + reg_info->event_ctrl);
drivers/perf/hisilicon/hisi_uncore_mn_pmu.c
157
writel(val, mn_pmu->base + reg_info->int_mask);
drivers/perf/hisilicon/hisi_uncore_mn_pmu.c
168
writel(val, mn_pmu->base + reg_info->int_mask);
drivers/perf/hisilicon/hisi_uncore_mn_pmu.c
182
writel(BIT(idx), mn_pmu->base + reg_info->int_clear);
drivers/perf/hisilicon/hisi_uncore_mn_pmu.c
64
writel(val, mn_pmu->base + reg_info->dyn_ctrl);
drivers/perf/hisilicon/hisi_uncore_noc_pmu.c
116
writel(reg, noc_pmu->base + NOC_PMU_EVENT_CTRLn(reg_info->event_ctrl0, hwc->idx));
drivers/perf/hisilicon/hisi_uncore_noc_pmu.c
127
writel(reg, noc_pmu->base + NOC_PMU_EVENT_CTRLn(reg_info->event_ctrl0, hwc->idx));
drivers/perf/hisilicon/hisi_uncore_noc_pmu.c
148
writel(reg, noc_pmu->base + reg_info->pmu_ctrl);
drivers/perf/hisilicon/hisi_uncore_noc_pmu.c
158
writel(reg, noc_pmu->base + reg_info->pmu_ctrl);
drivers/perf/hisilicon/hisi_uncore_noc_pmu.c
175
writel(reg, noc_pmu->base + reg_info->overflow_status);
drivers/perf/hisilicon/hisi_uncore_noc_pmu.c
193
writel(reg, noc_pmu->base + NOC_PMU_EVENT_CTRLn(reg_info->event_ctrl0, hwc->idx));
drivers/perf/hisilicon/hisi_uncore_noc_pmu.c
202
writel(reg, noc_pmu->base + reg_info->pmu_ctrl);
drivers/perf/hisilicon/hisi_uncore_noc_pmu.c
223
writel(reg, noc_pmu->base + reg_info->pmu_ctrl);
drivers/perf/hisilicon/hisi_uncore_noc_pmu.c
75
writel(reg, noc_pmu->base + NOC_PMU_EVENT_CTRLn(reg_info->event_ctrl0, idx));
drivers/perf/hisilicon/hisi_uncore_pa_pmu.c
108
writel(PA_TGTID_NONE, pa_pmu->base + PA_TGTID_CTRL);
drivers/perf/hisilicon/hisi_uncore_pa_pmu.c
120
writel(val, pa_pmu->base + PA_SRCID_CTRL);
drivers/perf/hisilicon/hisi_uncore_pa_pmu.c
130
writel(PA_SRCID_NONE, pa_pmu->base + PA_SRCID_CTRL);
drivers/perf/hisilicon/hisi_uncore_pa_pmu.c
188
writel(val, pa_pmu->base + reg);
drivers/perf/hisilicon/hisi_uncore_pa_pmu.c
197
writel(val, pa_pmu->base + PA_PERF_CTRL);
drivers/perf/hisilicon/hisi_uncore_pa_pmu.c
206
writel(val, pa_pmu->base + PA_PERF_CTRL);
drivers/perf/hisilicon/hisi_uncore_pa_pmu.c
217
writel(val, pa_pmu->base + PA_EVENT_CTRL);
drivers/perf/hisilicon/hisi_uncore_pa_pmu.c
228
writel(val, pa_pmu->base + PA_EVENT_CTRL);
drivers/perf/hisilicon/hisi_uncore_pa_pmu.c
240
writel(val, pa_pmu->base + regs->mask_offset);
drivers/perf/hisilicon/hisi_uncore_pa_pmu.c
252
writel(val, pa_pmu->base + regs->mask_offset);
drivers/perf/hisilicon/hisi_uncore_pa_pmu.c
266
writel(1 << idx, pa_pmu->base + regs->clear_offset);
drivers/perf/hisilicon/hisi_uncore_pa_pmu.c
71
writel(val, pa_pmu->base + PA_TT_CTRL);
drivers/perf/hisilicon/hisi_uncore_pa_pmu.c
85
writel(val, pa_pmu->base + PA_TT_CTRL);
drivers/perf/hisilicon/hisi_uncore_pa_pmu.c
98
writel(val, pa_pmu->base + PA_TGTID_CTRL);
drivers/perf/hisilicon/hisi_uncore_sllc_pmu.c
103
writel(val, sllc_pmu->base + regs->perf_ctrl);
drivers/perf/hisilicon/hisi_uncore_sllc_pmu.c
118
writel(val, sllc_pmu->base + regs->perf_ctrl);
drivers/perf/hisilicon/hisi_uncore_sllc_pmu.c
133
writel(val, sllc_pmu->base + regs->tgtid_ctrl);
drivers/perf/hisilicon/hisi_uncore_sllc_pmu.c
137
writel(val, sllc_pmu->base + regs->perf_ctrl);
drivers/perf/hisilicon/hisi_uncore_sllc_pmu.c
151
writel(SLLC_TGTID_NONE, sllc_pmu->base + regs->tgtid_ctrl);
drivers/perf/hisilicon/hisi_uncore_sllc_pmu.c
155
writel(val, sllc_pmu->base + regs->perf_ctrl);
drivers/perf/hisilicon/hisi_uncore_sllc_pmu.c
171
writel(val, sllc_pmu->base + regs->srcid_ctrl);
drivers/perf/hisilicon/hisi_uncore_sllc_pmu.c
175
writel(val, sllc_pmu->base + regs->perf_ctrl);
drivers/perf/hisilicon/hisi_uncore_sllc_pmu.c
188
writel(SLLC_SRCID_NONE, sllc_pmu->base + regs->srcid_ctrl);
drivers/perf/hisilicon/hisi_uncore_sllc_pmu.c
192
writel(val, sllc_pmu->base + regs->perf_ctrl);
drivers/perf/hisilicon/hisi_uncore_sllc_pmu.c
249
writel(val, sllc_pmu->base + reg);
drivers/perf/hisilicon/hisi_uncore_sllc_pmu.c
259
writel(val, sllc_pmu->base + regs->perf_ctrl);
drivers/perf/hisilicon/hisi_uncore_sllc_pmu.c
269
writel(val, sllc_pmu->base + regs->perf_ctrl);
drivers/perf/hisilicon/hisi_uncore_sllc_pmu.c
280
writel(val, sllc_pmu->base + regs->event_ctrl);
drivers/perf/hisilicon/hisi_uncore_sllc_pmu.c
291
writel(val, sllc_pmu->base + regs->event_ctrl);
drivers/perf/hisilicon/hisi_uncore_sllc_pmu.c
302
writel(val, sllc_pmu->base + regs->int_mask);
drivers/perf/hisilicon/hisi_uncore_sllc_pmu.c
313
writel(val, sllc_pmu->base + regs->int_mask);
drivers/perf/hisilicon/hisi_uncore_sllc_pmu.c
327
writel(BIT_ULL(idx), sllc_pmu->base + regs->int_clear);
drivers/perf/hisilicon/hisi_uncore_uc_pmu.c
113
writel(val, uc_pmu->base + HISI_UC_TRACETAG_CTRL_REG);
drivers/perf/hisilicon/hisi_uncore_uc_pmu.c
132
writel(val, uc_pmu->base + HISI_UC_TRACETAG_CTRL_REG);
drivers/perf/hisilicon/hisi_uncore_uc_pmu.c
137
writel(val, uc_pmu->base + HISI_UC_SRCID_CTRL_REG);
drivers/perf/hisilicon/hisi_uncore_uc_pmu.c
161
writel(val, uc_pmu->base + HISI_UC_TRACETAG_CTRL_REG);
drivers/perf/hisilicon/hisi_uncore_uc_pmu.c
165
writel(val, uc_pmu->base + HISI_UC_SRCID_CTRL_REG);
drivers/perf/hisilicon/hisi_uncore_uc_pmu.c
186
writel(val, uc_pmu->base + HISI_UC_EVENT_CTRL_REG);
drivers/perf/hisilicon/hisi_uncore_uc_pmu.c
205
writel(val, uc_pmu->base + HISI_UC_EVENT_CTRL_REG);
drivers/perf/hisilicon/hisi_uncore_uc_pmu.c
240
writel(val, uc_pmu->base + HISI_UC_EVTYPE_REGn(idx / 4));
drivers/perf/hisilicon/hisi_uncore_uc_pmu.c
249
writel(val, uc_pmu->base + HISI_UC_EVENT_CTRL_REG);
drivers/perf/hisilicon/hisi_uncore_uc_pmu.c
258
writel(val, uc_pmu->base + HISI_UC_EVENT_CTRL_REG);
drivers/perf/hisilicon/hisi_uncore_uc_pmu.c
269
writel(val, uc_pmu->base + HISI_UC_EVENT_CTRL_REG);
drivers/perf/hisilicon/hisi_uncore_uc_pmu.c
280
writel(val, uc_pmu->base + HISI_UC_EVENT_CTRL_REG);
drivers/perf/hisilicon/hisi_uncore_uc_pmu.c
342
writel(val, uc_pmu->base + HISI_UC_INT_MASK_REG);
drivers/perf/hisilicon/hisi_uncore_uc_pmu.c
352
writel(val, uc_pmu->base + HISI_UC_INT_MASK_REG);
drivers/perf/hisilicon/hisi_uncore_uc_pmu.c
362
writel(1 << idx, uc_pmu->base + HISI_UC_INT_CLEAR_REG);
drivers/perf/hisilicon/hisi_uncore_uc_pmu.c
93
writel(val, uc_pmu->base + HISI_UC_TRACETAG_CTRL_REG);
drivers/perf/hisilicon/hns3_pmu.c
1381
writel(val, hns3_pmu->base + HNS3_PMU_REG_GLOBAL_CTRL);
drivers/perf/hisilicon/hns3_pmu.c
1391
writel(val, hns3_pmu->base + HNS3_PMU_REG_GLOBAL_CTRL);
drivers/perf/hisilicon/hns3_pmu.c
748
writel(val, hns3_pmu->base + offset);
drivers/perf/qcom_l3_pmu.c
360
writel(BC_SATROLL_CR_RESET, l3pmu->regs + L3_M_BC_SATROLL_CR);
drivers/perf/qcom_l3_pmu.c
385
writel(BC_ENABLE, l3pmu->regs + L3_M_BC_CR);
drivers/perf/thunderx2_pmu.c
301
writel(val, (void __iomem *)addr);
drivers/perf/xgene_pmu.c
1198
writel(0x0, csr + PMU_PMOVSR);
drivers/perf/xgene_pmu.c
1200
writel(pmovsr, csr + PMU_PMOVSR);
drivers/perf/xgene_pmu.c
1202
writel(pmovsr, csr + PMU_PMOVSCLR);
drivers/perf/xgene_pmu.c
701
writel(PCPPMU_INTENMASK, xgene_pmu->pcppmu_csr + PCPPMU_INTMASK_REG);
drivers/perf/xgene_pmu.c
706
writel(PCPPMU_V3_INTENMASK, xgene_pmu->pcppmu_csr + PCPPMU_INTMASK_REG);
drivers/perf/xgene_pmu.c
711
writel(PCPPMU_INTCLRMASK, xgene_pmu->pcppmu_csr + PCPPMU_INTMASK_REG);
drivers/perf/xgene_pmu.c
716
writel(PCPPMU_V3_INTCLRMASK,
drivers/perf/xgene_pmu.c
748
writel(val, pmu_dev->inf->csr + PMU_PMEVCNTR0 + (4 * idx));
drivers/perf/xgene_pmu.c
767
writel(val, pmu_dev->inf->csr + PMU_PMEVTYPER0 + (4 * idx));
drivers/perf/xgene_pmu.c
773
writel(val, pmu_dev->inf->csr + PMU_PMAMR0);
drivers/perf/xgene_pmu.c
782
writel(val, pmu_dev->inf->csr + PMU_PMAMR1);
drivers/perf/xgene_pmu.c
795
writel(val, pmu_dev->inf->csr + PMU_PMCNTENSET);
drivers/perf/xgene_pmu.c
805
writel(val, pmu_dev->inf->csr + PMU_PMCNTENCLR);
drivers/perf/xgene_pmu.c
815
writel(val, pmu_dev->inf->csr + PMU_PMINTENSET);
drivers/perf/xgene_pmu.c
825
writel(val, pmu_dev->inf->csr + PMU_PMINTENCLR);
drivers/perf/xgene_pmu.c
834
writel(val, pmu_dev->inf->csr + PMU_PMCR);
drivers/perf/xgene_pmu.c
843
writel(val, pmu_dev->inf->csr + PMU_PMCR);
drivers/perf/xgene_pmu.c
852
writel(val, pmu_dev->inf->csr + PMU_PMCR);
drivers/phy/allwinner/phy-sun4i-usb.c
156
writel(iscr, data->base + REG_ISCR);
drivers/phy/allwinner/phy-sun4i-usb.c
192
writel(0, phyctl);
drivers/phy/allwinner/phy-sun4i-usb.c
203
writel(temp, phyctl);
drivers/phy/allwinner/phy-sun4i-usb.c
253
writel(reg_value, phy->pmu);
drivers/phy/allwinner/phy-sun4i-usb.c
318
writel(val, phy2->pmu + REG_HCI_PHY_CTL);
drivers/phy/allwinner/phy-sun4i-usb.c
327
writel(val, phy->pmu + REG_HCI_PHY_CTL);
drivers/phy/allwinner/phy-sun4i-usb.c
335
writel(val, data->base + data->cfg->phyctl_offset);
drivers/phy/allwinner/phy-sun4i-usb.c
378
writel(readl(phyctl) | PHY_CTL_SIDDQ, phyctl);
drivers/phy/allwinner/phy-sun4i-usb.c
579
writel(regval, data->base + REG_PHY_OTGCTL);
drivers/phy/allwinner/phy-sun50i-usb3.c
69
writel(val, phy->regs + SUNXI_PHY_EXTERNAL_CONTROL);
drivers/phy/allwinner/phy-sun50i-usb3.c
73
writel(val, phy->regs + SUNXI_PIPE_CLOCK_CONTROL);
drivers/phy/allwinner/phy-sun50i-usb3.c
77
writel(val, phy->regs + SUNXI_ISCR);
drivers/phy/allwinner/phy-sun50i-usb3.c
84
writel(0x0047fc87, phy->regs + SUNXI_PHY_TUNE_LOW);
drivers/phy/allwinner/phy-sun50i-usb3.c
95
writel(val, phy->regs + SUNXI_PHY_TUNE_HIGH);
drivers/phy/allwinner/phy-sun9i-usb.c
63
writel(reg_value, phy->pmu);
drivers/phy/apple/atc.c
1031
writel(0, atcphy->regs.core + ACIOPHY_TOP_BIST_CIOPHY_CFG1);
drivers/phy/apple/atc.c
1052
writel(0, atcphy->regs.core + ACIOPHY_TOP_BIST_OV_CFG);
drivers/phy/apple/atc.c
1507
writel(reg, atcphy->regs.core + AUSPLL_APB_CMD_OVERRIDE);
drivers/phy/apple/atc.c
1620
writel(USB2PHY_USBCTL_ISOLATION, atcphy->regs.usb2phy + USB2PHY_USBCTL);
drivers/phy/apple/atc.c
1692
writel(USB2PHY_USBCTL_RUN, atcphy->regs.usb2phy + USB2PHY_USBCTL);
drivers/phy/apple/atc.c
843
writel(value, reg);
drivers/phy/broadcom/phy-bcm-cygnus-pcie.c
75
writel(val, core->base + PCIE_CFG_OFFSET);
drivers/phy/broadcom/phy-bcm-cygnus-pcie.c
84
writel(val, core->base + PCIE_CFG_OFFSET);
drivers/phy/broadcom/phy-bcm-kona-usb2.c
47
writel(val, phy->regs + OTGCTL);
drivers/phy/broadcom/phy-bcm-kona-usb2.c
59
writel(val, phy->regs + P1CTL);
drivers/phy/broadcom/phy-bcm-kona-usb2.c
60
writel(val & ~P1CTL_SOFT_RESET, phy->regs + P1CTL);
drivers/phy/broadcom/phy-bcm-kona-usb2.c
63
writel(val | P1CTL_SOFT_RESET, phy->regs + P1CTL);
drivers/phy/broadcom/phy-bcm-ns-usb2.c
69
writel(usb2ctl, usb2->base);
drivers/phy/broadcom/phy-bcm-ns-usb3.c
145
writel(0, usb3->dmp + BCMA_RESET_CTL);
drivers/phy/broadcom/phy-bcm-ns-usb3.c
156
writel(BCMA_RESET_CTL_RESET, usb3->dmp + BCMA_RESET_CTL);
drivers/phy/broadcom/phy-bcm-ns-usb3.c
95
writel(0, usb3->dmp + BCMA_RESET_CTL);
drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c
103
writel(val, driver->icfgdrd_regs + ICFG_FSM_CTRL);
drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c
116
writel(val, driver->crmu_usb2_ctrl);
drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c
120
writel(val, driver->crmu_usb2_ctrl);
drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c
125
writel(val, driver->icfgdrd_regs + ICFG_FSM_CTRL);
drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c
139
writel(DRD_DEV_VAL, driver->icfgdrd_regs + ICFG_DRD_P0CTL);
drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c
143
writel(val, driver->idmdrd_rst_ctrl);
drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c
147
writel(val, driver->crmu_usb2_ctrl);
drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c
152
writel(val, driver->crmu_usb2_ctrl);
drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c
160
writel(DRD_HOST_VAL, driver->icfgdrd_regs + ICFG_DRD_P0CTL);
drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c
164
writel(val, driver->crmu_usb2_ctrl);
drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c
174
writel(val, driver->idmdrd_rst_ctrl);
drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c
179
writel(val, driver->usb2h_strap_reg);
drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c
196
writel(val, driver->icfgdrd_regs + ICFG_FSM_CTRL);
drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c
199
writel(val, driver->icfgdrd_regs + ICFG_FSM_CTRL);
drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c
203
writel(val, driver->icfgdrd_regs + ICFG_DRD_P0CTL);
drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c
208
writel(val, driver->icfgdrd_regs + ICFG_FSM_CTRL);
drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c
211
writel(val, driver->icfgdrd_regs + ICFG_FSM_CTRL);
drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c
215
writel(val, driver->usb2h_strap_reg);
drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c
219
writel(val, driver->icfgdrd_regs + ICFG_DRD_P0CTL);
drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c
378
writel(val, driver->crmu_usb2_ctrl);
drivers/phy/broadcom/phy-bcm-sr-usb.c
103
writel(readl(addr) & ~clear, addr);
drivers/phy/broadcom/phy-bcm-sr-usb.c
108
writel(readl(addr) | set, addr);
drivers/phy/broadcom/phy-bcm-sr-usb.c
137
writel(rd_data, regs + offset[PHY_CTRL]);
drivers/phy/broadcom/phy-brcm-sata.c
223
writel(bank, pcb_base + SATA_PCB_BANK_OFFSET);
drivers/phy/broadcom/phy-brcm-sata.c
226
writel(tmp, pcb_base + SATA_PCB_REG_OFFSET(ofs));
drivers/phy/broadcom/phy-brcm-sata.c
239
writel(bank, pcb_base + SATA_PCB_BANK_OFFSET);
drivers/phy/broadcom/phy-brcm-sata.c
462
writel(PHY_CTRL_1_RESET, ctrl_base + PHY_CTRL_1);
drivers/phy/broadcom/phy-brcm-sata.c
464
writel(0x0, ctrl_base + PHY_CTRL_1);
drivers/phy/cadence/cdns-dphy-rx.c
183
writel(reg, dphy->regs + DPHY_LANE);
drivers/phy/cadence/cdns-dphy-rx.c
196
writel(reg, dphy->regs + DPHY_BAND_CFG);
drivers/phy/cadence/cdns-dphy-rx.c
203
writel(reg, dphy->regs + DPHY_POWER_ISLAND_EN_DATA);
drivers/phy/cadence/cdns-dphy-rx.c
205
writel(reg, dphy->regs + DPHY_POWER_ISLAND_EN_CLK);
drivers/phy/cadence/cdns-dphy-rx.c
85
writel(DPHY_CMN_SSM_EN | DPHY_CMN_RX_MODE_EN |
drivers/phy/cadence/cdns-dphy-rx.c
97
writel(0, dphy->regs + DPHY_CMN_SSM);
drivers/phy/cadence/cdns-dphy.c
220
writel(DPHY_CMN_IPDIV_FROM_REG | DPHY_CMN_OPDIV_FROM_REG |
drivers/phy/cadence/cdns-dphy.c
224
writel(DPHY_CMN_FBDIV_FROM_REG |
drivers/phy/cadence/cdns-dphy.c
227
writel(DPHY_CMN_PWM_HIGH(6) | DPHY_CMN_PWM_LOW(0x101) |
drivers/phy/cadence/cdns-dphy.c
234
writel(DPHY_PSM_CFG_FROM_REG | DPHY_PSM_CLK_DIV(div),
drivers/phy/cadence/cdns-dphy.c
252
writel(DPHY_CMN_PWM_HIGH(6) | DPHY_CMN_PWM_LOW(0x101) |
drivers/phy/cadence/cdns-dphy.c
256
writel((FIELD_PREP(DPHY_TX_J721E_WIZ_IPDIV, cfg->pll_ipdiv) |
drivers/phy/cadence/cdns-dphy.c
261
writel(DPHY_TX_J721E_WIZ_LANE_RSTB,
drivers/phy/cadence/cdns-dphy.c
267
writel(div, dphy->regs + DPHY_TX_J721E_WIZ_PSM_FREQ);
drivers/phy/cadence/cdns-dphy.c
413
writel(reg, dphy->regs + DPHY_BAND_CFG);
drivers/phy/cadence/cdns-dphy.c
417
writel((reg & DPHY_CMN_SSM_CAL_WAIT_TIME) | DPHY_CMN_SSM_EN | DPHY_CMN_TX_MODE_EN,
drivers/phy/cadence/cdns-dphy.c
454
writel(reg & ~DPHY_CMN_SSM_EN, dphy->regs + DPHY_CMN_SSM);
drivers/phy/cadence/phy-cadence-salvo.c
159
writel(val, salvo_phy->base + offset +
drivers/phy/cadence/phy-cadence-torrent.c
508
writel(val, ctx->base + offset);
drivers/phy/freescale/phy-fsl-imx8m-pcie.c
101
writel(val & ~ANA_PLL_CLK_OUT_TO_EXT_IO_EN,
drivers/phy/freescale/phy-fsl-imx8m-pcie.c
105
writel(ANA_PLL_CLK_OUT_TO_EXT_IO_EN,
drivers/phy/freescale/phy-fsl-imx8m-pcie.c
112
writel(ANA_PLL_CLK_OUT_TO_EXT_IO_SEL,
drivers/phy/freescale/phy-fsl-imx8m-pcie.c
115
writel(AUX_PLL_REFCLK_SEL_SYS_PLL,
drivers/phy/freescale/phy-fsl-imx8m-pcie.c
119
writel(val | ANA_AUX_RX_TERM_GND_EN,
drivers/phy/freescale/phy-fsl-imx8m-pcie.c
121
writel(ANA_AUX_RX_TERM | ANA_AUX_TX_LVL,
drivers/phy/freescale/phy-fsl-imx8m-pcie.c
86
writel(imx8_phy->tx_deemph_gen1,
drivers/phy/freescale/phy-fsl-imx8m-pcie.c
89
writel(imx8_phy->tx_deemph_gen2,
drivers/phy/freescale/phy-fsl-imx8mq-usb.c
194
writel(val, tca->base + TCA_GCFG);
drivers/phy/freescale/phy-fsl-imx8mq-usb.c
197
writel(val, tca->base + TCA_TCPC);
drivers/phy/freescale/phy-fsl-imx8mq-usb.c
204
writel(val, tca->base + TCA_GCFG);
drivers/phy/freescale/phy-fsl-imx8mq-usb.c
209
writel(val, tca->base + TCA_SYSMODE_CFG);
drivers/phy/freescale/phy-fsl-imx8mq-usb.c
216
writel(val, tca->base + TCA_SYSMODE_CFG);
drivers/phy/freescale/phy-fsl-imx8mq-usb.c
220
writel(val, tca->base + TCA_SYSMODE_CFG);
drivers/phy/freescale/phy-fsl-imx8mq-usb.c
234
writel(val, tca->base + TCA_CLK_RST);
drivers/phy/freescale/phy-fsl-imx8mq-usb.c
240
writel(val, tca->base + TCA_CLK_RST);
drivers/phy/freescale/phy-fsl-imx8mq-usb.c
493
writel(value, imx_phy->base + PHY_CTRL4);
drivers/phy/freescale/phy-fsl-imx8mq-usb.c
501
writel(value, imx_phy->base + PHY_CTRL5);
drivers/phy/freescale/phy-fsl-imx8mq-usb.c
542
writel(value, imx_phy->base + PHY_CTRL3);
drivers/phy/freescale/phy-fsl-imx8mq-usb.c
554
writel(value, imx_phy->base + PHY_CTRL1);
drivers/phy/freescale/phy-fsl-imx8mq-usb.c
558
writel(value, imx_phy->base + PHY_CTRL0);
drivers/phy/freescale/phy-fsl-imx8mq-usb.c
562
writel(value, imx_phy->base + PHY_CTRL2);
drivers/phy/freescale/phy-fsl-imx8mq-usb.c
566
writel(value, imx_phy->base + PHY_CTRL1);
drivers/phy/freescale/phy-fsl-imx8mq-usb.c
581
writel(value, imx_phy->base + PHY_CTRL0);
drivers/phy/freescale/phy-fsl-imx8mq-usb.c
586
writel(value, imx_phy->base + PHY_CTRL6);
drivers/phy/freescale/phy-fsl-imx8mq-usb.c
591
writel(value, imx_phy->base + PHY_CTRL1);
drivers/phy/freescale/phy-fsl-imx8mq-usb.c
598
writel(value, imx_phy->base + PHY_CTRL0);
drivers/phy/freescale/phy-fsl-imx8mq-usb.c
602
writel(value, imx_phy->base + PHY_CTRL2);
drivers/phy/freescale/phy-fsl-imx8mq-usb.c
608
writel(value, imx_phy->base + PHY_CTRL1);
drivers/phy/freescale/phy-fsl-imx8mq-usb.c
641
writel(value, imx_phy->base + PHY_CTRL6);
drivers/phy/freescale/phy-fsl-imx8mq-usb.c
654
writel(value, imx_phy->base + PHY_CTRL6);
drivers/phy/hisilicon/phy-hi3670-pcie.c
176
writel(val, phy->base + APB_PHY_START_ADDR + reg);
drivers/phy/hisilicon/phy-hi3670-pcie.c
198
writel(val, phy->base + reg);
drivers/phy/hisilicon/phy-hisi-inno-usb2.c
75
writel(val, reg);
drivers/phy/hisilicon/phy-hisi-inno-usb2.c
82
writel(value, reg);
drivers/phy/hisilicon/phy-hisi-inno-usb2.c
84
writel(val, reg);
drivers/phy/hisilicon/phy-histb-combphy.c
119
writel(val, priv->mmio + COMBPHY_CFG_REG);
drivers/phy/hisilicon/phy-histb-combphy.c
130
writel(val, priv->mmio + COMBPHY_CFG_REG);
drivers/phy/hisilicon/phy-histb-combphy.c
151
writel(val, priv->mmio + COMBPHY_CFG_REG);
drivers/phy/hisilicon/phy-histb-combphy.c
65
writel(val, reg);
drivers/phy/hisilicon/phy-histb-combphy.c
69
writel(val, reg);
drivers/phy/hisilicon/phy-histb-combphy.c
71
writel(val, reg);
drivers/phy/ingenic/phy-ingenic-usb.c
116
writel(reg & ~USBPCR_POR, priv->base + REG_USBPCR_OFFSET);
drivers/phy/ingenic/phy-ingenic-usb.c
168
writel(reg, priv->base + REG_USBPCR_OFFSET);
drivers/phy/ingenic/phy-ingenic-usb.c
177
writel(reg, priv->base + REG_USBPCR_OFFSET);
drivers/phy/ingenic/phy-ingenic-usb.c
186
writel(reg, priv->base + REG_USBPCR_OFFSET);
drivers/phy/ingenic/phy-ingenic-usb.c
218
writel(reg, priv->base + REG_USBPCR_OFFSET);
drivers/phy/ingenic/phy-ingenic-usb.c
228
writel(reg, priv->base + REG_USBPCR1_OFFSET);
drivers/phy/ingenic/phy-ingenic-usb.c
232
writel(reg, priv->base + REG_USBPCR_OFFSET);
drivers/phy/ingenic/phy-ingenic-usb.c
242
writel(reg, priv->base + REG_USBPCR1_OFFSET);
drivers/phy/ingenic/phy-ingenic-usb.c
245
writel(reg, priv->base + REG_USBPCR_OFFSET);
drivers/phy/ingenic/phy-ingenic-usb.c
254
writel(reg, priv->base + REG_USBPCR1_OFFSET);
drivers/phy/ingenic/phy-ingenic-usb.c
260
writel(reg, priv->base + REG_USBPCR_OFFSET);
drivers/phy/ingenic/phy-ingenic-usb.c
269
writel(USBRDT_VBFIL_EN | USBRDT_UTMI_RST, priv->base + REG_USBRDT_OFFSET);
drivers/phy/ingenic/phy-ingenic-usb.c
273
writel(reg, priv->base + REG_USBPCR1_OFFSET);
drivers/phy/ingenic/phy-ingenic-usb.c
277
writel(reg, priv->base + REG_USBPCR_OFFSET);
drivers/phy/ingenic/phy-ingenic-usb.c
286
writel(reg & ~USBPCR1_PORT_RST, priv->base + REG_USBPCR1_OFFSET);
drivers/phy/ingenic/phy-ingenic-usb.c
289
writel(reg, priv->base + REG_USBPCR_OFFSET);
drivers/phy/intel/phy-intel-lgm-combo.c
138
writel(reg_val, base + reg);
drivers/phy/marvell/phy-armada375-usb2.c
45
writel(reg, cluster_phy->reg);
drivers/phy/marvell/phy-armada38x-comphy.c
75
writel(conf, priv->conf);
drivers/phy/marvell/phy-armada38x-comphy.c
85
writel(val | value, lane->base + offset);
drivers/phy/marvell/phy-berlin-sata.c
102
writel(regval, priv->base + HOST_VSA_DATA);
drivers/phy/marvell/phy-berlin-sata.c
125
writel(regval, ctrl_reg + PORT_SCR_CTL);
drivers/phy/marvell/phy-berlin-sata.c
145
writel(CONTROL_REGISTER, priv->base + HOST_VSA_ADDR);
drivers/phy/marvell/phy-berlin-sata.c
148
writel(regval, priv->base + HOST_VSA_DATA);
drivers/phy/marvell/phy-berlin-sata.c
72
writel(phy_base + reg, ctrl_reg + PORT_VSR_ADDR);
drivers/phy/marvell/phy-berlin-sata.c
78
writel(regval, ctrl_reg + PORT_VSR_DATA);
drivers/phy/marvell/phy-berlin-sata.c
93
writel(CONTROL_REGISTER, priv->base + HOST_VSA_ADDR);
drivers/phy/marvell/phy-berlin-sata.c
96
writel(regval, priv->base + HOST_VSA_DATA);
drivers/phy/marvell/phy-berlin-sata.c
99
writel(MBUS_SIZE_CONTROL, priv->base + HOST_VSA_ADDR);
drivers/phy/marvell/phy-berlin-usb.c
121
writel(priv->pll_divider,
drivers/phy/marvell/phy-berlin-usb.c
123
writel(CLK_STABLE | PLL_CTRL_REG | PHASE_OFF_TOL_250 | KVC0_REG_CTRL |
drivers/phy/marvell/phy-berlin-usb.c
125
writel(V2I_VCO_RATIO(0x5) | R_ROTATE_0 | ANA_TEST_DC_CTRL(0x5),
drivers/phy/marvell/phy-berlin-usb.c
127
writel(PHASE_FREEZE_DLY_4_CL | ACK_LENGTH_16_CL | SQ_LENGTH_12 |
drivers/phy/marvell/phy-berlin-usb.c
131
writel(TX_VDD12_13 | TX_OUT_AMP(0x3), priv->base + USB_PHY_TX_CTRL1);
drivers/phy/marvell/phy-berlin-usb.c
132
writel(EXT_HS_RCAL_EN | IMPCAL_VTH_DIV(0x3) | EXT_RS_RCAL_DIV(0x4),
drivers/phy/marvell/phy-berlin-usb.c
135
writel(EXT_HS_RCAL_EN | IMPCAL_VTH_DIV(0x3) | EXT_RS_RCAL_DIV(0x4) |
drivers/phy/marvell/phy-berlin-usb.c
138
writel(EXT_HS_RCAL_EN | IMPCAL_VTH_DIV(0x3) | EXT_RS_RCAL_DIV(0x4),
drivers/phy/marvell/phy-berlin-usb.c
140
writel(TX_CHAN_CTRL_REG(0xf) | DRV_SLEWRATE(0x3) | IMP_CAL_FS_HS_DLY_3 |
drivers/phy/marvell/phy-mvebu-a3700-comphy.c
375
writel(val, addr);
drivers/phy/marvell/phy-mvebu-a3700-comphy.c
391
writel(offset,
drivers/phy/marvell/phy-mvebu-a3700-comphy.c
425
writel(reg + COMPHY_LANE2_REGS_BASE,
drivers/phy/marvell/phy-mvebu-a3700-comphy.c
516
writel(new, lane->priv->comphy_regs + COMPHY_SELECTOR_PHY_REG);
drivers/phy/marvell/phy-mvebu-a3700-utmi.c
102
writel(reg, utmi->regs + USB2_PHY_PLL_CTRL_REG0);
drivers/phy/marvell/phy-mvebu-a3700-utmi.c
113
writel(reg, utmi->regs + USB2_PHY_OTG_CTRL);
drivers/phy/marvell/phy-mvebu-a3700-utmi.c
119
writel(reg, utmi->regs + USB2_PHY_CHRGR_DETECT);
drivers/phy/marvell/phy-mvebu-a3700-utmi.c
173
writel(reg, utmi->regs + USB2_PHY_CTRL(usb32));
drivers/phy/marvell/phy-mvebu-a3700-utmi.c
179
writel(reg, utmi->regs + USB2_PHY_OTG_CTRL);
drivers/phy/marvell/phy-mvebu-cp110-comphy.c
385
writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG0(lane->id));
drivers/phy/marvell/phy-mvebu-cp110-comphy.c
414
writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));
drivers/phy/marvell/phy-mvebu-cp110-comphy.c
420
writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));
drivers/phy/marvell/phy-mvebu-cp110-comphy.c
435
writel(val, priv->base + MVEBU_COMPHY_MISC_CTRL0(lane->id));
drivers/phy/marvell/phy-mvebu-cp110-comphy.c
443
writel(val, priv->base + MVEBU_COMPHY_PWRPLL_CTRL(lane->id));
drivers/phy/marvell/phy-mvebu-cp110-comphy.c
448
writel(val, priv->base + MVEBU_COMPHY_LOOPBACK(lane->id));
drivers/phy/marvell/phy-mvebu-cp110-comphy.c
463
writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG0(lane->id));
drivers/phy/marvell/phy-mvebu-cp110-comphy.c
478
writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));
drivers/phy/marvell/phy-mvebu-cp110-comphy.c
489
writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));
drivers/phy/marvell/phy-mvebu-cp110-comphy.c
508
writel(val, priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id));
drivers/phy/marvell/phy-mvebu-cp110-comphy.c
512
writel(val, priv->base + MVEBU_COMPHY_DTL_CTRL(lane->id));
drivers/phy/marvell/phy-mvebu-cp110-comphy.c
522
writel(val, priv->base + MVEBU_COMPHY_GEN1_S0(lane->id));
drivers/phy/marvell/phy-mvebu-cp110-comphy.c
541
writel(val, priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id));
drivers/phy/marvell/phy-mvebu-cp110-comphy.c
545
writel(val, priv->base + MVEBU_COMPHY_DTL_CTRL(lane->id));
drivers/phy/marvell/phy-mvebu-cp110-comphy.c
549
writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG2(lane->id));
drivers/phy/marvell/phy-mvebu-cp110-comphy.c
553
writel(val, priv->base + MVEBU_COMPHY_DFE_RES(lane->id));
drivers/phy/marvell/phy-mvebu-cp110-comphy.c
558
writel(val, priv->base + MVEBU_COMPHY_GEN1_S0(lane->id));
drivers/phy/marvell/phy-mvebu-cp110-comphy.c
566
writel(val, priv->base + MVEBU_COMPHY_GEN1_S1(lane->id));
drivers/phy/marvell/phy-mvebu-cp110-comphy.c
570
writel(val, priv->base + MVEBU_COMPHY_COEF(lane->id));
drivers/phy/marvell/phy-mvebu-cp110-comphy.c
575
writel(val, priv->base + MVEBU_COMPHY_GEN1_S4(lane->id));
drivers/phy/marvell/phy-mvebu-cp110-comphy.c
594
writel(val, priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id));
drivers/phy/marvell/phy-mvebu-cp110-comphy.c
598
writel(val, priv->base + MVEBU_COMPHY_DTL_CTRL(lane->id));
drivers/phy/marvell/phy-mvebu-cp110-comphy.c
603
writel(val, priv->base + MVEBU_COMPHY_SPEED_DIV(lane->id));
drivers/phy/marvell/phy-mvebu-cp110-comphy.c
607
writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG2(lane->id));
drivers/phy/marvell/phy-mvebu-cp110-comphy.c
612
writel(val, priv->base + MVEBU_COMPHY_DFE_RES(lane->id));
drivers/phy/marvell/phy-mvebu-cp110-comphy.c
619
writel(val, priv->base + MVEBU_COMPHY_GEN1_S0(lane->id));
drivers/phy/marvell/phy-mvebu-cp110-comphy.c
624
writel(val, priv->base + MVEBU_COMPHY_GEN1_S2(lane->id));
drivers/phy/marvell/phy-mvebu-cp110-comphy.c
629
writel(val, priv->base + MVEBU_COMPHY_TX_SLEW_RATE(lane->id));
drivers/phy/marvell/phy-mvebu-cp110-comphy.c
636
writel(val, priv->base + MVEBU_COMPHY_IMP_CAL(lane->id));
drivers/phy/marvell/phy-mvebu-cp110-comphy.c
640
writel(val, priv->base + MVEBU_COMPHY_GEN1_S5(lane->id));
drivers/phy/marvell/phy-mvebu-cp110-comphy.c
652
writel(val, priv->base + MVEBU_COMPHY_GEN1_S1(lane->id));
drivers/phy/marvell/phy-mvebu-cp110-comphy.c
656
writel(val, priv->base + MVEBU_COMPHY_COEF(lane->id));
drivers/phy/marvell/phy-mvebu-cp110-comphy.c
661
writel(val, priv->base + MVEBU_COMPHY_GEN1_S4(lane->id));
drivers/phy/marvell/phy-mvebu-cp110-comphy.c
665
writel(val, priv->base + MVEBU_COMPHY_GEN1_S3(lane->id));
drivers/phy/marvell/phy-mvebu-cp110-comphy.c
671
writel(val, priv->base + MVEBU_COMPHY_TRAINING5(lane->id));
drivers/phy/marvell/phy-mvebu-cp110-comphy.c
676
writel(val, priv->base + MVEBU_COMPHY_TRAINING0(lane->id));
drivers/phy/marvell/phy-mvebu-cp110-comphy.c
681
writel(val, priv->base + MVEBU_COMPHY_TX_PRESET(lane->id));
drivers/phy/marvell/phy-mvebu-cp110-comphy.c
685
writel(val, priv->base + MVEBU_COMPHY_FRAME_DETECT3(lane->id));
drivers/phy/marvell/phy-mvebu-cp110-comphy.c
690
writel(val, priv->base + MVEBU_COMPHY_TX_TRAIN_PRESET(lane->id));
drivers/phy/marvell/phy-mvebu-cp110-comphy.c
695
writel(val, priv->base + MVEBU_COMPHY_FRAME_DETECT0(lane->id));
drivers/phy/marvell/phy-mvebu-cp110-comphy.c
699
writel(val, priv->base + MVEBU_COMPHY_DME(lane->id));
drivers/phy/marvell/phy-mvebu-cp110-comphy.c
703
writel(val, priv->base + MVEBU_COMPHY_VDD_CAL0(lane->id));
drivers/phy/marvell/phy-mvebu-cp110-comphy.c
709
writel(val, priv->base + MVEBU_SP_CALIB(lane->id));
drivers/phy/marvell/phy-mvebu-cp110-comphy.c
711
writel(val, priv->base + MVEBU_SP_CALIB(lane->id));
drivers/phy/marvell/phy-mvebu-cp110-comphy.c
717
writel(val, priv->base + MVEBU_COMPHY_EXT_SELV(lane->id));
drivers/phy/marvell/phy-mvebu-cp110-comphy.c
761
writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));
drivers/phy/marvell/phy-mvebu-cp110-comphy.c
884
writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));
drivers/phy/marvell/phy-mvebu-cp110-utmi.c
129
writel(reg, PORT_REGS(port) + UTMI_PLL_CTRL_REG);
drivers/phy/marvell/phy-mvebu-cp110-utmi.c
135
writel(reg, PORT_REGS(port) + UTMI_CAL_CTRL_REG);
drivers/phy/marvell/phy-mvebu-cp110-utmi.c
141
writel(reg, PORT_REGS(port) + UTMI_TX_CH_CTRL_REG);
drivers/phy/marvell/phy-mvebu-cp110-utmi.c
147
writel(reg, PORT_REGS(port) + UTMI_RX_CH_CTRL0_REG);
drivers/phy/marvell/phy-mvebu-cp110-utmi.c
156
writel(reg, PORT_REGS(port) + UTMI_RX_CH_CTRL1_REG);
drivers/phy/marvell/phy-mvebu-cp110-utmi.c
165
writel(reg, PORT_REGS(port) + UTMI_CHGDTC_CTRL_REG);
drivers/phy/marvell/phy-mvebu-cp110-utmi.c
172
writel(reg, PORT_REGS(port) + UTMI_DIG_CTRL1_REG);
drivers/phy/marvell/phy-mvebu-cp110-utmi.c
231
writel(reg, PORT_REGS(port) + UTMI_CTRL_STATUS0_REG);
drivers/phy/marvell/phy-mvebu-cp110-utmi.c
246
writel(reg, PORT_REGS(port) + UTMI_CTRL_STATUS0_REG);
drivers/phy/marvell/phy-mvebu-sata.c
40
writel(reg , priv->base + SATA_PHY_MODE_2);
drivers/phy/marvell/phy-mvebu-sata.c
45
writel(reg, priv->base + SATA_IF_CTRL);
drivers/phy/marvell/phy-mvebu-sata.c
63
writel(reg, priv->base + SATA_PHY_MODE_2);
drivers/phy/marvell/phy-mvebu-sata.c
68
writel(reg, priv->base + SATA_IF_CTRL);
drivers/phy/marvell/phy-pxa-28nm-hsic.c
132
writel(readl(base + PHY_28NM_HSIC_CTRL) & ~PHY_28NM_HSIC_S2H_HSIC_EN,
drivers/phy/marvell/phy-pxa-28nm-hsic.c
144
writel(readl(base + PHY_28NM_HSIC_PLL_CTRL2) &
drivers/phy/marvell/phy-pxa-28nm-hsic.c
66
writel(0x1 << PHY_28NM_HSIC_PLL_SELLPFR_SHIFT |
drivers/phy/marvell/phy-pxa-28nm-hsic.c
72
writel(readl(base + PHY_28NM_HSIC_PLL_CTRL2) |
drivers/phy/marvell/phy-pxa-28nm-hsic.c
99
writel(reg, base + PHY_28NM_HSIC_CTRL);
drivers/phy/marvell/phy-pxa-28nm-usb2.c
163
writel(reg | (0x1 << PHY_28NM_PLL_SELLPFR_SHIFT
drivers/phy/marvell/phy-pxa-28nm-usb2.c
171
writel(reg | PHY_28NM_PLL_PU_PLL | PHY_28NM_PLL_PU_BY_REG,
drivers/phy/marvell/phy-pxa-28nm-usb2.c
176
writel(reg | PHY_28NM_TX_PU_BY_REG | 0x3 << PHY_28NM_TX_AMP_SHIFT |
drivers/phy/marvell/phy-pxa-28nm-usb2.c
182
writel(reg | 0xa << PHY_28NM_RX_SQ_THRESH_SHIFT,
drivers/phy/marvell/phy-pxa-28nm-usb2.c
190
writel(reg | (0x1 << PHY_28NM_DIG_SYNC_NUM_SHIFT |
drivers/phy/marvell/phy-pxa-28nm-usb2.c
196
writel(reg & ~PHY_28NM_OTG_CONTROL_BY_PIN, base + PHY_28NM_OTG_REG);
drivers/phy/marvell/phy-pxa-28nm-usb2.c
239
writel(readl(base + PHY_28NM_CTRL_REG3) |
drivers/phy/marvell/phy-pxa-28nm-usb2.c
252
writel(readl(base + PHY_28NM_CTRL_REG3) |
drivers/phy/mediatek/phy-mtk-io.h
19
writel(tmp, reg);
drivers/phy/mediatek/phy-mtk-io.h
27
writel(tmp, reg);
drivers/phy/mediatek/phy-mtk-io.h
36
writel(tmp, reg);
drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c
197
writel(pcw, base + MIPITX_DSI_PLL_CON2);
drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c
140
writel(RG_DSI_PAD_TIEL_SEL | RG_DSI_BG_CORE_EN, base + MIPITX_LANE_CON);
drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c
142
writel(RG_DSI_BG_CORE_EN | RG_DSI_BG_LPF_EN, base + MIPITX_LANE_CON);
drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c
171
writel(RG_DSI_PAD_TIEL_SEL | RG_DSI_BG_CORE_EN, base + MIPITX_LANE_CON);
drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c
172
writel(RG_DSI_PAD_TIEL_SEL, base + MIPITX_LANE_CON);
drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c
82
writel(pcw, base + MIPITX_PLL_CON0);
drivers/phy/mediatek/phy-mtk-tphy.c
715
writel(tmp, fmreg + U3P_U2FREQ_FMCR0);
drivers/phy/mediatek/phy-mtk-tphy.c
815
writel(P2R_RG_U2PLL_FBDIV_26M, com + U3P_U2PHYA_RESV);
drivers/phy/mediatek/phy-mtk-tphy.c
948
writel(tmp, u2_banks->com + U3P_U2PHYDTM1);
drivers/phy/mediatek/phy-mtk-xfi-tphy.c
153
writel(0x01423342, xfi_tphy->base + 0x00f8);
drivers/phy/mediatek/phy-mtk-xfi-tphy.c
155
writel(0x00a132a1, xfi_tphy->base + 0x00f8);
drivers/phy/mediatek/phy-mtk-xfi-tphy.c
157
writel(0x009c329c, xfi_tphy->base + 0x00f8);
drivers/phy/mediatek/phy-mtk-xfi-tphy.c
159
writel(0x00fa32fa, xfi_tphy->base + 0x00f8);
drivers/phy/mediatek/phy-mtk-xfi-tphy.c
172
writel(XTP_PCS_RX_EQ_IN_PROGRESS(2) | XTP_PCS_PWD_SYNC(2) | XTP_PCS_PWD_ASYNC(2),
drivers/phy/mediatek/phy-mtk-xfi-tphy.c
176
writel(XTP_LN_FRC_TX_DATA_EN, xfi_tphy->base + REG_DIG_LN_TRX_40);
drivers/phy/mediatek/phy-mtk-xfi-tphy.c
180
writel(0x00008a01, xfi_tphy->base + 0x3028);
drivers/phy/mediatek/phy-mtk-xfi-tphy.c
181
writel(0x0000a884, xfi_tphy->base + 0x302c);
drivers/phy/mediatek/phy-mtk-xfi-tphy.c
182
writel(0x00083002, xfi_tphy->base + 0x3024);
drivers/phy/mediatek/phy-mtk-xfi-tphy.c
186
writel(0x00011110, xfi_tphy->base + 0x3010);
drivers/phy/mediatek/phy-mtk-xfi-tphy.c
187
writel(0x40704000, xfi_tphy->base + 0x3048);
drivers/phy/mediatek/phy-mtk-xfi-tphy.c
189
writel(0x00022220, xfi_tphy->base + 0x3010);
drivers/phy/mediatek/phy-mtk-xfi-tphy.c
190
writel(0x0f020a01, xfi_tphy->base + 0x5064);
drivers/phy/mediatek/phy-mtk-xfi-tphy.c
191
writel(0x06100600, xfi_tphy->base + 0x50b4);
drivers/phy/mediatek/phy-mtk-xfi-tphy.c
193
writel(0x40704000, xfi_tphy->base + 0x3048);
drivers/phy/mediatek/phy-mtk-xfi-tphy.c
195
writel(0x47684100, xfi_tphy->base + 0x3048);
drivers/phy/mediatek/phy-mtk-xfi-tphy.c
199
writel(0x0000c000, xfi_tphy->base + 0x3064);
drivers/phy/mediatek/phy-mtk-xfi-tphy.c
208
writel(0x00000f00, xfi_tphy->base + 0x306c);
drivers/phy/mediatek/phy-mtk-xfi-tphy.c
210
writel(0x22000f00, xfi_tphy->base + 0x306c);
drivers/phy/mediatek/phy-mtk-xfi-tphy.c
212
writel(0x20200f00, xfi_tphy->base + 0x306c);
drivers/phy/mediatek/phy-mtk-xsphy.c
241
writel(tmp, inst->port_base + XSP_U2PHYDTM1);
drivers/phy/microchip/lan966x_serdes.c
56
writel(v, mem + offset);
drivers/phy/microchip/sparx5_serdes.h
124
writel(nval, addr);
drivers/phy/microchip/sparx5_serdes.h
139
writel(nval, addr);
drivers/phy/microchip/sparx5_serdes.h
148
writel(nval, addr);
drivers/phy/phy-airoha-pcie.c
1036
writel(0x804000, pcie_phy->pma0 + REG_PCIE_PMA_DIG_RESERVE_27);
drivers/phy/phy-airoha-pcie.c
1060
writel(0x804000, pcie_phy->pma1 + REG_PCIE_PMA_DIG_RESERVE_27);
drivers/phy/phy-airoha-pcie.c
1121
writel(val, pcie_phy->p0_xr_dtime + REG_PCIE_PEXTP_DIG_GLB44);
drivers/phy/phy-airoha-pcie.c
1122
writel(val, pcie_phy->p1_xr_dtime + REG_PCIE_PEXTP_DIG_GLB44);
drivers/phy/phy-airoha-pcie.c
1126
writel(val, pcie_phy->rx_aeq + REG_PCIE_PEXTP_DIG_LN_RX30_P0);
drivers/phy/phy-airoha-pcie.c
1127
writel(val, pcie_phy->rx_aeq + REG_PCIE_PEXTP_DIG_LN_RX30_P1);
drivers/phy/phy-airoha-pcie.c
427
writel(0xcccbcccb, pcie_phy->pma0 + REG_PCIE_PMA_DIG_RESERVE_21);
drivers/phy/phy-airoha-pcie.c
428
writel(0xcccb, pcie_phy->pma0 + REG_PCIE_PMA_DIG_RESERVE_22);
drivers/phy/phy-airoha-pcie.c
429
writel(0xcccbcccb, pcie_phy->pma1 + REG_PCIE_PMA_DIG_RESERVE_21);
drivers/phy/phy-airoha-pcie.c
430
writel(0xcccb, pcie_phy->pma1 + REG_PCIE_PMA_DIG_RESERVE_22);
drivers/phy/phy-airoha-pcie.c
481
writel(0x2a00090b, pcie_phy->pma0 + REG_PCIE_PMA_DIG_RESERVE_17);
drivers/phy/phy-airoha-pcie.c
482
writel(0x2a00090b, pcie_phy->pma1 + REG_PCIE_PMA_DIG_RESERVE_17);
drivers/phy/phy-airoha-pcie.c
515
writel(0x0, pcie_phy->csr_2l + REG_CSR_2L_JCPLL_SSC_DELTA1);
drivers/phy/phy-airoha-pcie.c
56
writel(val, reg);
drivers/phy/phy-airoha-pcie.c
63
writel(val, reg);
drivers/phy/phy-airoha-pcie.c
649
writel(0x0, pcie_phy->csr_2l + REG_CSR_2L_TXPLL_SSC_DELTA1);
drivers/phy/phy-airoha-pcie.c
686
writel(0x0, pcie_phy->csr_2l + REG_CSR_2L_TXPLL_SSC_DELTA1);
drivers/phy/phy-airoha-pcie.c
72
writel(tmp, reg);
drivers/phy/phy-google-usb.c
71
writel(reg, gphy->usbdp_top_base + USBCS_PHY_CFG1_OFFSET);
drivers/phy/phy-google-usb.c
75
writel(reg, gphy->usbdp_top_base + USBCS_PHY_CFG1_OFFSET);
drivers/phy/phy-lgm-usb.c
112
writel(TCPC_DISCONN, ta->phy.io_priv + TCPC_OFFSET);
drivers/phy/phy-lgm-usb.c
165
writel(val, ta->phy.io_priv + TCPC_OFFSET);
drivers/phy/phy-lgm-usb.c
86
writel(readl(ctrl1) | SRAM_EXT_LD_DONE, ctrl1);
drivers/phy/phy-lgm-usb.c
90
writel(TCPC_CONN, ta->phy.io_priv + TCPC_OFFSET);
drivers/phy/phy-spacemit-k1-pcie.c
195
writel(val, regs + PCIE_PU_ADDR_CLK_CFG);
drivers/phy/phy-spacemit-k1-pcie.c
200
writel(val, regs + PCIE_PU_PLL_1);
drivers/phy/phy-spacemit-k1-pcie.c
214
writel(val, regs + PCIE_PU_ADDR_CLK_CFG);
drivers/phy/phy-spacemit-k1-pcie.c
222
writel(val, regs + PCIE_RC_DONE_STATUS);
drivers/phy/phy-spacemit-k1-pcie.c
227
writel(val, regs + PCIE_PU_PLL_1);
drivers/phy/phy-spacemit-k1-pcie.c
231
writel(val, regs + PCIE_PU_PLL_2);
drivers/phy/phy-spacemit-k1-pcie.c
254
writel(val, regs + PCIE_PU_PLL_1);
drivers/phy/phy-spacemit-k1-pcie.c
260
writel(val, regs + PCIE_PU_ADDR_CLK_CFG);
drivers/phy/phy-spacemit-k1-pcie.c
345
writel(val, regs + PCIE_RX_REG1);
drivers/phy/phy-spacemit-k1-pcie.c
350
writel(val, regs + PCIE_RX_REG2);
drivers/phy/phy-spacemit-k1-pcie.c
360
writel(val, regs + PCIE_TX_REG1);
drivers/phy/phy-spacemit-k1-pcie.c
367
writel(val, regs + PCIE_RC_CAL_REG2);
drivers/phy/phy-spacemit-k1-pcie.c
371
writel(val, regs + PCIE_RC_CAL_REG2);
drivers/phy/phy-spacemit-k1-pcie.c
378
writel(val, regs + PCIE_LTSSM_DIS_ENTRY);
drivers/phy/phy-spacemit-k1-pcie.c
390
writel(0, k1_phy->regs + USB3_TEST_CTRL);
drivers/phy/phy-xgene.c
1144
writel(0xdf, csr_serdes + SATA_ENET_SDS_RST_CTL);
drivers/phy/phy-xgene.c
1263
writel(0x0, sds_base + SATA_ENET_SDS_RST_CTL);
drivers/phy/phy-xgene.c
1266
writel(0x20, sds_base + SATA_ENET_SDS_RST_CTL);
drivers/phy/phy-xgene.c
1269
writel(0xde, sds_base + SATA_ENET_SDS_RST_CTL);
drivers/phy/phy-xgene.c
1276
writel(val, sds_base + SATA_ENET_SDS_CTL1);
drivers/phy/phy-xgene.c
1281
writel(val, sds_base + SATA_ENET_SDS_CTL0);
drivers/phy/phy-xgene.c
1300
writel(val, sds_base + SATA_ENET_SDS_PCS_CTL0);
drivers/phy/phy-xgene.c
560
writel(data, csr_base + indirect_data_reg);
drivers/phy/phy-xgene.c
562
writel(cmd, csr_base + indirect_cmd_reg);
drivers/phy/phy-xgene.c
582
writel(cmd, csr_base + indirect_cmd_reg);
drivers/phy/qualcomm/phy-qcom-edp.c
1000
writel(0x04, edp->tx1 + TXn_TX_BAND);
drivers/phy/qualcomm/phy-qcom-edp.c
1006
writel(0x01, edp->edp + DP_PHY_CFG);
drivers/phy/qualcomm/phy-qcom-edp.c
1007
writel(0x05, edp->edp + DP_PHY_CFG);
drivers/phy/qualcomm/phy-qcom-edp.c
1008
writel(0x01, edp->edp + DP_PHY_CFG);
drivers/phy/qualcomm/phy-qcom-edp.c
1009
writel(0x09, edp->edp + DP_PHY_CFG);
drivers/phy/qualcomm/phy-qcom-edp.c
1015
writel(0x19, edp->edp + DP_PHY_CFG);
drivers/phy/qualcomm/phy-qcom-edp.c
1016
writel(0x1f, edp->tx0 + TXn_HIGHZ_DRVR_EN);
drivers/phy/qualcomm/phy-qcom-edp.c
1017
writel(0x04, edp->tx0 + TXn_HIGHZ_DRVR_EN);
drivers/phy/qualcomm/phy-qcom-edp.c
1018
writel(0x00, edp->tx0 + TXn_TX_POL_INV);
drivers/phy/qualcomm/phy-qcom-edp.c
1019
writel(0x1f, edp->tx1 + TXn_HIGHZ_DRVR_EN);
drivers/phy/qualcomm/phy-qcom-edp.c
1020
writel(0x04, edp->tx1 + TXn_HIGHZ_DRVR_EN);
drivers/phy/qualcomm/phy-qcom-edp.c
1021
writel(0x00, edp->tx1 + TXn_TX_POL_INV);
drivers/phy/qualcomm/phy-qcom-edp.c
1022
writel(0x10, edp->tx0 + TXn_TX_DRV_LVL_OFFSET);
drivers/phy/qualcomm/phy-qcom-edp.c
1023
writel(0x10, edp->tx1 + TXn_TX_DRV_LVL_OFFSET);
drivers/phy/qualcomm/phy-qcom-edp.c
1024
writel(0x11, edp->tx0 + TXn_RES_CODE_LANE_OFFSET_TX0);
drivers/phy/qualcomm/phy-qcom-edp.c
1025
writel(0x11, edp->tx0 + TXn_RES_CODE_LANE_OFFSET_TX1);
drivers/phy/qualcomm/phy-qcom-edp.c
1026
writel(0x11, edp->tx1 + TXn_RES_CODE_LANE_OFFSET_TX0);
drivers/phy/qualcomm/phy-qcom-edp.c
1027
writel(0x11, edp->tx1 + TXn_RES_CODE_LANE_OFFSET_TX1);
drivers/phy/qualcomm/phy-qcom-edp.c
1029
writel(0x10, edp->tx0 + TXn_TX_EMP_POST1_LVL);
drivers/phy/qualcomm/phy-qcom-edp.c
1030
writel(0x10, edp->tx1 + TXn_TX_EMP_POST1_LVL);
drivers/phy/qualcomm/phy-qcom-edp.c
1031
writel(0x1f, edp->tx0 + TXn_TX_DRV_LVL);
drivers/phy/qualcomm/phy-qcom-edp.c
1032
writel(0x1f, edp->tx1 + TXn_TX_DRV_LVL);
drivers/phy/qualcomm/phy-qcom-edp.c
1054
writel(drvr0_en, edp->tx0 + TXn_HIGHZ_DRVR_EN);
drivers/phy/qualcomm/phy-qcom-edp.c
1055
writel(bias0_en, edp->tx0 + TXn_TRANSCEIVER_BIAS_EN);
drivers/phy/qualcomm/phy-qcom-edp.c
1056
writel(drvr1_en, edp->tx1 + TXn_HIGHZ_DRVR_EN);
drivers/phy/qualcomm/phy-qcom-edp.c
1057
writel(bias1_en, edp->tx1 + TXn_TRANSCEIVER_BIAS_EN);
drivers/phy/qualcomm/phy-qcom-edp.c
1058
writel(cfg1, edp->edp + DP_PHY_CFG_1);
drivers/phy/qualcomm/phy-qcom-edp.c
1060
writel(0x18, edp->edp + DP_PHY_CFG);
drivers/phy/qualcomm/phy-qcom-edp.c
1063
writel(0x19, edp->edp + DP_PHY_CFG);
drivers/phy/qualcomm/phy-qcom-edp.c
1080
writel(DP_PHY_PD_CTL_PSR_PWRDN, edp->edp + DP_PHY_PD_CTL);
drivers/phy/qualcomm/phy-qcom-edp.c
249
writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
drivers/phy/qualcomm/phy-qcom-edp.c
257
writel(DP_PHY_PD_CTL_PSR_PWRDN, edp->edp + DP_PHY_PD_CTL);
drivers/phy/qualcomm/phy-qcom-edp.c
260
writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
drivers/phy/qualcomm/phy-qcom-edp.c
273
writel(0xfc, edp->edp + DP_PHY_MODE);
drivers/phy/qualcomm/phy-qcom-edp.c
276
writel(aux_cfg[i], edp->edp + DP_PHY_AUX_CFG(i));
drivers/phy/qualcomm/phy-qcom-edp.c
278
writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
drivers/phy/qualcomm/phy-qcom-edp.c
326
writel(ldo_config, edp->tx0 + TXn_LDO_CONFIG);
drivers/phy/qualcomm/phy-qcom-edp.c
327
writel(swing, edp->tx0 + TXn_TX_DRV_LVL);
drivers/phy/qualcomm/phy-qcom-edp.c
328
writel(emph, edp->tx0 + TXn_TX_EMP_POST1_LVL);
drivers/phy/qualcomm/phy-qcom-edp.c
330
writel(ldo_config, edp->tx1 + TXn_LDO_CONFIG);
drivers/phy/qualcomm/phy-qcom-edp.c
331
writel(swing, edp->tx1 + TXn_TX_DRV_LVL);
drivers/phy/qualcomm/phy-qcom-edp.c
332
writel(emph, edp->tx1 + TXn_TX_EMP_POST1_LVL);
drivers/phy/qualcomm/phy-qcom-edp.c
392
writel(vco_div, edp->edp + DP_PHY_VCO_DIV);
drivers/phy/qualcomm/phy-qcom-edp.c
401
writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
drivers/phy/qualcomm/phy-qcom-edp.c
405
writel(0xfc, edp->edp + DP_PHY_MODE);
drivers/phy/qualcomm/phy-qcom-edp.c
415
writel(0x20, edp->pll + QSERDES_V4_COM_RESETSM_CNTRL);
drivers/phy/qualcomm/phy-qcom-edp.c
429
writel(0x17, edp->pll + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN);
drivers/phy/qualcomm/phy-qcom-edp.c
458
writel(0x01, edp->pll + QSERDES_V4_COM_SSC_EN_CENTER);
drivers/phy/qualcomm/phy-qcom-edp.c
459
writel(0x00, edp->pll + QSERDES_V4_COM_SSC_ADJ_PER1);
drivers/phy/qualcomm/phy-qcom-edp.c
460
writel(0x36, edp->pll + QSERDES_V4_COM_SSC_PER1);
drivers/phy/qualcomm/phy-qcom-edp.c
461
writel(0x01, edp->pll + QSERDES_V4_COM_SSC_PER2);
drivers/phy/qualcomm/phy-qcom-edp.c
462
writel(step1, edp->pll + QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
463
writel(step2, edp->pll + QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
520
writel(0x01, edp->pll + QSERDES_V4_COM_SVS_MODE_CLK_SEL);
drivers/phy/qualcomm/phy-qcom-edp.c
521
writel(0x0b, edp->pll + QSERDES_V4_COM_SYSCLK_EN_SEL);
drivers/phy/qualcomm/phy-qcom-edp.c
522
writel(0x02, edp->pll + QSERDES_V4_COM_SYS_CLK_CTRL);
drivers/phy/qualcomm/phy-qcom-edp.c
523
writel(0x0c, edp->pll + QSERDES_V4_COM_CLK_ENABLE1);
drivers/phy/qualcomm/phy-qcom-edp.c
524
writel(0x06, edp->pll + QSERDES_V4_COM_SYSCLK_BUF_ENABLE);
drivers/phy/qualcomm/phy-qcom-edp.c
525
writel(0x30, edp->pll + QSERDES_V4_COM_CLK_SELECT);
drivers/phy/qualcomm/phy-qcom-edp.c
526
writel(hsclk_sel, edp->pll + QSERDES_V4_COM_HSCLK_SEL);
drivers/phy/qualcomm/phy-qcom-edp.c
527
writel(0x0f, edp->pll + QSERDES_V4_COM_PLL_IVCO);
drivers/phy/qualcomm/phy-qcom-edp.c
528
writel(0x08, edp->pll + QSERDES_V4_COM_LOCK_CMP_EN);
drivers/phy/qualcomm/phy-qcom-edp.c
529
writel(0x36, edp->pll + QSERDES_V4_COM_PLL_CCTRL_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
530
writel(0x16, edp->pll + QSERDES_V4_COM_PLL_RCTRL_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
531
writel(0x06, edp->pll + QSERDES_V4_COM_CP_CTRL_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
532
writel(dec_start_mode0, edp->pll + QSERDES_V4_COM_DEC_START_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
533
writel(0x00, edp->pll + QSERDES_V4_COM_DIV_FRAC_START1_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
534
writel(div_frac_start2_mode0, edp->pll + QSERDES_V4_COM_DIV_FRAC_START2_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
535
writel(div_frac_start3_mode0, edp->pll + QSERDES_V4_COM_DIV_FRAC_START3_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
536
writel(0x02, edp->pll + QSERDES_V4_COM_CMN_CONFIG);
drivers/phy/qualcomm/phy-qcom-edp.c
537
writel(0x3f, edp->pll + QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
538
writel(0x00, edp->pll + QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
539
writel(0x00, edp->pll + QSERDES_V4_COM_VCO_TUNE_MAP);
drivers/phy/qualcomm/phy-qcom-edp.c
540
writel(lock_cmp1_mode0, edp->pll + QSERDES_V4_COM_LOCK_CMP1_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
541
writel(lock_cmp2_mode0, edp->pll + QSERDES_V4_COM_LOCK_CMP2_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
543
writel(0x0a, edp->pll + QSERDES_V4_COM_BG_TIMER);
drivers/phy/qualcomm/phy-qcom-edp.c
544
writel(0x14, edp->pll + QSERDES_V4_COM_CORECLK_DIV_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
545
writel(0x00, edp->pll + QSERDES_V4_COM_VCO_TUNE_CTRL);
drivers/phy/qualcomm/phy-qcom-edp.c
546
writel(0x17, edp->pll + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN);
drivers/phy/qualcomm/phy-qcom-edp.c
547
writel(0x0f, edp->pll + QSERDES_V4_COM_CORE_CLK_EN);
drivers/phy/qualcomm/phy-qcom-edp.c
548
writel(0xa0, edp->pll + QSERDES_V4_COM_VCO_TUNE1_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
549
writel(0x03, edp->pll + QSERDES_V4_COM_VCO_TUNE2_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
596
writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
drivers/phy/qualcomm/phy-qcom-edp.c
600
writel(0xfc, edp->edp + DP_PHY_MODE);
drivers/phy/qualcomm/phy-qcom-edp.c
610
writel(0x20, edp->pll + QSERDES_V6_COM_RESETSM_CNTRL);
drivers/phy/qualcomm/phy-qcom-edp.c
619
writel(0x1f, edp->pll + QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN);
drivers/phy/qualcomm/phy-qcom-edp.c
648
writel(0x01, edp->pll + QSERDES_V6_COM_SSC_EN_CENTER);
drivers/phy/qualcomm/phy-qcom-edp.c
649
writel(0x00, edp->pll + QSERDES_V6_COM_SSC_ADJ_PER1);
drivers/phy/qualcomm/phy-qcom-edp.c
650
writel(0x36, edp->pll + QSERDES_V6_COM_SSC_PER1);
drivers/phy/qualcomm/phy-qcom-edp.c
651
writel(0x01, edp->pll + QSERDES_V6_COM_SSC_PER2);
drivers/phy/qualcomm/phy-qcom-edp.c
652
writel(step1, edp->pll + QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
653
writel(step2, edp->pll + QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
720
writel(0x01, edp->pll + QSERDES_V6_COM_SVS_MODE_CLK_SEL);
drivers/phy/qualcomm/phy-qcom-edp.c
721
writel(0x0b, edp->pll + QSERDES_V6_COM_SYSCLK_EN_SEL);
drivers/phy/qualcomm/phy-qcom-edp.c
722
writel(0x02, edp->pll + QSERDES_V6_COM_SYS_CLK_CTRL);
drivers/phy/qualcomm/phy-qcom-edp.c
723
writel(0x0c, edp->pll + QSERDES_V6_COM_CLK_ENABLE1);
drivers/phy/qualcomm/phy-qcom-edp.c
724
writel(0x06, edp->pll + QSERDES_V6_COM_SYSCLK_BUF_ENABLE);
drivers/phy/qualcomm/phy-qcom-edp.c
725
writel(0x30, edp->pll + QSERDES_V6_COM_CLK_SELECT);
drivers/phy/qualcomm/phy-qcom-edp.c
726
writel(hsclk_sel, edp->pll + QSERDES_V6_COM_HSCLK_SEL_1);
drivers/phy/qualcomm/phy-qcom-edp.c
727
writel(0x07, edp->pll + QSERDES_V6_COM_PLL_IVCO);
drivers/phy/qualcomm/phy-qcom-edp.c
728
writel(0x08, edp->pll + QSERDES_V6_COM_LOCK_CMP_EN);
drivers/phy/qualcomm/phy-qcom-edp.c
729
writel(0x36, edp->pll + QSERDES_V6_COM_PLL_CCTRL_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
730
writel(0x16, edp->pll + QSERDES_V6_COM_PLL_RCTRL_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
731
writel(0x06, edp->pll + QSERDES_V6_COM_CP_CTRL_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
732
writel(dec_start_mode0, edp->pll + QSERDES_V6_COM_DEC_START_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
733
writel(0x00, edp->pll + QSERDES_V6_COM_DIV_FRAC_START1_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
734
writel(div_frac_start2_mode0, edp->pll + QSERDES_V6_COM_DIV_FRAC_START2_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
735
writel(div_frac_start3_mode0, edp->pll + QSERDES_V6_COM_DIV_FRAC_START3_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
736
writel(0x12, edp->pll + QSERDES_V6_COM_CMN_CONFIG_1);
drivers/phy/qualcomm/phy-qcom-edp.c
737
writel(0x3f, edp->pll + QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
738
writel(0x00, edp->pll + QSERDES_V6_COM_INTEGLOOP_GAIN1_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
739
writel(0x00, edp->pll + QSERDES_V6_COM_VCO_TUNE_MAP);
drivers/phy/qualcomm/phy-qcom-edp.c
740
writel(lock_cmp1_mode0, edp->pll + QSERDES_V6_COM_LOCK_CMP1_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
741
writel(lock_cmp2_mode0, edp->pll + QSERDES_V6_COM_LOCK_CMP2_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
743
writel(0x0a, edp->pll + QSERDES_V6_COM_BG_TIMER);
drivers/phy/qualcomm/phy-qcom-edp.c
744
writel(0x14, edp->pll + QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
745
writel(0x00, edp->pll + QSERDES_V6_COM_VCO_TUNE_CTRL);
drivers/phy/qualcomm/phy-qcom-edp.c
746
writel(0x1f, edp->pll + QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN);
drivers/phy/qualcomm/phy-qcom-edp.c
747
writel(0x0f, edp->pll + QSERDES_V6_COM_CORE_CLK_EN);
drivers/phy/qualcomm/phy-qcom-edp.c
748
writel(0xa0, edp->pll + QSERDES_V6_COM_VCO_TUNE1_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
749
writel(0x03, edp->pll + QSERDES_V6_COM_VCO_TUNE2_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
751
writel(code1_mode0, edp->pll + QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
752
writel(code2_mode0, edp->pll + QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
797
writel(0x01, edp->pll + DP_QSERDES_V8_COM_SSC_EN_CENTER);
drivers/phy/qualcomm/phy-qcom-edp.c
798
writel(0x00, edp->pll + DP_QSERDES_V8_COM_SSC_ADJ_PER1);
drivers/phy/qualcomm/phy-qcom-edp.c
799
writel(0x6b, edp->pll + DP_QSERDES_V8_COM_SSC_PER1);
drivers/phy/qualcomm/phy-qcom-edp.c
800
writel(0x02, edp->pll + DP_QSERDES_V8_COM_SSC_PER2);
drivers/phy/qualcomm/phy-qcom-edp.c
801
writel(step1, edp->pll + DP_QSERDES_V8_COM_SSC_STEP_SIZE1_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
802
writel(step2, edp->pll + DP_QSERDES_V8_COM_SSC_STEP_SIZE2_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
859
writel(0x01, edp->pll + DP_QSERDES_V8_COM_SVS_MODE_CLK_SEL);
drivers/phy/qualcomm/phy-qcom-edp.c
860
writel(0x3b, edp->pll + DP_QSERDES_V8_COM_SYSCLK_EN_SEL);
drivers/phy/qualcomm/phy-qcom-edp.c
861
writel(0x02, edp->pll + DP_QSERDES_V8_COM_SYS_CLK_CTRL);
drivers/phy/qualcomm/phy-qcom-edp.c
862
writel(0x0c, edp->pll + DP_QSERDES_V8_COM_CLK_ENABLE1);
drivers/phy/qualcomm/phy-qcom-edp.c
863
writel(0x06, edp->pll + DP_QSERDES_V8_COM_SYSCLK_BUF_ENABLE);
drivers/phy/qualcomm/phy-qcom-edp.c
864
writel(0x30, edp->pll + DP_QSERDES_V8_COM_CLK_SELECT);
drivers/phy/qualcomm/phy-qcom-edp.c
865
writel(hsclk_sel, edp->pll + DP_QSERDES_V8_COM_HSCLK_SEL_1);
drivers/phy/qualcomm/phy-qcom-edp.c
866
writel(0x07, edp->pll + DP_QSERDES_V8_COM_PLL_IVCO);
drivers/phy/qualcomm/phy-qcom-edp.c
867
writel(0x00, edp->pll + DP_QSERDES_V8_COM_LOCK_CMP_EN);
drivers/phy/qualcomm/phy-qcom-edp.c
868
writel(0x36, edp->pll + DP_QSERDES_V8_COM_PLL_CCTRL_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
869
writel(0x16, edp->pll + DP_QSERDES_V8_COM_PLL_RCTRL_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
870
writel(0x06, edp->pll + DP_QSERDES_V8_COM_CP_CTRL_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
871
writel(dec_start_mode0, edp->pll + DP_QSERDES_V8_COM_DEC_START_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
872
writel(0x00, edp->pll + DP_QSERDES_V8_COM_DIV_FRAC_START1_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
873
writel(div_frac_start2_mode0, edp->pll + DP_QSERDES_V8_COM_DIV_FRAC_START2_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
874
writel(div_frac_start3_mode0, edp->pll + DP_QSERDES_V8_COM_DIV_FRAC_START3_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
875
writel(0x96, edp->pll + DP_QSERDES_V8_COM_CMN_CONFIG_1);
drivers/phy/qualcomm/phy-qcom-edp.c
876
writel(0x3f, edp->pll + DP_QSERDES_V8_COM_INTEGLOOP_GAIN0_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
877
writel(0x00, edp->pll + DP_QSERDES_V8_COM_INTEGLOOP_GAIN1_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
878
writel(0x00, edp->pll + DP_QSERDES_V8_COM_VCO_TUNE_MAP);
drivers/phy/qualcomm/phy-qcom-edp.c
879
writel(lock_cmp1_mode0, edp->pll + DP_QSERDES_V8_COM_LOCK_CMP1_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
880
writel(lock_cmp2_mode0, edp->pll + DP_QSERDES_V8_COM_LOCK_CMP2_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
882
writel(0x0a, edp->pll + DP_QSERDES_V8_COM_BG_TIMER);
drivers/phy/qualcomm/phy-qcom-edp.c
883
writel(0x0a, edp->pll + DP_QSERDES_V8_COM_CORECLK_DIV_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
884
writel(0x00, edp->pll + DP_QSERDES_V8_COM_VCO_TUNE_CTRL);
drivers/phy/qualcomm/phy-qcom-edp.c
885
writel(0x1f, edp->pll + DP_QSERDES_V8_COM_BIAS_EN_CLKBUFLR_EN);
drivers/phy/qualcomm/phy-qcom-edp.c
886
writel(0x00, edp->pll + DP_QSERDES_V8_COM_CORE_CLK_EN);
drivers/phy/qualcomm/phy-qcom-edp.c
887
writel(0xa0, edp->pll + DP_QSERDES_V8_COM_VCO_TUNE1_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
888
writel(0x01, edp->pll + DP_QSERDES_V8_COM_VCO_TUNE2_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
890
writel(code1_mode0, edp->pll + DP_QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE1_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
891
writel(code2_mode0, edp->pll + DP_QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE2_MODE0);
drivers/phy/qualcomm/phy-qcom-edp.c
901
writel(0x20, edp->pll + DP_QSERDES_V8_COM_RESETSM_CNTRL);
drivers/phy/qualcomm/phy-qcom-edp.c
909
writel(0x3f, edp->pll + DP_QSERDES_V8_COM_CLK_FWD_CONFIG_1);
drivers/phy/qualcomm/phy-qcom-edp.c
917
writel(0x1f, edp->pll + DP_QSERDES_V8_COM_BIAS_EN_CLKBUFLR_EN);
drivers/phy/qualcomm/phy-qcom-edp.c
926
writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
drivers/phy/qualcomm/phy-qcom-edp.c
930
writel(0xfc, edp->edp + DP_PHY_MODE);
drivers/phy/qualcomm/phy-qcom-edp.c
969
writel(ldo_config, edp->tx0 + TXn_LDO_CONFIG);
drivers/phy/qualcomm/phy-qcom-edp.c
970
writel(ldo_config, edp->tx1 + TXn_LDO_CONFIG);
drivers/phy/qualcomm/phy-qcom-edp.c
971
writel(0x00, edp->tx0 + TXn_LANE_MODE_1);
drivers/phy/qualcomm/phy-qcom-edp.c
972
writel(0x00, edp->tx1 + TXn_LANE_MODE_1);
drivers/phy/qualcomm/phy-qcom-edp.c
985
writel(0x05, edp->edp + DP_PHY_TX0_TX1_LANE_CTL);
drivers/phy/qualcomm/phy-qcom-edp.c
986
writel(0x05, edp->edp + DP_PHY_TX2_TX3_LANE_CTL);
drivers/phy/qualcomm/phy-qcom-edp.c
989
writel(0x03, edp->tx0 + TXn_TRANSCEIVER_BIAS_EN);
drivers/phy/qualcomm/phy-qcom-edp.c
990
writel(0x0f, edp->tx0 + TXn_CLKBUF_ENABLE);
drivers/phy/qualcomm/phy-qcom-edp.c
991
writel(0x03, edp->tx0 + TXn_RESET_TSYNC_EN);
drivers/phy/qualcomm/phy-qcom-edp.c
992
writel(0x01, edp->tx0 + TXn_TRAN_DRVR_EMP_EN);
drivers/phy/qualcomm/phy-qcom-edp.c
993
writel(0x04, edp->tx0 + TXn_TX_BAND);
drivers/phy/qualcomm/phy-qcom-edp.c
996
writel(0x03, edp->tx1 + TXn_TRANSCEIVER_BIAS_EN);
drivers/phy/qualcomm/phy-qcom-edp.c
997
writel(0x0f, edp->tx1 + TXn_CLKBUF_ENABLE);
drivers/phy/qualcomm/phy-qcom-edp.c
998
writel(0x03, edp->tx1 + TXn_RESET_TSYNC_EN);
drivers/phy/qualcomm/phy-qcom-edp.c
999
writel(0x01, edp->tx1 + TXn_TRAN_DRVR_EMP_EN);
drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c
151
writel(write_val, phy_dwc3->base + offset);
drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c
180
writel(addr, phy_dwc3->base + CR_PROTOCOL_DATA_IN_REG);
drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c
181
writel(SS_CR_CAP_ADDR_REG,
drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c
188
writel(val, phy_dwc3->base + CR_PROTOCOL_DATA_IN_REG);
drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c
189
writel(SS_CR_CAP_DATA_REG,
drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c
196
writel(SS_CR_WRITE_REG, phy_dwc3->base + CR_PROTOCOL_WRITE_REG);
drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c
218
writel(addr, phy_dwc3->base + CR_PROTOCOL_DATA_IN_REG);
drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c
219
writel(SS_CR_CAP_ADDR_REG,
drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c
231
writel(SS_CR_READ_REG, phy_dwc3->base + CR_PROTOCOL_READ_REG);
drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c
240
writel(SS_CR_READ_REG, phy_dwc3->base + CR_PROTOCOL_READ_REG);
drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c
282
writel(val, phy_dwc3->base + HSUSB_PHY_CTRL_REG);
drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c
286
writel(HSUSB_GCFG_XHCI_REV, phy_dwc3->base + QSCRATCH_GENERAL_CFG);
drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c
319
writel(data | SSUSB_CTRL_SS_PHY_RESET,
drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c
322
writel(data, phy_dwc3->base + SSUSB_PHY_CTRL_REG);
drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c
330
writel(data, phy_dwc3->base + SSUSB_PHY_CTRL_REG);
drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c
336
writel(data, phy_dwc3->base + SSUSB_PHY_CTRL_REG);
drivers/phy/qualcomm/phy-qcom-m31-eusb2.c
138
writel(write_val, base + offset);
drivers/phy/qualcomm/phy-qcom-m31.c
237
writel(0x0, qphy->base + USB2PHY_PORT_UTMI_CTRL2);
drivers/phy/qualcomm/phy-qcom-m31.c
240
writel(POWER_UP, qphy->base + USB2PHY_PORT_POWERDOWN);
drivers/phy/qualcomm/phy-qcom-m31.c
244
writel(regs[i].val, qphy->base + regs[i].off);
drivers/phy/qualcomm/phy-qcom-pcie2.c
102
writel(val, qphy->base + PCIE20_PARF_PCS_SWING_CTRL1);
drivers/phy/qualcomm/phy-qcom-pcie2.c
107
writel(val, qphy->base + PCIE20_PARF_PCS_SWING_CTRL2);
drivers/phy/qualcomm/phy-qcom-pcie2.c
113
writel(val, qphy->base + PCIE20_PARF_PCS_DEEMPH1);
drivers/phy/qualcomm/phy-qcom-pcie2.c
118
writel(val, qphy->base + PCIE20_PARF_PCS_DEEMPH2);
drivers/phy/qualcomm/phy-qcom-pcie2.c
123
writel(val, qphy->base + PCIE20_PARF_PCS_DEEMPH3);
drivers/phy/qualcomm/phy-qcom-pcie2.c
129
writel(val, qphy->base + PCIE20_PARF_CONFIGBITS);
drivers/phy/qualcomm/phy-qcom-pcie2.c
135
writel(val, qphy->base + PCIE20_PARF_PHY_CTRL3);
drivers/phy/qualcomm/phy-qcom-pcie2.c
140
writel(val, qphy->base + PCIE20_PARF_PCS_CTRL);
drivers/phy/qualcomm/phy-qcom-pcie2.c
145
writel(val, qphy->base + PCIE2_PHY_RESET_CTRL);
drivers/phy/qualcomm/phy-qcom-pcie2.c
179
writel(val, qphy->base + PCIE2_PHY_RESET_CTRL);
drivers/phy/qualcomm/phy-qcom-pcie2.c
77
writel(val, qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL2);
drivers/phy/qualcomm/phy-qcom-pcie2.c
84
writel(val, qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL2);
drivers/phy/qualcomm/phy-qcom-pcie2.c
89
writel(val, qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL3);
drivers/phy/qualcomm/phy-qcom-pcie2.c
96
writel(val, qphy->base + PCIE2_PHY_RESET_CTRL);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
2340
writel(reg, base + offset);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
2352
writel(reg, base + offset);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3070
writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3075
writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX |
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3079
writel(DP_PHY_PD_CTL_PSR_PWRDN, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3081
writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3087
writel(QSERDES_V3_COM_BIAS_EN |
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3093
writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG0);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3094
writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3095
writel(0x24, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3096
writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG3);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3097
writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG4);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3098
writel(0x26, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG5);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3099
writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG6);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3100
writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG7);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3101
writel(0xbb, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG8);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3102
writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG9);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3105
writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3140
writel(voltage_swing_cfg, qmp->dp_tx + cfg->regs[QPHY_TX_TX_DRV_LVL]);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3141
writel(pre_emphasis_cfg, qmp->dp_tx + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3142
writel(voltage_swing_cfg, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_DRV_LVL]);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3143
writel(pre_emphasis_cfg, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3164
writel(drvr_en, qmp->dp_tx + QSERDES_V3_TX_HIGHZ_DRVR_EN);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3165
writel(bias_en, qmp->dp_tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3166
writel(drvr_en, qmp->dp_tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3167
writel(bias_en, qmp->dp_tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3184
writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3187
writel(0x4c, qmp->dp_dp_phy + QSERDES_DP_PHY_MODE);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3189
writel(0x5c, qmp->dp_dp_phy + QSERDES_DP_PHY_MODE);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3222
writel(phy_vco_div, qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_VCO_DIV]);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3238
writel(0x05, qmp->dp_dp_phy + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3239
writel(0x05, qmp->dp_dp_phy + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3245
writel(0x04, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3246
writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3247
writel(0x05, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3248
writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3249
writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3251
writel(0x20, qmp->dp_serdes + cfg->regs[QPHY_COM_RESETSM_CNTRL]);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3260
writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3269
writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3271
writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3293
writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3302
writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3307
writel(0x17, qmp->dp_serdes + cfg->regs[QPHY_COM_BIAS_EN_CLKBUFLR_EN]);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3309
writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG0);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3310
writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3311
writel(0xa4, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3312
writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG3);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3313
writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG4);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3314
writel(0x26, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG5);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3315
writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG6);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3316
writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG7);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3317
writel(0xb7, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG8);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3318
writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG9);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3321
writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3331
writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3336
writel(0x1c, qmp->dp_serdes + cfg->regs[QPHY_COM_BIAS_EN_CLKBUFLR_EN]);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3338
writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG0);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3339
writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3340
writel(0x06, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3341
writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG3);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3342
writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG4);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3343
writel(0x26, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG5);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3344
writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG6);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3345
writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG7);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3346
writel(0xb7, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG8);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3347
writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG9);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3350
writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3361
writel(0x27, qmp->dp_tx + cfg->regs[QPHY_TX_TX_DRV_LVL]);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3362
writel(0x27, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_DRV_LVL]);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3364
writel(0x20, qmp->dp_tx + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3365
writel(0x20, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3398
writel(phy_vco_div, qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_VCO_DIV]);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3401
writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3403
writel(0x04, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_AUXLESS_SETUP_CYC);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3404
writel(0x08, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_AUXLESS_SILENCE_CYC);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3405
writel(0x08, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_LFPS_CYC);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3406
writel(0x11, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_LFPS_PERIOD);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3408
writel(0x3e, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_TSYNC_OVRD);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3409
writel(0x05, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_TX2_TX3_LANE_CTL);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3410
writel(0x05, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_TX0_TX1_LANE_CTL);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3411
writel(0x01, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_AUXLESS_CFG1);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3412
writel(0x11, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_LFPS_PERIOD);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3413
writel(0x1f, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_LN0_DRV_LVL);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3414
writel(0x1f, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_LN1_DRV_LVL);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3428
writel(0x0f, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG_1);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3432
writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3433
writel(0xa4, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3435
writel(0x05, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3436
writel(0x05, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3442
writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3443
writel(0x05, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3444
writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3445
writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3447
writel(0x20, qmp->dp_serdes + cfg->regs[QPHY_COM_RESETSM_CNTRL]);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3470
writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3524
writel(drvr0_en, qmp->dp_tx + cfg->regs[QPHY_TX_HIGHZ_DRVR_EN]);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3525
writel(bias0_en, qmp->dp_tx + cfg->regs[QPHY_TX_TRANSCEIVER_BIAS_EN]);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3526
writel(drvr1_en, qmp->dp_tx2 + cfg->regs[QPHY_TX_HIGHZ_DRVR_EN]);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3527
writel(bias1_en, qmp->dp_tx2 + cfg->regs[QPHY_TX_TRANSCEIVER_BIAS_EN]);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3529
writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3531
writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3540
writel(0x0a, qmp->dp_tx + cfg->regs[QPHY_TX_TX_POL_INV]);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3541
writel(0x0a, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_POL_INV]);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3543
writel(0x27, qmp->dp_tx + cfg->regs[QPHY_TX_TX_DRV_LVL]);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3544
writel(0x27, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_DRV_LVL]);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3546
writel(0x20, qmp->dp_tx + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3547
writel(0x20, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3582
writel(drvr0_en, qmp->dp_tx + cfg->regs[QPHY_TX_HIGHZ_DRVR_EN]);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3583
writel(bias0_en, qmp->dp_tx + cfg->regs[QPHY_TX_TRANSCEIVER_BIAS_EN]);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3584
writel(drvr1_en, qmp->dp_tx2 + cfg->regs[QPHY_TX_HIGHZ_DRVR_EN]);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3585
writel(bias1_en, qmp->dp_tx2 + cfg->regs[QPHY_TX_TRANSCEIVER_BIAS_EN]);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3587
writel(0x08, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3589
writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3599
writel(0x00, qmp->dp_tx + cfg->regs[QPHY_TX_TX_DRV_LVL]);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3600
writel(0x00, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_DRV_LVL]);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3602
writel(0x2b, qmp->dp_tx + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3603
writel(0x2b, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3621
writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3715
writel(val, com + QPHY_V3_DP_COM_TYPEC_CTRL);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3719
writel(USB3_MODE | DP_MODE, com + QPHY_V3_DP_COM_PHY_MODE_CTRL);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3728
writel(DP_MODE, com + QPHY_V3_DP_COM_PHY_MODE_CTRL);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3736
writel(USB3_MODE, com + QPHY_V3_DP_COM_PHY_MODE_CTRL);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
3848
writel(DP_PHY_PD_CTL_PSR_PWRDN, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL);
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
4508
writel(DP_PHY_PD_CTL_PSR_PWRDN, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL);
drivers/phy/qualcomm/phy-qcom-qmp-common.h
52
writel(t->val, base + t->offset);
drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
227
writel(reg, base + offset);
drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
239
writel(reg, base + offset);
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
3353
writel(reg, base + offset);
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
3365
writel(reg, base + offset);
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
1210
writel(reg, base + offset);
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
1222
writel(reg, base + offset);
drivers/phy/qualcomm/phy-qcom-qmp-usb-legacy.c
556
writel(reg, base + offset);
drivers/phy/qualcomm/phy-qcom-qmp-usb-legacy.c
568
writel(reg, base + offset);
drivers/phy/qualcomm/phy-qcom-qmp-usb-legacy.c
716
writel(t->val, base + t->offset);
drivers/phy/qualcomm/phy-qcom-qmp-usb.c
1448
writel(reg, base + offset);
drivers/phy/qualcomm/phy-qcom-qmp-usb.c
1460
writel(reg, base + offset);
drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
1008
writel(val, qmp->pcs_misc);
drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
1293
writel(DP_PHY_PD_CTL_PSR_PWRDN, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL);
drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
483
writel(reg, base + offset);
drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
495
writel(reg, base + offset);
drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
749
writel(DP_PHY_PD_CTL_AUX_PWRDN |
drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
754
writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
759
writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG0);
drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
760
writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1);
drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
761
writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2);
drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
762
writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG3);
drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
763
writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG4);
drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
764
writel(0x26, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG5);
drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
765
writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG6);
drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
766
writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG7);
drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
767
writel(0xbb, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG8);
drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
768
writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG9);
drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
771
writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
812
writel(voltage_swing_cfg, tx + QSERDES_V2_TX_TX_DRV_LVL);
drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
813
writel(pre_emphasis_cfg, tx + QSERDES_V2_TX_TX_EMP_POST1_LVL);
drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
814
writel(voltage_swing_cfg, tx2 + QSERDES_V2_TX_TX_DRV_LVL);
drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
815
writel(pre_emphasis_cfg, tx2 + QSERDES_V2_TX_TX_EMP_POST1_LVL);
drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
828
writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL);
drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
831
writel(0xc9, qmp->dp_dp_phy + QSERDES_DP_PHY_MODE);
drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
833
writel(0xd9, qmp->dp_dp_phy + QSERDES_DP_PHY_MODE);
drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
859
writel(phy_vco_div, qmp->dp_dp_phy + QSERDES_V2_DP_PHY_VCO_DIV);
drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
874
writel(0x2a, tx + QSERDES_V2_TX_TX_DRV_LVL);
drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
875
writel(0x20, tx + QSERDES_V2_TX_TX_EMP_POST1_LVL);
drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
876
writel(0x2a, tx2 + QSERDES_V2_TX_TX_DRV_LVL);
drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
877
writel(0x20, tx2 + QSERDES_V2_TX_TX_EMP_POST1_LVL);
drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
880
writel(0xc4, tx + QSERDES_V2_TX_LANE_MODE_1);
drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
881
writel(0xc4, tx2 + QSERDES_V2_TX_LANE_MODE_1);
drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
883
writel(0xc6, tx + QSERDES_V2_TX_LANE_MODE_1);
drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
884
writel(0xc6, tx2 + QSERDES_V2_TX_LANE_MODE_1);
drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
897
writel(0x05, qmp->dp_dp_phy + QSERDES_V2_DP_PHY_TX0_TX1_LANE_CTL);
drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
898
writel(0x05, qmp->dp_dp_phy + QSERDES_V2_DP_PHY_TX2_TX3_LANE_CTL);
drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
904
writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
905
writel(0x05, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
906
writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
907
writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
909
writel(0x20, qmp->dp_serdes + QSERDES_COM_RESETSM_CNTRL);
drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
938
writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
958
writel(0x3f, qmp->dp_tx + QSERDES_V2_TX_TRANSCEIVER_BIAS_EN);
drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
959
writel(0x10, qmp->dp_tx + QSERDES_V2_TX_HIGHZ_DRVR_EN);
drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
960
writel(0x0a, qmp->dp_tx + QSERDES_V2_TX_TX_POL_INV);
drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
961
writel(0x3f, qmp->dp_tx2 + QSERDES_V2_TX_TRANSCEIVER_BIAS_EN);
drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
962
writel(0x10, qmp->dp_tx2 + QSERDES_V2_TX_HIGHZ_DRVR_EN);
drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
963
writel(0x0a, qmp->dp_tx2 + QSERDES_V2_TX_TX_POL_INV);
drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
965
writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
966
writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
989
writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1);
drivers/phy/qualcomm/phy-qcom-qusb2.c
481
writel(reg, base + offset);
drivers/phy/qualcomm/phy-qcom-qusb2.c
493
writel(reg, base + offset);
drivers/phy/qualcomm/phy-qcom-qusb2.c
505
writel(reg, base + offset);
drivers/phy/qualcomm/phy-qcom-qusb2.c
520
writel(tbl[i].val, base + regs[tbl[i].offset]);
drivers/phy/qualcomm/phy-qcom-qusb2.c
522
writel(tbl[i].val, base + tbl[i].offset);
drivers/phy/qualcomm/phy-qcom-qusb2.c
669
writel(intr_mask, qphy->base + cfg->regs[QUSB2PHY_INTR_CTRL]);
drivers/phy/qualcomm/phy-qcom-qusb2.c
730
writel(0x0, qphy->base + cfg->regs[QUSB2PHY_INTR_CTRL]);
drivers/phy/qualcomm/phy-qcom-qusb2.c
865
writel(val, qphy->base + QUSB2PHY_PLL_TEST);
drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c
152
writel(init_seq[i].val, base + init_seq[i].offset);
drivers/phy/qualcomm/phy-qcom-usb-ss.c
47
writel((readl(addr) & ~mask) | val, addr);
drivers/phy/ralink/phy-ralink-usb.c
63
writel(val, phy->base + reg);
drivers/phy/realtek/phy-rtk-usb2.c
171
writel(val, reg_gusb2phyacc0);
drivers/phy/realtek/phy-rtk-usb2.c
178
writel(val, reg_gusb2phyacc0);
drivers/phy/realtek/phy-rtk-usb2.c
197
writel((u32)data << shift_bits, reg_wrap_vstatus);
drivers/phy/realtek/phy-rtk-usb2.c
206
writel(val, reg_gusb2phyacc0);
drivers/phy/realtek/phy-rtk-usb2.c
214
writel(val, reg_gusb2phyacc0);
drivers/phy/realtek/phy-rtk-usb3.c
125
writel(tmp, phy_reg->reg_mdio_ctl);
drivers/phy/realtek/phy-rtk-usb3.c
143
writel(val, phy_reg->reg_mdio_ctl);
drivers/phy/renesas/phy-rcar-gen2.c
134
writel(value, base + USBHS_UGCTRL);
drivers/phy/renesas/phy-rcar-gen2.c
145
writel(value, base + USBHS_UGCTRL);
drivers/phy/renesas/phy-rcar-gen2.c
177
writel(value, base + USBHS_UGCTRL);
drivers/phy/renesas/phy-rcar-gen2.c
185
writel(value, base + USBHS_UGCTRL);
drivers/phy/renesas/phy-rcar-gen2.c
205
writel(value, base + USBHS_UGCTRL);
drivers/phy/renesas/phy-rcar-gen2.c
239
writel(value, base + USBHS_UGCTRL);
drivers/phy/renesas/phy-rcar-gen2.c
99
writel(ugctrl2, drv->base + USBHS_UGCTRL2);
drivers/phy/renesas/phy-rcar-gen3-pcie.c
40
writel(value, base + reg);
drivers/phy/renesas/phy-rcar-gen3-usb2.c
193
writel(val, usb2_base + USB2_COMMCTRL);
drivers/phy/renesas/phy-rcar-gen3-usb2.c
207
writel(val, usb2_base + USB2_LINECTRL1);
drivers/phy/renesas/phy-rcar-gen3-usb2.c
223
writel(val, usb2_base + vbus_ctrl_reg);
drivers/phy/renesas/phy-rcar-gen3-usb2.c
258
writel(val, usb2_base + USB2_OBINTEN);
drivers/phy/renesas/phy-rcar-gen3-usb2.c
287
writel(val | USB2_LINECTRL1_OPMODE_NODRV, usb2_base + USB2_LINECTRL1);
drivers/phy/renesas/phy-rcar-gen3-usb2.c
294
writel(val & ~USB2_LINECTRL1_OPMODE_NODRV, usb2_base + USB2_LINECTRL1);
drivers/phy/renesas/phy-rcar-gen3-usb2.c
458
writel(val, usb2_base + USB2_LINECTRL1);
drivers/phy/renesas/phy-rcar-gen3-usb2.c
464
writel(val, usb2_base + USB2_VBCTRL);
drivers/phy/renesas/phy-rcar-gen3-usb2.c
466
writel(val | USB2_ADPCTRL_IDPULLUP | USB2_ADPCTRL_DRVVBUS,
drivers/phy/renesas/phy-rcar-gen3-usb2.c
471
writel(val | USB2_VBCTRL_DRVVBUSSEL, usb2_base + USB2_VBCTRL);
drivers/phy/renesas/phy-rcar-gen3-usb2.c
473
writel(val | USB2_ADPCTRL_IDPULLUP, usb2_base + USB2_ADPCTRL);
drivers/phy/renesas/phy-rcar-gen3-usb2.c
478
writel(0xffffffff, usb2_base + USB2_OBINTSTA);
drivers/phy/renesas/phy-rcar-gen3-usb2.c
479
writel(ch->phy_data->obint_enable_bits, usb2_base + USB2_OBINTEN);
drivers/phy/renesas/phy-rcar-gen3-usb2.c
498
writel(val, usb2_base + USB2_VBCTRL);
drivers/phy/renesas/phy-rcar-gen3-usb2.c
519
writel(USB2_OBINTSTA_CLEAR, usb2_base + USB2_OBINTSTA);
drivers/phy/renesas/phy-rcar-gen3-usb2.c
521
writel(ch->phy_data->obint_enable_bits, usb2_base + USB2_OBINTSTA);
drivers/phy/renesas/phy-rcar-gen3-usb2.c
545
writel(val, usb2_base + USB2_INT_ENABLE);
drivers/phy/renesas/phy-rcar-gen3-usb2.c
548
writel(USB2_SPD_RSM_TIMSET_INIT, usb2_base + USB2_SPD_RSM_TIMSET);
drivers/phy/renesas/phy-rcar-gen3-usb2.c
549
writel(USB2_OC_TIMSET_INIT, usb2_base + USB2_OC_TIMSET);
drivers/phy/renesas/phy-rcar-gen3-usb2.c
558
writel(readl(usb2_base + USB2_VBCTRL) | USB2_VBCTRL_SIDDQREL,
drivers/phy/renesas/phy-rcar-gen3-usb2.c
565
writel(val, usb2_base + USB2_REGEN_CG_CTRL);
drivers/phy/renesas/phy-rcar-gen3-usb2.c
567
writel(USB2_UTMI_CTRL_INIT, usb2_base + USB2_UTMI_CTRL);
drivers/phy/renesas/phy-rcar-gen3-usb2.c
568
writel(val & ~USB2_REGEN_CG_CTRL_UPHY_WEN, usb2_base + USB2_REGEN_CG_CTRL);
drivers/phy/renesas/phy-rcar-gen3-usb2.c
591
writel(val, usb2_base + USB2_INT_ENABLE);
drivers/phy/renesas/phy-rcar-gen3-usb2.c
617
writel(val, usb2_base + USB2_USBCTR);
drivers/phy/renesas/phy-rcar-gen3-usb2.c
619
writel(val, usb2_base + USB2_USBCTR);
drivers/phy/renesas/phy-rcar-gen3-usb2.c
641
writel(val, channel->base + USB2_USBCTR);
drivers/phy/renesas/phy-rcar-gen3-usb2.c
813
writel(val, channel->base + USB2_AHB_BUS_CTR);
drivers/phy/renesas/phy-rzg3e-usb3.c
103
writel(val, base + USB3_TEST_UTMICTRL2);
drivers/phy/renesas/phy-rzg3e-usb3.c
105
writel(USB3_TEST_RESET_RELEASE_OVERRIDE, base + USB3_TEST_RESET);
drivers/phy/renesas/phy-rzg3e-usb3.c
113
writel(USB3_TEST_CREGCTRL_PARA_SEL, base + USB3_TEST_CREGCTRL);
drivers/phy/renesas/phy-rzg3e-usb3.c
114
writel(USB3_TEST_RSTCTRL_ASSERT, base + USB3_TEST_RSTCTRL);
drivers/phy/renesas/phy-rzg3e-usb3.c
117
writel(USB3_TEST_CLKCTRL_MPLLA_SSC_EN, base + USB3_TEST_CLKCTRL);
drivers/phy/renesas/phy-rzg3e-usb3.c
118
writel(USB3_TEST_LANECONFIG0_DEFAULT, base + USB3_TEST_LANECONFIG0);
drivers/phy/renesas/phy-rzg3e-usb3.c
119
writel(USB3_TEST_RSTCTRL_RELEASE_HARDRESET, base + USB3_TEST_RSTCTRL);
drivers/phy/renesas/phy-rzg3e-usb3.c
126
writel(USB3_TEST_RSTCTRL_DEASSERT, base + USB3_TEST_RSTCTRL);
drivers/phy/renesas/phy-rzg3e-usb3.c
127
writel(USB3_TEST_RAMCTRL_SRAM_EXT_LD_DONE, base + USB3_TEST_RAMCTRL);
drivers/phy/renesas/phy-rzg3e-usb3.c
128
writel(USB3_TEST_RSTCTRL_RELEASE_OVERRIDE, base + USB3_TEST_RSTCTRL);
drivers/phy/renesas/phy-rzg3e-usb3.c
78
writel(val, base + USB3_TEST_UTMICTRL2);
drivers/phy/renesas/phy-rzg3e-usb3.c
83
writel(val, base + USB3_TEST_PRMCTRL5_R);
drivers/phy/renesas/phy-rzg3e-usb3.c
88
writel(val, base + USB3_TEST_PRMCTRL6_R);
drivers/phy/renesas/phy-rzg3e-usb3.c
94
writel(val, base + USB3_TEST_RESET);
drivers/phy/renesas/phy-rzg3e-usb3.c
98
writel(val, base + USB3_TEST_RESET);
drivers/phy/rockchip/phy-rockchip-inno-csidphy.c
208
writel(val, priv->phy_base + drv_data->ths_settle_offset + offset);
drivers/phy/rockchip/phy-rockchip-inno-csidphy.c
265
writel(CSIDPHY_CTRL_PWRCTL_UNDEFINED |
drivers/phy/rockchip/phy-rockchip-inno-csidphy.c
273
writel(val, priv->phy_base + CSIDPHY_CTRL_LANE_ENABLE);
drivers/phy/rockchip/phy-rockchip-inno-csidphy.c
277
writel(CSIDPHY_CTRL_PWRCTL_UNDEFINED,
drivers/phy/rockchip/phy-rockchip-inno-csidphy.c
282
writel(CSIDPHY_CTRL_DIG_RST_UNDEFINED,
drivers/phy/rockchip/phy-rockchip-inno-csidphy.c
284
writel(CSIDPHY_CTRL_DIG_RST_UNDEFINED + CSIDPHY_CTRL_DIG_RST_RESET,
drivers/phy/rockchip/phy-rockchip-inno-csidphy.c
292
writel(CSIDPHY_CALIB_EN,
drivers/phy/rockchip/phy-rockchip-inno-csidphy.c
296
writel(CSIDPHY_CALIB_EN,
drivers/phy/rockchip/phy-rockchip-inno-csidphy.c
320
writel(CSIDPHY_CTRL_LANE_ENABLE_UNDEFINED,
drivers/phy/rockchip/phy-rockchip-inno-csidphy.c
325
writel(CSIDPHY_CTRL_PWRCTL_UNDEFINED |
drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c
333
writel(tmp, inno->phy_base + reg);
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
1000
writel(RK3568_PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + RK3568_PHYREG12);
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
1007
writel(RK3568_PHYREG18_PLL_LOOP, priv->mmio + RK3568_PHYREG18);
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
1010
writel(RK3568_PHYREG11_SU_TRIM_0_7, priv->mmio + RK3568_PHYREG11);
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
1013
writel(RK3576_PHYREG21_RX_SQUELCH_VAL, priv->mmio + RK3576_PHYREG21);
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
1024
writel(val, priv->mmio + RK3568_PHYREG15);
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
1029
writel(val, priv->mmio + RK3568_PHYREG7);
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
1056
writel(RK3568_PHYREG16_SSC_CNT_VALUE, priv->mmio + RK3568_PHYREG16);
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
1065
writel(0x00, priv->mmio + RK3588_PHYREG27);
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
1073
writel(0x90, priv->mmio + RK3568_PHYREG11);
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
1074
writel(0x02, priv->mmio + RK3568_PHYREG12);
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
1075
writel(0x57, priv->mmio + RK3568_PHYREG14);
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
1077
writel(RK3568_PHYREG16_SSC_CNT_VALUE, priv->mmio + RK3568_PHYREG16);
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
1089
writel(0xc0, priv->mmio + RK3576_PHYREG30);
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
1098
writel(0x4c, priv->mmio + RK3588_PHYREG27);
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
1108
writel(0x90, priv->mmio + RK3568_PHYREG11);
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
1109
writel(0x43, priv->mmio + RK3568_PHYREG12);
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
1110
writel(0x88, priv->mmio + RK3568_PHYREG13);
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
1111
writel(0x56, priv->mmio + RK3568_PHYREG14);
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
1142
writel(0x0c, priv->mmio + RK3588_PHYREG27);
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
1152
writel(0x90, priv->mmio + RK3568_PHYREG11);
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
1153
writel(0x43, priv->mmio + RK3568_PHYREG12);
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
1154
writel(0x88, priv->mmio + RK3568_PHYREG13);
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
1155
writel(0x56, priv->mmio + RK3568_PHYREG14);
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
1162
writel(val, priv->mmio + RK3568_PHYREG8);
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
1166
writel(0x00, priv->mmio + RK3576_PHYREG17);
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
1167
writel(RK3568_PHYREG18_PLL_LOOP, priv->mmio + RK3568_PHYREG18);
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
1170
writel(0x00, priv->mmio + RK3588_PHYREG27);
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
1179
writel(0x90, priv->mmio + RK3568_PHYREG11);
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
1180
writel(0x02, priv->mmio + RK3568_PHYREG12);
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
1181
writel(0x08, priv->mmio + RK3568_PHYREG13);
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
1182
writel(0x57, priv->mmio + RK3568_PHYREG14);
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
1183
writel(0x40, priv->mmio + RK3568_PHYREG15);
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
1185
writel(RK3568_PHYREG16_SSC_CNT_VALUE, priv->mmio + RK3568_PHYREG16);
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
1189
writel(val, priv->mmio + RK3568_PHYREG33);
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
1265
writel(val, priv->mmio + RK3568_PHYREG15);
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
1272
writel(RK3568_PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + RK3568_PHYREG12);
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
1279
writel(RK3568_PHYREG18_PLL_LOOP, priv->mmio + RK3568_PHYREG18);
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
1280
writel(RK3568_PHYREG11_SU_TRIM_0_7, priv->mmio + RK3568_PHYREG11);
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
1290
writel(val, priv->mmio + RK3568_PHYREG15);
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
1297
writel(val, priv->mmio + RK3568_PHYREG7);
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
1323
writel(RK3568_PHYREG16_SSC_CNT_VALUE, priv->mmio + RK3568_PHYREG16);
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
1339
writel(RK3568_PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + RK3568_PHYREG12);
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
1342
writel(RK3588_PHYREG27_RX_TRIM, priv->mmio + RK3588_PHYREG27);
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
1345
writel(RK3568_PHYREG11_SU_TRIM_0_7, priv->mmio + RK3568_PHYREG11);
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
1370
writel(val, priv->mmio + RK3568_PHYREG14);
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
1377
writel(val, priv->mmio + RK3568_PHYREG8);
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
223
writel(temp, priv->mmio + reg);
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
524
writel(0x570804f0, priv->mmio + RK3528_PHYREG42);
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
627
writel(RK3568_PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + RK3568_PHYREG12);
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
634
writel(RK3568_PHYREG18_PLL_LOOP, priv->mmio + RK3568_PHYREG18);
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
637
writel(RK3568_PHYREG11_SU_TRIM_0_7, priv->mmio + RK3568_PHYREG11);
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
660
writel(RK3568_PHYREG16_SSC_CNT_VALUE, priv->mmio + RK3568_PHYREG16);
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
680
writel(0x4, priv->mmio + RK3568_PHYREG12);
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
686
writel(0x32, priv->mmio + RK3568_PHYREG18);
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
687
writel(0xf0, priv->mmio + RK3568_PHYREG11);
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
705
writel(val, priv->mmio + RK3568_PHYREG14);
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
712
writel(val, priv->mmio + RK3568_PHYREG8);
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
777
writel(val, priv->mmio + RK3568_PHYREG15);
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
784
writel(RK3568_PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + RK3568_PHYREG12);
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
791
writel(RK3568_PHYREG18_PLL_LOOP, priv->mmio + RK3568_PHYREG18);
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
792
writel(RK3568_PHYREG11_SU_TRIM_0_7, priv->mmio + RK3568_PHYREG11);
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
812
writel(val, priv->mmio + RK3568_PHYREG15);
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
819
writel(val, priv->mmio + RK3568_PHYREG7);
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
858
writel(RK3568_PHYREG16_SSC_CNT_VALUE, priv->mmio + RK3568_PHYREG16);
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
875
writel(RK3568_PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + RK3568_PHYREG12);
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
881
writel(RK3568_PHYREG18_PLL_LOOP, priv->mmio + RK3568_PHYREG18);
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
882
writel(RK3568_PHYREG11_SU_TRIM_0_7, priv->mmio + RK3568_PHYREG11);
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
908
writel(val, priv->mmio + RK3568_PHYREG14);
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
915
writel(val, priv->mmio + RK3568_PHYREG8);
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
993
writel(val, priv->mmio + RK3568_PHYREG15);
drivers/phy/rockchip/phy-rockchip-typec.c
1024
writel(DP_MODE_ENTER_A2, tcphy->base + DP_MODE_CTL);
drivers/phy/rockchip/phy-rockchip-typec.c
465
writel(0x830, tcphy->base + PMA_CMN_CTRL1);
drivers/phy/rockchip/phy-rockchip-typec.c
471
writel(0x90, tcphy->base + XCVR_DIAG_LANE_FCM_EN_MGN(i));
drivers/phy/rockchip/phy-rockchip-typec.c
472
writel(0x960, tcphy->base + TX_RCVDET_EN_TMR(i));
drivers/phy/rockchip/phy-rockchip-typec.c
473
writel(0x30, tcphy->base + TX_RCVDET_ST_TMR(i));
drivers/phy/rockchip/phy-rockchip-typec.c
479
writel(rdata, tcphy->base + CMN_DIAG_HSCLK_SEL);
drivers/phy/rockchip/phy-rockchip-typec.c
488
writel(usb3_pll_cfg[i].value,
drivers/phy/rockchip/phy-rockchip-typec.c
497
writel(DP_PLL_CLOCK_ENABLE | DP_PLL_ENABLE | DP_PLL_DATA_RATE_RBR,
drivers/phy/rockchip/phy-rockchip-typec.c
502
writel(dp_pll_cfg[i].value, tcphy->base + dp_pll_cfg[i].addr);
drivers/phy/rockchip/phy-rockchip-typec.c
507
writel(0x7799, tcphy->base + TX_PSC_A0(lane));
drivers/phy/rockchip/phy-rockchip-typec.c
508
writel(0x7798, tcphy->base + TX_PSC_A1(lane));
drivers/phy/rockchip/phy-rockchip-typec.c
509
writel(0x5098, tcphy->base + TX_PSC_A2(lane));
drivers/phy/rockchip/phy-rockchip-typec.c
510
writel(0x5098, tcphy->base + TX_PSC_A3(lane));
drivers/phy/rockchip/phy-rockchip-typec.c
511
writel(0, tcphy->base + TX_TXCC_MGNFS_MULT_000(lane));
drivers/phy/rockchip/phy-rockchip-typec.c
512
writel(0xbf, tcphy->base + XCVR_DIAG_BIDI_CTRL(lane));
drivers/phy/rockchip/phy-rockchip-typec.c
517
writel(0xa6fd, tcphy->base + RX_PSC_A0(lane));
drivers/phy/rockchip/phy-rockchip-typec.c
518
writel(0xa6fd, tcphy->base + RX_PSC_A1(lane));
drivers/phy/rockchip/phy-rockchip-typec.c
519
writel(0xa410, tcphy->base + RX_PSC_A2(lane));
drivers/phy/rockchip/phy-rockchip-typec.c
520
writel(0x2410, tcphy->base + RX_PSC_A3(lane));
drivers/phy/rockchip/phy-rockchip-typec.c
521
writel(0x23ff, tcphy->base + RX_PSC_CAL(lane));
drivers/phy/rockchip/phy-rockchip-typec.c
522
writel(0x13, tcphy->base + RX_SIGDET_HL_FILT_TMR(lane));
drivers/phy/rockchip/phy-rockchip-typec.c
523
writel(0x03e7, tcphy->base + RX_REE_CTRL_DATA_MASK(lane));
drivers/phy/rockchip/phy-rockchip-typec.c
524
writel(0x1004, tcphy->base + RX_DIAG_SIGDET_TUNE(lane));
drivers/phy/rockchip/phy-rockchip-typec.c
525
writel(0x2010, tcphy->base + RX_PSC_RDY(lane));
drivers/phy/rockchip/phy-rockchip-typec.c
526
writel(0xfb, tcphy->base + XCVR_DIAG_BIDI_CTRL(lane));
drivers/phy/rockchip/phy-rockchip-typec.c
533
writel(0xbefc, tcphy->base + XCVR_PSM_RCTRL(lane));
drivers/phy/rockchip/phy-rockchip-typec.c
534
writel(0x6799, tcphy->base + TX_PSC_A0(lane));
drivers/phy/rockchip/phy-rockchip-typec.c
535
writel(0x6798, tcphy->base + TX_PSC_A1(lane));
drivers/phy/rockchip/phy-rockchip-typec.c
536
writel(0x98, tcphy->base + TX_PSC_A2(lane));
drivers/phy/rockchip/phy-rockchip-typec.c
537
writel(0x98, tcphy->base + TX_PSC_A3(lane));
drivers/phy/rockchip/phy-rockchip-typec.c
539
writel(0, tcphy->base + TX_TXCC_MGNFS_MULT_000(lane));
drivers/phy/rockchip/phy-rockchip-typec.c
540
writel(0, tcphy->base + TX_TXCC_MGNFS_MULT_001(lane));
drivers/phy/rockchip/phy-rockchip-typec.c
541
writel(0, tcphy->base + TX_TXCC_MGNFS_MULT_010(lane));
drivers/phy/rockchip/phy-rockchip-typec.c
542
writel(0, tcphy->base + TX_TXCC_MGNFS_MULT_011(lane));
drivers/phy/rockchip/phy-rockchip-typec.c
543
writel(0, tcphy->base + TX_TXCC_MGNFS_MULT_100(lane));
drivers/phy/rockchip/phy-rockchip-typec.c
544
writel(0, tcphy->base + TX_TXCC_MGNFS_MULT_101(lane));
drivers/phy/rockchip/phy-rockchip-typec.c
545
writel(0, tcphy->base + TX_TXCC_MGNFS_MULT_110(lane));
drivers/phy/rockchip/phy-rockchip-typec.c
546
writel(0, tcphy->base + TX_TXCC_MGNFS_MULT_111(lane));
drivers/phy/rockchip/phy-rockchip-typec.c
547
writel(0, tcphy->base + TX_TXCC_CPOST_MULT_10(lane));
drivers/phy/rockchip/phy-rockchip-typec.c
548
writel(0, tcphy->base + TX_TXCC_CPOST_MULT_01(lane));
drivers/phy/rockchip/phy-rockchip-typec.c
549
writel(0, tcphy->base + TX_TXCC_CPOST_MULT_00(lane));
drivers/phy/rockchip/phy-rockchip-typec.c
550
writel(0, tcphy->base + TX_TXCC_CPOST_MULT_11(lane));
drivers/phy/rockchip/phy-rockchip-typec.c
552
writel(0x128, tcphy->base + TX_TXCC_CAL_SCLR_MULT(lane));
drivers/phy/rockchip/phy-rockchip-typec.c
553
writel(0x400, tcphy->base + TX_DIAG_TX_DRV(lane));
drivers/phy/rockchip/phy-rockchip-typec.c
557
writel(rdata, tcphy->base + XCVR_DIAG_PLLDRC_CTRL(lane));
drivers/phy/rockchip/phy-rockchip-typec.c
585
writel(tx_ana_ctrl_reg_1, tcphy->base + TX_ANA_CTRL_REG_1);
drivers/phy/rockchip/phy-rockchip-typec.c
614
writel(tx_ana_ctrl_reg_1, tcphy->base + TX_ANA_CTRL_REG_1);
drivers/phy/rockchip/phy-rockchip-typec.c
620
writel(val, tcphy->base + TX_DIG_CTRL_REG_2);
drivers/phy/rockchip/phy-rockchip-typec.c
629
writel(tx_ana_ctrl_reg_1, tcphy->base + TX_ANA_CTRL_REG_1);
drivers/phy/rockchip/phy-rockchip-typec.c
633
writel(0, tcphy->base + PHY_DP_TX_CTL);
drivers/phy/rockchip/phy-rockchip-typec.c
637
writel(tx_ana_ctrl_reg_2, tcphy->base + TX_ANA_CTRL_REG_2);
drivers/phy/rockchip/phy-rockchip-typec.c
640
writel(tx_ana_ctrl_reg_2, tcphy->base + TX_ANA_CTRL_REG_2);
drivers/phy/rockchip/phy-rockchip-typec.c
642
writel(0, tcphy->base + TX_ANA_CTRL_REG_3);
drivers/phy/rockchip/phy-rockchip-typec.c
645
writel(tx_ana_ctrl_reg_1, tcphy->base + TX_ANA_CTRL_REG_1);
drivers/phy/rockchip/phy-rockchip-typec.c
648
writel(tx_ana_ctrl_reg_1, tcphy->base + TX_ANA_CTRL_REG_1);
drivers/phy/rockchip/phy-rockchip-typec.c
650
writel(0, tcphy->base + TX_ANA_CTRL_REG_5);
drivers/phy/rockchip/phy-rockchip-typec.c
656
writel(0x1001, tcphy->base + TX_ANA_CTRL_REG_4);
drivers/phy/rockchip/phy-rockchip-typec.c
660
writel(tx_ana_ctrl_reg_1, tcphy->base + TX_ANA_CTRL_REG_1);
drivers/phy/rockchip/phy-rockchip-typec.c
663
writel(tx_ana_ctrl_reg_1, tcphy->base + TX_ANA_CTRL_REG_1);
drivers/phy/rockchip/phy-rockchip-typec.c
670
writel(tx_ana_ctrl_reg_2, tcphy->base + TX_ANA_CTRL_REG_2);
drivers/phy/rockchip/phy-rockchip-typec.c
673
writel(tx_ana_ctrl_reg_2, tcphy->base + TX_ANA_CTRL_REG_2);
drivers/phy/rockchip/phy-rockchip-typec.c
690
writel(tx_ana_ctrl_reg_1, tcphy->base + TX_ANA_CTRL_REG_1);
drivers/phy/rockchip/phy-rockchip-typec.c
693
writel(tx_ana_ctrl_reg_1, tcphy->base + TX_ANA_CTRL_REG_1);
drivers/phy/rockchip/phy-rockchip-typec.c
700
writel(0, tcphy->base + TX_ANA_CTRL_REG_4);
drivers/phy/rockchip/phy-rockchip-typec.c
703
writel(0, tcphy->base + TXDA_COEFF_CALC_CTRL);
drivers/phy/rockchip/phy-rockchip-typec.c
706
writel(0, tcphy->base + TXDA_CYA_AUXDA_CYA);
drivers/phy/rockchip/phy-rockchip-typec.c
719
writel(val, tcphy->base + TX_DIG_CTRL_REG_2);
drivers/phy/rockchip/phy-rockchip-typec.c
752
writel(PIN_ASSIGN_C_E, tcphy->base + PMA_LANE_CFG);
drivers/phy/rockchip/phy-rockchip-typec.c
768
writel(PIN_ASSIGN_D_F, tcphy->base + PMA_LANE_CFG);
drivers/phy/rockchip/phy-rockchip-typec.c
771
writel(DP_MODE_ENTER_A2, tcphy->base + DP_MODE_CTL);
drivers/phy/rockchip/phy-rockchip-typec.c
992
writel(DP_MODE_ENTER_A0, tcphy->base + DP_MODE_CTL);
drivers/phy/rockchip/phy-rockchip-typec.c
998
writel(DP_MODE_ENTER_A2, tcphy->base + DP_MODE_CTL);
drivers/phy/samsung/phy-exynos-pcie.c
46
writel(val, base + offset);
drivers/phy/samsung/phy-exynos4210-usb2.c
167
writel(on, drv->reg_phy + EXYNOS_4210_UPHY1CON);
drivers/phy/samsung/phy-exynos4210-usb2.c
185
writel(clk, drv->reg_phy + EXYNOS_4210_UPHYCLK);
drivers/phy/samsung/phy-exynos4210-usb2.c
189
writel(pwr, drv->reg_phy + EXYNOS_4210_UPHYPWR);
drivers/phy/samsung/phy-exynos4210-usb2.c
193
writel(rst, drv->reg_phy + EXYNOS_4210_UPHYRST);
drivers/phy/samsung/phy-exynos4210-usb2.c
196
writel(rst, drv->reg_phy + EXYNOS_4210_UPHYRST);
drivers/phy/samsung/phy-exynos4210-usb2.c
203
writel(pwr, drv->reg_phy + EXYNOS_4210_UPHYPWR);
drivers/phy/samsung/phy-exynos4x12-usb2.c
205
writel(clk, drv->reg_phy + EXYNOS_4x12_UPHYCLK);
drivers/phy/samsung/phy-exynos4x12-usb2.c
242
writel(pwr, drv->reg_phy + EXYNOS_4x12_UPHYPWR);
drivers/phy/samsung/phy-exynos4x12-usb2.c
246
writel(rst, drv->reg_phy + EXYNOS_4x12_UPHYRST);
drivers/phy/samsung/phy-exynos4x12-usb2.c
249
writel(rst, drv->reg_phy + EXYNOS_4x12_UPHYRST);
drivers/phy/samsung/phy-exynos4x12-usb2.c
256
writel(pwr, drv->reg_phy + EXYNOS_4x12_UPHYPWR);
drivers/phy/samsung/phy-exynos5-usbdrd.c
1041
writel(val | cmd, phy_drd->reg_phy + EXYNOS5_DRD_PHYREG0);
drivers/phy/samsung/phy-exynos5-usbdrd.c
1050
writel(val, phy_drd->reg_phy + EXYNOS5_DRD_PHYREG0);
drivers/phy/samsung/phy-exynos5-usbdrd.c
1070
writel(val, phy_drd->reg_phy + EXYNOS5_DRD_PHYREG0);
drivers/phy/samsung/phy-exynos5-usbdrd.c
1077
writel(val, phy_drd->reg_phy + EXYNOS5_DRD_PHYREG0);
drivers/phy/samsung/phy-exynos5-usbdrd.c
1222
writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST);
drivers/phy/samsung/phy-exynos5-usbdrd.c
1227
writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST);
drivers/phy/samsung/phy-exynos5-usbdrd.c
1237
writel(reg, phy_drd->reg_phy + EXYNOS7870_DRD_HSPHYPLLTUNE);
drivers/phy/samsung/phy-exynos5-usbdrd.c
1244
writel(reg, phy_drd->reg_phy + EXYNOS7870_DRD_HSPHYCTRL);
drivers/phy/samsung/phy-exynos5-usbdrd.c
1258
writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_LINKSYSTEM);
drivers/phy/samsung/phy-exynos5-usbdrd.c
1273
writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYUTMI);
drivers/phy/samsung/phy-exynos5-usbdrd.c
1278
writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_LINKPORT);
drivers/phy/samsung/phy-exynos5-usbdrd.c
1283
writel(reg, phy_drd->reg_phy + EXYNOS7870_DRD_HSPHYCTRL);
drivers/phy/samsung/phy-exynos5-usbdrd.c
1289
writel(reg, phy_drd->reg_phy + EXYNOS7870_DRD_HSPHYCTRL);
drivers/phy/samsung/phy-exynos5-usbdrd.c
1333
writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYUTMI);
drivers/phy/samsung/phy-exynos5-usbdrd.c
1338
writel(reg, phy_drd->reg_phy + EXYNOS7870_DRD_HSPHYCTRL);
drivers/phy/samsung/phy-exynos5-usbdrd.c
1343
writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_LINKSYSTEM);
drivers/phy/samsung/phy-exynos5-usbdrd.c
1376
writel(reg, regs_base + EXYNOS850_DRD_LINKCTRL);
drivers/phy/samsung/phy-exynos5-usbdrd.c
1381
writel(reg, regs_base + EXYNOS2200_DRD_CLKRST);
drivers/phy/samsung/phy-exynos5-usbdrd.c
1386
writel(reg, regs_base + EXYNOS2200_DRD_UTMI);
drivers/phy/samsung/phy-exynos5-usbdrd.c
1405
writel(reg, regs_base + EXYNOS850_DRD_LINKCTRL);
drivers/phy/samsung/phy-exynos5-usbdrd.c
1417
writel(reg, regs_base + EXYNOS2200_DRD_HSP_MISC);
drivers/phy/samsung/phy-exynos5-usbdrd.c
1425
writel(reg, regs_base + EXYNOS2200_DRD_CLKRST);
drivers/phy/samsung/phy-exynos5-usbdrd.c
1482
writel(reg, regs_base + EXYNOS2200_DRD_UTMI);
drivers/phy/samsung/phy-exynos5-usbdrd.c
1486
writel(reg, regs_base + EXYNOS2200_DRD_CLKRST);
drivers/phy/samsung/phy-exynos5-usbdrd.c
1511
writel(reg, regs_base + EXYNOS850_DRD_LINKCTRL);
drivers/phy/samsung/phy-exynos5-usbdrd.c
1516
writel(reg, regs_base + EXYNOS850_DRD_SECPMACTL);
drivers/phy/samsung/phy-exynos5-usbdrd.c
1532
writel(reg, regs_base + EXYNOS850_DRD_LINKCTRL);
drivers/phy/samsung/phy-exynos5-usbdrd.c
1545
writel(reg, regs_base + EXYNOS850_DRD_CLKRST);
drivers/phy/samsung/phy-exynos5-usbdrd.c
1551
writel(reg, regs_base + EXYNOS850_DRD_UTMI);
drivers/phy/samsung/phy-exynos5-usbdrd.c
1556
writel(reg, regs_base + EXYNOS850_DRD_HSP);
drivers/phy/samsung/phy-exynos5-usbdrd.c
1561
writel(reg, regs_base + EXYNOS850_DRD_LINKCTRL);
drivers/phy/samsung/phy-exynos5-usbdrd.c
1566
writel(reg, regs_base + EXYNOS850_DRD_UTMI);
drivers/phy/samsung/phy-exynos5-usbdrd.c
1570
writel(reg, regs_base + EXYNOS850_DRD_HSP);
drivers/phy/samsung/phy-exynos5-usbdrd.c
1596
writel(reg, regs_base + EXYNOS850_DRD_SSPPLLCTL);
drivers/phy/samsung/phy-exynos5-usbdrd.c
1605
writel(reg, regs_base + EXYNOS850_DRD_HSP_TEST);
drivers/phy/samsung/phy-exynos5-usbdrd.c
1615
writel(reg, regs_base + EXYNOS850_DRD_CLKRST);
drivers/phy/samsung/phy-exynos5-usbdrd.c
1621
writel(reg, regs_base + EXYNOS850_DRD_HSP);
drivers/phy/samsung/phy-exynos5-usbdrd.c
1664
writel(reg, regs_base + EXYNOS850_DRD_UTMI);
drivers/phy/samsung/phy-exynos5-usbdrd.c
1669
writel(reg, regs_base + EXYNOS850_DRD_HSP_TEST);
drivers/phy/samsung/phy-exynos5-usbdrd.c
1674
writel(reg, regs_base + EXYNOS850_DRD_CLKRST);
drivers/phy/samsung/phy-exynos5-usbdrd.c
1677
writel(reg, regs_base + EXYNOS850_DRD_CLKRST);
drivers/phy/samsung/phy-exynos5-usbdrd.c
1704
writel(reg, regs_pma + EXYNOS9_PMA_USBDP_CMN_REG0008);
drivers/phy/samsung/phy-exynos5-usbdrd.c
1716
writel(reg, regs_phy + EXYNOS850_DRD_SECPMACTL);
drivers/phy/samsung/phy-exynos5-usbdrd.c
1860
writel(reg, regs_base + EXYNOS850_DRD_UTMI);
drivers/phy/samsung/phy-exynos5-usbdrd.c
1865
writel(reg, regs_base + EXYNOS850_DRD_HSP);
drivers/phy/samsung/phy-exynos5-usbdrd.c
1869
writel(reg, regs_base + EXYNOS850_DRD_UTMI);
drivers/phy/samsung/phy-exynos5-usbdrd.c
1873
writel(reg, regs_base + EXYNOS850_DRD_HSP);
drivers/phy/samsung/phy-exynos5-usbdrd.c
2122
writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0);
drivers/phy/samsung/phy-exynos5-usbdrd.c
2141
writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0);
drivers/phy/samsung/phy-exynos5-usbdrd.c
2142
writel(0x0, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON1);
drivers/phy/samsung/phy-exynos5-usbdrd.c
2143
writel(0x0, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON2);
drivers/phy/samsung/phy-exynos5-usbdrd.c
2161
writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0);
drivers/phy/samsung/phy-exynos5-usbdrd.c
2175
writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0);
drivers/phy/samsung/phy-exynos5-usbdrd.c
2191
writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0);
drivers/phy/samsung/phy-exynos5-usbdrd.c
2201
writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON2);
drivers/phy/samsung/phy-exynos5-usbdrd.c
2209
writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0);
drivers/phy/samsung/phy-exynos5-usbdrd.c
2247
writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_RST_CTRL);
drivers/phy/samsung/phy-exynos5-usbdrd.c
2256
writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_RST_CTRL);
drivers/phy/samsung/phy-exynos5-usbdrd.c
2267
writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_RST_CTRL);
drivers/phy/samsung/phy-exynos5-usbdrd.c
2276
writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_RST_CTRL);
drivers/phy/samsung/phy-exynos5-usbdrd.c
2300
writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CONFIG0);
drivers/phy/samsung/phy-exynos5-usbdrd.c
2310
writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CONFIG7);
drivers/phy/samsung/phy-exynos5-usbdrd.c
2327
writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CONFIG4);
drivers/phy/samsung/phy-exynos5-usbdrd.c
2352
writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CONFIG7);
drivers/phy/samsung/phy-exynos5-usbdrd.c
2368
writel(reg, reg_phy + EXYNOS850_DRD_LINKCTRL);
drivers/phy/samsung/phy-exynos5-usbdrd.c
2373
writel(reg, reg_phy + EXYNOS2200_DRD_CLKRST);
drivers/phy/samsung/phy-exynos5-usbdrd.c
2378
writel(reg, reg_phy + EXYNOSAUTOV920_DRD_HSP_CLKRST);
drivers/phy/samsung/phy-exynos5-usbdrd.c
2384
writel(reg, reg_phy + EXYNOS2200_DRD_UTMI);
drivers/phy/samsung/phy-exynos5-usbdrd.c
2389
writel(reg, reg_phy + EXYNOSAUTOV920_DRD_HSPCTL);
drivers/phy/samsung/phy-exynos5-usbdrd.c
2396
writel(reg, reg_phy + EXYNOS850_DRD_LINKCTRL);
drivers/phy/samsung/phy-exynos5-usbdrd.c
2400
writel(reg, reg_phy + EXYNOS2200_DRD_UTMI);
drivers/phy/samsung/phy-exynos5-usbdrd.c
2404
writel(reg, reg_phy + EXYNOSAUTOV920_DRD_HSPCTL);
drivers/phy/samsung/phy-exynos5-usbdrd.c
2431
writel(reg, reg_phy + EXYNOSAUTOV920_DRD_HSPPLLTUNE);
drivers/phy/samsung/phy-exynos5-usbdrd.c
2436
writel(reg, reg_phy + EXYNOSAUTOV920_DRD_HSP_TEST);
drivers/phy/samsung/phy-exynos5-usbdrd.c
2445
writel(reg, reg_phy + EXYNOSAUTOV920_DRD_HSP_CLKRST);
drivers/phy/samsung/phy-exynos5-usbdrd.c
2453
writel(reg, reg_phy + EXYNOS850_DRD_LINKCTRL);
drivers/phy/samsung/phy-exynos5-usbdrd.c
2458
writel(reg, reg_phy + EXYNOS2200_DRD_CLKRST);
drivers/phy/samsung/phy-exynos5-usbdrd.c
2471
writel(reg, reg_phy + EXYNOS2200_DRD_UTMI);
drivers/phy/samsung/phy-exynos5-usbdrd.c
2476
writel(reg, reg_phy + EXYNOSAUTOV920_DRD_HSP_TEST);
drivers/phy/samsung/phy-exynos5-usbdrd.c
2481
writel(reg, reg_phy + EXYNOS850_DRD_LINKCTRL);
drivers/phy/samsung/phy-exynos5-usbdrd.c
2486
writel(reg, reg_phy + EXYNOS2200_DRD_CLKRST);
drivers/phy/samsung/phy-exynos5-usbdrd.c
2489
writel(reg, reg_phy + EXYNOS2200_DRD_CLKRST);
drivers/phy/samsung/phy-exynos5-usbdrd.c
707
writel(reg, reg_base + tune->off);
drivers/phy/samsung/phy-exynos5-usbdrd.c
719
writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1);
drivers/phy/samsung/phy-exynos5-usbdrd.c
723
writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST);
drivers/phy/samsung/phy-exynos5-usbdrd.c
735
writel(reg, regs_base + EXYNOS850_DRD_CLKRST);
drivers/phy/samsung/phy-exynos5-usbdrd.c
747
writel(reg, regs_base + EXYNOS850_DRD_SECPMACTL);
drivers/phy/samsung/phy-exynos5-usbdrd.c
753
writel(reg, regs_base + EXYNOS850_DRD_SECPMACTL);
drivers/phy/samsung/phy-exynos5-usbdrd.c
760
writel(reg, regs_base + EXYNOS850_DRD_LINKCTRL);
drivers/phy/samsung/phy-exynos5-usbdrd.c
767
writel(reg, regs_base + EXYNOS850_DRD_SECPMACTL);
drivers/phy/samsung/phy-exynos5-usbdrd.c
789
writel(reg, regs_base + EXYNOS9_PMA_USBDP_CMN_REG00B8);
drivers/phy/samsung/phy-exynos5-usbdrd.c
800
writel(reg, regs_base + EXYNOS9_PMA_USBDP_TRSV_REG0413);
drivers/phy/samsung/phy-exynos5-usbdrd.c
811
writel(reg, regs_base + EXYNOS9_PMA_USBDP_TRSV_REG0813);
drivers/phy/samsung/phy-exynos5-usbdrd.c
870
writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM0);
drivers/phy/samsung/phy-exynos5-usbdrd.c
876
writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1);
drivers/phy/samsung/phy-exynos5-usbdrd.c
879
writel(PHYUTMI_OTGDISABLE, phy_drd->reg_phy + EXYNOS5_DRD_PHYUTMI);
drivers/phy/samsung/phy-exynos5-usbdrd.c
883
writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST);
drivers/phy/samsung/phy-exynos5-usbdrd.c
898
writel(0x0, phy_drd->reg_phy + EXYNOS5_DRD_PHYREG0);
drivers/phy/samsung/phy-exynos5-usbdrd.c
899
writel(0x0, phy_drd->reg_phy + EXYNOS5_DRD_PHYRESUME);
drivers/phy/samsung/phy-exynos5-usbdrd.c
907
writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_LINKSYSTEM);
drivers/phy/samsung/phy-exynos5-usbdrd.c
912
writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM0);
drivers/phy/samsung/phy-exynos5-usbdrd.c
917
writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYUTMICLKSEL);
drivers/phy/samsung/phy-exynos5-usbdrd.c
936
writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST);
drivers/phy/samsung/phy-exynos5-usbdrd.c
941
writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST);
drivers/phy/samsung/phy-exynos5-usbdrd.c
962
writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYUTMI);
drivers/phy/samsung/phy-exynos5-usbdrd.c
969
writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST);
drivers/phy/samsung/phy-exynos5-usbdrd.c
975
writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST);
drivers/phy/samsung/phy-exynos5250-sata.c
105
writel(val, sata_phy->regs + EXYNOS5_SATA_RESET);
drivers/phy/samsung/phy-exynos5250-sata.c
109
writel(val, sata_phy->regs + EXYNOS5_SATA_RESET);
drivers/phy/samsung/phy-exynos5250-sata.c
113
writel(val, sata_phy->regs + EXYNOS5_SATA_RESET);
drivers/phy/samsung/phy-exynos5250-sata.c
117
writel(val, sata_phy->regs + EXYNOS5_SATA_PHSATA_CTRLM);
drivers/phy/samsung/phy-exynos5250-sata.c
122
writel(val, sata_phy->regs + EXYNOS5_SATA_PHSATA_CTRLM);
drivers/phy/samsung/phy-exynos5250-sata.c
126
writel(val, sata_phy->regs + EXYNOS5_SATA_CTRL0);
drivers/phy/samsung/phy-exynos5250-sata.c
130
writel(val, sata_phy->regs + EXYNOS5_SATA_MODE0);
drivers/phy/samsung/phy-exynos5250-sata.c
139
writel(val, sata_phy->regs + EXYNOS5_SATA_RESET);
drivers/phy/samsung/phy-exynos5250-sata.c
143
writel(val, sata_phy->regs + EXYNOS5_SATA_RESET);
drivers/phy/samsung/phy-exynos5250-sata.c
99
writel(val, sata_phy->regs + EXYNOS5_SATA_RESET);
drivers/phy/samsung/phy-exynos5250-usb2.c
228
writel(otg, drv->reg_phy + EXYNOS_5250_USBOTGSYS);
drivers/phy/samsung/phy-exynos5250-usb2.c
234
writel(otg, drv->reg_phy + EXYNOS_5250_USBOTGSYS);
drivers/phy/samsung/phy-exynos5250-usb2.c
257
writel(ctrl0, drv->reg_phy + EXYNOS_5250_HOSTPHYCTRL0);
drivers/phy/samsung/phy-exynos5250-usb2.c
261
writel(ctrl0, drv->reg_phy + EXYNOS_5250_HOSTPHYCTRL0);
drivers/phy/samsung/phy-exynos5250-usb2.c
280
writel(otg, drv->reg_phy + EXYNOS_5250_USBOTGSYS);
drivers/phy/samsung/phy-exynos5250-usb2.c
290
writel(hsic, drv->reg_phy + EXYNOS_5250_HSICPHYCTRL1);
drivers/phy/samsung/phy-exynos5250-usb2.c
291
writel(hsic, drv->reg_phy + EXYNOS_5250_HSICPHYCTRL2);
drivers/phy/samsung/phy-exynos5250-usb2.c
294
writel(hsic, drv->reg_phy + EXYNOS_5250_HSICPHYCTRL1);
drivers/phy/samsung/phy-exynos5250-usb2.c
295
writel(hsic, drv->reg_phy + EXYNOS_5250_HSICPHYCTRL2);
drivers/phy/samsung/phy-exynos5250-usb2.c
306
writel(ehci, drv->reg_phy + EXYNOS_5250_HOSTEHCICTRL);
drivers/phy/samsung/phy-exynos5250-usb2.c
312
writel(ohci, drv->reg_phy + EXYNOS_5250_HOSTOHCICTRL);
drivers/phy/samsung/phy-exynos5250-usb2.c
336
writel(otg, drv->reg_phy + EXYNOS_5250_USBOTGSYS);
drivers/phy/samsung/phy-exynos5250-usb2.c
345
writel(ctrl0, drv->reg_phy + EXYNOS_5250_HOSTPHYCTRL0);
drivers/phy/samsung/phy-exynos5250-usb2.c
355
writel(hsic, drv->reg_phy + EXYNOS_5250_HSICPHYCTRL1);
drivers/phy/samsung/phy-exynos5250-usb2.c
356
writel(hsic, drv->reg_phy + EXYNOS_5250_HSICPHYCTRL2);
drivers/phy/samsung/phy-gs101-ufs.c
189
writel(LN0_OVRD_RX_CDR_EN, ufs_phy->reg_pma +
drivers/phy/samsung/phy-gs101-ufs.c
191
writel(LN0_OVRD_RX_CDR_EN | LN0_RX_CDR_EN,
drivers/phy/samsung/phy-s5pv210-usb2.c
130
writel(drv->ref_reg_val, drv->reg_phy + S5PV210_UPHYCLK);
drivers/phy/samsung/phy-s5pv210-usb2.c
134
writel(pwr, drv->reg_phy + S5PV210_UPHYPWR);
drivers/phy/samsung/phy-s5pv210-usb2.c
138
writel(rst, drv->reg_phy + S5PV210_UPHYRST);
drivers/phy/samsung/phy-s5pv210-usb2.c
141
writel(rst, drv->reg_phy + S5PV210_UPHYRST);
drivers/phy/samsung/phy-s5pv210-usb2.c
149
writel(pwr, drv->reg_phy + S5PV210_UPHYPWR);
drivers/phy/samsung/phy-samsung-ufs.c
39
writel(cfg->val, (phy)->reg_pma + cfg->off_0);
drivers/phy/samsung/phy-samsung-ufs.c
43
writel(cfg->val, (phy)->reg_pma + cfg->off_1);
drivers/phy/socionext/phy-uniphier-ahci.c
107
writel(val, priv->base + RXTXCTRL);
drivers/phy/socionext/phy-uniphier-ahci.c
120
writel(val, priv->base + CKCTRL0);
drivers/phy/socionext/phy-uniphier-ahci.c
125
writel(val, priv->base + RXTXCTRL);
drivers/phy/socionext/phy-uniphier-ahci.c
165
writel(val, priv->base + RXTXCTRL);
drivers/phy/socionext/phy-uniphier-ahci.c
170
writel(val, priv->base + CKCTRL0);
drivers/phy/socionext/phy-uniphier-ahci.c
186
writel(val, priv->base + RXTXCTRL);
drivers/phy/socionext/phy-uniphier-ahci.c
191
writel(val, priv->base + CKCTRL0);
drivers/phy/socionext/phy-uniphier-ahci.c
205
writel(val, priv->base + CKCTRL);
drivers/phy/socionext/phy-uniphier-ahci.c
207
writel(val, priv->base + CKCTRL);
drivers/phy/socionext/phy-uniphier-ahci.c
210
writel(val, priv->base + CKCTRL);
drivers/phy/socionext/phy-uniphier-ahci.c
212
writel(val, priv->base + CKCTRL);
drivers/phy/socionext/phy-uniphier-ahci.c
258
writel(val, priv->base + TXCTRL0);
drivers/phy/socionext/phy-uniphier-ahci.c
86
writel(val, priv->base + CKCTRL0);
drivers/phy/socionext/phy-uniphier-ahci.c
94
writel(val, priv->base + CKCTRL1);
drivers/phy/socionext/phy-uniphier-pcie.c
129
writel(val, priv->base + PCL_PHY_RESET);
drivers/phy/socionext/phy-uniphier-pcie.c
138
writel(val, priv->base + PCL_PHY_RESET);
drivers/phy/socionext/phy-uniphier-pcie.c
167
writel(val, priv->base + PCL_PHY_CLKCTRL);
drivers/phy/socionext/phy-uniphier-pcie.c
80
writel(data, priv->base + PCL_PHY_TEST_I);
drivers/phy/socionext/phy-uniphier-usb3hs.c
186
writel(val, priv->base + HSPHY_CFG1);
drivers/phy/socionext/phy-uniphier-usb3hs.c
190
writel(val, priv->base + HSPHY_CFG1);
drivers/phy/socionext/phy-uniphier-usb3hs.c
196
writel(val, priv->base + HSPHY_CFG1);
drivers/phy/socionext/phy-uniphier-usb3hs.c
200
writel(val, priv->base + HSPHY_CFG1);
drivers/phy/socionext/phy-uniphier-usb3hs.c
285
writel(config0, priv->base + HSPHY_CFG0);
drivers/phy/socionext/phy-uniphier-usb3hs.c
286
writel(config1, priv->base + HSPHY_CFG1);
drivers/phy/socionext/phy-uniphier-usb3ss.c
73
writel(data, priv->base + SSPHY_TESTI);
drivers/phy/starfive/phy-jh7110-dphy-rx.c
101
writel(FIELD_PREP(STF_DPHY_PRECOUNTER_IN_LAN3, 7),
drivers/phy/starfive/phy-jh7110-dphy-rx.c
78
writel(FIELD_PREP(STF_DPHY_ENABLE_CLK, 1) |
drivers/phy/starfive/phy-jh7110-dphy-rx.c
90
writel(FIELD_PREP(STF_DPHY_LANE_SWAP_LAN2, info->maps[3]) |
drivers/phy/starfive/phy-jh7110-dphy-rx.c
95
writel(FIELD_PREP(STF_DPHY_PRECOUNTER_IN_CLK1, 8) |
drivers/phy/starfive/phy-jh7110-dphy-tx.c
217
writel(FIELD_PREP(STF_DPHY_RESETB, assert),
drivers/phy/starfive/phy-jh7110-dphy-tx.c
249
writel(tmp, dphy->topsys + STF_DPHY_APBIFSAIF_SYSCFG(100));
drivers/phy/starfive/phy-jh7110-dphy-tx.c
251
writel(FIELD_PREP(STF_DPHY_RG_CDTX_L0N_HSTX_RES, 0x10) |
drivers/phy/starfive/phy-jh7110-dphy-tx.c
255
writel(FIELD_PREP(STF_DPHY_RG_CDTX_L0N_HSTX_RES, 0x10) |
drivers/phy/starfive/phy-jh7110-dphy-tx.c
263
writel(FIELD_PREP(STF_DPHY_RG_CDTX_L4N_HSTX_RES, 0x10) |
drivers/phy/starfive/phy-jh7110-dphy-tx.c
268
writel(FIELD_PREP(STF_DPHY_AON_POWER_READY_N,
drivers/phy/starfive/phy-jh7110-dphy-tx.c
278
writel(FIELD_PREP(STF_DPHY_RG_CDTX_PLL_SSC_EN, 0x0),
drivers/phy/starfive/phy-jh7110-dphy-tx.c
281
writel(FIELD_PREP(STF_DPHY_RG_CDTX_PLL_LDO_STB_X2_EN, 0x1) |
drivers/phy/starfive/phy-jh7110-dphy-tx.c
287
writel(FIELD_PREP(STF_DPHY_RG_CDTX_PLL_FBK_FRA,
drivers/phy/starfive/phy-jh7110-dphy-tx.c
293
writel(FIELD_PREP(STF_DPHY_RG_EXTD_CYCLE_SEL, p[i].extd_cycle_sel),
drivers/phy/starfive/phy-jh7110-dphy-tx.c
296
writel(FIELD_PREP(STF_DPHY_RG_DLANE_HS_PRE_TIME, p[i].dlane_hs_pre_time) |
drivers/phy/starfive/phy-jh7110-dphy-tx.c
302
writel(FIELD_PREP(STF_DPHY_RG_CLANE_HS_PRE_TIME, p[i].clane_hs_pre_time) |
drivers/phy/starfive/phy-jh7110-dphy-tx.c
318
writel(FIELD_PREP(STF_DPHY_SCFG_PPI_C_READY_SEL, 0) |
drivers/phy/starfive/phy-jh7110-dphy-tx.c
322
writel(FIELD_PREP(STF_DPHY_SCFG_C_HS_PRE_ZERO_TIME, 0x30),
drivers/phy/starfive/phy-jh7110-pcie.c
66
writel(PCIE_USB3_PHY_ENABLE, data->regs + PCIE_USB3_PHY_PLL_CTL_OFF);
drivers/phy/starfive/phy-jh7110-pcie.c
92
writel(val, data->regs + PCIE_USB3_PHY_PLL_CTL_OFF);
drivers/phy/starfive/phy-jh7110-pcie.c
98
writel(PHY_KVCO_FINE_TUNE_LEVEL, phy->regs + PCIE_KVCO_LEVEL_OFF);
drivers/phy/starfive/phy-jh7110-pcie.c
99
writel(PHY_KVCO_FINE_TUNE_SIGNALS, phy->regs + PCIE_KVCO_TUNE_SIGNAL_OFF);
drivers/phy/starfive/phy-jh7110-usb.c
49
writel(val, phy->regs + USB_LS_KEEPALIVE_OFF);
drivers/phy/starfive/phy-jh7110-usb.c
95
writel(val, phy->regs + USB_CLK_MODE_OFF);
drivers/phy/sunplus/phy-sunplus-usb2.c
106
writel(val, usbphy->phy_regs + CONFIG7);
drivers/phy/sunplus/phy-sunplus-usb2.c
126
writel(HIGH_MASK_BITS | 0x4002, usbphy->moon4_regs + UPHY_CONTROL0);
drivers/phy/sunplus/phy-sunplus-usb2.c
127
writel(HIGH_MASK_BITS | 0x8747, usbphy->moon4_regs + UPHY_CONTROL1);
drivers/phy/sunplus/phy-sunplus-usb2.c
137
writel(val, usbphy->phy_regs + CONFIG9);
drivers/phy/sunplus/phy-sunplus-usb2.c
141
writel(val, usbphy->phy_regs + CONFIG1);
drivers/phy/sunplus/phy-sunplus-usb2.c
145
writel(val, usbphy->phy_regs + CONFIG23);
drivers/phy/sunplus/phy-sunplus-usb2.c
148
writel(MASK_MO1_UPHY_RX_CLK_SEL | MO1_UPHY_RX_CLK_SEL,
drivers/phy/sunplus/phy-sunplus-usb2.c
152
writel(J_TBCWAIT_1P1_MS | J_TVDM_SRC_DIS_8P2_MS | J_TVDM_SRC_EN_1P6_MS | J_BC_EN,
drivers/phy/sunplus/phy-sunplus-usb2.c
154
writel(IBG_TRIM0_SSLVHT | J_VDATREE_TRIM_DEFAULT, usbphy->phy_regs + CONFIG17);
drivers/phy/sunplus/phy-sunplus-usb2.c
157
writel(J_FORCE_DISC_ON | J_DEBUG_CTRL_ADDR_MACRO, usbphy->phy_regs + CONFIG3);
drivers/phy/sunplus/phy-sunplus-usb2.c
180
writel(MASK_MO1_UPHY_PLL_POWER_OFF_SEL | MASK_UPHY_PLL_POWER_OFF | pll_pwr_off,
drivers/phy/sunplus/phy-sunplus-usb2.c
183
writel(MASK_MO1_UPHY_PLL_POWER_OFF_SEL | MASK_UPHY_PLL_POWER_OFF | pll_pwr_on,
drivers/phy/sunplus/phy-sunplus-usb2.c
186
writel(MASK_MO1_UPHY_PLL_POWER_OFF_SEL | MASK_UPHY_PLL_POWER_OFF | pll_pwr_off,
drivers/phy/sunplus/phy-sunplus-usb2.c
189
writel(MASK_MO1_UPHY_PLL_POWER_OFF_SEL | MASK_UPHY_PLL_POWER_OFF | pll_pwr_on,
drivers/phy/sunplus/phy-sunplus-usb2.c
192
writel(MASK_MO1_UPHY_PLL_POWER_OFF_SEL | MASK_UPHY_PLL_POWER_OFF | 0x0,
drivers/phy/sunplus/phy-sunplus-usb2.c
206
writel(MASK_MO1_UPHY_PLL_POWER_OFF_SEL | MASK_UPHY_PLL_POWER_OFF | pll_pwr_off,
drivers/phy/sunplus/phy-sunplus-usb2.c
209
writel(MASK_MO1_UPHY_PLL_POWER_OFF_SEL | MASK_UPHY_PLL_POWER_OFF | 0x0,
drivers/phy/tegra/xusb-tegra186.c
283
writel(value, priv->ao_regs + offset);
drivers/phy/tegra/xusb.h
469
writel(value, padctl->regs + offset);
drivers/phy/ti/phy-omap-control.c
133
writel(val, control_phy->power);
drivers/phy/ti/phy-omap-control.c
151
writel(val, ctrl_phy->otghs_control);
drivers/phy/ti/phy-omap-control.c
170
writel(val, ctrl_phy->otghs_control);
drivers/phy/ti/phy-omap-control.c
188
writel(val, ctrl_phy->otghs_control);
drivers/phy/ti/phy-omap-control.c
49
writel(val, control_phy->pcie_pcs);
drivers/phy/xilinx/phy-zynqmp.c
276
writel(value, gtr_dev->serdes + reg);
drivers/phy/xilinx/phy-zynqmp.c
303
writel(value, addr);
drivers/phy/xilinx/phy-zynqmp.c
312
writel((readl(addr) & ~clr) | set, addr);
drivers/phy/xilinx/phy-zynqmp.c
532
writel(gtr_phy->lane, gtr_dev->siou + SATA_CONTROL_OFFSET);
drivers/pinctrl/bcm/pinctrl-bcm2835.c
260
writel(val, pc->base + reg);
drivers/pinctrl/bcm/pinctrl-bcm4908.c
438
writel(0x0, bcm4908_pinctrl->base + BCM4908_TEST_PORT_BLOCK_DATA_MSB);
drivers/pinctrl/bcm/pinctrl-bcm4908.c
439
writel(lsb, bcm4908_pinctrl->base + BCM4908_TEST_PORT_BLOCK_DATA_LSB);
drivers/pinctrl/bcm/pinctrl-bcm4908.c
440
writel(BCM4908_TEST_PORT_CMD_LOAD_MUX_REG,
drivers/pinctrl/bcm/pinctrl-brcmstb.c
130
writel(val, pc->base + BIT_TO_REG(bit));
drivers/pinctrl/bcm/pinctrl-brcmstb.c
314
writel(val, pc->base + BIT_TO_REG(bit));
drivers/pinctrl/bcm/pinctrl-cygnus-mux.c
816
writel(val, pinctrl->base0 + grp->mux.offset);
drivers/pinctrl/bcm/pinctrl-cygnus-mux.c
857
writel(val, pinctrl->base1 + mux->offset);
drivers/pinctrl/bcm/pinctrl-cygnus-mux.c
884
writel(val, pinctrl->base1 + mux->offset);
drivers/pinctrl/bcm/pinctrl-iproc-gpio.c
153
writel(val, chip->base + offset);
drivers/pinctrl/bcm/pinctrl-iproc-gpio.c
186
writel(BIT(bit), chip->base + (i * GPIO_BANK_SIZE) +
drivers/pinctrl/bcm/pinctrl-iproc-gpio.c
207
writel(val, chip->base + offset);
drivers/pinctrl/bcm/pinctrl-iproc-gpio.c
524
writel(val_1, base + IPROC_GPIO_PULL_UP_OFFSET);
drivers/pinctrl/bcm/pinctrl-iproc-gpio.c
525
writel(val_2, base + IPROC_GPIO_PULL_DN_OFFSET);
drivers/pinctrl/bcm/pinctrl-iproc-gpio.c
606
writel(val, base + offset);
drivers/pinctrl/bcm/pinctrl-ns.c
179
writel(tmp, ns_pinctrl->base);
drivers/pinctrl/bcm/pinctrl-ns2-mux.c
624
writel(val, (base_address + grp->mux.offset));
drivers/pinctrl/bcm/pinctrl-ns2-mux.c
670
writel(val, (base_address + pin_data->pin_conf.offset));
drivers/pinctrl/bcm/pinctrl-ns2-mux.c
716
writel(val, (base_address + pin_data->pin_conf.offset));
drivers/pinctrl/bcm/pinctrl-ns2-mux.c
758
writel(val, (base_address + pin_data->pin_conf.offset));
drivers/pinctrl/bcm/pinctrl-ns2-mux.c
807
writel(val, (base_address + pin_data->pin_conf.offset));
drivers/pinctrl/bcm/pinctrl-nsp-gpio.c
109
writel(val, base_address + reg);
drivers/pinctrl/bcm/pinctrl-nsp-gpio.c
163
writel(val, chip->base + NSP_GPIO_EVENT);
drivers/pinctrl/bcm/pinctrl-nsp-gpio.c
413
writel(val, chip->io_ctrl + offset);
drivers/pinctrl/bcm/pinctrl-nsp-gpio.c
669
writel(val, (chip->base + NSP_CHIP_A_INT_MASK));
drivers/pinctrl/bcm/pinctrl-nsp-mux.c
444
writel(val, base_address);
drivers/pinctrl/bcm/pinctrl-nsp-mux.c
488
writel(val, pinctrl->base0);
drivers/pinctrl/bcm/pinctrl-nsp-mux.c
510
writel(val, pinctrl->base0);
drivers/pinctrl/cix/pinctrl-sky1-base.c
293
writel(reg_val, pin_reg);
drivers/pinctrl/cix/pinctrl-sky1-base.c
372
writel(reg_val, pin_reg);
drivers/pinctrl/cix/pinctrl-sky1-base.c
403
writel(reg_val, pin_reg);
drivers/pinctrl/freescale/pinctrl-imx.c
187
writel(reg, ipctl->base + pin_reg->mux_reg);
drivers/pinctrl/freescale/pinctrl-imx.c
191
writel(pin_mmio->mux_mode, ipctl->base + pin_reg->mux_reg);
drivers/pinctrl/freescale/pinctrl-imx.c
222
writel(val, ipctl->base + pin_mmio->input_reg);
drivers/pinctrl/freescale/pinctrl-imx.c
229
writel(pin_mmio->input_val, ipctl->input_sel_base +
drivers/pinctrl/freescale/pinctrl-imx.c
232
writel(pin_mmio->input_val, ipctl->base +
drivers/pinctrl/freescale/pinctrl-imx.c
351
writel(reg, ipctl->base + pin_reg->conf_reg);
drivers/pinctrl/freescale/pinctrl-imx.c
355
writel(configs[i], ipctl->base + pin_reg->conf_reg);
drivers/pinctrl/freescale/pinctrl-imx1-core.c
112
writel(new_val, reg);
drivers/pinctrl/freescale/pinctrl-imx1-core.c
132
writel(new_val, reg);
drivers/pinctrl/freescale/pinctrl-imx7ulp.c
278
writel(reg, ipctl->base + pin_reg->mux_reg);
drivers/pinctrl/freescale/pinctrl-imx8ulp.c
237
writel(reg, ipctl->base + pin_reg->mux_reg);
drivers/pinctrl/freescale/pinctrl-mxs.c
200
writel(tmp, reg);
drivers/pinctrl/freescale/pinctrl-mxs.c
294
writel(1 << shift, reg + SET);
drivers/pinctrl/freescale/pinctrl-mxs.c
296
writel(1 << shift, reg + CLR);
drivers/pinctrl/freescale/pinctrl-mxs.c
305
writel(1 << shift, reg + SET);
drivers/pinctrl/freescale/pinctrl-mxs.c
307
writel(1 << shift, reg + CLR);
drivers/pinctrl/freescale/pinctrl-vf610.c
311
writel(reg, ipctl->base + pin_reg->mux_reg);
drivers/pinctrl/intel/pinctrl-baytrail.c
1023
writel(debounce, db_reg);
drivers/pinctrl/intel/pinctrl-baytrail.c
1036
writel(conf, conf_reg);
drivers/pinctrl/intel/pinctrl-baytrail.c
1080
writel(old_val | BYT_LEVEL, reg);
drivers/pinctrl/intel/pinctrl-baytrail.c
1082
writel(old_val & ~BYT_LEVEL, reg);
drivers/pinctrl/intel/pinctrl-baytrail.c
1119
writel(reg, val_reg);
drivers/pinctrl/intel/pinctrl-baytrail.c
1148
writel(reg, val_reg);
drivers/pinctrl/intel/pinctrl-baytrail.c
1270
writel(BIT(hwirq % 32), reg);
drivers/pinctrl/intel/pinctrl-baytrail.c
1319
writel(value, reg);
drivers/pinctrl/intel/pinctrl-baytrail.c
1349
writel(value, reg);
drivers/pinctrl/intel/pinctrl-baytrail.c
1474
writel(value, reg);
drivers/pinctrl/intel/pinctrl-baytrail.c
1498
writel(0xffffffff, reg);
drivers/pinctrl/intel/pinctrl-baytrail.c
1684
writel(value, reg);
drivers/pinctrl/intel/pinctrl-baytrail.c
1701
writel(v, reg);
drivers/pinctrl/intel/pinctrl-baytrail.c
632
writel(value, padcfg0);
drivers/pinctrl/intel/pinctrl-baytrail.c
658
writel(value, padcfg0);
drivers/pinctrl/intel/pinctrl-baytrail.c
707
writel(value, reg);
drivers/pinctrl/intel/pinctrl-baytrail.c
736
writel(value, reg);
drivers/pinctrl/intel/pinctrl-baytrail.c
787
writel(value, val_reg);
drivers/pinctrl/intel/pinctrl-baytrail.c
859
writel(value, reg);
drivers/pinctrl/intel/pinctrl-cherryview.c
579
writel(value, reg);
drivers/pinctrl/intel/pinctrl-cherryview.c
605
writel(value, reg);
drivers/pinctrl/intel/pinctrl-intel.c
1060
writel(padcfg0, reg);
drivers/pinctrl/intel/pinctrl-intel.c
1141
writel(BIT(gpp_offset), is);
drivers/pinctrl/intel/pinctrl-intel.c
1167
writel(BIT(gpp_offset), is);
drivers/pinctrl/intel/pinctrl-intel.c
1174
writel(value, reg);
drivers/pinctrl/intel/pinctrl-intel.c
1244
writel(value, reg);
drivers/pinctrl/intel/pinctrl-intel.c
1329
writel(0, reg);
drivers/pinctrl/intel/pinctrl-intel.c
1330
writel(0xffff, is);
drivers/pinctrl/intel/pinctrl-intel.c
1843
writel(updated, reg);
drivers/pinctrl/intel/pinctrl-intel.c
459
writel(value, padcfg0);
drivers/pinctrl/intel/pinctrl-intel.c
537
writel(value, padcfg0);
drivers/pinctrl/intel/pinctrl-intel.c
588
writel(value, padcfg0);
drivers/pinctrl/intel/pinctrl-intel.c
842
writel(value, padcfg1);
drivers/pinctrl/intel/pinctrl-intel.c
858
writel(value, padcfg0);
drivers/pinctrl/intel/pinctrl-intel.c
898
writel(value0, padcfg0);
drivers/pinctrl/intel/pinctrl-intel.c
899
writel(value2, padcfg2);
drivers/pinctrl/intel/pinctrl-tangier.c
132
writel(value, bufcfg);
drivers/pinctrl/mediatek/mtk-eint.c
122
writel(mask, reg + reg_offset);
drivers/pinctrl/mediatek/mtk-eint.c
142
writel(mask, reg);
drivers/pinctrl/mediatek/mtk-eint.c
156
writel(mask, reg);
drivers/pinctrl/mediatek/mtk-eint.c
179
writel(mask, reg);
drivers/pinctrl/mediatek/mtk-eint.c
211
writel(mask, reg);
drivers/pinctrl/mediatek/mtk-eint.c
214
writel(mask, reg);
drivers/pinctrl/mediatek/mtk-eint.c
219
writel(mask, reg);
drivers/pinctrl/mediatek/mtk-eint.c
222
writel(mask, reg);
drivers/pinctrl/mediatek/mtk-eint.c
327
writel(0xffffffff, dom_reg);
drivers/pinctrl/mediatek/mtk-eint.c
328
writel(0xffffffff, mask_reg);
drivers/pinctrl/mediatek/mtk-eint.c
351
writel(rst, eint->base[inst] + ctrl_offset);
drivers/pinctrl/mediatek/mtk-eint.c
395
writel(mask, reg);
drivers/pinctrl/mediatek/mtk-eint.c
414
writel(mask, reg);
drivers/pinctrl/mediatek/mtk-eint.c
481
writel(clr_bit, eint->base[inst] + clr_offset);
drivers/pinctrl/mediatek/mtk-eint.c
486
writel(rst | bit, eint->base[inst] + set_offset);
drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
1096
writel(info->pm.irq_en_l, info->base + IRQ_EN);
drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
1097
writel(info->pm.irq_en_h, info->base + IRQ_EN + sizeof(u32));
drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
1098
writel(info->pm.irq_pol_l, info->base + IRQ_POL);
drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
1099
writel(info->pm.irq_pol_h, info->base + IRQ_POL + sizeof(u32));
drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
539
writel(d->mask, info->base + reg);
drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
553
writel(val & ~d->mask, info->base + reg);
drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
569
writel(val | d->mask, info->base + reg);
drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
587
writel(val, info->base + reg);
drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
627
writel(val, info->base + reg);
drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
658
writel(p, info->base + IRQ_POL + 4 * reg_idx);
drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
702
writel(1 << hwirq,
drivers/pinctrl/mvebu/pinctrl-armada-xp.c
563
writel(mpp_saved_regs[i], soc->control_data[0].base + i * 4);
drivers/pinctrl/mvebu/pinctrl-dove.c
164
writel(mpp4, mpp4_base);
drivers/pinctrl/mvebu/pinctrl-dove.c
207
writel(pmu, data->base + PMU_MPP_GENERAL_CTRL);
drivers/pinctrl/mvebu/pinctrl-dove.c
251
writel(mpp4, mpp4_base);
drivers/pinctrl/mvebu/pinctrl-dove.c
90
writel(pmu & ~BIT(pid), data->base + PMU_MPP_GENERAL_CTRL);
drivers/pinctrl/mvebu/pinctrl-dove.c
94
writel(pmu | BIT(pid), data->base + PMU_MPP_GENERAL_CTRL);
drivers/pinctrl/mvebu/pinctrl-dove.c
98
writel(func, pmu_base + PMU_SIGNAL_SELECT_0 + off);
drivers/pinctrl/mvebu/pinctrl-mvebu.c
77
writel(reg | (config << shift), data->base + off);
drivers/pinctrl/mvebu/pinctrl-orion.c
54
writel(reg | (config << shift), mpp_base + off);
drivers/pinctrl/mvebu/pinctrl-orion.c
58
writel(reg | (config << shift), high_mpp_base);
drivers/pinctrl/nomadik/pinctrl-nomadik.c
227
writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA);
drivers/pinctrl/nomadik/pinctrl-nomadik.c
228
writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB);
drivers/pinctrl/nomadik/pinctrl-nomadik.c
244
writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS);
drivers/pinctrl/nomadik/pinctrl-nomadik.c
248
writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATS);
drivers/pinctrl/nomadik/pinctrl-nomadik.c
251
writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATC);
drivers/pinctrl/nomadik/pinctrl-nomadik.c
275
writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DIRC);
drivers/pinctrl/nomadik/pinctrl-nomadik.c
289
writel(rwimsc & ~bit, nmk_chip->addr + NMK_GPIO_RWIMSC);
drivers/pinctrl/nomadik/pinctrl-nomadik.c
290
writel(fwimsc & ~bit, nmk_chip->addr + NMK_GPIO_FWIMSC);
drivers/pinctrl/nomadik/pinctrl-nomadik.c
300
writel(rwimsc, nmk_chip->addr + NMK_GPIO_RWIMSC);
drivers/pinctrl/nomadik/pinctrl-nomadik.c
301
writel(fwimsc, nmk_chip->addr + NMK_GPIO_FWIMSC);
drivers/pinctrl/nomadik/pinctrl-nomadik.c
341
writel(val, reg);
drivers/pinctrl/nomadik/pinctrl-nomadik.c
464
writel(temp, chip->addr + NMK_GPIO_SLPC);
drivers/pinctrl/nomadik/pinctrl-nomadik.c
480
writel(slpm[i], chip->addr + NMK_GPIO_SLPC);
drivers/pinctrl/nuvoton/pinctrl-ma35.c
309
writel(regval, reg_mode);
drivers/pinctrl/nuvoton/pinctrl-ma35.c
345
writel(regval, reg_dout);
drivers/pinctrl/nuvoton/pinctrl-ma35.c
371
writel(regval, reg_dout);
drivers/pinctrl/nuvoton/pinctrl-ma35.c
404
writel(BIT(hwirq), reg_intsrc);
drivers/pinctrl/nuvoton/pinctrl-ma35.c
418
writel(regval, reg_ien);
drivers/pinctrl/nuvoton/pinctrl-ma35.c
432
writel(regval | bval, reg_itype);
drivers/pinctrl/nuvoton/pinctrl-ma35.c
437
writel(regval | bval, reg_ien);
drivers/pinctrl/nuvoton/pinctrl-ma35.c
469
writel(bank->irqtype, bank->reg_base + MA35_GP_REG_INTTYPE);
drivers/pinctrl/nuvoton/pinctrl-ma35.c
470
writel(bank->irqinten, bank->reg_base + MA35_GP_REG_INTEN);
drivers/pinctrl/nuvoton/pinctrl-ma35.c
642
writel(regval, base + MA35_GP_REG_PUSEL);
drivers/pinctrl/nuvoton/pinctrl-ma35.c
740
writel(regval, base + MA35_GP_REG_SPW);
drivers/pinctrl/nuvoton/pinctrl-ma35.c
799
writel(regval, base + MA35_GP_DS_REG(port));
drivers/pinctrl/nuvoton/pinctrl-ma35.c
834
writel(regval, base + MA35_GP_REG_SMTEN);
drivers/pinctrl/nuvoton/pinctrl-ma35.c
866
writel(regval, base + MA35_GP_REG_SLEWCTL);
drivers/pinctrl/pinctrl-amd.c
1034
writel(gpio_dev->saved_regs[i], gpio_dev->base + pin * 4);
drivers/pinctrl/pinctrl-amd.c
119
writel(pin_reg, gpio_dev->base + offset * 4);
drivers/pinctrl/pinctrl-amd.c
188
writel(pin_reg, gpio_dev->base + offset * 4);
drivers/pinctrl/pinctrl-amd.c
392
writel(pin_reg, gpio_dev->base + hwirq * 4);
drivers/pinctrl/pinctrl-amd.c
408
writel(pin_reg, gpio_dev->base + hwirq * 4);
drivers/pinctrl/pinctrl-amd.c
425
writel(pin_reg, gpio_dev->base + hwirq * 4);
drivers/pinctrl/pinctrl-amd.c
440
writel(pin_reg, gpio_dev->base + hwirq * 4);
drivers/pinctrl/pinctrl-amd.c
465
writel(pin_reg, gpio_dev->base + hwirq * 4);
drivers/pinctrl/pinctrl-amd.c
490
writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG);
drivers/pinctrl/pinctrl-amd.c
570
writel(pin_reg_irq_en, gpio_dev->base + hwirq * 4);
drivers/pinctrl/pinctrl-amd.c
573
writel(pin_reg, gpio_dev->base + hwirq * 4);
drivers/pinctrl/pinctrl-amd.c
67
writel(pin_reg, gpio_dev->base + offset * 4);
drivers/pinctrl/pinctrl-amd.c
670
writel(regval, regs + i);
drivers/pinctrl/pinctrl-amd.c
682
writel(regval, gpio_dev->base + WAKE_INT_MASTER_REG);
drivers/pinctrl/pinctrl-amd.c
821
writel(pin_reg, gpio_dev->base + pin*4);
drivers/pinctrl/pinctrl-amd.c
87
writel(pin_reg, gpio_dev->base + offset * 4);
drivers/pinctrl/pinctrl-amd.c
901
writel(pin_reg, gpio_dev->base + pin * 4);
drivers/pinctrl/pinctrl-amd.c
983
writel(gpio_dev->saved_regs[i] & ~BIT(INTERRUPT_MASK_OFF),
drivers/pinctrl/pinctrl-amdisp.c
132
writel(pin_reg, pctrl->gpiobase + gpio_offset[gpio]);
drivers/pinctrl/pinctrl-apple-gpio.c
268
writel(BIT(data->hwirq % 32), pctl->base + REG_IRQ(irqgrp, data->hwirq));
drivers/pinctrl/pinctrl-artpec6.c
687
writel(regval, pmx->base + reg);
drivers/pinctrl/pinctrl-artpec6.c
827
writel(regval, reg);
drivers/pinctrl/pinctrl-artpec6.c
840
writel(regval, reg);
drivers/pinctrl/pinctrl-artpec6.c
853
writel(regval, reg);
drivers/pinctrl/pinctrl-artpec6.c
867
writel(regval, reg);
drivers/pinctrl/pinctrl-da850-pupd.c
133
writel(sel, data->base + DA850_PUPD_SEL);
drivers/pinctrl/pinctrl-da850-pupd.c
134
writel(ena, data->base + DA850_PUPD_ENA);
drivers/pinctrl/pinctrl-equilibrium.c
326
writel(pmx, mem + (offset * 4));
drivers/pinctrl/pinctrl-equilibrium.c
34
writel(BIT(offset), gctrl->membase + GPIO_IRNENCLR);
drivers/pinctrl/pinctrl-equilibrium.c
49
writel(BIT(offset), gctrl->membase + GPIO_IRNRNSET);
drivers/pinctrl/pinctrl-equilibrium.c
525
writel(regval, mem);
drivers/pinctrl/pinctrl-equilibrium.c
61
writel(BIT(offset), gctrl->membase + GPIO_IRNCR);
drivers/pinctrl/pinctrl-equilibrium.c
73
writel(BIT(offset), gctrl->membase + GPIO_IRNENCLR);
drivers/pinctrl/pinctrl-equilibrium.c
74
writel(BIT(offset), gctrl->membase + GPIO_IRNCR);
drivers/pinctrl/pinctrl-equilibrium.c
82
writel(readl(addr) | BIT(offset), addr);
drivers/pinctrl/pinctrl-equilibrium.c
84
writel(readl(addr) & ~BIT(offset), addr);
drivers/pinctrl/pinctrl-eyeq5.c
207
writel((readl(ptr) & ~mask) | (val & mask), ptr);
drivers/pinctrl/pinctrl-k210.c
504
writel(val, &pdata->fpioa->pins[pin]);
drivers/pinctrl/pinctrl-k210.c
589
writel(val, &pdata->fpioa->pins[pin]);
drivers/pinctrl/pinctrl-k210.c
916
writel(val, &fpioa->tie_val[i]);
drivers/pinctrl/pinctrl-k210.c
917
writel(val, &fpioa->tie_en[i]);
drivers/pinctrl/pinctrl-keembay.c
885
writel(val, base + KEEMBAY_GPIO_REG_OFFSET(pin));
drivers/pinctrl/pinctrl-loongson2.c
217
writel(val, reg);
drivers/pinctrl/pinctrl-lpc18xx.c
1004
writel(reg_val, scu->base + reg_offset);
drivers/pinctrl/pinctrl-lpc18xx.c
1119
writel(reg, scu->base + pin_cap->offset);
drivers/pinctrl/pinctrl-lpc18xx.c
1180
writel(LPC18XX_SCU_ANALOG_PIN_CFG, scu->base + pin->offset);
drivers/pinctrl/pinctrl-lpc18xx.c
1189
writel(reg, scu->base + offset);
drivers/pinctrl/pinctrl-lpc18xx.c
1195
writel(LPC18XX_SCU_ANALOG_PIN_CFG, scu->base + pin->offset);
drivers/pinctrl/pinctrl-lpc18xx.c
1199
writel(reg, scu->base + LPC18XX_SCU_REG_ENAIO2);
drivers/pinctrl/pinctrl-lpc18xx.c
1214
writel(reg | func, scu->base + pin->offset);
drivers/pinctrl/pinctrl-mlxbf3.c
197
writel(BIT(group), priv->fw_ctrl_clr0);
drivers/pinctrl/pinctrl-mlxbf3.c
199
writel(BIT(group % MLXBF3_NGPIOS_GPIO0), priv->fw_ctrl_clr1);
drivers/pinctrl/pinctrl-mlxbf3.c
204
writel(BIT(group), priv->fw_ctrl_set0);
drivers/pinctrl/pinctrl-mlxbf3.c
206
writel(BIT(group % MLXBF3_NGPIOS_GPIO0), priv->fw_ctrl_set1);
drivers/pinctrl/pinctrl-mlxbf3.c
219
writel(BIT(offset), priv->fw_ctrl_set0);
drivers/pinctrl/pinctrl-mlxbf3.c
221
writel(BIT(offset % MLXBF3_NGPIOS_GPIO0), priv->fw_ctrl_set1);
drivers/pinctrl/pinctrl-ocelot.c
31
writel((readl(addr) & ~(clear)) | (set), (addr))
drivers/pinctrl/pinctrl-pic32.c
1783
writel(functions->muxval, pctl->reg_base + functions->muxreg);
drivers/pinctrl/pinctrl-pic32.c
1807
writel(mask, bank->reg_base + PIC32_CLR(ANSEL_REG));
drivers/pinctrl/pinctrl-pic32.c
1818
writel(mask, bank->reg_base + PIC32_SET(TRIS_REG));
drivers/pinctrl/pinctrl-pic32.c
1837
writel(mask, bank->reg_base + PIC32_SET(PORT_REG));
drivers/pinctrl/pinctrl-pic32.c
1839
writel(mask, bank->reg_base + PIC32_CLR(PORT_REG));
drivers/pinctrl/pinctrl-pic32.c
1851
writel(mask, bank->reg_base + PIC32_CLR(TRIS_REG));
drivers/pinctrl/pinctrl-pic32.c
1941
writel(mask, bank->reg_base +PIC32_SET(CNPU_REG));
drivers/pinctrl/pinctrl-pic32.c
1945
writel(mask, bank->reg_base + PIC32_SET(CNPD_REG));
drivers/pinctrl/pinctrl-pic32.c
1949
writel(mask, bank->reg_base + PIC32_CLR(ANSEL_REG));
drivers/pinctrl/pinctrl-pic32.c
1953
writel(mask, bank->reg_base + PIC32_SET(ANSEL_REG));
drivers/pinctrl/pinctrl-pic32.c
1957
writel(mask, bank->reg_base + PIC32_SET(ODCU_REG));
drivers/pinctrl/pinctrl-pic32.c
2004
writel(0, bank->reg_base + CNF_REG);
drivers/pinctrl/pinctrl-pic32.c
2011
writel(BIT(PIC32_CNCON_ON), bank->reg_base + PIC32_CLR(CNCON_REG));
drivers/pinctrl/pinctrl-pic32.c
2020
writel(BIT(PIC32_CNCON_ON), bank->reg_base + PIC32_SET(CNCON_REG));
drivers/pinctrl/pinctrl-pic32.c
2041
writel(mask, bank->reg_base + PIC32_SET(CNEN_REG));
drivers/pinctrl/pinctrl-pic32.c
2043
writel(mask, bank->reg_base + PIC32_CLR(CNNE_REG));
drivers/pinctrl/pinctrl-pic32.c
2045
writel(BIT(PIC32_CNCON_EDGE), bank->reg_base + PIC32_SET(CNCON_REG));
drivers/pinctrl/pinctrl-pic32.c
2049
writel(mask, bank->reg_base + PIC32_CLR(CNEN_REG));
drivers/pinctrl/pinctrl-pic32.c
2051
writel(mask, bank->reg_base + PIC32_SET(CNNE_REG));
drivers/pinctrl/pinctrl-pic32.c
2053
writel(BIT(PIC32_CNCON_EDGE), bank->reg_base + PIC32_SET(CNCON_REG));
drivers/pinctrl/pinctrl-pic32.c
2057
writel(mask, bank->reg_base + PIC32_SET(CNEN_REG));
drivers/pinctrl/pinctrl-pic32.c
2059
writel(mask, bank->reg_base + PIC32_SET(CNNE_REG));
drivers/pinctrl/pinctrl-pic32.c
2061
writel(BIT(PIC32_CNCON_EDGE), bank->reg_base + PIC32_SET(CNCON_REG));
drivers/pinctrl/pinctrl-pistachio.c
839
writel(val, pctl->base + reg);
drivers/pinctrl/pinctrl-pistachio.c
855
writel(val, bank->base + reg);
drivers/pinctrl/pinctrl-single.c
265
writel(val, reg);
drivers/pinctrl/pinctrl-st.c
1297
writel(BIT(irqd_to_hwirq(d)), bank->base + REG_PIO_CLR_PMASK);
drivers/pinctrl/pinctrl-st.c
1307
writel(BIT(irqd_to_hwirq(d)), bank->base + REG_PIO_SET_PMASK);
drivers/pinctrl/pinctrl-st.c
1367
writel(val, bank->base + REG_PIO_PCOMP);
drivers/pinctrl/pinctrl-st.c
1424
writel(BIT(n),
drivers/pinctrl/pinctrl-st.c
667
writel(BIT(offset), bank->base + REG_PIO_SET_POUT);
drivers/pinctrl/pinctrl-st.c
669
writel(BIT(offset), bank->base + REG_PIO_CLR_POUT);
drivers/pinctrl/pinctrl-st.c
696
writel(BIT(offset), bank->base + REG_PIO_SET_PC(i));
drivers/pinctrl/pinctrl-st.c
698
writel(BIT(offset), bank->base + REG_PIO_CLR_PC(i));
drivers/pinctrl/qcom/pinctrl-msm.c
1473
writel(0, pctrl->regs[0] + PS_HOLD_OFFSET);
drivers/pinctrl/qcom/pinctrl-msm.c
94
writel(val, pctrl->regs[g->tile] + g->name##_reg); \
drivers/pinctrl/qcom/tlmm-test.c
88
writel(tlmm_suite.low_val, tlmm_suite.reg);
drivers/pinctrl/qcom/tlmm-test.c
94
writel(tlmm_suite.high_val, tlmm_suite.reg);
drivers/pinctrl/renesas/pinctrl-rzg2l.c
214
writel(_val, _addr); \
drivers/pinctrl/renesas/pinctrl-rzg2l.c
2473
writel(readl(addr) | BIT(bit * 8), addr);
drivers/pinctrl/renesas/pinctrl-rzg2l.c
2475
writel(readl(addr) & ~BIT(bit * 8), addr);
drivers/pinctrl/renesas/pinctrl-rzg2l.c
3175
writel(pfc, pctrl->base + PFC(off));
drivers/pinctrl/renesas/pinctrl-rzg2l.c
3257
writel(0x0, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=0 */
drivers/pinctrl/renesas/pinctrl-rzg2l.c
3258
writel(PWPR_B0WI, pctrl->base + regs->pwpr); /* B0WI=1, PFCWE=0 */
drivers/pinctrl/renesas/pinctrl-rzg2l.c
3261
writel(0x0, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=0 */
drivers/pinctrl/renesas/pinctrl-rzg2l.c
3262
writel(PWPR_PFCWE, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=1 */
drivers/pinctrl/renesas/pinctrl-rzg2l.c
568
writel(pfc | (func << (pin * 4)), pctrl->base + PFC(off));
drivers/pinctrl/renesas/pinctrl-rzg2l.c
893
writel(reg | (val << (bit * 8)), addr);
drivers/pinctrl/renesas/pinctrl-rzn1.c
189
writel(val, &ipctl->lev1->status_protect);
drivers/pinctrl/renesas/pinctrl-rzn1.c
195
writel(val, &ipctl->lev2->status_protect);
drivers/pinctrl/renesas/pinctrl-rzn1.c
208
writel(func, &ipctl->lev2->l2_mdio[mdio]);
drivers/pinctrl/renesas/pinctrl-rzn1.c
279
writel(l1, &ipctl->lev1->conf[pin]);
drivers/pinctrl/renesas/pinctrl-rzn1.c
280
writel(l2, &ipctl->lev2->conf[pin]);
drivers/pinctrl/renesas/pinctrl-rzn1.c
613
writel(l1, &ipctl->lev1->conf[pin]);
drivers/pinctrl/renesas/pinctrl-rzv2m.c
139
writel((BIT(16) | value) << shift, addr);
drivers/pinctrl/renesas/pinctrl-rzv2m.c
153
writel(((PFC_MASK << 16) | func) << ((pin % 4) * 4), addr);
drivers/pinctrl/renesas/pinctrl-rzv2m.c
449
writel(reg | (val << shift), addr);
drivers/pinctrl/samsung/pinctrl-exynos.c
1022
writel(save->eint_con, regs + EXYNOS_GPIO_ECON_OFFSET
drivers/pinctrl/samsung/pinctrl-exynos.c
1024
writel(save->eint_fltcon0, regs + EXYNOS_GPIO_EFLTCON_OFFSET
drivers/pinctrl/samsung/pinctrl-exynos.c
1026
writel(save->eint_fltcon1, regs + EXYNOS_GPIO_EFLTCON_OFFSET
drivers/pinctrl/samsung/pinctrl-exynos.c
1028
writel(save->eint_mask, regs + bank->irq_chip->eint_mask
drivers/pinctrl/samsung/pinctrl-exynos.c
1050
writel(save->eint_con,
drivers/pinctrl/samsung/pinctrl-exynos.c
1052
writel(save->eint_mask,
drivers/pinctrl/samsung/pinctrl-exynos.c
107
writel(1 << irqd->hwirq, bank->eint_base + reg_pend);
drivers/pinctrl/samsung/pinctrl-exynos.c
147
writel(mask, bank->eint_base + reg_mask);
drivers/pinctrl/samsung/pinctrl-exynos.c
205
writel(con, bank->eint_base + reg_con);
drivers/pinctrl/samsung/pinctrl-exynos.c
258
writel(con, bank->pctl_base + reg_con);
drivers/pinctrl/samsung/pinctrl-exynos.c
290
writel(con, bank->pctl_base + reg_con);
drivers/pinctrl/samsung/pinctrl-exynos.c
390
writel(val, reg);
drivers/pinctrl/samsung/pinctrl-exynos.c
82
writel(mask, bank->eint_base + reg_mask);
drivers/pinctrl/samsung/pinctrl-exynos.c
989
writel(save->eint_con, regs + EXYNOS_GPIO_ECON_OFFSET
drivers/pinctrl/samsung/pinctrl-exynos.c
991
writel(save->eint_fltcon0, eint_fltcfg0);
drivers/pinctrl/samsung/pinctrl-exynos.c
994
writel(save->eint_fltcon1, eint_fltcfg0 + 4);
drivers/pinctrl/samsung/pinctrl-exynos.c
995
writel(save->eint_mask, regs + bank->irq_chip->eint_mask
drivers/pinctrl/samsung/pinctrl-s3c64xx.c
307
writel(val, reg);
drivers/pinctrl/samsung/pinctrl-s3c64xx.c
329
writel(val, reg);
drivers/pinctrl/samsung/pinctrl-s3c64xx.c
349
writel(1 << index, reg);
drivers/pinctrl/samsung/pinctrl-s3c64xx.c
377
writel(val, reg);
drivers/pinctrl/samsung/pinctrl-s3c64xx.c
533
writel(val, d->virt_base + EINT0MASK_REG);
drivers/pinctrl/samsung/pinctrl-s3c64xx.c
552
writel(1 << ddata->eints[irqd->hwirq],
drivers/pinctrl/samsung/pinctrl-s3c64xx.c
587
writel(val, reg);
drivers/pinctrl/samsung/pinctrl-samsung.c
1022
writel(data, reg + type->reg_offset[PINCFG_TYPE_PUD]);
drivers/pinctrl/samsung/pinctrl-samsung.c
1445
writel(bank->pm_save[PINCFG_TYPE_NUM],
drivers/pinctrl/samsung/pinctrl-samsung.c
1454
writel(bank->pm_save[type], reg + offs[type]);
drivers/pinctrl/samsung/pinctrl-samsung.c
411
writel(data, reg + type->reg_offset[PINCFG_TYPE_FUNC]);
drivers/pinctrl/samsung/pinctrl-samsung.c
476
writel(data, reg_base + cfg_reg);
drivers/pinctrl/samsung/pinctrl-samsung.c
569
writel(data, reg + type->reg_offset[PINCFG_TYPE_DAT]);
drivers/pinctrl/samsung/pinctrl-samsung.c
655
writel(data, reg);
drivers/pinctrl/sophgo/pinctrl-cv18xx.c
401
writel(reg, addr);
drivers/pinctrl/sophgo/pinctrl-sg2042-ops.c
82
writel(v, reg);
drivers/pinctrl/sprd/pinctrl-sprd.c
424
writel(reg, (void __iomem *)pin->reg);
drivers/pinctrl/sprd/pinctrl-sprd.c
728
writel(reg, (void __iomem *)pin->reg);
drivers/pinctrl/sprd/pinctrl-sprd.c
733
writel(reg, (void __iomem *)pin->reg);
drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c
1200
writel(0, sfp->base + GPIOIE + 0);
drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c
1201
writel(0, sfp->base + GPIOIE + 4);
drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c
1203
writel(~0U, sfp->base + GPIOIC + 0);
drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c
1204
writel(~0U, sfp->base + GPIOIC + 4);
drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c
1206
writel(1, sfp->base + GPIOEN);
drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c
1273
writel(value, sfp->padctl + IO_PADSHARE_SEL);
drivers/pinctrl/starfive/pinctrl-starfive-jh7110-sys.c
385
writel(0U, sfp->base + JH7110_SYS_GPIOIE0);
drivers/pinctrl/starfive/pinctrl-starfive-jh7110-sys.c
386
writel(0U, sfp->base + JH7110_SYS_GPIOIE1);
drivers/pinctrl/starfive/pinctrl-starfive-jh7110-sys.c
388
writel(~0U, sfp->base + JH7110_SYS_GPIOIC0);
drivers/pinctrl/starfive/pinctrl-starfive-jh7110-sys.c
389
writel(~0U, sfp->base + JH7110_SYS_GPIOIC1);
drivers/pinctrl/starfive/pinctrl-starfive-jh7110-sys.c
391
writel(1U, sfp->base + JH7110_SYS_GPIOEN);
drivers/pinctrl/sunplus/sppctl.c
109
writel(val, spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_OD + off);
drivers/pinctrl/sunplus/sppctl.c
204
writel(reg, pctl->moon2_base + offset);
drivers/pinctrl/sunplus/sppctl.c
240
writel(reg, pctl->moon1_base + reg_off * 4);
drivers/pinctrl/sunplus/sppctl.c
46
writel(val, spp_gchip->first_base + SPPCTL_GPIO_OFF_FIRST + off);
drivers/pinctrl/sunplus/sppctl.c
57
writel(val, spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_MASTER + off);
drivers/pinctrl/sunplus/sppctl.c
67
writel(val, spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_OE + off);
drivers/pinctrl/sunplus/sppctl.c
72
writel(val, spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_OUT + off);
drivers/pinctrl/sunplus/sppctl.c
88
writel(val, spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_IINV + off);
drivers/pinctrl/sunplus/sppctl.c
99
writel(val, spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_OINV + off);
drivers/pinctrl/sunxi/pinctrl-sunxi.c
1034
writel(val, pctl->membase + reg);
drivers/pinctrl/sunxi/pinctrl-sunxi.c
1180
writel(regval | (mode << index), pctl->membase + reg);
drivers/pinctrl/sunxi/pinctrl-sunxi.c
1194
writel(1 << status_idx, pctl->membase + status_reg);
drivers/pinctrl/sunxi/pinctrl-sunxi.c
1209
writel(val & ~(1 << idx), pctl->membase + reg);
drivers/pinctrl/sunxi/pinctrl-sunxi.c
1226
writel(val | (1 << idx), pctl->membase + reg);
drivers/pinctrl/sunxi/pinctrl-sunxi.c
1558
writel(src | div << 4,
drivers/pinctrl/sunxi/pinctrl-sunxi.c
1747
writel(0, pctl->membase +
drivers/pinctrl/sunxi/pinctrl-sunxi.c
1749
writel(0xffffffff,
drivers/pinctrl/sunxi/pinctrl-sunxi.c
699
writel((readl(pctl->membase + reg) & ~mask) | val << shift,
drivers/pinctrl/sunxi/pinctrl-sunxi.c
767
writel(reg | val, pctl->membase + sunxi_grp_config_reg(pin));
drivers/pinctrl/sunxi/pinctrl-sunxi.c
776
writel(reg | val, pctl->membase + pctl->pow_mod_sel_offset +
drivers/pinctrl/sunxi/pinctrl-sunxi.c
787
writel(reg | val << bank,
drivers/pinctrl/sunxi/pinctrl-sunxi.c
837
writel((readl(pctl->membase + reg) & ~mask) | config << shift,
drivers/pinctrl/tegra/pinctrl-tegra-xusb.c
99
writel(value, padctl->regs + offset);
drivers/pinctrl/visconti/pinctrl-common.c
109
writel(val, priv->base + pin->dsel_offset);
drivers/pinctrl/visconti/pinctrl-common.c
239
writel(val, priv->base + mux->offset);
drivers/pinctrl/visconti/pinctrl-common.c
264
writel(val, priv->base + gpio_mux->offset);
drivers/pinctrl/visconti/pinctrl-common.c
67
writel(val, priv->base + pin->pudsel_offset);
drivers/pinctrl/visconti/pinctrl-common.c
75
writel(val, priv->base + pin->pude_offset);
drivers/pinctrl/visconti/pinctrl-tmpv7700.c
317
writel(1, base + REG_KEY_CTRL);
drivers/pinctrl/visconti/pinctrl-tmpv7700.c
318
writel(tmpv7700_MAGIC_NUM, base + REG_KEY_CMD);
drivers/platform/goldfish/goldfish_pipe.c
223
writel(pipe->id, pipe->dev->base + PIPE_REG_CMD);
drivers/platform/goldfish/goldfish_pipe.c
801
writel(upper_32_bits(paddr), porth);
drivers/platform/goldfish/goldfish_pipe.c
802
writel(lower_32_bits(paddr), portl);
drivers/platform/goldfish/goldfish_pipe.c
855
writel(MAX_SIGNALLED_PIPES,
drivers/platform/goldfish/goldfish_pipe.c
908
writel(PIPE_DRIVER_VERSION, dev->base + PIPE_REG_VERSION);
drivers/platform/mellanox/mlxbf-pmc.c
1089
writel(value, addr);
drivers/platform/mips/ls2k-reset.c
19
writel(0x1, base + RST_CNT);
drivers/platform/mips/ls2k-reset.c
25
writel((readl(base + PM1_STS) & 0xffffffff), base + PM1_STS);
drivers/platform/mips/ls2k-reset.c
27
writel(GENMASK(12, 10) | BIT(13), base + PM1_CNT);
drivers/platform/raspberrypi/vchiq-interface/vchiq_core.c
562
writel(0, mgmt->regs + BELL2); /* trigger vc interrupt */
drivers/platform/x86/amd/pmc/mp2_stb.c
96
writel(cmd_base.ul, mp2->mmio + AMD_C2P_MSG0);
drivers/platform/x86/intel/pmc/core.c
74
writel(val, pmc->regbase + reg_offset);
drivers/platform/x86/intel/pmt/crashlog.c
141
writel(reg, entry->disc_table + control->offset);
drivers/platform/x86/intel/punit_ipc.c
58
writel(cmd, ipcdev->base[type][BASE_IFACE]);
drivers/platform/x86/intel/punit_ipc.c
73
writel(data, ipcdev->base[type][BASE_DATA] + OFFSET_DATA_LOW);
drivers/platform/x86/intel/punit_ipc.c
78
writel(data, ipcdev->base[type][BASE_DATA] + OFFSET_DATA_HIGH);
drivers/platform/x86/intel/speed_select_if/isst_if_mmio.c
177
writel(punit_dev->range_0[i], punit_dev->punit_mmio +
drivers/platform/x86/intel/speed_select_if/isst_if_mmio.c
186
writel(punit_dev->range_1[i], punit_dev->punit_mmio + addr);
drivers/platform/x86/intel/speed_select_if/isst_if_mmio.c
74
writel(io_reg->value, punit_dev->punit_mmio+io_reg->reg);
drivers/platform/x86/intel/vsec_tpmi.c
500
writel(value, mem + addr);
drivers/platform/x86/intel_ips.c
236
#define thm_writel(off, val) writel((val), ips->regmap + (off))
drivers/platform/x86/intel_scu_ipc.c
193
writel(cmd | IPC_IOC, scu->ipc_base);
drivers/platform/x86/intel_scu_ipc.c
204
writel(data, scu->ipc_base + IPC_WRITE_BUFFER + offset);
drivers/platform/x86/intel_scu_ipc.c
531
writel(status | IPC_STATUS_IRQ, scu->ipc_base + IPC_STATUS);
drivers/platform/x86/pmc_atom.c
213
writel(val, pmc->regmap + reg_offset);
drivers/platform/x86/samsung-laptop.c
415
writel(in->d0, samsung->sabi_iface + SABI_IFACE_DATA);
drivers/platform/x86/samsung-laptop.c
416
writel(in->d1, samsung->sabi_iface + SABI_IFACE_DATA + 4);
drivers/pmdomain/actions/owl-sps-helper.c
33
writel(val, base + OWL_SPS_PG_CTL);
drivers/pmdomain/bcm/bcm2835-power.c
112
#define PM_WRITE(reg, val) writel(PM_PASSWORD | (val), power->base + (reg))
drivers/pmdomain/bcm/bcm2835-power.c
175
writel(PM_PASSWORD | val, base + reg);
drivers/pmdomain/imx/imx93-pd.c
50
writel(val, addr + MIX_SLICE_SW_CTRL_OFF);
drivers/pmdomain/imx/imx93-pd.c
72
writel(val, addr + MIX_SLICE_SW_CTRL_OFF);
drivers/pmdomain/mediatek/mtk-mfg-pmdomain.c
296
writel((readl(addr) & ~mask) | (val & mask), addr);
drivers/pmdomain/mediatek/mtk-scpsys.c
241
writel(val, ctl_addr);
drivers/pmdomain/mediatek/mtk-scpsys.c
271
writel(val, ctl_addr);
drivers/pmdomain/mediatek/mtk-scpsys.c
322
writel(val, ctl_addr);
drivers/pmdomain/mediatek/mtk-scpsys.c
324
writel(val, ctl_addr);
drivers/pmdomain/mediatek/mtk-scpsys.c
333
writel(val, ctl_addr);
drivers/pmdomain/mediatek/mtk-scpsys.c
336
writel(val, ctl_addr);
drivers/pmdomain/mediatek/mtk-scpsys.c
339
writel(val, ctl_addr);
drivers/pmdomain/mediatek/mtk-scpsys.c
380
writel(val, ctl_addr);
drivers/pmdomain/mediatek/mtk-scpsys.c
383
writel(val, ctl_addr);
drivers/pmdomain/mediatek/mtk-scpsys.c
386
writel(val, ctl_addr);
drivers/pmdomain/mediatek/mtk-scpsys.c
389
writel(val, ctl_addr);
drivers/pmdomain/mediatek/mtk-scpsys.c
392
writel(val, ctl_addr);
drivers/pmdomain/renesas/rmobile-sysc.c
60
writel(mask, rmobile_pd->base + SPDCR);
drivers/pmdomain/renesas/rmobile-sysc.c
80
writel(mask, rmobile_pd->base + SWUCR);
drivers/pmdomain/starfive/jh71xx-pmu.c
129
writel(mask, pmu->base + mode);
drivers/pmdomain/starfive/jh71xx-pmu.c
139
writel(JH71XX_PMU_SW_ENCOURAGE_ON, pmu->base + JH71XX_PMU_SW_ENCOURAGE);
drivers/pmdomain/starfive/jh71xx-pmu.c
140
writel(encourage_lo, pmu->base + JH71XX_PMU_SW_ENCOURAGE);
drivers/pmdomain/starfive/jh71xx-pmu.c
141
writel(encourage_hi, pmu->base + JH71XX_PMU_SW_ENCOURAGE);
drivers/pmdomain/starfive/jh71xx-pmu.c
179
writel(val, pmu->base + JH71XX_AON_PMU_SWITCH);
drivers/pmdomain/starfive/jh71xx-pmu.c
239
writel(val, pmu->base + JH71XX_PMU_TIMER_INT_MASK);
drivers/pmdomain/starfive/jh71xx-pmu.c
262
writel(val, pmu->base + JH71XX_PMU_INT_STATUS);
drivers/pmdomain/starfive/jh71xx-pmu.c
263
writel(val, pmu->base + JH71XX_PMU_EVENT_STATUS);
drivers/pmdomain/sunxi/sun20i-ppu.c
73
writel(state, pd->base + PD_COMMAND_REG);
drivers/pmdomain/sunxi/sun20i-ppu.c
83
writel(status, pd->base + PD_STATUS_REG);
drivers/pmdomain/sunxi/sun50i-h6-prcm-ppu.c
97
writel(reg | pd->gate_mask, pd->reg);
drivers/pmdomain/sunxi/sun50i-h6-prcm-ppu.c
99
writel(reg & ~pd->gate_mask, pd->reg);
drivers/pmdomain/sunxi/sun55i-pck600.c
114
writel(desc->device_ctrl0_delay, pd->base + PPU_DCDR0);
drivers/pmdomain/sunxi/sun55i-pck600.c
115
writel(desc->device_ctrl1_delay, pd->base + PPU_DCDR1);
drivers/pmdomain/sunxi/sun55i-pck600.c
116
writel(desc->logic_power_switch0_delay,
drivers/pmdomain/sunxi/sun55i-pck600.c
118
writel(desc->logic_power_switch1_delay,
drivers/pmdomain/sunxi/sun55i-pck600.c
120
writel(desc->off2on_delay, pd->base + desc->off2on_delay_offset);
drivers/pmdomain/sunxi/sun55i-pck600.c
82
writel(reg, pd->base + PPU_PWPR);
drivers/power/reset/at91-poweroff.c
149
writel(wakeup_mode | mode, at91_shdwc.shdwc_base + AT91_SHDW_MR);
drivers/power/reset/at91-reset.c
396
writel(AT91_RSTC_KEY | AT91_RSTC_URSTASYNC | val,
drivers/power/reset/at91-sama5d2_shdwc.c
254
writel(mode, shdw->shdwc_base + AT91_SHDW_MR);
drivers/power/reset/at91-sama5d2_shdwc.c
257
writel(input, shdw->shdwc_base + AT91_SHDW_WUIR);
drivers/power/reset/at91-sama5d2_shdwc.c
434
writel(0, shdw->shdwc_base + AT91_SHDW_MR);
drivers/power/reset/at91-sama5d2_shdwc.c
435
writel(0, shdw->shdwc_base + AT91_SHDW_WUIR);
drivers/power/reset/brcm-kona-reset.c
25
writel((RSTMGR_WR_PASSWORD << RSTMGR_WR_PASSWORD_SHIFT) |
drivers/power/reset/brcm-kona-reset.c
28
writel(0, kona_reset_base + RSTMGR_REG_CHIP_SOFT_RST_OFFSET);
drivers/power/reset/gemini-poweroff.c
128
writel(val, gpw->base + GEMINI_PWC_CTRLREG);
drivers/power/reset/gemini-poweroff.c
133
writel(val, gpw->base + GEMINI_PWC_CTRLREG);
drivers/power/reset/gemini-poweroff.c
143
writel(val, gpw->base + GEMINI_PWC_CTRLREG);
drivers/power/reset/gemini-poweroff.c
44
writel(val, gpw->base + GEMINI_PWC_CTRLREG);
drivers/power/reset/gemini-poweroff.c
81
writel(val, gpw->base + GEMINI_PWC_CTRLREG);
drivers/power/reset/gemini-poweroff.c
85
writel(val, gpw->base + GEMINI_PWC_CTRLREG);
drivers/power/reset/msm-poweroff.c
20
writel(0, msm_ps_hold);
drivers/power/reset/ocelot-reset.c
63
writel(SOFT_CHIP_RST, ctx->base);
drivers/power/reset/qnap-poweroff.c
60
writel(0x83, UART1_REG(LCR));
drivers/power/reset/qnap-poweroff.c
61
writel(divisor & 0xff, UART1_REG(DLL));
drivers/power/reset/qnap-poweroff.c
62
writel((divisor >> 8) & 0xff, UART1_REG(DLM));
drivers/power/reset/qnap-poweroff.c
63
writel(0x03, UART1_REG(LCR));
drivers/power/reset/qnap-poweroff.c
64
writel(0x00, UART1_REG(IER));
drivers/power/reset/qnap-poweroff.c
65
writel(0x00, UART1_REG(FCR));
drivers/power/reset/qnap-poweroff.c
66
writel(0x00, UART1_REG(MCR));
drivers/power/reset/qnap-poweroff.c
69
writel(cfg->cmd, UART1_REG(TX));
drivers/power/reset/rmobile-reset.c
27
writel(RESCNT2_PRES, sysc_base2 + RESCNT2);
drivers/power/reset/xgene-reboot.c
34
writel(ctx->mask, ctx->csr);
drivers/power/supply/goldfish_battery.c
33
(writel(x, data->reg_base + addr))
drivers/pps/generators/pps_gen_tio.c
59
writel(value, tio->base + TIOCTL);
drivers/ptp/ptp_dfl_tod.c
119
writel(seconds_msb, base + TOD_SECONDSH);
drivers/ptp/ptp_dfl_tod.c
120
writel(seconds_lsb, base + TOD_SECONDSL);
drivers/ptp/ptp_dfl_tod.c
121
writel(nanosec, base + TOD_NANOSEC);
drivers/ptp/ptp_dfl_tod.c
161
writel(tod_period, base + TOD_PERIOD);
drivers/ptp/ptp_dfl_tod.c
162
writel(0, base + TOD_ADJUST_PERIOD);
drivers/ptp/ptp_dfl_tod.c
163
writel(0, base + TOD_ADJUST_COUNT);
drivers/ptp/ptp_dfl_tod.c
164
writel(tod_drift_adjust_fns, base + TOD_DRIFT_ADJUST);
drivers/ptp/ptp_dfl_tod.c
165
writel(tod_drift_adjust_rate, base + TOD_DRIFT_ADJUST_RATE);
drivers/ptp/ptp_dfl_tod.c
262
writel(seconds_msb, base + TOD_SECONDSH);
drivers/ptp/ptp_dfl_tod.c
263
writel(seconds_lsb, base + TOD_SECONDSL);
drivers/ptp/ptp_dfl_tod.c
264
writel(nanosec, base + TOD_NANOSEC);
drivers/ptp/ptp_dfl_tod.c
86
writel(adjust_period, base + TOD_ADJUST_PERIOD);
drivers/ptp/ptp_dfl_tod.c
87
writel(adjust_count, base + TOD_ADJUST_COUNT);
drivers/ptp/ptp_dte.c
155
writel(nco_incr, ptp_dte->regs + DTE_NCO_INC_REG);
drivers/ptp/ptp_dte.c
194
writel(0, ptp_dte->regs + DTE_NCO_INC_REG);
drivers/ptp/ptp_dte.c
203
writel(DTE_NCO_INC_DEFAULT, ptp_dte->regs + DTE_NCO_INC_REG);
drivers/ptp/ptp_dte.c
269
writel(0, ptp_dte->regs + (i * sizeof(u32)));
drivers/ptp/ptp_dte.c
284
writel(0, ptp_dte->regs + DTE_NCO_INC_REG);
drivers/ptp/ptp_dte.c
296
writel(ptp_dte->reg_val[i],
drivers/ptp/ptp_dte.c
299
writel(((ptp_dte->reg_val[i] &
drivers/ptp/ptp_dte.c
65
writel(0, (regs + DTE_NCO_LOW_TIME_REG));
drivers/ptp/ptp_dte.c
66
writel(sum2, (regs + DTE_NCO_TIME_REG));
drivers/ptp/ptp_dte.c
67
writel(sum3, (regs + DTE_NCO_OVERFLOW_REG));
drivers/pwm/pwm-apple.c
66
writel(on_cycles, fpwm->base + APPLE_PWM_ON_CYCLES);
drivers/pwm/pwm-apple.c
67
writel(off_cycles, fpwm->base + APPLE_PWM_OFF_CYCLES);
drivers/pwm/pwm-apple.c
68
writel(APPLE_PWM_CTRL_ENABLE | APPLE_PWM_CTRL_OUTPUT_ENABLE | APPLE_PWM_CTRL_UPDATE,
drivers/pwm/pwm-apple.c
71
writel(0, fpwm->base + APPLE_PWM_CTRL);
drivers/pwm/pwm-bcm-iproc.c
160
writel(value, ip->base + IPROC_PWM_PRESCALE_OFFSET);
drivers/pwm/pwm-bcm-iproc.c
163
writel(period, ip->base + IPROC_PWM_PERIOD_OFFSET(pwm->hwpwm));
drivers/pwm/pwm-bcm-iproc.c
164
writel(duty, ip->base + IPROC_PWM_DUTY_CYCLE_OFFSET(pwm->hwpwm));
drivers/pwm/pwm-bcm-iproc.c
174
writel(value, ip->base + IPROC_PWM_CTRL_OFFSET);
drivers/pwm/pwm-bcm-iproc.c
221
writel(value, ip->base + IPROC_PWM_CTRL_OFFSET);
drivers/pwm/pwm-bcm-iproc.c
52
writel(value, ip->base + IPROC_PWM_CTRL_OFFSET);
drivers/pwm/pwm-bcm-iproc.c
64
writel(value, ip->base + IPROC_PWM_CTRL_OFFSET);
drivers/pwm/pwm-bcm-kona.c
145
writel(value, kp->base + PRESCALE_OFFSET);
drivers/pwm/pwm-bcm-kona.c
147
writel(pc, kp->base + PERIOD_COUNT_OFFSET(chan));
drivers/pwm/pwm-bcm-kona.c
149
writel(dc, kp->base + DUTY_CYCLE_HIGH_OFFSET(chan));
drivers/pwm/pwm-bcm-kona.c
179
writel(value, kp->base + PWM_CONTROL_OFFSET);
drivers/pwm/pwm-bcm-kona.c
211
writel(0, kp->base + DUTY_CYCLE_HIGH_OFFSET(chan));
drivers/pwm/pwm-bcm-kona.c
212
writel(0, kp->base + PERIOD_COUNT_OFFSET(chan));
drivers/pwm/pwm-bcm-kona.c
217
writel(value, kp->base + PRESCALE_OFFSET);
drivers/pwm/pwm-bcm-kona.c
309
writel(value, kp->base + PWM_CONTROL_OFFSET);
drivers/pwm/pwm-bcm-kona.c
78
writel(value, kp->base + PWM_CONTROL_OFFSET);
drivers/pwm/pwm-bcm-kona.c
94
writel(value, kp->base + PWM_CONTROL_OFFSET);
drivers/pwm/pwm-bcm2835.c
73
writel(period_cycles, pc->base + PERIOD(pwm->hwpwm));
drivers/pwm/pwm-bcm2835.c
77
writel(val, pc->base + DUTY(pwm->hwpwm));
drivers/pwm/pwm-bcm2835.c
96
writel(val, pc->base + PWM_CONTROL);
drivers/pwm/pwm-clps711x.c
60
writel(pmpcon, priv->pmpcon);
drivers/pwm/pwm-dwc.h
71
writel(value, dwc->base + offset);
drivers/pwm/pwm-hibvt.c
79
writel(value, address);
drivers/pwm/pwm-img.c
81
writel(val, imgchip->base + reg);
drivers/pwm/pwm-imx-tpm.c
205
writel(val, tpm->base + PWM_IMX_TPM_SC);
drivers/pwm/pwm-imx-tpm.c
215
writel(0x0, tpm->base + PWM_IMX_TPM_CNT);
drivers/pwm/pwm-imx-tpm.c
224
writel(p->mod, tpm->base + PWM_IMX_TPM_MOD);
drivers/pwm/pwm-imx-tpm.c
244
writel(p->val, tpm->base + PWM_IMX_TPM_CnV(pwm->hwpwm));
drivers/pwm/pwm-imx-tpm.c
283
writel(val, tpm->base + PWM_IMX_TPM_CnSC(pwm->hwpwm));
drivers/pwm/pwm-imx-tpm.c
295
writel(val, tpm->base + PWM_IMX_TPM_SC);
drivers/pwm/pwm-imx1.c
107
writel(value, imx->mmio_base + MX1_PWMC);
drivers/pwm/pwm-imx1.c
119
writel(value, imx->mmio_base + MX1_PWMC);
drivers/pwm/pwm-imx1.c
90
writel(max - p, imx->mmio_base + MX1_PWMS);
drivers/pwm/pwm-imx27.c
167
writel(MX3_PWMCR_SWR, imx->mmio_base + MX3_PWMCR);
drivers/pwm/pwm-imx27.c
341
writel(period_cycles, imx->mmio_base + MX3_PWMPR);
drivers/pwm/pwm-imx27.c
361
writel(cr, imx->mmio_base + MX3_PWMCR);
drivers/pwm/pwm-keembay.c
171
writel(pwm_count, priv->base + KMB_PWM_HIGHLOW_OFFSET(pwm->hwpwm));
drivers/pwm/pwm-keembay.c
76
writel(buff, priv->base + offset);
drivers/pwm/pwm-loongson.c
73
writel(val, ddata->base + offset);
drivers/pwm/pwm-lpc18xx-sct.c
115
writel(val, lpc18xx_pwm->base + reg);
drivers/pwm/pwm-lpc32xx.c
146
writel(val, lpc32xx->base);
drivers/pwm/pwm-lpc32xx.c
58
writel(val, lpc32xx->base);
drivers/pwm/pwm-lpc32xx.c
75
writel(val, lpc32xx->base);
drivers/pwm/pwm-lpc32xx.c
87
writel(val, lpc32xx->base);
drivers/pwm/pwm-lpss.c
86
writel(value, lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM);
drivers/pwm/pwm-mediatek.c
127
writel(value, chip->regs + chip->soc->chanreg_base +
drivers/pwm/pwm-mediatek.c
360
writel(ctrl, pc->regs);
drivers/pwm/pwm-mediatek.c
365
writel(0, pc->regs + pc->soc->pwm_ck_26m_sel_reg);
drivers/pwm/pwm-mediatek.c
373
writel(ctrl, pc->regs);
drivers/pwm/pwm-meson.c
243
writel(value, meson->base + channel_data->reg_offset);
drivers/pwm/pwm-meson.c
260
writel(value, meson->base + REG_MISC_AB);
drivers/pwm/pwm-meson.c
286
writel(value, meson->base + REG_MISC_AB);
drivers/pwm/pwm-mtk-disp.c
66
writel(value, address);
drivers/pwm/pwm-mxs.c
101
writel(PERIOD_PERIOD(period_cycles) | pol_bits | PERIOD_CDIV(div),
drivers/pwm/pwm-mxs.c
110
writel(1 << pwm->hwpwm, mxs->base + PWM_CTRL + SET);
drivers/pwm/pwm-mxs.c
71
writel(1 << pwm->hwpwm, mxs->base + PWM_CTRL + CLR);
drivers/pwm/pwm-mxs.c
99
writel(duty_cycles << 16,
drivers/pwm/pwm-pxa.c
96
writel(prescale | PWMCR_SD, pc->mmio_base + offset + PWMCR);
drivers/pwm/pwm-pxa.c
97
writel(dc, pc->mmio_base + offset + PWMDCR);
drivers/pwm/pwm-pxa.c
98
writel(pv, pc->mmio_base + offset + PWMPCR);
drivers/pwm/pwm-rcar.c
54
writel(data, rp->base + offset);
drivers/pwm/pwm-rockchip.c
141
writel(period_ticks, pc->base + pc->data->regs.period);
drivers/pwm/pwm-rockchip.c
142
writel(duty_ticks, pc->base + pc->data->regs.duty);
drivers/pwm/pwm-rockchip.c
160
writel(ctrl, pc->base + pc->data->regs.ctrl);
drivers/pwm/pwm-rzg2l-gpt.c
106
writel(data, rzg2l_gpt->mmio + reg);
drivers/pwm/pwm-samsung.c
128
writel(tcon, our_chip->base + REG_TCON);
drivers/pwm/pwm-samsung.c
131
writel(tcon, our_chip->base + REG_TCON);
drivers/pwm/pwm-samsung.c
149
writel(reg, our_chip->base + REG_TCFG1);
drivers/pwm/pwm-samsung.c
258
writel(tcon, our_chip->base + REG_TCON);
drivers/pwm/pwm-samsung.c
262
writel(tcon, our_chip->base + REG_TCON);
drivers/pwm/pwm-samsung.c
282
writel(tcon, our_chip->base + REG_TCON);
drivers/pwm/pwm-samsung.c
360
writel(tcnt, our_chip->base + REG_TCNTB(pwm->hwpwm));
drivers/pwm/pwm-samsung.c
361
writel(tcmp, our_chip->base + REG_TCMPB(pwm->hwpwm));
drivers/pwm/pwm-samsung.c
405
writel(tcon, our_chip->base + REG_TCON);
drivers/pwm/pwm-sifive.c
117
writel(val, ddata->regs + PWM_SIFIVE_PWMCFG);
drivers/pwm/pwm-sifive.c
219
writel(inactive, ddata->regs + PWM_SIFIVE_PWMCMP(pwm->hwpwm));
drivers/pwm/pwm-sophgo-sg2042.c
155
writel(pwmstart, ddata->base + SG2044_PWM_PWMSTART);
drivers/pwm/pwm-sophgo-sg2042.c
170
writel(pwm_oe, ddata->base + SG2044_PWM_OE);
drivers/pwm/pwm-sophgo-sg2042.c
185
writel(pwm_polarity, ddata->base + SG2044_PWM_POLARITY);
drivers/pwm/pwm-sophgo-sg2042.c
74
writel(period_ticks, base + SG2042_PWM_PERIOD(chan));
drivers/pwm/pwm-sophgo-sg2042.c
75
writel(hlperiod_ticks, base + SG2042_PWM_HLPERIOD(chan));
drivers/pwm/pwm-sun4i.c
104
writel(val, sun4ichip->base + offset);
drivers/pwm/pwm-sunplus.c
100
writel(dd_freq, priv->base + SP7021_PWM_FREQ(pwm->hwpwm));
drivers/pwm/pwm-sunplus.c
120
writel(duty, priv->base + SP7021_PWM_DUTY(pwm->hwpwm));
drivers/pwm/pwm-sunplus.c
121
writel(mode1, priv->base + SP7021_PWM_MODE1);
drivers/pwm/pwm-sunplus.c
122
writel(mode0, priv->base + SP7021_PWM_MODE0);
drivers/pwm/pwm-sunplus.c
69
writel(mode0, priv->base + SP7021_PWM_MODE0);
drivers/pwm/pwm-sunplus.c
73
writel(mode1, priv->base + SP7021_PWM_MODE1);
drivers/pwm/pwm-tegra.c
91
writel(value, pc->regs + (offset << 4));
drivers/pwm/pwm-tiecap.c
290
writel(pc->ctx.cap3, pc->mmio_base + CAP3);
drivers/pwm/pwm-tiecap.c
291
writel(pc->ctx.cap4, pc->mmio_base + CAP4);
drivers/pwm/pwm-tiecap.c
87
writel(duty_cycles, pc->mmio_base + CAP2);
drivers/pwm/pwm-tiecap.c
88
writel(period_cycles, pc->mmio_base + CAP1);
drivers/pwm/pwm-tiecap.c
95
writel(duty_cycles, pc->mmio_base + CAP4);
drivers/pwm/pwm-tiecap.c
96
writel(period_cycles, pc->mmio_base + CAP3);
drivers/pwm/pwm-visconti.c
100
writel(period, priv->base + PIPGM_PCSR(pwm->hwpwm));
drivers/pwm/pwm-visconti.c
52
writel(0, priv->base + PIPGM_PCSR(pwm->hwpwm));
drivers/pwm/pwm-visconti.c
98
writel(pwmc0, priv->base + PIPGM_PWMC(pwm->hwpwm));
drivers/pwm/pwm-visconti.c
99
writel(duty_cycle, priv->base + PIPGM_PDUT(pwm->hwpwm));
drivers/pwm/pwm-vt8500.c
108
writel(prescale, vt8500->base + REG_SCALAR(pwm->hwpwm));
drivers/pwm/pwm-vt8500.c
111
writel(pv, vt8500->base + REG_PERIOD(pwm->hwpwm));
drivers/pwm/pwm-vt8500.c
114
writel(dc, vt8500->base + REG_DUTY(pwm->hwpwm));
drivers/pwm/pwm-vt8500.c
119
writel(val, vt8500->base + REG_CTRL(pwm->hwpwm));
drivers/pwm/pwm-vt8500.c
140
writel(val, vt8500->base + REG_CTRL(pwm->hwpwm));
drivers/pwm/pwm-vt8500.c
153
writel(val, vt8500->base + REG_CTRL(pwm->hwpwm));
drivers/pwm/pwm-vt8500.c
173
writel(val, vt8500->base + REG_CTRL(pwm->hwpwm));
drivers/regulator/ti-abb-regulator.c
127
writel(val, reg);
drivers/regulator/ti-abb-regulator.c
149
writel(abb->txdone_mask, abb->int_base);
drivers/regulator/ti-abb-regulator.c
227
writel(val, abb->ldo_base);
drivers/remoteproc/da8xx_remoteproc.c
114
writel(SYSCFG_CHIPSIG0, drproc->chipsig + 4);
drivers/remoteproc/da8xx_remoteproc.c
148
writel(rproc->bootaddr, drproc->bootreg);
drivers/remoteproc/da8xx_remoteproc.c
189
writel(SYSCFG_CHIPSIG2, drproc->chipsig);
drivers/remoteproc/imx_dsp_rproc.c
224
writel(pwrctl, dap + IMX8M_DAP_PWRCTL);
drivers/remoteproc/imx_dsp_rproc.c
234
writel(pwrctl, dap + IMX8M_DAP_PWRCTL);
drivers/remoteproc/imx_dsp_rproc.c
820
writel(source[i], dest + i * 4);
drivers/remoteproc/imx_dsp_rproc.c
837
writel(tmp, dest + q * 4);
drivers/remoteproc/imx_dsp_rproc.c
868
writel(tmp_val, tmp_dst++);
drivers/remoteproc/imx_dsp_rproc.c
882
writel(tmp, tmp_dst);
drivers/remoteproc/ingenic_rproc.c
100
writel(ctrl, vpu->aux_base + REG_AUX_CTRL);
drivers/remoteproc/ingenic_rproc.c
112
writel(AUX_CTRL_SW_RESET, vpu->aux_base + REG_AUX_CTRL);
drivers/remoteproc/ingenic_rproc.c
121
writel(vqid, vpu->aux_base + REG_CORE_MSG);
drivers/remoteproc/ingenic_rproc.c
161
writel(0, vpu->aux_base + REG_AUX_MSG_ACK);
drivers/remoteproc/meson_mx_ao_arc.c
105
writel(tmp, priv->cpu_base + AO_CPU_CNTL);
drivers/remoteproc/meson_mx_ao_arc.c
116
writel(AO_CPU_CNTL_HALT, priv->cpu_base + AO_CPU_CNTL);
drivers/remoteproc/meson_mx_ao_arc.c
71
writel(tmp, priv->remap_base + AO_REMAP_REG0);
drivers/remoteproc/meson_mx_ao_arc.c
80
writel(0x0, priv->remap_base + AO_REMAP_REG1);
drivers/remoteproc/mtk_scp.c
178
writel(val, scp->cluster->reg_base + MT8183_SW_RSTN);
drivers/remoteproc/mtk_scp.c
187
writel(val, scp->cluster->reg_base + MT8183_SW_RSTN);
drivers/remoteproc/mtk_scp.c
192
writel(1, scp->cluster->reg_base + MT8192_CORE0_SW_RSTN_SET);
drivers/remoteproc/mtk_scp.c
197
writel(1, scp->cluster->reg_base + MT8192_CORE0_SW_RSTN_CLR);
drivers/remoteproc/mtk_scp.c
202
writel(1, scp->cluster->reg_base + MT8195_CORE1_SW_RSTN_SET);
drivers/remoteproc/mtk_scp.c
207
writel(1, scp->cluster->reg_base + MT8195_CORE1_SW_RSTN_CLR);
drivers/remoteproc/mtk_scp.c
221
writel(MT8183_SCP_IPC_INT_BIT | MT8183_SCP_WDT_INT_BIT,
drivers/remoteproc/mtk_scp.c
238
writel(MT8192_SCP_IPC_INT_BIT,
drivers/remoteproc/mtk_scp.c
242
writel(1, scp->cluster->reg_base + MT8192_CORE0_WDT_IRQ);
drivers/remoteproc/mtk_scp.c
258
writel(1, scp->cluster->reg_base + MT8192_CORE0_WDT_IRQ);
drivers/remoteproc/mtk_scp.c
261
writel(1, scp->cluster->reg_base + MT8195_CORE1_WDT_IRQ);
drivers/remoteproc/mtk_scp.c
266
writel(scp_to_host, scp->cluster->reg_base + MT8192_SCP2APMCU_IPC_CLR);
drivers/remoteproc/mtk_scp.c
278
writel(scp_to_host, scp->cluster->reg_base + MT8195_SSHUB2APMCU_IPC_CLR);
drivers/remoteproc/mtk_scp.c
410
writel(MT8183_SCP_IPC_INT_BIT, scp->cluster->reg_base + MT8183_SCP_TO_HOST);
drivers/remoteproc/mtk_scp.c
413
writel(0x0, scp->cluster->reg_base + MT8183_SCP_CLK_SW_SEL);
drivers/remoteproc/mtk_scp.c
414
writel(0x0, scp->cluster->reg_base + MT8183_SCP_CLK_DIV_SEL);
drivers/remoteproc/mtk_scp.c
417
writel(0x0, scp->cluster->reg_base + MT8183_SCP_L1_SRAM_PD);
drivers/remoteproc/mtk_scp.c
418
writel(0x0, scp->cluster->reg_base + MT8183_SCP_TCM_TAIL_SRAM_PD);
drivers/remoteproc/mtk_scp.c
421
writel(0x0, scp->cluster->reg_base + MT8183_SCP_SRAM_PDN);
drivers/remoteproc/mtk_scp.c
427
writel(MT8183_SCP_CACHE_CON_WAYEN | MT8183_SCP_CACHESIZE_8KB,
drivers/remoteproc/mtk_scp.c
429
writel(MT8183_SCP_CACHESIZE_8KB, scp->cluster->reg_base + MT8183_SCP_DCACHE_CON);
drivers/remoteproc/mtk_scp.c
439
writel(GENMASK(i, 0) & ~reserved_mask, addr);
drivers/remoteproc/mtk_scp.c
440
writel(0, addr);
drivers/remoteproc/mtk_scp.c
447
writel(0, addr);
drivers/remoteproc/mtk_scp.c
449
writel(GENMASK(i, 0) & ~reserved_mask, addr);
drivers/remoteproc/mtk_scp.c
455
writel(MT8183_SCP_IPC_INT_BIT, scp->cluster->reg_base + MT8183_SCP_TO_HOST);
drivers/remoteproc/mtk_scp.c
458
writel(0x0, scp->cluster->reg_base + MT8183_SCP_CLK_SW_SEL);
drivers/remoteproc/mtk_scp.c
459
writel(0x0, scp->cluster->reg_base + MT8183_SCP_CLK_DIV_SEL);
drivers/remoteproc/mtk_scp.c
465
writel(0x0, scp->cluster->reg_base + MT8183_SCP_L1_SRAM_PD);
drivers/remoteproc/mtk_scp.c
466
writel(0x0, scp->cluster->reg_base + MT8183_SCP_TCM_TAIL_SRAM_PD);
drivers/remoteproc/mtk_scp.c
467
writel(0x0, scp->cluster->reg_base + MT8186_SCP_L1_SRAM_PD_P1);
drivers/remoteproc/mtk_scp.c
468
writel(0x0, scp->cluster->reg_base + MT8186_SCP_L1_SRAM_PD_p2);
drivers/remoteproc/mtk_scp.c
474
writel(MT8183_SCP_CACHE_CON_WAYEN | MT8183_SCP_CACHESIZE_8KB,
drivers/remoteproc/mtk_scp.c
476
writel(MT8183_SCP_CACHESIZE_8KB, scp->cluster->reg_base + MT8183_SCP_DCACHE_CON);
drivers/remoteproc/mtk_scp.c
489
writel(0xff, scp->cluster->reg_base + MT8192_SCP2SPM_IPC_CLR);
drivers/remoteproc/mtk_scp.c
507
writel(1, scp->cluster->reg_base + MT8192_CORE0_SW_RSTN_SET);
drivers/remoteproc/mtk_scp.c
514
writel(0xff, scp->cluster->reg_base + MT8192_CORE0_MEM_ATT_PREDEF);
drivers/remoteproc/mtk_scp.c
532
writel(0xff, scp->cluster->reg_base + MT8195_CORE1_MEM_ATT_PREDEF);
drivers/remoteproc/mtk_scp.c
547
writel(0, scp->cluster->reg_base + MT8195_L2TCM_OFFSET_RANGE_0_LOW);
drivers/remoteproc/mtk_scp.c
548
writel(scp->sram_size, scp->cluster->reg_base + MT8195_L2TCM_OFFSET_RANGE_0_HIGH);
drivers/remoteproc/mtk_scp.c
551
writel(scp->sram_phys - scp_c0->sram_phys, scp->cluster->reg_base + MT8195_L2TCM_OFFSET);
drivers/remoteproc/mtk_scp.c
556
writel(sec_ctrl, scp->cluster->reg_base + MT8195_SEC_CTRL);
drivers/remoteproc/mtk_scp.c
564
writel(0xff, scp->cluster->reg_base + MT8192_SCP2SPM_IPC_CLR);
drivers/remoteproc/mtk_scp.c
566
writel(1, scp->cluster->reg_base + MT8192_CORE0_SW_RSTN_SET);
drivers/remoteproc/mtk_scp.c
576
writel(0xff, scp->cluster->reg_base + MT8192_CORE0_MEM_ATT_PREDEF);
drivers/remoteproc/mtk_scp.c
589
writel(0xff, scp->cluster->reg_base + MT8192_SCP2SPM_IPC_CLR);
drivers/remoteproc/mtk_scp.c
608
writel(1, scp->cluster->reg_base + MT8192_CORE0_SW_RSTN_SET);
drivers/remoteproc/mtk_scp.c
615
writel(0xff, scp->cluster->reg_base + MT8192_CORE0_MEM_ATT_PREDEF);
drivers/remoteproc/mtk_scp.c
633
writel(0xff, scp->cluster->reg_base + MT8195_CORE1_MEM_ATT_PREDEF);
drivers/remoteproc/mtk_scp.c
648
writel(0, scp->cluster->reg_base + MT8195_L2TCM_OFFSET_RANGE_0_LOW);
drivers/remoteproc/mtk_scp.c
649
writel(scp->sram_size, scp->cluster->reg_base + MT8195_L2TCM_OFFSET_RANGE_0_HIGH);
drivers/remoteproc/mtk_scp.c
652
writel(scp->sram_phys - scp_c0->sram_phys, scp->cluster->reg_base + MT8195_L2TCM_OFFSET);
drivers/remoteproc/mtk_scp.c
657
writel(sec_ctrl, scp->cluster->reg_base + MT8195_SEC_CTRL);
drivers/remoteproc/mtk_scp.c
808
writel(0, scp->cluster->reg_base + MT8183_WDT_CFG);
drivers/remoteproc/mtk_scp.c
838
writel(0, scp->cluster->reg_base + MT8192_CORE0_WDT_CFG);
drivers/remoteproc/mtk_scp.c
849
writel(0, scp->cluster->reg_base + MT8195_CORE1_WDT_CFG);
drivers/remoteproc/mtk_scp.c
862
writel(0, scp->cluster->reg_base + MT8192_CORE0_WDT_CFG);
drivers/remoteproc/mtk_scp.c
893
writel(0, scp->cluster->reg_base + MT8192_CORE0_WDT_CFG);
drivers/remoteproc/mtk_scp.c
904
writel(0, scp->cluster->reg_base + MT8195_CORE1_WDT_CFG);
drivers/remoteproc/mtk_scp_ipi.c
192
writel(len, &send_obj->len);
drivers/remoteproc/mtk_scp_ipi.c
193
writel(id, &send_obj->id);
drivers/remoteproc/mtk_scp_ipi.c
197
writel(scp->data->host_to_scp_int_bit,
drivers/remoteproc/qcom_pil_info.c
110
writel(base, entry + PIL_RELOC_NAME_LEN);
drivers/remoteproc/qcom_pil_info.c
111
writel((u64)base >> 32, entry + PIL_RELOC_NAME_LEN + 4);
drivers/remoteproc/qcom_pil_info.c
112
writel(size, entry + PIL_RELOC_NAME_LEN + sizeof(__le64));
drivers/remoteproc/qcom_q6v5_adsp.c
259
writel(val, adsp->qdsp6ss_base + RET_CFG_REG);
drivers/remoteproc/qcom_q6v5_adsp.c
404
writel(1, adsp->qdsp6ss_base + QDSP6SS_XO_CBCR);
drivers/remoteproc/qcom_q6v5_adsp.c
407
writel(1, adsp->qdsp6ss_base + QDSP6SS_SLEEP_CBCR);
drivers/remoteproc/qcom_q6v5_adsp.c
410
writel(1, adsp->qdsp6ss_base + QDSP6SS_CORE_CBCR);
drivers/remoteproc/qcom_q6v5_adsp.c
413
writel(adsp->mem_phys >> 4, adsp->qdsp6ss_base + RST_EVB_REG);
drivers/remoteproc/qcom_q6v5_adsp.c
416
writel(LPASS_EFUSE_Q6SS_EVB_SEL, adsp->lpass_efuse);
drivers/remoteproc/qcom_q6v5_adsp.c
419
writel(LPASS_BOOT_CORE_START, adsp->qdsp6ss_base + CORE_START_REG);
drivers/remoteproc/qcom_q6v5_adsp.c
422
writel(LPASS_BOOT_CMD_START, adsp->qdsp6ss_base + BOOT_CMD_REG);
drivers/remoteproc/qcom_q6v5_mss.c
1079
writel(phys, qproc->rmb_base + RMB_PMI_META_DATA_REG);
drivers/remoteproc/qcom_q6v5_mss.c
1080
writel(RMB_CMD_META_DATA_READY, qproc->rmb_base + RMB_MBA_COMMAND_REG);
drivers/remoteproc/qcom_q6v5_mss.c
1217
writel(qproc->mba_phys, qproc->rmb_base + RMB_MBA_IMAGE_REG);
drivers/remoteproc/qcom_q6v5_mss.c
1219
writel(qproc->mba_phys + SZ_1M, qproc->rmb_base + RMB_PMI_CODE_START_REG);
drivers/remoteproc/qcom_q6v5_mss.c
1220
writel(qproc->dp_size, qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG);
drivers/remoteproc/qcom_q6v5_mss.c
1313
writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
drivers/remoteproc/qcom_q6v5_mss.c
1419
writel(0, qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG);
drivers/remoteproc/qcom_q6v5_mss.c
1548
writel(boot_addr, qproc->rmb_base + RMB_PMI_CODE_START_REG);
drivers/remoteproc/qcom_q6v5_mss.c
1549
writel(RMB_CMD_LOAD_READY, qproc->rmb_base + RMB_MBA_COMMAND_REG);
drivers/remoteproc/qcom_q6v5_mss.c
1551
writel(size, qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG);
drivers/remoteproc/qcom_q6v5_mss.c
580
writel(1, qproc->rmb_base + RMB_MBA_ALT_RESET);
drivers/remoteproc/qcom_q6v5_mss.c
582
writel(0, qproc->rmb_base + RMB_MBA_ALT_RESET);
drivers/remoteproc/qcom_q6v5_mss.c
673
writel(val, qproc->reg_base + QDSP6SS_SLEEP);
drivers/remoteproc/qcom_q6v5_mss.c
684
writel(1, qproc->reg_base + QDSP6SS_BOOT_CORE_START);
drivers/remoteproc/qcom_q6v5_mss.c
686
writel(1, qproc->reg_base + QDSP6SS_BOOT_CMD);
drivers/remoteproc/qcom_q6v5_mss.c
701
writel(val, qproc->reg_base + QDSP6SS_SLEEP);
drivers/remoteproc/qcom_q6v5_mss.c
714
writel(val, qproc->reg_base + QDSP6SS_XO_CBCR);
drivers/remoteproc/qcom_q6v5_mss.c
727
writel(val, qproc->reg_base + QDSP6SS_CORE_CBCR);
drivers/remoteproc/qcom_q6v5_mss.c
730
writel(1, qproc->reg_base + QDSP6SS_BOOT_CORE_START);
drivers/remoteproc/qcom_q6v5_mss.c
736
writel(1, qproc->reg_base + QDSP6SS_BOOT_CMD);
drivers/remoteproc/qcom_q6v5_mss.c
757
writel(QDSP6SS_ACC_OVERRIDE_VAL,
drivers/remoteproc/qcom_q6v5_mss.c
763
writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
drivers/remoteproc/qcom_q6v5_mss.c
768
writel(val, qproc->reg_base + QDSP6SS_XO_CBCR);
drivers/remoteproc/qcom_q6v5_mss.c
782
writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
drivers/remoteproc/qcom_q6v5_mss.c
798
writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
drivers/remoteproc/qcom_q6v5_mss.c
806
writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
drivers/remoteproc/qcom_q6v5_mss.c
810
writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
drivers/remoteproc/qcom_q6v5_mss.c
825
writel(val, qproc->reg_base + mem_pwr_ctl);
drivers/remoteproc/qcom_q6v5_mss.c
839
writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
drivers/remoteproc/qcom_q6v5_mss.c
844
writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
drivers/remoteproc/qcom_q6v5_mss.c
851
writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
drivers/remoteproc/qcom_q6v5_mss.c
856
writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
drivers/remoteproc/qcom_q6v5_mss.c
861
writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
drivers/remoteproc/qcom_q6v5_mss.c
871
writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
drivers/remoteproc/qcom_q6v5_mss.c
873
writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
drivers/remoteproc/qcom_q6v5_mss.c
875
writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
drivers/remoteproc/qcom_q6v5_mss.c
877
writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
drivers/remoteproc/qcom_q6v5_mss.c
881
writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
drivers/remoteproc/qcom_q6v5_mss.c
886
writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
drivers/remoteproc/qcom_q6v5_mss.c
891
writel(val, qproc->reg_base + QDSP6SS_GFMUX_CTL_REG);
drivers/remoteproc/qcom_q6v5_mss.c
896
writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
drivers/remoteproc/qcom_q6v5_wcss.c
164
writel(val, wcss->reg_base + Q6SS_RESET_REG);
drivers/remoteproc/qcom_q6v5_wcss.c
169
writel(val, wcss->reg_base + Q6SS_XO_CBCR);
drivers/remoteproc/qcom_q6v5_wcss.c
183
writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
drivers/remoteproc/qcom_q6v5_wcss.c
188
writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
drivers/remoteproc/qcom_q6v5_wcss.c
193
writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
drivers/remoteproc/qcom_q6v5_wcss.c
197
writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
drivers/remoteproc/qcom_q6v5_wcss.c
203
writel(val, wcss->reg_base + Q6SS_MEM_PWR_CTL);
drivers/remoteproc/qcom_q6v5_wcss.c
215
writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
drivers/remoteproc/qcom_q6v5_wcss.c
219
writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
drivers/remoteproc/qcom_q6v5_wcss.c
224
writel(val, wcss->reg_base + Q6SS_RESET_REG);
drivers/remoteproc/qcom_q6v5_wcss.c
229
writel(val, wcss->reg_base + Q6SS_GFMUX_CTL_REG);
drivers/remoteproc/qcom_q6v5_wcss.c
234
writel(val, wcss->reg_base + Q6SS_RESET_REG);
drivers/remoteproc/qcom_q6v5_wcss.c
274
writel(rproc->bootaddr >> 4, wcss->reg_base + Q6SS_RST_EVB);
drivers/remoteproc/qcom_q6v5_wcss.c
347
writel(val, wcss->reg_base + Q6SS_XO_CBCR);
drivers/remoteproc/qcom_q6v5_wcss.c
358
writel(0, wcss->reg_base + Q6SS_CGC_OVERRIDE);
drivers/remoteproc/qcom_q6v5_wcss.c
363
writel(val, wcss->reg_base + Q6SS_SLEEP_CBCR);
drivers/remoteproc/qcom_q6v5_wcss.c
373
writel(val, wcss->reg_base + Q6SS_RESET_REG);
drivers/remoteproc/qcom_q6v5_wcss.c
376
writel(0x01700000, wcss->reg_base + Q6SS_PWR_CTL_REG);
drivers/remoteproc/qcom_q6v5_wcss.c
378
writel(0x03700000, wcss->reg_base + Q6SS_PWR_CTL_REG);
drivers/remoteproc/qcom_q6v5_wcss.c
380
writel(0x03300000, wcss->reg_base + Q6SS_PWR_CTL_REG);
drivers/remoteproc/qcom_q6v5_wcss.c
382
writel(0x033C0000, wcss->reg_base + Q6SS_PWR_CTL_REG);
drivers/remoteproc/qcom_q6v5_wcss.c
389
writel((readl(wcss->reg_base + Q6SS_MEM_PWR_CTL) |
drivers/remoteproc/qcom_q6v5_wcss.c
393
writel(0x031C0000, wcss->reg_base + Q6SS_PWR_CTL_REG);
drivers/remoteproc/qcom_q6v5_wcss.c
394
writel(0x030C0000, wcss->reg_base + Q6SS_PWR_CTL_REG);
drivers/remoteproc/qcom_q6v5_wcss.c
398
writel(val, wcss->reg_base + Q6SS_RESET_REG);
drivers/remoteproc/qcom_q6v5_wcss.c
403
writel(val, wcss->reg_base + Q6SS_GFMUX_CTL_REG);
drivers/remoteproc/qcom_q6v5_wcss.c
415
writel(val, wcss->reg_base + Q6SS_GFMUX_CTL_REG);
drivers/remoteproc/qcom_q6v5_wcss.c
420
writel(val, wcss->reg_base + Q6SS_SLEEP_CBCR);
drivers/remoteproc/qcom_q6v5_wcss.c
424
writel(val, wcss->reg_base + Q6SS_XO_CBCR);
drivers/remoteproc/qcom_q6v5_wcss.c
446
writel(0x80800000, wcss->reg_base + Q6SS_STRAP_ACC);
drivers/remoteproc/qcom_q6v5_wcss.c
451
writel(val, wcss->reg_base + Q6SS_RESET_REG);
drivers/remoteproc/qcom_q6v5_wcss.c
477
writel(rproc->bootaddr >> 4, wcss->reg_base + Q6SS_RST_EVB);
drivers/remoteproc/qcom_q6v5_wcss.c
541
writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
drivers/remoteproc/qcom_q6v5_wcss.c
544
writel((readl(wcss->reg_base + Q6SS_MEM_PWR_CTL) &
drivers/remoteproc/qcom_q6v5_wcss.c
551
writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
drivers/remoteproc/qcom_q6v5_wcss.c
561
writel(val, wcss->reg_base + Q6SS_SLEEP_CBCR);
drivers/remoteproc/qcom_q6v5_wcss.c
565
writel(val, wcss->reg_base + Q6SS_XO_CBCR);
drivers/remoteproc/qcom_q6v5_wcss.c
572
writel(val, wcss->reg_base + Q6SS_GFMUX_CTL_REG);
drivers/remoteproc/qcom_q6v5_wcss.c
606
writel(val, wcss->rmb_base + SSCAON_CONFIG);
drivers/remoteproc/qcom_q6v5_wcss.c
611
writel(val, wcss->rmb_base + SSCAON_CONFIG);
drivers/remoteproc/qcom_q6v5_wcss.c
615
writel(val, wcss->rmb_base + SSCAON_CONFIG);
drivers/remoteproc/qcom_q6v5_wcss.c
633
writel(val, wcss->rmb_base + SSCAON_CONFIG);
drivers/remoteproc/qcom_q6v5_wcss.c
653
writel(val, wcss->reg_base + Q6SS_GFMUX_CTL_REG);
drivers/remoteproc/qcom_q6v5_wcss.c
658
writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
drivers/remoteproc/qcom_q6v5_wcss.c
662
writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
drivers/remoteproc/qcom_q6v5_wcss.c
666
writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
drivers/remoteproc/qcom_q6v5_wcss.c
670
writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
drivers/remoteproc/qcom_q6v5_wcss.c
676
writel(val, wcss->reg_base + Q6SS_MEM_PWR_CTL);
drivers/remoteproc/qcom_q6v5_wcss.c
683
writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
drivers/remoteproc/qcom_q6v5_wcss.c
687
writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
drivers/remoteproc/qcom_wcnss.c
178
writel(val, wcnss->spare_out);
drivers/remoteproc/qcom_wcnss.c
186
writel(0, wcnss->pmu_cfg);
drivers/remoteproc/qcom_wcnss.c
189
writel(val, wcnss->pmu_cfg);
drivers/remoteproc/qcom_wcnss.c
197
writel(val, wcnss->pmu_cfg);
drivers/remoteproc/qcom_wcnss.c
201
writel(val, wcnss->pmu_cfg);
drivers/remoteproc/qcom_wcnss.c
209
writel(val, wcnss->pmu_cfg);
drivers/remoteproc/qcom_wcnss.c
213
writel(val, wcnss->pmu_cfg);
drivers/remoteproc/qcom_wcnss.c
222
writel(val, wcnss->pmu_cfg);
drivers/remoteproc/st_slim_rproc.c
120
writel(val, slim_rproc->slimcore + SLIM_CLK_GATE_OFST);
drivers/remoteproc/st_slim_rproc.c
123
writel(SLIM_STBUS_SYNC_DIS, slim_rproc->peri + SLIM_STBUS_SYNC_OFST);
drivers/remoteproc/st_slim_rproc.c
126
writel(!SLIM_CLK_GATE_DIS,
drivers/remoteproc/st_slim_rproc.c
130
writel(~0U, slim_rproc->peri + SLIM_INT_CLR_OFST);
drivers/remoteproc/st_slim_rproc.c
131
writel(~0U, slim_rproc->peri + SLIM_CMD_CLR_OFST);
drivers/remoteproc/st_slim_rproc.c
134
writel(~0U, slim_rproc->peri + SLIM_INT_MASK_OFST);
drivers/remoteproc/st_slim_rproc.c
135
writel(~0U, slim_rproc->peri + SLIM_CMD_MASK_OFST);
drivers/remoteproc/st_slim_rproc.c
138
writel(SLIM_EN_RUN, slim_rproc->slimcore + SLIM_EN_OFST);
drivers/remoteproc/st_slim_rproc.c
159
writel(0UL, slim_rproc->peri + SLIM_INT_MASK_OFST);
drivers/remoteproc/st_slim_rproc.c
160
writel(0UL, slim_rproc->peri + SLIM_CMD_MASK_OFST);
drivers/remoteproc/st_slim_rproc.c
163
writel(SLIM_CLK_GATE_DIS, slim_rproc->slimcore + SLIM_CLK_GATE_OFST);
drivers/remoteproc/st_slim_rproc.c
165
writel(!SLIM_EN_RUN, slim_rproc->slimcore + SLIM_EN_OFST);
drivers/reset/amlogic/reset-meson-audio-arb.c
129
writel(0, arb->regs);
drivers/reset/amlogic/reset-meson-audio-arb.c
169
writel(BIT(ARB_GENERAL_BIT), arb->regs);
drivers/reset/amlogic/reset-meson-audio-arb.c
75
writel(val, arb->regs);
drivers/reset/reset-aspeed.c
165
writel(rc->info->signal[id].bit, reg_offset);
drivers/reset/reset-aspeed.c
168
writel(readl(reg_offset) & ~rc->info->signal[id].bit, reg_offset);
drivers/reset/reset-aspeed.c
180
writel(rc->info->signal[id].bit, reg_offset + 0x04);
drivers/reset/reset-aspeed.c
183
writel(readl(reg_offset) | rc->info->signal[id].bit, reg_offset);
drivers/reset/reset-ath79.c
39
writel(val, ath79_reset->base);
drivers/reset/reset-axs10x.c
34
writel(BIT(id), rst->regs_rst);
drivers/reset/reset-brcmstb-rescal.c
33
writel(reg | BRCM_RESCAL_START_BIT, base + BRCM_RESCAL_START);
drivers/reset/reset-brcmstb-rescal.c
48
writel(reg & ~BRCM_RESCAL_START_BIT, base + BRCM_RESCAL_START);
drivers/reset/reset-eyeq.c
256
writel(readl(reg) & ~BIT(offset), reg);
drivers/reset/reset-eyeq.c
261
writel(readl(reg) | EQR_EYEQ5_ACRP_PD_REQ, reg);
drivers/reset/reset-eyeq.c
265
writel(readl(base) & ~BIT(offset), base);
drivers/reset/reset-eyeq.c
272
writel(val, base + EQR_EYEQ6H_SARCR_RST_REQUEST);
drivers/reset/reset-eyeq.c
273
writel(val, base + EQR_EYEQ6H_SARCR_CLK_REQUEST);
drivers/reset/reset-eyeq.c
310
writel(readl(reg) | BIT(offset), reg);
drivers/reset/reset-eyeq.c
315
writel(readl(reg) & ~EQR_EYEQ5_ACRP_PD_REQ, reg);
drivers/reset/reset-eyeq.c
319
writel(readl(base) | BIT(offset), base);
drivers/reset/reset-eyeq.c
326
writel(val, base + EQR_EYEQ6H_SARCR_RST_REQUEST);
drivers/reset/reset-eyeq.c
327
writel(val, base + EQR_EYEQ6H_SARCR_CLK_REQUEST);
drivers/reset/reset-hsdk.c
54
writel(rst_map[id], rst->regs_ctl + CGU_SYS_RST_CTRL);
drivers/reset/reset-hsdk.c
65
writel(reg, rst->regs_rst + CGU_IP_SW_RESET);
drivers/reset/reset-k230.c
171
writel(reg, rstc->base + rmap->offset);
drivers/reset/reset-k230.c
208
writel(reg, rstc->base + rmap->offset);
drivers/reset/reset-lpc18xx.c
50
writel(BIT(LPC18XX_RGU_CORE_RST), rc->base + LPC18XX_RGU_CTRL0);
drivers/reset/reset-lpc18xx.c
82
writel(stat | rst_bit, rc->base + ctrl_offset);
drivers/reset/reset-lpc18xx.c
84
writel(stat & ~rst_bit, rc->base + ctrl_offset);
drivers/reset/reset-npcm.c
109
writel(NPCM_SWRST << rc->sw_reset_number, rc->base + NPCM_SWRSTR);
drivers/reset/reset-npcm.c
129
writel(stat | rst_bit, rc->base + ctrl_offset);
drivers/reset/reset-npcm.c
131
writel(stat & ~rst_bit, rc->base + ctrl_offset);
drivers/reset/reset-npcm.c
229
writel(iprst1, rc->base + NPCM_IPSRST1);
drivers/reset/reset-npcm.c
230
writel(iprst2, rc->base + NPCM_IPSRST2);
drivers/reset/reset-npcm.c
231
writel(iprst3, rc->base + NPCM_IPSRST3);
drivers/reset/reset-npcm.c
241
writel(iprst3, rc->base + NPCM_IPSRST3);
drivers/reset/reset-npcm.c
256
writel(iprst1, rc->base + NPCM_IPSRST1);
drivers/reset/reset-npcm.c
257
writel(iprst2, rc->base + NPCM_IPSRST2);
drivers/reset/reset-npcm.c
258
writel(iprst3, rc->base + NPCM_IPSRST3);
drivers/reset/reset-npcm.c
301
writel(iprst1, rc->base + NPCM_IPSRST1);
drivers/reset/reset-npcm.c
302
writel(iprst2, rc->base + NPCM_IPSRST2);
drivers/reset/reset-npcm.c
303
writel(iprst3, rc->base + NPCM_IPSRST3);
drivers/reset/reset-npcm.c
304
writel(iprst4, rc->base + NPCM_IPSRST4);
drivers/reset/reset-npcm.c
316
writel(iprst3, rc->base + NPCM_IPSRST3);
drivers/reset/reset-npcm.c
318
writel(iprst4, rc->base + NPCM_IPSRST4);
drivers/reset/reset-npcm.c
334
writel(iprst1, rc->base + NPCM_IPSRST1);
drivers/reset/reset-npcm.c
335
writel(iprst2, rc->base + NPCM_IPSRST2);
drivers/reset/reset-npcm.c
336
writel(iprst3, rc->base + NPCM_IPSRST3);
drivers/reset/reset-npcm.c
337
writel(iprst4, rc->base + NPCM_IPSRST4);
drivers/reset/reset-qcom-aoss.c
56
writel(1, data->base + map->reg);
drivers/reset/reset-qcom-aoss.c
68
writel(0, data->base + map->reg);
drivers/reset/reset-rzg2l-usbphy-ctrl.c
105
writel(val, priv->base + RESET);
drivers/reset/reset-rzg2l-usbphy-ctrl.c
60
writel(val, base + RESET);
drivers/reset/reset-rzg2l-usbphy-ctrl.c
79
writel(val, base + RESET);
drivers/reset/reset-rzv2h-usb2phy.c
100
writel(data->reset_deassert_val, priv->base + data->reset_reg);
drivers/reset/reset-rzv2h-usb2phy.c
101
writel(data->reset2_release_val, priv->base + data->reset2_reg);
drivers/reset/reset-rzv2h-usb2phy.c
102
writel(data->reset_release_val, priv->base + data->reset_reg);
drivers/reset/reset-rzv2h-usb2phy.c
179
writel(data->init_vals[i].val, priv->base + data->init_vals[i].reg);
drivers/reset/reset-rzv2h-usb2phy.c
58
writel(data->reset2_acquire_val, priv->base + data->reset2_reg);
drivers/reset/reset-rzv2h-usb2phy.c
59
writel(data->reset_assert_val, priv->base + data->reset_reg);
drivers/reset/reset-simple.c
47
writel(reg, data->membase + (bank * reg_width));
drivers/reset/reset-sunplus.c
121
writel(val, reset->base + (index * 4));
drivers/reset/starfive/reset-starfive-jh71x0.c
55
writel(value, reg_assert);
drivers/rpmsg/qcom_glink_rpm.c
120
writel(tail, pipe->tail);
drivers/rpmsg/qcom_glink_rpm.c
192
writel(head, pipe->head);
drivers/rpmsg/qcom_glink_rpm.c
342
writel(0, rpm->tx_pipe.head);
drivers/rpmsg/qcom_glink_rpm.c
343
writel(0, rpm->rx_pipe.tail);
drivers/rtc/rtc-armada38x.c
105
writel(0, rtc->regs + RTC_STATUS);
drivers/rtc/rtc-armada38x.c
106
writel(0, rtc->regs + RTC_STATUS);
drivers/rtc/rtc-armada38x.c
107
writel(val, rtc->regs + offset);
drivers/rtc/rtc-armada38x.c
121
writel(reg, rtc->regs_soc + RTC_38X_BRIDGE_TIMING_CTL);
drivers/rtc/rtc-armada38x.c
133
writel(reg, rtc->regs_soc + RTC_8K_BRIDGE_TIMING_CTL0);
drivers/rtc/rtc-armada38x.c
138
writel(reg, rtc->regs_soc + RTC_8K_BRIDGE_TIMING_CTL1);
drivers/rtc/rtc-armada38x.c
192
writel(val & ~SOC_RTC_ALARM1, rtc->regs_soc + SOC_RTC_INTERRUPT);
drivers/rtc/rtc-armada38x.c
199
writel(val | SOC_RTC_ALARM1_MASK, rtc->regs_soc + SOC_RTC_INTERRUPT);
drivers/rtc/rtc-armada38x.c
204
writel(RTC_8K_ALARM2, rtc->regs_soc + RTC_8K_ISR);
drivers/rtc/rtc-armada38x.c
209
writel(RTC_8K_ALARM2, rtc->regs_soc + RTC_8K_IMR);
drivers/rtc/rtc-aspeed.c
68
writel(ctrl | RTC_UNLOCK, rtc->base + RTC_CTRL);
drivers/rtc/rtc-aspeed.c
70
writel(reg1, rtc->base + RTC_TIME);
drivers/rtc/rtc-aspeed.c
71
writel(reg2, rtc->base + RTC_YEAR);
drivers/rtc/rtc-aspeed.c
74
writel(ctrl | RTC_ENABLE, rtc->base + RTC_CTRL);
drivers/rtc/rtc-at91sam9.c
84
writel((val), (rtc)->rtt + AT91_RTT_ ## field)
drivers/rtc/rtc-cadence.c
171
writel(timr, crtc->regs + CDNS_RTC_TIMR);
drivers/rtc/rtc-cadence.c
172
writel(calr, crtc->regs + CDNS_RTC_CALR);
drivers/rtc/rtc-cadence.c
190
writel((CDNS_RTC_AEI_SEC | CDNS_RTC_AEI_MIN | CDNS_RTC_AEI_HOUR
drivers/rtc/rtc-cadence.c
193
writel(CDNS_RTC_AEI_ALRM, crtc->regs + CDNS_RTC_IENR);
drivers/rtc/rtc-cadence.c
195
writel(0, crtc->regs + CDNS_RTC_AENR);
drivers/rtc/rtc-cadence.c
196
writel(CDNS_RTC_AEI_ALRM, crtc->regs + CDNS_RTC_IDISR);
drivers/rtc/rtc-cadence.c
232
writel(timar, crtc->regs + CDNS_RTC_TIMAR);
drivers/rtc/rtc-cadence.c
233
writel(calar, crtc->regs + CDNS_RTC_CALAR);
drivers/rtc/rtc-cadence.c
336
writel(0, crtc->regs + CDNS_RTC_HMR);
drivers/rtc/rtc-cadence.c
337
writel(CDNS_RTC_KRTCR_KRTC, crtc->regs + CDNS_RTC_KRTCR);
drivers/rtc/rtc-cadence.c
91
writel(reg, crtc->regs + CDNS_RTC_CTLR);
drivers/rtc/rtc-ep93xx.c
68
writel(secs + 1, ep93xx_rtc->mmio_base + EP93XX_RTC_LOAD);
drivers/rtc/rtc-ftrtc010.c
98
writel(offset, rtc->rtc_base + FTRTC010_RTC_RECORD);
drivers/rtc/rtc-ftrtc010.c
99
writel(0x01, rtc->rtc_base + FTRTC010_RTC_CR);
drivers/rtc/rtc-imxdi.c
175
writel(val, imxdi->ioaddr + reg);
drivers/rtc/rtc-imxdi.c
447
writel(readl(imxdi->ioaddr + DIER) | intr,
drivers/rtc/rtc-imxdi.c
460
writel(readl(imxdi->ioaddr + DIER) & ~intr,
drivers/rtc/rtc-imxdi.c
479
writel(DSR_WEF, imxdi->ioaddr + DSR);
drivers/rtc/rtc-imxdi.c
511
writel(val, imxdi->ioaddr + reg);
drivers/rtc/rtc-imxdi.c
793
writel(0, imxdi->ioaddr + DIER);
drivers/rtc/rtc-imxdi.c
840
writel(0, imxdi->ioaddr + DIER);
drivers/rtc/rtc-jz4740.c
111
writel(val, rtc->base + reg);
drivers/rtc/rtc-jz4740.c
95
writel(JZ_RTC_WENR_MAGIC, rtc->base + JZ_REG_RTC_WENR);
drivers/rtc/rtc-loongson.c
148
writel(readl(priv->pm_base + PM1_EN_REG) & ~RTC_EN,
drivers/rtc/rtc-loongson.c
152
writel(RTC_STS, priv->pm_base + PM1_STS_REG);
drivers/rtc/rtc-loongson.c
273
writel(enabled ? val | RTC_EN : val & ~RTC_EN,
drivers/rtc/rtc-lpc24xx.c
59
#define rtc_writel(dev, reg, val) writel((val), (dev)->rtc_base + (reg))
drivers/rtc/rtc-mpfs.c
107
writel((u32)time, rtcdev->base + DATETIME_LOWER_REG);
drivers/rtc/rtc-mpfs.c
108
writel((u32)(time >> 32) & DATETIME_UPPER_MASK, rtcdev->base + DATETIME_UPPER_REG);
drivers/rtc/rtc-mpfs.c
113
writel(ctrl, rtcdev->base + CONTROL_REG);
drivers/rtc/rtc-mpfs.c
150
writel(ctrl, rtcdev->base + CONTROL_REG);
drivers/rtc/rtc-mpfs.c
154
writel((u32)time, rtcdev->base + ALARM_LOWER_REG);
drivers/rtc/rtc-mpfs.c
155
writel((u32)(time >> 32) & ALARM_UPPER_MASK, rtcdev->base + ALARM_UPPER_REG);
drivers/rtc/rtc-mpfs.c
158
writel(GENMASK(31, 0), rtcdev->base + COMPARE_LOWER_REG);
drivers/rtc/rtc-mpfs.c
159
writel(GENMASK(29, 0), rtcdev->base + COMPARE_UPPER_REG);
drivers/rtc/rtc-mpfs.c
172
writel(ctrl, rtcdev->base + CONTROL_REG);
drivers/rtc/rtc-mpfs.c
173
writel(mode, rtcdev->base + MODE_REG);
drivers/rtc/rtc-mpfs.c
191
writel(ctrl, rtcdev->base + CONTROL_REG);
drivers/rtc/rtc-mpfs.c
266
writel(prescaler, rtcdev->base + PRESCALER_REG);
drivers/rtc/rtc-mpfs.c
68
writel(ctrl, rtcdev->base + CONTROL_REG);
drivers/rtc/rtc-mpfs.c
77
writel(val, rtcdev->base + CONTROL_REG);
drivers/rtc/rtc-mt2712.c
93
writel(val, mt2712_rtc->base + reg);
drivers/rtc/rtc-mv.c
146
writel(rtc_reg, ioaddr + RTC_ALARM_TIME_REG_OFFS);
drivers/rtc/rtc-mv.c
162
writel(rtc_reg, ioaddr + RTC_ALARM_DATE_REG_OFFS);
drivers/rtc/rtc-mv.c
163
writel(0, ioaddr + RTC_ALARM_INTERRUPT_CASUE_REG_OFFS);
drivers/rtc/rtc-mv.c
164
writel(alm->enabled ? 1 : 0,
drivers/rtc/rtc-mv.c
179
writel(1, ioaddr + RTC_ALARM_INTERRUPT_MASK_REG_OFFS);
drivers/rtc/rtc-mv.c
181
writel(0, ioaddr + RTC_ALARM_INTERRUPT_MASK_REG_OFFS);
drivers/rtc/rtc-mv.c
195
writel(0, ioaddr + RTC_ALARM_INTERRUPT_CASUE_REG_OFFS);
drivers/rtc/rtc-mv.c
257
writel(0, pdata->ioaddr + RTC_ALARM_INTERRUPT_MASK_REG_OFFS);
drivers/rtc/rtc-mv.c
56
writel(rtc_reg, ioaddr + RTC_TIME_REG_OFFS);
drivers/rtc/rtc-mv.c
61
writel(rtc_reg, ioaddr + RTC_DATE_REG_OFFS);
drivers/rtc/rtc-mxc_v2.c
102
writel(lp_status, ioaddr + SRTC_LPSR);
drivers/rtc/rtc-mxc_v2.c
173
writel(time, pdata->ioaddr + SRTC_LPSCMR);
drivers/rtc/rtc-mxc_v2.c
216
writel(lp_cr, pdata->ioaddr + SRTC_LPCR);
drivers/rtc/rtc-mxc_v2.c
247
writel((u32)time, pdata->ioaddr + SRTC_LPSAR);
drivers/rtc/rtc-mxc_v2.c
250
writel(SRTC_LPSR_ALP, pdata->ioaddr + SRTC_LPSR);
drivers/rtc/rtc-mxc_v2.c
314
writel(SRTC_LPPDR_INIT, ioaddr + SRTC_LPPDR);
drivers/rtc/rtc-mxc_v2.c
317
writel(0xFFFFFFFF, ioaddr + SRTC_LPSR);
drivers/rtc/rtc-mxc_v2.c
320
writel((SRTC_LPCR_IE | SRTC_LPCR_NSA), ioaddr + SRTC_LPCR);
drivers/rtc/rtc-mxc_v2.c
329
writel((SRTC_LPCR_IE | SRTC_LPCR_NVE | SRTC_LPCR_NSA |
drivers/rtc/rtc-mxc_v2.c
99
writel(lp_cr, ioaddr + SRTC_LPCR);
drivers/rtc/rtc-omap.c
172
writel(val, rtc->base + reg);
drivers/rtc/rtc-pic32.c
104
writel(PIC32_RTCALRM_ALRMEN,
drivers/rtc/rtc-pic32.c
122
writel(PIC32_RTCALRM_AMASK, base + PIC32_CLR(PIC32_RTCALRM));
drivers/rtc/rtc-pic32.c
123
writel(freq << 8, base + PIC32_SET(PIC32_RTCALRM));
drivers/rtc/rtc-pic32.c
124
writel(PIC32_RTCALRM_CHIME, base + PIC32_SET(PIC32_RTCALRM));
drivers/rtc/rtc-pic32.c
230
writel(0x00, base + PIC32_ALRMTIME);
drivers/rtc/rtc-pic32.c
231
writel(0x00, base + PIC32_ALRMDATE);
drivers/rtc/rtc-pic32.c
273
writel(PIC32_RTCCON_ON, base + PIC32_CLR(PIC32_RTCCON));
drivers/rtc/rtc-pic32.c
277
writel(PIC32_RTCCON_RTCWREN, base + PIC32_SET(PIC32_RTCCON));
drivers/rtc/rtc-pic32.c
278
writel(3 << 9, base + PIC32_CLR(PIC32_RTCCON));
drivers/rtc/rtc-pic32.c
281
writel(PIC32_RTCCON_ON, base + PIC32_SET(PIC32_RTCCON));
drivers/rtc/rtc-pl030.c
144
writel(0, rtc->base + RTC_CR);
drivers/rtc/rtc-pl030.c
30
writel(0, rtc->base + RTC_EOI);
drivers/rtc/rtc-pl030.c
46
writel(rtc_tm_to_time64(&alrm->time), rtc->base + RTC_MR);
drivers/rtc/rtc-pl030.c
72
writel(rtc_tm_to_time64(tm) + 1, rtc->base + RTC_LR);
drivers/rtc/rtc-pl031.c
102
writel(RTC_BIT_AI, ldata->base + RTC_ICR);
drivers/rtc/rtc-pl031.c
107
writel(imsc | RTC_BIT_AI, ldata->base + RTC_IMSC);
drivers/rtc/rtc-pl031.c
109
writel(imsc & ~RTC_BIT_AI, ldata->base + RTC_IMSC);
drivers/rtc/rtc-pl031.c
187
writel(bcd_year, ldata->base + RTC_YLR);
drivers/rtc/rtc-pl031.c
188
writel(time, ldata->base + RTC_LR);
drivers/rtc/rtc-pl031.c
218
writel(bcd_year, ldata->base + RTC_YMR);
drivers/rtc/rtc-pl031.c
219
writel(time, ldata->base + RTC_MR);
drivers/rtc/rtc-pl031.c
235
writel(RTC_BIT_AI, ldata->base + RTC_ICR);
drivers/rtc/rtc-pl031.c
258
writel(rtc_tm_to_time64(tm), ldata->base + RTC_LR);
drivers/rtc/rtc-pl031.c
279
writel(rtc_tm_to_time64(&alarm->time), ldata->base + RTC_MR);
drivers/rtc/rtc-pl031.c
334
writel(data, ldata->base + RTC_CR);
drivers/rtc/rtc-pl031.c
347
writel(0x2000, ldata->base + RTC_YLR);
drivers/rtc/rtc-pl031.c
348
writel(time, ldata->base + RTC_LR);
drivers/rtc/rtc-rtd119x.c
64
writel(val, data->base + RTD_RTCCR);
drivers/rtc/rtc-rzn1.c
121
writel(RZN1_RTC_CTL2_WAIT, rtc->base + RZN1_RTC_CTL2);
drivers/rtc/rtc-rzn1.c
134
writel(val, rtc->base + RZN1_RTC_TIME);
drivers/rtc/rtc-rzn1.c
140
writel(val, rtc->base + RZN1_RTC_CAL);
drivers/rtc/rtc-rzn1.c
142
writel(0, rtc->base + RZN1_RTC_CTL2);
drivers/rtc/rtc-rzn1.c
163
writel(ctl1, rtc->base + RZN1_RTC_CTL1);
drivers/rtc/rtc-rzn1.c
178
writel(ctl1, rtc->base + RZN1_RTC_CTL1);
drivers/rtc/rtc-rzn1.c
215
writel(ctl1, rtc->base + RZN1_RTC_CTL1);
drivers/rtc/rtc-rzn1.c
219
writel(ctl1, rtc->base + RZN1_RTC_CTL1);
drivers/rtc/rtc-rzn1.c
281
writel(bin2bcd(tm->tm_min), rtc->base + RZN1_RTC_ALM);
drivers/rtc/rtc-rzn1.c
282
writel(bin2bcd(tm->tm_hour), rtc->base + RZN1_RTC_ALH);
drivers/rtc/rtc-rzn1.c
283
writel(BIT(wday), rtc->base + RZN1_RTC_ALW);
drivers/rtc/rtc-rzn1.c
357
writel(subu, rtc->base + RZN1_RTC_SUBU);
drivers/rtc/rtc-rzn1.c
436
writel(val, rtc->base + RZN1_RTC_CTL0);
drivers/rtc/rtc-rzn1.c
444
writel(RZN1_RTC_CTL0_AMPM | scmp_val, rtc->base + RZN1_RTC_CTL0);
drivers/rtc/rtc-rzn1.c
447
writel(rate - 1, rtc->base + RZN1_RTC_SCMP);
drivers/rtc/rtc-rzn1.c
454
writel(RZN1_RTC_CTL0_CE | RZN1_RTC_CTL0_AMPM | scmp_val, rtc->base + RZN1_RTC_CTL0);
drivers/rtc/rtc-rzn1.c
457
writel(0, rtc->base + RZN1_RTC_CTL1);
drivers/rtc/rtc-rzn1.c
494
writel(0, rtc->base + RZN1_RTC_CTL1);
drivers/rtc/rtc-s32g.c
140
writel(rtcc, priv->rtc_base + RTCC_OFFSET);
drivers/rtc/rtc-s32g.c
171
writel(cycles, priv->rtc_base + APIVAL_OFFSET);
drivers/rtc/rtc-s32g.c
187
writel(rtcc, priv->rtc_base + RTCC_OFFSET);
drivers/rtc/rtc-s32g.c
195
writel(rtcc, priv->rtc_base + RTCC_OFFSET);
drivers/rtc/rtc-s32g.c
227
writel(rtcc, priv->rtc_base + RTCC_OFFSET);
drivers/rtc/rtc-s32g.c
87
writel(0x0, priv->rtc_base + APIVAL_OFFSET);
drivers/rtc/rtc-s32g.c
88
writel(status | RTCS_APIF, priv->rtc_base + RTCS_OFFSET);
drivers/rtc/rtc-spear.c
105
writel(val, config->ioaddr + CTRL_REG);
drivers/rtc/rtc-spear.c
116
writel(val, config->ioaddr + CTRL_REG);
drivers/rtc/rtc-spear.c
242
writel(time, config->ioaddr + TIME_REG);
drivers/rtc/rtc-spear.c
243
writel(date, config->ioaddr + DATE_REG);
drivers/rtc/rtc-spear.c
301
writel(time, config->ioaddr + ALARM_TIME_REG);
drivers/rtc/rtc-spear.c
302
writel(date, config->ioaddr + ALARM_DATE_REG);
drivers/rtc/rtc-spear.c
93
writel(val, config->ioaddr + STATUS_REG);
drivers/rtc/rtc-stmp3xxx.c
164
writel(rtc_tm_to_time64(rtc_tm), rtc_data->io + STMP3XXX_RTC_SECONDS);
drivers/rtc/rtc-stmp3xxx.c
175
writel(STMP3XXX_RTC_CTRL_ALARM_IRQ,
drivers/rtc/rtc-stmp3xxx.c
189
writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN |
drivers/rtc/rtc-stmp3xxx.c
193
writel(STMP3XXX_RTC_CTRL_ALARM_IRQ_EN,
drivers/rtc/rtc-stmp3xxx.c
196
writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN |
drivers/rtc/rtc-stmp3xxx.c
200
writel(STMP3XXX_RTC_CTRL_ALARM_IRQ_EN,
drivers/rtc/rtc-stmp3xxx.c
218
writel(rtc_tm_to_time64(&alm->time), rtc_data->io + STMP3XXX_RTC_ALARM);
drivers/rtc/rtc-stmp3xxx.c
241
writel(STMP3XXX_RTC_CTRL_ALARM_IRQ_EN,
drivers/rtc/rtc-stmp3xxx.c
341
writel(pers0_set, rtc_data->io + STMP3XXX_RTC_PERSISTENT0 +
drivers/rtc/rtc-stmp3xxx.c
344
writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN |
drivers/rtc/rtc-stmp3xxx.c
349
writel(STMP3XXX_RTC_CTRL_ONEMSEC_IRQ_EN |
drivers/rtc/rtc-stmp3xxx.c
387
writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN |
drivers/rtc/rtc-stmp3xxx.c
82
writel(timeout, rtc_data->io + STMP3XXX_RTC_WATCHDOG);
drivers/rtc/rtc-stmp3xxx.c
83
writel(STMP3XXX_RTC_CTRL_WATCHDOGEN,
drivers/rtc/rtc-stmp3xxx.c
85
writel(STMP3XXX_RTC_PERSISTENT1_FORCE_UPDATER,
drivers/rtc/rtc-stmp3xxx.c
88
writel(STMP3XXX_RTC_CTRL_WATCHDOGEN,
drivers/rtc/rtc-stmp3xxx.c
90
writel(STMP3XXX_RTC_PERSISTENT1_FORCE_UPDATER,
drivers/rtc/rtc-sun6i.c
208
writel(val, rtc->base + SUN6I_LOSC_CTRL);
drivers/rtc/rtc-sun6i.c
259
writel(reg, rtc->base + SUN6I_LOSC_CTRL);
drivers/rtc/rtc-sun6i.c
268
writel(reg, rtc->base + SUN6I_LOSC_CTRL);
drivers/rtc/rtc-sun6i.c
426
writel(val, chip->base + SUN6I_ALRM_IRQ_STA);
drivers/rtc/rtc-sun6i.c
449
writel(SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND,
drivers/rtc/rtc-sun6i.c
454
writel(alrm_val, chip->base + SUN6I_ALRM_EN);
drivers/rtc/rtc-sun6i.c
455
writel(alrm_irq_val, chip->base + SUN6I_ALRM_IRQ_EN);
drivers/rtc/rtc-sun6i.c
456
writel(alrm_wake_val, chip->base + SUN6I_ALARM_CONFIG);
drivers/rtc/rtc-sun6i.c
565
writel(0, chip->base + SUN6I_ALRM_COUNTER);
drivers/rtc/rtc-sun6i.c
567
writel(0, chip->base + SUN6I_ALRM_COUNTER_HMS);
drivers/rtc/rtc-sun6i.c
570
writel(counter_val, chip->base + SUN6I_ALRM_COUNTER);
drivers/rtc/rtc-sun6i.c
572
writel(counter_val_hms, chip->base + SUN6I_ALRM_COUNTER_HMS);
drivers/rtc/rtc-sun6i.c
630
writel(time, chip->base + SUN6I_RTC_HMS);
drivers/rtc/rtc-sun6i.c
644
writel(date, chip->base + SUN6I_RTC_YMD);
drivers/rtc/rtc-sun6i.c
698
writel(val[i], chip->base + SUN6I_GP_DATA + offset + 4 * i);
drivers/rtc/rtc-sun6i.c
802
writel(0, chip->base + SUN6I_ALRM_COUNTER);
drivers/rtc/rtc-sun6i.c
805
writel(0, chip->base + SUN6I_ALRM_EN);
drivers/rtc/rtc-sun6i.c
808
writel(0, chip->base + SUN6I_ALRM_IRQ_EN);
drivers/rtc/rtc-sun6i.c
811
writel(0, chip->base + SUN6I_ALRM1_EN);
drivers/rtc/rtc-sun6i.c
814
writel(0, chip->base + SUN6I_ALRM1_IRQ_EN);
drivers/rtc/rtc-sun6i.c
817
writel(SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND,
drivers/rtc/rtc-sun6i.c
821
writel(SUN6I_ALRM1_IRQ_STA_WEEK_IRQ_PEND,
drivers/rtc/rtc-sun6i.c
825
writel(0, chip->base + SUN6I_ALARM_CONFIG);
drivers/rtc/rtc-sunplus.c
107
writel((u32)alarm_time, sp_rtc->reg_base + RTC_ALARM_SET);
drivers/rtc/rtc-sunplus.c
135
writel((TIMER_FREEZE_MASK_BIT | DIS_SYS_RST_RTC_MASK_BIT |
drivers/rtc/rtc-sunplus.c
141
writel((ALARM_EN_OVERDUE_MASK_BIT | ALARM_EN_PMC_MASK_BIT | ALARM_EN_MASK_BIT) |
drivers/rtc/rtc-sunplus.c
210
writel(BAT_CHARGE_RSEL_MASK_BIT | rsel, sp_rtc->reg_base + RTC_BATT_CHARGE_CTRL);
drivers/rtc/rtc-sunplus.c
214
writel(BAT_CHARGE_DSEL_MASK_BIT | BAT_CHARGE_DSEL_OFF,
drivers/rtc/rtc-sunplus.c
218
writel(BAT_CHARGE_DSEL_MASK_BIT | BAT_CHARGE_DSEL_ON,
drivers/rtc/rtc-sunplus.c
226
writel(BAT_CHARGE_EN_MASK_BIT | BAT_CHARGE_EN, sp_rtc->reg_base + RTC_BATT_CHARGE_CTRL);
drivers/rtc/rtc-sunplus.c
294
writel(DIS_SYS_RST_RTC_MASK_BIT | DIS_SYS_RST_RTC, sp_rtc->reg_base + RTC_CTRL);
drivers/rtc/rtc-sunplus.c
76
writel((u32)secs, sp_rtc->reg_base + RTC_TIMER_SET);
drivers/rtc/rtc-sunxi.c
153
writel(val, chip->base + SUNXI_ALRM_IRQ_STA);
drivers/rtc/rtc-sunxi.c
175
writel(SUNXI_ALRM_IRQ_STA_CNT_IRQ_PEND,
drivers/rtc/rtc-sunxi.c
179
writel(alrm_val, chip->base + SUNXI_ALRM_EN);
drivers/rtc/rtc-sunxi.c
180
writel(alrm_irq_val, chip->base + SUNXI_ALRM_IRQ_EN);
drivers/rtc/rtc-sunxi.c
291
writel(0, chip->base + SUNXI_ALRM_DHMS);
drivers/rtc/rtc-sunxi.c
298
writel(alrm, chip->base + SUNXI_ALRM_DHMS);
drivers/rtc/rtc-sunxi.c
300
writel(0, chip->base + SUNXI_ALRM_IRQ_EN);
drivers/rtc/rtc-sunxi.c
301
writel(SUNXI_ALRM_IRQ_EN_CNT_IRQ_EN, chip->base + SUNXI_ALRM_IRQ_EN);
drivers/rtc/rtc-sunxi.c
361
writel(0, chip->base + SUNXI_RTC_HMS);
drivers/rtc/rtc-sunxi.c
362
writel(0, chip->base + SUNXI_RTC_YMD);
drivers/rtc/rtc-sunxi.c
364
writel(time, chip->base + SUNXI_RTC_HMS);
drivers/rtc/rtc-sunxi.c
378
writel(date, chip->base + SUNXI_RTC_YMD);
drivers/rtc/rtc-sunxi.c
457
writel(0, chip->base + SUNXI_ALRM_DHMS);
drivers/rtc/rtc-sunxi.c
460
writel(0, chip->base + SUNXI_ALRM_EN);
drivers/rtc/rtc-sunxi.c
463
writel(0, chip->base + SUNXI_ALRM_IRQ_EN);
drivers/rtc/rtc-sunxi.c
466
writel(SUNXI_ALRM_IRQ_STA_CNT_IRQ_PEND, chip->base +
drivers/rtc/rtc-tegra.c
140
writel(sec, info->base + TEGRA_RTC_REG_SECONDS);
drivers/rtc/rtc-tegra.c
186
writel(status, info->base + TEGRA_RTC_REG_INTR_MASK);
drivers/rtc/rtc-tegra.c
204
writel(sec, info->base + TEGRA_RTC_REG_SECONDS_ALARM0);
drivers/rtc/rtc-tegra.c
244
writel(0, info->base + TEGRA_RTC_REG_INTR_MASK);
drivers/rtc/rtc-tegra.c
245
writel(status, info->base + TEGRA_RTC_REG_INTR_STATUS);
drivers/rtc/rtc-tegra.c
322
writel(0, info->base + TEGRA_RTC_REG_SECONDS_ALARM0);
drivers/rtc/rtc-tegra.c
323
writel(0xffffffff, info->base + TEGRA_RTC_REG_INTR_STATUS);
drivers/rtc/rtc-tegra.c
324
writel(0, info->base + TEGRA_RTC_REG_INTR_MASK);
drivers/rtc/rtc-tegra.c
350
writel(0xffffffff, info->base + TEGRA_RTC_REG_INTR_STATUS);
drivers/rtc/rtc-tegra.c
351
writel(TEGRA_RTC_INTR_STATUS_SEC_ALARM0,
drivers/rtc/rtc-vt8500.c
125
writel((bin2bcd(tm->tm_year % 100) << DATE_YEAR_S)
drivers/rtc/rtc-vt8500.c
130
writel((bin2bcd(tm->tm_wday) << TIME_DOW_S)
drivers/rtc/rtc-vt8500.c
162
writel((alrm->enabled ? ALARM_ENABLE_MASK : 0)
drivers/rtc/rtc-vt8500.c
182
writel(tmp, vt8500_rtc->regbase + VT8500_RTC_AS);
drivers/rtc/rtc-vt8500.c
216
writel(VT8500_RTC_CR_ENABLE,
drivers/rtc/rtc-vt8500.c
243
writel(0, vt8500_rtc->regbase + VT8500_RTC_IS);
drivers/rtc/rtc-vt8500.c
89
writel(isr, vt8500_rtc->regbase + VT8500_RTC_IS);
drivers/rtc/rtc-xgene.c
105
writel((u32)rtc_tm_to_time64(&alrm->time), pdata->csr_base + RTC_CMR);
drivers/rtc/rtc-xgene.c
175
writel(RTC_CCR_EN, pdata->csr_base + RTC_CCR);
drivers/rtc/rtc-xgene.c
59
writel((u32)rtc_tm_to_time64(tm), pdata->csr_base + RTC_CLR);
drivers/rtc/rtc-xgene.c
89
writel(ccr, pdata->csr_base + RTC_CCR);
drivers/rtc/rtc-zynqmp.c
141
writel(RTC_INT_ALRM, xrtcdev->reg_base + RTC_INT_STS);
drivers/rtc/rtc-zynqmp.c
144
writel(RTC_INT_ALRM, xrtcdev->reg_base + RTC_INT_EN);
drivers/rtc/rtc-zynqmp.c
146
writel(RTC_INT_ALRM, xrtcdev->reg_base + RTC_INT_DIS);
drivers/rtc/rtc-zynqmp.c
159
writel((u32)alarm_time, (xrtcdev->reg_base + RTC_ALRM));
drivers/rtc/rtc-zynqmp.c
173
writel(rtc_ctrl, xrtcdev->reg_base + RTC_CTRL);
drivers/rtc/rtc-zynqmp.c
242
writel(calibval, (xrtcdev->reg_base + RTC_CALIB_WR));
drivers/rtc/rtc-zynqmp.c
268
writel(RTC_INT_ALRM, xrtcdev->reg_base + RTC_INT_DIS);
drivers/rtc/rtc-zynqmp.c
305
writel(pending_alrm_irq, xrtcdev->reg_base + RTC_INT_STS);
drivers/rtc/rtc-zynqmp.c
358
writel(xrtcdev->freq, (xrtcdev->reg_base + RTC_CALIB_WR));
drivers/rtc/rtc-zynqmp.c
364
writel(RTC_INT_ALRM, xrtcdev->reg_base + RTC_INT_EN);
drivers/rtc/rtc-zynqmp.c
69
writel(new_time, xrtcdev->reg_base + RTC_SET_TM_WR);
drivers/rtc/rtc-zynqmp.c
79
writel(RTC_INT_SEC, xrtcdev->reg_base + RTC_INT_STS);
drivers/scsi/3w-9xxx.c
1525
writel((u32)command_que_value, TW_COMMAND_QUEUE_REG_ADDR_LARGE(tw_dev));
drivers/scsi/3w-9xxx.c
1557
writel((u32)((u64)command_que_value >> 32), TW_COMMAND_QUEUE_REG_ADDR_LARGE(tw_dev) + 0x4);
drivers/scsi/3w-9xxx.c
1561
writel((u32)command_que_value, TW_COMMAND_QUEUE_REG_ADDR(tw_dev));
drivers/scsi/3w-9xxx.c
1562
writel((u32)((u64)command_que_value >> 32), TW_COMMAND_QUEUE_REG_ADDR(tw_dev) + 0x4);
drivers/scsi/3w-9xxx.c
1564
writel(TW_COMMAND_OFFSET + command_que_value, TW_COMMAND_QUEUE_REG_ADDR(tw_dev));
drivers/scsi/3w-9xxx.c
915
writel(TW_CONTROL_CLEAR_PARITY_ERROR, TW_CONTROL_REG_ADDR(tw_dev));
drivers/scsi/3w-9xxx.c
920
writel(TW_CONTROL_CLEAR_PCI_ABORT, TW_CONTROL_REG_ADDR(tw_dev));
drivers/scsi/3w-9xxx.c
929
writel(TW_CONTROL_CLEAR_QUEUE_ERROR, TW_CONTROL_REG_ADDR(tw_dev));
drivers/scsi/3w-9xxx.h
453
(writel(TW_STATUS_VALID_INTERRUPT, TW_CONTROL_REG_ADDR(x)))
drivers/scsi/3w-9xxx.h
455
(writel(TW_CONTROL_CLEAR_ATTENTION_INTERRUPT, TW_CONTROL_REG_ADDR(x)))
drivers/scsi/3w-9xxx.h
457
(writel(TW_CONTROL_CLEAR_HOST_INTERRUPT, TW_CONTROL_REG_ADDR(x)))
drivers/scsi/3w-9xxx.h
459
(writel(TW_CONTROL_DISABLE_INTERRUPTS, TW_CONTROL_REG_ADDR(x)))
drivers/scsi/3w-9xxx.h
461
(writel(TW_CONTROL_CLEAR_ATTENTION_INTERRUPT | \
drivers/scsi/3w-9xxx.h
465
(writel(TW_CONTROL_MASK_COMMAND_INTERRUPT, TW_CONTROL_REG_ADDR(x)))
drivers/scsi/3w-9xxx.h
467
(writel(TW_CONTROL_UNMASK_COMMAND_INTERRUPT, TW_CONTROL_REG_ADDR(x)))
drivers/scsi/3w-9xxx.h
468
#define TW_SOFT_RESET(x) (writel(TW_CONTROL_ISSUE_SOFT_RESET | \
drivers/scsi/3w-sas.c
1179
writel((u32)((u64)tw_dev->sense_buffer_phys[i] >> 32), TWL_HOBQPH_REG_ADDR(tw_dev));
drivers/scsi/3w-sas.c
1180
writel((u32)tw_dev->sense_buffer_phys[i], TWL_HOBQPL_REG_ADDR(tw_dev));
drivers/scsi/3w-sas.c
1302
writel((u32)((u64)tw_dev->sense_buffer_phys[i] >> 32), TWL_HOBQPH_REG_ADDR(tw_dev));
drivers/scsi/3w-sas.c
1303
writel((u32)tw_dev->sense_buffer_phys[i], TWL_HOBQPL_REG_ADDR(tw_dev));
drivers/scsi/3w-sas.c
279
writel((u32)((u64)command_que_value >> 32), TWL_HIBQPH_REG_ADDR(tw_dev));
drivers/scsi/3w-sas.c
281
writel((u32)(command_que_value | TWL_PULL_MODE), TWL_HIBQPL_REG_ADDR(tw_dev));
drivers/scsi/3w-sas.h
198
(writel(~0, TWL_HIMASK_REG_ADDR(tw_dev)))
drivers/scsi/3w-sas.h
200
(writel(~TWL_HISTATUS_VALID_INTERRUPT, TWL_HIMASK_REG_ADDR(tw_dev)))
drivers/scsi/3w-sas.h
202
(writel(~0, TWL_HOBDBC_REG_ADDR(tw_dev)))
drivers/scsi/3w-sas.h
204
(writel(TWL_ISSUE_SOFT_RESET, TWL_HIBDB_REG_ADDR(tw_dev)))
drivers/scsi/aacraid/aacraid.h
1080
#define sa_writel(AEP, CSR, value) writel(value, &((AEP)->regs.sa->CSR))
drivers/scsi/aacraid/aacraid.h
1142
#define rx_writel(AEP, CSR, value) writel(value, &((AEP)->regs.rx->CSR))
drivers/scsi/aacraid/aacraid.h
1160
#define rkt_writel(AEP, CSR, value) writel(value, &((AEP)->regs.rkt->CSR))
drivers/scsi/aacraid/aacraid.h
1209
#define src_writel(AEP, CSR, value) writel(value, \
drivers/scsi/aacraid/rx.c
172
writel(command, &dev->IndexRegs->Mailbox[0]);
drivers/scsi/aacraid/rx.c
176
writel(p1, &dev->IndexRegs->Mailbox[1]);
drivers/scsi/aacraid/rx.c
177
writel(p2, &dev->IndexRegs->Mailbox[2]);
drivers/scsi/aacraid/rx.c
178
writel(p3, &dev->IndexRegs->Mailbox[3]);
drivers/scsi/aacraid/rx.c
179
writel(p4, &dev->IndexRegs->Mailbox[4]);
drivers/scsi/aacraid/rx.c
445
writel((u32)(addr & 0xffffffff), device);
drivers/scsi/aacraid/rx.c
447
writel((u32)(addr >> 32), device);
drivers/scsi/aacraid/rx.c
449
writel(le16_to_cpu(fib->hw_fib_va->header.Size), device);
drivers/scsi/aacraid/src.c
129
writel(events, &dev->IndexRegs->Mailbox[0]);
drivers/scsi/aacraid/src.c
220
writel(command, &dev->IndexRegs->Mailbox[0]);
drivers/scsi/aacraid/src.c
224
writel(p1, &dev->IndexRegs->Mailbox[1]);
drivers/scsi/aacraid/src.c
225
writel(p2, &dev->IndexRegs->Mailbox[2]);
drivers/scsi/aacraid/src.c
226
writel(p3, &dev->IndexRegs->Mailbox[3]);
drivers/scsi/aacraid/src.c
227
writel(p4, &dev->IndexRegs->Mailbox[4]);
drivers/scsi/aacraid/src.c
785
writel(val, ((char *)(dev->base) + IBW_SWR_OFFSET));
drivers/scsi/advansys.c
867
#define ADV_MEM_WRITEDW(addr, dword) writel(dword, addr)
drivers/scsi/aic94xx/aic94xx_reg.c
46
writel(val, asd_ha->io_handle[0].addr + offs);
drivers/scsi/arcmsr/arcmsr_hba.c
1241
writel(0, &acb->pmuE->host_int_status);
drivers/scsi/arcmsr/arcmsr_hba.c
1242
writel(ARCMSR_HBEMU_DOORBELL_SYNC, &acb->pmuE->iobound_doorbell);
drivers/scsi/arcmsr/arcmsr_hba.c
1248
writel(0, &acb->pmuF->host_int_status);
drivers/scsi/arcmsr/arcmsr_hba.c
1249
writel(ARCMSR_HBFMU_DOORBELL_SYNC, &acb->pmuF->iobound_doorbell);
drivers/scsi/arcmsr/arcmsr_hba.c
1277
writel(ARCMSR_INBOUND_MESG0_ABORT_CMD, ®->inbound_msgaddr0);
drivers/scsi/arcmsr/arcmsr_hba.c
1291
writel(ARCMSR_MESSAGE_ABORT_CMD, reg->drv2iop_doorbell);
drivers/scsi/arcmsr/arcmsr_hba.c
1303
writel(ARCMSR_INBOUND_MESG0_ABORT_CMD, ®->inbound_msgaddr0);
drivers/scsi/arcmsr/arcmsr_hba.c
1304
writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, ®->inbound_doorbell);
drivers/scsi/arcmsr/arcmsr_hba.c
1318
writel(ARCMSR_INBOUND_MESG0_ABORT_CMD, reg->inbound_msgaddr0);
drivers/scsi/arcmsr/arcmsr_hba.c
1331
writel(ARCMSR_INBOUND_MESG0_ABORT_CMD, ®->inbound_msgaddr0);
drivers/scsi/arcmsr/arcmsr_hba.c
1333
writel(pACB->out_doorbell, ®->iobound_doorbell);
drivers/scsi/arcmsr/arcmsr_hba.c
1407
writel(orig_mask|ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE, \
drivers/scsi/arcmsr/arcmsr_hba.c
1414
writel(0, reg->iop2drv_doorbell_mask);
drivers/scsi/arcmsr/arcmsr_hba.c
1421
writel(orig_mask|ARCMSR_HBCMU_ALL_INTMASKENABLE, ®->host_int_mask);
drivers/scsi/arcmsr/arcmsr_hba.c
1427
writel(ARCMSR_ARC1214_ALL_INT_DISABLE, reg->pcief0_int_enable);
drivers/scsi/arcmsr/arcmsr_hba.c
1434
writel(orig_mask | ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR | ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR, ®->host_int_mask);
drivers/scsi/arcmsr/arcmsr_hba.c
1539
writel(outbound_intstatus, ®->outbound_intstatus);/*clear interrupt*/
drivers/scsi/arcmsr/arcmsr_hba.c
1556
writel(ARCMSR_DOORBELL_INT_CLEAR_PATTERN, reg->iop2drv_doorbell); /* clear doorbell interrupt */
drivers/scsi/arcmsr/arcmsr_hba.c
1624
writel(doneq_index,
drivers/scsi/arcmsr/arcmsr_hba.c
1804
writel(mask, ®->outbound_intmask);
drivers/scsi/arcmsr/arcmsr_hba.c
1815
writel(mask, reg->iop2drv_doorbell_mask);
drivers/scsi/arcmsr/arcmsr_hba.c
1822
writel(intmask_org & mask, ®->host_int_mask);
drivers/scsi/arcmsr/arcmsr_hba.c
1830
writel(intmask_org | mask, reg->pcief0_int_enable);
drivers/scsi/arcmsr/arcmsr_hba.c
1838
writel(intmask_org & mask, ®->host_int_mask);
drivers/scsi/arcmsr/arcmsr_hba.c
1910
writel(cdb_phyaddr | ARCMSR_CCBPOST_FLAG_SGL_BSIZE,
drivers/scsi/arcmsr/arcmsr_hba.c
1913
writel(cdb_phyaddr, ®->inbound_queueport);
drivers/scsi/arcmsr/arcmsr_hba.c
1932
writel(ARCMSR_DRV2IOP_CDB_POSTED, reg->drv2iop_doorbell);
drivers/scsi/arcmsr/arcmsr_hba.c
1941
writel(upper_32_bits(ccb->cdb_phyaddr), &phbcmu->inbound_queueport_high);
drivers/scsi/arcmsr/arcmsr_hba.c
1942
writel(ccb_post_stamp, &phbcmu->inbound_queueport_low);
drivers/scsi/arcmsr/arcmsr_hba.c
1964
writel(postq_index, pmu->inboundlist_write_pointer);
drivers/scsi/arcmsr/arcmsr_hba.c
1974
writel(0, &pmu->inbound_queueport_high);
drivers/scsi/arcmsr/arcmsr_hba.c
1975
writel(ccb_post_stamp, &pmu->inbound_queueport_low);
drivers/scsi/arcmsr/arcmsr_hba.c
1991
writel(0, &pmu->inbound_queueport_high);
drivers/scsi/arcmsr/arcmsr_hba.c
1992
writel(ccb_post_stamp, &pmu->inbound_queueport_low);
drivers/scsi/arcmsr/arcmsr_hba.c
2002
writel(ARCMSR_INBOUND_MESG0_STOP_BGRB, ®->inbound_msgaddr0);
drivers/scsi/arcmsr/arcmsr_hba.c
2014
writel(ARCMSR_MESSAGE_STOP_BGRB, reg->drv2iop_doorbell);
drivers/scsi/arcmsr/arcmsr_hba.c
2027
writel(ARCMSR_INBOUND_MESG0_STOP_BGRB, ®->inbound_msgaddr0);
drivers/scsi/arcmsr/arcmsr_hba.c
2028
writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, ®->inbound_doorbell);
drivers/scsi/arcmsr/arcmsr_hba.c
2042
writel(ARCMSR_INBOUND_MESG0_STOP_BGRB, reg->inbound_msgaddr0);
drivers/scsi/arcmsr/arcmsr_hba.c
2053
writel(ARCMSR_INBOUND_MESG0_STOP_BGRB, ®->inbound_msgaddr0);
drivers/scsi/arcmsr/arcmsr_hba.c
2055
writel(pACB->out_doorbell, ®->iobound_doorbell);
drivers/scsi/arcmsr/arcmsr_hba.c
2117
writel(ARCMSR_INBOUND_DRIVER_DATA_READ_OK, ®->inbound_doorbell);
drivers/scsi/arcmsr/arcmsr_hba.c
2122
writel(ARCMSR_DRV2IOP_DATA_READ_OK, reg->drv2iop_doorbell);
drivers/scsi/arcmsr/arcmsr_hba.c
2128
writel(ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK, ®->inbound_doorbell);
drivers/scsi/arcmsr/arcmsr_hba.c
2133
writel(ARCMSR_ARC1214_DRV2IOP_DATA_OUT_READ,
drivers/scsi/arcmsr/arcmsr_hba.c
2141
writel(acb->out_doorbell, ®->iobound_doorbell);
drivers/scsi/arcmsr/arcmsr_hba.c
2156
writel(ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK, ®->inbound_doorbell);
drivers/scsi/arcmsr/arcmsr_hba.c
2166
writel(ARCMSR_DRV2IOP_DATA_WRITE_OK, reg->drv2iop_doorbell);
drivers/scsi/arcmsr/arcmsr_hba.c
2175
writel(ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK, ®->inbound_doorbell);
drivers/scsi/arcmsr/arcmsr_hba.c
2180
writel(ARCMSR_ARC1214_DRV2IOP_DATA_IN_READY,
drivers/scsi/arcmsr/arcmsr_hba.c
2188
writel(acb->out_doorbell, ®->iobound_doorbell);
drivers/scsi/arcmsr/arcmsr_hba.c
2385
writel(data, iop_data);
drivers/scsi/arcmsr/arcmsr_hba.c
2391
writel(data, iop_data);
drivers/scsi/arcmsr/arcmsr_hba.c
2393
writel(allxfer_len, &pwbuffer->data_len);
drivers/scsi/arcmsr/arcmsr_hba.c
2424
writel(allxfer_len, &pwbuffer->data_len);
drivers/scsi/arcmsr/arcmsr_hba.c
2448
writel(outbound_doorbell, ®->outbound_doorbell);
drivers/scsi/arcmsr/arcmsr_hba.c
2470
writel(outbound_doorbell, ®->outbound_doorbell_clear);
drivers/scsi/arcmsr/arcmsr_hba.c
2491
writel(outbound_doorbell, pmu->outbound_doorbell);
drivers/scsi/arcmsr/arcmsr_hba.c
2519
writel(0, ®->host_int_status); /* clear interrupt */
drivers/scsi/arcmsr/arcmsr_hba.c
2611
writel(ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING,
drivers/scsi/arcmsr/arcmsr_hba.c
2652
writel(doneq_index, pmu->outboundlist_read_pointer);
drivers/scsi/arcmsr/arcmsr_hba.c
2656
writel(ARCMSR_ARC1214_OUTBOUND_LIST_INTERRUPT_CLEAR,
drivers/scsi/arcmsr/arcmsr_hba.c
2685
writel(doneq_index, &pmu->reply_post_consumer_index);
drivers/scsi/arcmsr/arcmsr_hba.c
2715
writel(doneq_index, &phbcmu->reply_post_consumer_index);
drivers/scsi/arcmsr/arcmsr_hba.c
2731
writel(ARCMSR_MU_OUTBOUND_MESSAGE0_INT, ®->outbound_intstatus);
drivers/scsi/arcmsr/arcmsr_hba.c
2740
writel(ARCMSR_MESSAGE_INT_CLEAR_PATTERN, reg->iop2drv_doorbell);
drivers/scsi/arcmsr/arcmsr_hba.c
2757
writel(ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR, ®->outbound_doorbell_clear);
drivers/scsi/arcmsr/arcmsr_hba.c
2766
writel(ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE, reg->outbound_doorbell);
drivers/scsi/arcmsr/arcmsr_hba.c
2776
writel(0, ®->host_int_status);
drivers/scsi/arcmsr/arcmsr_hba.c
2790
writel(outbound_intstatus, ®->outbound_intstatus);
drivers/scsi/arcmsr/arcmsr_hba.c
2814
writel(~outbound_doorbell, reg->iop2drv_doorbell);
drivers/scsi/arcmsr/arcmsr_hba.c
2815
writel(ARCMSR_DRV2IOP_END_OF_INTERRUPT, reg->drv2iop_doorbell);
drivers/scsi/arcmsr/arcmsr_hba.c
295
writel(ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR, &acb->pmuC->outbound_doorbell_clear);/*clear interrupt*/
drivers/scsi/arcmsr/arcmsr_hba.c
323
writel(0, &acb->pmuE->host_int_status); /*clear interrupt*/
drivers/scsi/arcmsr/arcmsr_hba.c
324
writel(ARCMSR_HBEMU_DOORBELL_SYNC, &acb->pmuE->iobound_doorbell); /* synchronize doorbell to 0 */
drivers/scsi/arcmsr/arcmsr_hba.c
336
writel(0, &acb->pmuF->host_int_status); /* clear interrupt */
drivers/scsi/arcmsr/arcmsr_hba.c
337
writel(ARCMSR_HBFMU_DOORBELL_SYNC, &acb->pmuF->iobound_doorbell);
drivers/scsi/arcmsr/arcmsr_hba.c
3412
writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, ®->inbound_msgaddr0);
drivers/scsi/arcmsr/arcmsr_hba.c
3426
writel(ARCMSR_MESSAGE_START_DRIVER_MODE, reg->drv2iop_doorbell);
drivers/scsi/arcmsr/arcmsr_hba.c
3431
writel(ARCMSR_MESSAGE_GET_CONFIG, reg->drv2iop_doorbell);
drivers/scsi/arcmsr/arcmsr_hba.c
3448
writel(intmask_org|ARCMSR_HBCMU_ALL_INTMASKENABLE, ®->host_int_mask);
drivers/scsi/arcmsr/arcmsr_hba.c
3452
writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, ®->inbound_msgaddr0);
drivers/scsi/arcmsr/arcmsr_hba.c
3453
writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, ®->inbound_doorbell);
drivers/scsi/arcmsr/arcmsr_hba.c
3470
writel(ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE,
drivers/scsi/arcmsr/arcmsr_hba.c
3475
writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, reg->inbound_msgaddr0);
drivers/scsi/arcmsr/arcmsr_hba.c
3493
writel(intmask_org | ARCMSR_HBEMU_ALL_INTMASKENABLE, ®->host_int_mask);
drivers/scsi/arcmsr/arcmsr_hba.c
3498
writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, ®->inbound_msgaddr0);
drivers/scsi/arcmsr/arcmsr_hba.c
3501
writel(pACB->out_doorbell, ®->iobound_doorbell);
drivers/scsi/arcmsr/arcmsr_hba.c
3519
writel(intmask_org | ARCMSR_HBEMU_ALL_INTMASKENABLE, ®->host_int_mask);
drivers/scsi/arcmsr/arcmsr_hba.c
3523
writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, ®->inbound_msgaddr0);
drivers/scsi/arcmsr/arcmsr_hba.c
3526
writel(pACB->out_doorbell, ®->iobound_doorbell);
drivers/scsi/arcmsr/arcmsr_hba.c
3588
writel(outbound_intstatus, ®->outbound_intstatus);/*clear interrupt*/
drivers/scsi/arcmsr/arcmsr_hba.c
3649
writel(ARCMSR_DOORBELL_INT_CLEAR_PATTERN, reg->iop2drv_doorbell);
drivers/scsi/arcmsr/arcmsr_hba.c
3907
writel(doneq_index, ®->reply_post_consumer_index);
drivers/scsi/arcmsr/arcmsr_hba.c
3972
writel(datetime.b.msg_time[0], ®->message_rwbuffer[0]);
drivers/scsi/arcmsr/arcmsr_hba.c
3973
writel(datetime.b.msg_time[1], ®->message_rwbuffer[1]);
drivers/scsi/arcmsr/arcmsr_hba.c
3974
writel(ARCMSR_INBOUND_MESG0_SYNC_TIMER, ®->inbound_msgaddr0);
drivers/scsi/arcmsr/arcmsr_hba.c
3981
writel(datetime.b.msg_time[0], rwbuffer++);
drivers/scsi/arcmsr/arcmsr_hba.c
3982
writel(datetime.b.msg_time[1], rwbuffer++);
drivers/scsi/arcmsr/arcmsr_hba.c
3983
writel(ARCMSR_MESSAGE_SYNC_TIMER, reg->drv2iop_doorbell);
drivers/scsi/arcmsr/arcmsr_hba.c
3988
writel(datetime.b.msg_time[0], ®->msgcode_rwbuffer[0]);
drivers/scsi/arcmsr/arcmsr_hba.c
3989
writel(datetime.b.msg_time[1], ®->msgcode_rwbuffer[1]);
drivers/scsi/arcmsr/arcmsr_hba.c
3990
writel(ARCMSR_INBOUND_MESG0_SYNC_TIMER, ®->inbound_msgaddr0);
drivers/scsi/arcmsr/arcmsr_hba.c
3991
writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, ®->inbound_doorbell);
drivers/scsi/arcmsr/arcmsr_hba.c
3998
writel(datetime.b.msg_time[0], rwbuffer++);
drivers/scsi/arcmsr/arcmsr_hba.c
3999
writel(datetime.b.msg_time[1], rwbuffer++);
drivers/scsi/arcmsr/arcmsr_hba.c
4000
writel(ARCMSR_INBOUND_MESG0_SYNC_TIMER, reg->inbound_msgaddr0);
drivers/scsi/arcmsr/arcmsr_hba.c
4005
writel(datetime.b.msg_time[0], ®->msgcode_rwbuffer[0]);
drivers/scsi/arcmsr/arcmsr_hba.c
4006
writel(datetime.b.msg_time[1], ®->msgcode_rwbuffer[1]);
drivers/scsi/arcmsr/arcmsr_hba.c
4007
writel(ARCMSR_INBOUND_MESG0_SYNC_TIMER, ®->inbound_msgaddr0);
drivers/scsi/arcmsr/arcmsr_hba.c
4009
writel(pacb->out_doorbell, ®->iobound_doorbell);
drivers/scsi/arcmsr/arcmsr_hba.c
4017
writel(ARCMSR_INBOUND_MESG0_SYNC_TIMER, ®->inbound_msgaddr0);
drivers/scsi/arcmsr/arcmsr_hba.c
4019
writel(pacb->out_doorbell, ®->iobound_doorbell);
drivers/scsi/arcmsr/arcmsr_hba.c
4069
writel(ARCMSR_SIGNATURE_SET_CONFIG, \
drivers/scsi/arcmsr/arcmsr_hba.c
4071
writel(cdb_phyaddr_hi32, ®->message_rwbuffer[1]);
drivers/scsi/arcmsr/arcmsr_hba.c
4072
writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, \
drivers/scsi/arcmsr/arcmsr_hba.c
4090
writel(ARCMSR_MESSAGE_SET_POST_WINDOW, reg->drv2iop_doorbell);
drivers/scsi/arcmsr/arcmsr_hba.c
4098
writel(ARCMSR_SIGNATURE_SET_CONFIG, rwbuffer++);
drivers/scsi/arcmsr/arcmsr_hba.c
4100
writel(cdb_phyaddr_hi32, rwbuffer++);
drivers/scsi/arcmsr/arcmsr_hba.c
4102
writel(cdb_phyaddr, rwbuffer++);
drivers/scsi/arcmsr/arcmsr_hba.c
4104
writel(cdb_phyaddr + 1056, rwbuffer++);
drivers/scsi/arcmsr/arcmsr_hba.c
4106
writel(1056, rwbuffer);
drivers/scsi/arcmsr/arcmsr_hba.c
4108
writel(ARCMSR_MESSAGE_SET_CONFIG, reg->drv2iop_doorbell);
drivers/scsi/arcmsr/arcmsr_hba.c
411
writel(ARCMSR_MU_OUTBOUND_MESSAGE0_INT,
drivers/scsi/arcmsr/arcmsr_hba.c
4114
writel(ARCMSR_MESSAGE_START_DRIVER_MODE, reg->drv2iop_doorbell);
drivers/scsi/arcmsr/arcmsr_hba.c
4127
writel(ARCMSR_SIGNATURE_SET_CONFIG, ®->msgcode_rwbuffer[0]);
drivers/scsi/arcmsr/arcmsr_hba.c
4128
writel(cdb_phyaddr_hi32, ®->msgcode_rwbuffer[1]);
drivers/scsi/arcmsr/arcmsr_hba.c
4129
writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, ®->inbound_msgaddr0);
drivers/scsi/arcmsr/arcmsr_hba.c
4130
writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, ®->inbound_doorbell);
drivers/scsi/arcmsr/arcmsr_hba.c
4144
writel(ARCMSR_SIGNATURE_SET_CONFIG, rwbuffer++);
drivers/scsi/arcmsr/arcmsr_hba.c
4145
writel(cdb_phyaddr_hi32, rwbuffer++);
drivers/scsi/arcmsr/arcmsr_hba.c
4146
writel(cdb_phyaddr, rwbuffer++);
drivers/scsi/arcmsr/arcmsr_hba.c
4147
writel(cdb_phyaddr + (ARCMSR_MAX_ARC1214_POSTQUEUE *
drivers/scsi/arcmsr/arcmsr_hba.c
4149
writel(0x100, rwbuffer);
drivers/scsi/arcmsr/arcmsr_hba.c
4150
writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, reg->inbound_msgaddr0);
drivers/scsi/arcmsr/arcmsr_hba.c
4160
writel(ARCMSR_SIGNATURE_SET_CONFIG, ®->msgcode_rwbuffer[0]);
drivers/scsi/arcmsr/arcmsr_hba.c
4161
writel(ARCMSR_SIGNATURE_1884, ®->msgcode_rwbuffer[1]);
drivers/scsi/arcmsr/arcmsr_hba.c
4162
writel(cdb_phyaddr, ®->msgcode_rwbuffer[2]);
drivers/scsi/arcmsr/arcmsr_hba.c
4163
writel(cdb_phyaddr_hi32, ®->msgcode_rwbuffer[3]);
drivers/scsi/arcmsr/arcmsr_hba.c
4164
writel(acb->ccbsize, ®->msgcode_rwbuffer[4]);
drivers/scsi/arcmsr/arcmsr_hba.c
4165
writel(lower_32_bits(acb->dma_coherent_handle2), ®->msgcode_rwbuffer[5]);
drivers/scsi/arcmsr/arcmsr_hba.c
4166
writel(upper_32_bits(acb->dma_coherent_handle2), ®->msgcode_rwbuffer[6]);
drivers/scsi/arcmsr/arcmsr_hba.c
4167
writel(acb->ioqueue_size, ®->msgcode_rwbuffer[7]);
drivers/scsi/arcmsr/arcmsr_hba.c
4168
writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, ®->inbound_msgaddr0);
drivers/scsi/arcmsr/arcmsr_hba.c
4170
writel(acb->out_doorbell, ®->iobound_doorbell);
drivers/scsi/arcmsr/arcmsr_hba.c
4195
writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, ®->inbound_msgaddr0);
drivers/scsi/arcmsr/arcmsr_hba.c
4197
writel(acb->out_doorbell, ®->iobound_doorbell);
drivers/scsi/arcmsr/arcmsr_hba.c
4231
writel(ARCMSR_DRV2IOP_END_OF_INTERRUPT, reg->drv2iop_doorbell);
drivers/scsi/arcmsr/arcmsr_hba.c
4277
writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, ®->inbound_msgaddr0);
drivers/scsi/arcmsr/arcmsr_hba.c
4282
writel(ARCMSR_MESSAGE_GET_CONFIG, reg->drv2iop_doorbell);
drivers/scsi/arcmsr/arcmsr_hba.c
4287
writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, ®->inbound_msgaddr0);
drivers/scsi/arcmsr/arcmsr_hba.c
4288
writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, ®->inbound_doorbell);
drivers/scsi/arcmsr/arcmsr_hba.c
429
writel(ARCMSR_MESSAGE_INT_CLEAR_PATTERN,
drivers/scsi/arcmsr/arcmsr_hba.c
4293
writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, reg->inbound_msgaddr0);
drivers/scsi/arcmsr/arcmsr_hba.c
4298
writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, ®->inbound_msgaddr0);
drivers/scsi/arcmsr/arcmsr_hba.c
4300
writel(acb->out_doorbell, ®->iobound_doorbell);
drivers/scsi/arcmsr/arcmsr_hba.c
431
writel(ARCMSR_DRV2IOP_END_OF_INTERRUPT,
drivers/scsi/arcmsr/arcmsr_hba.c
4310
writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, ®->inbound_msgaddr0);
drivers/scsi/arcmsr/arcmsr_hba.c
4312
writel(acb->out_doorbell, ®->iobound_doorbell);
drivers/scsi/arcmsr/arcmsr_hba.c
4328
writel(ARCMSR_INBOUND_MESG0_START_BGRB, ®->inbound_msgaddr0);
drivers/scsi/arcmsr/arcmsr_hba.c
4339
writel(ARCMSR_MESSAGE_START_BGRB, reg->drv2iop_doorbell);
drivers/scsi/arcmsr/arcmsr_hba.c
4350
writel(ARCMSR_INBOUND_MESG0_START_BGRB, &phbcmu->inbound_msgaddr0);
drivers/scsi/arcmsr/arcmsr_hba.c
4351
writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &phbcmu->inbound_doorbell);
drivers/scsi/arcmsr/arcmsr_hba.c
4364
writel(ARCMSR_INBOUND_MESG0_START_BGRB, pmu->inbound_msgaddr0);
drivers/scsi/arcmsr/arcmsr_hba.c
4376
writel(ARCMSR_INBOUND_MESG0_START_BGRB, &pmu->inbound_msgaddr0);
drivers/scsi/arcmsr/arcmsr_hba.c
4378
writel(pACB->out_doorbell, &pmu->iobound_doorbell);
drivers/scsi/arcmsr/arcmsr_hba.c
4416
writel(outbound_doorbell, ®->outbound_doorbell);
drivers/scsi/arcmsr/arcmsr_hba.c
4417
writel(ARCMSR_INBOUND_DRIVER_DATA_READ_OK, ®->inbound_doorbell);
drivers/scsi/arcmsr/arcmsr_hba.c
4424
writel(ARCMSR_DOORBELL_INT_CLEAR_PATTERN, reg->iop2drv_doorbell);
drivers/scsi/arcmsr/arcmsr_hba.c
4425
writel(ARCMSR_DRV2IOP_DATA_READ_OK, reg->drv2iop_doorbell);
drivers/scsi/arcmsr/arcmsr_hba.c
4431
writel(ARCMSR_DOORBELL_INT_CLEAR_PATTERN, reg->iop2drv_doorbell);
drivers/scsi/arcmsr/arcmsr_hba.c
4432
writel(ARCMSR_DRV2IOP_DATA_READ_OK, reg->drv2iop_doorbell);
drivers/scsi/arcmsr/arcmsr_hba.c
4443
writel(outbound_doorbell, ®->outbound_doorbell_clear);
drivers/scsi/arcmsr/arcmsr_hba.c
4444
writel(ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK, ®->inbound_doorbell);
drivers/scsi/arcmsr/arcmsr_hba.c
4450
writel(outbound_doorbell,
drivers/scsi/arcmsr/arcmsr_hba.c
4452
writel(ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK,
drivers/scsi/arcmsr/arcmsr_hba.c
4464
writel(outbound_doorbell, reg->outbound_doorbell);
drivers/scsi/arcmsr/arcmsr_hba.c
4465
writel(ARCMSR_ARC1214_DRV2IOP_DATA_OUT_READ,
drivers/scsi/arcmsr/arcmsr_hba.c
4472
writel(outbound_doorbell,
drivers/scsi/arcmsr/arcmsr_hba.c
4474
writel(ARCMSR_ARC1214_DRV2IOP_DATA_OUT_READ,
drivers/scsi/arcmsr/arcmsr_hba.c
4487
writel(0, ®->host_int_status); /*clear interrupt*/
drivers/scsi/arcmsr/arcmsr_hba.c
4489
writel(acb->out_doorbell, ®->iobound_doorbell);
drivers/scsi/arcmsr/arcmsr_hba.c
449
writel(ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR,
drivers/scsi/arcmsr/arcmsr_hba.c
4495
writel(0, ®->host_int_status); /*clear interrupt*/
drivers/scsi/arcmsr/arcmsr_hba.c
4497
writel(acb->out_doorbell, ®->iobound_doorbell);
drivers/scsi/arcmsr/arcmsr_hba.c
4514
writel(ARCMSR_MESSAGE_ACTIVE_EOI_MODE, reg->drv2iop_doorbell);
drivers/scsi/arcmsr/arcmsr_hba.c
4542
writel(ARCMSR_ARC1680_BUS_RESET, &pmuA->reserved1[0]);
drivers/scsi/arcmsr/arcmsr_hba.c
4546
writel(0xF, &pmuC->write_sequence);
drivers/scsi/arcmsr/arcmsr_hba.c
4547
writel(0x4, &pmuC->write_sequence);
drivers/scsi/arcmsr/arcmsr_hba.c
4548
writel(0xB, &pmuC->write_sequence);
drivers/scsi/arcmsr/arcmsr_hba.c
4549
writel(0x2, &pmuC->write_sequence);
drivers/scsi/arcmsr/arcmsr_hba.c
4550
writel(0x7, &pmuC->write_sequence);
drivers/scsi/arcmsr/arcmsr_hba.c
4551
writel(0xD, &pmuC->write_sequence);
drivers/scsi/arcmsr/arcmsr_hba.c
4553
writel(ARCMSR_ARC1880_RESET_ADAPTER, &pmuC->host_diagnostic);
drivers/scsi/arcmsr/arcmsr_hba.c
4558
writel(0x4, &pmuE->write_sequence_3xxx);
drivers/scsi/arcmsr/arcmsr_hba.c
4559
writel(0xB, &pmuE->write_sequence_3xxx);
drivers/scsi/arcmsr/arcmsr_hba.c
4560
writel(0x2, &pmuE->write_sequence_3xxx);
drivers/scsi/arcmsr/arcmsr_hba.c
4561
writel(0x7, &pmuE->write_sequence_3xxx);
drivers/scsi/arcmsr/arcmsr_hba.c
4562
writel(0xD, &pmuE->write_sequence_3xxx);
drivers/scsi/arcmsr/arcmsr_hba.c
4566
writel(ARCMSR_ARC188X_RESET_ADAPTER, &pmuE->host_diagnostic_3xxx);
drivers/scsi/arcmsr/arcmsr_hba.c
4568
writel(0x20, pmuD->reset_request);
drivers/scsi/arcmsr/arcmsr_hba.c
467
writel(ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE,
drivers/scsi/arcmsr/arcmsr_hba.c
485
writel(0, &phbcmu->host_int_status); /*clear interrupt*/
drivers/scsi/arcmsr/arcmsr_hba.c
498
writel(ARCMSR_INBOUND_MESG0_FLUSH_CACHE, ®->inbound_msgaddr0);
drivers/scsi/arcmsr/arcmsr_hba.c
514
writel(ARCMSR_MESSAGE_FLUSH_CACHE, reg->drv2iop_doorbell);
drivers/scsi/arcmsr/arcmsr_hba.c
530
writel(ARCMSR_INBOUND_MESG0_FLUSH_CACHE, ®->inbound_msgaddr0);
drivers/scsi/arcmsr/arcmsr_hba.c
531
writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, ®->inbound_doorbell);
drivers/scsi/arcmsr/arcmsr_hba.c
549
writel(ARCMSR_INBOUND_MESG0_FLUSH_CACHE, reg->inbound_msgaddr0);
drivers/scsi/arcmsr/arcmsr_hba.c
566
writel(ARCMSR_INBOUND_MESG0_FLUSH_CACHE, ®->inbound_msgaddr0);
drivers/scsi/arcmsr/arcmsr_hba.c
568
writel(pACB->out_doorbell, ®->iobound_doorbell);
drivers/scsi/arcmsr/arcmsr_hba.c
668
writel(lower_32_bits(host_buffer_dma | 1), &pmuF->inbound_msgaddr0);
drivers/scsi/arcmsr/arcmsr_hba.c
670
writel(upper_32_bits(host_buffer_dma), &pmuF->inbound_msgaddr1);
drivers/scsi/arcmsr/arcmsr_hba.c
672
writel(ARCMSR_HBFMU_DOORBELL_SYNC1, &pmuF->iobound_doorbell);
drivers/scsi/arm/eesox.c
312
writel(*(u16 *)buf << 16, reg_dmadata);
drivers/scsi/arm/eesox.c
326
writel(l1 << 16, reg_dmadata);
drivers/scsi/arm/eesox.c
327
writel(l1, reg_dmadata);
drivers/scsi/arm/eesox.c
328
writel(l2 << 16, reg_dmadata);
drivers/scsi/arm/eesox.c
329
writel(l2, reg_dmadata);
drivers/scsi/arm/eesox.c
340
writel(l1 << 16, reg_dmadata);
drivers/scsi/arm/eesox.c
341
writel(l1, reg_dmadata);
drivers/scsi/arm/eesox.c
347
writel(*(u16 *)buf << 16, reg_dmadata);
drivers/scsi/bfa/bfa.h
54
writel((__bfa)->iocfc.req_cq_pi[__reqq], \
drivers/scsi/bfa/bfa_core.c
811
writel(qintr, bfa->iocfc.bfa_regs.intr_status);
drivers/scsi/bfa/bfa_core.c
863
writel(umsk, bfa->iocfc.bfa_regs.intr_status);
drivers/scsi/bfa/bfa_core.c
864
writel(~umsk, bfa->iocfc.bfa_regs.intr_mask);
drivers/scsi/bfa/bfa_core.c
879
writel(-1L, bfa->iocfc.bfa_regs.intr_mask);
drivers/scsi/bfa/bfa_core.c
939
writel(curr_value, bfa->ioc.ioc_regs.ll_halt);
drivers/scsi/bfa/bfa_core.c
950
writel(curr_value,
drivers/scsi/bfa/bfa_core.c
954
writel(intr, bfa->iocfc.bfa_regs.intr_status);
drivers/scsi/bfa/bfa_hw_cb.c
34
writel(__HFN_INT_CPE_Q0 << CPE_Q_NUM(bfa_ioc_pcifn(&bfa->ioc), reqq),
drivers/scsi/bfa/bfa_hw_cb.c
48
writel(__HFN_INT_RME_Q0 << RME_Q_NUM(bfa_ioc_pcifn(&bfa->ioc), rspq),
drivers/scsi/bfa/bfa_hw_cb.c
55
writel(ci, bfa->iocfc.bfa_regs.rme_q_ci[rspq]);
drivers/scsi/bfa/bfa_hw_cb.c
65
writel(ci, bfa->iocfc.bfa_regs.rme_q_ci[rspq]);
drivers/scsi/bfa/bfa_hw_ct.c
57
writel(r32, bfa->iocfc.bfa_regs.cpe_q_ctrl[reqq]);
drivers/scsi/bfa/bfa_hw_ct.c
72
writel(r32, bfa->iocfc.bfa_regs.rme_q_ctrl[rspq]);
drivers/scsi/bfa/bfa_hw_ct.c
75
writel(ci, bfa->iocfc.bfa_regs.rme_q_ci[rspq]);
drivers/scsi/bfa/bfa_hw_ct.c
87
writel(ci, bfa->iocfc.bfa_regs.rme_q_ci[rspq]);
drivers/scsi/bfa/bfa_ioc.c
1081
writel(1, ioc->ioc_regs.ioc_sem_reg);
drivers/scsi/bfa/bfa_ioc.c
1152
writel(1, ioc->ioc_regs.ioc_sem_reg);
drivers/scsi/bfa/bfa_ioc.c
1241
writel(1, ioc->ioc_regs.ioc_sem_reg);
drivers/scsi/bfa/bfa_ioc.c
1247
writel(1, ioc->ioc_regs.ioc_sem_reg);
drivers/scsi/bfa/bfa_ioc.c
1385
writel(pss_ctl, ioc->ioc_regs.pss_ctl_reg);
drivers/scsi/bfa/bfa_ioc.c
1404
writel(pss_ctl, ioc->ioc_regs.pss_ctl_reg);
drivers/scsi/bfa/bfa_ioc.c
1418
writel(pss_ctl, ioc->ioc_regs.pss_ctl_reg);
drivers/scsi/bfa/bfa_ioc.c
1432
writel(pss_ctl, ioc->ioc_regs.pss_ctl_reg);
drivers/scsi/bfa/bfa_ioc.c
1447
writel(pgnum, ioc->ioc_regs.host_page_num_fn);
drivers/scsi/bfa/bfa_ioc.c
1671
writel(pgnum, ioc->ioc_regs.host_page_num_fn);
drivers/scsi/bfa/bfa_ioc.c
1687
writel(1, ioc->ioc_regs.lpu_mbox_cmd);
drivers/scsi/bfa/bfa_ioc.c
1779
writel(cpu_to_le32(msgp[i]),
drivers/scsi/bfa/bfa_ioc.c
1783
writel(0, ioc->ioc_regs.hfn_mbox + i * sizeof(u32));
drivers/scsi/bfa/bfa_ioc.c
1788
writel(1, ioc->ioc_regs.hfn_mbox_cmd);
drivers/scsi/bfa/bfa_ioc.c
1891
writel(pgnum, ioc->ioc_regs.host_page_num_fn);
drivers/scsi/bfa/bfa_ioc.c
1928
writel(pgnum, ioc->ioc_regs.host_page_num_fn);
drivers/scsi/bfa/bfa_ioc.c
1932
writel(PSS_SMEM_PGNUM(ioc->ioc_regs.smem_pg0, 0),
drivers/scsi/bfa/bfa_ioc.c
2060
writel(pgnum, ioc->ioc_regs.host_page_num_fn);
drivers/scsi/bfa/bfa_ioc.c
2075
writel(pgnum, ioc->ioc_regs.host_page_num_fn);
drivers/scsi/bfa/bfa_ioc.c
2078
writel(PSS_SMEM_PGNUM(ioc->ioc_regs.smem_pg0, 0),
drivers/scsi/bfa/bfa_ioc.c
2084
writel(1, ioc->ioc_regs.ioc_init_sem_reg);
drivers/scsi/bfa/bfa_ioc.c
2117
writel(pgnum, ioc->ioc_regs.host_page_num_fn);
drivers/scsi/bfa/bfa_ioc.c
2131
writel(pgnum, ioc->ioc_regs.host_page_num_fn);
drivers/scsi/bfa/bfa_ioc.c
2134
writel(PSS_SMEM_PGNUM(ioc->ioc_regs.smem_pg0, 0),
drivers/scsi/bfa/bfa_ioc.c
2141
writel(1, ioc->ioc_regs.ioc_init_sem_reg);
drivers/scsi/bfa/bfa_ioc.c
2201
writel(1, ioc->ioc_regs.ioc_init_sem_reg);
drivers/scsi/bfa/bfa_ioc.c
2287
writel(1, ioc->ioc_regs.lpu_mbox_cmd);
drivers/scsi/bfa/bfa_ioc.c
4743
writel(pgnum, ioc->ioc_regs.host_page_num_fn);
drivers/scsi/bfa/bfa_ioc.c
6709
writel(cmd.i, (pci_bar + FLI_CMD_REG));
drivers/scsi/bfa/bfa_ioc.c
6719
writel(addr.i, (pci_bar + FLI_ADDR_REG));
drivers/scsi/bfa/bfa_ioc.c
6950
writel(0, (bar + FLASH_SEM_LOCK_REG));
drivers/scsi/bfa/bfa_ioc.c
718
writel(1, iocpf->ioc->ioc_regs.ioc_init_sem_reg);
drivers/scsi/bfa/bfa_ioc.c
725
writel(1, iocpf->ioc->ioc_regs.ioc_init_sem_reg);
drivers/scsi/bfa/bfa_ioc.c
733
writel(pgnum, iocpf->ioc->ioc_regs.host_page_num_fn);
drivers/scsi/bfa/bfa_ioc.c
753
writel(1, iocpf->ioc->ioc_regs.ioc_init_sem_reg);
drivers/scsi/bfa/bfa_ioc.c
777
writel(1, ioc->ioc_regs.ioc_sem_reg);
drivers/scsi/bfa/bfa_ioc.c
781
writel(1, ioc->ioc_regs.ioc_sem_reg);
drivers/scsi/bfa/bfa_ioc.c
879
writel(1, ioc->ioc_regs.ioc_sem_reg);
drivers/scsi/bfa/bfa_ioc.c
923
writel(1, ioc->ioc_regs.ioc_sem_reg);
drivers/scsi/bfa/bfa_ioc.c
931
writel(1, ioc->ioc_regs.ioc_sem_reg);
drivers/scsi/bfa/bfa_ioc.c
965
writel(1, ioc->ioc_regs.ioc_sem_reg);
drivers/scsi/bfa/bfa_ioc.c
974
writel(1, ioc->ioc_regs.ioc_sem_reg);
drivers/scsi/bfa/bfa_ioc.c
982
writel(1, ioc->ioc_regs.ioc_sem_reg);
drivers/scsi/bfa/bfa_ioc.h
224
writel(swab32((_val)), ((_raddr) + (_off)))
drivers/scsi/bfa/bfa_ioc_cb.c
114
writel(~0U, ioc->ioc_regs.err_set);
drivers/scsi/bfa/bfa_ioc_cb.c
227
writel(BFI_IOC_UNINIT, ioc->ioc_regs.ioc_fwstate);
drivers/scsi/bfa/bfa_ioc_cb.c
228
writel(BFI_IOC_UNINIT, ioc->ioc_regs.alt_ioc_fwstate);
drivers/scsi/bfa/bfa_ioc_cb.c
248
writel(1, ioc->ioc_regs.ioc_sem_reg);
drivers/scsi/bfa/bfa_ioc_cb.c
260
writel((r32 | join_pos), ioc->ioc_regs.ioc_fwstate);
drivers/scsi/bfa/bfa_ioc_cb.c
269
writel((r32 & ~join_pos), ioc->ioc_regs.ioc_fwstate);
drivers/scsi/bfa/bfa_ioc_cb.c
278
writel((fwstate | (r32 & BFA_IOC_CB_JOIN_MASK)),
drivers/scsi/bfa/bfa_ioc_cb.c
295
writel((fwstate | (r32 & BFA_IOC_CB_JOIN_MASK)),
drivers/scsi/bfa/bfa_ioc_cb.c
371
writel((BFI_IOC_UNINIT | join_bits), (rb + BFA_IOC0_STATE_REG));
drivers/scsi/bfa/bfa_ioc_cb.c
374
writel((BFI_IOC_UNINIT | join_bits), (rb + BFA_IOC1_STATE_REG));
drivers/scsi/bfa/bfa_ioc_cb.c
375
writel(0xffffffffU, (rb + HOSTFN0_INT_MSK));
drivers/scsi/bfa/bfa_ioc_cb.c
376
writel(0xffffffffU, (rb + HOSTFN1_INT_MSK));
drivers/scsi/bfa/bfa_ioc_cb.c
377
writel(0xffffffffU, (rb + HOSTFN0_INT_STATUS));
drivers/scsi/bfa/bfa_ioc_cb.c
378
writel(0xffffffffU, (rb + HOSTFN1_INT_STATUS));
drivers/scsi/bfa/bfa_ioc_cb.c
379
writel(0xffffffffU, (rb + HOSTFN0_INT_MSK));
drivers/scsi/bfa/bfa_ioc_cb.c
380
writel(0xffffffffU, (rb + HOSTFN1_INT_MSK));
drivers/scsi/bfa/bfa_ioc_cb.c
381
writel(__APP_PLL_SCLK_LOGIC_SOFT_RESET, rb + APP_PLL_SCLK_CTL_REG);
drivers/scsi/bfa/bfa_ioc_cb.c
382
writel(__APP_PLL_SCLK_BYPASS | __APP_PLL_SCLK_LOGIC_SOFT_RESET,
drivers/scsi/bfa/bfa_ioc_cb.c
384
writel(__APP_PLL_LCLK_LOGIC_SOFT_RESET, rb + APP_PLL_LCLK_CTL_REG);
drivers/scsi/bfa/bfa_ioc_cb.c
385
writel(__APP_PLL_LCLK_BYPASS | __APP_PLL_LCLK_LOGIC_SOFT_RESET,
drivers/scsi/bfa/bfa_ioc_cb.c
388
writel(__APP_PLL_SCLK_LOGIC_SOFT_RESET, rb + APP_PLL_SCLK_CTL_REG);
drivers/scsi/bfa/bfa_ioc_cb.c
389
writel(__APP_PLL_LCLK_LOGIC_SOFT_RESET, rb + APP_PLL_LCLK_CTL_REG);
drivers/scsi/bfa/bfa_ioc_cb.c
390
writel(pll_sclk | __APP_PLL_SCLK_LOGIC_SOFT_RESET,
drivers/scsi/bfa/bfa_ioc_cb.c
392
writel(pll_fclk | __APP_PLL_LCLK_LOGIC_SOFT_RESET,
drivers/scsi/bfa/bfa_ioc_cb.c
395
writel(0xffffffffU, (rb + HOSTFN0_INT_STATUS));
drivers/scsi/bfa/bfa_ioc_cb.c
396
writel(0xffffffffU, (rb + HOSTFN1_INT_STATUS));
drivers/scsi/bfa/bfa_ioc_cb.c
397
writel(pll_sclk, (rb + APP_PLL_SCLK_CTL_REG));
drivers/scsi/bfa/bfa_ioc_cb.c
398
writel(pll_fclk, (rb + APP_PLL_LCLK_CTL_REG));
drivers/scsi/bfa/bfa_ioc_ct.c
117
writel(usecnt, ioc->ioc_regs.ioc_usage_reg);
drivers/scsi/bfa/bfa_ioc_ct.c
121
writel(1, ioc->ioc_regs.ioc_usage_sem_reg);
drivers/scsi/bfa/bfa_ioc_ct.c
131
writel(__FW_INIT_HALT_P, ioc->ioc_regs.ll_halt);
drivers/scsi/bfa/bfa_ioc_ct.c
132
writel(__FW_INIT_HALT_P, ioc->ioc_regs.alt_ll_halt);
drivers/scsi/bfa/bfa_ioc_ct.c
137
writel(~0U, ioc->ioc_regs.err_set);
drivers/scsi/bfa/bfa_ioc_ct.c
364
writel(r32, rb + FNC_PERS_REG);
drivers/scsi/bfa/bfa_ioc_ct.c
374
writel(1, ioc->ioc_regs.lpu_read_stat);
drivers/scsi/bfa/bfa_ioc_ct.c
389
writel(0, ioc->ioc_regs.ioc_usage_reg);
drivers/scsi/bfa/bfa_ioc_ct.c
391
writel(1, ioc->ioc_regs.ioc_usage_sem_reg);
drivers/scsi/bfa/bfa_ioc_ct.c
393
writel(0, ioc->ioc_regs.ioc_fail_sync);
drivers/scsi/bfa/bfa_ioc_ct.c
400
writel(1, ioc->ioc_regs.ioc_sem_reg);
drivers/scsi/bfa/bfa_ioc_ct.c
417
writel(0, ioc->ioc_regs.ioc_fail_sync);
drivers/scsi/bfa/bfa_ioc_ct.c
418
writel(1, ioc->ioc_regs.ioc_usage_reg);
drivers/scsi/bfa/bfa_ioc_ct.c
419
writel(BFI_IOC_UNINIT, ioc->ioc_regs.ioc_fwstate);
drivers/scsi/bfa/bfa_ioc_ct.c
420
writel(BFI_IOC_UNINIT, ioc->ioc_regs.alt_ioc_fwstate);
drivers/scsi/bfa/bfa_ioc_ct.c
436
writel((r32 | sync_pos), ioc->ioc_regs.ioc_fail_sync);
drivers/scsi/bfa/bfa_ioc_ct.c
446
writel((r32 & ~sync_msk), ioc->ioc_regs.ioc_fail_sync);
drivers/scsi/bfa/bfa_ioc_ct.c
454
writel((r32 | bfa_ioc_ct_sync_pos(ioc)),
drivers/scsi/bfa/bfa_ioc_ct.c
481
writel(bfa_ioc_ct_clear_sync_ackd(r32),
drivers/scsi/bfa/bfa_ioc_ct.c
483
writel(BFI_IOC_FAIL, ioc->ioc_regs.ioc_fwstate);
drivers/scsi/bfa/bfa_ioc_ct.c
484
writel(BFI_IOC_FAIL, ioc->ioc_regs.alt_ioc_fwstate);
drivers/scsi/bfa/bfa_ioc_ct.c
494
writel((r32 | sync_ackd), ioc->ioc_regs.ioc_fail_sync);
drivers/scsi/bfa/bfa_ioc_ct.c
569
writel(r32 & __MSIX_VT_OFST_,
drivers/scsi/bfa/bfa_ioc_ct.c
574
writel(__MSIX_VT_NUMVT_(HOSTFN_MSIX_DEFAULT - 1) |
drivers/scsi/bfa/bfa_ioc_ct.c
577
writel(HOSTFN_MSIX_DEFAULT * bfa_ioc_pcifn(ioc),
drivers/scsi/bfa/bfa_ioc_ct.c
597
writel(0, (rb + OP_MODE));
drivers/scsi/bfa/bfa_ioc_ct.c
598
writel(__APP_EMS_CMLCKSEL | __APP_EMS_REFCKBUFEN2 |
drivers/scsi/bfa/bfa_ioc_ct.c
601
writel(__GLOBAL_FCOE_MODE, (rb + OP_MODE));
drivers/scsi/bfa/bfa_ioc_ct.c
602
writel(__APP_EMS_REFCKBUFEN1, (rb + ETH_MAC_SER_REG));
drivers/scsi/bfa/bfa_ioc_ct.c
604
writel(BFI_IOC_UNINIT, (rb + BFA_IOC0_STATE_REG));
drivers/scsi/bfa/bfa_ioc_ct.c
605
writel(BFI_IOC_UNINIT, (rb + BFA_IOC1_STATE_REG));
drivers/scsi/bfa/bfa_ioc_ct.c
606
writel(0xffffffffU, (rb + HOSTFN0_INT_MSK));
drivers/scsi/bfa/bfa_ioc_ct.c
607
writel(0xffffffffU, (rb + HOSTFN1_INT_MSK));
drivers/scsi/bfa/bfa_ioc_ct.c
608
writel(0xffffffffU, (rb + HOSTFN0_INT_STATUS));
drivers/scsi/bfa/bfa_ioc_ct.c
609
writel(0xffffffffU, (rb + HOSTFN1_INT_STATUS));
drivers/scsi/bfa/bfa_ioc_ct.c
610
writel(0xffffffffU, (rb + HOSTFN0_INT_MSK));
drivers/scsi/bfa/bfa_ioc_ct.c
611
writel(0xffffffffU, (rb + HOSTFN1_INT_MSK));
drivers/scsi/bfa/bfa_ioc_ct.c
612
writel(pll_sclk | __APP_PLL_SCLK_LOGIC_SOFT_RESET,
drivers/scsi/bfa/bfa_ioc_ct.c
614
writel(pll_fclk | __APP_PLL_LCLK_LOGIC_SOFT_RESET,
drivers/scsi/bfa/bfa_ioc_ct.c
616
writel(pll_sclk | __APP_PLL_SCLK_LOGIC_SOFT_RESET |
drivers/scsi/bfa/bfa_ioc_ct.c
618
writel(pll_fclk | __APP_PLL_LCLK_LOGIC_SOFT_RESET |
drivers/scsi/bfa/bfa_ioc_ct.c
622
writel(0xffffffffU, (rb + HOSTFN0_INT_STATUS));
drivers/scsi/bfa/bfa_ioc_ct.c
623
writel(0xffffffffU, (rb + HOSTFN1_INT_STATUS));
drivers/scsi/bfa/bfa_ioc_ct.c
624
writel(pll_sclk | __APP_PLL_SCLK_ENABLE, rb + APP_PLL_SCLK_CTL_REG);
drivers/scsi/bfa/bfa_ioc_ct.c
625
writel(pll_fclk | __APP_PLL_LCLK_ENABLE, rb + APP_PLL_LCLK_CTL_REG);
drivers/scsi/bfa/bfa_ioc_ct.c
628
writel(__PMM_1T_RESET_P, (rb + PMM_1T_RESET_REG_P0));
drivers/scsi/bfa/bfa_ioc_ct.c
629
writel(__PMM_1T_RESET_P, (rb + PMM_1T_RESET_REG_P1));
drivers/scsi/bfa/bfa_ioc_ct.c
633
writel(r32, (rb + PSS_CTL_REG));
drivers/scsi/bfa/bfa_ioc_ct.c
636
writel(0, (rb + PMM_1T_RESET_REG_P0));
drivers/scsi/bfa/bfa_ioc_ct.c
637
writel(0, (rb + PMM_1T_RESET_REG_P1));
drivers/scsi/bfa/bfa_ioc_ct.c
640
writel(__EDRAM_BISTR_START, (rb + MBIST_CTL_REG));
drivers/scsi/bfa/bfa_ioc_ct.c
643
writel(0, (rb + MBIST_CTL_REG));
drivers/scsi/bfa/bfa_ioc_ct.c
659
writel(r32, (rb + CT2_APP_PLL_SCLK_CTL_REG));
drivers/scsi/bfa/bfa_ioc_ct.c
66
writel(1, ioc->ioc_regs.ioc_usage_reg);
drivers/scsi/bfa/bfa_ioc_ct.c
667
writel(r32, (rb + CT2_APP_PLL_SCLK_CTL_REG));
drivers/scsi/bfa/bfa_ioc_ct.c
673
writel(r32 | __ETH_CLK_ENABLE_PORT0, (rb + CT2_CHIP_MISC_PRG));
drivers/scsi/bfa/bfa_ioc_ct.c
676
writel(r32 | __ETH_CLK_ENABLE_PORT1, (rb + CT2_PCIE_MISC_REG));
drivers/scsi/bfa/bfa_ioc_ct.c
68
writel(1, ioc->ioc_regs.ioc_usage_sem_reg);
drivers/scsi/bfa/bfa_ioc_ct.c
684
writel(r32 | 0x1061731b, (rb + CT2_APP_PLL_SCLK_CTL_REG));
drivers/scsi/bfa/bfa_ioc_ct.c
69
writel(0, ioc->ioc_regs.ioc_fail_sync);
drivers/scsi/bfa/bfa_ioc_ct.c
704
writel(r32, (rb + CT2_APP_PLL_LCLK_CTL_REG));
drivers/scsi/bfa/bfa_ioc_ct.c
710
writel(r32, (rb + CT2_CHIP_MISC_PRG));
drivers/scsi/bfa/bfa_ioc_ct.c
716
writel(r32, (rb + CT2_APP_PLL_LCLK_CTL_REG));
drivers/scsi/bfa/bfa_ioc_ct.c
724
writel(r32, (rb + CT2_APP_PLL_LCLK_CTL_REG));
drivers/scsi/bfa/bfa_ioc_ct.c
739
writel(r32, (rb + PSS_CTL_REG));
drivers/scsi/bfa/bfa_ioc_ct.c
742
writel(__EDRAM_BISTR_START, (rb + CT2_MBIST_CTL_REG));
drivers/scsi/bfa/bfa_ioc_ct.c
744
writel(0, (rb + CT2_MBIST_CTL_REG));
drivers/scsi/bfa/bfa_ioc_ct.c
751
writel((__CSI_MAC_RESET | __CSI_MAC_AHB_RESET),
drivers/scsi/bfa/bfa_ioc_ct.c
753
writel((__CSI_MAC_RESET | __CSI_MAC_AHB_RESET),
drivers/scsi/bfa/bfa_ioc_ct.c
763
writel(r32 & ~1, (rb + PSS_GPIO_OUT_REG));
drivers/scsi/bfa/bfa_ioc_ct.c
765
writel(r32 | 1, (rb + PSS_GPIO_OE_REG));
drivers/scsi/bfa/bfa_ioc_ct.c
791
writel(__HALT_NFC_CONTROLLER, rb + CT2_NFC_CSR_SET_REG);
drivers/scsi/bfa/bfa_ioc_ct.c
806
writel(__HALT_NFC_CONTROLLER, rb + CT2_NFC_CSR_CLR_REG);
drivers/scsi/bfa/bfa_ioc_ct.c
828
writel(r32 & ~__APP_PLL_SCLK_LOGIC_SOFT_RESET,
drivers/scsi/bfa/bfa_ioc_ct.c
832
writel(r32 & ~__APP_PLL_LCLK_LOGIC_SOFT_RESET,
drivers/scsi/bfa/bfa_ioc_ct.c
844
writel(r32, (rb + PSS_CTL_REG));
drivers/scsi/bfa/bfa_ioc_ct.c
846
writel(__RESET_AND_START_SCLK_LCLK_PLLS, rb + CT2_CSI_FW_CTL_SET_REG);
drivers/scsi/bfa/bfa_ioc_ct.c
88
writel(1, ioc->ioc_regs.ioc_usage_sem_reg);
drivers/scsi/bfa/bfa_ioc_ct.c
933
writel((r32 & 0xfbffffff), (rb + CT2_CHIP_MISC_PRG));
drivers/scsi/bfa/bfa_ioc_ct.c
940
writel(1, (rb + CT2_LPU0_HOSTFN_MBOX0_MSK));
drivers/scsi/bfa/bfa_ioc_ct.c
941
writel(1, (rb + CT2_LPU1_HOSTFN_MBOX0_MSK));
drivers/scsi/bfa/bfa_ioc_ct.c
948
writel(1, (rb + CT2_LPU0_HOSTFN_CMD_STAT));
drivers/scsi/bfa/bfa_ioc_ct.c
953
writel(1, (rb + CT2_LPU1_HOSTFN_CMD_STAT));
drivers/scsi/bfa/bfa_ioc_ct.c
960
writel(BFI_IOC_UNINIT, (rb + CT2_BFA_IOC0_STATE_REG));
drivers/scsi/bfa/bfa_ioc_ct.c
961
writel(BFI_IOC_UNINIT, (rb + CT2_BFA_IOC1_STATE_REG));
drivers/scsi/bfa/bfa_ioc_ct.c
97
writel(usecnt, ioc->ioc_regs.ioc_usage_reg);
drivers/scsi/bfa/bfa_ioc_ct.c
970
writel(fwstate, ioc->ioc_regs.ioc_fwstate);
drivers/scsi/bfa/bfa_ioc_ct.c
983
writel(fwstate, ioc->ioc_regs.alt_ioc_fwstate);
drivers/scsi/bfa/bfa_ioc_ct.c
99
writel(1, ioc->ioc_regs.ioc_usage_sem_reg);
drivers/scsi/bfa/bfad_debugfs.c
347
writel(val, reg_addr);
drivers/scsi/bnx2fc/bnx2fc_hwi.c
1439
writel(cpu_to_le32(msg), tgt->ctx_base);
drivers/scsi/bnx2fc/bnx2fc_hwi.c
966
writel(cpu_to_le32(msg), tgt->ctx_base);
drivers/scsi/bnx2i/bnx2i.h
131
writel(val, __hba->regview + offset)
drivers/scsi/bnx2i/bnx2i_hwi.c
220
writel(cpu_to_le32(msg), conn->ep->qp.ctx_base);
drivers/scsi/csiostor/csio_defs.h
61
writel(val, addr);
drivers/scsi/csiostor/csio_defs.h
62
writel(val >> 32, addr + 4);
drivers/scsi/csiostor/csio_hw.h
570
#define csio_wr_reg32(_h, _v, _r) writel((_v), \
drivers/scsi/elx/libefc_sli/sli4.c
1079
writel(val, q->db_regaddr);
drivers/scsi/elx/libefc_sli/sli4.c
1102
writel(val, q->db_regaddr);
drivers/scsi/elx/libefc_sli/sli4.c
1111
writel(val, q->db_regaddr);
drivers/scsi/elx/libefc_sli/sli4.c
1140
writel(val, q->db_regaddr);
drivers/scsi/elx/libefc_sli/sli4.c
1160
writel(val, q->db_regaddr);
drivers/scsi/elx/libefc_sli/sli4.c
1189
writel(val, q->db_regaddr);
drivers/scsi/elx/libefc_sli/sli4.c
2890
writel(val, (sli4->reg[0] + SLI4_BMBX_REG));
drivers/scsi/elx/libefc_sli/sli4.c
2897
writel(val, (sli4->reg[0] + SLI4_BMBX_REG));
drivers/scsi/elx/libefc_sli/sli4.c
4063
writel(val, (sli4->reg[0] + SLI4_PORT_CTRL_REG));
drivers/scsi/elx/libefc_sli/sli4.c
4761
writel(SLI4_PHYDEV_CTRL_FRST, (sli4->reg[0] + SLI4_PHYDEV_CTRL_REG));
drivers/scsi/elx/libefc_sli/sli4.c
4959
writel(val, (sli4->reg[0] + SLI4_PORT_CTRL_REG));
drivers/scsi/elx/libefc_sli/sli4.c
4965
writel(val, (sli4->reg[0] + SLI4_PHYDEV_CTRL_REG));
drivers/scsi/esas2r/esas2r.h
145
writel(data, (void __iomem *)(a->regs + (reg) + MW_REG_OFFSET_HWREG))
drivers/scsi/fnic/vnic_dev.h
66
writel(val & 0xffffffff, reg);
drivers/scsi/fnic/vnic_dev.h
67
writel(val >> 32, reg + 0x4UL);
drivers/scsi/hisi_sas/hisi_sas_v1_hw.c
424
writel(val, regs);
drivers/scsi/hisi_sas/hisi_sas_v1_hw.c
432
writel(val, regs);
drivers/scsi/hisi_sas/hisi_sas_v2_hw.c
747
writel(val, regs);
drivers/scsi/hisi_sas/hisi_sas_v2_hw.c
755
writel(val, regs);
drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
622
writel(val, regs);
drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
630
writel(val, regs);
drivers/scsi/hpsa.c
1161
writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
drivers/scsi/hpsa.c
1165
writel(c->busaddr, h->vaddr + IOACCEL2_INBOUND_POSTQ_32);
drivers/scsi/hpsa.c
1169
writel(c->busaddr, h->vaddr + IOACCEL2_INBOUND_POSTQ_32);
drivers/scsi/hpsa.c
7133
writel(le32_to_cpu(paddr32), vaddr + SA5_REQUEST_PORT_OFFSET);
drivers/scsi/hpsa.c
7178
writel(use_doorbell, vaddr + SA5_DOORBELL);
drivers/scsi/hpsa.c
7746
writel(driver_support, &(h->cfgtable->driver_support));
drivers/scsi/hpsa.c
7760
writel(dma_prefetch, h->vaddr + I2O_DMA1_CFG);
drivers/scsi/hpsa.c
7821
writel(CFGTBL_Trans_Simple, &(h->cfgtable->HostWrite.TransportRequest));
drivers/scsi/hpsa.c
7822
writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi);
drivers/scsi/hpsa.c
7823
writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
drivers/scsi/hpsa.c
7983
writel(SA5_INTR_OFF, vaddr + SA5_REPLY_INTR_MASK_OFFSET);
drivers/scsi/hpsa.c
8272
writel(DOORBELL_GENERATE_CHKPT, h->vaddr + SA5_DOORBELL);
drivers/scsi/hpsa.c
8421
writel(h->events, &(h->cfgtable->clear_event_notify));
drivers/scsi/hpsa.c
8423
writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL);
drivers/scsi/hpsa.c
8429
writel(h->events, &(h->cfgtable->clear_event_notify));
drivers/scsi/hpsa.c
8430
writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL);
drivers/scsi/hpsa.c
9221
writel(bft[i], &h->transtable->BlockFetch[i]);
drivers/scsi/hpsa.c
9224
writel(h->max_commands, &h->transtable->RepQSize);
drivers/scsi/hpsa.c
9225
writel(h->nreply_queues, &h->transtable->RepQCount);
drivers/scsi/hpsa.c
9226
writel(0, &h->transtable->RepQCtrAddrLow32);
drivers/scsi/hpsa.c
9227
writel(0, &h->transtable->RepQCtrAddrHigh32);
drivers/scsi/hpsa.c
9230
writel(0, &h->transtable->RepQAddr[i].upper);
drivers/scsi/hpsa.c
9231
writel(h->reply_queue[i].busaddr,
drivers/scsi/hpsa.c
9235
writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi);
drivers/scsi/hpsa.c
9236
writel(transMethod, &(h->cfgtable->HostWrite.TransportRequest));
drivers/scsi/hpsa.c
9242
writel(10, &h->cfgtable->HostWrite.CoalIntDelay);
drivers/scsi/hpsa.c
9243
writel(4, &h->cfgtable->HostWrite.CoalIntCount);
drivers/scsi/hpsa.c
9247
writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
drivers/scsi/hpsa.c
9270
writel(i, h->vaddr + IOACCEL_MODE1_REPLY_QUEUE_INDEX);
drivers/scsi/hpsa.c
9325
writel(bft2[i], &h->ioaccel2_bft2_regs[i]);
drivers/scsi/hpsa.c
9327
writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
drivers/scsi/hpsa.h
423
writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
drivers/scsi/hpsa.h
430
writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
drivers/scsi/hpsa.h
436
writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
drivers/scsi/hpsa.h
448
writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
drivers/scsi/hpsa.h
452
writel(SA5_INTR_OFF,
drivers/scsi/hpsa.h
465
writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
drivers/scsi/hpsa.h
469
writel(SA5B_INTR_OFF,
drivers/scsi/hpsa.h
479
writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
drivers/scsi/hpsa.h
483
writel(SA5_PERF_INTR_OFF,
drivers/scsi/hpsa.h
500
writel(SA5_OUTDB_CLEAR_PERF_BIT, h->vaddr + SA5_OUTDB_CLEAR);
drivers/scsi/hpsa.h
609
writel((q << 24) | rq->current_entry, h->vaddr +
drivers/scsi/hptiop.c
105
writel(1, &p->context);
drivers/scsi/hptiop.c
121
writel(1, plx + 0x11C60);
drivers/scsi/hptiop.c
129
writel(IOPMU_OUTBOUND_INT_MSG0, &iop->outbound_intstatus);
drivers/scsi/hptiop.c
1523
writel(int_mask |
drivers/scsi/hptiop.c
1531
writel(0, &hba->u.mv.regs->outbound_intmask);
drivers/scsi/hptiop.c
1537
writel(0, &(hba->u.mvfrey.mu->f0_doorbell_enable));
drivers/scsi/hptiop.c
1539
writel(0, &(hba->u.mvfrey.mu->isr_enable));
drivers/scsi/hptiop.c
1541
writel(0, &(hba->u.mvfrey.mu->pcie_f0_int_enable));
drivers/scsi/hptiop.c
155
writel(outbound_tail, &mu->outbound_tail);
drivers/scsi/hptiop.c
170
writel(head, &hba->u.mv.mu->inbound_head);
drivers/scsi/hptiop.c
171
writel(MVIOP_MU_INBOUND_INT_POSTQUEUE,
drivers/scsi/hptiop.c
209
writel(~status, &hba->u.mv.regs->outbound_doorbell);
drivers/scsi/hptiop.c
259
writel(0, &(hba->u.mvfrey.mu->pcie_f0_int_enable));
drivers/scsi/hptiop.c
263
writel(status, &(hba->u.mvfrey.mu->f0_doorbell));
drivers/scsi/hptiop.c
274
writel(status, &(hba->u.mvfrey.mu->isr_cause));
drivers/scsi/hptiop.c
293
writel(0x1010, &(hba->u.mvfrey.mu->pcie_f0_int_enable));
drivers/scsi/hptiop.c
304
writel(readl(&req->flags) | IOP_REQUEST_FLAG_SYNC_REQUEST, &req->flags);
drivers/scsi/hptiop.c
305
writel(0, &req->context);
drivers/scsi/hptiop.c
306
writel((unsigned long)req - (unsigned long)hba->u.itl.iop,
drivers/scsi/hptiop.c
362
writel(msg, &hba->u.itl.iop->inbound_msgaddr0);
drivers/scsi/hptiop.c
368
writel(msg, &hba->u.mv.mu->inbound_msg);
drivers/scsi/hptiop.c
369
writel(MVIOP_MU_INBOUND_INT_MSG, &hba->u.mv.regs->inbound_doorbell);
drivers/scsi/hptiop.c
375
writel(msg, &(hba->u.mvfrey.mu->f0_to_cpu_msg_a));
drivers/scsi/hptiop.c
413
writel(0, &req->header.flags);
drivers/scsi/hptiop.c
414
writel(IOP_REQUEST_TYPE_GET_CONFIG, &req->header.type);
drivers/scsi/hptiop.c
415
writel(sizeof(struct hpt_iop_request_get_config), &req->header.size);
drivers/scsi/hptiop.c
416
writel(IOP_RESULT_PENDING, &req->header.result);
drivers/scsi/hptiop.c
424
writel(req32, &hba->u.itl.iop->outbound_queue);
drivers/scsi/hptiop.c
490
writel(0, &req->header.flags);
drivers/scsi/hptiop.c
491
writel(IOP_REQUEST_TYPE_SET_CONFIG, &req->header.type);
drivers/scsi/hptiop.c
492
writel(sizeof(struct hpt_iop_request_set_config), &req->header.size);
drivers/scsi/hptiop.c
493
writel(IOP_RESULT_PENDING, &req->header.result);
drivers/scsi/hptiop.c
500
writel(req32, &hba->u.itl.iop->outbound_queue);
drivers/scsi/hptiop.c
551
writel(~(IOPMU_OUTBOUND_INT_POSTQUEUE | IOPMU_OUTBOUND_INT_MSG0),
drivers/scsi/hptiop.c
557
writel(MVIOP_MU_OUTBOUND_INT_POSTQUEUE | MVIOP_MU_OUTBOUND_INT_MSG,
drivers/scsi/hptiop.c
563
writel(CPU_TO_F0_DRBL_MSG_BIT, &(hba->u.mvfrey.mu->f0_doorbell_enable));
drivers/scsi/hptiop.c
564
writel(0x1, &(hba->u.mvfrey.mu->isr_enable));
drivers/scsi/hptiop.c
565
writel(0x1010, &(hba->u.mvfrey.mu->pcie_f0_int_enable));
drivers/scsi/hptiop.c
59
writel(req, &hba->u.itl.iop->outbound_queue);
drivers/scsi/hptiop.c
830
writel(tag, &hba->u.itl.iop->outbound_queue);
drivers/scsi/hptiop.c
893
writel(_req->req_shifted_phy | size_bits,
drivers/scsi/hptiop.c
896
writel(_req->req_shifted_phy | IOPMU_QUEUE_ADDR_HOST_BIT,
drivers/scsi/hptiop.c
950
writel(hba->u.mvfrey.inlist_wptr,
drivers/scsi/hptiop.c
975
writel(cpu_to_le32(hba->u.mvfrey.inlist_phy & 0xffffffff),
drivers/scsi/hptiop.c
977
writel(cpu_to_le32((hba->u.mvfrey.inlist_phy >> 16) >> 16),
drivers/scsi/hptiop.c
980
writel(cpu_to_le32(hba->u.mvfrey.outlist_phy & 0xffffffff),
drivers/scsi/hptiop.c
982
writel(cpu_to_le32((hba->u.mvfrey.outlist_phy >> 16) >> 16),
drivers/scsi/hptiop.c
985
writel(cpu_to_le32(hba->u.mvfrey.outlist_cptr_phy & 0xffffffff),
drivers/scsi/hptiop.c
987
writel(cpu_to_le32((hba->u.mvfrey.outlist_cptr_phy >> 16) >> 16),
drivers/scsi/ipr.c
2767
writel(start_addr+(i*4), ioa_cfg->regs.dump_addr_reg);
drivers/scsi/ipr.c
2797
writel((IPR_UPROCI_RESET_ALERT | IPR_UPROCI_IO_DEBUG_ALERT),
drivers/scsi/ipr.c
2809
writel(IPR_PCII_IO_DEBUG_ACKNOWLEDGE,
drivers/scsi/ipr.c
2813
writel(start_addr, ioa_cfg->ioa_mailbox);
drivers/scsi/ipr.c
2816
writel(IPR_UPROCI_RESET_ALERT,
drivers/scsi/ipr.c
2835
writel(IPR_PCII_IO_DEBUG_ACKNOWLEDGE,
drivers/scsi/ipr.c
2841
writel(IPR_UPROCI_RESET_ALERT,
drivers/scsi/ipr.c
2844
writel(IPR_UPROCI_IO_DEBUG_ALERT,
drivers/scsi/ipr.c
2848
writel(IPR_PCII_IO_DEBUG_ACKNOWLEDGE,
drivers/scsi/ipr.c
5347
writel(IPR_PCII_IPL_STAGE_CHANGE, ioa_cfg->regs.clr_interrupt_reg);
drivers/scsi/ipr.c
5361
writel(IPR_PCII_IOA_TRANS_TO_OPER, ioa_cfg->regs.set_interrupt_mask_reg);
drivers/scsi/ipr.c
5372
writel(IPR_PCII_HRRQ_UPDATED, ioa_cfg->regs.clr_interrupt_reg32);
drivers/scsi/ipr.c
5528
writel(IPR_PCII_HRRQ_UPDATED,
drivers/scsi/ipr.c
742
writel(~0, ioa_cfg->regs.set_interrupt_mask_reg);
drivers/scsi/ipr.c
746
writel(~0, ioa_cfg->regs.clr_interrupt_reg);
drivers/scsi/ipr.c
747
writel(clr_ints, ioa_cfg->regs.clr_interrupt_reg32);
drivers/scsi/ipr.c
7584
writel(IPR_PCII_IPL_STAGE_CHANGE, ioa_cfg->regs.set_interrupt_mask_reg);
drivers/scsi/ipr.c
7638
writel(IPR_ENDIAN_SWAP_KEY, ioa_cfg->regs.endian_swap_reg);
drivers/scsi/ipr.c
7645
writel((IPR_PCII_ERROR_INTERRUPTS | IPR_PCII_HRRQ_UPDATED),
drivers/scsi/ipr.c
7652
writel(ioa_cfg->doorbell, ioa_cfg->regs.set_uproc_interrupt_reg32);
drivers/scsi/ipr.c
7659
writel(IPR_PCII_OPER_INTERRUPTS, ioa_cfg->regs.clr_interrupt_mask_reg32);
drivers/scsi/ipr.c
7898
writel(IPR_ENDIAN_SWAP_KEY, ioa_cfg->regs.endian_swap_reg);
drivers/scsi/ipr.c
7967
writel(IPR_UPROCI_SIS64_START_BIST,
drivers/scsi/ipr.c
8173
writel(IPR_UPROCI_RESET_ALERT, ioa_cfg->regs.set_uproc_interrupt_reg32);
drivers/scsi/ipr.c
910
writel(send_dma_addr, ioa_cfg->regs.ioarrin_reg);
drivers/scsi/ipr.c
9327
writel(IPR_PCII_IO_DEBUG_ACKNOWLEDGE, ioa_cfg->regs.clr_interrupt_mask_reg32);
drivers/scsi/ipr.c
9338
writel(IPR_PCII_IO_DEBUG_ACKNOWLEDGE, ioa_cfg->regs.sense_interrupt_reg32);
drivers/scsi/ipr.h
1924
writel(((u32) (val >> 32)), addr);
drivers/scsi/ipr.h
1925
writel(((u32) (val)), (addr + 4));
drivers/scsi/ips.c
2235
writel(0, ha->mem_ptr + IPS_REG_FLAP);
drivers/scsi/ips.c
2242
writel(1, ha->mem_ptr + IPS_REG_FLAP);
drivers/scsi/ips.c
2250
writel(0x1FF, ha->mem_ptr + IPS_REG_FLAP);
drivers/scsi/ips.c
2257
writel(0x1FE, ha->mem_ptr + IPS_REG_FLAP);
drivers/scsi/ips.c
2263
writel(0x1FD, ha->mem_ptr + IPS_REG_FLAP);
drivers/scsi/ips.c
4667
writel(Oimr, ha->mem_ptr + IPS_REG_I960_OIMR);
drivers/scsi/ips.c
4842
writel(0x1010, ha->mem_ptr + IPS_REG_CCCR);
drivers/scsi/ips.c
4849
writel(0, ha->mem_ptr + IPS_REG_NDAE);
drivers/scsi/ips.c
4905
writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR);
drivers/scsi/ips.c
4925
writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR);
drivers/scsi/ips.c
4957
writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR);
drivers/scsi/ips.c
4962
writel(Oimr, ha->mem_ptr + IPS_REG_I960_OIMR);
drivers/scsi/ips.c
5090
writel(0x80000000, ha->mem_ptr + IPS_REG_I960_IDR);
drivers/scsi/ips.c
5161
writel(phys_status_start, ha->mem_ptr + IPS_REG_SQSR);
drivers/scsi/ips.c
5162
writel(phys_status_start + IPS_STATUS_Q_SIZE,
drivers/scsi/ips.c
5164
writel(phys_status_start + IPS_STATUS_SIZE, ha->mem_ptr + IPS_REG_SQHR);
drivers/scsi/ips.c
5165
writel(phys_status_start, ha->mem_ptr + IPS_REG_SQTR);
drivers/scsi/ips.c
5220
writel(ha->adapt->hw_status_tail, ha->mem_ptr + IPS_REG_SQTR);
drivers/scsi/ips.c
5347
writel(scb->scb_busaddr, ha->mem_ptr + IPS_REG_CCSAR);
drivers/scsi/ips.c
5348
writel(IPS_BIT_START_CMD, ha->mem_ptr + IPS_REG_CCCR);
drivers/scsi/ips.c
5412
writel(scb->scb_busaddr, ha->mem_ptr + IPS_REG_I2O_INMSGQ);
drivers/scsi/ips.c
6119
writel(0, ha->mem_ptr + IPS_REG_FLAP);
drivers/scsi/ips.c
6146
writel(0, ha->mem_ptr + IPS_REG_FLAP);
drivers/scsi/ips.c
6172
writel(0, ha->mem_ptr + IPS_REG_FLAP);
drivers/scsi/ips.c
6325
writel(i + offset, ha->mem_ptr + IPS_REG_FLAP);
drivers/scsi/ips.c
6341
writel(0, ha->mem_ptr + IPS_REG_FLAP);
drivers/scsi/ips.c
6356
writel(0, ha->mem_ptr + IPS_REG_FLAP);
drivers/scsi/ips.c
6370
writel(0, ha->mem_ptr + IPS_REG_FLAP);
drivers/scsi/ips.c
6383
writel(0, ha->mem_ptr + IPS_REG_FLAP);
drivers/scsi/ips.c
6461
writel(0, ha->mem_ptr + IPS_REG_FLAP);
drivers/scsi/ips.c
6468
writel(1, ha->mem_ptr + IPS_REG_FLAP);
drivers/scsi/ips.c
6477
writel(i + offset, ha->mem_ptr + IPS_REG_FLAP);
drivers/scsi/isci/host.c
1072
writel(SMU_ISR_COMPLETION, &ihost->smu_registers->interrupt_status);
drivers/scsi/isci/host.c
1074
writel(0xFF000000, &ihost->smu_registers->interrupt_mask);
drivers/scsi/isci/host.c
1075
writel(0, &ihost->smu_registers->interrupt_mask);
drivers/scsi/isci/host.c
1133
writel(SMU_ICC_GEN_VAL(NUMBER, active) |
drivers/scsi/isci/host.c
1245
writel(SGPIO_HW_CONTROL, &ihost->scu_registers->peg0.sgpio.output_data_select[i]);
drivers/scsi/isci/host.c
1265
writel(0, &ihost->scu_registers->peg0.sgpio.interface_control);
drivers/scsi/isci/host.c
1430
writel(SMU_ICC_GEN_VAL(NUMBER, coalesce_number) |
drivers/scsi/isci/host.c
1453
writel(val, &ihost->smu_registers->clock_gating_control);
drivers/scsi/isci/host.c
1546
writel(0xFFFFFFFF, &ihost->smu_registers->soft_reset_control);
drivers/scsi/isci/host.c
1552
writel(0x00000000, &ihost->smu_registers->completion_queue_get);
drivers/scsi/isci/host.c
1555
writel(0, &ihost->scu_registers->sdma.unsolicited_frame_get_pointer);
drivers/scsi/isci/host.c
1558
writel(~SMU_INTERRUPT_STATUS_RESERVED_MASK, &ihost->smu_registers->interrupt_status);
drivers/scsi/isci/host.c
1931
writel(0x0081000f, &afe->afe_dfx_master_control0);
drivers/scsi/isci/host.c
1938
writel(0x0007FFFF, &afe->afe_pmsn_master_control2);
drivers/scsi/isci/host.c
1944
writel(0x00005A00, &afe->afe_bias_control);
drivers/scsi/isci/host.c
1946
writel(0x00005F00, &afe->afe_bias_control);
drivers/scsi/isci/host.c
1948
writel(0x00005500, &afe->afe_bias_control);
drivers/scsi/isci/host.c
1954
writel(0x80040908, &afe->afe_pll_control0);
drivers/scsi/isci/host.c
1956
writel(0x80040A08, &afe->afe_pll_control0);
drivers/scsi/isci/host.c
1958
writel(0x80000B08, &afe->afe_pll_control0);
drivers/scsi/isci/host.c
1960
writel(0x00000B08, &afe->afe_pll_control0);
drivers/scsi/isci/host.c
1962
writel(0x80000B08, &afe->afe_pll_control0);
drivers/scsi/isci/host.c
1977
writel(0x7bcc96ad, &afe->afe_pmsn_master_control0);
drivers/scsi/isci/host.c
1993
writel(0x00004512, &xcvr->afe_xcvr_control0);
drivers/scsi/isci/host.c
1996
writel(0x0050100F, &xcvr->afe_xcvr_control1);
drivers/scsi/isci/host.c
200
writel(SMU_ISR_COMPLETION, &ihost->smu_registers->interrupt_status);
drivers/scsi/isci/host.c
2000
writel(0x00030000, &xcvr->afe_tx_ssc_control);
drivers/scsi/isci/host.c
2004
writel(0x00010202, &xcvr->afe_tx_ssc_control);
drivers/scsi/isci/host.c
2010
writel(0x00014500, &xcvr->afe_xcvr_control0);
drivers/scsi/isci/host.c
2014
writel(0x00010202, &xcvr->afe_tx_ssc_control);
drivers/scsi/isci/host.c
2020
writel(0x0001C500, &xcvr->afe_xcvr_control0);
drivers/scsi/isci/host.c
2028
writel(0x000003F0, &xcvr->afe_channel_control);
drivers/scsi/isci/host.c
2030
writel(0x000003D7, &xcvr->afe_channel_control);
drivers/scsi/isci/host.c
2033
writel(0x000003D4, &xcvr->afe_channel_control);
drivers/scsi/isci/host.c
2035
writel(0x000001E7, &xcvr->afe_channel_control);
drivers/scsi/isci/host.c
2038
writel(0x000001E4, &xcvr->afe_channel_control);
drivers/scsi/isci/host.c
2040
writel(cable_length_long ? 0x000002F7 : 0x000001F7,
drivers/scsi/isci/host.c
2044
writel(cable_length_long ? 0x000002F4 : 0x000001F4,
drivers/scsi/isci/host.c
2051
writel(0x00040000, &xcvr->afe_tx_control);
drivers/scsi/isci/host.c
2060
writel(0x00004100, &xcvr->afe_xcvr_control0);
drivers/scsi/isci/host.c
2062
writel(0x00014100, &xcvr->afe_xcvr_control0);
drivers/scsi/isci/host.c
2064
writel(0x0001C100, &xcvr->afe_xcvr_control0);
drivers/scsi/isci/host.c
2069
writel(0x3F11103F, &xcvr->afe_rx_ssc_control0);
drivers/scsi/isci/host.c
2071
writel(0x3F11103F, &xcvr->afe_rx_ssc_control0);
drivers/scsi/isci/host.c
2074
writel(0x00040000, &xcvr->afe_tx_control);
drivers/scsi/isci/host.c
2076
writel(0x01400C0F, &xcvr->afe_rx_ssc_control1);
drivers/scsi/isci/host.c
2079
writel(0x3F6F103F, &xcvr->afe_rx_ssc_control0);
drivers/scsi/isci/host.c
2083
writel(0x00040000, &xcvr->afe_tx_control);
drivers/scsi/isci/host.c
2085
writel(cable_length_long ? 0x01500C0C :
drivers/scsi/isci/host.c
2090
writel(0x000003E0, &xcvr->afe_dfx_rx_control1);
drivers/scsi/isci/host.c
2093
writel(cable_length_long ? 0x33091C1F :
drivers/scsi/isci/host.c
2099
writel(0x00040000, &xcvr->afe_tx_control);
drivers/scsi/isci/host.c
210
writel(0xFF000000, &ihost->smu_registers->interrupt_mask);
drivers/scsi/isci/host.c
2104
writel(oem_phy->afe_tx_amp_control0, &xcvr->afe_tx_amp_control0);
drivers/scsi/isci/host.c
2107
writel(oem_phy->afe_tx_amp_control1, &xcvr->afe_tx_amp_control1);
drivers/scsi/isci/host.c
211
writel(0, &ihost->smu_registers->interrupt_mask);
drivers/scsi/isci/host.c
2110
writel(oem_phy->afe_tx_amp_control2, &xcvr->afe_tx_amp_control2);
drivers/scsi/isci/host.c
2113
writel(oem_phy->afe_tx_amp_control3, &xcvr->afe_tx_amp_control3);
drivers/scsi/isci/host.c
2118
writel(0x00010f00, &afe->afe_dfx_master_control0);
drivers/scsi/isci/host.c
2163
writel(0, &ihost->smu_registers->soft_reset_control);
drivers/scsi/isci/host.c
2199
writel(i, &ptsg->protocol_engine[i]);
drivers/scsi/isci/host.c
2205
writel(val, &ihost->scu_registers->sdma.pdma_configuration);
drivers/scsi/isci/host.c
2209
writel(val, &ihost->scu_registers->sdma.cdma_configuration);
drivers/scsi/isci/host.c
2303
writel(lower_32_bits(ihost->cq_dma), &ihost->smu_registers->completion_queue_lower);
drivers/scsi/isci/host.c
2304
writel(upper_32_bits(ihost->cq_dma), &ihost->smu_registers->completion_queue_upper);
drivers/scsi/isci/host.c
2306
writel(lower_32_bits(ihost->rnc_dma), &ihost->smu_registers->remote_node_context_lower);
drivers/scsi/isci/host.c
2307
writel(upper_32_bits(ihost->rnc_dma), &ihost->smu_registers->remote_node_context_upper);
drivers/scsi/isci/host.c
2309
writel(lower_32_bits(ihost->tc_dma), &ihost->smu_registers->host_task_table_lower);
drivers/scsi/isci/host.c
2310
writel(upper_32_bits(ihost->tc_dma), &ihost->smu_registers->host_task_table_upper);
drivers/scsi/isci/host.c
2318
writel(lower_32_bits(ihost->uf_control.headers.physical_address),
drivers/scsi/isci/host.c
2320
writel(upper_32_bits(ihost->uf_control.headers.physical_address),
drivers/scsi/isci/host.c
2323
writel(lower_32_bits(ihost->uf_control.address_table.physical_address),
drivers/scsi/isci/host.c
2325
writel(upper_32_bits(ihost->uf_control.address_table.physical_address),
drivers/scsi/isci/host.c
2371
writel(1, &ihost->scu_registers->peg0.sgpio.interface_control);
drivers/scsi/isci/host.c
2373
writel(SGPIO_HW_CONTROL, &ihost->scu_registers->peg0.sgpio.output_data_select[i]);
drivers/scsi/isci/host.c
2374
writel(0, &ihost->scu_registers->peg0.sgpio.vendor_specific_code);
drivers/scsi/isci/host.c
2455
writel(request, &ihost->smu_registers->post_context_port);
drivers/scsi/isci/host.c
249
writel(0xff, &ihost->smu_registers->interrupt_mask);
drivers/scsi/isci/host.c
250
writel(0, &ihost->smu_registers->interrupt_mask);
drivers/scsi/isci/host.c
2546
writel(ihost->uf_control.get,
drivers/scsi/isci/host.c
2780
writel(val, &ihost->scu_registers->peg0.sgpio.output_data_select[d]);
drivers/scsi/isci/host.c
567
writel(ihost->completion_queue_get,
drivers/scsi/isci/host.c
590
writel(SMU_ISR_QUEUE_SUSPEND, &ihost->smu_registers->interrupt_status);
drivers/scsi/isci/host.c
603
writel(0, &ihost->smu_registers->interrupt_mask);
drivers/scsi/isci/host.c
612
writel(SMU_ISR_COMPLETION, &ihost->smu_registers->interrupt_status);
drivers/scsi/isci/host.c
705
writel(0, &ihost->smu_registers->interrupt_mask);
drivers/scsi/isci/host.c
711
writel(0xffffffff, &ihost->smu_registers->interrupt_mask);
drivers/scsi/isci/host.c
724
writel(port_task_scheduler_value,
drivers/scsi/isci/host.c
744
writel(task_assignment,
drivers/scsi/isci/host.c
762
writel(completion_queue_control_value,
drivers/scsi/isci/host.c
774
writel(completion_queue_get_value,
drivers/scsi/isci/host.c
783
writel(completion_queue_put_value,
drivers/scsi/isci/host.c
806
writel(frame_queue_control_value,
drivers/scsi/isci/host.c
815
writel(frame_queue_get_value,
drivers/scsi/isci/host.c
819
writel(frame_queue_put_value,
drivers/scsi/isci/phy.c
101
writel(SCIC_SDS_REMOTE_NODE_CONTEXT_INVALID_INDEX,
drivers/scsi/isci/phy.c
110
writel(tl_control, &iphy->transport_layer_registers->control);
drivers/scsi/isci/phy.c
1187
writel(scu_sas_pcfg_value,
drivers/scsi/isci/phy.c
1193
writel(enable_spinup_value, &iphy->link_layer_registers->notify_enable_spinup_control);
drivers/scsi/isci/phy.c
1206
writel(val, &ll->phy_configuration);
drivers/scsi/isci/phy.c
1213
writel(val, &ll->phy_configuration);
drivers/scsi/isci/phy.c
1241
writel(phy_configuration_value,
drivers/scsi/isci/phy.c
1247
writel(phy_configuration_value,
drivers/scsi/isci/phy.c
138
writel(SCU_SAS_TIID_GEN_BIT(SMP_INITIATOR) |
drivers/scsi/isci/phy.c
146
writel(0xFEDCBA98, &llr->sas_device_name_high);
drivers/scsi/isci/phy.c
147
writel(phy_idx, &llr->sas_device_name_low);
drivers/scsi/isci/phy.c
150
writel(phy_oem->sas_address.high, &llr->source_sas_address_high);
drivers/scsi/isci/phy.c
151
writel(phy_oem->sas_address.low, &llr->source_sas_address_low);
drivers/scsi/isci/phy.c
154
writel(0, &llr->identify_frame_phy_id);
drivers/scsi/isci/phy.c
155
writel(SCU_SAS_TIPID_GEN_VALUE(ID, phy_idx), &llr->identify_frame_phy_id);
drivers/scsi/isci/phy.c
162
writel(phy_configuration, &llr->phy_configuration);
drivers/scsi/isci/phy.c
205
writel(reg, &xcvr->afe_xcvr_control0);
drivers/scsi/isci/phy.c
209
writel(reg, &xcvr->afe_tx_ssc_control);
drivers/scsi/isci/phy.c
217
writel(reg, &xcvr->afe_tx_ssc_control);
drivers/scsi/isci/phy.c
221
writel(reg, &llr->stp_control);
drivers/scsi/isci/phy.c
241
writel(phy_cap.all, &llr->phy_capabilities);
drivers/scsi/isci/phy.c
246
writel(SCU_ENSPINUP_GEN_VAL(COUNT,
drivers/scsi/isci/phy.c
259
writel(clksm_value, &llr->clock_skew_management);
drivers/scsi/isci/phy.c
262
writel(0x04210400, &llr->afe_lookup_table_control);
drivers/scsi/isci/phy.c
263
writel(0x020A7C05, &llr->sas_primitive_timeout);
drivers/scsi/isci/phy.c
265
writel(0x02108421, &llr->afe_lookup_table_control);
drivers/scsi/isci/phy.c
282
writel(llctl, &llr->link_layer_control);
drivers/scsi/isci/phy.c
294
writel(sp_timeouts, &llr->sas_phy_timeouts);
drivers/scsi/isci/phy.c
303
writel(SCIC_SDS_PHY_MAX_ARBITRATION_WAIT_TIME,
drivers/scsi/isci/phy.c
310
writel(0, &llr->link_layer_hang_detection_timeout);
drivers/scsi/isci/phy.c
410
writel(device_id, &iphy->transport_layer_registers->stp_rni);
drivers/scsi/isci/phy.c
418
writel(tl_control, &iphy->transport_layer_registers->control);
drivers/scsi/isci/phy.c
428
writel(scu_sas_pcfg_value,
drivers/scsi/isci/phy.c
441
writel(scu_sas_pcfg_value,
drivers/scsi/isci/phy.c
528
writel(enable_spinup, &iphy->link_layer_registers->notify_enable_spinup_control);
drivers/scsi/isci/phy.c
544
writel(scu_sas_pcfg_value,
drivers/scsi/isci/phy.c
550
writel(scu_sas_pcfg_value,
drivers/scsi/isci/phy.c
575
writel(phy_control,
drivers/scsi/isci/phy.c
678
writel(val, &iphy->link_layer_registers->transmit_comsas_signal);
drivers/scsi/isci/port.c
1448
writel(pts_control_value, &iport->port_task_scheduler_registers->control);
drivers/scsi/isci/port.c
1458
writel(pts_control_value, &iport->port_task_scheduler_registers->control);
drivers/scsi/isci/port.c
155
writel(val, &iphy->link_layer_registers->link_layer_control);
drivers/scsi/isci/port.c
1569
writel(timeout,
drivers/scsi/isci/port.c
657
writel(iphy->phy_index,
drivers/scsi/isci/port.c
768
writel(iphy->phy_index,
drivers/scsi/isci/port.c
832
writel(sas_address.high,
drivers/scsi/isci/port.c
834
writel(sas_address.low,
drivers/scsi/isci/port.c
838
writel(0, &iport->viit_registers->reserved);
drivers/scsi/isci/port.c
841
writel(SCU_VIIT_ENTRY_ID_VIIT |
drivers/scsi/isci/port.c
873
writel(pts_control_value, &iport->port_task_scheduler_registers->control);
drivers/scsi/isci/port.c
940
writel(pts_control_value, &iport->port_task_scheduler_registers->control);
drivers/scsi/isci/port.c
976
writel(iport->physical_port_index,
drivers/scsi/lpfc/lpfc.h
1640
writel(HA_ERATT, phba->HAregaddr);
drivers/scsi/lpfc/lpfc.h
1707
writel(reg_data.word0, phba->sli4_hba.u.if_type2.EQDregaddr);
drivers/scsi/lpfc/lpfc_attr.c
1873
writel(reg_val, phba->sli4_hba.conf_regs_memmap_p +
drivers/scsi/lpfc/lpfc_attr.c
2699
writel(creg_val, phba->HCregaddr);
drivers/scsi/lpfc/lpfc_attr.c
2720
writel(creg_val, phba->HCregaddr);
drivers/scsi/lpfc/lpfc_attr.c
6353
writel(*((uint32_t *)(buf + buf_off + LPFC_REG_WRITE_KEY_SIZE)),
drivers/scsi/lpfc/lpfc_bsg.c
1551
writel(creg_val, phba->HCregaddr);
drivers/scsi/lpfc/lpfc_bsg.c
497
writel(creg_val, phba->HCregaddr);
drivers/scsi/lpfc/lpfc_bsg.c
744
writel(creg_val, phba->HCregaddr);
drivers/scsi/lpfc/lpfc_compat.h
52
writel( *src32, dest32);
drivers/scsi/lpfc/lpfc_debugfs.c
3864
writel(value, mem_mapped_bar + offset);
drivers/scsi/lpfc/lpfc_debugfs.c
3870
writel(u32val, mem_mapped_bar + offset);
drivers/scsi/lpfc/lpfc_debugfs.c
3876
writel(u32val, mem_mapped_bar + offset);
drivers/scsi/lpfc/lpfc_debugfs.c
4784
writel(reg_val, drb_reg);
drivers/scsi/lpfc/lpfc_debugfs.c
5008
writel(reg_val, ctl_reg);
drivers/scsi/lpfc/lpfc_els.c
4639
writel(control, phba->HCregaddr);
drivers/scsi/lpfc/lpfc_hbadisc.c
1082
writel(control, phba->HCregaddr);
drivers/scsi/lpfc/lpfc_hbadisc.c
1484
writel(control, phba->HCregaddr);
drivers/scsi/lpfc/lpfc_hbadisc.c
1506
writel(control, phba->HCregaddr);
drivers/scsi/lpfc/lpfc_hbadisc.c
3718
writel(control, phba->HCregaddr);
drivers/scsi/lpfc/lpfc_init.c
11748
writel(reg_data.word0, phba->sli4_hba.u.if_type2.
drivers/scsi/lpfc/lpfc_init.c
2224
writel(HA_LATT, phba->HAregaddr);
drivers/scsi/lpfc/lpfc_init.c
2239
writel(control, phba->HCregaddr);
drivers/scsi/lpfc/lpfc_init.c
2243
writel(HA_LATT, phba->HAregaddr);
drivers/scsi/lpfc/lpfc_init.c
5056
writel(0, phba->HCregaddr);
drivers/scsi/lpfc/lpfc_init.c
5059
writel(0xffffffff, phba->HAregaddr);
drivers/scsi/lpfc/lpfc_init.c
591
writel(status, phba->HCregaddr);
drivers/scsi/lpfc/lpfc_init.c
811
writel(0, phba->HCregaddr);
drivers/scsi/lpfc/lpfc_init.c
814
writel(0xffffffff, phba->HAregaddr);
drivers/scsi/lpfc/lpfc_init.c
892
writel(0, phba->HCregaddr);
drivers/scsi/lpfc/lpfc_sli.c
10036
writel(dma_address->addr_hi, phba->sli4_hba.BMBXregaddr);
drivers/scsi/lpfc/lpfc_sli.c
10044
writel(dma_address->addr_lo, phba->sli4_hba.BMBXregaddr);
drivers/scsi/lpfc/lpfc_sli.c
13217
writel(creg_val, phba->HCregaddr);
drivers/scsi/lpfc/lpfc_sli.c
13284
writel(creg_val, phba->HCregaddr);
drivers/scsi/lpfc/lpfc_sli.c
13457
writel(0, phba->HCregaddr);
drivers/scsi/lpfc/lpfc_sli.c
13751
writel(hc_copy & ~(HC_MBINT_ENA | HC_R2INT_ENA |
drivers/scsi/lpfc/lpfc_sli.c
13754
writel((ha_copy & (HA_MBATT | HA_R2_CLR_MSK)),
drivers/scsi/lpfc/lpfc_sli.c
13756
writel(hc_copy, phba->HCregaddr);
drivers/scsi/lpfc/lpfc_sli.c
13776
writel(control, phba->HCregaddr);
drivers/scsi/lpfc/lpfc_sli.c
13812
writel(control, phba->HCregaddr);
drivers/scsi/lpfc/lpfc_sli.c
13840
writel(0, phba->HCregaddr);
drivers/scsi/lpfc/lpfc_sli.c
14035
writel((ha_copy & (HA_R0_CLR_MSK | HA_R1_CLR_MSK)),
drivers/scsi/lpfc/lpfc_sli.c
14135
writel(hc_copy & ~(HC_MBINT_ENA | HC_R0INT_ENA | HC_R1INT_ENA
drivers/scsi/lpfc/lpfc_sli.c
14138
writel((phba->ha_copy & ~(HA_LATT | HA_ERATT)), phba->HAregaddr);
drivers/scsi/lpfc/lpfc_sli.c
14139
writel(hc_copy, phba->HCregaddr);
drivers/scsi/lpfc/lpfc_sli.c
2234
writel(pring->sli.sli3.cmdidx, &phba->host_gp[pring->ringno].cmdPutInx);
drivers/scsi/lpfc/lpfc_sli.c
2262
writel((CA_R0ATT|CA_R0CE_REQ) << (ringno*4), phba->CAregaddr);
drivers/scsi/lpfc/lpfc_sli.c
2287
writel(CA_R0ATT << (ringno * 4), phba->CAregaddr);
drivers/scsi/lpfc/lpfc_sli.c
2468
writel(hbqp->hbqPutIdx, phba->hbq_put + hbqno);
drivers/scsi/lpfc/lpfc_sli.c
345
writel(doorbell.word0, q->db_regaddr);
drivers/scsi/lpfc/lpfc_sli.c
407
writel(doorbell.word0, q->phba->sli4_hba.MQDBregaddr);
drivers/scsi/lpfc/lpfc_sli.c
4140
writel(pring->sli.sli3.rspidx,
drivers/scsi/lpfc/lpfc_sli.c
4150
writel(status, phba->CAregaddr);
drivers/scsi/lpfc/lpfc_sli.c
4459
writel(pring->sli.sli3.rspidx,
drivers/scsi/lpfc/lpfc_sli.c
4482
writel(status, phba->CAregaddr);
drivers/scsi/lpfc/lpfc_sli.c
486
writel(doorbell.word0, q->phba->sli4_hba.EQDBregaddr);
drivers/scsi/lpfc/lpfc_sli.c
4903
writel((hc_copy & ~HC_ERINT_ENA), phba->HCregaddr);
drivers/scsi/lpfc/lpfc_sli.c
4911
writel(HA_ERATT, phba->HAregaddr);
drivers/scsi/lpfc/lpfc_sli.c
4919
writel(BARRIER_TEST_PATTERN, (resp_buf + 1));
drivers/scsi/lpfc/lpfc_sli.c
4921
writel(mbox.word0, mbox_buf);
drivers/scsi/lpfc/lpfc_sli.c
4965
writel(HA_ERATT, phba->HAregaddr);
drivers/scsi/lpfc/lpfc_sli.c
4971
writel(hc_copy, phba->HCregaddr);
drivers/scsi/lpfc/lpfc_sli.c
501
writel(doorbell.word0, q->phba->sli4_hba.EQDBregaddr);
drivers/scsi/lpfc/lpfc_sli.c
5015
writel(status, phba->HCregaddr);
drivers/scsi/lpfc/lpfc_sli.c
5057
writel(HA_ERATT, phba->HAregaddr);
drivers/scsi/lpfc/lpfc_sli.c
5119
writel(HC_INITFF, phba->HCregaddr);
drivers/scsi/lpfc/lpfc_sli.c
5122
writel(0, phba->HCregaddr);
drivers/scsi/lpfc/lpfc_sli.c
5237
writel(mb.word0, to_slim);
drivers/scsi/lpfc/lpfc_sli.c
5246
writel(mb.word0, to_slim);
drivers/scsi/lpfc/lpfc_sli.c
536
writel(doorbell.word0, q->phba->sli4_hba.EQDBregaddr);
drivers/scsi/lpfc/lpfc_sli.c
5420
writel(0, phba->HCregaddr);
drivers/scsi/lpfc/lpfc_sli.c
5424
writel(0xffffffff, phba->HAregaddr);
drivers/scsi/lpfc/lpfc_sli.c
569
writel(doorbell.word0, q->phba->sli4_hba.EQDBregaddr);
drivers/scsi/lpfc/lpfc_sli.c
6865
writel(LPFC_CTL_PDEV_CTL_DDL_RAS,
drivers/scsi/lpfc/lpfc_sli.c
754
writel(doorbell.word0, q->phba->sli4_hba.CQDBregaddr);
drivers/scsi/lpfc/lpfc_sli.c
784
writel(doorbell.word0, q->phba->sli4_hba.CQDBregaddr);
drivers/scsi/lpfc/lpfc_sli.c
846
writel(doorbell.word0, hq->db_regaddr);
drivers/scsi/lpfc/lpfc_sli.c
9659
writel(ldata, to_slim);
drivers/scsi/lpfc/lpfc_sli.c
9674
writel(CA_MBATT, phba->CAregaddr);
drivers/scsi/lpfc/lpfc_sli.c
9683
writel(CA_MBATT, phba->CAregaddr);
drivers/scsi/lpfc/lpfc_sli.c
9784
writel(HA_MBATT, phba->HAregaddr);
drivers/scsi/mac53c94.c
112
writel((RUN|PAUSE|FLUSH|WAKE) << 16, &dma->control);
drivers/scsi/mac53c94.c
137
writel((RUN|PAUSE|FLUSH|WAKE) << 16, &dma->control);
drivers/scsi/mac53c94.c
218
writel(RUN << 16, &dma->control); /* stop dma */
drivers/scsi/mac53c94.c
274
writel(virt_to_phys(state->dma_cmds), &dma->cmdptr);
drivers/scsi/mac53c94.c
275
writel((RUN << 16) | RUN, &dma->control);
drivers/scsi/mac53c94.c
313
writel(RUN << 16, &dma->control); /* stop dma */
drivers/scsi/megaraid.c
81
#define WRINDOOR(adapter,value) writel(value, (adapter)->mmio_base + 0x20)
drivers/scsi/megaraid.c
82
#define WROUTDOOR(adapter,value) writel(value, (adapter)->mmio_base + 0x2C)
drivers/scsi/megaraid/megaraid_mbox.h
229
#define WRINDOOR(rdev, value) writel(value, (rdev)->baseaddr + 0x20)
drivers/scsi/megaraid/megaraid_mbox.h
230
#define WROUTDOOR(rdev, value) writel(value, (rdev)->baseaddr + 0x2C)
drivers/scsi/megaraid/megaraid_sas_base.c
1006
writel((frame_phys_addr | (frame_count<<1))|1,
drivers/scsi/megaraid/megaraid_sas_base.c
1030
writel(0, seq_offset);
drivers/scsi/megaraid/megaraid_sas_base.c
1031
writel(4, seq_offset);
drivers/scsi/megaraid/megaraid_sas_base.c
1032
writel(0xb, seq_offset);
drivers/scsi/megaraid/megaraid_sas_base.c
1033
writel(2, seq_offset);
drivers/scsi/megaraid/megaraid_sas_base.c
1034
writel(7, seq_offset);
drivers/scsi/megaraid/megaraid_sas_base.c
1035
writel(0xd, seq_offset);
drivers/scsi/megaraid/megaraid_sas_base.c
1054
writel((HostDiag | DIAG_RESET_ADAPTER), hostdiag_offset);
drivers/scsi/megaraid/megaraid_sas_base.c
2236
writel(MFI_STOP_ADP, &instance->reg_set->doorbell);
drivers/scsi/megaraid/megaraid_sas_base.c
2243
writel(MFI_STOP_ADP,
drivers/scsi/megaraid/megaraid_sas_base.c
4160
writel(
drivers/scsi/megaraid/megaraid_sas_base.c
4164
writel(
drivers/scsi/megaraid/megaraid_sas_base.c
4177
writel(MFI_INIT_HOTPLUG,
drivers/scsi/megaraid/megaraid_sas_base.c
4180
writel(MFI_INIT_HOTPLUG,
drivers/scsi/megaraid/megaraid_sas_base.c
4196
writel(MFI_RESET_FLAGS,
drivers/scsi/megaraid/megaraid_sas_base.c
4212
writel(MFI_RESET_FLAGS,
drivers/scsi/megaraid/megaraid_sas_base.c
463
writel(0, &(regs)->outbound_intr_mask);
drivers/scsi/megaraid/megaraid_sas_base.c
480
writel(mask, ®s->outbound_intr_mask);
drivers/scsi/megaraid/megaraid_sas_base.c
520
writel(status, ®s->outbound_intr_status);
drivers/scsi/megaraid/megaraid_sas_base.c
544
writel((frame_phys_addr >> 3)|(frame_count),
drivers/scsi/megaraid/megaraid_sas_base.c
561
writel(MFI_ADP_RESET, ®s->inbound_doorbell);
drivers/scsi/megaraid/megaraid_sas_base.c
643
writel(0xFFFFFFFF, &(regs)->outbound_doorbell_clear);
drivers/scsi/megaraid/megaraid_sas_base.c
645
writel(~0x80000000, &(regs)->outbound_intr_mask);
drivers/scsi/megaraid/megaraid_sas_base.c
662
writel(mask, ®s->outbound_intr_mask);
drivers/scsi/megaraid/megaraid_sas_base.c
702
writel(status, ®s->outbound_doorbell_clear);
drivers/scsi/megaraid/megaraid_sas_base.c
726
writel((frame_phys_addr | (frame_count<<1))|1,
drivers/scsi/megaraid/megaraid_sas_base.c
772
writel(0xFFFFFFFF, &(regs)->outbound_intr_mask);
drivers/scsi/megaraid/megaraid_sas_base.c
774
writel(~MFI_SKINNY_ENABLE_INTERRUPT_MASK, &(regs)->outbound_intr_mask);
drivers/scsi/megaraid/megaraid_sas_base.c
791
writel(mask, ®s->outbound_intr_mask);
drivers/scsi/megaraid/megaraid_sas_base.c
839
writel(status, ®s->outbound_intr_status);
drivers/scsi/megaraid/megaraid_sas_base.c
865
writel(upper_32_bits(frame_phys_addr),
drivers/scsi/megaraid/megaraid_sas_base.c
867
writel((lower_32_bits(frame_phys_addr) | (frame_count<<1))|1,
drivers/scsi/megaraid/megaraid_sas_base.c
919
writel(0xFFFFFFFF, &(regs)->outbound_doorbell_clear);
drivers/scsi/megaraid/megaraid_sas_base.c
922
writel(~MFI_GEN2_ENABLE_INTERRUPT_MASK, &(regs)->outbound_intr_mask);
drivers/scsi/megaraid/megaraid_sas_base.c
939
writel(mask, ®s->outbound_intr_mask);
drivers/scsi/megaraid/megaraid_sas_base.c
982
writel(status, ®s->outbound_doorbell_clear);
drivers/scsi/megaraid/megaraid_sas_fusion.c
172
writel(~0, ®s->outbound_intr_status);
drivers/scsi/megaraid/megaraid_sas_fusion.c
175
writel(~MFI_FUSION_ENABLE_INTERRUPT_MASK, &(regs)->outbound_intr_mask);
drivers/scsi/megaraid/megaraid_sas_fusion.c
194
writel(mask, ®s->outbound_intr_mask);
drivers/scsi/megaraid/megaraid_sas_fusion.c
213
writel(status, ®s->outbound_intr_status);
drivers/scsi/megaraid/megaraid_sas_fusion.c
303
writel(le32_to_cpu(req_desc->u.low),
drivers/scsi/megaraid/megaraid_sas_fusion.c
305
writel(le32_to_cpu(req_desc->u.high),
drivers/scsi/megaraid/megaraid_sas_fusion.c
324
writel(le32_to_cpu(req_desc->u.low),
drivers/scsi/megaraid/megaraid_sas_fusion.c
3688
writel(((MSIxIndex & 0x7) << 24) |
drivers/scsi/megaraid/megaraid_sas_fusion.c
3692
writel((MSIxIndex << 24) |
drivers/scsi/megaraid/megaraid_sas_fusion.c
3711
writel(((MSIxIndex & 0x7) << 24) |
drivers/scsi/megaraid/megaraid_sas_fusion.c
3715
writel((MSIxIndex << 24) |
drivers/scsi/megaraid/megaraid_sas_fusion.c
4060
writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &instance->reg_set->fusion_seq_offset);
drivers/scsi/megaraid/megaraid_sas_fusion.c
4061
writel(MPI2_WRSEQ_1ST_KEY_VALUE, &instance->reg_set->fusion_seq_offset);
drivers/scsi/megaraid/megaraid_sas_fusion.c
4062
writel(MPI2_WRSEQ_2ND_KEY_VALUE, &instance->reg_set->fusion_seq_offset);
drivers/scsi/megaraid/megaraid_sas_fusion.c
4063
writel(MPI2_WRSEQ_3RD_KEY_VALUE, &instance->reg_set->fusion_seq_offset);
drivers/scsi/megaraid/megaraid_sas_fusion.c
4064
writel(MPI2_WRSEQ_4TH_KEY_VALUE, &instance->reg_set->fusion_seq_offset);
drivers/scsi/megaraid/megaraid_sas_fusion.c
4065
writel(MPI2_WRSEQ_5TH_KEY_VALUE, &instance->reg_set->fusion_seq_offset);
drivers/scsi/megaraid/megaraid_sas_fusion.c
4066
writel(MPI2_WRSEQ_6TH_KEY_VALUE, &instance->reg_set->fusion_seq_offset);
drivers/scsi/megaraid/megaraid_sas_fusion.c
4086
writel(host_diag | HOST_DIAG_RESET_ADAPTER,
drivers/scsi/megaraid/megaraid_sas_fusion.c
4149
writel(MFI_ADP_TRIGGER_SNAP_DUMP,
drivers/scsi/megaraid/megaraid_sas_fusion.c
4945
writel(status_reg | MFI_STATE_FORCE_OCR,
drivers/scsi/megaraid/megaraid_sas_fusion.c
5223
writel(status_reg,
drivers/scsi/megaraid/megaraid_sas_fusion.c
5263
writel(status_reg, &instance->reg_set->outbound_scratch_pad_0);
drivers/scsi/megaraid/megaraid_sas_fusion.c
5276
writel(status_reg, &instance->reg_set->outbound_scratch_pad_0);
drivers/scsi/mpi3mr/mpi3mr_fw.c
1346
writel(ioc_status, &mrioc->sysif_regs->ioc_status);
drivers/scsi/mpi3mr/mpi3mr_fw.c
1375
writel(scratch_pad0, &mrioc->sysif_regs->scratchpad[0]);
drivers/scsi/mpi3mr/mpi3mr_fw.c
1378
writel(ioc_config, &mrioc->sysif_regs->ioc_configuration);
drivers/scsi/mpi3mr/mpi3mr_fw.c
158
writel(mrioc->reply_free_queue_host_index,
drivers/scsi/mpi3mr/mpi3mr_fw.c
1609
writel(ioc_config, &mrioc->sysif_regs->ioc_configuration);
drivers/scsi/mpi3mr/mpi3mr_fw.c
1726
writel(ioc_config, &mrioc->sysif_regs->ioc_configuration);
drivers/scsi/mpi3mr/mpi3mr_fw.c
175
writel(mrioc->sbq_host_index,
drivers/scsi/mpi3mr/mpi3mr_fw.c
1778
writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_FLUSH,
drivers/scsi/mpi3mr/mpi3mr_fw.c
1780
writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_1ST,
drivers/scsi/mpi3mr/mpi3mr_fw.c
1782
writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_2ND,
drivers/scsi/mpi3mr/mpi3mr_fw.c
1784
writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_3RD,
drivers/scsi/mpi3mr/mpi3mr_fw.c
1786
writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_4TH,
drivers/scsi/mpi3mr/mpi3mr_fw.c
1788
writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_5TH,
drivers/scsi/mpi3mr/mpi3mr_fw.c
1790
writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_6TH,
drivers/scsi/mpi3mr/mpi3mr_fw.c
1802
writel(scratch_pad0, &mrioc->sysif_regs->scratchpad[0]);
drivers/scsi/mpi3mr/mpi3mr_fw.c
1805
writel(host_diagnostic | reset_type,
drivers/scsi/mpi3mr/mpi3mr_fw.c
1838
writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_2ND,
drivers/scsi/mpi3mr/mpi3mr_fw.c
1908
writel(mrioc->admin_req_pi, &mrioc->sysif_regs->admin_request_queue_pi);
drivers/scsi/mpi3mr/mpi3mr_fw.c
2621
writel(op_req_q->pi,
drivers/scsi/mpi3mr/mpi3mr_fw.c
3082
writel(num_admin_entries, &mrioc->sysif_regs->admin_queue_num_entries);
drivers/scsi/mpi3mr/mpi3mr_fw.c
3089
writel(mrioc->admin_req_pi, &mrioc->sysif_regs->admin_request_queue_pi);
drivers/scsi/mpi3mr/mpi3mr_fw.c
3090
writel(mrioc->admin_reply_ci, &mrioc->sysif_regs->admin_reply_queue_ci);
drivers/scsi/mpi3mr/mpi3mr_fw.c
3658
writel(mrioc->reply_free_queue_host_index,
drivers/scsi/mpi3mr/mpi3mr_fw.c
3662
writel(mrioc->sbq_host_index,
drivers/scsi/mpi3mr/mpi3mr_fw.c
43
writel((u32)(data_out), addr);
drivers/scsi/mpi3mr/mpi3mr_fw.c
44
writel((u32)(data_out >> 32), (addr + 4));
drivers/scsi/mpi3mr/mpi3mr_fw.c
497
writel(admin_reply_ci,
drivers/scsi/mpi3mr/mpi3mr_fw.c
503
writel(admin_reply_ci, &mrioc->sysif_regs->admin_reply_queue_ci);
drivers/scsi/mpi3mr/mpi3mr_fw.c
5074
writel(ioc_config, &mrioc->sysif_regs->ioc_configuration);
drivers/scsi/mpi3mr/mpi3mr_fw.c
609
writel(reply_ci,
drivers/scsi/mpi3mr/mpi3mr_fw.c
616
writel(reply_ci,
drivers/scsi/mpt3sas/mpt3sas_base.c
1650
writel(him_register, &ioc->chip->HostInterruptMask);
drivers/scsi/mpt3sas/mpt3sas_base.c
1667
writel(him_register, &ioc->chip->HostInterruptMask);
drivers/scsi/mpt3sas/mpt3sas_base.c
1780
writel(ioc->reply_free_host_index,
drivers/scsi/mpt3sas/mpt3sas_base.c
1801
writel(reply_q->reply_post_host_index |
drivers/scsi/mpt3sas/mpt3sas_base.c
1806
writel(reply_q->reply_post_host_index |
drivers/scsi/mpt3sas/mpt3sas_base.c
1835
writel(reply_q->reply_post_host_index,
drivers/scsi/mpt3sas/mpt3sas_base.c
1857
writel(reply_q->reply_post_host_index | ((msix_index & 7) <<
drivers/scsi/mpt3sas/mpt3sas_base.c
1861
writel(reply_q->reply_post_host_index | (msix_index <<
drivers/scsi/mpt3sas/mpt3sas_base.c
261
writel(reply, reply_free_iomem);
drivers/scsi/mpt3sas/mpt3sas_base.c
279
writel((u32)src_virt_mem[i],
drivers/scsi/mpt3sas/mpt3sas_base.c
297
writel((u32)src_virt_mem[i],
drivers/scsi/mpt3sas/mpt3sas_base.c
4360
writel(cpu_to_le32(*request), &ioc->chip->AtomicRequestDescriptorPost);
drivers/scsi/mpt3sas/mpt3sas_base.c
4382
writel(cpu_to_le32(*request), &ioc->chip->AtomicRequestDescriptorPost);
drivers/scsi/mpt3sas/mpt3sas_base.c
4405
writel(cpu_to_le32(*request), &ioc->chip->AtomicRequestDescriptorPost);
drivers/scsi/mpt3sas/mpt3sas_base.c
4426
writel(cpu_to_le32(*request), &ioc->chip->AtomicRequestDescriptorPost);
drivers/scsi/mpt3sas/mpt3sas_base.c
6955
writel(reset_type << MPI2_DOORBELL_FUNCTION_SHIFT,
drivers/scsi/mpt3sas/mpt3sas_base.c
7069
writel(0, &ioc->chip->HostInterruptStatus);
drivers/scsi/mpt3sas/mpt3sas_base.c
7072
writel(((MPI2_FUNCTION_HANDSHAKE<<MPI2_DOORBELL_FUNCTION_SHIFT) |
drivers/scsi/mpt3sas/mpt3sas_base.c
7081
writel(0, &ioc->chip->HostInterruptStatus);
drivers/scsi/mpt3sas/mpt3sas_base.c
7091
writel(cpu_to_le32(request[i]), &ioc->chip->Doorbell);
drivers/scsi/mpt3sas/mpt3sas_base.c
7112
writel(0, &ioc->chip->HostInterruptStatus);
drivers/scsi/mpt3sas/mpt3sas_base.c
7120
writel(0, &ioc->chip->HostInterruptStatus);
drivers/scsi/mpt3sas/mpt3sas_base.c
7134
writel(0, &ioc->chip->HostInterruptStatus);
drivers/scsi/mpt3sas/mpt3sas_base.c
7143
writel(0, &ioc->chip->HostInterruptStatus);
drivers/scsi/mpt3sas/mpt3sas_base.c
7975
writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence);
drivers/scsi/mpt3sas/mpt3sas_base.c
7976
writel(MPI2_WRSEQ_1ST_KEY_VALUE, &ioc->chip->WriteSequence);
drivers/scsi/mpt3sas/mpt3sas_base.c
7977
writel(MPI2_WRSEQ_2ND_KEY_VALUE, &ioc->chip->WriteSequence);
drivers/scsi/mpt3sas/mpt3sas_base.c
7978
writel(MPI2_WRSEQ_3RD_KEY_VALUE, &ioc->chip->WriteSequence);
drivers/scsi/mpt3sas/mpt3sas_base.c
7979
writel(MPI2_WRSEQ_4TH_KEY_VALUE, &ioc->chip->WriteSequence);
drivers/scsi/mpt3sas/mpt3sas_base.c
7980
writel(MPI2_WRSEQ_5TH_KEY_VALUE, &ioc->chip->WriteSequence);
drivers/scsi/mpt3sas/mpt3sas_base.c
7981
writel(MPI2_WRSEQ_6TH_KEY_VALUE, &ioc->chip->WriteSequence);
drivers/scsi/mpt3sas/mpt3sas_base.c
8011
writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence);
drivers/scsi/mpt3sas/mpt3sas_base.c
8040
writel(host_diagnostic | MPI2_DIAG_RESET_ADAPTER,
drivers/scsi/mpt3sas/mpt3sas_base.c
8072
writel(host_diagnostic, &ioc->chip->HostDiagnostic);
drivers/scsi/mpt3sas/mpt3sas_base.c
8075
writel(hcb_size | MPI2_HCB_SIZE_HCB_ENABLE,
drivers/scsi/mpt3sas/mpt3sas_base.c
8080
writel(host_diagnostic & ~MPI2_DIAG_HOLD_IOC_RESET,
drivers/scsi/mpt3sas/mpt3sas_base.c
8320
writel(ioc->reply_free_host_index, &ioc->chip->ReplyFreeHostIndex);
drivers/scsi/mpt3sas/mpt3sas_base.c
8325
writel((reply_q->msix_index & 7)<<
drivers/scsi/mpt3sas/mpt3sas_base.c
8329
writel(reply_q->msix_index <<
drivers/scsi/mpt3sas/mpt3sas_base.c
966
writel(0xC0FFEE00, &ioc->chip->Doorbell);
drivers/scsi/mpt3sas/mpt3sas_ctl.c
2646
writel(host_diagnostic, &ioc->chip->HostDiagnostic);
drivers/scsi/mvsas/mv_64xx.c
336
writel(0x0E008000, regs + 0x000);
drivers/scsi/mvsas/mv_64xx.c
337
writel(0x59000008, regs + 0x004);
drivers/scsi/mvsas/mv_64xx.c
338
writel(0x20, regs + 0x008);
drivers/scsi/mvsas/mv_64xx.c
339
writel(0x20, regs + 0x00c);
drivers/scsi/mvsas/mv_64xx.c
340
writel(0x20, regs + 0x010);
drivers/scsi/mvsas/mv_64xx.c
341
writel(0x20, regs + 0x014);
drivers/scsi/mvsas/mv_64xx.c
342
writel(0x20, regs + 0x018);
drivers/scsi/mvsas/mv_64xx.c
343
writel(0x20, regs + 0x01c);
drivers/scsi/mvsas/mv_94xx.c
477
writel(0x0E008000, regs + 0x000);
drivers/scsi/mvsas/mv_94xx.c
478
writel(0x59000008, regs + 0x004);
drivers/scsi/mvsas/mv_94xx.c
479
writel(0x20, regs + 0x008);
drivers/scsi/mvsas/mv_94xx.c
480
writel(0x20, regs + 0x00c);
drivers/scsi/mvsas/mv_94xx.c
481
writel(0x20, regs + 0x010);
drivers/scsi/mvsas/mv_94xx.c
482
writel(0x20, regs + 0x014);
drivers/scsi/mvsas/mv_94xx.c
483
writel(0x20, regs + 0x018);
drivers/scsi/mvsas/mv_94xx.c
484
writel(0x20, regs + 0x01c);
drivers/scsi/mvsas/mv_94xx.c
600
writel(tmp, regs + 0x0C);
drivers/scsi/mvsas/mv_94xx.c
601
writel(tmp, regs + 0x10);
drivers/scsi/mvsas/mv_94xx.c
602
writel(tmp, regs + 0x14);
drivers/scsi/mvsas/mv_94xx.c
603
writel(tmp, regs + 0x18);
drivers/scsi/mvsas/mv_94xx.c
616
writel(tmp, regs + 0x0C);
drivers/scsi/mvsas/mv_94xx.c
617
writel(tmp, regs + 0x10);
drivers/scsi/mvsas/mv_94xx.c
618
writel(tmp, regs + 0x14);
drivers/scsi/mvsas/mv_94xx.c
619
writel(tmp, regs + 0x18);
drivers/scsi/mvsas/mv_chips.h
15
#define mw32(reg, val) writel((val), regs + reg)
drivers/scsi/mvsas/mv_chips.h
73
writel(val, regs + port * 8);
drivers/scsi/mvsas/mv_chips.h
75
writel(val, regs2 + (port - 4) * 8);
drivers/scsi/myrb.c
2599
writel(mbox->words[0], base + DAC960_LA_CMDOP_OFFSET);
drivers/scsi/myrb.c
2600
writel(mbox->words[1], base + DAC960_LA_MBOX4_OFFSET);
drivers/scsi/myrb.c
2601
writel(mbox->words[2], base + DAC960_LA_MBOX8_OFFSET);
drivers/scsi/myrb.c
2764
writel(DAC960_PG_IDB_HWMBOX_NEW_CMD, base + DAC960_PG_IDB_OFFSET);
drivers/scsi/myrb.c
2769
writel(DAC960_PG_IDB_HWMBOX_ACK_STS, base + DAC960_PG_IDB_OFFSET);
drivers/scsi/myrb.c
2774
writel(DAC960_PG_IDB_CTRL_RESET, base + DAC960_PG_IDB_OFFSET);
drivers/scsi/myrb.c
2779
writel(DAC960_PG_IDB_MMBOX_NEW_CMD, base + DAC960_PG_IDB_OFFSET);
drivers/scsi/myrb.c
2798
writel(DAC960_PG_ODB_HWMBOX_ACK_IRQ, base + DAC960_PG_ODB_OFFSET);
drivers/scsi/myrb.c
2803
writel(DAC960_PG_ODB_HWMBOX_ACK_IRQ | DAC960_PG_ODB_MMBOX_ACK_IRQ,
drivers/scsi/myrb.c
2819
writel(imask, base + DAC960_PG_IRQMASK_OFFSET);
drivers/scsi/myrb.c
2826
writel(imask, base + DAC960_PG_IRQMASK_OFFSET);
drivers/scsi/myrb.c
2845
writel(mbox->words[0], base + DAC960_PG_CMDOP_OFFSET);
drivers/scsi/myrb.c
2846
writel(mbox->words[1], base + DAC960_PG_MBOX4_OFFSET);
drivers/scsi/myrb.c
2847
writel(mbox->words[2], base + DAC960_PG_MBOX8_OFFSET);
drivers/scsi/myrb.c
3064
writel(mbox->words[0], base + DAC960_PD_CMDOP_OFFSET);
drivers/scsi/myrb.c
3065
writel(mbox->words[1], base + DAC960_PD_MBOX4_OFFSET);
drivers/scsi/myrb.c
3066
writel(mbox->words[2], base + DAC960_PD_MBOX8_OFFSET);
drivers/scsi/myrs.c
2402
writel(val, base + DAC960_GEM_IDB_READ_OFFSET);
drivers/scsi/myrs.c
2409
writel(val, base + DAC960_GEM_IDB_CLEAR_OFFSET);
drivers/scsi/myrs.c
2416
writel(val, base + DAC960_GEM_IDB_READ_OFFSET);
drivers/scsi/myrs.c
2423
writel(val, base + DAC960_GEM_IDB_READ_OFFSET);
drivers/scsi/myrs.c
2446
writel(val, base + DAC960_GEM_ODB_CLEAR_OFFSET);
drivers/scsi/myrs.c
2454
writel(val, base + DAC960_GEM_ODB_CLEAR_OFFSET);
drivers/scsi/myrs.c
2469
writel(val, base + DAC960_GEM_IRQMASK_CLEAR_OFFSET);
drivers/scsi/myrs.c
2476
writel(val, base + DAC960_GEM_IRQMASK_READ_OFFSET);
drivers/scsi/myrs.c
2514
writel(0x03000000, base + DAC960_GEM_ERRSTS_CLEAR_OFFSET);
drivers/scsi/myrs.h
1034
writel(u.wl[0], write_address);
drivers/scsi/myrs.h
1035
writel(u.wl[1], write_address + 4);
drivers/scsi/ncr53c8xx.h
285
#define writel_b2l writel
drivers/scsi/ncr53c8xx.h
289
#define writel_raw writel
drivers/scsi/ncr53c8xx.h
304
#define writel_raw writel
drivers/scsi/nsp32_io.h
103
writel(cpu_to_le32(val), ptr);
drivers/scsi/pcmcia/nsp_io.h
257
writel(*tmp, ptr);
drivers/scsi/pm8001/pm8001_chips.h
63
writel(val, pm8001_ha->io_mem[bar].memvirtaddr + addr);
drivers/scsi/pm8001/pm8001_chips.h
71
writel(val, addr + offset);
drivers/scsi/qedf/qedf_io.c
791
writel(*(u32 *)&dbell, fcport->p_doorbell);
drivers/scsi/qedi/qedi_fw.c
929
writel(*(u32 *)&qedi_conn->ep->db_data, qedi_conn->ep->p_doorbell);
drivers/scsi/qla2xxx/qla_def.h
200
return writel(data, addr);
drivers/scsi/qla2xxx/qla_nx.c
367
writel(ha->crb_win, CRB_WINDOW_2M + ha->nx_pcibase);
drivers/scsi/qla2xxx/qla_nx.c
451
writel(data, (void __iomem *)off);
drivers/scsi/qla2xxx/qla_nx.c
773
writel(*(u32 *)data, addr);
drivers/scsi/qla2xxx/qla_nx2.c
42
writel(val, (void __iomem *)((ha)->nx_pcibase + addr));
drivers/scsi/qla4xxx/ql4_83xx.c
1275
writel(mb_int, &ha->qla4_83xx_reg->mbox_int);
drivers/scsi/qla4xxx/ql4_83xx.c
1276
writel(1, &ha->qla4_83xx_reg->leg_int_mask);
drivers/scsi/qla4xxx/ql4_83xx.c
1300
writel(mb_int, &ha->qla4_83xx_reg->mbox_int);
drivers/scsi/qla4xxx/ql4_83xx.c
1301
writel(0, &ha->qla4_83xx_reg->leg_int_mask);
drivers/scsi/qla4xxx/ql4_83xx.c
1321
writel(mbx_cmd[i], &ha->qla4_83xx_reg->mailbox_in[i]);
drivers/scsi/qla4xxx/ql4_83xx.c
1323
writel(mbx_cmd[0], &ha->qla4_83xx_reg->mailbox_in[0]);
drivers/scsi/qla4xxx/ql4_83xx.c
1328
writel(HINT_MBX_INT_PENDING, &ha->qla4_83xx_reg->host_intr);
drivers/scsi/qla4xxx/ql4_83xx.c
22
writel(val, (void __iomem *)(ha->nx_pcibase + addr));
drivers/scsi/qla4xxx/ql4_dbg.c
124
writel(HOST_MEM_CFG_PAGE & set_rmask(CSR_SCSI_PAGE_SELECT),
drivers/scsi/qla4xxx/ql4_dbg.c
129
writel(PORT_CTRL_STAT_PAGE & set_rmask(CSR_SCSI_PAGE_SELECT),
drivers/scsi/qla4xxx/ql4_init.c
101
writel(0,
drivers/scsi/qla4xxx/ql4_init.c
103
writel(0,
drivers/scsi/qla4xxx/ql4_init.c
105
writel(0,
drivers/scsi/qla4xxx/ql4_init.c
108
writel(0,
drivers/scsi/qla4xxx/ql4_init.c
110
writel(0,
drivers/scsi/qla4xxx/ql4_init.c
112
writel(0,
drivers/scsi/qla4xxx/ql4_init.c
126
writel(0, &ha->reg->req_q_in);
drivers/scsi/qla4xxx/ql4_init.c
127
writel(0, &ha->reg->rsp_q_out);
drivers/scsi/qla4xxx/ql4_init.c
639
writel((0xFFFF << 16) | extHwConfig.Asuint32_t, isp_ext_hw_conf(ha));
drivers/scsi/qla4xxx/ql4_init.c
703
writel(jiffies, &ha->reg->mailbox[7]);
drivers/scsi/qla4xxx/ql4_init.c
705
writel(set_rmask(NVR_WRITE_ENABLE),
drivers/scsi/qla4xxx/ql4_init.c
708
writel(2, &ha->reg->mailbox[6]);
drivers/scsi/qla4xxx/ql4_init.c
711
writel(set_rmask(CSR_BOOT_ENABLE), &ha->reg->ctrl_status);
drivers/scsi/qla4xxx/ql4_init.c
745
writel(set_rmask(CSR_SCSI_PROCESSOR_INTR),
drivers/scsi/qla4xxx/ql4_init.c
828
writel(set_rmask(CSR_SCSI_PROCESSOR_INTR),
drivers/scsi/qla4xxx/ql4_init.c
831
writel(set_rmask(CSR_SCSI_COMPLETION_INTR),
drivers/scsi/qla4xxx/ql4_inline.h
41
writel(set_rmask(IMR_SCSI_INTR_ENABLE),
drivers/scsi/qla4xxx/ql4_inline.h
45
writel(set_rmask(CSR_SCSI_INTR_ENABLE), &ha->reg->ctrl_status);
drivers/scsi/qla4xxx/ql4_inline.h
55
writel(clr_rmask(IMR_SCSI_INTR_ENABLE),
drivers/scsi/qla4xxx/ql4_inline.h
59
writel(clr_rmask(CSR_SCSI_INTR_ENABLE), &ha->reg->ctrl_status);
drivers/scsi/qla4xxx/ql4_iocb.c
196
writel(ha->request_in, &ha->qla4_83xx_reg->req_q_in);
drivers/scsi/qla4xxx/ql4_iocb.c
202
writel(ha->response_out, &ha->qla4_83xx_reg->rsp_q_out);
drivers/scsi/qla4xxx/ql4_iocb.c
233
writel(ha->response_out, &ha->qla4_82xx_reg->rsp_q_out);
drivers/scsi/qla4xxx/ql4_iocb.c
246
writel(ha->request_in, &ha->reg->req_q_in);
drivers/scsi/qla4xxx/ql4_iocb.c
260
writel(ha->response_out, &ha->reg->rsp_q_out);
drivers/scsi/qla4xxx/ql4_isr.c
1032
writel(0, &ha->qla4_83xx_reg->risc_intr);
drivers/scsi/qla4xxx/ql4_isr.c
1038
writel(0, &ha->qla4_83xx_reg->mb_int_mask);
drivers/scsi/qla4xxx/ql4_isr.c
1063
writel(0, &ha->qla4_82xx_reg->host_int);
drivers/scsi/qla4xxx/ql4_isr.c
1088
writel(set_rmask(CSR_SCSI_PROCESSOR_INTR),
drivers/scsi/qla4xxx/ql4_isr.c
1108
writel(0, &ha->qla4_82xx_reg->host_int);
drivers/scsi/qla4xxx/ql4_isr.c
1173
writel(set_rmask(CSR_SOFT_RESET),
drivers/scsi/qla4xxx/ql4_isr.c
1178
writel(set_rmask(CSR_FATAL_ERROR),
drivers/scsi/qla4xxx/ql4_isr.c
1191
writel(set_rmask(CSR_SCSI_RESET_INTR),
drivers/scsi/qla4xxx/ql4_isr.c
1313
writel(0, &ha->qla4_83xx_reg->leg_int_trig);
drivers/scsi/qla4xxx/ql4_isr.c
1366
writel(ival, &ha->qla4_83xx_reg->mb_int_mask);
drivers/scsi/qla4xxx/ql4_isr.c
1372
writel(0, &ha->qla4_83xx_reg->risc_intr);
drivers/scsi/qla4xxx/ql4_isr.c
1375
writel(ival, &ha->qla4_83xx_reg->mb_int_mask);
drivers/scsi/qla4xxx/ql4_isr.c
1444
writel(0, &ha->qla4_83xx_reg->iocb_int_mask);
drivers/scsi/qla4xxx/ql4_isr.c
1449
writel(0, &ha->qla4_82xx_reg->host_int);
drivers/scsi/qla4xxx/ql4_mbx.c
21
writel(mbx_cmd[i], &ha->reg->mailbox[i]);
drivers/scsi/qla4xxx/ql4_mbx.c
24
writel(mbx_cmd[0], &ha->reg->mailbox[0]);
drivers/scsi/qla4xxx/ql4_mbx.c
26
writel(set_rmask(CSR_INTR_RISC), &ha->reg->ctrl_status);
drivers/scsi/qla4xxx/ql4_nvram.c
14
writel(cmd, isp_nvram(ha));
drivers/scsi/qla4xxx/ql4_nvram.c
212
writel((sem_mask | sem_bits), isp_semaphore(ha));
drivers/scsi/qla4xxx/ql4_nvram.c
231
writel(sem_mask, isp_semaphore(ha));
drivers/scsi/qla4xxx/ql4_nvram.c
245
writel((sem_mask | sem_bits), isp_semaphore(ha));
drivers/scsi/qla4xxx/ql4_nx.c
3596
writel(0, &ha->qla4_83xx_reg->risc_intr);
drivers/scsi/qla4xxx/ql4_nx.c
3599
writel(0, &ha->qla4_82xx_reg->host_int);
drivers/scsi/qla4xxx/ql4_nx.c
364
writel(ha->crb_win,
drivers/scsi/qla4xxx/ql4_nx.c
3903
writel(mbx_cmd[i], &ha->qla4_82xx_reg->mailbox_in[i]);
drivers/scsi/qla4xxx/ql4_nx.c
3906
writel(mbx_cmd[0], &ha->qla4_82xx_reg->mailbox_in[0]);
drivers/scsi/qla4xxx/ql4_nx.c
3908
writel(HINT_MBX_INT_PENDING, &ha->qla4_82xx_reg->hint);
drivers/scsi/qla4xxx/ql4_nx.c
423
writel(data, (void __iomem *)off);
drivers/scsi/qla4xxx/ql4_nx.c
462
writel(off_value, (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
drivers/scsi/qla4xxx/ql4_nx.c
488
writel(off_value, (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
drivers/scsi/qla4xxx/ql4_nx.c
501
writel(data, (void __iomem *)(off_value + CRB_INDIRECT_2M +
drivers/scsi/qla4xxx/ql4_nx.c
829
writel(*(u32 *)data, addr);
drivers/scsi/qla4xxx/ql4_os.c
4690
writel(set_rmask(CSR_SCSI_RESET_INTR), &ha->reg->ctrl_status);
drivers/scsi/qla4xxx/ql4_os.c
4693
writel(set_rmask(CSR_SOFT_RESET), &ha->reg->ctrl_status);
drivers/scsi/qla4xxx/ql4_os.c
4735
writel(set_rmask(CSR_NET_RESET_INTR), &ha->reg->ctrl_status);
drivers/scsi/qla4xxx/ql4_os.c
4762
writel(set_rmask(CSR_SCSI_RESET_INTR), &ha->reg->ctrl_status);
drivers/scsi/qla4xxx/ql4_os.c
4776
writel(set_rmask(CSR_FORCE_SOFT_RESET), &ha->reg->ctrl_status);
drivers/scsi/qla4xxx/ql4_os.c
5489
writel(set_rmask(CSR_SCSI_PROCESSOR_INTR),
drivers/scsi/qla4xxx/ql4_os.c
5493
writel(0, &ha->qla4_82xx_reg->host_int);
drivers/scsi/qla4xxx/ql4_os.c
5496
writel(0, &ha->qla4_83xx_reg->risc_intr);
drivers/scsi/smartpqi/smartpqi_init.c
3523
writel(oq_ci, queue_group->oq_ci);
drivers/scsi/smartpqi/smartpqi_init.c
3583
writel(iq_pi, queue_group->iq_pi[RAID_PATH]);
drivers/scsi/smartpqi/smartpqi_init.c
3944
writel(oq_ci, event_queue->oq_ci);
drivers/scsi/smartpqi/smartpqi_init.c
3968
writel(intx_mask, register_addr);
drivers/scsi/smartpqi/smartpqi_init.c
4406
writel(reg, &pqi_registers->admin_iq_num_elements);
drivers/scsi/smartpqi/smartpqi_init.c
4408
writel(PQI_CREATE_ADMIN_QUEUE_PAIR,
drivers/scsi/smartpqi/smartpqi_init.c
4458
writel(iq_pi, admin_queues->iq_pi);
drivers/scsi/smartpqi/smartpqi_init.c
4495
writel(oq_ci, admin_queues->oq_ci);
drivers/scsi/smartpqi/smartpqi_init.c
4574
writel(iq_pi, queue_group->iq_pi[path]);
drivers/scsi/smartpqi/smartpqi_init.c
7732
writel(reset_reg.all_bits, &ctrl_info->pqi_registers->device_reset);
drivers/scsi/smartpqi/smartpqi_init.c
8588
writel(0, admin_queues->oq_pi);
drivers/scsi/smartpqi/smartpqi_init.c
8595
writel(0, ctrl_info->queue_groups[i].iq_ci[RAID_PATH]);
drivers/scsi/smartpqi/smartpqi_init.c
8596
writel(0, ctrl_info->queue_groups[i].iq_ci[AIO_PATH]);
drivers/scsi/smartpqi/smartpqi_init.c
8597
writel(0, ctrl_info->queue_groups[i].oq_pi);
drivers/scsi/smartpqi/smartpqi_init.c
8601
writel(0, event_queue->oq_pi);
drivers/scsi/smartpqi/smartpqi_sis.c
194
writel(cmd, ®isters->sis_mailbox[0]);
drivers/scsi/smartpqi/smartpqi_sis.c
201
writel(params->mailbox[i], ®isters->sis_mailbox[i]);
drivers/scsi/smartpqi/smartpqi_sis.c
204
writel(SIS_CLEAR_CTRL_TO_HOST_DOORBELL,
drivers/scsi/smartpqi/smartpqi_sis.c
208
writel(~0, ®isters->sis_interrupt_mask);
drivers/scsi/smartpqi/smartpqi_sis.c
218
writel(SIS_CMD_READY, ®isters->sis_host_to_ctrl_doorbell);
drivers/scsi/smartpqi/smartpqi_sis.c
398
writel(bit, &ctrl_info->registers->sis_host_to_ctrl_doorbell);
drivers/scsi/smartpqi/smartpqi_sis.c
422
writel(ctrl_shutdown_reason, &ctrl_info->registers->sis_ctrl_shutdown_reason_code);
drivers/scsi/smartpqi/smartpqi_sis.c
424
writel(SIS_TRIGGER_SHUTDOWN, &ctrl_info->registers->sis_host_to_ctrl_doorbell);
drivers/scsi/smartpqi/smartpqi_sis.c
439
writel(value, &ctrl_info->registers->sis_driver_scratch);
drivers/scsi/smartpqi/smartpqi_sis.c
472
writel(SIS_SOFT_RESET,
drivers/scsi/snic/vnic_dev.h
22
writel(lower_32_bits(val), reg);
drivers/scsi/snic/vnic_dev.h
23
writel(upper_32_bits(val), reg + 0x4UL);
drivers/scsi/stex.c
1009
writel(data, base + PSCRATCH1);
drivers/scsi/stex.c
1010
writel((1 << 22), base + YH2I_INT);
drivers/scsi/stex.c
1034
writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL);
drivers/scsi/stex.c
1075
writel(status_phys, base + IMR0);
drivers/scsi/stex.c
1077
writel((status_phys >> 16) >> 16, base + IMR1);
drivers/scsi/stex.c
1080
writel((status_phys >> 16) >> 16, base + OMR0); /* old fw compatible */
drivers/scsi/stex.c
1082
writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL);
drivers/scsi/stex.c
1098
writel(0, base + IMR0);
drivers/scsi/stex.c
1100
writel(0, base + OMR0);
drivers/scsi/stex.c
1102
writel(0, base + IMR1);
drivers/scsi/stex.c
1104
writel(0, base + OMR1);
drivers/scsi/stex.c
1166
writel(data, base + YINT_EN);
drivers/scsi/stex.c
1167
writel((hba->dma_handle >> 16) >> 16, base + YH2I_REQ_HI);
drivers/scsi/stex.c
1169
writel(hba->dma_handle, base + YH2I_REQ);
drivers/scsi/stex.c
1175
writel(data, base + YINT_EN);
drivers/scsi/stex.c
1178
writel((1 << 6), base + YH2I_INT);
drivers/scsi/stex.c
1181
writel((hba->dma_handle >> 16) >> 16, base + YH2I_REQ_HI);
drivers/scsi/stex.c
1182
writel(hba->dma_handle, base + YH2I_REQ);
drivers/scsi/stex.c
1272
writel(data, base + YI2H_INT_C);
drivers/scsi/stex.c
1279
writel(data, base + PSCRATCH1);
drivers/scsi/stex.c
1280
writel((1 << 22), base + YH2I_INT);
drivers/scsi/stex.c
1288
writel(data, base + ODBL);
drivers/scsi/stex.c
1354
writel(MU_INBOUND_DOORBELL_RESET, base + IDBL);
drivers/scsi/stex.c
1380
writel(SS_H2I_INT_RESET, hba->mmio_base + YH2I_INT);
drivers/scsi/stex.c
1387
writel(SS_H2I_INT_RESET, hba->mmio_base + YH2I_INT);
drivers/scsi/stex.c
525
writel(hba->req_head, hba->mmio_base + IMR0);
drivers/scsi/stex.c
526
writel(MU_INBOUND_DOORBELL_REQHEADCHANGED, hba->mmio_base + IDBL);
drivers/scsi/stex.c
555
writel((addr >> 16) >> 16, hba->mmio_base + YH2I_REQ_HI);
drivers/scsi/stex.c
556
writel(addr, hba->mmio_base + YH2I_REQ);
drivers/scsi/stex.c
558
writel((addr >> 16) >> 16, hba->mmio_base + YH2I_REQ_HI);
drivers/scsi/stex.c
560
writel(addr, hba->mmio_base + YH2I_REQ);
drivers/scsi/stex.c
879
writel(hba->status_head, base + IMR1);
drivers/scsi/stex.c
896
writel(data, base + ODBL);
drivers/scsi/stex.c
997
writel(data, base + YI2H_INT_C);
drivers/scsi/sun3x_esp.c
46
writel((VAL), esp->dma_regs + (REG))
drivers/scsi/sym53c8xx_2/sym_glue.h
105
#define writel_b2l writel
drivers/scsi/sym53c8xx_2/sym_glue.h
112
#define writel_raw writel
drivers/scsi/vmw_pvscsi.c
210
writel(val, adapter->mmioBase + offset);
drivers/slimbus/qcom-ngd-ctrl.c
780
writel(stat, base + NGD_INT_CLR);
drivers/soc/apple/sart.c
106
writel(paddr_shifted, sart->regs + APPLE_SART0_PADDR(index));
drivers/soc/apple/sart.c
107
writel(cfg, sart->regs + APPLE_SART0_CONFIG(index));
drivers/soc/apple/sart.c
139
writel(paddr_shifted, sart->regs + APPLE_SART2_PADDR(index));
drivers/soc/apple/sart.c
140
writel(cfg, sart->regs + APPLE_SART2_CONFIG(index));
drivers/soc/apple/sart.c
166
writel(paddr_shifted, sart->regs + APPLE_SART3_PADDR(index));
drivers/soc/apple/sart.c
167
writel(size_shifted, sart->regs + APPLE_SART3_SIZE(index));
drivers/soc/apple/sart.c
168
writel(flags, sart->regs + APPLE_SART3_CONFIG(index));
drivers/soc/apple/tunable.c
73
writel(val, regs + tunable->values[i].offset);
drivers/soc/bcm/brcmstb/biuctrl.c
78
writel(val, cpubiuctrl_base + offset);
drivers/soc/dove/pmu.c
273
writel(0, pmu->pmc_base + PMC_IRQ_MASK);
drivers/soc/dove/pmu.c
274
writel(0, pmu->pmc_base + PMC_IRQ_CAUSE);
drivers/soc/fujitsu/a64fx-diag.c
46
writel(BMC_DIAG_INTERRUPT_MASK, diag_status_reg_addr);
drivers/soc/fujitsu/a64fx-diag.c
58
writel(mmsc, diag_enable_reg_addr);
drivers/soc/fujitsu/a64fx-diag.c
71
writel(mmsc, diag_enable_reg_addr);
drivers/soc/loongson/loongson2_pm.c
41
#define loongson2_pm_writel(val, reg) writel(val, loongson2_pm.base + reg)
drivers/soc/mediatek/mtk-devapc.c
136
writel(0x1 << min_shift_group, pd_vio_shift_sel_reg);
drivers/soc/mediatek/mtk-devapc.c
139
writel(0x1, pd_vio_shift_con_reg);
drivers/soc/mediatek/mtk-devapc.c
149
writel(0x0, pd_vio_shift_con_reg);
drivers/soc/mediatek/mtk-devapc.c
152
writel(0x1 << min_shift_group, pd_vio_shift_sta_reg);
drivers/soc/mediatek/mtk-devapc.c
206
writel(BIT(31), ctx->infra_base + ctx->data->regs_ofs->apc_con_offset);
drivers/soc/mediatek/mtk-devapc.c
218
writel(BIT(2), ctx->infra_base + ctx->data->regs_ofs->apc_con_offset);
drivers/soc/mediatek/mtk-devapc.c
67
writel(GENMASK(31, 0), reg + 4 * i);
drivers/soc/mediatek/mtk-devapc.c
69
writel(GENMASK(VIO_MOD_TO_REG_OFF(ctx->data->vio_idx_num) - 1, 0),
drivers/soc/mediatek/mtk-devapc.c
87
writel(val, reg + 4 * i);
drivers/soc/mediatek/mtk-devapc.c
97
writel(val, reg + 4 * i);
drivers/soc/mediatek/mtk-dvfsrc.c
135
writel(val, dvfs->regs + dvfs->dvd->regs[offset]);
drivers/soc/mediatek/mtk-mutex.c
1014
writel(0, mtx->regs + DISP_REG_MUTEX_EN(mutex->id));
drivers/soc/mediatek/mtk-mutex.c
1024
writel(1, mtx->regs + DISP_REG_MUTEX_EN(mutex->id));
drivers/soc/mediatek/mtk-mutex.c
1025
writel(1, mtx->regs + DISP_REG_MUTEX(mutex->id));
drivers/soc/mediatek/mtk-mutex.c
1037
writel(0, mtx->regs + DISP_REG_MUTEX(mutex->id));
drivers/soc/mediatek/mtk-mutex.c
984
writel(1, mtx->regs + DISP_REG_MUTEX_EN(mutex->id));
drivers/soc/mediatek/mtk-pmic-wrap.c
1396
writel(val, wrp->base + wrp->master->regs[reg]);
drivers/soc/mediatek/mtk-pmic-wrap.c
1963
writel(0x7f, wrp->bridge_base + PWRAP_MT8135_BRIDGE_IORD_ARB_EN);
drivers/soc/mediatek/mtk-pmic-wrap.c
1964
writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WACS3_EN);
drivers/soc/mediatek/mtk-pmic-wrap.c
1965
writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WACS4_EN);
drivers/soc/mediatek/mtk-pmic-wrap.c
1966
writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WDT_UNIT);
drivers/soc/mediatek/mtk-pmic-wrap.c
1967
writel(0xffff, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WDT_SRC_EN);
drivers/soc/mediatek/mtk-pmic-wrap.c
1968
writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_TIMER_EN);
drivers/soc/mediatek/mtk-pmic-wrap.c
1969
writel(0x7ff, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INT_EN);
drivers/soc/mediatek/mtk-pmic-wrap.c
2134
writel(1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INIT_DONE3);
drivers/soc/mediatek/mtk-pmic-wrap.c
2135
writel(1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INIT_DONE4);
drivers/soc/qcom/ice.c
96
writel((val), (engine)->base + (reg))
drivers/soc/qcom/ocmem.c
104
writel(data, ocmem->mmio + reg);
drivers/soc/qcom/qcom-geni-se.c
1105
writel(0x0, se->base + SE_IRQ_EN);
drivers/soc/qcom/qcom-geni-se.c
1106
writel(DMA_RX_EVENT_EN | DMA_TX_EVENT_EN | GENI_M_EVENT_EN | GENI_S_EVENT_EN,
drivers/soc/qcom/qcom-geni-se.c
1112
writel(DMA_RX_IRQ_EN | DMA_TX_IRQ_EN | GENI_M_IRQ_EN | GENI_S_IRQ_EN,
drivers/soc/qcom/qcom-geni-se.c
1114
writel(0x0, se->base + SE_GSI_EVENT_EN);
drivers/soc/qcom/qcom-geni-se.c
1119
writel(DMA_RX_IRQ_EN | DMA_TX_IRQ_EN | GENI_M_IRQ_EN | GENI_S_IRQ_EN,
drivers/soc/qcom/qcom-geni-se.c
1121
writel(0x0, se->base + SE_GSI_EVENT_EN);
drivers/soc/qcom/qcom-geni-se.c
1142
writel(M_COMMON_GENI_M_IRQ_EN, se->base + SE_GENI_M_IRQ_EN);
drivers/soc/qcom/qcom-geni-se.c
1147
writel(val, se->base + SE_GENI_S_IRQ_ENABLE);
drivers/soc/qcom/qcom-geni-se.c
1151
writel(val, se->base + SE_DMA_TX_IRQ_EN_SET);
drivers/soc/qcom/qcom-geni-se.c
1154
writel(val, se->base + SE_DMA_RX_IRQ_EN_SET);
drivers/soc/qcom/qcom-geni-se.c
1172
writel(reg, se->base + SE_GENI_FW_REVISION);
drivers/soc/qcom/qcom-geni-se.c
1173
writel(reg, se->base + SE_GENI_S_FW_REVISION);
drivers/soc/qcom/qcom-geni-se.c
1232
writel(0x0, se->base + GENI_OUTPUT_CTRL);
drivers/soc/qcom/qcom-geni-se.c
1236
writel(0x0, se->base + SE_GENI_CLK_CTRL);
drivers/soc/qcom/qcom-geni-se.c
1245
writel(DEFAULT_CGC_EN, se->base + SE_GENI_CGC_CTRL);
drivers/soc/qcom/qcom-geni-se.c
1248
writel(le16_to_cpu(hdr->cfg_version), se->base + SE_GENI_INIT_CFG_REVISION);
drivers/soc/qcom/qcom-geni-se.c
1249
writel(le16_to_cpu(hdr->cfg_version), se->base + SE_GENI_S_INIT_CFG_REVISION);
drivers/soc/qcom/qcom-geni-se.c
1253
writel(cfg_val_arr[i],
drivers/soc/qcom/qcom-geni-se.c
1258
writel(reg_value - 2, se->base + SE_GENI_RX_RFR_WATERMARK_REG);
drivers/soc/qcom/qcom-geni-se.c
280
#define geni_setbits32(_addr, _v) writel(readl(_addr) | (_v), _addr)
drivers/soc/qcom/qcom-geni-se.c
281
#define geni_clrbits32(_addr, _v) writel(readl(_addr) & ~(_v), _addr)
drivers/soc/qcom/qcom-geni-se.c
422
writel(0, se->base + SE_IRQ_EN);
drivers/soc/qcom/qcom-geni-se.c
427
writel(val, se->base + SE_GENI_M_IRQ_EN);
drivers/soc/qcom/qcom-geni-se.c
429
writel(GENI_DMA_MODE_EN, se->base + SE_GENI_DMA_MODE_EN);
drivers/soc/qcom/qcom-geni-se.c
433
writel(val, se->base + SE_GSI_EVENT_EN);
drivers/soc/qcom/qcom-geni-se.c
782
writel(len, se->base + SE_DMA_TX_LEN);
drivers/soc/qcom/qcom-geni-se.c
834
writel(len, se->base + SE_DMA_RX_LEN);
drivers/soc/qcom/qcom_aoss.c
149
writel(val, qmp->msgram + QMP_DESC_UCORE_LINK_STATE_ACK);
drivers/soc/qcom/qcom_aoss.c
152
writel(QMP_STATE_UP, qmp->msgram + QMP_DESC_MCORE_LINK_STATE);
drivers/soc/qcom/qcom_aoss.c
162
writel(QMP_STATE_UP, qmp->msgram + QMP_DESC_MCORE_CH_STATE);
drivers/soc/qcom/qcom_aoss.c
173
writel(QMP_STATE_UP, qmp->msgram + QMP_DESC_UCORE_CH_STATE_ACK);
drivers/soc/qcom/qcom_aoss.c
186
writel(QMP_STATE_DOWN, qmp->msgram + QMP_DESC_MCORE_CH_STATE);
drivers/soc/qcom/qcom_aoss.c
189
writel(QMP_STATE_DOWN, qmp->msgram + QMP_DESC_MCORE_LINK_STATE);
drivers/soc/qcom/qcom_aoss.c
197
writel(QMP_STATE_DOWN, qmp->msgram + QMP_DESC_MCORE_CH_STATE);
drivers/soc/qcom/qcom_aoss.c
198
writel(QMP_STATE_DOWN, qmp->msgram + QMP_DESC_MCORE_LINK_STATE);
drivers/soc/qcom/qcom_aoss.c
254
writel(sizeof(buf), qmp->msgram + qmp->offset);
drivers/soc/qcom/qcom_aoss.c
267
writel(0, qmp->msgram + qmp->offset);
drivers/soc/qcom/rpmh-rsc.c
235
writel(data, tcs_reg_addr(drv, reg, tcs_id));
drivers/soc/qcom/smp2p.c
422
writel(val, entry->value);
drivers/soc/qcom/smsm.c
171
writel(val, smsm->local_state);
drivers/soc/qcom/smsm.c
259
writel(val, entry->subscription + smsm->local_host);
drivers/soc/qcom/smsm.c
290
writel(val, entry->subscription + smsm->local_host);
drivers/soc/qcom/smsm.c
635
writel(0, entry->subscription + smsm->local_host);
drivers/soc/renesas/pwc-rzv2m.c
108
writel(BIT(17) | BIT(16), priv->base + PWC_GPIO);
drivers/soc/renesas/pwc-rzv2m.c
38
writel(reg, priv->base + PWC_GPIO);
drivers/soc/renesas/pwc-rzv2m.c
78
writel(PWC_PWCRST_RSTSOFTAX, priv->base + PWC_PWCRST);
drivers/soc/renesas/pwc-rzv2m.c
79
writel(PWC_PWCCKEN_ENGCKMAIN, priv->base + PWC_PWCCKEN);
drivers/soc/renesas/pwc-rzv2m.c
80
writel(PWC_PWCCTL_PWOFF, priv->base + PWC_PWCCTL);
drivers/soc/renesas/r9a06g032-smp.c
43
writel(__pa_symbol(secondary_startup), cpu_bootaddr);
drivers/soc/renesas/rzn1_irqmux.c
104
writel(imap_item.child_imap[0], regs + index);
drivers/soc/samsung/exynos-usi.c
185
writel(val, usi->regs + USI_CON);
drivers/soc/samsung/exynos-usi.c
193
writel(val, usi->regs + USI_OPTION);
drivers/soc/samsung/exynos-usi.c
237
writel(val, usi->regs + USI_OPTION);
drivers/soc/samsung/exynos-usi.c
242
writel(val, usi->regs + USI_CON);
drivers/soc/sunxi/sunxi_sram.c
256
writel(val | ((device << sram_data->offset) & mask),
drivers/soc/tegra/cbb/tegra194-cbb.c
1669
writel(1, priv->regs + ERRLOGGER_0_FAULTEN_0);
drivers/soc/tegra/cbb/tegra194-cbb.c
1670
writel(1, priv->regs + ERRLOGGER_1_FAULTEN_0);
drivers/soc/tegra/cbb/tegra194-cbb.c
1671
writel(1, priv->regs + ERRLOGGER_2_FAULTEN_0);
drivers/soc/tegra/cbb/tegra194-cbb.c
1678
writel(1, priv->regs + ERRLOGGER_0_STALLEN_0);
drivers/soc/tegra/cbb/tegra194-cbb.c
1679
writel(1, priv->regs + ERRLOGGER_1_STALLEN_0);
drivers/soc/tegra/cbb/tegra194-cbb.c
1680
writel(1, priv->regs + ERRLOGGER_2_STALLEN_0);
drivers/soc/tegra/cbb/tegra194-cbb.c
1687
writel(1, priv->regs + ERRLOGGER_0_ERRCLR_0);
drivers/soc/tegra/cbb/tegra194-cbb.c
1688
writel(1, priv->regs + ERRLOGGER_1_ERRCLR_0);
drivers/soc/tegra/cbb/tegra194-cbb.c
1689
writel(1, priv->regs + ERRLOGGER_2_ERRCLR_0);
drivers/soc/tegra/cbb/tegra194-cbb.c
1711
writel(0xffffffff, addr + DMAAPB_X_RAW_INTERRUPT_STATUS);
drivers/soc/tegra/cbb/tegra234-cbb.c
229
writel(priv->fabric->err_intr_enbl, addr + FABRIC_EN_CFG_INTERRUPT_ENABLE_0_0);
drivers/soc/tegra/cbb/tegra234-cbb.c
237
writel(0, priv->mon + FABRIC_MN_INITIATOR_ERR_FORCE_0);
drivers/soc/tegra/cbb/tegra234-cbb.c
239
writel(priv->fabric->err_status_clr, priv->mon + FABRIC_MN_INITIATOR_ERR_STATUS_0);
drivers/soc/tegra/cbb/tegra234-cbb.c
258
writel(0x1, cbb->regs + cbb->fabric->off_mask_erd);
drivers/soc/tegra/cbb/tegra234-cbb.c
371
writel(target_id, cbb->regs + notifier + FABRIC_EN_CFG_TARGET_NODE_ADDR_INDEX_0_0);
drivers/soc/tegra/cbb/tegra234-cbb.c
600
writel(mask, cbb->regs + notifier + FABRIC_EN_CFG_ADDR_INDEX_0_0);
drivers/soc/tegra/flowctrl.c
44
writel(value, tegra_flowctrl_base + offset);
drivers/soc/tegra/fuse/fuse-tegra.c
373
writel(reg, base + 0x48);
drivers/soc/tegra/fuse/fuse-tegra.c
381
writel(reg, base + 0x14);
drivers/soc/tegra/pmc.c
2618
writel(value, pmc->wake + WAKE_AOWAKE_CNTRL(SW_WAKE_ID));
drivers/soc/tegra/pmc.c
2632
writel(0x1, pmc->wake + WAKE_AOWAKE_STATUS_W(data->hwirq));
drivers/soc/tegra/pmc.c
2642
writel(value, pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset));
drivers/soc/tegra/pmc.c
2645
writel(!!on, pmc->wake + WAKE_AOWAKE_MASK_W(data->hwirq));
drivers/soc/tegra/pmc.c
2682
writel(value, pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq));
drivers/soc/tegra/pmc.c
3284
writel(value, pmc->wake + offset);
drivers/soc/tegra/pmc.c
3299
writel(value, pmc->wake + offset);
drivers/soc/tegra/pmc.c
4104
writel(value, wake + WAKE_AOWAKE_CTRL);
drivers/soc/tegra/pmc.c
4702
writel(value, pmc->base + pmc->soc->regs->scratch0);
drivers/soc/tegra/pmc.c
4712
writel(saved, pmc->base + pmc->soc->regs->scratch0);
drivers/soc/tegra/pmc.c
543
writel(value, pmc->base + offset);
drivers/soc/tegra/pmc.c
561
writel(value, pmc->scratch + offset);
drivers/soc/ti/k3-ringacc.c
1121
writel(-1, &ring->rt->db);
drivers/soc/ti/k3-ringacc.c
1141
writel(-1 & K3_DMARING_RT_DB_ENTRY_MASK, &ring->rt->db);
drivers/soc/ti/k3-ringacc.c
1146
writel(K3_DMARING_RT_DB_TDOWN_ACK, &ring->rt->db);
drivers/soc/ti/k3-ringacc.c
1170
writel(1, &ring->rt->db);
drivers/soc/ti/k3-ringacc.c
1188
writel(-1, &ring->rt->db);
drivers/soc/ti/k3-ringacc.c
553
writel(db_ring_cnt_cur, &ring->rt->db);
drivers/soc/ti/k3-ringacc.c
942
writel(val, &ring->proxy->control);
drivers/soc/ti/wkup_m3_ipc.c
232
writel(AM33XX_M3_TXEV_ACK,
drivers/soc/ti/wkup_m3_ipc.c
238
writel(AM33XX_M3_TXEV_ENABLE,
drivers/soc/ti/wkup_m3_ipc.c
249
writel(val, m3_ipc->ipc_mem_base +
drivers/soundwire/amd_init.h
19
writel(tmp, mmio + offset);
drivers/soundwire/amd_manager.c
101
writel(AMD_SDW_IRQ_ERROR_MASK, amd_manager->mmio + ACP_SW_ERROR_INTR_MASK);
drivers/soundwire/amd_manager.c
1116
writel(0x01, amd_manager->acp_mmio + ACP_SW_WAKE_EN(amd_manager->instance));
drivers/soundwire/amd_manager.c
1130
writel(val, amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL);
drivers/soundwire/amd_manager.c
1135
writel(0, amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL);
drivers/soundwire/amd_manager.c
114
writel(0x00, amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_MASK_0TO7);
drivers/soundwire/amd_manager.c
115
writel(0x00, amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_MASK_8TO11);
drivers/soundwire/amd_manager.c
116
writel(0x00, amd_manager->mmio + ACP_SW_ERROR_INTR_MASK);
drivers/soundwire/amd_manager.c
1299
writel(1, amd_manager->acp_mmio + ACP_PME_EN);
drivers/soundwire/amd_manager.c
130
writel(frame_size, amd_manager->mmio + ACP_SW_FRAMESIZE);
drivers/soundwire/amd_manager.c
1331
writel(0x00, amd_manager->acp_mmio + ACP_SW_WAKE_EN(amd_manager->instance));
drivers/soundwire/amd_manager.c
1340
writel(val, amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL);
drivers/soundwire/amd_manager.c
1345
writel(0, amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL);
drivers/soundwire/amd_manager.c
143
writel(wake_ctrl, amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_MASK_8TO11);
drivers/soundwire/amd_manager.c
163
writel(sdw_dev_state, amd_manager->acp_mmio + AMD_SDW_DEVICE_STATE);
drivers/soundwire/amd_manager.c
193
writel(intr_cntl1, amd_manager->acp_mmio + ACP_EXTERNAL_INTR_CNTL(ACP_SDW1));
drivers/soundwire/amd_manager.c
241
writel(AMD_SDW_IMM_RES_VALID, amd_manager->mmio + ACP_SW_IMM_CMD_STS);
drivers/soundwire/amd_manager.c
243
writel(upper_data, amd_manager->mmio + ACP_SW_IMM_CMD_UPPER_WORD);
drivers/soundwire/amd_manager.c
244
writel(lower_data, amd_manager->mmio + ACP_SW_IMM_CMD_LOWER_QWORD);
drivers/soundwire/amd_manager.c
256
writel(AMD_SDW_IMM_RES_VALID, amd_manager->mmio + ACP_SW_IMM_CMD_STS);
drivers/soundwire/amd_manager.c
35
writel(AMD_SDW_ENABLE, amd_manager->mmio + ACP_SW_EN);
drivers/soundwire/amd_manager.c
42
writel(AMD_SDW_BUS_RESET_REQ, amd_manager->mmio + ACP_SW_BUS_RESET_CTRL);
drivers/soundwire/amd_manager.c
48
writel(AMD_SDW_BUS_RESET_CLEAR_REQ, amd_manager->mmio + ACP_SW_BUS_RESET_CTRL);
drivers/soundwire/amd_manager.c
513
writel(dpn_frame_fmt, amd_manager->mmio + frame_fmt_reg);
drivers/soundwire/amd_manager.c
565
writel(AMD_SDW_SSP_COUNTER_VAL, amd_manager->mmio + ACP_SW_SSP_COUNTER);
drivers/soundwire/amd_manager.c
57
writel(AMD_SDW_DISABLE, amd_manager->mmio + ACP_SW_EN);
drivers/soundwire/amd_manager.c
571
writel(dpn_frame_fmt, amd_manager->mmio + frame_fmt_reg);
drivers/soundwire/amd_manager.c
574
writel(dpn_sampleinterval, amd_manager->mmio + sample_int_reg);
drivers/soundwire/amd_manager.c
578
writel(dpn_hctrl, amd_manager->mmio + hctrl_dp0_reg);
drivers/soundwire/amd_manager.c
582
writel(dpn_offsetctrl, amd_manager->mmio + offset_reg);
drivers/soundwire/amd_manager.c
590
writel(dpn_lanectrl, amd_manager->mmio + lane_ctrl_ch_en_reg);
drivers/soundwire/amd_manager.c
633
writel(dpn_ch_enable, amd_manager->mmio + lane_ctrl_ch_en_reg);
drivers/soundwire/amd_manager.c
635
writel(0, amd_manager->mmio + lane_ctrl_ch_en_reg);
drivers/soundwire/amd_manager.c
66
writel(AMD_SDW_ENABLE, amd_manager->mmio + ACP_SW_EN);
drivers/soundwire/amd_manager.c
75
writel(AMD_SDW_DISABLE, amd_manager->mmio + ACP_SW_EN);
drivers/soundwire/amd_manager.c
866
writel(0, amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_MASK_0TO7);
drivers/soundwire/amd_manager.c
867
writel(0, amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_MASK_8TO11);
drivers/soundwire/amd_manager.c
881
writel(AMD_SDW_IRQ_MASK_0TO7, amd_manager->mmio +
drivers/soundwire/amd_manager.c
883
writel(AMD_SDW_IRQ_MASK_8TO11, amd_manager->mmio +
drivers/soundwire/amd_manager.c
923
writel(0x00, amd_manager->acp_mmio + ACP_SW_WAKE_EN(amd_manager->instance));
drivers/soundwire/amd_manager.c
924
writel(0x00, amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_8TO11);
drivers/soundwire/amd_manager.c
952
writel(0x00, amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_8TO11);
drivers/soundwire/amd_manager.c
953
writel(0x00, amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_0TO7);
drivers/soundwire/amd_manager.c
97
writel(AMD_SDW_IRQ_MASK_0TO7, amd_manager->mmio +
drivers/soundwire/amd_manager.c
99
writel(AMD_SDW_IRQ_MASK_8TO11, amd_manager->mmio +
drivers/soundwire/cadence_master.c
213
writel(value, cdns->registers + offset);
drivers/soundwire/cadence_master.c
262
writel(value, cdns->registers + offset);
drivers/soundwire/intel.c
42
writel(value, base + offset);
drivers/soundwire/intel.c
48
writel(value, base + offset);
drivers/soundwire/intel.h
114
writel(value, base + offset);
drivers/soundwire/qcom.c
381
writel(val, ctrl->mmio + reg);
drivers/spi/spi-amd.c
153
writel(val, ((u8 __iomem *)amd_spi->io_remap_addr + idx));
drivers/spi/spi-amlogic-spifc-a1.c
119
writel(SPIFC_A1_USER_REQUEST_ENABLE,
drivers/spi/spi-amlogic-spifc-a1.c
134
writel(SPIFC_A1_DBUF_AUTO_UPDATE_ADDR,
drivers/spi/spi-amlogic-spifc-a1.c
151
writel(SPIFC_A1_DBUF_DIR | SPIFC_A1_DBUF_AUTO_UPDATE_ADDR,
drivers/spi/spi-amlogic-spifc-a1.c
157
writel(data, spifc->base + SPIFC_A1_DBUF_DATA_REG);
drivers/spi/spi-amlogic-spifc-a1.c
163
writel(0, spifc->base + SPIFC_A1_USER_CTRL0_REG);
drivers/spi/spi-amlogic-spifc-a1.c
164
writel(0, spifc->base + SPIFC_A1_USER_CTRL1_REG);
drivers/spi/spi-amlogic-spifc-a1.c
165
writel(0, spifc->base + SPIFC_A1_USER_CTRL2_REG);
drivers/spi/spi-amlogic-spifc-a1.c
166
writel(0, spifc->base + SPIFC_A1_USER_CTRL3_REG);
drivers/spi/spi-amlogic-spifc-a1.c
177
writel(val, spifc->base + SPIFC_A1_USER_CTRL1_REG);
drivers/spi/spi-amlogic-spifc-a1.c
185
writel(addr, spifc->base + SPIFC_A1_USER_ADDR_REG);
drivers/spi/spi-amlogic-spifc-a1.c
190
writel(val, spifc->base + SPIFC_A1_USER_CTRL1_REG);
drivers/spi/spi-amlogic-spifc-a1.c
200
writel(val, spifc->base + SPIFC_A1_USER_CTRL2_REG);
drivers/spi/spi-amlogic-spifc-a1.c
213
writel(val, spifc->base + SPIFC_A1_USER_CTRL3_REG);
drivers/spi/spi-amlogic-spifc-a1.c
234
writel(val, spifc->base + SPIFC_A1_USER_CTRL1_REG);
drivers/spi/spi-amlogic-spifc-a1.c
279
writel(0, spifc->base + SPIFC_A1_USER_DBUF_ADDR_REG);
drivers/spi/spi-amlogic-spifc-a1.c
307
writel(regv, spifc->base + SPIFC_A1_AHB_REQ_CTRL_REG);
drivers/spi/spi-amlogic-spifc-a1.c
311
writel(regv, spifc->base + SPIFC_A1_AHB_CTRL_REG);
drivers/spi/spi-amlogic-spifc-a1.c
313
writel(SPIFC_A1_ACTIMING0_VAL, spifc->base + SPIFC_A1_ACTIMING0_REG);
drivers/spi/spi-amlogic-spifc-a1.c
315
writel(0, spifc->base + SPIFC_A1_USER_DBUF_ADDR_REG);
drivers/spi/spi-armada-3700.c
123
writel(data, a3700_spi->base + offset);
drivers/spi/spi-aspeed-smc.c
1185
writel(fread_timing_val, aspi->regs + data->timing);
drivers/spi/spi-aspeed-smc.c
1211
writel(fread_timing_val, aspi->regs + data->timing);
drivers/spi/spi-aspeed-smc.c
137
writel(ctl, chip->ctl);
drivers/spi/spi-aspeed-smc.c
1389
writel(ctl_val, chip->ctl);
drivers/spi/spi-aspeed-smc.c
1418
writel(tv, chip->ctl);
drivers/spi/spi-aspeed-smc.c
1449
writel(chip->ctl_val[ASPEED_SPI_READ], chip->ctl);
drivers/spi/spi-aspeed-smc.c
146
writel(ctl, chip->ctl);
drivers/spi/spi-aspeed-smc.c
149
writel(ctl, chip->ctl);
drivers/spi/spi-aspeed-smc.c
1513
writel(fread_timing_val, TIMING_REG_AST2600(chip));
drivers/spi/spi-aspeed-smc.c
1529
writel(fread_timing_val, TIMING_REG_AST2600(chip));
drivers/spi/spi-aspeed-smc.c
1554
writel(fread_timing_val, TIMING_REG_AST2600(chip));
drivers/spi/spi-aspeed-smc.c
157
writel(ctl, chip->ctl);
drivers/spi/spi-aspeed-smc.c
160
writel(chip->ctl_val[ASPEED_SPI_READ], chip->ctl);
drivers/spi/spi-aspeed-smc.c
353
writel(addr_mode, aspi->regs + CE_CTRL_REG);
drivers/spi/spi-aspeed-smc.c
354
writel(ctl_val, chip->ctl);
drivers/spi/spi-aspeed-smc.c
371
writel(addr_mode_backup, aspi->regs + CE_CTRL_REG);
drivers/spi/spi-aspeed-smc.c
372
writel(chip->ctl_val[ASPEED_SPI_READ], chip->ctl);
drivers/spi/spi-aspeed-smc.c
425
writel(seg_val, seg_reg);
drivers/spi/spi-aspeed-smc.c
434
writel(seg_val_backup, seg_reg);
drivers/spi/spi-aspeed-smc.c
741
writel(addr_mode, aspi->regs + CE_CTRL_REG);
drivers/spi/spi-aspeed-smc.c
752
writel(chip->ctl_val[ASPEED_SPI_READ], chip->ctl);
drivers/spi/spi-aspeed-smc.c
797
writel(reg, aspi->regs + CONFIG_REG);
drivers/spi/spi-aspeed-smc.c
809
writel(reg, aspi->regs + CONFIG_REG);
drivers/spi/spi-bcm2835.c
214
writel(val, bs->regs + reg);
drivers/spi/spi-bcm2835aux.c
151
writel(val, bs->regs + reg);
drivers/spi/spi-cadence-quadspi.c
1000
writel(0x0, reg_base + CQSPI_REG_VERSAL_DMA_DST_I_DIS);
drivers/spi/spi-cadence-quadspi.c
1003
writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
drivers/spi/spi-cadence-quadspi.c
1010
writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
drivers/spi/spi-cadence-quadspi.c
1039
writel(reg, reg_base + CQSPI_REG_WR_INSTR);
drivers/spi/spi-cadence-quadspi.c
1041
writel(reg, reg_base + CQSPI_REG_RD_INSTR);
drivers/spi/spi-cadence-quadspi.c
1057
writel(reg, reg_base + CQSPI_REG_WR_COMPLETION_CTRL);
drivers/spi/spi-cadence-quadspi.c
1069
writel(reg, reg_base + CQSPI_REG_SIZE);
drivers/spi/spi-cadence-quadspi.c
1088
writel(to_addr, reg_base + CQSPI_REG_INDIRECTWRSTARTADDR);
drivers/spi/spi-cadence-quadspi.c
1089
writel(remaining, reg_base + CQSPI_REG_INDIRECTWRBYTES);
drivers/spi/spi-cadence-quadspi.c
1092
writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS);
drivers/spi/spi-cadence-quadspi.c
1094
writel(CQSPI_IRQ_MASK_WR, reg_base + CQSPI_REG_IRQMASK);
drivers/spi/spi-cadence-quadspi.c
1097
writel(CQSPI_REG_INDIRECTWR_START_MASK,
drivers/spi/spi-cadence-quadspi.c
1159
writel(0, reg_base + CQSPI_REG_IRQMASK);
drivers/spi/spi-cadence-quadspi.c
1162
writel(CQSPI_REG_INDIRECTWR_DONE_MASK, reg_base + CQSPI_REG_INDIRECTWR);
drivers/spi/spi-cadence-quadspi.c
1170
writel(0, reg_base + CQSPI_REG_IRQMASK);
drivers/spi/spi-cadence-quadspi.c
1173
writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
drivers/spi/spi-cadence-quadspi.c
1204
writel(reg, reg_base + CQSPI_REG_CONFIG);
drivers/spi/spi-cadence-quadspi.c
1247
writel(reg, iobase + CQSPI_REG_DELAY);
drivers/spi/spi-cadence-quadspi.c
1270
writel(reg, reg_base + CQSPI_REG_CONFIG);
drivers/spi/spi-cadence-quadspi.c
1293
writel(reg, reg_base + CQSPI_REG_READCAPTURE);
drivers/spi/spi-cadence-quadspi.c
1639
writel(0, cqspi->iobase + CQSPI_REG_REMAP);
drivers/spi/spi-cadence-quadspi.c
1642
writel(0, cqspi->iobase + CQSPI_REG_IRQMASK);
drivers/spi/spi-cadence-quadspi.c
1646
writel(cqspi->fifo_depth / 2, cqspi->iobase + CQSPI_REG_SRAMPARTITION);
drivers/spi/spi-cadence-quadspi.c
1648
writel(cqspi->trigger_address,
drivers/spi/spi-cadence-quadspi.c
1652
writel(cqspi->fifo_depth * cqspi->fifo_width / 2,
drivers/spi/spi-cadence-quadspi.c
1655
writel(cqspi->fifo_depth * cqspi->fifo_width / 8,
drivers/spi/spi-cadence-quadspi.c
1661
writel(0, cqspi->iobase + CQSPI_REG_WR_PROT_CTRL);
drivers/spi/spi-cadence-quadspi.c
1667
writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
drivers/spi/spi-cadence-quadspi.c
1674
writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
drivers/spi/spi-cadence-quadspi.c
1690
writel(U32_MAX, cqspi->iobase + CQSPI_REG_SRAMPARTITION);
drivers/spi/spi-cadence-quadspi.c
367
writel(dma_status, cqspi->iobase +
drivers/spi/spi-cadence-quadspi.c
383
writel(irq_status, cqspi->iobase + CQSPI_REG_IRQSTATUS);
drivers/spi/spi-cadence-quadspi.c
462
writel(reg, reg_base + CQSPI_REG_CMDCTRL);
drivers/spi/spi-cadence-quadspi.c
465
writel(reg, reg_base + CQSPI_REG_CMDCTRL);
drivers/spi/spi-cadence-quadspi.c
498
writel(reg, reg_base + CQSPI_REG_OP_EXT_LOWER);
drivers/spi/spi-cadence-quadspi.c
533
writel(reg, reg_base + CQSPI_REG_CONFIG);
drivers/spi/spi-cadence-quadspi.c
571
writel(rdreg, reg_base + CQSPI_REG_RD_INSTR);
drivers/spi/spi-cadence-quadspi.c
594
writel(op->addr.val, reg_base + CQSPI_REG_CMDADDRESS);
drivers/spi/spi-cadence-quadspi.c
616
writel(0, reg_base + CQSPI_REG_CMDCTRL);
drivers/spi/spi-cadence-quadspi.c
646
writel(reg, reg_base + CQSPI_REG_RD_INSTR);
drivers/spi/spi-cadence-quadspi.c
661
writel(op->addr.val, reg_base + CQSPI_REG_CMDADDRESS);
drivers/spi/spi-cadence-quadspi.c
672
writel(data, reg_base + CQSPI_REG_CMDWRITEDATALOWER);
drivers/spi/spi-cadence-quadspi.c
678
writel(data, reg_base + CQSPI_REG_CMDWRITEDATAUPPER);
drivers/spi/spi-cadence-quadspi.c
685
writel(0, reg_base + CQSPI_REG_CMDCTRL);
drivers/spi/spi-cadence-quadspi.c
722
writel(reg, reg_base + CQSPI_REG_RD_INSTR);
drivers/spi/spi-cadence-quadspi.c
728
writel(reg, reg_base + CQSPI_REG_SIZE);
drivers/spi/spi-cadence-quadspi.c
751
writel(from_addr, reg_base + CQSPI_REG_INDIRECTRDSTARTADDR);
drivers/spi/spi-cadence-quadspi.c
752
writel(remaining, reg_base + CQSPI_REG_INDIRECTRDBYTES);
drivers/spi/spi-cadence-quadspi.c
755
writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS);
drivers/spi/spi-cadence-quadspi.c
766
writel(CQSPI_IRQ_MASK_RD_SLOW_SRAM, reg_base + CQSPI_REG_IRQMASK);
drivers/spi/spi-cadence-quadspi.c
768
writel(CQSPI_IRQ_MASK_RD, reg_base + CQSPI_REG_IRQMASK);
drivers/spi/spi-cadence-quadspi.c
770
writel(0, reg_base + CQSPI_REG_IRQMASK);
drivers/spi/spi-cadence-quadspi.c
773
writel(CQSPI_REG_INDIRECTRD_START_MASK,
drivers/spi/spi-cadence-quadspi.c
833
writel(0, reg_base + CQSPI_REG_IRQMASK);
drivers/spi/spi-cadence-quadspi.c
836
writel(CQSPI_REG_INDIRECTRD_DONE_MASK, reg_base + CQSPI_REG_INDIRECTRD);
drivers/spi/spi-cadence-quadspi.c
842
writel(0, reg_base + CQSPI_REG_IRQMASK);
drivers/spi/spi-cadence-quadspi.c
845
writel(CQSPI_REG_INDIRECTRD_CANCEL_MASK,
drivers/spi/spi-cadence-quadspi.c
856
writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
drivers/spi/spi-cadence-quadspi.c
861
writel(reg & ~CQSPI_REG_CONFIG_RESET_PIN_FLD_MASK, cqspi->iobase + CQSPI_REG_CONFIG);
drivers/spi/spi-cadence-quadspi.c
863
writel(reg | CQSPI_REG_CONFIG_RESET_PIN_FLD_MASK, cqspi->iobase + CQSPI_REG_CONFIG);
drivers/spi/spi-cadence-quadspi.c
865
writel(reg & ~CQSPI_REG_CONFIG_RESET_PIN_FLD_MASK, cqspi->iobase + CQSPI_REG_CONFIG);
drivers/spi/spi-cadence-quadspi.c
881
writel(reg, reg_base + CQSPI_REG_CONFIG);
drivers/spi/spi-cadence-quadspi.c
912
writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
drivers/spi/spi-cadence-quadspi.c
922
writel(from_addr, reg_base + CQSPI_REG_INDIRECTRDSTARTADDR);
drivers/spi/spi-cadence-quadspi.c
923
writel(bytes_to_dma, reg_base + CQSPI_REG_INDIRECTRDBYTES);
drivers/spi/spi-cadence-quadspi.c
924
writel(CQSPI_REG_VERSAL_ADDRRANGE_WIDTH_VAL,
drivers/spi/spi-cadence-quadspi.c
928
writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS);
drivers/spi/spi-cadence-quadspi.c
931
writel(CQSPI_REG_VERSAL_DMA_DST_DONE_MASK,
drivers/spi/spi-cadence-quadspi.c
935
writel(CQSPI_REG_VERSAL_DMA_VAL, reg_base + CQSPI_REG_DMA);
drivers/spi/spi-cadence-quadspi.c
938
writel(lower_32_bits(dma_addr),
drivers/spi/spi-cadence-quadspi.c
940
writel(upper_32_bits(dma_addr),
drivers/spi/spi-cadence-quadspi.c
944
writel(cqspi->trigger_address, reg_base +
drivers/spi/spi-cadence-quadspi.c
948
writel(bytes_to_dma, reg_base + CQSPI_REG_VERSAL_DMA_DST_SIZE);
drivers/spi/spi-cadence-quadspi.c
951
writel(CQSPI_REG_VERSAL_DMA_DST_CTRL_VAL,
drivers/spi/spi-cadence-quadspi.c
954
writel(CQSPI_REG_INDIRECTRD_START_MASK,
drivers/spi/spi-cadence-quadspi.c
966
writel(0x0, cqspi->iobase + CQSPI_REG_VERSAL_DMA_DST_I_DIS);
drivers/spi/spi-cadence-quadspi.c
969
writel(CQSPI_REG_INDIRECTRD_DONE_MASK,
drivers/spi/spi-cadence-quadspi.c
977
writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
drivers/spi/spi-cadence-xspi.c
1054
writel(xfer_control, cdns_xspi->xferbase + MRVL_XFER_FUNC_CTRL);
drivers/spi/spi-cadence-xspi.c
1120
writel(xfer_control, cdns_xspi->xferbase + MRVL_XFER_FUNC_CTRL);
drivers/spi/spi-cadence-xspi.c
390
writel(dll_cntrl, cdns_xspi->iobase +
drivers/spi/spi-cadence-xspi.c
406
writel(cdns_xspi->driver_data->dll_phy_ctrl,
drivers/spi/spi-cadence-xspi.c
408
writel(cdns_xspi->driver_data->ctb_rfile_phy_ctrl,
drivers/spi/spi-cadence-xspi.c
410
writel(cdns_xspi->driver_data->rfile_phy_tsel,
drivers/spi/spi-cadence-xspi.c
412
writel(cdns_xspi->driver_data->rfile_phy_dq_timing,
drivers/spi/spi-cadence-xspi.c
414
writel(cdns_xspi->driver_data->rfile_phy_dqs_timing,
drivers/spi/spi-cadence-xspi.c
416
writel(cdns_xspi->driver_data->rfile_phy_gate_lpbk_ctrl,
drivers/spi/spi-cadence-xspi.c
418
writel(cdns_xspi->driver_data->rfile_phy_dll_master_ctrl,
drivers/spi/spi-cadence-xspi.c
420
writel(cdns_xspi->driver_data->rfile_phy_dll_slave_ctrl,
drivers/spi/spi-cadence-xspi.c
453
writel(clk_reg,
drivers/spi/spi-cadence-xspi.c
464
writel(clk_reg,
drivers/spi/spi-cadence-xspi.c
485
writel(cmd_regs[5], cdns_xspi->iobase + CDNS_XSPI_CMD_REG_5);
drivers/spi/spi-cadence-xspi.c
486
writel(cmd_regs[4], cdns_xspi->iobase + CDNS_XSPI_CMD_REG_4);
drivers/spi/spi-cadence-xspi.c
487
writel(cmd_regs[3], cdns_xspi->iobase + CDNS_XSPI_CMD_REG_3);
drivers/spi/spi-cadence-xspi.c
488
writel(cmd_regs[2], cdns_xspi->iobase + CDNS_XSPI_CMD_REG_2);
drivers/spi/spi-cadence-xspi.c
489
writel(cmd_regs[1], cdns_xspi->iobase + CDNS_XSPI_CMD_REG_1);
drivers/spi/spi-cadence-xspi.c
490
writel(cmd_regs[0], cdns_xspi->iobase + CDNS_XSPI_CMD_REG_0);
drivers/spi/spi-cadence-xspi.c
539
writel(intr_enable, cdns_xspi->iobase + CDNS_XSPI_INTR_ENABLE_REG);
drivers/spi/spi-cadence-xspi.c
549
writel(irq_status, cdns_xspi->iobase + CDNS_XSPI_INTR_STATUS_REG);
drivers/spi/spi-cadence-xspi.c
556
writel(intr_enable, cdns_xspi->iobase + CDNS_XSPI_INTR_ENABLE_REG);
drivers/spi/spi-cadence-xspi.c
688
writel(FIELD_PREP(CDNS_XSPI_CTRL_WORK_MODE, CDNS_XSPI_WORK_MODE_STIG),
drivers/spi/spi-cadence-xspi.c
858
writel(irq_status, cdns_xspi->iobase + CDNS_XSPI_INTR_STATUS_REG);
drivers/spi/spi-cadence-xspi.c
881
writel(irq_status,
drivers/spi/spi-clps711x.c
64
writel(data | SYNCIO_FRMLEN(hw->bpw) | SYNCIO_TXFRMEN, hw->syncio);
drivers/spi/spi-clps711x.c
83
writel(data | SYNCIO_FRMLEN(hw->bpw) | SYNCIO_TXFRMEN,
drivers/spi/spi-dw-mmio.c
115
writel(0, dwsmscc->spi_mst + MSCC_SPI_MST_SW_MODE);
drivers/spi/spi-dw-mmio.c
90
writel(sw_mode, dwsmscc->spi_mst + MSCC_SPI_MST_SW_MODE);
drivers/spi/spi-ep93xx.c
169
writel(div_cpsr, espi->mmio + SSPCPSR);
drivers/spi/spi-ep93xx.c
170
writel(cr0, espi->mmio + SSPCR0);
drivers/spi/spi-ep93xx.c
190
writel(val, espi->mmio + SSPDR);
drivers/spi/spi-ep93xx.c
445
writel(0, espi->mmio + SSPICR);
drivers/spi/spi-ep93xx.c
471
writel(val, espi->mmio + SSPCR1);
drivers/spi/spi-ep93xx.c
509
writel(val, espi->mmio + SSPCR1);
drivers/spi/spi-ep93xx.c
555
writel(val, espi->mmio + SSPCR1);
drivers/spi/spi-ep93xx.c
567
writel(val, espi->mmio + SSPCR1);
drivers/spi/spi-ep93xx.c
690
writel(0, espi->mmio + SSPCR1);
drivers/spi/spi-fsl-lpspi.c
183
writel(val, fsl_lpspi->base + IMX7ULP_TDR); \
drivers/spi/spi-fsl-lpspi.c
196
writel(enable, fsl_lpspi->base + IMX7ULP_IER);
drivers/spi/spi-fsl-lpspi.c
270
writel(temp, fsl_lpspi->base + IMX7ULP_TCR);
drivers/spi/spi-fsl-lpspi.c
314
writel(temp, fsl_lpspi->base + IMX7ULP_TCR);
drivers/spi/spi-fsl-lpspi.c
329
writel(temp, fsl_lpspi->base + IMX7ULP_FCR);
drivers/spi/spi-fsl-lpspi.c
368
writel(scldiv | (scldiv << 8) | ((scldiv >> 1) << 16),
drivers/spi/spi-fsl-lpspi.c
448
writel(temp, fsl_lpspi->base + IMX7ULP_CFGR1);
drivers/spi/spi-fsl-lpspi.c
452
writel(temp, fsl_lpspi->base + IMX7ULP_CR);
drivers/spi/spi-fsl-lpspi.c
457
writel(temp, fsl_lpspi->base + IMX7ULP_DER);
drivers/spi/spi-fsl-lpspi.c
531
writel(0, fsl_lpspi->base + IMX7ULP_IER);
drivers/spi/spi-fsl-lpspi.c
534
writel(CR_RRF | CR_RTF, fsl_lpspi->base + IMX7ULP_CR);
drivers/spi/spi-fsl-lpspi.c
535
writel(SR_CLEAR_MASK, fsl_lpspi->base + IMX7ULP_SR);
drivers/spi/spi-fsl-lpspi.c
588
writel(temp, fsl_lpspi->base + IMX7ULP_CR);
drivers/spi/spi-fsl-lpspi.c
591
writel(SR_CLEAR_MASK, fsl_lpspi->base + IMX7ULP_SR);
drivers/spi/spi-fsl-lpspi.c
839
writel(SR_FCF, fsl_lpspi->base + IMX7ULP_SR);
drivers/spi/spi-fsl-lpspi.c
845
writel(SR_FCF, fsl_lpspi->base + IMX7ULP_SR);
drivers/spi/spi-geni-qcom.c
1000
writel(m_irq, se->base + SE_GENI_M_IRQ_CLEAR);
drivers/spi/spi-geni-qcom.c
111
writel(SPI_SLAVE_EN, se->base + SE_SPI_SLAVE_EN);
drivers/spi/spi-geni-qcom.c
112
writel(GENI_IO_MUX_0_EN, se->base + GENI_OUTPUT_CTRL);
drivers/spi/spi-geni-qcom.c
113
writel(START_TRIGGER, se->base + SE_GENI_CFG_SEQ_START);
drivers/spi/spi-geni-qcom.c
158
writel(0, se->base + SE_GENI_TX_WATERMARK_REG);
drivers/spi/spi-geni-qcom.c
198
writel(1, se->base + SE_DMA_TX_FSM_RST);
drivers/spi/spi-geni-qcom.c
207
writel(1, se->base + SE_DMA_RX_FSM_RST);
drivers/spi/spi-geni-qcom.c
302
writel(word_len, se->base + SE_SPI_WORD_LEN);
drivers/spi/spi-geni-qcom.c
332
writel(clk_sel, se->base + SE_GENI_CLK_SEL);
drivers/spi/spi-geni-qcom.c
333
writel(m_clk_cfg, se->base + GENI_SER_M_CLK_CFG);
drivers/spi/spi-geni-qcom.c
359
writel((spi_slv->mode & SPI_LOOP) ? LOOPBACK_ENABLE : 0, se->base + SE_SPI_LOOPBACK);
drivers/spi/spi-geni-qcom.c
361
writel(chipselect, se->base + SE_SPI_DEMUX_SEL);
drivers/spi/spi-geni-qcom.c
363
writel((spi_slv->mode & SPI_CPHA) ? CPHA : 0, se->base + SE_SPI_CPHA);
drivers/spi/spi-geni-qcom.c
365
writel((spi_slv->mode & SPI_CPOL) ? CPOL : 0, se->base + SE_SPI_CPOL);
drivers/spi/spi-geni-qcom.c
367
writel((spi_slv->mode & SPI_CS_HIGH) ? BIT(chipselect) : 0, se->base + SE_SPI_DEMUX_OUTPUT_INV);
drivers/spi/spi-geni-qcom.c
666
writel(0, se->base + SE_SPI_LOOPBACK);
drivers/spi/spi-geni-qcom.c
667
writel(0, se->base + SE_SPI_DEMUX_SEL);
drivers/spi/spi-geni-qcom.c
668
writel(0, se->base + SE_SPI_CPHA);
drivers/spi/spi-geni-qcom.c
669
writel(0, se->base + SE_SPI_CPOL);
drivers/spi/spi-geni-qcom.c
670
writel(0, se->base + SE_SPI_DEMUX_OUTPUT_INV);
drivers/spi/spi-geni-qcom.c
679
writel(spi_tx_cfg, se->base + SE_SPI_TRANS_CFG);
drivers/spi/spi-geni-qcom.c
711
writel(0, se->base + SE_GENI_TX_WATERMARK_REG);
drivers/spi/spi-geni-qcom.c
733
writel(0, se->base + SE_GENI_TX_WATERMARK_REG);
drivers/spi/spi-geni-qcom.c
827
writel(len, se->base + SE_SPI_TX_TRANS_LEN);
drivers/spi/spi-geni-qcom.c
832
writel(len, se->base + SE_SPI_RX_TRANS_LEN);
drivers/spi/spi-geni-qcom.c
873
writel(mas->tx_wm, se->base + SE_GENI_TX_WATERMARK_REG);
drivers/spi/spi-geni-qcom.c
950
writel(0, se->base + SE_GENI_TX_WATERMARK_REG);
drivers/spi/spi-geni-qcom.c
965
writel(dma_tx_status, se->base + SE_DMA_TX_IRQ_CLR);
drivers/spi/spi-geni-qcom.c
967
writel(dma_rx_status, se->base + SE_DMA_RX_IRQ_CLR);
drivers/spi/spi-gxp.c
117
writel(value, reg_base + OFFSET_SPIMCFG);
drivers/spi/spi-gxp.c
119
writel(0, reg_base + OFFSET_SPIADDR);
drivers/spi/spi-gxp.c
173
writel(value, reg_base + OFFSET_SPIMCFG);
drivers/spi/spi-gxp.c
175
writel(op->addr.val, reg_base + OFFSET_SPIADDR);
drivers/spi/spi-gxp.c
79
writel(value, reg_base + OFFSET_SPIMCFG);
drivers/spi/spi-gxp.c
81
writel(0, reg_base + OFFSET_SPIADDR);
drivers/spi/spi-hisi-kunpeng.c
207
writel(0, hs->regs + HISI_SPI_ENR);
drivers/spi/spi-hisi-kunpeng.c
208
writel(IMR_MASK, hs->regs + HISI_SPI_IMR);
drivers/spi/spi-hisi-kunpeng.c
209
writel(ICR_MASK, hs->regs + HISI_SPI_ICR);
drivers/spi/spi-hisi-kunpeng.c
269
writel(txw, hs->regs + HISI_SPI_DIN);
drivers/spi/spi-hisi-kunpeng.c
326
writel(FIELD_PREP(FIFOC_TX_MASK, HISI_SPI_TX_64_OR_LESS) |
drivers/spi/spi-hisi-kunpeng.c
385
writel(cr, hs->regs + HISI_SPI_CR);
drivers/spi/spi-hisi-kunpeng.c
402
writel(~(u32)IMR_MASK, hs->regs + HISI_SPI_IMR);
drivers/spi/spi-hisi-kunpeng.c
403
writel(1, hs->regs + HISI_SPI_ENR);
drivers/spi/spi-hisi-sfc-v3xx.c
309
writel(op->addr.val, host->regbase + HISI_SFC_V3XX_CMD_ADDR);
drivers/spi/spi-hisi-sfc-v3xx.c
310
writel(op->cmd.opcode, host->regbase + HISI_SFC_V3XX_CMD_INS);
drivers/spi/spi-hisi-sfc-v3xx.c
312
writel(config, host->regbase + HISI_SFC_V3XX_CMD_CFG);
drivers/spi/spi-hisi-sfc-v3xx.c
86
writel(0, host->regbase + HISI_SFC_V3XX_INT_MASK);
drivers/spi/spi-hisi-sfc-v3xx.c
91
writel(HISI_SFC_V3XX_INT_MASK_ALL, host->regbase + HISI_SFC_V3XX_INT_MASK);
drivers/spi/spi-hisi-sfc-v3xx.c
96
writel(HISI_SFC_V3XX_INT_MASK_ALL, host->regbase + HISI_SFC_V3XX_INT_CLR);
drivers/spi/spi-img-spfi.c
111
writel(val, spfi->regs + reg);
drivers/spi/spi-imx.c
1019
writel(reg, spi_imx->base + MXC_CSPICTRL);
drivers/spi/spi-imx.c
1031
writel(1, spi_imx->base + MXC_RESET);
drivers/spi/spi-imx.c
1054
writel(val, spi_imx->base + MXC_CSPIINT);
drivers/spi/spi-imx.c
1063
writel(reg, spi_imx->base + MXC_CSPICTRL);
drivers/spi/spi-imx.c
1089
writel(reg, spi_imx->base + MXC_CSPICTRL);
drivers/spi/spi-imx.c
1101
writel(1, spi_imx->base + MXC_RESET);
drivers/spi/spi-imx.c
1243
writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
drivers/spi/spi-imx.c
196
writel(val, spi_imx->base + MXC_CSPITXDATA); \
drivers/spi/spi-imx.c
1963
writel(spi_imx->dma_data[i].cmd_word, spi_imx->base + MX51_ECSPI_CTRL);
drivers/spi/spi-imx.c
2408
writel(0, spi_imx->base + MXC_CSPICTRL);
drivers/spi/spi-imx.c
426
writel(val, spi_imx->base + MXC_CSPITXDATA);
drivers/spi/spi-imx.c
454
writel(val, spi_imx->base + MXC_CSPITXDATA);
drivers/spi/spi-imx.c
510
writel(val, spi_imx->base + MXC_CSPITXDATA);
drivers/spi/spi-imx.c
564
writel(val, spi_imx->base + MX51_ECSPI_INT);
drivers/spi/spi-imx.c
574
writel(reg, spi_imx->base + MX51_ECSPI_DMA);
drivers/spi/spi-imx.c
578
writel(reg, spi_imx->base + MX51_ECSPI_CTRL);
drivers/spi/spi-imx.c
588
writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
drivers/spi/spi-imx.c
629
writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
drivers/spi/spi-imx.c
636
writel(testreg, spi_imx->base + MX51_ECSPI_TESTREG);
drivers/spi/spi-imx.c
669
writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG);
drivers/spi/spi-imx.c
719
writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG);
drivers/spi/spi-imx.c
759
writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
drivers/spi/spi-imx.c
801
writel(FIELD_PREP(MX51_ECSPI_PERIOD_MASK, word_delay_sck),
drivers/spi/spi-imx.c
817
writel(MX51_ECSPI_DMA_RX_WML(spi_imx->wml - 1) |
drivers/spi/spi-imx.c
875
writel(val, spi_imx->base + MXC_CSPIINT);
drivers/spi/spi-imx.c
884
writel(reg, spi_imx->base + MXC_CSPICTRL);
drivers/spi/spi-imx.c
924
writel(reg, spi_imx->base + MXC_CSPICTRL);
drivers/spi/spi-imx.c
931
writel(reg, spi_imx->base + MX31_CSPI_TESTREG);
drivers/spi/spi-imx.c
938
writel(MX31_DMAREG_RH_DEN | MX31_DMAREG_TH_DEN,
drivers/spi/spi-imx.c
979
writel(val, spi_imx->base + MXC_CSPIINT);
drivers/spi/spi-imx.c
988
writel(reg, spi_imx->base + MXC_CSPICTRL);
drivers/spi/spi-intel.c
1134
writel(val, ispi->base + HSFSTS_CTL);
drivers/spi/spi-intel.c
1168
writel(val, ispi->sregs + SSFSTS_CTL);
drivers/spi/spi-intel.c
359
writel(opcode, ispi->sregs + OPMENU0);
drivers/spi/spi-intel.c
361
writel(optype << 16 | preop, ispi->sregs + PREOP_OPTYPE);
drivers/spi/spi-intel.c
381
writel(val, ispi->base + HSFSTS_CTL);
drivers/spi/spi-intel.c
443
writel(val, ispi->sregs + SSFSTS_CTL);
drivers/spi/spi-intel.c
476
writel(addr, ispi->base + FADDR);
drivers/spi/spi-intel.c
518
writel(opcode, ispi->sregs + PREOP_OPTYPE);
drivers/spi/spi-intel.c
538
writel(addr, ispi->base + FADDR);
drivers/spi/spi-intel.c
575
writel(addr, ispi->base + FADDR);
drivers/spi/spi-intel.c
583
writel(val, ispi->base + HSFSTS_CTL);
drivers/spi/spi-intel.c
632
writel(addr, ispi->base + FADDR);
drivers/spi/spi-intel.c
648
writel(val, ispi->base + HSFSTS_CTL);
drivers/spi/spi-intel.c
684
writel(addr, ispi->base + FADDR);
drivers/spi/spi-intel.c
698
writel(val, ispi->base + HSFSTS_CTL);
drivers/spi/spi-jcore.c
123
writel(tx ? *tx++ : 0, data_reg);
drivers/spi/spi-jcore.c
124
writel(xmit, ctrl_reg);
drivers/spi/spi-jcore.c
65
writel(hw->cs_reg | hw->speed_reg, ctrl_reg);
drivers/spi/spi-meson-spicc.c
1103
writel(0, spicc->base + SPICC_CONREG);
drivers/spi/spi-meson-spicc.c
474
writel(0, spicc->base + SPICC_INTREG);
drivers/spi/spi-meson-spicc.c
725
writel(0, spicc->base + SPICC_INTREG);
drivers/spi/spi-mpfs.c
123
writel(val, spi->regs + reg);
drivers/spi/spi-mt65xx.c
1026
writel(0, mdata->base + SPI_CFG1_REG);
drivers/spi/spi-mt65xx.c
1059
writel(reg_val, mdata->base + SPI_CFG3_IPM_REG);
drivers/spi/spi-mt65xx.c
1126
writel(reg_val, mdata->base + SPI_CMD_REG);
drivers/spi/spi-mt65xx.c
1142
writel(reg_val, mdata->base + SPI_CMD_REG);
drivers/spi/spi-mt65xx.c
291
writel(reg_val, mdata->base + SPI_CMD_REG);
drivers/spi/spi-mt65xx.c
295
writel(reg_val, mdata->base + SPI_CMD_REG);
drivers/spi/spi-mt65xx.c
351
writel(reg_val, mdata->base + SPI_CFG0_REG);
drivers/spi/spi-mt65xx.c
359
writel(reg_val, mdata->base + SPI_CFG1_REG);
drivers/spi/spi-mt65xx.c
436
writel(reg_val, mdata->base + SPI_CMD_REG);
drivers/spi/spi-mt65xx.c
440
writel(mdata->pad_sel[spi_get_chipselect(spi, 0)],
drivers/spi/spi-mt65xx.c
450
writel(reg_val, mdata->base + SPI_CMD_REG);
drivers/spi/spi-mt65xx.c
456
writel(reg_val, mdata->base + SPI_CFG1_REG);
drivers/spi/spi-mt65xx.c
463
writel(reg_val, mdata->base + SPI_CFG1_REG);
drivers/spi/spi-mt65xx.c
497
writel(reg_val, mdata->base + SPI_CMD_REG);
drivers/spi/spi-mt65xx.c
500
writel(reg_val, mdata->base + SPI_CMD_REG);
drivers/spi/spi-mt65xx.c
527
writel(reg_val, mdata->base + SPI_CFG2_REG);
drivers/spi/spi-mt65xx.c
535
writel(reg_val, mdata->base + SPI_CFG0_REG);
drivers/spi/spi-mt65xx.c
563
writel(reg_val, mdata->base + SPI_CFG1_REG);
drivers/spi/spi-mt65xx.c
592
writel(cmd, mdata->base + SPI_CMD_REG);
drivers/spi/spi-mt65xx.c
644
writel((u32)(xfer->tx_dma & MTK_SPI_32BITS_MASK),
drivers/spi/spi-mt65xx.c
648
writel((u32)(xfer->tx_dma >> 32),
drivers/spi/spi-mt65xx.c
654
writel((u32)(xfer->rx_dma & MTK_SPI_32BITS_MASK),
drivers/spi/spi-mt65xx.c
658
writel((u32)(xfer->rx_dma >> 32),
drivers/spi/spi-mt65xx.c
685
writel(reg_val, mdata->base + SPI_TX_DATA_REG);
drivers/spi/spi-mt65xx.c
715
writel(cmd, mdata->base + SPI_CMD_REG);
drivers/spi/spi-mt65xx.c
759
writel(reg_val, mdata->base + SPI_CFG3_IPM_REG);
drivers/spi/spi-mt65xx.c
834
writel(reg_val, mdata->base + SPI_TX_DATA_REG);
drivers/spi/spi-mt65xx.c
868
writel(cmd, mdata->base + SPI_CMD_REG);
drivers/spi/spi-mt65xx.c
948
writel((u32)(mdata->tx_dma & MTK_SPI_32BITS_MASK),
drivers/spi/spi-mt65xx.c
952
writel((u32)(mdata->tx_dma >> 32),
drivers/spi/spi-mt65xx.c
957
writel((u32)(mdata->rx_dma & MTK_SPI_32BITS_MASK),
drivers/spi/spi-mt65xx.c
961
writel((u32)(mdata->rx_dma >> 32),
drivers/spi/spi-mtk-nor.c
137
writel(val, sp->base + reg);
drivers/spi/spi-mtk-nor.c
146
writel(cmd, sp->base + MTK_NOR_REG_CMD);
drivers/spi/spi-mtk-nor.c
160
writel(MTK_NOR_ENABLE_SF_CMD, sp->base + MTK_NOR_REG_WP);
drivers/spi/spi-mtk-nor.c
373
writel(from, sp->base + MTK_NOR_REG_DMA_FADR);
drivers/spi/spi-mtk-nor.c
374
writel(dma_addr, sp->base + MTK_NOR_REG_DMA_DADR);
drivers/spi/spi-mtk-nor.c
375
writel(dma_addr + length, sp->base + MTK_NOR_REG_DMA_END_DADR);
drivers/spi/spi-mtk-nor.c
378
writel(upper_32_bits(dma_addr),
drivers/spi/spi-mtk-nor.c
380
writel(upper_32_bits(dma_addr + length),
drivers/spi/spi-mtk-nor.c
470
writel(val | MTK_NOR_WR_BUF_EN, sp->base + MTK_NOR_REG_CFG2);
drivers/spi/spi-mtk-nor.c
474
writel(val & ~MTK_NOR_WR_BUF_EN, sp->base + MTK_NOR_REG_CFG2);
drivers/spi/spi-mtk-nor.c
498
writel(val, sp->base + MTK_NOR_REG_PP_DATA);
drivers/spi/spi-mtk-nor.c
577
writel(prg_len * BITS_PER_BYTE + sp->caps->extra_dummy_bit,
drivers/spi/spi-mtk-nor.c
580
writel(prg_len * BITS_PER_BYTE, sp->base + MTK_NOR_REG_PRG_CNT);
drivers/spi/spi-mtk-nor.c
679
writel(trx_len * BITS_PER_BYTE, sp->base + MTK_NOR_REG_PRG_CNT);
drivers/spi/spi-mtk-nor.c
746
writel(0, sp->base + MTK_NOR_REG_IRQ_EN);
drivers/spi/spi-mtk-nor.c
747
writel(MTK_NOR_IRQ_MASK, sp->base + MTK_NOR_REG_IRQ_STAT);
drivers/spi/spi-mtk-nor.c
749
writel(MTK_NOR_ENABLE_SF_CMD, sp->base + MTK_NOR_REG_WP);
drivers/spi/spi-mtk-nor.c
763
writel(irq_status, sp->base + MTK_NOR_REG_IRQ_STAT);
drivers/spi/spi-mtk-nor.c
770
writel(0, sp->base + MTK_NOR_REG_IRQ_EN);
drivers/spi/spi-mtk-snfi.c
348
writel(val, snf->nfi_base + reg);
drivers/spi/spi-mtk-snfi.c
363
writel(val, snf->nfi_base + reg);
drivers/spi/spi-mxic.c
219
writel(IDLY_CODE_VAL(0, idly_code) |
drivers/spi/spi-mxic.c
224
writel(IDLY_CODE_VAL(4, idly_code) |
drivers/spi/spi-mxic.c
287
writel(0, mxic->regs + DATA_STROB);
drivers/spi/spi-mxic.c
288
writel(INT_STS_ALL, mxic->regs + INT_STS_EN);
drivers/spi/spi-mxic.c
289
writel(0, mxic->regs + HC_EN);
drivers/spi/spi-mxic.c
290
writel(0, mxic->regs + LRD_CFG);
drivers/spi/spi-mxic.c
291
writel(0, mxic->regs + LRD_CTRL);
drivers/spi/spi-mxic.c
292
writel(HC_CFG_NIO(1) | HC_CFG_TYPE(0, HC_CFG_TYPE_SPI_NOR) |
drivers/spi/spi-mxic.c
370
writel(data, mxic->regs + TXD(nbytes % 4));
drivers/spi/spi-mxic.c
406
writel(mxic_spi_prep_hc_cfg(desc->mem->spi, 0, desc->info.op_tmpl.data.swap16),
drivers/spi/spi-mxic.c
409
writel(mxic_spi_mem_prep_op_cfg(&desc->info.op_tmpl, len),
drivers/spi/spi-mxic.c
411
writel(desc->info.offset + offs, mxic->regs + LRD_ADDR);
drivers/spi/spi-mxic.c
413
writel(len, mxic->regs + LRD_RANGE);
drivers/spi/spi-mxic.c
414
writel(LMODE_CMD0(desc->info.op_tmpl.cmd.opcode) |
drivers/spi/spi-mxic.c
429
writel(INT_LRD_DIS, mxic->regs + INT_STS);
drivers/spi/spi-mxic.c
430
writel(0, mxic->regs + LRD_CTRL);
drivers/spi/spi-mxic.c
451
writel(mxic_spi_prep_hc_cfg(desc->mem->spi, 0, desc->info.op_tmpl.data.swap16),
drivers/spi/spi-mxic.c
454
writel(mxic_spi_mem_prep_op_cfg(&desc->info.op_tmpl, len),
drivers/spi/spi-mxic.c
456
writel(desc->info.offset + offs, mxic->regs + LWR_ADDR);
drivers/spi/spi-mxic.c
458
writel(len, mxic->regs + LWR_RANGE);
drivers/spi/spi-mxic.c
459
writel(LMODE_CMD0(desc->info.op_tmpl.cmd.opcode) |
drivers/spi/spi-mxic.c
474
writel(INT_LWR_DIS, mxic->regs + INT_STS);
drivers/spi/spi-mxic.c
475
writel(0, mxic->regs + LWR_CTRL);
drivers/spi/spi-mxic.c
529
writel(mxic_spi_prep_hc_cfg(mem->spi, HC_CFG_MAN_CS_EN, op->data.swap16),
drivers/spi/spi-mxic.c
532
writel(HC_EN_BIT, mxic->regs + HC_EN);
drivers/spi/spi-mxic.c
534
writel(mxic_spi_mem_prep_op_cfg(op, op->data.nbytes),
drivers/spi/spi-mxic.c
537
writel(readl(mxic->regs + HC_CFG) | HC_CFG_MAN_CS_ASSERT,
drivers/spi/spi-mxic.c
566
writel(readl(mxic->regs + HC_CFG) & ~HC_CFG_MAN_CS_ASSERT,
drivers/spi/spi-mxic.c
568
writel(0, mxic->regs + HC_EN);
drivers/spi/spi-mxic.c
593
writel(readl(mxic->regs + HC_CFG) | HC_CFG_MAN_CS_EN,
drivers/spi/spi-mxic.c
595
writel(HC_EN_BIT, mxic->regs + HC_EN);
drivers/spi/spi-mxic.c
596
writel(readl(mxic->regs + HC_CFG) | HC_CFG_MAN_CS_ASSERT,
drivers/spi/spi-mxic.c
599
writel(readl(mxic->regs + HC_CFG) & ~HC_CFG_MAN_CS_ASSERT,
drivers/spi/spi-mxic.c
601
writel(0, mxic->regs + HC_EN);
drivers/spi/spi-mxic.c
637
writel(OP_CMD_BYTES(1) | OP_CMD_BUSW(busw) |
drivers/spi/spi-mxs.c
100
writel(0x0, ssp->base + HW_SSP_CMD1);
drivers/spi/spi-mxs.c
305
writel(BM_SSP_CTRL0_IGNORE_CRC,
drivers/spi/spi-mxs.c
310
writel(BM_SSP_CTRL0_IGNORE_CRC,
drivers/spi/spi-mxs.c
314
writel(BM_SSP_CTRL0_XFER_COUNT,
drivers/spi/spi-mxs.c
316
writel(1,
drivers/spi/spi-mxs.c
319
writel(1, ssp->base + HW_SSP_XFER_SIZE);
drivers/spi/spi-mxs.c
323
writel(BM_SSP_CTRL0_READ,
drivers/spi/spi-mxs.c
326
writel(BM_SSP_CTRL0_READ,
drivers/spi/spi-mxs.c
329
writel(BM_SSP_CTRL0_RUN,
drivers/spi/spi-mxs.c
336
writel(*buf, ssp->base + HW_SSP_DATA(ssp));
drivers/spi/spi-mxs.c
338
writel(BM_SSP_CTRL0_DATA_XFER,
drivers/spi/spi-mxs.c
371
writel(BM_SSP_CTRL0_WAIT_FOR_CMD | BM_SSP_CTRL0_WAIT_FOR_IRQ,
drivers/spi/spi-mxs.c
373
writel(mxs_spi_cs_to_reg(spi_get_chipselect(m->spi, 0)),
drivers/spi/spi-mxs.c
400
writel(BM_SSP_CTRL1_DMA_ENABLE,
drivers/spi/spi-mxs.c
413
writel(BM_SSP_CTRL1_DMA_ENABLE,
drivers/spi/spi-mxs.c
90
writel(BM_SSP_CTRL0_LOCK_CS,
drivers/spi/spi-mxs.c
93
writel(BF_SSP_CTRL1_SSP_MODE(BV_SSP_CTRL1_SSP_MODE__SPI) |
drivers/spi/spi-mxs.c
99
writel(0x0, ssp->base + HW_SSP_CMD0);
drivers/spi/spi-nxp-xspi.c
1059
writel(0xA, base + XSPI_BUF0CR);
drivers/spi/spi-nxp-xspi.c
1060
writel(0x2, base + XSPI_BUF1CR);
drivers/spi/spi-nxp-xspi.c
1061
writel(0xD, base + XSPI_BUF2CR);
drivers/spi/spi-nxp-xspi.c
1069
writel(reg, base + XSPI_BUF3CR);
drivers/spi/spi-nxp-xspi.c
1072
writel(0, base + XSPI_BUF0IND);
drivers/spi/spi-nxp-xspi.c
1073
writel(0, base + XSPI_BUF1IND);
drivers/spi/spi-nxp-xspi.c
1074
writel(0, base + XSPI_BUF2IND);
drivers/spi/spi-nxp-xspi.c
1081
writel(reg, base + XSPI_BFGENCR);
drivers/spi/spi-nxp-xspi.c
1090
writel(0, base + XSPI_MGC);
drivers/spi/spi-nxp-xspi.c
1095
writel(reg, base + XSPI_TG0MDAD);
drivers/spi/spi-nxp-xspi.c
1101
writel(reg, base + XSPI_FRAD0_WORD2);
drivers/spi/spi-nxp-xspi.c
1106
writel(reg, base + XSPI_FRAD0_WORD3);
drivers/spi/spi-nxp-xspi.c
1112
writel(0xFFFFFFFF, base + XSPI_MTO);
drivers/spi/spi-nxp-xspi.c
1117
writel(reg, base + XSPI_MCR);
drivers/spi/spi-nxp-xspi.c
1127
writel(reg, base + XSPI_MCR);
drivers/spi/spi-nxp-xspi.c
1134
writel(reg, base + XSPI_SFACR);
drivers/spi/spi-nxp-xspi.c
1140
writel(reg, base + XSPI_FLSHCR);
drivers/spi/spi-nxp-xspi.c
1145
writel(reg, base + XSPI_MCR);
drivers/spi/spi-nxp-xspi.c
1150
writel(XSPI_RSER_TFIE, base + XSPI_RSER);
drivers/spi/spi-nxp-xspi.c
1198
writel(0, xspi->iobase + XSPI_RSER);
drivers/spi/spi-nxp-xspi.c
1200
writel(0xFFFFFFFF, xspi->iobase + XSPI_FR);
drivers/spi/spi-nxp-xspi.c
1204
writel(reg, xspi->iobase + XSPI_MCR);
drivers/spi/spi-nxp-xspi.c
1271
writel(0xFFFFFFFF, xspi->iobase + XSPI_ERRSTAT);
drivers/spi/spi-nxp-xspi.c
1272
writel(0xFFFFFFFF, xspi->iobase + XSPI_FR);
drivers/spi/spi-nxp-xspi.c
1304
writel(reg, xspi->iobase + XSPI_MCR);
drivers/spi/spi-nxp-xspi.c
1323
writel(reg, xspi->iobase + XSPI_MCR);
drivers/spi/spi-nxp-xspi.c
360
writel(XSPI_FR_TFF, xspi->iobase + XSPI_FR);
drivers/spi/spi-nxp-xspi.c
469
writel(XSPI_LUT_KEY_VAL, xspi->iobase + XSPI_LUTKEY);
drivers/spi/spi-nxp-xspi.c
470
writel(XSPI_LOKCR_UNLOCK, xspi->iobase + XSPI_LCKCR);
drivers/spi/spi-nxp-xspi.c
474
writel(lutval[i], base + XSPI_LUT_REG(i));
drivers/spi/spi-nxp-xspi.c
481
writel(XSPI_LUT_KEY_VAL, xspi->iobase + XSPI_LUTKEY);
drivers/spi/spi-nxp-xspi.c
482
writel(XSPI_LOKCR_LOCK, xspi->iobase + XSPI_LCKCR);
drivers/spi/spi-nxp-xspi.c
493
writel(reg, base + XSPI_MCR);
drivers/spi/spi-nxp-xspi.c
499
writel(reg, base + XSPI_MCR);
drivers/spi/spi-nxp-xspi.c
504
writel(reg, base + XSPI_FLSHCR);
drivers/spi/spi-nxp-xspi.c
508
writel(reg, base + XSPI_SMPR);
drivers/spi/spi-nxp-xspi.c
513
writel(reg, base + XSPI_MCR);
drivers/spi/spi-nxp-xspi.c
524
writel(reg, base + XSPI_MCR);
drivers/spi/spi-nxp-xspi.c
530
writel(reg, base + XSPI_MCR);
drivers/spi/spi-nxp-xspi.c
536
writel(reg, base + XSPI_FLSHCR);
drivers/spi/spi-nxp-xspi.c
539
writel(reg, base + XSPI_SMPR);
drivers/spi/spi-nxp-xspi.c
544
writel(reg, base + XSPI_MCR);
drivers/spi/spi-nxp-xspi.c
564
writel(reg, base + XSPI_MCR);
drivers/spi/spi-nxp-xspi.c
572
writel(reg, base + XSPI_MCR);
drivers/spi/spi-nxp-xspi.c
593
writel(reg, base + XSPI_MCR);
drivers/spi/spi-nxp-xspi.c
597
writel(reg, base + XSPI_MCR);
drivers/spi/spi-nxp-xspi.c
609
writel(reg, base + XSPI_MCR);
drivers/spi/spi-nxp-xspi.c
621
writel(0, base + XSPI_DLLCRA);
drivers/spi/spi-nxp-xspi.c
625
writel(reg, base + XSPI_DLLCRA);
drivers/spi/spi-nxp-xspi.c
630
writel(reg, base + XSPI_DLLCRA);
drivers/spi/spi-nxp-xspi.c
633
writel(reg, base + XSPI_DLLCRA);
drivers/spi/spi-nxp-xspi.c
651
writel(0, base + XSPI_DLLCRA);
drivers/spi/spi-nxp-xspi.c
655
writel(reg, base + XSPI_DLLCRA);
drivers/spi/spi-nxp-xspi.c
663
writel(reg, base + XSPI_DLLCRA);
drivers/spi/spi-nxp-xspi.c
666
writel(reg, base + XSPI_DLLCRA);
drivers/spi/spi-nxp-xspi.c
669
writel(reg, base + XSPI_DLLCRA);
drivers/spi/spi-nxp-xspi.c
755
writel(cs0_top_address, xspi->iobase + XSPI_SFA1AD);
drivers/spi/spi-nxp-xspi.c
756
writel(cs1_top_address, xspi->iobase + XSPI_SFA2AD);
drivers/spi/spi-nxp-xspi.c
763
writel(reg, xspi->iobase + XSPI_SFACR);
drivers/spi/spi-nxp-xspi.c
813
writel(reg, base + XSPI_FR);
drivers/spi/spi-nxp-xspi.c
826
writel(left, base + XSPI_TBDR);
drivers/spi/spi-nxp-xspi.c
828
writel(*(u32 *)(buf + i), base + XSPI_TBDR);
drivers/spi/spi-nxp-xspi.c
869
writel(reg, base + XSPI_FR);
drivers/spi/spi-nxp-xspi.c
895
writel(reg, base + XSPI_MCR);
drivers/spi/spi-nxp-xspi.c
915
writel(reg, base + XSPI_MCR);
drivers/spi/spi-nxp-xspi.c
927
writel(reg, base + XSPI_TBCT);
drivers/spi/spi-nxp-xspi.c
948
writel(reg, base + XSPI_MCR);
drivers/spi/spi-nxp-xspi.c
958
writel(reg, base + XSPI_RBCT);
drivers/spi/spi-nxp-xspi.c
964
writel(op->addr.val + xspi->memmap_phy, base + XSPI_SFP_TG_SFAR);
drivers/spi/spi-nxp-xspi.c
969
writel(reg, base + XSPI_SFP_TG_IPCR);
drivers/spi/spi-oc-tiny.c
76
writel(baud, hw->base + TINY_SPI_BAUD);
drivers/spi/spi-oc-tiny.c
77
writel(hw->mode, hw->base + TINY_SPI_CONTROL);
drivers/spi/spi-orion.c
121
writel(val, reg_addr);
drivers/spi/spi-orion.c
132
writel(val, reg_addr);
drivers/spi/spi-orion.c
227
writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
drivers/spi/spi-orion.c
251
writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
drivers/spi/spi-orion.c
286
writel(reg, spi_reg(orion_spi, ORION_SPI_TIMING_PARAMS_REG));
drivers/spi/spi-orion.c
364
writel(val, ctrl_reg);
drivers/spi/spi-orion.c
401
writel(0x0, int_reg);
drivers/spi/spi-orion.c
404
writel(*(*tx_buf)++, tx_reg);
drivers/spi/spi-orion.c
406
writel(0, tx_reg);
drivers/spi/spi-orion.c
448
writel(0x0, int_reg);
drivers/spi/spi-orion.c
451
writel(__cpu_to_le16(get_unaligned((*tx_buf)++)), tx_reg);
drivers/spi/spi-orion.c
453
writel(0, tx_reg);
drivers/spi/spi-orion.c
572
writel(0, spi_reg(orion_spi, SPI_DIRECT_WRITE_CONFIG_REG));
drivers/spi/spi-pci1xxxx.c
1007
writel(reg1, spi_ptr->reg_base +
drivers/spi/spi-pci1xxxx.c
206
writel(SPI_SYSLOCK, par->reg_base + SPI_SYSLOCK_REG);
drivers/spi/spi-pci1xxxx.c
221
writel(0x0, par->reg_base + SPI_SYSLOCK_REG);
drivers/spi/spi-pci1xxxx.c
290
writel(msi.address_hi, spi_bus->dma_offset_bar +
drivers/spi/spi-pci1xxxx.c
292
writel(msi.address_hi, spi_bus->dma_offset_bar +
drivers/spi/spi-pci1xxxx.c
294
writel(msi.address_hi, spi_bus->dma_offset_bar +
drivers/spi/spi-pci1xxxx.c
296
writel(msi.address_hi, spi_bus->dma_offset_bar +
drivers/spi/spi-pci1xxxx.c
298
writel(msi.address_lo, spi_bus->dma_offset_bar +
drivers/spi/spi-pci1xxxx.c
300
writel(msi.address_lo, spi_bus->dma_offset_bar +
drivers/spi/spi-pci1xxxx.c
302
writel(msi.address_lo, spi_bus->dma_offset_bar +
drivers/spi/spi-pci1xxxx.c
304
writel(msi.address_lo, spi_bus->dma_offset_bar +
drivers/spi/spi-pci1xxxx.c
306
writel(0, spi_bus->dma_offset_bar + SPI_DMA_INTR_WR_IMWR_DATA);
drivers/spi/spi-pci1xxxx.c
307
writel(0, spi_bus->dma_offset_bar + SPI_DMA_INTR_RD_IMWR_DATA);
drivers/spi/spi-pci1xxxx.c
311
writel((regval | (data << (iter * 16))), spi_bus->dma_offset_bar +
drivers/spi/spi-pci1xxxx.c
318
writel(regval | (data << (iter * 16)), spi_bus->dma_offset_bar +
drivers/spi/spi-pci1xxxx.c
338
writel(SPI_DMA_ENGINE_EN, spi_bus->dma_offset_bar + SPI_DMA_GLOBAL_WR_ENGINE_EN);
drivers/spi/spi-pci1xxxx.c
339
writel(SPI_DMA_ENGINE_EN, spi_bus->dma_offset_bar + SPI_DMA_GLOBAL_RD_ENGINE_EN);
drivers/spi/spi-pci1xxxx.c
382
writel(regval, par->reg_base + SPI_MST_CTL_REG_OFFSET(p->hw_inst));
drivers/spi/spi-pci1xxxx.c
419
writel(DMA_INTR_EN, base + SPI_DMA_CH_CTL1_OFFSET);
drivers/spi/spi-pci1xxxx.c
420
writel(len, base + SPI_DMA_CH_XFER_LEN_OFFSET);
drivers/spi/spi-pci1xxxx.c
421
writel(lower_32_bits(dma_addr), base + SPI_DMA_CH_SAR_LO_OFFSET);
drivers/spi/spi-pci1xxxx.c
422
writel(upper_32_bits(dma_addr), base + SPI_DMA_CH_SAR_HI_OFFSET);
drivers/spi/spi-pci1xxxx.c
424
writel(lower_32_bits(SPI_PERI_ADDR_BASE + SPI_MST_CMD_BUF_OFFSET(p->hw_inst)),
drivers/spi/spi-pci1xxxx.c
426
writel(upper_32_bits(SPI_PERI_ADDR_BASE + SPI_MST_CMD_BUF_OFFSET(p->hw_inst)),
drivers/spi/spi-pci1xxxx.c
440
writel(DMA_INTR_EN, base + SPI_DMA_CH_CTL1_OFFSET);
drivers/spi/spi-pci1xxxx.c
441
writel(len, base + SPI_DMA_CH_XFER_LEN_OFFSET);
drivers/spi/spi-pci1xxxx.c
442
writel(lower_32_bits(dma_addr), base + SPI_DMA_CH_DAR_LO_OFFSET);
drivers/spi/spi-pci1xxxx.c
443
writel(upper_32_bits(dma_addr), base + SPI_DMA_CH_DAR_HI_OFFSET);
drivers/spi/spi-pci1xxxx.c
444
writel(lower_32_bits(SPI_PERI_ADDR_BASE + SPI_MST_RSP_BUF_OFFSET(p->hw_inst)),
drivers/spi/spi-pci1xxxx.c
446
writel(upper_32_bits(SPI_PERI_ADDR_BASE + SPI_MST_RSP_BUF_OFFSET(p->hw_inst)),
drivers/spi/spi-pci1xxxx.c
464
writel(regval, par->reg_base + SPI_MST_CTL_REG_OFFSET(hw_inst));
drivers/spi/spi-pci1xxxx.c
474
writel(regval, p->parent->reg_base + SPI_MST_CTL_REG_OFFSET(p->hw_inst));
drivers/spi/spi-pci1xxxx.c
498
writel(regval, par->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst));
drivers/spi/spi-pci1xxxx.c
554
writel(regval, par->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst));
drivers/spi/spi-pci1xxxx.c
566
writel(regval, par->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst));
drivers/spi/spi-pci1xxxx.c
572
writel(p->hw_inst, par->dma_offset_bar + SPI_DMA_RD_DOORBELL_REG);
drivers/spi/spi-pci1xxxx.c
580
writel(SPI_DMA_ENGINE_DIS,
drivers/spi/spi-pci1xxxx.c
594
writel(SPI_DMA_ENGINE_EN,
drivers/spi/spi-pci1xxxx.c
600
writel(SPI_DMA_ENGINE_DIS,
drivers/spi/spi-pci1xxxx.c
616
writel(SPI_DMA_ENGINE_EN,
drivers/spi/spi-pci1xxxx.c
651
writel(p->hw_inst, p->parent->dma_offset_bar +
drivers/spi/spi-pci1xxxx.c
657
writel(regval, p->parent->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst));
drivers/spi/spi-pci1xxxx.c
672
writel(p->hw_inst, p->parent->dma_offset_bar + SPI_DMA_RD_DOORBELL_REG);
drivers/spi/spi-pci1xxxx.c
687
writel(p->hw_inst, p->parent->dma_offset_bar + SPI_DMA_WR_DOORBELL_REG);
drivers/spi/spi-pci1xxxx.c
712
writel((SPI_DMA_DONE_INT_MASK(p->hw_inst) | SPI_DMA_ABORT_INT_MASK(p->hw_inst)),
drivers/spi/spi-pci1xxxx.c
745
writel((SPI_DMA_DONE_INT_MASK(p->hw_inst) | SPI_DMA_ABORT_INT_MASK(p->hw_inst)),
drivers/spi/spi-pci1xxxx.c
764
writel(regval, p->parent->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst));
drivers/spi/spi-pci1xxxx.c
867
writel(regval, spi_bus->reg_base +
drivers/spi/spi-pci1xxxx.c
893
writel(regval, spi_bus->reg_base + SPI_PCI_CTRL_REG_OFFSET(0));
drivers/spi/spi-pci1xxxx.c
904
writel(regval, spi_bus->reg_base +
drivers/spi/spi-pci1xxxx.c
964
writel(regval,
drivers/spi/spi-pci1xxxx.c
966
writel((spi_sub_ptr->prev_val.msi_vector_sel << 4),
drivers/spi/spi-pci1xxxx.c
981
writel(regval, spi_ptr->reg_base +
drivers/spi/spi-pic32-sqi.c
157
writel(readl(reg) | set, reg);
drivers/spi/spi-pic32-sqi.c
162
writel(readl(reg) & ~clr, reg);
drivers/spi/spi-pic32-sqi.c
177
writel(val, sqi->regs + PESQI_CLK_CTRL_REG);
drivers/spi/spi-pic32-sqi.c
188
writel(mask, sqi->regs + PESQI_INT_ENABLE_REG);
drivers/spi/spi-pic32-sqi.c
190
writel(mask, sqi->regs + PESQI_INT_SIGEN_REG);
drivers/spi/spi-pic32-sqi.c
195
writel(0, sqi->regs + PESQI_INT_ENABLE_REG);
drivers/spi/spi-pic32-sqi.c
196
writel(0, sqi->regs + PESQI_INT_SIGEN_REG);
drivers/spi/spi-pic32-sqi.c
235
writel(enable, sqi->regs + PESQI_INT_ENABLE_REG);
drivers/spi/spi-pic32-sqi.c
378
writel(val, sqi->regs + PESQI_CONF_REG);
drivers/spi/spi-pic32-sqi.c
403
writel(rdesc->bd_dma, sqi->regs + PESQI_BD_BASE_ADDR_REG);
drivers/spi/spi-pic32-sqi.c
410
writel(val, sqi->regs + PESQI_BD_CTRL_REG);
drivers/spi/spi-pic32-sqi.c
425
writel(0, sqi->regs + PESQI_BD_CTRL_REG);
drivers/spi/spi-pic32-sqi.c
519
writel(PESQI_SOFT_RESET, sqi->regs + PESQI_CONF_REG);
drivers/spi/spi-pic32-sqi.c
536
writel(val, sqi->regs + PESQI_CMD_THRES_REG);
drivers/spi/spi-pic32-sqi.c
542
writel(val, sqi->regs + PESQI_INT_THRES_REG);
drivers/spi/spi-pic32-sqi.c
550
writel(val, sqi->regs + PESQI_CONF_REG);
drivers/spi/spi-pic32-sqi.c
560
writel(val, sqi->regs + PESQI_CONF_REG);
drivers/spi/spi-pic32-sqi.c
563
writel(0, sqi->regs + PESQI_BD_POLL_CTRL_REG);
drivers/spi/spi-pic32.c
125
writel(CTRL_ON | CTRL_SIDL, &pic32s->regs->ctrl_set);
drivers/spi/spi-pic32.c
130
writel(CTRL_ON | CTRL_SIDL, &pic32s->regs->ctrl_clr);
drivers/spi/spi-pic32.c
143
writel(div & BAUD_MASK, &pic32s->regs->baud);
drivers/spi/spi-pic32.c
242
writel(STAT_RX_OV, &pic32s->regs->status_clr);
drivers/spi/spi-pic32.c
243
writel(STAT_TX_UR, &pic32s->regs->status_clr);
drivers/spi/spi-pic32.c
424
writel(v, &pic32s->regs->ctrl);
drivers/spi/spi-pic32.c
477
writel(val, &pic32s->regs->ctrl);
drivers/spi/spi-pic32.c
700
writel(ctrl, &pic32s->regs->ctrl);
drivers/spi/spi-pic32.c
704
writel(ctrl, &pic32s->regs->ctrl2_set);
drivers/spi/spi-pl022.c
476
writel(chip->cr0, SSP_CR0(pl022->virtbase));
drivers/spi/spi-pl022.c
564
writel(DEFAULT_SSP_REG_CR0_ST_PL023, SSP_CR0(pl022->virtbase));
drivers/spi/spi-pl022.c
567
writel(DEFAULT_SSP_REG_CR0_ST, SSP_CR0(pl022->virtbase));
drivers/spi/spi-pl022.c
639
writel(*(u32 *) (pl022->tx), SSP_DR(pl022->virtbase));
drivers/spi/spi-pxa2xx.c
322
writel(value, drv_data->lpss_base + offset);
drivers/spi/spi-qcom-qspi.c
217
writel(pio_xfer_cfg, ctrl->base + PIO_XFER_CFG);
drivers/spi/spi-qcom-qspi.c
227
writel(pio_xfer_ctrl, ctrl->base + PIO_XFER_CTRL);
drivers/spi/spi-qcom-qspi.c
237
writel(QSPI_ALL_IRQS, ctrl->base + MSTR_INT_STATUS);
drivers/spi/spi-qcom-qspi.c
244
writel(ints, ctrl->base + MSTR_INT_EN);
drivers/spi/spi-qcom-qspi.c
259
writel(0, ctrl->base + MSTR_INT_EN);
drivers/spi/spi-qcom-qspi.c
261
writel(int_status, ctrl->base + MSTR_INT_STATUS);
drivers/spi/spi-qcom-qspi.c
399
writel(DMA_CHAIN_DONE, ctrl->base + MSTR_INT_EN);
drivers/spi/spi-qcom-qspi.c
402
writel((u32)((ctrl->dma_cmd_desc)[0]), ctrl->base + NEXT_DMA_DESC_ADDR);
drivers/spi/spi-qcom-qspi.c
453
writel(mstr_cfg, ctrl->base + MSTR_CONFIG);
drivers/spi/spi-qcom-qspi.c
470
writel(mstr_cfg, ctrl->base + MSTR_CONFIG);
drivers/spi/spi-qcom-qspi.c
508
writel(mstr_cfg, ctrl->base + MSTR_CONFIG);
drivers/spi/spi-qcom-qspi.c
587
writel(*byte_buf++,
drivers/spi/spi-qcom-qspi.c
620
writel(int_status, ctrl->base + MSTR_INT_STATUS);
drivers/spi/spi-qcom-qspi.c
645
writel(0, ctrl->base + MSTR_INT_EN);
drivers/spi/spi-qcom-qspi.c
653
writel(0, ctrl->base + MSTR_INT_EN);
drivers/spi/spi-realtek-rtl.c
140
writel(value, REG(RTL_SPI_SFCR));
drivers/spi/spi-realtek-rtl.c
147
writel(value, REG(RTL_SPI_SFCSR));
drivers/spi/spi-realtek-rtl.c
44
writel(value, REG(RTL_SPI_SFCSR));
drivers/spi/spi-realtek-rtl.c
57
writel(value, REG(RTL_SPI_SFCSR));
drivers/spi/spi-realtek-rtl.c
69
writel(*buf, REG(RTL_SPI_SFDR));
drivers/spi/spi-realtek-rtl.c
76
writel(buf[0] << 24, REG(RTL_SPI_SFDR));
drivers/spi/spi-rockchip-sfc.c
244
writel(reg, sfc->regbase + SFC_IMR);
drivers/spi/spi-rockchip-sfc.c
254
writel(reg, sfc->regbase + SFC_IMR);
drivers/spi/spi-rockchip-sfc.c
259
writel(0, sfc->regbase + SFC_CTRL);
drivers/spi/spi-rockchip-sfc.c
260
writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR);
drivers/spi/spi-rockchip-sfc.c
263
writel(SFC_LEN_CTRL_TRB_SEL, sfc->regbase + SFC_LEN_CTRL);
drivers/spi/spi-rockchip-sfc.c
337
writel(op->addr.nbytes * 8 - 1,
drivers/spi/spi-rockchip-sfc.c
356
writel(len, sfc->regbase + SFC_LEN_EXT);
drivers/spi/spi-rockchip-sfc.c
378
writel(ctrl, sfc->regbase + cs * SFC_CS1_REG_OFFSET + SFC_CTRL);
drivers/spi/spi-rockchip-sfc.c
379
writel(cmd, sfc->regbase + SFC_CMD);
drivers/spi/spi-rockchip-sfc.c
381
writel(op->addr.val, sfc->regbase + SFC_ADDR);
drivers/spi/spi-rockchip-sfc.c
411
writel(tmp, sfc->regbase + SFC_DATA);
drivers/spi/spi-rockchip-sfc.c
451
writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR);
drivers/spi/spi-rockchip-sfc.c
452
writel((u32)dma_buf, sfc->regbase + SFC_DMA_ADDR);
drivers/spi/spi-rockchip-sfc.c
453
writel(SFC_DMA_TRIGGER_START, sfc->regbase + SFC_DMA_TRIGGER);
drivers/spi/spi-rzv2h-rspi.c
134
RZV2H_RSPI_TX(writel, u32)
drivers/spi/spi-rzv2h-rspi.c
148
writel(tmp, rspi->base + reg_offs);
drivers/spi/spi-rzv2h-rspi.c
644
writel(conf32, rspi->base + RSPI_SPCR);
drivers/spi/spi-rzv2h-rspi.c
661
writel(conf32, rspi->base + RSPI_SPCMD);
drivers/spi/spi-rzv2m-csi.c
124
writel(tmp, csi->base + reg_offs);
drivers/spi/spi-rzv2m-csi.c
167
writel(buf[i], csi->base + CSI_OFIFO);
drivers/spi/spi-rzv2m-csi.c
172
writel(buf[i], csi->base + CSI_OFIFO);
drivers/spi/spi-rzv2m-csi.c
264
writel(cnt & ~enable_bits, csi->base + CSI_CNT);
drivers/spi/spi-rzv2m-csi.c
276
writel(irqs, csi->base + CSI_INT);
drivers/spi/spi-rzv2m-csi.c
290
writel(cnt | enable_bits, csi->base + CSI_CNT);
drivers/spi/spi-rzv2m-csi.c
405
writel(CSI_MODE_SETUP, csi->base + CSI_MODE);
drivers/spi/spi-rzv2m-csi.c
451
writel(0, csi->base + CSI_OFIFOL);
drivers/spi/spi-rzv2m-csi.c
454
writel(0, csi->base + CSI_IFIFOL);
drivers/spi/spi-rzv2m-csi.c
478
writel(readl(csi->base + CSI_INT), csi->base + CSI_INT);
drivers/spi/spi-s3c64xx.c
1107
writel((val & ~S3C64XX_SPI_INT_RX_FIFORDY_EN),
drivers/spi/spi-s3c64xx.c
1112
writel(clr, sdd->regs + S3C64XX_SPI_PENDING_CLR);
drivers/spi/spi-s3c64xx.c
1113
writel(0, sdd->regs + S3C64XX_SPI_PENDING_CLR);
drivers/spi/spi-s3c64xx.c
1127
writel(0, sdd->regs + S3C64XX_SPI_CS_REG);
drivers/spi/spi-s3c64xx.c
1129
writel(S3C64XX_SPI_CS_SIG_INACT, sdd->regs + S3C64XX_SPI_CS_REG);
drivers/spi/spi-s3c64xx.c
1132
writel(0, regs + S3C64XX_SPI_INT_EN);
drivers/spi/spi-s3c64xx.c
1135
writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT,
drivers/spi/spi-s3c64xx.c
1137
writel(0, regs + S3C64XX_SPI_MODE_CFG);
drivers/spi/spi-s3c64xx.c
1138
writel(0, regs + S3C64XX_SPI_PACKET_CNT);
drivers/spi/spi-s3c64xx.c
1145
writel(val, regs + S3C64XX_SPI_PENDING_CLR);
drivers/spi/spi-s3c64xx.c
1146
writel(0, regs + S3C64XX_SPI_PENDING_CLR);
drivers/spi/spi-s3c64xx.c
1148
writel(0, regs + S3C64XX_SPI_SWAP_CFG);
drivers/spi/spi-s3c64xx.c
1153
writel(val, regs + S3C64XX_SPI_MODE_CFG);
drivers/spi/spi-s3c64xx.c
1368
writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN |
drivers/spi/spi-s3c64xx.c
1402
writel(0, sdd->regs + S3C64XX_SPI_INT_EN);
drivers/spi/spi-s3c64xx.c
1487
writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN |
drivers/spi/spi-s3c64xx.c
235
writel(0, regs + S3C64XX_SPI_PACKET_CNT);
drivers/spi/spi-s3c64xx.c
239
writel(val, regs + S3C64XX_SPI_CH_CFG);
drivers/spi/spi-s3c64xx.c
244
writel(val, regs + S3C64XX_SPI_CH_CFG);
drivers/spi/spi-s3c64xx.c
270
writel(val, regs + S3C64XX_SPI_CH_CFG);
drivers/spi/spi-s3c64xx.c
274
writel(val, regs + S3C64XX_SPI_MODE_CFG);
drivers/spi/spi-s3c64xx.c
365
writel(0, sdd->regs + S3C64XX_SPI_CS_REG);
drivers/spi/spi-s3c64xx.c
371
writel(ssel, sdd->regs + S3C64XX_SPI_CS_REG);
drivers/spi/spi-s3c64xx.c
375
writel(S3C64XX_SPI_CS_SIG_INACT,
drivers/spi/spi-s3c64xx.c
511
writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
drivers/spi/spi-s3c64xx.c
537
writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
drivers/spi/spi-s3c64xx.c
547
writel(modecfg, regs + S3C64XX_SPI_MODE_CFG);
drivers/spi/spi-s3c64xx.c
548
writel(chcfg, regs + S3C64XX_SPI_CH_CFG);
drivers/spi/spi-s3c64xx.c
706
writel(val, regs + S3C64XX_SPI_CLK_CFG);
drivers/spi/spi-s3c64xx.c
721
writel(val, regs + S3C64XX_SPI_CH_CFG);
drivers/spi/spi-s3c64xx.c
748
writel(val, regs + S3C64XX_SPI_MODE_CFG);
drivers/spi/spi-s3c64xx.c
761
writel(val, regs + S3C64XX_SPI_CLK_CFG);
drivers/spi/spi-s3c64xx.c
766
writel(val, regs + S3C64XX_SPI_CLK_CFG);
drivers/spi/spi-s3c64xx.c
784
writel(0, sdd->regs + S3C64XX_SPI_FB_CLK);
drivers/spi/spi-s3c64xx.c
786
writel(cs->fb_delay & 0x3, sdd->regs + S3C64XX_SPI_FB_CLK);
drivers/spi/spi-s3c64xx.c
865
writel(val, sdd->regs + S3C64XX_SPI_MODE_CFG);
drivers/spi/spi-s3c64xx.c
869
writel((val | S3C64XX_SPI_INT_RX_FIFORDY_EN),
drivers/spi/spi-sg2044-nor.c
132
writel(reg, spifmc->io_base + SPIFMC_TRAN_CSR);
drivers/spi/spi-sg2044-nor.c
152
writel(0, spifmc->io_base + SPIFMC_FIFO_PT);
drivers/spi/spi-sg2044-nor.c
161
writel(len, spifmc->io_base + SPIFMC_TRAN_NUM);
drivers/spi/spi-sg2044-nor.c
162
writel(0, spifmc->io_base + SPIFMC_INT_STS);
drivers/spi/spi-sg2044-nor.c
164
writel(reg, spifmc->io_base + SPIFMC_TRAN_CSR);
drivers/spi/spi-sg2044-nor.c
188
writel(0, spifmc->io_base + SPIFMC_FIFO_PT);
drivers/spi/spi-sg2044-nor.c
234
writel(0, spifmc->io_base + SPIFMC_FIFO_PT);
drivers/spi/spi-sg2044-nor.c
243
writel(0, spifmc->io_base + SPIFMC_INT_STS);
drivers/spi/spi-sg2044-nor.c
244
writel(op->data.nbytes, spifmc->io_base + SPIFMC_TRAN_NUM);
drivers/spi/spi-sg2044-nor.c
246
writel(reg, spifmc->io_base + SPIFMC_TRAN_CSR);
drivers/spi/spi-sg2044-nor.c
252
writel(0, spifmc->io_base + SPIFMC_FIFO_PT);
drivers/spi/spi-sg2044-nor.c
272
writel(0, spifmc->io_base + SPIFMC_FIFO_PT);
drivers/spi/spi-sg2044-nor.c
288
writel(0, spifmc->io_base + SPIFMC_FIFO_PT);
drivers/spi/spi-sg2044-nor.c
297
writel(0, spifmc->io_base + SPIFMC_INT_STS);
drivers/spi/spi-sg2044-nor.c
299
writel(reg, spifmc->io_base + SPIFMC_TRAN_CSR);
drivers/spi/spi-sg2044-nor.c
305
writel(0, spifmc->io_base + SPIFMC_FIFO_PT);
drivers/spi/spi-sg2044-nor.c
345
writel(SPIFMC_OPT_DISABLE_FIFO_FLUSH, spifmc->io_base + SPIFMC_OPT);
drivers/spi/spi-sg2044-nor.c
355
writel(len, spifmc->io_base + SPIFMC_TRAN_NUM);
drivers/spi/spi-sg2044-nor.c
359
writel(0, spifmc->io_base + SPIFMC_FIFO_PT);
drivers/spi/spi-sg2044-nor.c
369
writel(0, spifmc->io_base + SPIFMC_INT_STS);
drivers/spi/spi-sg2044-nor.c
370
writel(len, spifmc->io_base + SPIFMC_TRAN_NUM);
drivers/spi/spi-sg2044-nor.c
372
writel(reg, spifmc->io_base + SPIFMC_TRAN_CSR);
drivers/spi/spi-sg2044-nor.c
383
writel(0, spifmc->io_base + SPIFMC_FIFO_PT);
drivers/spi/spi-sg2044-nor.c
416
writel(0, spifmc->io_base + SPIFMC_DMMR);
drivers/spi/spi-sg2044-nor.c
422
writel(reg, spifmc->io_base + SPIFMC_CTRL);
drivers/spi/spi-sg2044-nor.c
424
writel(0, spifmc->io_base + SPIFMC_CE_CTRL);
drivers/spi/spi-sg2044-nor.c
430
writel(tran_csr, spifmc->io_base + SPIFMC_TRAN_CSR);
drivers/spi/spi-slave-mt27xx.c
105
writel(reg_val, mdata->base + SPIS_DMA_CFG_REG);
drivers/spi/spi-slave-mt27xx.c
115
writel(reg_val, mdata->base + SPIS_CFG_REG);
drivers/spi/spi-slave-mt27xx.c
157
writel(reg_val, mdata->base + SPIS_CFG_REG);
drivers/spi/spi-slave-mt27xx.c
169
writel(SPIS_SOFT_RST, mdata->base + SPIS_SOFT_RST_REG);
drivers/spi/spi-slave-mt27xx.c
176
writel(reg_val, mdata->base + SPIS_CFG_REG);
drivers/spi/spi-slave-mt27xx.c
187
writel(reg_val, mdata->base + SPIS_TX_DATA_REG);
drivers/spi/spi-slave-mt27xx.c
193
writel(SPIS_SOFT_RST, mdata->base + SPIS_SOFT_RST_REG);
drivers/spi/spi-slave-mt27xx.c
207
writel(SPIS_SOFT_RST, mdata->base + SPIS_SOFT_RST_REG);
drivers/spi/spi-slave-mt27xx.c
232
writel(xfer->tx_dma, mdata->base + SPIS_TX_SRC_REG);
drivers/spi/spi-slave-mt27xx.c
233
writel(xfer->rx_dma, mdata->base + SPIS_RX_DST_REG);
drivers/spi/spi-slave-mt27xx.c
235
writel(SPIS_DMA_ADDR_EN, mdata->base + SPIS_SOFT_RST_REG);
drivers/spi/spi-slave-mt27xx.c
243
writel(reg_val, mdata->base + SPIS_CFG_REG);
drivers/spi/spi-slave-mt27xx.c
248
writel(reg_val, mdata->base + SPIS_DMA_CFG_REG);
drivers/spi/spi-slave-mt27xx.c
256
writel(reg_val, mdata->base + SPIS_DMA_CFG_REG);
drivers/spi/spi-slave-mt27xx.c
277
writel(SPIS_SOFT_RST, mdata->base + SPIS_SOFT_RST_REG);
drivers/spi/spi-slave-mt27xx.c
305
writel(reg_val, mdata->base + SPIS_IRQ_EN_REG);
drivers/spi/spi-slave-mt27xx.c
309
writel(reg_val, mdata->base + SPIS_IRQ_MASK_REG);
drivers/spi/spi-slave-mt27xx.c
335
writel(int_status, mdata->base + SPIS_IRQ_CLR_REG);
drivers/spi/spi-slave-mt27xx.c
343
writel(SPIS_SOFT_RST, mdata->base + SPIS_SOFT_RST_REG);
drivers/spi/spi-sn-f-ospi.c
127
writel(OSPI_IRQ_CS_DEASSERT | OSPI_IRQ_CS_TRANS_COMP,
drivers/spi/spi-sn-f-ospi.c
137
writel(val, ospi->base + OSPI_IRQ_STAT_EN);
drivers/spi/spi-sn-f-ospi.c
146
writel(val, ospi->base + OSPI_IRQ_STAT_EN);
drivers/spi/spi-sn-f-ospi.c
155
writel(val, ospi->base + OSPI_IRQ_SIG_EN);
drivers/spi/spi-sn-f-ospi.c
165
writel(val, ospi->base + OSPI_CLK_CTL);
drivers/spi/spi-sn-f-ospi.c
183
writel(val, ospi->base + OSPI_CLK_CTL);
drivers/spi/spi-sn-f-ospi.c
229
writel(val, ospi->base + OSPI_CLK_CTL);
drivers/spi/spi-sn-f-ospi.c
273
writel(BIT(spi_get_chipselect(spi, 0)), ospi->base + OSPI_SSEL);
drivers/spi/spi-sn-f-ospi.c
334
writel(prot, ospi->base + OSPI_PROT_CTL_INDIR);
drivers/spi/spi-sn-f-ospi.c
335
writel(val, ospi->base + OSPI_DAT_SIZE_INDIR);
drivers/spi/spi-sn-f-ospi.c
352
writel(f_ospi_get_dummy_cycle(op), ospi->base + OSPI_DMY_INDIR);
drivers/spi/spi-sn-f-ospi.c
353
writel(op->addr.val, ospi->base + OSPI_ADDR);
drivers/spi/spi-sn-f-ospi.c
354
writel(op->cmd.opcode, ospi->base + OSPI_CMD_IDX_INDIR);
drivers/spi/spi-sn-f-ospi.c
385
writel(OSPI_TRANS_CTL_START_REQ, ospi->base + OSPI_TRANS_CTL);
drivers/spi/spi-sn-f-ospi.c
391
writel(OSPI_TRANS_CTL_STOP_REQ, ospi->base + OSPI_TRANS_CTL);
drivers/spi/spi-sn-f-ospi.c
439
writel(OSPI_IRQ_CS_TRANS_COMP, ospi->base + OSPI_IRQ);
drivers/spi/spi-sn-f-ospi.c
446
writel(OSPI_SWRST_INDIR_READ_FIFO, ospi->base + OSPI_SWRST);
drivers/spi/spi-sn-f-ospi.c
484
writel(buf[i], ospi->base + OSPI_DAT);
drivers/spi/spi-sn-f-ospi.c
497
writel(OSPI_IRQ_CS_TRANS_COMP, ospi->base + OSPI_IRQ);
drivers/spi/spi-sn-f-ospi.c
595
writel(OSPI_ACC_MODE_BOOT_DISABLE, ospi->base + OSPI_ACC_MODE);
drivers/spi/spi-sun4i.c
97
writel(value, sspi->base_addr + reg);
drivers/spi/spi-sun6i.c
124
writel(value, sspi->base_addr + reg);
drivers/spi/spi-sunplus-sp7021.c
106
writel(data_status, pspim->s_base + SP7021_DATA_RDY_REG);
drivers/spi/spi-sunplus-sp7021.c
127
writel(value, pspim->s_base + SP7021_SLAVE_DMA_CTRL_REG);
drivers/spi/spi-sunplus-sp7021.c
128
writel(xfer->len, pspim->s_base + SP7021_SLAVE_DMA_LENGTH_REG);
drivers/spi/spi-sunplus-sp7021.c
129
writel(xfer->tx_dma, pspim->s_base + SP7021_SLAVE_DMA_ADDR_REG);
drivers/spi/spi-sunplus-sp7021.c
132
writel(value, pspim->s_base + SP7021_DATA_RDY_REG);
drivers/spi/spi-sunplus-sp7021.c
147
writel(value, pspim->s_base + SP7021_SLAVE_DMA_CTRL_REG);
drivers/spi/spi-sunplus-sp7021.c
148
writel(xfer->len, pspim->s_base + SP7021_SLAVE_DMA_LENGTH_REG);
drivers/spi/spi-sunplus-sp7021.c
149
writel(xfer->rx_dma, pspim->s_base + SP7021_SLAVE_DMA_ADDR_REG);
drivers/spi/spi-sunplus-sp7021.c
154
writel(SP7021_SLAVE_SW_RST, pspim->s_base + SP7021_SLAVE_DMA_CTRL_REG);
drivers/spi/spi-sunplus-sp7021.c
174
writel(pspim->tx_buf[pspim->tx_cur_len],
drivers/spi/spi-sunplus-sp7021.c
231
writel(value, pspim->m_base + SP7021_INT_BUSY_REG);
drivers/spi/spi-sunplus-sp7021.c
232
writel(SP7021_FINISH_FLAG, pspim->m_base + SP7021_SPI_STATUS_REG);
drivers/spi/spi-sunplus-sp7021.c
260
writel(valus, pspim->m_base + SP7021_SPI_STATUS_REG);
drivers/spi/spi-sunplus-sp7021.c
279
writel(pspim->xfer_conf, pspim->m_base + SP7021_SPI_CONFIG_REG);
drivers/spi/spi-sunplus-sp7021.c
295
writel(pspim->xfer_conf, pspim->m_base + SP7021_SPI_CONFIG_REG);
drivers/spi/spi-sunplus-sp7021.c
334
writel(reg_temp, pspim->m_base + SP7021_SPI_CONFIG_REG);
drivers/spi/spi-sunplus-sp7021.c
339
writel(reg_temp, pspim->m_base + SP7021_SPI_STATUS_REG);
drivers/spi/spi-sunplus-sp7021.c
349
writel(SP7021_FINISH_FLAG, pspim->m_base + SP7021_SPI_STATUS_REG);
drivers/spi/spi-sunplus-sp7021.c
350
writel(readl(pspim->m_base + SP7021_SPI_CONFIG_REG) &
drivers/spi/spi-sunplus-sp7021.c
355
writel(pspim->xfer_conf, pspim->m_base + SP7021_SPI_CONFIG_REG);
drivers/spi/spi-synquacer.c
321
writel(val, sspi->regs + SYNQUACER_HSSPI_REG_PCC(cs));
drivers/spi/spi-synquacer.c
327
writel(val, sspi->regs + SYNQUACER_HSSPI_REG_FIFOCFG);
drivers/spi/spi-synquacer.c
342
writel(val, sspi->regs + SYNQUACER_HSSPI_REG_DMSTART);
drivers/spi/spi-synquacer.c
366
writel(val, sspi->regs + SYNQUACER_HSSPI_REG_DMSTART);
drivers/spi/spi-synquacer.c
371
writel(val, sspi->regs + SYNQUACER_HSSPI_REG_FIFOCFG);
drivers/spi/spi-synquacer.c
437
writel(val, sspi->regs + SYNQUACER_HSSPI_REG_FIFOCFG);
drivers/spi/spi-synquacer.c
440
writel(~0, sspi->regs + SYNQUACER_HSSPI_REG_TXC);
drivers/spi/spi-synquacer.c
441
writel(~0, sspi->regs + SYNQUACER_HSSPI_REG_RXC);
drivers/spi/spi-synquacer.c
446
writel(val, sspi->regs + SYNQUACER_HSSPI_REG_DMSTART);
drivers/spi/spi-synquacer.c
450
writel(val, sspi->regs + SYNQUACER_HSSPI_REG_TXE);
drivers/spi/spi-synquacer.c
453
writel(0, sspi->regs + SYNQUACER_HSSPI_REG_TXE);
drivers/spi/spi-synquacer.c
461
writel(val, sspi->regs + SYNQUACER_HSSPI_REG_RXE);
drivers/spi/spi-synquacer.c
464
writel(0, sspi->regs + SYNQUACER_HSSPI_REG_RXE);
drivers/spi/spi-synquacer.c
469
writel(val, sspi->regs + SYNQUACER_HSSPI_REG_DMSTART);
drivers/spi/spi-synquacer.c
496
writel(val, sspi->regs + SYNQUACER_HSSPI_REG_DMSTART);
drivers/spi/spi-synquacer.c
527
writel(0, sspi->regs + SYNQUACER_HSSPI_REG_MCTRL);
drivers/spi/spi-synquacer.c
532
writel(0, sspi->regs + SYNQUACER_HSSPI_REG_TXE);
drivers/spi/spi-synquacer.c
533
writel(0, sspi->regs + SYNQUACER_HSSPI_REG_RXE);
drivers/spi/spi-synquacer.c
534
writel(~0, sspi->regs + SYNQUACER_HSSPI_REG_TXC);
drivers/spi/spi-synquacer.c
535
writel(~0, sspi->regs + SYNQUACER_HSSPI_REG_RXC);
drivers/spi/spi-synquacer.c
536
writel(~0, sspi->regs + SYNQUACER_HSSPI_REG_FAULTC);
drivers/spi/spi-synquacer.c
541
writel(val, sspi->regs + SYNQUACER_HSSPI_REG_DMCFG);
drivers/spi/spi-synquacer.c
554
writel(val, sspi->regs + SYNQUACER_HSSPI_REG_MCTRL);
drivers/spi/spi-synquacer.c
573
writel(0, sspi->regs + SYNQUACER_HSSPI_REG_RXE);
drivers/spi/spi-synquacer.c
590
writel(0, sspi->regs + SYNQUACER_HSSPI_REG_TXE);
drivers/spi/spi-tegra114.c
235
writel(val, tspi->base + reg);
drivers/spi/spi-tegra20-sflash.c
148
writel(val, tsd->base + reg);
drivers/spi/spi-tegra20-slink.c
218
writel(val, tspi->base + reg);
drivers/spi/spi-tegra210-quad.c
248
writel(value, tqspi->base + offset);
drivers/spi/spi-ti-qspi.c
135
writel(val, qspi->base + reg);
drivers/spi/spi-ti-qspi.c
265
writel(data, qspi->base +
drivers/spi/spi-ti-qspi.c
268
writel(data, qspi->base +
drivers/spi/spi-ti-qspi.c
271
writel(data, qspi->base +
drivers/spi/spi-ti-qspi.c
274
writel(data, qspi->base +
drivers/spi/spi-ti-qspi.c
293
writel(*((u32 *)txbuf), qspi->base + QSPI_SPI_DATA_REG);
drivers/spi/spi-uniphier.c
115
writel(val, priv->base + SSI_IE);
drivers/spi/spi-uniphier.c
125
writel(val, priv->base + SSI_IE);
drivers/spi/spi-uniphier.c
171
writel(val1, priv->base + SSI_CKS);
drivers/spi/spi-uniphier.c
172
writel(val2, priv->base + SSI_FPS);
drivers/spi/spi-uniphier.c
177
writel(val1, priv->base + SSI_TXWDS);
drivers/spi/spi-uniphier.c
178
writel(val1, priv->base + SSI_RXWDS);
drivers/spi/spi-uniphier.c
190
writel(val, priv->base + SSI_TXWDS);
drivers/spi/spi-uniphier.c
195
writel(val, priv->base + SSI_RXWDS);
drivers/spi/spi-uniphier.c
214
writel(val, priv->base + SSI_CKS);
drivers/spi/spi-uniphier.c
248
writel(val, priv->base + SSI_FC);
drivers/spi/spi-uniphier.c
275
writel(val, priv->base + SSI_TXDR);
drivers/spi/spi-uniphier.c
314
writel(val, priv->base + SSI_FC);
drivers/spi/spi-uniphier.c
346
writel(val, priv->base + SSI_FPS);
drivers/spi/spi-uniphier.c
560
writel(SSI_CTL_EN, priv->base + SSI_CTL);
drivers/spi/spi-uniphier.c
569
writel(0, priv->base + SSI_CTL);
drivers/spi/spi-uniphier.c
581
writel(0, priv->base + SSI_CTL);
drivers/spi/spi-uniphier.c
585
writel(val, priv->base + SSI_FC);
drivers/spi/spi-uniphier.c
607
writel(val, priv->base + SSI_IC);
drivers/spi/spi-xlp.c
113
writel(val, priv->base + regoff + cs * SPI_CS_OFFSET);
drivers/spi/spi-xlp.c
119
writel(val, priv->base + regoff);
drivers/spmi/hisi-spmi-controller.c
152
writel(cmd, spmi_controller->base + chnl_ofst + SPMI_APB_SPMI_CMD_BASE_ADDR);
drivers/spmi/hisi-spmi-controller.c
239
writel((u32 __force)cpu_to_be32(data),
drivers/spmi/hisi-spmi-controller.c
246
writel(cmd, spmi_controller->base + chnl_ofst + SPMI_APB_SPMI_CMD_BASE_ADDR);
drivers/spmi/spmi-apple-controller.c
101
writel(spmi_cmd, spmi->regs + SPMI_CMD_REG);
drivers/spmi/spmi-apple-controller.c
109
writel(spmi_cmd, spmi->regs + SPMI_CMD_REG);
drivers/spmi/spmi-apple-controller.c
71
writel(spmi_cmd, spmi->regs + SPMI_CMD_REG);
drivers/spmi/spmi-mtk-pmif.c
299
writel(val, pbus->base + arb->data->regs[reg]);
drivers/spmi/spmi-mtk-pmif.c
310
writel(val, pbus->spmimst_base + arb->data->spmimst_regs[reg]);
drivers/ssb/driver_pcicore.c
196
writel(val, mmio);
drivers/ssb/host_soc.c
110
writel(value, bus->mmio + offset);
drivers/staging/media/atomisp/pci/atomisp_compat_css20.c
82
writel(data, isp->base + (addr & 0x003FFFFF));
drivers/staging/media/imx/imx6-mipi-csi2.c
135
writel(0x1, csi2->base + CSI2_PHY_SHUTDOWNZ);
drivers/staging/media/imx/imx6-mipi-csi2.c
136
writel(0x1, csi2->base + CSI2_DPHY_RSTZ);
drivers/staging/media/imx/imx6-mipi-csi2.c
137
writel(0x1, csi2->base + CSI2_RESETN);
drivers/staging/media/imx/imx6-mipi-csi2.c
139
writel(0x0, csi2->base + CSI2_PHY_SHUTDOWNZ);
drivers/staging/media/imx/imx6-mipi-csi2.c
140
writel(0x0, csi2->base + CSI2_DPHY_RSTZ);
drivers/staging/media/imx/imx6-mipi-csi2.c
141
writel(0x0, csi2->base + CSI2_RESETN);
drivers/staging/media/imx/imx6-mipi-csi2.c
147
writel(lanes - 1, csi2->base + CSI2_N_LANES);
drivers/staging/media/imx/imx6-mipi-csi2.c
154
writel(PHY_TESTCLR, csi2->base + CSI2_PHY_TST_CTRL0);
drivers/staging/media/imx/imx6-mipi-csi2.c
155
writel(0x0, csi2->base + CSI2_PHY_TST_CTRL1);
drivers/staging/media/imx/imx6-mipi-csi2.c
156
writel(0x0, csi2->base + CSI2_PHY_TST_CTRL0);
drivers/staging/media/imx/imx6-mipi-csi2.c
159
writel(PHY_TESTCLK, csi2->base + CSI2_PHY_TST_CTRL0);
drivers/staging/media/imx/imx6-mipi-csi2.c
162
writel(PHY_TESTEN | test_code, csi2->base + CSI2_PHY_TST_CTRL1);
drivers/staging/media/imx/imx6-mipi-csi2.c
163
writel(0x0, csi2->base + CSI2_PHY_TST_CTRL0);
drivers/staging/media/imx/imx6-mipi-csi2.c
166
writel(test_data, csi2->base + CSI2_PHY_TST_CTRL1);
drivers/staging/media/imx/imx6-mipi-csi2.c
167
writel(PHY_TESTCLK, csi2->base + CSI2_PHY_TST_CTRL0);
drivers/staging/media/imx/imx6-mipi-csi2.c
170
writel(0x0, csi2->base + CSI2_PHY_TST_CTRL0);
drivers/staging/media/imx/imx6-mipi-csi2.c
301
writel(reg, csi2->base + CSI2IPU_GASKET);
drivers/staging/media/ipu3/ipu3-css.c
1099
writel(data, &q->host2sp_bufq[thread][queue][end]);
drivers/staging/media/ipu3/ipu3-css.c
1102
writel(data, &q->host2sp_evtq[end]);
drivers/staging/media/ipu3/ipu3-css.c
184
writel(*buf++, addr);
drivers/staging/media/ipu3/ipu3-css.c
209
writel(0, base + IMGU_REG_GP_BUSY);
drivers/staging/media/ipu3/ipu3-css.c
219
writel(readl(base + IMGU_REG_PM_CTRL) | IMGU_PM_CTRL_FORCE_RESET,
drivers/staging/media/ipu3/ipu3-css.c
2323
writel(imgu_status, base + IMGU_REG_INT_STATUS);
drivers/staging/media/ipu3/ipu3-css.c
234
writel(IMGU_PM_CTRL_RACE_TO_HALT | IMGU_PM_CTRL_START,
drivers/staging/media/ipu3/ipu3-css.c
2342
writel(irq_status[i], base + IMGU_REG_IRQCTRL_CLEAR(i));
drivers/staging/media/ipu3/ipu3-css.c
243
writel(IMGU_PM_CTRL_RACE_TO_HALT, base + IMGU_REG_PM_CTRL);
drivers/staging/media/ipu3/ipu3-css.c
247
writel(readl(base + IMGU_REG_GP_BUSY) | 1, base + IMGU_REG_GP_BUSY);
drivers/staging/media/ipu3/ipu3-css.c
252
writel(val, base + IMGU_REG_PM_CTRL);
drivers/staging/media/ipu3/ipu3-css.c
253
writel(0, base + IMGU_REG_GP_BUSY);
drivers/staging/media/ipu3/ipu3-css.c
260
writel(val, base + IMGU_REG_SYSTEM_REQ);
drivers/staging/media/ipu3/ipu3-css.c
261
writel(1, base + IMGU_REG_GP_BUSY);
drivers/staging/media/ipu3/ipu3-css.c
262
writel(readl(base + IMGU_REG_PM_CTRL) | IMGU_PM_CTRL_FORCE_HALT,
drivers/staging/media/ipu3/ipu3-css.c
270
writel(readl(base + IMGU_REG_PM_CTRL) | IMGU_PM_CTRL_START,
drivers/staging/media/ipu3/ipu3-css.c
276
writel(readl(base + IMGU_REG_PM_CTRL) | IMGU_PM_CTRL_FORCE_UNHALT,
drivers/staging/media/ipu3/ipu3-css.c
282
writel(val, base + IMGU_REG_PM_CTRL);
drivers/staging/media/ipu3/ipu3-css.c
305
writel(1, base + IMGU_REG_GP_HALT);
drivers/staging/media/ipu3/ipu3-css.c
311
writel(0, base + IMGU_REG_GP_BUSY);
drivers/staging/media/ipu3/ipu3-css.c
326
writel(val, base + IMGU_REG_SP_CTRL(0));
drivers/staging/media/ipu3/ipu3-css.c
327
writel(val | IMGU_CTRL_IRQ_CLEAR, base + IMGU_REG_SP_CTRL(0));
drivers/staging/media/ipu3/ipu3-css.c
330
writel(IMGU_REG_INT_CSS_IRQ, base + IMGU_REG_INT_ENABLE);
drivers/staging/media/ipu3/ipu3-css.c
332
writel(IMGU_REG_INT_CSS_IRQ, base + IMGU_REG_INT_STATUS);
drivers/staging/media/ipu3/ipu3-css.c
335
writel(~0, base + IMGU_REG_IRQCTRL_EDGE_NOT_PULSE(IMGU_IRQCTRL_MAIN));
drivers/staging/media/ipu3/ipu3-css.c
336
writel(0, base + IMGU_REG_IRQCTRL_MASK(IMGU_IRQCTRL_MAIN));
drivers/staging/media/ipu3/ipu3-css.c
337
writel(IMGU_IRQCTRL_IRQ_MASK,
drivers/staging/media/ipu3/ipu3-css.c
339
writel(IMGU_IRQCTRL_IRQ_MASK,
drivers/staging/media/ipu3/ipu3-css.c
341
writel(IMGU_IRQCTRL_IRQ_MASK,
drivers/staging/media/ipu3/ipu3-css.c
343
writel(IMGU_IRQCTRL_IRQ_MASK,
drivers/staging/media/ipu3/ipu3-css.c
350
writel(~0, base + IMGU_REG_IRQCTRL_EDGE_NOT_PULSE(i));
drivers/staging/media/ipu3/ipu3-css.c
351
writel(0, base + IMGU_REG_IRQCTRL_MASK(i));
drivers/staging/media/ipu3/ipu3-css.c
352
writel(IMGU_IRQCTRL_IRQ_MASK, base + IMGU_REG_IRQCTRL_EDGE(i));
drivers/staging/media/ipu3/ipu3-css.c
353
writel(IMGU_IRQCTRL_IRQ_MASK,
drivers/staging/media/ipu3/ipu3-css.c
355
writel(IMGU_IRQCTRL_IRQ_MASK, base + IMGU_REG_IRQCTRL_CLEAR(i));
drivers/staging/media/ipu3/ipu3-css.c
356
writel(IMGU_IRQCTRL_IRQ_MASK, base + IMGU_REG_IRQCTRL_MASK(i));
drivers/staging/media/ipu3/ipu3-css.c
422
writel(css->binary[css->fw_sp[i]].daddr,
drivers/staging/media/ipu3/ipu3-css.c
424
writel(readl(base + IMGU_REG_SP_CTRL(bi->type)) |
drivers/staging/media/ipu3/ipu3-css.c
428
writel(css->binary[css->fw_bl].daddr, base + IMGU_REG_ISP_ICACHE_ADDR);
drivers/staging/media/ipu3/ipu3-css.c
429
writel(readl(base + IMGU_REG_ISP_CTRL) | IMGU_CTRL_ICACHE_INV,
drivers/staging/media/ipu3/ipu3-css.c
460
writel(val0 | (val1 << 16),
drivers/staging/media/ipu3/ipu3-css.c
462
writel(val2 | (val3 << 16),
drivers/staging/media/ipu3/ipu3-css.c
487
writel(bi->info.sp.sp_entry, base + IMGU_REG_SP_START_ADDR(sp));
drivers/staging/media/ipu3/ipu3-css.c
489
writel(readl(base + IMGU_REG_SP_CTRL(sp))
drivers/staging/media/ipu3/ipu3-css.c
521
writel(IMGU_TLB_INVALIDATE, base + IMGU_REG_TLB_INVALIDATE);
drivers/staging/media/ipu3/ipu3-css.c
525
writel(IMGU_ABI_BL_SWSTATE_BUSY,
drivers/staging/media/ipu3/ipu3-css.c
527
writel(IMGU_NUM_SP,
drivers/staging/media/ipu3/ipu3-css.c
547
writel(bl->info.bl.bl_entry, base + IMGU_REG_ISP_START_ADDR);
drivers/staging/media/ipu3/ipu3-css.c
549
writel(readl(base + IMGU_REG_ISP_CTRL)
drivers/staging/media/ipu3/ipu3-css.c
565
writel(css->xmem_sp_group_ptrs.daddr,
drivers/staging/media/ipu3/ipu3-css.c
568
writel(IMGU_ABI_SP_SWSTATE_TERMINATED,
drivers/staging/media/ipu3/ipu3-css.c
570
writel(1, base + IMGU_REG_SP_DMEM_BASE(0) + bi->info.sp.invalidate_tlb);
drivers/staging/media/ipu3/ipu3-css.c
575
writel(0, base + IMGU_REG_SP_DMEM_BASE(0) + bi->info.sp.isp_started);
drivers/staging/media/ipu3/ipu3-css.c
576
writel(0, base + IMGU_REG_SP_DMEM_BASE(0) +
drivers/staging/media/ipu3/ipu3-css.c
578
writel(0, base + IMGU_REG_SP_DMEM_BASE(0) + bi->info.sp.sleep_mode);
drivers/staging/media/ipu3/ipu3-css.c
579
writel(0, base + IMGU_REG_SP_DMEM_BASE(0) + bi->info.sp.invalidate_tlb);
drivers/staging/media/ipu3/ipu3-css.c
580
writel(IMGU_ABI_SP_COMM_COMMAND_READY, base + IMGU_REG_SP_DMEM_BASE(0)
drivers/staging/media/ipu3/ipu3-css.c
586
writel(event_mask, base + IMGU_REG_SP_DMEM_BASE(0)
drivers/staging/media/ipu3/ipu3-css.c
589
writel(1, base + IMGU_REG_SP_DMEM_BASE(0) +
drivers/staging/media/ipu3/ipu3-css.c
596
writel(IMGU_ABI_SP_SWSTATE_TERMINATED,
drivers/staging/media/ipu3/ipu3-css.c
602
writel(IMGU_ABI_SP_COMM_COMMAND_READY, base + IMGU_REG_SP_DMEM_BASE(1)
drivers/staging/media/ipu3/ipu3-css.c
614
writel(IMGU_ABI_SP_COMM_COMMAND_TERMINATE,
drivers/staging/media/ipu3/ipu3-css.c
636
writel(0, base + IMGU_REG_GP_BUSY);
drivers/staging/media/ipu3/ipu3-css.c
644
writel(readl(base + IMGU_REG_PM_CTRL) | IMGU_PM_CTRL_FORCE_RESET,
drivers/staging/media/ipu3/ipu3-mmu.c
106
writel(halt, mmu->base + REG_GP_HALT);
drivers/staging/media/ipu3/ipu3-mmu.c
477
writel(pteval, mmu->base + REG_L1_PHYS);
drivers/staging/media/ipu3/ipu3-mmu.c
533
writel(pteval, mmu->base + REG_L1_PHYS);
drivers/staging/media/ipu3/ipu3-mmu.c
80
writel(TLB_INVALIDATE, mmu->base + REG_TLB_INVALIDATE);
drivers/staging/media/ipu7/ipu7-boot.c
105
writel(val, base + ucx_ctrl_status);
drivers/staging/media/ipu7/ipu7-boot.c
122
writel(val, base + ucx_ctrl_status);
drivers/staging/media/ipu7/ipu7-boot.c
149
writel(val, base + ctx->status_ctrl_reg);
drivers/staging/media/ipu7/ipu7-boot.c
165
writel(val, base + ctx->status_ctrl_reg);
drivers/staging/media/ipu7/ipu7-boot.c
174
writel(val, base + ctx->status_ctrl_reg);
drivers/staging/media/ipu7/ipu7-boot.c
184
writel(adev->fw_entry, base + ctx->fw_start_address_reg);
drivers/staging/media/ipu7/ipu7-boot.c
73
writel(val, base + get_fw_boot_reg_addr(adev, reg));
drivers/staging/media/ipu7/ipu7-buttress.c
1020
writel(val, base + BUTTRESS_REG_TSC_CTL);
drivers/staging/media/ipu7/ipu7-buttress.c
1022
writel(val, base + BUTTRESS_REG_TSC_CTL);
drivers/staging/media/ipu7/ipu7-buttress.c
1071
writel(val, isp->base + BUTTRESS_REG_DRV_IS_UCX_CONTROL_STATUS);
drivers/staging/media/ipu7/ipu7-buttress.c
1081
writel(val, isp->base + BUTTRESS_REG_DRV_PS_UCX_CONTROL_STATUS);
drivers/staging/media/ipu7/ipu7-buttress.c
1097
writel(0, isp->pb_base + GLOBAL_INTERRUPT_MASK);
drivers/staging/media/ipu7/ipu7-buttress.c
1105
writel(val, isp->pb_base + BAR2_MISC_CONFIG);
drivers/staging/media/ipu7/ipu7-buttress.c
1109
writel(BIT(13), isp->pb_base + TLBID_HASH_ENABLE_63_32);
drivers/staging/media/ipu7/ipu7-buttress.c
1110
writel(BIT(9), isp->pb_base + TLBID_HASH_ENABLE_95_64);
drivers/staging/media/ipu7/ipu7-buttress.c
1115
writel(BIT(14), isp->pb_base + TLBID_HASH_ENABLE_63_32);
drivers/staging/media/ipu7/ipu7-buttress.c
1116
writel(BIT(9), isp->pb_base + TLBID_HASH_ENABLE_95_64);
drivers/staging/media/ipu7/ipu7-buttress.c
112
writel(ENTRY | EXIT, isp->base + ipc->csr_in);
drivers/staging/media/ipu7/ipu7-buttress.c
1121
writel(BIT(22), isp->pb_base + TLBID_HASH_ENABLE_63_32);
drivers/staging/media/ipu7/ipu7-buttress.c
1122
writel(BIT(1), isp->pb_base + TLBID_HASH_ENABLE_127_96);
drivers/staging/media/ipu7/ipu7-buttress.c
1128
writel(BUTTRESS_IRQS, isp->base + BUTTRESS_REG_IRQ_CLEAR);
drivers/staging/media/ipu7/ipu7-buttress.c
1129
writel(BUTTRESS_IRQS, isp->base + BUTTRESS_REG_IRQ_MASK);
drivers/staging/media/ipu7/ipu7-buttress.c
113
writel(QUERY, isp->base + ipc->csr_out);
drivers/staging/media/ipu7/ipu7-buttress.c
1130
writel(BUTTRESS_IRQS, isp->base + BUTTRESS_REG_IRQ_ENABLE);
drivers/staging/media/ipu7/ipu7-buttress.c
1132
writel(PS_FSM_CG, isp->base + BUTTRESS_REG_CG_CTRL_BITS);
drivers/staging/media/ipu7/ipu7-buttress.c
1141
writel(b->wdt_cached_value, isp->base + BUTTRESS_REG_IDLE_WDT);
drivers/staging/media/ipu7/ipu7-buttress.c
1202
writel(0, isp->base + BUTTRESS_REG_IRQ_ENABLE);
drivers/staging/media/ipu7/ipu7-buttress.c
124
writel(ENTRY | QUERY, isp->base + ipc->csr_in);
drivers/staging/media/ipu7/ipu7-buttress.c
125
writel(ENTRY, isp->base + ipc->csr_out);
drivers/staging/media/ipu7/ipu7-buttress.c
142
writel(EXIT, isp->base + ipc->csr_in);
drivers/staging/media/ipu7/ipu7-buttress.c
143
writel(0, isp->base + ipc->db0_in);
drivers/staging/media/ipu7/ipu7-buttress.c
144
writel(csr_in_clr, isp->base + ipc->csr_in);
drivers/staging/media/ipu7/ipu7-buttress.c
145
writel(EXIT, isp->base + ipc->csr_out);
drivers/staging/media/ipu7/ipu7-buttress.c
167
writel(QUERY, isp->base + ipc->csr_in);
drivers/staging/media/ipu7/ipu7-buttress.c
168
writel(ENTRY, isp->base + ipc->csr_out);
drivers/staging/media/ipu7/ipu7-buttress.c
185
writel(BUTTRESS_IU2CSECSR_IPC_PEER_DEASSERTED_REG_VALID_REQ,
drivers/staging/media/ipu7/ipu7-buttress.c
198
writel(BUTTRESS_IU2CSECSR_IPC_PEER_ASSERTED_REG_VALID_REQ,
drivers/staging/media/ipu7/ipu7-buttress.c
217
writel(0, isp->base + ipc->db0_in);
drivers/staging/media/ipu7/ipu7-buttress.c
249
writel(msg->cmd, isp->base + ipc->data0_out);
drivers/staging/media/ipu7/ipu7-buttress.c
251
writel(val, isp->base + ipc->db0_out);
drivers/staging/media/ipu7/ipu7-buttress.c
263
writel(0, isp->base + ipc->db0_out);
drivers/staging/media/ipu7/ipu7-buttress.c
352
writel(pb_irq, isp->pb_base + INTERRUPT_STATUS);
drivers/staging/media/ipu7/ipu7-buttress.c
389
writel(irq_status, isp->base + BUTTRESS_REG_IRQ_CLEAR);
drivers/staging/media/ipu7/ipu7-buttress.c
434
writel(BUTTRESS_IRQS & ~disable_irqs,
drivers/staging/media/ipu7/ipu7-buttress.c
460
writel(BUTTRESS_IRQS, isp->base + BUTTRESS_REG_IRQ_ENABLE);
drivers/staging/media/ipu7/ipu7-buttress.c
481
writel(val, isp->base + BUTTRESS_REG_D2D_CTL);
drivers/staging/media/ipu7/ipu7-buttress.c
517
writel(val, isp->base + nde_reg);
drivers/staging/media/ipu7/ipu7-buttress.c
543
writel(val, isp->base + BUTTRESS_REG_SLEEP_LEVEL_CFG);
drivers/staging/media/ipu7/ipu7-buttress.c
555
writel(val, isp->base + ctrl->freq_ctl);
drivers/staging/media/ipu7/ipu7-buttress.c
572
writel(val, isp->base + BUTTRESS_REG_SLEEP_LEVEL_CFG);
drivers/staging/media/ipu7/ipu7-buttress.c
597
writel(val, isp->base + ctrl->freq_ctl);
drivers/staging/media/ipu7/ipu7-buttress.c
642
writel(1, isp->base + BUTTRESS_REG_PS_PLL_ENABLE);
drivers/staging/media/ipu7/ipu7-buttress.c
654
writel(val, isp->base + ctrl->freq_ctl);
drivers/staging/media/ipu7/ipu7-buttress.c
692
writel(val, isp->base + ctrl->freq_ctl);
drivers/staging/media/ipu7/ipu7-buttress.c
713
writel(0, isp->base + BUTTRESS_REG_PS_PLL_ENABLE);
drivers/staging/media/ipu7/ipu7-buttress.c
824
writel(BUTTRESS_FW_RESET_CTL_START, isp->base +
drivers/staging/media/ipu7/ipu7-buttress.c
83
writel(val, isp->base + ipc->csr_in);
drivers/staging/media/ipu7/ipu7-buttress.c
836
writel(0, isp->base + BUTTRESS_REG_FW_RESET_CTL);
drivers/staging/media/ipu7/ipu7-buttress.c
86
writel(ENTRY, isp->base + ipc->csr_out);
drivers/staging/media/ipu7/ipu7-buttress.c
867
writel(isp->cpd_fw->size, isp->base + BUTTRESS_REG_FW_SOURCE_SIZE);
drivers/staging/media/ipu7/ipu7-buttress.c
868
writel(sg_dma_address(isp->psys->fw_sgt.sgl),
drivers/staging/media/ipu7/ipu7-buttress.c
956
writel(BUTTRESS_TSC_CMD_START_TSC_SYNC,
drivers/staging/media/ipu7/ipu7-buttress.c
997
writel(val, base + BUTTRESS_REG_TSC_CTL);
drivers/staging/media/ipu7/ipu7-isys-csi-phy.c
162
writel(data, base + addr);
drivers/staging/media/ipu7/ipu7-isys-csi-phy.c
176
writel(data, base + addr);
drivers/staging/media/ipu7/ipu7-isys-csi2.c
100
writel(mask, csi2->base + offset + IRQ_CTL_MASK);
drivers/staging/media/ipu7/ipu7-isys-csi2.c
101
writel(mask, csi2->base + offset + IRQ_CTL_ENABLE);
drivers/staging/media/ipu7/ipu7-isys-csi2.c
106
writel(mask, csi2->base + offset + IRQ_CTL_CLEAR);
drivers/staging/media/ipu7/ipu7-isys-csi2.c
107
writel(mask, csi2->base + offset + IRQ_CTL_MASK);
drivers/staging/media/ipu7/ipu7-isys-csi2.c
108
writel(mask, csi2->base + offset + IRQ_CTL_ENABLE);
drivers/staging/media/ipu7/ipu7-isys-csi2.c
112
writel(mask, csi2->base + offset + IRQ1_CTL_CLEAR);
drivers/staging/media/ipu7/ipu7-isys-csi2.c
113
writel(mask, csi2->base + offset + IRQ1_CTL_MASK);
drivers/staging/media/ipu7/ipu7-isys-csi2.c
114
writel(mask, csi2->base + offset + IRQ1_CTL_ENABLE);
drivers/staging/media/ipu7/ipu7-isys-csi2.c
126
writel(mask, csi2->base + offset + IRQ_CTL_CLEAR);
drivers/staging/media/ipu7/ipu7-isys-csi2.c
127
writel(0, csi2->base + offset + IRQ_CTL_MASK);
drivers/staging/media/ipu7/ipu7-isys-csi2.c
128
writel(0, csi2->base + offset + IRQ_CTL_ENABLE);
drivers/staging/media/ipu7/ipu7-isys-csi2.c
133
writel(mask, csi2->base + offset + IRQ_CTL_CLEAR);
drivers/staging/media/ipu7/ipu7-isys-csi2.c
134
writel(0, csi2->base + offset + IRQ_CTL_MASK);
drivers/staging/media/ipu7/ipu7-isys-csi2.c
135
writel(0, csi2->base + offset + IRQ_CTL_ENABLE);
drivers/staging/media/ipu7/ipu7-isys-csi2.c
138
writel(mask, csi2->base + offset + IRQ1_CTL_CLEAR);
drivers/staging/media/ipu7/ipu7-isys-csi2.c
139
writel(0, csi2->base + offset + IRQ1_CTL_MASK);
drivers/staging/media/ipu7/ipu7-isys-csi2.c
140
writel(0, csi2->base + offset + IRQ1_CTL_ENABLE);
drivers/staging/media/ipu7/ipu7-isys-csi2.c
151
writel(0x4, isys_base + IS_IO_GPREGS_BASE + CLK_DIV_FACTOR_APB_CLK);
drivers/staging/media/ipu7/ipu7-isys-csi2.c
167
writel(0x2, isys_base + offset + CLK_DIV_FACTOR_APB_CLK);
drivers/staging/media/ipu7/ipu7-isys-csi2.c
173
writel(0x1, isys_base + offset + CSI_PORTAB_AGGREGATION);
drivers/staging/media/ipu7/ipu7-isys-csi2.c
178
writel(CSI_SENSOR_INPUT, isys_base + offset + CSI2_ADPL_INPUT_MODE);
drivers/staging/media/ipu7/ipu7-isys-csi2.c
179
writel(1, isys_base + offset + CSI2_ADPL_CSI_RX_ERR_IRQ_CLEAR_EN);
drivers/staging/media/ipu7/ipu7-isys-csi2.c
99
writel(mask, csi2->base + offset + IRQ_CTL_CLEAR);
drivers/staging/media/ipu7/ipu7-isys.c
1041
writel(sync, csi2->base + offset + IRQ_CTL_CLEAR);
drivers/staging/media/ipu7/ipu7-isys.c
1046
writel(fe, csi2->base + offset + IRQ1_CTL_CLEAR);
drivers/staging/media/ipu7/ipu7-isys.c
1101
writel(status_sw, base + sw_offset + TO_SW_IRQ_CNTL_CLEAR);
drivers/staging/media/ipu7/ipu7-isys.c
1102
writel(status_csi, base + csi_offset + IRQ_CTL_CLEAR);
drivers/staging/media/ipu7/ipu7-isys.c
1126
writel(TO_SW_IRQ_MASK, base + sw_offset + TO_SW_IRQ_CNTL_MASK_N);
drivers/staging/media/ipu7/ipu7-isys.c
449
writel(mask, base + offset + IRQ_CTL_CLEAR);
drivers/staging/media/ipu7/ipu7-isys.c
450
writel(0, base + offset + IRQ_CTL_ENABLE);
drivers/staging/media/ipu7/ipu7-isys.c
454
writel(mask, base + offset + IRQ_CTL_EDGE);
drivers/staging/media/ipu7/ipu7-isys.c
455
writel(mask, base + offset + IRQ_CTL_CLEAR);
drivers/staging/media/ipu7/ipu7-isys.c
456
writel(mask, base + offset + IRQ_CTL_MASK);
drivers/staging/media/ipu7/ipu7-isys.c
457
writel(mask, base + offset + IRQ_CTL_ENABLE);
drivers/staging/media/ipu7/ipu7-isys.c
467
writel(0, base + offset + TO_SW_IRQ_CNTL_ENABLE);
drivers/staging/media/ipu7/ipu7-isys.c
471
writel(mask, base + offset + TO_SW_IRQ_CNTL_CLEAR);
drivers/staging/media/ipu7/ipu7-isys.c
472
writel(mask, base + offset + TO_SW_IRQ_CNTL_MASK_N);
drivers/staging/media/ipu7/ipu7-isys.c
473
writel(mask, base + offset + TO_SW_IRQ_CNTL_ENABLE);
drivers/staging/media/ipu7/ipu7-isys.c
484
writel(0x0, base + offset + CLK_EN_TXCLKESC);
drivers/staging/media/ipu7/ipu7-isys.c
486
writel(0x0, base + offset + CLK_DIV_FACTOR_IS_CLK);
drivers/staging/media/ipu7/ipu7-isys.c
488
writel(0x200, base + IS_UC_CTRL_BASE + PRINTF_AXI_CNTL);
drivers/staging/media/ipu7/ipu7-isys.c
833
writel(status & mask, csi2->base + offset + IRQ_CTL_CLEAR);
drivers/staging/media/ipu7/ipu7-mmu.c
467
writel((phys_addr_t)mmu_info->l1_pt_dma,
drivers/staging/media/ipu7/ipu7-mmu.c
473
writel(mmu_hw->info_bits,
drivers/staging/media/ipu7/ipu7-mmu.c
475
writel(mmu_hw->refill, mmu_hw->base + MMU_REG_AXI_REFILL_IF_ID);
drivers/staging/media/ipu7/ipu7-mmu.c
476
writel(mmu_hw->collapse_en_bitmap,
drivers/staging/media/ipu7/ipu7-mmu.c
484
writel(mmu_hw->at_sp_arb_cfg,
drivers/staging/media/ipu7/ipu7-mmu.c
488
writel(0x3ff, mmu_hw->base + MMU_REG_IRQ_MASK);
drivers/staging/media/ipu7/ipu7-mmu.c
489
writel(0x3ff, mmu_hw->base + MMU_REG_IRQ_ENABLE);
drivers/staging/media/ipu7/ipu7-mmu.c
493
writel(mmu_hw->l1_block_sz[j], mmu_hw->base +
drivers/staging/media/ipu7/ipu7-mmu.c
498
writel(mmu_hw->l2_block_sz[j], mmu_hw->base +
drivers/staging/media/ipu7/ipu7-mmu.c
505
writel(mmu_hw->uao_p2tlb[j], mmu_hw->uao_base + 4U * j);
drivers/staging/media/ipu7/ipu7-mmu.c
524
writel(mmu_hw->zlx_axi_pool[j],
drivers/staging/media/ipu7/ipu7-mmu.c
532
writel(mmu_hw->zlx_conf[j],
drivers/staging/media/ipu7/ipu7-mmu.c
540
writel(mmu_hw->zlx_en[j],
drivers/staging/media/ipu7/ipu7-mmu.c
65
writel(0x1ffff, mmu->mmu_hw[i].base + MMU_REG_IRQ_CLEAR);
drivers/staging/media/ipu7/ipu7-mmu.c
83
writel(0xffffffffU, mmu->mmu_hw[i].base +
drivers/staging/media/ipu7/ipu7-mmu.c
88
writel(0xffffffffU, mmu->mmu_hw[i].base +
drivers/staging/media/ipu7/ipu7-syscom.c
68
writel((index + 1U) % queue_params->max_capacity,
drivers/staging/media/sunxi/cedrus/cedrus.h
212
writel(val, dev->base + reg);
drivers/staging/media/tegra-video/tegra20.c
153
writel(val, chan->vi->iomem + addr);
drivers/staging/media/tegra-video/tegra20.c
245
writel(val, apb_misc + reg_offset);
drivers/staging/most/dim2/dim2.c
1006
writel(0x0, dev->io_base + 0x600);
drivers/staging/most/dim2/dim2.c
1028
writel(0x04, dev->io_base + 0x600);
drivers/staging/most/dim2/dim2.c
1030
writel(enable_512fs, dev->io_base + 0x604);
drivers/staging/most/dim2/dim2.c
1033
writel(0x03, dev->io_base + 0x500);
drivers/staging/most/dim2/dim2.c
1034
writel(0x0002FF02, dev->io_base + 0x508);
drivers/staging/most/dim2/dim2.c
1046
writel(0x0, dev->io_base + 0x600);
drivers/staging/most/dim2/dim2.c
948
writel(0x888, dev->io_base + 0x38);
drivers/staging/most/dim2/dim2.c
984
writel(0x03, dev->io_base + 0x600);
drivers/staging/most/dim2/dim2.c
986
writel(0x888, dev->io_base + 0x38);
drivers/staging/most/dim2/dim2.c
989
writel(0x04, dev->io_base + 0x600);
drivers/staging/most/dim2/dim2.c
993
writel(0x03, dev->io_base + 0x500);
drivers/staging/most/dim2/dim2.c
994
writel(0x0002FF02, dev->io_base + 0x508);
drivers/staging/most/dim2/hal.c
147
writel(val, &g.dim2->MADR);
drivers/staging/most/dim2/hal.c
153
writel(0, &g.dim2->MCTL); /* clear transfer complete */
drivers/staging/most/dim2/hal.c
163
writel(0, &g.dim2->MCTL); /* clear transfer complete */
drivers/staging/most/dim2/hal.c
164
writel(0, &g.dim2->MDAT0);
drivers/staging/most/dim2/hal.c
181
writel(0, &g.dim2->MCTL); /* clear transfer complete */
drivers/staging/most/dim2/hal.c
184
writel(value[0], &g.dim2->MDAT0);
drivers/staging/most/dim2/hal.c
186
writel(value[1], &g.dim2->MDAT1);
drivers/staging/most/dim2/hal.c
188
writel(value[2], &g.dim2->MDAT2);
drivers/staging/most/dim2/hal.c
190
writel(value[3], &g.dim2->MDAT3);
drivers/staging/most/dim2/hal.c
192
writel(mask[0], &g.dim2->MDWE0);
drivers/staging/most/dim2/hal.c
193
writel(mask[1], &g.dim2->MDWE1);
drivers/staging/most/dim2/hal.c
194
writel(mask[2], &g.dim2->MDWE2);
drivers/staging/most/dim2/hal.c
195
writel(mask[3], &g.dim2->MDWE3);
drivers/staging/most/dim2/hal.c
359
writel(readl(&g.dim2->ACMR0) | bit_mask(ch_addr), &g.dim2->ACMR0);
drivers/staging/most/dim2/hal.c
365
writel(readl(&g.dim2->ACMR0) & ~bit_mask(ch_addr), &g.dim2->ACMR0);
drivers/staging/most/dim2/hal.c
374
writel(bit_mask(ch_addr), &g.dim2->ACSR0);
drivers/staging/most/dim2/hal.c
518
writel(false << MLBC0_MLBEN_BIT, &g.dim2->MLBC0);
drivers/staging/most/dim2/hal.c
523
writel(0, &g.dim2->MIEN);
drivers/staging/most/dim2/hal.c
526
writel(0xFFFFFFFF, &g.dim2->ACSR0);
drivers/staging/most/dim2/hal.c
527
writel(0xFFFFFFFF, &g.dim2->ACSR1);
drivers/staging/most/dim2/hal.c
530
writel(0, &g.dim2->ACMR0);
drivers/staging/most/dim2/hal.c
531
writel(0, &g.dim2->ACMR1);
drivers/staging/most/dim2/hal.c
539
writel(enable_6pin << MLBC0_MLBPEN_BIT |
drivers/staging/most/dim2/hal.c
546
writel(0xFFFFFFFF, &g.dim2->HCMR0);
drivers/staging/most/dim2/hal.c
547
writel(0xFFFFFFFF, &g.dim2->HCMR1);
drivers/staging/most/dim2/hal.c
550
writel(bit_mask(HCTL_EN_BIT), &g.dim2->HCTL);
drivers/staging/most/dim2/hal.c
553
writel(ACTL_DMA_MODE_VAL_DMA_MODE_1 << ACTL_DMA_MODE_BIT |
drivers/staging/most/dim2/hal.c
565
writel(c1 & nda_mask, &g.dim2->MLBC1);
drivers/staging/most/dim2/hal.c
590
writel(bit_mask(ch_addr), &g.dim2->ACSR0);
drivers/staging/most/dim2/hal.c
776
writel(0, &g.dim2->MS0);
drivers/staging/most/dim2/hal.c
777
writel(0, &g.dim2->MS1);
drivers/staging/most/dim2/hal.c
824
writel(bit_mask(20), &g.dim2->MIEN);
drivers/staging/most/dim2/hal.c
891
writel(0, &g.dim2->MIEN);
drivers/staging/sm750fb/ddk750_chip.h
23
writel(data, addr + mmio750);
drivers/staging/sm750fb/sm750_accel.c
22
writel(reg_value, accel->dpr_base + offset);
drivers/staging/sm750fb/sm750_accel.c
32
writel(data, accel->dp_port_base);
drivers/staging/sm750fb/sm750_cursor.c
22
writel((data), cursor->mmio + (addr))
drivers/thermal/airoha_thermal.c
268
writel(TEMP_TO_RAW(priv, high) >> 4,
drivers/thermal/airoha_thermal.c
280
writel(TEMP_TO_RAW(priv, low) >> 4,
drivers/thermal/airoha_thermal.c
288
writel(EN7581_SENSE0_EN, priv->base + EN7581_TEMPMONCTL0);
drivers/thermal/airoha_thermal.c
321
writel(status, priv->base + EN7581_TEMPMONINTSTS);
drivers/thermal/airoha_thermal.c
362
writel(FIELD_PREP(EN7581_MSRCTL0, EN7581_MSRCTL_6SAMPLE_MAX_MIX_AVG4),
drivers/thermal/airoha_thermal.c
378
writel(priv->scu_adc_res.start + EN7581_DOUT_TADC,
drivers/thermal/airoha_thermal.c
385
writel(FIELD_PREP(EN7581_ADV_RD_VALID_POS, 16),
drivers/thermal/airoha_thermal.c
394
writel(FIELD_PREP(EN7581_ADC_VOLTAGE_SHIFT, 4),
drivers/thermal/airoha_thermal.c
398
writel(FIELD_PREP(EN7581_PERIOD_UNIT, 3),
drivers/thermal/airoha_thermal.c
405
writel(FIELD_PREP(EN7581_FILT_INTERVAL, 1) |
drivers/thermal/airoha_thermal.c
410
writel(FIELD_PREP(EN7581_ADC_POLL_INTVL, 146),
drivers/thermal/airoha_thermal.c
465
writel(EN7581_HOFSINTEN0 | EN7581_LOFSINTEN0,
drivers/thermal/broadcom/bcm2835_thermal.c
236
writel(val, data->regs + BCM2835_TS_TSENSCTL);
drivers/thermal/broadcom/bcm2835_thermal.c
238
writel(val, data->regs + BCM2835_TS_TSENSCTL);
drivers/thermal/broadcom/ns-thermal.c
32
writel(val, pvtmon + PVTMON_CONTROL0);
drivers/thermal/broadcom/sr-thermal.c
84
writel(0, sr_thermal->regs + SR_TMON_TEMP_BASE(i));
drivers/thermal/dove_thermal.c
61
writel(reg, priv->control);
drivers/thermal/dove_thermal.c
65
writel((reg | PMU_TDC0_SW_RST_MASK), priv->control);
drivers/thermal/dove_thermal.c
66
writel(reg, priv->control);
drivers/thermal/dove_thermal.c
71
writel(reg, priv->sensor);
drivers/thermal/hisi_thermal.c
163
writel(DIV_ROUND_UP(value, HI6220_TEMP_STEP) & 0x1F,
drivers/thermal/hisi_thermal.c
169
writel(value, addr + HI6220_TEMP0_INT_CLR);
drivers/thermal/hisi_thermal.c
174
writel(value, addr + HI6220_TEMP0_INT_EN);
drivers/thermal/hisi_thermal.c
179
writel(hi6220_thermal_temp_to_step(temp) | 0x0FFFFFF00,
drivers/thermal/hisi_thermal.c
185
writel(hi6220_thermal_temp_to_step(temp), addr + HI6220_TEMP0_RST_TH);
drivers/thermal/hisi_thermal.c
190
writel(value, addr + HI6220_TEMP0_RST_MSK);
drivers/thermal/hisi_thermal.c
195
writel(value, addr + HI6220_TEMP0_EN);
drivers/thermal/hisi_thermal.c
215
writel(DIV_ROUND_UP(value, HI3660_TEMP_STEP) & 0x7F,
drivers/thermal/hisi_thermal.c
222
writel(value, addr + HI3660_INT_CLR(id));
drivers/thermal/hisi_thermal.c
228
writel(value, addr + HI3660_INT_EN(id));
drivers/thermal/hisi_thermal.c
234
writel(value, addr + HI3660_TH(id));
drivers/thermal/hisi_thermal.c
254
writel((readl(addr + HI6220_TEMP0_CFG) & ~HI6220_TEMP0_CFG_SS_MSK) |
drivers/thermal/hisi_thermal.c
270
writel((readl(addr + HI6220_TEMP0_CFG) & ~HI6220_TEMP0_CFG_HDAK_MSK) |
drivers/thermal/imx8mm_thermal.c
184
writel(FIELD_PREP(TASR_BUF_VREF_MASK,
drivers/thermal/imx8mm_thermal.c
190
writel(FIELD_PREP(TCALIV_RT_MASK, FIELD_GET(ANA0_RT_MASK, ana0)) |
drivers/thermal/imx8mm_thermal.c
229
writel(FIELD_PREP(TCALIV_SNSR25C_MASK, 0x63c),
drivers/thermal/imx8mm_thermal.c
231
writel(FIELD_PREP(TCALIV_SNSR25C_MASK, 0x63c),
drivers/thermal/imx8mm_thermal.c
236
writel(FIELD_PREP(TASR_BUF_VERF_SEL_MASK,
drivers/thermal/imx8mm_thermal.c
242
writel(FIELD_PREP(TRIM_BJT_CUR_MASK,
drivers/thermal/imx8mm_thermal.c
249
writel(FIELD_PREP(TCALIV_SNSR25C_MASK,
drivers/thermal/imx8mm_thermal.c
256
writel(FIELD_PREP(TCALIV_SNSR25C_MASK,
drivers/thermal/imx8mm_thermal.c
262
writel(FIELD_PREP(TCALIV_SNSR25C_MASK,
drivers/thermal/imx91_thermal.c
183
writel(IMX91_TMU_STAT0_THR1_IF, tmu->base + IMX91_TMU_STAT0 + REG_CLR);
drivers/thermal/intel/int340x_thermal/processor_thermal_mbox.c
52
writel(data, (proc_priv->mmio_base + MBOX_OFFSET_DATA));
drivers/thermal/intel/int340x_thermal/processor_thermal_mbox.c
55
writel(reg_data, (proc_priv->mmio_base + MBOX_OFFSET_INTERFACE));
drivers/thermal/intel/int340x_thermal/processor_thermal_mbox.c
73
writel(reg_data, (proc_priv->mmio_base + MBOX_OFFSET_INTERFACE));
drivers/thermal/intel/int340x_thermal/processor_thermal_rfim.c
264
writel(reg_val, (void __iomem *) (proc_priv->mmio_base + mmio_regs[ret].offset));\
drivers/thermal/k3_bandgap.c
212
writel(val, data[id].bgp->base + data[id].ctrl_offset);
drivers/thermal/k3_j72xx_bandgap.c
356
writel(val, bgp->cfg2_base + data->ctrl_offset);
drivers/thermal/k3_j72xx_bandgap.c
369
writel((low_temp << 16) | high_max, bgp->cfg2_base + K3_VTM_MISC_CTRL2_OFFSET);
drivers/thermal/k3_j72xx_bandgap.c
370
writel(K3_VTM_ANYMAXT_OUTRG_ALERT_EN, bgp->cfg2_base + K3_VTM_MISC_CTRL_OFFSET);
drivers/thermal/mediatek/auxadc_thermal.c
1179
writel(tmp, apmixed_base + mt->conf->apmixed_buffer_ctl_reg);
drivers/thermal/mediatek/auxadc_thermal.c
1188
writel(0x800, auxadc_base + AUXADC_CON1_SET_V);
drivers/thermal/mediatek/auxadc_thermal.c
1189
writel(0x1, mt->thermal_base + TEMP_MONCTL0);
drivers/thermal/mediatek/auxadc_thermal.c
1191
writel((tmp & (~0x10e)), mt->thermal_base + TEMP_MSRCTL1);
drivers/thermal/mediatek/auxadc_thermal.c
791
writel(val, mt->thermal_base + PTPCORESEL);
drivers/thermal/mediatek/auxadc_thermal.c
890
writel(TEMP_MONCTL1_PERIOD_UNIT(12), controller_base + TEMP_MONCTL1);
drivers/thermal/mediatek/auxadc_thermal.c
896
writel(TEMP_MONCTL2_FILTER_INTERVAL(1) |
drivers/thermal/mediatek/auxadc_thermal.c
901
writel(TEMP_AHBPOLL_ADC_POLL_INTERVAL(768),
drivers/thermal/mediatek/auxadc_thermal.c
905
writel(0x0, controller_base + TEMP_MSRCTL0);
drivers/thermal/mediatek/auxadc_thermal.c
908
writel(0xffffffff, controller_base + TEMP_AHBTO);
drivers/thermal/mediatek/auxadc_thermal.c
911
writel(0x0, controller_base + TEMP_MONIDET0);
drivers/thermal/mediatek/auxadc_thermal.c
912
writel(0x0, controller_base + TEMP_MONIDET1);
drivers/thermal/mediatek/auxadc_thermal.c
927
writel(BIT(conf->auxadc_channel), controller_base + TEMP_ADCMUX);
drivers/thermal/mediatek/auxadc_thermal.c
930
writel(auxadc_phys_base + AUXADC_CON1_CLR_V,
drivers/thermal/mediatek/auxadc_thermal.c
935
writel(apmixed_phys_base + APMIXED_SYS_TS_CON1,
drivers/thermal/mediatek/auxadc_thermal.c
940
writel(BIT(conf->auxadc_channel), controller_base + TEMP_ADCEN);
drivers/thermal/mediatek/auxadc_thermal.c
943
writel(auxadc_phys_base + AUXADC_CON1_SET_V,
drivers/thermal/mediatek/auxadc_thermal.c
947
writel(auxadc_phys_base + AUXADC_DATA(conf->auxadc_channel),
drivers/thermal/mediatek/auxadc_thermal.c
951
writel(auxadc_phys_base + AUXADC_DATA(conf->auxadc_channel),
drivers/thermal/mediatek/auxadc_thermal.c
955
writel(0x0, controller_base + TEMP_RDCTRL);
drivers/thermal/mediatek/auxadc_thermal.c
958
writel(TEMP_ADCVALIDMASK_VALID_HIGH | TEMP_ADCVALIDMASK_VALID_POS(12),
drivers/thermal/mediatek/auxadc_thermal.c
962
writel(0x0, controller_base + TEMP_ADCVOLTAGESHIFT);
drivers/thermal/mediatek/auxadc_thermal.c
965
writel(TEMP_ADCWRITECTRL_ADC_MUX_WRITE,
drivers/thermal/mediatek/auxadc_thermal.c
969
writel(conf->sensor_mux_values[conf->bank_data[num].sensors[i]],
drivers/thermal/mediatek/auxadc_thermal.c
972
writel((1 << conf->bank_data[num].num_sensors) - 1,
drivers/thermal/mediatek/auxadc_thermal.c
975
writel(TEMP_ADCWRITECTRL_ADC_PNP_WRITE |
drivers/thermal/mediatek/lvts_thermal.c
1025
writel(sensor_map | BIT(9), LVTS_MONCTL0(lvts_ctrl->base));
drivers/thermal/mediatek/lvts_thermal.c
1042
writel(cmds[i], LVTS_CONFIG(lvts_ctrl->base));
drivers/thermal/mediatek/lvts_thermal.c
1082
writel(0, LVTS_MONINT(lvts_ctrl->base));
drivers/thermal/mediatek/lvts_thermal.c
1110
writel(enable, LVTS_CLKEN(lvts_ctrl->base));
drivers/thermal/mediatek/lvts_thermal.c
1164
writel(lvts_ctrl->calibration[i], lvts_edata[i]);
drivers/thermal/mediatek/lvts_thermal.c
1174
writel(lvts_ctrl->lvts_data->msr_offset,
drivers/thermal/mediatek/lvts_thermal.c
1195
writel(value, LVTS_TSSEL(lvts_ctrl->base));
drivers/thermal/mediatek/lvts_thermal.c
1224
writel(value, LVTS_MSRCTL0(lvts_ctrl->base));
drivers/thermal/mediatek/lvts_thermal.c
1267
writel(value, LVTS_MONCTL1(lvts_ctrl->base));
drivers/thermal/mediatek/lvts_thermal.c
1280
writel(value, LVTS_MONCTL2(lvts_ctrl->base));
drivers/thermal/mediatek/lvts_thermal.c
1360
writel(sensor_map, LVTS_MSRCTL1(lvts_ctrl->base));
drivers/thermal/mediatek/lvts_thermal.c
1367
writel(sensor_map | BIT(9), LVTS_MONCTL0(lvts_ctrl->base));
drivers/thermal/mediatek/lvts_thermal.c
423
writel(value, LVTS_MONINT(lvts_ctrl->base));
drivers/thermal/mediatek/lvts_thermal.c
477
writel(raw_low, LVTS_OFFSETL(base));
drivers/thermal/mediatek/lvts_thermal.c
490
writel(raw_high, LVTS_OFFSETH(base));
drivers/thermal/mediatek/lvts_thermal.c
591
writel(value, LVTS_MONINTSTS(lvts_ctrl->base));
drivers/thermal/qcom/lmh.c
58
writel(0xff, lmh_data->base + LMH_REG_DCVS_INTR_CLR);
drivers/thermal/renesas/rzg3e_thermal.c
116
writel(TSU_SICR_ADCLR | TSU_SICR_CMPCLR, priv->base + TSU_SICR);
drivers/thermal/renesas/rzg3e_thermal.c
119
writel(0, priv->base + TSU_SIER);
drivers/thermal/renesas/rzg3e_thermal.c
126
writel(val, priv->base + TSU_SSUSR);
drivers/thermal/renesas/rzg3e_thermal.c
133
writel(val, priv->base + TSU_SOSR1);
drivers/thermal/renesas/rzg3e_thermal.c
158
writel(0, priv->base + TSU_SIER);
drivers/thermal/renesas/rzg3e_thermal.c
161
writel(TSU_SICR_ADCLR | TSU_SICR_CMPCLR, priv->base + TSU_SICR);
drivers/thermal/renesas/rzg3e_thermal.c
164
writel(TSU_SSUSR_ADC_PD_TS, priv->base + TSU_SSUSR);
drivers/thermal/renesas/rzg3e_thermal.c
219
writel(TSU_SICR_ADCLR, priv->base + TSU_SICR);
drivers/thermal/renesas/rzg3e_thermal.c
222
writel(TSU_STRGR_ADST, priv->base + TSU_STRGR);
drivers/thermal/renesas/rzg3e_thermal.c
236
writel(TSU_SICR_ADCLR, priv->base + TSU_SICR);
drivers/thermal/renesas/rzg3e_thermal.c
276
writel(0, priv->base + TSU_SIER);
drivers/thermal/renesas/rzg3e_thermal.c
277
writel(0, priv->base + TSU_CMSR);
drivers/thermal/renesas/rzg3e_thermal.c
280
writel(TSU_SICR_CMPCLR, priv->base + TSU_SICR);
drivers/thermal/renesas/rzg3e_thermal.c
283
writel(low_code, priv->base + TSU_LLSR);
drivers/thermal/renesas/rzg3e_thermal.c
284
writel(high_code, priv->base + TSU_ULSR);
drivers/thermal/renesas/rzg3e_thermal.c
292
writel(val, priv->base + TSU_SOSR1);
drivers/thermal/renesas/rzg3e_thermal.c
295
writel(TSU_CMSR_CMPEN, priv->base + TSU_CMSR);
drivers/thermal/renesas/rzg3e_thermal.c
298
writel(TSU_SIER_CMPIE, priv->base + TSU_SIER);
drivers/thermal/renesas/rzg3e_thermal.c
299
writel(TSU_STRGR_ADST, priv->base + TSU_STRGR);
drivers/thermal/renesas/rzg3e_thermal.c
329
writel(TSU_SICR_CMPCLR, priv->base + TSU_SICR);
drivers/thermal/renesas/rzg3e_thermal.c
330
writel(0, priv->base + TSU_SIER);
drivers/thermal/renesas/rzg3s_thermal.c
113
writel(0, priv->base + TSU_SM);
drivers/thermal/renesas/rzg3s_thermal.c
115
writel(TSU_SM_EN, priv->base + TSU_SM);
drivers/thermal/renesas/rzg3s_thermal.c
122
writel(TSU_SM_OE | TSU_SM_EN, priv->base + TSU_SM);
drivers/thermal/samsung/exynos_tmu.c
348
writel(interrupt_en, data->base + reg_off);
drivers/thermal/samsung/exynos_tmu.c
364
writel(th, data->base + reg_off);
drivers/thermal/samsung/exynos_tmu.c
455
writel(ctrl, data->base + EXYNOS_TMU_TRIMINFO_CON1);
drivers/thermal/samsung/exynos_tmu.c
459
writel(ctrl, data->base + EXYNOS_TMU_TRIMINFO_CON2);
drivers/thermal/samsung/exynos_tmu.c
521
writel(trim_info, data->base + EXYNOS_TMU_REG_TRIMINFO);
drivers/thermal/samsung/exynos_tmu.c
597
writel(con, data->base + EXYNOS_TMU_REG_CONTROL);
drivers/thermal/samsung/exynos_tmu.c
614
writel(pd_det_en, data->base + EXYNOS5433_TMU_PD_DET_EN);
drivers/thermal/samsung/exynos_tmu.c
615
writel(con, data->base + EXYNOS_TMU_REG_CONTROL);
drivers/thermal/samsung/exynos_tmu.c
633
writel(con, data->base + EXYNOS_TMU_REG_CONTROL);
drivers/thermal/samsung/exynos_tmu.c
711
writel(val, data->base + emul_con);
drivers/thermal/samsung/exynos_tmu.c
805
writel(val_irq, data->base + tmu_intclear);
drivers/thermal/sprd_thermal.c
118
writel(tmp, reg);
drivers/thermal/sprd_thermal.c
274
writel(SPRD_THM_INT_CLR_MASK, thm->base + SPRD_THM_INT_CLR);
drivers/thermal/sprd_thermal.c
483
writel(SPRD_THM_INT_CLR_MASK, thm->base + SPRD_THM_INT_CLR);
drivers/thermal/tegra/soctherm.c
1015
writel(st, ts->regs + OC_INTR_STATUS);
drivers/thermal/tegra/soctherm.c
1049
writel(st, ts->regs + OC_INTR_STATUS);
drivers/thermal/tegra/soctherm.c
1079
writel(r, ts->regs + OC_INTR_DISABLE);
drivers/thermal/tegra/soctherm.c
1806
writel(r, ts->regs + THROT_PSKIP_CTRL(throt, THROTTLE_DEV_CPU));
drivers/thermal/tegra/soctherm.c
1810
writel(r, ts->regs + THROT_PSKIP_RAMP(throt, THROTTLE_DEV_CPU));
drivers/thermal/tegra/soctherm.c
1839
writel(r, ts->regs + THROT_PSKIP_CTRL(throt, THROTTLE_DEV_CPU));
drivers/thermal/tegra/soctherm.c
1844
writel(r, ts->regs + THROT_PSKIP_RAMP(throt, THROTTLE_DEV_CPU));
drivers/thermal/tegra/soctherm.c
1867
writel(r, ts->regs + THROT_PSKIP_CTRL(throt, THROTTLE_DEV_GPU));
drivers/thermal/tegra/soctherm.c
1883
writel(r, ts->regs + ALARM_CFG(throt));
drivers/thermal/tegra/soctherm.c
1884
writel(oc->throt_period, ts->regs + ALARM_THROTTLE_PERIOD(throt));
drivers/thermal/tegra/soctherm.c
1885
writel(oc->alarm_cnt_thresh, ts->regs + ALARM_CNT_THRESHOLD(throt));
drivers/thermal/tegra/soctherm.c
1886
writel(oc->alarm_filter, ts->regs + ALARM_FILTER(throt));
drivers/thermal/tegra/soctherm.c
1921
writel(r, ts->regs + THROT_PRIORITY_CTRL(throt));
drivers/thermal/tegra/soctherm.c
1924
writel(r, ts->regs + THROT_DELAY_CTRL(throt));
drivers/thermal/tegra/soctherm.c
1932
writel(r, ts->regs + THROT_PRIORITY_LOCK);
drivers/thermal/tegra/soctherm.c
1960
writel(v, ts->regs + THROT_GLOBAL_CFG);
drivers/thermal/tegra/soctherm.c
1964
writel(v, ts->clk_regs + CAR_SUPER_CCLKG_DIVIDER);
drivers/thermal/tegra/soctherm.c
1970
writel(v, ts->regs + THERMCTL_STATS_CTL);
drivers/thermal/tegra/soctherm.c
2047
writel(pdiv, tegra->regs + SENSOR_PDIV);
drivers/thermal/tegra/soctherm.c
2048
writel(hotspot, tegra->regs + SENSOR_HOTSPOT_OFF);
drivers/thermal/tegra/soctherm.c
377
writel(value, (ts->ccroc_regs + reg));
drivers/thermal/tegra/soctherm.c
399
writel(val, base + SENSOR_CONFIG0);
drivers/thermal/tegra/soctherm.c
405
writel(val, base + SENSOR_CONFIG1);
drivers/thermal/tegra/soctherm.c
407
writel(tegra->calib[i], base + SENSOR_CONFIG2);
drivers/thermal/tegra/soctherm.c
498
writel(r, ts->regs + THERMCTL_THERMTRIP_CTL);
drivers/thermal/tegra/soctherm.c
557
writel(r, ts->regs + reg_off);
drivers/thermal/tegra/soctherm.c
645
writel(r, zn->ts->regs + THERMCTL_INTR_ENABLE);
drivers/thermal/tegra/soctherm.c
657
writel(r, zn->ts->regs + THERMCTL_INTR_DISABLE);
drivers/thermal/tegra/soctherm.c
670
writel(r, zone->ts->regs + zone->sg->thermctl_lvl0_offset);
drivers/thermal/tegra/soctherm.c
679
writel(r, zone->ts->regs + zone->sg->thermctl_lvl0_offset);
drivers/thermal/tegra/soctherm.c
815
writel(r, ts->regs + THERMCTL_INTR_DISABLE);
drivers/thermal/tegra/soctherm.c
860
writel(ex, ts->regs + THERMCTL_INTR_STATUS);
drivers/thermal/tegra/soctherm.c
895
writel(st, ts->regs + THERMCTL_INTR_STATUS);
drivers/thermal/tegra/soctherm.c
938
writel(r, ts->regs + OC_INTR_ENABLE);
drivers/thermal/ti-soc-thermal/ti-bandgap.c
69
writel(val, bgp->base + reg);
drivers/tty/nozomi.c
441
writel(__cpu_to_le32(*buf), ptr);
drivers/tty/nozomi.c
453
writel(__cpu_to_le32(*buf), ptr);
drivers/tty/serial/8250/8250_bcm7271.c
256
writel(value, priv->regs[reg_type] + offset);
drivers/tty/serial/8250/8250_bcm7271.c
267
writel(value, reg);
drivers/tty/serial/8250/8250_bcm7271.c
278
writel(value, reg);
drivers/tty/serial/8250/8250_ce4100.c
59
writel(value, p->membase + offset);
drivers/tty/serial/8250/8250_dw.c
370
writel(value, p->membase + (offset << p->regshift));
drivers/tty/serial/8250/8250_dwlib.h
39
writel(reg, p->membase + offset);
drivers/tty/serial/8250/8250_early.c
70
writel(value, port->membase + offset);
drivers/tty/serial/8250/8250_em.c
46
writel(value, p->membase + ((offset + 1) << 2));
drivers/tty/serial/8250/8250_em.c
49
writel(value, p->membase + (UART_FCR_EM_HW << 2));
drivers/tty/serial/8250/8250_em.c
57
writel(value, p->membase + (offset << 2));
drivers/tty/serial/8250/8250_ingenic.c
51
writel(value, port->membase + (offset << 2));
drivers/tty/serial/8250/8250_lpc18xx.c
81
writel(value, p->membase + offset);
drivers/tty/serial/8250/8250_lpss.c
101
writel(reg, p->membase + BYT_PRV_CLK);
drivers/tty/serial/8250/8250_lpss.c
151
writel(BYT_TX_OVF_INT_MASK, port->membase + BYT_TX_OVF_INT);
drivers/tty/serial/8250/8250_lpss.c
99
writel(reg, p->membase + BYT_PRV_CLK);
drivers/tty/serial/8250/8250_mid.c
235
writel(ps, p->membase + INTEL_MID_UART_PS); /* set PS */
drivers/tty/serial/8250/8250_mid.c
236
writel(mul, p->membase + INTEL_MID_UART_MUL); /* set MUL */
drivers/tty/serial/8250/8250_mid.c
237
writel(div, p->membase + INTEL_MID_UART_DIV);
drivers/tty/serial/8250/8250_mtk.c
573
writel(0x0, uart.port.membase +
drivers/tty/serial/8250/8250_omap.c
1726
writel(val, priv->membase + (reg << OMAP_UART_REGSHIFT));
drivers/tty/serial/8250/8250_pci.c
357
writel(irq_config, p + 0x4c);
drivers/tty/serial/8250/8250_pci.c
380
writel(0, p + 0x4c);
drivers/tty/serial/8250/8250_pci.c
408
writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
drivers/tty/serial/8250/8250_pci.c
437
writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
drivers/tty/serial/8250/8250_pci.c
766
writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
drivers/tty/serial/8250/8250_pci.c
804
writel(device_window, p + MITE_IOWBSR1);
drivers/tty/serial/8250/8250_pci.c
807
writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
drivers/tty/serial/8250/8250_pci.c
811
writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
drivers/tty/serial/8250/8250_pci.c
814
writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
drivers/tty/serial/8250/8250_pci1xxxx.c
167
writel(UART_SYSLOCK, port->membase + UART_SYSLOCK_REG);
drivers/tty/serial/8250/8250_pci1xxxx.c
183
writel(0x0, port->membase + UART_SYSLOCK_REG);
drivers/tty/serial/8250/8250_pci1xxxx.c
262
writel(UART_BIT_DIVISOR_8, port->membase + FRAC_DIV_CFG_REG);
drivers/tty/serial/8250/8250_pci1xxxx.c
264
writel(UART_BIT_DIVISOR_16, port->membase + FRAC_DIV_CFG_REG);
drivers/tty/serial/8250/8250_pci1xxxx.c
266
writel(FIELD_PREP(BAUD_CLOCK_DIV_INT_MSK, quot) | frac,
drivers/tty/serial/8250/8250_pci1xxxx.c
293
writel((fract_div_cfg_reg &
drivers/tty/serial/8250/8250_pci1xxxx.c
298
writel((adcl_cfg_reg | (ADCL_CFG_EN |
drivers/tty/serial/8250/8250_pci1xxxx.c
303
writel(adcl_cfg_reg, port->membase + ADCL_CFG_REG);
drivers/tty/serial/8250/8250_pci1xxxx.c
305
writel(fract_div_cfg_reg, port->membase +
drivers/tty/serial/8250/8250_pci1xxxx.c
357
writel(mode_cfg, port->membase + ADCL_CFG_REG);
drivers/tty/serial/8250/8250_pci1xxxx.c
461
writel(c, port->membase + UART_TX_BURST_FIFO);
drivers/tty/serial/8250/8250_pci1xxxx.c
628
writel(data | UART_RESET_D3_RESET_DISABLE, p + UART_RESET_REG);
drivers/tty/serial/8250/8250_pci1xxxx.c
659
writel(data & ~UART_RESET_D3_RESET_DISABLE, p + UART_RESET_REG);
drivers/tty/serial/8250/8250_port.c
376
writel(value, p->membase + offset);
drivers/tty/serial/8250/8250_uniphier.c
123
writel(value, p->membase + offset);
drivers/tty/serial/8250/8250_uniphier.c
138
writel(tmp, p->membase + offset);
drivers/tty/serial/8250/8250_uniphier.c
155
writel(value, up->port.membase + UNIPHIER_UART_DLR);
drivers/tty/serial/altera_jtaguart.c
136
writel(ch, port->membase + ALTERA_JTAGUART_DATA_REG),
drivers/tty/serial/altera_jtaguart.c
165
writel(0, port->membase + ALTERA_JTAGUART_CONTROL_REG);
drivers/tty/serial/altera_jtaguart.c
185
writel(port->read_status_mask,
drivers/tty/serial/altera_jtaguart.c
201
writel(port->read_status_mask,
drivers/tty/serial/altera_jtaguart.c
276
writel(c, port->membase + ALTERA_JTAGUART_DATA_REG);
drivers/tty/serial/altera_jtaguart.c
290
writel(c, port->membase + ALTERA_JTAGUART_DATA_REG);
drivers/tty/serial/altera_jtaguart.c
78
writel(port->read_status_mask,
drivers/tty/serial/altera_jtaguart.c
85
writel(port->read_status_mask,
drivers/tty/serial/altera_jtaguart.c
92
writel(port->read_status_mask,
drivers/tty/serial/altera_uart.c
90
writel(dat, port->membase + (reg << port->regshift));
drivers/tty/serial/amba-pl010.c
110
writel(cr, uap->port.membase + UART010_CR);
drivers/tty/serial/amba-pl010.c
131
writel(0, port->membase + UART01x_ECR);
drivers/tty/serial/amba-pl010.c
172
writel(ch, port->membase + UART01x_DR),
drivers/tty/serial/amba-pl010.c
181
writel(0, port->membase + UART010_ICR);
drivers/tty/serial/amba-pl010.c
279
writel(lcr_h, port->membase + UART010_LCRH);
drivers/tty/serial/amba-pl010.c
313
writel(UART01x_CR_UARTEN | UART010_CR_RIE | UART010_CR_RTIE,
drivers/tty/serial/amba-pl010.c
337
writel(0, port->membase + UART010_CR);
drivers/tty/serial/amba-pl010.c
340
writel(readb(port->membase + UART010_LCRH) &
drivers/tty/serial/amba-pl010.c
430
writel((quot & 0xf00) >> 8, port->membase + UART010_LCRM);
drivers/tty/serial/amba-pl010.c
431
writel(quot & 0xff, port->membase + UART010_LCRL);
drivers/tty/serial/amba-pl010.c
438
writel(lcr_h, port->membase + UART010_LCRH);
drivers/tty/serial/amba-pl010.c
439
writel(old_cr, port->membase + UART010_CR);
drivers/tty/serial/amba-pl010.c
541
writel(ch, port->membase + UART01x_DR);
drivers/tty/serial/amba-pl010.c
557
writel(UART01x_CR_UARTEN, port->membase + UART010_CR);
drivers/tty/serial/amba-pl010.c
569
writel(old_cr, port->membase + UART010_CR);
drivers/tty/serial/amba-pl010.c
67
writel(cr, uap->port.membase + UART010_CR);
drivers/tty/serial/amba-pl010.c
78
writel(cr, uap->port.membase + UART010_CR);
drivers/tty/serial/amba-pl010.c
89
writel(cr, uap->port.membase + UART010_CR);
drivers/tty/serial/amba-pl010.c
99
writel(cr, uap->port.membase + UART010_CR);
drivers/tty/serial/amba-pl011.c
2627
writel(c, port->membase + UART01x_DR);
drivers/tty/serial/amba-pl011.c
2644
writel(c, port->membase + UART01x_DR);
drivers/tty/serial/ar933x_uart.c
66
writel(value, up->port.membase + offset);
drivers/tty/serial/clps711x.c
217
writel(ubrlcr, port->membase + UBRLCR_OFFSET);
drivers/tty/serial/clps711x.c
236
writel(readl(port->membase + UBRLCR_OFFSET) & ~UBRLCR_BREAK,
drivers/tty/serial/clps711x.c
309
writel(ubrlcr | (quot - 1), port->membase + UBRLCR_OFFSET);
drivers/tty/serial/esp32_acm.c
50
writel(v, port->membase + reg);
drivers/tty/serial/esp32_uart.c
146
writel(v, port->membase + reg);
drivers/tty/serial/fsl_linflexuart.c
149
writel(ier, port->membase + LINIER);
drivers/tty/serial/fsl_linflexuart.c
157
writel(ier & ~LINFLEXD_LINIER_DRIE, port->membase + LINIER);
drivers/tty/serial/fsl_linflexuart.c
172
writel(status | LINFLEXD_UARTSR_DTFTFF, sport->membase + UARTSR);
drivers/tty/serial/fsl_linflexuart.c
198
writel(ier | LINFLEXD_LINIER_DTIE, port->membase + LINIER);
drivers/tty/serial/fsl_linflexuart.c
258
writel(status, sport->membase + UARTSR);
drivers/tty/serial/fsl_linflexuart.c
322
writel(ier, sport->membase + LINIER);
drivers/tty/serial/fsl_linflexuart.c
326
writel(cr, sport->membase + UARTCR);
drivers/tty/serial/fsl_linflexuart.c
333
writel(cr1, sport->membase + LINCR1);
drivers/tty/serial/fsl_linflexuart.c
350
writel(LINFLEXD_UARTCR_UART, sport->membase + UARTCR);
drivers/tty/serial/fsl_linflexuart.c
355
writel(cr, sport->membase + UARTCR);
drivers/tty/serial/fsl_linflexuart.c
359
writel(cr1, sport->membase + LINCR1);
drivers/tty/serial/fsl_linflexuart.c
365
writel(ier, sport->membase + LINIER);
drivers/tty/serial/fsl_linflexuart.c
395
writel(ier, port->membase + LINIER);
drivers/tty/serial/fsl_linflexuart.c
416
writel(cr1, port->membase + LINCR1);
drivers/tty/serial/fsl_linflexuart.c
505
writel(cr, port->membase + UARTCR);
drivers/tty/serial/fsl_linflexuart.c
509
writel(cr1, port->membase + LINCR1);
drivers/tty/serial/fsl_linflexuart.c
575
writel((readl(port->membase + UARTSR) |
drivers/tty/serial/fsl_linflexuart.c
633
writel(cr, sport->membase + UARTCR);
drivers/tty/serial/fsl_linflexuart.c
637
writel(ier, sport->membase + LINIER);
drivers/tty/serial/fsl_lpuart.c
2847
writel(UART_GLOBAL_RST, global_addr);
drivers/tty/serial/fsl_lpuart.c
2849
writel(0, global_addr);
drivers/tty/serial/fsl_lpuart.c
401
writel(val, port->membase + off);
drivers/tty/serial/icom.c
1130
writel(adapter_interrupts, int_reg);
drivers/tty/serial/icom.c
1157
writel(adapter_interrupts, int_reg);
drivers/tty/serial/icom.c
1497
writel(icom_port->statStg_pci + offset,
drivers/tty/serial/icom.c
1501
writel(icom_port->xmitRestart_pci,
drivers/tty/serial/icom.c
559
writel(temp, stop_proc[port].global_control_reg);
drivers/tty/serial/icom.c
590
writel(temp, start_proc[port].global_control_reg);
drivers/tty/serial/icom.c
705
writel(temp_pci, &icom_port->dram->mac_load_addr);
drivers/tty/serial/icom.c
825
writel(temp & ~int_mask_tbl[port].processor_id, int_mask_tbl[port].global_int_mask);
drivers/tty/serial/icom.c
860
writel(temp | int_mask_tbl[port].processor_id, int_mask_tbl[port].global_int_mask);
drivers/tty/serial/imx.c
278
writel(val, sport->port.membase + offset);
drivers/tty/serial/lpc32xx_hs.c
128
writel((u32)ch, LPC32XX_HSUART_FIFO(port->membase));
drivers/tty/serial/lpc32xx_hs.c
258
writel(LPC32XX_HSU_FE_INT,
drivers/tty/serial/lpc32xx_hs.c
287
writel(ch, LPC32XX_HSUART_FIFO(port->membase)));
drivers/tty/serial/lpc32xx_hs.c
303
writel(LPC32XX_HSU_BRK_INT, LPC32XX_HSUART_IIR(port->membase));
drivers/tty/serial/lpc32xx_hs.c
310
writel(LPC32XX_HSU_FE_INT, LPC32XX_HSUART_IIR(port->membase));
drivers/tty/serial/lpc32xx_hs.c
314
writel(LPC32XX_HSU_RX_OE_INT,
drivers/tty/serial/lpc32xx_hs.c
327
writel(LPC32XX_HSU_TX_INT, LPC32XX_HSUART_IIR(port->membase));
drivers/tty/serial/lpc32xx_hs.c
368
writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
drivers/tty/serial/lpc32xx_hs.c
379
writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
drivers/tty/serial/lpc32xx_hs.c
389
writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
drivers/tty/serial/lpc32xx_hs.c
391
writel((LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT |
drivers/tty/serial/lpc32xx_hs.c
408
writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
drivers/tty/serial/lpc32xx_hs.c
423
writel((LPC32XX_HSU_TX_INT | LPC32XX_HSU_FE_INT |
drivers/tty/serial/lpc32xx_hs.c
427
writel(0xFF, LPC32XX_HSUART_RATE(port->membase));
drivers/tty/serial/lpc32xx_hs.c
435
writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
drivers/tty/serial/lpc32xx_hs.c
444
writel((tmp | LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN),
drivers/tty/serial/lpc32xx_hs.c
460
writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
drivers/tty/serial/lpc32xx_hs.c
497
writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
drivers/tty/serial/lpc32xx_hs.c
499
writel(quot, LPC32XX_HSUART_RATE(port->membase));
drivers/tty/serial/lpc32xx_hs.c
560
writel((LPC32XX_HSU_TX_INT | LPC32XX_HSU_FE_INT |
drivers/tty/serial/lpc32xx_hs.c
564
writel(0xFF, LPC32XX_HSUART_RATE(port->membase));
drivers/tty/serial/lpc32xx_hs.c
568
writel(LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B |
drivers/tty/serial/meson_uart.c
113
writel(val, port->membase + AML_UART_CONTROL);
drivers/tty/serial/meson_uart.c
122
writel(val, port->membase + AML_UART_CONTROL);
drivers/tty/serial/meson_uart.c
137
writel(val, port->membase + AML_UART_CONTROL);
drivers/tty/serial/meson_uart.c
155
writel(port->x_char, port->membase + AML_UART_WFIFO);
drivers/tty/serial/meson_uart.c
164
writel(ch, port->membase + AML_UART_WFIFO);
drivers/tty/serial/meson_uart.c
170
writel(val, port->membase + AML_UART_CONTROL);
drivers/tty/serial/meson_uart.c
198
writel(mode, port->membase + AML_UART_CONTROL);
drivers/tty/serial/meson_uart.c
202
writel(mode, port->membase + AML_UART_CONTROL);
drivers/tty/serial/meson_uart.c
273
writel(val, port->membase + AML_UART_CONTROL);
drivers/tty/serial/meson_uart.c
276
writel(val, port->membase + AML_UART_CONTROL);
drivers/tty/serial/meson_uart.c
289
writel(val, port->membase + AML_UART_CONTROL);
drivers/tty/serial/meson_uart.c
291
writel(val, port->membase + AML_UART_CONTROL);
drivers/tty/serial/meson_uart.c
294
writel(val, port->membase + AML_UART_CONTROL);
drivers/tty/serial/meson_uart.c
297
writel(val, port->membase + AML_UART_CONTROL);
drivers/tty/serial/meson_uart.c
300
writel(val, port->membase + AML_UART_MISC);
drivers/tty/serial/meson_uart.c
331
writel(val, port->membase + AML_UART_REG5);
drivers/tty/serial/meson_uart.c
390
writel(val, port->membase + AML_UART_CONTROL);
drivers/tty/serial/meson_uart.c
496
writel(c, port->membase + AML_UART_WFIFO);
drivers/tty/serial/meson_uart.c
540
writel(val, port->membase + AML_UART_CONTROL);
drivers/tty/serial/meson_uart.c
550
writel(ch, port->membase + AML_UART_WFIFO);
drivers/tty/serial/meson_uart.c
567
writel(tmp, port->membase + AML_UART_CONTROL);
drivers/tty/serial/meson_uart.c
570
writel(val, port->membase + AML_UART_CONTROL);
drivers/tty/serial/mvebu-uart.c
1145
writel(val, uart_clock_base->reg1);
drivers/tty/serial/mvebu-uart.c
1158
writel(val, uart_clock_base->reg2);
drivers/tty/serial/mvebu-uart.c
1185
writel(val, uart_clock_base->reg1);
drivers/tty/serial/mvebu-uart.c
1209
writel(val, uart_clock_base->reg1);
drivers/tty/serial/mvebu-uart.c
1252
writel(uart_clock->pm_context_reg1, uart_clock_base->reg1);
drivers/tty/serial/mvebu-uart.c
1253
writel(uart_clock->pm_context_reg2, uart_clock_base->reg2);
drivers/tty/serial/mvebu-uart.c
216
writel(ctl, port->membase + UART_INTR(port));
drivers/tty/serial/mvebu-uart.c
225
writel(c, port->membase + UART_TSH(port));
drivers/tty/serial/mvebu-uart.c
229
writel(ctl, port->membase + UART_INTR(port));
drivers/tty/serial/mvebu-uart.c
238
writel(ctl, port->membase + UART_CTRL(port));
drivers/tty/serial/mvebu-uart.c
242
writel(ctl, port->membase + UART_INTR(port));
drivers/tty/serial/mvebu-uart.c
256
writel(ctl, port->membase + UART_CTRL(port));
drivers/tty/serial/mvebu-uart.c
285
writel(ret, port->membase + UART_STAT);
drivers/tty/serial/mvebu-uart.c
339
writel(ch, port->membase + UART_TSH(port)),
drivers/tty/serial/mvebu-uart.c
387
writel(CTRL_TXFIFO_RST | CTRL_RXFIFO_RST,
drivers/tty/serial/mvebu-uart.c
394
writel(ret, port->membase + UART_STAT);
drivers/tty/serial/mvebu-uart.c
396
writel(CTRL_BRK_INT, port->membase + UART_CTRL(port));
drivers/tty/serial/mvebu-uart.c
400
writel(ctl, port->membase + UART_INTR(port));
drivers/tty/serial/mvebu-uart.c
443
writel(0, port->membase + UART_INTR(port));
drivers/tty/serial/mvebu-uart.c
521
writel(brdv, port->membase + UART_BRDV);
drivers/tty/serial/mvebu-uart.c
529
writel(osamp, port->membase + UART_OSAMP);
drivers/tty/serial/mvebu-uart.c
632
writel(c, port->membase + UART_TSH(port));
drivers/tty/serial/mvebu-uart.c
671
writel(c, port->membase + UART_STD_TSH);
drivers/tty/serial/mvebu-uart.c
724
writel(ch, port->membase + UART_TSH(port));
drivers/tty/serial/mvebu-uart.c
743
writel(0, port->membase + UART_CTRL(port));
drivers/tty/serial/mvebu-uart.c
744
writel(0, port->membase + UART_INTR(port));
drivers/tty/serial/mvebu-uart.c
751
writel(ier, port->membase + UART_CTRL(port));
drivers/tty/serial/mvebu-uart.c
755
writel(ctl, port->membase + UART_INTR(port));
drivers/tty/serial/mvebu-uart.c
849
writel(mvuart->pm_regs.rbr, port->membase + UART_RBR(port));
drivers/tty/serial/mvebu-uart.c
850
writel(mvuart->pm_regs.tsh, port->membase + UART_TSH(port));
drivers/tty/serial/mvebu-uart.c
851
writel(mvuart->pm_regs.ctrl, port->membase + UART_CTRL(port));
drivers/tty/serial/mvebu-uart.c
852
writel(mvuart->pm_regs.intr, port->membase + UART_INTR(port));
drivers/tty/serial/mvebu-uart.c
853
writel(mvuart->pm_regs.stat, port->membase + UART_STAT);
drivers/tty/serial/mvebu-uart.c
855
writel(mvuart->pm_regs.brdv, port->membase + UART_BRDV);
drivers/tty/serial/mvebu-uart.c
857
writel(mvuart->pm_regs.osamp, port->membase + UART_OSAMP);
drivers/tty/serial/mvebu-uart.c
979
writel(CTRL_SOFT_RST, port->membase + UART_CTRL(port));
drivers/tty/serial/mvebu-uart.c
981
writel(0, port->membase + UART_CTRL(port));
drivers/tty/serial/owl-uart.c
86
writel(val, port->membase + off);
drivers/tty/serial/pxa.c
61
writel(value, up->port.membase + offset);
drivers/tty/serial/qcom_geni_serial.c
1002
writel(irq_en | M_TX_FIFO_WATERMARK_EN,
drivers/tty/serial/qcom_geni_serial.c
1014
writel(M_TX_FIFO_WATERMARK_EN,
drivers/tty/serial/qcom_geni_serial.c
1021
writel(irq_en & ~M_TX_FIFO_WATERMARK_EN,
drivers/tty/serial/qcom_geni_serial.c
1072
writel(m_irq_status, uport->membase + SE_GENI_M_IRQ_CLEAR);
drivers/tty/serial/qcom_geni_serial.c
1073
writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR);
drivers/tty/serial/qcom_geni_serial.c
1074
writel(dma_tx_status, uport->membase + SE_DMA_TX_IRQ_CLR);
drivers/tty/serial/qcom_geni_serial.c
1075
writel(dma_rx_status, uport->membase + SE_DMA_RX_IRQ_CLR);
drivers/tty/serial/qcom_geni_serial.c
1204
writel(rxstale, uport->membase + SE_UART_RX_STALE_CNT);
drivers/tty/serial/qcom_geni_serial.c
1217
writel(pin_swap, uport->membase + SE_UART_IO_MACRO_CTRL);
drivers/tty/serial/qcom_geni_serial.c
1303
writel(ser_clk_cfg, uport->membase + GENI_SER_M_CLK_CFG);
drivers/tty/serial/qcom_geni_serial.c
1304
writel(ser_clk_cfg, uport->membase + GENI_SER_S_CLK_CFG);
drivers/tty/serial/qcom_geni_serial.c
1306
writel(clk_idx & CLK_SEL_MSK, uport->membase + SE_GENI_CLK_SEL);
drivers/tty/serial/qcom_geni_serial.c
1426
writel(port->loopback,
drivers/tty/serial/qcom_geni_serial.c
1428
writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG);
drivers/tty/serial/qcom_geni_serial.c
1429
writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG);
drivers/tty/serial/qcom_geni_serial.c
1430
writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG);
drivers/tty/serial/qcom_geni_serial.c
1431
writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG);
drivers/tty/serial/qcom_geni_serial.c
1432
writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN);
drivers/tty/serial/qcom_geni_serial.c
1433
writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN);
drivers/tty/serial/qcom_geni_serial.c
1434
writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN);
drivers/tty/serial/qcom_geni_serial.c
1553
writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG);
drivers/tty/serial/qcom_geni_serial.c
1554
writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG);
drivers/tty/serial/qcom_geni_serial.c
1555
writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG);
drivers/tty/serial/qcom_geni_serial.c
1556
writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG);
drivers/tty/serial/qcom_geni_serial.c
1557
writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN);
drivers/tty/serial/qcom_geni_serial.c
1558
writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN);
drivers/tty/serial/qcom_geni_serial.c
1559
writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN);
drivers/tty/serial/qcom_geni_serial.c
202
writel(rfr, uport->membase + SE_UART_MANUAL_RFR);
drivers/tty/serial/qcom_geni_serial.c
255
writel(uart_manual_rfr, uport->membase + SE_UART_MANUAL_RFR);
drivers/tty/serial/qcom_geni_serial.c
347
writel(xmit_size, uport->membase + SE_UART_TX_TRANS_LEN);
drivers/tty/serial/qcom_geni_serial.c
349
writel(m_cmd, uport->membase + SE_GENI_M_CMD0);
drivers/tty/serial/qcom_geni_serial.c
359
writel(M_GENI_CMD_ABORT, uport->membase +
drivers/tty/serial/qcom_geni_serial.c
363
writel(M_CMD_ABORT_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
drivers/tty/serial/qcom_geni_serial.c
371
writel(S_GENI_CMD_ABORT, uport->membase + SE_GENI_S_CMD_CTRL_REG);
drivers/tty/serial/qcom_geni_serial.c
374
writel(irq_clear, uport->membase + SE_GENI_S_IRQ_CLEAR);
drivers/tty/serial/qcom_geni_serial.c
375
writel(FORCE_DEFAULT, uport->membase + GENI_FORCE_DEFAULT_REG);
drivers/tty/serial/qcom_geni_serial.c
388
writel(status, uport->membase + SE_GENI_M_IRQ_CLEAR);
drivers/tty/serial/qcom_geni_serial.c
391
writel(status, uport->membase + SE_GENI_S_IRQ_CLEAR);
drivers/tty/serial/qcom_geni_serial.c
429
writel(M_CMD_DONE_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
drivers/tty/serial/qcom_geni_serial.c
431
writel(c, uport->membase + SE_GENI_TX_FIFOn);
drivers/tty/serial/qcom_geni_serial.c
471
writel(private_data->write_cached_bytes,
drivers/tty/serial/qcom_geni_serial.c
495
writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
drivers/tty/serial/qcom_geni_serial.c
496
writel(M_CMD_DONE_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
drivers/tty/serial/qcom_geni_serial.c
514
writel(M_TX_FIFO_WATERMARK_EN, uport->membase +
drivers/tty/serial/qcom_geni_serial.c
522
writel(private_data->write_cached_bytes,
drivers/tty/serial/qcom_geni_serial.c
553
writel(0, uport->membase + SE_GENI_M_IRQ_EN);
drivers/tty/serial/qcom_geni_serial.c
554
writel(0, uport->membase + SE_GENI_S_IRQ_EN);
drivers/tty/serial/qcom_geni_serial.c
568
writel(m_irq_en, uport->membase + SE_GENI_M_IRQ_EN);
drivers/tty/serial/qcom_geni_serial.c
569
writel(s_irq_en, uport->membase + SE_GENI_S_IRQ_EN);
drivers/tty/serial/qcom_geni_serial.c
663
writel(M_CMD_ABORT_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
drivers/tty/serial/qcom_geni_serial.c
666
writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
drivers/tty/serial/qcom_geni_serial.c
714
writel(M_CMD_DONE_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
drivers/tty/serial/qcom_geni_serial.c
716
writel(c, uport->membase + SE_GENI_TX_FIFOn);
drivers/tty/serial/qcom_geni_serial.c
722
writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
drivers/tty/serial/qcom_geni_serial.c
723
writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
drivers/tty/serial/qcom_geni_serial.c
732
writel(0, uport->membase + SE_GENI_TX_WATERMARK_REG);
drivers/tty/serial/qcom_geni_serial.c
733
writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
drivers/tty/serial/qcom_geni_serial.c
746
writel(M_CMD_ABORT_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
drivers/tty/serial/qcom_geni_serial.c
748
writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
drivers/tty/serial/qcom_geni_serial.c
796
writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN);
drivers/tty/serial/qcom_geni_serial.c
800
writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
drivers/tty/serial/qcom_geni_serial.c
816
writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR);
drivers/tty/serial/qcom_geni_serial.c
834
writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN);
drivers/tty/serial/qcom_geni_serial.c
838
writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
drivers/tty/serial/qcom_geni_serial.c
853
writel(RX_EOT | RX_DMA_DONE,
drivers/tty/serial/qcom_geni_serial.c
858
writel(1, uport->membase + SE_DMA_RX_FSM_RST);
drivers/tty/serial/qcom_geni_serial.c
861
writel(RX_RESET_DONE | RX_DMA_DONE,
drivers/tty/serial/rda-uart.c
128
writel(val, port->membase + off);
drivers/tty/serial/rp2.c
238
writel(tmp, up->base + reg);
drivers/tty/serial/rp2.c
263
writel(irq_mask, up->asic_base + RP2_CH_IRQ_MASK);
drivers/tty/serial/rp2.c
449
writel(status, up->base + RP2_CHAN_STAT);
drivers/tty/serial/rp2.c
582
writel(0, base + RP2_CLK_PRESCALER);
drivers/tty/serial/rp2.c
590
writel(ALL_PORTS_MASK, base + RP2_CH_IRQ_MASK);
drivers/tty/serial/rp2.c
591
writel(RP2_ASIC_IRQ_EN_m, base + RP2_ASIC_IRQ);
drivers/tty/serial/rp2.c
596
writel(4, card->bar0 + RP2_FPGA_CTL0);
drivers/tty/serial/rp2.c
597
writel(0, card->bar0 + RP2_FPGA_CTL1);
drivers/tty/serial/rp2.c
603
writel(RP2_IRQ_MASK_EN_m, card->bar0 + RP2_IRQ_MASK);
drivers/tty/serial/rp2.c
610
writel(RP2_UART_CTL_RESET_CH_m, up->base + RP2_UART_CTL);
drivers/tty/serial/rp2.c
614
writel(0, up->base + RP2_TXRX_CTL);
drivers/tty/serial/rp2.c
615
writel(0, up->base + RP2_UART_CTL);
drivers/tty/serial/rsci.c
159
writel(value, p->membase + offset);
drivers/tty/serial/samsung_tty.c
2716
writel(val, portaddr(port, reg));
drivers/tty/serial/serial-tegra.c
165
writel(val, tup->uport.membase + (reg << tup->uport.regshift));
drivers/tty/serial/st-asc.c
165
writel(value, port->membase + offset);
drivers/tty/serial/sunplus-uart.c
128
writel(mcr, port->membase + SUP_UART_MCR);
drivers/tty/serial/sunplus-uart.c
161
writel(isc, port->membase + SUP_UART_ISC);
drivers/tty/serial/sunplus-uart.c
170
writel(isc, port->membase + SUP_UART_ISC);
drivers/tty/serial/sunplus-uart.c
179
writel(isc, port->membase + SUP_UART_ISC);
drivers/tty/serial/sunplus-uart.c
196
writel(lcr, port->membase + SUP_UART_LCR);
drivers/tty/serial/sunplus-uart.c
313
writel(isc, port->membase + SUP_UART_ISC);
drivers/tty/serial/sunplus-uart.c
328
writel(0, port->membase + SUP_UART_ISC); /* disable all interrupt */
drivers/tty/serial/sunplus-uart.c
404
writel(0, port->membase + SUP_UART_RX_RESIDUE);
drivers/tty/serial/sunplus-uart.c
408
writel(div_h, port->membase + SUP_UART_DIV_H);
drivers/tty/serial/sunplus-uart.c
409
writel(div_l, port->membase + SUP_UART_DIV_L);
drivers/tty/serial/sunplus-uart.c
410
writel(lcr, port->membase + SUP_UART_LCR);
drivers/tty/serial/sunplus-uart.c
742
writel(c, port->membase + SUP_UART_DATA);
drivers/tty/serial/sunplus-uart.c
82
writel(ch, port->membase + SUP_UART_DATA);
drivers/tty/serial/tegra-utc.c
361
writel(c, port->membase + TEGRA_UTC_DATA);
drivers/tty/serial/tegra-utc.c
388
writel(TEGRA_UTC_COMMAND_FLUSH | TEGRA_UTC_COMMAND_RESET,
drivers/tty/serial/tegra-utc.c
390
writel(TEGRA_UTC_DEFAULT_FIFO_THRESHOLD, device->port.membase + TEGRA_UTC_FIFO_THRESHOLD);
drivers/tty/serial/tegra-utc.c
393
writel(TEGRA_UTC_INTR_COMMON, device->port.membase + TEGRA_UTC_INTR_CLEAR);
drivers/tty/serial/tegra-utc.c
395
writel(0x0, device->port.membase + TEGRA_UTC_INTR_MASK);
drivers/tty/serial/tegra-utc.c
396
writel(0x0, device->port.membase + TEGRA_UTC_INTR_SET);
drivers/tty/serial/tegra-utc.c
399
writel(TEGRA_UTC_ENABLE_CLIENT_ENABLE, device->port.membase + TEGRA_UTC_ENABLE);
drivers/tty/serial/uartlite.c
584
writel(c & 0xff, port->membase + ULITE_TX);
drivers/tty/serial/vt8500_serial.c
114
writel(val, port->membase + off);
drivers/tty/serial/xilinx_uartps.c
1000
writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
drivers/tty/serial/xilinx_uartps.c
1003
writel(readl(port->membase + CDNS_UART_ISR),
drivers/tty/serial/xilinx_uartps.c
1017
writel(CDNS_UART_RX_IRQS | CDNS_UART_IXR_BRK,
drivers/tty/serial/xilinx_uartps.c
1020
writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IER);
drivers/tty/serial/xilinx_uartps.c
1042
writel(status, port->membase + CDNS_UART_IDR);
drivers/tty/serial/xilinx_uartps.c
1043
writel(0xffffffff, port->membase + CDNS_UART_ISR);
drivers/tty/serial/xilinx_uartps.c
1046
writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
drivers/tty/serial/xilinx_uartps.c
1191
writel(val, port->membase + CDNS_UART_MODEMCR);
drivers/tty/serial/xilinx_uartps.c
1192
writel(mode_reg, port->membase + CDNS_UART_MR);
drivers/tty/serial/xilinx_uartps.c
1225
writel(c, port->membase + CDNS_UART_FIFO);
drivers/tty/serial/xilinx_uartps.c
1311
writel(ch, port->membase + CDNS_UART_FIFO);
drivers/tty/serial/xilinx_uartps.c
1331
writel(CDNS_UART_CR_TX_EN|CDNS_UART_CR_TXRST|CDNS_UART_CR_RXRST,
drivers/tty/serial/xilinx_uartps.c
1348
writel(mr, port->membase + CDNS_UART_MR);
drivers/tty/serial/xilinx_uartps.c
1349
writel(cd, port->membase + CDNS_UART_BAUDGEN);
drivers/tty/serial/xilinx_uartps.c
1350
writel(bdiv, port->membase + CDNS_UART_BAUDDIV);
drivers/tty/serial/xilinx_uartps.c
1387
writel(imr, port->membase + CDNS_UART_IDR);
drivers/tty/serial/xilinx_uartps.c
1396
writel(ctrl, port->membase + CDNS_UART_CR);
drivers/tty/serial/xilinx_uartps.c
1403
writel(imr, port->membase + CDNS_UART_IER);
drivers/tty/serial/xilinx_uartps.c
1479
writel(1, port->membase + CDNS_UART_RXWM);
drivers/tty/serial/xilinx_uartps.c
1481
writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IDR);
drivers/tty/serial/xilinx_uartps.c
1525
writel(ctrl_reg, port->membase + CDNS_UART_CR);
drivers/tty/serial/xilinx_uartps.c
1531
writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
drivers/tty/serial/xilinx_uartps.c
1536
writel(ctrl_reg, port->membase + CDNS_UART_CR);
drivers/tty/serial/xilinx_uartps.c
1544
writel(rx_trigger_level, port->membase + CDNS_UART_RXWM);
drivers/tty/serial/xilinx_uartps.c
1546
writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IER);
drivers/tty/serial/xilinx_uartps.c
1622
writel(val, port->membase + CDNS_UART_MODEMCR);
drivers/tty/serial/xilinx_uartps.c
341
writel(val, cdns_uart->port->membase + CDNS_UART_MODEMCR);
drivers/tty/serial/xilinx_uartps.c
435
writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IDR);
drivers/tty/serial/xilinx_uartps.c
449
writel(ch, port->membase + CDNS_UART_FIFO);
drivers/tty/serial/xilinx_uartps.c
457
writel(CDNS_UART_IXR_TXEMPTY, cdns_uart->port->membase + CDNS_UART_IER);
drivers/tty/serial/xilinx_uartps.c
478
writel(isrstatus, port->membase + CDNS_UART_ISR);
drivers/tty/serial/xilinx_uartps.c
586
writel(mreg, port->membase + CDNS_UART_MR);
drivers/tty/serial/xilinx_uartps.c
587
writel(cd, port->membase + CDNS_UART_BAUDGEN);
drivers/tty/serial/xilinx_uartps.c
588
writel(bdiv, port->membase + CDNS_UART_BAUDDIV);
drivers/tty/serial/xilinx_uartps.c
637
writel(ctrl_reg, port->membase + CDNS_UART_CR);
drivers/tty/serial/xilinx_uartps.c
664
writel(ctrl_reg, port->membase + CDNS_UART_CR);
drivers/tty/serial/xilinx_uartps.c
675
writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
drivers/tty/serial/xilinx_uartps.c
679
writel(ctrl_reg, port->membase + CDNS_UART_CR);
drivers/tty/serial/xilinx_uartps.c
724
writel(status, port->membase + CDNS_UART_CR);
drivers/tty/serial/xilinx_uartps.c
730
writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_ISR);
drivers/tty/serial/xilinx_uartps.c
759
writel(regval, port->membase + CDNS_UART_CR);
drivers/tty/serial/xilinx_uartps.c
771
writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IDR);
drivers/tty/serial/xilinx_uartps.c
776
writel(regval, port->membase + CDNS_UART_CR);
drivers/tty/serial/xilinx_uartps.c
795
writel(CDNS_UART_CR_STARTBRK | (~CDNS_UART_CR_STOPBRK & status),
drivers/tty/serial/xilinx_uartps.c
799
writel(CDNS_UART_CR_STOPBRK | status,
drivers/tty/serial/xilinx_uartps.c
826
writel(ctrl_reg, port->membase + CDNS_UART_CR);
drivers/tty/serial/xilinx_uartps.c
847
writel(ctrl_reg, port->membase + CDNS_UART_CR);
drivers/tty/serial/xilinx_uartps.c
860
writel(ctrl_reg, port->membase + CDNS_UART_CR);
drivers/tty/serial/xilinx_uartps.c
862
writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
drivers/tty/serial/xilinx_uartps.c
923
writel(cval, port->membase + CDNS_UART_MR);
drivers/tty/serial/xilinx_uartps.c
930
writel(cval, port->membase + CDNS_UART_MODEMCR);
drivers/tty/serial/xilinx_uartps.c
958
writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
drivers/tty/serial/xilinx_uartps.c
964
writel(CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST,
drivers/tty/serial/xilinx_uartps.c
981
writel(status, port->membase + CDNS_UART_CR);
drivers/tty/serial/xilinx_uartps.c
986
writel(CDNS_UART_MR_CHMODE_NORM | CDNS_UART_MR_STOPMODE_1_BIT
drivers/tty/serial/xilinx_uartps.c
994
writel(rx_trigger_level, port->membase + CDNS_UART_RXWM);
drivers/tty/synclink_gt.c
3767
writel(value, calc_regaddr(info, addr));
drivers/ufs/core/ufs-mcq.c
271
writel(val, mcq_opr_base(hba, OPR_CQIS, i) + REG_CQIS);
drivers/ufs/core/ufs-mcq.c
402
writel(1, mcq_opr_base(hba, OPR_CQIS, i) + REG_CQIE);
drivers/ufs/core/ufs-mcq.c
492
writel(SQ_STOP, mcq_opr_base(hba, OPR_SQD, id) + REG_SQRTC);
drivers/ufs/core/ufs-mcq.c
511
writel(SQ_START, mcq_opr_base(hba, OPR_SQD, id) + REG_SQRTC);
drivers/ufs/core/ufs-mcq.c
561
writel(nexus, opr_sqd_base + REG_SQCTI);
drivers/ufs/core/ufs-mcq.c
564
writel(readl(opr_sqd_base + REG_SQRTC) | SQ_ICU,
drivers/ufs/core/ufshcd-priv.h
395
writel(val, q->mcq_sq_tail);
drivers/ufs/core/ufshcd-priv.h
419
writel(q->cq_head_slot * sizeof(struct cq_entry), q->mcq_cq_head);
drivers/ufs/host/ti-j721e-ufs.c
58
writel(ufs->reg, ufs->regbase + TI_UFS_SS_CTRL);
drivers/ufs/host/ti-j721e-ufs.c
89
writel(ufs->reg, ufs->regbase + TI_UFS_SS_CTRL);
drivers/ufs/host/ufs-exynos.h
259
writel(val, ufs->reg_##name + reg); \
drivers/ufs/host/ufs-hisi.h
94
writel((val), (host)->ufs_sys_ctrl + (reg))
drivers/ufs/host/ufs-rockchip.h
80
writel((val), (base) + (reg))
drivers/ufs/host/ufshcd-pci.c
268
writel(ltr, hba->mmio_base + INTEL_ACTIVELTR);
drivers/ufs/host/ufshcd-pci.c
269
writel(ltr, hba->mmio_base + INTEL_IDLELTR);
drivers/usb/cdns3/cdns3-ep0.c
118
writel(EP_CMD_SSTALL, &priv_dev->regs->ep_cmd);
drivers/usb/cdns3/cdns3-ep0.c
124
writel((send_erdy ? EP_CMD_ERDY : 0) | EP_CMD_REQ_CMPL,
drivers/usb/cdns3/cdns3-ep0.c
204
writel(reg | USB_CMD_FADDR(addr) | USB_CMD_SET_ADDR,
drivers/usb/cdns3/cdns3-ep0.c
60
writel(EP_STS_TRBERR, ®s->ep_sts);
drivers/usb/cdns3/cdns3-ep0.c
61
writel(EP_TRADDR_TRADDR(priv_ep->trb_pool_dma), ®s->ep_traddr);
drivers/usb/cdns3/cdns3-ep0.c
617
writel(ep_sts_reg, &priv_dev->regs->ep_sts);
drivers/usb/cdns3/cdns3-ep0.c
66
writel(EP_CMD_DRDY, ®s->ep_cmd);
drivers/usb/cdns3/cdns3-ep0.c
72
writel(EP_CMD_ERDY, &priv_dev->regs->ep_cmd);
drivers/usb/cdns3/cdns3-ep0.c
850
writel(ep_cfg, ®s->ep_cfg);
drivers/usb/cdns3/cdns3-ep0.c
852
writel(EP_STS_EN_SETUPEN | EP_STS_EN_DESCMISEN | EP_STS_EN_TRBERREN,
drivers/usb/cdns3/cdns3-ep0.c
859
writel(ep_cfg, ®s->ep_cfg);
drivers/usb/cdns3/cdns3-ep0.c
863
writel(EP_STS_EN_SETUPEN | EP_STS_EN_TRBERREN, ®s->ep_sts_en);
drivers/usb/cdns3/cdns3-gadget.c
101
writel(mask, ptr);
drivers/usb/cdns3/cdns3-gadget.c
1060
writel(EP_TRADDR_TRADDR(priv_ep->trb_pool_dma),
drivers/usb/cdns3/cdns3-gadget.c
1066
writel(EP_STS_TRBERR | EP_STS_DESCMIS, &priv_dev->regs->ep_sts);
drivers/usb/cdns3/cdns3-gadget.c
1076
writel(EP_CMD_TDL_SET(tdl) | EP_CMD_STDL,
drivers/usb/cdns3/cdns3-gadget.c
1079
writel(tdl, &priv_dev->regs->ep_tdl);
drivers/usb/cdns3/cdns3-gadget.c
1082
writel(EP_CMD_DRDY, &priv_dev->regs->ep_cmd);
drivers/usb/cdns3/cdns3-gadget.c
1083
writel(EP_CMD_ERDY_SID(priv_req->request.stream_id) |
drivers/usb/cdns3/cdns3-gadget.c
1104
writel(EP_STS_TRBERR, &priv_dev->regs->ep_sts);
drivers/usb/cdns3/cdns3-gadget.c
1105
writel(EP_CMD_DRDY, &priv_dev->regs->ep_cmd);
drivers/usb/cdns3/cdns3-gadget.c
1341
writel(EP_CMD_TDL_SET(tdl) | EP_CMD_STDL,
drivers/usb/cdns3/cdns3-gadget.c
1398
writel(EP_TRADDR_TRADDR(priv_ep->trb_pool_dma +
drivers/usb/cdns3/cdns3-gadget.c
1408
writel(EP_STS_TRBERR | EP_STS_DESCMIS, &priv_dev->regs->ep_sts);
drivers/usb/cdns3/cdns3-gadget.c
1409
writel(EP_CMD_DRDY, &priv_dev->regs->ep_cmd);
drivers/usb/cdns3/cdns3-gadget.c
1429
writel(USB_CONF_CFGSET, &priv_dev->regs->usb_conf);
drivers/usb/cdns3/cdns3-gadget.c
1663
writel(EP_CMD_DRDY, &priv_dev->regs->ep_cmd);
drivers/usb/cdns3/cdns3-gadget.c
1684
writel(EP_CMD_TDL_SET(tdl) | EP_CMD_STDL, &priv_dev->regs->ep_cmd);
drivers/usb/cdns3/cdns3-gadget.c
169
writel(ep, &priv_dev->regs->ep_sel);
drivers/usb/cdns3/cdns3-gadget.c
1706
writel(ep_sts_reg, &priv_dev->regs->ep_sts);
drivers/usb/cdns3/cdns3-gadget.c
1722
writel(EP_CMD_ERDY |
drivers/usb/cdns3/cdns3-gadget.c
1758
writel(ep_cfg, &priv_dev->regs->ep_cfg);
drivers/usb/cdns3/cdns3-gadget.c
1935
writel(reg, &priv_dev->regs->usb_ien);
drivers/usb/cdns3/cdns3-gadget.c
1942
writel(0, &priv_dev->regs->ep_ien);
drivers/usb/cdns3/cdns3-gadget.c
1971
writel(reg, &priv_dev->regs->usb_ists);
drivers/usb/cdns3/cdns3-gadget.c
1972
writel(USB_IEN_INIT, &priv_dev->regs->usb_ien);
drivers/usb/cdns3/cdns3-gadget.c
2006
writel(~0, &priv_dev->regs->ep_ien);
drivers/usb/cdns3/cdns3-gadget.c
2067
writel(USB_CONF_DMULT, ®s->usb_conf);
drivers/usb/cdns3/cdns3-gadget.c
2070
writel(USB_CONF2_EN_TDL_TRB, ®s->usb_conf2);
drivers/usb/cdns3/cdns3-gadget.c
2208
writel(ep_cfg, &priv_dev->regs->ep_cfg);
drivers/usb/cdns3/cdns3-gadget.c
2446
writel(EP_CMD_EPRST, &priv_dev->regs->ep_cmd);
drivers/usb/cdns3/cdns3-gadget.c
2465
writel(reg, &priv_dev->regs->ep_sts_en);
drivers/usb/cdns3/cdns3-gadget.c
2522
writel(ep_cfg, &priv_dev->regs->ep_cfg);
drivers/usb/cdns3/cdns3-gadget.c
2531
writel(EP_CMD_EPRST, &priv_dev->regs->ep_cmd);
drivers/usb/cdns3/cdns3-gadget.c
269
writel(EP_CMD_DFLUSH | EP_CMD_ERDY | EP_CMD_SSTALL,
drivers/usb/cdns3/cdns3-gadget.c
2735
writel(EP_CMD_DFLUSH, &priv_dev->regs->ep_cmd);
drivers/usb/cdns3/cdns3-gadget.c
2809
writel(EP_CMD_CSTALL | EP_CMD_EPRST, &priv_dev->regs->ep_cmd);
drivers/usb/cdns3/cdns3-gadget.c
287
writel(USB_CONF_CFGRST, &priv_dev->regs->usb_conf);
drivers/usb/cdns3/cdns3-gadget.c
2899
writel(USB_CONF_LGO_L0, &priv_dev->regs->usb_conf);
drivers/usb/cdns3/cdns3-gadget.c
2933
writel(USB_CONF_DEVEN, &priv_dev->regs->usb_conf);
drivers/usb/cdns3/cdns3-gadget.c
2935
writel(~0, &priv_dev->regs->ep_ists);
drivers/usb/cdns3/cdns3-gadget.c
2936
writel(~0, &priv_dev->regs->usb_ists);
drivers/usb/cdns3/cdns3-gadget.c
2937
writel(USB_CONF_DEVDS, &priv_dev->regs->usb_conf);
drivers/usb/cdns3/cdns3-gadget.c
2951
writel(EP_IEN_EP_OUT0 | EP_IEN_EP_IN0, ®s->ep_ien);
drivers/usb/cdns3/cdns3-gadget.c
2963
writel(reg, ®s->dbg_link1);
drivers/usb/cdns3/cdns3-gadget.c
2974
writel(reg, ®s->dma_axi_ctrl);
drivers/usb/cdns3/cdns3-gadget.c
2977
writel(USB_IEN_INIT, ®s->usb_ien);
drivers/usb/cdns3/cdns3-gadget.c
2978
writel(USB_CONF_CLK2OFFDS | USB_CONF_L1DS, ®s->usb_conf);
drivers/usb/cdns3/cdns3-gadget.c
2980
writel(PUSB_PWR_FST_REG_ACCESS, &priv_dev->regs->usb_pwr);
drivers/usb/cdns3/cdns3-gadget.c
3007
writel(USB_CONF_SFORCE_FS, &priv_dev->regs->usb_conf);
drivers/usb/cdns3/cdns3-gadget.c
3008
writel(USB_CONF_USB3DIS, &priv_dev->regs->usb_conf);
drivers/usb/cdns3/cdns3-gadget.c
3011
writel(USB_CONF_USB3DIS, &priv_dev->regs->usb_conf);
drivers/usb/cdns3/cdns3-gadget.c
3055
writel(EP_CMD_EPRST, &priv_dev->regs->ep_cmd);
drivers/usb/cdns3/cdns3-gadget.c
3063
writel(0, &priv_dev->regs->usb_ien);
drivers/usb/cdns3/cdns3-gadget.c
3064
writel(0, &priv_dev->regs->usb_pwr);
drivers/usb/cdns3/cdns3-gadget.c
3065
writel(USB_CONF_DEVDS, &priv_dev->regs->usb_conf);
drivers/usb/cdns3/cdns3-gadget.c
3471
writel(0, &priv_dev->regs->usb_ien);
drivers/usb/cdns3/cdns3-gadget.c
3485
writel(USB_CONF_DEVEN, &priv_dev->regs->usb_conf);
drivers/usb/cdns3/cdns3-gadget.c
354
writel(USB_CONF_L1EN, &priv_dev->regs->usb_conf);
drivers/usb/cdns3/cdns3-gadget.c
356
writel(USB_CONF_L1DS, &priv_dev->regs->usb_conf);
drivers/usb/cdns3/cdns3-gadget.c
567
writel(reg, &priv_dev->regs->ep_sts_en);
drivers/usb/cdns3/cdns3-gadget.c
717
writel(EP_CMD_TDL_SET(reset_val) | EP_CMD_STDL,
drivers/usb/cdns3/cdns3-gadget.c
757
writel(ep_sts_en_reg,
drivers/usb/cdns3/cdns3-gadget.c
774
writel(EP_CMD_DRDY,
drivers/usb/cdns3/cdns3-gadget.c
90
writel(mask, ptr);
drivers/usb/cdns3/cdns3-imx.c
104
writel(value, data->noncore + offset);
drivers/usb/cdns3/cdns3-imx.c
267
writel(value, xhci_regs + XECP_PM_PMCSR);
drivers/usb/cdns3/cdns3-imx.c
306
writel(value, xhci_regs + XECP_PM_PMCSR);
drivers/usb/cdns3/cdns3-imx.c
311
writel(value, xhci_regs + XECP_AUX_CTRL_REG1);
drivers/usb/cdns3/cdns3-ti.c
87
writel(value, data->usbss + offset);
drivers/usb/cdns3/cdnsp-ep0.c
199
writel(temp, &pdev->active_port->regs->portpmsc);
drivers/usb/cdns3/cdnsp-gadget.c
113
writel(temp, port_regs);
drivers/usb/cdns3/cdnsp-gadget.c
122
writel(temp, port_regs);
drivers/usb/cdns3/cdnsp-gadget.c
1287
writel(temp, &pdev->ir_set->irq_control);
drivers/usb/cdns3/cdnsp-gadget.c
131
writel(temp | PORT_PED, port_regs);
drivers/usb/cdns3/cdnsp-gadget.c
1314
writel(temp, &pdev->port3x_regs->mode_addr);
drivers/usb/cdns3/cdnsp-gadget.c
1326
writel(PORT_REG6_L1_L0_HW_EN | fs_speed, &pdev->port20_regs->port_reg6);
drivers/usb/cdns3/cdnsp-gadget.c
1336
writel(temp, &pdev->op_regs->command);
drivers/usb/cdns3/cdnsp-gadget.c
1339
writel(IMAN_IE_SET(temp), &pdev->ir_set->irq_pending);
drivers/usb/cdns3/cdnsp-gadget.c
139
writel(cdnsp_port_state_to_neutral(portsc) |
drivers/usb/cdns3/cdnsp-gadget.c
1478
writel((temp & ~0x1fff) | STS_EINT, &pdev->op_regs->status);
drivers/usb/cdns3/cdnsp-gadget.c
1480
writel(IMAN_IE_CLEAR(temp), &pdev->ir_set->irq_pending);
drivers/usb/cdns3/cdnsp-gadget.c
1488
writel(temp, &pdev->ir_set->irq_pending);
drivers/usb/cdns3/cdnsp-gadget.c
160
writel(cpu_to_le32(val), reg);
drivers/usb/cdns3/cdnsp-gadget.c
174
writel(bit, reg);
drivers/usb/cdns3/cdnsp-gadget.c
188
writel(bit, reg);
drivers/usb/cdns3/cdnsp-gadget.c
1895
writel(reg, &pdev->port3x_regs->mode_2);
drivers/usb/cdns3/cdnsp-gadget.c
208
writel(cmd, &pdev->op_regs->command);
drivers/usb/cdns3/cdnsp-gadget.c
261
writel(temp, &pdev->op_regs->command);
drivers/usb/cdns3/cdnsp-gadget.c
307
writel(command, &pdev->op_regs->command);
drivers/usb/cdns3/cdnsp-gadget.c
953
writel(PORT_BESL(CDNSP_DEFAULT_BESL) | PORT_L1S_NYET | PORT_HLE,
drivers/usb/cdns3/cdnsp-gadget.c
956
writel(PORT_L1S_NYET, &pdev->active_port->regs->portpmsc);
drivers/usb/cdns3/cdnsp-mem.c
1224
writel(val, &pdev->op_regs->config_reg);
drivers/usb/cdns3/cdnsp-mem.c
1295
writel(val, &pdev->ir_set->erst_size);
drivers/usb/cdns3/cdnsp-ring.c
1588
writel(status | STS_EINT, &pdev->op_regs->status);
drivers/usb/cdns3/cdnsp-ring.c
1591
writel(irq_pending, &pdev->ir_set->irq_pending);
drivers/usb/cdns3/cdnsp-ring.c
269
writel(DB_VALUE_CMD, &pdev->dba->cmd_db);
drivers/usb/cdns3/cdnsp-ring.c
309
writel(db_value, reg_addr);
drivers/usb/cdns3/cdnsp-ring.c
785
writel(PORT_U1_TIMEOUT(1) | PORT_U2_TIMEOUT(1),
drivers/usb/cdns3/cdnsp-ring.c
816
writel(cdnsp_port_state_to_neutral(portsc) |
drivers/usb/cdns3/drd.c
115
writel(reg, &cdns->otg_cdnsp_regs->override);
drivers/usb/cdns3/drd.c
128
writel(reg, &cdns->otg_cdnsp_regs->override);
drivers/usb/cdns3/drd.c
160
writel(0, &cdns->otg_irq_regs->ien);
drivers/usb/cdns3/drd.c
169
writel(OTGIEN_ID_CHANGE_INT | OTGIEN_VBUSVALID_RISE_INT |
drivers/usb/cdns3/drd.c
185
writel(OTGCMD_HOST_BUS_REQ | OTGCMD_OTG_DIS,
drivers/usb/cdns3/drd.c
213
writel(OTGCMD_HOST_BUS_DROP | OTGCMD_DEV_BUS_DROP |
drivers/usb/cdns3/drd.c
238
writel(OTGCMD_DEV_BUS_REQ | reg, &cdns->otg_regs->cmd);
drivers/usb/cdns3/drd.c
273
writel(OTGCMD_HOST_BUS_DROP | OTGCMD_DEV_BUS_DROP |
drivers/usb/cdns3/drd.c
297
writel(~0, &cdns->otg_irq_regs->ivect);
drivers/usb/cdns3/drd.c
385
writel(~0, &cdns->otg_irq_regs->ivect);
drivers/usb/cdns3/drd.c
416
writel(1, &cdns->otg_v0_regs->simulate);
drivers/usb/cdns3/drd.c
435
writel(1, &cdns->otg_v1_regs->simulate);
drivers/usb/cdns3/drd.c
441
writel(reg, &cdns->otg_v1_regs->susp_ctrl);
drivers/usb/cdns3/drd.c
55
writel(reg, override_reg);
drivers/usb/cdns3/drd.c
67
writel(reg, &cdns->otg_v1_regs->phyrst_cfg);
drivers/usb/cdns3/host.c
40
writel(value, &xhci->op_regs->command);
drivers/usb/cdns3/host.c
45
writel(value, hcd->regs + XECP_AUX_CTRL_REG1);
drivers/usb/cdns3/host.c
49
writel(value, hcd->regs + XECP_PORT_CAP_REG);
drivers/usb/chipidea/ci_hdrc_msm.c
62
writel(val, addr);
drivers/usb/chipidea/ci_hdrc_msm.c
70
writel(val, addr);
drivers/usb/chipidea/usbmisc_imx.c
1030
writel(reg, usbmisc->base);
drivers/usb/chipidea/usbmisc_imx.c
1034
writel(reg | MX6_BM_NON_BURST_SETTING, usbmisc->base);
drivers/usb/chipidea/usbmisc_imx.c
1038
writel(reg | MX6_BM_UTMI_ON_CLOCK, usbmisc->base);
drivers/usb/chipidea/usbmisc_imx.c
1042
writel(reg, usbmisc->base + MX6_USB_HSIC_CTRL_OFFSET);
drivers/usb/chipidea/usbmisc_imx.c
1049
writel(reg | MX7D_USBNC_AUTO_RESUME,
drivers/usb/chipidea/usbmisc_imx.c
1054
writel(reg | MX7D_USB_VBUS_WAKEUP_SOURCE_BVALID,
drivers/usb/chipidea/usbmisc_imx.c
1079
writel(val, usbmisc->base + MX7D_USBNC_USB_CTRL2);
drivers/usb/chipidea/usbmisc_imx.c
1089
writel(val, usbmisc->base + MX7D_USBNC_USB_CTRL2);
drivers/usb/chipidea/usbmisc_imx.c
1168
writel(val, usbmisc->blkctl + BLKCTL_USB_WAKEUP_CTRL);
drivers/usb/chipidea/usbmisc_imx.c
225
writel(val, usbmisc->base);
drivers/usb/chipidea/usbmisc_imx.c
241
writel(val, usbmisc->base);
drivers/usb/chipidea/usbmisc_imx.c
272
writel(val, reg);
drivers/usb/chipidea/usbmisc_imx.c
304
writel(val, usbmisc->base);
drivers/usb/chipidea/usbmisc_imx.c
324
writel(val, usbmisc->base + MX53_USB_OTG_PHY_CTRL_1_OFFSET);
drivers/usb/chipidea/usbmisc_imx.c
333
writel(val, reg);
drivers/usb/chipidea/usbmisc_imx.c
340
writel(val, reg);
drivers/usb/chipidea/usbmisc_imx.c
351
writel(val, reg);
drivers/usb/chipidea/usbmisc_imx.c
356
writel(val, reg);
drivers/usb/chipidea/usbmisc_imx.c
363
writel(val, reg);
drivers/usb/chipidea/usbmisc_imx.c
370
writel(val, reg);
drivers/usb/chipidea/usbmisc_imx.c
381
writel(val, reg);
drivers/usb/chipidea/usbmisc_imx.c
386
writel(val, reg);
drivers/usb/chipidea/usbmisc_imx.c
394
writel(val, reg);
drivers/usb/chipidea/usbmisc_imx.c
400
writel(val, reg);
drivers/usb/chipidea/usbmisc_imx.c
444
writel(val, usbmisc->base + data->index * 4);
drivers/usb/chipidea/usbmisc_imx.c
479
writel(reg, usbmisc->base + data->index * 4);
drivers/usb/chipidea/usbmisc_imx.c
483
writel(reg | MX6_BM_NON_BURST_SETTING,
drivers/usb/chipidea/usbmisc_imx.c
489
writel(reg | MX6_BM_UTMI_ON_CLOCK,
drivers/usb/chipidea/usbmisc_imx.c
494
writel(reg, usbmisc->base + MX6_USB_HSIC_CTRL_OFFSET
drivers/usb/chipidea/usbmisc_imx.c
542
writel(val | MX6_BM_HSIC_DEV_CONN,
drivers/usb/chipidea/usbmisc_imx.c
571
writel(val, usbmisc->base + MX6_USB_HSIC_CTRL_OFFSET + offset);
drivers/usb/chipidea/usbmisc_imx.c
592
writel(val | MX6SX_USB_VBUS_WAKEUP_SOURCE_BVALID, reg);
drivers/usb/chipidea/usbmisc_imx.c
598
writel(val & ~MX6SX_BM_DPDM_WAKEUP_EN,
drivers/usb/chipidea/usbmisc_imx.c
607
writel(val, usbmisc->base + MX6_USB_HSIC_CTRL_OFFSET);
drivers/usb/chipidea/usbmisc_imx.c
627
writel(reg | VF610_OVER_CUR_DIS, usbmisc->base);
drivers/usb/chipidea/usbmisc_imx.c
647
writel(reg, usbmisc->base);
drivers/usb/chipidea/usbmisc_imx.c
666
writel(reg, usbmisc->base);
drivers/usb/chipidea/usbmisc_imx.c
696
writel(val, usbmisc->base);
drivers/usb/chipidea/usbmisc_imx.c
700
writel(val & ~MX6_USB_OTG_WAKEUP_BITS, usbmisc->base);
drivers/usb/chipidea/usbmisc_imx.c
735
writel(reg, usbmisc->base);
drivers/usb/chipidea/usbmisc_imx.c
739
writel(reg | MX6_BM_NON_BURST_SETTING, usbmisc->base);
drivers/usb/chipidea/usbmisc_imx.c
744
writel(reg | MX7D_USB_VBUS_WAKEUP_SOURCE_BVALID
drivers/usb/chipidea/usbmisc_imx.c
770
writel(reg, usbmisc->base + MX7D_USB_OTG_PHY_CFG1);
drivers/usb/chipidea/usbmisc_imx.c
791
writel(val, usbmisc->base + MX7D_USB_OTG_PHY_CFG2);
drivers/usb/chipidea/usbmisc_imx.c
800
writel(val | MX7D_USB_OTG_PHY_CFG2_CHRG_VDATSRCENB0 |
drivers/usb/chipidea/usbmisc_imx.c
838
writel(val, usbmisc->base + MX7D_USB_OTG_PHY_CFG2);
drivers/usb/chipidea/usbmisc_imx.c
843
writel(val, usbmisc->base + MX7D_USBNC_USB_CTRL2);
drivers/usb/chipidea/usbmisc_imx.c
846
writel(val & ~MX7D_USBNC_USB_CTRL2_OPMODE_OVERRIDE_EN,
drivers/usb/chipidea/usbmisc_imx.c
861
writel(val | MX7D_USB_OTG_PHY_CFG2_CHRG_DCDENB,
drivers/usb/chipidea/usbmisc_imx.c
881
writel(val & ~MX7D_USB_OTG_PHY_CFG2_CHRG_DCDENB,
drivers/usb/chipidea/usbmisc_imx.c
905
writel(val | MX7D_USB_OTG_PHY_CFG2_CHRG_VDATSRCENB0 |
drivers/usb/chipidea/usbmisc_imx.c
954
writel(val, usbmisc->base + MX7D_USBNC_USB_CTRL2);
drivers/usb/chipidea/usbmisc_imx.c
957
writel(val | MX7D_USBNC_USB_CTRL2_OPMODE_OVERRIDE_EN,
drivers/usb/chipidea/usbmisc_imx.c
997
writel(val, usbmisc->base + MX7D_USB_OTG_PHY_CFG2);
drivers/usb/dwc2/core.c
1209
writel(otgctl, hsotg->regs + GOTGCTL);
drivers/usb/dwc2/core.h
1245
writel(swab32(value), hsotg->regs + offset);
drivers/usb/dwc2/core.h
1247
writel(value, hsotg->regs + offset);
drivers/usb/dwc3/dwc3-am62.c
149
writel(value, (am62->usbss) + offset);
drivers/usb/dwc3/dwc3-am62.c
198
writel(reg, am62->phy_regs + USB_PHY_PLL_REG12);
drivers/usb/dwc3/dwc3-apple.c
132
writel(value, appledwc->apple_regs + offset - APPLE_DWC3_REGS_START);
drivers/usb/dwc3/dwc3-imx8mp.c
120
writel(val, dwc3_imx->hsio_blk_base + USB_WAKEUP_CTRL);
drivers/usb/dwc3/dwc3-imx8mp.c
129
writel(val, dwc3_imx->hsio_blk_base + USB_WAKEUP_CTRL);
drivers/usb/dwc3/dwc3-imx8mp.c
84
writel(value, dwc3_imx->glue_base + USB_CTRL0);
drivers/usb/dwc3/dwc3-imx8mp.c
97
writel(value, dwc3_imx->glue_base + USB_CTRL1);
drivers/usb/dwc3/dwc3-keystone.c
49
writel(value, base + offset);
drivers/usb/dwc3/dwc3-omap.c
148
writel(value, base + offset);
drivers/usb/dwc3/dwc3-pci.c
125
writel(value, reg + GP_RWREG1);
drivers/usb/dwc3/dwc3-qcom-legacy.c
101
writel(reg, base + offset);
drivers/usb/dwc3/dwc3-qcom-legacy.c
113
writel(reg, base + offset);
drivers/usb/dwc3/dwc3-qcom.c
110
writel(reg, base + offset);
drivers/usb/dwc3/dwc3-qcom.c
98
writel(reg, base + offset);
drivers/usb/dwc3/dwc3-rtk.c
211
writel(DISABLE_MULTI_REQ | val, reg);
drivers/usb/dwc3/dwc3-rtk.c
218
writel(USB2_PHY_EN_PHY_PLL_PORT1 | val, reg);
drivers/usb/dwc3/dwc3-rtk.c
224
writel(TXHSVM_EN | val, reg);
drivers/usb/dwc3/dwc3-rtk.c
231
writel(U3PORT_DIS | val, reg);
drivers/usb/dwc3/dwc3-rtk.c
235
writel(FORCE_PIPE3_PHY_STATUS_TO_0 | val, reg);
drivers/usb/dwc3/dwc3-rtk.c
239
writel(RESET_DISABLE_PIPE3_P0 | val, reg);
drivers/usb/dwc3/dwc3-rtk.c
243
writel(U3PORT_DIS | val, reg);
drivers/usb/dwc3/dwc3-rtk.c
247
writel(~USB3_MBIAS_ENABLE & val, reg);
drivers/usb/dwc3/dwc3-rtk.c
255
writel(DESC_R2W_MULTI_DISABLE | val, reg);
drivers/usb/dwc3/dwc3-rtk.c
260
writel(USB2_PHY_SWITCH_HOST | val, reg);
drivers/usb/dwc3/dwc3-rtk.c
265
writel(val, reg);
drivers/usb/dwc3/dwc3-rtk.c
75
writel(USB2_PHY_SWITCH_DEVICE | val, reg);
drivers/usb/dwc3/dwc3-rtk.c
78
writel(USB2_PHY_SWITCH_HOST | val, reg);
drivers/usb/dwc3/dwc3-xilinx.c
200
writel(FPD_POWER_PRSNT_OPTION, priv_data->regs + XLNX_USB_FPD_POWER_PRSNT);
drivers/usb/dwc3/dwc3-xilinx.c
202
writel(PIPE_CLK_SELECT, priv_data->regs + XLNX_USB_FPD_PIPE_CLK);
drivers/usb/dwc3/dwc3-xilinx.c
205
writel(PIPE_CLK_DESELECT, priv_data->regs + XLNX_USB_FPD_PIPE_CLK);
drivers/usb/dwc3/dwc3-xilinx.c
69
writel(reg, priv_data->regs + XLNX_USB_PHY_RST_EN);
drivers/usb/dwc3/dwc3-xilinx.c
85
writel(reg, priv_data->regs + coherency_offset);
drivers/usb/dwc3/host.c
57
writel(reg, xhci_regs + offset);
drivers/usb/dwc3/io.h
50
writel(value, base + offset - DWC3_GLOBALS_REGS_START);
drivers/usb/early/ehci-dbgp.c
176
writel(ctrl | DBGP_DONE, &ehci_debug->control);
drivers/usb/early/ehci-dbgp.c
201
writel(ctrl | DBGP_GO, &ehci_debug->control);
drivers/usb/early/ehci-dbgp.c
247
writel(lo, &ehci_debug->data03);
drivers/usb/early/ehci-dbgp.c
248
writel(hi, &ehci_debug->data47);
drivers/usb/early/ehci-dbgp.c
286
writel(addr, &ehci_debug->address);
drivers/usb/early/ehci-dbgp.c
287
writel(pids, &ehci_debug->pids);
drivers/usb/early/ehci-dbgp.c
312
writel(addr, &ehci_debug->address);
drivers/usb/early/ehci-dbgp.c
313
writel(pids, &ehci_debug->pids);
drivers/usb/early/ehci-dbgp.c
353
writel(addr, &ehci_debug->address);
drivers/usb/early/ehci-dbgp.c
354
writel(pids, &ehci_debug->pids);
drivers/usb/early/ehci-dbgp.c
435
writel(ctrl, &ehci_debug->control);
drivers/usb/early/ehci-dbgp.c
443
writel(cmd, &ehci_regs->command);
drivers/usb/early/ehci-dbgp.c
446
writel(FLAG_CF, &ehci_regs->configured_flag);
drivers/usb/early/ehci-dbgp.c
473
writel(cmd, &ehci_regs->command);
drivers/usb/early/ehci-dbgp.c
517
writel(cmd, &ehci_regs->command);
drivers/usb/early/ehci-dbgp.c
520
writel(portsc, &ehci_regs->port_status[dbg_port - 1]);
drivers/usb/early/ehci-dbgp.c
536
writel(ctrl, &ehci_debug->control);
drivers/usb/early/ehci-dbgp.c
540
writel(ctrl & ~DBGP_CLAIM, &ehci_debug->control);
drivers/usb/early/ehci-dbgp.c
548
writel(portsc, &ehci_regs->port_status[dbg_port - 1]);
drivers/usb/early/ehci-dbgp.c
619
writel(portsc, &ehci_regs->port_status[port - 1]);
drivers/usb/early/ehci-dbgp.c
632
writel(portsc & ~(PORT_RWC_BITS | PORT_RESET),
drivers/usb/early/ehci-dbgp.c
805
writel(ctrl, &ehci_debug->control);
drivers/usb/early/ehci-dbgp.c
930
writel(cmd, &ehci_regs->command);
drivers/usb/early/ehci-dbgp.c
956
writel(cmd, &ehci_regs->command);
drivers/usb/early/ehci-dbgp.c
990
writel(ctrl, &ehci_debug->control);
drivers/usb/early/xhci-dbc.c
1006
writel(0, &xdbc.xdbc_reg->control);
drivers/usb/early/xhci-dbc.c
160
writel(val | XHCI_HC_OS_OWNED, xdbc.xhci_base + offset);
drivers/usb/early/xhci-dbc.c
165
writel(val & ~XHCI_HC_BIOS_OWNED, xdbc.xhci_base + offset);
drivers/usb/early/xhci-dbc.c
173
writel(val, xdbc.xhci_base + offset + XHCI_LEGACY_CONTROL_OFFSET);
drivers/usb/early/xhci-dbc.c
257
writel(1, &xdbc.xdbc_reg->ersts);
drivers/usb/early/xhci-dbc.c
339
writel(dev_info, &xdbc.xdbc_reg->devinfo1);
drivers/usb/early/xhci-dbc.c
342
writel(dev_info, &xdbc.xdbc_reg->devinfo2);
drivers/usb/early/xhci-dbc.c
363
writel(val | PORT_RESET, portsc);
drivers/usb/early/xhci-dbc.c
415
writel(DOOR_BELL_TARGET(target), &xdbc.xdbc_reg->doorbell);
drivers/usb/early/xhci-dbc.c
424
writel(ctrl | CTRL_DBC_ENABLE | CTRL_PORT_ENABLE, &xdbc.xdbc_reg->control);
drivers/usb/early/xhci-dbc.c
529
writel(0, &xdbc.xdbc_reg->control);
drivers/usb/early/xhci-dbc.c
557
writel(0, &xdbc.xdbc_reg->control);
drivers/usb/early/xhci-dbc.c
590
writel(0, &xdbc.xdbc_reg->control);
drivers/usb/early/xhci-dbc.c
718
writel(port_reg, &xdbc.xdbc_reg->portsc);
drivers/usb/early/xhci-dbc.c
785
writel(reg, &xdbc.xdbc_reg->control);
drivers/usb/early/xhci-dbc.c
956
writel(0, &xdbc.xdbc_reg->control);
drivers/usb/fotg210/fotg210-hcd.h
659
writel(val, regs);
drivers/usb/gadget/udc/amd5536udc_pci.c
70
writel(AMD_BIT(UDC_DEVCFG_SOFTRESET), &dev->regs->cfg);
drivers/usb/gadget/udc/aspeed-vhub/core.c
110
writel(istat, vhub->regs + AST_VHUB_ISR);
drivers/usb/gadget/udc/aspeed-vhub/core.c
121
writel(ep_acks, vhub->regs + AST_VHUB_EP_ACK_ISR);
drivers/usb/gadget/udc/aspeed-vhub/core.c
199
writel(ctrl, vhub->regs + AST_VHUB_CTRL);
drivers/usb/gadget/udc/aspeed-vhub/core.c
205
writel(ctrl, vhub->regs + AST_VHUB_CTRL);
drivers/usb/gadget/udc/aspeed-vhub/core.c
212
writel(VHUB_SW_RESET_ROOT_HUB |
drivers/usb/gadget/udc/aspeed-vhub/core.c
217
writel(0, vhub->regs + AST_VHUB_SW_RESET);
drivers/usb/gadget/udc/aspeed-vhub/core.c
221
writel(0, vhub->regs + AST_VHUB_EP_ACK_IER);
drivers/usb/gadget/udc/aspeed-vhub/core.c
222
writel(0, vhub->regs + AST_VHUB_EP_NACK_IER);
drivers/usb/gadget/udc/aspeed-vhub/core.c
223
writel(epn_mask, vhub->regs + AST_VHUB_EP_ACK_ISR);
drivers/usb/gadget/udc/aspeed-vhub/core.c
224
writel(epn_mask, vhub->regs + AST_VHUB_EP_NACK_ISR);
drivers/usb/gadget/udc/aspeed-vhub/core.c
227
writel(0, vhub->regs + AST_VHUB_EP0_CTRL);
drivers/usb/gadget/udc/aspeed-vhub/core.c
228
writel(VHUB_EP1_CTRL_RESET_TOGGLE |
drivers/usb/gadget/udc/aspeed-vhub/core.c
231
writel(0, vhub->regs + AST_VHUB_EP1_STS_CHG);
drivers/usb/gadget/udc/aspeed-vhub/core.c
234
writel(vhub->ep0.buf_dma, vhub->regs + AST_VHUB_EP0_DATA);
drivers/usb/gadget/udc/aspeed-vhub/core.c
237
writel(0, vhub->regs + AST_VHUB_CONF);
drivers/usb/gadget/udc/aspeed-vhub/core.c
244
writel(ctrl, vhub->regs + AST_VHUB_CTRL);
drivers/usb/gadget/udc/aspeed-vhub/core.c
247
writel(VHUB_IRQ_HUB_EP0_IN_ACK_STALL |
drivers/usb/gadget/udc/aspeed-vhub/core.c
273
writel(0, vhub->regs + AST_VHUB_IER);
drivers/usb/gadget/udc/aspeed-vhub/core.c
274
writel(VHUB_IRQ_ACK_ALL, vhub->regs + AST_VHUB_ISR);
drivers/usb/gadget/udc/aspeed-vhub/core.c
277
writel(VHUB_CTRL_PHY_CLK |
drivers/usb/gadget/udc/aspeed-vhub/core.c
371
writel(0, vhub->regs + AST_VHUB_IER);
drivers/usb/gadget/udc/aspeed-vhub/core.c
372
writel(VHUB_IRQ_ACK_ALL, vhub->regs + AST_VHUB_ISR);
drivers/usb/gadget/udc/aspeed-vhub/dev.c
100
writel(reg, d->vhub->regs + AST_VHUB_IER);
drivers/usb/gadget/udc/aspeed-vhub/dev.c
103
writel(0, d->regs + AST_VHUB_DEV_EN_CTRL);
drivers/usb/gadget/udc/aspeed-vhub/dev.c
126
writel(val, d->vhub->regs + AST_VHUB_CTRL);
drivers/usb/gadget/udc/aspeed-vhub/dev.c
214
writel(reg, d->regs + AST_VHUB_DEV_EN_CTRL);
drivers/usb/gadget/udc/aspeed-vhub/dev.c
35
writel(istat, d->regs + AST_VHUB_DEV_ISR);
drivers/usb/gadget/udc/aspeed-vhub/dev.c
62
writel(reg, d->regs + AST_VHUB_DEV_EN_CTRL);
drivers/usb/gadget/udc/aspeed-vhub/dev.c
68
writel(reg, d->vhub->regs + AST_VHUB_IER);
drivers/usb/gadget/udc/aspeed-vhub/dev.c
71
writel(d->ep0.buf_dma, d->regs + AST_VHUB_DEV_EP0_DATA);
drivers/usb/gadget/udc/aspeed-vhub/ep0.c
163
writel(VHUB_EP0_CTRL_STALL, ep->ep0.ctlstat);
drivers/usb/gadget/udc/aspeed-vhub/ep0.c
170
writel(VHUB_EP0_TX_BUFF_RDY, ep->ep0.ctlstat);
drivers/usb/gadget/udc/aspeed-vhub/ep0.c
193
writel(VHUB_EP0_RX_BUFF_RDY, ep->ep0.ctlstat);
drivers/usb/gadget/udc/aspeed-vhub/ep0.c
222
writel(reg, ep->ep0.ctlstat);
drivers/usb/gadget/udc/aspeed-vhub/ep0.c
223
writel(reg | VHUB_EP0_TX_BUFF_RDY, ep->ep0.ctlstat);
drivers/usb/gadget/udc/aspeed-vhub/ep0.c
232
writel(VHUB_EP0_RX_BUFF_RDY, ep->ep0.ctlstat);
drivers/usb/gadget/udc/aspeed-vhub/ep0.c
267
writel(VHUB_EP0_TX_BUFF_RDY, ep->ep0.ctlstat);
drivers/usb/gadget/udc/aspeed-vhub/ep0.c
353
writel(VHUB_EP0_CTRL_STALL, ep->ep0.ctlstat);
drivers/usb/gadget/udc/aspeed-vhub/ep0.c
426
writel(VHUB_EP0_TX_BUFF_RDY, ep->ep0.ctlstat);
drivers/usb/gadget/udc/aspeed-vhub/ep0.c
462
writel(VHUB_EP0_CTRL_STALL, ep->ep0.ctlstat);
drivers/usb/gadget/udc/aspeed-vhub/epn.c
241
writel(VHUB_EP_DMA_SET_CPU_WPTR(ep->epn.d_next),
drivers/usb/gadget/udc/aspeed-vhub/epn.c
426
writel(VHUB_EP_DMA_CTRL_RESET, ep->epn.regs + AST_VHUB_EP_DMA_CTLSTAT);
drivers/usb/gadget/udc/aspeed-vhub/epn.c
428
writel(0, ep->epn.regs + AST_VHUB_EP_DMA_CTLSTAT);
drivers/usb/gadget/udc/aspeed-vhub/epn.c
460
writel(reg, ep->epn.regs + AST_VHUB_EP_DESC_STATUS);
drivers/usb/gadget/udc/aspeed-vhub/epn.c
463
writel(ep->epn.dma_conf,
drivers/usb/gadget/udc/aspeed-vhub/epn.c
467
writel(ep->epn.dma_conf,
drivers/usb/gadget/udc/aspeed-vhub/epn.c
514
writel(reg, ep->epn.regs + AST_VHUB_EP_CONFIG);
drivers/usb/gadget/udc/aspeed-vhub/epn.c
517
writel(VHUB_EP_TOGGLE_SET_EPNUM(ep->epn.g_idx),
drivers/usb/gadget/udc/aspeed-vhub/epn.c
580
writel(0, ep->epn.regs + AST_VHUB_EP_CONFIG);
drivers/usb/gadget/udc/aspeed-vhub/epn.c
586
writel(ep_ier, vhub->regs + AST_VHUB_EP_ACK_IER);
drivers/usb/gadget/udc/aspeed-vhub/epn.c
587
writel(imask, vhub->regs + AST_VHUB_EP_ACK_ISR);
drivers/usb/gadget/udc/aspeed-vhub/epn.c
67
writel(ep->buf_dma, ep->epn.regs + AST_VHUB_EP_DESC_BASE);
drivers/usb/gadget/udc/aspeed-vhub/epn.c
702
writel(0, ep->epn.regs + AST_VHUB_EP_CONFIG);
drivers/usb/gadget/udc/aspeed-vhub/epn.c
703
writel(VHUB_EP_DMA_CTRL_RESET,
drivers/usb/gadget/udc/aspeed-vhub/epn.c
707
writel(ep_conf, ep->epn.regs + AST_VHUB_EP_CONFIG);
drivers/usb/gadget/udc/aspeed-vhub/epn.c
71
writel(req->req.dma + act, ep->epn.regs + AST_VHUB_EP_DESC_BASE);
drivers/usb/gadget/udc/aspeed-vhub/epn.c
711
writel(0, ep->epn.regs + AST_VHUB_EP_DESC_STATUS);
drivers/usb/gadget/udc/aspeed-vhub/epn.c
714
writel(ep->epn.descs_dma,
drivers/usb/gadget/udc/aspeed-vhub/epn.c
723
writel(ep->epn.dma_conf | VHUB_EP_DMA_CTRL_RESET,
drivers/usb/gadget/udc/aspeed-vhub/epn.c
727
writel(ep->epn.dma_conf,
drivers/usb/gadget/udc/aspeed-vhub/epn.c
734
writel(ep->epn.dma_conf | VHUB_EP_DMA_CTRL_RESET,
drivers/usb/gadget/udc/aspeed-vhub/epn.c
736
writel(ep->epn.dma_conf,
drivers/usb/gadget/udc/aspeed-vhub/epn.c
738
writel(0, ep->epn.regs + AST_VHUB_EP_DESC_STATUS);
drivers/usb/gadget/udc/aspeed-vhub/epn.c
742
writel(VHUB_EP_TOGGLE_SET_EPNUM(ep->epn.g_idx),
drivers/usb/gadget/udc/aspeed-vhub/epn.c
747
writel(imask, vhub->regs + AST_VHUB_EP_ACK_ISR);
drivers/usb/gadget/udc/aspeed-vhub/epn.c
750
writel(ep_ier, vhub->regs + AST_VHUB_EP_ACK_IER);
drivers/usb/gadget/udc/aspeed-vhub/epn.c
76
writel(VHUB_EP_DMA_SET_TX_SIZE(chunk),
drivers/usb/gadget/udc/aspeed-vhub/epn.c
78
writel(VHUB_EP_DMA_SET_TX_SIZE(chunk) | VHUB_EP_DMA_SINGLE_KICK,
drivers/usb/gadget/udc/aspeed-vhub/hub.c
231
writel(val, ep->vhub->regs + AST_VHUB_CTRL);
drivers/usb/gadget/udc/aspeed-vhub/hub.c
268
writel(reg, ep->vhub->regs + AST_VHUB_EP1_CTRL);
drivers/usb/gadget/udc/aspeed-vhub/hub.c
426
writel(wValue, vhub->regs + AST_VHUB_CONF);
drivers/usb/gadget/udc/aspeed-vhub/hub.c
491
writel(reg, vhub->regs + AST_VHUB_EP1_STS_CHG);
drivers/usb/gadget/udc/aspeed-vhub/hub.c
538
writel(reg, vhub->regs + AST_VHUB_CTRL);
drivers/usb/gadget/udc/aspeed-vhub/hub.c
897
writel(0, vhub->regs + AST_VHUB_CONF);
drivers/usb/gadget/udc/aspeed-vhub/hub.c
898
writel(0, vhub->regs + AST_VHUB_EP0_CTRL);
drivers/usb/gadget/udc/aspeed-vhub/hub.c
899
writel(VHUB_EP1_CTRL_RESET_TOGGLE |
drivers/usb/gadget/udc/aspeed-vhub/hub.c
902
writel(0, vhub->regs + AST_VHUB_EP1_STS_CHG);
drivers/usb/gadget/udc/aspeed_udc.c
272
writel((val), (udc)->reg + (offset))
drivers/usb/gadget/udc/aspeed_udc.c
277
writel((val), (ep)->ep_reg + (reg))
drivers/usb/gadget/udc/bdc/bdc.h
465
writel(value, base + offset);
drivers/usb/gadget/udc/cdns2/cdns2-ep0.c
486
writel(ep_sts_reg, &pdev->adma_regs->ep_sts);
drivers/usb/gadget/udc/cdns2/cdns2-ep0.c
634
writel(DMA_EP_CFG_ENABLE, &pdev->adma_regs->ep_cfg);
drivers/usb/gadget/udc/cdns2/cdns2-ep0.c
638
writel(DMA_EP_CFG_ENABLE, &pdev->adma_regs->ep_cfg);
drivers/usb/gadget/udc/cdns2/cdns2-ep0.c
641
writel(DMA_EP_IEN_EP_OUT0 | DMA_EP_IEN_EP_IN0,
drivers/usb/gadget/udc/cdns2/cdns2-ep0.c
67
writel(0, &pdev->ep0_regs->rxbc);
drivers/usb/gadget/udc/cdns2/cdns2-ep0.c
71
writel(DMA_EP_STS_TRBERR, ®s->ep_sts);
drivers/usb/gadget/udc/cdns2/cdns2-ep0.c
72
writel(pep->ring.dma, ®s->ep_traddr);
drivers/usb/gadget/udc/cdns2/cdns2-ep0.c
76
writel(DMA_EP_CMD_DRDY, ®s->ep_cmd);
drivers/usb/gadget/udc/cdns2/cdns2-gadget.c
1064
writel(DMA_EP_CMD_DRDY, &pdev->adma_regs->ep_cmd);
drivers/usb/gadget/udc/cdns2/cdns2-gadget.c
1085
writel(ep_sts_reg, &pdev->adma_regs->ep_sts);
drivers/usb/gadget/udc/cdns2/cdns2-gadget.c
1110
writel(DMA_EP_CMD_DFLUSH, &pep->pdev->adma_regs->ep_cmd);
drivers/usb/gadget/udc/cdns2/cdns2-gadget.c
1188
writel(0, &pdev->adma_regs->ep_ien);
drivers/usb/gadget/udc/cdns2/cdns2-gadget.c
1191
writel(0, &pdev->adma_regs->ep_sts);
drivers/usb/gadget/udc/cdns2/cdns2-gadget.c
1205
writel(~0, &pdev->adma_regs->ep_ien);
drivers/usb/gadget/udc/cdns2/cdns2-gadget.c
1330
writel(~0, &pdev->adma_regs->ep_ien);
drivers/usb/gadget/udc/cdns2/cdns2-gadget.c
1381
writel(tx_offset,
drivers/usb/gadget/udc/cdns2/cdns2-gadget.c
1400
writel(rx_offset,
drivers/usb/gadget/udc/cdns2/cdns2-gadget.c
1479
writel(DMA_EP_CMD_EPRST | DMA_EP_CMD_DFLUSH, &pdev->adma_regs->ep_cmd);
drivers/usb/gadget/udc/cdns2/cdns2-gadget.c
1489
writel(DMA_EP_STS_TRBERR | DMA_EP_STS_ISOERR, &pdev->adma_regs->ep_sts_en);
drivers/usb/gadget/udc/cdns2/cdns2-gadget.c
1492
writel(DMA_EP_CFG_ENABLE, &pdev->adma_regs->ep_cfg);
drivers/usb/gadget/udc/cdns2/cdns2-gadget.c
1601
writel(pep->ring.dma, &pdev->adma_regs->ep_traddr);
drivers/usb/gadget/udc/cdns2/cdns2-gadget.c
161
writel(DMA_EP_CMD_DFLUSH, &pdev->adma_regs->ep_cmd);
drivers/usb/gadget/udc/cdns2/cdns2-gadget.c
1645
writel(DMA_EP_CMD_EPRST, &pdev->adma_regs->ep_cmd);
drivers/usb/gadget/udc/cdns2/cdns2-gadget.c
1789
writel(DMA_EP_CMD_DFLUSH, &pep->pdev->adma_regs->ep_cmd);
drivers/usb/gadget/udc/cdns2/cdns2-gadget.c
2050
writel(~0x0, &pdev->adma_regs->ep_ien);
drivers/usb/gadget/udc/cdns2/cdns2-gadget.c
2054
writel(DMA_CONF_DMULT, &pdev->adma_regs->conf);
drivers/usb/gadget/udc/cdns2/cdns2-gadget.c
2143
writel(DMA_EP_CMD_EPRST, &pdev->adma_regs->ep_cmd);
drivers/usb/gadget/udc/cdns2/cdns2-gadget.c
2389
writel(0, &pdev->adma_regs->ep_ien);
drivers/usb/gadget/udc/cdns2/cdns2-gadget.c
47
writel(mask, ptr);
drivers/usb/gadget/udc/cdns2/cdns2-gadget.c
58
writel(mask, ptr);
drivers/usb/gadget/udc/cdns2/cdns2-gadget.c
700
writel(DMA_EP_STS_TRBERR | DMA_EP_STS_DESCMIS,
drivers/usb/gadget/udc/cdns2/cdns2-gadget.c
702
writel(DMA_EP_CMD_DRDY, &pdev->adma_regs->ep_cmd);
drivers/usb/gadget/udc/cdns2/cdns2-gadget.c
705
writel(DMA_EP_STS_TRBERR, &pdev->adma_regs->ep_sts);
drivers/usb/gadget/udc/cdns2/cdns2-gadget.c
706
writel(DMA_EP_CMD_DRDY, &pdev->adma_regs->ep_cmd);
drivers/usb/gadget/udc/cdns2/cdns2-gadget.c
724
writel(pep->ring.dma + pep->ring.dequeue,
drivers/usb/gadget/udc/cdns2/cdns2-gadget.c
755
writel(pep->ring.dma + (TRBS_PER_SEGMENT * TRB_SIZE),
drivers/usb/gadget/udc/cdns2/cdns2-gadget.c
97
writel(ep, &pdev->adma_regs->ep_sel);
drivers/usb/gadget/udc/fsl_udc_core.c
142
#define fsl_writel(val32, addr) writel(val32, addr)
drivers/usb/gadget/udc/goku_udc.c
1299
writel(0, ®s->power_detect);
drivers/usb/gadget/udc/goku_udc.c
1300
writel(0, ®s->int_enable);
drivers/usb/gadget/udc/goku_udc.c
1308
writel(PW_RESETB, ®s->power_detect);
drivers/usb/gadget/udc/goku_udc.c
1324
writel( G_REQMODE_SET_INTF | G_REQMODE_GET_INTF
drivers/usb/gadget/udc/goku_udc.c
1335
writel(0, ®s->descriptors[i]);
drivers/usb/gadget/udc/goku_udc.c
1336
writel(0, ®s->UsbReady);
drivers/usb/gadget/udc/goku_udc.c
1339
writel(PW_RESETB | PW_PULLUP, ®s->power_detect);
drivers/usb/gadget/udc/goku_udc.c
1341
writel(dev->int_enable, &dev->regs->int_enable);
drivers/usb/gadget/udc/goku_udc.c
1355
writel(dev->int_enable, &dev->regs->int_enable);
drivers/usb/gadget/udc/goku_udc.c
1434
writel(0, ®s->SetupRecv);
drivers/usb/gadget/udc/goku_udc.c
1442
writel(ICONTROL_STATUSNAK, &dev->regs->IntControl);
drivers/usb/gadget/udc/goku_udc.c
1475
writel(~(1<<0), ®s->EOP);
drivers/usb/gadget/udc/goku_udc.c
1531
writel(~irqbit, ®s->int_status); \
drivers/usb/gadget/udc/goku_udc.c
1563
writel(~stat, ®s->int_status);
drivers/usb/gadget/udc/goku_udc.c
1573
writel(dev->int_enable, &dev->regs->int_enable);
drivers/usb/gadget/udc/goku_udc.c
1638
writel(~(1<<0), ®s->EOP);
drivers/usb/gadget/udc/goku_udc.c
171
writel(tmp, ®s->EPxSingle);
drivers/usb/gadget/udc/goku_udc.c
175
writel(tmp, ®s->EPxBCS);
drivers/usb/gadget/udc/goku_udc.c
177
writel(mode, ep->reg_mode);
drivers/usb/gadget/udc/goku_udc.c
207
writel(dev->int_enable, ®s->int_enable);
drivers/usb/gadget/udc/goku_udc.c
215
writel(tmp, &r->EPxSingle);
drivers/usb/gadget/udc/goku_udc.c
219
writel(tmp, &r->EPxBCS);
drivers/usb/gadget/udc/goku_udc.c
233
writel(master, ®s->dma_master);
drivers/usb/gadget/udc/goku_udc.c
344
writel(*buf++, fifo);
drivers/usb/gadget/udc/goku_udc.c
371
writel(~INT_EPxDATASET(ep->num), &dev->regs->int_status);
drivers/usb/gadget/udc/goku_udc.c
377
writel(~(1<<ep->num), &dev->regs->EOP);
drivers/usb/gadget/udc/goku_udc.c
427
writel(~INT_EPxDATASET(ep->num), ®s->int_status);
drivers/usb/gadget/udc/goku_udc.c
479
writel(ep->dev->configured
drivers/usb/gadget/udc/goku_udc.c
484
writel(~(1<<0), ®s->EOP);
drivers/usb/gadget/udc/goku_udc.c
507
writel(dev->int_enable, ®s->int_enable);
drivers/usb/gadget/udc/goku_udc.c
516
writel(dev->int_enable, ®s->int_enable);
drivers/usb/gadget/udc/goku_udc.c
551
writel(end, ®s->in_dma_end);
drivers/usb/gadget/udc/goku_udc.c
552
writel(start, ®s->in_dma_start);
drivers/usb/gadget/udc/goku_udc.c
576
writel(end, ®s->out_dma_end);
drivers/usb/gadget/udc/goku_udc.c
577
writel(start, ®s->out_dma_start);
drivers/usb/gadget/udc/goku_udc.c
585
writel(master, ®s->dma_master);
drivers/usb/gadget/udc/goku_udc.c
586
writel(ep->dev->int_enable, ®s->int_enable);
drivers/usb/gadget/udc/goku_udc.c
604
writel(dev->int_enable, ®s->int_enable);
drivers/usb/gadget/udc/goku_udc.c
665
writel(curr, ®s->in_dma_end);
drivers/usb/gadget/udc/goku_udc.c
666
writel(curr, ®s->in_dma_start);
drivers/usb/gadget/udc/goku_udc.c
670
writel(master, ®s->dma_master);
drivers/usb/gadget/udc/goku_udc.c
680
writel(curr, ®s->out_dma_end);
drivers/usb/gadget/udc/goku_udc.c
681
writel(curr, ®s->out_dma_start);
drivers/usb/gadget/udc/goku_udc.c
685
writel(master, ®s->dma_master);
drivers/usb/gadget/udc/goku_udc.c
86
writel(COMMAND_EP(epnum) | command, ®s->Command);
drivers/usb/gadget/udc/lpc32xx_udc.c
1040
writel((1 << i), USBD_EOTINTCLR(udc->udp_baseaddr));
drivers/usb/gadget/udc/lpc32xx_udc.c
1041
writel((1 << i), USBD_NDDRTINTCLR(udc->udp_baseaddr));
drivers/usb/gadget/udc/lpc32xx_udc.c
1042
writel((1 << i), USBD_SYSERRTINTCLR(udc->udp_baseaddr));
drivers/usb/gadget/udc/lpc32xx_udc.c
1043
writel((1 << i), USBD_DMARCLR(udc->udp_baseaddr));
drivers/usb/gadget/udc/lpc32xx_udc.c
1047
writel(0, USBD_DMAINTEN(udc->udp_baseaddr));
drivers/usb/gadget/udc/lpc32xx_udc.c
1049
writel(0, USBD_UDCAH(udc->udp_baseaddr));
drivers/usb/gadget/udc/lpc32xx_udc.c
1064
writel(USBD_EP_FAST, USBD_DEVINTPRI(udc->udp_baseaddr));
drivers/usb/gadget/udc/lpc32xx_udc.c
1065
writel(0xFFFF, USBD_EPINTPRI(udc->udp_baseaddr));
drivers/usb/gadget/udc/lpc32xx_udc.c
1068
writel(0x3FF, USBD_DEVINTCLR(udc->udp_baseaddr));
drivers/usb/gadget/udc/lpc32xx_udc.c
1071
writel(udc->udca_p_base, USBD_UDCAH(udc->udp_baseaddr));
drivers/usb/gadget/udc/lpc32xx_udc.c
1094
writel((USBD_SYS_ERR_INT | USBD_EOT_INT),
drivers/usb/gadget/udc/lpc32xx_udc.c
1210
writel(hwrep, USBD_CTRL(udc->udp_baseaddr));
drivers/usb/gadget/udc/lpc32xx_udc.c
1227
writel(((hwep & 0x1E) << 1), USBD_CTRL(udc->udp_baseaddr));
drivers/usb/gadget/udc/lpc32xx_udc.c
1250
writel(*p32++, USBD_TXDATA(udc->udp_baseaddr));
drivers/usb/gadget/udc/lpc32xx_udc.c
1259
writel(tmp, USBD_TXDATA(udc->udp_baseaddr));
drivers/usb/gadget/udc/lpc32xx_udc.c
1275
writel(tmp, USBD_TXDATA(udc->udp_baseaddr));
drivers/usb/gadget/udc/lpc32xx_udc.c
1287
writel(tmp, USBD_TXDATA(udc->udp_baseaddr));
drivers/usb/gadget/udc/lpc32xx_udc.c
1297
writel(tmp, USBD_TXDATA(udc->udp_baseaddr));
drivers/usb/gadget/udc/lpc32xx_udc.c
1315
writel(hwwep, USBD_CTRL(udc->udp_baseaddr));
drivers/usb/gadget/udc/lpc32xx_udc.c
1317
writel(bytes, USBD_TXPLEN(udc->udp_baseaddr));
drivers/usb/gadget/udc/lpc32xx_udc.c
1321
writel(0, USBD_TXDATA(udc->udp_baseaddr));
drivers/usb/gadget/udc/lpc32xx_udc.c
1325
writel(((hwep & 0x1E) << 1), USBD_CTRL(udc->udp_baseaddr));
drivers/usb/gadget/udc/lpc32xx_udc.c
1576
writel(1 << ep->hwep_num, USBD_EOTINTCLR(udc->udp_baseaddr));
drivers/usb/gadget/udc/lpc32xx_udc.c
1577
writel(1 << ep->hwep_num, USBD_NDDRTINTCLR(udc->udp_baseaddr));
drivers/usb/gadget/udc/lpc32xx_udc.c
1578
writel(1 << ep->hwep_num, USBD_SYSERRTINTCLR(udc->udp_baseaddr));
drivers/usb/gadget/udc/lpc32xx_udc.c
1579
writel(1 << ep->hwep_num, USBD_DMARCLR(udc->udp_baseaddr));
drivers/usb/gadget/udc/lpc32xx_udc.c
1688
writel(1 << ep->hwep_num, USBD_EOTINTCLR(udc->udp_baseaddr));
drivers/usb/gadget/udc/lpc32xx_udc.c
1689
writel(1 << ep->hwep_num, USBD_NDDRTINTCLR(udc->udp_baseaddr));
drivers/usb/gadget/udc/lpc32xx_udc.c
1690
writel(1 << ep->hwep_num, USBD_SYSERRTINTCLR(udc->udp_baseaddr));
drivers/usb/gadget/udc/lpc32xx_udc.c
1691
writel(1 << ep->hwep_num, USBD_DMARCLR(udc->udp_baseaddr));
drivers/usb/gadget/udc/lpc32xx_udc.c
1997
writel((1 << ep->hwep_num), USBD_EOTINTCLR(udc->udp_baseaddr));
drivers/usb/gadget/udc/lpc32xx_udc.c
1998
writel((1 << ep->hwep_num), USBD_NDDRTINTCLR(udc->udp_baseaddr));
drivers/usb/gadget/udc/lpc32xx_udc.c
2003
writel((1 << ep->hwep_num),
drivers/usb/gadget/udc/lpc32xx_udc.c
2730
writel(devstat, USBD_DEVINTCLR(udc->udp_baseaddr));
drivers/usb/gadget/udc/lpc32xx_udc.c
2766
writel(USBD_EP_FAST, USBD_DEVINTCLR(udc->udp_baseaddr));
drivers/usb/gadget/udc/lpc32xx_udc.c
703
writel(USBD_CCEMPTY, USBD_DEVINTCLR(udc->udp_baseaddr));
drivers/usb/gadget/udc/lpc32xx_udc.c
706
writel(cmd, USBD_CMDCODE(udc->udp_baseaddr));
drivers/usb/gadget/udc/lpc32xx_udc.c
735
writel((USBD_CDFULL | USBD_CCEMPTY),
drivers/usb/gadget/udc/lpc32xx_udc.c
760
writel(udc->enabled_devints, USBD_DEVINTEN(udc->udp_baseaddr));
drivers/usb/gadget/udc/lpc32xx_udc.c
767
writel(udc->enabled_devints, USBD_DEVINTEN(udc->udp_baseaddr));
drivers/usb/gadget/udc/lpc32xx_udc.c
773
writel(mask, USBD_DEVINTCLR(udc->udp_baseaddr));
drivers/usb/gadget/udc/lpc32xx_udc.c
785
writel(udc->enabled_hwepints, USBD_EPINTEN(udc->udp_baseaddr));
drivers/usb/gadget/udc/lpc32xx_udc.c
792
writel(udc->enabled_hwepints, USBD_EPINTEN(udc->udp_baseaddr));
drivers/usb/gadget/udc/lpc32xx_udc.c
798
writel((1 << hwep), USBD_EPINTCLR(udc->udp_baseaddr));
drivers/usb/gadget/udc/lpc32xx_udc.c
804
writel((1 << hwep), USBD_EPDMAEN(udc->udp_baseaddr));
drivers/usb/gadget/udc/lpc32xx_udc.c
810
writel((1 << hwep), USBD_EPDMADIS(udc->udp_baseaddr));
drivers/usb/gadget/udc/lpc32xx_udc.c
826
writel(USBD_EP_RLZED, USBD_DEVINTCLR(udc->udp_baseaddr));
drivers/usb/gadget/udc/lpc32xx_udc.c
827
writel(hwep, USBD_EPIND(udc->udp_baseaddr));
drivers/usb/gadget/udc/lpc32xx_udc.c
829
writel(udc->realized_eps, USBD_REEP(udc->udp_baseaddr));
drivers/usb/gadget/udc/lpc32xx_udc.c
830
writel(maxpacket, USBD_EPMAXPSIZE(udc->udp_baseaddr));
drivers/usb/gadget/udc/lpc32xx_udc.c
839
writel(USBD_EP_RLZED, USBD_DEVINTCLR(udc->udp_baseaddr));
drivers/usb/gadget/udc/lpc32xx_udc.c
846
writel(udc->realized_eps, USBD_REEP(udc->udp_baseaddr));
drivers/usb/gadget/udc/net2280.c
1079
writel(BIT(CLEAR_NAK_OUT_PACKETS),
drivers/usb/gadget/udc/net2280.c
1207
writel(BIT(DMA_ABORT), &ep->dma->dmastat);
drivers/usb/gadget/udc/net2280.c
1306
writel(dmactl, &ep->dma->dmactl);
drivers/usb/gadget/udc/net2280.c
1439
writel(BIT(FIFO_FLUSH), &ep->regs->ep_stat);
drivers/usb/gadget/udc/net2280.c
1489
writel(BIT(GENERATE_RESUME), &dev->usb->usbstat);
drivers/usb/gadget/udc/net2280.c
1515
writel(tmp, &dev->usb->usbctl);
drivers/usb/gadget/udc/net2280.c
1536
writel(tmp | BIT(USB_DETECT_ENABLE), &dev->usb->usbctl);
drivers/usb/gadget/udc/net2280.c
1538
writel(tmp & ~BIT(USB_DETECT_ENABLE), &dev->usb->usbctl);
drivers/usb/gadget/udc/net2280.c
176
writel(tmp, &ep->dev->regs->pciirqenb0);
drivers/usb/gadget/udc/net2280.c
1910
writel((0xffff << PCI_BASE2_RANGE) | mode, &dev->regs->fifoctl);
drivers/usb/gadget/udc/net2280.c
1950
writel(i, &ep->cfg->ep_cfg);
drivers/usb/gadget/udc/net2280.c
1955
writel(0, &dev->dep[i].dep_cfg);
drivers/usb/gadget/udc/net2280.c
1960
writel(((tmp_reg & ~0x1f) | ep_sel), &dev->plregs->pl_ep_ctrl);
drivers/usb/gadget/udc/net2280.c
1969
writel(tmp_reg, &dev->plregs->pl_ep_cfg_4);
drivers/usb/gadget/udc/net2280.c
1972
writel(tmp_reg, &dev->plregs->pl_ep_ctrl);
drivers/usb/gadget/udc/net2280.c
2001
writel(tmp, &dev->ep[i].cfg->ep_cfg);
drivers/usb/gadget/udc/net2280.c
2005
writel(tmp, &dev->dep[1].dep_cfg);
drivers/usb/gadget/udc/net2280.c
2006
writel(tmp, &dev->dep[3].dep_cfg);
drivers/usb/gadget/udc/net2280.c
2007
writel(tmp, &dev->dep[4].dep_cfg);
drivers/usb/gadget/udc/net2280.c
2008
writel(tmp, &dev->dep[5].dep_cfg);
drivers/usb/gadget/udc/net2280.c
2015
writel(((tmp_reg & ~0x1f) | ep_sel),
drivers/usb/gadget/udc/net2280.c
2022
writel(tmp, &dev->plregs->pl_ep_ctrl);
drivers/usb/gadget/udc/net2280.c
2032
writel(tmp, &dev->plregs->pl_ep_cfg_4);
drivers/usb/gadget/udc/net2280.c
2036
writel(tmp, &dev->plregs->pl_ep_ctrl);
drivers/usb/gadget/udc/net2280.c
2067
writel(0, &dev->usb->stdrsp);
drivers/usb/gadget/udc/net2280.c
2068
writel(0, &dev->regs->pciirqenb0);
drivers/usb/gadget/udc/net2280.c
2069
writel(0, &dev->regs->pciirqenb1);
drivers/usb/gadget/udc/net2280.c
2078
writel(~0, &dev->regs->irqstat0),
drivers/usb/gadget/udc/net2280.c
2079
writel(~(u32)BIT(SUSPEND_REQUEST_INTERRUPT), &dev->regs->irqstat1),
drivers/usb/gadget/udc/net2280.c
2087
writel(tmp, &dev->regs->devinit);
drivers/usb/gadget/udc/net2280.c
2104
writel(0, &dev->usb->stdrsp);
drivers/usb/gadget/udc/net2280.c
2105
writel(0, &dev->regs->pciirqenb0);
drivers/usb/gadget/udc/net2280.c
2106
writel(0, &dev->regs->pciirqenb1);
drivers/usb/gadget/udc/net2280.c
2118
writel(BIT(DMA_ABORT), &dma->dmastat);
drivers/usb/gadget/udc/net2280.c
2119
writel(0, &dma->dmactl);
drivers/usb/gadget/udc/net2280.c
2123
writel(~0, &dev->regs->irqstat0), writel(~0, &dev->regs->irqstat1);
drivers/usb/gadget/udc/net2280.c
2133
writel(tmp, &dev->regs->devinit);
drivers/usb/gadget/udc/net2280.c
2185
writel(EP_DONTUSE, &dev->dep[tmp].dep_cfg);
drivers/usb/gadget/udc/net2280.c
2217
writel(ne[i], &ep->cfg->ep_cfg);
drivers/usb/gadget/udc/net2280.c
2239
writel(tmp, &dev->usb_ext->usbctl2);
drivers/usb/gadget/udc/net2280.c
2246
writel(val, &dev->llregs->ll_lfps_5);
drivers/usb/gadget/udc/net2280.c
2251
writel(val, &dev->llregs->ll_lfps_6);
drivers/usb/gadget/udc/net2280.c
2261
writel(val, &dev->llregs->ll_tsn_counters_2);
drivers/usb/gadget/udc/net2280.c
2266
writel(val, &dev->llregs->ll_tsn_counters_3);
drivers/usb/gadget/udc/net2280.c
2275
writel((val & 0xffff0000) | LFPS_TIMERS_2_WORKAROUND_VALUE,
drivers/usb/gadget/udc/net2280.c
2288
writel(val, &dev->llregs->ll_tsn_chicken_bit);
drivers/usb/gadget/udc/net2280.c
2293
writel(0x0D, &dev->dep[0].dep_cfg);
drivers/usb/gadget/udc/net2280.c
2294
writel(0x0D, &dev->dep[1].dep_cfg);
drivers/usb/gadget/udc/net2280.c
2295
writel(0x0E, &dev->dep[2].dep_cfg);
drivers/usb/gadget/udc/net2280.c
2296
writel(0x0E, &dev->dep[3].dep_cfg);
drivers/usb/gadget/udc/net2280.c
2297
writel(0x0F, &dev->dep[4].dep_cfg);
drivers/usb/gadget/udc/net2280.c
2298
writel(0x0C, &dev->dep[5].dep_cfg);
drivers/usb/gadget/udc/net2280.c
2310
writel(BIT(CLEAR_EP_HIDE_STATUS_PHASE) |
drivers/usb/gadget/udc/net2280.c
2321
writel(BIT(SET_TEST_MODE) |
drivers/usb/gadget/udc/net2280.c
2327
writel(BIT(USB_ROOT_PORT_WAKEUP_ENABLE) |
drivers/usb/gadget/udc/net2280.c
2335
writel(BIT(SETUP_PACKET_INTERRUPT_ENABLE) |
drivers/usb/gadget/udc/net2280.c
2338
writel(BIT(PCI_INTERRUPT_ENABLE) |
drivers/usb/gadget/udc/net2280.c
2355
writel(BIT(CLEAR_NAK_OUT_PACKETS_MODE) |
drivers/usb/gadget/udc/net2280.c
2365
writel(BIT(SET_ISOCHRONOUS_DELAY) |
drivers/usb/gadget/udc/net2280.c
2373
writel(BIT(USB_ROOT_PORT_WAKEUP_ENABLE) |
drivers/usb/gadget/udc/net2280.c
2379
writel(BIT(SETUP_PACKET_INTERRUPT_ENABLE) |
drivers/usb/gadget/udc/net2280.c
2382
writel(BIT(PCI_INTERRUPT_ENABLE) |
drivers/usb/gadget/udc/net2280.c
243
writel(BIT(FIFO_FLUSH), &ep->regs->ep_stat);
drivers/usb/gadget/udc/net2280.c
2537
writel(t & ~BIT(NAK_OUT_PACKETS), &ep->regs->ep_stat);
drivers/usb/gadget/udc/net2280.c
2540
writel(t, &ep->regs->ep_stat);
drivers/usb/gadget/udc/net2280.c
264
writel(BIT(CLEAR_NAK_OUT_PACKETS_MODE),
drivers/usb/gadget/udc/net2280.c
2667
writel(BIT(DMA_ABORT), &ep->dma->dmastat);
drivers/usb/gadget/udc/net2280.c
2856
writel(val, &dev->plregs->pl_ep_ctrl);
drivers/usb/gadget/udc/net2280.c
2858
writel(val, &dev->plregs->pl_ep_ctrl);
drivers/usb/gadget/udc/net2280.c
2887
writel(0, &dev->epregs[0].ep_irqenb);
drivers/usb/gadget/udc/net2280.c
2889
writel((__force u32) status, &dev->epregs[0].ep_data);
drivers/usb/gadget/udc/net2280.c
2899
writel(0, &dev->epregs[0].ep_irqenb);
drivers/usb/gadget/udc/net2280.c
2901
writel((__force u32) status, &dev->epregs[0].ep_data);
drivers/usb/gadget/udc/net2280.c
2917
writel(readl(&dev->usb_ext->usbctl2) &
drivers/usb/gadget/udc/net2280.c
2925
writel(readl(&dev->usb_ext->usbctl2) &
drivers/usb/gadget/udc/net2280.c
2933
writel(readl(&dev->usb_ext->usbctl2) &
drivers/usb/gadget/udc/net2280.c
2945
writel(readl(&dev->usb->usbctl) &
drivers/usb/gadget/udc/net2280.c
2983
writel(readl(&dev->usb_ext->usbctl2) |
drivers/usb/gadget/udc/net2280.c
2991
writel(readl(&dev->usb_ext->usbctl2) |
drivers/usb/gadget/udc/net2280.c
2999
writel(readl(&dev->usb_ext->usbctl2) |
drivers/usb/gadget/udc/net2280.c
3011
writel(readl(&dev->usb->usbctl) |
drivers/usb/gadget/udc/net2280.c
307
writel(BIT(SET_NAK_OUT_PACKETS), &ep->regs->ep_rsp);
drivers/usb/gadget/udc/net2280.c
312
writel(BIT(CLEAR_NAK_OUT_PACKETS) |
drivers/usb/gadget/udc/net2280.c
3152
writel(tmp | BIT(TIMEOUT) |
drivers/usb/gadget/udc/net2280.c
318
writel(tmp, &ep->cfg->ep_cfg);
drivers/usb/gadget/udc/net2280.c
3182
writel(BIT(SETUP_PACKET_INTERRUPT), &dev->regs->irqstat0);
drivers/usb/gadget/udc/net2280.c
3200
writel(scratch, &dev->epregs[0].ep_irqenb);
drivers/usb/gadget/udc/net2280.c
3230
writel(0, &dev->epregs[0].ep_irqenb);
drivers/usb/gadget/udc/net2280.c
3232
writel((__force u32)status, &dev->epregs[0].ep_data);
drivers/usb/gadget/udc/net2280.c
328
writel(tmp, &ep->regs->ep_irqenb);
drivers/usb/gadget/udc/net2280.c
332
writel(tmp, &dev->regs->pciirqenb1);
drivers/usb/gadget/udc/net2280.c
3382
writel(tmp, &dev->regs->irqstat1);
drivers/usb/gadget/udc/net2280.c
340
writel(tmp, &ep->regs->ep_irqenb);
drivers/usb/gadget/udc/net2280.c
3426
writel(tmp, &dev->regs->irqstat1);
drivers/usb/gadget/udc/net2280.c
3444
writel(stat, &dev->regs->irqstat1);
drivers/usb/gadget/udc/net2280.c
3482
writel(tmp, &dma->dmastat);
drivers/usb/gadget/udc/net2280.c
3557
writel(pciirqenb1 & 0x7FFFFFFF, &dev->regs->pciirqenb1);
drivers/usb/gadget/udc/net2280.c
3558
writel(pciirqenb1, &dev->regs->pciirqenb1);
drivers/usb/gadget/udc/net2280.c
3701
writel(0, &dev->usb->usbctl);
drivers/usb/gadget/udc/net2280.c
3708
writel(0, &dev->usb->usbctl);
drivers/usb/gadget/udc/net2280.c
3761
writel(BIT(DMA_MEMORY_WRITE_AND_INVALIDATE_ENABLE) |
drivers/usb/gadget/udc/net2280.c
3809
writel(0, &dev->regs->pciirqenb0);
drivers/usb/gadget/udc/net2280.c
3810
writel(0, &dev->regs->pciirqenb1);
drivers/usb/gadget/udc/net2280.c
3813
writel(0, &dev->usb->usbctl);
drivers/usb/gadget/udc/net2280.c
391
writel(0, &ep->dma->dmactl);
drivers/usb/gadget/udc/net2280.c
392
writel(BIT(DMA_SCATTER_GATHER_DONE_INTERRUPT) |
drivers/usb/gadget/udc/net2280.c
399
writel(tmp, ®s->pciirqenb0);
drivers/usb/gadget/udc/net2280.c
403
writel(tmp, ®s->pciirqenb1);
drivers/usb/gadget/udc/net2280.c
405
writel(0, &ep->regs->ep_irqenb);
drivers/usb/gadget/udc/net2280.c
427
writel(tmp, &ep->regs->ep_rsp);
drivers/usb/gadget/udc/net2280.c
436
writel(tmp | BIT(TIMEOUT) |
drivers/usb/gadget/udc/net2280.c
467
writel(0, &ep->dma->dmactl);
drivers/usb/gadget/udc/net2280.c
468
writel(BIT(DMA_ABORT_DONE_INTERRUPT) |
drivers/usb/gadget/udc/net2280.c
479
writel(0x5a, &ep->dma->dmastat);
drivers/usb/gadget/udc/net2280.c
484
writel(tmp, ®s->pciirqenb0);
drivers/usb/gadget/udc/net2280.c
489
writel(tmp, ®s->pciirqenb1);
drivers/usb/gadget/udc/net2280.c
492
writel(0, &ep->regs->ep_irqenb);
drivers/usb/gadget/udc/net2280.c
494
writel(BIT(SHORT_PACKET_OUT_DONE_INTERRUPT) |
drivers/usb/gadget/udc/net2280.c
507
writel(tmp, &ep->cfg->ep_cfg);
drivers/usb/gadget/udc/net2280.c
642
writel(tmp, ®s->ep_data);
drivers/usb/gadget/udc/net2280.c
655
writel(tmp, ®s->ep_data);
drivers/usb/gadget/udc/net2280.c
679
writel(BIT(SET_NAK_OUT_PACKETS), &ep->regs->ep_rsp);
drivers/usb/gadget/udc/net2280.c
682
writel(BIT(DATA_OUT_PING_TOKEN_INTERRUPT) |
drivers/usb/gadget/udc/net2280.c
685
writel(BIT(FIFO_FLUSH), statp);
drivers/usb/gadget/udc/net2280.c
787
writel(BIT(CLEAR_NAK_OUT_PACKETS), &ep->regs->ep_rsp);
drivers/usb/gadget/udc/net2280.c
843
writel(readl(&dma->dmactl) & ~BIT(DMA_ENABLE), &dma->dmactl);
drivers/usb/gadget/udc/net2280.c
855
writel(tmp, &dma->dmacount);
drivers/usb/gadget/udc/net2280.c
856
writel(readl(&dma->dmastat), &dma->dmastat);
drivers/usb/gadget/udc/net2280.c
858
writel(td_dma, &dma->dmadesc);
drivers/usb/gadget/udc/net2280.c
861
writel(dmactl, &dma->dmactl);
drivers/usb/gadget/udc/net2280.c
866
writel(BIT(DMA_START), &dma->dmastat);
drivers/usb/gadget/udc/net2280.c
878
writel(0, &ep->dma->dmactl);
drivers/usb/gadget/udc/net2280.c
883
writel(BIT(SHORT_PACKET_TRANSFERRED_INTERRUPT),
drivers/usb/gadget/udc/net2280.c
888
writel(readl(&dma->dmastat), &dma->dmastat);
drivers/usb/gadget/udc/net2280.c
891
writel(req->req.dma, &dma->dmaaddr);
drivers/usb/gadget/udc/net2280.c
896
writel(BIT(DMA_DONE_INTERRUPT_ENABLE) | tmp,
drivers/usb/gadget/udc/net2280.c
901
writel(BIT(DMA_ENABLE), &dma->dmactl);
drivers/usb/gadget/udc/net2280.c
902
writel(BIT(DMA_START), &dma->dmastat);
drivers/usb/gadget/udc/net2280.h
117
writel(BIT(CLEAR_CONTROL_STATUS_PHASE_HANDSHAKE) |
drivers/usb/gadget/udc/net2280.h
131
writel(BIT(CLEAR_CONTROL_STATUS_PHASE_HANDSHAKE), &ep->regs->ep_rsp);
drivers/usb/gadget/udc/net2280.h
192
writel(BIT(CLEAR_CONTROL_STATUS_PHASE_HANDSHAKE) |
drivers/usb/gadget/udc/net2280.h
202
writel(BIT(CLEAR_ENDPOINT_HALT) |
drivers/usb/gadget/udc/net2280.h
254
writel(BIT(GPIO3_LED_SELECT) |
drivers/usb/gadget/udc/net2280.h
26
writel(index, ®s->idxaddr);
drivers/usb/gadget/udc/net2280.h
283
writel(val, &dev->regs->gpioctl);
drivers/usb/gadget/udc/net2280.h
296
writel(val, &dev->regs->gpioctl);
drivers/usb/gadget/udc/net2280.h
302
writel(readl(&dev->regs->gpioctl) & ~0x0f,
drivers/usb/gadget/udc/net2280.h
34
writel(index, ®s->idxaddr);
drivers/usb/gadget/udc/net2280.h
340
writel(tmp | (count << EP_FIFO_BYTE_COUNT), &ep->cfg->ep_cfg);
drivers/usb/gadget/udc/net2280.h
347
writel(BIT(SET_NAK_OUT_PACKETS), &ep->regs->ep_rsp);
drivers/usb/gadget/udc/net2280.h
35
writel(value, ®s->idxdata);
drivers/usb/gadget/udc/net2280.h
358
writel(BIT(CLEAR_NAK_OUT_PACKETS), &ep->regs->ep_rsp);
drivers/usb/gadget/udc/pxa25x_udc.c
305
writel(val, dev->regs + reg);
drivers/usb/gadget/udc/renesas_usbf.c
433
writel(val, udc->regs + offset);
drivers/usb/gadget/udc/renesas_usbf.c
478
writel(val, ep->regs + offset);
drivers/usb/gadget/udc/renesas_usbf.c
524
writel(val, ep->dma_regs + offset);
drivers/usb/gadget/udc/rzv2m_usb3drd.c
27
writel(val, usb3->reg + offs);
drivers/usb/gadget/udc/rzv2m_usb3drd.c
36
writel(val, usb3->reg + offs);
drivers/usb/gadget/udc/snps_udc_core.c
1043
writel(tmp, &dev->regs->ctl);
drivers/usb/gadget/udc/snps_udc_core.c
1106
writel(tmp, &dev->regs->ctl);
drivers/usb/gadget/udc/snps_udc_core.c
1114
writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
drivers/usb/gadget/udc/snps_udc_core.c
1145
writel(tmp, &dev->regs->ctl);
drivers/usb/gadget/udc/snps_udc_core.c
1160
writel(req->td_phys, &ep->regs->desptr);
drivers/usb/gadget/udc/snps_udc_core.c
1166
writel(tmp, &ep->regs->ctl);
drivers/usb/gadget/udc/snps_udc_core.c
1175
writel(tmp, &dev->regs->ep_irqmsk);
drivers/usb/gadget/udc/snps_udc_core.c
1181
writel(tmp, &dev->regs->ep_irqmsk);
drivers/usb/gadget/udc/snps_udc_core.c
1277
writel(tmp & AMD_UNMASK_BIT(UDC_DEVCTL_RDE),
drivers/usb/gadget/udc/snps_udc_core.c
1289
writel(ep->bna_dummy_req->td_phys,
drivers/usb/gadget/udc/snps_udc_core.c
1292
writel(tmp, &udc->regs->ctl);
drivers/usb/gadget/udc/snps_udc_core.c
1335
writel(tmp, &ep->regs->ctl);
drivers/usb/gadget/udc/snps_udc_core.c
1357
writel(tmp, &ep->regs->ctl);
drivers/usb/gadget/udc/snps_udc_core.c
1401
writel(tmp, &dev->regs->ctl);
drivers/usb/gadget/udc/snps_udc_core.c
1403
writel(tmp, &dev->regs->ctl);
drivers/usb/gadget/udc/snps_udc_core.c
1475
writel(tmp, &dev->regs->ctl);
drivers/usb/gadget/udc/snps_udc_core.c
1484
writel(tmp, &dev->regs->cfg);
drivers/usb/gadget/udc/snps_udc_core.c
1515
writel(tmp, &dev->regs->cfg);
drivers/usb/gadget/udc/snps_udc_core.c
1579
writel(reg, &dev->ep[tmp].regs->ctl);
drivers/usb/gadget/udc/snps_udc_core.c
1674
writel(tmp, &dev->regs->cfg);
drivers/usb/gadget/udc/snps_udc_core.c
1689
writel(UDC_EPINT_MSK_DISABLE_ALL, &dev->regs->ep_irqsts);
drivers/usb/gadget/udc/snps_udc_core.c
1691
writel(UDC_DEV_MSK_DISABLE, &dev->regs->irqsts);
drivers/usb/gadget/udc/snps_udc_core.c
1698
writel(AMD_BIT(UDC_DEVCFG_SOFTRESET), &dev->regs->cfg);
drivers/usb/gadget/udc/snps_udc_core.c
1720
writel(tmp, &udc->regs->ctl);
drivers/usb/gadget/udc/snps_udc_core.c
1777
writel(tmp, &ep->regs->ctl);
drivers/usb/gadget/udc/snps_udc_core.c
1828
writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
drivers/usb/gadget/udc/snps_udc_core.c
1842
writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->bufin_framenum);
drivers/usb/gadget/udc/snps_udc_core.c
1852
writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->bufout_maxpkt);
drivers/usb/gadget/udc/snps_udc_core.c
1862
writel(tmp, &dev->ep[UDC_EP0OUT_IX].regs->bufout_maxpkt);
drivers/usb/gadget/udc/snps_udc_core.c
1872
writel(tmp, &dev->csr->ne[0]);
drivers/usb/gadget/udc/snps_udc_core.c
1878
writel(dev->ep[UDC_EP0OUT_IX].td_stp_dma,
drivers/usb/gadget/udc/snps_udc_core.c
1880
writel(dev->ep[UDC_EP0OUT_IX].td_phys,
drivers/usb/gadget/udc/snps_udc_core.c
1899
writel(tmp, &dev->regs->ctl);
drivers/usb/gadget/udc/snps_udc_core.c
1905
writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
drivers/usb/gadget/udc/snps_udc_core.c
1912
writel(tmp, &dev->ep[UDC_EP0OUT_IX].regs->ctl);
drivers/usb/gadget/udc/snps_udc_core.c
1950
writel(tmp, &dev->regs->ctl);
drivers/usb/gadget/udc/snps_udc_core.c
1991
writel(tmp, &dev->regs->ctl);
drivers/usb/gadget/udc/snps_udc_core.c
2010
writel(reg, &dev->ep[tmp].regs->ctl);
drivers/usb/gadget/udc/snps_udc_core.c
2021
writel(reg, &dev->ep[UDC_EP0OUT_IX].regs->ctl);
drivers/usb/gadget/udc/snps_udc_core.c
2076
writel(tmp | AMD_BIT(UDC_EPSTS_BNA), &ep->regs->sts);
drivers/usb/gadget/udc/snps_udc_core.c
2090
writel(tmp | AMD_BIT(UDC_EPSTS_HE), &ep->regs->sts);
drivers/usb/gadget/udc/snps_udc_core.c
2207
writel(req->td_phys,
drivers/usb/gadget/udc/snps_udc_core.c
2220
writel(ep->bna_dummy_req->td_phys,
drivers/usb/gadget/udc/snps_udc_core.c
2264
writel(UDC_EPSTS_OUT_CLEAR, &ep->regs->sts);
drivers/usb/gadget/udc/snps_udc_core.c
2292
writel(epsts, &ep->regs->sts);
drivers/usb/gadget/udc/snps_udc_core.c
230
writel(tmp, &dev->regs->irqmsk);
drivers/usb/gadget/udc/snps_udc_core.c
2304
writel(epsts | AMD_BIT(UDC_EPSTS_HE), &ep->regs->sts);
drivers/usb/gadget/udc/snps_udc_core.c
233
writel(UDC_EPINT_MSK_DISABLE_ALL, &dev->regs->ep_irqmsk);
drivers/usb/gadget/udc/snps_udc_core.c
2338
writel(tmp, &dev->regs->ep_irqmsk);
drivers/usb/gadget/udc/snps_udc_core.c
2389
writel(req->td_phys, &ep->regs->desptr);
drivers/usb/gadget/udc/snps_udc_core.c
2401
writel(tmp, &ep->regs->ctl);
drivers/usb/gadget/udc/snps_udc_core.c
2410
writel(tmp,
drivers/usb/gadget/udc/snps_udc_core.c
2415
writel(epsts, &ep->regs->sts);
drivers/usb/gadget/udc/snps_udc_core.c
2438
writel(AMD_BIT(UDC_EPINT_OUT_EP0), &dev->regs->ep_irqsts);
drivers/usb/gadget/udc/snps_udc_core.c
2444
writel(AMD_BIT(UDC_EPSTS_BNA),
drivers/usb/gadget/udc/snps_udc_core.c
2465
writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
drivers/usb/gadget/udc/snps_udc_core.c
2471
writel(UDC_EPSTS_OUT_CLEAR,
drivers/usb/gadget/udc/snps_udc_core.c
2500
writel(ep->bna_dummy_req->td_phys,
drivers/usb/gadget/udc/snps_udc_core.c
251
writel(tmp, &dev->regs->ep_irqmsk);
drivers/usb/gadget/udc/snps_udc_core.c
2551
writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
drivers/usb/gadget/udc/snps_udc_core.c
2558
writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
drivers/usb/gadget/udc/snps_udc_core.c
2567
writel(tmp, &dev->ep[UDC_EP0OUT_IX].regs->ctl);
drivers/usb/gadget/udc/snps_udc_core.c
2574
writel(UDC_EPSTS_OUT_CLEAR,
drivers/usb/gadget/udc/snps_udc_core.c
2581
writel(UDC_EPSTS_OUT_CLEAR, &dev->ep[UDC_EP0OUT_IX].regs->sts);
drivers/usb/gadget/udc/snps_udc_core.c
2603
writel(dev->ep[UDC_EP0OUT_IX].td_phys,
drivers/usb/gadget/udc/snps_udc_core.c
2650
writel(AMD_BIT(UDC_EPINT_IN_EP0), &dev->regs->ep_irqsts);
drivers/usb/gadget/udc/snps_udc_core.c
2659
writel(AMD_BIT(UDC_EPSTS_TDC),
drivers/usb/gadget/udc/snps_udc_core.c
2668
writel(AMD_BIT(UDC_EPSTS_IN),
drivers/usb/gadget/udc/snps_udc_core.c
2676
writel(tmp, &ep->regs->ctl);
drivers/usb/gadget/udc/snps_udc_core.c
2685
writel(req->td_phys, &ep->regs->desptr);
drivers/usb/gadget/udc/snps_udc_core.c
2697
writel(tmp,
drivers/usb/gadget/udc/snps_udc_core.c
272
writel(tmp, &dev->regs->irqmsk);
drivers/usb/gadget/udc/snps_udc_core.c
2729
writel(AMD_BIT(UDC_EPSTS_IN),
drivers/usb/gadget/udc/snps_udc_core.c
2786
writel(tmp, &dev->csr->ne[udc_csr_epix]);
drivers/usb/gadget/udc/snps_udc_core.c
2792
writel(tmp, &ep->regs->ctl);
drivers/usb/gadget/udc/snps_udc_core.c
2845
writel(tmp, &dev->csr->ne[udc_csr_epix]);
drivers/usb/gadget/udc/snps_udc_core.c
2851
writel(tmp, &ep->regs->ctl);
drivers/usb/gadget/udc/snps_udc_core.c
2901
writel(tmp | AMD_BIT(UDC_DEVCFG_DMARST), &dev->regs->cfg);
drivers/usb/gadget/udc/snps_udc_core.c
2902
writel(tmp, &dev->regs->cfg);
drivers/usb/gadget/udc/snps_udc_core.c
2913
writel(tmp, &dev->regs->irqmsk);
drivers/usb/gadget/udc/snps_udc_core.c
2957
writel(tmp, &dev->regs->irqmsk);
drivers/usb/gadget/udc/snps_udc_core.c
2997
writel(ep_irq, &dev->regs->ep_irqsts);
drivers/usb/gadget/udc/snps_udc_core.c
3013
writel(reg, &dev->regs->irqsts);
drivers/usb/gadget/udc/snps_udc_core.c
3178
writel(reg, &dev->regs->ctl);
drivers/usb/gadget/udc/snps_udc_core.c
350
writel(tmp, &dev->ep[ep->num].regs->ctl);
drivers/usb/gadget/udc/snps_udc_core.c
357
writel(tmp, &dev->ep[ep->num].regs->bufout_maxpkt);
drivers/usb/gadget/udc/snps_udc_core.c
373
writel(tmp, &dev->ep[ep->num].regs->bufin_framenum);
drivers/usb/gadget/udc/snps_udc_core.c
381
writel(tmp, &ep->regs->ctl);
drivers/usb/gadget/udc/snps_udc_core.c
392
writel(tmp, &dev->csr->ne[ep->num - UDC_CSR_EP_OUT_IX_OFS]);
drivers/usb/gadget/udc/snps_udc_core.c
421
writel(tmp, &dev->csr->ne[udc_csr_epix]);
drivers/usb/gadget/udc/snps_udc_core.c
426
writel(tmp, &dev->regs->ep_irqmsk);
drivers/usb/gadget/udc/snps_udc_core.c
435
writel(tmp, &ep->regs->ctl);
drivers/usb/gadget/udc/snps_udc_core.c
460
writel(tmp, &ep->regs->ctl);
drivers/usb/gadget/udc/snps_udc_core.c
466
writel(tmp, ®s->ep_irqmsk);
drivers/usb/gadget/udc/snps_udc_core.c
472
writel(tmp, &ep->regs->ctl);
drivers/usb/gadget/udc/snps_udc_core.c
476
writel(tmp, &ep->regs->sts);
drivers/usb/gadget/udc/snps_udc_core.c
481
writel(tmp, &ep->regs->ctl);
drivers/usb/gadget/udc/snps_udc_core.c
485
writel(0, &ep->regs->desptr);
drivers/usb/gadget/udc/snps_udc_core.c
667
writel(*(buf + i), ep->txfifo);
drivers/usb/gadget/udc/snps_udc_core.c
676
writel(0, &ep->regs->confirm);
drivers/usb/gadget/udc/snps_udc_core.c
948
writel(tmp, &ep->regs->ctl);
drivers/usb/gadget/udc/snps_udc_plat.c
42
writel(reg, &udc->regs->ctl);
drivers/usb/gadget/udc/snps_udc_plat.c
46
writel(reg, &udc->regs->ctl);
drivers/usb/gadget/udc/tegra-xudc.c
569
writel(val, xudc->fpci + offset);
drivers/usb/gadget/udc/tegra-xudc.c
580
writel(val, xudc->ipfs + offset);
drivers/usb/gadget/udc/tegra-xudc.c
591
writel(val, xudc->base + offset);
drivers/usb/host/ehci-atmel.c
160
writel(EHCI_INSNREG08_HSIC_EN, hcd->regs + EHCI_INSNREG(8));
drivers/usb/host/ehci-exynos.c
200
writel(EHCI_INSNREG00_ENABLE_DMA_BURST, EHCI_INSNREG00(hcd->regs));
drivers/usb/host/ehci-exynos.c
272
writel(EHCI_INSNREG00_ENABLE_DMA_BURST, EHCI_INSNREG00(hcd->regs));
drivers/usb/host/ehci-fsl.c
135
writel(PORT_PTS_UTMI, hcd->regs + FSL_SOC_USB_PORTSC1);
drivers/usb/host/ehci-fsl.c
651
writel(PORT_RESET |
drivers/usb/host/ehci-fsl.c
655
writel(PORT_RESET, &ehci->regs->port_status[port]);
drivers/usb/host/ehci-st.c
57
writel(threshold, hcd->regs + AHB2STBUS_INSREG01);
drivers/usb/host/ehci.h
787
writel(val, regs);
drivers/usb/host/ehci.h
792
writel(val, regs);
drivers/usb/host/ohci-at91.c
112
writel(0, ®s->control);
drivers/usb/host/ohci-omap.c
139
writel(OHCI_CTRL_RWC, &ohci->regs->control);
drivers/usb/host/ohci-omap.c
81
writel (RH_PS_PSS, &ohci->regs->roothub.portstatus [port]);
drivers/usb/host/ohci.h
579
writel (val, regs);
drivers/usb/host/ohci.h
581
writel (val, regs);
drivers/usb/host/oxu210hp-hcd.c
1908
writel(cmd, &oxu->regs->command);
drivers/usb/host/oxu210hp-hcd.c
2117
writel(cmd & ~CMD_ASE, &oxu->regs->command);
drivers/usb/host/oxu210hp-hcd.c
2146
writel(cmd, &oxu->regs->command);
drivers/usb/host/oxu210hp-hcd.c
2288
writel(cmd, &oxu->regs->command);
drivers/usb/host/oxu210hp-hcd.c
2314
writel(cmd, &oxu->regs->command);
drivers/usb/host/oxu210hp-hcd.c
2750
writel(PORT_RWC_BITS, &oxu->regs->port_status[port]);
drivers/usb/host/oxu210hp-hcd.c
2856
writel(status, &oxu->regs->status);
drivers/usb/host/oxu210hp-hcd.c
2916
writel(0, &oxu->regs->configured_flag);
drivers/usb/host/oxu210hp-hcd.c
2968
writel(STS_IAA, &oxu->regs->status);
drivers/usb/host/oxu210hp-hcd.c
3104
writel(oxu->periodic_dma, &oxu->regs->frame_list);
drivers/usb/host/oxu210hp-hcd.c
3105
writel((u32) oxu->async->qh_dma, &oxu->regs->async_next);
drivers/usb/host/oxu210hp-hcd.c
3120
writel(0, &oxu->regs->segment);
drivers/usb/host/oxu210hp-hcd.c
3125
writel(oxu->command, &oxu->regs->command);
drivers/usb/host/oxu210hp-hcd.c
3135
writel(FLAG_CF, &oxu->regs->configured_flag);
drivers/usb/host/oxu210hp-hcd.c
3144
writel(INTR_MASK, &oxu->regs->intr_enable); /* Turn On Interrupts */
drivers/usb/host/oxu210hp-hcd.c
3164
writel(0, &oxu->regs->intr_enable);
drivers/usb/host/oxu210hp-hcd.c
3168
writel(0, &oxu->regs->configured_flag);
drivers/usb/host/oxu210hp-hcd.c
3192
writel(0, &oxu->regs->configured_flag);
drivers/usb/host/oxu210hp-hcd.c
3585
writel(temp & ~PORT_PE, status_reg);
drivers/usb/host/oxu210hp-hcd.c
3588
writel((temp & ~PORT_RWC_BITS) | PORT_PEC, status_reg);
drivers/usb/host/oxu210hp-hcd.c
3598
writel(temp | PORT_RESUME, status_reg);
drivers/usb/host/oxu210hp-hcd.c
3608
writel(temp & ~(PORT_RWC_BITS | PORT_POWER),
drivers/usb/host/oxu210hp-hcd.c
3612
writel((temp & ~PORT_RWC_BITS) | PORT_CSC, status_reg);
drivers/usb/host/oxu210hp-hcd.c
3615
writel((temp & ~PORT_RWC_BITS) | PORT_OCC, status_reg);
drivers/usb/host/oxu210hp-hcd.c
3669
writel(temp & ~(PORT_RWC_BITS | PORT_RESUME),
drivers/usb/host/oxu210hp-hcd.c
3691
writel(temp & ~(PORT_RWC_BITS | PORT_RESET),
drivers/usb/host/oxu210hp-hcd.c
3714
writel(temp, status_reg);
drivers/usb/host/oxu210hp-hcd.c
3775
writel(temp | PORT_SUSPEND, status_reg);
drivers/usb/host/oxu210hp-hcd.c
3779
writel(temp | PORT_POWER, status_reg);
drivers/usb/host/oxu210hp-hcd.c
3798
writel(temp, status_reg);
drivers/usb/host/oxu210hp-hcd.c
3813
writel(temp, status_reg);
drivers/usb/host/oxu210hp-hcd.c
3884
writel(t2, reg);
drivers/usb/host/oxu210hp-hcd.c
3899
writel(mask, &oxu->regs->intr_enable);
drivers/usb/host/oxu210hp-hcd.c
3930
writel(0, &oxu->regs->intr_enable);
drivers/usb/host/oxu210hp-hcd.c
3933
writel(0, &oxu->regs->segment);
drivers/usb/host/oxu210hp-hcd.c
3934
writel(oxu->periodic_dma, &oxu->regs->frame_list);
drivers/usb/host/oxu210hp-hcd.c
3935
writel((u32) oxu->async->qh_dma, &oxu->regs->async_next);
drivers/usb/host/oxu210hp-hcd.c
3938
writel(oxu->command, &oxu->regs->command);
drivers/usb/host/oxu210hp-hcd.c
3954
writel(temp, &oxu->regs->port_status[i]);
drivers/usb/host/oxu210hp-hcd.c
3962
writel(temp, &oxu->regs->port_status[i]);
drivers/usb/host/oxu210hp-hcd.c
3976
writel(oxu->command, &oxu->regs->command);
drivers/usb/host/oxu210hp-hcd.c
3983
writel(INTR_MASK, &oxu->regs->intr_enable);
drivers/usb/host/oxu210hp-hcd.c
663
writel(val, base + reg);
drivers/usb/host/oxu210hp-hcd.c
746
writel(0, &oxu->regs->intr_enable);
drivers/usb/host/oxu210hp-hcd.c
753
writel(temp, &oxu->regs->command);
drivers/usb/host/oxu210hp-hcd.c
767
writel(tmp, reg_ptr);
drivers/usb/host/oxu210hp-hcd.c
778
writel(command, &oxu->regs->command);
drivers/usb/host/oxu210hp-hcd.c
813
writel(temp, &oxu->regs->command);
drivers/usb/host/pci-quirks.c
1002
writel(0x3f, op_reg_base + EHCI_USBSTS);
drivers/usb/host/pci-quirks.c
1011
writel(0, op_reg_base + EHCI_USBINTR);
drivers/usb/host/pci-quirks.c
1012
writel(0x3f, op_reg_base + EHCI_USBSTS);
drivers/usb/host/pci-quirks.c
1195
writel(val, base + ext_cap_offset);
drivers/usb/host/pci-quirks.c
1200
writel(val | XHCI_HC_OS_OWNED, base + ext_cap_offset);
drivers/usb/host/pci-quirks.c
1211
writel(val & ~XHCI_HC_BIOS_OWNED, base + ext_cap_offset);
drivers/usb/host/pci-quirks.c
1221
writel(val, base + ext_cap_offset + XHCI_LEGACY_CONTROL_OFFSET);
drivers/usb/host/pci-quirks.c
1245
writel(val, op_reg_base + XHCI_CMD_OFFSET);
drivers/usb/host/pci-quirks.c
791
writel(OHCI_INTR_OC, base + OHCI_INTRENABLE);
drivers/usb/host/pci-quirks.c
792
writel(OHCI_OCR, base + OHCI_CMDSTATUS);
drivers/usb/host/pci-quirks.c
806
writel((u32) ~0, base + OHCI_INTRDISABLE);
drivers/usb/host/pci-quirks.c
809
writel(control & OHCI_CTRL_MASK, base + OHCI_CONTROL);
drivers/usb/host/pci-quirks.c
816
writel(OHCI_HCR, base + OHCI_CMDSTATUS);
drivers/usb/host/pci-quirks.c
826
writel(fminterval, base + OHCI_FMINTERVAL);
drivers/usb/host/pci-quirks.c
936
writel(0, op_reg_base + EHCI_CONFIGFLAG);
drivers/usb/host/pci-quirks.c
998
writel(val, op_reg_base + EHCI_USBCMD);
drivers/usb/host/uhci-hcd.h
615
writel(val, uhci->regs + uhci_aspeed_reg(reg));
drivers/usb/host/uhci-hcd.h
621
writel(val, uhci->regs + reg);
drivers/usb/host/uhci-hcd.h
643
writel(val, uhci->regs + uhci_aspeed_reg(reg));
drivers/usb/host/uhci-hcd.h
671
writel(val, uhci->regs + uhci_aspeed_reg(reg));
drivers/usb/host/xhci-dbgcap.c
1125
writel(dev_info, ptr);
drivers/usb/host/xhci-dbgcap.c
1167
writel(dev_info, ptr);
drivers/usb/host/xhci-dbgcap.c
1208
writel(dev_info, ptr);
drivers/usb/host/xhci-dbgcap.c
1357
writel(dev_info, ptr);
drivers/usb/host/xhci-dbgcap.c
167
writel(dev_info, &dbc->regs->devinfo1);
drivers/usb/host/xhci-dbgcap.c
170
writel(dev_info, &dbc->regs->devinfo2);
drivers/usb/host/xhci-dbgcap.c
331
writel(DBC_DOOR_BELL_TARGET(dep->direction), &dbc->regs->doorbell);
drivers/usb/host/xhci-dbgcap.c
576
writel(dbc->erst.num_entries, &dbc->regs->ersts);
drivers/usb/host/xhci-dbgcap.c
640
writel(0, &dbc->regs->control);
drivers/usb/host/xhci-dbgcap.c
652
writel(ctrl | DBC_CTRL_DBC_ENABLE | DBC_CTRL_PORT_ENABLE,
drivers/usb/host/xhci-dbgcap.c
670
writel(0, &dbc->regs->control);
drivers/usb/host/xhci-dbgcap.c
744
writel(DBC_DOOR_BELL_TARGET(dep->direction),
drivers/usb/host/xhci-dbgcap.c
768
writel(portsc & ~DBC_PORTSC_RESET_CHANGE, &dbc->regs->portsc);
drivers/usb/host/xhci-dbgcap.c
908
writel(portsc, &dbc->regs->portsc);
drivers/usb/host/xhci-dbgcap.c
929
writel(portsc, &dbc->regs->portsc);
drivers/usb/host/xhci-dbgcap.c
943
writel(ctrl, &dbc->regs->control);
drivers/usb/host/xhci-histb.c
60
writel(regval, histb->ctrl + REG_GUSB2PHYCFG0);
drivers/usb/host/xhci-histb.c
75
writel(regval, histb->ctrl + REG_GUSB3PIPECTL0);
drivers/usb/host/xhci-histb.c
78
writel(0x23100000, histb->ctrl + GTXTHRCFG);
drivers/usb/host/xhci-histb.c
79
writel(0x23100000, histb->ctrl + GRXTHRCFG);
drivers/usb/host/xhci-hub.c
1526
writel(temp, &port->port_reg->portpmsc);
drivers/usb/host/xhci-hub.c
1534
writel(temp, &port->port_reg->portpmsc);
drivers/usb/host/xhci-hub.c
688
writel(temp, &port->port_reg->portpmsc);
drivers/usb/host/xhci-mem.c
1837
writel(tmp, &ir->ir_set->erst_size);
drivers/usb/host/xhci-mem.c
2334
writel(erst_size, &ir->ir_set->erst_size);
drivers/usb/host/xhci-mtk.c
151
writel(value, hcd->regs + HFCNTR_CFG);
drivers/usb/host/xhci-mtk.c
156
writel(value, hcd->regs + LS_EOF_CFG);
drivers/usb/host/xhci-mtk.c
161
writel(value, hcd->regs + FS_EOF_CFG);
drivers/usb/host/xhci-mtk.c
166
writel(value, hcd->regs + SS_GEN1_EOF_CFG);
drivers/usb/host/xhci-mtk.c
171
writel(value, hcd->regs + SS_GEN2_EOF_CFG);
drivers/usb/host/xhci-mtk.c
191
writel(value, hcd->regs + HSCH_CFG1);
drivers/usb/host/xhci-mtk.c
217
writel(value, &ippc->ip_pw_ctr1);
drivers/usb/host/xhci-mtk.c
229
writel(value, &ippc->u3_ctrl_p[i]);
drivers/usb/host/xhci-mtk.c
240
writel(value, &ippc->u2_ctrl_p[i]);
drivers/usb/host/xhci-mtk.c
280
writel(value, &ippc->u3_ctrl_p[i]);
drivers/usb/host/xhci-mtk.c
290
writel(value, &ippc->u2_ctrl_p[i]);
drivers/usb/host/xhci-mtk.c
296
writel(value, &ippc->ip_pw_ctr1);
drivers/usb/host/xhci-mtk.c
320
writel(value, &ippc->ip_pw_ctr0);
drivers/usb/host/xhci-mtk.c
324
writel(value, &ippc->ip_pw_ctr0);
drivers/usb/host/xhci-mtk.c
332
writel(value, &ippc->ip_pw_ctr2);
drivers/usb/host/xhci-mvebu.c
29
writel(0, base + USB3_WIN_CTRL(win));
drivers/usb/host/xhci-mvebu.c
30
writel(0, base + USB3_WIN_BASE(win));
drivers/usb/host/xhci-mvebu.c
37
writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) |
drivers/usb/host/xhci-mvebu.c
41
writel((cs->base & 0xffff0000), base + USB3_WIN_BASE(win));
drivers/usb/host/xhci-pci.c
758
writel(val, reg);
drivers/usb/host/xhci-pci.c
766
writel(val, reg);
drivers/usb/host/xhci-pci.c
770
writel(val, reg);
drivers/usb/host/xhci-pci.c
787
writel(val | BIT(28), reg);
drivers/usb/host/xhci-pci.c
797
writel(reg, hcd->regs + SPARSE_CNTL_ENABLE);
drivers/usb/host/xhci-rcar.c
138
writel(temp, regs + RCAR_USB3_DL_CTRL);
drivers/usb/host/xhci-rcar.c
146
writel(data, regs + RCAR_USB3_FW_DATA0);
drivers/usb/host/xhci-rcar.c
149
writel(temp, regs + RCAR_USB3_DL_CTRL);
drivers/usb/host/xhci-rcar.c
160
writel(temp, regs + RCAR_USB3_DL_CTRL);
drivers/usb/host/xhci-rcar.c
38
writel(RCAR_USB3_LCLK_ENA_VAL, hcd->regs + RCAR_USB3_LCLK);
drivers/usb/host/xhci-rcar.c
40
writel(RCAR_USB3_CONF1_VAL, hcd->regs + RCAR_USB3_CONF1);
drivers/usb/host/xhci-rcar.c
41
writel(RCAR_USB3_CONF2_VAL, hcd->regs + RCAR_USB3_CONF2);
drivers/usb/host/xhci-rcar.c
42
writel(RCAR_USB3_CONF3_VAL, hcd->regs + RCAR_USB3_CONF3);
drivers/usb/host/xhci-rcar.c
44
writel(RCAR_USB3_RX_POL_VAL, hcd->regs + RCAR_USB3_RX_POL);
drivers/usb/host/xhci-rcar.c
45
writel(RCAR_USB3_TX_POL_VAL, hcd->regs + RCAR_USB3_TX_POL);
drivers/usb/host/xhci-rcar.c
66
writel(temp, hcd->regs + RCAR_USB3_INT_ENA);
drivers/usb/host/xhci-rcar.c
78
writel(0x03130200, hcd->regs + RZG3E_USB3_HOST_U3P0PIPESC(0));
drivers/usb/host/xhci-rcar.c
79
writel(0x00160200, hcd->regs + RZG3E_USB3_HOST_U3P0PIPESC(1));
drivers/usb/host/xhci-rcar.c
80
writel(0x03150000, hcd->regs + RZG3E_USB3_HOST_U3P0PIPESC(2));
drivers/usb/host/xhci-rcar.c
81
writel(0x03130200, hcd->regs + RZG3E_USB3_HOST_U3P0PIPESC(3));
drivers/usb/host/xhci-rcar.c
82
writel(0x00180000, hcd->regs + RZG3E_USB3_HOST_U3P0PIPESC(4));
drivers/usb/host/xhci-rcar.c
87
writel(int_en, hcd->regs + RZG3E_USB3_HOST_INTEN);
drivers/usb/host/xhci-ring.c
1983
writel(0x6F, hcd->regs + 0x1048);
drivers/usb/host/xhci-ring.c
1986
writel(0x7F, hcd->regs + 0x1048);
drivers/usb/host/xhci-ring.c
3075
writel(iman, &ir->ir_set->iman);
drivers/usb/host/xhci-ring.c
3214
writel(status, &xhci->op_regs->status);
drivers/usb/host/xhci-ring.c
431
writel(DB_VALUE_HOST, &xhci->dba->doorbell[0]);
drivers/usb/host/xhci-ring.c
570
writel(DB_VALUE(ep_index, stream_id), db_addr);
drivers/usb/host/xhci-rzv2m.c
37
writel(int_en, hcd->regs + RZV2M_USB3_INTEN);
drivers/usb/host/xhci-tegra.c
2231
writel(usbcmd, &xhci->op_regs->command);
drivers/usb/host/xhci-tegra.c
2278
writel(usbcmd, &xhci->op_regs->command);
drivers/usb/host/xhci-tegra.c
2350
writel(usbcmd, &xhci->op_regs->command);
drivers/usb/host/xhci-tegra.c
333
writel(value, tegra->fpci_base + offset);
drivers/usb/host/xhci-tegra.c
344
writel(value, tegra->ipfs_base + offset);
drivers/usb/host/xhci-tegra.c
355
writel(value, tegra->bar2_base + offset);
drivers/usb/host/xhci.c
1015
writel(command, &xhci->op_regs->command);
drivers/usb/host/xhci.c
1034
writel(command, &xhci->op_regs->command);
drivers/usb/host/xhci.c
1132
writel(command, &xhci->op_regs->command);
drivers/usb/host/xhci.c
116
writel(cmd, &xhci->op_regs->command);
drivers/usb/host/xhci.c
1182
writel((temp & ~0x1fff) | STS_EINT, &xhci->op_regs->status);
drivers/usb/host/xhci.c
1227
writel(command, &xhci->op_regs->command);
drivers/usb/host/xhci.c
160
writel(temp, &xhci->op_regs->command);
drivers/usb/host/xhci.c
210
writel(command, &xhci->op_regs->command);
drivers/usb/host/xhci.c
278
writel(val, &xhci->op_regs->command);
drivers/usb/host/xhci.c
283
writel(val, &xhci->op_regs->status);
drivers/usb/host/xhci.c
323
writel(iman, &ir->ir_set->iman);
drivers/usb/host/xhci.c
340
writel(iman, &ir->ir_set->iman);
drivers/usb/host/xhci.c
364
writel(imod, &ir->ir_set->imod);
drivers/usb/host/xhci.c
47
writel(val, &port->port_reg->portsc);
drivers/usb/host/xhci.c
4707
writel(hlpm_val, &port_reg->porthlmpc);
drivers/usb/host/xhci.c
4716
writel(pm_val, &port_reg->portpmsc);
drivers/usb/host/xhci.c
4719
writel(pm_val, &port_reg->portpmsc);
drivers/usb/host/xhci.c
4724
writel(pm_val, &port_reg->portpmsc);
drivers/usb/host/xhci.c
493
writel(config_reg, &xhci->op_regs->config_reg);
drivers/usb/host/xhci.c
536
writel(dev_notf, &xhci->op_regs->dev_notification);
drivers/usb/host/xhci.c
610
writel(temp, &xhci->op_regs->command);
drivers/usb/host/xhci.c
744
writel((temp & ~0x1fff) | STS_EINT, &xhci->op_regs->status);
drivers/usb/host/xhci.c
834
writel(xhci->s3.command, &xhci->op_regs->command);
drivers/usb/host/xhci.c
835
writel(xhci->s3.dev_nt, &xhci->op_regs->dev_notification);
drivers/usb/host/xhci.c
837
writel(xhci->s3.config_reg, &xhci->op_regs->config_reg);
drivers/usb/host/xhci.c
845
writel(ir->s3_erst_size, &ir->ir_set->erst_size);
drivers/usb/host/xhci.c
848
writel(ir->s3_iman, &ir->ir_set->iman);
drivers/usb/host/xhci.c
849
writel(ir->s3_imod, &ir->ir_set->imod);
drivers/usb/isp1760/isp1760-hcd.c
220
writel(port_status | bit, priv->base + portsc1_reg);
drivers/usb/isp1760/isp1760-hcd.c
222
writel(port_status & ~bit, priv->base + portsc1_reg);
drivers/usb/isp1760/isp1760-if.c
117
writel(reg_data, iobase + PLX_INT_CSR_REG);
drivers/usb/isp1760/isp1760-if.c
80
writel(0xface, iobase + ISP176x_HC_SCRATCH);
drivers/usb/misc/brcmstb-usb-pinmap.c
48
writel(val, reg);
drivers/usb/misc/brcmstb-usb-pinmap.c
57
writel(val, reg);
drivers/usb/misc/qcom_eud.c
134
writel(0, chip->base + EUD_REG_SW_ATTACH_DET);
drivers/usb/misc/qcom_eud.c
144
writel(EUD_INT_PET_EUD, chip->base + EUD_REG_SW_ATTACH_DET);
drivers/usb/misc/qcom_eud.c
178
writel(BIT(0), chip->base + EUD_REG_VBUS_INT_CLR);
drivers/usb/misc/qcom_eud.c
179
writel(0, chip->base + EUD_REG_VBUS_INT_CLR);
drivers/usb/misc/qcom_eud.c
53
writel(EUD_ENABLE, priv->base + EUD_REG_CSR_EUD_EN);
drivers/usb/misc/qcom_eud.c
54
writel(EUD_INT_VBUS | EUD_INT_SAFE_MODE,
drivers/usb/misc/qcom_eud.c
68
writel(0, priv->base + EUD_REG_CSR_EUD_EN);
drivers/usb/mtu3/mtu3.h
401
writel(data, base + offset);
drivers/usb/mtu3/mtu3.h
414
writel((tmp | (bits)), addr);
drivers/usb/mtu3/mtu3.h
422
writel((tmp & ~(bits)), addr);
drivers/usb/phy/phy-am335x-control.c
59
writel(val, usb_ctrl->wkup);
drivers/usb/phy/phy-am335x-control.c
98
writel(val, usb_ctrl->phy_reg + reg);
drivers/usb/phy/phy-fsl-usb.c
102
#define fsl_writel(val, addr) writel(val, addr)
drivers/usb/phy/phy-keystone.c
41
writel(value, base + offset);
drivers/usb/phy/phy-mxs-usb.c
275
writel(phytx, base + HW_USBPHY_TX);
drivers/usb/phy/phy-mxs-usb.c
286
writel(BM_USBPHY_PLL_REG_ENABLE, base + HW_USBPHY_PLL_SIC_SET);
drivers/usb/phy/phy-mxs-usb.c
287
writel(BM_USBPHY_PLL_BYPASS, base + HW_USBPHY_PLL_SIC_CLR);
drivers/usb/phy/phy-mxs-usb.c
288
writel(BM_USBPHY_PLL_POWER, base + HW_USBPHY_PLL_SIC_SET);
drivers/usb/phy/phy-mxs-usb.c
295
writel(BM_USBPHY_PLL_EN_USB_CLKS, base +
drivers/usb/phy/phy-mxs-usb.c
298
writel(BM_USBPHY_PLL_EN_USB_CLKS, base +
drivers/usb/phy/phy-mxs-usb.c
300
writel(BM_USBPHY_PLL_POWER, base + HW_USBPHY_PLL_SIC_CLR);
drivers/usb/phy/phy-mxs-usb.c
301
writel(BM_USBPHY_PLL_BYPASS, base + HW_USBPHY_PLL_SIC_SET);
drivers/usb/phy/phy-mxs-usb.c
302
writel(BM_USBPHY_PLL_REG_ENABLE, base + HW_USBPHY_PLL_SIC_CLR);
drivers/usb/phy/phy-mxs-usb.c
334
writel(0, base + HW_USBPHY_PWD);
drivers/usb/phy/phy-mxs-usb.c
341
writel(BM_USBPHY_CTRL_ENAUTOSET_USBCLKS |
drivers/usb/phy/phy-mxs-usb.c
351
writel(BM_USBPHY_IP_FIX, base + HW_USBPHY_IP_SET);
drivers/usb/phy/phy-mxs-usb.c
484
writel(value, phy->io_priv + HW_USBPHY_CTRL_CLR);
drivers/usb/phy/phy-mxs-usb.c
485
writel(0xffffffff, phy->io_priv + HW_USBPHY_PWD);
drivers/usb/phy/phy-mxs-usb.c
487
writel(BM_USBPHY_CTRL_CLKGATE,
drivers/usb/phy/phy-mxs-usb.c
545
writel(0xffbfffff, x->io_priv + HW_USBPHY_PWD);
drivers/usb/phy/phy-mxs-usb.c
547
writel(0xffffffff, x->io_priv + HW_USBPHY_PWD);
drivers/usb/phy/phy-mxs-usb.c
549
writel(BM_USBPHY_CTRL_CLKGATE,
drivers/usb/phy/phy-mxs-usb.c
564
writel(BM_USBPHY_CTRL_CLKGATE,
drivers/usb/phy/phy-mxs-usb.c
566
writel(0, x->io_priv + HW_USBPHY_PWD);
drivers/usb/phy/phy-mxs-usb.c
596
writel(BM_USBPHY_CTRL_ENHOSTDISCONDETECT,
drivers/usb/phy/phy-mxs-usb.c
611
writel(BM_USBPHY_CTRL_ENHOSTDISCONDETECT,
drivers/usb/phy/phy-omap-otg.c
47
writel(l, otg_dev->base + OMAP_OTG_CTRL);
drivers/usb/phy/phy-ulpi-viewport.c
34
writel(ULPI_VIEW_WAKEUP | ULPI_VIEW_WRITE, view);
drivers/usb/phy/phy-ulpi-viewport.c
39
writel(ULPI_VIEW_RUN | ULPI_VIEW_READ | ULPI_VIEW_ADDR(reg), view);
drivers/usb/phy/phy-ulpi-viewport.c
52
writel(ULPI_VIEW_WAKEUP | ULPI_VIEW_WRITE, view);
drivers/usb/phy/phy-ulpi-viewport.c
57
writel(ULPI_VIEW_RUN | ULPI_VIEW_WRITE | ULPI_VIEW_DATA_WRITE(val) |
drivers/usb/roles/intel-xhci-usb-role-switch.c
106
writel(val, data->base + DUAL_ROLE_CFG0);
drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c
311
writel(0x1, qm->io_base + QM_VFT_CFG_OP_WR);
drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c
313
writel(0x0, qm->io_base + QM_VFT_CFG_TYPE);
drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c
314
writel(vf_id, qm->io_base + QM_VFT_CFG);
drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c
316
writel(0x0, qm->io_base + QM_VFT_CFG_RDY);
drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c
317
writel(0x1, qm->io_base + QM_VFT_CFG_OP_ENABLE);
drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c
339
writel(0x1, qm->io_base + QM_IFC_INT_SOURCE_V);
drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c
342
writel(0x0, qm->io_base + QM_IFC_INT_MASK);
drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c
350
writel(0x1, qm->io_base + QM_CACHE_WB_START);
drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c
73
writel(data[i], qm->io_base + reg + i * QM_REG_ADDR_OFFSET);
drivers/vfio/platform/reset/vfio_platform_calxedaxgmac.c
42
writel(value, ioaddr + XGMAC_DMA_CONTROL);
drivers/vfio/platform/reset/vfio_platform_calxedaxgmac.c
46
writel(value, ioaddr + XGMAC_CONTROL);
drivers/vfio/platform/reset/vfio_platform_calxedaxgmac.c
63
writel(0, reg->ioaddr + XGMAC_DMA_INTR_ENA);
drivers/video/backlight/apple_dwi_bl.c
52
writel(cmd, dwi_bl->base + DWI_BL_CMD);
drivers/video/backlight/apple_dwi_bl.c
53
writel(DWI_BL_CTL_SEND, dwi_bl->base + DWI_BL_CTL);
drivers/video/backlight/ep93xx_bl.c
29
writel((brightness << 8) | EP93XX_MAX_COUNT, ep93xxbl->mmio);
drivers/video/fbdev/aty/aty128fb.c
531
writel (val, par->regbase + regindex);
drivers/video/fbdev/aty/atyfb.h
250
writel(val, par->ati_regbase + regindex);
drivers/video/fbdev/aty/atyfb.h
263
writel(val, par->ati_regbase + regindex);
drivers/video/fbdev/aty/radeonfb.h
381
#define OUTREG(addr,val) writel(val, (rinfo->mmio_base)+addr)
drivers/video/fbdev/carminefb.c
143
writel(val, par->display_reg + offset);
drivers/video/fbdev/carminefb.c
155
writel(val, hw->v_regs + offset);
drivers/video/fbdev/clps711x-fb.c
143
writel(lcdcon, cfb->base + CLPS711X_LCDCON);
drivers/video/fbdev/clps711x-fb.c
62
writel((readl(cfb->base + regno) & ~mask) | level, cfb->base + regno);
drivers/video/fbdev/cobalt_lcdfb.c
56
writel((u32)control << 24, info->screen_base);
drivers/video/fbdev/cobalt_lcdfb.c
66
writel((u32)data << 24, info->screen_base + LCD_DATA_REG_OFFSET);
drivers/video/fbdev/cyber2000fb.c
109
#define cyber2000fb_writel(val, reg, cfb) writel(val, (cfb)->regs + (reg))
drivers/video/fbdev/geode/display_gx1.c
100
writel(gcfg, par->dc_regs + DC_GENERAL_CFG);
drivers/video/fbdev/geode/display_gx1.c
104
writel(gcfg, par->dc_regs + DC_GENERAL_CFG);
drivers/video/fbdev/geode/display_gx1.c
110
writel(gcfg, par->dc_regs + DC_GENERAL_CFG);
drivers/video/fbdev/geode/display_gx1.c
131
writel(0, par->dc_regs + DC_FB_ST_OFFSET);
drivers/video/fbdev/geode/display_gx1.c
134
writel(info->fix.line_length >> 2, par->dc_regs + DC_LINE_DELTA);
drivers/video/fbdev/geode/display_gx1.c
135
writel(((info->var.xres * info->var.bits_per_pixel/8) >> 3) + 2,
drivers/video/fbdev/geode/display_gx1.c
162
writel(val, par->dc_regs + DC_H_TIMING_1);
drivers/video/fbdev/geode/display_gx1.c
164
writel(val, par->dc_regs + DC_H_TIMING_2);
drivers/video/fbdev/geode/display_gx1.c
166
writel(val, par->dc_regs + DC_H_TIMING_3);
drivers/video/fbdev/geode/display_gx1.c
167
writel(val, par->dc_regs + DC_FP_H_TIMING);
drivers/video/fbdev/geode/display_gx1.c
169
writel(val, par->dc_regs + DC_V_TIMING_1);
drivers/video/fbdev/geode/display_gx1.c
171
writel(val, par->dc_regs + DC_V_TIMING_2);
drivers/video/fbdev/geode/display_gx1.c
173
writel(val, par->dc_regs + DC_V_TIMING_3);
drivers/video/fbdev/geode/display_gx1.c
175
writel(val, par->dc_regs + DC_FP_V_TIMING);
drivers/video/fbdev/geode/display_gx1.c
178
writel(ocfg, par->dc_regs + DC_OUTPUT_CFG);
drivers/video/fbdev/geode/display_gx1.c
179
writel(tcfg, par->dc_regs + DC_TIMING_CFG);
drivers/video/fbdev/geode/display_gx1.c
181
writel(gcfg, par->dc_regs + DC_GENERAL_CFG);
drivers/video/fbdev/geode/display_gx1.c
186
writel(0, par->dc_regs + DC_UNLOCK);
drivers/video/fbdev/geode/display_gx1.c
203
writel(regno, par->dc_regs + DC_PAL_ADDRESS);
drivers/video/fbdev/geode/display_gx1.c
204
writel(val, par->dc_regs + DC_PAL_DATA);
drivers/video/fbdev/geode/display_gx1.c
86
writel(DC_UNLOCK_CODE, par->dc_regs + DC_UNLOCK);
drivers/video/fbdev/geode/display_gx1.c
93
writel(tcfg, par->dc_regs + DC_TIMING_CFG);
drivers/video/fbdev/geode/gxfb.h
300
writel(val, par->gp_regs + 4*reg);
drivers/video/fbdev/geode/gxfb.h
310
writel(val, par->dc_regs + 4*reg);
drivers/video/fbdev/geode/gxfb.h
320
writel(val, par->vid_regs + 8*reg);
drivers/video/fbdev/geode/gxfb.h
330
writel(val, par->vid_regs + 8*reg + VP_FP_START);
drivers/video/fbdev/geode/lxfb.h
383
writel(val, par->gp_regs + 4*reg);
drivers/video/fbdev/geode/lxfb.h
393
writel(val, par->dc_regs + 4*reg);
drivers/video/fbdev/geode/lxfb.h
403
writel(val, par->vp_regs + 8*reg);
drivers/video/fbdev/geode/lxfb.h
413
writel(val, par->vp_regs + 8*reg + VP_FP_START);
drivers/video/fbdev/geode/video_cs5530.c
130
writel(dcfg, par->vid_regs + CS5530_DISPLAY_CONFIG);
drivers/video/fbdev/geode/video_cs5530.c
180
writel(dcfg, par->vid_regs + CS5530_DISPLAY_CONFIG);
drivers/video/fbdev/geode/video_cs5530.c
88
writel(value, par->vid_regs + CS5530_DOT_CLK_CONFIG);
drivers/video/fbdev/geode/video_cs5530.c
89
writel(value | 0x80000100, par->vid_regs + CS5530_DOT_CLK_CONFIG); /* set reset and bypass */
drivers/video/fbdev/geode/video_cs5530.c
91
writel(value & 0x7FFFFFFF, par->vid_regs + CS5530_DOT_CLK_CONFIG); /* clear reset */
drivers/video/fbdev/geode/video_cs5530.c
92
writel(value & 0x7FFFFEFF, par->vid_regs + CS5530_DOT_CLK_CONFIG); /* clear bypass */
drivers/video/fbdev/goldfishfb.c
123
writel(fb->rotation, fb->reg_base + FB_SET_ROTATION);
drivers/video/fbdev/goldfishfb.c
138
writel(fb->fb.fix.smem_start + fb->fb.var.xres * 2 * var->yoffset,
drivers/video/fbdev/goldfishfb.c
154
writel(1, fb->reg_base + FB_SET_BLANK);
drivers/video/fbdev/goldfishfb.c
157
writel(0, fb->reg_base + FB_SET_BLANK);
drivers/video/fbdev/goldfishfb.c
259
writel(FB_INT_BASE_UPDATE_DONE, fb->reg_base + FB_INT_ENABLE);
drivers/video/fbdev/gxt4500.c
143
#define writereg(par, reg, val) writel((val), (par)->regs + (reg))
drivers/video/fbdev/i740fb.c
835
writel(itemp, par->regs + FWATER_BLC);
drivers/video/fbdev/i810/i810.h
296
#define i810_writel(where, mmio, val) writel(val, mmio + where)
drivers/video/fbdev/imsttfb.c
419
writel(val, base + regindex);
drivers/video/fbdev/imxfb.c
289
writel(val, fbi->regs + 0x800 + (regno << 2));
drivers/video/fbdev/imxfb.c
520
writel(fbi->map_dma, fbi->regs + LCDC_SSA);
drivers/video/fbdev/imxfb.c
523
writel(FIELD_PREP(POS_POS_MASK, 0), fbi->regs + LCDC_POS);
drivers/video/fbdev/imxfb.c
526
writel(readl(fbi->regs + LCDC_CPOS) & ~(CPOS_CC0 | CPOS_CC1),
drivers/video/fbdev/imxfb.c
533
writel(RMCR_LCDC_EN_MX1, fbi->regs + LCDC_RMCR);
drivers/video/fbdev/imxfb.c
555
writel(0, fbi->regs + LCDC_RMCR);
drivers/video/fbdev/imxfb.c
572
writel(0, fbi->regs + LCDC_RMCR);
drivers/video/fbdev/imxfb.c
657
writel(FIELD_PREP(VPW_VPW_MASK,
drivers/video/fbdev/imxfb.c
661
writel(FIELD_PREP(HCR_H_WIDTH_MASK, var->hsync_len - 1) |
drivers/video/fbdev/imxfb.c
667
writel(FIELD_PREP(VCR_V_WIDTH_MASK, var->vsync_len) |
drivers/video/fbdev/imxfb.c
672
writel(FIELD_PREP(SIZE_XMAX_MASK, var->xres >> 4) |
drivers/video/fbdev/imxfb.c
676
writel(fbi->pcr, fbi->regs + LCDC_PCR);
drivers/video/fbdev/imxfb.c
678
writel(fbi->pwmr, fbi->regs + LCDC_PWMR);
drivers/video/fbdev/imxfb.c
679
writel(fbi->lscr1, fbi->regs + LCDC_LSCR1);
drivers/video/fbdev/imxfb.c
683
writel(fbi->dmacr, fbi->regs + LCDC_DMACR);
drivers/video/fbdev/imxfb.c
686
writel(fbi->lauscr, fbi->regs + LCDC_LAUSCR);
drivers/video/fbdev/imxfb.c
805
writel(fbi->pwmr, fbi->regs + LCDC_PWMR);
drivers/video/fbdev/kyro/STG4000Reg.h
24
#define STG_WRITE_REG(reg,data) (writel(data,&pSTGReg->reg))
drivers/video/fbdev/matrox/matroxfb_base.h
144
writel(value, va.vaddr + offs);
drivers/video/fbdev/mb862xx/mb862xxfb.h
109
#define gdc_write writel
drivers/video/fbdev/mb862xx/mb862xxfbdrv.c
858
writel(1, par->fb_base + MB862XX_MMIO_BASE + GC_RSW);
drivers/video/fbdev/mmp/hw/mmp_ctrl.c
177
writel(tmp, ctrl_regs(path) + dma_ctrl(0, path->id));
drivers/video/fbdev/mmp/hw/mmp_spi.c
58
writel(tmp, reg_base + LCD_SPU_SPI_CTRL);
drivers/video/fbdev/mmp/hw/mmp_spi.c
91
writel(tmp, reg_base + LCD_SPU_SPI_CTRL);
drivers/video/fbdev/neofb.c
1372
writel(NEO_BC3_FIFO_EN |
drivers/video/fbdev/neofb.c
1380
writel(rect->color, &par->neo2200->fgColor);
drivers/video/fbdev/neofb.c
1384
writel(((u32 *) (info->pseudo_palette))[rect->color],
drivers/video/fbdev/neofb.c
1389
writel(dst * ((info->var.bits_per_pixel + 7) >> 3),
drivers/video/fbdev/neofb.c
1391
writel((rect->height << 16) | (rect->width & 0xffff),
drivers/video/fbdev/neofb.c
1420
writel(bltCntl, &par->neo2200->bltCntl);
drivers/video/fbdev/neofb.c
1422
writel(src, &par->neo2200->srcStart);
drivers/video/fbdev/neofb.c
1423
writel(dst, &par->neo2200->dstStart);
drivers/video/fbdev/neofb.c
1424
writel((area->height << 16) | (area->width & 0xffff),
drivers/video/fbdev/neofb.c
1465
writel(image->fg_color, &par->neo2200->fgColor);
drivers/video/fbdev/neofb.c
1466
writel(image->bg_color, &par->neo2200->bgColor);
drivers/video/fbdev/neofb.c
147
writel(val, par->neo2200 + par->cursorOff + regindex);
drivers/video/fbdev/neofb.c
1470
writel(((u32 *) (info->pseudo_palette))[image->fg_color],
drivers/video/fbdev/neofb.c
1472
writel(((u32 *) (info->pseudo_palette))[image->bg_color],
drivers/video/fbdev/neofb.c
1477
writel(NEO_BC0_SYS_TO_VID |
drivers/video/fbdev/neofb.c
1482
writel(0, &par->neo2200->srcStart);
drivers/video/fbdev/neofb.c
1484
writel(((image->dx & 0xffff) * (info->var.bits_per_pixel >> 3) +
drivers/video/fbdev/neofb.c
1486
writel((image->height << 16) | (image->width & 0xffff),
drivers/video/fbdev/neofb.c
543
writel(bltMod << 16, &neo2200->bltStat);
drivers/video/fbdev/neofb.c
544
writel((pitch << 16) | pitch, &neo2200->pitch);
drivers/video/fbdev/offb.c
173
writel(1, par->cmap_adr + AVIVO_DC_LUT_RW_SELECT);
drivers/video/fbdev/offb.c
175
writel(((red) << 22) | ((green) << 12) | ((blue) << 2),
drivers/video/fbdev/offb.c
177
writel(0, par->cmap_adr + AVIVO_DC_LUT_RW_SELECT);
drivers/video/fbdev/offb.c
179
writel(((red) << 22) | ((green) << 12) | ((blue) << 2),
drivers/video/fbdev/offb.c
240
writel(1, par->cmap_adr + AVIVO_DC_LUT_RW_SELECT);
drivers/video/fbdev/offb.c
242
writel(0, par->cmap_adr + AVIVO_DC_LUT_30_COLOR);
drivers/video/fbdev/offb.c
243
writel(0, par->cmap_adr + AVIVO_DC_LUT_RW_SELECT);
drivers/video/fbdev/offb.c
245
writel(0, par->cmap_adr + AVIVO_DC_LUT_30_COLOR);
drivers/video/fbdev/offb.c
259
writel(0, par->cmap_adr + AVIVO_DC_LUTA_CONTROL);
drivers/video/fbdev/offb.c
260
writel(0, par->cmap_adr + AVIVO_DC_LUTA_BLACK_OFFSET_BLUE);
drivers/video/fbdev/offb.c
261
writel(0, par->cmap_adr + AVIVO_DC_LUTA_BLACK_OFFSET_GREEN);
drivers/video/fbdev/offb.c
262
writel(0, par->cmap_adr + AVIVO_DC_LUTA_BLACK_OFFSET_RED);
drivers/video/fbdev/offb.c
263
writel(0x0000ffff, par->cmap_adr + AVIVO_DC_LUTA_WHITE_OFFSET_BLUE);
drivers/video/fbdev/offb.c
264
writel(0x0000ffff, par->cmap_adr + AVIVO_DC_LUTA_WHITE_OFFSET_GREEN);
drivers/video/fbdev/offb.c
265
writel(0x0000ffff, par->cmap_adr + AVIVO_DC_LUTA_WHITE_OFFSET_RED);
drivers/video/fbdev/offb.c
266
writel(0, par->cmap_adr + AVIVO_DC_LUTB_CONTROL);
drivers/video/fbdev/offb.c
267
writel(0, par->cmap_adr + AVIVO_DC_LUTB_BLACK_OFFSET_BLUE);
drivers/video/fbdev/offb.c
268
writel(0, par->cmap_adr + AVIVO_DC_LUTB_BLACK_OFFSET_GREEN);
drivers/video/fbdev/offb.c
269
writel(0, par->cmap_adr + AVIVO_DC_LUTB_BLACK_OFFSET_RED);
drivers/video/fbdev/offb.c
270
writel(0x0000ffff, par->cmap_adr + AVIVO_DC_LUTB_WHITE_OFFSET_BLUE);
drivers/video/fbdev/offb.c
271
writel(0x0000ffff, par->cmap_adr + AVIVO_DC_LUTB_WHITE_OFFSET_GREEN);
drivers/video/fbdev/offb.c
272
writel(0x0000ffff, par->cmap_adr + AVIVO_DC_LUTB_WHITE_OFFSET_RED);
drivers/video/fbdev/offb.c
273
writel(1, par->cmap_adr + AVIVO_DC_LUT_RW_SELECT);
drivers/video/fbdev/offb.c
274
writel(0, par->cmap_adr + AVIVO_DC_LUT_RW_MODE);
drivers/video/fbdev/offb.c
275
writel(0x0000003f, par->cmap_adr + AVIVO_DC_LUT_WRITE_EN_MASK);
drivers/video/fbdev/offb.c
276
writel(0, par->cmap_adr + AVIVO_DC_LUT_RW_SELECT);
drivers/video/fbdev/offb.c
277
writel(0, par->cmap_adr + AVIVO_DC_LUT_RW_MODE);
drivers/video/fbdev/offb.c
278
writel(0x0000003f, par->cmap_adr + AVIVO_DC_LUT_WRITE_EN_MASK);
drivers/video/fbdev/omap/sossi.c
89
writel(value, sossi.base + reg);
drivers/video/fbdev/pm3fb.c
1280
writel(0x0000000, (screen_mem + (i * 1048576)));
drivers/video/fbdev/pmagb-b-fb.c
71
writel(v, par->sfb + reg / 4);
drivers/video/fbdev/pmagb-b-fb.c
91
writel(v, par->mmio + PMAGB_B_GP0);
drivers/video/fbdev/pxa168fb.c
287
writel(x, fbi->reg_base + LCD_CFG_SCLK_DIV);
drivers/video/fbdev/pxa168fb.c
322
writel(x, fbi->reg_base + LCD_SPU_DMA_CTRL0);
drivers/video/fbdev/pxa168fb.c
344
writel(x, fbi->reg_base + LCD_SPU_DMA_CTRL1);
drivers/video/fbdev/pxa168fb.c
357
writel(addr, fbi->reg_base + LCD_CFG_GRA_START_ADDR0);
drivers/video/fbdev/pxa168fb.c
382
writel(x, fbi->reg_base + LCD_SPU_DUMB_CTRL);
drivers/video/fbdev/pxa168fb.c
395
writel((y << 16) | x, fbi->reg_base + LCD_SPUT_V_H_TOTAL);
drivers/video/fbdev/pxa168fb.c
419
writel(x & ~1, fbi->reg_base + LCD_SPU_DUMB_CTRL);
drivers/video/fbdev/pxa168fb.c
424
writel((var->yres << 16) | var->xres,
drivers/video/fbdev/pxa168fb.c
444
writel(x, fbi->reg_base + LCD_CFG_GRA_PITCH);
drivers/video/fbdev/pxa168fb.c
445
writel((var->yres << 16) | var->xres,
drivers/video/fbdev/pxa168fb.c
447
writel((var->yres << 16) | var->xres,
drivers/video/fbdev/pxa168fb.c
456
writel((var->left_margin << 16) | var->right_margin,
drivers/video/fbdev/pxa168fb.c
458
writel((var->upper_margin << 16) | var->lower_margin,
drivers/video/fbdev/pxa168fb.c
465
writel(x | 1, fbi->reg_base + LCD_SPU_DUMB_CTRL);
drivers/video/fbdev/pxa168fb.c
504
writel(val, fbi->reg_base + LCD_SPU_SRAM_WRDAT);
drivers/video/fbdev/pxa168fb.c
505
writel(0x8300 | regno, fbi->reg_base + LCD_SPU_SRAM_CTRL);
drivers/video/fbdev/pxa168fb.c
536
writel(isr & (~GRA_FRAME_IRQ0_ENA_MASK),
drivers/video/fbdev/pxa168fb.c
707
writel(0, fbi->reg_base + LCD_SPU_BLANKCOLOR);
drivers/video/fbdev/pxa168fb.c
708
writel(mi->io_pin_allocation_mode, fbi->reg_base + SPU_IOPAD_CONTROL);
drivers/video/fbdev/pxa168fb.c
709
writel(0, fbi->reg_base + LCD_CFG_GRA_START_ADDR1);
drivers/video/fbdev/pxa168fb.c
710
writel(0, fbi->reg_base + LCD_SPU_GRA_OVSA_HPXL_VLN);
drivers/video/fbdev/pxa168fb.c
711
writel(0, fbi->reg_base + LCD_SPU_SRAM_PARA0);
drivers/video/fbdev/pxa168fb.c
712
writel(CFG_CSB_256x32(0x1)|CFG_CSB_256x24(0x1)|CFG_CSB_256x8(0x1),
drivers/video/fbdev/pxa168fb.c
737
writel(GRA_FRAME_IRQ0_ENA(0x1), fbi->reg_base + SPU_IRQ_ENA);
drivers/video/fbdev/pxa168fb.c
778
writel(data, fbi->reg_base + LCD_SPU_DMA_CTRL0);
drivers/video/fbdev/pxa168fb.c
784
writel(GRA_FRAME_IRQ0_ENA(0x0), fbi->reg_base + SPU_IRQ_ENA);
drivers/video/fbdev/riva/fbdev.c
506
writel(tmp, &par->riva.CURSOR[k++]);
drivers/video/fbdev/s3c-fb.c
1150
writel(data, sfb->regs + SHADOWCON);
drivers/video/fbdev/s3c-fb.c
1308
writel(data, regs + VIDCON0);
drivers/video/fbdev/s3c-fb.c
1313
writel(data, regs + sfb->variant.vidtcon);
drivers/video/fbdev/s3c-fb.c
1318
writel(data, regs + sfb->variant.vidtcon + 4);
drivers/video/fbdev/s3c-fb.c
1324
writel(data, regs + sfb->variant.vidtcon + 8);
drivers/video/fbdev/s3c-fb.c
1339
writel(0, regs + sfb->variant.wincon + (win * 4));
drivers/video/fbdev/s3c-fb.c
1340
writel(0, regs + VIDOSD_A(win, sfb->variant));
drivers/video/fbdev/s3c-fb.c
1341
writel(0, regs + VIDOSD_B(win, sfb->variant));
drivers/video/fbdev/s3c-fb.c
1342
writel(0, regs + VIDOSD_C(win, sfb->variant));
drivers/video/fbdev/s3c-fb.c
1349
writel(reg, sfb->regs + SHADOWCON);
drivers/video/fbdev/s3c-fb.c
1438
writel(pd->vidcon1, sfb->regs + VIDCON1);
drivers/video/fbdev/s3c-fb.c
1445
writel(reg, sfb->regs + VIDCON1);
drivers/video/fbdev/s3c-fb.c
1458
writel(0xffffff, regs + WKEYCON0);
drivers/video/fbdev/s3c-fb.c
1459
writel(0xffffff, regs + WKEYCON1);
drivers/video/fbdev/s3c-fb.c
1572
writel(pd->vidcon1, sfb->regs + VIDCON1);
drivers/video/fbdev/s3c-fb.c
1579
writel(reg, sfb->regs + VIDCON1);
drivers/video/fbdev/s3c-fb.c
1594
writel(0xffffff, regs + WKEYCON0);
drivers/video/fbdev/s3c-fb.c
1595
writel(0xffffff, regs + WKEYCON1);
drivers/video/fbdev/s3c-fb.c
1642
writel(pd->vidcon1, sfb->regs + VIDCON1);
drivers/video/fbdev/s3c-fb.c
399
writel(size, sfb->regs + OSD_BASE(win->index, sfb->variant)
drivers/video/fbdev/s3c-fb.c
414
writel(alpha, sfb->regs + VIDOSD_C(win->index, sfb->variant));
drivers/video/fbdev/s3c-fb.c
430
writel(PRTCON_PROTECT, sfb->regs + PRTCON);
drivers/video/fbdev/s3c-fb.c
433
writel(reg | SHADOWCON_WINx_PROTECT(win->index),
drivers/video/fbdev/s3c-fb.c
438
writel(0, sfb->regs + PRTCON);
drivers/video/fbdev/s3c-fb.c
441
writel(reg & ~SHADOWCON_WINx_PROTECT(win->index),
drivers/video/fbdev/s3c-fb.c
472
writel(vidcon0, sfb->regs + VIDCON0);
drivers/video/fbdev/s3c-fb.c
531
writel(0, regs + WINCON(win_no));
drivers/video/fbdev/s3c-fb.c
541
writel(info->fix.smem_start, buf + sfb->variant.buf_start);
drivers/video/fbdev/s3c-fb.c
544
writel(data, buf + sfb->variant.buf_end);
drivers/video/fbdev/s3c-fb.c
551
writel(data, regs + sfb->variant.buf_size + (win_no * 4));
drivers/video/fbdev/s3c-fb.c
557
writel(data, regs + VIDOSD_A(win_no, sfb->variant));
drivers/video/fbdev/s3c-fb.c
566
writel(data, regs + VIDOSD_B(win_no, sfb->variant));
drivers/video/fbdev/s3c-fb.c
581
writel(data, sfb->regs + SHADOWCON);
drivers/video/fbdev/s3c-fb.c
658
writel(keycon0_data, keycon + WKEYCON0);
drivers/video/fbdev/s3c-fb.c
659
writel(keycon1_data, keycon + WKEYCON1);
drivers/video/fbdev/s3c-fb.c
662
writel(data, regs + sfb->variant.wincon + (win_no * 4));
drivers/video/fbdev/s3c-fb.c
663
writel(0x0, regs + sfb->variant.winmap + (win_no * 4));
drivers/video/fbdev/s3c-fb.c
673
writel(data, sfb->regs + BLENDCON);
drivers/video/fbdev/s3c-fb.c
713
writel(palcon | WPALCON_PAL_UPDATE, sfb->regs + WPALCON);
drivers/video/fbdev/s3c-fb.c
718
writel(value, palreg + (reg * 4));
drivers/video/fbdev/s3c-fb.c
720
writel(palcon, sfb->regs + WPALCON);
drivers/video/fbdev/s3c-fb.c
818
writel(WINxMAP_MAP | WINxMAP_MAP_COLOUR(0x0),
drivers/video/fbdev/s3c-fb.c
825
writel(0x0, sfb->regs + sfb->variant.winmap + (index * 4));
drivers/video/fbdev/s3c-fb.c
839
writel(wincon, sfb->regs + sfb->variant.wincon + (index * 4));
drivers/video/fbdev/s3c-fb.c
904
writel(info->fix.smem_start + start_boff, buf + sfb->variant.buf_start);
drivers/video/fbdev/s3c-fb.c
905
writel(info->fix.smem_start + end_boff, buf + sfb->variant.buf_end);
drivers/video/fbdev/s3c-fb.c
934
writel(irq_ctrl_reg, regs + VIDINTCON0);
drivers/video/fbdev/s3c-fb.c
954
writel(irq_ctrl_reg, regs + VIDINTCON0);
drivers/video/fbdev/s3c-fb.c
971
writel(VIDINTCON1_INT_FRAME, regs + VIDINTCON1);
drivers/video/fbdev/savage/savagefb-i2c.c
55
writel(r, chan->ioaddr + chan->reg);
drivers/video/fbdev/savage/savagefb-i2c.c
69
writel(r, chan->ioaddr + chan->reg);
drivers/video/fbdev/savage/savagefb.h
127
#define BCI_SEND(dw) writel(dw, par->bci_base + par->bci_ptr++)
drivers/video/fbdev/savage/savagefb.h
280
writel(val, par->mmio.vbase + addr);
drivers/video/fbdev/sis/sis.h
397
#define MMIO_OUT32(base, offset, val) writel(((u32)(val)), (base+offset))
drivers/video/fbdev/sis/sis_main.c
2881
writel(0x16800000 + 0x8240, ivideo->video_vbase + tempq);
drivers/video/fbdev/sis/sis_main.c
2882
writel(templ | (1 << 10), ivideo->video_vbase + tempq + 4);
drivers/video/fbdev/sis/sis_main.c
2883
writel(0x168F0000, ivideo->video_vbase + tempq + 8);
drivers/video/fbdev/sis/sis_main.c
2884
writel(0x168F0000, ivideo->video_vbase + tempq + 12);
drivers/video/fbdev/sis/sis_main.c
4186
writel(0x01234567L, FBAddress);
drivers/video/fbdev/sis/sis_main.c
4187
writel(0x456789ABL, (FBAddress + 4));
drivers/video/fbdev/sis/sis_main.c
4188
writel(0x89ABCDEFL, (FBAddress + 8));
drivers/video/fbdev/sis/sis_main.c
4189
writel(0xCDEF0123L, (FBAddress + 12));
drivers/video/fbdev/sis/sis_main.c
4576
writel(0, ivideo->video_vbase);
drivers/video/fbdev/sis/sis_main.c
4581
writel(pos, ivideo->video_vbase + pos);
drivers/video/fbdev/sm712fb.c
1238
writel(0x0, sfb->vp_regs + 0x0C);
drivers/video/fbdev/sm712fb.c
1239
writel(0x0, sfb->vp_regs + 0x40);
drivers/video/fbdev/sm712fb.c
1245
writel(0x0, sfb->vp_regs + 0x0);
drivers/video/fbdev/sm712fb.c
1248
writel(0x00020000, sfb->vp_regs + 0x0);
drivers/video/fbdev/sm712fb.c
1251
writel(0x00040000, sfb->vp_regs + 0x0);
drivers/video/fbdev/sm712fb.c
1254
writel(0x00030000, sfb->vp_regs + 0x0);
drivers/video/fbdev/sm712fb.c
1257
writel((u32)(((m_nscreenstride + 2) << 16) | m_nscreenstride),
drivers/video/fbdev/sstfb.c
193
writel(val, vbase + reg);
drivers/video/fbdev/sstfb.c
840
writel(0xdeadbeef, fbbase_virt);
drivers/video/fbdev/sstfb.c
841
writel(0xdeadbeef, fbbase_virt+0x100000);
drivers/video/fbdev/sstfb.c
842
writel(0xdeadbeef, fbbase_virt+0x200000);
drivers/video/fbdev/sstfb.c
847
writel(0xabcdef01, fbbase_virt);
drivers/video/fbdev/sunxvr500.c
106
writel(index, ramdac + RAMDAC_INDEX);
drivers/video/fbdev/sunxvr500.c
107
writel(val, ramdac + RAMDAC_DATA);
drivers/video/fbdev/tdfxfb.c
249
writel(val, par->regbase_virt + reg);
drivers/video/fbdev/via/accel.c
100
writel(tmp, engine + 0x0C);
drivers/video/fbdev/via/accel.c
108
writel(tmp, engine + 0x10);
drivers/video/fbdev/via/accel.c
111
writel(fg_color, engine + 0x18);
drivers/video/fbdev/via/accel.c
114
writel(bg_color, engine + 0x1C);
drivers/video/fbdev/via/accel.c
124
writel(tmp, engine + 0x30);
drivers/video/fbdev/via/accel.c
133
writel(tmp, engine + 0x34);
drivers/video/fbdev/via/accel.c
145
writel(tmp, engine + 0x38);
drivers/video/fbdev/via/accel.c
158
writel(ge_cmd, engine);
drivers/video/fbdev/via/accel.c
167
writel(src_mem[i], engine + VIA_MMIO_BLTBASE);
drivers/video/fbdev/via/accel.c
226
writel(tmp, engine + 0x08);
drivers/video/fbdev/via/accel.c
234
writel(tmp, engine + 0x0C);
drivers/video/fbdev/via/accel.c
242
writel(tmp, engine + 0x10);
drivers/video/fbdev/via/accel.c
250
writel(tmp, engine + 0x14);
drivers/video/fbdev/via/accel.c
260
writel(tmp, engine + 0x18);
drivers/video/fbdev/via/accel.c
269
writel(tmp, engine + 0x1C);
drivers/video/fbdev/via/accel.c
273
writel(fg_color, engine + 0x58);
drivers/video/fbdev/via/accel.c
275
writel(fg_color, engine + 0x4C);
drivers/video/fbdev/via/accel.c
276
writel(bg_color, engine + 0x50);
drivers/video/fbdev/via/accel.c
290
writel(ge_cmd, engine);
drivers/video/fbdev/via/accel.c
299
writel(src_mem[i], engine + VIA_MMIO_BLTBASE);
drivers/video/fbdev/via/accel.c
34
writel(gemode, engine + VIA_REG_GEMODE);
drivers/video/fbdev/via/accel.c
384
writel(0x0, engine + i);
drivers/video/fbdev/via/accel.c
393
writel(0x00100000, engine + VIA_REG_CR_TRANSET);
drivers/video/fbdev/via/accel.c
394
writel(0x680A0000, engine + VIA_REG_CR_TRANSPACE);
drivers/video/fbdev/via/accel.c
395
writel(0x02000000, engine + VIA_REG_CR_TRANSPACE);
drivers/video/fbdev/via/accel.c
399
writel(0x00100000, engine + VIA_REG_TRANSET);
drivers/video/fbdev/via/accel.c
400
writel(0x00000000, engine + VIA_REG_TRANSPACE);
drivers/video/fbdev/via/accel.c
401
writel(0x00333004, engine + VIA_REG_TRANSPACE);
drivers/video/fbdev/via/accel.c
402
writel(0x60000000, engine + VIA_REG_TRANSPACE);
drivers/video/fbdev/via/accel.c
403
writel(0x61000000, engine + VIA_REG_TRANSPACE);
drivers/video/fbdev/via/accel.c
404
writel(0x62000000, engine + VIA_REG_TRANSPACE);
drivers/video/fbdev/via/accel.c
405
writel(0x63000000, engine + VIA_REG_TRANSPACE);
drivers/video/fbdev/via/accel.c
406
writel(0x64000000, engine + VIA_REG_TRANSPACE);
drivers/video/fbdev/via/accel.c
407
writel(0x7D000000, engine + VIA_REG_TRANSPACE);
drivers/video/fbdev/via/accel.c
409
writel(0xFE020000, engine + VIA_REG_TRANSET);
drivers/video/fbdev/via/accel.c
410
writel(0x00000000, engine + VIA_REG_TRANSPACE);
drivers/video/fbdev/via/accel.c
435
writel(0x00100000, engine + VIA_REG_CR_TRANSET);
drivers/video/fbdev/via/accel.c
436
writel(vq_high, engine + VIA_REG_CR_TRANSPACE);
drivers/video/fbdev/via/accel.c
437
writel(vq_start_low, engine + VIA_REG_CR_TRANSPACE);
drivers/video/fbdev/via/accel.c
438
writel(vq_end_low, engine + VIA_REG_CR_TRANSPACE);
drivers/video/fbdev/via/accel.c
439
writel(vq_len, engine + VIA_REG_CR_TRANSPACE);
drivers/video/fbdev/via/accel.c
440
writel(0x74301001, engine + VIA_REG_CR_TRANSPACE);
drivers/video/fbdev/via/accel.c
441
writel(0x00000000, engine + VIA_REG_CR_TRANSPACE);
drivers/video/fbdev/via/accel.c
444
writel(0x00FE0000, engine + VIA_REG_TRANSET);
drivers/video/fbdev/via/accel.c
445
writel(0x080003FE, engine + VIA_REG_TRANSPACE);
drivers/video/fbdev/via/accel.c
446
writel(0x0A00027C, engine + VIA_REG_TRANSPACE);
drivers/video/fbdev/via/accel.c
447
writel(0x0B000260, engine + VIA_REG_TRANSPACE);
drivers/video/fbdev/via/accel.c
448
writel(0x0C000274, engine + VIA_REG_TRANSPACE);
drivers/video/fbdev/via/accel.c
449
writel(0x0D000264, engine + VIA_REG_TRANSPACE);
drivers/video/fbdev/via/accel.c
450
writel(0x0E000000, engine + VIA_REG_TRANSPACE);
drivers/video/fbdev/via/accel.c
451
writel(0x0F000020, engine + VIA_REG_TRANSPACE);
drivers/video/fbdev/via/accel.c
452
writel(0x1000027E, engine + VIA_REG_TRANSPACE);
drivers/video/fbdev/via/accel.c
453
writel(0x110002FE, engine + VIA_REG_TRANSPACE);
drivers/video/fbdev/via/accel.c
454
writel(0x200F0060, engine + VIA_REG_TRANSPACE);
drivers/video/fbdev/via/accel.c
456
writel(0x00000006, engine + VIA_REG_TRANSPACE);
drivers/video/fbdev/via/accel.c
457
writel(0x40008C0F, engine + VIA_REG_TRANSPACE);
drivers/video/fbdev/via/accel.c
458
writel(0x44000000, engine + VIA_REG_TRANSPACE);
drivers/video/fbdev/via/accel.c
459
writel(0x45080C04, engine + VIA_REG_TRANSPACE);
drivers/video/fbdev/via/accel.c
460
writel(0x46800408, engine + VIA_REG_TRANSPACE);
drivers/video/fbdev/via/accel.c
462
writel(vq_high, engine + VIA_REG_TRANSPACE);
drivers/video/fbdev/via/accel.c
463
writel(vq_start_low, engine + VIA_REG_TRANSPACE);
drivers/video/fbdev/via/accel.c
464
writel(vq_end_low, engine + VIA_REG_TRANSPACE);
drivers/video/fbdev/via/accel.c
465
writel(vq_len, engine + VIA_REG_TRANSPACE);
drivers/video/fbdev/via/accel.c
470
writel(viapar->shared->cursor_vram_addr, engine + VIA_REG_CURSOR_MODE);
drivers/video/fbdev/via/accel.c
471
writel(0x0, engine + VIA_REG_CURSOR_POS);
drivers/video/fbdev/via/accel.c
472
writel(0x0, engine + VIA_REG_CURSOR_ORG);
drivers/video/fbdev/via/accel.c
473
writel(0x0, engine + VIA_REG_CURSOR_BG);
drivers/video/fbdev/via/accel.c
474
writel(0x0, engine + VIA_REG_CURSOR_FG);
drivers/video/fbdev/via/accel.c
500
writel(temp, viapar->shared->vdev->engine_mmio + VIA_REG_CURSOR_MODE);
drivers/video/fbdev/via/accel.c
91
writel(tmp, engine + 0x08);
drivers/video/fbdev/via/viafbdev.c
778
writel(temp, engine + VIA_REG_CURSOR_ORG);
drivers/video/fbdev/via/viafbdev.c
786
writel(temp, engine + VIA_REG_CURSOR_POS);
drivers/video/fbdev/via/viafbdev.c
806
writel(temp, engine + VIA_REG_CURSOR_MODE);
drivers/video/fbdev/via/viafbdev.c
835
writel(bg_color, engine + VIA_REG_CURSOR_BG);
drivers/video/fbdev/via/viafbdev.c
836
writel(fg_color, engine + VIA_REG_CURSOR_FG);
drivers/video/fbdev/vt8500lcdfb.c
113
writel(0, fbi->regbase);
drivers/video/fbdev/vt8500lcdfb.c
116
writel((((info->var.hsync_len - 1) & 0x3f) << 26)
drivers/video/fbdev/vt8500lcdfb.c
120
writel((((info->var.vsync_len - 1) & 0x3f) << 26)
drivers/video/fbdev/vt8500lcdfb.c
124
writel((((info->var.yres - 1) & 0x400) << 2)
drivers/video/fbdev/vt8500lcdfb.c
126
writel(0x80000000, fbi->regbase + 0x20);
drivers/video/fbdev/vt8500lcdfb.c
127
writel(control0 | (reg_bpp << 1) | 0x100, fbi->regbase);
drivers/video/fbdev/vt8500lcdfb.c
186
writel(0xffffffff ^ (1 << 3), fbi->regbase + 0x3c);
drivers/video/fbdev/vt8500lcdfb.c
190
writel(0xffffffff, fbi->regbase + 0x3c);
drivers/video/fbdev/vt8500lcdfb.c
208
writel((1 << 31)
drivers/video/fbdev/vt8500lcdfb.c
264
writel(0xffffffff, fbi->regbase + 0x38);
drivers/video/fbdev/vt8500lcdfb.c
408
writel(fbi->fb.fix.smem_start >> 22, fbi->regbase + 0x1c);
drivers/video/fbdev/vt8500lcdfb.c
409
writel((fbi->palette_phys & 0xfffffe00) | 1, fbi->regbase + 0x18);
drivers/video/fbdev/vt8500lcdfb.c
423
writel(readl(fbi->regbase) | 1, fbi->regbase);
drivers/video/fbdev/vt8500lcdfb.c
453
writel(0, fbi->regbase);
drivers/video/fbdev/wm8505fb.c
100
writel(v_end, fbi->regbase + WMT_GOVR_TIMING_V_END);
drivers/video/fbdev/wm8505fb.c
101
writel(v_all, fbi->regbase + WMT_GOVR_TIMING_V_ALL);
drivers/video/fbdev/wm8505fb.c
102
writel(v_sync, fbi->regbase + WMT_GOVR_TIMING_V_SYNC);
drivers/video/fbdev/wm8505fb.c
104
writel(1, fbi->regbase + WMT_GOVR_TG);
drivers/video/fbdev/wm8505fb.c
145
writel(fbi->contrast<<16 | fbi->contrast<<8 | fbi->contrast,
drivers/video/fbdev/wm8505fb.c
228
writel(var->xoffset, fbi->regbase + WMT_GOVR_XPAN);
drivers/video/fbdev/wm8505fb.c
229
writel(var->yoffset, fbi->regbase + WMT_GOVR_YPAN);
drivers/video/fbdev/wm8505fb.c
242
writel(0, fbi->regbase + WMT_GOVR_TIMING_V_SYNC);
drivers/video/fbdev/wm8505fb.c
382
writel(0, fbi->regbase);
drivers/video/fbdev/wm8505fb.c
51
writel(0, fbi->regbase + i);
drivers/video/fbdev/wm8505fb.c
54
writel(fbi->fb.fix.smem_start, fbi->regbase + WMT_GOVR_FBADDR);
drivers/video/fbdev/wm8505fb.c
55
writel(fbi->fb.fix.smem_start, fbi->regbase + WMT_GOVR_FBADDR1);
drivers/video/fbdev/wm8505fb.c
62
writel(0x31c, fbi->regbase + WMT_GOVR_COLORSPACE);
drivers/video/fbdev/wm8505fb.c
63
writel(1, fbi->regbase + WMT_GOVR_COLORSPACE1);
drivers/video/fbdev/wm8505fb.c
66
writel(info->var.xres, fbi->regbase + WMT_GOVR_XRES);
drivers/video/fbdev/wm8505fb.c
67
writel(info->var.xres_virtual, fbi->regbase + WMT_GOVR_XRES_VIRTUAL);
drivers/video/fbdev/wm8505fb.c
70
writel(0xf, fbi->regbase + WMT_GOVR_FHI);
drivers/video/fbdev/wm8505fb.c
71
writel(4, fbi->regbase + WMT_GOVR_DVO_SET);
drivers/video/fbdev/wm8505fb.c
72
writel(1, fbi->regbase + WMT_GOVR_MIF_ENABLE);
drivers/video/fbdev/wm8505fb.c
73
writel(1, fbi->regbase + WMT_GOVR_REG_UPDATE);
drivers/video/fbdev/wm8505fb.c
92
writel(0, fbi->regbase + WMT_GOVR_TG);
drivers/video/fbdev/wm8505fb.c
94
writel(h_start, fbi->regbase + WMT_GOVR_TIMING_H_START);
drivers/video/fbdev/wm8505fb.c
95
writel(h_end, fbi->regbase + WMT_GOVR_TIMING_H_END);
drivers/video/fbdev/wm8505fb.c
96
writel(h_all, fbi->regbase + WMT_GOVR_TIMING_H_ALL);
drivers/video/fbdev/wm8505fb.c
97
writel(h_sync, fbi->regbase + WMT_GOVR_TIMING_H_SYNC);
drivers/video/fbdev/wm8505fb.c
99
writel(v_start, fbi->regbase + WMT_GOVR_TIMING_V_START);
drivers/video/fbdev/wmt_ge_rops.c
100
writel(pat, regbase + GE_PAT0C_OFF);
drivers/video/fbdev/wmt_ge_rops.c
101
writel(1, regbase + GE_COMMAND_OFF);
drivers/video/fbdev/wmt_ge_rops.c
102
writel(rect->rop == ROP_XOR ? 0x5a : 0xf0, regbase + GE_ROPCODE_OFF);
drivers/video/fbdev/wmt_ge_rops.c
103
writel(1, regbase + GE_FIRE_OFF);
drivers/video/fbdev/wmt_ge_rops.c
115
writel(p->var.bits_per_pixel > 16 ? 3 :
drivers/video/fbdev/wmt_ge_rops.c
118
writel(p->fix.smem_start, regbase + GE_SRCBASE_OFF);
drivers/video/fbdev/wmt_ge_rops.c
119
writel(p->var.xres_virtual - 1, regbase + GE_SRCDISPW_OFF);
drivers/video/fbdev/wmt_ge_rops.c
120
writel(p->var.yres_virtual - 1, regbase + GE_SRCDISPH_OFF);
drivers/video/fbdev/wmt_ge_rops.c
121
writel(area->sx, regbase + GE_SRCAREAX_OFF);
drivers/video/fbdev/wmt_ge_rops.c
122
writel(area->sy, regbase + GE_SRCAREAY_OFF);
drivers/video/fbdev/wmt_ge_rops.c
123
writel(area->width - 1, regbase + GE_SRCAREAW_OFF);
drivers/video/fbdev/wmt_ge_rops.c
124
writel(area->height - 1, regbase + GE_SRCAREAH_OFF);
drivers/video/fbdev/wmt_ge_rops.c
126
writel(p->fix.smem_start, regbase + GE_DESTBASE_OFF);
drivers/video/fbdev/wmt_ge_rops.c
127
writel(p->var.xres_virtual - 1, regbase + GE_DESTDISPW_OFF);
drivers/video/fbdev/wmt_ge_rops.c
128
writel(p->var.yres_virtual - 1, regbase + GE_DESTDISPH_OFF);
drivers/video/fbdev/wmt_ge_rops.c
129
writel(area->dx, regbase + GE_DESTAREAX_OFF);
drivers/video/fbdev/wmt_ge_rops.c
130
writel(area->dy, regbase + GE_DESTAREAY_OFF);
drivers/video/fbdev/wmt_ge_rops.c
131
writel(area->width - 1, regbase + GE_DESTAREAW_OFF);
drivers/video/fbdev/wmt_ge_rops.c
132
writel(area->height - 1, regbase + GE_DESTAREAH_OFF);
drivers/video/fbdev/wmt_ge_rops.c
134
writel(0xcc, regbase + GE_ROPCODE_OFF);
drivers/video/fbdev/wmt_ge_rops.c
135
writel(1, regbase + GE_COMMAND_OFF);
drivers/video/fbdev/wmt_ge_rops.c
136
writel(1, regbase + GE_FIRE_OFF);
drivers/video/fbdev/wmt_ge_rops.c
171
writel(1, regbase + GE_ENABLE_OFF);
drivers/video/fbdev/wmt_ge_rops.c
89
writel(p->var.bits_per_pixel == 32 ? 3 :
drivers/video/fbdev/wmt_ge_rops.c
91
writel(p->var.bits_per_pixel == 15 ? 1 : 0, regbase + GE_HIGHCOLOR_OFF);
drivers/video/fbdev/wmt_ge_rops.c
92
writel(p->fix.smem_start, regbase + GE_DESTBASE_OFF);
drivers/video/fbdev/wmt_ge_rops.c
93
writel(p->var.xres_virtual - 1, regbase + GE_DESTDISPW_OFF);
drivers/video/fbdev/wmt_ge_rops.c
94
writel(p->var.yres_virtual - 1, regbase + GE_DESTDISPH_OFF);
drivers/video/fbdev/wmt_ge_rops.c
95
writel(rect->dx, regbase + GE_DESTAREAX_OFF);
drivers/video/fbdev/wmt_ge_rops.c
96
writel(rect->dy, regbase + GE_DESTAREAY_OFF);
drivers/video/fbdev/wmt_ge_rops.c
97
writel(rect->width - 1, regbase + GE_DESTAREAW_OFF);
drivers/video/fbdev/wmt_ge_rops.c
98
writel(rect->height - 1, regbase + GE_DESTAREAH_OFF);
drivers/virtio/virtio_mmio.c
103
writel(0, vm_dev->base + VIRTIO_MMIO_DEVICE_FEATURES_SEL);
drivers/virtio/virtio_mmio.c
123
writel(1, vm_dev->base + VIRTIO_MMIO_DRIVER_FEATURES_SEL);
drivers/virtio/virtio_mmio.c
124
writel((u32)(vdev->features >> 32),
drivers/virtio/virtio_mmio.c
127
writel(0, vm_dev->base + VIRTIO_MMIO_DRIVER_FEATURES_SEL);
drivers/virtio/virtio_mmio.c
128
writel((u32)vdev->features,
drivers/virtio/virtio_mmio.c
206
writel(le32_to_cpu(l), base + offset);
drivers/virtio/virtio_mmio.c
210
writel(le32_to_cpu(l), base + offset);
drivers/virtio/virtio_mmio.c
212
writel(le32_to_cpu(l), base + offset + sizeof l);
drivers/virtio/virtio_mmio.c
248
writel(status, vm_dev->base + VIRTIO_MMIO_STATUS);
drivers/virtio/virtio_mmio.c
256
writel(0, vm_dev->base + VIRTIO_MMIO_STATUS);
drivers/virtio/virtio_mmio.c
270
writel(vq->index, vm_dev->base + VIRTIO_MMIO_QUEUE_NOTIFY);
drivers/virtio/virtio_mmio.c
279
writel(data, vm_dev->base + VIRTIO_MMIO_QUEUE_NOTIFY);
drivers/virtio/virtio_mmio.c
294
writel(status, vm_dev->base + VIRTIO_MMIO_INTERRUPT_ACK);
drivers/virtio/virtio_mmio.c
317
writel(index, vm_dev->base + VIRTIO_MMIO_QUEUE_SEL);
drivers/virtio/virtio_mmio.c
319
writel(0, vm_dev->base + VIRTIO_MMIO_QUEUE_PFN);
drivers/virtio/virtio_mmio.c
321
writel(0, vm_dev->base + VIRTIO_MMIO_QUEUE_READY);
drivers/virtio/virtio_mmio.c
365
writel(index, vm_dev->base + VIRTIO_MMIO_QUEUE_SEL);
drivers/virtio/virtio_mmio.c
391
writel(virtqueue_get_vring_size(vq), vm_dev->base + VIRTIO_MMIO_QUEUE_NUM);
drivers/virtio/virtio_mmio.c
408
writel(PAGE_SIZE, vm_dev->base + VIRTIO_MMIO_QUEUE_ALIGN);
drivers/virtio/virtio_mmio.c
409
writel(q_pfn, vm_dev->base + VIRTIO_MMIO_QUEUE_PFN);
drivers/virtio/virtio_mmio.c
414
writel((u32)addr, vm_dev->base + VIRTIO_MMIO_QUEUE_DESC_LOW);
drivers/virtio/virtio_mmio.c
415
writel((u32)(addr >> 32),
drivers/virtio/virtio_mmio.c
419
writel((u32)addr, vm_dev->base + VIRTIO_MMIO_QUEUE_AVAIL_LOW);
drivers/virtio/virtio_mmio.c
420
writel((u32)(addr >> 32),
drivers/virtio/virtio_mmio.c
424
writel((u32)addr, vm_dev->base + VIRTIO_MMIO_QUEUE_USED_LOW);
drivers/virtio/virtio_mmio.c
425
writel((u32)(addr >> 32),
drivers/virtio/virtio_mmio.c
428
writel(1, vm_dev->base + VIRTIO_MMIO_QUEUE_READY);
drivers/virtio/virtio_mmio.c
437
writel(0, vm_dev->base + VIRTIO_MMIO_QUEUE_PFN);
drivers/virtio/virtio_mmio.c
439
writel(0, vm_dev->base + VIRTIO_MMIO_QUEUE_READY);
drivers/virtio/virtio_mmio.c
499
writel(id, vm_dev->base + VIRTIO_MMIO_SHM_SEL);
drivers/virtio/virtio_mmio.c
551
writel(PAGE_SIZE, vm_dev->base + VIRTIO_MMIO_GUEST_PAGE_SIZE);
drivers/virtio/virtio_mmio.c
622
writel(PAGE_SIZE, vm_dev->base + VIRTIO_MMIO_GUEST_PAGE_SIZE);
drivers/virtio/virtio_mmio.c
99
writel(1, vm_dev->base + VIRTIO_MMIO_DEVICE_FEATURES_SEL);
drivers/w1/masters/sgi_w1.c
49
writel(MCR_PACK(520, 65), dev->mcr);
drivers/w1/masters/sgi_w1.c
66
writel(MCR_PACK(6, 13), dev->mcr);
drivers/w1/masters/sgi_w1.c
68
writel(MCR_PACK(80, 30), dev->mcr);
drivers/watchdog/airoha_wdt.c
61
writel(val, airoha_wdt->base + TIMER_CTRL);
drivers/watchdog/airoha_wdt.c
63
writel(val, airoha_wdt->base + WDT_TIMER_LOAD_VALUE);
drivers/watchdog/airoha_wdt.c
75
writel(val, airoha_wdt->base + TIMER_CTRL);
drivers/watchdog/airoha_wdt.c
87
writel(val, airoha_wdt->base + WDT_RELOAD);
drivers/watchdog/armada_37xx_wdt.c
100
writel(val & 0xffffffff, dev->reg + CNTR_COUNT_LOW(id));
drivers/watchdog/armada_37xx_wdt.c
101
writel(val >> 32, dev->reg + CNTR_COUNT_HIGH(id));
drivers/watchdog/armada_37xx_wdt.c
110
writel(reg, dev->reg + CNTR_CTRL(id));
drivers/watchdog/armada_37xx_wdt.c
119
writel(reg, dev->reg + CNTR_CTRL(id));
drivers/watchdog/armada_37xx_wdt.c
141
writel(reg, dev->reg + CNTR_CTRL(id));
drivers/watchdog/aspeed_wdt.c
177
writel(0, wdt->base + WDT_CTRL);
drivers/watchdog/aspeed_wdt.c
178
writel(count, wdt->base + WDT_RELOAD_VALUE);
drivers/watchdog/aspeed_wdt.c
179
writel(WDT_RESTART_MAGIC, wdt->base + WDT_RESTART);
drivers/watchdog/aspeed_wdt.c
180
writel(wdt->ctrl, wdt->base + WDT_CTRL);
drivers/watchdog/aspeed_wdt.c
197
writel(wdt->ctrl, wdt->base + WDT_CTRL);
drivers/watchdog/aspeed_wdt.c
206
writel(WDT_RESTART_MAGIC, wdt->base + WDT_RESTART);
drivers/watchdog/aspeed_wdt.c
221
writel(actual * WDT_RATE_1MHZ, wdt->base + WDT_RELOAD_VALUE);
drivers/watchdog/aspeed_wdt.c
222
writel(WDT_RESTART_MAGIC, wdt->base + WDT_RESTART);
drivers/watchdog/aspeed_wdt.c
242
writel(wdt->ctrl, wdt->base + WDT_CTRL);
drivers/watchdog/aspeed_wdt.c
332
writel(WDT_CLEAR_TIMEOUT_AND_BOOT_CODE_SELECTION,
drivers/watchdog/aspeed_wdt.c
511
writel(reg, wdt->base + WDT_RESET_WIDTH);
drivers/watchdog/aspeed_wdt.c
519
writel(reg, wdt->base + WDT_RESET_WIDTH);
drivers/watchdog/aspeed_wdt.c
524
writel(reset_mask[i], wdt->base + WDT_RESET_MASK1 + i * 4);
drivers/watchdog/aspeed_wdt.c
551
writel(duration - 1, wdt->base + WDT_RESET_WIDTH);
drivers/watchdog/dw_wdt.c
117
writel(val, dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);
drivers/watchdog/dw_wdt.c
192
writel(WDOG_COUNTER_RESTART_KICK_VALUE, dw_wdt->regs +
drivers/watchdog/dw_wdt.c
225
writel(top_val | top_val << WDOG_TIMEOUT_RANGE_TOPINIT_SHIFT,
drivers/watchdog/dw_wdt.c
271
writel(val, dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);
drivers/watchdog/dw_wdt.c
305
writel(0, dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET);
drivers/watchdog/dw_wdt.c
308
writel(WDOG_COUNTER_RESTART_KICK_VALUE,
drivers/watchdog/dw_wdt.c
405
writel(dw_wdt->timeout, dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET);
drivers/watchdog/dw_wdt.c
406
writel(dw_wdt->control, dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);
drivers/watchdog/ep93xx_wdt.c
49
writel(0xaaaa, priv->mmio + EP93XX_WATCHDOG);
drivers/watchdog/ep93xx_wdt.c
58
writel(0xaa55, priv->mmio + EP93XX_WATCHDOG);
drivers/watchdog/ep93xx_wdt.c
67
writel(0x5555, priv->mmio + EP93XX_WATCHDOG);
drivers/watchdog/ftwdt010_wdt.c
170
writel(reg, gwdt->base + FTWDT010_WDCR);
drivers/watchdog/ftwdt010_wdt.c
200
writel(reg, gwdt->base + FTWDT010_WDCR);
drivers/watchdog/ftwdt010_wdt.c
213
writel(reg, gwdt->base + FTWDT010_WDCR);
drivers/watchdog/ftwdt010_wdt.c
56
writel(timeout * WDT_CLOCK, gwdt->base + FTWDT010_WDLOAD);
drivers/watchdog/ftwdt010_wdt.c
57
writel(WDRESTART_MAGIC, gwdt->base + FTWDT010_WDRESTART);
drivers/watchdog/ftwdt010_wdt.c
60
writel(enable, gwdt->base + FTWDT010_WDCR);
drivers/watchdog/ftwdt010_wdt.c
64
writel(enable, gwdt->base + FTWDT010_WDCR);
drivers/watchdog/ftwdt010_wdt.c
79
writel(0, gwdt->base + FTWDT010_WDCR);
drivers/watchdog/ftwdt010_wdt.c
88
writel(WDRESTART_MAGIC, gwdt->base + FTWDT010_WDRESTART);
drivers/watchdog/i6300esb.c
170
writel(val, ESB_TIMER1_REG(edev));
drivers/watchdog/i6300esb.c
174
writel(val, ESB_TIMER2_REG(edev));
drivers/watchdog/iTCO_wdt.c
209
writel(val32, p->gcs_pmc);
drivers/watchdog/imgpdc_wdt.c
106
writel(val, wdt->base + PDC_WDT_CONFIG);
drivers/watchdog/imgpdc_wdt.c
121
writel(val, wdt->base + PDC_WDT_CONFIG);
drivers/watchdog/imgpdc_wdt.c
146
writel(val, wdt->base + PDC_WDT_CONFIG);
drivers/watchdog/imgpdc_wdt.c
157
writel(0x1, wdt->base + PDC_WDT_SOFT_RESET);
drivers/watchdog/imgpdc_wdt.c
93
writel(PDC_WDT_TICKLE1_MAGIC, wdt->base + PDC_WDT_TICKLE1);
drivers/watchdog/imgpdc_wdt.c
94
writel(PDC_WDT_TICKLE2_MAGIC, wdt->base + PDC_WDT_TICKLE2);
drivers/watchdog/imx7ulp_wdt.c
110
writel(UNLOCK, wdt->base + WDOG_CNT);
drivers/watchdog/imx7ulp_wdt.c
115
writel(val | WDOG_CS_EN, wdt->base + WDOG_CS);
drivers/watchdog/imx7ulp_wdt.c
117
writel(val & ~WDOG_CS_EN, wdt->base + WDOG_CS);
drivers/watchdog/imx7ulp_wdt.c
151
writel(REFRESH, wdt->base + WDOG_CNT);
drivers/watchdog/imx7ulp_wdt.c
172
writel(UNLOCK, wdt->base + WDOG_CNT);
drivers/watchdog/imx7ulp_wdt.c
176
writel(toval, wdt->base + WDOG_TOVAL);
drivers/watchdog/imx7ulp_wdt.c
252
writel(UNLOCK, wdt->base + WDOG_CNT);
drivers/watchdog/imx7ulp_wdt.c
266
writel(timeout, wdt->base + WDOG_TOVAL);
drivers/watchdog/imx7ulp_wdt.c
267
writel(cs, wdt->base + WDOG_CS);
drivers/watchdog/keembay_wdt.c
66
writel(WDT_UNLOCK, wdt->base + TIM_SAFE);
drivers/watchdog/keembay_wdt.c
67
writel(val, wdt->base + offset);
drivers/watchdog/loongson1_wdt.c
104
writel(drvdata->pdata->wdt_en_bit, drvdata->base + WDT_EN);
drivers/watchdog/loongson1_wdt.c
105
writel(0x1, drvdata->base + drvdata->pdata->timer_offset);
drivers/watchdog/loongson1_wdt.c
106
writel(0x1, drvdata->base + drvdata->pdata->set_offset);
drivers/watchdog/loongson1_wdt.c
59
writel(0x1, drvdata->base + drvdata->pdata->set_offset);
drivers/watchdog/loongson1_wdt.c
74
writel(counts, drvdata->base + drvdata->pdata->timer_offset);
drivers/watchdog/loongson1_wdt.c
83
writel(drvdata->pdata->wdt_en_bit, drvdata->base + WDT_EN);
drivers/watchdog/loongson1_wdt.c
94
writel(val, drvdata->base + WDT_EN);
drivers/watchdog/lpc18xx_wdt.c
110
writel(val, lpc18xx_wdt->base + LPC18XX_WDT_TC);
drivers/watchdog/lpc18xx_wdt.c
144
writel(val, lpc18xx_wdt->base + LPC18XX_WDT_MOD);
drivers/watchdog/lpc18xx_wdt.c
171
writel(val, lpc18xx_wdt->base + LPC18XX_WDT_MOD);
drivers/watchdog/lpc18xx_wdt.c
173
writel(LPC18XX_WDT_FEED_MAGIC1, lpc18xx_wdt->base + LPC18XX_WDT_FEED);
drivers/watchdog/lpc18xx_wdt.c
174
writel(LPC18XX_WDT_FEED_MAGIC2, lpc18xx_wdt->base + LPC18XX_WDT_FEED);
drivers/watchdog/lpc18xx_wdt.c
176
writel(LPC18XX_WDT_FEED_MAGIC1, lpc18xx_wdt->base + LPC18XX_WDT_FEED);
drivers/watchdog/lpc18xx_wdt.c
177
writel(LPC18XX_WDT_FEED_MAGIC1, lpc18xx_wdt->base + LPC18XX_WDT_FEED);
drivers/watchdog/lpc18xx_wdt.c
71
writel(LPC18XX_WDT_FEED_MAGIC1, lpc18xx_wdt->base + LPC18XX_WDT_FEED);
drivers/watchdog/lpc18xx_wdt.c
72
writel(LPC18XX_WDT_FEED_MAGIC2, lpc18xx_wdt->base + LPC18XX_WDT_FEED);
drivers/watchdog/meson_gxbb_wdt.c
213
writel(ctrl_reg, data->reg_base + GXBB_WDT_CTRL_REG);
drivers/watchdog/meson_gxbb_wdt.c
55
writel(readl(data->reg_base + GXBB_WDT_CTRL_REG) | GXBB_WDT_CTRL_EN,
drivers/watchdog/meson_gxbb_wdt.c
65
writel(readl(data->reg_base + GXBB_WDT_CTRL_REG) & ~GXBB_WDT_CTRL_EN,
drivers/watchdog/meson_gxbb_wdt.c
75
writel(0, data->reg_base + GXBB_WDT_RSET_REG);
drivers/watchdog/meson_gxbb_wdt.c
93
writel(tcnt, data->reg_base + GXBB_WDT_TCNT_REG);
drivers/watchdog/meson_wdt.c
116
writel(reg, meson_wdt->wdt_base + MESON_WDT_TC);
drivers/watchdog/meson_wdt.c
131
writel(reg, meson_wdt->wdt_base + MESON_WDT_TC);
drivers/watchdog/meson_wdt.c
70
writel(tc_reboot, meson_wdt->wdt_base + MESON_WDT_TC);
drivers/watchdog/meson_wdt.c
81
writel(0, meson_wdt->wdt_base + MESON_WDT_RESET);
drivers/watchdog/meson_wdt.c
95
writel(reg, meson_wdt->wdt_base + MESON_WDT_TC);
drivers/watchdog/moxart_wdt.c
38
writel(1, moxart_wdt->base + REG_COUNT);
drivers/watchdog/moxart_wdt.c
39
writel(0x5ab9, moxart_wdt->base + REG_MODE);
drivers/watchdog/moxart_wdt.c
40
writel(0x03, moxart_wdt->base + REG_ENABLE);
drivers/watchdog/moxart_wdt.c
49
writel(0, moxart_wdt->base + REG_ENABLE);
drivers/watchdog/moxart_wdt.c
58
writel(moxart_wdt->clock_frequency * wdt_dev->timeout,
drivers/watchdog/moxart_wdt.c
60
writel(0x5ab9, moxart_wdt->base + REG_MODE);
drivers/watchdog/moxart_wdt.c
61
writel(0x03, moxart_wdt->base + REG_ENABLE);
drivers/watchdog/mtk_wdt.c
147
writel(tmp, data->wdt_base + WDT_SWSYSRST_EN);
drivers/watchdog/mtk_wdt.c
169
writel(tmp, data->wdt_base + WDT_SWSYSRST);
drivers/watchdog/mtk_wdt.c
240
writel(reg | WDT_MODE_KEY, wdt_base + WDT_MODE);
drivers/watchdog/mtk_wdt.c
243
writel(WDT_SWRST_KEY, wdt_base + WDT_SWRST);
drivers/watchdog/npcm_wdt.c
105
writel(0, wdt->reg);
drivers/watchdog/npcm_wdt.c
159
writel(NPCM_WTR | NPCM_WTRE | NPCM_WTE, wdt->reg);
drivers/watchdog/npcm_wdt.c
61
writel(val | NPCM_WTR, wdt->reg);
drivers/watchdog/npcm_wdt.c
96
writel(val, wdt->reg);
drivers/watchdog/orion_wdt.c
187
writel(dev->clk_rate * wdt_dev->timeout,
drivers/watchdog/orion_wdt.c
190
writel(dev->clk_rate * (wdt_dev->timeout - wdt_dev->pretimeout),
drivers/watchdog/orion_wdt.c
202
writel(dev->clk_rate * wdt_dev->timeout,
drivers/watchdog/orion_wdt.c
205
writel(dev->clk_rate * (wdt_dev->timeout - wdt_dev->pretimeout),
drivers/watchdog/orion_wdt.c
220
writel(reg, dev->rstout);
drivers/watchdog/orion_wdt.c
232
writel(dev->clk_rate * wdt_dev->timeout,
drivers/watchdog/orion_wdt.c
247
writel(reg, dev->rstout);
drivers/watchdog/orion_wdt.c
256
writel(dev->clk_rate * wdt_dev->timeout,
drivers/watchdog/orion_wdt.c
301
writel(reg, dev->rstout);
drivers/watchdog/orion_wdt.c
320
writel(reg, dev->rstout);
drivers/watchdog/pic32-dmt.c
117
writel(RESETCON_DMT_TIMEOUT, PIC32_CLR(rst_base));
drivers/watchdog/pic32-dmt.c
48
writel(DMT_ON, PIC32_SET(dmt->regs + DMTCON_REG));
drivers/watchdog/pic32-dmt.c
53
writel(DMT_ON, PIC32_CLR(dmt->regs + DMTCON_REG));
drivers/watchdog/pic32-dmt.c
79
writel(DMT_STEP1_KEY << 8, dmt->regs + DMTPRECLR_REG);
drivers/watchdog/pic32-dmt.c
89
writel(DMT_STEP2_KEY, dmt->regs + DMTCLR_REG);
drivers/watchdog/pic32-wdt.c
109
writel(WDTCON_ON, PIC32_SET(wdt->regs + WDTCON_REG));
drivers/watchdog/pic32-wdt.c
119
writel(WDTCON_ON, PIC32_CLR(wdt->regs + WDTCON_REG));
drivers/watchdog/pic32-wdt.c
66
writel(RESETCON_WDT_TIMEOUT, PIC32_CLR(wdt->rst_base));
drivers/watchdog/pnx4008_wdt.c
100
writel(wdd->timeout * WDOG_COUNTER_RATE, WDTIM_MATCH0(wdt_base));
drivers/watchdog/pnx4008_wdt.c
102
writel(COUNT_ENAB | DEBUG_EN, WDTIM_CTRL(wdt_base));
drivers/watchdog/pnx4008_wdt.c
112
writel(0, WDTIM_CTRL(wdt_base)); /*stop counter */
drivers/watchdog/pnx4008_wdt.c
145
writel(EXT_MATCH0, WDTIM_EMR(wdt_base));
drivers/watchdog/pnx4008_wdt.c
147
writel(M_RES1, WDTIM_MCTRL(wdt_base));
drivers/watchdog/pnx4008_wdt.c
150
writel(13000, WDTIM_PULSE(wdt_base));
drivers/watchdog/pnx4008_wdt.c
151
writel(M_RES2 | RESFRC1 | RESFRC2, WDTIM_MCTRL(wdt_base));
drivers/watchdog/pnx4008_wdt.c
88
writel(RESET_COUNT, WDTIM_CTRL(wdt_base));
drivers/watchdog/pnx4008_wdt.c
93
writel(M_RES2 | STOP_COUNT0 | RESET_COUNT0, WDTIM_MCTRL(wdt_base));
drivers/watchdog/pnx4008_wdt.c
95
writel(MATCH_OUTPUT_HIGH, WDTIM_EMR(wdt_base));
drivers/watchdog/pnx4008_wdt.c
97
writel(MATCH_INT, WDTIM_INT(wdt_base));
drivers/watchdog/pnx4008_wdt.c
99
writel(0xFFFF, WDTIM_PULSE(wdt_base));
drivers/watchdog/qcom-wdt.c
129
writel(0, wdt_addr(wdt, WDT_EN));
drivers/watchdog/qcom-wdt.c
130
writel(1, wdt_addr(wdt, WDT_RST));
drivers/watchdog/qcom-wdt.c
131
writel(timeout, wdt_addr(wdt, WDT_BARK_TIME));
drivers/watchdog/qcom-wdt.c
132
writel(timeout, wdt_addr(wdt, WDT_BITE_TIME));
drivers/watchdog/qcom-wdt.c
133
writel(QCOM_WDT_ENABLE, wdt_addr(wdt, WDT_EN));
drivers/watchdog/qcom-wdt.c
79
writel(0, wdt_addr(wdt, WDT_EN));
drivers/watchdog/qcom-wdt.c
80
writel(1, wdt_addr(wdt, WDT_RST));
drivers/watchdog/qcom-wdt.c
81
writel(bark * wdt->rate, wdt_addr(wdt, WDT_BARK_TIME));
drivers/watchdog/qcom-wdt.c
82
writel(wdd->timeout * wdt->rate, wdt_addr(wdt, WDT_BITE_TIME));
drivers/watchdog/qcom-wdt.c
83
writel(QCOM_WDT_ENABLE, wdt_addr(wdt, WDT_EN));
drivers/watchdog/qcom-wdt.c
91
writel(0, wdt_addr(wdt, WDT_EN));
drivers/watchdog/qcom-wdt.c
99
writel(1, wdt_addr(wdt, WDT_RST));
drivers/watchdog/rc32434_wdt.c
133
writel(0, &wdt_reg->wtcount);
drivers/watchdog/rc32434_wdt.c
69
writel((readl(&addr) | or) & ~nand, &addr)
drivers/watchdog/rc32434_wdt.c
81
writel(SEC2WTCOMP(timeout), &wdt_reg->wtcompare);
drivers/watchdog/rc32434_wdt.c
94
writel(0, &wdt_reg->wtcount);
drivers/watchdog/rtd119x_wdt.c
41
writel(val, data->base + RTD119X_TCWCR);
drivers/watchdog/rtd119x_wdt.c
54
writel(val, data->base + RTD119X_TCWCR);
drivers/watchdog/rtd119x_wdt.c
72
writel(val * clk_get_rate(data->clk), data->base + RTD119X_TCWOV);
drivers/watchdog/rzn1_wdt.c
56
writel(0, wdt->base + RZN1_WDT_RETRIGGER);
drivers/watchdog/rzn1_wdt.c
77
writel(val, wdt->base + RZN1_WDT_RETRIGGER);
drivers/watchdog/rzv2h_wdt.c
103
writel(reg & ~WDTDCR_WDTSTOPCTRL, priv->wdtdcr + WDTDCR);
drivers/watchdog/rzv2h_wdt.c
96
writel(reg | WDTDCR_WDTSTOPCTRL, priv->wdtdcr + WDTDCR);
drivers/watchdog/s32g_wdt.c
106
writel(val, S32G_SWT_CR(wdev->base));
drivers/watchdog/s32g_wdt.c
115
writel(wdog_sec_to_count(wdev, timeout), S32G_SWT_TO(wdev->base));
drivers/watchdog/s32g_wdt.c
173
writel(val, S32G_SWT_TO(wdev->base));
drivers/watchdog/s32g_wdt.c
202
writel(val, S32G_SWT_CR(wdev->base));
drivers/watchdog/s32g_wdt.c
77
writel(S32G_WDT_SEQ1, S32G_SWT_SR(wdev->base));
drivers/watchdog/s32g_wdt.c
78
writel(S32G_WDT_SEQ2, S32G_SWT_SR(wdev->base));
drivers/watchdog/s32g_wdt.c
92
writel(val, S32G_SWT_CR(wdev->base));
drivers/watchdog/s3c2410_wdt.c
494
writel(wtcon, wdt->reg_base + S3C2410_WTCON);
drivers/watchdog/s3c2410_wdt.c
503
writel(wdt->count, wdt->reg_base + S3C2410_WTCNT);
drivers/watchdog/s3c2410_wdt.c
515
writel(wtcon, wdt->reg_base + S3C2410_WTCON);
drivers/watchdog/s3c2410_wdt.c
554
writel(wdt->count, wdt->reg_base + S3C2410_WTDAT);
drivers/watchdog/s3c2410_wdt.c
555
writel(wdt->count, wdt->reg_base + S3C2410_WTCNT);
drivers/watchdog/s3c2410_wdt.c
556
writel(wtcon, wdt->reg_base + S3C2410_WTCON);
drivers/watchdog/s3c2410_wdt.c
605
writel(count, wdt->reg_base + S3C2410_WTDAT);
drivers/watchdog/s3c2410_wdt.c
606
writel(wtcon, wdt->reg_base + S3C2410_WTCON);
drivers/watchdog/s3c2410_wdt.c
620
writel(0, wdt_base + S3C2410_WTCON);
drivers/watchdog/s3c2410_wdt.c
623
writel(0x80, wdt_base + S3C2410_WTCNT);
drivers/watchdog/s3c2410_wdt.c
624
writel(0x80, wdt_base + S3C2410_WTDAT);
drivers/watchdog/s3c2410_wdt.c
627
writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV16 |
drivers/watchdog/s3c2410_wdt.c
671
writel(0x1, wdt->reg_base + S3C2410_WTCLRINT);
drivers/watchdog/s3c2410_wdt.c
913
writel(wdt->wtdat_save, wdt->reg_base + S3C2410_WTDAT);
drivers/watchdog/s3c2410_wdt.c
914
writel(wdt->wtdat_save, wdt->reg_base + S3C2410_WTCNT);/* Reset count */
drivers/watchdog/s3c2410_wdt.c
915
writel(wdt->wtcon_save, wdt->reg_base + S3C2410_WTCON);
drivers/watchdog/sbsa_gwdt.c
145
writel((u32)val, gwdt->control_base + SBSA_GWDT_WOR);
drivers/watchdog/sbsa_gwdt.c
229
writel(0, gwdt->refresh_base + SBSA_GWDT_WRR);
drivers/watchdog/sbsa_gwdt.c
253
writel(SBSA_GWDT_WCS_EN, gwdt->control_base + SBSA_GWDT_WCS);
drivers/watchdog/sbsa_gwdt.c
263
writel(0, gwdt->control_base + SBSA_GWDT_WCS);
drivers/watchdog/sbsa_gwdt.c
364
writel(0, rf_base + SBSA_GWDT_WRR);
drivers/watchdog/sp5100_tco.c
116
writel(val, SP5100_WDT_CONTROL(tco->tcobase));
drivers/watchdog/sp5100_tco.c
120
writel(val, SP5100_WDT_CONTROL(tco->tcobase));
drivers/watchdog/sp5100_tco.c
132
writel(val, SP5100_WDT_CONTROL(tco->tcobase));
drivers/watchdog/sp5100_tco.c
144
writel(val, SP5100_WDT_CONTROL(tco->tcobase));
drivers/watchdog/sp5100_tco.c
155
writel(t, SP5100_WDT_COUNT(tco->tcobase));
drivers/watchdog/sp5100_tco.c
315
writel(val, SP5100_WDT_CONTROL(tco->tcobase));
drivers/watchdog/starfive-wdt.c
210
writel(wdt->variant->unlock_key, wdt->base + wdt->variant->unlock);
drivers/watchdog/starfive-wdt.c
216
writel(~wdt->variant->unlock_key, wdt->base + wdt->variant->unlock);
drivers/watchdog/starfive-wdt.c
227
writel(val, wdt->base + wdt->variant->control);
drivers/watchdog/starfive-wdt.c
257
writel(STARFIVE_WDT_INTCLR, wdt->base + wdt->variant->int_clr);
drivers/watchdog/starfive-wdt.c
264
writel(val, wdt->base + wdt->variant->load);
drivers/watchdog/starfive-wdt.c
279
writel(val, wdt->base + wdt->variant->enable);
drivers/watchdog/starfive-wdt.c
289
writel(val, wdt->base + wdt->variant->enable);
drivers/watchdog/starfive-wdt.c
298
writel(0x1, wdt->base + wdt->variant->reload);
drivers/watchdog/sunplus_wdt.c
105
writel(WDT_RESUME, base + WDT_CTRL);
drivers/watchdog/sunplus_wdt.c
57
writel(WDT_STOP, base + WDT_CTRL);
drivers/watchdog/sunplus_wdt.c
58
writel(WDT_UNLOCK, base + WDT_CTRL);
drivers/watchdog/sunplus_wdt.c
59
writel(0x0001, base + WDT_CNT);
drivers/watchdog/sunplus_wdt.c
60
writel(WDT_LOCK, base + WDT_CTRL);
drivers/watchdog/sunplus_wdt.c
61
writel(WDT_RESUME, base + WDT_CTRL);
drivers/watchdog/sunplus_wdt.c
74
writel(WDT_CONMAX, base + WDT_CTRL);
drivers/watchdog/sunplus_wdt.c
76
writel(WDT_UNLOCK, base + WDT_CTRL);
drivers/watchdog/sunplus_wdt.c
83
writel(count, base + WDT_CNT);
drivers/watchdog/sunplus_wdt.c
84
writel(WDT_LOCK, base + WDT_CTRL);
drivers/watchdog/sunplus_wdt.c
95
writel(WDT_STOP, base + WDT_CTRL);
drivers/watchdog/sunxi_wdt.c
102
writel(val, wdt_base + regs->wdt_mode);
drivers/watchdog/sunxi_wdt.c
108
writel(WDT_CTRL_RELOAD, wdt_base + regs->wdt_ctrl);
drivers/watchdog/sunxi_wdt.c
115
writel(val, wdt_base + regs->wdt_mode);
drivers/watchdog/sunxi_wdt.c
126
writel(WDT_CTRL_RELOAD, wdt_base + regs->wdt_ctrl);
drivers/watchdog/sunxi_wdt.c
148
writel(reg, wdt_base + regs->wdt_mode);
drivers/watchdog/sunxi_wdt.c
161
writel(regs->wdt_key_val, wdt_base + regs->wdt_mode);
drivers/watchdog/sunxi_wdt.c
184
writel(reg, wdt_base + regs->wdt_cfg);
drivers/watchdog/sunxi_wdt.c
190
writel(reg, wdt_base + regs->wdt_mode);
drivers/watchdog/sunxi_wdt.c
95
writel(val, wdt_base + regs->wdt_cfg);
drivers/watchdog/tegra_wdt.c
103
writel(val, wdt->wdt_regs + WDT_CFG);
drivers/watchdog/tegra_wdt.c
105
writel(WDT_CMD_START_COUNTER, wdt->wdt_regs + WDT_CMD);
drivers/watchdog/tegra_wdt.c
114
writel(WDT_UNLOCK_PATTERN, wdt->wdt_regs + WDT_UNLOCK);
drivers/watchdog/tegra_wdt.c
115
writel(WDT_CMD_DISABLE_COUNTER, wdt->wdt_regs + WDT_CMD);
drivers/watchdog/tegra_wdt.c
116
writel(0, wdt->tmr_regs + TIMER_PTV);
drivers/watchdog/tegra_wdt.c
125
writel(WDT_CMD_START_COUNTER, wdt->wdt_regs + WDT_CMD);
drivers/watchdog/tegra_wdt.c
91
writel(val, wdt->tmr_regs + TIMER_PTV);
drivers/watchdog/via_wdt.c
112
writel(wdd->timeout, wdt_mem + VIA_WDT_COUNT);
drivers/watchdog/via_wdt.c
113
writel(ctl | VIA_WDT_RUNNING | VIA_WDT_TRIGGER, wdt_mem);
drivers/watchdog/via_wdt.c
123
writel(ctl & ~VIA_WDT_RUNNING, wdt_mem);
drivers/watchdog/via_wdt.c
130
writel(new_timeout, wdt_mem + VIA_WDT_COUNT);
drivers/watchdog/via_wdt.c
79
writel(ctl | VIA_WDT_TRIGGER, wdt_mem);
drivers/watchdog/visconti_wdt.c
45
writel(priv->div, priv->base + WDT_DIV);
drivers/watchdog/visconti_wdt.c
46
writel(0, priv->base + WDT_MIN);
drivers/watchdog/visconti_wdt.c
47
writel(timeout, priv->base + WDT_MAX);
drivers/watchdog/visconti_wdt.c
48
writel(0, priv->base + WDT_CTL);
drivers/watchdog/visconti_wdt.c
49
writel(WDT_CMD_START_STOP, priv->base + WDT_CMD);
drivers/watchdog/visconti_wdt.c
58
writel(1, priv->base + WDT_CTL);
drivers/watchdog/visconti_wdt.c
59
writel(WDT_CMD_START_STOP, priv->base + WDT_CMD);
drivers/watchdog/visconti_wdt.c
68
writel(WDT_CMD_CLEAR, priv->base + WDT_CMD);
drivers/watchdog/visconti_wdt.c
95
writel(WDT_CMD_CLEAR, priv->base + WDT_CMD);
drivers/watchdog/visconti_wdt.c
96
writel(val, priv->base + WDT_MAX);
include/asm-generic/io.h
286
#ifndef writel
include/asm-generic/io.h
287
#define writel writel
include/asm-generic/io.h
940
writel(value, addr);
include/asm-generic/io.h
992
writel(swab32(value), addr);
include/linux/amba/sp810.h
56
writel(0x2, base + SCCTRL);
include/linux/amba/sp810.h
59
writel(0, base + SCSYSSTAT);
include/linux/coresight.h
531
writel(val, csa->base + offset);
include/linux/io-64-nonatomic-hi-lo.h
21
writel(val >> 32, addr + 4);
include/linux/io-64-nonatomic-hi-lo.h
22
writel(val, addr);
include/linux/io-64-nonatomic-lo-hi.h
21
writel(val, addr);
include/linux/io-64-nonatomic-lo-hi.h
22
writel(val >> 32, addr + 4);
include/linux/iosys-map.h
369
u32: writel(val__, vaddr_iomem__), \
include/linux/irq.h
1230
writel(val, gc->reg_base + reg_offset);
include/linux/litex.h
16
writel((u32 __force)cpu_to_le32(val), addr);
include/linux/qed/qed_if.h
441
#define DIRECT_REG_WR(reg_addr, val) writel((u32)val, \
include/linux/reset/bcm63xx_pmb.h
40
writel(cmd, master + PMB_CTRL);
include/linux/reset/bcm63xx_pmb.h
74
writel(val, master + PMB_WR_DATA);
include/linux/sm501.h
166
#define smc501_writel(val, addr) writel(val, addr)
include/linux/soc/qcom/geni-se.h
349
writel(m_cmd, se->base + SE_GENI_M_CMD0);
include/linux/soc/qcom/geni-se.h
369
writel(s_cmd, se->base + SE_GENI_S_CMD0);
include/media/drv-intf/saa7146.h
22
#define saa7146_write(sxy,adr,dat) writel((dat),(sxy->mem+(adr)))
include/sound/hdaudio.h
460
#define snd_hdac_reg_writel(bus, addr, val) writel(val, addr)
include/sound/hdaudio.h
508
writel(((readl(addr + reg) & ~(mask)) | (val)), addr + reg)
include/ufs/ufshcd.h
1266
writel((val), (hba)->mcq_base + (reg))
include/ufs/ufshcd.h
1276
writel((val), (hba)->mmio_base + (reg))
include/video/tgafb.h
230
writel(v, par->tga_regs_base +r);
lib/iomap.c
199
#define mmio_write32be(val,port) writel(swab32(val),port)
lib/iomap.c
225
IO_COND(addr, outl(val,port), writel(val, addr));
lib/stmp_device.c
30
writel(mask, addr + STMP_OFFSET_REG_CLR);
lib/stmp_device.c
49
writel(STMP_MODULE_CLKGATE, reset_addr + STMP_OFFSET_REG_CLR);
lib/stmp_device.c
52
writel(STMP_MODULE_SFTRST, reset_addr + STMP_OFFSET_REG_SET);
rust/helpers/io.c
56
writel(value, addr);
sound/arm/aaci.c
1037
writel(0, aaci->base + AACI_MAINCR);
sound/arm/aaci.c
121
writel((reg << 12) | (1 << 19), aaci->base + AACI_SL1TX);
sound/arm/aaci.c
194
writel(ICLR_RXOEC1 << channel, aaci->base + AACI_INTCLR);
sound/arm/aaci.c
199
writel(ICLR_RXTOFEC1 << channel, aaci->base + AACI_INTCLR);
sound/arm/aaci.c
209
writel(0, aacirun->base + AACI_IE);
sound/arm/aaci.c
257
writel(ICLR_TXUEC1 << channel, aaci->base + AACI_INTCLR);
sound/arm/aaci.c
267
writel(0, aacirun->base + AACI_IE);
sound/arm/aaci.c
51
writel(maincr, aaci->base + AACI_MAINCR);
sound/arm/aaci.c
554
writel(ie, aacirun->base + AACI_IE);
sound/arm/aaci.c
557
writel(aacirun->cr, aacirun->base + AACI_TXCR);
sound/arm/aaci.c
569
writel(ie, aacirun->base + AACI_IE);
sound/arm/aaci.c
570
writel(aacirun->cr, aacirun->base + AACI_TXCR);
sound/arm/aaci.c
627
writel(ie, aacirun->base+AACI_IE);
sound/arm/aaci.c
631
writel(aacirun->cr, aacirun->base + AACI_RXCR);
sound/arm/aaci.c
646
writel(aacirun->cr, aacirun->base + AACI_RXCR);
sound/arm/aaci.c
650
writel(ie, aacirun->base + AACI_IE);
sound/arm/aaci.c
802
writel(0, aaci->base + AACI_RESET);
sound/arm/aaci.c
804
writel(RESET_NRST, aaci->base + AACI_RESET);
sound/arm/aaci.c
84
writel(val << 4, aaci->base + AACI_SL2TX);
sound/arm/aaci.c
85
writel(reg << 12, aaci->base + AACI_SL1TX);
sound/arm/aaci.c
918
writel(CR_FEN | CR_SZ16 | CR_EN, aacirun->base + AACI_TXCR);
sound/arm/aaci.c
921
writel(0, aacirun->fifo);
sound/arm/aaci.c
923
writel(0, aacirun->base + AACI_TXCR);
sound/arm/aaci.c
930
writel(aaci->maincr & ~MAINCR_IE, aaci->base + AACI_MAINCR);
sound/arm/aaci.c
933
writel(aaci->maincr, aaci->base + AACI_MAINCR);
sound/arm/aaci.c
984
writel(0, base + AACI_IE);
sound/arm/aaci.c
985
writel(0, base + AACI_TXCR);
sound/arm/aaci.c
986
writel(0, base + AACI_RXCR);
sound/arm/aaci.c
989
writel(0x1fff, aaci->base + AACI_INTCLR);
sound/arm/aaci.c
990
writel(aaci->maincr, aaci->base + AACI_MAINCR);
sound/arm/pxa2xx-ac97-lib.c
104
writel(GSR_CDONE | GSR_SDONE, ac97_reg_base + GSR);
sound/arm/pxa2xx-ac97-lib.c
106
writel(val, reg_addr);
sound/arm/pxa2xx-ac97-lib.c
123
writel(readl(ac97_reg_base + GCR) | (GCR_WARM_RST), ac97_reg_base + GCR);
sound/arm/pxa2xx-ac97-lib.c
128
writel(readl(ac97_reg_base + GCR) & ( GCR_COLD_RST), ac97_reg_base + GCR); /* clear everything but nCRST */
sound/arm/pxa2xx-ac97-lib.c
129
writel(readl(ac97_reg_base + GCR) & (~GCR_COLD_RST), ac97_reg_base + GCR); /* then assert nCRST */
sound/arm/pxa2xx-ac97-lib.c
133
writel(GCR_COLD_RST, ac97_reg_base + GCR);
sound/arm/pxa2xx-ac97-lib.c
145
writel(readl(ac97_reg_base + GCR) | (GCR_WARM_RST), ac97_reg_base + GCR);
sound/arm/pxa2xx-ac97-lib.c
152
writel(readl(ac97_reg_base + GCR) & ( GCR_COLD_RST), ac97_reg_base + GCR); /* clear everything but nCRST */
sound/arm/pxa2xx-ac97-lib.c
153
writel(readl(ac97_reg_base + GCR) & (~GCR_COLD_RST), ac97_reg_base + GCR); /* then assert nCRST */
sound/arm/pxa2xx-ac97-lib.c
161
writel(GCR_COLD_RST | GCR_WARM_RST, ac97_reg_base + GCR);
sound/arm/pxa2xx-ac97-lib.c
171
writel(readl(ac97_reg_base + GCR) | (GCR_WARM_RST), ac97_reg_base + GCR);
sound/arm/pxa2xx-ac97-lib.c
177
writel(0, ac97_reg_base + GCR);
sound/arm/pxa2xx-ac97-lib.c
178
writel(GCR_CLKBPB, ac97_reg_base + GCR);
sound/arm/pxa2xx-ac97-lib.c
180
writel(0, ac97_reg_base + GCR);
sound/arm/pxa2xx-ac97-lib.c
182
writel(readl(ac97_reg_base + GCR) & ( GCR_COLD_RST), ac97_reg_base + GCR); /* clear everything but nCRST */
sound/arm/pxa2xx-ac97-lib.c
183
writel(readl(ac97_reg_base + GCR) & (~GCR_COLD_RST), ac97_reg_base + GCR); /* then assert nCRST */
sound/arm/pxa2xx-ac97-lib.c
188
writel(readl(ac97_reg_base + GCR) & (~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN)), ac97_reg_base + GCR);
sound/arm/pxa2xx-ac97-lib.c
190
writel(GCR_WARM_RST | GCR_COLD_RST, ac97_reg_base + GCR);
sound/arm/pxa2xx-ac97-lib.c
274
writel(gcr, ac97_reg_base + GCR);
sound/arm/pxa2xx-ac97-lib.c
284
writel(status, ac97_reg_base + GSR);
sound/arm/pxa2xx-ac97-lib.c
292
writel(MISR_EOC, ac97_reg_base + MISR);
sound/arm/pxa2xx-ac97-lib.c
293
writel(PISR_EOC, ac97_reg_base + PISR);
sound/arm/pxa2xx-ac97-lib.c
294
writel(MCSR_EOC, ac97_reg_base + MCSR);
sound/arm/pxa2xx-ac97-lib.c
306
writel(readl(ac97_reg_base + GCR) | (GCR_ACLINK_OFF), ac97_reg_base + GCR);
sound/arm/pxa2xx-ac97-lib.c
387
writel(readl(ac97_reg_base + GCR) | (GCR_ACLINK_OFF), ac97_reg_base + GCR);
sound/arm/pxa2xx-ac97-lib.c
403
writel(readl(ac97_reg_base + GCR) | (GCR_ACLINK_OFF), ac97_reg_base + GCR);
sound/arm/pxa2xx-ac97-lib.c
66
writel(GSR_CDONE | GSR_SDONE, ac97_reg_base + GSR);
sound/arm/pxa2xx-ac97-lib.c
79
writel(GSR_CDONE | GSR_SDONE, ac97_reg_base + GSR);
sound/atmel/ac97c.c
254
writel(runtime->dma_addr, chip->regs + ATMEL_PDC_TPR);
sound/atmel/ac97c.c
255
writel(block_size / 2, chip->regs + ATMEL_PDC_TCR);
sound/atmel/ac97c.c
256
writel(runtime->dma_addr + block_size, chip->regs + ATMEL_PDC_TNPR);
sound/atmel/ac97c.c
257
writel(block_size / 2, chip->regs + ATMEL_PDC_TNCR);
sound/atmel/ac97c.c
336
writel(runtime->dma_addr, chip->regs + ATMEL_PDC_RPR);
sound/atmel/ac97c.c
337
writel(block_size / 2, chip->regs + ATMEL_PDC_RCR);
sound/atmel/ac97c.c
338
writel(runtime->dma_addr + block_size, chip->regs + ATMEL_PDC_RNPR);
sound/atmel/ac97c.c
339
writel(block_size / 2, chip->regs + ATMEL_PDC_RNCR);
sound/atmel/ac97c.c
371
writel(ptcr, chip->regs + ATMEL_PDC_PTCR);
sound/atmel/ac97c.c
403
writel(ptcr, chip->regs + ATMEL_PDC_PTCR);
sound/atmel/ac97c.c
491
writel(runtime->dma_addr + offset, chip->regs + ATMEL_PDC_TNPR);
sound/atmel/ac97c.c
492
writel(block_size / 2, chip->regs + ATMEL_PDC_TNCR);
sound/atmel/ac97c.c
509
writel(runtime->dma_addr + offset, chip->regs + ATMEL_PDC_RNPR);
sound/atmel/ac97c.c
510
writel(block_size / 2, chip->regs + ATMEL_PDC_RNCR);
sound/hda/codecs/ca0132.c
3656
writel(0x0000007e, spec->mem_base + 0x210);
sound/hda/codecs/ca0132.c
3658
writel(0x0000005a, spec->mem_base + 0x210);
sound/hda/codecs/ca0132.c
3662
writel(0x00800005, spec->mem_base + 0x20c);
sound/hda/codecs/ca0132.c
3663
writel(group, spec->mem_base + 0x804);
sound/hda/codecs/ca0132.c
3665
writel(0x00800005, spec->mem_base + 0x20c);
sound/hda/codecs/ca0132.c
3670
writel(write_val, spec->mem_base + 0x204);
sound/hda/codecs/ca0132.c
3680
writel(0x00800004, spec->mem_base + 0x20c);
sound/hda/codecs/ca0132.c
3681
writel(0x00000000, spec->mem_base + 0x210);
sound/hda/codecs/ca0132.c
3695
writel(0x0000007e, spec->mem_base + 0x210);
sound/hda/codecs/ca0132.c
3697
writel(0x0000005a, spec->mem_base + 0x210);
sound/hda/codecs/ca0132.c
3701
writel(0x00800003, spec->mem_base + 0x20c);
sound/hda/codecs/ca0132.c
3702
writel(group, spec->mem_base + 0x804);
sound/hda/codecs/ca0132.c
3704
writel(0x00800005, spec->mem_base + 0x20c);
sound/hda/codecs/ca0132.c
3709
writel(write_val, spec->mem_base + 0x204);
sound/hda/codecs/ca0132.c
3715
writel(0x00800004, spec->mem_base + 0x20c);
sound/hda/codecs/ca0132.c
3716
writel(0x00000000, spec->mem_base + 0x210);
sound/hda/codecs/ca0132.c
9096
writel(0x00820680, spec->mem_base + 0x01C);
sound/hda/codecs/ca0132.c
9097
writel(0x00820680, spec->mem_base + 0x01C);
sound/hda/codecs/ca0132.c
9213
writel(0x00000000, spec->mem_base + addr[i]);
sound/hda/codecs/ca0132.c
9236
writel(tmp[i], spec->mem_base + addr[cur_addr + i]);
sound/hda/codecs/ca0132.c
9252
writel(data[i], spec->mem_base + addr[cur_addr + i]);
sound/hda/codecs/ca0132.c
9266
writel(0x00000680, spec->mem_base + 0x1c);
sound/hda/codecs/ca0132.c
9267
writel(0x00880680, spec->mem_base + 0x1c);
sound/hda/codecs/ca0132.c
9276
writel(0x00800001, spec->mem_base + addr[i]);
sound/hda/codecs/ca0132.c
9280
writel(data[i], spec->mem_base + addr[i]);
sound/hda/codecs/ca0132.c
9284
writel(0x00880680, spec->mem_base + 0x1c);
sound/hda/codecs/ca0132.c
9356
writel(data[i], spec->mem_base + addr[cur_addr]);
sound/hda/codecs/ca0132.c
9358
writel(0x00800001, spec->mem_base + 0x20c);
sound/hda/controllers/intel.c
498
writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
sound/hda/controllers/intel.c
541
writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
sound/hda/controllers/tegra.c
111
writel(v, hda->regs + HDA_IPFS_CONFIG);
sound/hda/controllers/tegra.c
118
writel(v, hda->regs + HDA_CFG_CMD);
sound/hda/controllers/tegra.c
120
writel(HDA_BAR0_INIT_PROGRAM, hda->regs + HDA_CFG_BAR0);
sound/hda/controllers/tegra.c
121
writel(HDA_BAR0_FINAL_PROGRAM, hda->regs + HDA_CFG_BAR0);
sound/hda/controllers/tegra.c
122
writel(HDA_FPCI_BAR0_START, hda->regs + HDA_IPFS_FPCI_BAR0);
sound/hda/controllers/tegra.c
126
writel(v, hda->regs + HDA_IPFS_INTR_MASK);
sound/hda/controllers/tegra.c
312
writel(val, hda->regs + FPCI_DBG_CFG_2);
sound/hda/core/bus.c
261
writel(v, aligned_addr);
sound/hda/core/ext/stream.c
214
writel(val, hext_stream->pplc_addr + AZX_REG_PPLCCTL);
sound/hda/core/ext/stream.c
245
writel(val, hext_stream->pplc_addr + AZX_REG_PPLCCTL);
sound/hda/core/stream.c
820
writel(value, azx_dev->spib_addr);
sound/hda/core/stream.c
887
writel(value, azx_dev->dpibr_addr);
sound/isa/msnd/msnd_pinnacle.c
356
writel(0x00010000, chip->SMA + SMA_dwCurrPlayPitch);
sound/isa/msnd/msnd_pinnacle.c
357
writel(0x00000001, chip->SMA + SMA_dwCurrPlayRate);
sound/mips/snd-n64.c
68
writel(value, priv->ai_reg_base + reg);
sound/mips/snd-n64.c
73
writel(value, priv->mi_reg_base + reg);
sound/pci/ad1889.c
117
writel(val, chip->iobase + reg);
sound/pci/atiixp.c
1477
writel((u32)dma->desc_buf.addr | ATI_REG_LINKPTR_EN,
sound/pci/atiixp.c
308
writel(data, addr);
sound/pci/atiixp.c
316
writel(value, chip->remap_addr + ATI_REG_##reg)
sound/pci/atiixp.c
366
writel(0, chip->remap_addr + dma->ops->llp_offset);
sound/pci/atiixp.c
388
writel((u32)dma->desc_buf.addr | ATI_REG_LINKPTR_EN,
sound/pci/atiixp.c
404
writel(0, chip->remap_addr + dma->ops->llp_offset);
sound/pci/atiixp.c
720
writel(dma->saved_curptr, chip->remap_addr +
sound/pci/atiixp_modem.c
276
writel(data, addr);
sound/pci/atiixp_modem.c
284
writel(value, chip->remap_addr + ATI_REG_##reg)
sound/pci/atiixp_modem.c
333
writel(0, chip->remap_addr + dma->ops->llp_offset);
sound/pci/atiixp_modem.c
355
writel((u32)dma->desc_buf.addr | ATI_REG_LINKPTR_EN,
sound/pci/atiixp_modem.c
372
writel(0, chip->remap_addr + dma->ops->llp_offset);
sound/pci/au88x0/au88x0.h
27
#define hwwrite(x,y,z) writel((z),(x)+(y))
sound/pci/aw2/aw2-saa7146.c
28
#define WRITEREG(value, addr) writel((value), chip->base_addr + (addr))
sound/pci/bt87x.c
208
writel(value, chip->mmio + reg);
sound/pci/cs4281.c
1807
writel((unsigned int)cmd, port);
sound/pci/cs4281.c
1810
writel((unsigned int)val, port + 4);
sound/pci/cs4281.c
498
writel(val, chip->ba0 + offset);
sound/pci/cs46xx/cs46xx_lib.c
320
writel(*src++, dst);
sound/pci/cs46xx/cs46xx_lib.c
483
writel(0, dst);
sound/pci/cs46xx/cs46xx_lib.h
55
writel(val, chip->region.idx[bank+1].remap_addr + offset);
sound/pci/cs46xx/cs46xx_lib.h
67
writel(val, chip->region.name.ba0.remap_addr + offset);
sound/pci/cs46xx/dsp_spos.c
872
writel(task_data[i],spdst);
sound/pci/cs46xx/dsp_spos.c
886
writel(scb_data[i],spdst);
sound/pci/cs46xx/dsp_spos_scb_lib.c
154
writel(0, dst);
sound/pci/ctxfi/cthw20k1.c
1868
writel(CTLX, (mem_base + UAA_CORE_CHANGE));
sound/pci/ctxfi/cthw20k1.c
1869
writel(CTL_, (mem_base + UAA_CORE_CHANGE));
sound/pci/ctxfi/cthw20k1.c
1870
writel(CTLF, (mem_base + UAA_CORE_CHANGE));
sound/pci/ctxfi/cthw20k1.c
1871
writel(CTLi, (mem_base + UAA_CORE_CHANGE));
sound/pci/ctxfi/cthw20k2.c
2256
writel(data, hw->mem_base + reg);
sound/pci/echoaudio/echoaudio.h
453
writel(value, &chip->dsp_registers[index]);
sound/pci/korg1212/korg1212.c
1057
writel(doorbellValue, korg1212->inDoorbellPtr);
sound/pci/korg1212/korg1212.c
521
writel(mailBox3Val, korg1212->mailbox3Ptr);
sound/pci/korg1212/korg1212.c
522
writel(mailBox2Val, korg1212->mailbox2Ptr);
sound/pci/korg1212/korg1212.c
523
writel(mailBox1Val, korg1212->mailbox1Ptr);
sound/pci/korg1212/korg1212.c
524
writel(mailBox0Val, korg1212->mailbox0Ptr);
sound/pci/korg1212/korg1212.c
525
writel(doorbellVal, korg1212->outDoorbellPtr); // interrupt the card
sound/pci/korg1212/korg1212.c
706
writel(PCI_INT_ENABLE_BIT |
sound/pci/korg1212/korg1212.c
822
writel(0, korg1212->statusRegPtr);
sound/pci/korg1212/korg1212.c
861
writel(0, korg1212->mailbox3Ptr);
sound/pci/lola/lola.h
384
writel((val), (chip)->bar[idx].remap_addr + LOLA_##idx##_##name)
sound/pci/lola/lola.h
394
writel((val), (chip)->bar[BAR1].remap_addr + LOLA_BAR1_DSD0_OFFSET + \
sound/pci/lola/lola_mixer.c
231
writel(val, &chip->mixer.array->src_gain_enable);
sound/pci/lola/lola_mixer.c
252
writel(mask, &chip->mixer.array->src_gain_enable);
sound/pci/lola/lola_mixer.c
286
writel(val, &chip->mixer.array->dest_mix_gain_enable[dest]);
sound/pci/lola/lola_mixer.c
307
writel(mask, &chip->mixer.array->dest_mix_gain_enable[id]);
sound/pci/mixart/mixart_core.c
154
writel(0, MIXART_MEM(mgr, tailptr)); /* set address to zero on this fifo position */
sound/pci/mixart/mixart_core.c
405
writel(it_reg, MIXART_REG(mgr, MIXART_PCI_ODBR_OFFSET));
sound/pci/mixart/mixart_core.c
562
writel( 0, MIXART_MEM( mgr, MSG_HOST_RSC_PROTECTION ) );
sound/pci/mixart/mixart_core.c
563
writel( 0, MIXART_MEM( mgr, MSG_AGENT_RSC_PROTECTION ) );
sound/pci/nm256/nm256.c
294
writel(val, chip->cport + offset);
sound/pci/rme32.c
1005
writel(0, rme32->iobase + RME32_IO_RESET_POS);
sound/pci/rme32.c
1345
writel(0, rme32->iobase + RME32_IO_RESET_POS);
sound/pci/rme32.c
1351
writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
sound/pci/rme32.c
1506
writel(val, rme32->iobase + RME32_IO_CONTROL_REGISTER);
sound/pci/rme32.c
1711
writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
sound/pci/rme32.c
386
writel(rme32->wcreg | RME32_WCR_PD,
sound/pci/rme32.c
388
writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
sound/pci/rme32.c
525
writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
sound/pci/rme32.c
556
writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
sound/pci/rme32.c
588
writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
sound/pci/rme32.c
630
writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
sound/pci/rme32.c
676
writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
sound/pci/rme32.c
700
writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
sound/pci/rme32.c
718
writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
sound/pci/rme32.c
735
writel(0, rme32->iobase + RME32_IO_RESET_POS);
sound/pci/rme32.c
739
writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
sound/pci/rme32.c
750
writel(0, rme32->iobase + RME32_IO_CONFIRM_ACTION_IRQ);
sound/pci/rme32.c
755
writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
sound/pci/rme32.c
757
writel(0, rme32->iobase + RME32_IO_RESET_POS);
sound/pci/rme32.c
774
writel(0, rme32->iobase + RME32_IO_CONFIRM_ACTION_IRQ);
sound/pci/rme32.c
811
writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
sound/pci/rme32.c
892
writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
sound/pci/rme32.c
986
writel(0, rme32->iobase + RME32_IO_RESET_POS);
sound/pci/rme32.c
990
writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
sound/pci/rme96.c
1000
writel(rme96->wcreg |= rme96->wcreg_spdif_stream, rme96->iobase + RME96_IO_CONTROL_REGISTER);
sound/pci/rme96.c
1063
writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
sound/pci/rme96.c
1065
writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
sound/pci/rme96.c
1069
writel(0, rme96->iobase + RME96_IO_CONFIRM_PLAY_IRQ);
sound/pci/rme96.c
1074
writel(0, rme96->iobase + RME96_IO_CONFIRM_REC_IRQ);
sound/pci/rme96.c
1084
writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
sound/pci/rme96.c
1106
writel(0, rme96->iobase + RME96_IO_CONFIRM_PLAY_IRQ);
sound/pci/rme96.c
1111
writel(0, rme96->iobase + RME96_IO_CONFIRM_REC_IRQ);
sound/pci/rme96.c
1157
writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
sound/pci/rme96.c
1223
writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
sound/pci/rme96.c
1321
writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
sound/pci/rme96.c
1334
writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
sound/pci/rme96.c
1518
writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
sound/pci/rme96.c
1622
writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
sound/pci/rme96.c
1623
writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
sound/pci/rme96.c
1626
writel(rme96->areg | RME96_AR_PD2,
sound/pci/rme96.c
1628
writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
sound/pci/rme96.c
1633
writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
sound/pci/rme96.c
1636
writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
sound/pci/rme96.c
1637
writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
sound/pci/rme96.c
1821
writel(val, rme96->iobase + RME96_IO_CONTROL_REGISTER);
sound/pci/rme96.c
2110
writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
sound/pci/rme96.c
2311
writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
sound/pci/rme96.c
2321
writel(0, rme96->iobase + RME96_IO_SET_PLAY_POS
sound/pci/rme96.c
2323
writel(0, rme96->iobase + RME96_IO_SET_REC_POS
sound/pci/rme96.c
2333
writel(rme96->areg | RME96_AR_PD2,
sound/pci/rme96.c
2335
writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
sound/pci/rme96.c
2340
writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
sound/pci/rme96.c
484
writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
sound/pci/rme96.c
487
writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
sound/pci/rme96.c
493
writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
sound/pci/rme96.c
496
writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
sound/pci/rme96.c
514
writel(rme96->wcreg | RME96_WCR_PD,
sound/pci/rme96.c
516
writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
sound/pci/rme96.c
540
writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
sound/pci/rme96.c
575
writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
sound/pci/rme96.c
722
writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
sound/pci/rme96.c
765
writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
sound/pci/rme96.c
792
writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
sound/pci/rme96.c
793
writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
sound/pci/rme96.c
843
writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
sound/pci/rme96.c
862
writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
sound/pci/rme96.c
864
writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
sound/pci/rme96.c
913
writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
sound/pci/rme96.c
930
writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
sound/pci/rme96.c
950
writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
sound/pci/rme9652/hdsp.c
638
writel(val, hdsp->iobase + reg);
sound/pci/rme9652/hdspm.c
1137
writel(val, hdspm->iobase + reg);
sound/pci/rme9652/rme9652.c
301
writel(val, rme9652->iobase + reg);
sound/pci/sis7019.c
1113
writel(i, SIS_MIXER_START_ADDR(ioaddr, i));
sound/pci/sis7019.c
1114
writel(SIS_MIXER_RIGHT_NO_ATTEN | SIS_MIXER_LEFT_NO_ATTEN |
sound/pci/sis7019.c
532
writel(format, ctrl_base + SIS_PLAY_DMA_FORMAT_CSO);
sound/pci/sis7019.c
533
writel(dma_addr, ctrl_base + SIS_PLAY_DMA_BASE);
sound/pci/sis7019.c
534
writel(control, ctrl_base + SIS_PLAY_DMA_CONTROL);
sound/pci/sis7019.c
535
writel(sso_eso, ctrl_base + SIS_PLAY_DMA_SSO_ESO);
sound/pci/sis7019.c
538
writel(0, wave_base + reg);
sound/pci/sis7019.c
540
writel(SIS_WAVE_GENERAL_WAVE_VOLUME, wave_base + SIS_WAVE_GENERAL);
sound/pci/sis7019.c
541
writel(delta << 16, wave_base + SIS_WAVE_GENERAL_ARTICULATION);
sound/pci/sis7019.c
542
writel(SIS_WAVE_CHANNEL_CONTROL_FIRST_SAMPLE |
sound/pci/sis7019.c
769
writel(format, play_base + SIS_PLAY_DMA_FORMAT_CSO);
sound/pci/sis7019.c
770
writel(sis->silence_dma_addr, play_base + SIS_PLAY_DMA_BASE);
sound/pci/sis7019.c
771
writel(control, play_base + SIS_PLAY_DMA_CONTROL);
sound/pci/sis7019.c
772
writel(sso_eso, play_base + SIS_PLAY_DMA_SSO_ESO);
sound/pci/sis7019.c
775
writel(0, wave_base + reg);
sound/pci/sis7019.c
777
writel(SIS_WAVE_GENERAL_WAVE_VOLUME, wave_base + SIS_WAVE_GENERAL);
sound/pci/sis7019.c
778
writel(delta << 16, wave_base + SIS_WAVE_GENERAL_ARTICULATION);
sound/pci/sis7019.c
779
writel(SIS_WAVE_CHANNEL_CONTROL_FIRST_SAMPLE |
sound/pci/sis7019.c
820
writel(format, rec_base + SIS_CAPTURE_DMA_FORMAT_CSO);
sound/pci/sis7019.c
821
writel(dma_addr, rec_base + SIS_CAPTURE_DMA_BASE);
sound/pci/sis7019.c
822
writel(control, rec_base + SIS_CAPTURE_DMA_CONTROL);
sound/pci/ymfpci/ymfpci_main.c
56
writel(val, chip->reg_area_virt + offset);
sound/sh/aica.c
116
writel(val, to);
sound/sh/aica.c
134
writel(regval, ARM_RESET_REGISTER);
sound/sh/aica.c
142
writel(regval, SPU_REGISTER_BASE + (i * 0x80));
sound/sh/aica.c
155
writel(regval, ARM_RESET_REGISTER);
sound/sh/aica.c
181
writel(AICA_CMD_KICK | AICA_CMD_START, (u32 *) AICA_CONTROL_POINT);
sound/sh/aica.c
191
writel(AICA_CMD_KICK | AICA_CMD_STOP, (u32 *) AICA_CONTROL_POINT);
sound/sh/aica.c
95
writel(what, toi + SPU_MEMORY_BASE);
sound/soc/amd/acp-pcm-dma.c
125
writel(val, acp_mmio + (reg * 4));
sound/soc/amd/acp/acp-i2s.c
269
writel(val, chip->base + reg_val);
sound/soc/amd/acp/acp-i2s.c
273
writel(val | BIT(1), chip->base + reg_val);
sound/soc/amd/acp/acp-i2s.c
278
writel(tdm_fmt, chip->base + fmt_reg);
sound/soc/amd/acp/acp-i2s.c
453
writel(period_bytes, chip->base + water_val);
sound/soc/amd/acp/acp-i2s.c
454
writel(buf_size, chip->base + buf_reg);
sound/soc/amd/acp/acp-i2s.c
459
writel(val, chip->base + reg_val);
sound/soc/amd/acp/acp-i2s.c
460
writel(1, chip->base + ier_val);
sound/soc/amd/acp/acp-i2s.c
499
writel(val, chip->base + reg_val);
sound/soc/amd/acp/acp-i2s.c
503
writel(0, chip->base + ACP_BTTDM_IER);
sound/soc/amd/acp/acp-i2s.c
506
writel(0, chip->base + ACP_I2STDM_IER);
sound/soc/amd/acp/acp-i2s.c
509
writel(0, chip->base + ACP_HSTDM_IER);
sound/soc/amd/acp/acp-i2s.c
541
writel(phy_addr, chip->base + ACP_I2S_TX_RINGBUFADDR(chip));
sound/soc/amd/acp/acp-i2s.c
553
writel(phy_addr, chip->base + ACP_I2S_RX_RINGBUFADDR(chip));
sound/soc/amd/acp/acp-i2s.c
568
writel(phy_addr, chip->base + ACP_BT_TX_RINGBUFADDR(chip));
sound/soc/amd/acp/acp-i2s.c
580
writel(phy_addr, chip->base + ACP_BT_RX_RINGBUFADDR(chip));
sound/soc/amd/acp/acp-i2s.c
595
writel(phy_addr, chip->base + ACP_HS_TX_RINGBUFADDR);
sound/soc/amd/acp/acp-i2s.c
607
writel(phy_addr, chip->base + ACP_HS_RX_RINGBUFADDR);
sound/soc/amd/acp/acp-i2s.c
615
writel(DMA_SIZE, chip->base + reg_dma_size);
sound/soc/amd/acp/acp-i2s.c
616
writel(acp_fifo_addr, chip->base + reg_fifo_addr);
sound/soc/amd/acp/acp-i2s.c
617
writel(FIFO_SIZE, chip->base + reg_fifo_size);
sound/soc/amd/acp/acp-i2s.c
627
writel(ext_int_ctrl, ACP_EXTERNAL_INTR_CNTL(chip, rsrc->irqp_used));
sound/soc/amd/acp/acp-i2s.c
69
writel(val, chip->base + i2s_clk_reg);
sound/soc/amd/acp/acp-legacy-common.c
104
writel(stream->irq_bit, ACP_EXTERNAL_INTR_STAT(chip,
sound/soc/amd/acp/acp-legacy-common.c
124
writel(0x01, ACP_EXTERNAL_INTR_ENB(chip));
sound/soc/amd/acp/acp-legacy-common.c
127
writel(ext_intr_ctrl, ACP_EXTERNAL_INTR_CNTL(chip, rsrc->irqp_used));
sound/soc/amd/acp/acp-legacy-common.c
138
writel(ACP_EXT_INTR_STAT_CLEAR_MASK, ACP_EXTERNAL_INTR_STAT(chip, rsrc->irqp_used));
sound/soc/amd/acp/acp-legacy-common.c
139
writel(0x00, ACP_EXTERNAL_INTR_ENB(chip));
sound/soc/amd/acp/acp-legacy-common.c
160
writel(physical_addr, chip->base + ACP_WOV_RX_RINGBUFADDR);
sound/soc/amd/acp/acp-legacy-common.c
161
writel(pdm_size, chip->base + ACP_WOV_RX_RINGBUFSIZE);
sound/soc/amd/acp/acp-legacy-common.c
162
writel(period_bytes, chip->base + ACP_WOV_RX_INTR_WATERMARK_SIZE);
sound/soc/amd/acp/acp-legacy-common.c
163
writel(0x01, chip->base + ACPAXI2AXI_ATU_CTRL);
sound/soc/amd/acp/acp-legacy-common.c
174
writel(PDM_CLK_FREQ_MASK, chip->base + ACP_WOV_CLK_CTRL);
sound/soc/amd/acp/acp-legacy-common.c
177
writel(pdm_ctrl, chip->base + ACP_WOV_MISC_CTRL);
sound/soc/amd/acp/acp-legacy-common.c
192
writel(chip->ch_mask, chip->base + ACP_WOV_PDM_NO_OF_CHANNELS);
sound/soc/amd/acp/acp-legacy-common.c
193
writel(PDM_DEC_64, chip->base + ACP_WOV_PDM_DECIMATION_FACTOR);
sound/soc/amd/acp/acp-legacy-common.c
198
writel(ext_int_ctrl, ACP_EXTERNAL_INTR_CNTL(chip, 0));
sound/soc/amd/acp/acp-legacy-common.c
226
writel(phy_addr, chip->base + ACP_I2S_TX_RINGBUFADDR(chip));
sound/soc/amd/acp/acp-legacy-common.c
237
writel(phy_addr, chip->base + ACP_I2S_RX_RINGBUFADDR(chip));
sound/soc/amd/acp/acp-legacy-common.c
251
writel(phy_addr, chip->base + ACP_BT_TX_RINGBUFADDR(chip));
sound/soc/amd/acp/acp-legacy-common.c
262
writel(phy_addr, chip->base + ACP_BT_RX_RINGBUFADDR(chip));
sound/soc/amd/acp/acp-legacy-common.c
276
writel(phy_addr, chip->base + ACP_HS_TX_RINGBUFADDR);
sound/soc/amd/acp/acp-legacy-common.c
287
writel(phy_addr, chip->base + ACP_HS_RX_RINGBUFADDR);
sound/soc/amd/acp/acp-legacy-common.c
295
writel(DMA_SIZE, chip->base + reg_dma_size);
sound/soc/amd/acp/acp-legacy-common.c
296
writel(acp_fifo_addr, chip->base + reg_fifo_addr);
sound/soc/amd/acp/acp-legacy-common.c
297
writel(FIFO_SIZE, chip->base + reg_fifo_size);
sound/soc/amd/acp/acp-legacy-common.c
307
writel(ext_int_ctrl, ACP_EXTERNAL_INTR_CNTL(chip, rsrc->irqp_used));
sound/soc/amd/acp/acp-legacy-common.c
362
writel(val, chip->base + reg_val);
sound/soc/amd/acp/acp-legacy-common.c
364
writel(tdm_fmt, chip->base + fmt_reg);
sound/soc/amd/acp/acp-legacy-common.c
366
writel(val | 0x2, chip->base + reg_val);
sound/soc/amd/acp/acp-legacy-common.c
406
writel(ACP_PGFSM_CNTL_POWER_ON_MASK, base + acp_pgfsm_ctrl_reg);
sound/soc/amd/acp/acp-legacy-common.c
417
writel(1, base + ACP_SOFT_RESET);
sound/soc/amd/acp/acp-legacy-common.c
423
writel(0, base + ACP_SOFT_RESET);
sound/soc/amd/acp/acp-legacy-common.c
437
writel(0x01, chip->base + ACP_CONTROL);
sound/soc/amd/acp/acp-legacy-common.c
446
writel(0, chip->base + ACP_ZSC_DSP_CTRL);
sound/soc/amd/acp/acp-legacy-common.c
461
writel(0, chip->base + ACP_CONTROL);
sound/soc/amd/acp/acp-legacy-common.c
463
writel(0x01, chip->base + ACP_ZSC_DSP_CTRL);
sound/soc/amd/acp/acp-legacy-common.c
97
writel(stream->irq_bit,
sound/soc/amd/acp/acp-pdm.c
136
writel(ch_mask, chip->base + ACP_WOV_PDM_NO_OF_CHANNELS);
sound/soc/amd/acp/acp-pdm.c
137
writel(PDM_DEC_64, chip->base + ACP_WOV_PDM_DECIMATION_FACTOR);
sound/soc/amd/acp/acp-pdm.c
158
writel(ext_int_ctrl, ACP_EXTERNAL_INTR_CNTL(chip, 0));
sound/soc/amd/acp/acp-pdm.c
173
writel(ext_int_ctrl, ACP_EXTERNAL_INTR_CNTL(chip, 0));
sound/soc/amd/acp/acp-pdm.c
39
writel(PDM_CLK_FREQ_MASK, chip->base + ACP_WOV_CLK_CTRL);
sound/soc/amd/acp/acp-pdm.c
42
writel(dmic_ctrl, chip->base + ACP_WOV_MISC_CTRL);
sound/soc/amd/acp/acp-pdm.c
55
writel(physical_addr, chip->base + ACP_WOV_RX_RINGBUFADDR);
sound/soc/amd/acp/acp-pdm.c
56
writel(size_dmic, chip->base + ACP_WOV_RX_RINGBUFSIZE);
sound/soc/amd/acp/acp-pdm.c
57
writel(period_bytes, chip->base + ACP_WOV_RX_INTR_WATERMARK_SIZE);
sound/soc/amd/acp/acp-pdm.c
58
writel(0x01, chip->base + ACPAXI2AXI_ATU_CTRL);
sound/soc/amd/acp/acp-pdm.c
77
writel(PDM_ENABLE, chip->base + ACP_WOV_PDM_ENABLE);
sound/soc/amd/acp/acp-pdm.c
78
writel(PDM_ENABLE, chip->base + ACP_WOV_PDM_DMA_ENABLE);
sound/soc/amd/acp/acp-pdm.c
90
writel(PDM_DISABLE, chip->base + ACP_WOV_PDM_ENABLE);
sound/soc/amd/acp/acp-pdm.c
91
writel(PDM_DISABLE, chip->base + ACP_WOV_PDM_DMA_ENABLE);
sound/soc/amd/acp/acp-platform.c
118
writel((reg_val + GRP1_OFFSET) | BIT(31), chip->base + ACPAXI2AXI_ATU_BASE_ADDR_GRP_1);
sound/soc/amd/acp/acp-platform.c
119
writel(PAGE_SIZE_4K_ENABLE, chip->base + ACPAXI2AXI_ATU_PAGE_SIZE_GRP_1);
sound/soc/amd/acp/acp-platform.c
121
writel((reg_val + GRP2_OFFSET) | BIT(31), chip->base + ACPAXI2AXI_ATU_BASE_ADDR_GRP_2);
sound/soc/amd/acp/acp-platform.c
122
writel(PAGE_SIZE_4K_ENABLE, chip->base + ACPAXI2AXI_ATU_PAGE_SIZE_GRP_2);
sound/soc/amd/acp/acp-platform.c
124
writel(reg_val | BIT(31), chip->base + ACPAXI2AXI_ATU_BASE_ADDR_GRP_5);
sound/soc/amd/acp/acp-platform.c
125
writel(PAGE_SIZE_4K_ENABLE, chip->base + ACPAXI2AXI_ATU_PAGE_SIZE_GRP_5);
sound/soc/amd/acp/acp-platform.c
127
writel(0x01, chip->base + ACPAXI2AXI_ATU_CTRL);
sound/soc/amd/acp/acp-platform.c
180
writel(low, chip->base + rsrc->scratch_reg_offset + val);
sound/soc/amd/acp/acp-platform.c
182
writel(high, chip->base + rsrc->scratch_reg_offset + val + 4);
sound/soc/amd/acp/acp-platform.c
245
writel(1, ACP_EXTERNAL_INTR_ENB(chip));
sound/soc/amd/ps/pci-ps.c
131
writel(ACP63_P1_AUDIO1_RX_THRESHOLD,
sound/soc/amd/ps/pci-ps.c
137
writel(ACP63_P1_AUDIO1_TX_THRESHOLD,
sound/soc/amd/ps/pci-ps.c
150
writel(BIT(index),
sound/soc/amd/ps/pci-ps.c
211
writel(ACP_SDW0_STAT, adata->acp63_base + ACP_EXTERNAL_INTR_STAT);
sound/soc/amd/ps/pci-ps.c
220
writel(ACP_SDW1_STAT, adata->acp63_base + ACP_EXTERNAL_INTR_STAT1);
sound/soc/amd/ps/pci-ps.c
228
writel(ACP_ERROR_IRQ, adata->acp63_base + ACP_EXTERNAL_INTR_STAT);
sound/soc/amd/ps/pci-ps.c
230
writel(0, adata->acp63_base + ACP_SW0_I2S_ERROR_REASON);
sound/soc/amd/ps/pci-ps.c
231
writel(0, adata->acp63_base + ACP_SW1_I2S_ERROR_REASON);
sound/soc/amd/ps/pci-ps.c
232
writel(0, adata->acp63_base + ACP_ERROR_STATUS);
sound/soc/amd/ps/pci-ps.c
241
writel(BIT(PDM_DMA_STAT), adata->acp63_base + ACP_EXTERNAL_INTR_STAT);
sound/soc/amd/ps/pci-ps.c
51
writel(ACP70_SDW0_HOST_WAKE_STAT, adata->acp63_base + ACP_EXTERNAL_INTR_STAT1);
sound/soc/amd/ps/pci-ps.c
57
writel(ACP70_SDW1_HOST_WAKE_STAT, adata->acp63_base + ACP_EXTERNAL_INTR_STAT1);
sound/soc/amd/ps/pci-ps.c
63
writel(0, adata->acp63_base + ACP_SW0_WAKE_EN);
sound/soc/amd/ps/pci-ps.c
64
writel(ACP70_SDW0_PME_STAT, adata->acp63_base + ACP_EXTERNAL_INTR_STAT1);
sound/soc/amd/ps/pci-ps.c
70
writel(0, adata->acp63_base + ACP_SW1_WAKE_EN);
sound/soc/amd/ps/pci-ps.c
71
writel(ACP70_SDW1_PME_STAT, adata->acp63_base + ACP_EXTERNAL_INTR_STAT1);
sound/soc/amd/ps/pci-ps.c
93
writel(BIT(index), adata->acp63_base + ACP_EXTERNAL_INTR_STAT);
sound/soc/amd/ps/ps-common.c
167
writel(1, adata->acp63_base + ACP_ZSC_DSP_CTRL);
sound/soc/amd/ps/ps-common.c
185
writel(0, adata->acp63_base + ACP_ZSC_DSP_CTRL);
sound/soc/amd/ps/ps-common.c
207
writel(0, adata->acp63_base + ACP_ZSC_DSP_CTRL);
sound/soc/amd/ps/ps-common.c
218
writel(adata->acp_sw_pad_keeper_en, adata->acp63_base + ACP_SW0_PAD_KEEPER_EN);
sound/soc/amd/ps/ps-common.c
219
writel(adata->acp_pad_pulldown_ctrl, adata->acp63_base + ACP_PAD_PULLDOWN_CTRL);
sound/soc/amd/ps/ps-common.c
268
writel(ACP70_PGFSM_CNTL_POWER_ON_MASK, acp_base + ACP_PGFSM_CONTROL);
sound/soc/amd/ps/ps-common.c
278
writel(1, acp_base + ACP_SOFT_RESET);
sound/soc/amd/ps/ps-common.c
286
writel(0, acp_base + ACP_SOFT_RESET);
sound/soc/amd/ps/ps-common.c
297
writel(ext_intr_cntl1, acp_base + ACP_EXTERNAL_INTR_CNTL1);
sound/soc/amd/ps/ps-common.c
304
writel(1, acp_base + ACP_EXTERNAL_INTR_ENB);
sound/soc/amd/ps/ps-common.c
305
writel(ACP_ERROR_IRQ, acp_base + ACP_EXTERNAL_INTR_CNTL);
sound/soc/amd/ps/ps-common.c
314
writel(ACP_EXT_INTR_STAT_CLEAR_MASK, acp_base + ACP_EXTERNAL_INTR_STAT);
sound/soc/amd/ps/ps-common.c
315
writel(0, acp_base + ACP_EXTERNAL_INTR_CNTL);
sound/soc/amd/ps/ps-common.c
316
writel(0, acp_base + ACP_EXTERNAL_INTR_ENB);
sound/soc/amd/ps/ps-common.c
32
writel(ACP63_PGFSM_CNTL_POWER_ON_MASK, acp_base + ACP_PGFSM_CONTROL);
sound/soc/amd/ps/ps-common.c
328
writel(0x01, acp_base + ACP_CONTROL);
sound/soc/amd/ps/ps-common.c
334
writel(0, acp_base + ACP_ZSC_DSP_CTRL);
sound/soc/amd/ps/ps-common.c
336
writel(0x1, acp_base + ACP_PME_EN);
sound/soc/amd/ps/ps-common.c
350
writel(0x01, acp_base + ACP_ZSC_DSP_CTRL);
sound/soc/amd/ps/ps-common.c
42
writel(1, acp_base + ACP_SOFT_RESET);
sound/soc/amd/ps/ps-common.c
424
writel(1, adata->acp63_base + ACP_ZSC_DSP_CTRL);
sound/soc/amd/ps/ps-common.c
443
writel(0, adata->acp63_base + ACP_ZSC_DSP_CTRL);
sound/soc/amd/ps/ps-common.c
444
writel(1, adata->acp63_base + ACP_PME_EN);
sound/soc/amd/ps/ps-common.c
465
writel(0, adata->acp63_base + ACP_ZSC_DSP_CTRL);
sound/soc/amd/ps/ps-common.c
466
writel(1, adata->acp63_base + ACP_PME_EN);
sound/soc/amd/ps/ps-common.c
477
writel(adata->acp_sw_pad_keeper_en, adata->acp63_base + ACP_SW0_PAD_KEEPER_EN);
sound/soc/amd/ps/ps-common.c
478
writel(adata->acp_pad_pulldown_ctrl, adata->acp63_base + ACP_PAD_PULLDOWN_CTRL);
sound/soc/amd/ps/ps-common.c
50
writel(0, acp_base + ACP_SOFT_RESET);
sound/soc/amd/ps/ps-common.c
57
writel(1, acp_base + ACP_EXTERNAL_INTR_ENB);
sound/soc/amd/ps/ps-common.c
58
writel(ACP_ERROR_IRQ, acp_base + ACP_EXTERNAL_INTR_CNTL);
sound/soc/amd/ps/ps-common.c
63
writel(ACP_EXT_INTR_STAT_CLEAR_MASK, acp_base + ACP_EXTERNAL_INTR_STAT);
sound/soc/amd/ps/ps-common.c
64
writel(0, acp_base + ACP_EXTERNAL_INTR_CNTL);
sound/soc/amd/ps/ps-common.c
65
writel(0, acp_base + ACP_EXTERNAL_INTR_ENB);
sound/soc/amd/ps/ps-common.c
77
writel(0x01, acp_base + ACP_CONTROL);
sound/soc/amd/ps/ps-common.c
84
writel(0, acp_base + ACP_ZSC_DSP_CTRL);
sound/soc/amd/ps/ps-common.c
98
writel(0, acp_base + ACP_CONTROL);
sound/soc/amd/ps/ps-common.c
99
writel(1, acp_base + ACP_ZSC_DSP_CTRL);
sound/soc/amd/ps/ps-pdm-dma.c
114
writel(pdm_enable, acp_base + ACP_WOV_PDM_ENABLE);
sound/soc/amd/ps/ps-pdm-dma.c
115
writel(pdm_dma_enable, acp_base + ACP_WOV_PDM_DMA_ENABLE);
sound/soc/amd/ps/ps-pdm-dma.c
138
writel(pdm_dma_enable, acp_base + ACP_WOV_PDM_DMA_ENABLE);
sound/soc/amd/ps/ps-pdm-dma.c
151
writel(pdm_enable, acp_base + ACP_WOV_PDM_ENABLE);
sound/soc/amd/ps/ps-pdm-dma.c
153
writel(0x01, acp_base + ACP_WOV_PDM_FIFO_FLUSH);
sound/soc/amd/ps/ps-pdm-dma.c
167
writel(ACP_SRAM_PTE_OFFSET | BIT(31), rtd->acp63_base + ACPAXI2AXI_ATU_BASE_ADDR_GRP_1);
sound/soc/amd/ps/ps-pdm-dma.c
168
writel(PAGE_SIZE_4K_ENABLE, rtd->acp63_base + ACPAXI2AXI_ATU_PAGE_SIZE_GRP_1);
sound/soc/amd/ps/ps-pdm-dma.c
174
writel(low, rtd->acp63_base + ACP_SCRATCH_REG_0 + val);
sound/soc/amd/ps/ps-pdm-dma.c
176
writel(high, rtd->acp63_base + ACP_SCRATCH_REG_0 + val + 4);
sound/soc/amd/ps/ps-pdm-dma.c
310
writel(ch_mask, rtd->acp63_base + ACP_WOV_PDM_NO_OF_CHANNELS);
sound/soc/amd/ps/ps-pdm-dma.c
311
writel(PDM_DECIMATION_FACTOR, rtd->acp63_base + ACP_WOV_PDM_DECIMATION_FACTOR);
sound/soc/amd/ps/ps-pdm-dma.c
48
writel(physical_addr, acp_base + ACP_WOV_RX_RINGBUFADDR);
sound/soc/amd/ps/ps-pdm-dma.c
49
writel(buffer_size, acp_base + ACP_WOV_RX_RINGBUFSIZE);
sound/soc/amd/ps/ps-pdm-dma.c
50
writel(watermark_size, acp_base + ACP_WOV_RX_INTR_WATERMARK_SIZE);
sound/soc/amd/ps/ps-pdm-dma.c
51
writel(0x01, acp_base + ACPAXI2AXI_ATU_CTRL);
sound/soc/amd/ps/ps-pdm-dma.c
61
writel(pdm_clk_enable, acp_base + ACP_WOV_CLK_CTRL);
sound/soc/amd/ps/ps-pdm-dma.c
65
writel(pdm_ctrl, acp_base + ACP_WOV_MISC_CTRL);
sound/soc/amd/ps/ps-pdm-dma.c
75
writel(ext_int_ctrl, adata->acp63_base + ACP_EXTERNAL_INTR_CNTL);
sound/soc/amd/ps/ps-pdm-dma.c
86
writel(ext_int_ctrl, adata->acp63_base + ACP_EXTERNAL_INTR_CNTL);
sound/soc/amd/ps/ps-sdw-dma.c
192
writel(ext_intr_cntl, acp_base + ACP_EXTERNAL_INTR_CNTL);
sound/soc/amd/ps/ps-sdw-dma.c
195
writel(ext_intr_cntl1, acp_base + ACP_EXTERNAL_INTR_CNTL1);
sound/soc/amd/ps/ps-sdw-dma.c
199
writel(ext_intr_cntl, acp_base + ACP_EXTERNAL_INTR_CNTL);
sound/soc/amd/ps/ps-sdw-dma.c
202
writel(ext_intr_cntl1, acp_base + ACP_EXTERNAL_INTR_CNTL1);
sound/soc/amd/ps/ps-sdw-dma.c
219
writel(ACP_SDW_SRAM_PTE_OFFSET | BIT(31), acp_base + ACPAXI2AXI_ATU_BASE_ADDR_GRP_2);
sound/soc/amd/ps/ps-sdw-dma.c
220
writel(PAGE_SIZE_4K_ENABLE, acp_base + ACPAXI2AXI_ATU_PAGE_SIZE_GRP_2);
sound/soc/amd/ps/ps-sdw-dma.c
226
writel(low, acp_base + ACP_SCRATCH_REG_0 + val);
sound/soc/amd/ps/ps-sdw-dma.c
228
writel(high, acp_base + ACP_SCRATCH_REG_0 + val + 4);
sound/soc/amd/ps/ps-sdw-dma.c
232
writel(0x1, acp_base + ACPAXI2AXI_ATU_CTRL);
sound/soc/amd/ps/ps-sdw-dma.c
300
writel(sdw_ring_buf_size, acp_base + reg_ring_buf_size);
sound/soc/amd/ps/ps-sdw-dma.c
301
writel(sdw_ring_buf_addr, acp_base + reg_ring_buf_addr);
sound/soc/amd/ps/ps-sdw-dma.c
302
writel(sdw_fifo_addr, acp_base + reg_fifo_addr);
sound/soc/amd/ps/ps-sdw-dma.c
303
writel(SDW_DMA_SIZE, acp_base + reg_dma_size);
sound/soc/amd/ps/ps-sdw-dma.c
304
writel(SDW_FIFO_SIZE, acp_base + reg_fifo_size);
sound/soc/amd/ps/ps-sdw-dma.c
427
writel(ext_intr_ctrl, sdw_data->acp_base + acp_ext_intr_cntl_reg);
sound/soc/amd/ps/ps-sdw-dma.c
428
writel(period_bytes, sdw_data->acp_base + water_mark_size_reg);
sound/soc/amd/ps/ps-sdw-dma.c
598
writel(dma_enable, acp_base + sdw_dma_en_reg);
sound/soc/amd/ps/ps-sdw-dma.c
726
writel(period_bytes, sdw_data->acp_base + water_mark_size_reg);
sound/soc/amd/ps/ps-sdw-dma.c
767
writel(period_bytes, sdw_data->acp_base + water_mark_size_reg);
sound/soc/amd/raven/acp3x.h
121
writel(val, base_addr - ACP3x_PHY_BASE_ADDRESS);
sound/soc/amd/renoir/rn_acp3x.h
89
writel(val, base_addr - ACP_PHY_BASE_ADDRESS);
sound/soc/amd/rpl/rpl_acp6x.h
35
writel(val, base_addr - ACP6x_PHY_BASE_ADDRESS);
sound/soc/amd/vangogh/acp5x.h
147
writel(val, base_addr - ACP5x_PHY_BASE_ADDRESS);
sound/soc/amd/yc/acp6x.h
106
writel(val, base_addr - ACP6x_PHY_BASE_ADDRESS);
sound/soc/bcm/cygnus-pcm.c
239
writel(start, audio_io + p_rbuf->baseaddr);
sound/soc/bcm/cygnus-pcm.c
240
writel(end, audio_io + p_rbuf->endaddr);
sound/soc/bcm/cygnus-pcm.c
241
writel(fmark_val, audio_io + p_rbuf->fmark);
sound/soc/bcm/cygnus-pcm.c
242
writel(initial_rd, audio_io + p_rbuf->rdaddr);
sound/soc/bcm/cygnus-pcm.c
243
writel(initial_wr, audio_io + p_rbuf->wraddr);
sound/soc/bcm/cygnus-pcm.c
322
writel(clear_mask, aio->cygaud->audio + ESR0_STATUS_CLR_OFFSET);
sound/soc/bcm/cygnus-pcm.c
323
writel(clear_mask, aio->cygaud->audio + ESR1_STATUS_CLR_OFFSET);
sound/soc/bcm/cygnus-pcm.c
324
writel(clear_mask, aio->cygaud->audio + ESR3_STATUS_CLR_OFFSET);
sound/soc/bcm/cygnus-pcm.c
326
writel(clear_mask, aio->cygaud->audio + ESR0_MASK_CLR_OFFSET);
sound/soc/bcm/cygnus-pcm.c
327
writel(clear_mask, aio->cygaud->audio + ESR1_MASK_CLR_OFFSET);
sound/soc/bcm/cygnus-pcm.c
328
writel(clear_mask, aio->cygaud->audio + ESR3_MASK_CLR_OFFSET);
sound/soc/bcm/cygnus-pcm.c
330
writel(ANY_PLAYBACK_IRQ,
sound/soc/bcm/cygnus-pcm.c
333
writel(clear_mask, aio->cygaud->audio + ESR2_STATUS_CLR_OFFSET);
sound/soc/bcm/cygnus-pcm.c
334
writel(clear_mask, aio->cygaud->audio + ESR4_STATUS_CLR_OFFSET);
sound/soc/bcm/cygnus-pcm.c
335
writel(clear_mask, aio->cygaud->audio + ESR2_MASK_CLR_OFFSET);
sound/soc/bcm/cygnus-pcm.c
336
writel(clear_mask, aio->cygaud->audio + ESR4_MASK_CLR_OFFSET);
sound/soc/bcm/cygnus-pcm.c
338
writel(ANY_CAPTURE_IRQ,
sound/soc/bcm/cygnus-pcm.c
359
writel(set_mask, aio->cygaud->audio + ESR0_MASK_SET_OFFSET);
sound/soc/bcm/cygnus-pcm.c
360
writel(set_mask, aio->cygaud->audio + ESR1_MASK_SET_OFFSET);
sound/soc/bcm/cygnus-pcm.c
361
writel(set_mask, aio->cygaud->audio + ESR3_MASK_SET_OFFSET);
sound/soc/bcm/cygnus-pcm.c
363
writel(set_mask, aio->cygaud->audio + ESR2_MASK_SET_OFFSET);
sound/soc/bcm/cygnus-pcm.c
364
writel(set_mask, aio->cygaud->audio + ESR4_MASK_SET_OFFSET);
sound/soc/bcm/cygnus-pcm.c
411
writel(regval, aio->cygaud->audio + p_rbuf->wraddr);
sound/soc/bcm/cygnus-pcm.c
415
writel(regval, aio->cygaud->audio + p_rbuf->rdaddr);
sound/soc/bcm/cygnus-pcm.c
476
writel(esr_status0, audio_io + ESR0_STATUS_CLR_OFFSET);
sound/soc/bcm/cygnus-pcm.c
477
writel(esr_status1, audio_io + ESR1_STATUS_CLR_OFFSET);
sound/soc/bcm/cygnus-pcm.c
478
writel(esr_status3, audio_io + ESR3_STATUS_CLR_OFFSET);
sound/soc/bcm/cygnus-pcm.c
480
writel(esr_status3, audio_io + BF_REARM_FREE_MARK_OFFSET);
sound/soc/bcm/cygnus-pcm.c
530
writel(esr_status2, audio_io + ESR2_STATUS_CLR_OFFSET);
sound/soc/bcm/cygnus-pcm.c
531
writel(esr_status4, audio_io + ESR4_STATUS_CLR_OFFSET);
sound/soc/bcm/cygnus-pcm.c
533
writel(esr_status4, audio_io + BF_REARM_FULL_MARK_OFFSET);
sound/soc/bcm/cygnus-pcm.c
557
writel(ANY_PLAYBACK_IRQ & r5_status,
sound/soc/bcm/cygnus-pcm.c
564
writel(ANY_CAPTURE_IRQ & r5_status,
sound/soc/bcm/cygnus-ssp.c
1031
writel(value, aio->cygaud->i2s_in + aio->regs.i2s_cap_cfg);
sound/soc/bcm/cygnus-ssp.c
1039
writel(value, aio->cygaud->audio + aio->regs.i2s_cfg);
sound/soc/bcm/cygnus-ssp.c
1322
writel(CYGNUS_SSP_TRISTATE_MASK,
sound/soc/bcm/cygnus-ssp.c
255
writel(aio->portnum,
sound/soc/bcm/cygnus-ssp.c
262
writel(value, aio->cygaud->audio + aio->regs.i2s_stream_cfg);
sound/soc/bcm/cygnus-ssp.c
269
writel(value, aio->cygaud->audio + aio->regs.bf_sourcech_cfg);
sound/soc/bcm/cygnus-ssp.c
276
writel(value, aio->cygaud->i2s_in +
sound/soc/bcm/cygnus-ssp.c
287
writel(value, aio->cygaud->audio + aio->regs.bf_destch_cfg);
sound/soc/bcm/cygnus-ssp.c
292
writel(value, aio->cygaud->audio + AUD_MISC_SEROUT_OE_REG_BASE);
sound/soc/bcm/cygnus-ssp.c
295
writel(aio->portnum, aio->cygaud->audio + BF_SRC_GRP3_OFFSET);
sound/soc/bcm/cygnus-ssp.c
299
writel(value, aio->cygaud->audio + SPDIF_CTRL_OFFSET);
sound/soc/bcm/cygnus-ssp.c
306
writel(value, aio->cygaud->audio + SPDIF_STREAM_CFG_OFFSET);
sound/soc/bcm/cygnus-ssp.c
312
writel(value, aio->cygaud->audio + aio->regs.bf_sourcech_cfg);
sound/soc/bcm/cygnus-ssp.c
317
writel(value, aio->cygaud->audio + AUD_MISC_SEROUT_OE_REG_BASE);
sound/soc/bcm/cygnus-ssp.c
333
writel(value, aio->cygaud->audio + aio->regs.bf_destch_cfg);
sound/soc/bcm/cygnus-ssp.c
335
writel(0x1, aio->cygaud->audio + aio->regs.bf_destch_ctrl);
sound/soc/bcm/cygnus-ssp.c
340
writel(value, aio->cygaud->audio + aio->regs.i2s_cfg);
sound/soc/bcm/cygnus-ssp.c
344
writel(value, aio->cygaud->i2s_in + aio->regs.i2s_cap_stream_cfg);
sound/soc/bcm/cygnus-ssp.c
355
writel(value, aio->cygaud->i2s_in + aio->regs.i2s_cap_stream_cfg);
sound/soc/bcm/cygnus-ssp.c
364
writel(value, aio->cygaud->audio + aio->regs.i2s_cfg);
sound/soc/bcm/cygnus-ssp.c
367
writel(0x0, aio->cygaud->audio + aio->regs.bf_destch_ctrl);
sound/soc/bcm/cygnus-ssp.c
371
writel(value, aio->cygaud->audio + aio->regs.bf_destch_cfg);
sound/soc/bcm/cygnus-ssp.c
383
writel(value, aio->cygaud->audio + aio->regs.i2s_stream_cfg);
sound/soc/bcm/cygnus-ssp.c
385
writel(1, aio->cygaud->audio + aio->regs.bf_sourcech_ctrl);
sound/soc/bcm/cygnus-ssp.c
390
writel(value, aio->cygaud->audio + aio->regs.i2s_cfg);
sound/soc/bcm/cygnus-ssp.c
394
writel(value, aio->cygaud->audio + aio->regs.bf_sourcech_cfg);
sound/soc/bcm/cygnus-ssp.c
401
writel(value, aio->cygaud->audio + SPDIF_FORMAT_CFG_OFFSET);
sound/soc/bcm/cygnus-ssp.c
403
writel(1, aio->cygaud->audio + aio->regs.bf_sourcech_ctrl);
sound/soc/bcm/cygnus-ssp.c
407
writel(value, aio->cygaud->audio + aio->regs.bf_sourcech_cfg);
sound/soc/bcm/cygnus-ssp.c
432
writel(value, aio->cygaud->audio + aio->regs.i2s_cfg);
sound/soc/bcm/cygnus-ssp.c
438
writel(value, aio->cygaud->audio + BF_SRC_GRP_SYNC_DIS_OFFSET);
sound/soc/bcm/cygnus-ssp.c
440
writel(0, aio->cygaud->audio + aio->regs.bf_sourcech_ctrl);
sound/soc/bcm/cygnus-ssp.c
444
writel(value, aio->cygaud->audio + aio->regs.bf_sourcech_cfg);
sound/soc/bcm/cygnus-ssp.c
449
writel(value, aio->cygaud->audio + BF_SRC_GRP_SYNC_DIS_OFFSET);
sound/soc/bcm/cygnus-ssp.c
453
writel(value, aio->cygaud->audio + aio->regs.i2s_stream_cfg);
sound/soc/bcm/cygnus-ssp.c
458
writel(value, aio->cygaud->i2s_in + IOP_SW_INIT_LOGIC);
sound/soc/bcm/cygnus-ssp.c
460
writel(value, aio->cygaud->i2s_in + IOP_SW_INIT_LOGIC);
sound/soc/bcm/cygnus-ssp.c
465
writel(value, aio->cygaud->audio + SPDIF_FORMAT_CFG_OFFSET);
sound/soc/bcm/cygnus-ssp.c
466
writel(0, aio->cygaud->audio + aio->regs.bf_sourcech_ctrl);
sound/soc/bcm/cygnus-ssp.c
470
writel(value, aio->cygaud->audio + aio->regs.bf_sourcech_cfg);
sound/soc/bcm/cygnus-ssp.c
587
writel(value, aio->cygaud->audio + aio->regs.i2s_cfg);
sound/soc/bcm/cygnus-ssp.c
602
writel(value, aio->cygaud->audio + aio->regs.i2s_mclk_cfg);
sound/soc/bcm/cygnus-ssp.c
649
writel(value, aio->cygaud->audio + aio->regs.bf_sourcech_cfg);
sound/soc/bcm/cygnus-ssp.c
668
writel(value, aio->cygaud->audio + aio->regs.bf_sourcech_cfg);
sound/soc/bcm/cygnus-ssp.c
677
writel(value, aio->cygaud->audio +
sound/soc/bcm/cygnus-ssp.c
685
writel(value, aio->cygaud->audio +
sound/soc/bcm/cygnus-ssp.c
728
writel(value, aio->cygaud->audio + aio->regs.i2s_mclk_cfg);
sound/soc/bcm/cygnus-ssp.c
888
writel(ssp_outcfg, aio->cygaud->audio + aio->regs.i2s_cfg);
sound/soc/bcm/cygnus-ssp.c
896
writel(ssp_incfg, aio->cygaud->i2s_in + aio->regs.i2s_cap_cfg);
sound/soc/bcm/cygnus-ssp.c
917
writel(val, aio->cygaud->audio + AUD_MISC_SEROUT_OE_REG_BASE);
sound/soc/codecs/jz4725b.c
563
writel(tmp, icdc->base + ICDC_RGADW_OFFSET);
sound/soc/codecs/jz4725b.c
583
writel(ICDC_RGADW_RGWR | (reg << ICDC_RGADW_RGADDR_OFFSET) | val,
sound/soc/codecs/jz4760.c
764
writel(tmp, codec->base + ICDC_RGADW_OFFSET);
sound/soc/codecs/jz4760.c
784
writel(ICDC_RGADW_RGWR | FIELD_PREP(ICDC_RGADW_RGADDR_MASK, reg) | val,
sound/soc/codecs/jz4770.c
809
writel(tmp, codec->base + ICDC_RGADW_OFFSET);
sound/soc/codecs/jz4770.c
829
writel(ICDC_RGADW_RGWR | (reg << ICDC_RGADW_RGADDR_OFFSET) | val,
sound/soc/dwc/dwc-i2s.c
33
writel(val, io_base + reg);
sound/soc/fsl/imx-audmux.c
190
writel(pcr, audmux_base + port_mapping[port]);
sound/soc/fsl/imx-audmux.c
211
writel(ptcr, audmux_base + IMX_AUDMUX_V2_PTCR(port));
sound/soc/fsl/imx-audmux.c
212
writel(pdcr, audmux_base + IMX_AUDMUX_V2_PDCR(port));
sound/soc/fsl/imx-audmux.c
344
writel(regcache[i], audmux_base + i * 4);
sound/soc/google/chv3-i2s.c
103
writel(val, i2s->iobase + offset);
sound/soc/google/chv3-i2s.c
126
writel(reg, i2s->iobase_irq + I2S_IRQ_CLR);
sound/soc/google/chv3-i2s.c
224
writel(I2S_IRQ_RX_BIT | I2S_IRQ_TX_BIT, i2s->iobase_irq + I2S_IRQ_MASK);
sound/soc/hisilicon/hi6210-i2s.c
82
writel(val, i2s->base + reg);
sound/soc/img/img-i2s-in.c
101
writel(val, i2s->channel_base + (chan * IMG_I2S_IN_CH_STRIDE) + reg);
sound/soc/img/img-i2s-in.c
90
writel(val, i2s->base + reg);
sound/soc/img/img-i2s-out.c
101
writel(val, i2s->base + reg);
sound/soc/img/img-i2s-out.c
112
writel(val, i2s->channel_base + (chan * IMG_I2S_OUT_CH_STRIDE) + reg);
sound/soc/img/img-parallel-out.c
70
writel(val, prl->base + reg);
sound/soc/img/img-spdif-in.c
116
writel(val, spdif->base + reg);
sound/soc/img/img-spdif-out.c
86
writel(val, spdif->base + reg);
sound/soc/intel/atom/sst/sst_pvt.c
32
writel(value, addr + offset);
sound/soc/intel/avs/apl.c
180
writel(layout.write_ptr, addr);
sound/soc/intel/avs/apl.c
96
writel(layout.write_ptr, addr);
sound/soc/intel/avs/core.c
117
writel(0, hlink->ml_addr + AZX_REG_ML_LOSIDV);
sound/soc/intel/avs/pcm.c
1122
writel(host_stream->pphcllpl, host_stream->pphc_addr + AZX_REG_PPHCLLPL);
sound/soc/intel/avs/pcm.c
1123
writel(host_stream->pphcllpu, host_stream->pphc_addr + AZX_REG_PPHCLLPU);
sound/soc/intel/avs/pcm.c
1124
writel(host_stream->pphcldpl, host_stream->pphc_addr + AZX_REG_PPHCLDPL);
sound/soc/intel/avs/pcm.c
1125
writel(host_stream->pphcldpu, host_stream->pphc_addr + AZX_REG_PPHCLDPU);
sound/soc/intel/catpt/registers.h
152
writel(val, catpt_ssp_addr(cdev, ssp) + (reg))
sound/soc/intel/catpt/registers.h
157
writel(val, catpt_shim_addr(cdev) + CATPT_SHIM_##reg)
sound/soc/intel/catpt/registers.h
169
writel(val, cdev->pci_ba + CATPT_PCI_##reg)
sound/soc/intel/keembay/kmb_platform.c
113
writel(((u16(*)[2])buf)[tx_ptr][0], i2s_base + LRBR_LTHR(0));
sound/soc/intel/keembay/kmb_platform.c
114
writel(((u16(*)[2])buf)[tx_ptr][1], i2s_base + RRBR_RTHR(0));
sound/soc/intel/keembay/kmb_platform.c
116
writel(((u32(*)[2])buf)[tx_ptr][0], i2s_base + LRBR_LTHR(0));
sound/soc/intel/keembay/kmb_platform.c
117
writel(((u32(*)[2])buf)[tx_ptr][1], i2s_base + RRBR_RTHR(0));
sound/soc/intel/keembay/kmb_platform.c
175
writel(0, kmb_i2s->i2s_base + TER(i));
sound/soc/intel/keembay/kmb_platform.c
178
writel(0, kmb_i2s->i2s_base + RER(i));
sound/soc/intel/keembay/kmb_platform.c
215
writel(irq, kmb_i2s->i2s_base + IMR(i));
sound/soc/intel/keembay/kmb_platform.c
427
writel(dma_reg, kmb_i2s->i2s_base + I2S_DMACR);
sound/soc/intel/keembay/kmb_platform.c
438
writel(1, kmb_i2s->i2s_base + I2S_RTXDMA);
sound/soc/intel/keembay/kmb_platform.c
441
writel(1, kmb_i2s->i2s_base + I2S_RRXDMA);
sound/soc/intel/keembay/kmb_platform.c
443
writel(dma_reg, kmb_i2s->i2s_base + I2S_DMACR);
sound/soc/intel/keembay/kmb_platform.c
452
writel(1, kmb_i2s->i2s_base + IER);
sound/soc/intel/keembay/kmb_platform.c
455
writel(1, kmb_i2s->i2s_base + ITER);
sound/soc/intel/keembay/kmb_platform.c
457
writel(1, kmb_i2s->i2s_base + IRER);
sound/soc/intel/keembay/kmb_platform.c
466
writel(1, kmb_i2s->i2s_base + CER);
sound/soc/intel/keembay/kmb_platform.c
468
writel(0, kmb_i2s->i2s_base + CER);
sound/soc/intel/keembay/kmb_platform.c
478
writel(0, kmb_i2s->i2s_base + ITER);
sound/soc/intel/keembay/kmb_platform.c
480
writel(0, kmb_i2s->i2s_base + IRER);
sound/soc/intel/keembay/kmb_platform.c
485
writel(0, kmb_i2s->i2s_base + CER);
sound/soc/intel/keembay/kmb_platform.c
486
writel(0, kmb_i2s->i2s_base + IER);
sound/soc/intel/keembay/kmb_platform.c
506
writel(CLOCK_PROVIDER_MODE, kmb_i2s->pss_base + I2S_GEN_CFG_0);
sound/soc/intel/keembay/kmb_platform.c
560
writel(kmb_i2s->xfer_resolution,
sound/soc/intel/keembay/kmb_platform.c
563
writel(kmb_i2s->fifo_th - 1,
sound/soc/intel/keembay/kmb_platform.c
566
writel(1, kmb_i2s->i2s_base + TER(ch_reg));
sound/soc/intel/keembay/kmb_platform.c
568
writel(kmb_i2s->xfer_resolution,
sound/soc/intel/keembay/kmb_platform.c
571
writel(kmb_i2s->fifo_th - 1,
sound/soc/intel/keembay/kmb_platform.c
574
writel(1, kmb_i2s->i2s_base + RER(ch_reg));
sound/soc/intel/keembay/kmb_platform.c
634
writel(write_val, kmb_i2s->pss_base + I2S_GEN_CFG_0);
sound/soc/intel/keembay/kmb_platform.c
648
writel(write_val, kmb_i2s->pss_base + I2S_GEN_CFG_0);
sound/soc/intel/keembay/kmb_platform.c
657
writel(kmb_i2s->ccr, kmb_i2s->i2s_base + CCR);
sound/soc/intel/keembay/kmb_platform.c
682
writel(1, kmb_i2s->i2s_base + TXFFR);
sound/soc/intel/keembay/kmb_platform.c
684
writel(1, kmb_i2s->i2s_base + RXFFR);
sound/soc/intel/keembay/kmb_platform.c
717
writel(0, kmb_i2s->i2s_base + ITER);
sound/soc/intel/keembay/kmb_platform.c
719
writel(0, kmb_i2s->i2s_base + IRER);
sound/soc/intel/keembay/kmb_platform.c
727
writel(0, kmb_i2s->i2s_base + CER);
sound/soc/intel/keembay/kmb_platform.c
728
writel(0, kmb_i2s->i2s_base + IER);
sound/soc/kirkwood/kirkwood-dma.c
140
writel((unsigned int)-1, priv->io + KIRKWOOD_ERR_MASK);
sound/soc/kirkwood/kirkwood-dma.c
170
writel(0, priv->io + KIRKWOOD_ERR_MASK);
sound/soc/kirkwood/kirkwood-dma.c
210
writel(count, priv->io + KIRKWOOD_PLAY_BYTE_INT_COUNT);
sound/soc/kirkwood/kirkwood-dma.c
211
writel(runtime->dma_addr, priv->io + KIRKWOOD_PLAY_BUF_ADDR);
sound/soc/kirkwood/kirkwood-dma.c
212
writel(size, priv->io + KIRKWOOD_PLAY_BUF_SIZE);
sound/soc/kirkwood/kirkwood-dma.c
214
writel(count, priv->io + KIRKWOOD_REC_BYTE_INT_COUNT);
sound/soc/kirkwood/kirkwood-dma.c
215
writel(runtime->dma_addr, priv->io + KIRKWOOD_REC_BUF_ADDR);
sound/soc/kirkwood/kirkwood-dma.c
216
writel(size, priv->io + KIRKWOOD_REC_BUF_SIZE);
sound/soc/kirkwood/kirkwood-dma.c
53
writel(cause, priv->io + KIRKWOOD_ERR_CAUSE);
sound/soc/kirkwood/kirkwood-dma.c
65
writel(status, priv->io + KIRKWOOD_INT_CAUSE);
sound/soc/kirkwood/kirkwood-dma.c
84
writel(0, base + KIRKWOOD_AUDIO_WIN_CTRL_REG(win));
sound/soc/kirkwood/kirkwood-dma.c
85
writel(0, base + KIRKWOOD_AUDIO_WIN_BASE_REG(win));
sound/soc/kirkwood/kirkwood-dma.c
91
writel(cs->base & 0xffff0000,
sound/soc/kirkwood/kirkwood-dma.c
93
writel(((cs->size - 1) & 0xffff0000) |
sound/soc/kirkwood/kirkwood-i2s.c
124
writel(reg_val, base + A38X_PLL_CONF_REG0);
sound/soc/kirkwood/kirkwood-i2s.c
129
writel(reg_val, base + A38X_PLL_CONF_REG2);
sound/soc/kirkwood/kirkwood-i2s.c
134
writel(reg_val, base + A38X_PLL_CONF_REG1);
sound/soc/kirkwood/kirkwood-i2s.c
140
writel(reg_val, base + A38X_PLL_CONF_REG1);
sound/soc/kirkwood/kirkwood-i2s.c
147
writel(reg_val, base + A38X_PLL_CONF_REG1);
sound/soc/kirkwood/kirkwood-i2s.c
178
writel(value, priv->io+KIRKWOOD_I2S_PLAYCTL);
sound/soc/kirkwood/kirkwood-i2s.c
183
writel(value, priv->io+KIRKWOOD_I2S_RECCTL);
sound/soc/kirkwood/kirkwood-i2s.c
205
writel(value, io + KIRKWOOD_DCO_CTL);
sound/soc/kirkwood/kirkwood-i2s.c
240
writel(clks_ctrl, priv->io + KIRKWOOD_CLOCKS_CTRL);
sound/soc/kirkwood/kirkwood-i2s.c
333
writel(i2s_value, priv->io+i2s_reg);
sound/soc/kirkwood/kirkwood-i2s.c
385
writel(value, priv->io + KIRKWOOD_PLAYCTL);
sound/soc/kirkwood/kirkwood-i2s.c
391
writel(value, priv->io + KIRKWOOD_INT_MASK);
sound/soc/kirkwood/kirkwood-i2s.c
395
writel(ctl, priv->io + KIRKWOOD_PLAYCTL);
sound/soc/kirkwood/kirkwood-i2s.c
402
writel(ctl, priv->io + KIRKWOOD_PLAYCTL);
sound/soc/kirkwood/kirkwood-i2s.c
406
writel(value, priv->io + KIRKWOOD_INT_MASK);
sound/soc/kirkwood/kirkwood-i2s.c
410
writel(ctl, priv->io + KIRKWOOD_PLAYCTL);
sound/soc/kirkwood/kirkwood-i2s.c
417
writel(ctl, priv->io + KIRKWOOD_PLAYCTL);
sound/soc/kirkwood/kirkwood-i2s.c
425
writel(ctl, priv->io + KIRKWOOD_PLAYCTL);
sound/soc/kirkwood/kirkwood-i2s.c
453
writel(value, priv->io + KIRKWOOD_RECCTL);
sound/soc/kirkwood/kirkwood-i2s.c
458
writel(value, priv->io + KIRKWOOD_INT_MASK);
sound/soc/kirkwood/kirkwood-i2s.c
461
writel(ctl, priv->io + KIRKWOOD_RECCTL);
sound/soc/kirkwood/kirkwood-i2s.c
468
writel(value, priv->io + KIRKWOOD_RECCTL);
sound/soc/kirkwood/kirkwood-i2s.c
472
writel(value, priv->io + KIRKWOOD_INT_MASK);
sound/soc/kirkwood/kirkwood-i2s.c
477
writel(value, priv->io + KIRKWOOD_RECCTL);
sound/soc/kirkwood/kirkwood-i2s.c
484
writel(value, priv->io + KIRKWOOD_RECCTL);
sound/soc/kirkwood/kirkwood-i2s.c
491
writel(value, priv->io + KIRKWOOD_RECCTL);
sound/soc/kirkwood/kirkwood-i2s.c
519
writel(0xffffffff, priv->io + KIRKWOOD_INT_CAUSE);
sound/soc/kirkwood/kirkwood-i2s.c
520
writel(0, priv->io + KIRKWOOD_INT_MASK);
sound/soc/kirkwood/kirkwood-i2s.c
525
writel(reg_data, priv->io + 0x1200);
sound/soc/kirkwood/kirkwood-i2s.c
532
writel(reg_data, priv->io + 0x1200);
sound/soc/kirkwood/kirkwood-i2s.c
537
writel(value, priv->io + KIRKWOOD_PLAYCTL);
sound/soc/kirkwood/kirkwood-i2s.c
541
writel(value, priv->io + KIRKWOOD_RECCTL);
sound/soc/kirkwood/kirkwood-i2s.c
77
writel(reg_val, priv->soc_control);
sound/soc/kirkwood/kirkwood-i2s.c
98
writel(reg_val, base + A38X_PLL_CONF_REG1);
sound/soc/loongson/loongson1_ac97.c
150
writel(0, ls1x_ac97->reg_base + AC97_INTRAW);
sound/soc/loongson/loongson1_ac97.c
151
writel(0, ls1x_ac97->reg_base + AC97_INTM);
sound/soc/loongson/loongson_i2s_plat.c
108
writel(val, regs);
sound/soc/pxa/pxa2xx-i2s.c
103
writel(0, i2s_reg_base + SACR0);
sound/soc/pxa/pxa2xx-i2s.c
175
writel(0, i2s_reg_base + SACR0);
sound/soc/pxa/pxa2xx-i2s.c
177
writel(readl(i2s_reg_base + SACR0) | (SACR0_BCKD), i2s_reg_base + SACR0);
sound/soc/pxa/pxa2xx-i2s.c
179
writel(readl(i2s_reg_base + SACR0) | (SACR0_RFTH(14) | SACR0_TFTH(1)), i2s_reg_base + SACR0);
sound/soc/pxa/pxa2xx-i2s.c
180
writel(readl(i2s_reg_base + SACR1) | (pxa_i2s.fmt), i2s_reg_base + SACR1);
sound/soc/pxa/pxa2xx-i2s.c
183
writel(readl(i2s_reg_base + SAIMR) | (SAIMR_TFS), i2s_reg_base + SAIMR);
sound/soc/pxa/pxa2xx-i2s.c
185
writel(readl(i2s_reg_base + SAIMR) | (SAIMR_RFS), i2s_reg_base + SAIMR);
sound/soc/pxa/pxa2xx-i2s.c
189
writel(0x48, i2s_reg_base + SADIV);
sound/soc/pxa/pxa2xx-i2s.c
192
writel(0x34, i2s_reg_base + SADIV);
sound/soc/pxa/pxa2xx-i2s.c
195
writel(0x24, i2s_reg_base + SADIV);
sound/soc/pxa/pxa2xx-i2s.c
198
writel(0x1a, i2s_reg_base + SADIV);
sound/soc/pxa/pxa2xx-i2s.c
201
writel(0xd, i2s_reg_base + SADIV);
sound/soc/pxa/pxa2xx-i2s.c
204
writel(0xc, i2s_reg_base + SADIV);
sound/soc/pxa/pxa2xx-i2s.c
207
writel(0x6, i2s_reg_base + SADIV);
sound/soc/pxa/pxa2xx-i2s.c
222
writel(readl(i2s_reg_base + SACR1) & (~SACR1_DRPL), i2s_reg_base + SACR1);
sound/soc/pxa/pxa2xx-i2s.c
224
writel(readl(i2s_reg_base + SACR1) & (~SACR1_DREC), i2s_reg_base + SACR1);
sound/soc/pxa/pxa2xx-i2s.c
225
writel(readl(i2s_reg_base + SACR0) | (SACR0_ENB), i2s_reg_base + SACR0);
sound/soc/pxa/pxa2xx-i2s.c
244
writel(readl(i2s_reg_base + SACR1) | (SACR1_DRPL), i2s_reg_base + SACR1);
sound/soc/pxa/pxa2xx-i2s.c
245
writel(readl(i2s_reg_base + SAIMR) & (~SAIMR_TFS), i2s_reg_base + SAIMR);
sound/soc/pxa/pxa2xx-i2s.c
247
writel(readl(i2s_reg_base + SACR1) | (SACR1_DREC), i2s_reg_base + SACR1);
sound/soc/pxa/pxa2xx-i2s.c
248
writel(readl(i2s_reg_base + SAIMR) & (~SAIMR_RFS), i2s_reg_base + SAIMR);
sound/soc/pxa/pxa2xx-i2s.c
252
writel(readl(i2s_reg_base + SACR0) & (~SACR0_ENB), i2s_reg_base + SACR0);
sound/soc/pxa/pxa2xx-i2s.c
271
writel(readl(i2s_reg_base + SACR0) & (~SACR0_ENB), i2s_reg_base + SACR0);
sound/soc/pxa/pxa2xx-i2s.c
280
writel(pxa_i2s.sacr0 & ~SACR0_ENB, i2s_reg_base + SACR0);
sound/soc/pxa/pxa2xx-i2s.c
281
writel(pxa_i2s.sacr1, i2s_reg_base + SACR1);
sound/soc/pxa/pxa2xx-i2s.c
282
writel(pxa_i2s.saimr, i2s_reg_base + SAIMR);
sound/soc/pxa/pxa2xx-i2s.c
283
writel(pxa_i2s.sadiv, i2s_reg_base + SADIV);
sound/soc/pxa/pxa2xx-i2s.c
285
writel(pxa_i2s.sacr0, i2s_reg_base + SACR0);
sound/soc/pxa/pxa2xx-i2s.c
307
writel(SACR0_RST, i2s_reg_base + SACR0);
sound/soc/pxa/pxa2xx-i2s.c
308
writel(0, i2s_reg_base + SACR0);
sound/soc/pxa/pxa2xx-i2s.c
310
writel(SACR1_DRPL | SACR1_DREC, i2s_reg_base + SACR1);
sound/soc/pxa/pxa2xx-i2s.c
312
writel(readl(i2s_reg_base + SAIMR) & (~(SAIMR_RFS | SAIMR_TFS)), i2s_reg_base + SAIMR);
sound/soc/qcom/apq8016_sbc.c
70
writel(readl(pdata->spkr_iomux) | SPKR_CTL_PRI_WS_SLAVE_SEL_11,
sound/soc/qcom/apq8016_sbc.c
76
writel(readl(pdata->mic_iomux) | MIC_CTRL_QUA_WS_SLAVE_SEL_10 |
sound/soc/qcom/apq8016_sbc.c
85
writel(value | SPKR_CTL_TLMM_MCLK_EN | SPKR_CTL_TLMM_SCLK_EN |
sound/soc/qcom/apq8016_sbc.c
90
writel(readl(pdata->mic_iomux) | MIC_CTRL_TER_WS_SLAVE_SEL |
sound/soc/renesas/rz-ssi.c
157
writel(data, (priv->base + reg));
sound/soc/renesas/rz-ssi.c
172
writel(val, (priv->base + reg));
sound/soc/samsung/i2s.c
1071
writel(CON_RSTCLR, priv->addr + I2SCON);
sound/soc/samsung/i2s.c
1110
writel(0, priv->addr + I2SCON);
sound/soc/samsung/i2s.c
1250
writel(priv->suspend_i2scon, priv->addr + I2SCON);
sound/soc/samsung/i2s.c
1251
writel(priv->suspend_i2smod, priv->addr + I2SMOD);
sound/soc/samsung/i2s.c
1252
writel(priv->suspend_i2spsr, priv->addr + I2SPSR);
sound/soc/samsung/i2s.c
1309
writel(val | PSR_PSREN, priv->addr + I2SPSR);
sound/soc/samsung/i2s.c
1598
writel(PSR_PSVAL(2) | PSR_PSREN, priv->addr + I2SPSR);
sound/soc/samsung/i2s.c
305
writel(mod, priv->addr + I2SMOD);
sound/soc/samsung/i2s.c
379
writel(mod, priv->addr + I2SMOD);
sound/soc/samsung/i2s.c
431
writel(con, addr + I2SCON);
sound/soc/samsung/i2s.c
443
writel(mod, addr + I2SMOD);
sound/soc/samsung/i2s.c
444
writel(con, addr + I2SCON);
sound/soc/samsung/i2s.c
474
writel(mod, addr + I2SMOD);
sound/soc/samsung/i2s.c
475
writel(con, addr + I2SCON);
sound/soc/samsung/i2s.c
493
writel(readl(fic) | flush, fic);
sound/soc/samsung/i2s.c
500
writel(readl(fic) & ~flush, fic);
sound/soc/samsung/i2s.c
618
writel(mod, priv->addr + I2SMOD);
sound/soc/samsung/i2s.c
717
writel(mod, priv->addr + I2SMOD);
sound/soc/samsung/i2s.c
807
writel(mod, priv->addr + I2SMOD);
sound/soc/samsung/i2s.c
842
writel(CON_RSTCLR, i2s->priv->addr + I2SCON);
sound/soc/samsung/i2s.c
926
writel(((psr - 1) << 8) | PSR_PSREN, priv->addr + I2SPSR);
sound/soc/samsung/idma.c
127
writel(val, idma.regs + I2SAHB);
sound/soc/samsung/idma.c
151
writel(ahb, idma.regs + I2SAHB);
sound/soc/samsung/idma.c
152
writel(mod, idma.regs + I2SMOD);
sound/soc/samsung/idma.c
268
writel(iisahb, idma.regs + I2SAHB);
sound/soc/samsung/idma.c
275
writel(addr, idma.regs + I2SLVL0ADDR);
sound/soc/samsung/idma.c
76
writel(val, idma.regs + I2SLVL0ADDR);
sound/soc/samsung/idma.c
80
writel(val, idma.regs + I2SSTR0);
sound/soc/samsung/idma.c
90
writel(val, idma.regs + I2SSIZE);
sound/soc/samsung/idma.c
94
writel(val, idma.regs + I2SAHB);
sound/soc/samsung/pcm.c
181
writel(clkctl, regs + S3C_PCM_CLKCTL);
sound/soc/samsung/pcm.c
182
writel(ctl, regs + S3C_PCM_CTL);
sound/soc/samsung/pcm.c
212
writel(clkctl, regs + S3C_PCM_CLKCTL);
sound/soc/samsung/pcm.c
213
writel(ctl, regs + S3C_PCM_CTL);
sound/soc/samsung/pcm.c
307
writel(clkctl, regs + S3C_PCM_CLKCTL);
sound/soc/samsung/pcm.c
381
writel(ctl, regs + S3C_PCM_CTL);
sound/soc/samsung/pcm.c
430
writel(clkctl, regs + S3C_PCM_CLKCTL);
sound/soc/samsung/spdif.c
114
writel(clkcon | CLKCTL_PWR_ON, regs + CLKCON);
sound/soc/samsung/spdif.c
116
writel(clkcon & ~CLKCTL_PWR_ON, regs + CLKCON);
sound/soc/samsung/spdif.c
134
writel(clkcon, spdif->regs + CLKCON);
sound/soc/samsung/spdif.c
267
writel(con, regs + CON);
sound/soc/samsung/spdif.c
268
writel(cstas, regs + CSTAS);
sound/soc/samsung/spdif.c
269
writel(clkcon, regs + CLKCON);
sound/soc/samsung/spdif.c
292
writel(con | CON_SW_RESET, regs + CON);
sound/soc/samsung/spdif.c
295
writel(clkcon & ~CLKCTL_PWR_ON, regs + CLKCON);
sound/soc/samsung/spdif.c
310
writel(con | CON_SW_RESET, spdif->regs + CON);
sound/soc/samsung/spdif.c
322
writel(spdif->saved_clkcon, spdif->regs + CLKCON);
sound/soc/samsung/spdif.c
323
writel(spdif->saved_con, spdif->regs + CON);
sound/soc/samsung/spdif.c
324
writel(spdif->saved_cstas, spdif->regs + CSTAS);
sound/soc/sof/imx/imx8.c
143
writel(pwrctl, chip->dap + IMX8M_DAP_PWRCTL);
sound/soc/sof/imx/imx8.c
153
writel(pwrctl, chip->dap + IMX8M_DAP_PWRCTL);
sound/soc/sof/intel/hda-mlink.c
235
writel(val, lctl);
sound/soc/sof/intel/hda-mlink.c
249
writel(val, lctl);
sound/soc/sof/intel/hda-mlink.c
264
writel(val, lctl);
sound/soc/sof/intel/hda-mlink.c
308
writel(val, lsync);
sound/soc/sof/intel/hda-mlink.c
323
writel(val, lsync);
sound/soc/sof/intel/hda-mlink.c
333
writel(val, lsync);
sound/soc/sof/intel/hda-mlink.c
384
writel(val, lctl);
sound/soc/sof/intel/hda-mlink.c
902
writel(0, hlink->ml_addr + AZX_REG_ML_LOSIDV);
sound/soc/sof/iomem-utils.c
28
writel(value, addr);
sound/soc/sof/mediatek/mt8195/mt8195.c
127
writel(srampool_con & ~DSP_SRAM_POOL_PD_MASK, va_dspsysreg);
sound/soc/sof/mediatek/mt8195/mt8195.c
129
writel(srampool_con | DSP_SRAM_POOL_PD_MASK, va_dspsysreg);
sound/soc/sof/mediatek/mt8195/mt8195.c
155
writel(offset, vaddr_emi_map);
sound/soc/sof/ops.h
328
writel(value, sdev->bar[bar] + offset);
sound/soc/sophgo/cv1800b-sound-adc.c
126
writel(val, priv->regs + CV1800B_RXADC_CLK);
sound/soc/sophgo/cv1800b-sound-adc.c
138
writel(val, priv->regs + CV1800B_RXADC_CTRL0);
sound/soc/sophgo/cv1800b-sound-adc.c
178
writel(val, priv->regs + CV1800B_RXADCC_CTRL1);
sound/soc/sophgo/cv1800b-sound-adc.c
261
writel(val, priv->regs + CV1800B_RXADC_ANA0);
sound/soc/sophgo/cv1800b-sound-dac.c
57
writel(val, priv->regs + CV1800B_TXDAC_CTRL0);
sound/soc/sophgo/cv1800b-sound-dac.c
71
writel(val, priv->regs + CV1800B_TXDAC_ANA2);
sound/soc/sophgo/cv1800b-sound-dac.c
83
writel(val, priv->regs + CV1800B_TXDAC_CTRL1);
sound/soc/sophgo/cv1800b-sound-dac.c
96
writel(val, priv->regs + CV1800B_TXDAC_AFE0);
sound/soc/sophgo/cv1800b-tdm.c
155
writel(val, i2s->base + CV1800B_FIFO_RESET);
sound/soc/sophgo/cv1800b-tdm.c
162
writel(val, i2s->base + CV1800B_FIFO_RESET);
sound/soc/sophgo/cv1800b-tdm.c
172
writel(val, i2s->base + CV1800B_I2S_RESET);
sound/soc/sophgo/cv1800b-tdm.c
179
writel(val, i2s->base + CV1800B_I2S_RESET);
sound/soc/sophgo/cv1800b-tdm.c
188
writel(val, i2s->base + CV1800B_CLK_CTRL1);
sound/soc/sophgo/cv1800b-tdm.c
198
writel(val, i2s->base + CV1800B_BLK_MODE_SETTING);
sound/soc/sophgo/cv1800b-tdm.c
211
writel(val, i2s->base + CV1800B_CLK_CTRL1);
sound/soc/sophgo/cv1800b-tdm.c
240
writel(val, i2s->base + CV1800B_DATA_FORMAT);
sound/soc/sophgo/cv1800b-tdm.c
250
writel(val, i2s->base + CV1800B_CLK_CTRL0);
sound/soc/sophgo/cv1800b-tdm.c
285
writel(val, i2s->base + CV1800B_SLOT_SETTING1);
sound/soc/sophgo/cv1800b-tdm.c
290
writel(val, i2s->base + CV1800B_FRAME_SETTING);
sound/soc/sophgo/cv1800b-tdm.c
454
writel(val, i2s->base + CV1800B_I2S_ENABLE);
sound/soc/sophgo/cv1800b-tdm.c
514
writel(val, i2s->base + CV1800B_BLK_MODE_SETTING);
sound/soc/sophgo/cv1800b-tdm.c
545
writel(val, i2s->base + CV1800B_CLK_CTRL0);
sound/soc/sophgo/cv1800b-tdm.c
590
writel(val, i2s->base + CV1800B_I2S_ENABLE);
sound/soc/sophgo/cv1800b-tdm.c
595
writel(val, i2s->base + CV1800B_CLK_CTRL0);
sound/soc/sophgo/cv1800b-tdm.c
600
writel(val, i2s->base + CV1800B_I2S_RESET);
sound/soc/sophgo/cv1800b-tdm.c
605
writel(val, i2s->base + CV1800B_FIFO_RESET);
sound/soc/sophgo/cv1800b-tdm.c
614
writel(val, i2s->base + CV1800B_BLK_MODE_SETTING);
sound/soc/sophgo/cv1800b-tdm.c
620
writel(val, i2s->base + CV1800B_CLK_CTRL0);
sound/soc/sophgo/cv1800b-tdm.c
626
writel(val, i2s->base + CV1800B_FIFO_THRESHOLD);
sound/soc/sophgo/cv1800b-tdm.c
630
writel(val, i2s->base + CV1800B_I2S_ENABLE);
sound/soc/spacemit/k1_i2s.c
102
writel(sscr_val, i2s->base + SSCR);
sound/soc/spacemit/k1_i2s.c
103
writel(ssfcr_val, i2s->base + SSFCR);
sound/soc/spacemit/k1_i2s.c
104
writel(sspsp_val, i2s->base + SSPSP);
sound/soc/spacemit/k1_i2s.c
105
writel(ssrwt_val, i2s->base + SSRWT);
sound/soc/spacemit/k1_i2s.c
106
writel(0, i2s->base + SSINTEN);
sound/soc/spacemit/k1_i2s.c
186
writel(val, i2s->base + SSCR);
sound/soc/spacemit/k1_i2s.c
238
writel(sspsp_val, i2s->base + SSPSP);
sound/soc/spacemit/k1_i2s.c
256
writel(val, i2s->base + SSCR);
sound/soc/spacemit/k1_i2s.c
269
writel(val, i2s->base + SSCR);
sound/soc/spear/spdif_in.c
130
writel(ctrl, host->io_base + SPDIF_IN_CTRL);
sound/soc/spear/spdif_in.c
131
writel(0xF, host->io_base + SPDIF_IN_IRQ_MASK);
sound/soc/spear/spdif_in.c
139
writel(ctrl, host->io_base + SPDIF_IN_CTRL);
sound/soc/spear/spdif_in.c
140
writel(0x0, host->io_base + SPDIF_IN_IRQ_MASK);
sound/soc/spear/spdif_in.c
197
writel(0, host->io_base + SPDIF_IN_IRQ);
sound/soc/spear/spdif_in.c
52
writel(ctrl, host->io_base + SPDIF_IN_CTRL);
sound/soc/spear/spdif_in.c
53
writel(0xF, host->io_base + SPDIF_IN_IRQ_MASK);
sound/soc/spear/spdif_in.c
74
writel(0x0, host->io_base + SPDIF_IN_IRQ_MASK);
sound/soc/spear/spdif_in.c
91
writel(ctrl, host->io_base + SPDIF_IN_CTRL);
sound/soc/spear/spdif_out.c
102
writel(ctrl, host->io_base + SPDIF_OUT_CTRL);
sound/soc/spear/spdif_out.c
172
writel(ctrl, host->io_base + SPDIF_OUT_CTRL);
sound/soc/spear/spdif_out.c
181
writel(ctrl, host->io_base + SPDIF_OUT_CTRL);
sound/soc/spear/spdif_out.c
209
writel(val, host->io_base + SPDIF_OUT_CTRL);
sound/soc/spear/spdif_out.c
46
writel(SPDIF_OUT_RESET, host->io_base + SPDIF_OUT_SOFT_RST);
sound/soc/spear/spdif_out.c
48
writel(readl(host->io_base + SPDIF_OUT_SOFT_RST) & ~SPDIF_OUT_RESET,
sound/soc/spear/spdif_out.c
51
writel(SPDIF_OUT_FDMA_TRIG_16 | SPDIF_OUT_MEMFMT_16_16 |
sound/soc/spear/spdif_out.c
56
writel(0x7F, host->io_base + SPDIF_OUT_INT_STA_CLR);
sound/soc/spear/spdif_out.c
57
writel(0x7F, host->io_base + SPDIF_OUT_INT_EN_CLR);
sound/soc/starfive/jh7110_pwmdac.c
103
writel(val, io_base + reg);
sound/soc/sunxi/sun8i-adda-pr-regmap.c
35
writel(readl(base) | ADDA_PR_RESET, base);
sound/soc/sunxi/sun8i-adda-pr-regmap.c
38
writel(readl(base) & ~ADDA_PR_WRITE, base);
sound/soc/sunxi/sun8i-adda-pr-regmap.c
44
writel(tmp, base);
sound/soc/sunxi/sun8i-adda-pr-regmap.c
58
writel(readl(base) | ADDA_PR_RESET, base);
sound/soc/sunxi/sun8i-adda-pr-regmap.c
64
writel(tmp, base);
sound/soc/sunxi/sun8i-adda-pr-regmap.c
70
writel(tmp, base);
sound/soc/sunxi/sun8i-adda-pr-regmap.c
73
writel(readl(base) | ADDA_PR_WRITE, base);
sound/soc/sunxi/sun8i-adda-pr-regmap.c
76
writel(readl(base) & ~ADDA_PR_WRITE, base);
sound/soc/ux500/ux500_msp_i2s.c
138
writel(temp_reg, msp->registers + MSP_TCF);
sound/soc/ux500/ux500_msp_i2s.c
166
writel(temp_reg, msp->registers + MSP_RCF);
sound/soc/ux500/ux500_msp_i2s.c
205
writel(temp_reg, msp->registers + MSP_GCR);
sound/soc/ux500/ux500_msp_i2s.c
208
writel(temp_reg, msp->registers + MSP_GCR);
sound/soc/ux500/ux500_msp_i2s.c
223
writel(reg_val_GCR & ~SRG_ENABLE, msp->registers + MSP_GCR);
sound/soc/ux500/ux500_msp_i2s.c
255
writel(temp_reg, msp->registers + MSP_SRG);
sound/soc/ux500/ux500_msp_i2s.c
262
writel(reg_val_GCR | SRG_ENABLE, msp->registers + MSP_GCR);
sound/soc/ux500/ux500_msp_i2s.c
292
writel(reg_val_MCR | (mcfg->tx_multichannel_enable ?
sound/soc/ux500/ux500_msp_i2s.c
295
writel(mcfg->tx_channel_0_enable,
sound/soc/ux500/ux500_msp_i2s.c
297
writel(mcfg->tx_channel_1_enable,
sound/soc/ux500/ux500_msp_i2s.c
299
writel(mcfg->tx_channel_2_enable,
sound/soc/ux500/ux500_msp_i2s.c
301
writel(mcfg->tx_channel_3_enable,
sound/soc/ux500/ux500_msp_i2s.c
313
writel(reg_val_MCR | (mcfg->rx_multichannel_enable ?
sound/soc/ux500/ux500_msp_i2s.c
316
writel(mcfg->rx_channel_0_enable,
sound/soc/ux500/ux500_msp_i2s.c
318
writel(mcfg->rx_channel_1_enable,
sound/soc/ux500/ux500_msp_i2s.c
320
writel(mcfg->rx_channel_2_enable,
sound/soc/ux500/ux500_msp_i2s.c
322
writel(mcfg->rx_channel_3_enable,
sound/soc/ux500/ux500_msp_i2s.c
332
writel(reg_val_MCR |
sound/soc/ux500/ux500_msp_i2s.c
336
writel(mcfg->comparison_mask,
sound/soc/ux500/ux500_msp_i2s.c
338
writel(mcfg->comparison_value,
sound/soc/ux500/ux500_msp_i2s.c
368
writel(reg_val_DMACR, msp->registers + MSP_DMACR);
sound/soc/ux500/ux500_msp_i2s.c
370
writel(config->iodelay, msp->registers + MSP_IODLY);
sound/soc/ux500/ux500_msp_i2s.c
374
writel(reg_val_GCR | FRAME_GEN_ENABLE, msp->registers + MSP_GCR);
sound/soc/ux500/ux500_msp_i2s.c
385
writel(reg_val_GCR | RX_ENABLE, msp->registers + MSP_GCR);
sound/soc/ux500/ux500_msp_i2s.c
393
writel(reg_val_GCR, msp->registers + MSP_GCR);
sound/soc/ux500/ux500_msp_i2s.c
402
writel(reg_val_GCR | TX_ENABLE, msp->registers + MSP_GCR);
sound/soc/ux500/ux500_msp_i2s.c
403
writel(MSP_ITCR_ITEN | MSP_ITCR_TESTFIFO, msp->registers + MSP_ITCR);
sound/soc/ux500/ux500_msp_i2s.c
410
writel(0x0, msp->registers + MSP_ITCR);
sound/soc/ux500/ux500_msp_i2s.c
411
writel(reg_val_GCR, msp->registers + MSP_GCR);
sound/soc/ux500/ux500_msp_i2s.c
465
writel(new_reg, msp->registers + MSP_GCR);
sound/soc/ux500/ux500_msp_i2s.c
489
writel(reg_val_GCR & ~RX_ENABLE, msp->registers + MSP_GCR);
sound/soc/ux500/ux500_msp_i2s.c
491
writel(reg_val_DMACR & ~RX_DMA_ENABLE, msp->registers + MSP_DMACR);
sound/soc/ux500/ux500_msp_i2s.c
493
writel(reg_val_IMSC &
sound/soc/ux500/ux500_msp_i2s.c
505
writel(reg_val_GCR & ~TX_ENABLE, msp->registers + MSP_GCR);
sound/soc/ux500/ux500_msp_i2s.c
507
writel(reg_val_DMACR & ~TX_DMA_ENABLE, msp->registers + MSP_DMACR);
sound/soc/ux500/ux500_msp_i2s.c
509
writel(reg_val_IMSC &
sound/soc/ux500/ux500_msp_i2s.c
526
writel(reg_val_GCR | LOOPBACK_MASK,
sound/soc/ux500/ux500_msp_i2s.c
533
writel((readl(msp->registers + MSP_GCR) &
sound/soc/ux500/ux500_msp_i2s.c
540
writel((readl(msp->registers + MSP_GCR) &
sound/soc/ux500/ux500_msp_i2s.c
573
writel(reg_val_GCR | enable_bit, msp->registers + MSP_GCR);
sound/soc/ux500/ux500_msp_i2s.c
601
writel((readl(msp->registers + MSP_GCR) &
sound/soc/ux500/ux500_msp_i2s.c
605
writel(0, msp->registers + MSP_GCR);
sound/soc/ux500/ux500_msp_i2s.c
606
writel(0, msp->registers + MSP_TCF);
sound/soc/ux500/ux500_msp_i2s.c
607
writel(0, msp->registers + MSP_RCF);
sound/soc/ux500/ux500_msp_i2s.c
608
writel(0, msp->registers + MSP_DMACR);
sound/soc/ux500/ux500_msp_i2s.c
609
writel(0, msp->registers + MSP_SRG);
sound/soc/ux500/ux500_msp_i2s.c
610
writel(0, msp->registers + MSP_MCR);
sound/soc/ux500/ux500_msp_i2s.c
611
writel(0, msp->registers + MSP_RCM);
sound/soc/ux500/ux500_msp_i2s.c
612
writel(0, msp->registers + MSP_RCV);
sound/soc/ux500/ux500_msp_i2s.c
613
writel(0, msp->registers + MSP_TCE0);
sound/soc/ux500/ux500_msp_i2s.c
614
writel(0, msp->registers + MSP_TCE1);
sound/soc/ux500/ux500_msp_i2s.c
615
writel(0, msp->registers + MSP_TCE2);
sound/soc/ux500/ux500_msp_i2s.c
616
writel(0, msp->registers + MSP_TCE3);
sound/soc/ux500/ux500_msp_i2s.c
617
writel(0, msp->registers + MSP_RCE0);
sound/soc/ux500/ux500_msp_i2s.c
618
writel(0, msp->registers + MSP_RCE1);
sound/soc/ux500/ux500_msp_i2s.c
619
writel(0, msp->registers + MSP_RCE2);
sound/soc/ux500/ux500_msp_i2s.c
620
writel(0, msp->registers + MSP_RCE3);
sound/soc/xilinx/xlnx_formatter_pcm.c
253
writel(val, mmio_base + XLNX_AUD_CTRL);
sound/soc/xilinx/xlnx_formatter_pcm.c
277
writel(val, mmio_base + XLNX_AUD_CTRL);
sound/soc/xilinx/xlnx_formatter_pcm.c
290
writel(val & AUD_STS_IOC_IRQ_MASK, reg);
sound/soc/xilinx/xlnx_formatter_pcm.c
309
writel(val & AUD_STS_IOC_IRQ_MASK, reg);
sound/soc/xilinx/xlnx_formatter_pcm.c
414
writel(val, stream_data->mmio + XLNX_AUD_CTRL);
sound/soc/xilinx/xlnx_formatter_pcm.c
479
writel(mclk_fs, stream_data->mmio + XLNX_AUD_FS_MULTIPLIER);
sound/soc/xilinx/xlnx_formatter_pcm.c
502
writel(low, stream_data->mmio + XLNX_AUD_BUFF_ADDR_LSB);
sound/soc/xilinx/xlnx_formatter_pcm.c
503
writel(high, stream_data->mmio + XLNX_AUD_BUFF_ADDR_MSB);
sound/soc/xilinx/xlnx_formatter_pcm.c
528
writel(val, stream_data->mmio + XLNX_AUD_CTRL);
sound/soc/xilinx/xlnx_formatter_pcm.c
532
writel(val, stream_data->mmio + XLNX_AUD_PERIOD_CONFIG);
sound/soc/xilinx/xlnx_formatter_pcm.c
534
writel(bytes_per_ch, stream_data->mmio + XLNX_BYTES_PER_CH);
sound/soc/xilinx/xlnx_formatter_pcm.c
553
writel(val, stream_data->mmio + XLNX_AUD_CTRL);
sound/soc/xilinx/xlnx_formatter_pcm.c
560
writel(val, stream_data->mmio + XLNX_AUD_CTRL);
sound/soc/xilinx/xlnx_i2s.c
114
writel(sclk_div, drv_data->base + I2S_I2STIM_OFFSET);
sound/soc/xilinx/xlnx_i2s.c
121
writel(chan_id, drv_data->base + reg_off);
sound/soc/xilinx/xlnx_i2s.c
137
writel(I2S_CORE_CTRL_ENABLE, drv_data->base + I2S_CORE_CTRL_OFFSET);
sound/soc/xilinx/xlnx_i2s.c
142
writel(0, drv_data->base + I2S_CORE_CTRL_OFFSET);
sound/soc/xilinx/xlnx_i2s.c
48
writel(div, drv_data->base + I2S_I2STIM_OFFSET);
sound/soc/xilinx/xlnx_spdif.c
102
writel(XSPDIF_SOFT_RESET_VALUE, ctx->base + XSPDIF_SOFT_RESET_REG);
sound/soc/xilinx/xlnx_spdif.c
144
writel(val, ctx->base + XSPDIF_CONTROL_REG);
sound/soc/xilinx/xlnx_spdif.c
181
writel(val, ctx->base + XSPDIF_CONTROL_REG);
sound/soc/xilinx/xlnx_spdif.c
189
writel(val, ctx->base + XSPDIF_CONTROL_REG);
sound/soc/xilinx/xlnx_spdif.c
301
writel(XSPDIF_SOFT_RESET_VALUE, ctx->base + XSPDIF_SOFT_RESET_REG);
sound/soc/xilinx/xlnx_spdif.c
62
writel(val & XSPDIF_CH_STS_MASK,
sound/soc/xilinx/xlnx_spdif.c
66
writel(val & ~XSPDIF_CH_STS_MASK,
sound/soc/xilinx/xlnx_spdif.c
85
writel(val, ctx->base + XSPDIF_CONTROL_REG);
sound/soc/xilinx/xlnx_spdif.c
88
writel(XSPDIF_CH_STS_MASK,
sound/soc/xilinx/xlnx_spdif.c
90
writel(XSPDIF_GLOBAL_IRQ_ENABLE,
tools/arch/x86/include/asm/io.h
29
build_mmio_write(writel, "l", unsigned int, "r", :"memory")
tools/arch/x86/include/asm/io.h
47
#define writel writel
tools/include/asm-generic/io.h
233
#ifndef writel
tools/include/asm-generic/io.h
234
#define writel writel
tools/testing/selftests/kvm/lib/arm64/gic_v3.c
143
writel(reg_val, base + offset);
tools/testing/selftests/kvm/lib/arm64/gic_v3.c
287
writel(val, redist_base + GICR_WAKER);
tools/testing/selftests/kvm/lib/arm64/gic_v3.c
332
writel(~0, sgi_base + GICR_IGROUPR0);
tools/testing/selftests/kvm/lib/arm64/gic_v3.c
333
writel(~0, sgi_base + GICR_ICACTIVER0);
tools/testing/selftests/kvm/lib/arm64/gic_v3.c
334
writel(~0, sgi_base + GICR_ICENABLER0);
tools/testing/selftests/kvm/lib/arm64/gic_v3.c
338
writel(GICD_INT_DEF_PRI_X4,
tools/testing/selftests/kvm/lib/arm64/gic_v3.c
361
writel(0, GICD_BASE_GVA + GICD_CTLR);
tools/testing/selftests/kvm/lib/arm64/gic_v3.c
369
writel(~0, GICD_BASE_GVA + GICD_IGROUPR + i / 8);
tools/testing/selftests/kvm/lib/arm64/gic_v3.c
370
writel(~0, GICD_BASE_GVA + GICD_ICACTIVER + i / 8);
tools/testing/selftests/kvm/lib/arm64/gic_v3.c
371
writel(~0, GICD_BASE_GVA + GICD_ICENABLER + i / 8);
tools/testing/selftests/kvm/lib/arm64/gic_v3.c
376
writel(GICD_INT_DEF_PRI_X4,
tools/testing/selftests/kvm/lib/arm64/gic_v3.c
383
writel(GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A |
tools/testing/selftests/vfio/lib/drivers/dsa/dsa.c
123
writel(cmd_reg.bits, bar0 + IDXD_CMD_OFFSET);
tools/testing/selftests/vfio/lib/drivers/dsa/dsa.c
167
writel(wqcfg.bits[i], dsa->wqcfg_table + offsetof(union wqcfg, bits[i]));
tools/testing/selftests/vfio/lib/drivers/ioat/ioat.c
77
writel(errors, registers + IOAT_CHANERR_OFFSET);
