// SPDX-License-Identifier: MIT
//
// Copyright 2026 Advanced Micro Devices, Inc.

#include "reg_helper.h"

#include "core_types.h"
#include "link_encoder.h"
#include "dcn35/dcn35_dio_link_encoder.h"
#include "dcn42_dio_link_encoder.h"

#ifndef MIN
#define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
#endif

#define CTX \
        enc10->base.ctx
#define DC_LOGGER \
        enc10->base.ctx->logger

#define REG(reg)\
        (enc10->link_regs->reg)

#undef FN
#define FN(reg_name, field_name) \
        enc10->link_shift->field_name, enc10->link_mask->field_name

#define HPD_REG(reg)\
        (enc10->hpd_regs->reg)

#define HPD_REG_GET(reg_name, field, val)       \
                generic_reg_get(CTX, HPD_REG(reg_name), \
                                FN(reg_name, field), val)

#define HPD_REG_SET_N(reg_name, n, initial_val, ...)    \
                generic_reg_set_ex(CTX, \
                                HPD_REG(reg_name), \
                                initial_val, \
                                n, __VA_ARGS__)

#define HPD_REG_SET_2(reg, init_value, f1, v1, f2, v2)  \
                HPD_REG_SET_N(reg, 2, init_value, \
                                FN(reg, f1), v1,\
                                FN(reg, f2), v2)

bool dcn42_get_hpd_state(struct link_encoder *enc)
{
        struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
        uint32_t state;

        HPD_REG_GET(DC_HPD_INT_STATUS, DC_HPD_SENSE, &state);

        return state;
}

bool dcn42_program_hpd_filter(struct link_encoder *enc, int delay_on_connect_in_ms,     int delay_on_disconnect_in_ms)
{
        struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);

        HPD_REG_SET_2(DC_HPD_TOGGLE_FILT_CNTL, 0,
                        DC_HPD_CONNECT_INT_DELAY, delay_on_connect_in_ms,
                        DC_HPD_DISCONNECT_INT_DELAY, delay_on_disconnect_in_ms);

        return true;
}

static const struct link_encoder_funcs dcn42_link_enc_funcs = {
        .read_state = link_enc2_read_state,
        .validate_output_with_stream =
                        dcn30_link_encoder_validate_output_with_stream,
        .hw_init = dcn35_link_encoder_init,
        .setup = dcn35_link_encoder_setup,
        .enable_tmds_output = dcn10_link_encoder_enable_tmds_output,
        .enable_dp_output = dcn35_link_encoder_enable_dp_output,
        .enable_dp_mst_output = dcn35_link_encoder_enable_dp_mst_output,
        .disable_output = dcn35_link_encoder_disable_output,
        .dp_set_lane_settings = dcn10_link_encoder_dp_set_lane_settings,
        .dp_set_phy_pattern = dcn10_link_encoder_dp_set_phy_pattern,
        .update_mst_stream_allocation_table =
                dcn10_link_encoder_update_mst_stream_allocation_table,
        .psr_program_dp_dphy_fast_training =
                        dcn10_psr_program_dp_dphy_fast_training,
        .psr_program_secondary_packet = dcn10_psr_program_secondary_packet,
        .connect_dig_be_to_fe = dcn10_link_encoder_connect_dig_be_to_fe,
        .enable_hpd = dcn10_link_encoder_enable_hpd,
        .disable_hpd = dcn10_link_encoder_disable_hpd,
        .is_dig_enabled = dcn35_is_dig_enabled,
        .destroy = dcn10_link_encoder_destroy,
        .fec_set_enable = enc2_fec_set_enable,
        .fec_set_ready = enc2_fec_set_ready,
        .fec_is_active = enc2_fec_is_active,
        .get_dig_frontend = dcn10_get_dig_frontend,
        .get_dig_mode = dcn401_get_dig_mode,
        .is_in_alt_mode = dcn32_link_encoder_is_in_alt_mode,
        .get_max_link_cap = dcn32_link_encoder_get_max_link_cap,
        .dpcstx_set_order_invert_18_bit = NULL,
        .set_phy_source = NULL,
        .dpcs_initialize_phy = NULL,
        .dpcs_configure_phypll = NULL,
        .dpcs_configure_dpcs = NULL,
        .dpcs_enable_dpcs = NULL,
        .prog_eq_setting = dpcs401_program_eq_setting,
        .get_txffe = dpcs401_get_txffe,
        .set_txffe = dpcs401_set_txffe,
        .set_dio_phy_mux = dcn31_link_encoder_set_dio_phy_mux,
        .enable_dpia_output = dcn35_link_encoder_enable_dpia_output,
        .disable_dpia_output = dcn35_link_encoder_disable_dpia_output,
        .get_hpd_state = dcn42_get_hpd_state,
        .program_hpd_filter = dcn42_program_hpd_filter,
};

void dcn42_link_encoder_construct(
        struct dcn20_link_encoder *enc20,
        const struct encoder_init_data *init_data,
        const struct encoder_feature_support *enc_features,
        const struct dcn10_link_enc_registers *link_regs,
        const struct dcn10_link_enc_aux_registers *aux_regs,
        const struct dcn10_link_enc_hpd_registers *hpd_regs,
        const struct dcn10_link_enc_shift *link_shift,
        const struct dcn10_link_enc_mask *link_mask)
{
        struct bp_connector_speed_cap_info bp_cap_info = {0};
        const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs;
        enum bp_result result = BP_RESULT_OK;
        struct dcn10_link_encoder *enc10 = &enc20->enc10;

        enc10->base.funcs = &dcn42_link_enc_funcs;
        enc10->base.ctx = init_data->ctx;
        enc10->base.id = init_data->encoder;

        enc10->base.hpd_source = init_data->hpd_source;
        enc10->base.connector = init_data->connector;


        enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;

        enc10->base.features = *enc_features;
        if (enc10->base.connector.id == CONNECTOR_ID_USBC)
                enc10->base.features.flags.bits.DP_IS_USB_C = 1;

        enc10->base.transmitter = init_data->transmitter;

        /* set the flag to indicate whether driver poll the I2C data pin
         * while doing the DP sink detect
         */

/*      if (dal_adapter_service_is_feature_supported(as,
                FEATURE_DP_SINK_DETECT_POLL_DATA_PIN))
                enc10->base.features.flags.bits.
                        DP_SINK_DETECT_POLL_DATA_PIN = true;*/

        enc10->base.output_signals =
                SIGNAL_TYPE_DVI_SINGLE_LINK |
                SIGNAL_TYPE_DVI_DUAL_LINK |
                SIGNAL_TYPE_LVDS |
                SIGNAL_TYPE_DISPLAY_PORT |
                SIGNAL_TYPE_DISPLAY_PORT_MST |
                SIGNAL_TYPE_EDP |
                SIGNAL_TYPE_HDMI_TYPE_A;

        enc10->link_regs = link_regs;
        enc10->aux_regs = aux_regs;
        enc10->hpd_regs = hpd_regs;
        enc10->link_shift = link_shift;
        enc10->link_mask = link_mask;

        switch (enc10->base.transmitter) {
        case TRANSMITTER_UNIPHY_A:
                enc10->base.preferred_engine = ENGINE_ID_DIGA;
        break;
        case TRANSMITTER_UNIPHY_B:
                enc10->base.preferred_engine = ENGINE_ID_DIGB;
        break;
        case TRANSMITTER_UNIPHY_C:
                enc10->base.preferred_engine = ENGINE_ID_DIGC;
        break;
        case TRANSMITTER_UNIPHY_D:
                enc10->base.preferred_engine = ENGINE_ID_DIGD;
        break;
        case TRANSMITTER_UNIPHY_E:
                enc10->base.preferred_engine = ENGINE_ID_DIGE;
        break;
        default:
                ASSERT_CRITICAL(false);
                enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
        }

        /* default to one to mirror Windows behavior */
        enc10->base.features.flags.bits.HDMI_6GB_EN = 1;

        if (bp_funcs->get_connector_speed_cap_info)
                result = bp_funcs->get_connector_speed_cap_info(enc10->base.ctx->dc_bios,
                                                enc10->base.connector, &bp_cap_info);

        /* Override features with DCE-specific values */
        if (result == BP_RESULT_OK) {
                enc10->base.features.flags.bits.IS_HBR2_CAPABLE =
                                bp_cap_info.DP_HBR2_EN;
                enc10->base.features.flags.bits.IS_HBR3_CAPABLE =
                                bp_cap_info.DP_HBR3_EN;
                enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;
                enc10->base.features.flags.bits.IS_DP2_CAPABLE = 1;
                enc10->base.features.flags.bits.IS_UHBR10_CAPABLE = bp_cap_info.DP_UHBR10_EN;
                enc10->base.features.flags.bits.IS_UHBR13_5_CAPABLE = bp_cap_info.DP_UHBR13_5_EN;
                enc10->base.features.flags.bits.IS_UHBR20_CAPABLE = bp_cap_info.DP_UHBR20_EN;
                enc10->base.features.flags.bits.IS_HDMI_FRL_CAPABLE =
                                bp_cap_info.FRL_8G_EN || bp_cap_info.FRL_10G_EN || bp_cap_info.FRL_12G_EN;
                enc10->base.features.flags.bits.IS_FRL_8G_CAPABLE = bp_cap_info.FRL_8G_EN;
                enc10->base.features.flags.bits.IS_FRL_10G_CAPABLE = bp_cap_info.FRL_10G_EN;
                enc10->base.features.flags.bits.IS_FRL_12G_CAPABLE = bp_cap_info.FRL_12G_EN;
                enc10->base.txffe_state = 0;
        } else {
                DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n",
                                __func__,
                                result);
        }
        if (enc10->base.ctx->dc->debug.hdmi20_disable) {
                enc10->base.features.flags.bits.HDMI_6GB_EN = 0;
        }
        if (enc10->base.ctx->dc->config.force_hdmi21_frl_enc_enable) {
                enc10->base.features.flags.bits.IS_HDMI_FRL_CAPABLE = 1;
                enc10->base.features.flags.bits.IS_FRL_8G_CAPABLE = 1;
                enc10->base.features.flags.bits.IS_FRL_10G_CAPABLE = 1;
                enc10->base.features.flags.bits.IS_FRL_12G_CAPABLE = 1;
        }
}