common/lib/libx86emu/x86emu.c

1076

common_inc_word_long(struct X86EMU *emu, union X86EMU_register *reg)

common/lib/libx86emu/x86emu.c

1079

reg->I32_reg.e_reg = inc_long(emu, reg->I32_reg.e_reg);

common/lib/libx86emu/x86emu.c

1081

reg->I16_reg.x_reg = inc_word(emu, reg->I16_reg.x_reg);

common/lib/libx86emu/x86emu.c

1085

common_dec_word_long(struct X86EMU *emu, union X86EMU_register *reg)

common/lib/libx86emu/x86emu.c

1088

reg->I32_reg.e_reg = dec_long(emu, reg->I32_reg.e_reg);

common/lib/libx86emu/x86emu.c

1090

reg->I16_reg.x_reg = dec_word(emu, reg->I16_reg.x_reg);

common/lib/libx86emu/x86emu.c

1311

common_push_word_long(struct X86EMU *emu, union X86EMU_register *reg)

common/lib/libx86emu/x86emu.c

1314

push_long(emu, reg->I32_reg.e_reg);

common/lib/libx86emu/x86emu.c

1316

push_word(emu, reg->I16_reg.x_reg);

common/lib/libx86emu/x86emu.c

1320

common_pop_word_long(struct X86EMU *emu, union X86EMU_register *reg)

common/lib/libx86emu/x86emu.c

1323

reg->I32_reg.e_reg = pop_long(emu);

common/lib/libx86emu/x86emu.c

1325

reg->I16_reg.x_reg = pop_word(emu);

common/lib/libx86emu/x86emu.c

623

decode_rm_byte_register(struct X86EMU *emu, int reg)

common/lib/libx86emu/x86emu.c

625

switch (reg) {

common/lib/libx86emu/x86emu.c

670

decode_rm_word_register(struct X86EMU *emu, int reg)

common/lib/libx86emu/x86emu.c

672

switch (reg) {

common/lib/libx86emu/x86emu.c

717

decode_rm_long_register(struct X86EMU *emu, int reg)

common/lib/libx86emu/x86emu.c

719

switch (reg) {

games/mille/end.c

144

reg PLAY *pp;

games/mille/end.c

145

reg int i;

games/mille/end.c

99

reg int x, num, tot, count;

include/vis_proto.h

449

vis_u64 reg = *((vis_u64 *)&var);

include/vis_proto.h

450

vis_u32 hi = (reg >> 32) & 0xffffffff;

include/vis_proto.h

459

vis_u64 reg = *((vis_u64 *)&var);

include/vis_proto.h

460

vis_u32 lo = reg & 0xffffffff;

lib/libarch/alpha/alpha_pci_conf.c

43

alpha_pci_conf_read(u_int bus, u_int device, u_int func, u_int reg)

lib/libarch/alpha/alpha_pci_conf.c

51

args.reg = reg;

lib/libarch/alpha/alpha_pci_conf.c

60

alpha_pci_conf_write(u_int bus, u_int device, u_int func, u_int reg,

lib/libarch/alpha/alpha_pci_conf.c

69

args.reg = reg;

lib/libcompat/regexp/regexp.c

179

STATIC char *reg __P((int, int *));

lib/libcompat/regexp/regexp.c

231

if (reg(0, &flags) == NULL)

lib/libcompat/regexp/regexp.c

249

if (reg(0, &flags) == NULL) {

lib/libcompat/regexp/regexp.c

535

ret = reg(1, &flags);

lib/libcurses/PSD.doc/life.c

148

reg LIST *hp;

lib/libcurses/PSD.doc/life.c

91

reg char c;

lib/libcurses/PSD.doc/life.c

92

reg int x, y;

lib/libexecinfo/unwind_arm_ehabi_stub.c

61

_Unwind_SetGR(struct _Unwind_Context *context, int reg, _Unwind_Ptr val)

lib/libexecinfo/unwind_arm_ehabi_stub.c

63

_Unwind_VRS_Set(context, 0 /*_UVRSC_CORE*/, reg, 0 /*_UVRSD_UINT32*/,

lib/libnvmm/libnvmm_x86.c

1002

const struct x86_reg *reg;

lib/libnvmm/libnvmm_x86.c

1876

instr->src.u.reg = &gpr_map__special[1][2][adrsize-1];

lib/libnvmm/libnvmm_x86.c

1881

instr->dst.u.reg = &gpr_map__special[1][3][adrsize-1];

lib/libnvmm/libnvmm_x86.c

1905

instr->src.u.reg = &gpr_map__special[1][2][adrsize-1];

lib/libnvmm/libnvmm_x86.c

1910

instr->dst.u.reg = &gpr_map__special[1][3][adrsize-1];

lib/libnvmm/libnvmm_x86.c

1942

streg->u.reg = &gpr_map[0][0][regsize-1]; /* ?AX */

lib/libnvmm/libnvmm_x86.c

1947

stlo->u.reg = &gpr_map__special[1][3][adrsize-1];

lib/libnvmm/libnvmm_x86.c

1951

stlo->u.reg = &gpr_map__special[1][2][adrsize-1];

lib/libnvmm/libnvmm_x86.c

1979

streg->u.reg = &gpr_map[0][0][regsize-1]; /* ?AX */

lib/libnvmm/libnvmm_x86.c

2120

const struct x86_reg *reg;

lib/libnvmm/libnvmm_x86.c

2124

reg = &gpr_map[instr->rexpref.x][enc][regsize-1];

lib/libnvmm/libnvmm_x86.c

2126

if (reg->num == -1) {

lib/libnvmm/libnvmm_x86.c

2127

reg = resolve_special_register(instr, enc, regsize);

lib/libnvmm/libnvmm_x86.c

2130

return reg;

lib/libnvmm/libnvmm_x86.c

2137

const struct x86_reg *reg;

lib/libnvmm/libnvmm_x86.c

2141

reg = &gpr_map[instr->rexpref.b][enc][regsize-1];

lib/libnvmm/libnvmm_x86.c

2142

if (reg->num == -1) {

lib/libnvmm/libnvmm_x86.c

2143

reg = resolve_special_register(instr, enc, regsize);

lib/libnvmm/libnvmm_x86.c

2146

return reg;

lib/libnvmm/libnvmm_x86.c

2205

uint8_t enc = instr->regmodrm.reg;

lib/libnvmm/libnvmm_x86.c

2206

const struct x86_reg *reg;

lib/libnvmm/libnvmm_x86.c

2211

reg = &gpr_map[instr->rexpref.r][enc][regsize-1];

lib/libnvmm/libnvmm_x86.c

2212

if (reg->num == -1) {

lib/libnvmm/libnvmm_x86.c

2213

reg = resolve_special_register(instr, enc, regsize);

lib/libnvmm/libnvmm_x86.c

2216

return reg;

lib/libnvmm/libnvmm_x86.c

2223

const struct x86_reg *reg;

lib/libnvmm/libnvmm_x86.c

2233

reg = &gpr_map[instr->rexpref.b][enc][regsize-1];

lib/libnvmm/libnvmm_x86.c

2234

if (reg->num == -1) {

lib/libnvmm/libnvmm_x86.c

2235

reg = resolve_special_register(instr, enc, regsize);

lib/libnvmm/libnvmm_x86.c

2238

return reg;

lib/libnvmm/libnvmm_x86.c

2307

const struct x86_reg *reg;

lib/libnvmm/libnvmm_x86.c

2317

instr->regmodrm.reg = ((byte & 0b00111000) >> 3);

lib/libnvmm/libnvmm_x86.c

2336

if (group1[instr->regmodrm.reg].emul == NULL) {

lib/libnvmm/libnvmm_x86.c

2339

instr->emul = group1[instr->regmodrm.reg].emul;

lib/libnvmm/libnvmm_x86.c

2341

if (group3[instr->regmodrm.reg].emul == NULL) {

lib/libnvmm/libnvmm_x86.c

2344

instr->emul = group3[instr->regmodrm.reg].emul;

lib/libnvmm/libnvmm_x86.c

2346

if (group11[instr->regmodrm.reg].emul == NULL) {

lib/libnvmm/libnvmm_x86.c

2349

instr->emul = group11[instr->regmodrm.reg].emul;

lib/libnvmm/libnvmm_x86.c

2353

reg = get_register_reg(instr, opcode);

lib/libnvmm/libnvmm_x86.c

2354

if (reg == NULL) {

lib/libnvmm/libnvmm_x86.c

2358

strg->u.reg = reg;

lib/libnvmm/libnvmm_x86.c

2373

strm->u.reg = &gpr_map__rip;

lib/libnvmm/libnvmm_x86.c

2382

strm->u.reg = NULL;

lib/libnvmm/libnvmm_x86.c

2391

strm->u.reg = NULL;

lib/libnvmm/libnvmm_x86.c

2403

reg = get_register_rm(instr, opcode);

lib/libnvmm/libnvmm_x86.c

2404

if (reg == NULL) {

lib/libnvmm/libnvmm_x86.c

2408

strm->u.reg = reg;

lib/libnvmm/libnvmm_x86.c

3045

uint64_t reg;

lib/libnvmm/libnvmm_x86.c

3053

reg = gpr_read_address(instr, state, sib->idx->num);

lib/libnvmm/libnvmm_x86.c

3054

gva += sib->scale * reg;

lib/libnvmm/libnvmm_x86.c

3057

if (store->u.reg == NULL) {

lib/libnvmm/libnvmm_x86.c

3061

gva = gpr_read_address(instr, state, store->u.reg->num);

lib/libnvmm/libnvmm_x86.c

3343

val = state->gprs[instr->src.u.reg->num];

lib/libnvmm/libnvmm_x86.c

3344

val = __SHIFTOUT(val, instr->src.u.reg->mask);

lib/libnvmm/libnvmm_x86.c

3364

val = state->gprs[instr->dst.u.reg->num];

lib/libnvmm/libnvmm_x86.c

3365

val = __SHIFTOUT(val, instr->dst.u.reg->mask);

lib/libnvmm/libnvmm_x86.c

3387

val = __SHIFTIN(val, instr->dst.u.reg->mask);

lib/libnvmm/libnvmm_x86.c

3388

state->gprs[instr->dst.u.reg->num] &= ~instr->dst.u.reg->mask;

lib/libnvmm/libnvmm_x86.c

3389

state->gprs[instr->dst.u.reg->num] |= val;

lib/libnvmm/libnvmm_x86.c

3390

state->gprs[instr->dst.u.reg->num] &= ~instr->zeroextend_mask;

lib/libnvmm/libnvmm_x86.c

3402

val = __SHIFTIN(val, instr->src.u.reg->mask);

lib/libnvmm/libnvmm_x86.c

3403

state->gprs[instr->src.u.reg->num] &= ~instr->src.u.reg->mask;

lib/libnvmm/libnvmm_x86.c

3404

state->gprs[instr->src.u.reg->num] |= val;

lib/libnvmm/libnvmm_x86.c

3405

state->gprs[instr->src.u.reg->num] &= ~instr->zeroextend_mask;

lib/libnvmm/libnvmm_x86.c

720

int reg = 0; /* GCC */

lib/libnvmm/libnvmm_x86.c

759

reg = NVMM_X64_GPR_RDI;

lib/libnvmm/libnvmm_x86.c

761

reg = NVMM_X64_GPR_RSI;

lib/libnvmm/libnvmm_x86.c

764

gva = state->gprs[reg];

lib/libnvmm/libnvmm_x86.c

829

state->gprs[reg] -= iocnt * io.size;

lib/libnvmm/libnvmm_x86.c

831

state->gprs[reg] += iocnt * io.size;

lib/libnvmm/libnvmm_x86.c

976

uint8_t reg:3;

lib/libpci/pci_bus.c

58

pcibus_conf_read(int fd, u_int bus, u_int device, u_int func, u_int reg,

lib/libpci/pci_bus.c

67

bdfr.cfgreg.reg = reg;

lib/libpci/pci_bus.c

85

pcibus_conf_write(int fd, u_int bus, u_int device, u_int func, u_int reg,

lib/libpci/pci_bus.c

93

bdfr.cfgreg.reg = reg;

lib/libpci/pci_device.c

58

pcidev_conf_read(int fd, u_int reg, uint32_t *valp)

lib/libpci/pci_device.c

63

r.reg = reg;

lib/libpci/pci_device.c

81

pcidev_conf_write(int fd, u_int reg, uint32_t val)

lib/libpci/pci_device.c

85

r.reg = reg;

sys/arch/aarch64/aarch64/aarch64_machdep.c

132

uint64_t reg;

sys/arch/aarch64/aarch64/aarch64_machdep.c

134

reg = reg_id_aa64pfr1_el1_read();

sys/arch/aarch64/aarch64/aarch64_machdep.c

136

if (reg >= ID_AA64PFR1_EL1_BT_SUPPORTED) {

sys/arch/aarch64/aarch64/core_machdep.c

69

md_core.reg = lwp_trapframe(l)->tf_regs;

sys/arch/aarch64/aarch64/core_machdep.c

70

md_core.reg.r_tpidr = (uint64_t)(uintptr_t)l->l_private;

sys/arch/aarch64/aarch64/cpu_machdep.c

182

CTASSERT(sizeof(struct reg) == sizeof(__gregset_t));

sys/arch/aarch64/aarch64/cpu_machdep.c

183

CTASSERT(offsetof(struct reg, r_pc) == _REG_PC * sizeof(__greg_t));

sys/arch/aarch64/aarch64/cpu_machdep.c

184

CTASSERT(offsetof(struct reg, r_sp) == _REG_SP * sizeof(__greg_t));

sys/arch/aarch64/aarch64/cpu_machdep.c

185

CTASSERT(offsetof(struct reg, r_spsr) == _REG_SPSR * sizeof(__greg_t));

sys/arch/aarch64/aarch64/cpu_machdep.c

186

CTASSERT(offsetof(struct reg, r_tpidr) == _REG_TPIDR * sizeof(__greg_t));

sys/arch/aarch64/aarch64/cpufunc.c

550

uint64_t reg, sctlr;

sys/arch/aarch64/aarch64/cpufunc.c

554

reg = reg_id_aa64mmfr1_el1_read();

sys/arch/aarch64/aarch64/cpufunc.c

555

if (__SHIFTOUT(reg, ID_AA64MMFR1_EL1_PAN) !=

sys/arch/aarch64/aarch64/cpufunc.c

585

uint64_t reg;

sys/arch/aarch64/aarch64/cpufunc.c

589

reg = reg_id_aa64isar1_el1_read();

sys/arch/aarch64/aarch64/cpufunc.c

590

if (__SHIFTOUT(reg, ID_AA64ISAR1_EL1_APA) !=

sys/arch/aarch64/aarch64/cpufunc.c

593

if (__SHIFTOUT(reg, ID_AA64ISAR1_EL1_API) !=

sys/arch/aarch64/aarch64/cpufunc.c

596

if (__SHIFTOUT(reg, ID_AA64ISAR1_EL1_GPA) !=

sys/arch/aarch64/aarch64/cpufunc.c

599

if (__SHIFTOUT(reg, ID_AA64ISAR1_EL1_GPI) !=

sys/arch/aarch64/aarch64/db_interface.c

263

db_fetch_reg(unsigned int reg, db_regs_t *regs, bool use_sp)

sys/arch/aarch64/aarch64/db_interface.c

265

if (reg >= 32)

sys/arch/aarch64/aarch64/db_interface.c

268

if (reg == 31) {

sys/arch/aarch64/aarch64/db_interface.c

272

return regs->tf_reg[reg];

sys/arch/aarch64/aarch64/process_machdep.c

47

process_read_regs(struct lwp *l, struct reg *regs)

sys/arch/aarch64/aarch64/process_machdep.c

55

process_write_regs(struct lwp *l, const struct reg *regs)

sys/arch/aarch64/aarch64/procfs_machdep.c

79

#define SO_EQ(reg, mask, val) (__SHIFTOUT((reg), (mask)) == (val))

sys/arch/aarch64/aarch64/trap.c

976

const struct reg *r = &tf->tf_regs;

sys/arch/aarch64/include/asm.h

15

.macro adrl reg, addr

sys/arch/aarch64/include/frame.h

40

struct reg tf_regs __aligned(16);

sys/arch/aarch64/include/pcb.h

45

struct reg reg;

sys/arch/algor/dev/mcclock_mainbus.c

100

mcclock_mainbus_write(struct mc146818_softc *sc, u_int reg, u_int datum)

sys/arch/algor/dev/mcclock_mainbus.c

105

bus_space_write_1(iot, ioh, 0, reg);

sys/arch/algor/dev/mcclock_mainbus.c

110

mcclock_mainbus_read(struct mc146818_softc *sc, u_int reg)

sys/arch/algor/dev/mcclock_mainbus.c

115

bus_space_write_1(iot, ioh, 0, reg);

sys/arch/alpha/alpha/compat_13_machdep.c

92

regtoframe((struct reg *)ksc.sc_regs, l->l_md.md_tf);

sys/arch/alpha/alpha/compat_16_machdep.c

130

frametoreg(tf, (struct reg *)frame.sf_sc.sc_regs);

sys/arch/alpha/alpha/compat_16_machdep.c

280

regtoframe((struct reg *)ksc.sc_regs, l->l_md.md_tf);

sys/arch/alpha/alpha/db_interface.c

593

unsigned long reg;

sys/arch/alpha/alpha/db_interface.c

595

db_read_bytes((db_addr_t)regp, sizeof(reg), (char *)&reg);

sys/arch/alpha/alpha/db_interface.c

596

return reg;

sys/arch/alpha/alpha/db_trace.c

341

unsigned long reg;

sys/arch/alpha/alpha/db_trace.c

344

sizeof(reg), (char *)&reg);

sys/arch/alpha/alpha/db_trace.c

345

callpc = reg;

sys/arch/alpha/alpha/machdep.c

1371

frametoreg(const struct trapframe *framep, struct reg *regp)

sys/arch/alpha/alpha/machdep.c

1409

regtoframe(const struct reg *regp, struct trapframe *framep)

sys/arch/alpha/alpha/machdep.c

1447

printregs(struct reg *regp)

sys/arch/alpha/alpha/machdep.c

1459

struct reg reg;

sys/arch/alpha/alpha/machdep.c

1461

frametoreg(framep, &reg);

sys/arch/alpha/alpha/machdep.c

1462

reg.r_regs[R_SP] = alpha_pal_rdusp();

sys/arch/alpha/alpha/machdep.c

1465

printregs(&reg);

sys/arch/alpha/alpha/machdep.c

1847

frametoreg(frame, (struct reg *)gr);

sys/arch/alpha/alpha/machdep.c

1905

regtoframe((const struct reg *)gr, l->l_md.md_tf);

sys/arch/alpha/alpha/machdep.c

213

void printregs(struct reg *);

sys/arch/alpha/alpha/process_machdep.c

74

process_read_regs(struct lwp *l, struct reg *regs)

sys/arch/alpha/alpha/process_machdep.c

85

process_write_regs(struct lwp *l, const struct reg *regs)

sys/arch/alpha/alpha/sys_machdep.c

210

if (args.reg > 0xff) /* XXX MAGIC NUMBER */

sys/arch/alpha/alpha/sys_machdep.c

217

pci_conf_write(alpha_pci_chipset, tag, args.reg,

sys/arch/alpha/alpha/sys_machdep.c

221

args.reg);

sys/arch/alpha/alpha/trap.c

628

#define irp(l, reg) \

sys/arch/alpha/alpha/trap.c

629

((reg_to_framereg[(reg)] == -1) ? NULL : \

sys/arch/alpha/alpha/trap.c

630

&(l)->l_md.md_tf->tf_regs[reg_to_framereg[(reg)]])

sys/arch/alpha/alpha/trap.c

632

#define frp(l, reg) \

sys/arch/alpha/alpha/trap.c

633

(&pcb->pcb_fp.fpr_regs[(reg)])

sys/arch/alpha/alpha/trap.c

639

if ((regptr = ptrf(l, reg)) != NULL) \

sys/arch/alpha/alpha/trap.c

643

if ((regptr = ptrf(l, reg)) != NULL) \

sys/arch/alpha/alpha/trap.c

792

unaligned_fixup(u_long va, u_long opcode, u_long reg, struct lwp *l)

sys/arch/alpha/gbus/mcclock_gbus.c

101

bus_space_write_1(sc->sc_bst, sc->sc_bsh, reg, (uint8_t)val);

sys/arch/alpha/gbus/mcclock_gbus.c

105

mcclock_gbus_read(struct mc146818_softc *sc, u_int reg)

sys/arch/alpha/gbus/mcclock_gbus.c

107

return bus_space_read_1(sc->sc_bst, sc->sc_bsh, reg);

sys/arch/alpha/gbus/mcclock_gbus.c

99

mcclock_gbus_write(struct mc146818_softc *sc, u_int reg, u_int val)

sys/arch/alpha/include/alpha.h

104

void frametoreg(const struct trapframe *, struct reg *);

sys/arch/alpha/include/alpha.h

114

void regtoframe(const struct reg *, struct trapframe *);

sys/arch/alpha/include/alpha.h

74

struct reg;

sys/arch/alpha/include/asm.h

487

#define MSG(msg,reg,label) \

sys/arch/alpha/include/asm.h

488

lda reg, label; \

sys/arch/alpha/include/asm.h

610

#define LDGP(reg) \

sys/arch/alpha/include/asm.h

611

ldgp gp, 0(reg)

sys/arch/alpha/include/cpu.h

252

struct reg;

sys/arch/alpha/include/sysarch.h

80

u_int reg;

sys/arch/alpha/include/z8530var.h

108

u_int zs_read_reg(struct zs_chanstate *cs, u_int reg);

sys/arch/alpha/include/z8530var.h

112

void zs_write_reg(struct zs_chanstate *cs, u_int reg, u_int val);

sys/arch/alpha/isa/mcclock_isa.c

117

mcclock_isa_write(struct mc146818_softc *sc, u_int reg, u_int datum)

sys/arch/alpha/isa/mcclock_isa.c

122

bus_space_write_1(iot, ioh, 0, reg);

sys/arch/alpha/isa/mcclock_isa.c

127

mcclock_isa_read(struct mc146818_softc *sc, u_int reg)

sys/arch/alpha/isa/mcclock_isa.c

132

bus_space_write_1(iot, ioh, 0, reg);

sys/arch/alpha/jensenio/mcclock_jensenio.c

134

mcclock_jensenio_write(struct mc146818_softc *sc, u_int reg, u_int datum)

sys/arch/alpha/jensenio/mcclock_jensenio.c

139

bus_space_write_1(iot, ioh, 0, reg);

sys/arch/alpha/jensenio/mcclock_jensenio.c

144

mcclock_jensenio_read(struct mc146818_softc *sc, u_int reg)

sys/arch/alpha/jensenio/mcclock_jensenio.c

149

bus_space_write_1(iot, ioh, 0, reg);

sys/arch/alpha/pci/apecs_pci.c

148

reg, data, datap);

sys/arch/alpha/pci/apecs_pci.c

97

printf("apecs_conf_read: tag 0x%lx, reg 0x%lx -> %x @ %p%s\n", tag, reg,

sys/arch/alpha/pci/cia_pci.c

147

printf("cia_conf_read: tag 0x%lx, reg 0x%lx -> %x @ %p%s\n", tag, reg,

sys/arch/alpha/pci/cia_pci.c

215

reg, data, datap);

sys/arch/alpha/pci/irongate.c

75

pcireg_t reg;

sys/arch/alpha/pci/irongate.c

87

reg = irongate_conf_read0(icp, tag, PCI_CLASS_REG);

sys/arch/alpha/pci/irongate.c

88

icp->ic_rev = PCI_REVISION(reg);

sys/arch/alpha/pci/lca_pci.c

117

printf("lca_conf_read: tag 0x%lx, reg 0x%lx -> %x @ %p%s\n", tag, reg,

sys/arch/alpha/pci/lca_pci.c

165

reg, data, datap);

sys/arch/alpha/pci/mcpciareg.h

300

#define CAP_REV(reg) ((reg) & 0xf)

sys/arch/alpha/pci/mcpciareg.h

301

#define HORSE_REV(reg) (((reg) >> 4) & 0xf)

sys/arch/alpha/pci/mcpciareg.h

302

#define SADDLE_REV(reg) (((reg) >> 8) & 0xf)

sys/arch/alpha/pci/mcpciareg.h

303

#define SADDLE_TYPE(reg) (((reg) >> 12) & 0x3)

sys/arch/alpha/pci/mcpciareg.h

304

#define EISA_PRESENT(reg) ((reg) & (1 << 15))

sys/arch/alpha/pci/mcpciareg.h

305

#define IS_MCPCIA_MAGIC(reg) (((reg) & 0xffff0000) == 0x6000000)

sys/arch/alpha/pci/pci_machdep.c

552

pci_conf_read(pci_chipset_tag_t const pc, pcitag_t const tag, int const reg)

sys/arch/alpha/pci/pci_machdep.c

555

return pc->pc_conf_read(pc->pc_conf_v, tag, reg);

sys/arch/alpha/pci/pci_machdep.c

559

pci_conf_write(pci_chipset_tag_t const pc, pcitag_t const tag, int const reg,

sys/arch/alpha/pci/pci_machdep.c

563

pc->pc_conf_write(pc->pc_conf_v, tag, reg, val);

sys/arch/alpha/tc/mcclock_ioasic.c

100

mcclock_ioasic_write(struct mc146818_softc *sc, u_int reg, u_int datum)

sys/arch/alpha/tc/mcclock_ioasic.c

104

isc->sc_dp[reg].datum = datum;

sys/arch/alpha/tc/mcclock_ioasic.c

108

mcclock_ioasic_read(struct mc146818_softc *sc, u_int reg)

sys/arch/alpha/tc/mcclock_ioasic.c

112

return isc->sc_dp[reg].datum;

sys/arch/amd64/amd64/netbsd32_machdep.c

1140

cpu_mcontext32from64_validate(struct lwp *l, const struct reg *regp)

sys/arch/amd64/amd64/process_machdep.c

112

process_read_regs(struct lwp *l, struct reg *regp)

sys/arch/amd64/amd64/process_machdep.c

177

process_write_regs(struct lwp *l, const struct reg *regp)

sys/arch/amd64/include/frame.h

86

#define tf(reg, REG, idx) uint64_t tf_##reg;

sys/arch/amd64/include/frame_regs.h

67

#define _FRAME_NOREG(reg, REG, idx)

sys/arch/amd64/include/frameasm.h

370

#define CHECK_ASTPENDING(reg) cmpl $0, L_MD_ASTPENDING(reg)

sys/arch/amd64/include/frameasm.h

371

#define CLEAR_ASTPENDING(reg) movl $0, L_MD_ASTPENDING(reg)

sys/arch/amd64/include/mcontext.h

42

#define GREG_OFFSETS(reg, REG, idx) _REG_##REG = idx,

sys/arch/amd64/include/xen/hypercalls.h

204

int reg, unsigned long value)

sys/arch/amd64/include/xen/hypercalls.h

206

return _hypercall2(int, set_debugreg, reg, value);

sys/arch/amd64/include/xen/hypercalls.h

211

int reg)

sys/arch/amd64/include/xen/hypercalls.h

213

return _hypercall1(unsigned long, get_debugreg, reg);

sys/arch/amd64/include/xen/hypercalls.h

314

int reg, unsigned long value)

sys/arch/amd64/include/xen/hypercalls.h

316

return _hypercall2(int, set_segment_base, reg, value);

sys/arch/amiga/dev/acafh.c

237

acafh_reg_read(struct acafh_softc *sc, uint8_t reg)

sys/arch/amiga/dev/acafh.c

241

val = bus_space_read_2(sc->sc_aca_iot, sc->sc_aca_ioh, reg * 0x4000);

sys/arch/amiga/dev/acafh.c

244

reg, sc->sc_aca_ioh + reg, (bus_addr_t) kvtop((void*)

sys/arch/amiga/dev/acafh.c

245

((unsigned) sc->sc_aca_ioh + reg * 0x4000)), val);

sys/arch/amiga/dev/bzivsc.c

247

bzivsc_read_reg(struct ncr53c9x_softc *sc, int reg)

sys/arch/amiga/dev/bzivsc.c

251

return bsc->sc_reg[reg * 4];

sys/arch/amiga/dev/bzivsc.c

255

bzivsc_write_reg(struct ncr53c9x_softc *sc, int reg, uint8_t val)

sys/arch/amiga/dev/bzivsc.c

260

bsc->sc_reg[reg * 4] = v;

sys/arch/amiga/dev/bzivsc.c

263

reg == NCR_CMD/* && bsc->sc_active*/) {

sys/arch/amiga/dev/bzsc.c

255

bzsc_read_reg(struct ncr53c9x_softc *sc, int reg)

sys/arch/amiga/dev/bzsc.c

259

return bsc->sc_reg[reg * 2];

sys/arch/amiga/dev/bzsc.c

263

bzsc_write_reg(struct ncr53c9x_softc *sc, int reg, uint8_t val)

sys/arch/amiga/dev/bzsc.c

268

bsc->sc_reg[reg * 2] = v;

sys/arch/amiga/dev/bzsc.c

271

reg == NCR_CMD/* && bsc->sc_active*/) {

sys/arch/amiga/dev/bztzsc.c

251

bztzsc_read_reg(struct ncr53c9x_softc *sc, int reg)

sys/arch/amiga/dev/bztzsc.c

255

return bsc->sc_reg[reg * 4];

sys/arch/amiga/dev/bztzsc.c

259

bztzsc_write_reg(struct ncr53c9x_softc *sc, int reg, uint8_t val)

sys/arch/amiga/dev/bztzsc.c

264

bsc->sc_reg[reg * 4] = v;

sys/arch/amiga/dev/bztzsc.c

267

reg == NCR_CMD/* && bsc->sc_active*/) {

sys/arch/amiga/dev/cbiisc.c

243

cbiisc_read_reg(struct ncr53c9x_softc *sc, int reg)

sys/arch/amiga/dev/cbiisc.c

247

return csc->sc_reg[reg * 4];

sys/arch/amiga/dev/cbiisc.c

251

cbiisc_write_reg(struct ncr53c9x_softc *sc, int reg, uint8_t val)

sys/arch/amiga/dev/cbiisc.c

256

csc->sc_reg[reg * 4] = v;

sys/arch/amiga/dev/cbiisc.c

259

reg == NCR_CMD/* && csc->sc_active*/) {

sys/arch/amiga/dev/cbsc.c

247

cbsc_read_reg(struct ncr53c9x_softc *sc, int reg)

sys/arch/amiga/dev/cbsc.c

251

return csc->sc_reg[reg * 4];

sys/arch/amiga/dev/cbsc.c

255

cbsc_write_reg(struct ncr53c9x_softc *sc, int reg, uint8_t val)

sys/arch/amiga/dev/cbsc.c

260

csc->sc_reg[reg * 4] = v;

sys/arch/amiga/dev/cbsc.c

263

reg == NCR_CMD/* && csc->sc_active*/) {

sys/arch/amiga/dev/flsc.c

229

flsc_read_reg(struct ncr53c9x_softc *sc, int reg)

sys/arch/amiga/dev/flsc.c

233

return fsc->sc_reg[reg * 4];

sys/arch/amiga/dev/flsc.c

237

flsc_write_reg(struct ncr53c9x_softc *sc, int reg, uint8_t val)

sys/arch/amiga/dev/flsc.c

243

if (fsc->sc_piomode && reg == NCR_CMD &&

sys/arch/amiga/dev/flsc.c

254

if (reg == NCR_SELID) {

sys/arch/amiga/dev/flsc.c

275

if (reg == NCR_CMD && v == NCRCMD_SETATN &&

sys/arch/amiga/dev/flsc.c

282

fsc->sc_reg[reg * 4] = v;

sys/arch/amiga/dev/grf_clreg.h

71

#define vgar(ba, reg) (*(((volatile unsigned char *)ba)+reg))

sys/arch/amiga/dev/grf_clreg.h

74

#define vgaw(ba, reg, val) \

sys/arch/amiga/dev/grf_clreg.h

75

*(((volatile unsigned char *)ba)+reg) = ((val) & 0xff)

sys/arch/amiga/dev/grf_cv3dreg.h

101

#define vgaw16(ba, reg, val) \

sys/arch/amiga/dev/grf_cv3dreg.h

102

*((volatile unsigned short *) (((volatile char *)ba)+reg)) = val

sys/arch/amiga/dev/grf_cv3dreg.h

59

#define vgar(ba, reg) \

sys/arch/amiga/dev/grf_cv3dreg.h

60

*(((volatile char *)ba)+(reg ^ 3))

sys/arch/amiga/dev/grf_cv3dreg.h

63

#define vgaw(ba, reg, val) \

sys/arch/amiga/dev/grf_cv3dreg.h

64

*(((volatile char *)ba)+(reg ^ 3)) = ((val) & 0xff)

sys/arch/amiga/dev/grf_cv3dreg.h

69

#define vgario(ba, reg) \

sys/arch/amiga/dev/grf_cv3dreg.h

70

*(((volatile char *)ba) + ( ByteAccessIO(reg) ))

sys/arch/amiga/dev/grf_cv3dreg.h

72

#define vgawio(ba, reg, val) \

sys/arch/amiga/dev/grf_cv3dreg.h

80

( ByteAccessIO(reg) & 0xffff )) = ((val) & 0xff); \

sys/arch/amiga/dev/grf_cv3dreg.h

89

#define vgar32(ba, reg) \

sys/arch/amiga/dev/grf_cv3dreg.h

90

*((volatile unsigned long *) (((volatile char *)ba)+reg))

sys/arch/amiga/dev/grf_cv3dreg.h

93

#define vgaw32(ba, reg, val) \

sys/arch/amiga/dev/grf_cv3dreg.h

94

*((volatile unsigned long *) (((volatile char *)ba)+reg)) = val

sys/arch/amiga/dev/grf_cv3dreg.h

97

#define vgar16(ba, reg) \

sys/arch/amiga/dev/grf_cv3dreg.h

98

*((volatile unsigned short *) (((volatile char *)ba)+reg))

sys/arch/amiga/dev/grf_cvreg.h

62

#define vgar(ba, reg) \

sys/arch/amiga/dev/grf_cvreg.h

63

(*(((volatile char *)ba)+reg))

sys/arch/amiga/dev/grf_cvreg.h

66

#define vgaw(ba, reg, val) \

sys/arch/amiga/dev/grf_cvreg.h

67

*(((volatile char *)ba)+reg) = ((val) & 0xff); \

sys/arch/amiga/dev/grf_cvreg.h

71

#define vgar32(ba, reg) \

sys/arch/amiga/dev/grf_cvreg.h

72

( *((volatile unsigned long *) (((volatile char *)ba)+reg)) )

sys/arch/amiga/dev/grf_cvreg.h

75

#define vgaw32(ba, reg, val) \

sys/arch/amiga/dev/grf_cvreg.h

76

*((unsigned long *) (((volatile char *)ba)+reg)) = val; \

sys/arch/amiga/dev/grf_cvreg.h

80

#define vgar16(ba, reg) \

sys/arch/amiga/dev/grf_cvreg.h

81

( *((volatile unsigned short *) (((volatile char *)ba)+reg)) )

sys/arch/amiga/dev/grf_cvreg.h

84

#define vgaw16(ba, reg, val) \

sys/arch/amiga/dev/grf_cvreg.h

85

*((volatile unsigned short *) (((volatile char *)ba)+reg)) = val; \

sys/arch/amiga/dev/grf_etreg.h

83

#define vgar(ba, reg) (*(((volatile unsigned char *)ba)+reg))

sys/arch/amiga/dev/grf_etreg.h

86

#define vgaw(ba, reg, val) \

sys/arch/amiga/dev/grf_etreg.h

87

*(((volatile unsigned char *)ba)+reg) = ((unsigned char)val)

sys/arch/amiga/dev/grf_rhreg.h

423

#define vgar(ba, reg) (*(((volatile unsigned char *)ba)+reg))

sys/arch/amiga/dev/grf_rhreg.h

426

#define vgaw(ba, reg, val) \

sys/arch/amiga/dev/grf_rhreg.h

427

*(((volatile unsigned char *)ba)+reg) = val

sys/arch/amiga/dev/grf_rtreg.h

313

#define vgar(ba, reg) (*(((volatile unsigned char *)ba)+reg))

sys/arch/amiga/dev/grf_rtreg.h

316

#define vgaw(ba, reg, val) \

sys/arch/amiga/dev/grf_rtreg.h

317

*(((volatile unsigned char *)ba)+reg) = val

sys/arch/amiga/dev/mntva.c

337

mntva_reg_read(struct mntva_softc *sc, uint32_t reg)

sys/arch/amiga/dev/mntva.c

340

rv = bus_space_read_2(sc->sc_iot, sc->sc_regh, reg);

sys/arch/amiga/dev/mntva.c

345

mntva_reg_write(struct mntva_softc *sc, uint32_t reg, uint32_t val)

sys/arch/amiga/dev/mntva.c

347

bus_space_write_2(sc->sc_iot, sc->sc_regh, reg, val);

sys/arch/amiga/dev/mntva.c

67

static uint16_t mntva_reg_read(struct mntva_softc *sc, uint32_t reg);

sys/arch/amiga/dev/mntva.c

68

static void mntva_reg_write(struct mntva_softc *sc, uint32_t reg, uint32_t val);

sys/arch/amiga/dev/repulse.c

371

repac_read(void *arg, u_int8_t reg, u_int16_t *valuep)

sys/arch/amiga/dev/repulse.c

380

bp->rhw_reg_address = (reg & 0x7F) | 0x80;

sys/arch/amiga/dev/repulse.c

391

repac_write(void *arg, uint8_t reg, uint16_t value)

sys/arch/amiga/dev/repulse.c

399

bp->rhw_reg_address = reg & 0x7F;

sys/arch/amiga/dev/sbic.c

108

#define SCSI_PHASE(reg) (reg&0x07)

sys/arch/amiga/dev/toccata.c

400

unsigned reg;

sys/arch/amiga/dev/toccata.c

408

reg = ad_read(&sc->sc_ad, SP_INTERFACE_CONFIG);

sys/arch/amiga/dev/toccata.c

410

(reg & ~(CAPTURE_ENABLE|PLAYBACK_ENABLE)));

sys/arch/amiga/dev/toccata.c

469

unsigned reg;

sys/arch/amiga/dev/toccata.c

478

reg = ad_read(&sc->sc_ad, SP_INTERFACE_CONFIG);

sys/arch/amiga/dev/toccata.c

479

ad_write(&sc->sc_ad, SP_INTERFACE_CONFIG, (reg & ~CAPTURE_ENABLE));

sys/arch/amiga/dev/toccata.c

489

unsigned int reg;

sys/arch/amiga/dev/toccata.c

501

reg = ad_read(&sc->sc_ad, SP_INTERFACE_CONFIG);

sys/arch/amiga/dev/toccata.c

503

(reg | CAPTURE_ENABLE));

sys/arch/amiga/dev/toccata.c

519

unsigned int reg;

sys/arch/amiga/dev/toccata.c

527

reg = ad_read(&sc->sc_ad, SP_INTERFACE_CONFIG);

sys/arch/amiga/dev/toccata.c

528

ad_write(&sc->sc_ad, SP_INTERFACE_CONFIG, (reg & ~PLAYBACK_ENABLE));

sys/arch/amiga/dev/toccata.c

538

unsigned reg;

sys/arch/amiga/dev/toccata.c

568

reg = ad_read(&sc->sc_ad, SP_INTERFACE_CONFIG);

sys/arch/amiga/dev/toccata.c

570

(reg | PLAYBACK_ENABLE));

sys/arch/amiga/pci/cv3dpb.c

147

cv3dpb_pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg)

sys/arch/amiga/pci/cv3dpb.c

152

if ((unsigned int)reg >= PCI_CONF_SIZE)

sys/arch/amiga/pci/cv3dpb.c

158

(func<<5) + reg);

sys/arch/amiga/pci/cv3dpb.c

162

pc->pci_conf_datah, bus, dev, func, reg, data);

sys/arch/amiga/pci/cv3dpb.c

168

cv3dpb_pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t val)

sys/arch/amiga/pci/cv3dpb.c

172

if ((unsigned int)reg >= PCI_CONF_SIZE)

sys/arch/amiga/pci/cv3dpb.c

178

(func << 5) + reg, val);

sys/arch/amiga/pci/cv3dpb.c

182

pc->pci_conf_datah, bus, dev, func, reg, val);

sys/arch/amiga/pci/em4k.c

310

em4k_pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg)

sys/arch/amiga/pci/em4k.c

315

if ((unsigned int)reg >= PCI_CONF_SIZE)

sys/arch/amiga/pci/em4k.c

321

EMPB_CONF_DEV_STRIDE*dev + EMPB_CONF_FUNC_STRIDE*func + reg);

sys/arch/amiga/pci/em4k.c

325

pc->pci_conf_datah, bus, dev, func, reg, data);

sys/arch/amiga/pci/em4k.c

332

em4k_pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t val)

sys/arch/amiga/pci/em4k.c

336

if ((unsigned int)reg >= PCI_CONF_SIZE)

sys/arch/amiga/pci/em4k.c

342

EMPB_CONF_DEV_STRIDE*dev + EMPB_CONF_FUNC_STRIDE*func + reg, val);

sys/arch/amiga/pci/em4k.c

346

pc->pci_conf_datah, bus, dev, func, reg, val);

sys/arch/amiga/pci/empb.c

387

empb_pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg)

sys/arch/amiga/pci/empb.c

394

if ((unsigned int)reg >= PCI_CONF_SIZE)

sys/arch/amiga/pci/empb.c

406

EMPB_CONF_DEV_STRIDE*dev + EMPB_CONF_FUNC_STRIDE*func + reg);

sys/arch/amiga/pci/empb.c

410

pc->pci_conf_datah, bus, dev, func, reg, data);

sys/arch/amiga/pci/empb.c

421

empb_pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t val)

sys/arch/amiga/pci/empb.c

427

if ((unsigned int)reg >= PCI_CONF_SIZE)

sys/arch/amiga/pci/empb.c

439

EMPB_CONF_DEV_STRIDE*dev + EMPB_CONF_FUNC_STRIDE*func + reg, val);

sys/arch/amiga/pci/empb.c

443

pc->pci_conf_datah, bus, dev, func, reg, val);

sys/arch/amiga/pci/mppb.c

192

mppb_pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg)

sys/arch/amiga/pci/mppb.c

197

if ((unsigned int)reg >= PCI_CONF_SIZE)

sys/arch/amiga/pci/mppb.c

203

(MPPB_CONF_STRIDE*dev) + reg);

sys/arch/amiga/pci/mppb.c

207

pc->pci_conf_datah, bus, dev, func, reg, data);

sys/arch/amiga/pci/mppb.c

213

mppb_pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t val)

sys/arch/amiga/pci/mppb.c

217

if ((unsigned int)reg >= PCI_CONF_SIZE)

sys/arch/amiga/pci/mppb.c

223

(MPPB_CONF_STRIDE*dev) + reg, val);

sys/arch/amiga/pci/mppb.c

227

pc->pci_conf_datah, bus, dev, func, reg, val);

sys/arch/amiga/pci/p5pb.c

340

p5pb_pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg)

sys/arch/amiga/pci/p5pb.c

346

if ((unsigned int)reg >= PCI_CONF_SIZE)

sys/arch/amiga/pci/p5pb.c

351

offset = (OFF_PCI_DEVICE << dev) + reg;

sys/arch/amiga/pci/p5pb.c

370

pc->pci_conf_datah, bus, dev, func, reg, data);

sys/arch/amiga/pci/p5pb.c

376

p5pb_pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t val)

sys/arch/amiga/pci/p5pb.c

381

if ((unsigned int)reg >= PCI_CONF_SIZE)

sys/arch/amiga/pci/p5pb.c

386

offset = (OFF_PCI_DEVICE << dev) + reg;

sys/arch/amiga/pci/p5pb.c

405

pc->pci_conf_datah, bus, dev, func, reg, val);

sys/arch/amigappc/amigappc/p5reg.h

100

#define P5read(reg, val) \

sys/arch/amigappc/amigappc/p5reg.h

102

(val) = *(volatile unsigned char *)(P5BASE + (reg)); \

sys/arch/amigappc/amigappc/p5reg.h

106

#define P5write(reg, val) \

sys/arch/amigappc/amigappc/p5reg.h

108

*(volatile unsigned char *)(P5BASE + (reg)) = (val); \

sys/arch/arc/arc/c_jazz_eisa.c

108

mc_jazz_eisa_read(struct mc146818_softc *sc, u_int reg)

sys/arch/arc/arc/c_jazz_eisa.c

113

out32(arc_bus_io.bs_vbase + C_JAZZ_EISA_TODCLOCK_AS, as | reg);

sys/arch/arc/arc/c_jazz_eisa.c

119

mc_jazz_eisa_write(struct mc146818_softc *sc, u_int reg, u_int datum)

sys/arch/arc/arc/c_jazz_eisa.c

124

out32(arc_bus_io.bs_vbase + C_JAZZ_EISA_TODCLOCK_AS, as | reg);

sys/arch/arc/arc/c_nec_pci.c

132

mc_nec_pci_read(struct mc146818_softc *sc, u_int reg)

sys/arch/arc/arc/c_nec_pci.c

137

bus_space_write_1(sc->sc_bst, sc->sc_bsh, 1, as | reg);

sys/arch/arc/arc/c_nec_pci.c

143

mc_nec_pci_write(struct mc146818_softc *sc, u_int reg, u_int datum)

sys/arch/arc/arc/c_nec_pci.c

148

bus_space_write_1(sc->sc_bst, sc->sc_bsh, 1, as | reg);

sys/arch/arc/dev/pccons.c

219

#define crtc_read_1(reg) \

sys/arch/arc/dev/pccons.c

221

pccons_console_context.pc_6845_ioh, reg)

sys/arch/arc/dev/pccons.c

222

#define crtc_write_1(reg, data) \

sys/arch/arc/dev/pccons.c

224

pccons_console_context.pc_6845_ioh, reg, data)

sys/arch/arc/isa/mcclock_isa.c

141

mc_isa_read(struct mc146818_softc *sc, u_int reg)

sys/arch/arc/isa/mcclock_isa.c

144

bus_space_write_1(sc->sc_bst, sc->sc_bsh, 0, reg);

sys/arch/arc/isa/mcclock_isa.c

149

mc_isa_write(struct mc146818_softc *sc, u_int reg, u_int datum)

sys/arch/arc/isa/mcclock_isa.c

152

bus_space_write_1(sc->sc_bst, sc->sc_bsh, 0, reg);

sys/arch/arc/jazz/asc.c

251

asc_read_reg(struct ncr53c9x_softc *sc, int reg)

sys/arch/arc/jazz/asc.c

255

return bus_space_read_1(asc->sc_iot, asc->sc_ioh, reg);

sys/arch/arc/jazz/asc.c

259

asc_write_reg(struct ncr53c9x_softc *sc, int reg, uint8_t val)

sys/arch/arc/jazz/asc.c

263

bus_space_write_1(asc->sc_iot, asc->sc_ioh, reg, val);

sys/arch/arc/pci/necpb.c

327

necpb_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg)

sys/arch/arc/pci/necpb.c

332

if ((unsigned int)reg >= PCI_CONF_SIZE)

sys/arch/arc/pci/necpb.c

336

out32(RD94_SYS_PCI_CONFADDR, tag | reg);

sys/arch/arc/pci/necpb.c

345

necpb_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data)

sys/arch/arc/pci/necpb.c

349

if ((unsigned int)reg >= PCI_CONF_SIZE)

sys/arch/arc/pci/necpb.c

353

out32(RD94_SYS_PCI_CONFADDR, tag | reg);

sys/arch/arm/acpi/acpi_pci_graviton.c

55

acpi_pci_graviton_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t *data)

sys/arch/arm/acpi/acpi_pci_graviton.c

67

*data = bus_space_read_4(ap->ap_bst, ap->ap_conf_bsh, reg);

sys/arch/arm/acpi/acpi_pci_graviton.c

71

return acpimcfg_conf_read(pc, tag, reg, data);

sys/arch/arm/acpi/acpi_pci_graviton.c

75

acpi_pci_graviton_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data)

sys/arch/arm/acpi/acpi_pci_graviton.c

86

bus_space_write_4(ap->ap_bst, ap->ap_conf_bsh, reg, data);

sys/arch/arm/acpi/acpi_pci_graviton.c

90

return acpimcfg_conf_write(pc, tag, reg, data);

sys/arch/arm/acpi/acpi_pci_layerscape_gen4.c

100

const bus_size_t page_addr = indirect ? REG_TO_PAGE_ADDR(reg) : reg;

sys/arch/arm/acpi/acpi_pci_layerscape_gen4.c

108

bus_size_t reg, pcireg_t data)

sys/arch/arm/acpi/acpi_pci_layerscape_gen4.c

110

const bool indirect = reg >= INDIRECT_ADDR_BOUNDARY;

sys/arch/arm/acpi/acpi_pci_layerscape_gen4.c

111

const u_int page_index = indirect ? REG_TO_PAGE_INDEX(reg) : 0;

sys/arch/arm/acpi/acpi_pci_layerscape_gen4.c

112

const bus_size_t page_addr = indirect ? REG_TO_PAGE_ADDR(reg) : reg;

sys/arch/arm/acpi/acpi_pci_layerscape_gen4.c

134

acpi_pci_layerscape_gen4_is_tag_okay(pci_chipset_tag_t pc, pcitag_t tag, int reg)

sys/arch/arm/acpi/acpi_pci_layerscape_gen4.c

145

return acpimcfg_conf_valid(pc, tag, reg);

sys/arch/arm/acpi/acpi_pci_layerscape_gen4.c

151

acpi_pci_layerscape_gen4_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t *data)

sys/arch/arm/acpi/acpi_pci_layerscape_gen4.c

159

if (!acpi_pci_layerscape_gen4_is_tag_okay(pc, tag, reg)) {

sys/arch/arm/acpi/acpi_pci_layerscape_gen4.c

166

if (pcie->rev == 0x10 && reg == PCI_ID_REG)

sys/arch/arm/acpi/acpi_pci_layerscape_gen4.c

170

*data = acpi_pci_layerscape_gen4_ccsr_read4(pcie, reg);

sys/arch/arm/acpi/acpi_pci_layerscape_gen4.c

173

*data = bus_space_read_4(pcie->bst, pcie->win_bsh, reg);

sys/arch/arm/acpi/acpi_pci_layerscape_gen4.c

176

if (pcie->rev == 0x10 && reg == PCI_ID_REG)

sys/arch/arm/acpi/acpi_pci_layerscape_gen4.c

185

acpi_pci_layerscape_gen4_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data)

sys/arch/arm/acpi/acpi_pci_layerscape_gen4.c

193

if (!acpi_pci_layerscape_gen4_is_tag_okay(pc, tag, reg))

sys/arch/arm/acpi/acpi_pci_layerscape_gen4.c

199

acpi_pci_layerscape_gen4_ccsr_write4(pcie, reg, data);

sys/arch/arm/acpi/acpi_pci_layerscape_gen4.c

202

bus_space_write_4(pcie->bst, pcie->win_bsh, reg, data);

sys/arch/arm/acpi/acpi_pci_layerscape_gen4.c

69

#define REG_TO_PAGE_INDEX(reg) (((reg) >> 10) & 0x3ff)

sys/arch/arm/acpi/acpi_pci_layerscape_gen4.c

70

#define REG_TO_PAGE_ADDR(reg) (((reg) & 0x3ff) | INDIRECT_ADDR_BOUNDARY)

sys/arch/arm/acpi/acpi_pci_layerscape_gen4.c

96

acpi_pci_layerscape_gen4_ccsr_read4(struct acpi_pci_layerscape_gen4 *pcie, bus_size_t reg)

sys/arch/arm/acpi/acpi_pci_layerscape_gen4.c

98

const bool indirect = reg >= INDIRECT_ADDR_BOUNDARY;

sys/arch/arm/acpi/acpi_pci_layerscape_gen4.c

99

const u_int page_index = indirect ? REG_TO_PAGE_INDEX(reg) : 0;

sys/arch/arm/acpi/acpi_pci_n1sdp.c

107

if (d > 0 || f > 0 || reg >= PCI_EXTCONF_SIZE) {

sys/arch/arm/acpi/acpi_pci_n1sdp.c

111

*data = bus_space_read_4(ap->ap_bst, ap->ap_conf_bsh, reg);

sys/arch/arm/acpi/acpi_pci_n1sdp.c

120

return acpimcfg_conf_read(pc, tag, reg, data);

sys/arch/arm/acpi/acpi_pci_n1sdp.c

124

acpi_pci_n1sdp_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data)

sys/arch/arm/acpi/acpi_pci_n1sdp.c

132

if (d > 0 || f > 0 || reg >= PCI_EXTCONF_SIZE) {

sys/arch/arm/acpi/acpi_pci_n1sdp.c

135

bus_space_write_4(ap->ap_bst, ap->ap_conf_bsh, reg, data);

sys/arch/arm/acpi/acpi_pci_n1sdp.c

142

return acpimcfg_conf_write(pc, tag, reg, data);

sys/arch/arm/acpi/acpi_pci_n1sdp.c

99

acpi_pci_n1sdp_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t *data)

sys/arch/arm/acpi/acpi_pci_smccc.c

48

acpi_pci_smccc_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg,

sys/arch/arm/acpi/acpi_pci_smccc.c

62

status = pci_smccc_read(PCI_SMCCC_SBDF(ap->ap_seg, b, d, f), reg,

sys/arch/arm/acpi/acpi_pci_smccc.c

73

acpi_pci_smccc_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg,

sys/arch/arm/acpi/acpi_pci_smccc.c

86

status = pci_smccc_write(PCI_SMCCC_SBDF(ap->ap_seg, b, d, f), reg,

sys/arch/arm/acpi/sbsawdt_acpi.c

83

#define REFRESH_RD4(sc, reg) \

sys/arch/arm/acpi/sbsawdt_acpi.c

84

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh_r, (reg))

sys/arch/arm/acpi/sbsawdt_acpi.c

85

#define REFRESH_WR4(sc, reg, val) \

sys/arch/arm/acpi/sbsawdt_acpi.c

86

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh_r, (reg), (val))

sys/arch/arm/acpi/sbsawdt_acpi.c

88

#define CONTROL_RD4(sc, reg) \

sys/arch/arm/acpi/sbsawdt_acpi.c

89

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh_c, (reg), (val))

sys/arch/arm/acpi/sbsawdt_acpi.c

90

#define CONTROL_WR4(sc, reg, val) \

sys/arch/arm/acpi/sbsawdt_acpi.c

91

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh_c, (reg), (val))

sys/arch/arm/amlogic/gxlphy.c

104

gxl_readreg(struct mii_softc *sc, u_int bank, u_int reg)

sys/arch/arm/amlogic/gxlphy.c

112

__SHIFTIN(reg, TSTCNTL_READ_ADDR));

sys/arch/arm/amlogic/gxlphy.c

120

gxl_writereg(struct mii_softc *sc, u_int bank, u_int reg, uint16_t val)

sys/arch/arm/amlogic/gxlphy.c

127

__SHIFTIN(reg, TSTCNTL_WRITE_ADDR));

sys/arch/arm/amlogic/gxlphy.c

194

uint16_t reg;

sys/arch/arm/amlogic/gxlphy.c

211

PHY_READ(sc, MII_BMCR, &reg);

sys/arch/arm/amlogic/gxlphy.c

212

PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);

sys/arch/arm/amlogic/meson6_timer.c

57

#define TIMER_READ(sc, reg) \

sys/arch/arm/amlogic/meson6_timer.c

58

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/amlogic/meson6_timer.c

59

#define TIMER_WRITE(sc, reg, val) \

sys/arch/arm/amlogic/meson6_timer.c

60

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/amlogic/meson8b_pinctrl.c

168

.reg = CBUS_REG((_gpiobase) + 0), \

sys/arch/arm/amlogic/meson8b_pinctrl.c

173

.reg = CBUS_REG((_gpiobase) + 1), \

sys/arch/arm/amlogic/meson8b_pinctrl.c

178

.reg = CBUS_REG((_gpiobase) + 2), \

sys/arch/arm/amlogic/meson8b_pinctrl.c

183

.reg = CBUS_REG(_pullbase), \

sys/arch/arm/amlogic/meson8b_pinctrl.c

188

.reg = CBUS_REG(_pullbase), \

sys/arch/arm/amlogic/meson8b_pinctrl.c

284

.reg = 0, \

sys/arch/arm/amlogic/meson8b_pinctrl.c

289

.reg = 0, \

sys/arch/arm/amlogic/meson8b_pinctrl.c

294

.reg = 4, \

sys/arch/arm/amlogic/meson8b_pinctrl.c

299

.reg = 0, \

sys/arch/arm/amlogic/meson8b_pinctrl.c

304

.reg = 0, \

sys/arch/arm/amlogic/meson_clk.c

380

meson_clk_read(struct meson_clk_softc *sc, bus_size_t reg)

sys/arch/arm/amlogic/meson_clk.c

383

return syscon_read_4(sc->sc_syscon, reg);

sys/arch/arm/amlogic/meson_clk.c

385

return bus_space_read_4(sc->sc_bst, sc->sc_bsh, reg);

sys/arch/arm/amlogic/meson_clk.c

389

meson_clk_write(struct meson_clk_softc *sc, bus_size_t reg, uint32_t val)

sys/arch/arm/amlogic/meson_clk.c

392

syscon_write_4(sc->sc_syscon, reg, val);

sys/arch/arm/amlogic/meson_clk.c

394

bus_space_write_4(sc->sc_bst, sc->sc_bsh, reg, val);

sys/arch/arm/amlogic/meson_clk.c

77

const uint32_t val = CLK_READ(sc, reset->reg);

sys/arch/arm/amlogic/meson_clk.c

78

CLK_WRITE(sc, reset->reg, val | reset->mask);

sys/arch/arm/amlogic/meson_clk.c

91

const uint32_t val = CLK_READ(sc, reset->reg);

sys/arch/arm/amlogic/meson_clk.c

92

CLK_WRITE(sc, reset->reg, val & ~reset->mask);

sys/arch/arm/amlogic/meson_clk.h

111

.u.gate.reg = (_reg), \

sys/arch/arm/amlogic/meson_clk.h

126

bus_size_t reg;

sys/arch/arm/amlogic/meson_clk.h

146

.u.div.reg = (_reg), \

sys/arch/arm/amlogic/meson_clk.h

189

bus_size_t reg;

sys/arch/arm/amlogic/meson_clk.h

207

.u.mux.reg = (_reg), \

sys/arch/arm/amlogic/meson_clk.h

222

.u.mux.reg = (_reg), \

sys/arch/arm/amlogic/meson_clk.h

233

bus_size_t reg;

sys/arch/arm/amlogic/meson_clk.h

238

{ .reg = (_reg), .mask = (_mask) }

sys/arch/arm/amlogic/meson_clk.h

392

#define CLK_WRITE_BITS(sc, reg, mask, val) \

sys/arch/arm/amlogic/meson_clk.h

394

uint32_t _cwb_tmp_ = CLK_READ((sc), (reg)); \

sys/arch/arm/amlogic/meson_clk.h

397

CLK_WRITE((sc), (reg), _cwb_tmp_); \

sys/arch/arm/amlogic/meson_clk.h

44

bus_size_t reg;

sys/arch/arm/amlogic/meson_clk.h

50

.reg = (_reg), \

sys/arch/arm/amlogic/meson_clk.h

93

bus_size_t reg;

sys/arch/arm/amlogic/meson_clk_div.c

104

val = CLK_READ(sc, div->reg);

sys/arch/arm/amlogic/meson_clk_div.c

129

CLK_WRITE(sc, div->reg, val);

sys/arch/arm/amlogic/meson_clk_div.c

60

val = CLK_READ(sc, div->reg);

sys/arch/arm/amlogic/meson_clk_gate.c

53

val = CLK_READ(sc, gate->reg);

sys/arch/arm/amlogic/meson_clk_gate.c

58

CLK_WRITE(sc, gate->reg, val);

sys/arch/arm/amlogic/meson_clk_mpll.c

63

val = CLK_READ(sc, mpll->sdm.reg);

sys/arch/arm/amlogic/meson_clk_mpll.c

66

val = CLK_READ(sc, mpll->n2.reg);

sys/arch/arm/amlogic/meson_clk_mux.c

49

val = CLK_READ(sc, mux->reg);

sys/arch/arm/amlogic/meson_clk_pll.c

144

CLK_WRITE_BITS(sc, pll->reset.reg, pll->reset.mask, 1);

sys/arch/arm/amlogic/meson_clk_pll.c

145

CLK_WRITE_BITS(sc, pll->reset.reg, pll->reset.mask, 0);

sys/arch/arm/amlogic/meson_clk_pll.c

151

CLK_WRITE_BITS(sc, pll->reset.reg, pll->reset.mask, 1);

sys/arch/arm/amlogic/meson_clk_pll.c

152

CLK_WRITE_BITS(sc, pll->enable.reg, pll->enable.mask, 0);

sys/arch/arm/amlogic/meson_clk_pll.c

155

CLK_WRITE_BITS(sc, pll->m.reg, pll->m.mask, m);

sys/arch/arm/amlogic/meson_clk_pll.c

156

CLK_WRITE_BITS(sc, pll->n.reg, pll->n.mask, n);

sys/arch/arm/amlogic/meson_clk_pll.c

158

CLK_WRITE_BITS(sc, pll->frac.reg, pll->frac.mask, frac);

sys/arch/arm/amlogic/meson_clk_pll.c

162

CLK_WRITE_BITS(sc, pll->reset.reg, pll->reset.mask, 1);

sys/arch/arm/amlogic/meson_clk_pll.c

163

CLK_WRITE_BITS(sc, pll->enable.reg, pll->enable.mask, 1);

sys/arch/arm/amlogic/meson_clk_pll.c

165

CLK_WRITE_BITS(sc, pll->reset.reg, pll->reset.mask, 0);

sys/arch/arm/amlogic/meson_clk_pll.c

62

val = CLK_READ(sc, pll->n.reg);

sys/arch/arm/amlogic/meson_clk_pll.c

65

val = CLK_READ(sc, pll->m.reg);

sys/arch/arm/amlogic/meson_clk_pll.c

69

val = CLK_READ(sc, pll->frac.reg);

sys/arch/arm/amlogic/meson_clk_pll.c

92

if ((CLK_READ(sc, pll->l.reg) & pll->l.mask) != 0)

sys/arch/arm/amlogic/meson_genfb.c

161

#define VPU_READ(sc, reg) \

sys/arch/arm/amlogic/meson_genfb.c

162

bus_space_read_4((sc)->sc_bst, (sc)->sc_vpu_bsh, (reg))

sys/arch/arm/amlogic/meson_genfb.c

163

#define VPU_WRITE(sc, reg, val) \

sys/arch/arm/amlogic/meson_genfb.c

164

bus_space_write_4((sc)->sc_bst, (sc)->sc_vpu_bsh, (reg), (val))

sys/arch/arm/amlogic/meson_genfb.c

166

#define CAV_READ(sc, reg) \

sys/arch/arm/amlogic/meson_genfb.c

167

bus_space_read_4((sc)->sc_bst, (sc)->sc_cav_bsh, (reg))

sys/arch/arm/amlogic/meson_genfb.c

168

#define CAV_WRITE(sc, reg, val) \

sys/arch/arm/amlogic/meson_genfb.c

169

bus_space_write_4((sc)->sc_bst, (sc)->sc_cav_bsh, (reg), (val))

sys/arch/arm/amlogic/meson_i2c.c

129

static void mesoni2c_set_mask(struct mesoni2c_softc *sc, bus_size_t reg, uint32_t mask, uint32_t value);

sys/arch/arm/amlogic/meson_i2c.c

153

#define RD4(sc, reg) \

sys/arch/arm/amlogic/meson_i2c.c

154

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/amlogic/meson_i2c.c

156

#define WR4(sc, reg, val) \

sys/arch/arm/amlogic/meson_i2c.c

157

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/amlogic/meson_i2c.c

160

mesoni2c_set_mask(struct mesoni2c_softc *sc, bus_size_t reg, uint32_t mask,

sys/arch/arm/amlogic/meson_i2c.c

163

uint32_t data = RD4(sc, reg);

sys/arch/arm/amlogic/meson_i2c.c

166

WR4(sc, reg, data);

sys/arch/arm/amlogic/meson_i2c.c

180

bus_size_t reg;

sys/arch/arm/amlogic/meson_i2c.c

184

reg = MESONI2C_TOKEN_LIST_REG1;

sys/arch/arm/amlogic/meson_i2c.c

187

reg = MESONI2C_TOKEN_LIST_REG0;

sys/arch/arm/amlogic/meson_i2c.c

193

mesoni2c_set_mask(sc, reg, MESONI2C_TOKEN_MASK << pos, token << pos);

sys/arch/arm/amlogic/meson_i2c.c

201

bus_size_t reg;

sys/arch/arm/amlogic/meson_i2c.c

205

reg = MESONI2C_TOKEN_WDATA_REG1;

sys/arch/arm/amlogic/meson_i2c.c

208

reg = MESONI2C_TOKEN_WDATA_REG0;

sys/arch/arm/amlogic/meson_i2c.c

214

mesoni2c_set_mask(sc, reg, MESONI2C_DATA_MASK << pos, ((uint32_t) data) << pos);

sys/arch/arm/amlogic/meson_i2c.c

221

bus_size_t reg;

sys/arch/arm/amlogic/meson_i2c.c

225

reg = MESONI2C_TOKEN_RDATA_REG1;

sys/arch/arm/amlogic/meson_i2c.c

228

reg = MESONI2C_TOKEN_RDATA_REG0;

sys/arch/arm/amlogic/meson_i2c.c

235

return (RD4(sc, reg) >> pos) & MESONI2C_DATA_MASK;

sys/arch/arm/amlogic/meson_pinctrl.c

102

#define MUX_READ(sc, reg) \

sys/arch/arm/amlogic/meson_pinctrl.c

103

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh_mux, (reg))

sys/arch/arm/amlogic/meson_pinctrl.c

104

#define MUX_WRITE(sc, reg, val) \

sys/arch/arm/amlogic/meson_pinctrl.c

105

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh_mux, (reg), (val))

sys/arch/arm/amlogic/meson_pinctrl.c

143

val = MUX_READ(sc, group->reg);

sys/arch/arm/amlogic/meson_pinctrl.c

154

MUX_WRITE(sc, group->reg, val);

sys/arch/arm/amlogic/meson_pinctrl.c

244

data = bus_space_read_4(sc->sc_bst, bsh, gpio_reg->reg);

sys/arch/arm/amlogic/meson_pinctrl.c

264

data = bus_space_read_4(sc->sc_bst, bsh, gpio_reg->reg);

sys/arch/arm/amlogic/meson_pinctrl.c

269

bus_space_write_4(sc->sc_bst, bsh, gpio_reg->reg, data);

sys/arch/arm/amlogic/meson_pinctrl.c

283

data = bus_space_read_4(sc->sc_bst, bsh, pin_def->oen.reg);

sys/arch/arm/amlogic/meson_pinctrl.c

288

bus_space_write_4(sc->sc_bst, bsh, pin_def->oen.reg, data);

sys/arch/arm/amlogic/meson_pinctrl.c

308

data = bus_space_read_4(sc->sc_bst, bsh, pin_def->pupd.reg);

sys/arch/arm/amlogic/meson_pinctrl.c

313

bus_space_write_4(sc->sc_bst, bsh, pin_def->pupd.reg, data);

sys/arch/arm/amlogic/meson_pinctrl.c

316

data = bus_space_read_4(sc->sc_bst, bsh, pin_def->pupden.reg);

sys/arch/arm/amlogic/meson_pinctrl.c

318

bus_space_write_4(sc->sc_bst, bsh, pin_def->pupden.reg, data);

sys/arch/arm/amlogic/meson_pinctrl.c

321

data = bus_space_read_4(sc->sc_bst, bsh, pin_def->pupden.reg);

sys/arch/arm/amlogic/meson_pinctrl.c

323

bus_space_write_4(sc->sc_bst, bsh, pin_def->pupden.reg, data);

sys/arch/arm/amlogic/meson_pinctrl.h

46

bus_size_t reg;

sys/arch/arm/amlogic/meson_pinctrl.h

62

bus_size_t reg;

sys/arch/arm/amlogic/meson_pwm.c

63

#define PWM_READ_REG(sc, reg) \

sys/arch/arm/amlogic/meson_pwm.c

64

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg) * 4)

sys/arch/arm/amlogic/meson_pwm.c

65

#define PWM_WRITE_REG(sc, reg, val) \

sys/arch/arm/amlogic/meson_pwm.c

66

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg) * 4, (val))

sys/arch/arm/amlogic/meson_resets.c

59

#define RESET_READ(sc, reg) \

sys/arch/arm/amlogic/meson_resets.c

60

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/amlogic/meson_resets.c

61

#define RESET_WRITE(sc, reg, val) \

sys/arch/arm/amlogic/meson_resets.c

62

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/amlogic/meson_rtc.c

71

#define RTC_WRITE(sc, reg, val) \

sys/arch/arm/amlogic/meson_rtc.c

72

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/amlogic/meson_rtc.c

73

#define RTC_READ(sc, reg) \

sys/arch/arm/amlogic/meson_rtc.c

74

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/amlogic/meson_rtc.c

77

setbits(struct meson_rtc_softc *sc, uint32_t reg, uint32_t bits)

sys/arch/arm/amlogic/meson_rtc.c

80

RTC_WRITE(sc, reg, RTC_READ(sc, reg) | bits);

sys/arch/arm/amlogic/meson_rtc.c

84

clrbits(struct meson_rtc_softc *sc, uint32_t reg, uint32_t bits)

sys/arch/arm/amlogic/meson_rtc.c

87

RTC_WRITE(sc, reg, RTC_READ(sc, reg) & ~bits);

sys/arch/arm/amlogic/meson_sdhc.c

138

#define SDHC_WRITE(sc, reg, val) \

sys/arch/arm/amlogic/meson_sdhc.c

139

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/amlogic/meson_sdhc.c

140

#define SDHC_READ(sc, reg) \

sys/arch/arm/amlogic/meson_sdhc.c

141

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/amlogic/meson_sdhc.c

145

meson_sdhc_set_clear(struct meson_sdhc_softc *sc, bus_addr_t reg, uint32_t set, uint32_t clr)

sys/arch/arm/amlogic/meson_sdhc.c

147

const uint32_t old = SDHC_READ(sc, reg);

sys/arch/arm/amlogic/meson_sdhc.c

150

SDHC_WRITE(sc, reg, new);

sys/arch/arm/amlogic/meson_sdio.c

128

#define SDIO_WRITE(sc, reg, val) \

sys/arch/arm/amlogic/meson_sdio.c

129

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/amlogic/meson_sdio.c

130

#define SDIO_READ(sc, reg) \

sys/arch/arm/amlogic/meson_sdio.c

131

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/amlogic/meson_thermal.c

64

#define THERMAL_READ_REG(sc, reg) \

sys/arch/arm/amlogic/meson_thermal.c

65

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg) * 4)

sys/arch/arm/amlogic/meson_thermal.c

66

#define THERMAL_WRITE_REG(sc, reg, val) \

sys/arch/arm/amlogic/meson_thermal.c

67

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg) * 4, (val))

sys/arch/arm/amlogic/meson_thermal.c

69

#define AOSECURE_READ(sc, reg) \

sys/arch/arm/amlogic/meson_thermal.c

70

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh_ao, (reg))

sys/arch/arm/amlogic/meson_thermal.c

71

#define AOSECURE_WRITE(sc, reg, val) \

sys/arch/arm/amlogic/meson_thermal.c

72

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh_ao, (reg), (val))

sys/arch/arm/amlogic/meson_usbctrl.c

102

#define USBCTRL_READ_REG(sc, reg) \

sys/arch/arm/amlogic/meson_usbctrl.c

103

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/amlogic/meson_usbctrl.c

104

#define USBCTRL_WRITE_REG(sc, reg, val) \

sys/arch/arm/amlogic/meson_usbctrl.c

105

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/amlogic/meson_usbctrl.c

107

#define USBCTRLGLUE_READ_REG(sc, reg) \

sys/arch/arm/amlogic/meson_usbctrl.c

108

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh + (sc)->sc_conf->glue_offset, (reg))

sys/arch/arm/amlogic/meson_usbctrl.c

109

#define USBCTRLGLUE_WRITE_REG(sc, reg, val) \

sys/arch/arm/amlogic/meson_usbctrl.c

110

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh + (sc)->sc_conf->glue_offset, (reg), (val))

sys/arch/arm/amlogic/meson_usbphy.c

122

struct fdtbus_regulator *reg;

sys/arch/arm/amlogic/meson_usbphy.c

128

reg = fdtbus_regulator_acquire(sc->sc_phandle, "phy-supply");

sys/arch/arm/amlogic/meson_usbphy.c

129

if (reg != NULL) {

sys/arch/arm/amlogic/meson_usbphy.c

130

error = fdtbus_regulator_enable(reg);

sys/arch/arm/amlogic/meson_usbphy.c

80

#define PHY_READ(sc, reg) \

sys/arch/arm/amlogic/meson_usbphy.c

81

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/amlogic/meson_usbphy.c

82

#define PHY_WRITE(sc, reg, val) \

sys/arch/arm/amlogic/meson_usbphy.c

83

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/amlogic/meson_wdt.c

69

#define WDT_READ(sc, reg) \

sys/arch/arm/amlogic/meson_wdt.c

70

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/amlogic/meson_wdt.c

71

#define WDT_WRITE(sc, reg, val) \

sys/arch/arm/amlogic/meson_wdt.c

72

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/amlogic/mesong12_clkc.c

1265

switch (clk->u.mux.reg) {

sys/arch/arm/amlogic/mesong12_clkc.c

1278

if ((CLK_READ(sc, clk->u.mux.reg) & __BIT(11)) == 0) {

sys/arch/arm/amlogic/mesong12_clkc.c

1284

switch (clk->u.mux.reg) {

sys/arch/arm/amlogic/mesong12_clkc.c

1325

switch (clk->u.mux.reg) {

sys/arch/arm/amlogic/mesong12_clkc.c

1351

val = CLK_READ(sc, clk->u.mux.reg);

sys/arch/arm/amlogic/mesong12_clkc.c

1352

CLK_WRITE(sc, clk->u.mux.reg, val & ~__BIT(11));

sys/arch/arm/amlogic/mesong12_clkc.c

1400

val = CLK_READ(sc, clk->u.mux.reg);

sys/arch/arm/amlogic/mesong12_clkc.c

1401

CLK_WRITE(sc, clk->u.mux.reg, val | __BIT(11));

sys/arch/arm/amlogic/mesong12_clkc.c

1441

CLK_WRITE_BITS(sc, pll->reset.reg, pll->reset.mask, 1);

sys/arch/arm/amlogic/mesong12_clkc.c

1470

CLK_WRITE_BITS(sc, pll->reset.reg, pll->reset.mask, 0);

sys/arch/arm/amlogic/mesong12_usb2phy.c

153

#define USB2PHY_READ_REG(sc, reg) \

sys/arch/arm/amlogic/mesong12_usb2phy.c

154

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/amlogic/mesong12_usb2phy.c

155

#define USB2PHY_WRITE_REG(sc, reg, val) \

sys/arch/arm/amlogic/mesong12_usb2phy.c

156

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/amlogic/mesong12_usb3pciephy.c

67

#define PHY_READ_REG(sc, reg) \

sys/arch/arm/amlogic/mesong12_usb3pciephy.c

68

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/amlogic/mesong12_usb3pciephy.c

69

#define PHY_WRITE_REG(sc, reg, val) \

sys/arch/arm/amlogic/mesong12_usb3pciephy.c

70

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/amlogic/mesong12a_pinctrl.c

161

.reg = CBUS_REG((_off) * 3 + 0), \

sys/arch/arm/amlogic/mesong12a_pinctrl.c

166

.reg = CBUS_REG((_off) * 3 + 1), \

sys/arch/arm/amlogic/mesong12a_pinctrl.c

171

.reg = CBUS_REG((_off) * 3 + 2), \

sys/arch/arm/amlogic/mesong12a_pinctrl.c

176

.reg = CBUS_REG(_off), \

sys/arch/arm/amlogic/mesong12a_pinctrl.c

181

.reg = CBUS_REG(_off), \

sys/arch/arm/amlogic/mesong12a_pinctrl.c

291

.reg = CBUS_REG(_off), \

sys/arch/arm/amlogic/mesong12a_pinctrl.c

296

.reg = CBUS_REG((_off) + 4), \

sys/arch/arm/amlogic/mesong12a_pinctrl.c

301

.reg = CBUS_REG((_off) + 1), \

sys/arch/arm/amlogic/mesong12a_pinctrl.c

306

.reg = CBUS_REG((_off) + 3), \

sys/arch/arm/amlogic/mesong12a_pinctrl.c

311

.reg = CBUS_REG((_off) + 2), \

sys/arch/arm/amlogic/mesong12a_pinctrl.c

338

{ .name = _name, .reg = CBUS_REG(_reg), .bit = (_func), \

sys/arch/arm/amlogic/mesong12a_pinctrl.c

594

{ .name = _name, .reg = CBUS_REG((_bit) / 8), .bit = (_func), \

sys/arch/arm/amlogic/mesongx_mmc.c

1038

for (u_int reg = 0x00; reg < 0x100; reg += 0x10) {

sys/arch/arm/amlogic/mesongx_mmc.c

1039

device_printf(sc->sc_dev, " %02x: %08x %08x %08x %08x\n", reg,

sys/arch/arm/amlogic/mesongx_mmc.c

1040

MMC_READ(sc, reg + 0),

sys/arch/arm/amlogic/mesongx_mmc.c

1041

MMC_READ(sc, reg + 4),

sys/arch/arm/amlogic/mesongx_mmc.c

1042

MMC_READ(sc, reg + 8),

sys/arch/arm/amlogic/mesongx_mmc.c

1043

MMC_READ(sc, reg + 12));

sys/arch/arm/amlogic/mesongx_mmc.c

260

#define MMC_WRITE(sc, reg, val) \

sys/arch/arm/amlogic/mesongx_mmc.c

261

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/amlogic/mesongx_mmc.c

262

#define MMC_READ(sc, reg) \

sys/arch/arm/amlogic/mesongx_mmc.c

263

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/amlogic/mesongx_wdt.c

72

#define WDT_READ(sc, reg) \

sys/arch/arm/amlogic/mesongx_wdt.c

73

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/amlogic/mesongx_wdt.c

74

#define WDT_WRITE(sc, reg, val) \

sys/arch/arm/amlogic/mesongx_wdt.c

75

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/amlogic/mesongxbb_pinctrl.c

207

.reg = CBUS_REG((_off) * 3 + 0), \

sys/arch/arm/amlogic/mesongxbb_pinctrl.c

212

.reg = CBUS_REG((_off) * 3 + 1), \

sys/arch/arm/amlogic/mesongxbb_pinctrl.c

217

.reg = CBUS_REG((_off) * 3 + 2), \

sys/arch/arm/amlogic/mesongxbb_pinctrl.c

222

.reg = CBUS_REG(_off), \

sys/arch/arm/amlogic/mesongxbb_pinctrl.c

227

.reg = CBUS_REG(_off), \

sys/arch/arm/amlogic/mesongxbb_pinctrl.c

368

.reg = 0, \

sys/arch/arm/amlogic/mesongxbb_pinctrl.c

373

.reg = 0, \

sys/arch/arm/amlogic/mesongxbb_pinctrl.c

378

.reg = 4, \

sys/arch/arm/amlogic/mesongxbb_pinctrl.c

383

.reg = 0, \

sys/arch/arm/amlogic/mesongxbb_pinctrl.c

388

.reg = 0, \

sys/arch/arm/amlogic/mesongxl_pinctrl.c

183

.reg = CBUS_REG((_off) * 3 + 0), \

sys/arch/arm/amlogic/mesongxl_pinctrl.c

188

.reg = CBUS_REG((_off) * 3 + 1), \

sys/arch/arm/amlogic/mesongxl_pinctrl.c

193

.reg = CBUS_REG((_off) * 3 + 2), \

sys/arch/arm/amlogic/mesongxl_pinctrl.c

198

.reg = CBUS_REG(_off), \

sys/arch/arm/amlogic/mesongxl_pinctrl.c

203

.reg = CBUS_REG(_off), \

sys/arch/arm/amlogic/mesongxl_pinctrl.c

288

.reg = 0, \

sys/arch/arm/amlogic/mesongxl_pinctrl.c

293

.reg = 0, \

sys/arch/arm/amlogic/mesongxl_pinctrl.c

298

.reg = 4, \

sys/arch/arm/amlogic/mesongxl_pinctrl.c

303

.reg = 0, \

sys/arch/arm/amlogic/mesongxl_pinctrl.c

308

.reg = 0, \

sys/arch/arm/amlogic/mesongxl_usb2phy.c

66

#define PHY_READ(sc, reg) \

sys/arch/arm/amlogic/mesongxl_usb2phy.c

67

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/amlogic/mesongxl_usb2phy.c

68

#define PHY_WRITE(sc, reg, val) \

sys/arch/arm/amlogic/mesongxl_usb2phy.c

69

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/amlogic/mesongxl_usb3phy.c

73

#define PHY_READ(sc, reg) \

sys/arch/arm/amlogic/mesongxl_usb3phy.c

74

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/amlogic/mesongxl_usb3phy.c

75

#define PHY_WRITE(sc, reg, val) \

sys/arch/arm/amlogic/mesongxl_usb3phy.c

76

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/apple/apple_dart.c

158

#define DART_READ(sc, reg) \

sys/arch/arm/apple/apple_dart.c

159

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/apple/apple_dart.c

160

#define DART_WRITE(sc, reg, val) \

sys/arch/arm/apple/apple_dart.c

161

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/apple/apple_iic.c

117

uint32_t reg;

sys/arch/arm/apple/apple_iic.c

142

reg = IIC_READ(sc, I2C_SMSTA);

sys/arch/arm/apple/apple_iic.c

143

if (reg & I2C_SMSTA_XEN)

sys/arch/arm/apple/apple_iic.c

146

if (reg & I2C_SMSTA_MTN)

sys/arch/arm/apple/apple_iic.c

152

reg = IIC_READ(sc, I2C_MRXFIFO);

sys/arch/arm/apple/apple_iic.c

153

if (reg & I2C_MRXFIFO_EMPTY)

sys/arch/arm/apple/apple_iic.c

155

bufbytes[i] = reg & I2C_MRXFIFO_DATA_MASK;

sys/arch/arm/apple/apple_iic.c

78

#define IIC_READ(sc, reg) \

sys/arch/arm/apple/apple_iic.c

79

(bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)))

sys/arch/arm/apple/apple_iic.c

80

#define IIC_WRITE(sc, reg, val) \

sys/arch/arm/apple/apple_iic.c

81

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/apple/apple_iic.c

82

#define HSET4(sc, reg, bits) \

sys/arch/arm/apple/apple_iic.c

83

IIC_WRITE((sc), (reg), IIC_READ((sc), (reg)) | (bits))

sys/arch/arm/apple/apple_iic.c

84

#define HCLR4(sc, reg, bits) \

sys/arch/arm/apple/apple_iic.c

85

IIC_WRITE((sc), (reg), IIC_READ((sc), (reg)) & ~(bits))

sys/arch/arm/apple/apple_intc.c

118

#define AIC_READ(sc, reg) \

sys/arch/arm/apple/apple_intc.c

119

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/apple/apple_intc.c

120

#define AIC_WRITE(sc, reg, val) \

sys/arch/arm/apple/apple_intc.c

121

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/apple/apple_mbox.c

69

#define MBOX_READ4(sc, reg) \

sys/arch/arm/apple/apple_mbox.c

70

(bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)))

sys/arch/arm/apple/apple_mbox.c

71

#define MBOX_READ8(sc, reg) \

sys/arch/arm/apple/apple_mbox.c

72

(bus_space_read_8((sc)->sc_bst, (sc)->sc_bsh, (reg)))

sys/arch/arm/apple/apple_mbox.c

73

#define MBOX_WRITE4(sc, reg, val) \

sys/arch/arm/apple/apple_mbox.c

74

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/apple/apple_mbox.c

75

#define MBOX_WRITE8(sc, reg, val) \

sys/arch/arm/apple/apple_mbox.c

76

bus_space_write_8((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/apple/apple_pcie.c

129

#define RREAD4(sc, reg) \

sys/arch/arm/apple/apple_pcie.c

130

(bus_space_read_4((sc)->sc_rc_bst, (sc)->sc_rc_bsh, (reg)))

sys/arch/arm/apple/apple_pcie.c

131

#define RWRITE4(sc, reg, val) \

sys/arch/arm/apple/apple_pcie.c

132

bus_space_write_4((sc)->sc_rc_bst, (sc)->sc_rc_bsh, (reg), (val))

sys/arch/arm/apple/apple_pcie.c

133

#define RSET4(sc, reg, bits) \

sys/arch/arm/apple/apple_pcie.c

134

RWRITE4((sc), (reg), RREAD4((sc), (reg)) | (bits))

sys/arch/arm/apple/apple_pcie.c

135

#define RCLR4(sc, reg, bits) \

sys/arch/arm/apple/apple_pcie.c

136

RWRITE4((sc), (reg), RREAD4((sc), (reg)) & ~(bits))

sys/arch/arm/apple/apple_pcie.c

153

const u_int *reg = fdtbus_get_prop(phandle, "reg", &len);

sys/arch/arm/apple/apple_pcie.c

158

u_int portno = __SHIFTOUT(be32toh(reg[0]), __BITS(13,11));

sys/arch/arm/apple/apple_pcie.c

171

#define PREAD4(bst, bsh, reg) \

sys/arch/arm/apple/apple_pcie.c

172

bus_space_read_4((bst), (bsh), (reg))

sys/arch/arm/apple/apple_pcie.c

173

#define PWRITE4(bst, bsh, reg, val) \

sys/arch/arm/apple/apple_pcie.c

174

bus_space_write_4((bst), (bsh), (reg), (val))

sys/arch/arm/apple/apple_pcie.c

175

#define PSET4(bst, bsh, reg, bits) \

sys/arch/arm/apple/apple_pcie.c

176

PWRITE4((bst), (bsh), (reg), PREAD4((bst), (bsh), (reg)) | (bits))

sys/arch/arm/apple/apple_pcie.c

177

#define PCLR4(bst, bsh, reg, bits) \

sys/arch/arm/apple/apple_pcie.c

178

PWRITE4((bst), (bsh), (reg), PREAD4((bst), (bsh), (reg)) & ~(bits))

sys/arch/arm/apple/apple_pinctrl.c

116

uint32_t reg = PINCTRL_READ(sc, GPIO_PIN(pin));

sys/arch/arm/apple/apple_pinctrl.c

117

reg &= ~GPIO_PIN_FUNC_MASK;

sys/arch/arm/apple/apple_pinctrl.c

118

reg &= ~GPIO_PIN_MODE_MASK;

sys/arch/arm/apple/apple_pinctrl.c

123

reg |= GPIO_PIN_MODE_INPUT;

sys/arch/arm/apple/apple_pinctrl.c

125

reg |= GPIO_PIN_MODE_OUTPUT;

sys/arch/arm/apple/apple_pinctrl.c

128

PINCTRL_WRITE(sc, GPIO_PIN(pin), reg);

sys/arch/arm/apple/apple_pinctrl.c

175

uint32_t reg = PINCTRL_READ(sc, GPIO_PIN(pin->pin_no));

sys/arch/arm/apple/apple_pinctrl.c

176

int val = __SHIFTOUT(reg, GPIO_PIN_DATA);

sys/arch/arm/apple/apple_pinctrl.c

222

uint32_t reg = PINCTRL_READ(sc, GPIO_PIN(pinno));

sys/arch/arm/apple/apple_pinctrl.c

223

reg &= ~GPIO_PIN_FUNC_MASK;

sys/arch/arm/apple/apple_pinctrl.c

224

reg |= __SHIFTIN(func, GPIO_PIN_FUNC_MASK);

sys/arch/arm/apple/apple_pinctrl.c

226

PINCTRL_WRITE(sc, GPIO_PIN(pinno), reg);

sys/arch/arm/apple/apple_pinctrl.c

80

#define PINCTRL_READ(sc, reg) \

sys/arch/arm/apple/apple_pinctrl.c

81

(bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)))

sys/arch/arm/apple/apple_pinctrl.c

82

#define PINCTRL_WRITE(sc, reg, val) \

sys/arch/arm/apple/apple_pinctrl.c

83

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/apple/apple_pinctrl.c

84

#define PINCTRL_SET(sc, reg, bits) \

sys/arch/arm/apple/apple_pinctrl.c

85

PINCTRL_WRITE((sc), (reg), PINCTRL_READ((sc), (reg)) | (bits))

sys/arch/arm/apple/apple_pinctrl.c

86

#define PINCTRL_CLR(sc, reg, bits) \

sys/arch/arm/apple/apple_pinctrl.c

87

PINCTRL_WRITE((sc), (reg), PINCTRL_READ((sc), (reg)) & ~(bits))

sys/arch/arm/apple/apple_pmgr.c

58

#define PMGR_READ(sc, reg) \

sys/arch/arm/apple/apple_pmgr.c

59

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/apple/apple_pmgr.c

60

#define PMGR_WRITE(sc, reg, val) \

sys/arch/arm/apple/apple_pmgr.c

61

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/apple/apple_wdog.c

60

#define WDOG_READ(sc, reg) \

sys/arch/arm/apple/apple_wdog.c

61

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/apple/apple_wdog.c

62

#define WDOG_WRITE(sc, reg, val) \

sys/arch/arm/apple/apple_wdog.c

63

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/arm/core_machdep.c

77

struct reg regs;

sys/arch/arm/arm/process_machdep.c

152

process_read_regs(struct lwp *l, struct reg *regs)

sys/arch/arm/arm/process_machdep.c

190

process_write_regs(struct lwp *l, const struct reg *regs)

sys/arch/arm/arm32/db_interface.c

346

db_fetch_reg(int reg, db_regs_t *regs)

sys/arch/arm/arm32/db_interface.c

349

switch (reg) {

sys/arch/arm/at91/at91aic.c

73

#define AICREG(reg) *((volatile uint32_t*) (AT91AIC_BASE + (reg)))

sys/arch/arm/at91/at91cf.c

74

bus_size_t reg;

sys/arch/arm/at91/at91dbgu.c

775

int reg;

sys/arch/arm/at91/at91dbgu.c

780

reg = 0xffff;

sys/arch/arm/at91/at91dbgu.c

787

reg =

sys/arch/arm/at91/at91dbgu.c

795

reg);

sys/arch/arm/at91/at91dbgureg.h

184

#define DBGUREG(reg) *((volatile uint32_t*)(AT91DBGU_BASE + (reg)))

sys/arch/arm/at91/at91emac.c

496

emac_mii_readreg(device_t self, int phy, int reg, uint16_t *val)

sys/arch/arm/at91/at91emac.c

504

| ((reg << ETH_MAN_REGA_SHIFT) & ETH_MAN_REGA)

sys/arch/arm/at91/at91emac.c

514

emac_mii_writereg(device_t self, int phy, int reg, uint16_t val)

sys/arch/arm/at91/at91emac.c

522

| ((reg << ETH_MAN_REGA_SHIFT) & ETH_MAN_REGA)

sys/arch/arm/at91/at91emac.c

535

uint32_t reg;

sys/arch/arm/at91/at91emac.c

541

reg = EMAC_READ(ETH_CFG);

sys/arch/arm/at91/at91emac.c

543

reg |= ETH_CFG_FD;

sys/arch/arm/at91/at91emac.c

545

reg &= ~ETH_CFG_FD;

sys/arch/arm/at91/at91emac.c

546

EMAC_WRITE(ETH_CFG, reg);

sys/arch/arm/at91/at91pmc.c

106

pclk >>= (reg & PMC_MCKR_PRES) >> PMC_MCKR_PRES_SHIFT;

sys/arch/arm/at91/at91pmc.c

107

mstclk = pclk / (((reg & PMC_MCKR_MDIV) >> PMC_MCKR_MDIV_SHIFT) + 1);

sys/arch/arm/at91/at91pmc.c

56

uint32_t reg;

sys/arch/arm/at91/at91pmc.c

58

if (!((reg = PMCREG(PMC_MOR)) & PMC_MOR_MOSCEN))

sys/arch/arm/at91/at91pmc.c

59

panic("%s: main oscillator not enabled (MOR=%#X)", __FUNCTION__, reg);

sys/arch/arm/at91/at91pmc.c

61

if (!((reg = PMCREG(PMC_MCFR)) & PMC_MCFR_MAINRDY))

sys/arch/arm/at91/at91pmc.c

62

panic("%s: main oscillator not ready (MCFR=%#X)", __FUNCTION__, reg);

sys/arch/arm/at91/at91pmc.c

64

mclk = ((reg & PMC_MCFR_MAINF) * SLOW_CLOCK) / 16U;

sys/arch/arm/at91/at91pmc.c

75

reg = PMCREG(PMC_PLLAR); pllaclk = 0;

sys/arch/arm/at91/at91pmc.c

76

if (reg & PMC_PLL_DIV) {

sys/arch/arm/at91/at91pmc.c

77

pllaclk = mclk * (((reg & PMC_PLL_MUL) >> PMC_PLL_MUL_SHIFT) + 1);

sys/arch/arm/at91/at91pmc.c

78

pllaclk /= (reg & PMC_PLL_DIV) >> PMC_PLL_DIV_SHIFT;

sys/arch/arm/at91/at91pmc.c

81

reg = PMCREG(PMC_PLLBR); pllbclk = 0;

sys/arch/arm/at91/at91pmc.c

82

if (reg & PMC_PLL_DIV) {

sys/arch/arm/at91/at91pmc.c

83

pllbclk = mclk * (((reg & PMC_PLL_MUL) >> PMC_PLL_MUL_SHIFT) + 1);

sys/arch/arm/at91/at91pmc.c

84

pllbclk /= (reg & PMC_PLL_DIV) >> PMC_PLL_DIV_SHIFT;

sys/arch/arm/at91/at91pmc.c

85

if (reg & PMC_PLLBR_USB_96M) {

sys/arch/arm/at91/at91pmc.c

90

reg = PMCREG(PMC_MCKR);

sys/arch/arm/at91/at91pmc.c

91

switch ((reg & PMC_MCKR_CSS)) {

sys/arch/arm/at91/at91streg.h

71

#define STREG(reg) *((volatile uint32_t *)(AT91ST_BASE + (reg)))

sys/arch/arm/at91/at91twi.c

131

at91twi_readreg(struct at91twi_softc *sc, int reg)

sys/arch/arm/at91/at91twi.c

133

return bus_space_read_4(sc->sc_iot, sc->sc_ioh, reg);

sys/arch/arm/at91/at91twi.c

137

at91twi_writereg(struct at91twi_softc *sc, int reg, u_int val)

sys/arch/arm/at91/at91twi.c

139

bus_space_write_4(sc->sc_iot, sc->sc_ioh, reg, val);

sys/arch/arm/at91/at91usart.c

219

at91usart_writereg(struct at91usart_softc *sc, int reg, u_int val)

sys/arch/arm/at91/at91usart.c

221

bus_space_write_4(sc->sc_iot, sc->sc_ioh, reg, val);

sys/arch/arm/at91/at91usart.c

225

at91usart_readreg(struct at91usart_softc *sc, int reg)

sys/arch/arm/at91/at91usart.c

227

return bus_space_read_4(sc->sc_iot, sc->sc_ioh, reg);

sys/arch/arm/broadcom/bcm2835_aux.c

92

#define BCMAUX_READ(sc, reg) \

sys/arch/arm/broadcom/bcm2835_aux.c

93

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/broadcom/bcm2835_aux.c

94

#define BCMAUX_WRITE(sc, reg, val) \

sys/arch/arm/broadcom/bcm2835_aux.c

95

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/broadcom/bcm2835_cm.c

59

#define CM_WRITE(sc, reg, val) \

sys/arch/arm/broadcom/bcm2835_cm.c

60

bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))

sys/arch/arm/broadcom/bcm2835_cm.c

61

#define CM_READ(sc, reg) \

sys/arch/arm/broadcom/bcm2835_cm.c

62

bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg))

sys/arch/arm/broadcom/bcm2835_dmac.c

82

#define DMAC_READ(sc, reg) \

sys/arch/arm/broadcom/bcm2835_dmac.c

83

bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg))

sys/arch/arm/broadcom/bcm2835_dmac.c

84

#define DMAC_WRITE(sc, reg, val) \

sys/arch/arm/broadcom/bcm2835_dmac.c

85

bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))

sys/arch/arm/broadcom/bcm2835_gpio.c

268

uint32_t reg;

sys/arch/arm/broadcom/bcm2835_gpio.c

288

reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, BCM2838_GPIO_GPPUPPDN(3));

sys/arch/arm/broadcom/bcm2835_gpio.c

289

sc->sc_is2835 = reg == 0x6770696f;

sys/arch/arm/broadcom/bcm2835_gpio.c

756

bus_size_t reg;

sys/arch/arm/broadcom/bcm2835_gpio.c

759

reg = BCM2835_GPIO_GPSET(pin / BCM2835_GPIO_GPSET_PINS_PER_REGISTER);

sys/arch/arm/broadcom/bcm2835_gpio.c

761

reg = BCM2835_GPIO_GPCLR(pin / BCM2835_GPIO_GPCLR_PINS_PER_REGISTER);

sys/arch/arm/broadcom/bcm2835_gpio.c

764

bus_space_write_4(sc->sc_iot, sc->sc_ioh, reg,

sys/arch/arm/broadcom/bcm2835_gpio.c

821

uint32_t reg;

sys/arch/arm/broadcom/bcm2835_gpio.c

853

reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh,

sys/arch/arm/broadcom/bcm2835_gpio.c

855

reg &= ~mask;

sys/arch/arm/broadcom/bcm2835_gpio.c

856

reg |= __SHIFTIN(pud, mask);

sys/arch/arm/broadcom/bcm2835_gpio.c

858

BCM2838_GPIO_GPPUPPDN(regid), reg);

sys/arch/arm/broadcom/bcm2835_pwm.c

79

#define PWM_WRITE(sc, reg, val) \

sys/arch/arm/broadcom/bcm2835_pwm.c

80

bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))

sys/arch/arm/broadcom/bcm2835_pwm.c

81

#define PWM_READ(sc, reg) \

sys/arch/arm/broadcom/bcm2835_pwm.c

82

bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg))

sys/arch/arm/broadcom/bcm2835_sdhost.c

172

#define SDHOST_WRITE(sc, reg, val) \

sys/arch/arm/broadcom/bcm2835_sdhost.c

173

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/broadcom/bcm2835_sdhost.c

174

#define SDHOST_READ(sc, reg) \

sys/arch/arm/broadcom/bcm2835_sdhost.c

175

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/broadcom/bcm2838_pcie.c

595

uint32_t idx, reg;

sys/arch/arm/broadcom/bcm2838_pcie.c

610

reg = bus > 0 ? PCIE_EXT_CFG_DATA + offset : offset;

sys/arch/arm/broadcom/bcm2838_pcie.c

614

data = STBREAD(sc, reg);

sys/arch/arm/broadcom/bcm2838_pcie.c

625

uint32_t idx, reg;

sys/arch/arm/broadcom/bcm2838_pcie.c

639

reg = bus > 0 ? PCIE_EXT_CFG_DATA + offset : offset;

sys/arch/arm/broadcom/bcm2838_pcie.c

643

STBWRITE(sc, reg, data);

sys/arch/arm/broadcom/bcm53xx_mdio.c

134

bcmmdio_mii_readreg(device_t self, int phy, int reg)

sys/arch/arm/broadcom/bcm53xx_mdio.c

142

bcmmdio_write_4(sc, MIICMD, MIICMD_RD(phy, reg));

sys/arch/arm/broadcom/bcm53xx_mdio.c

152

bcmmdio_mii_writereg(device_t self, int phy, int reg, int val)

sys/arch/arm/broadcom/bcm53xx_mdio.c

162

bcmmdio_write_4(sc, MIICMD, MIICMD_WR(phy, reg, val));

sys/arch/arm/broadcom/bcm53xx_pax.c

413

uint32_t reg = __SHIFTOUT(tag, CFG_ADDR_REG);

sys/arch/arm/broadcom/bcm53xx_pax.c

417

| __SHIFTIN(reg, CFG_IND_ADDR_REG));

sys/arch/arm/broadcom/bcm53xx_pax.c

430

bcmpax_conf_read(void *v, pcitag_t tag, int reg)

sys/arch/arm/broadcom/bcm53xx_pax.c

434

if ((unsigned int)reg >= PCI_CONF_SIZE)

sys/arch/arm/broadcom/bcm53xx_pax.c

443

&& reg == PCI_CLASS_REG) {

sys/arch/arm/broadcom/bcm53xx_pax.c

451

bus_size_t data_reg = bcmpax_conf_addr_write(sc, tag | reg);

sys/arch/arm/broadcom/bcm53xx_pax.c

469

bcmpax_conf_write(void *v, pcitag_t tag, int reg, pcireg_t val)

sys/arch/arm/broadcom/bcm53xx_pax.c

473

if ((unsigned int)reg >= PCI_CONF_SIZE)

sys/arch/arm/broadcom/bcm53xx_pax.c

477

bus_size_t data_reg = bcmpax_conf_addr_write(sc, tag | reg);

sys/arch/arm/cortex/gicv3.c

101

bus_space_write_8(sc->sc_bst, sc->sc_bsh_d, reg, val);

sys/arch/arm/cortex/gicv3.c

105

gicr_read_4(struct gicv3_softc *sc, u_int index, bus_size_t reg)

sys/arch/arm/cortex/gicv3.c

108

return bus_space_read_4(sc->sc_bst, sc->sc_bsh_r[index], reg);

sys/arch/arm/cortex/gicv3.c

112

gicr_write_4(struct gicv3_softc *sc, u_int index, bus_size_t reg, uint32_t val)

sys/arch/arm/cortex/gicv3.c

115

bus_space_write_4(sc->sc_bst, sc->sc_bsh_r[index], reg, val);

sys/arch/arm/cortex/gicv3.c

119

gicr_read_8(struct gicv3_softc *sc, u_int index, bus_size_t reg)

sys/arch/arm/cortex/gicv3.c

122

return bus_space_read_8(sc->sc_bst, sc->sc_bsh_r[index], reg);

sys/arch/arm/cortex/gicv3.c

126

gicr_write_8(struct gicv3_softc *sc, u_int index, bus_size_t reg, uint64_t val)

sys/arch/arm/cortex/gicv3.c

129

bus_space_write_8(sc->sc_bst, sc->sc_bsh_r[index], reg, val);

sys/arch/arm/cortex/gicv3.c

79

gicd_read_4(struct gicv3_softc *sc, bus_size_t reg)

sys/arch/arm/cortex/gicv3.c

81

return bus_space_read_4(sc->sc_bst, sc->sc_bsh_d, reg);

sys/arch/arm/cortex/gicv3.c

85

gicd_write_4(struct gicv3_softc *sc, bus_size_t reg, uint32_t val)

sys/arch/arm/cortex/gicv3.c

87

bus_space_write_4(sc->sc_bst, sc->sc_bsh_d, reg, val);

sys/arch/arm/cortex/gicv3.c

92

gicd_read_8(struct gicv3_softc *sc, bus_size_t reg)

sys/arch/arm/cortex/gicv3.c

94

return bus_space_read_8(sc->sc_bst, sc->sc_bsh_d, reg);

sys/arch/arm/cortex/gicv3.c

99

gicd_write_8(struct gicv3_softc *sc, bus_size_t reg, uint64_t val)

sys/arch/arm/cortex/gicv3_its.c

101

return bus_space_read_4(its->its_bst, its->its_bsh, reg);

sys/arch/arm/cortex/gicv3_its.c

105

gits_write_4(struct gicv3_its *its, bus_size_t reg, uint32_t val)

sys/arch/arm/cortex/gicv3_its.c

107

bus_space_write_4(its->its_bst, its->its_bsh, reg, val);

sys/arch/arm/cortex/gicv3_its.c

111

gits_read_8(struct gicv3_its *its, bus_size_t reg)

sys/arch/arm/cortex/gicv3_its.c

113

return bus_space_read_8(its->its_bst, its->its_bsh, reg);

sys/arch/arm/cortex/gicv3_its.c

117

gits_write_8(struct gicv3_its *its, bus_size_t reg, uint64_t val)

sys/arch/arm/cortex/gicv3_its.c

119

bus_space_write_8(its->its_bst, its->its_bsh, reg, val);

sys/arch/arm/cortex/gicv3_its.c

99

gits_read_4(struct gicv3_its *its, bus_size_t reg)

sys/arch/arm/ep93xx/ep93xx_intr.c

72

#define VIC1REG(reg) *((volatile uint32_t*) (EP93XX_AHB_VBASE + \

sys/arch/arm/ep93xx/ep93xx_intr.c

73

EP93XX_AHB_VIC1 + (reg)))

sys/arch/arm/ep93xx/ep93xx_intr.c

74

#define VIC2REG(reg) *((volatile uint32_t*) (EP93XX_AHB_VBASE + \

sys/arch/arm/ep93xx/ep93xx_intr.c

75

EP93XX_AHB_VIC2 + (reg)))

sys/arch/arm/ep93xx/epcom.c

777

int reg;

sys/arch/arm/ep93xx/epcom.c

782

reg = 0xffff;

sys/arch/arm/ep93xx/epcom.c

789

reg =

sys/arch/arm/ep93xx/epcom.c

797

reg);

sys/arch/arm/ep93xx/epe.c

435

epe_mii_readreg(device_t self, int phy, int reg, uint16_t *val)

sys/arch/arm/ep93xx/epe.c

441

EPE_WRITE(MIICmd, (MIICmd_READ | (phy << 5) | reg));

sys/arch/arm/ep93xx/epe.c

450

epe_mii_writereg(device_t self, int phy, int reg, uint16_t val)

sys/arch/arm/ep93xx/epe.c

457

EPE_WRITE(MIICmd, (MIICmd_WRITE | (phy << 5) | reg));

sys/arch/arm/ep93xx/epe.c

469

uint32_t reg;

sys/arch/arm/ep93xx/epe.c

475

reg = EPE_READ(TestCtl);

sys/arch/arm/ep93xx/epe.c

477

reg |= TestCtl_MFDX;

sys/arch/arm/ep93xx/epe.c

479

reg &= ~TestCtl_MFDX;

sys/arch/arm/ep93xx/epe.c

480

EPE_WRITE(TestCtl, reg);

sys/arch/arm/ep93xx/epgpio.c

648

epgpio_bit_set(struct epgpio_softc *sc, bus_size_t reg, int bit)

sys/arch/arm/ep93xx/epgpio.c

650

int t = bus_space_read_4(sc->sc_iot, sc->sc_ioh, reg) & 0xff;

sys/arch/arm/ep93xx/epgpio.c

651

bus_space_write_4(sc->sc_iot, sc->sc_ioh, reg, t | (1 << bit));

sys/arch/arm/ep93xx/epgpio.c

655

epgpio_bit_clear(struct epgpio_softc *sc, bus_size_t reg, int bit)

sys/arch/arm/ep93xx/epgpio.c

657

int t = bus_space_read_4(sc->sc_iot, sc->sc_ioh, reg) & 0xff;

sys/arch/arm/ep93xx/epgpio.c

658

bus_space_write_4(sc->sc_iot, sc->sc_ioh, reg, t & ~(1 << bit));

sys/arch/arm/ep93xx/eppcic.c

153

int reg;

sys/arch/arm/ep93xx/eppcic.c

188

ph->ph_space[IO].reg = EP93XX_PCMCIA0_IO;

sys/arch/arm/ep93xx/eppcic.c

191

ph->ph_space[COMMON].reg = EP93XX_PCMCIA0_Common;

sys/arch/arm/ep93xx/eppcic.c

195

ph->ph_space[ATTRIBUTE].reg = EP93XX_PCMCIA0_Attribute;

sys/arch/arm/ep93xx/eppcic.c

201

reg = EP93XX_PCMCIA_WEN | (pcic->socket_type)(sc, 0);

sys/arch/arm/ep93xx/eppcic.c

203

EP93XX_PCMCIA_RST | reg);

sys/arch/arm/ep93xx/eppcic.c

205

bus_space_write_4(sc->sc_iot, sc->sc_ioh, EP93XX_PCMCIA_Ctrl, reg);

sys/arch/arm/ep93xx/eppcic.c

671

bus_space_write_4(sc->sc_iot, sc->sc_ioh, ph->ph_space[kind].reg,

sys/arch/arm/ep93xx/eppcic.c

95

bus_size_t reg;

sys/arch/arm/fdt/pcihost_fdt.c

418

u_int reg;

sys/arch/arm/fdt/pcihost_fdt.c

428

reg = (b << 16) | (d << 11) | (f << 8) | offset;

sys/arch/arm/fdt/pcihost_fdt.c

432

reg = (b << 20) | (d << 15) | (f << 12) | offset;

sys/arch/arm/fdt/pcihost_fdt.c

437

return bus_space_read_4(sc->sc_bst, sc->sc_bsh, reg);

sys/arch/arm/fdt/pcihost_fdt.c

445

u_int reg;

sys/arch/arm/fdt/pcihost_fdt.c

455

reg = (b << 16) | (d << 11) | (f << 8) | offset;

sys/arch/arm/fdt/pcihost_fdt.c

459

reg = (b << 20) | (d << 15) | (f << 12) | offset;

sys/arch/arm/fdt/pcihost_fdt.c

464

bus_space_write_4(sc->sc_bst, sc->sc_bsh, reg, val);

sys/arch/arm/fdt/plfb_fdt.c

107

#define FB_READ(sc, reg) \

sys/arch/arm/fdt/plfb_fdt.c

108

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/fdt/plfb_fdt.c

109

#define FB_WRITE(sc, reg, val) \

sys/arch/arm/fdt/plfb_fdt.c

110

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/footbridge/footbridge_pci.c

174

footbridge_pci_conf_read(void *pcv, pcitag_t tag, int reg)

sys/arch/arm/footbridge/footbridge_pci.c

180

if ((unsigned int)reg >= PCI_CONF_SIZE)

sys/arch/arm/footbridge/footbridge_pci.c

191

address |= (function << 8) | reg;

sys/arch/arm/footbridge/footbridge_pci.c

196

pcv, (uint32_t)tag, reg, data);

sys/arch/arm/footbridge/footbridge_pci.c

202

footbridge_pci_conf_write(void *pcv, pcitag_t tag, int reg, pcireg_t data)

sys/arch/arm/footbridge/footbridge_pci.c

207

if ((unsigned int)reg >= PCI_CONF_SIZE)

sys/arch/arm/footbridge/footbridge_pci.c

217

address |= (function << 8) | reg;

sys/arch/arm/footbridge/footbridge_pci.c

221

pcv, (uint32_t)tag, reg, data);

sys/arch/arm/gemini/gemini_gmac.c

392

geminigmac_mii_readreg(device_t dv, int phy, int reg, uint16_t *val)

sys/arch/arm/gemini/gemini_gmac.c

400

reg, val);

sys/arch/arm/gemini/gemini_gmac.c

409

geminigmac_mii_writereg(device_t dv, int phy, int reg, uint16_t val)

sys/arch/arm/gemini/gemini_gmac.c

418

reg, val);

sys/arch/arm/gemini/gemini_gpio.c

105

#define GPIO_READ(gpio, reg) \

sys/arch/arm/gemini/gemini_gpio.c

106

bus_space_read_4((gpio)->gpio_memt, (gpio)->gpio_memh, (reg))

sys/arch/arm/gemini/gemini_gpio.c

107

#define GPIO_WRITE(gpio, reg, val) \

sys/arch/arm/gemini/gemini_gpio.c

108

bus_space_write_4((gpio)->gpio_memt, (gpio)->gpio_memh, (reg), (val))

sys/arch/arm/imx/if_enet.c

1051

enet_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val)

sys/arch/arm/imx/if_enet.c

1065

ENET_MMFR_PHY_REG(reg) | ENET_MMFR_PHY_ADDR(phy));

sys/arch/arm/imx/if_enet.c

1075

reg);

sys/arch/arm/imx/if_enet.c

1084

enet_miibus_writereg(device_t dev, int phy, int reg, uint16_t val)

sys/arch/arm/imx/if_enet.c

1097

ENET_MMFR_PHY_REG(reg) | ENET_MMFR_PHY_ADDR(phy) |

sys/arch/arm/imx/if_enet.c

1106

DEVICE_DPRINTF("MII write timeout: reg=0x%02x\n", reg);

sys/arch/arm/imx/if_enet.c

124

#define ENET_REG_READ(sc, reg) \

sys/arch/arm/imx/if_enet.c

125

bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, reg)

sys/arch/arm/imx/if_enet.c

127

#define ENET_REG_WRITE(sc, reg, value) \

sys/arch/arm/imx/if_enet.c

128

bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, reg, value)

sys/arch/arm/imx/if_enetreg.h

93

# define ENET_MMFR_PHY_REG(reg) __SHIFTIN(reg, __BITS(22, 18))

sys/arch/arm/imx/imx23_apbdma.c

328

uint32_t reg;

sys/arch/arm/imx/imx23_apbdma.c

346

reg =

sys/arch/arm/imx/imx23_apbdma.c

349

reg =

sys/arch/arm/imx/imx23_apbdma.c

351

DMA_WR(sc, reg, chan->chan_ds[0].ds_addr);

sys/arch/arm/imx/imx23_apbdma.c

355

reg = HW_APB_CHN_SEMA(HW_APBH_CH0_SEMA, chan->chan_index);

sys/arch/arm/imx/imx23_apbdma.c

358

reg = HW_APB_CHN_SEMA(HW_APBX_CH0_SEMA, chan->chan_index);

sys/arch/arm/imx/imx23_apbdma.c

361

DMA_WR(sc, reg, val);

sys/arch/arm/imx/imx23_apbdma.c

90

#define DMA_RD(sc, reg) \

sys/arch/arm/imx/imx23_apbdma.c

91

bus_space_read_4(sc->sc_iot, sc->sc_ioh, (reg))

sys/arch/arm/imx/imx23_apbdma.c

92

#define DMA_WR(sc, reg, val) \

sys/arch/arm/imx/imx23_apbdma.c

93

bus_space_write_4(sc->sc_iot, sc->sc_ioh, (reg), (val))

sys/arch/arm/imx/imx23_clkctrl.c

56

#define CLKCTRL_RD(sc, reg) \

sys/arch/arm/imx/imx23_clkctrl.c

57

bus_space_read_4(sc->sc_iot, sc->sc_hdl, (reg))

sys/arch/arm/imx/imx23_clkctrl.c

58

#define CLKCTRL_WR(sc, reg, val) \

sys/arch/arm/imx/imx23_clkctrl.c

59

bus_space_write_4(sc->sc_iot, sc->sc_hdl, (reg), (val))

sys/arch/arm/imx/imx23_digctl.c

66

#define DCTL_RD(sc, reg) \

sys/arch/arm/imx/imx23_digctl.c

67

bus_space_read_4(sc->sc_iot, sc->sc_hdl, (reg))

sys/arch/arm/imx/imx23_digctl.c

68

#define DCTL_WR(sc, reg, val) \

sys/arch/arm/imx/imx23_digctl.c

69

bus_space_write_4(sc->sc_iot, sc->sc_hdl, (reg), (val))

sys/arch/arm/imx/imx23_digfilt.c

115

#define AO_RD(sc, reg) \

sys/arch/arm/imx/imx23_digfilt.c

116

bus_space_read_4(sc->sc_iot, sc->sc_aohdl, (reg))

sys/arch/arm/imx/imx23_digfilt.c

117

#define AO_WR(sc, reg, val) \

sys/arch/arm/imx/imx23_digfilt.c

118

bus_space_write_4(sc->sc_iot, sc->sc_aohdl, (reg), (val))

sys/arch/arm/imx/imx23_icoll.c

55

#define ICOLL_READ(sc, reg) \

sys/arch/arm/imx/imx23_icoll.c

56

bus_space_read_4(sc->sc_iot, sc->sc_hdl, (reg))

sys/arch/arm/imx/imx23_icoll.c

57

#define ICOLL_WRITE(sc, reg, val) \

sys/arch/arm/imx/imx23_icoll.c

58

bus_space_write_4(sc->sc_iot, sc->sc_hdl, (reg), (val))

sys/arch/arm/imx/imx23_mmc.c

124

#define SSP_RD(sc, reg) \

sys/arch/arm/imx/imx23_mmc.c

125

bus_space_read_4(sc->sc_iot, sc->sc_hdl, (reg))

sys/arch/arm/imx/imx23_mmc.c

126

#define SSP_WR(sc, reg, val) \

sys/arch/arm/imx/imx23_mmc.c

127

bus_space_write_4(sc->sc_iot, sc->sc_hdl, (reg), (val))

sys/arch/arm/imx/imx23_mmc.c

508

uint32_t reg;

sys/arch/arm/imx/imx23_mmc.c

510

reg = SSP_RD(sc, HW_SSP_CTRL0);

sys/arch/arm/imx/imx23_mmc.c

511

reg |= HW_SSP_CTRL0_ENABLE;

sys/arch/arm/imx/imx23_mmc.c

514

reg &= ~(HW_SSP_CTRL0_BUS_WIDTH);

sys/arch/arm/imx/imx23_mmc.c

515

reg |= __SHIFTIN(BUS_WIDTH_1_BIT, HW_SSP_CTRL0_BUS_WIDTH) |

sys/arch/arm/imx/imx23_mmc.c

517

SSP_WR(sc, HW_SSP_CTRL0, reg);

sys/arch/arm/imx/imx23_mmc.c

521

reg = SSP_RD(sc, HW_SSP_TIMING);

sys/arch/arm/imx/imx23_mmc.c

522

reg &= ~(HW_SSP_TIMING_TIMEOUT);

sys/arch/arm/imx/imx23_mmc.c

523

reg |= __SHIFTIN(DATA_TIMEOUT, HW_SSP_TIMING_TIMEOUT);

sys/arch/arm/imx/imx23_mmc.c

524

SSP_WR(sc, HW_SSP_TIMING, reg);

sys/arch/arm/imx/imx23_mmc.c

529

reg = SSP_RD(sc, HW_SSP_CTRL1);

sys/arch/arm/imx/imx23_mmc.c

531

reg |= HW_SSP_CTRL1_RESP_ERR_IRQ_EN |

sys/arch/arm/imx/imx23_mmc.c

538

reg |= HW_SSP_CTRL1_DMA_ENABLE;

sys/arch/arm/imx/imx23_mmc.c

539

reg |= HW_SSP_CTRL1_POLARITY;

sys/arch/arm/imx/imx23_mmc.c

541

reg &= ~(HW_SSP_CTRL1_WORD_LENGTH | HW_SSP_CTRL1_SSP_MODE);

sys/arch/arm/imx/imx23_mmc.c

542

reg |= __SHIFTIN(0x7, HW_SSP_CTRL1_WORD_LENGTH) |

sys/arch/arm/imx/imx23_mmc.c

544

SSP_WR(sc, HW_SSP_CTRL1, reg);

sys/arch/arm/imx/imx23_mmc.c

559

uint32_t newclk, found, reg;

sys/arch/arm/imx/imx23_mmc.c

581

reg = SSP_RD(sc, HW_SSP_TIMING);

sys/arch/arm/imx/imx23_mmc.c

582

reg &= ~(HW_SSP_TIMING_CLOCK_DIVIDE | HW_SSP_TIMING_CLOCK_RATE);

sys/arch/arm/imx/imx23_mmc.c

583

reg |= __SHIFTIN(div, HW_SSP_TIMING_CLOCK_DIVIDE) |

sys/arch/arm/imx/imx23_mmc.c

585

SSP_WR(sc, HW_SSP_TIMING, reg);

sys/arch/arm/imx/imx23_pinctrl.c

304

#define PINCTRL_RD(sc, reg) \

sys/arch/arm/imx/imx23_pinctrl.c

305

bus_space_read_4(sc->sc_iot, sc->sc_hdl, (reg))

sys/arch/arm/imx/imx23_pinctrl.c

306

#define PINCTRL_WR(sc, reg, val) \

sys/arch/arm/imx/imx23_pinctrl.c

307

bus_space_write_4(sc->sc_iot, sc->sc_hdl, (reg), (val))

sys/arch/arm/imx/imx23_platform.c

55

#define REG_RD(reg) *(volatile uint32_t *)(reg)

sys/arch/arm/imx/imx23_platform.c

56

#define REG_WR(reg, val) \

sys/arch/arm/imx/imx23_platform.c

58

*(volatile uint32_t *)((reg)) = val; \

sys/arch/arm/imx/imx23_rtc.c

63

#define RTC_RD(sc, reg) \

sys/arch/arm/imx/imx23_rtc.c

64

bus_space_read_4(sc->sc_iot, sc->sc_hdl, (reg))

sys/arch/arm/imx/imx23_rtc.c

65

#define RTC_WR(sc, reg, val) \

sys/arch/arm/imx/imx23_rtc.c

66

bus_space_write_4(sc->sc_iot, sc->sc_hdl, (reg), (val))

sys/arch/arm/imx/imx23_timrot.c

79

#define TIMROT_READ(sc, reg) \

sys/arch/arm/imx/imx23_timrot.c

80

bus_space_read_4(sc->sc_iot, sc->sc_hdl, (reg))

sys/arch/arm/imx/imx23_timrot.c

81

#define TIMROT_WRITE(sc, reg, val) \

sys/arch/arm/imx/imx23_timrot.c

82

bus_space_write_4(sc->sc_iot, sc->sc_hdl, (reg), (val))

sys/arch/arm/imx/imx23_timrot.c

84

#define TIMER_WRITE(sc, reg, val) \

sys/arch/arm/imx/imx23_timrot.c

85

bus_space_write_4(sc->sc_iot, sc->sc_hdl, (reg), (val))

sys/arch/arm/imx/imx23_timrot.c

86

#define TIMER_WRITE_2(sc, reg, val) \

sys/arch/arm/imx/imx23_timrot.c

87

bus_space_write_2(sc->sc_iot, sc->sc_hdl, (reg), (val))

sys/arch/arm/imx/imx23_usbphy.c

59

#define PHY_RD(sc, reg) \

sys/arch/arm/imx/imx23_usbphy.c

60

bus_space_read_4(sc->sc_iot, sc->sc_hdl, (reg))

sys/arch/arm/imx/imx23_usbphy.c

61

#define PHY_WR(sc, reg, val) \

sys/arch/arm/imx/imx23_usbphy.c

62

bus_space_write_4(sc->sc_iot, sc->sc_hdl, (reg), (val))

sys/arch/arm/imx/imx31_gpio.c

91

#define GPIO_READ(gpio, reg) \

sys/arch/arm/imx/imx31_gpio.c

92

bus_space_read_4((gpio)->gpio_memt, (gpio)->gpio_memh, (reg))

sys/arch/arm/imx/imx31_gpio.c

93

#define GPIO_WRITE(gpio, reg, val) \

sys/arch/arm/imx/imx31_gpio.c

94

bus_space_write_4((gpio)->gpio_memt, (gpio)->gpio_memh, (reg), (val))

sys/arch/arm/imx/imx31_icu.c

76

#define INTC_READ(avic, reg) \

sys/arch/arm/imx/imx31_icu.c

77

bus_space_read_4((avic)->avic_memt, (avic)->avic_memh, (reg))

sys/arch/arm/imx/imx31_icu.c

78

#define INTC_WRITE(avic, reg, val) \

sys/arch/arm/imx/imx31_icu.c

79

bus_space_write_4((avic)->avic_memt, (avic)->avic_memh, (reg), (val))

sys/arch/arm/imx/imx51_ccm.c

584

uint32_t reg;

sys/arch/arm/imx/imx51_ccm.c

588

reg = bus_space_read_4(iot, ioh, CCMC_CCGR(group));

sys/arch/arm/imx/imx51_ccm.c

589

reg &= ~(0x03 << field * 2);

sys/arch/arm/imx/imx51_ccm.c

590

reg |= bit;

sys/arch/arm/imx/imx51_ccm.c

591

bus_space_write_4(iot, ioh, CCMC_CCGR(group), reg);

sys/arch/arm/imx/imx51_ccm.c

596

reg = bus_space_read_4(iot, ioh, CCMC_EPDC_AXI);

sys/arch/arm/imx/imx51_ccm.c

597

reg &= ~EPDC_AXI_CLKGATE;

sys/arch/arm/imx/imx51_ccm.c

598

reg |= EPDC_AXI_CLKGATE_ALWAYS;

sys/arch/arm/imx/imx51_ccm.c

599

bus_space_write_4(iot, ioh, CCMC_EPDC_AXI, reg);

sys/arch/arm/imx/imx51_ccm.c

602

reg |= EPDC_ASM_EN;

sys/arch/arm/imx/imx51_ccm.c

603

reg |= __SHIFTIN(5, EPDC_ASM_SLOW_DIV);

sys/arch/arm/imx/imx51_ccm.c

604

bus_space_write_4(iot, ioh, CCMC_EPDC_AXI, reg);

sys/arch/arm/imx/imx51_ccm.c

608

reg = bus_space_read_4(iot, ioh, CCMC_EPDC_PIX);

sys/arch/arm/imx/imx51_ccm.c

609

reg &= ~EPDC_PIX_CLKGATE;

sys/arch/arm/imx/imx51_ccm.c

610

reg |= EPDC_PIX_CLKGATE_ALWAYS;

sys/arch/arm/imx/imx51_ccm.c

611

bus_space_write_4(iot, ioh, CCMC_EPDC_PIX, reg);

sys/arch/arm/imx/imx51_ccm.c

624

uint32_t reg;

sys/arch/arm/imx/imx51_ccm.c

630

reg = bus_space_read_4(iot, ioh, CCMC_CLKSEQ_BYPASS);

sys/arch/arm/imx/imx51_ccm.c

631

reg &= ~CLKSEQ_EPDC_AXI_CLK;

sys/arch/arm/imx/imx51_ccm.c

632

reg |= __SHIFTIN(clk_base, CLKSEQ_EPDC_AXI_CLK);

sys/arch/arm/imx/imx51_ccm.c

633

bus_space_write_4(iot, ioh, CCMC_CLKSEQ_BYPASS, reg);

sys/arch/arm/imx/imx51_ccm.c

649

reg = bus_space_read_4(iot, ioh, CCMC_EPDC_AXI);

sys/arch/arm/imx/imx51_ccm.c

650

reg &= ~EPDC_AXI_DIV;

sys/arch/arm/imx/imx51_ccm.c

651

reg |= __SHIFTIN(div, EPDC_AXI_DIV);

sys/arch/arm/imx/imx51_ccm.c

652

bus_space_write_4(iot, ioh, CCMC_EPDC_AXI, reg);

sys/arch/arm/imx/imx51_ccm.c

657

reg = bus_space_read_4(iot, ioh, CCMC_CLKSEQ_BYPASS);

sys/arch/arm/imx/imx51_ccm.c

658

reg &= ~CLKSEQ_EPDC_PIX_CLK;

sys/arch/arm/imx/imx51_ccm.c

659

reg |= __SHIFTIN(clk_base, CLKSEQ_EPDC_PIX_CLK);

sys/arch/arm/imx/imx51_ccm.c

660

bus_space_write_4(iot, ioh, CCMC_CLKSEQ_BYPASS, reg);

sys/arch/arm/imx/imx51_ccm.c

679

reg = bus_space_read_4(iot, ioh, CCMC_EPDC_PIX);

sys/arch/arm/imx/imx51_ccm.c

680

reg &= ~EPDC_PIX_CLK_PRED;

sys/arch/arm/imx/imx51_ccm.c

681

reg |= __SHIFTIN(div, EPDC_PIX_CLK_PRED);

sys/arch/arm/imx/imx51_ccm.c

682

bus_space_write_4(iot, ioh, CCMC_EPDC_PIX, reg);

sys/arch/arm/imx/imx51_iomux.c

58

#define IOMUX_READ(iomux, reg) \

sys/arch/arm/imx/imx51_iomux.c

59

bus_space_read_4((iomux)->iomux_memt, (iomux)->iomux_memh, (reg))

sys/arch/arm/imx/imx51_iomux.c

60

#define IOMUX_WRITE(iomux, reg, val) \

sys/arch/arm/imx/imx51_iomux.c

61

bus_space_write_4((iomux)->iomux_memt, (iomux)->iomux_memh, (reg), (val))

sys/arch/arm/imx/imx51_ipuv3.c

125

uint32_t reg = 0;

sys/arch/arm/imx/imx51_ipuv3.c

130

reg = IPUV3_READ(sc, cm, IPU_CM_CONF);

sys/arch/arm/imx/imx51_ipuv3.c

131

reg |= CM_CONF_DP_EN |

sys/arch/arm/imx/imx51_ipuv3.c

135

IPUV3_WRITE(sc, cm, IPU_CM_CONF, reg);

sys/arch/arm/imx/imx51_ipuv3.c

177

uint32_t reg;

sys/arch/arm/imx/imx51_ipuv3.c

181

reg = IPUV3_READ(sc, dc, addr);

sys/arch/arm/imx/imx51_ipuv3.c

182

reg &= ~(0xFFFF << (16 * (map & 0x1)));

sys/arch/arm/imx/imx51_ipuv3.c

183

IPUV3_WRITE(sc, dc, addr, reg);

sys/arch/arm/imx/imx51_ipuv3.c

192

uint32_t reg;

sys/arch/arm/imx/imx51_ipuv3.c

196

reg = IPUV3_READ(sc, dc, addr);

sys/arch/arm/imx/imx51_ipuv3.c

197

reg &= ~(0xFFFF << (16 * ((map * 3 + byte) & 0x1)));

sys/arch/arm/imx/imx51_ipuv3.c

198

reg |= ((offset << 8) | mask) << (16 * ((map * 3 + byte) & 0x1));

sys/arch/arm/imx/imx51_ipuv3.c

199

IPUV3_WRITE(sc, dc, addr, reg);

sys/arch/arm/imx/imx51_ipuv3.c

201

printf("%s: addr 0x%08X reg 0x%08X\n", __func__, addr, reg);

sys/arch/arm/imx/imx51_ipuv3.c

205

reg = IPUV3_READ(sc, dc, addr);

sys/arch/arm/imx/imx51_ipuv3.c

206

reg &= ~(0x1F << ((16 * (map & 0x1)) + (5 * byte)));

sys/arch/arm/imx/imx51_ipuv3.c

207

reg |= ((map * 3) + byte) << ((16 * (map & 0x1)) + (5 * byte));

sys/arch/arm/imx/imx51_ipuv3.c

208

IPUV3_WRITE(sc, dc, addr, reg);

sys/arch/arm/imx/imx51_ipuv3.c

210

printf("%s: addr 0x%08X reg 0x%08X\n", __func__, addr, reg);

sys/arch/arm/imx/imx51_ipuv3.c

221

uint32_t reg;

sys/arch/arm/imx/imx51_ipuv3.c

223

reg = (sync << 0) |

sys/arch/arm/imx/imx51_ipuv3.c

228

IPUV3_WRITE(sc, dctmpl, index * 8, reg);

sys/arch/arm/imx/imx51_ipuv3.c

230

printf("%s: addr 0x%08X reg 0x%08X\n", __func__, index * 8, reg);

sys/arch/arm/imx/imx51_ipuv3.c

232

reg = (opecode << 0) |

sys/arch/arm/imx/imx51_ipuv3.c

234

IPUV3_WRITE(sc, dctmpl, index * 8 + 4, reg);

sys/arch/arm/imx/imx51_ipuv3.c

236

printf("%s: addr 0x%08X reg 0x%08X\n", __func__, index * 8 + 4, reg);

sys/arch/arm/imx/imx51_ipuv3.c

246

uint32_t reg;

sys/arch/arm/imx/imx51_ipuv3.c

248

reg = IPUV3_READ(sc, dc, IPU_DC_RL(base, evt));

sys/arch/arm/imx/imx51_ipuv3.c

249

reg &= ~(0xFFFF << (16 * (evt & 0x1)));

sys/arch/arm/imx/imx51_ipuv3.c

250

reg |= ((addr << 8) | pri) << (16 * (evt & 0x1));

sys/arch/arm/imx/imx51_ipuv3.c

251

IPUV3_WRITE(sc, dc, IPU_DC_RL(base, evt), reg);

sys/arch/arm/imx/imx51_ipuv3.c

256

(void *)IPU_DC_RL(base, evt), reg);

sys/arch/arm/imx/imx51_ipuv3.c

263

uint32_t reg;

sys/arch/arm/imx/imx51_ipuv3.c

296

reg = (4 << 5) | 0x2;

sys/arch/arm/imx/imx51_ipuv3.c

297

IPUV3_WRITE(sc, dc, IPU_DC_WR_CH_CONF_5, reg);

sys/arch/arm/imx/imx51_ipuv3.c

337

uint32_t reg;

sys/arch/arm/imx/imx51_ipuv3.c

341

reg = IPUV3_READ(sc, di0, IPU_DI_STP_REP(no));

sys/arch/arm/imx/imx51_ipuv3.c

342

reg &= ~DI_STP_REP(no);

sys/arch/arm/imx/imx51_ipuv3.c

343

reg |= __SHIFTIN(repeat, DI_STP_REP(no));

sys/arch/arm/imx/imx51_ipuv3.c

344

IPUV3_WRITE(sc, di0, IPU_DI_STP_REP(no), reg);

sys/arch/arm/imx/imx51_ipuv3.c

353

IPU_DI_STP_REP(no), reg);

sys/arch/arm/imx/imx51_ipuv3.c

362

uint32_t reg;

sys/arch/arm/imx/imx51_ipuv3.c

379

reg = IPUV3_READ(sc, cm, IPU_CM_DISP_GEN);

sys/arch/arm/imx/imx51_ipuv3.c

380

reg &= ~(CM_DISP_GEN_DI1_COUNTER_RELEASE |

sys/arch/arm/imx/imx51_ipuv3.c

382

IPUV3_WRITE(sc, cm, IPU_CM_DISP_GEN, reg);

sys/arch/arm/imx/imx51_ipuv3.c

394

reg = __SHIFTIN(div / 16 - 1, DI_DW_GEN_ACCESS_SIZE) |

sys/arch/arm/imx/imx51_ipuv3.c

397

IPUV3_WRITE(sc, di0, IPU_DI_DW_GEN(0), reg);

sys/arch/arm/imx/imx51_ipuv3.c

401

IPU_DI_DW_GEN(0), reg);

sys/arch/arm/imx/imx51_ipuv3.c

405

reg = __SHIFTIN(div / 16 * 2, DI_DW_SET_DOWN);

sys/arch/arm/imx/imx51_ipuv3.c

406

IPUV3_WRITE(sc, di0, IPU_DI_DW_SET(0, 3), reg);

sys/arch/arm/imx/imx51_ipuv3.c

409

IPU_DI_DW_SET(0, 3), reg);

sys/arch/arm/imx/imx51_ipuv3.c

458

reg = IPUV3_READ(sc, di0, IPU_DI_STP_REP(6));

sys/arch/arm/imx/imx51_ipuv3.c

459

reg &= ~DI_STP_REP(6);

sys/arch/arm/imx/imx51_ipuv3.c

460

IPUV3_WRITE(sc, di0, IPU_DI_STP_REP(6), reg);

sys/arch/arm/imx/imx51_ipuv3.c

465

reg = __SHIFTIN(3 - 1, DI_SYNC_AS_GEN_VSYNC_SEL) |

sys/arch/arm/imx/imx51_ipuv3.c

467

IPUV3_WRITE(sc, di0, IPU_DI_SYNC_AS_GEN, reg);

sys/arch/arm/imx/imx51_ipuv3.c

471

reg = IPUV3_READ(sc, cm, IPU_CM_DISP_GEN);

sys/arch/arm/imx/imx51_ipuv3.c

472

reg |= CM_DISP_GEN_DI0_COUNTER_RELEASE;

sys/arch/arm/imx/imx51_ipuv3.c

473

IPUV3_WRITE(sc, cm, IPU_CM_DISP_GEN, reg);

sys/arch/arm/imx/imx51_ipuv3.c

528

uint32_t reg;

sys/arch/arm/imx/imx51_ipuv3.c

54

#define IPUV3_READ(ipuv3, module, reg) \

sys/arch/arm/imx/imx51_ipuv3.c

548

reg = IPUV3_READ(sc, cm, IPU_CM_DISP_GEN);

sys/arch/arm/imx/imx51_ipuv3.c

549

reg |= CM_DISP_GEN_MCU_MAX_BURST_STOP |

sys/arch/arm/imx/imx51_ipuv3.c

55

bus_space_read_4((ipuv3)->iot, (ipuv3)->module##_ioh, (reg))

sys/arch/arm/imx/imx51_ipuv3.c

551

IPUV3_WRITE(sc, cm, IPU_CM_DISP_GEN, reg);

sys/arch/arm/imx/imx51_ipuv3.c

56

#define IPUV3_WRITE(ipuv3, module, reg, val) \

sys/arch/arm/imx/imx51_ipuv3.c

57

bus_space_write_4((ipuv3)->iot, (ipuv3)->module##_ioh, (reg), (val))

sys/arch/arm/imx/imx51_ipuv3.c

80

#define __DUMP(grp, reg) \

sys/arch/arm/imx/imx51_ipuv3.c

81

DPRINTFN(4, ("%-16s = 0x%08X\n", #reg, IPUV3_READ(sc, grp, IPU_##reg)))

sys/arch/arm/imx/imx51_ipuv3.c

831

uint32_t reg;

sys/arch/arm/imx/imx51_ipuv3.c

835

reg = IPUV3_READ(sc, idmac, IPU_IDMAC_CH_EN_1);

sys/arch/arm/imx/imx51_ipuv3.c

836

reg &= ~__BIT(CH_PANNEL_BG);

sys/arch/arm/imx/imx51_ipuv3.c

837

IPUV3_WRITE(sc, idmac, IPU_IDMAC_CH_EN_1, reg);

sys/arch/arm/imx/imx51_ipuv3.c

851

reg = IPUV3_READ(sc, cm, IPU_CM_CH_DB_MODE_SEL_0);

sys/arch/arm/imx/imx51_ipuv3.c

852

reg |= __BIT(CH_PANNEL_BG);

sys/arch/arm/imx/imx51_ipuv3.c

853

IPUV3_WRITE(sc, cm, IPU_CM_CH_DB_MODE_SEL_0, reg);

sys/arch/arm/imx/imx51_ipuv3.c

855

reg = IPUV3_READ(sc, idmac, IPU_IDMAC_CH_EN_1);

sys/arch/arm/imx/imx51_ipuv3.c

856

reg |= __BIT(CH_PANNEL_BG);

sys/arch/arm/imx/imx51_ipuv3.c

857

IPUV3_WRITE(sc, idmac, IPU_IDMAC_CH_EN_1, reg);

sys/arch/arm/imx/imx51_ipuv3.c

859

reg = IPUV3_READ(sc, cm, IPU_CM_GPR);

sys/arch/arm/imx/imx51_ipuv3.c

860

reg &= ~CM_GPR_IPU_CH_BUF0_RDY0_CLR;

sys/arch/arm/imx/imx51_ipuv3.c

861

IPUV3_WRITE(sc, cm, IPU_CM_GPR, reg);

sys/arch/arm/imx/imx51_tzic.c

216

uint32_t reg;

sys/arch/arm/imx/imx51_tzic.c

224

reg = INTC_READ(tzic, TZIC_PRIORITY(priority_offset));

sys/arch/arm/imx/imx51_tzic.c

225

reg &= ~(0xff << priority_shift);

sys/arch/arm/imx/imx51_tzic.c

226

reg |= SW_TO_HW_IPL(is->is_ipl) << priority_shift;

sys/arch/arm/imx/imx51_tzic.c

227

INTC_WRITE(tzic, TZIC_PRIORITY(priority_offset), reg);

sys/arch/arm/imx/imx51_tzic.c

90

#define INTC_READ(tzic, reg) \

sys/arch/arm/imx/imx51_tzic.c

91

bus_space_read_4((tzic)->sc_iot, (tzic)->sc_ioh, (reg))

sys/arch/arm/imx/imx51_tzic.c

92

#define INTC_WRITE(tzic, reg, val) \

sys/arch/arm/imx/imx51_tzic.c

93

bus_space_write_4((tzic)->sc_iot, (tzic)->sc_ioh, (reg), (val))

sys/arch/arm/imx/imxclock.c

102

reg = EPITCR_ENMOD | EPITCR_IOVW | EPITCR_RLD | imxclock->sc_clksrc;

sys/arch/arm/imx/imxclock.c

104

EPIT_EPITCR, reg);

sys/arch/arm/imx/imxclock.c

105

reg |= EPITCR_EN | EPITCR_OCIEN | EPITCR_WAITEN | EPITCR_DOZEN |

sys/arch/arm/imx/imxclock.c

108

EPIT_EPITCR, reg);

sys/arch/arm/imx/imxclock.c

74

uint32_t reg;

sys/arch/arm/imx/imxgpio.c

83

#define GPIO_READ(gpio, reg) \

sys/arch/arm/imx/imxgpio.c

84

bus_space_read_4((gpio)->gpio_memt, (gpio)->gpio_memh, (reg))

sys/arch/arm/imx/imxgpio.c

85

#define GPIO_WRITE(gpio, reg, val) \

sys/arch/arm/imx/imxgpio.c

86

bus_space_write_4((gpio)->gpio_memt, (gpio)->gpio_memh, (reg), (val))

sys/arch/arm/imx/imxpwm.c

147

uint32_t reg;

sys/arch/arm/imx/imxpwm.c

151

reg = PWM_IR_RIE;

sys/arch/arm/imx/imxpwm.c

152

PWM_WRITE(sc, PWM_IR, reg);

sys/arch/arm/imx/imxpwm.c

163

reg = PWM_READ(sc, PWM_CR);

sys/arch/arm/imx/imxpwm.c

164

reg &= PWM_CR_CLKSRC;

sys/arch/arm/imx/imxpwm.c

165

reg |= __SHIFTIN(CLKSRC_IPG_CLK, PWM_CR_CLKSRC);

sys/arch/arm/imx/imxpwm.c

166

PWM_WRITE(sc, PWM_CR, reg);

sys/arch/arm/imx/imxpwm.c

44

#define PWM_READ(sc, reg) \

sys/arch/arm/imx/imxpwm.c

45

bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg))

sys/arch/arm/imx/imxpwm.c

46

#define PWM_WRITE(sc, reg, val) \

sys/arch/arm/imx/imxpwm.c

47

bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))

sys/arch/arm/imx/imxsnvs.c

51

#define SNVS_READ(sc, reg) \

sys/arch/arm/imx/imxsnvs.c

52

bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, reg)

sys/arch/arm/imx/imxsnvs.c

54

#define SNVS_WRITE(sc, reg, val) \

sys/arch/arm/imx/imxsnvs.c

55

bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, reg, val)

sys/arch/arm/imx/imxuart.c

1345

uint32_t reg = 0xffff;

sys/arch/arm/imx/imxuart.c

1354

reg =

sys/arch/arm/imx/imxuart.c

1361

aprint_error_dev(sc->sc_dev, "imxuart_iflush timeout %02x\n", reg);

sys/arch/arm/imx/imxuart.c

422

uint32_t reg;

sys/arch/arm/imx/imxuart.c

423

reg = bus_space_read_4(iot, ioh, IMX_UCR1);

sys/arch/arm/imx/imxuart.c

424

reg |= IMX_UCR1_TXDMAEN | IMX_UCR1_RXDMAEN;

sys/arch/arm/imx/imxuart.c

425

bus_space_write_4(iot, ioh, IMX_UCR1, reg);

sys/arch/arm/imx/imxusb.c

225

uint32_t reg;

sys/arch/arm/imx/imxusb.c

228

reg = EOREAD4(hsc, EHCI_PORTSC(1));

sys/arch/arm/imx/imxusb.c

229

reg &= ~(PORTSC_PTS | PORTSC_PTW | PORTSC_PTS2);

sys/arch/arm/imx/imxusb.c

232

reg |= PORTSC_PTW_16;

sys/arch/arm/imx/imxusb.c

234

reg |= PORTSC_PTS_UTMI;

sys/arch/arm/imx/imxusb.c

237

reg |= PORTSC_PTS_PHILIPS;

sys/arch/arm/imx/imxusb.c

240

reg |= PORTSC_PTS_ULPI;

sys/arch/arm/imx/imxusb.c

243

reg |= PORTSC_PTS_SERIAL;

sys/arch/arm/imx/imxusb.c

246

reg |= PORTSC_PTS2;

sys/arch/arm/imx/imxusb.c

249

EOWRITE4(hsc, EHCI_PORTSC(1), reg);

sys/arch/arm/imx/imxusb.c

305

uint32_t reg;

sys/arch/arm/imx/imxusb.c

309

reg = ULPI_RUN | __SHIFTIN(addr, ULPI_ADDR);

sys/arch/arm/imx/imxusb.c

310

bus_space_write_4(sc->sc_iot, sc->sc_ioh, IMXUSB_ULPIVIEW, reg);

sys/arch/arm/imx/imxusb.c

312

reg = ulpi_wait(sc, TIMEOUT);

sys/arch/arm/imx/imxusb.c

314

return __SHIFTOUT(reg, ULPI_DATRD);

sys/arch/arm/imx/imxusb.c

320

uint32_t reg;

sys/arch/arm/imx/imxusb.c

324

reg = ULPI_RUN | ULPI_RW | __SHIFTIN(addr, ULPI_ADDR) | __SHIFTIN(data, ULPI_DATWR);

sys/arch/arm/imx/imxusb.c

325

bus_space_write_4(sc->sc_iot, sc->sc_ioh, IMXUSB_ULPIVIEW, reg);

sys/arch/arm/imx/imxusb.c

361

uint32_t reg;

sys/arch/arm/imx/imxusb.c

366

reg = EOREAD4(hsc, EHCI_USBCMD);

sys/arch/arm/imx/imxusb.c

367

reg &= ~EHCI_CMD_RS;

sys/arch/arm/imx/imxusb.c

368

EOWRITE4(hsc, EHCI_USBCMD, reg);

sys/arch/arm/imx/imxusb.c

371

reg = EOREAD4(hsc, EHCI_USBCMD);

sys/arch/arm/imx/imxusb.c

372

if ((reg & EHCI_CMD_RS) == 0)

sys/arch/arm/imx/imxusb.c

377

EOWRITE4(hsc, EHCI_USBCMD, reg | EHCI_CMD_HCRESET);

sys/arch/arm/imx/imxusb.c

380

reg = EOREAD4(hsc, EHCI_USBCMD);

sys/arch/arm/imx/imxusb.c

381

if ((reg & EHCI_CMD_HCRESET) == 0)

sys/arch/arm/imx/imxusb.c

387

aprint_error_dev(hsc->sc_dev, "reset timeout (%x)\n", reg);

sys/arch/arm/imx/imxusb.c

396

uint32_t reg;

sys/arch/arm/imx/imxusb.c

398

reg = EOREAD4(hsc, EHCI_PORTSC(1));

sys/arch/arm/imx/imxusb.c

399

reg &= ~(EHCI_PS_CSC | EHCI_PS_PEC | EHCI_PS_OCC);

sys/arch/arm/imx/imxusb.c

400

reg |= EHCI_PS_PP | EHCI_PS_PE;

sys/arch/arm/imx/imxusb.c

401

EOWRITE4(hsc, EHCI_PORTSC(1), reg);

sys/arch/arm/imx/imxusb.c

403

reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, IMXUSB_OTGSC);

sys/arch/arm/imx/imxusb.c

404

reg |= OTGSC_IDPU;

sys/arch/arm/imx/imxusb.c

407

reg |= OTGSC_DPIE;

sys/arch/arm/imx/imxusb.c

408

bus_space_write_4(sc->sc_iot, sc->sc_ioh, IMXUSB_OTGSC, reg);

sys/arch/arm/imx/imxusb.c

410

reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, IMXUSB_USBMODE);

sys/arch/arm/imx/imxusb.c

411

reg &= ~USBMODE_CM;

sys/arch/arm/imx/imxusb.c

412

reg |= USBMODE_CM_HOST;

sys/arch/arm/imx/imxusb.c

413

bus_space_write_4(sc->sc_iot, sc->sc_ioh, IMXUSB_USBMODE, reg);

sys/arch/arm/imx/imxwdog.c

124

reg = wdog_read(sc, IMX_WDOG_WCR);

sys/arch/arm/imx/imxwdog.c

125

reg &= ~WCR_WT;

sys/arch/arm/imx/imxwdog.c

126

reg |= __SHIFTIN(sc->sc_wdog_period * 2 - 1, WCR_WT);

sys/arch/arm/imx/imxwdog.c

127

reg |= WCR_WDE;

sys/arch/arm/imx/imxwdog.c

128

wdog_write(sc, IMX_WDOG_WCR, reg);

sys/arch/arm/imx/imxwdog.c

138

uint16_t reg;

sys/arch/arm/imx/imxwdog.c

157

reg = wdog_read(sc, IMX_WDOG_WCR);

sys/arch/arm/imx/imxwdog.c

158

reg &= ~WCR_WT;

sys/arch/arm/imx/imxwdog.c

159

reg |= __SHIFTIN(sc->sc_wdog_period * 2 - 1, WCR_WT);

sys/arch/arm/imx/imxwdog.c

160

wdog_write(sc, IMX_WDOG_WCR, reg);

sys/arch/arm/imx/imxwdog.c

183

reg = wdog_read(sc, IMX_WDOG_WCR);

sys/arch/arm/imx/imxwdog.c

184

reg |= WCR_WDE;

sys/arch/arm/imx/imxwdog.c

185

wdog_write(sc, IMX_WDOG_WCR, reg);

sys/arch/arm/imx/imxwdog.c

92

uint16_t reg;

sys/arch/arm/iomd/iomdreg.h

221

#define IOMD_ADDRESS(reg) (iomd_base + (reg << 2))

sys/arch/arm/iomd/iomdreg.h

222

#define IOMD_WRITE_BYTE(reg, val) \

sys/arch/arm/iomd/iomdreg.h

223

(*((volatile unsigned char *)(IOMD_ADDRESS(reg))) = (val))

sys/arch/arm/iomd/iomdreg.h

224

#define IOMD_WRITE_WORD(reg, val) \

sys/arch/arm/iomd/iomdreg.h

225

(*((volatile unsigned int *)(IOMD_ADDRESS(reg))) = (val))

sys/arch/arm/iomd/iomdreg.h

226

#define IOMD_READ_BYTE(reg) \

sys/arch/arm/iomd/iomdreg.h

227

(*((volatile unsigned char *)(IOMD_ADDRESS(reg))))

sys/arch/arm/iomd/iomdreg.h

228

#define IOMD_READ_WORD(reg) \

sys/arch/arm/iomd/iomdreg.h

229

(*((volatile unsigned int *)(IOMD_ADDRESS(reg))))

sys/arch/arm/iomd/vidc20config.c

178

vidcvideo_write(u_int reg, int value)

sys/arch/arm/iomd/vidc20config.c

193

if (reg == VIDC_PALREG) {

sys/arch/arm/iomd/vidc20config.c

195

WriteWord(vidc_base, reg | value);

sys/arch/arm/iomd/vidc20config.c

199

if (reg == VIDC_PALETTE) {

sys/arch/arm/iomd/vidc20config.c

200

WriteWord(vidc_base, reg | value);

sys/arch/arm/iomd/vidc20config.c

225

if (reg == tab[counter]) {

sys/arch/arm/iomd/vidc20config.c

226

WriteWord ( vidc_base, reg | value );

sys/arch/arm/iomd/vidc20config.h

40

extern int vidcvideo_write (u_int reg, int value);

sys/arch/arm/ixp12x0/ixp12x0.c

101

reg = bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh,

sys/arch/arm/ixp12x0/ixp12x0.c

104

SA_CONTROL, reg);

sys/arch/arm/ixp12x0/ixp12x0.c

133

reg = bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh,

sys/arch/arm/ixp12x0/ixp12x0.c

136

SA_CONTROL, reg);

sys/arch/arm/ixp12x0/ixp12x0.c

145

reg = bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh,

sys/arch/arm/ixp12x0/ixp12x0.c

151

PCI_COMMAND_STATUS_REG, reg);

sys/arch/arm/ixp12x0/ixp12x0.c

49

pcireg_t reg;

sys/arch/arm/ixp12x0/ixp12x0.c

79

reg = bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh,

sys/arch/arm/ixp12x0/ixp12x0.c

82

SA_CONTROL, reg);

sys/arch/arm/ixp12x0/ixp12x0_com.c

777

int reg;

sys/arch/arm/ixp12x0/ixp12x0_com.c

782

reg = 0xffff;

sys/arch/arm/ixp12x0/ixp12x0_com.c

789

reg =

sys/arch/arm/ixp12x0/ixp12x0_com.c

797

reg);

sys/arch/arm/ixp12x0/ixp12x0_intr.c

75

#define IXPREG(reg) *((volatile uint32_t*) (reg))

sys/arch/arm/marvell/armadaxp.c

1084

uint32_t reg;

sys/arch/arm/marvell/armadaxp.c

1087

reg = read_mlmbreg(MVSOC_MLMB_CIB_CTRL_CFG);

sys/arch/arm/marvell/armadaxp.c

1088

reg |= MVSOC_MLMB_CIB_CTRL_CFG_WB_EN;

sys/arch/arm/marvell/armadaxp.c

1089

write_mlmbreg(MVSOC_MLMB_CIB_CTRL_CFG, reg);

sys/arch/arm/marvell/armadaxp.c

1092

reg = read_mlmbreg(MVSOC_MLMB_CFU_FAB_CTRL);

sys/arch/arm/marvell/armadaxp.c

1093

reg |= MVSOC_MLMB_CFU_FAB_CTRL_SNOOP_CPU0;

sys/arch/arm/marvell/armadaxp.c

1094

write_mlmbreg(MVSOC_MLMB_CFU_FAB_CTRL, reg);

sys/arch/arm/marvell/armadaxp.c

1097

reg = read_mlmbreg(MVSOC_MLMB_CFU_CFG);

sys/arch/arm/marvell/armadaxp.c

1099

reg |= MVSOC_MLMB_CFU_CFG_L2_NOTIFY;

sys/arch/arm/marvell/armadaxp.c

1101

reg &= ~MVSOC_MLMB_CFU_CFG_L2_NOTIFY;

sys/arch/arm/marvell/armadaxp.c

1103

write_mlmbreg(MVSOC_MLMB_CFU_CFG, reg);

sys/arch/arm/marvell/armadaxp.c

1133

uint32_t reg;

sys/arch/arm/marvell/armadaxp.c

1138

reg = read_mlmbreg(MVSOC_MLMB_WCR(i));

sys/arch/arm/marvell/armadaxp.c

1139

reg &= ~MVSOC_MLMB_WCR_WINEN;

sys/arch/arm/marvell/armadaxp.c

1140

write_mlmbreg(MVSOC_MLMB_WCR(i), reg);

sys/arch/arm/marvell/armadaxp.c

1152

reg = def->base & MVSOC_MLMB_WBR_BASE_MASK;

sys/arch/arm/marvell/armadaxp.c

1153

write_mlmbreg(MVSOC_MLMB_WBR(def->window), reg);

sys/arch/arm/marvell/armadaxp.c

1156

reg = MVSOC_MLMB_WCR_SIZE(def->size);

sys/arch/arm/marvell/armadaxp.c

1157

reg |= MVSOC_MLMB_WCR_TARGET(def->target);

sys/arch/arm/marvell/armadaxp.c

1158

reg |= MVSOC_MLMB_WCR_ATTR(def->attr);

sys/arch/arm/marvell/armadaxp.c

1160

reg |= MVSOC_MLMB_WCR_SYNC; /* enable I/O coherency barrier */

sys/arch/arm/marvell/armadaxp.c

1162

reg |= MVSOC_MLMB_WCR_WINEN;

sys/arch/arm/marvell/armadaxp.c

1163

write_mlmbreg(MVSOC_MLMB_WCR(def->window), reg);

sys/arch/arm/marvell/armadaxp.c

71

#define MPIC_WRITE(reg, val) (bus_space_write_4(&mvsoc_bs_tag, \

sys/arch/arm/marvell/armadaxp.c

72

mpic_handle, reg, val))

sys/arch/arm/marvell/armadaxp.c

73

#define MPIC_CPU_WRITE(reg, val) (bus_space_write_4(&mvsoc_bs_tag, \

sys/arch/arm/marvell/armadaxp.c

734

uint32_t reg;

sys/arch/arm/marvell/armadaxp.c

738

reg = MPIC_CPU_READ(ARMADAXP_MLMB_MPIC_ERR_MASK);

sys/arch/arm/marvell/armadaxp.c

739

reg |= irq_mask;

sys/arch/arm/marvell/armadaxp.c

74

mpic_cpu_handle, reg, val))

sys/arch/arm/marvell/armadaxp.c

740

MPIC_CPU_WRITE(ARMADAXP_MLMB_MPIC_ERR_MASK, reg);

sys/arch/arm/marvell/armadaxp.c

747

uint32_t reg;

sys/arch/arm/marvell/armadaxp.c

751

reg = MPIC_CPU_READ(ARMADAXP_MLMB_MPIC_ERR_MASK);

sys/arch/arm/marvell/armadaxp.c

752

reg &= ~irq_mask;

sys/arch/arm/marvell/armadaxp.c

753

MPIC_CPU_WRITE(ARMADAXP_MLMB_MPIC_ERR_MASK, reg);

sys/arch/arm/marvell/armadaxp.c

759

uint32_t reg;

sys/arch/arm/marvell/armadaxp.c

76

#define MPIC_READ(reg) (bus_space_read_4(&mvsoc_bs_tag, \

sys/arch/arm/marvell/armadaxp.c

763

reg = MPIC_CPU_READ(ARMADAXP_MLMB_MPIC_ERR_MASK);

sys/arch/arm/marvell/armadaxp.c

764

reg |= ARMADAXP_IRQ_ERROR_BIT(is->is_irq);

sys/arch/arm/marvell/armadaxp.c

765

MPIC_CPU_WRITE(ARMADAXP_MLMB_MPIC_ERR_MASK, reg);

sys/arch/arm/marvell/armadaxp.c

77

mpic_handle, reg))

sys/arch/arm/marvell/armadaxp.c

772

uint32_t reg;

sys/arch/arm/marvell/armadaxp.c

775

reg = MPIC_READ(ARMADAXP_MLMB_MPIC_ERR_CAUSE);

sys/arch/arm/marvell/armadaxp.c

776

irq = ffs(reg);

sys/arch/arm/marvell/armadaxp.c

78

#define MPIC_CPU_READ(reg) (bus_space_read_4(&mvsoc_bs_tag, \

sys/arch/arm/marvell/armadaxp.c

79

mpic_cpu_handle, reg))

sys/arch/arm/marvell/armadaxp.c

81

#define L2_WRITE(reg, val) (bus_space_write_4(&mvsoc_bs_tag, \

sys/arch/arm/marvell/armadaxp.c

82

l2_handle, reg, val))

sys/arch/arm/marvell/armadaxp.c

83

#define L2_READ(reg) (bus_space_read_4(&mvsoc_bs_tag, \

sys/arch/arm/marvell/armadaxp.c

84

l2_handle, reg))

sys/arch/arm/marvell/armadaxp.c

887

u_int32_t reg;

sys/arch/arm/marvell/armadaxp.c

904

reg = L2_READ(ARMADAXP_L2_AUX_CTRL);

sys/arch/arm/marvell/armadaxp.c

905

reg &= ~(L2_AUX_WBWT_MODE_MASK);

sys/arch/arm/marvell/armadaxp.c

906

reg &= ~(L2_AUX_REP_STRAT_MASK);

sys/arch/arm/marvell/armadaxp.c

907

reg |= L2_AUX_ECC_ENABLE;

sys/arch/arm/marvell/armadaxp.c

908

reg |= L2_AUX_PARITY_ENABLE;

sys/arch/arm/marvell/armadaxp.c

909

reg |= L2_AUX_WBWT_MODE_BY_ATTR;

sys/arch/arm/marvell/armadaxp.c

910

reg |= L2_AUX_FORCE_WA_BY_ATTR;

sys/arch/arm/marvell/armadaxp.c

911

reg |= L2_AUX_REP_STRAT_SEMIPLRU;

sys/arch/arm/marvell/armadaxp.c

912

L2_WRITE(ARMADAXP_L2_AUX_CTRL, reg);

sys/arch/arm/marvell/armadaxp.c

921

__asm__ __volatile__ ("mrc p15, 1, %0, c15, c2, 0" : "=r"(reg));

sys/arch/arm/marvell/armadaxp.c

922

reg |= (1 << 8);

sys/arch/arm/marvell/armadaxp.c

923

__asm__ __volatile__ ("mcr p15, 1, %0, c15, c2, 0" : :"r"(reg));

sys/arch/arm/marvell/armadaxp.c

929

reg = read_mlmbreg(ARMADAXP_L2_CFU);

sys/arch/arm/marvell/armadaxp.c

930

reg |= (1 << 17) | (1 << 18);

sys/arch/arm/marvell/armadaxp.c

931

write_mlmbreg(ARMADAXP_L2_CFU, reg);

sys/arch/arm/marvell/armadaxp.c

934

reg = L2_READ(ARMADAXP_L2_CTRL);

sys/arch/arm/marvell/armadaxp.c

935

L2_WRITE(ARMADAXP_L2_CTRL, reg | L2_CTRL_ENABLE);

sys/arch/arm/marvell/dove.c

215

const size_t reg = DOVE_DB_MIRQIMR

sys/arch/arm/marvell/dove.c

219

write_dbreg(reg, read_dbreg(reg) | irq_mask);

sys/arch/arm/marvell/dove.c

227

const size_t reg = DOVE_DB_MIRQIMR

sys/arch/arm/marvell/dove.c

231

write_dbreg(reg, read_dbreg(reg) & ~irq_mask);

sys/arch/arm/marvell/kirkwood.c

170

const size_t reg = KIRKWOOD_MLMB_MIRQIMLR

sys/arch/arm/marvell/kirkwood.c

174

write_mlmbreg(reg, read_mlmbreg(reg) | irq_mask);

sys/arch/arm/marvell/kirkwood.c

182

const size_t reg = KIRKWOOD_MLMB_MIRQIMLR

sys/arch/arm/marvell/kirkwood.c

186

write_mlmbreg(reg, read_mlmbreg(reg) & ~irq_mask);

sys/arch/arm/marvell/kirkwood.c

235

uint32_t reg;

sys/arch/arm/marvell/kirkwood.c

247

reg = le32toh(*(volatile uint32_t *)(iobase + KIRKWOOD_MPP_BASE +

sys/arch/arm/marvell/kirkwood.c

250

switch (reg & 0x0000001c) {

sys/arch/arm/marvell/kirkwood.c

258

switch (reg & 0x0040001a) {

sys/arch/arm/marvell/kirkwood.c

272

switch (reg & 0x000001e0) {

sys/arch/arm/marvell/mv78xx0.c

212

uint32_t reg;

sys/arch/arm/marvell/mv78xx0.c

217

reg = le32toh(*(volatile uint32_t *)(iobase +

sys/arch/arm/marvell/mv78xx0.c

219

switch (reg & 0x180) {

sys/arch/arm/marvell/mv78xx0.c

225

reg = le32toh(*(volatile uint32_t *)(iobase +

sys/arch/arm/marvell/mv78xx0.c

228

switch (reg & 0x0e0) {

sys/arch/arm/marvell/mv78xx0.c

238

x = (reg & 0xf00) >> 8;

sys/arch/arm/marvell/mvsoc.c

1193

uint32_t reg;

sys/arch/arm/marvell/mvsoc.c

1198

reg = le32toh(*(volatile uint32_t *)(pex_base + PCI_ID_REG));

sys/arch/arm/marvell/mvsoc.c

1199

model = PCI_PRODUCT(reg);

sys/arch/arm/marvell/mvsoc.c

1203

reg = le32toh(*(volatile uint32_t *)(regbase + ORION_PMI_BASE +

sys/arch/arm/marvell/mvsoc.c

1205

if ((reg & ORION_PMISMPL_TCLK_MASK) == 0)

sys/arch/arm/marvell/mvsoc.c

1211

reg = le32toh(*(volatile uint32_t *)(regbase +

sys/arch/arm/marvell/mvsoc.c

1213

if (reg == 1) /* 88F6192 is 1 */

sys/arch/arm/marvell/mvsoc.c

1224

uint32_t reg;

sys/arch/arm/marvell/mvsoc.c

1229

reg = le32toh(*(volatile uint32_t *)(pex_base + PCI_CLASS_REG));

sys/arch/arm/marvell/mvsoc.c

1230

rev = PCI_REVISION(reg);

sys/arch/arm/marvell/mvsoc.c

1462

uint32_t reg, base, size, target, attr, enable;

sys/arch/arm/marvell/mvsoc.c

1466

reg = read_mlmbreg(MVSOC_MLMB_WCR(i));

sys/arch/arm/marvell/mvsoc.c

1467

enable = reg & MVSOC_MLMB_WCR_WINEN;

sys/arch/arm/marvell/mvsoc.c

1468

target = MVSOC_MLMB_WCR_GET_TARGET(reg);

sys/arch/arm/marvell/mvsoc.c

1469

attr = MVSOC_MLMB_WCR_GET_ATTR(reg);

sys/arch/arm/marvell/mvsoc.c

1470

size = MVSOC_MLMB_WCR_GET_SIZE(reg);

sys/arch/arm/marvell/mvsoc.c

1472

reg = read_mlmbreg(MVSOC_MLMB_WBR(i));

sys/arch/arm/marvell/mvsoc.c

1473

base = MVSOC_MLMB_WBR_GET_BASE(reg);

sys/arch/arm/marvell/mvsocgpp.c

60

#define MVSOCGPP_READ(sc, reg) \

sys/arch/arm/marvell/mvsocgpp.c

61

bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg))

sys/arch/arm/marvell/mvsocgpp.c

62

#define MVSOCGPP_WRITE(sc, reg, val) \

sys/arch/arm/marvell/mvsocgpp.c

63

bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))

sys/arch/arm/marvell/mvsocreg.h

100

(((reg) & MVSOC_MLMB_WCR_SIZE_MASK) + (1 << 16))

sys/arch/arm/marvell/mvsocreg.h

104

#define MVSOC_MLMB_WBR_GET_BASE(reg) (reg & MVSOC_MLMB_WBR_BASE_MASK)

sys/arch/arm/marvell/mvsocreg.h

107

#define MVSOC_MLMB_WRLR_GET_REMAP(reg) \

sys/arch/arm/marvell/mvsocreg.h

108

(reg & MVSOC_MLMB_WRLR_REMAP_MASK)

sys/arch/arm/marvell/mvsocreg.h

94

#define MVSOC_MLMB_WCR_GET_TARGET(reg) (((reg) >> 4) & 0xf)

sys/arch/arm/marvell/mvsocreg.h

96

#define MVSOC_MLMB_WCR_GET_ATTR(reg) (((reg) >> 8) & 0xff)

sys/arch/arm/marvell/mvsocreg.h

99

#define MVSOC_MLMB_WCR_GET_SIZE(reg) \

sys/arch/arm/marvell/mvsocrtc.c

156

uint32_t reg;

sys/arch/arm/marvell/mvsocrtc.c

159

reg = (bintobcd(dt->dt_sec) << MVSOCRTC_SECOND_OFFSET) |

sys/arch/arm/marvell/mvsocrtc.c

164

bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVSOCRTC_TIME, reg);

sys/arch/arm/marvell/mvsocrtc.c

167

reg = (bintobcd(dt->dt_day) << MVSOCRTC_DAY_OFFSET) |

sys/arch/arm/marvell/mvsocrtc.c

171

bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVSOCRTC_DATE, reg);

sys/arch/arm/marvell/orion.c

213

uint32_t reg, armddrclk, tclk;

sys/arch/arm/marvell/orion.c

227

reg = le32toh(*(volatile uint32_t *)(iobase + ORION_PMI_BASE +

sys/arch/arm/marvell/orion.c

229

armddrclk = (reg >> armddrclk_shift) & ORION_PMISMPL_ARMDDRCLK_MASK;

sys/arch/arm/marvell/orion.c

231

if (reg & ORION_PMISMPL_ARMDDRCLK_H_MASK)

sys/arch/arm/marvell/orion.c

240

tclk = (reg >> tclk_shift) & ORION_PMISMPL_TCLK_MASK;

sys/arch/arm/marvell/pci_machdep.c

271

gtpci_mbus_conf_read(void *v, pcitag_t tag, int reg)

sys/arch/arm/marvell/pci_machdep.c

274

const pcireg_t addr = tag | reg;

sys/arch/arm/marvell/pci_machdep.c

276

if ((unsigned int)reg >= PCI_CONF_SIZE)

sys/arch/arm/marvell/pci_machdep.c

289

gtpci_mbus_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data)

sys/arch/arm/marvell/pci_machdep.c

292

pcireg_t addr = tag | (reg & 0xfc);

sys/arch/arm/marvell/pci_machdep.c

294

if ((unsigned int)reg >= PCI_CONF_SIZE)

sys/arch/arm/marvell/pci_machdep.c

384

mvpex_mbus_conf_read(void *v, pcitag_t tag, int reg)

sys/arch/arm/marvell/pci_machdep.c

391

if ((unsigned int)reg >= PCI_CONF_SIZE)

sys/arch/arm/marvell/pci_machdep.c

415

addr = ((reg & 0xf00) << 24) | tag | (reg & 0xfc);

sys/arch/arm/nvidia/tegra124_car.c

1152

if (tmux->reg == CAR_CLKSRC_HDMI_REG &&

sys/arch/arm/nvidia/tegra124_car.c

1176

v = bus_space_read_4(bst, bsh, tmux->reg);

sys/arch/arm/nvidia/tegra124_car.c

1179

bus_space_write_4(bst, bsh, tmux->reg, v);

sys/arch/arm/nvidia/tegra124_car.c

1194

const uint32_t v = bus_space_read_4(bst, bsh, tmux->reg);

sys/arch/arm/nvidia/tegra124_car.c

1246

const uint32_t v = bus_space_read_4(bst, bsh, tdiv->reg);

sys/arch/arm/nvidia/tegra124_car.c

1249

switch (tdiv->reg) {

sys/arch/arm/nvidia/tegra124_car.c

1296

v = bus_space_read_4(bst, bsh, tdiv->reg);

sys/arch/arm/nvidia/tegra124_car.c

1300

switch (tdiv->reg) {

sys/arch/arm/nvidia/tegra124_car.c

1356

bus_space_write_4(bst, bsh, tdiv->reg, v);

sys/arch/arm/nvidia/tegra124_car.c

1368

bus_size_t reg;

sys/arch/arm/nvidia/tegra124_car.c

1382

reg = tgate->set_reg;

sys/arch/arm/nvidia/tegra124_car.c

1384

reg = tgate->clr_reg;

sys/arch/arm/nvidia/tegra124_car.c

1387

if (reg == CAR_CLK_ENB_V_SET_REG &&

sys/arch/arm/nvidia/tegra124_car.c

1394

bus_space_write_4(bst, bsh, reg, tgate->bits);

sys/arch/arm/nvidia/tegra124_car.c

1542

const u_int reg = reset_id / 32;

sys/arch/arm/nvidia/tegra124_car.c

1545

rst->set_reg = tegra124_car_reset_regs[reg].set_reg;

sys/arch/arm/nvidia/tegra124_car.c

1546

rst->clr_reg = tegra124_car_reset_regs[reg].clr_reg;

sys/arch/arm/nvidia/tegra124_car.c

316

.reg = (_reg), \

sys/arch/arm/nvidia/tegra124_car.c

337

.reg = (_reg), \

sys/arch/arm/nvidia/tegra210_car.c

1282

v = bus_space_read_4(bst, bsh, tmux->reg);

sys/arch/arm/nvidia/tegra210_car.c

1285

bus_space_write_4(bst, bsh, tmux->reg, v);

sys/arch/arm/nvidia/tegra210_car.c

1300

const uint32_t v = bus_space_read_4(bst, bsh, tmux->reg);

sys/arch/arm/nvidia/tegra210_car.c

1342

const uint32_t v = bus_space_read_4(bst, bsh, tdiv->reg);

sys/arch/arm/nvidia/tegra210_car.c

1345

switch (tdiv->reg) {

sys/arch/arm/nvidia/tegra210_car.c

1400

v = bus_space_read_4(bst, bsh, tdiv->reg);

sys/arch/arm/nvidia/tegra210_car.c

1404

switch (tdiv->reg) {

sys/arch/arm/nvidia/tegra210_car.c

1454

bus_space_write_4(bst, bsh, tdiv->reg, v);

sys/arch/arm/nvidia/tegra210_car.c

1466

bus_size_t reg;

sys/arch/arm/nvidia/tegra210_car.c

1480

reg = tgate->set_reg;

sys/arch/arm/nvidia/tegra210_car.c

1482

reg = tgate->clr_reg;

sys/arch/arm/nvidia/tegra210_car.c

1484

bus_space_write_4(bst, bsh, reg, tgate->bits);

sys/arch/arm/nvidia/tegra210_car.c

1632

const u_int reg = reset_id / 32;

sys/arch/arm/nvidia/tegra210_car.c

1635

rst->set_reg = tegra210_car_reset_regs[reg].set_reg;

sys/arch/arm/nvidia/tegra210_car.c

1636

rst->clr_reg = tegra210_car_reset_regs[reg].clr_reg;

sys/arch/arm/nvidia/tegra210_car.c

328

.reg = (_reg), \

sys/arch/arm/nvidia/tegra210_car.c

349

.reg = (_reg), \

sys/arch/arm/nvidia/tegra210_xusbpad.c

218

#define RD4(sc, reg) \

sys/arch/arm/nvidia/tegra210_xusbpad.c

219

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/nvidia/tegra210_xusbpad.c

220

#define WR4(sc, reg, val) \

sys/arch/arm/nvidia/tegra210_xusbpad.c

221

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/nvidia/tegra210_xusbpad.c

222

#define SETCLR4(sc, reg, set, clr) \

sys/arch/arm/nvidia/tegra210_xusbpad.c

223

tegra_reg_set_clear((sc)->sc_bst, (sc)->sc_bsh, (reg), (set), (clr))

sys/arch/arm/nvidia/tegra210_xusbpad.c

577

.reg = (r), \

sys/arch/arm/nvidia/tegra210_xusbpad.c

587

bus_size_t reg;

sys/arch/arm/nvidia/tegra210_xusbpad.c

630

.reg = (r), \

sys/arch/arm/nvidia/tegra210_xusbpad.c

638

bus_size_t reg;

sys/arch/arm/nvidia/tegra210_xusbpad.c

712

SETCLR4(sc, lane->reg, __SHIFTIN(func, lane->mask), lane->mask);

sys/arch/arm/nvidia/tegra210_xusbpad.c

849

SETCLR4(sc, port->reg, __SHIFTIN(internal, port->internal_mask), port->internal_mask);

sys/arch/arm/nvidia/tegra210_xusbpad.c

850

SETCLR4(sc, port->reg, __SHIFTIN(modeval, port->mask), port->mask);

sys/arch/arm/nvidia/tegra210_xusbpad.c

869

SETCLR4(sc, port->reg, __SHIFTIN(internal, port->internal_mask), port->internal_mask);

sys/arch/arm/nvidia/tegra210_xusbpad.c

870

SETCLR4(sc, port->reg, __SHIFTIN(companion, port->mask), port->mask);

sys/arch/arm/nvidia/tegra_ahcisata.c

134

struct fdtbus_regulator *reg;

sys/arch/arm/nvidia/tegra_ahcisata.c

210

reg = fdtbus_regulator_acquire(phandle, supply);

sys/arch/arm/nvidia/tegra_ahcisata.c

211

if (reg == NULL) {

sys/arch/arm/nvidia/tegra_ahcisata.c

215

if (fdtbus_regulator_enable(reg) != 0) {

sys/arch/arm/nvidia/tegra_ahcisata.c

218

fdtbus_regulator_release(reg);

sys/arch/arm/nvidia/tegra_apbdma.c

89

#define APBDMA_READ(sc, reg) \

sys/arch/arm/nvidia/tegra_apbdma.c

90

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/nvidia/tegra_apbdma.c

91

#define APBDMA_WRITE(sc, reg, val) \

sys/arch/arm/nvidia/tegra_apbdma.c

92

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/nvidia/tegra_cec.c

107

#define CEC_READ(sc, reg) \

sys/arch/arm/nvidia/tegra_cec.c

108

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/nvidia/tegra_cec.c

109

#define CEC_WRITE(sc, reg, val) \

sys/arch/arm/nvidia/tegra_cec.c

110

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/nvidia/tegra_cec.c

111

#define CEC_SET_CLEAR(sc, reg, set, clr) \

sys/arch/arm/nvidia/tegra_cec.c

112

tegra_reg_set_clear((sc)->sc_bst, (sc)->sc_bsh, (reg), (set), (clr))

sys/arch/arm/nvidia/tegra_clock.h

59

u_int reg;

sys/arch/arm/nvidia/tegra_clock.h

64

u_int reg;

sys/arch/arm/nvidia/tegra_drm.c

121

struct fdtbus_regulator *reg;

sys/arch/arm/nvidia/tegra_drm.c

181

reg = fdtbus_regulator_acquire(hdmi_phandle, supply);

sys/arch/arm/nvidia/tegra_drm.c

182

if (reg == NULL) {

sys/arch/arm/nvidia/tegra_drm.c

187

if (fdtbus_regulator_enable(reg) != 0) {

sys/arch/arm/nvidia/tegra_drm.c

191

fdtbus_regulator_release(reg);

sys/arch/arm/nvidia/tegra_drm.h

143

#define HDMI_READ(enc, reg) \

sys/arch/arm/nvidia/tegra_drm.h

144

bus_space_read_4((enc)->bst, (enc)->bsh, (reg))

sys/arch/arm/nvidia/tegra_drm.h

145

#define HDMI_WRITE(enc, reg, val) \

sys/arch/arm/nvidia/tegra_drm.h

146

bus_space_write_4((enc)->bst, (enc)->bsh, (reg), (val))

sys/arch/arm/nvidia/tegra_drm.h

147

#define HDMI_SET_CLEAR(enc, reg, set, clr) \

sys/arch/arm/nvidia/tegra_drm.h

148

tegra_reg_set_clear((enc)->bst, (enc)->bsh, (reg), (set), (clr))

sys/arch/arm/nvidia/tegra_drm.h

150

#define DC_READ(crtc, reg) \

sys/arch/arm/nvidia/tegra_drm.h

151

bus_space_read_4((crtc)->bst, (crtc)->bsh, (reg))

sys/arch/arm/nvidia/tegra_drm.h

152

#define DC_WRITE(crtc, reg, val) \

sys/arch/arm/nvidia/tegra_drm.h

153

bus_space_write_4((crtc)->bst, (crtc)->bsh, (reg), (val))

sys/arch/arm/nvidia/tegra_drm.h

154

#define DC_SET_CLEAR(crtc, reg, set, clr) \

sys/arch/arm/nvidia/tegra_drm.h

155

tegra_reg_set_clear((crtc)->bst, (crtc)->bsh, (reg), (set), (clr))

sys/arch/arm/nvidia/tegra_gpio.c

139

#define GPIO_WRITE(bank, reg, val) \

sys/arch/arm/nvidia/tegra_gpio.c

142

(bank)->bank_pb->base + (reg), (val))

sys/arch/arm/nvidia/tegra_gpio.c

143

#define GPIO_READ(bank, reg) \

sys/arch/arm/nvidia/tegra_gpio.c

146

(bank)->bank_pb->base + (reg))

sys/arch/arm/nvidia/tegra_i2c.c

79

#define I2C_WRITE(sc, reg, val) \

sys/arch/arm/nvidia/tegra_i2c.c

80

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/nvidia/tegra_i2c.c

81

#define I2C_READ(sc, reg) \

sys/arch/arm/nvidia/tegra_i2c.c

82

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/nvidia/tegra_i2c.c

83

#define I2C_SET_CLEAR(sc, reg, setval, clrval) \

sys/arch/arm/nvidia/tegra_i2c.c

84

tegra_reg_set_clear((sc)->sc_bst, (sc)->sc_bsh, (reg), (setval), (clrval))

sys/arch/arm/nvidia/tegra_mc.c

64

#define MC_READ(sc, reg) \

sys/arch/arm/nvidia/tegra_mc.c

65

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/nvidia/tegra_mc.c

66

#define MC_WRITE(sc, reg, val) \

sys/arch/arm/nvidia/tegra_mc.c

67

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/nvidia/tegra_mc.c

68

#define MC_SET_CLEAR(sc, reg, set, clr) \

sys/arch/arm/nvidia/tegra_mc.c

69

tegra_reg_set_clear((sc)->sc_bst, (sc)->sc_bsh, (reg), (set), (clr))

sys/arch/arm/nvidia/tegra_pcie.c

671

u_int reg;

sys/arch/arm/nvidia/tegra_pcie.c

684

reg = d * 0x1000 + offset;

sys/arch/arm/nvidia/tegra_pcie.c

687

reg = (d << 11) | (f << 8) | (offset & 0xff);

sys/arch/arm/nvidia/tegra_pcie.c

693

return bus_space_read_4(sc->sc_bst, bsh, reg);

sys/arch/arm/nvidia/tegra_pcie.c

702

u_int reg;

sys/arch/arm/nvidia/tegra_pcie.c

715

reg = d * 0x1000 + offset;

sys/arch/arm/nvidia/tegra_pcie.c

718

reg = (d << 11) | (f << 8) | (offset & 0xff);

sys/arch/arm/nvidia/tegra_pcie.c

724

bus_space_write_4(sc->sc_bst, bsh, reg, val);

sys/arch/arm/nvidia/tegra_pinmux.c

69

#define PADCTRL_WRITE(sc, reg, val) \

sys/arch/arm/nvidia/tegra_pinmux.c

70

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh[0], (reg), (val))

sys/arch/arm/nvidia/tegra_pinmux.c

71

#define PADCTRL_READ(sc, reg) \

sys/arch/arm/nvidia/tegra_pinmux.c

72

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh[0], (reg))

sys/arch/arm/nvidia/tegra_pinmux.c

73

#define PINMUX_WRITE(sc, reg, val) \

sys/arch/arm/nvidia/tegra_pinmux.c

74

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh[1], (reg), (val))

sys/arch/arm/nvidia/tegra_pinmux.c

75

#define PINMUX_READ(sc, reg) \

sys/arch/arm/nvidia/tegra_pinmux.c

76

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh[1], (reg))

sys/arch/arm/nvidia/tegra_rtc.c

65

#define RTC_READ(sc, reg) \

sys/arch/arm/nvidia/tegra_rtc.c

66

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/nvidia/tegra_rtc.c

67

#define RTC_WRITE(sc, reg, val) \

sys/arch/arm/nvidia/tegra_rtc.c

68

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/nvidia/tegra_soctherm.c

148

#define SOCTHERM_READ(sc, reg) \

sys/arch/arm/nvidia/tegra_soctherm.c

149

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/nvidia/tegra_soctherm.c

150

#define SOCTHERM_WRITE(sc, reg, val) \

sys/arch/arm/nvidia/tegra_soctherm.c

151

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/nvidia/tegra_soctherm.c

152

#define SOCTHERM_SET_CLEAR(sc, reg, set, clr) \

sys/arch/arm/nvidia/tegra_soctherm.c

153

tegra_reg_set_clear((sc)->sc_bst, (sc)->sc_bsh, (reg), (set), (clr))

sys/arch/arm/nvidia/tegra_soctherm.c

155

#define SENSOR_READ(sc, s, reg) \

sys/arch/arm/nvidia/tegra_soctherm.c

156

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (s)->s_base + (reg))

sys/arch/arm/nvidia/tegra_soctherm.c

157

#define SENSOR_WRITE(sc, s, reg, val) \

sys/arch/arm/nvidia/tegra_soctherm.c

158

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (s)->s_base + (reg), (val))

sys/arch/arm/nvidia/tegra_soctherm.c

159

#define SENSOR_SET_CLEAR(sc, s, reg, set, clr) \

sys/arch/arm/nvidia/tegra_soctherm.c

160

tegra_reg_set_clear((sc)->sc_bst, (sc)->sc_bsh, (s)->s_base + (reg), (set), (clr))

sys/arch/arm/nvidia/tegra_timer.c

67

#define TIMER_READ(sc, reg) \

sys/arch/arm/nvidia/tegra_timer.c

68

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/nvidia/tegra_timer.c

69

#define TIMER_WRITE(sc, reg, val) \

sys/arch/arm/nvidia/tegra_timer.c

70

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/nvidia/tegra_timer.c

71

#define TIMER_SET_CLEAR(sc, reg, set, clr) \

sys/arch/arm/nvidia/tegra_timer.c

72

tegra_reg_set_clear((sc)->sc_bst, (sc)->sc_bsh, (reg), (set), (clr))

sys/arch/arm/nvidia/tegra_usbphy.c

161

reg = fdtbus_regulator_acquire(phandle, "vbus-supply");

sys/arch/arm/nvidia/tegra_usbphy.c

162

if (reg) {

sys/arch/arm/nvidia/tegra_usbphy.c

166

fdtbus_regulator_enable(reg);

sys/arch/arm/nvidia/tegra_usbphy.c

99

struct fdtbus_regulator *reg;

sys/arch/arm/nvidia/tegra_xusb.c

605

struct fdtbus_regulator *reg;

sys/arch/arm/nvidia/tegra_xusb.c

611

reg = fdtbus_regulator_acquire(phandle, psc->sc_txd->txd_supplies[n]);

sys/arch/arm/nvidia/tegra_xusb.c

612

if (reg == NULL) {

sys/arch/arm/nvidia/tegra_xusb.c

617

error = fdtbus_regulator_enable(reg);

sys/arch/arm/nxp/imx6_ccm.c

167

uint32_t v = bus_space_read_4(sc->sc_iot, sc->sc_ioh_analog, pll->reg);

sys/arch/arm/nxp/imx6_ccm.c

182

uint32_t v = bus_space_read_4(sc->sc_iot, sc->sc_ioh_analog, pll->reg);

sys/arch/arm/nxp/imx6_ccm.c

200

uint32_t v = bus_space_read_4(sc->sc_iot, sc->sc_ioh_analog, pll->reg);

sys/arch/arm/nxp/imx6_ccm.c

203

pll->reg + PLL_AUDIO_VIDEO_NUM_OFFSET);

sys/arch/arm/nxp/imx6_ccm.c

205

pll->reg + PLL_AUDIO_VIDEO_DENOM_OFFSET);

sys/arch/arm/nxp/imx6_ccm.c

287

uint32_t v = bus_space_read_4(sc->sc_iot, ioh, div->reg);

sys/arch/arm/nxp/imx6_ccm.c

316

uint32_t v = bus_space_read_4(sc->sc_iot, sc->sc_ioh_analog, pfd->reg);

sys/arch/arm/nxp/imx6_ccm.c

365

uint32_t v = bus_space_read_4(sc->sc_iot, ioh, mux->reg);

sys/arch/arm/nxp/imx6_ccm.c

369

bus_space_write_4(sc->sc_iot, ioh, mux->reg, v);

sys/arch/arm/nxp/imx6_ccm.c

392

uint32_t v = bus_space_read_4(sc->sc_iot, ioh, mux->reg);

sys/arch/arm/nxp/imx6_ccm.c

433

uint32_t v = bus_space_read_4(sc->sc_iot, ioh, div->reg);

sys/arch/arm/nxp/imx6_ccm.c

450

bus_space_write_4(sc->sc_iot, ioh, div->reg, v);

sys/arch/arm/nxp/imx6_ccm.c

547

uint32_t v = bus_space_read_4(sc->sc_iot, ioh, pll->reg);

sys/arch/arm/nxp/imx6_ccm.c

554

bus_space_write_4(sc->sc_iot, ioh, pll->reg, v);

sys/arch/arm/nxp/imx6_ccm.c

557

while (!(bus_space_read_4(sc->sc_iot, ioh, pll->reg) & CCM_ANALOG_PLL_LOCK))

sys/arch/arm/nxp/imx6_ccm.c

576

uint32_t v = bus_space_read_4(sc->sc_iot, ioh, gate->reg);

sys/arch/arm/nxp/imx6_ccm.c

586

bus_space_write_4(sc->sc_iot, ioh, gate->reg, v);

sys/arch/arm/nxp/imx6_ccmvar.h

103

uint32_t reg;

sys/arch/arm/nxp/imx6_ccmvar.h

109

uint32_t reg;

sys/arch/arm/nxp/imx6_ccmvar.h

118

uint32_t reg;

sys/arch/arm/nxp/imx6_ccmvar.h

128

uint32_t reg;

sys/arch/arm/nxp/imx6_ccmvar.h

138

uint32_t reg;

sys/arch/arm/nxp/imx6_ccmvar.h

189

.reg = (CCM_ANALOG_##_reg), \

sys/arch/arm/nxp/imx6_ccmvar.h

202

.reg = (CCM_ANALOG_##_reg), \

sys/arch/arm/nxp/imx6_ccmvar.h

218

.reg = (CCM_##_reg), \

sys/arch/arm/nxp/imx6_ccmvar.h

232

.reg = (CCM_##_reg), \

sys/arch/arm/nxp/imx6_ccmvar.h

248

.reg = (CCM_ANALOG_##_reg), \

sys/arch/arm/nxp/imx6_ccmvar.h

262

.reg = (_base##_##_reg), \

sys/arch/arm/nxp/imx6_ccmvar.h

277

.reg = (CCM_##_reg), \

sys/arch/arm/nxp/imx6_ccmvar.h

294

.reg = (_base##_##_reg), \

sys/arch/arm/nxp/imx6_ccmvar.h

308

.reg = (_base##_##_reg), \

sys/arch/arm/nxp/imx6_iomux.c

100

reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, input_reg);

sys/arch/arm/nxp/imx6_iomux.c

101

reg &= ~mask;

sys/arch/arm/nxp/imx6_iomux.c

102

reg |= __SHIFTIN(sel, mask);

sys/arch/arm/nxp/imx6_iomux.c

103

bus_space_write_4(sc->sc_iot, sc->sc_ioh, input_reg, reg);

sys/arch/arm/nxp/imx6_iomux.c

106

input_reg, reg);

sys/arch/arm/nxp/imx6_iomux.c

108

reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, input_reg);

sys/arch/arm/nxp/imx6_iomux.c

112

input_reg, reg, input_val);

sys/arch/arm/nxp/imx6_iomux.c

59

uint32_t reg;

sys/arch/arm/nxp/imx6_iomux.c

80

reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, mux_reg);

sys/arch/arm/nxp/imx6_iomux.c

84

mux_reg, reg, mux_mode);

sys/arch/arm/nxp/imx6_iomux.c

87

reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, conf_reg);

sys/arch/arm/nxp/imx6_iomux.c

91

conf_reg, reg, config);

sys/arch/arm/nxp/imx6_pcie.c

251

imx6_pcie_gpr_read(void *cookie, uint32_t reg)

sys/arch/arm/nxp/imx6_pcie.c

255

return bus_space_read_4(sc->sc_iot, sc->sc_gpr_ioh, reg);

sys/arch/arm/nxp/imx6_pcie.c

259

imx6_pcie_gpr_write(void *cookie, uint32_t reg, uint32_t val)

sys/arch/arm/nxp/imx6_pcie.c

263

bus_space_write_4(sc->sc_iot, sc->sc_gpr_ioh, reg, val);

sys/arch/arm/nxp/imx6_usb.c

103

struct fdtbus_regulator *reg;

sys/arch/arm/nxp/imx6_usb.c

174

reg = fdtbus_regulator_acquire(phandle, "vbus-supply");

sys/arch/arm/nxp/imx6_usb.c

175

if (reg == NULL) {

sys/arch/arm/nxp/imx6_usb.c

179

error = fdtbus_regulator_enable(reg);

sys/arch/arm/nxp/imx6_usbphy.c

133

#define USBPHY_READ(sc, reg) \

sys/arch/arm/nxp/imx6_usbphy.c

134

bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg))

sys/arch/arm/nxp/imx6_usbphy.c

135

#define USBPHY_WRITE(sc, reg, val) \

sys/arch/arm/nxp/imx6_usbphy.c

136

bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))

sys/arch/arm/nxp/imx7_gpc.c

173

const u_int reg = irq / 32;

sys/arch/arm/nxp/imx7_gpc.c

179

GPC_IMRn_COREx(reg, cpu));

sys/arch/arm/nxp/imx7_gpc.c

182

GPC_IMRn_COREx(reg, cpu), val);

sys/arch/arm/nxp/imx7_gpc.c

189

const u_int reg = irq / 32;

sys/arch/arm/nxp/imx7_gpc.c

195

GPC_IMRn_COREx(reg, cpu));

sys/arch/arm/nxp/imx7_gpc.c

198

GPC_IMRn_COREx(reg, cpu), val);

sys/arch/arm/nxp/imx8mq_usbphy.c

102

reg = fdtbus_regulator_acquire(sc->sc_phandle, "vbus-supply");

sys/arch/arm/nxp/imx8mq_usbphy.c

103

if (reg != NULL) {

sys/arch/arm/nxp/imx8mq_usbphy.c

104

error = fdtbus_regulator_enable(reg);

sys/arch/arm/nxp/imx8mq_usbphy.c

70

#define PHY_READ(sc, reg) \

sys/arch/arm/nxp/imx8mq_usbphy.c

71

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/nxp/imx8mq_usbphy.c

72

#define PHY_WRITE(sc, reg, val) \

sys/arch/arm/nxp/imx8mq_usbphy.c

73

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/nxp/imx8mq_usbphy.c

96

struct fdtbus_regulator *reg;

sys/arch/arm/nxp/imx_ccm.h

110

bus_size_t reg;

sys/arch/arm/nxp/imx_ccm.h

136

.u.composite.reg = (_reg), \

sys/arch/arm/nxp/imx_ccm.h

148

bus_size_t reg;

sys/arch/arm/nxp/imx_ccm.h

171

.u.pll.reg = (_reg), \

sys/arch/arm/nxp/imx_ccm.h

226

bus_size_t reg;

sys/arch/arm/nxp/imx_ccm.h

247

.u.mux.reg = (_reg), \

sys/arch/arm/nxp/imx_ccm.h

256

bus_size_t reg;

sys/arch/arm/nxp/imx_ccm.h

278

.u.div.reg = (_reg), \

sys/arch/arm/nxp/imx_ccm.h

346

#define CCM_READ(sc, idx, reg) \

sys/arch/arm/nxp/imx_ccm.h

347

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh[idx], (reg))

sys/arch/arm/nxp/imx_ccm.h

348

#define CCM_WRITE(sc, idx, reg, val) \

sys/arch/arm/nxp/imx_ccm.h

349

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh[idx], (reg), (val))

sys/arch/arm/nxp/imx_ccm.h

77

bus_size_t reg;

sys/arch/arm/nxp/imx_ccm.h

97

.u.gate.reg = (_reg), \

sys/arch/arm/nxp/imx_ccm_composite.c

114

val = CCM_READ(sc, clk->regidx, composite->reg + CCM_TARGET_ROOT);

sys/arch/arm/nxp/imx_ccm_composite.c

154

val = CCM_READ(sc, clk->regidx, composite->reg + CCM_TARGET_ROOT);

sys/arch/arm/nxp/imx_ccm_composite.c

159

CCM_WRITE(sc, clk->regidx, composite->reg + CCM_TARGET_ROOT, val);

sys/arch/arm/nxp/imx_ccm_composite.c

172

const uint32_t val = CCM_READ(sc, clk->regidx, composite->reg + CCM_TARGET_ROOT);

sys/arch/arm/nxp/imx_ccm_composite.c

192

val = CCM_READ(sc, clk->regidx, composite->reg + CCM_TARGET_ROOT);

sys/arch/arm/nxp/imx_ccm_composite.c

195

CCM_WRITE(sc, clk->regidx, composite->reg + CCM_TARGET_ROOT, val);

sys/arch/arm/nxp/imx_ccm_composite.c

56

val = CCM_READ(sc, clk->regidx, composite->reg + CCM_TARGET_ROOT);

sys/arch/arm/nxp/imx_ccm_composite.c

61

CCM_WRITE(sc, clk->regidx, composite->reg + CCM_TARGET_ROOT, val);

sys/arch/arm/nxp/imx_ccm_composite.c

84

const uint32_t val = CCM_READ(sc, clk->regidx, composite->reg + CCM_TARGET_ROOT);

sys/arch/arm/nxp/imx_ccm_div.c

107

val = CCM_READ(sc, clk->regidx, div->reg);

sys/arch/arm/nxp/imx_ccm_div.c

110

CCM_WRITE(sc, clk->regidx, div->reg, val);

sys/arch/arm/nxp/imx_ccm_div.c

59

const uint32_t val = CCM_READ(sc, clk->regidx, div->reg);

sys/arch/arm/nxp/imx_ccm_gate.c

48

val = CCM_READ(sc, clk->regidx, gate->reg);

sys/arch/arm/nxp/imx_ccm_gate.c

53

CCM_WRITE(sc, clk->regidx, gate->reg, val);

sys/arch/arm/nxp/imx_ccm_mux.c

49

const uint32_t val = CCM_READ(sc, clk->regidx, mux->reg);

sys/arch/arm/nxp/imx_ccm_mux.c

69

val = CCM_READ(sc, clk->regidx, mux->reg);

sys/arch/arm/nxp/imx_ccm_mux.c

72

CCM_WRITE(sc, clk->regidx, mux->reg, val);

sys/arch/arm/nxp/imx_ccm_pll.c

58

val = CCM_READ(sc, clk->regidx, pll->reg);

sys/arch/arm/nxp/imx_ccm_pll.c

63

CCM_WRITE(sc, clk->regidx, pll->reg, val);

sys/arch/arm/nxp/imx_ccm_pll.c

91

const uint32_t val = CCM_READ(sc, clk->regidx, pll->reg);

sys/arch/arm/nxp/imxpcie.c

70

#define PCIE_READ(sc, reg) \

sys/arch/arm/nxp/imxpcie.c

71

bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, reg)

sys/arch/arm/nxp/imxpcie.c

72

#define PCIE_WRITE(sc, reg, val) \

sys/arch/arm/nxp/imxpcie.c

73

bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, reg, val)

sys/arch/arm/nxp/imxwdog.c

110

uint16_t reg;

sys/arch/arm/nxp/imxwdog.c

142

reg = wdog_read(sc, IMX_WDOG_WCR);

sys/arch/arm/nxp/imxwdog.c

143

reg &= ~WCR_WT;

sys/arch/arm/nxp/imxwdog.c

144

reg |= __SHIFTIN(sc->sc_wdog_period * 2 - 1, WCR_WT);

sys/arch/arm/nxp/imxwdog.c

145

reg |= WCR_WDE;

sys/arch/arm/nxp/imxwdog.c

146

wdog_write(sc, IMX_WDOG_WCR, reg);

sys/arch/arm/nxp/imxwdog.c

202

uint16_t reg = wdog_read(sc, IMX_WDOG_WCR);

sys/arch/arm/nxp/imxwdog.c

203

reg &= ~WCR_WT;

sys/arch/arm/nxp/imxwdog.c

204

reg |= __SHIFTIN(sc->sc_wdog_period * 2 - 1, WCR_WT);

sys/arch/arm/nxp/imxwdog.c

205

wdog_write(sc, IMX_WDOG_WCR, reg);

sys/arch/arm/nxp/imxwdog.c

228

reg = wdog_read(sc, IMX_WDOG_WCR);

sys/arch/arm/nxp/imxwdog.c

229

reg |= WCR_WDE;

sys/arch/arm/nxp/imxwdog.c

230

wdog_write(sc, IMX_WDOG_WCR, reg);

sys/arch/arm/rockchip/rk3288_iomux.c

127

struct rk3288_iomux_reg *reg)

sys/arch/arm/rockchip/rk3288_iomux.c

134

reg->syscon = sc->sc_pmu;

sys/arch/arm/rockchip/rk3288_iomux.c

135

reg->pull_reg = 0x64 + (idx / 8) * 4;

sys/arch/arm/rockchip/rk3288_iomux.c

136

reg->pull_bit = idx % 8 * 2;

sys/arch/arm/rockchip/rk3288_iomux.c

137

reg->drv_reg = 0x70 + (idx / 8) * 4;

sys/arch/arm/rockchip/rk3288_iomux.c

138

reg->drv_bit = idx % 8 * 2;

sys/arch/arm/rockchip/rk3288_iomux.c

140

reg->syscon = sc->sc_grf;

sys/arch/arm/rockchip/rk3288_iomux.c

141

reg->pull_reg = 0x130 + (bank * 0x10) + (idx / 8) * 4;

sys/arch/arm/rockchip/rk3288_iomux.c

142

reg->pull_bit = idx % 8 * 2;

sys/arch/arm/rockchip/rk3288_iomux.c

143

reg->drv_reg = 0x1b0 + (bank * 0x10) + (idx / 8) * 4;

sys/arch/arm/rockchip/rk3288_iomux.c

144

reg->drv_bit = idx % 8 * 2;

sys/arch/arm/rockchip/rk3288_iomux.c

146

reg->flags = rk3288_iomux_flags[bank][idx / 8];

sys/arch/arm/rockchip/rk3288_iomux.c

147

reg->mux_reg = rk3288_iomux_offset[bank][idx / 8];

sys/arch/arm/rockchip/rk3288_iomux.c

148

if (reg->mux_reg != -1) {

sys/arch/arm/rockchip/rk3288_iomux.c

149

if ((reg->flags & IOMUX_4BIT) == 0) {

sys/arch/arm/rockchip/rk3288_iomux.c

150

reg->mux_bit = idx % 8 * 2;

sys/arch/arm/rockchip/rk3288_iomux.c

152

reg->mux_bit = idx % 4 * 4;

sys/arch/arm/rockchip/rk3288_iomux.c

154

reg->mux_reg += 0x4;

sys/arch/arm/rockchip/rk3288_iomux.c

163

rk3288_iomux_set_bias(struct rk3288_iomux_softc *sc, struct rk3288_iomux_reg *reg,

sys/arch/arm/rockchip/rk3288_iomux.c

183

if (ISPMU(sc, reg)) {

sys/arch/arm/rockchip/rk3288_iomux.c

184

val = RD4(reg, reg->pull_reg);

sys/arch/arm/rockchip/rk3288_iomux.c

185

val &= ~(GPIO_P_CTL_MASK << reg->pull_bit);

sys/arch/arm/rockchip/rk3288_iomux.c

187

val = GPIO_P_CTL_MASK << (reg->pull_bit + 16);

sys/arch/arm/rockchip/rk3288_iomux.c

189

val |= p << reg->pull_bit;

sys/arch/arm/rockchip/rk3288_iomux.c

190

WR4(reg, reg->pull_reg, val);

sys/arch/arm/rockchip/rk3288_iomux.c

195

struct rk3288_iomux_reg *reg, int drv)

sys/arch/arm/rockchip/rk3288_iomux.c

217

if (ISPMU(sc, reg)) {

sys/arch/arm/rockchip/rk3288_iomux.c

218

val = RD4(reg, reg->drv_reg);

sys/arch/arm/rockchip/rk3288_iomux.c

219

val &= ~(GPIO_E_CTL_MASK << reg->drv_bit);

sys/arch/arm/rockchip/rk3288_iomux.c

221

val = GPIO_E_CTL_MASK << (reg->drv_bit + 16);

sys/arch/arm/rockchip/rk3288_iomux.c

223

val = e << reg->drv_bit;

sys/arch/arm/rockchip/rk3288_iomux.c

224

WR4(reg, reg->drv_reg, val);

sys/arch/arm/rockchip/rk3288_iomux.c

229

struct rk3288_iomux_reg *reg, u_int mux)

sys/arch/arm/rockchip/rk3288_iomux.c

233

KASSERT(reg->mux_reg != -1);

sys/arch/arm/rockchip/rk3288_iomux.c

235

const uint32_t mask = (reg->flags & IOMUX_4BIT) ? 0xf : 0x3;

sys/arch/arm/rockchip/rk3288_iomux.c

236

if (ISPMU(sc, reg)) {

sys/arch/arm/rockchip/rk3288_iomux.c

237

val = RD4(reg, reg->mux_reg);

sys/arch/arm/rockchip/rk3288_iomux.c

238

val &= ~(mask << reg->mux_bit);

sys/arch/arm/rockchip/rk3288_iomux.c

240

val = mask << (reg->mux_bit + 16);

sys/arch/arm/rockchip/rk3288_iomux.c

242

val |= mux << reg->mux_bit;

sys/arch/arm/rockchip/rk3288_iomux.c

243

WR4(reg, reg->mux_reg, val);

sys/arch/arm/rockchip/rk3288_iomux.c

247

rk3288_iomux_config(struct rk3288_iomux_softc *sc, struct rk3288_iomux_reg *reg,

sys/arch/arm/rockchip/rk3288_iomux.c

257

reg->syscon == sc->sc_pmu ? "pmu" : "grf",

sys/arch/arm/rockchip/rk3288_iomux.c

258

reg->mux_reg, reg->mux_bit,

sys/arch/arm/rockchip/rk3288_iomux.c

259

reg->pull_reg, reg->pull_bit,

sys/arch/arm/rockchip/rk3288_iomux.c

260

reg->drv_reg, reg->drv_bit,

sys/arch/arm/rockchip/rk3288_iomux.c

261

reg->flags);

sys/arch/arm/rockchip/rk3288_iomux.c

265

LOCK(reg);

sys/arch/arm/rockchip/rk3288_iomux.c

268

rk3288_iomux_set_bias(sc, reg, bias);

sys/arch/arm/rockchip/rk3288_iomux.c

271

rk3288_iomux_set_drive_strength(sc, reg, drv);

sys/arch/arm/rockchip/rk3288_iomux.c

273

if ((reg->flags & IOMUX_NOROUTE) == 0) {

sys/arch/arm/rockchip/rk3288_iomux.c

274

rk3288_iomux_set_mux(sc, reg, mux);

sys/arch/arm/rockchip/rk3288_iomux.c

277

UNLOCK(reg);

sys/arch/arm/rockchip/rk3288_iomux.c

79

#define LOCK(reg) \

sys/arch/arm/rockchip/rk3288_iomux.c

80

syscon_lock((reg)->syscon)

sys/arch/arm/rockchip/rk3288_iomux.c

81

#define UNLOCK(reg) \

sys/arch/arm/rockchip/rk3288_iomux.c

82

syscon_unlock((reg)->syscon)

sys/arch/arm/rockchip/rk3288_iomux.c

83

#define RD4(reg, off) \

sys/arch/arm/rockchip/rk3288_iomux.c

84

syscon_read_4((reg)->syscon, (off))

sys/arch/arm/rockchip/rk3288_iomux.c

85

#define WR4(reg, off, val) \

sys/arch/arm/rockchip/rk3288_iomux.c

86

syscon_write_4((reg)->syscon, (off), (val))

sys/arch/arm/rockchip/rk3288_iomux.c

87

#define ISPMU(sc, reg) \

sys/arch/arm/rockchip/rk3288_iomux.c

88

((reg)->syscon == (sc)->sc_pmu)

sys/arch/arm/rockchip/rk3328_iomux.c

133

#define RD4(sc, reg) \

sys/arch/arm/rockchip/rk3328_iomux.c

134

syscon_read_4((sc)->sc_syscon, (reg))

sys/arch/arm/rockchip/rk3328_iomux.c

135

#define WR4(sc, reg, val) \

sys/arch/arm/rockchip/rk3328_iomux.c

136

syscon_write_4((sc)->sc_syscon, (reg), (val))

sys/arch/arm/rockchip/rk3328_iomux.c

145

rk3328_iomux_calc_iomux_reg(struct rk3328_iomux_softc *sc, u_int bank, u_int pin, bus_size_t *reg, uint32_t *mask)

sys/arch/arm/rockchip/rk3328_iomux.c

151

*reg = banks[bank].iomux[pin / 8].base;

sys/arch/arm/rockchip/rk3328_iomux.c

154

*reg += 0x04;

sys/arch/arm/rockchip/rk3328_iomux.c

182

bus_size_t reg;

sys/arch/arm/rockchip/rk3328_iomux.c

185

rk3328_iomux_calc_iomux_reg(sc, bank, idx, &reg, &mask);

sys/arch/arm/rockchip/rk3328_iomux.c

187

WR4(sc, reg, (mask << 16) | __SHIFTIN(mux, mask));

sys/arch/arm/rockchip/rk3399_cru.c

149

.divs[0] = { .reg = (_reg0), .mask = (_reg0_mask), .val = (_reg0_val) },\

sys/arch/arm/rockchip/rk3399_cru.c

150

.divs[1] = { .reg = (_reg1), .mask = (_reg1_mask), .val = (_reg1_val) },\

sys/arch/arm/rockchip/rk3399_iomux.c

200

#define RD4(syscon, reg) \

sys/arch/arm/rockchip/rk3399_iomux.c

201

syscon_read_4(syscon, (reg))

sys/arch/arm/rockchip/rk3399_iomux.c

202

#define WR4(syscon, reg, val) \

sys/arch/arm/rockchip/rk3399_iomux.c

203

syscon_write_4(syscon, (reg), (val))

sys/arch/arm/rockchip/rk3399_iomux.c

215

bus_size_t reg;

sys/arch/arm/rockchip/rk3399_iomux.c

222

reg = 0x00040 + (0x10 * bank);

sys/arch/arm/rockchip/rk3399_iomux.c

224

reg = 0x0e040 + (0x10 * (bank - 2));

sys/arch/arm/rockchip/rk3399_iomux.c

226

reg += 0x4 * (idx / 8);

sys/arch/arm/rockchip/rk3399_iomux.c

248

printf("%s: bank %d idx %d flags %#x: %08x -> ", __func__, bank, idx, flags, RD4(syscon, reg));

sys/arch/arm/rockchip/rk3399_iomux.c

250

WR4(syscon, reg, bias_val | bias_mask);

sys/arch/arm/rockchip/rk3399_iomux.c

252

printf("%08x (reg %#lx)\n", RD4(syscon, reg), reg);

sys/arch/arm/rockchip/rk3399_iomux.c

270

bus_size_t reg;

sys/arch/arm/rockchip/rk3399_iomux.c

285

reg = 0x00040 + (0x10 * bank) + 0x4 * (idx / 4);

sys/arch/arm/rockchip/rk3399_iomux.c

289

reg = 0x0e100 + 0x4 * (idx / 4);

sys/arch/arm/rockchip/rk3399_iomux.c

297

reg = 0x0e110 + 0x8 * (idx / 4);

sys/arch/arm/rockchip/rk3399_iomux.c

301

reg = 0x0e128;

sys/arch/arm/rockchip/rk3399_iomux.c

311

reg = 0x0e12c;

sys/arch/arm/rockchip/rk3399_iomux.c

315

reg = 0x0e130;

sys/arch/arm/rockchip/rk3399_iomux.c

319

reg = 0x0e138;

sys/arch/arm/rockchip/rk3399_iomux.c

323

reg = 0x0e13c;

sys/arch/arm/rockchip/rk3399_iomux.c

340

printf("%s: bank %d idx %d val %d: %08x -> ", __func__, bank, idx, val, RD4(syscon, reg));

sys/arch/arm/rockchip/rk3399_iomux.c

342

WR4(syscon, reg, write_val | write_mask);

sys/arch/arm/rockchip/rk3399_iomux.c

344

printf("%08x (reg %#lx)\n", RD4(syscon, reg), reg);

sys/arch/arm/rockchip/rk3399_iomux.c

347

reg += 0x4;

sys/arch/arm/rockchip/rk3399_iomux.c

359

bus_size_t reg;

sys/arch/arm/rockchip/rk3399_iomux.c

366

reg = 0x00000 + (0x10 * bank);

sys/arch/arm/rockchip/rk3399_iomux.c

368

reg = 0x0e000 + (0x10 * (bank - 2));

sys/arch/arm/rockchip/rk3399_iomux.c

370

reg += 0x4 * (idx / 8);

sys/arch/arm/rockchip/rk3399_iomux.c

374

printf("%s: bank %d idx %d mux %#x: %08x -> ", __func__, bank, idx, mux, RD4(syscon, reg));

sys/arch/arm/rockchip/rk3399_iomux.c

376

WR4(syscon, reg, (mask << 16) | __SHIFTIN(mux, mask));

sys/arch/arm/rockchip/rk3399_iomux.c

378

printf("%08x (reg %#lx)\n", RD4(syscon, reg), reg);

sys/arch/arm/rockchip/rk3399_pcie.c

119

#define HREAD4(sc, reg) \

sys/arch/arm/rockchip/rk3399_pcie.c

120

bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg))

sys/arch/arm/rockchip/rk3399_pcie.c

121

#define HWRITE4(sc, reg, val) \

sys/arch/arm/rockchip/rk3399_pcie.c

122

bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))

sys/arch/arm/rockchip/rk3399_pcie.c

123

#define AXIPEEK4(sc, reg, valp) \

sys/arch/arm/rockchip/rk3399_pcie.c

124

bus_space_peek_4((sc)->sc_iot, (sc)->sc_axi_ioh, (reg), (valp))

sys/arch/arm/rockchip/rk3399_pcie.c

125

#define AXIPOKE4(sc, reg, val) \

sys/arch/arm/rockchip/rk3399_pcie.c

126

bus_space_poke_4((sc)->sc_iot, (sc)->sc_axi_ioh, (reg), (val))

sys/arch/arm/rockchip/rk3399_pcie.c

579

u_int reg;

sys/arch/arm/rockchip/rk3399_pcie.c

588

reg = (dev << 15) | (fn << 12) | offset;

sys/arch/arm/rockchip/rk3399_pcie.c

591

val = HREAD4(sc, PCIE_RC_NORMAL_BASE + reg);

sys/arch/arm/rockchip/rk3399_pcie.c

601

if (AXIPEEK4(sc, reg, &val) != 0)

sys/arch/arm/rockchip/rk3399_pcie.c

617

u_int reg;

sys/arch/arm/rockchip/rk3399_pcie.c

625

reg = (dev << 15) | (fn << 12) | offset;

sys/arch/arm/rockchip/rk3399_pcie.c

628

HWRITE4(sc, PCIE_RC_NORMAL_BASE + reg, data);

sys/arch/arm/rockchip/rk3399_pcie.c

638

AXIPOKE4(sc, reg, data);

sys/arch/arm/rockchip/rk3588_cru.c

111

.reg = CLKSEL_CON(DSU, 2), \

sys/arch/arm/rockchip/rk3588_cru.c

118

.reg = CLKSEL_CON(DSU, 3), \

sys/arch/arm/rockchip/rk3588_cru.c

196

.reg = CLKSEL_CON(_bigcore, 0), \

sys/arch/arm/rockchip/rk3588_cru.c

205

.reg = CLKSEL_CON(_bigcore, 1), \

sys/arch/arm/rockchip/rk3588_cru.c

78

.reg = CLKSEL_CON(DSU, 6 + (regoff)), \

sys/arch/arm/rockchip/rk3588_cru.c

85

.reg = CLKSEL_CON(DSU, 0), \

sys/arch/arm/rockchip/rk3588_cru.c

98

.reg = CLKSEL_CON(DSU, 1), \

sys/arch/arm/rockchip/rk3588_iomux.c

73

bus_size_t reg;

sys/arch/arm/rockchip/rk3588_iomux.c

78

bus_size_t reg;

sys/arch/arm/rockchip/rk3588_iomux.c

872

bus_size_t reg = rk3588_pull_regmap[pin].reg;

sys/arch/arm/rockchip/rk3588_iomux.c

876

syscon_write_4(sc->sc_grf, reg, val);

sys/arch/arm/rockchip/rk3588_iomux.c

882

reg, val);

sys/arch/arm/rockchip/rk3588_iomux.c

893

bus_size_t reg = rk3588_drive_regmap[pin].reg;

sys/arch/arm/rockchip/rk3588_iomux.c

897

syscon_write_4(sc->sc_grf, reg, val);

sys/arch/arm/rockchip/rk3588_iomux.c

901

rk3588_iomux_pinname(pin), drv, reg, val);

sys/arch/arm/rockchip/rk3588_iomux.c

908

bus_size_t reg = rk3588_iomux_regmap[pin].reg;

sys/arch/arm/rockchip/rk3588_iomux.c

919

syscon_write_4(sc->sc_grf, reg, val);

sys/arch/arm/rockchip/rk3588_iomux.c

923

rk3588_iomux_pinname(pin), mux, reg, val);

sys/arch/arm/rockchip/rk_cru.c

65

const bus_size_t reg = sc->sc_softrst_base + (reset_id / 16) * 4;

sys/arch/arm/rockchip/rk_cru.c

68

CRU_WRITE(sc, reg, (1 << (shift + 16)) | (1 << shift));

sys/arch/arm/rockchip/rk_cru.c

78

const bus_size_t reg = sc->sc_softrst_base + (reset_id / 16) * 4;

sys/arch/arm/rockchip/rk_cru.c

81

CRU_WRITE(sc, reg, (1 << (shift + 16)) | (0 << shift));

sys/arch/arm/rockchip/rk_cru.h

154

bus_size_t reg;

sys/arch/arm/rockchip/rk_cru.h

167

bus_size_t reg;

sys/arch/arm/rockchip/rk_cru.h

202

.u.arm.divs[0].reg = (_reg), \

sys/arch/arm/rockchip/rk_cru.h

236

.u.arm.divs[0].reg = (_div_reg), \

sys/arch/arm/rockchip/rk_cru.h

248

.u.arm.divs[0].reg = (_div0_reg), \

sys/arch/arm/rockchip/rk_cru.h

250

.u.arm.divs[1].reg = (_div1_reg), \

sys/arch/arm/rockchip/rk_cru.h

264

.u.arm.divs[0].reg = (_div0_reg), \

sys/arch/arm/rockchip/rk_cru.h

266

.u.arm.divs[1].reg = (_div1_reg), \

sys/arch/arm/rockchip/rk_cru.h

268

.u.arm.divs[2].reg = (_div2_reg), \

sys/arch/arm/rockchip/rk_cru.h

270

.u.arm.divs[3].reg = (_div3_reg), \

sys/arch/arm/rockchip/rk_cru.h

345

bus_size_t reg;

sys/arch/arm/rockchip/rk_cru.h

362

.u.gate.reg = (_reg), \

sys/arch/arm/rockchip/rk_cru.h

380

bus_size_t reg;

sys/arch/arm/rockchip/rk_cru.h

399

.u.mux.reg = (_reg), \

sys/arch/arm/rockchip/rk_cru.h

466

#define CRU_READ(sc, reg) \

sys/arch/arm/rockchip/rk_cru.h

467

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/rockchip/rk_cru.h

468

#define CRU_WRITE(sc, reg, val) \

sys/arch/arm/rockchip/rk_cru.h

469

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/rockchip/rk_cru_arm.c

103

if (arm->divs[i].reg == 0 && arm->divs[i].mask == 0)

sys/arch/arm/rockchip/rk_cru_arm.c

109

CRU_WRITE(sc, arm->divs[i].reg, write_mask | write_val);

sys/arch/arm/rockchip/rk_cru_arm.c

158

if (cpu_rate->divs[i].reg == 0 && cpu_rate->divs[i].mask == 0 &&

sys/arch/arm/rockchip/rk_cru_arm.c

164

CRU_WRITE(sc, cpu_rate->divs[i].reg, write_mask | write_val);

sys/arch/arm/rockchip/rk_cru_arm.c

168

if (arm->divs[i].reg == 0 && arm->divs[i].mask == 0)

sys/arch/arm/rockchip/rk_cru_arm.c

173

CRU_WRITE(sc, arm->divs[i].reg, write_mask | write_val);

sys/arch/arm/rockchip/rk_cru_arm.c

57

const uint32_t val = CRU_READ(sc, arm->divs[0].reg);

sys/arch/arm/rockchip/rk_cru_gate.c

50

CRU_WRITE(sc, gate->reg, write_mask | write_val);

sys/arch/arm/rockchip/rk_cru_mux.c

53

val = syscon_read_4(sc->sc_grf, mux->reg);

sys/arch/arm/rockchip/rk_cru_mux.c

56

val = CRU_READ(sc, mux->reg);

sys/arch/arm/rockchip/rk_cru_mux.c

82

syscon_write_4(sc->sc_grf, mux->reg, write_mask | write_val);

sys/arch/arm/rockchip/rk_cru_mux.c

85

CRU_WRITE(sc, mux->reg, write_mask | write_val);

sys/arch/arm/rockchip/rk_emmcphy.c

103

#define RD4(sc, reg) \

sys/arch/arm/rockchip/rk_emmcphy.c

104

syscon_read_4((sc)->sc_syscon, (sc)->sc_regbase + (reg))

sys/arch/arm/rockchip/rk_emmcphy.c

105

#define WR4(sc, reg, val) \

sys/arch/arm/rockchip/rk_emmcphy.c

106

syscon_write_4((sc)->sc_syscon, (sc)->sc_regbase + (reg), (val))

sys/arch/arm/rockchip/rk_gpio.c

112

#define RD4(sc, reg) \

sys/arch/arm/rockchip/rk_gpio.c

113

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/rockchip/rk_gpio.c

114

#define WR4(sc, reg, val) \

sys/arch/arm/rockchip/rk_gpio.c

115

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/rockchip/rk_i2c.c

124

#define RD4(sc, reg) \

sys/arch/arm/rockchip/rk_i2c.c

125

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/rockchip/rk_i2c.c

126

#define WR4(sc, reg, val) \

sys/arch/arm/rockchip/rk_i2c.c

127

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/rockchip/rk_i2s.c

164

#define RD4(sc, reg) \

sys/arch/arm/rockchip/rk_i2s.c

165

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/rockchip/rk_i2s.c

166

#define WR4(sc, reg, val) \

sys/arch/arm/rockchip/rk_i2s.c

167

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/rockchip/rk_pwm.c

82

#define PWM_READ(sc, reg) \

sys/arch/arm/rockchip/rk_pwm.c

83

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/rockchip/rk_pwm.c

84

#define PWM_WRITE(sc, reg, val) \

sys/arch/arm/rockchip/rk_pwm.c

85

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/rockchip/rk_spi.c

166

#define SPIREG_READ(sc, reg) \

sys/arch/arm/rockchip/rk_spi.c

167

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/rockchip/rk_spi.c

168

#define SPIREG_WRITE(sc, reg, val) \

sys/arch/arm/rockchip/rk_spi.c

169

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/rockchip/rk_spi.c

381

uint32_t reg;

sys/arch/arm/rockchip/rk_spi.c

388

reg = SPIREG_READ(sc, SPI_RXFLR);

sys/arch/arm/rockchip/rk_spi.c

389

avail = __SHIFTOUT(reg, SPI_RXFLR_RXFLR);

sys/arch/arm/rockchip/rk_spi.c

395

reg = SPIREG_READ(sc, SPI_TXFLR);

sys/arch/arm/rockchip/rk_spi.c

396

avail = SPI_FIFOLEN - __SHIFTOUT(reg, SPI_TXFLR_TXFLR);

sys/arch/arm/rockchip/rk_tcphy.c

100

(bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)))

sys/arch/arm/rockchip/rk_tcphy.c

101

#define HWRITE4(sc, reg, val) \

sys/arch/arm/rockchip/rk_tcphy.c

102

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/rockchip/rk_tcphy.c

103

#define HSET4(sc, reg, bits) \

sys/arch/arm/rockchip/rk_tcphy.c

104

HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))

sys/arch/arm/rockchip/rk_tcphy.c

105

#define HCLR4(sc, reg, bits) \

sys/arch/arm/rockchip/rk_tcphy.c

106

HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))

sys/arch/arm/rockchip/rk_tcphy.c

262

uint32_t reg;

sys/arch/arm/rockchip/rk_tcphy.c

266

reg = syscon_read_4(sc->sc_grf, GRF_USB3PHY_CON0(sc->sc_phy_ctrl_id));

sys/arch/arm/rockchip/rk_tcphy.c

268

reg |= USB3PHY_CON0_USB2_ONLY;

sys/arch/arm/rockchip/rk_tcphy.c

270

reg &= ~USB3PHY_CON0_USB2_ONLY;

sys/arch/arm/rockchip/rk_tcphy.c

272

reg |= (USB3PHY_CON0_USB2_ONLY) << 16;

sys/arch/arm/rockchip/rk_tcphy.c

273

syscon_write_4(sc->sc_grf, GRF_USB3PHY_CON0(sc->sc_phy_ctrl_id), reg);

sys/arch/arm/rockchip/rk_tcphy.c

276

reg = syscon_read_4(sc->sc_grf, GRF_USB3OTG_CON1(sc->sc_phy_ctrl_id));

sys/arch/arm/rockchip/rk_tcphy.c

278

reg |= USB3OTG_CON1_U3_DIS;

sys/arch/arm/rockchip/rk_tcphy.c

280

reg &= ~USB3OTG_CON1_U3_DIS;

sys/arch/arm/rockchip/rk_tcphy.c

282

reg |= (USB3OTG_CON1_U3_DIS) << 16;

sys/arch/arm/rockchip/rk_tcphy.c

283

syscon_write_4(sc->sc_grf, GRF_USB3OTG_CON1(sc->sc_phy_ctrl_id), reg);

sys/arch/arm/rockchip/rk_tcphy.c

291

uint32_t reg;

sys/arch/arm/rockchip/rk_tcphy.c

312

reg = HREAD4(sc, CMN_DIAG_HSCLK_SEL);

sys/arch/arm/rockchip/rk_tcphy.c

313

reg &= ~CMN_DIAG_HSCLK_SEL_PLL_MASK;

sys/arch/arm/rockchip/rk_tcphy.c

314

reg |= CMN_DIAG_HSCLK_SEL_PLL_CONFIG;

sys/arch/arm/rockchip/rk_tcphy.c

315

HWRITE4(sc, CMN_DIAG_HSCLK_SEL, reg);

sys/arch/arm/rockchip/rk_tcphy.c

359

reg = HREAD4(sc, PMA_CMN_CTRL1);

sys/arch/arm/rockchip/rk_tcphy.c

360

if (reg & PMA_CMN_CTRL1_READY)

sys/arch/arm/rockchip/rk_tcphy.c

99

#define HREAD4(sc, reg) \

sys/arch/arm/rockchip/rk_tsadc.c

452

#define TSADC_READ(sc, reg) \

sys/arch/arm/rockchip/rk_tsadc.c

453

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/rockchip/rk_tsadc.c

454

#define TSADC_WRITE(sc, reg, val) \

sys/arch/arm/rockchip/rk_tsadc.c

455

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/rockchip/rk_usb.c

121

uint32_t reg, write_mask, write_val;

sys/arch/arm/rockchip/rk_usb.c

125

reg = RK3328_CON2_REG;

sys/arch/arm/rockchip/rk_usb.c

130

reg = RK3399_PHY_NO(sc) == 0 ?

sys/arch/arm/rockchip/rk_usb.c

141

syscon_write_4(sc->sc_syscon, reg, write_mask | write_val);

sys/arch/arm/rockchip/rk_usb.c

151

uint32_t reg, write_mask, write_val;

sys/arch/arm/rockchip/rk_usb.c

155

reg = RK3328_CON2_REG;

sys/arch/arm/rockchip/rk_usb.c

160

reg = RK3399_PHY_NO(sc) == 0 ?

sys/arch/arm/rockchip/rk_usb.c

171

syscon_write_4(sc->sc_syscon, reg, write_mask | write_val);

sys/arch/arm/rockchip/rk_usb.c

303

uint32_t reg, write_mask, write_val;

sys/arch/arm/rockchip/rk_usb.c

308

reg = RK3328_CON0_REG;

sys/arch/arm/rockchip/rk_usb.c

313

reg = RK3399_PHY_NO(usb_sc) == 0 ?

sys/arch/arm/rockchip/rk_usb.c

331

syscon_write_4(usb_sc->sc_syscon, reg, write_mask | write_val);

sys/arch/arm/rockchip/rk_usb.c

342

uint32_t reg, write_mask, write_val;

sys/arch/arm/rockchip/rk_usb.c

347

reg = RK3328_CON1_REG;

sys/arch/arm/rockchip/rk_usb.c

352

reg = RK3399_PHY_NO(usb_sc) == 0 ?

sys/arch/arm/rockchip/rk_usb.c

370

syscon_write_4(usb_sc->sc_syscon, reg, write_mask | write_val);

sys/arch/arm/rockchip/rk_v1crypto.c

77

RKC_READ(struct rk_v1crypto_softc *sc, bus_addr_t reg)

sys/arch/arm/rockchip/rk_v1crypto.c

79

return bus_space_read_4(sc->sc_bst, sc->sc_bsh, reg);

sys/arch/arm/rockchip/rk_v1crypto.c

83

RKC_WRITE(struct rk_v1crypto_softc *sc, bus_addr_t reg, uint32_t v)

sys/arch/arm/rockchip/rk_v1crypto.c

85

bus_space_write_4(sc->sc_bst, sc->sc_bsh, reg, v);

sys/arch/arm/rockchip/rk_vop.c

184

#define RD4(sc, reg) \

sys/arch/arm/rockchip/rk_vop.c

185

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/rockchip/rk_vop.c

186

#define WR4(sc, reg, val) \

sys/arch/arm/rockchip/rk_vop.c

187

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/rockchip/rk_vop.c

190

WR4_MASK(struct rk_vop_softc *sc, bus_size_t reg, uint16_t mask, uint16_t val)

sys/arch/arm/rockchip/rk_vop.c

194

WR4(sc, reg, ((uint32_t)mask << 16) | val);

sys/arch/arm/s3c2xx0/s3c2410_intr.c

348

uint32_t reg;

sys/arch/arm/s3c2xx0/s3c2410_intr.c

358

reg = bus_space_read_4(s3c2xx0_softc->sc_iot,

sys/arch/arm/s3c2xx0/s3c2410_intr.c

362

reg = reg & ~(0x07 << (4*i));

sys/arch/arm/s3c2xx0/s3c2410_intr.c

363

reg |= trig << (4*i);

sys/arch/arm/s3c2xx0/s3c2410_intr.c

366

GPIO_EXTINT(regidx), reg);

sys/arch/arm/s3c2xx0/s3c2440_dma.c

363

uint32_t reg;

sys/arch/arm/s3c2xx0/s3c2440_dma.c

375

reg = bus_space_read_4(sc->sc_iot, sc->sc_dmach, DMA_STAT(channel_no));

sys/arch/arm/s3c2xx0/s3c2440_dma.c

376

if (reg & DMASTAT_BUSY)

sys/arch/arm/s3c2xx0/s3c2440_dma.c

465

uint32_t reg, transfer_size;

sys/arch/arm/s3c2xx0/s3c2440_dma.c

477

reg = 0;

sys/arch/arm/s3c2xx0/s3c2440_dma.c

479

reg |= DISRCC_LOC_APB;

sys/arch/arm/s3c2xx0/s3c2440_dma.c

481

reg |= DISRCC_LOC_AHB;

sys/arch/arm/s3c2xx0/s3c2440_dma.c

484

reg |= DISRCC_INC_INC;

sys/arch/arm/s3c2xx0/s3c2440_dma.c

486

reg |= DISRCC_INC_FIXED;

sys/arch/arm/s3c2xx0/s3c2440_dma.c

488

bus_space_write_4(sc->sc_iot, sc->sc_dmach, DMA_DISRCC(channel_no), reg);

sys/arch/arm/s3c2xx0/s3c2440_dma.c

494

reg = 0;

sys/arch/arm/s3c2xx0/s3c2440_dma.c

496

reg |= DIDSTC_LOC_APB;

sys/arch/arm/s3c2xx0/s3c2440_dma.c

498

reg |= DIDSTC_LOC_AHB;

sys/arch/arm/s3c2xx0/s3c2440_dma.c

501

reg |= DIDSTC_INC_INC;

sys/arch/arm/s3c2xx0/s3c2440_dma.c

503

reg |= DIDSTC_INC_FIXED;

sys/arch/arm/s3c2xx0/s3c2440_dma.c

505

bus_space_write_4(sc->sc_iot, sc->sc_dmach, DMA_DIDSTC(channel_no), reg);

sys/arch/arm/s3c2xx0/s3c2440_dma.c

538

reg = DMAMASKTRIG_ON;

sys/arch/arm/s3c2xx0/s3c2440_dma.c

540

reg |= DMAMASKTRIG_SW_TRIG;

sys/arch/arm/s3c2xx0/s3c2440_dma.c

543

reg);

sys/arch/arm/s3c2xx0/s3c2440_dma.c

546

reg = bus_space_read_4(sc->sc_iot, sc->sc_dmach, DMA_DISRC(channel_no));

sys/arch/arm/s3c2xx0/s3c2440_dma.c

547

printf("DMA_DISRC: 0x%X\n", reg);

sys/arch/arm/s3c2xx0/s3c2440_dma.c

549

reg = bus_space_read_4(sc->sc_iot, sc->sc_dmach, DMA_DISRCC(channel_no));

sys/arch/arm/s3c2xx0/s3c2440_dma.c

550

printf("DMA_DISRCC: 0x%X\n", reg);

sys/arch/arm/s3c2xx0/s3c2440_dma.c

552

reg = bus_space_read_4(sc->sc_iot, sc->sc_dmach, DMA_DIDST(channel_no));

sys/arch/arm/s3c2xx0/s3c2440_dma.c

553

printf("DMA_DIDST: 0x%X\n", reg);

sys/arch/arm/s3c2xx0/s3c2440_dma.c

555

reg = bus_space_read_4(sc->sc_iot, sc->sc_dmach, DMA_DIDSTC(channel_no));

sys/arch/arm/s3c2xx0/s3c2440_dma.c

556

printf("DMA_DIDSTC: 0x%X\n", reg);

sys/arch/arm/s3c2xx0/s3c2440_dma.c

558

reg = bus_space_read_4(sc->sc_iot, sc->sc_dmach, DMA_CON(channel_no));

sys/arch/arm/s3c2xx0/s3c2440_dma.c

559

printf("DMA_CON: 0x%X\n", reg);

sys/arch/arm/s3c2xx0/s3c2440_dma.c

561

reg = bus_space_read_4(sc->sc_iot, sc->sc_dmach, DMA_MASKTRIG(channel_no));

sys/arch/arm/s3c2xx0/s3c2440_dma.c

562

printf("DMA_MASKTRIG: 0x%X\n", reg);

sys/arch/arm/s3c2xx0/s3c2440_dma.c

564

reg = bus_space_read_4(sc->sc_iot, sc->sc_dmach, DMA_STAT(channel_no));

sys/arch/arm/s3c2xx0/s3c2440_dma.c

565

printf("DMA_STAT: 0x%X\n", reg);

sys/arch/arm/s3c2xx0/s3c2440_dma.c

650

uint32_t reg;

sys/arch/arm/s3c2xx0/s3c2440_dma.c

655

reg = bus_space_read_4(sc->sc_iot, sc->sc_dmach,

sys/arch/arm/s3c2xx0/s3c2440_dma.c

657

DPRINTF(("s3c2440_dma: channel %d mask trigger %x\n", dxs->dxs_channel, reg));

sys/arch/arm/s3c2xx0/s3c2440_dma.c

659

if ( !(reg & DMAMASKTRIG_ON) ) {

sys/arch/arm/s3c2xx0/s3c2440_i2s.c

131

uint32_t reg;

sys/arch/arm/s3c2xx0/s3c2440_i2s.c

147

reg = bus_space_read_4(sc->sc_iot, sc->sc_clkman_ioh, CLKMAN_CLKCON);

sys/arch/arm/s3c2xx0/s3c2440_i2s.c

148

bus_space_write_4(sc->sc_iot, sc->sc_clkman_ioh, CLKMAN_CLKCON, reg | CLKCON_IIS);

sys/arch/arm/s3c2xx0/s3c2440_i2s.c

151

reg = bus_space_read_4(sc->sc_iot, sc->sc_gpio_ioh, GPIO_PECON);

sys/arch/arm/s3c2xx0/s3c2440_i2s.c

152

reg = GPIO_SET_FUNC(reg, 0, 2);

sys/arch/arm/s3c2xx0/s3c2440_i2s.c

153

reg = GPIO_SET_FUNC(reg, 1, 2);

sys/arch/arm/s3c2xx0/s3c2440_i2s.c

154

reg = GPIO_SET_FUNC(reg, 2, 2);

sys/arch/arm/s3c2xx0/s3c2440_i2s.c

155

reg = GPIO_SET_FUNC(reg, 3, 2);

sys/arch/arm/s3c2xx0/s3c2440_i2s.c

156

reg = GPIO_SET_FUNC(reg, 4, 2);

sys/arch/arm/s3c2xx0/s3c2440_i2s.c

157

bus_space_write_4(sc->sc_iot, sc->sc_gpio_ioh, GPIO_PECON, reg);

sys/arch/arm/s3c2xx0/s3c2440_i2s.c

160

reg = bus_space_read_4(sc->sc_iot, sc->sc_gpio_ioh, GPIO_PEUP);

sys/arch/arm/s3c2xx0/s3c2440_i2s.c

162

reg = GPIO_SET_DATA(reg, 0, 1);

sys/arch/arm/s3c2xx0/s3c2440_i2s.c

163

reg = GPIO_SET_DATA(reg, 1, 1);

sys/arch/arm/s3c2xx0/s3c2440_i2s.c

164

reg = GPIO_SET_DATA(reg, 2, 1);

sys/arch/arm/s3c2xx0/s3c2440_i2s.c

165

reg = GPIO_SET_DATA(reg, 3, 1);

sys/arch/arm/s3c2xx0/s3c2440_i2s.c

166

reg = GPIO_SET_DATA(reg, 4, 1);

sys/arch/arm/s3c2xx0/s3c2440_i2s.c

168

bus_space_write_4(sc->sc_iot, sc->sc_gpio_ioh, GPIO_PEUP, reg);

sys/arch/arm/s3c2xx0/s3c2440_intr.c

380

uint32_t reg;

sys/arch/arm/s3c2xx0/s3c2440_intr.c

392

reg = bus_space_read_4(s3c2xx0_softc->sc_iot,

sys/arch/arm/s3c2xx0/s3c2440_intr.c

396

reg = reg & ~(0x07 << (4*i));

sys/arch/arm/s3c2xx0/s3c2440_intr.c

397

reg |= trig << (4*i);

sys/arch/arm/s3c2xx0/s3c2440_intr.c

400

GPIO_EXTINT(regidx), reg);

sys/arch/arm/s3c2xx0/s3c2440_intr.c

410

reg = bus_space_read_4(s3c2xx0_softc->sc_iot, s3c2xx0_softc->sc_gpio_ioh,

sys/arch/arm/s3c2xx0/s3c2440_intr.c

412

reg = GPIO_SET_FUNC(reg, offset, 2);

sys/arch/arm/s3c2xx0/s3c2440_intr.c

414

gpio, reg);

sys/arch/arm/s3c2xx0/s3c2440_rtc.c

105

uint8_t reg;

sys/arch/arm/s3c2xx0/s3c2440_rtc.c

107

reg = bus_space_read_1(sc->sc_iot, sc->sc_ioh, RTC_BCDSEC);

sys/arch/arm/s3c2xx0/s3c2440_rtc.c

108

DPRINTF(("BCDSEC: %02X\n", reg));

sys/arch/arm/s3c2xx0/s3c2440_rtc.c

109

dt->dt_sec = bcdtobin(reg);

sys/arch/arm/s3c2xx0/s3c2440_rtc.c

111

reg = bus_space_read_1(sc->sc_iot, sc->sc_ioh, RTC_BCDMIN);

sys/arch/arm/s3c2xx0/s3c2440_rtc.c

112

DPRINTF(("BCDMIN: %02X\n", reg));

sys/arch/arm/s3c2xx0/s3c2440_rtc.c

113

dt->dt_min = bcdtobin(reg);

sys/arch/arm/s3c2xx0/s3c2440_rtc.c

115

reg = bus_space_read_1(sc->sc_iot, sc->sc_ioh, RTC_BCDHOUR);

sys/arch/arm/s3c2xx0/s3c2440_rtc.c

116

DPRINTF(("BCDHOUR: %02X\n", reg));

sys/arch/arm/s3c2xx0/s3c2440_rtc.c

117

dt->dt_hour = bcdtobin(reg);

sys/arch/arm/s3c2xx0/s3c2440_rtc.c

119

reg = bus_space_read_1(sc->sc_iot, sc->sc_ioh, RTC_BCDDATE);

sys/arch/arm/s3c2xx0/s3c2440_rtc.c

120

DPRINTF(("BCDDATE: %02X\n", reg));

sys/arch/arm/s3c2xx0/s3c2440_rtc.c

121

dt->dt_day = bcdtobin(reg);

sys/arch/arm/s3c2xx0/s3c2440_rtc.c

123

reg = bus_space_read_1(sc->sc_iot, sc->sc_ioh, RTC_BCDDAY);

sys/arch/arm/s3c2xx0/s3c2440_rtc.c

124

DPRINTF(("BCDDAY: %02X\n", reg));

sys/arch/arm/s3c2xx0/s3c2440_rtc.c

125

dt->dt_wday = bcdtobin(reg);

sys/arch/arm/s3c2xx0/s3c2440_rtc.c

127

reg = bus_space_read_1(sc->sc_iot, sc->sc_ioh, RTC_BCDMON);

sys/arch/arm/s3c2xx0/s3c2440_rtc.c

128

DPRINTF(("BCDMON: %02X\n", reg));

sys/arch/arm/s3c2xx0/s3c2440_rtc.c

129

dt->dt_mon = bcdtobin(reg);

sys/arch/arm/s3c2xx0/s3c2440_rtc.c

131

reg = bus_space_read_1(sc->sc_iot, sc->sc_ioh, RTC_BCDYEAR);

sys/arch/arm/s3c2xx0/s3c2440_rtc.c

132

DPRINTF(("BCDYEAR: %02X\n", reg));

sys/arch/arm/s3c2xx0/s3c2440_rtc.c

133

dt->dt_year = SSRTC_YEAR_ZERO + bcdtobin(reg);

sys/arch/arm/s3c2xx0/s3c2440_rtc.c

150

uint8_t reg;

sys/arch/arm/s3c2xx0/s3c2440_rtc.c

155

reg = bus_space_read_1(sc->sc_iot, sc->sc_ioh, RTC_RTCCON);

sys/arch/arm/s3c2xx0/s3c2440_rtc.c

156

bus_space_write_1(sc->sc_iot, sc->sc_ioh, RTC_RTCCON, reg | RTCCON_RTCEN);

sys/arch/arm/s3c2xx0/s3c2440_rtc.c

167

reg = bus_space_read_1(sc->sc_iot, sc->sc_ioh, RTC_RTCCON);

sys/arch/arm/s3c2xx0/s3c2440_rtc.c

168

bus_space_write_1(sc->sc_iot, sc->sc_ioh, RTC_RTCCON, reg & ~RTCCON_RTCEN);

sys/arch/arm/s3c2xx0/s3c2440_spi.c

285

uint32_t reg;

sys/arch/arm/s3c2xx0/s3c2440_spi.c

287

reg = bus_space_read_4(sc->iot, sc->ioh, SPI_SPSTA);

sys/arch/arm/s3c2xx0/s3c2440_spi.c

288

} while(! (reg & SPSTA_REDY));

sys/arch/arm/s3c2xx0/s3c2440_spi.c

295

uint32_t reg;

sys/arch/arm/s3c2xx0/s3c2440_spi.c

297

reg = bus_space_read_4(sc->iot, sc->ioh, SPI_SPSTA);

sys/arch/arm/s3c2xx0/s3c2440_spi.c

298

} while(!(reg & SPSTA_REDY));

sys/arch/arm/s3c2xx0/s3c2440_spi.c

337

uint32_t reg;

sys/arch/arm/s3c2xx0/s3c2440_spi.c

342

reg = bus_space_read_4(sc->iot, sc->ioh, SPI_SPSTA);

sys/arch/arm/s3c2xx0/s3c2440_spi.c

343

if (reg & SPSTA_REDY) {

sys/arch/arm/s3c2xx0/s3c2440_touch.c

171

uint32_t reg;

sys/arch/arm/s3c2xx0/s3c2440_touch.c

176

reg = bus_space_read_4(sc->iot, sc->ioh, ADC_ADCUPDN);

sys/arch/arm/s3c2xx0/s3c2440_touch.c

178

if( sc->next_stylus_intr == STYLUS_DOWN && (reg & ADCUPDN_TSC_DN) ) {

sys/arch/arm/s3c2xx0/s3c2440_touch.c

183

} else if (sc->next_stylus_intr == STYLUS_UP && (reg & ADCUPDN_TSC_UP)) {

sys/arch/arm/s3c2xx0/s3c2440_touch.c

207

uint32_t reg;

sys/arch/arm/s3c2xx0/s3c2440_touch.c

211

reg = bus_space_read_4(sc->iot, sc->ioh, ADC_ADCDAT0);

sys/arch/arm/s3c2xx0/s3c2440_touch.c

212

y = reg & ADCDAT_DATAMASK;

sys/arch/arm/s3c2xx0/s3c2440_touch.c

214

reg = bus_space_read_4(sc->iot, sc->ioh, ADC_ADCDAT1);

sys/arch/arm/s3c2xx0/s3c2440_touch.c

215

x = reg & ADCDAT_DATAMASK;

sys/arch/arm/s3c2xx0/s3c2440_touch.c

303

uint32_t reg;

sys/arch/arm/s3c2xx0/s3c2440_touch.c

309

reg = bus_space_read_4(sc->iot, sc->ioh, ADC_ADCCON);

sys/arch/arm/s3c2xx0/s3c2440_touch.c

311

reg | ADCCON_ENABLE_START);

sys/arch/arm/s3c2xx0/s3c2440reg.h

335

#define SDIDATCNT_BLK_CNT(reg) (reg & SDIDATCON_BLKNUM_MASK)

sys/arch/arm/s3c2xx0/s3c2440reg.h

338

#define SDIDATCNT_BLK_NUM_CNT(reg) ( (reg & SDIDATCNT_BLK_NUM_CNT_MASK) >> SDIDATCNT_BLK_NUM_CNT_SHIFT)

sys/arch/arm/s3c2xx0/s3c2440reg.h

352

#define SDIDATFSTA_FFCNT(reg) (reg & SDIDATFSTA_FFCNT_MASK)

sys/arch/arm/s3c2xx0/s3c24x0_clk.c

223

uint32_t reg;

sys/arch/arm/s3c2xx0/s3c24x0_clk.c

267

reg = bus_space_read_4(iot, ioh, TIMER_TCFG0);

sys/arch/arm/s3c2xx0/s3c24x0_clk.c

269

(reg & ~0xff00) | ((prescaler-1) << 8));

sys/arch/arm/s3c2xx0/s3c24x0_clk.c

272

reg = bus_space_read_4(iot, ioh, TIMER_TCFG1);

sys/arch/arm/s3c2xx0/s3c24x0_clk.c

274

(reg & ~(TCFG1_MUX_MASK(3)|TCFG1_MUX_MASK(4))) |

sys/arch/arm/s3c2xx0/s3c24x0_clk.c

280

reg = bus_space_read_4(iot, ioh, TIMER_TCON);

sys/arch/arm/s3c2xx0/s3c24x0_clk.c

281

reg &= ~(TCON_MASK(3)|TCON_MASK(4));

sys/arch/arm/s3c2xx0/s3c24x0_clk.c

286

bus_space_write_4(iot, ioh, TIMER_TCON, reg |

sys/arch/arm/s3c2xx0/s3c24x0_clk.c

289

bus_space_write_4(iot, ioh, TIMER_TCON, reg |

sys/arch/arm/s3c2xx0/s3c24x0_lcd.c

113

reg = (info->lcdcon1 & ~LCDCON1_CLKVAL_MASK) |

sys/arch/arm/s3c2xx0/s3c24x0_lcd.c

115

reg &= ~LCDCON1_ENVID;

sys/arch/arm/s3c2xx0/s3c24x0_lcd.c

116

bus_space_write_4(iot, ioh, LCDC_LCDCON1, reg);

sys/arch/arm/s3c2xx0/s3c24x0_lcd.c

120

hclk, info->pixel_clock, clkval, reg);

sys/arch/arm/s3c2xx0/s3c24x0_lcd.c

296

uint32_t reg;

sys/arch/arm/s3c2xx0/s3c24x0_lcd.c

298

reg = bus_space_read_4(iot, ioh, LCDC_LCDCON5);

sys/arch/arm/s3c2xx0/s3c24x0_lcd.c

301

reg |= LCDCON5_PWREN;

sys/arch/arm/s3c2xx0/s3c24x0_lcd.c

303

reg &= ~LCDCON5_PWREN;

sys/arch/arm/s3c2xx0/s3c24x0_lcd.c

305

bus_space_write_4(iot, ioh, LCDC_LCDCON5, reg);

sys/arch/arm/s3c2xx0/s3c24x0_lcd.c

98

uint32_t reg;

sys/arch/arm/s3c2xx0/s3c2800_intr.c

157

uint32_t reg;

sys/arch/arm/s3c2xx0/s3c2800_intr.c

162

reg = bus_space_read_4(s3c2xx0_softc->sc_iot,

sys/arch/arm/s3c2xx0/s3c2800_intr.c

166

reg = reg & ~(0x0f << (4*irqno));

sys/arch/arm/s3c2xx0/s3c2800_intr.c

167

reg |= trig << (4*irqno);

sys/arch/arm/s3c2xx0/s3c2800_intr.c

170

GPIO_EXTINTR, reg);

sys/arch/arm/s3c2xx0/s3c2800_pci.c

653

pcireg_t reg;

sys/arch/arm/s3c2xx0/s3c2800_pci.c

657

reg = bus_space_read_4(iot, ioh, i);

sys/arch/arm/s3c2xx0/s3c2800_pci.c

658

printf("%03x: %08x\n", i, reg);

sys/arch/arm/s3c2xx0/s3c2800_pci.c

661

reg = bus_space_read_4(iot, ioh, i);

sys/arch/arm/s3c2xx0/s3c2800_pci.c

662

printf("%03x: %08x\n", i, reg);

sys/arch/arm/sa11x0/sa11x0_com.c

943

int reg;

sys/arch/arm/sa11x0/sa11x0_com.c

948

reg = 0xffff;

sys/arch/arm/sa11x0/sa11x0_com.c

956

reg =

sys/arch/arm/sa11x0/sa11x0_com.c

973

aprint_debug_dev(sc->sc_dev, "sacom_iflush timeout %02x\n", reg);

sys/arch/arm/sa11x0/sa11x1_pcic.c

123

sacpcic_read(struct sapcic_socket *so, int reg)

sys/arch/arm/sa11x0/sa11x1_pcic.c

130

switch (reg) {

sys/arch/arm/sa11x0/sa11x1_pcic.c

156

sacpcic_write(struct sapcic_socket *so, int reg, int arg)

sys/arch/arm/sa11x0/sa11x1_pcic.c

164

switch (reg) {

sys/arch/arm/samsung/exynos5410_clock.c

197

.reg = (_reg), \

sys/arch/arm/samsung/exynos5410_clock.c

215

.reg = (_reg), \

sys/arch/arm/samsung/exynos5410_clock.c

230

.reg = (_reg), \

sys/arch/arm/samsung/exynos5410_clock.c

467

#define CLOCK_READ(sc, reg) \

sys/arch/arm/samsung/exynos5410_clock.c

468

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/samsung/exynos5410_clock.c

469

#define CLOCK_WRITE(sc, reg, val) \

sys/arch/arm/samsung/exynos5410_clock.c

470

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/samsung/exynos5410_clock.c

753

uint32_t v = CLOCK_READ(sc, emux->reg);

sys/arch/arm/samsung/exynos5410_clock.c

756

CLOCK_WRITE(sc, emux->reg, v);

sys/arch/arm/samsung/exynos5410_clock.c

769

const uint32_t v = CLOCK_READ(sc, emux->reg);

sys/arch/arm/samsung/exynos5410_clock.c

789

const uint32_t v = CLOCK_READ(sc, ediv->reg);

sys/arch/arm/samsung/exynos5410_clock.c

819

uint32_t v = CLOCK_READ(sc, ediv->reg);

sys/arch/arm/samsung/exynos5410_clock.c

822

CLOCK_WRITE(sc, ediv->reg, v);

sys/arch/arm/samsung/exynos5410_clock.c

835

uint32_t v = CLOCK_READ(sc, egate->reg);

sys/arch/arm/samsung/exynos5410_clock.c

841

CLOCK_WRITE(sc, egate->reg, v);

sys/arch/arm/samsung/exynos5422_clock.c

300

.reg = (_reg), \

sys/arch/arm/samsung/exynos5422_clock.c

317

.reg = (_reg), \

sys/arch/arm/samsung/exynos5422_clock.c

329

.reg = (_reg), \

sys/arch/arm/samsung/exynos5422_clock.c

599

#define CLOCK_READ(sc, reg) \

sys/arch/arm/samsung/exynos5422_clock.c

600

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/samsung/exynos5422_clock.c

601

#define CLOCK_WRITE(sc, reg, val) \

sys/arch/arm/samsung/exynos5422_clock.c

602

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/samsung/exynos5422_clock.c

800

uint32_t v = CLOCK_READ(sc, emux->reg);

sys/arch/arm/samsung/exynos5422_clock.c

803

CLOCK_WRITE(sc, emux->reg, v);

sys/arch/arm/samsung/exynos5422_clock.c

816

const uint32_t v = CLOCK_READ(sc, emux->reg);

sys/arch/arm/samsung/exynos5422_clock.c

836

const uint32_t v = CLOCK_READ(sc, ediv->reg);

sys/arch/arm/samsung/exynos5422_clock.c

866

uint32_t v = CLOCK_READ(sc, ediv->reg);

sys/arch/arm/samsung/exynos5422_clock.c

869

CLOCK_WRITE(sc, ediv->reg, v);

sys/arch/arm/samsung/exynos5422_clock.c

882

uint32_t v = CLOCK_READ(sc, egate->reg);

sys/arch/arm/samsung/exynos5422_clock.c

888

CLOCK_WRITE(sc, egate->reg, v);

sys/arch/arm/samsung/exynos_clock.h

56

u_int reg;

sys/arch/arm/samsung/exynos_clock.h

61

u_int reg;

sys/arch/arm/samsung/exynos_clock.h

66

u_int reg;

sys/arch/arm/samsung/exynos_gpio.c

241

#define GPIO_WRITE(bank, reg, val) \

sys/arch/arm/samsung/exynos_gpio.c

244

(bank)->bank_core_offset + (reg), (val))

sys/arch/arm/samsung/exynos_gpio.c

245

#define GPIO_READ(bank, reg) \

sys/arch/arm/samsung/exynos_gpio.c

248

(bank)->bank_core_offset + (reg))

sys/arch/arm/samsung/exynos_i2c.c

89

#define I2C_WRITE(sc, reg, val) \

sys/arch/arm/samsung/exynos_i2c.c

90

bus_space_write_1((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/samsung/exynos_i2c.c

91

#define I2C_READ(sc, reg) \

sys/arch/arm/samsung/exynos_i2c.c

92

bus_space_read_1((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/samsung/exynos_pwm.c

83

#define PWM_READ(sc, reg) \

sys/arch/arm/samsung/exynos_pwm.c

84

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/samsung/exynos_pwm.c

85

#define PWM_WRITE(sc, reg, val) \

sys/arch/arm/samsung/exynos_pwm.c

86

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/samsung/exynos_rtc.c

71

#define RTC_READ(sc, reg) \

sys/arch/arm/samsung/exynos_rtc.c

72

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/samsung/exynos_rtc.c

73

#define RTC_WRITE(sc, reg, val) \

sys/arch/arm/samsung/exynos_rtc.c

74

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/samsung/exynos_soc.c

408

reg = EXYNOS##v##_CMU_##var + PLL_CON0_OFFSET;\

sys/arch/arm/samsung/exynos_soc.c

409

regval = bus_space_read_4(&armv7_generic_bs_tag, exynos_cmu_bsh, reg); \

sys/arch/arm/samsung/exynos_soc.c

417

uint32_t reg = 0;

sys/arch/arm/samsung/exynos_soc.c

677

bus_addr_t reg;

sys/arch/arm/samsung/exynos_soc.c

680

reg = EXYNOS_PMU_USB_PHY_CTRL;

sys/arch/arm/samsung/exynos_soc.c

687

reg = EXYNOS_PMU_USBHOST_PHY_CTRL;

sys/arch/arm/samsung/exynos_soc.c

692

regval = bus_space_read_4(&armv7_generic_bs_tag, exynos_pmu_bsh, reg);

sys/arch/arm/samsung/exynos_soc.c

696

reg, regval);

sys/arch/arm/samsung/exynos_uart.c

110

#define RD4(sc, reg) \

sys/arch/arm/samsung/exynos_uart.c

111

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/samsung/exynos_uart.c

112

#define WR4(sc, reg, val) \

sys/arch/arm/samsung/exynos_uart.c

113

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/samsung/exynos_usbdrdphy.c

118

#define PHY_READ(sc, reg) \

sys/arch/arm/samsung/exynos_usbdrdphy.c

119

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/samsung/exynos_usbdrdphy.c

120

#define PHY_WRITE(sc, reg, val) \

sys/arch/arm/samsung/exynos_usbdrdphy.c

121

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/samsung/exynos_usbphy.c

100

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/samsung/exynos_usbphy.c

101

#define PHY_WRITE(sc, reg, val) \

sys/arch/arm/samsung/exynos_usbphy.c

102

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/samsung/exynos_usbphy.c

190

const bus_size_t reg = phy->phy_index == PHY_ID_HSIC0 ?

sys/arch/arm/samsung/exynos_usbphy.c

196

PHY_WRITE(sc, reg, val);

sys/arch/arm/samsung/exynos_usbphy.c

201

PHY_WRITE(sc, reg, val);

sys/arch/arm/samsung/exynos_usbphy.c

99

#define PHY_READ(sc, reg) \

sys/arch/arm/sociox/if_scx.c

1778

mii_readreg(device_t self, int phy, int reg, uint16_t *val)

sys/arch/arm/sociox/if_scx.c

1784

miia = (phy << GAR_PHY) | (reg << GAR_REG) | sc->sc_mdclk;

sys/arch/arm/sociox/if_scx.c

1798

mii_writereg(device_t self, int phy, int reg, uint16_t val)

sys/arch/arm/sociox/if_scx.c

1805

miia = (phy << GAR_PHY) | (reg << GAR_REG) | sc->sc_mdclk;

sys/arch/arm/sociox/if_scx.c

592

#define WAIT_FOR_SET(sc, reg, set) \

sys/arch/arm/sociox/if_scx.c

593

wait_for_bits(sc, reg, set, ~0, 0)

sys/arch/arm/sociox/if_scx.c

594

#define WAIT_FOR_CLR(sc, reg, clr) \

sys/arch/arm/sociox/if_scx.c

595

wait_for_bits(sc, reg, 0, clr, 0)

sys/arch/arm/sociox/if_scx.c

598

wait_for_bits(struct scx_softc *sc, int reg,

sys/arch/arm/sociox/if_scx.c

605

val = CSR_READ(sc, reg);

sys/arch/arm/sociox/if_scx.c

617

mac_read(struct scx_softc *sc, int reg)

sys/arch/arm/sociox/if_scx.c

620

CSR_WRITE(sc, MACCMD, reg | CMD_BUSY);

sys/arch/arm/sociox/if_scx.c

626

mac_write(struct scx_softc *sc, int reg, int val)

sys/arch/arm/sociox/if_scx.c

630

CSR_WRITE(sc, MACCMD, reg | CMD_IOWR | CMD_BUSY);

sys/arch/arm/sociox/sni_i2c.c

137

#define CSR_READ(sc, reg) \

sys/arch/arm/sociox/sni_i2c.c

138

bus_space_read_4((sc)->sc_ioh,(sc)->sc_ioh,(reg))

sys/arch/arm/sociox/sni_i2c.c

139

#define CSR_WRITE(sc, reg, val) \

sys/arch/arm/sociox/sni_i2c.c

140

bus_space_write_4((sc)->sc_ioh,(sc)->sc_ioh,(reg),(val))

sys/arch/arm/sunxi/sun4i_a10_ccu.c

419

.u.div.reg = LCD0CH0_CFG_REG,

sys/arch/arm/sunxi/sun4i_a10_ccu.c

436

.u.div.reg = LCD1CH0_CFG_REG,

sys/arch/arm/sunxi/sun4i_a10_ccu.c

453

.u.div.reg = LCD0CH1_CFG_REG,

sys/arch/arm/sunxi/sun4i_a10_ccu.c

469

.u.div.reg = LCD1CH1_CFG_REG,

sys/arch/arm/sunxi/sun4i_a10_codec.c

108

#define RD4(sc, reg) \

sys/arch/arm/sunxi/sun4i_a10_codec.c

109

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/sunxi/sun4i_a10_codec.c

110

#define WR4(sc, reg, val) \

sys/arch/arm/sunxi/sun4i_a10_codec.c

111

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/sunxi/sun4i_a10_codec.c

112

#define SET4(sc, reg, mask) \

sys/arch/arm/sunxi/sun4i_a10_codec.c

113

WR4((sc), (reg), RD4((sc), (reg)) | (mask))

sys/arch/arm/sunxi/sun4i_a10_codec.c

114

#define CLR4(sc, reg, mask) \

sys/arch/arm/sunxi/sun4i_a10_codec.c

115

WR4((sc), (reg), RD4((sc), (reg)) & ~(mask))

sys/arch/arm/sunxi/sun4i_a10_codec.c

160

val = RD4(sc, mix->reg);

sys/arch/arm/sunxi/sun4i_a10_codec.c

165

WR4(sc, mix->reg, val);

sys/arch/arm/sunxi/sun4i_a10_codec.c

183

val = RD4(sc, mix->reg);

sys/arch/arm/sunxi/sun4i_a10_codec.c

99

u_int reg;

sys/arch/arm/sunxi/sun4i_dma.c

126

#define DMA_READ(sc, reg) \

sys/arch/arm/sunxi/sun4i_dma.c

127

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/sunxi/sun4i_dma.c

128

#define DMA_WRITE(sc, reg, val) \

sys/arch/arm/sunxi/sun4i_dma.c

129

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/sunxi/sun4i_emac.c

389

sun4i_emac_miibus_read_reg(device_t self, int phy, int reg, uint16_t *val)

sys/arch/arm/sunxi/sun4i_emac.c

395

sun4i_emac_write(sc, EMAC_MAC_MADR_REG, (phy << 8) | reg);

sys/arch/arm/sunxi/sun4i_emac.c

412

sun4i_emac_miibus_write_reg(device_t self, int phy, int reg, uint16_t val)

sys/arch/arm/sunxi/sun4i_emac.c

418

sun4i_emac_write(sc, EMAC_MAC_MADR_REG, (phy << 8) | reg);

sys/arch/arm/sunxi/sun4i_spi.c

63

#define SPIREG_READ(sc, reg) \

sys/arch/arm/sunxi/sun4i_spi.c

64

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/sunxi/sun4i_spi.c

65

#define SPIREG_WRITE(sc, reg, val) \

sys/arch/arm/sunxi/sun4i_spi.c

66

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/sunxi/sun50i_a64_acodec.c

135

u_int reg;

sys/arch/arm/sunxi/sun50i_a64_acodec.c

153

#define RD4(sc, reg) \

sys/arch/arm/sunxi/sun50i_a64_acodec.c

154

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/sunxi/sun50i_a64_acodec.c

155

#define WR4(sc, reg, val) \

sys/arch/arm/sunxi/sun50i_a64_acodec.c

156

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/sunxi/sun50i_a64_acodec.c

296

val = a64_acodec_pr_read(sc, mix->reg);

sys/arch/arm/sunxi/sun50i_a64_acodec.c

301

a64_acodec_pr_write(sc, mix->reg, val);

sys/arch/arm/sunxi/sun50i_a64_acodec.c

385

val = a64_acodec_pr_read(sc, mix->reg);

sys/arch/arm/sunxi/sun6i_a31_codec.c

142

u_int reg;

sys/arch/arm/sunxi/sun6i_a31_codec.c

151

#define RD4(sc, reg) \

sys/arch/arm/sunxi/sun6i_a31_codec.c

152

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/sunxi/sun6i_a31_codec.c

153

#define WR4(sc, reg, val) \

sys/arch/arm/sunxi/sun6i_a31_codec.c

154

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/sunxi/sun6i_a31_codec.c

155

#define SET4(sc, reg, mask) \

sys/arch/arm/sunxi/sun6i_a31_codec.c

156

WR4((sc), (reg), RD4((sc), (reg)) | (mask))

sys/arch/arm/sunxi/sun6i_a31_codec.c

157

#define CLR4(sc, reg, mask) \

sys/arch/arm/sunxi/sun6i_a31_codec.c

158

WR4((sc), (reg), RD4((sc), (reg)) & ~(mask))

sys/arch/arm/sunxi/sun6i_a31_codec.c

221

val = RD4(sc, mix->reg);

sys/arch/arm/sunxi/sun6i_a31_codec.c

226

WR4(sc, mix->reg, val);

sys/arch/arm/sunxi/sun6i_a31_codec.c

244

val = RD4(sc, mix->reg);

sys/arch/arm/sunxi/sun6i_dma.c

222

#define DMA_READ(sc, reg) \

sys/arch/arm/sunxi/sun6i_dma.c

223

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/sunxi/sun6i_dma.c

224

#define DMA_WRITE(sc, reg, val) \

sys/arch/arm/sunxi/sun6i_dma.c

225

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/sunxi/sun6i_spi.c

67

#define SPIREG_READ(sc, reg) \

sys/arch/arm/sunxi/sun6i_spi.c

68

bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg))

sys/arch/arm/sunxi/sun6i_spi.c

69

#define SPIREG_WRITE(sc, reg, val) \

sys/arch/arm/sunxi/sun6i_spi.c

70

bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))

sys/arch/arm/sunxi/sun8i_a23_apbclk.c

78

#define RD4(sc, reg) \

sys/arch/arm/sunxi/sun8i_a23_apbclk.c

79

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/sunxi/sun8i_a23_apbclk.c

80

#define WR4(sc, reg, val) \

sys/arch/arm/sunxi/sun8i_a23_apbclk.c

81

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/sunxi/sun8i_a83t_ccu.c

138

const int cluster = clk->u.nkmp.reg == PLL_C0CPUX_CTRL_REG ? 0 : 1;

sys/arch/arm/sunxi/sun8i_a83t_ccu.c

155

val = CCU_READ(sc, nkmp->reg);

sys/arch/arm/sunxi/sun8i_a83t_ccu.c

158

CCU_WRITE(sc, nkmp->reg, val);

sys/arch/arm/sunxi/sun8i_a83t_ccu.c

178

.u.nkmp.reg = PLL_C0CPUX_CTRL_REG,

sys/arch/arm/sunxi/sun8i_a83t_ccu.c

199

.u.nkmp.reg = PLL_C1CPUX_CTRL_REG,

sys/arch/arm/sunxi/sun8i_codec.c

129

#define RD4(sc, reg) \

sys/arch/arm/sunxi/sun8i_codec.c

130

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/sunxi/sun8i_codec.c

131

#define WR4(sc, reg, val) \

sys/arch/arm/sunxi/sun8i_codec.c

132

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/sunxi/sun8i_crypto.c

335

sun8i_crypto_read(struct sun8i_crypto_softc *sc, bus_size_t reg)

sys/arch/arm/sunxi/sun8i_crypto.c

337

uint32_t v = bus_space_read_4(sc->sc_bst, sc->sc_bsh, reg);

sys/arch/arm/sunxi/sun8i_crypto.c

339

SDT_PROBE2(sdt, sun8i_crypto, register, read, reg, v);

sys/arch/arm/sunxi/sun8i_crypto.c

344

sun8i_crypto_write(struct sun8i_crypto_softc *sc, bus_size_t reg, uint32_t v)

sys/arch/arm/sunxi/sun8i_crypto.c

347

SDT_PROBE2(sdt, sun8i_crypto, register, write, reg, v);

sys/arch/arm/sunxi/sun8i_crypto.c

348

bus_space_write_4(sc->sc_bst, sc->sc_bsh, reg, v);

sys/arch/arm/sunxi/sun8i_h3_codec.c

109

u_int reg;

sys/arch/arm/sunxi/sun8i_h3_codec.c

126

#define RD4(sc, reg) \

sys/arch/arm/sunxi/sun8i_h3_codec.c

127

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/sunxi/sun8i_h3_codec.c

128

#define WR4(sc, reg, val) \

sys/arch/arm/sunxi/sun8i_h3_codec.c

129

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/sunxi/sun8i_h3_codec.c

296

val = h3_codec_pr_read(csc, mix->reg);

sys/arch/arm/sunxi/sun8i_h3_codec.c

301

h3_codec_pr_write(csc, mix->reg, val);

sys/arch/arm/sunxi/sun8i_h3_codec.c

329

val = h3_codec_pr_read(csc, mix->reg);

sys/arch/arm/sunxi/sun8i_v3s_codec.c

102

u_int reg;

sys/arch/arm/sunxi/sun8i_v3s_codec.c

113

#define RD4(sc, reg) \

sys/arch/arm/sunxi/sun8i_v3s_codec.c

114

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/sunxi/sun8i_v3s_codec.c

115

#define WR4(sc, reg, val) \

sys/arch/arm/sunxi/sun8i_v3s_codec.c

116

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/sunxi/sun8i_v3s_codec.c

278

val = v3s_codec_pr_read(csc, mix->reg);

sys/arch/arm/sunxi/sun8i_v3s_codec.c

283

v3s_codec_pr_write(csc, mix->reg, val);

sys/arch/arm/sunxi/sun8i_v3s_codec.c

308

val = v3s_codec_pr_read(csc, mix->reg);

sys/arch/arm/sunxi/sun9i_a80_ccu.c

140

const int cluster = clk->u.nkmp.reg == PLL_C0CPUX_CTRL_REG ? 0 : 1;

sys/arch/arm/sunxi/sun9i_a80_ccu.c

157

val = CCU_READ(sc, nkmp->reg);

sys/arch/arm/sunxi/sun9i_a80_ccu.c

160

CCU_WRITE(sc, nkmp->reg, val);

sys/arch/arm/sunxi/sun9i_a80_ccu.c

180

.u.nkmp.reg = PLL_C0CPUX_CTRL_REG,

sys/arch/arm/sunxi/sun9i_a80_ccu.c

201

.u.nkmp.reg = PLL_C1CPUX_CTRL_REG,

sys/arch/arm/sunxi/sun9i_a80_cpusclk.c

80

#define RD4(sc, reg) \

sys/arch/arm/sunxi/sun9i_a80_cpusclk.c

81

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/sunxi/sun9i_a80_cpusclk.c

82

#define WR4(sc, reg, val) \

sys/arch/arm/sunxi/sun9i_a80_cpusclk.c

83

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/sunxi/sun9i_a80_usbphy.c

74

#define PHY_READ(sc, reg) \

sys/arch/arm/sunxi/sun9i_a80_usbphy.c

75

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/sunxi/sun9i_a80_usbphy.c

76

#define PHY_WRITE(sc, reg, val) \

sys/arch/arm/sunxi/sun9i_a80_usbphy.c

77

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/sunxi/sunxi_can.c

345

uint32_t reg;

sys/arch/arm/sunxi/sunxi_can.c

354

reg = sunxi_can_read(sc, SUNXI_CAN_REC_REG);

sys/arch/arm/sunxi/sunxi_can.c

356

device_xname(sc->sc_dev), sts, reg);

sys/arch/arm/sunxi/sunxi_can.c

490

uint32_t reg;

sys/arch/arm/sunxi/sunxi_can.c

493

reg = SUNXI_CAN_MODSEL_RST;

sys/arch/arm/sunxi/sunxi_can.c

495

reg |= SUNXI_CAN_MODSEL_LST_ONLY;

sys/arch/arm/sunxi/sunxi_can.c

498

reg |= SUNXI_CAN_MODSEL_LB_MOD;

sys/arch/arm/sunxi/sunxi_can.c

500

sunxi_can_write(sc, SUNXI_CAN_MODSEL_REG, reg);

sys/arch/arm/sunxi/sunxi_can.c

502

reg = 0;

sys/arch/arm/sunxi/sunxi_can.c

509

reg |= (sc->sc_timings.clt_brp - 1) << 0;

sys/arch/arm/sunxi/sunxi_can.c

514

reg |= (sc->sc_timings.clt_ps1 - 1) << 16;

sys/arch/arm/sunxi/sunxi_can.c

519

reg |= (sc->sc_timings.clt_ps2 - 1) << 20;

sys/arch/arm/sunxi/sunxi_can.c

524

reg |= (sc->sc_timings.clt_sjw - 1) << 14;

sys/arch/arm/sunxi/sunxi_can.c

527

reg |= SUNXI_CAN_BUS_TIME_SAM;

sys/arch/arm/sunxi/sunxi_can.c

529

sunxi_can_write(sc, SUNXI_CAN_BUS_TIME_REG, reg);

sys/arch/arm/sunxi/sunxi_ccu.c

79

const uint32_t val = CCU_READ(sc, reset->reg);

sys/arch/arm/sunxi/sunxi_ccu.c

80

CCU_WRITE(sc, reset->reg, val & ~reset->mask);

sys/arch/arm/sunxi/sunxi_ccu.c

91

const uint32_t val = CCU_READ(sc, reset->reg);

sys/arch/arm/sunxi/sunxi_ccu.c

92

CCU_WRITE(sc, reset->reg, val | reset->mask);

sys/arch/arm/sunxi/sunxi_ccu.h

102

bus_size_t reg;

sys/arch/arm/sunxi/sunxi_ccu.h

134

.u.nkmp.reg = (_reg), \

sys/arch/arm/sunxi/sunxi_ccu.h

157

bus_size_t reg;

sys/arch/arm/sunxi/sunxi_ccu.h

187

.u.nm.reg = (_reg), \

sys/arch/arm/sunxi/sunxi_ccu.h

203

bus_size_t reg;

sys/arch/arm/sunxi/sunxi_ccu.h

238

.u.div.reg = (_reg), \

sys/arch/arm/sunxi/sunxi_ccu.h

265

bus_size_t reg;

sys/arch/arm/sunxi/sunxi_ccu.h

298

.u.prediv.reg = (_reg), \

sys/arch/arm/sunxi/sunxi_ccu.h

314

bus_size_t reg;

sys/arch/arm/sunxi/sunxi_ccu.h

330

.u.phase.reg = (_reg), \

sys/arch/arm/sunxi/sunxi_ccu.h

364

bus_size_t reg;

sys/arch/arm/sunxi/sunxi_ccu.h

397

.u.fractional.reg = (_reg), \

sys/arch/arm/sunxi/sunxi_ccu.h

418

bus_size_t reg;

sys/arch/arm/sunxi/sunxi_ccu.h

43

bus_size_t reg;

sys/arch/arm/sunxi/sunxi_ccu.h

436

.u.mux.reg = (_reg), \

sys/arch/arm/sunxi/sunxi_ccu.h

49

.reg = (_reg), \

sys/arch/arm/sunxi/sunxi_ccu.h

496

#define CCU_READ(sc, reg) \

sys/arch/arm/sunxi/sunxi_ccu.h

497

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/sunxi/sunxi_ccu.h

498

#define CCU_WRITE(sc, reg, val) \

sys/arch/arm/sunxi/sunxi_ccu.h

499

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/sunxi/sunxi_ccu.h

71

bus_size_t reg;

sys/arch/arm/sunxi/sunxi_ccu.h

87

.u.gate.reg = (_reg), \

sys/arch/arm/sunxi/sunxi_ccu_div.c

157

val = CCU_READ(sc, div->reg);

sys/arch/arm/sunxi/sunxi_ccu_div.c

178

CCU_WRITE(sc, div->reg, val);

sys/arch/arm/sunxi/sunxi_ccu_div.c

204

val = CCU_READ(sc, div->reg);

sys/arch/arm/sunxi/sunxi_ccu_div.c

207

CCU_WRITE(sc, div->reg, val);

sys/arch/arm/sunxi/sunxi_ccu_div.c

225

val = CCU_READ(sc, div->reg);

sys/arch/arm/sunxi/sunxi_ccu_div.c

51

val = CCU_READ(sc, div->reg);

sys/arch/arm/sunxi/sunxi_ccu_div.c

56

CCU_WRITE(sc, div->reg, val);

sys/arch/arm/sunxi/sunxi_ccu_div.c

81

val = CCU_READ(sc, div->reg);

sys/arch/arm/sunxi/sunxi_ccu_fractional.c

125

val = CCU_READ(sc, fractional->reg);

sys/arch/arm/sunxi/sunxi_ccu_fractional.c

146

CCU_WRITE(sc, fractional->reg, val);

sys/arch/arm/sunxi/sunxi_ccu_fractional.c

177

CCU_WRITE(sc, fractional->reg, val);

sys/arch/arm/sunxi/sunxi_ccu_fractional.c

204

val = CCU_READ(sc, fractional->reg);

sys/arch/arm/sunxi/sunxi_ccu_fractional.c

209

val = CCU_READ(sc, fractional->reg);

sys/arch/arm/sunxi/sunxi_ccu_fractional.c

51

val = CCU_READ(sc, fractional->reg);

sys/arch/arm/sunxi/sunxi_ccu_fractional.c

56

CCU_WRITE(sc, fractional->reg, val);

sys/arch/arm/sunxi/sunxi_ccu_fractional.c

81

val = CCU_READ(sc, fractional->reg);

sys/arch/arm/sunxi/sunxi_ccu_gate.c

48

val = CCU_READ(sc, gate->reg);

sys/arch/arm/sunxi/sunxi_ccu_gate.c

53

CCU_WRITE(sc, gate->reg, val);

sys/arch/arm/sunxi/sunxi_ccu_mux.c

60

val = CCU_READ(sc, mux->reg);

sys/arch/arm/sunxi/sunxi_ccu_mux.c

63

CCU_WRITE(sc, mux->reg, val);

sys/arch/arm/sunxi/sunxi_ccu_mux.c

78

val = CCU_READ(sc, mux->reg);

sys/arch/arm/sunxi/sunxi_ccu_nkmp.c

155

val = CCU_READ(sc, nkmp->reg);

sys/arch/arm/sunxi/sunxi_ccu_nkmp.c

161

CCU_WRITE(sc, nkmp->reg, val);

sys/arch/arm/sunxi/sunxi_ccu_nkmp.c

167

CCU_WRITE(sc, nkmp->reg, val);

sys/arch/arm/sunxi/sunxi_ccu_nkmp.c

178

CCU_WRITE(sc, nkmp->reg, val);

sys/arch/arm/sunxi/sunxi_ccu_nkmp.c

183

CCU_WRITE(sc, nkmp->reg, val);

sys/arch/arm/sunxi/sunxi_ccu_nkmp.c

189

CCU_WRITE(sc, nkmp->reg, val);

sys/arch/arm/sunxi/sunxi_ccu_nkmp.c

209

CCU_WRITE(sc, nkmp->reg, val);

sys/arch/arm/sunxi/sunxi_ccu_nkmp.c

52

val = CCU_READ(sc, nkmp->reg);

sys/arch/arm/sunxi/sunxi_ccu_nkmp.c

57

CCU_WRITE(sc, nkmp->reg, val);

sys/arch/arm/sunxi/sunxi_ccu_nkmp.c

61

val = CCU_READ(sc, nkmp->reg);

sys/arch/arm/sunxi/sunxi_ccu_nkmp.c

93

val = CCU_READ(sc, nkmp->reg);

sys/arch/arm/sunxi/sunxi_ccu_nm.c

130

val = CCU_READ(sc, nm->reg);

sys/arch/arm/sunxi/sunxi_ccu_nm.c

133

CCU_WRITE(sc, nm->reg, val);

sys/arch/arm/sunxi/sunxi_ccu_nm.c

177

val = CCU_READ(sc, nm->reg);

sys/arch/arm/sunxi/sunxi_ccu_nm.c

184

CCU_WRITE(sc, nm->reg, val);

sys/arch/arm/sunxi/sunxi_ccu_nm.c

210

val = CCU_READ(sc, nm->reg);

sys/arch/arm/sunxi/sunxi_ccu_nm.c

213

CCU_WRITE(sc, nm->reg, val);

sys/arch/arm/sunxi/sunxi_ccu_nm.c

228

val = CCU_READ(sc, nm->reg);

sys/arch/arm/sunxi/sunxi_ccu_nm.c

51

val = CCU_READ(sc, nm->reg);

sys/arch/arm/sunxi/sunxi_ccu_nm.c

56

CCU_WRITE(sc, nm->reg, val);

sys/arch/arm/sunxi/sunxi_ccu_nm.c

81

val = CCU_READ(sc, nm->reg);

sys/arch/arm/sunxi/sunxi_ccu_phase.c

109

val = CCU_READ(sc, phase->reg);

sys/arch/arm/sunxi/sunxi_ccu_phase.c

112

CCU_WRITE(sc, phase->reg, val);

sys/arch/arm/sunxi/sunxi_ccu_phase.c

77

val = CCU_READ(sc, phase->reg);

sys/arch/arm/sunxi/sunxi_ccu_prediv.c

117

val = CCU_READ(sc, prediv->reg);

sys/arch/arm/sunxi/sunxi_ccu_prediv.c

120

CCU_WRITE(sc, prediv->reg, val);

sys/arch/arm/sunxi/sunxi_ccu_prediv.c

135

val = CCU_READ(sc, prediv->reg);

sys/arch/arm/sunxi/sunxi_ccu_prediv.c

59

val = CCU_READ(sc, prediv->reg);

sys/arch/arm/sunxi/sunxi_codec.c

100

#define CODEC_READ(sc, reg) \

sys/arch/arm/sunxi/sunxi_codec.c

101

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/sunxi/sunxi_codec.c

102

#define CODEC_WRITE(sc, reg, val) \

sys/arch/arm/sunxi/sunxi_codec.c

103

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/sunxi/sunxi_debe.c

100

#define DEBE_READ(sc, reg) \

sys/arch/arm/sunxi/sunxi_debe.c

1003

DEBE_READ(sc, regs[i].reg));

sys/arch/arm/sunxi/sunxi_debe.c

101

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/sunxi/sunxi_debe.c

102

#define DEBE_WRITE(sc, reg, val) \

sys/arch/arm/sunxi/sunxi_debe.c

103

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/sunxi/sunxi_debe.c

255

for (unsigned int reg = 0x800; reg < 0x1000; reg += 4) {

sys/arch/arm/sunxi/sunxi_debe.c

256

DEBE_WRITE(sc, reg, 0);

sys/arch/arm/sunxi/sunxi_debe.c

955

uint16_t reg;

sys/arch/arm/sunxi/sunxi_emac.c

1001

reg |= EMAC_CLK_PIT_MII | EMAC_CLK_SRC_MII;

sys/arch/arm/sunxi/sunxi_emac.c

1005

reg &= ~EMAC_CLK_ETXDC;

sys/arch/arm/sunxi/sunxi_emac.c

1006

reg |= ((tx_delay / 100) << EMAC_CLK_ETXDC_SHIFT);

sys/arch/arm/sunxi/sunxi_emac.c

1008

reg &= ~EMAC_CLK_ETXDC;

sys/arch/arm/sunxi/sunxi_emac.c

1009

reg |= (tx_delay << EMAC_CLK_ETXDC_SHIFT);

sys/arch/arm/sunxi/sunxi_emac.c

1013

reg &= ~EMAC_CLK_ERXDC;

sys/arch/arm/sunxi/sunxi_emac.c

1014

reg |= ((rx_delay / 100) << EMAC_CLK_ERXDC_SHIFT);

sys/arch/arm/sunxi/sunxi_emac.c

1016

reg &= ~EMAC_CLK_ERXDC;

sys/arch/arm/sunxi/sunxi_emac.c

1017

reg |= (rx_delay << EMAC_CLK_ERXDC_SHIFT);

sys/arch/arm/sunxi/sunxi_emac.c

1022

reg |= EMAC_CLK_EPHY_SELECT;

sys/arch/arm/sunxi/sunxi_emac.c

1023

reg &= ~EMAC_CLK_EPHY_SHUTDOWN;

sys/arch/arm/sunxi/sunxi_emac.c

1026

reg |= EMAC_CLK_EPHY_LED_POL;

sys/arch/arm/sunxi/sunxi_emac.c

1028

reg &= ~EMAC_CLK_EPHY_LED_POL;

sys/arch/arm/sunxi/sunxi_emac.c

1031

reg &= ~EMAC_CLK_EPHY_ADDR;

sys/arch/arm/sunxi/sunxi_emac.c

1032

reg |= (1 << EMAC_CLK_EPHY_ADDR_SHIFT);

sys/arch/arm/sunxi/sunxi_emac.c

1034

reg &= ~EMAC_CLK_EPHY_SELECT;

sys/arch/arm/sunxi/sunxi_emac.c

1038

aprint_debug_dev(sc->dev, "EMAC clock: 0x%08x\n", reg);

sys/arch/arm/sunxi/sunxi_emac.c

1040

syscon_write_4(sc->syscon, EMAC_CLK_REG, reg);

sys/arch/arm/sunxi/sunxi_emac.c

200

#define RD4(sc, reg) \

sys/arch/arm/sunxi/sunxi_emac.c

201

bus_space_read_4((sc)->bst, (sc)->bsh, (reg))

sys/arch/arm/sunxi/sunxi_emac.c

202

#define WR4(sc, reg, val) \

sys/arch/arm/sunxi/sunxi_emac.c

203

bus_space_write_4((sc)->bst, (sc)->bsh, (reg), (val))

sys/arch/arm/sunxi/sunxi_emac.c

206

sunxi_emac_mii_readreg(device_t dev, int phy, int reg, uint16_t *val)

sys/arch/arm/sunxi/sunxi_emac.c

214

(reg << PHY_REG_ADDR_SHIFT) |

sys/arch/arm/sunxi/sunxi_emac.c

226

phy, reg);

sys/arch/arm/sunxi/sunxi_emac.c

234

sunxi_emac_mii_writereg(device_t dev, int phy, int reg, uint16_t val)

sys/arch/arm/sunxi/sunxi_emac.c

243

(reg << PHY_REG_ADDR_SHIFT) |

sys/arch/arm/sunxi/sunxi_emac.c

253

phy, reg);

sys/arch/arm/sunxi/sunxi_emac.c

605

u_int reg;

sys/arch/arm/sunxi/sunxi_emac.c

636

RD4(sc, regs[n].reg));

sys/arch/arm/sunxi/sunxi_emac.c

983

uint32_t reg, tx_delay, rx_delay;

sys/arch/arm/sunxi/sunxi_emac.c

993

reg = syscon_read_4(sc->syscon, EMAC_CLK_REG);

sys/arch/arm/sunxi/sunxi_emac.c

995

reg &= ~(EMAC_CLK_PIT | EMAC_CLK_SRC | EMAC_CLK_RMII_EN);

sys/arch/arm/sunxi/sunxi_emac.c

997

reg |= EMAC_CLK_PIT_RGMII | EMAC_CLK_SRC_RGMII;

sys/arch/arm/sunxi/sunxi_emac.c

999

reg |= EMAC_CLK_RMII_EN;

sys/arch/arm/sunxi/sunxi_gates.c

68

#define GATE_READ(sc, reg) \

sys/arch/arm/sunxi/sunxi_gates.c

69

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/sunxi/sunxi_gates.c

70

#define GATE_WRITE(sc, reg, val) \

sys/arch/arm/sunxi/sunxi_gates.c

71

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/sunxi/sunxi_gmacclk.c

84

#define RD4(sc, reg) \

sys/arch/arm/sunxi/sunxi_gmacclk.c

85

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/sunxi/sunxi_gmacclk.c

86

#define WR4(sc, reg, val) \

sys/arch/arm/sunxi/sunxi_gmacclk.c

87

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/sunxi/sunxi_gpio.c

184

#define GPIO_READ(sc, reg) \

sys/arch/arm/sunxi/sunxi_gpio.c

185

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/sunxi/sunxi_gpio.c

186

#define GPIO_WRITE(sc, reg, val) \

sys/arch/arm/sunxi/sunxi_gpio.c

187

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/sunxi/sunxi_hdmi.c

100

#define HDMI_READ(sc, reg) \

sys/arch/arm/sunxi/sunxi_hdmi.c

101

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/sunxi/sunxi_hdmi.c

102

#define HDMI_WRITE(sc, reg, val) \

sys/arch/arm/sunxi/sunxi_hdmi.c

103

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val));

sys/arch/arm/sunxi/sunxi_hdmi.c

1194

uint16_t reg;

sys/arch/arm/sunxi/sunxi_hdmi.c

1220

HDMI_READ(sc, regs[i].reg));

sys/arch/arm/sunxi/sunxi_hdmi.c

333

sunxi_hdmi_i2c_xfer_1_3(void *priv, i2c_addr_t addr, uint8_t block, uint8_t reg,

sys/arch/arm/sunxi/sunxi_hdmi.c

346

val |= __SHIFTIN(reg, SUNXI_HDMI_DDC_SLAVE_ADDR_2);

sys/arch/arm/sunxi/sunxi_hdmi.c

382

sunxi_hdmi_i2c_xfer_1_4(void *priv, i2c_addr_t addr, uint8_t block, uint8_t reg,

sys/arch/arm/sunxi/sunxi_hdmi.c

395

val |= __SHIFTIN(reg, SUNXI_A31_HDMI_DDC_SLAVE_ADDR_OFF_ADR);

sys/arch/arm/sunxi/sunxi_hdmi.c

424

sunxi_hdmi_i2c_xfer(void *priv, i2c_addr_t addr, uint8_t block, uint8_t reg,

sys/arch/arm/sunxi/sunxi_hdmi.c

431

rv = sunxi_hdmi_i2c_xfer_1_3(priv, addr, block, reg, len,

sys/arch/arm/sunxi/sunxi_hdmi.c

434

rv = sunxi_hdmi_i2c_xfer_1_4(priv, addr, block, reg, len,

sys/arch/arm/sunxi/sunxi_hdmiphy.c

142

#define PHY_READ(sc, reg) \

sys/arch/arm/sunxi/sunxi_hdmiphy.c

143

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/sunxi/sunxi_hdmiphy.c

144

#define PHY_WRITE(sc, reg, val) \

sys/arch/arm/sunxi/sunxi_hdmiphy.c

145

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/sunxi/sunxi_hdmiphy.c

146

#define PHY_SET_CLEAR(sc, reg, set, clr) \

sys/arch/arm/sunxi/sunxi_hdmiphy.c

148

uint32_t _tval = PHY_READ((sc), (reg)); \

sys/arch/arm/sunxi/sunxi_hdmiphy.c

151

PHY_WRITE((sc), (reg), _tval); \

sys/arch/arm/sunxi/sunxi_hdmiphy.c

153

#define PHY_SET(sc, reg, set) \

sys/arch/arm/sunxi/sunxi_hdmiphy.c

154

PHY_SET_CLEAR(sc, reg, set, 0)

sys/arch/arm/sunxi/sunxi_hdmiphy.c

155

#define PHY_CLEAR(sc, reg, clr) \

sys/arch/arm/sunxi/sunxi_hdmiphy.c

156

PHY_SET_CLEAR(sc, reg, 0, clr)

sys/arch/arm/sunxi/sunxi_hstimer.c

96

#define TIMER_READ(sc, reg) \

sys/arch/arm/sunxi/sunxi_hstimer.c

97

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/sunxi/sunxi_hstimer.c

98

#define TIMER_WRITE(sc, reg, val) \

sys/arch/arm/sunxi/sunxi_hstimer.c

99

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/sunxi/sunxi_i2s.c

206

#define I2S_READ(sc, reg) \

sys/arch/arm/sunxi/sunxi_i2s.c

207

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/sunxi/sunxi_i2s.c

208

#define I2S_WRITE(sc, reg, val) \

sys/arch/arm/sunxi/sunxi_i2s.c

209

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/sunxi/sunxi_intc.c

86

#define INTC_READ(sc, reg) \

sys/arch/arm/sunxi/sunxi_intc.c

87

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/sunxi/sunxi_intc.c

88

#define INTC_WRITE(sc, reg, val) \

sys/arch/arm/sunxi/sunxi_intc.c

89

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/sunxi/sunxi_lcdc.c

144

#define TCON_READ(sc, reg) \

sys/arch/arm/sunxi/sunxi_lcdc.c

145

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/sunxi/sunxi_lcdc.c

146

#define TCON_WRITE(sc, reg, val) \

sys/arch/arm/sunxi/sunxi_lcdc.c

147

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/sunxi/sunxi_lradc.c

66

#define ADC_READ(sc, reg) \

sys/arch/arm/sunxi/sunxi_lradc.c

67

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/sunxi/sunxi_lradc.c

68

#define ADC_WRITE(sc, reg, val) \

sys/arch/arm/sunxi/sunxi_lradc.c

69

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/sunxi/sunxi_mixer.c

244

#define GLB_READ(sc, reg) \

sys/arch/arm/sunxi/sunxi_mixer.c

245

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, GLB_BASE + (reg))

sys/arch/arm/sunxi/sunxi_mixer.c

246

#define GLB_WRITE(sc, reg, val) \

sys/arch/arm/sunxi/sunxi_mixer.c

247

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, GLB_BASE + (reg), (val))

sys/arch/arm/sunxi/sunxi_mixer.c

249

#define BLD_READ(sc, reg) \

sys/arch/arm/sunxi/sunxi_mixer.c

250

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, BLD_BASE + (reg))

sys/arch/arm/sunxi/sunxi_mixer.c

251

#define BLD_WRITE(sc, reg, val) \

sys/arch/arm/sunxi/sunxi_mixer.c

252

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, BLD_BASE + (reg), (val))

sys/arch/arm/sunxi/sunxi_mixer.c

254

#define OVL_V_READ(sc, reg) \

sys/arch/arm/sunxi/sunxi_mixer.c

255

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, OVL_BASE(0) + (reg))

sys/arch/arm/sunxi/sunxi_mixer.c

256

#define OVL_V_WRITE(sc, reg, val) \

sys/arch/arm/sunxi/sunxi_mixer.c

257

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, OVL_BASE(0) + (reg), (val))

sys/arch/arm/sunxi/sunxi_mixer.c

259

#define OVL_UI_READ(sc, n, reg) \

sys/arch/arm/sunxi/sunxi_mixer.c

260

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, OVL_BASE((n) + 1) + (reg))

sys/arch/arm/sunxi/sunxi_mixer.c

261

#define OVL_UI_WRITE(sc, n, reg, val) \

sys/arch/arm/sunxi/sunxi_mixer.c

262

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, OVL_BASE((n) + 1) + (reg), (val))

sys/arch/arm/sunxi/sunxi_mixer.c

264

#define VSU_READ(sc, reg) \

sys/arch/arm/sunxi/sunxi_mixer.c

265

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, VSU_BASE + (reg))

sys/arch/arm/sunxi/sunxi_mixer.c

266

#define VSU_WRITE(sc, reg, val) \

sys/arch/arm/sunxi/sunxi_mixer.c

267

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, VSU_BASE + (reg), (val))

sys/arch/arm/sunxi/sunxi_mixer.c

269

#define CSC_READ(sc, n, reg) \

sys/arch/arm/sunxi/sunxi_mixer.c

270

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, CSC_BASE(n) + (reg))

sys/arch/arm/sunxi/sunxi_mixer.c

271

#define CSC_WRITE(sc, n, reg, val) \

sys/arch/arm/sunxi/sunxi_mixer.c

272

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, CSC_BASE(n) + (reg), (val))

sys/arch/arm/sunxi/sunxi_mixer.c

554

bus_size_t reg;

sys/arch/arm/sunxi/sunxi_mixer.c

570

for (reg = 0; reg < 0xc000; reg += 4)

sys/arch/arm/sunxi/sunxi_mixer.c

571

bus_space_write_4(sc->sc_bst, sc->sc_bsh, reg, 0);

sys/arch/arm/sunxi/sunxi_mmc.c

209

#define MMC_WRITE(sc, reg, val) \

sys/arch/arm/sunxi/sunxi_mmc.c

210

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/sunxi/sunxi_mmc.c

211

#define MMC_READ(sc, reg) \

sys/arch/arm/sunxi/sunxi_mmc.c

212

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/sunxi/sunxi_nand.c

150

#define NAND_READ(sc, reg) \

sys/arch/arm/sunxi/sunxi_nand.c

151

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/sunxi/sunxi_nand.c

152

#define NAND_WRITE(sc, reg, val) \

sys/arch/arm/sunxi/sunxi_nand.c

153

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/sunxi/sunxi_nmi.c

119

#define NMI_READ(sc, reg) \

sys/arch/arm/sunxi/sunxi_nmi.c

120

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/sunxi/sunxi_nmi.c

121

#define NMI_WRITE(sc, reg, val) \

sys/arch/arm/sunxi/sunxi_nmi.c

122

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/sunxi/sunxi_pwm.c

77

#define PWM_READ(sc, reg) \

sys/arch/arm/sunxi/sunxi_pwm.c

78

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/sunxi/sunxi_pwm.c

79

#define PWM_WRITE(sc, reg, val) \

sys/arch/arm/sunxi/sunxi_pwm.c

80

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/sunxi/sunxi_resets.c

55

#define RESET_READ(sc, reg) \

sys/arch/arm/sunxi/sunxi_resets.c

56

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/sunxi/sunxi_resets.c

57

#define RESET_WRITE(sc, reg, val) \

sys/arch/arm/sunxi/sunxi_resets.c

58

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/sunxi/sunxi_rsb.c

100

#define RSB_WRITE(sc, reg, val) \

sys/arch/arm/sunxi/sunxi_rsb.c

101

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/sunxi/sunxi_rsb.c

98

#define RSB_READ(sc, reg) \

sys/arch/arm/sunxi/sunxi_rsb.c

99

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/sunxi/sunxi_rtc.c

304

#define RTC_READ(sc, reg) \

sys/arch/arm/sunxi/sunxi_rtc.c

305

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/sunxi/sunxi_rtc.c

306

#define RTC_WRITE(sc, reg, val) \

sys/arch/arm/sunxi/sunxi_rtc.c

307

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/sunxi/sunxi_rtc.c

407

uint32_t reg = SUN6I_LOSC_CTRL_KEY;

sys/arch/arm/sunxi/sunxi_rtc.c

413

reg |= sc->sc_conf->auto_swt_bypass;

sys/arch/arm/sunxi/sunxi_rtc.c

414

RTC_WRITE(sc, SUN6I_LOSC_CTRL_REG, reg);

sys/arch/arm/sunxi/sunxi_rtc.c

418

reg |= SUN6I_LOSC_CTRL_EXT_OSC | sc->sc_conf->ext_losc_en;

sys/arch/arm/sunxi/sunxi_rtc.c

419

RTC_WRITE(sc, SUN6I_LOSC_CTRL_REG, reg);

sys/arch/arm/sunxi/sunxi_rtc.c

552

uint32_t reg = RTC_READ(sc, SUN6I_RTC_LOSC_OUT_GATING_REG);

sys/arch/arm/sunxi/sunxi_rtc.c

553

if ((reg & SUN6I_RTC_LOSC_OUT_EN) == 0) {

sys/arch/arm/sunxi/sunxi_rtc.c

554

reg |= SUN6I_RTC_LOSC_OUT_EN;

sys/arch/arm/sunxi/sunxi_rtc.c

555

RTC_WRITE(sc, SUN6I_RTC_LOSC_OUT_GATING_REG, reg);

sys/arch/arm/sunxi/sunxi_rtc.c

571

uint32_t reg = RTC_READ(sc, SUN6I_RTC_LOSC_OUT_GATING_REG);

sys/arch/arm/sunxi/sunxi_rtc.c

572

if (reg & SUN6I_RTC_LOSC_OUT_EN) {

sys/arch/arm/sunxi/sunxi_rtc.c

573

reg &= ~SUN6I_RTC_LOSC_OUT_EN;

sys/arch/arm/sunxi/sunxi_rtc.c

574

RTC_WRITE(sc, SUN6I_RTC_LOSC_OUT_GATING_REG, reg);

sys/arch/arm/sunxi/sunxi_rtc.c

594

uint32_t reg = RTC_READ(sc, SUN6I_LOSC_CTRL_REG);

sys/arch/arm/sunxi/sunxi_rtc.c

596

reg |= SUN6I_LOSC_CTRL_EXT_OSC | sc->sc_conf->ext_losc_en;

sys/arch/arm/sunxi/sunxi_rtc.c

598

reg &= ~(SUN6I_LOSC_CTRL_EXT_OSC | sc->sc_conf->ext_losc_en);

sys/arch/arm/sunxi/sunxi_rtc.c

599

RTC_WRITE(sc, SUN6I_LOSC_CTRL_REG, reg | SUN6I_LOSC_CTRL_KEY);

sys/arch/arm/sunxi/sunxi_rtc.c

609

uint32_t reg;

sys/arch/arm/sunxi/sunxi_rtc.c

614

reg = RTC_READ(sc, SUN6I_LOSC_CTRL_REG);

sys/arch/arm/sunxi/sunxi_rtc.c

615

if (reg & SUN6I_LOSC_CTRL_EXT_OSC)

sys/arch/arm/sunxi/sunxi_sid.c

76

#define EFUSE_READ(sc, reg) \

sys/arch/arm/sunxi/sunxi_sid.c

77

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (sc)->sc_conf->efuse_offset + (reg))

sys/arch/arm/sunxi/sunxi_sid.c

78

#define EFUSE_WRITE(sc, reg, val) \

sys/arch/arm/sunxi/sunxi_sid.c

79

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (sc)->sc_conf->efuse_offset + (reg), (val))

sys/arch/arm/sunxi/sunxi_sramc.c

116

#define SRAMC_READ(sc, reg) \

sys/arch/arm/sunxi/sunxi_sramc.c

117

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/sunxi/sunxi_sramc.c

118

#define SRAMC_WRITE(sc, reg, val) \

sys/arch/arm/sunxi/sunxi_sramc.c

119

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/sunxi/sunxi_sramc.c

174

sunxi_sramc_read_4(void *priv, bus_size_t reg)

sys/arch/arm/sunxi/sunxi_sramc.c

180

return SRAMC_READ(sc, reg);

sys/arch/arm/sunxi/sunxi_sramc.c

184

sunxi_sramc_write_4(void *priv, bus_size_t reg, uint32_t val)

sys/arch/arm/sunxi/sunxi_sramc.c

190

SRAMC_WRITE(sc, reg, val);

sys/arch/arm/sunxi/sunxi_sramc.c

260

val = SRAMC_READ(sc, node->area->reg);

sys/arch/arm/sunxi/sunxi_sramc.c

263

SRAMC_WRITE(sc, node->area->reg, val);

sys/arch/arm/sunxi/sunxi_sramc.c

58

bus_size_t reg;

sys/arch/arm/sunxi/sunxi_sramc.c

66

.reg = 0x04,

sys/arch/arm/sunxi/sunxi_sramc.c

73

.reg = 0x04,

sys/arch/arm/sunxi/sunxi_sramc.c

80

.reg = 0x04,

sys/arch/arm/sunxi/sunxi_tcon.c

887

uint16_t reg;

sys/arch/arm/sunxi/sunxi_tcon.c

91

#define TCON_READ(sc, reg) \

sys/arch/arm/sunxi/sunxi_tcon.c

92

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/sunxi/sunxi_tcon.c

922

TCON_READ(sc, regs[i].reg));

sys/arch/arm/sunxi/sunxi_tcon.c

93

#define TCON_WRITE(sc, reg, val) \

sys/arch/arm/sunxi/sunxi_tcon.c

94

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/sunxi/sunxi_thermal.c

338

#define RD4(sc, reg) \

sys/arch/arm/sunxi/sunxi_thermal.c

339

bus_space_read_4((sc)->bst, (sc)->bsh, (reg))

sys/arch/arm/sunxi/sunxi_thermal.c

340

#define WR4(sc, reg, val) \

sys/arch/arm/sunxi/sunxi_thermal.c

341

bus_space_write_4((sc)->bst, (sc)->bsh, (reg), (val))

sys/arch/arm/sunxi/sunxi_timer.c

110

#define TIMER_READ(sc, reg) \

sys/arch/arm/sunxi/sunxi_timer.c

111

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/sunxi/sunxi_timer.c

112

#define TIMER_WRITE(sc, reg, val) \

sys/arch/arm/sunxi/sunxi_timer.c

113

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/sunxi/sunxi_timer.c

195

u_int reg;

sys/arch/arm/sunxi/sunxi_timer.c

255

reg = __SHIFTIN(LOSC_CTRL_KEY_FIELD_V, LOSC_CTRL_KEY_FIELD) |

sys/arch/arm/sunxi/sunxi_timer.c

258

TIMER_WRITE(sc, LOSC_CTRL_REG, reg);

sys/arch/arm/sunxi/sunxi_timer.c

264

TIMER_WRITE(sc, LOSC_CTRL_REG, reg & ~LOSC_CTRL_OSC32K_SEL);

sys/arch/arm/sunxi/sunxi_ts.c

176

#define TS_READ(sc, reg) \

sys/arch/arm/sunxi/sunxi_ts.c

177

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/sunxi/sunxi_ts.c

178

#define TS_WRITE(sc, reg, val) \

sys/arch/arm/sunxi/sunxi_ts.c

179

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/sunxi/sunxi_usb3phy.c

91

#define PHY_READ(phy, reg) \

sys/arch/arm/sunxi/sunxi_usb3phy.c

92

bus_space_read_4((phy)->phy_bst, (phy)->phy_bsh, (reg))

sys/arch/arm/sunxi/sunxi_usb3phy.c

93

#define PHY_WRITE(phy, reg, val) \

sys/arch/arm/sunxi/sunxi_usb3phy.c

94

bus_space_write_4((phy)->phy_bst, (phy)->phy_bsh, (reg), (val))

sys/arch/arm/sunxi/sunxi_usbphy.c

123

#define PHYCTL_READ(sc, reg) \

sys/arch/arm/sunxi/sunxi_usbphy.c

125

(sc)->sc_bsh_phy_ctrl, (reg))

sys/arch/arm/sunxi/sunxi_usbphy.c

126

#define PHYCTL_WRITE(sc, reg, val) \

sys/arch/arm/sunxi/sunxi_usbphy.c

128

(sc)->sc_bsh_phy_ctrl, (reg), (val))

sys/arch/arm/sunxi/sunxi_usbphy.c

129

#define PMU_READ(sc, id, reg) \

sys/arch/arm/sunxi/sunxi_usbphy.c

131

(sc)->sc_phys[(id)].phy_bsh, (reg))

sys/arch/arm/sunxi/sunxi_usbphy.c

132

#define PMU_WRITE(sc, id, reg, val) \

sys/arch/arm/sunxi/sunxi_usbphy.c

134

(sc)->sc_phys[(id)].phy_bsh, (reg), (val))

sys/arch/arm/sunxi/sunxi_usbphy.c

145

bus_size_t reg;

sys/arch/arm/sunxi/sunxi_usbphy.c

153

reg = PHYCTL_A10;

sys/arch/arm/sunxi/sunxi_usbphy.c

160

reg = PHYCTL_A33;

sys/arch/arm/sunxi/sunxi_usbphy.c

166

if (reg == PHYCTL_A33)

sys/arch/arm/sunxi/sunxi_usbphy.c

167

PHYCTL_WRITE(sc, reg, 0);

sys/arch/arm/sunxi/sunxi_usbphy.c

170

val = PHYCTL_READ(sc, reg);

sys/arch/arm/sunxi/sunxi_usbphy.c

173

PHYCTL_WRITE(sc, reg, val);

sys/arch/arm/sunxi/sunxi_usbphy.c

175

val = PHYCTL_READ(sc, reg);

sys/arch/arm/sunxi/sunxi_usbphy.c

178

PHYCTL_WRITE(sc, reg, val);

sys/arch/arm/sunxi/sunxi_usbphy.c

180

PHYCTL_READ(sc, reg);

sys/arch/arm/sunxi/sunxi_usbphy.c

182

PHYCTL_WRITE(sc, reg, val);

sys/arch/arm/sunxi/sunxi_usbphy.c

184

PHYCTL_READ(sc, reg);

sys/arch/arm/sunxi/sunxi_usbphy.c

186

PHYCTL_WRITE(sc, reg, val);

sys/arch/arm/sunxi/sunxi_wdt.c

104

#define WDT_READ(sc, reg) \

sys/arch/arm/sunxi/sunxi_wdt.c

105

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/sunxi/sunxi_wdt.c

106

#define WDT_WRITE(sc, reg, val) \

sys/arch/arm/sunxi/sunxi_wdt.c

107

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/ti/am18xx_intc.c

190

uint32_t reg = AM18XX_AINTC_SECR1 + (4 * group);

sys/arch/arm/ti/am18xx_intc.c

191

uint32_t pending = INTC_READ(sc, reg);

sys/arch/arm/ti/am18xx_intc.c

194

INTC_WRITE(sc, reg, pending);

sys/arch/arm/ti/am18xx_intc.c

82

#define INTC_READ(sc, reg) \

sys/arch/arm/ti/am18xx_intc.c

83

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, reg)

sys/arch/arm/ti/am18xx_intc.c

84

#define INTC_WRITE(sc, reg, val) \

sys/arch/arm/ti/am18xx_intc.c

85

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, reg, val)

sys/arch/arm/ti/am18xx_pllc.c

100

#define PLLC_WRITE(sc, reg, val) \

sys/arch/arm/ti/am18xx_pllc.c

101

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, reg, val)

sys/arch/arm/ti/am18xx_pllc.c

98

#define PLLC_READ(sc, reg) \

sys/arch/arm/ti/am18xx_pllc.c

99

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, reg)

sys/arch/arm/ti/am18xx_psc.c

101

#define PSC_READ(sc, reg) \

sys/arch/arm/ti/am18xx_psc.c

102

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, reg)

sys/arch/arm/ti/am18xx_psc.c

103

#define PSC_WRITE(sc, reg, val) \

sys/arch/arm/ti/am18xx_psc.c

104

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, reg, val)

sys/arch/arm/ti/am18xx_timer.c

70

#define TIMER_READ(sc, reg) \

sys/arch/arm/ti/am18xx_timer.c

71

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, reg)

sys/arch/arm/ti/am18xx_timer.c

72

#define TIMER_WRITE(sc, reg, val) \

sys/arch/arm/ti/am18xx_timer.c

73

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, reg, val)

sys/arch/arm/ti/am3_prcm.c

241

if (tclk->u.hwmod.reg == regoff)

sys/arch/arm/ti/am3_prcm.c

81

val = PRCM_READ(sc, tc->u.hwmod.reg);

sys/arch/arm/ti/am3_prcm.c

86

PRCM_WRITE(sc, tc->u.hwmod.reg, val);

sys/arch/arm/ti/if_cpsw.c

771

cpsw_mii_wait(struct cpsw_softc * const sc, int reg)

sys/arch/arm/ti/if_cpsw.c

776

if ((cpsw_read_4(sc, reg) & __BIT(31)) == 0)

sys/arch/arm/ti/if_cpsw.c

784

cpsw_mii_readreg(device_t dev, int phy, int reg, uint16_t *val)

sys/arch/arm/ti/if_cpsw.c

793

((reg & 0x1F) << 21) | ((phy & 0x1F) << 16));

sys/arch/arm/ti/if_cpsw.c

808

cpsw_mii_writereg(device_t dev, int phy, int reg, uint16_t val)

sys/arch/arm/ti/if_cpsw.c

819

((reg & 0x1F) << 21) | ((phy & 0x1F) << 16) | val);

sys/arch/arm/ti/omap2_nand.c

137

gpmc_register_read(struct omap2_nand_softc *sc, bus_size_t reg)

sys/arch/arm/ti/omap2_nand.c

139

return bus_space_read_4(sc->sc_iot, sc->sc_gpmc_ioh, reg);

sys/arch/arm/ti/omap2_nand.c

143

gpmc_register_write(struct omap2_nand_softc *sc, bus_size_t reg, const uint32_t data)

sys/arch/arm/ti/omap2_nand.c

145

bus_space_write_4(sc->sc_iot, sc->sc_gpmc_ioh, reg, data);

sys/arch/arm/ti/omap3_cm.c

68

val = PRCM_READ(sc, tc->u.hwmod.reg + CM_FCLKEN);

sys/arch/arm/ti/omap3_cm.c

73

PRCM_WRITE(sc, tc->u.hwmod.reg + CM_FCLKEN, val);

sys/arch/arm/ti/omap3_cm.c

75

val = PRCM_READ(sc, tc->u.hwmod.reg + CM_ICLKEN);

sys/arch/arm/ti/omap3_cm.c

80

PRCM_WRITE(sc, tc->u.hwmod.reg + CM_ICLKEN, val);

sys/arch/arm/ti/omap3_cm.c

83

val = PRCM_READ(sc, tc->u.hwmod.reg + CM_AUTOIDLE);

sys/arch/arm/ti/omap3_cm.c

85

PRCM_WRITE(sc, tc->u.hwmod.reg + CM_AUTOIDLE, val);

sys/arch/arm/ti/omap3_dss.c

1117

uint32_t pos, reg, addr;

sys/arch/arm/ti/omap3_dss.c

1162

reg = bus_space_read_4(sc->sc_iot, sc->sc_regh, OMAPFB_DISPC_CONTROL);

sys/arch/arm/ti/omap3_dss.c

1164

reg | OMAP_DISPC_CTRL_GO_LCD | OMAP_DISPC_CTRL_GO_DIGITAL);

sys/arch/arm/ti/omap3_dss.c

1229

uint32_t reg;

sys/arch/arm/ti/omap3_dss.c

1231

reg = bus_space_read_4(sc->sc_iot, sc->sc_regh,

sys/arch/arm/ti/omap3_dss.c

1234

reg | OMAP_DISPC_CTRL_GO_LCD | OMAP_DISPC_CTRL_GO_DIGITAL);

sys/arch/arm/ti/omap3_dss.c

198

uint32_t sz, reg;

sys/arch/arm/ti/omap3_dss.c

321

reg = bus_space_read_4(sc->sc_iot, sc->sc_regh, OMAPFB_DISPC_SYSCONFIG);

sys/arch/arm/ti/omap3_dss.c

322

reg &= ~(OMAP_DISPC_SYSC_STANDBY_MASK | OMAP_DISPC_SYSC_IDLE_MASK);

sys/arch/arm/ti/omap3_dss.c

323

reg |= OMAP_DISPC_SYSC_SMART_STANDBY | OMAP_DISPC_SYSC_SMART_IDLE |

sys/arch/arm/ti/omap3_dss.c

325

bus_space_write_4(sc->sc_iot, sc->sc_regh, OMAPFB_DISPC_SYSCONFIG, reg);

sys/arch/arm/ti/omap3_dss.c

330

reg = OMAP_DISPC_CFG_TV_ALPHA_EN | OMAP_DISPC_CFG_LCD_ALPHA_EN;

sys/arch/arm/ti/omap3_dss.c

331

bus_space_write_4(sc->sc_iot, sc->sc_regh, OMAPFB_DISPC_CONFIG, reg);

sys/arch/arm/ti/omap3_dss.c

332

sc->sc_dispc_config = reg;

sys/arch/arm/ti/omap3_dss.c

412

reg = bus_space_read_4(sc->sc_iot, sc->sc_regh, OMAPFB_DISPC_CONTROL);

sys/arch/arm/ti/omap3_dss.c

414

reg | OMAP_DISPC_CTRL_GO_LCD | OMAP_DISPC_CTRL_GO_DIGITAL);

sys/arch/arm/ti/omap3_dss.c

766

uint32_t reg;

sys/arch/arm/ti/omap3_dss.c

771

reg = (r << 16) | (g << 8) | b;

sys/arch/arm/ti/omap3_dss.c

772

sc->sc_clut[idx] = reg;

sys/arch/arm/ti/omap3_dss.c

778

uint32_t reg;

sys/arch/arm/ti/omap3_dss.c

780

reg = OMAP_VID_ATTR_ENABLE |

sys/arch/arm/ti/omap3_dss.c

785

reg |= OMAP_VID_ATTR_RGB16;

sys/arch/arm/ti/omap3_dss.c

788

reg |= OMAP_VID_ATTR_RGB24;

sys/arch/arm/ti/omap3_dss.c

797

OMAPFB_DISPC_VID1_ATTRIBUTES, reg);

sys/arch/arm/ti/omap3_dss.c

803

reg = bus_space_read_4(sc->sc_iot, sc->sc_regh, OMAPFB_DISPC_CONTROL);

sys/arch/arm/ti/omap3_dss.c

805

reg | OMAP_DISPC_CTRL_GO_LCD | OMAP_DISPC_CTRL_GO_DIGITAL);

sys/arch/arm/ti/omap3_dss.c

822

uint32_t reg;

sys/arch/arm/ti/omap3_dss.c

842

reg = bus_space_read_4(sc->sc_iot, sc->sc_regh, OMAPFB_DISPC_CONTROL);

sys/arch/arm/ti/omap3_dss.c

844

reg | OMAP_DISPC_CTRL_GO_LCD | OMAP_DISPC_CTRL_GO_DIGITAL);

sys/arch/arm/ti/omap4_prcm.c

110

val = PRCM_READ(sc, tc->u.hwmod.reg);

sys/arch/arm/ti/omap4_prcm.c

118

PRCM_WRITE(sc, tc->u.hwmod.reg, val);

sys/arch/arm/ti/omap4_prcm.c

121

val = PRCM_READ(sc, tc->u.hwmod.reg);

sys/arch/arm/ti/omap4_prcm.c

269

if (tclk->u.hwmod.reg == regoff)

sys/arch/arm/ti/omap4_prcm.c

84

val = PRCM_READ(sc, tc->u.hwmod.reg);

sys/arch/arm/ti/omap4_prcm.c

92

PRCM_WRITE(sc, tc->u.hwmod.reg, val);

sys/arch/arm/ti/omap4_prcm.c

95

val = PRCM_READ(sc, tc->u.hwmod.reg);

sys/arch/arm/ti/ti_comp_clock.c

78

#define RD4(sc, reg) \

sys/arch/arm/ti/ti_comp_clock.c

79

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/ti/ti_comp_clock.c

80

#define WR4(sc, reg, val) \

sys/arch/arm/ti/ti_comp_clock.c

81

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/ti/ti_edma.c

94

#define EDMA_READ(sc, reg) \

sys/arch/arm/ti/ti_edma.c

95

bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg))

sys/arch/arm/ti/ti_edma.c

96

#define EDMA_WRITE(sc, reg, val) \

sys/arch/arm/ti/ti_edma.c

97

bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))

sys/arch/arm/ti/ti_gate_clock.c

78

#define RD4(sc, reg) \

sys/arch/arm/ti/ti_gate_clock.c

79

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/ti/ti_gate_clock.c

80

#define WR4(sc, reg, val) \

sys/arch/arm/ti/ti_gate_clock.c

81

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/ti/ti_gpio.c

139

#define RD4(sc, reg) \

sys/arch/arm/ti/ti_gpio.c

140

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, ti_gpio_regmap[(sc)->sc_type][(reg)])

sys/arch/arm/ti/ti_gpio.c

141

#define WR4(sc, reg, val) \

sys/arch/arm/ti/ti_gpio.c

142

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, ti_gpio_regmap[(sc)->sc_type][(reg)], (val))

sys/arch/arm/ti/ti_iic.c

190

#define I2C_READ_REG(sc, reg) \

sys/arch/arm/ti/ti_iic.c

191

bus_space_read_2((sc)->sc_iot, (sc)->sc_ioh, ti_iic_regmap[(sc)->sc_type][(reg)])

sys/arch/arm/ti/ti_iic.c

194

#define I2C_WRITE_REG(sc, reg, val) \

sys/arch/arm/ti/ti_iic.c

195

bus_space_write_2((sc)->sc_iot, (sc)->sc_ioh, ti_iic_regmap[(sc)->sc_type][(reg)], (val))

sys/arch/arm/ti/ti_lcdc.h

122

#define RD4(sc, reg) \

sys/arch/arm/ti/ti_lcdc.h

123

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/ti/ti_lcdc.h

124

#define WR4(sc, reg, val) \

sys/arch/arm/ti/ti_lcdc.h

125

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/ti/ti_mux_clock.c

79

#define RD4(sc, reg) \

sys/arch/arm/ti/ti_mux_clock.c

80

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/ti/ti_mux_clock.c

81

#define WR4(sc, reg, val) \

sys/arch/arm/ti/ti_mux_clock.c

82

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/ti/ti_omapmusb.c

75

#define RD1(sc, reg) \

sys/arch/arm/ti/ti_omapmusb.c

76

bus_space_read_1((sc)->sc_iot, (sc)->sc_ioh, (reg))

sys/arch/arm/ti/ti_omapmusb.c

77

#define WR1(sc, reg, val) \

sys/arch/arm/ti/ti_omapmusb.c

78

bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))

sys/arch/arm/ti/ti_omapmusb.c

79

#define RD2(sc, reg) \

sys/arch/arm/ti/ti_omapmusb.c

80

bus_space_read_2((sc)->sc_iot, (sc)->sc_ioh, (reg))

sys/arch/arm/ti/ti_omapmusb.c

81

#define WR2(sc, reg, val) \

sys/arch/arm/ti/ti_omapmusb.c

82

bus_space_write_2((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))

sys/arch/arm/ti/ti_omapmusb.c

83

#define RD4(sc, reg) \

sys/arch/arm/ti/ti_omapmusb.c

84

bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg))

sys/arch/arm/ti/ti_omapmusb.c

85

#define WR4(sc, reg, val) \

sys/arch/arm/ti/ti_omapmusb.c

86

bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))

sys/arch/arm/ti/ti_omaptimer.c

115

#define RD4(sc, reg) \

sys/arch/arm/ti/ti_omaptimer.c

116

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, omaptimer_regmap[(sc)->sc_type][(reg)])

sys/arch/arm/ti/ti_omaptimer.c

117

#define WR4(sc, reg, val) \

sys/arch/arm/ti/ti_omaptimer.c

118

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, omaptimer_regmap[(sc)->sc_type][(reg)], val)

sys/arch/arm/ti/ti_otgreg.h

28

#define TIOTG_USBSS_READ4(sc, reg) \

sys/arch/arm/ti/ti_otgreg.h

29

bus_space_read_4(sc->sc_iot, sc->sc_ioh, (reg) + TIOTG_USBSS_OFFSET)

sys/arch/arm/ti/ti_otgreg.h

30

#define TIOTG_USBSS_WRITE4(sc, reg, val) \

sys/arch/arm/ti/ti_otgreg.h

31

bus_space_write_4(sc->sc_iot, sc->sc_ioh, (reg) + TIOTG_USBSS_OFFSET, (val))

sys/arch/arm/ti/ti_otgreg.h

47

#define TIOTG_USBC_READ4(sc, reg) \

sys/arch/arm/ti/ti_otgreg.h

48

bus_space_read_4(sc->sc_ctrliot, sc->sc_ctrlioh, (reg))

sys/arch/arm/ti/ti_otgreg.h

49

#define TIOTG_USBC_WRITE4(sc, reg, val) \

sys/arch/arm/ti/ti_otgreg.h

50

bus_space_write_4(sc->sc_ctrliot, sc->sc_ctrlioh, (reg), (val))

sys/arch/arm/ti/ti_prcm.h

149

.u.hwmod.reg = (_reg), \

sys/arch/arm/ti/ti_prcm.h

169

#define PRCM_READ(sc, reg) \

sys/arch/arm/ti/ti_prcm.h

170

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/ti/ti_prcm.h

171

#define PRCM_WRITE(sc, reg, val) \

sys/arch/arm/ti/ti_prcm.h

172

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/ti/ti_prcm.h

57

bus_size_t reg;

sys/arch/arm/ti/ti_rng.c

64

#define RD4(sc, reg) \

sys/arch/arm/ti/ti_rng.c

65

bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg))

sys/arch/arm/ti/ti_rng.c

66

#define WR4(sc, reg, val) \

sys/arch/arm/ti/ti_rng.c

67

bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))

sys/arch/arm/ti/ti_sdhc.c

67

#define SDHC_READ(sc, reg) \

sys/arch/arm/ti/ti_sdhc.c

68

bus_space_read_4((sc)->sc_bst, (sc)->sc_sdhc_bsh, (reg))

sys/arch/arm/ti/ti_sdhc.c

69

#define SDHC_WRITE(sc, reg, val) \

sys/arch/arm/ti/ti_sdhc.c

70

bus_space_write_4((sc)->sc_bst, (sc)->sc_sdhc_bsh, (reg), (val))

sys/arch/arm/ti/ti_usb.c

139

#define RD4(sc, reg) \

sys/arch/arm/ti/ti_usb.c

140

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/ti/ti_usb.c

141

#define WR4(sc, reg, val) \

sys/arch/arm/ti/ti_usb.c

142

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/ti/ti_usbtll.c

100

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/ti/ti_usbtll.c

97

#define RD4(sc, reg) \

sys/arch/arm/ti/ti_usbtll.c

98

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/ti/ti_usbtll.c

99

#define WR4(sc, reg, val) \

sys/arch/arm/ti/ti_wdt.c

88

#define RD4(sc, reg) \

sys/arch/arm/ti/ti_wdt.c

89

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/ti/ti_wdt.c

90

#define WR4(sc, reg, val) \

sys/arch/arm/ti/ti_wdt.c

91

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/xilinx/zynq7000_clkc.c

170

bus_addr_t reg)

sys/arch/arm/xilinx/zynq7000_clkc.c

175

val = syscon_read_4(sc->sc_syscon, reg);

sys/arch/arm/xilinx/zynq7000_clkc.c

183

bus_addr_t reg)

sys/arch/arm/xilinx/zynq7000_clkc.c

189

val = syscon_read_4(sc->sc_syscon, reg);

sys/arch/arm/xilinx/zynq7000_clkc.c

270

bus_addr_t reg;

sys/arch/arm/xilinx/zynq7000_clkc.c

273

reg = ARM_CLK_CTRL;

sys/arch/arm/xilinx/zynq7000_clkc.c

276

reg = ARM_CLK_CTRL;

sys/arch/arm/xilinx/zynq7000_clkc.c

279

reg = ARM_CLK_CTRL;

sys/arch/arm/xilinx/zynq7000_clkc.c

282

reg = ARM_CLK_CTRL;

sys/arch/arm/xilinx/zynq7000_clkc.c

285

reg = SDIO_CLK_CTRL;

sys/arch/arm/xilinx/zynq7000_clkc.c

288

reg = SDIO_CLK_CTRL;

sys/arch/arm/xilinx/zynq7000_clkc.c

291

reg = UART_CLK_CTRL;

sys/arch/arm/xilinx/zynq7000_clkc.c

294

reg = UART_CLK_CTRL;

sys/arch/arm/xilinx/zynq7000_clkc.c

297

reg = PCAP_CLK_CTRL;

sys/arch/arm/xilinx/zynq7000_clkc.c

300

reg = APER_CLK_CTRL;

sys/arch/arm/xilinx/zynq7000_clkc.c

303

reg = APER_CLK_CTRL;

sys/arch/arm/xilinx/zynq7000_clkc.c

306

reg = APER_CLK_CTRL;

sys/arch/arm/xilinx/zynq7000_clkc.c

309

reg = APER_CLK_CTRL;

sys/arch/arm/xilinx/zynq7000_clkc.c

312

reg = APER_CLK_CTRL;

sys/arch/arm/xilinx/zynq7000_clkc.c

315

reg = APER_CLK_CTRL;

sys/arch/arm/xilinx/zynq7000_clkc.c

322

val = syscon_read_4(sc->sc_syscon, reg);

sys/arch/arm/xilinx/zynq7000_clkc.c

323

syscon_write_4(sc->sc_syscon, reg, val | mask);

sys/arch/arm/xilinx/zynq_gpio.c

78

#define RD4(sc, reg) \

sys/arch/arm/xilinx/zynq_gpio.c

79

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/xilinx/zynq_gpio.c

80

#define WR4(sc, reg, val) \

sys/arch/arm/xilinx/zynq_gpio.c

81

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/xilinx/zynq_uart.c

1302

uint32_t reg = 0xffff;

sys/arch/arm/xilinx/zynq_uart.c

1311

reg =

sys/arch/arm/xilinx/zynq_uart.c

1319

aprint_error_dev(sc->sc_dev, "zynquart_iflush timeout %02x\n", reg);

sys/arch/arm/xilinx/zynq_usb.c

192

uint32_t reg;

sys/arch/arm/xilinx/zynq_usb.c

195

reg = EOREAD4(hsc, EHCI_PORTSC(1));

sys/arch/arm/xilinx/zynq_usb.c

196

reg &= ~(PORTSC_PTS | PORTSC_PTW);

sys/arch/arm/xilinx/zynq_usb.c

199

reg |= PORTSC_PTW_16;

sys/arch/arm/xilinx/zynq_usb.c

201

reg |= PORTSC_PTS_UTMI;

sys/arch/arm/xilinx/zynq_usb.c

204

reg |= PORTSC_PTS_PHILIPS;

sys/arch/arm/xilinx/zynq_usb.c

207

reg |= PORTSC_PTS_ULPI;

sys/arch/arm/xilinx/zynq_usb.c

210

reg |= PORTSC_PTS_SERIAL;

sys/arch/arm/xilinx/zynq_usb.c

213

EOWRITE4(hsc, EHCI_PORTSC(1), reg);

sys/arch/arm/xilinx/zynq_usb.c

284

uint32_t reg;

sys/arch/arm/xilinx/zynq_usb.c

288

reg = ULPI_RUN | ULPI_RW | __SHIFTIN(addr, ULPI_ADDR) | __SHIFTIN(data, ULPI_DATWR);

sys/arch/arm/xilinx/zynq_usb.c

289

bus_space_write_4(sc->sc_iot, sc->sc_ioh, ZYNQUSB_ULPIVIEW, reg);

sys/arch/arm/xilinx/zynq_usb.c

323

uint32_t reg;

sys/arch/arm/xilinx/zynq_usb.c

327

reg = EOREAD4(hsc, EHCI_USBCMD);

sys/arch/arm/xilinx/zynq_usb.c

328

reg &= ~EHCI_CMD_RS;

sys/arch/arm/xilinx/zynq_usb.c

329

EOWRITE4(hsc, EHCI_USBCMD, reg);

sys/arch/arm/xilinx/zynq_usb.c

332

reg = EOREAD4(hsc, EHCI_USBCMD);

sys/arch/arm/xilinx/zynq_usb.c

333

if ((reg & EHCI_CMD_RS) == 0)

sys/arch/arm/xilinx/zynq_usb.c

338

EOWRITE4(hsc, EHCI_USBCMD, reg | EHCI_CMD_HCRESET);

sys/arch/arm/xilinx/zynq_usb.c

340

reg = EOREAD4(hsc, EHCI_USBCMD);

sys/arch/arm/xilinx/zynq_usb.c

341

if ((reg & EHCI_CMD_HCRESET) == 0)

sys/arch/arm/xilinx/zynq_usb.c

346

aprint_error_dev(hsc->sc_dev, "reset timeout (%x)\n", reg);

sys/arch/arm/xilinx/zynq_usb.c

356

uint32_t reg;

sys/arch/arm/xilinx/zynq_usb.c

358

reg = EOREAD4(hsc, EHCI_PORTSC(1));

sys/arch/arm/xilinx/zynq_usb.c

359

reg &= ~(EHCI_PS_CSC | EHCI_PS_PEC | EHCI_PS_OCC);

sys/arch/arm/xilinx/zynq_usb.c

360

reg |= EHCI_PS_PP | EHCI_PS_PE;

sys/arch/arm/xilinx/zynq_usb.c

361

EOWRITE4(hsc, EHCI_PORTSC(1), reg);

sys/arch/arm/xilinx/zynq_usb.c

363

reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ZYNQUSB_OTGSC);

sys/arch/arm/xilinx/zynq_usb.c

364

reg |= OTGSC_IDPU;

sys/arch/arm/xilinx/zynq_usb.c

365

reg |= OTGSC_DPIE | OTGSC_IDIE;

sys/arch/arm/xilinx/zynq_usb.c

366

bus_space_write_4(sc->sc_iot, sc->sc_ioh, ZYNQUSB_OTGSC, reg);

sys/arch/arm/xilinx/zynq_usb.c

368

reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ZYNQUSB_USBMODE);

sys/arch/arm/xilinx/zynq_usb.c

369

reg &= ~USBMODE_CM;

sys/arch/arm/xilinx/zynq_usb.c

370

reg |= USBMODE_CM_HOST;

sys/arch/arm/xilinx/zynq_usb.c

371

bus_space_write_4(sc->sc_iot, sc->sc_ioh, ZYNQUSB_USBMODE, reg);

sys/arch/arm/xilinx/zynq_xadc.c

118

uint16_t reg;

sys/arch/arm/xilinx/zynq_xadc.c

147

#define RD4(sc, reg) \

sys/arch/arm/xilinx/zynq_xadc.c

148

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/arm/xilinx/zynq_xadc.c

149

#define WR4(sc, reg, val) \

sys/arch/arm/xilinx/zynq_xadc.c

150

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/arm/xilinx/zynq_xadc.c

159

zynq_xadc_write(struct zynq_xadc_softc *sc, uint16_t reg,

sys/arch/arm/xilinx/zynq_xadc.c

172

WR4(sc, XADCIF_CMDFIFO, XADC_COMMAND(XADC_CMD_WRITE, reg, data));

sys/arch/arm/xilinx/zynq_xadc.c

190

zynq_xadc_read(struct zynq_xadc_softc *sc, uint16_t reg)

sys/arch/arm/xilinx/zynq_xadc.c

207

WR4(sc, XADCIF_CMDFIFO, XADC_COMMAND(XADC_CMD_READ, reg, 0));

sys/arch/arm/xilinx/zynq_xadc.c

259

val.u16 = zynq_xadc_read(sc, zynq_xadc_sensors[edata->sensor].reg);

sys/arch/arm/xscale/becc.c

104

__asm volatile("mrc p13, 0, %0, c1, c1, 0" : "=r" (reg));

sys/arch/arm/xscale/becc.c

105

__asm volatile("mcr p13, 0, %0, c1, c1, 0" : : "r" (reg | BCUMOD_AF));

sys/arch/arm/xscale/becc.c

112

reg = becc_pcicore_read(sc, PCI_COMMAND_STATUS_REG);

sys/arch/arm/xscale/becc.c

113

reg &= ~(PCI_COMMAND_MEM_ENABLE|PCI_COMMAND_MASTER_ENABLE);

sys/arch/arm/xscale/becc.c

114

becc_pcicore_write(sc, PCI_COMMAND_STATUS_REG, reg);

sys/arch/arm/xscale/becc.c

122

reg = becc_pcicore_read(sc, PCI_MAPREG_START + 0);

sys/arch/arm/xscale/becc.c

128

reg = becc_pcicore_read(sc, PCI_MAPREG_START + 4);

sys/arch/arm/xscale/becc.c

138

reg = becc_pcicore_read(sc, PCI_MAPREG_START + 8);

sys/arch/arm/xscale/becc.c

175

reg = becc_pcicore_read(sc, PCI_COMMAND_STATUS_REG);

sys/arch/arm/xscale/becc.c

176

reg |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE |

sys/arch/arm/xscale/becc.c

178

becc_pcicore_write(sc, PCI_COMMAND_STATUS_REG, reg);

sys/arch/arm/xscale/becc.c

337

becc_pcicore_read(struct becc_softc *sc, bus_addr_t reg)

sys/arch/arm/xscale/becc.c

339

vaddr_t va = sc->sc_pci_cfg_base | (1U << BECC_IDSEL_BIT) | reg;

sys/arch/arm/xscale/becc.c

345

becc_pcicore_write(struct becc_softc *sc, bus_addr_t reg, uint32_t val)

sys/arch/arm/xscale/becc.c

347

vaddr_t va = sc->sc_pci_cfg_base | (1U << BECC_IDSEL_BIT) | reg;

sys/arch/arm/xscale/becc.c

95

uint32_t reg;

sys/arch/arm/xscale/becc_pci.c

223

uint32_t reg;

sys/arch/arm/xscale/becc_pci.c

228

reg = becc_pcicore_read(sc, PCI_COMMAND_STATUS_REG);

sys/arch/arm/xscale/becc_pci.c

229

if (reg & 0xf9000000) {

sys/arch/arm/xscale/becc_pci.c

231

reg, reg & 0xf9000000));

sys/arch/arm/xscale/becc_pci.c

235

reg & 0xf900ffff);

sys/arch/arm/xscale/becc_pci.c

236

reg = becc_pcicore_read(sc, PCI_COMMAND_STATUS_REG);

sys/arch/arm/xscale/becc_pci.c

239

reg, reg & 0xf9000000));

sys/arch/arm/xscale/becc_pci.c

241

reg = BECC_CSR_READ(BECC_PMISR);

sys/arch/arm/xscale/becc_pci.c

242

if (reg & 0x000f000d) {

sys/arch/arm/xscale/becc_pci.c

244

reg, reg & 0x000f000d));

sys/arch/arm/xscale/becc_pci.c

247

BECC_CSR_WRITE(BECC_PMISR, reg & 0x000f000d);

sys/arch/arm/xscale/becc_pci.c

248

reg = BECC_CSR_READ(BECC_PMISR);

sys/arch/arm/xscale/becc_pci.c

251

reg, reg & 0x000f000d));

sys/arch/arm/xscale/becc_pci.c

253

reg = BECC_CSR_READ(BECC_PSISR);

sys/arch/arm/xscale/becc_pci.c

254

if (reg & 0x000f0210) {

sys/arch/arm/xscale/becc_pci.c

256

reg, reg & 0x000f0210));

sys/arch/arm/xscale/becc_pci.c

259

BECC_CSR_WRITE(BECC_PSISR, reg & 0x000f0210);

sys/arch/arm/xscale/becc_pci.c

260

reg = BECC_CSR_READ(BECC_PSISR);

sys/arch/arm/xscale/becc_pci.c

263

reg, reg & 0x000f0210));

sys/arch/arm/xscale/ixp425_if_npe.c

1552

npe_mii_mdio_read(struct npe_softc *sc, int reg)

sys/arch/arm/xscale/ixp425_if_npe.c

1554

#define MII_RD4(sc, reg) bus_space_read_4(sc->sc_iot, sc->sc_miih, reg)

sys/arch/arm/xscale/ixp425_if_npe.c

1558

v = (MII_RD4(sc, reg+0) & 0xff) << 0;

sys/arch/arm/xscale/ixp425_if_npe.c

1559

v |= (MII_RD4(sc, reg+4) & 0xff) << 8;

sys/arch/arm/xscale/ixp425_if_npe.c

1560

v |= (MII_RD4(sc, reg+8) & 0xff) << 16;

sys/arch/arm/xscale/ixp425_if_npe.c

1561

v |= (MII_RD4(sc, reg+12) & 0xff) << 24;

sys/arch/arm/xscale/ixp425_if_npe.c

1567

npe_mii_mdio_write(struct npe_softc *sc, int reg, uint32_t cmd)

sys/arch/arm/xscale/ixp425_if_npe.c

1569

#define MII_WR4(sc, reg, v) \

sys/arch/arm/xscale/ixp425_if_npe.c

1570

bus_space_write_4(sc->sc_iot, sc->sc_miih, reg, v)

sys/arch/arm/xscale/ixp425_if_npe.c

1573

MII_WR4(sc, reg+0, cmd & 0xff);

sys/arch/arm/xscale/ixp425_if_npe.c

1574

MII_WR4(sc, reg+4, (cmd >> 8) & 0xff);

sys/arch/arm/xscale/ixp425_if_npe.c

1575

MII_WR4(sc, reg+8, (cmd >> 16) & 0xff);

sys/arch/arm/xscale/ixp425_if_npe.c

1576

MII_WR4(sc, reg+12, (cmd >> 24) & 0xff);

sys/arch/arm/xscale/ixp425_if_npe.c

1597

npe_miibus_readreg(device_t self, int phy, int reg, uint16_t *val)

sys/arch/arm/xscale/ixp425_if_npe.c

1604

v = (phy << NPE_MII_ADDR_SHL) | (reg << NPE_MII_REG_SHL)

sys/arch/arm/xscale/ixp425_if_npe.c

1621

npe_miibus_writereg(device_t self, int phy, int reg, uint16_t val)

sys/arch/arm/xscale/ixp425_if_npe.c

1628

v = (phy << NPE_MII_ADDR_SHL) | (reg << NPE_MII_REG_SHL)

sys/arch/arm/xscale/ixp425_if_npe.c

346

uint32_t reg;

sys/arch/arm/xscale/ixp425_if_npe.c

351

reg = RD4(sc, NPE_MAC_RX_CNTRL1);

sys/arch/arm/xscale/ixp425_if_npe.c

352

WR4(sc, NPE_MAC_RX_CNTRL1, reg | NPE_RX_CNTRL1_ADDR_FLTR_EN);

sys/arch/arm/xscale/ixp425_intr.h

51

#define IXPREG(reg) *((volatile uint32_t*) (reg))

sys/arch/arm/xscale/ixp425_npe.c

173

static int npe_checkbits(struct ixpnpe_softc *, uint32_t reg, uint32_t);

sys/arch/arm/xscale/ixp425_npe.c

195

uint32_t reg, uint32_t data);

sys/arch/arm/xscale/ixp425_npe.c

196

static uint32_t npe_ecs_reg_read(struct ixpnpe_softc *, uint32_t reg);

sys/arch/arm/xscale/ixp425_npe.c

500

npe_checkbits(struct ixpnpe_softc *sc, uint32_t reg, uint32_t expectedBitsSet)

sys/arch/arm/xscale/ixp425_npe.c

504

val = npe_reg_read(sc, reg);

sys/arch/arm/xscale/ixp425_npe.c

506

__func__, reg, expectedBitsSet, val,

sys/arch/arm/xscale/ixp425_npe.c

578

uint32_t reg = (addrInfo & IX_NPEDL_MASK_STATE_ADDR_CTXT_REG);

sys/arch/arm/xscale/ixp425_npe.c

583

if (reg >= IX_NPEDL_CTXT_REG_MAX) {

sys/arch/arm/xscale/ixp425_npe.c

585

reg);

sys/arch/arm/xscale/ixp425_npe.c

596

if (cNum == 0 && reg == IX_NPEDL_CTXT_REG_STEVT) {

sys/arch/arm/xscale/ixp425_npe.c

602

if (npe_ctx_reg_write(sc, cNum, reg, regVal, verify) != 0) {

sys/arch/arm/xscale/ixp425_npe.c

989

npe_ecs_reg_write(struct ixpnpe_softc *sc, uint32_t reg, uint32_t data)

sys/arch/arm/xscale/ixp425_npe.c

991

npe_cmd_issue_write(sc, IX_NPEDL_EXCTL_CMD_WR_ECS_REG, reg, data);

sys/arch/arm/xscale/ixp425_npe.c

995

npe_ecs_reg_read(struct ixpnpe_softc *sc, uint32_t reg)

sys/arch/arm/xscale/ixp425_npe.c

997

return npe_cmd_issue_read(sc, IX_NPEDL_EXCTL_CMD_RD_ECS_REG, reg);

sys/arch/arm/xscale/ixp425_pci.c

255

ixp425_pci_conf_reg_read(struct ixp425_softc *sc, uint32_t reg)

sys/arch/arm/xscale/ixp425_pci.c

260

PCI_CRP_AD_CBE, ((reg & ~3) | COMMAND_CRP_READ));

sys/arch/arm/xscale/ixp425_pci.c

268

ixp425_pci_conf_reg_write(struct ixp425_softc *sc, uint32_t reg,

sys/arch/arm/xscale/ixp425_pci.c

272

PCI_CRP_AD_CBE, ((reg & ~3) | COMMAND_CRP_WRITE));

sys/arch/arm/xscale/ixp425_qmgr.c

910

bus_size_t reg;

sys/arch/arm/xscale/ixp425_qmgr.c

914

reg = IX_QMGR_QUEIEREG0_OFFSET;

sys/arch/arm/xscale/ixp425_qmgr.c

916

reg = IX_QMGR_QUEIEREG1_OFFSET;

sys/arch/arm/xscale/ixp425_qmgr.c

917

v = aqm_reg_read(sc, reg);

sys/arch/arm/xscale/ixp425_qmgr.c

918

aqm_reg_write(sc, reg, v | (1 << (qId % IX_QMGR_MIN_QUEUPP_QID)));

sys/arch/arm/xscale/ixp425_qmgr.c

921

__func__, qId, reg, v, aqm_reg_read(sc, reg));

sys/arch/arm/xscale/ixp425_qmgr.c

927

bus_size_t reg;

sys/arch/arm/xscale/ixp425_qmgr.c

931

reg = IX_QMGR_QUEIEREG0_OFFSET;

sys/arch/arm/xscale/ixp425_qmgr.c

933

reg = IX_QMGR_QUEIEREG1_OFFSET;

sys/arch/arm/xscale/ixp425_qmgr.c

934

v = aqm_reg_read(sc, reg);

sys/arch/arm/xscale/ixp425_qmgr.c

935

aqm_reg_write(sc, reg, v &~ (1 << (qId % IX_QMGR_MIN_QUEUPP_QID)));

sys/arch/arm/xscale/ixp425_qmgr.c

938

__func__, qId, reg, v, aqm_reg_read(sc, reg));

sys/arch/arm/xscale/ixp425_sipvar.h

53

#define EXP_CSR_WRITE_4(sc, reg, data) \

sys/arch/arm/xscale/ixp425_sipvar.h

54

bus_space_write_4(sc->sc_iot, sc->sc_ioh, reg, data)

sys/arch/arm/xscale/ixp425_sipvar.h

56

#define EXP_CSR_READ_4(sc, reg) \

sys/arch/arm/xscale/ixp425_sipvar.h

57

bus_space_read_4(sc->sc_iot, sc->sc_ioh, reg)

sys/arch/arm/xscale/ixp425_wdog.c

136

uint32_t reg;

sys/arch/arm/xscale/ixp425_wdog.c

142

reg = bus_space_read_4(sc->sc_bust, sc->sc_bush, IXP425_OST_WDOG_ENAB);

sys/arch/arm/xscale/ixp425_wdog.c

145

reg &= ~(OST_WDOG_ENAB_CNT_ENA | OST_WDOG_ENAB_RST_ENA);

sys/arch/arm/xscale/ixp425_wdog.c

149

reg |= OST_WDOG_ENAB_CNT_ENA | OST_WDOG_ENAB_RST_ENA;

sys/arch/arm/xscale/ixp425_wdog.c

152

bus_space_write_4(sc->sc_bust, sc->sc_bush, IXP425_OST_WDOG_ENAB, reg);

sys/arch/arm/xscale/ixp425var.h

41

#define PCI_CSR_WRITE_4(sc, reg, data) \

sys/arch/arm/xscale/ixp425var.h

43

reg, data)

sys/arch/arm/xscale/ixp425var.h

45

#define PCI_CSR_READ_4(sc, reg) \

sys/arch/arm/xscale/ixp425var.h

46

bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh, reg)

sys/arch/arm/xscale/ixp425var.h

48

#define GPIO_CONF_WRITE_4(sc, reg, data) \

sys/arch/arm/xscale/ixp425var.h

50

reg, data)

sys/arch/arm/xscale/ixp425var.h

52

#define GPIO_CONF_READ_4(sc, reg) \

sys/arch/arm/xscale/ixp425var.h

53

bus_space_read_4(sc->sc_iot, sc->sc_gpio_ioh, reg)

sys/arch/arm/xscale/ixp425var.h

55

#define EXP_BUS_WRITE_4(sc, reg, data) \

sys/arch/arm/xscale/ixp425var.h

56

bus_space_write_4(sc->sc_iot, sc->sc_exp_ioh, reg, data)

sys/arch/arm/xscale/ixp425var.h

58

#define EXP_BUS_READ_4(sc, reg) \

sys/arch/arm/xscale/ixp425var.h

59

bus_space_read_4(sc->sc_iot, sc->sc_exp_ioh, reg)

sys/arch/arm/xscale/pxa2x0.c

161

#define MEMCTL_BOOTSTRAP_REG(reg) \

sys/arch/arm/xscale/pxa2x0.c

162

(*((volatile uint32_t *)(pxamemctl_regs + (reg))))

sys/arch/arm/xscale/pxa2x0.c

164

#define CLKMAN_BOOTSTRAP_REG(reg) \

sys/arch/arm/xscale/pxa2x0.c

165

(*((volatile uint32_t *)(pxaclkman_regs + (reg))))

sys/arch/arm/xscale/pxa2x0.c

447

pxa2x0_memctl_read(int reg)

sys/arch/arm/xscale/pxa2x0.c

457

return (bus_space_read_4(iot, ioh, reg));

sys/arch/arm/xscale/pxa2x0.c

459

return (MEMCTL_BOOTSTRAP_REG(reg));

sys/arch/arm/xscale/pxa2x0.c

466

pxa2x0_memctl_write(int reg, uint32_t val)

sys/arch/arm/xscale/pxa2x0.c

476

bus_space_write_4(iot, ioh, reg, val);

sys/arch/arm/xscale/pxa2x0.c

478

MEMCTL_BOOTSTRAP_REG(reg) = val;

sys/arch/arm/xscale/pxa2x0_ac97.c

192

acu_reg_read(struct acu_softc *sc, int reg)

sys/arch/arm/xscale/pxa2x0_ac97.c

195

return (bus_space_read_4(sc->sc_bust, sc->sc_bush, reg));

sys/arch/arm/xscale/pxa2x0_ac97.c

199

acu_reg_write(struct acu_softc *sc, int reg, uint32_t val)

sys/arch/arm/xscale/pxa2x0_ac97.c

202

bus_space_write_4(sc->sc_bust, sc->sc_bush, reg, val);

sys/arch/arm/xscale/pxa2x0_ac97.c

350

int reg, rv = 1;

sys/arch/arm/xscale/pxa2x0_ac97.c

359

reg = AC97_CODEC_BASE(0) + codec_reg * 2;

sys/arch/arm/xscale/pxa2x0_ac97.c

373

(void) acu_reg_read(sc, reg);

sys/arch/arm/xscale/pxa2x0_ac97.c

377

(void) acu_reg_read(sc, reg);

sys/arch/arm/xscale/pxa2x0_ac97.c

385

*valp = acu_reg_read(sc, reg);

sys/arch/arm/xscale/pxa2x0_ac97.c

463

uint32_t gsr, reg;

sys/arch/arm/xscale/pxa2x0_ac97.c

475

reg = acu_reg_read(sc, AC97_POSR);

sys/arch/arm/xscale/pxa2x0_ac97.c

476

acu_reg_write(sc, AC97_POSR, reg);

sys/arch/arm/xscale/pxa2x0_ac97.c

489

reg = acu_reg_read(sc, AC97_PISR);

sys/arch/arm/xscale/pxa2x0_ac97.c

490

acu_reg_write(sc, AC97_PISR, reg);

sys/arch/arm/xscale/pxa2x0_dmac.c

240

dmac_reg_read(struct pxadmac_softc *sc, int reg)

sys/arch/arm/xscale/pxa2x0_dmac.c

243

return (bus_space_read_4(sc->sc_bust, sc->sc_bush, reg));

sys/arch/arm/xscale/pxa2x0_dmac.c

247

dmac_reg_write(struct pxadmac_softc *sc, int reg, uint32_t val)

sys/arch/arm/xscale/pxa2x0_dmac.c

250

bus_space_write_4(sc->sc_bust, sc->sc_bush, reg, val);

sys/arch/arm/xscale/pxa2x0_gpio.c

100

#define GPIO_BOOTSTRAP_REG(reg) \

sys/arch/arm/xscale/pxa2x0_gpio.c

101

(*((volatile uint32_t *)(pxagpio_regs + (reg))))

sys/arch/arm/xscale/pxa2x0_gpio.c

111

pxagpio_reg_read(struct pxagpio_softc *sc, int reg)

sys/arch/arm/xscale/pxa2x0_gpio.c

114

return (bus_space_read_4(sc->sc_bust, sc->sc_bush, reg));

sys/arch/arm/xscale/pxa2x0_gpio.c

117

return (GPIO_BOOTSTRAP_REG(reg));

sys/arch/arm/xscale/pxa2x0_gpio.c

122

pxagpio_reg_write(struct pxagpio_softc *sc, int reg, uint32_t val)

sys/arch/arm/xscale/pxa2x0_gpio.c

125

bus_space_write_4(sc->sc_bust, sc->sc_bush, reg, val);

sys/arch/arm/xscale/pxa2x0_gpio.c

128

GPIO_BOOTSTRAP_REG(reg) = val;

sys/arch/arm/xscale/pxa2x0_gpio.c

256

uint32_t bit, reg;

sys/arch/arm/xscale/pxa2x0_gpio.c

310

reg = pxagpio_reg_read(sc, GPIO_REG(GPIO_GFER0, gpio));

sys/arch/arm/xscale/pxa2x0_gpio.c

311

pxagpio_reg_write(sc, GPIO_REG(GPIO_GFER0, gpio), reg | bit);

sys/arch/arm/xscale/pxa2x0_gpio.c

315

reg = pxagpio_reg_read(sc, GPIO_REG(GPIO_GRER0, gpio));

sys/arch/arm/xscale/pxa2x0_gpio.c

316

pxagpio_reg_write(sc, GPIO_REG(GPIO_GRER0, gpio), reg | bit);

sys/arch/arm/xscale/pxa2x0_gpio.c

320

reg = pxagpio_reg_read(sc, GPIO_REG(GPIO_GFER0, gpio));

sys/arch/arm/xscale/pxa2x0_gpio.c

321

pxagpio_reg_write(sc, GPIO_REG(GPIO_GFER0, gpio), reg | bit);

sys/arch/arm/xscale/pxa2x0_gpio.c

322

reg = pxagpio_reg_read(sc, GPIO_REG(GPIO_GRER0, gpio));

sys/arch/arm/xscale/pxa2x0_gpio.c

323

pxagpio_reg_write(sc, GPIO_REG(GPIO_GRER0, gpio), reg | bit);

sys/arch/arm/xscale/pxa2x0_gpio.c

335

uint32_t bit, reg;

sys/arch/arm/xscale/pxa2x0_gpio.c

339

reg = pxagpio_reg_read(sc, GPIO_REG(GPIO_GFER0, gh->gh_gpio));

sys/arch/arm/xscale/pxa2x0_gpio.c

340

reg &= ~bit;

sys/arch/arm/xscale/pxa2x0_gpio.c

341

pxagpio_reg_write(sc, GPIO_REG(GPIO_GFER0, gh->gh_gpio), reg);

sys/arch/arm/xscale/pxa2x0_gpio.c

342

reg = pxagpio_reg_read(sc, GPIO_REG(GPIO_GRER0, gh->gh_gpio));

sys/arch/arm/xscale/pxa2x0_gpio.c

343

reg &= ~bit;

sys/arch/arm/xscale/pxa2x0_gpio.c

344

pxagpio_reg_write(sc, GPIO_REG(GPIO_GRER0, gh->gh_gpio), reg);

sys/arch/arm/xscale/pxa2x0_gpio.c

628

uint32_t reg;

sys/arch/arm/xscale/pxa2x0_gpio.c

632

reg = pxagpio_reg_read(sc, GPIO_REG(GPIO_GPDR0, gpio)) & ~bit;

sys/arch/arm/xscale/pxa2x0_gpio.c

634

reg |= bit;

sys/arch/arm/xscale/pxa2x0_gpio.c

635

pxagpio_reg_write(sc, GPIO_REG(GPIO_GPDR0, gpio), reg);

sys/arch/arm/xscale/pxa2x0_mci.c

145

#define CSR_READ_1(sc, reg) \

sys/arch/arm/xscale/pxa2x0_mci.c

146

bus_space_read_1((sc)->sc_iot, (sc)->sc_ioh, (reg))

sys/arch/arm/xscale/pxa2x0_mci.c

147

#define CSR_WRITE_1(sc, reg, val) \

sys/arch/arm/xscale/pxa2x0_mci.c

148

bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))

sys/arch/arm/xscale/pxa2x0_mci.c

149

#define CSR_READ_4(sc, reg) \

sys/arch/arm/xscale/pxa2x0_mci.c

150

bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg))

sys/arch/arm/xscale/pxa2x0_mci.c

151

#define CSR_WRITE_4(sc, reg, val) \

sys/arch/arm/xscale/pxa2x0_mci.c

152

bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))

sys/arch/arm/xscale/pxa2x0_mci.c

153

#define CSR_SET_4(sc, reg, val) \

sys/arch/arm/xscale/pxa2x0_mci.c

154

CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (val))

sys/arch/arm/xscale/pxa2x0_mci.c

155

#define CSR_CLR_4(sc, reg, val) \

sys/arch/arm/xscale/pxa2x0_mci.c

156

CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(val))

sys/arch/arm/xscale/pxa2x0_pcic.c

502

uint32_t reg;

sys/arch/arm/xscale/pxa2x0_pcic.c

509

reg = bus_space_read_4(sc->sc_iot, sc->sc_memctl_ioh, MEMCTL_MECR);

sys/arch/arm/xscale/pxa2x0_pcic.c

511

reg | MECR_CIT);

sys/arch/arm/xscale/pxa2x0_pcic.c

521

uint32_t reg;

sys/arch/arm/xscale/pxa2x0_pcic.c

538

reg = bus_space_read_4(sc->sc_iot, sc->sc_memctl_ioh, MEMCTL_MECR);

sys/arch/arm/xscale/pxa2x0_pcic.c

540

reg & ~MECR_CIT);

sys/arch/atari/dev/grf_etreg.h

49

#define vgar(ba, reg) (*(((volatile u_char *)ba)+reg))

sys/arch/atari/dev/grf_etreg.h

50

#define vgaw(ba, reg, val) *(((volatile u_char *)ba)+reg) = ((u_char)val)

sys/arch/atari/dev/hdfd.c

143

#define wrt_fdc_reg(reg, val) { fdio_addr[reg] = val; }

sys/arch/atari/dev/hdfd.c

144

#define rd_fdc_reg(reg) ( fdio_addr[reg] )

sys/arch/atari/dev/if_ne_mb.c

380

bus_size_t reg)

sys/arch/atari/dev/if_ne_mb.c

384

va = (uint8_t *)(bh + (reg << ETHERNEC_PORT_STRIDE));

sys/arch/atari/dev/if_ne_mb.c

391

bus_size_t reg)

sys/arch/atari/dev/if_ne_mb.c

395

ba = (volatile uint8_t *)(bh + (reg << ETHERNEC_PORT_STRIDE));

sys/arch/atari/dev/if_ne_mb.c

402

bus_size_t reg, uint8_t val)

sys/arch/atari/dev/if_ne_mb.c

411

bt->stride + (reg << ETHERNEC_PORT_STRIDE));

sys/arch/atari/dev/if_ne_mb.c

419

bus_size_t reg, uint8_t *a, bus_size_t c)

sys/arch/atari/dev/if_ne_mb.c

423

ba = (volatile uint8_t *)(bh + (reg << ETHERNEC_PORT_STRIDE));

sys/arch/atari/dev/if_ne_mb.c

430

bus_size_t reg, uint16_t *a, bus_size_t c)

sys/arch/atari/dev/if_ne_mb.c

438

bus_size_t reg, const uint8_t *a, bus_size_t c)

sys/arch/atari/dev/if_ne_mb.c

444

bt->stride + (reg << ETHERNEC_PORT_STRIDE));

sys/arch/atari/dev/if_ne_mb.c

455

bus_size_t reg, const uint16_t *a, bus_size_t c)

sys/arch/atari/dev/zs.c

1317

zs_loadchannelregs(struct zschan *zc, uint8_t *reg)

sys/arch/atari/dev/zs.c

1325

ZS_WRITE(zc, 4, reg[4]);

sys/arch/atari/dev/zs.c

1326

ZS_WRITE(zc, 10, reg[10]);

sys/arch/atari/dev/zs.c

1327

ZS_WRITE(zc, 3, reg[3] & ~ZSWR3_RX_ENABLE);

sys/arch/atari/dev/zs.c

1328

ZS_WRITE(zc, 5, reg[5] & ~ZSWR5_TX_ENABLE);

sys/arch/atari/dev/zs.c

1329

ZS_WRITE(zc, 1, reg[1]);

sys/arch/atari/dev/zs.c

1330

ZS_WRITE(zc, 9, reg[9]);

sys/arch/atari/dev/zs.c

1331

ZS_WRITE(zc, 11, reg[11]);

sys/arch/atari/dev/zs.c

1332

ZS_WRITE(zc, 12, reg[12]);

sys/arch/atari/dev/zs.c

1333

ZS_WRITE(zc, 13, reg[13]);

sys/arch/atari/dev/zs.c

1334

ZS_WRITE(zc, 14, reg[14]);

sys/arch/atari/dev/zs.c

1335

ZS_WRITE(zc, 15, reg[15]);

sys/arch/atari/dev/zs.c

1336

ZS_WRITE(zc, 3, reg[3]);

sys/arch/atari/dev/zs.c

1337

ZS_WRITE(zc, 5, reg[5]);

sys/arch/atari/pci/pci_hades.c

81

pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg)

sys/arch/atari/pci/pci_hades.c

85

if ((uint32_t)reg >= PCI_CONF_SIZE)

sys/arch/atari/pci/pci_hades.c

88

data = *(uint32_t *)(pci_conf_addr + pci_config_offset(tag) + reg);

sys/arch/atari/pci/pci_hades.c

93

pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data)

sys/arch/atari/pci/pci_hades.c

96

if ((uint32_t)reg >= PCI_CONF_SIZE)

sys/arch/atari/pci/pci_hades.c

99

*((uint32_t *)(pci_conf_addr + pci_config_offset(tag) + reg))

sys/arch/atari/pci/pci_machdep.c

296

self->dev, self->reg, q->dev, q->reg);

sys/arch/atari/pci/pci_machdep.c

305

self->dev, self->reg, q->dev, q->reg);

sys/arch/atari/pci/pci_machdep.c

330

int dev, reg;

sys/arch/atari/pci/pci_machdep.c

375

p->reg = 0; /* there is no register

sys/arch/atari/pci/pci_machdep.c

386

for (reg = PCI_MAPREG_START; reg < PCI_MAPREG_END; reg += 4) {

sys/arch/atari/pci/pci_machdep.c

387

address = pci_conf_read(pc, tag, reg);

sys/arch/atari/pci/pci_machdep.c

388

pci_conf_write(pc, tag, reg, 0xffffffff);

sys/arch/atari/pci/pci_machdep.c

389

mask = pci_conf_read(pc, tag, reg);

sys/arch/atari/pci/pci_machdep.c

390

pci_conf_write(pc, tag, reg, address);

sys/arch/atari/pci/pci_machdep.c

399

p->reg = reg;

sys/arch/atari/pci/pci_machdep.c

450

reg++;

sys/arch/atari/pci/pci_machdep.c

522

p->dev, p->reg);

sys/arch/atari/pci/pci_machdep.c

523

p->reg = 0;

sys/arch/atari/pci/pci_machdep.c

548

p->dev, p->reg);

sys/arch/atari/pci/pci_machdep.c

549

p->reg = 0;

sys/arch/atari/pci/pci_machdep.c

552

if (p->reg > 0) {

sys/arch/atari/pci/pci_machdep.c

553

pci_conf_write(pc, p->tag, p->reg, p->address);

sys/arch/atari/pci/pci_machdep.c

596

p->dev, p->reg);

sys/arch/atari/pci/pci_machdep.c

598

pci_conf_write(pc, p->tag, p->reg, p->address);

sys/arch/atari/pci/pci_machdep.c

617

p->dev, p->reg, p->size, p->address);

sys/arch/atari/pci/pci_machdep.c

625

p->dev, p->reg, p->size, p->address);

sys/arch/atari/pci/pci_machdep.c

95

pcireg_t reg, address, mask;

sys/arch/atari/pci/pci_milan.c

67

pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg)

sys/arch/atari/pci/pci_milan.c

71

if ((uint32_t)reg >= PCI_CONF_SIZE)

sys/arch/atari/pci/pci_milan.c

74

data = bswap32(milan_pci_confread(tag | reg));

sys/arch/atari/pci/pci_milan.c

86

pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data)

sys/arch/atari/pci/pci_milan.c

89

if ((uint32_t)reg >= PCI_CONF_SIZE)

sys/arch/atari/pci/pci_milan.c

92

milan_pci_confwrite(tag | reg, bswap32(data));

sys/arch/atari/vme/if_we_vme.c

138

uint8_t sum, reg, type, hwr;

sys/arch/atari/vme/if_we_vme.c

200

reg = bus_space_read_1(asict, asich, WE_PROM + i);

sys/arch/atari/vme/if_we_vme.c

201

DPRINTF(("%02x ", reg));

sys/arch/atari/vme/if_we_vme.c

202

sum += reg;

sys/arch/atari/vme/if_we_vme.c

271

reg = bus_space_read_1(asict, asich, WE790_GCR);

sys/arch/atari/vme/if_we_vme.c

272

i = ((reg & WE790_GCR_IR2) >> 4) |

sys/arch/atari/vme/if_we_vme.c

273

((reg & (WE790_GCR_IR1|WE790_GCR_IR0)) >> 2);

sys/arch/atari/vme/if_we_vme.c

408

bus_size_t reg)

sys/arch/atari/vme/if_we_vme.c

412

if ((reg & 0x01) != 0) {

sys/arch/atari/vme/if_we_vme.c

414

rv = *(volatile uint8_t *)(bh + bt->stride + (reg & ~0x01));

sys/arch/atari/vme/if_we_vme.c

417

rv = *(volatile uint8_t *)(bh + reg);

sys/arch/atari/vme/if_we_vme.c

425

bus_size_t reg, uint8_t val)

sys/arch/atari/vme/if_we_vme.c

428

if ((reg & 0x01) != 0) {

sys/arch/atari/vme/if_we_vme.c

430

*(volatile uint8_t *)(bh + bt->stride + (reg & ~0x01)) = val;

sys/arch/atari/vme/if_we_vme.c

433

*(volatile uint8_t *)(bh + reg) = val;

sys/arch/atari/vme/if_we_vme.c

439

bus_size_t reg)

sys/arch/atari/vme/if_we_vme.c

443

if ((reg & 0x01) != 0) {

sys/arch/atari/vme/if_we_vme.c

445

va = (uint8_t *)(bh + bt->stride + (reg & ~0x01));

sys/arch/atari/vme/if_we_vme.c

448

va = (uint8_t *)(bh + reg);

sys/arch/bebox/include/bebox.h

39

#define READ_BEBOX_REG(reg) *(volatile uint32_t *)(BEBOX_REG + (reg))

sys/arch/bebox/include/bebox.h

40

#define SET_BEBOX_REG(reg, v) \

sys/arch/bebox/include/bebox.h

41

*(volatile uint32_t *)(BEBOX_REG + (reg)) = ((v) | BEBOX_SET_MASK)

sys/arch/bebox/include/bebox.h

42

#define CLEAR_BEBOX_REG(reg, v) \

sys/arch/bebox/include/bebox.h

43

*(volatile uint32_t *)(BEBOX_REG + (reg)) = ((v) | BEBOX_CLEAR_MASK)

sys/arch/bebox/isa/mcclock_isa.c

149

mcclock_isa_read(struct mc146818_softc *sc, unsigned reg)

sys/arch/bebox/isa/mcclock_isa.c

152

bus_space_write_1(sc->sc_bst, sc->sc_bsh, 0, reg);

sys/arch/bebox/isa/mcclock_isa.c

157

mcclock_isa_write(struct mc146818_softc *sc, unsigned reg, unsigned datum)

sys/arch/bebox/isa/mcclock_isa.c

160

bus_space_write_1(sc->sc_bst, sc->sc_bsh, 0, reg);

sys/arch/bebox/stand/boot/siop.c

1174

uint32_t reg;

sys/arch/bebox/stand/boot/siop.c

1212

reg = readb(addr + SIOP_SCNTL1);

sys/arch/bebox/stand/boot/siop.c

1213

writeb(addr + SIOP_SCNTL1, reg | SCNTL1_RST);

sys/arch/bebox/stand/boot/siop.c

1215

writeb(addr + SIOP_SCNTL1, reg);

sys/arch/bebox/stand/boot/wdvar.h

53

#define WDC_READ_REG(chp, reg) inb((chp)->c_cmdreg[(reg)])

sys/arch/bebox/stand/boot/wdvar.h

54

#define WDC_WRITE_REG(chp, reg, val) outb((chp)->c_cmdreg[(reg)], (val))

sys/arch/bebox/stand/boot/wdvar.h

55

#define WDC_READ_CTLREG(chp, reg) inb((chp)->c_ctlbase)

sys/arch/bebox/stand/boot/wdvar.h

56

#define WDC_WRITE_CTLREG(chp, reg, val) outb((chp)->c_ctlbase, (val))

sys/arch/cesfic/dev/zs.c

214

zs_read_reg(struct zs_chanstate *cs, uint8_t reg)

sys/arch/cesfic/dev/zs.c

218

*cs->cs_reg_csr = reg;

sys/arch/cesfic/dev/zs.c

226

zs_write_reg(struct zs_chanstate *cs, uint8_t reg, uint8_t val)

sys/arch/cesfic/dev/zs.c

228

*cs->cs_reg_csr = reg;

sys/arch/cesfic/include/z8530var.h

12

uint8_t zs_read_reg(struct zs_chanstate *cs, uint8_t reg);

sys/arch/cesfic/include/z8530var.h

16

void zs_write_reg(struct zs_chanstate *cs, uint8_t reg, uint8_t val);

sys/arch/cobalt/cobalt/interrupt.c

107

#define ICU1_READ(reg) \

sys/arch/cobalt/cobalt/interrupt.c

108

bus_space_read_1(icu_bst, icu1_bsh, (reg))

sys/arch/cobalt/cobalt/interrupt.c

109

#define ICU1_WRITE(reg, val) \

sys/arch/cobalt/cobalt/interrupt.c

110

bus_space_write_1(icu_bst, icu1_bsh, (reg), (val))

sys/arch/cobalt/cobalt/interrupt.c

111

#define ICU2_READ(reg) \

sys/arch/cobalt/cobalt/interrupt.c

112

bus_space_read_1(icu_bst, icu2_bsh, (reg))

sys/arch/cobalt/cobalt/interrupt.c

113

#define ICU2_WRITE(reg, val) \

sys/arch/cobalt/cobalt/interrupt.c

114

bus_space_write_1(icu_bst, icu2_bsh, (reg), (val))

sys/arch/cobalt/cobalt/interrupt.c

115

#define ELCR_READ(reg) \

sys/arch/cobalt/cobalt/interrupt.c

116

bus_space_read_1(icu_bst, elcr_bsh, (reg))

sys/arch/cobalt/cobalt/interrupt.c

117

#define ELCR_WRITE(reg, val) \

sys/arch/cobalt/cobalt/interrupt.c

118

bus_space_write_1(icu_bst, elcr_bsh, (reg), (val))

sys/arch/cobalt/cobalt/machdep.c

506

uint32_t reg;

sys/arch/cobalt/cobalt/machdep.c

512

#define COBALT_BOARD_ID(reg) ((reg & 0x000000f0) >> 4)

sys/arch/cobalt/cobalt/machdep.c

520

reg = *pcicfg_data;

sys/arch/cobalt/cobalt/machdep.c

523

return COBALT_BOARD_ID(reg);

sys/arch/cobalt/dev/mcclock.c

106

bus_space_write_1(iot, ioh, 0, reg);

sys/arch/cobalt/dev/mcclock.c

111

mcclock_read(struct mc146818_softc *sc, u_int reg)

sys/arch/cobalt/dev/mcclock.c

120

bus_space_write_1(iot, ioh, 0, reg);

sys/arch/cobalt/dev/mcclock.c

98

mcclock_write(struct mc146818_softc *sc, u_int reg, u_int datum)

sys/arch/cobalt/dev/zs.c

386

zs_read_reg(struct zs_chanstate *cs, uint8_t reg)

sys/arch/cobalt/dev/zs.c

390

*cs->cs_reg_csr = reg;

sys/arch/cobalt/dev/zs.c

398

zs_write_reg(struct zs_chanstate *cs, uint8_t reg, uint8_t val)

sys/arch/cobalt/dev/zs.c

401

*cs->cs_reg_csr = reg;

sys/arch/cobalt/include/z8530var.h

104

uint8_t zs_read_reg(struct zs_chanstate *cs, uint8_t reg);

sys/arch/cobalt/include/z8530var.h

108

void zs_write_reg(struct zs_chanstate *cs, uint8_t reg, uint8_t val);

sys/arch/cobalt/pci/pci_machdep.c

103

if ((unsigned int)reg >= PCI_CONF_SIZE)

sys/arch/cobalt/pci/pci_machdep.c

120

PCICFG_ENABLE | tag | reg);

sys/arch/cobalt/pci/pci_machdep.c

128

pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data)

sys/arch/cobalt/pci/pci_machdep.c

131

if ((unsigned int)reg >= PCI_CONF_SIZE)

sys/arch/cobalt/pci/pci_machdep.c

135

PCICFG_ENABLE | tag | reg);

sys/arch/cobalt/pci/pci_machdep.c

96

pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg)

sys/arch/cobalt/stand/boot/boot.c

388

uint32_t tag, reg;

sys/arch/cobalt/stand/boot/boot.c

394

#define COBALT_BOARD_ID(reg) ((reg & 0x000000f0) >> 4)

sys/arch/cobalt/stand/boot/boot.c

398

reg = pcicfgread(tag, PCIB_BOARD_ID_REG);

sys/arch/cobalt/stand/boot/boot.c

400

return COBALT_BOARD_ID(reg);

sys/arch/cobalt/stand/boot/lcd.c

40

#define CSR_READ(base, reg) \

sys/arch/cobalt/stand/boot/lcd.c

41

(((*(volatile uint32_t *)((base) + (reg))) >> 24), delay(10))

sys/arch/cobalt/stand/boot/lcd.c

44

#define CSR_WRITE(base, reg, val) \

sys/arch/cobalt/stand/boot/lcd.c

46

*(volatile uint32_t *)((base) + (reg)) = ((val) << 24); \

sys/arch/cobalt/stand/boot/ns16550.c

39

#define CSR_READ(base, reg) (*(volatile uint8_t *)((base) + (reg)))

sys/arch/cobalt/stand/boot/ns16550.c

40

#define CSR_WRITE(base, reg, val) \

sys/arch/cobalt/stand/boot/ns16550.c

42

*(volatile uint8_t *)((base) + (reg)) = (val); \

sys/arch/cobalt/stand/boot/pci.c

42

uint32_t reg;

sys/arch/cobalt/stand/boot/pci.c

49

reg = *pcicfg_data;

sys/arch/cobalt/stand/boot/pci.c

52

return reg;

sys/arch/cobalt/stand/boot/tlp.c

434

tlp_mii_read(struct local *l, int phy, int reg)

sys/arch/cobalt/stand/boot/tlp.c

441

tlp_mii_write(struct local *l, int phy, int reg, int val)

sys/arch/cobalt/stand/boot/wdvar.h

60

#define WDC_READ_REG(chp, reg) *(chp)->c_cmdreg[(reg)]

sys/arch/cobalt/stand/boot/wdvar.h

61

#define WDC_WRITE_REG(chp, reg, val) *(chp)->c_cmdreg[(reg)] = (val)

sys/arch/cobalt/stand/boot/wdvar.h

62

#define WDC_READ_CTLREG(chp, reg) (chp)->c_ctlbase[(reg)]

sys/arch/cobalt/stand/boot/wdvar.h

63

#define WDC_WRITE_CTLREG(chp, reg, val) (chp)->c_ctlbase[(reg)] = (val)

sys/arch/cobalt/stand/boot/zs.c

52

zs_read(void *dev, uint8_t reg)

sys/arch/cobalt/stand/boot/zs.c

57

val = *(volatile uint8_t *)(zs + reg);

sys/arch/cobalt/stand/boot/zs.c

64

zs_write(void *dev, uint8_t reg, uint8_t val)

sys/arch/cobalt/stand/boot/zs.c

68

*(volatile uint8_t *)(zs + reg) = val;

sys/arch/cobalt/stand/boot/zs.c

73

zs_write_reg(void *dev, uint8_t reg, uint8_t val)

sys/arch/cobalt/stand/boot/zs.c

76

zs_write(dev, ZS_CSR, reg);

sys/arch/dreamcast/dev/g2/gapspci_pci.c

155

gaps_conf_read(void *v, pcitag_t tag, int reg)

sys/arch/dreamcast/dev/g2/gapspci_pci.c

162

if ((unsigned int)reg >= PCI_CONF_SIZE)

sys/arch/dreamcast/dev/g2/gapspci_pci.c

165

if (reg == (PCI_MAPREG_START + 4)) {

sys/arch/dreamcast/dev/g2/gapspci_pci.c

173

return bus_space_read_4(sc->sc_memt, sc->sc_pci_memh, reg);

sys/arch/dreamcast/dev/g2/gapspci_pci.c

177

gaps_conf_write(void *v, pcitag_t tag, int reg, pcireg_t val)

sys/arch/dreamcast/dev/g2/gapspci_pci.c

184

if ((unsigned int)reg >= PCI_CONF_SIZE)

sys/arch/dreamcast/dev/g2/gapspci_pci.c

188

if (reg == (PCI_MAPREG_START + 4) && val != 0x01000000)

sys/arch/dreamcast/dev/g2/gapspci_pci.c

191

bus_space_write_4(sc->sc_memt, sc->sc_pci_memh, reg, val);

sys/arch/dreamcast/dev/pvr.c

124

#define PVR_REG_READ(dc, reg) \

sys/arch/dreamcast/dev/pvr.c

125

((volatile uint32_t *)(dc)->dc_regvaddr)[(reg) >> 2]

sys/arch/dreamcast/dev/pvr.c

126

#define PVR_REG_WRITE(dc, reg, val) \

sys/arch/dreamcast/dev/pvr.c

127

((volatile uint32_t *)(dc)->dc_regvaddr)[(reg) >> 2] = (val)

sys/arch/evbarm/adi_brh/brh_machdep.c

650

uint32_t reg;

sys/arch/evbarm/adi_brh/brh_machdep.c

652

reg = *(volatile uint32_t *) va;

sys/arch/evbarm/adi_brh/brh_machdep.c

653

becc_rev = PCI_REVISION(reg);

sys/arch/evbarm/dev/plcom.c

1624

int reg;

sys/arch/evbarm/dev/plcom.c

1629

reg = 0xffff;

sys/arch/evbarm/dev/plcom.c

1636

reg =

sys/arch/evbarm/dev/plcom.c

1644

reg);

sys/arch/evbarm/dev/plcom.c

266

pread1(struct plcom_instance *pi, bus_size_t reg)

sys/arch/evbarm/dev/plcom.c

269

return bus_space_read_1(pi->pi_iot, pi->pi_ioh, reg);

sys/arch/evbarm/dev/plcom.c

271

return bus_space_read_4(pi->pi_iot, pi->pi_ioh, reg & -4) >>

sys/arch/evbarm/dev/plcom.c

272

(8 * (reg & 3));

sys/arch/evbarm/dev/plcom.c

276

pread2(struct plcom_instance *pi, bus_size_t reg)

sys/arch/evbarm/dev/plcom.c

279

return bus_space_read_2(pi->pi_iot, pi->pi_ioh, reg);

sys/arch/evbarm/dev/plcom.c

281

return bus_space_read_4(pi->pi_iot, pi->pi_ioh, reg & -4) >>

sys/arch/evbarm/dev/plcom.c

282

(8 * (reg & 3));

sys/arch/evbarm/dev/plcom.c

327

#define PREAD1(pi, reg) pread1(pi, reg)

sys/arch/evbarm/dev/plcom.c

328

#define PREAD2(pi, reg) pread2(pi, reg)

sys/arch/evbarm/dev/plcom.c

329

#define PREAD4(pi, reg) \

sys/arch/evbarm/dev/plcom.c

330

bus_space_read_4((pi)->pi_iot, (pi)->pi_ioh, (reg))

sys/arch/evbarm/dev/plcom.c

332

#define PWRITE1(pi, reg, val) pwrite1(pi, reg, val)

sys/arch/evbarm/dev/plcom.c

333

#define PWRITEM1(pi, reg, d, c) pwritem1(pi, reg, d, c)

sys/arch/evbarm/dev/plcom.c

334

#define PWRITE2(pi, reg, val) pwrite2(pi, reg, val)

sys/arch/evbarm/dev/plcom.c

335

#define PWRITE4(pi, reg, val) \

sys/arch/evbarm/dev/plcom.c

336

bus_space_write_4((pi)->pi_iot, (pi)->pi_ioh, (reg), (val))

sys/arch/evbarm/g42xxeb/g42xxeb_lcd.c

266

uint16_t reg;

sys/arch/evbarm/g42xxeb/g42xxeb_lcd.c

270

reg = bus_space_read_2(osc->sc_iot, osc->sc_obioreg_ioh,

sys/arch/evbarm/g42xxeb/g42xxeb_lcd.c

273

reg |= LCDCTL_BL_ON;

sys/arch/evbarm/g42xxeb/g42xxeb_lcd.c

275

reg &= ~LCDCTL_BL_ON;

sys/arch/evbarm/g42xxeb/g42xxeb_lcd.c

277

G42XXEB_LCDCTL, reg);

sys/arch/evbarm/g42xxeb/g42xxeb_lcd.c

279

G42XXEB_LED, reg);

sys/arch/evbarm/g42xxeb/g42xxeb_lcd.c

280

printf("LCD control: %x\n", reg);

sys/arch/evbarm/g42xxeb/g42xxeb_lcd.c

294

uint16_t reg;

sys/arch/evbarm/g42xxeb/g42xxeb_lcd.c

300

reg = bus_space_read_2(osc->sc_iot, osc->sc_obioreg_ioh, G42XXEB_LCDCTL);

sys/arch/evbarm/g42xxeb/g42xxeb_lcd.c

302

(reg & ~LCDCTL_BL_PWN) | 0x4000 | LCDCTL_BL_ON);

sys/arch/evbarm/g42xxeb/g42xxeb_lcd.c

318

uint16_t reg;

sys/arch/evbarm/g42xxeb/g42xxeb_lcd.c

322

reg = bus_space_read_2(osc->sc_iot, osc->sc_obioreg_ioh, G42XXEB_LCDCTL);

sys/arch/evbarm/g42xxeb/g42xxeb_lcd.c

324

(reg & ~LCDCTL_BL_PWN) | 0x4000 | LCDCTL_BL_ON);

sys/arch/evbarm/g42xxeb/g42xxeb_mci.c

219

uint16_t reg;

sys/arch/evbarm/g42xxeb/g42xxeb_mci.c

221

reg = bus_space_read_2(sc->sc_obio_iot, sc->sc_obio_ioh,

sys/arch/evbarm/g42xxeb/g42xxeb_mci.c

224

return !(reg & (1<<G42XXEB_INT_MMCSD));

sys/arch/evbarm/g42xxeb/g42xxeb_mci.c

234

uint16_t reg;

sys/arch/evbarm/g42xxeb/g42xxeb_mci.c

236

reg = bus_space_read_2(sc->sc_obio_iot, sc->sc_obio_ioh,

sys/arch/evbarm/g42xxeb/g42xxeb_mci.c

239

return reg & 1;

sys/arch/evbarm/g42xxeb/gb225.c

110

uint32_t reg;

sys/arch/evbarm/g42xxeb/gb225.c

121

reg = bus_space_read_4(iot, memctl_ioh, MEMCTL_MSC2);

sys/arch/evbarm/g42xxeb/gb225.c

122

reg |= MSC_RBW;

sys/arch/evbarm/g42xxeb/gb225.c

123

reg &= ~(MSC_RBW<<16);

sys/arch/evbarm/g42xxeb/gb225.c

125

bus_space_write_4(iot, memctl_ioh, MEMCTL_MSC2, reg);

sys/arch/evbarm/g42xxeb/gb225.c

129

reg = bus_space_read_4(iot, csc->saip.sc_gpioh, GPIO_GPDR1);

sys/arch/evbarm/g42xxeb/gb225.c

131

(reg & ~0x03ff0000) | 0x00ff0000);

sys/arch/evbarm/g42xxeb/gb225.c

132

reg = bus_space_read_4(iot, csc->saip.sc_gpioh, GPIO_GAFR1_U);

sys/arch/evbarm/g42xxeb/gb225.c

134

(reg & ~0x000fffff) | 0x0005aaaa );

sys/arch/evbarm/g42xxeb/gb225.c

143

reg = bus_space_read_2(iot, bsc->sc_obioreg_ioh, G42XXEB_EXTCTRL);

sys/arch/evbarm/g42xxeb/gb225.c

144

bus_space_write_2(iot, bsc->sc_obioreg_ioh, G42XXEB_EXTCTRL, reg | 3);

sys/arch/evbarm/g42xxeb/gb225.c

280

uint8_t reg;

sys/arch/evbarm/g42xxeb/gb225.c

282

reg = bus_space_read_1(iot, ioh, GB225_CFDET) & CARDDET_DET;

sys/arch/evbarm/g42xxeb/gb225.c

283

flag |= do_debounce(sc, OPIO_INTR_CF_INSERT, reg, DEBOUNCE_COUNT);

sys/arch/evbarm/g42xxeb/gb225.c

285

reg = bus_space_read_1(iot, ioh, GB225_PCMCIADET) & CARDDET_DET;

sys/arch/evbarm/g42xxeb/gb225.c

286

flag |= do_debounce(sc, OPIO_INTR_PCMCIA_INSERT, reg, DEBOUNCE_COUNT);

sys/arch/evbarm/g42xxeb/gb225.c

288

reg = bus_space_read_1(iot, ioh, GB225_DEVERROR);

sys/arch/evbarm/g42xxeb/gb225.c

290

flag |= do_debounce(sc, OPIO_INTR_USB_POWER, reg & DEVERROR_USB, 1);

sys/arch/evbarm/g42xxeb/gb225.c

292

flag |= do_debounce(sc, OPIO_INTR_CARD_POWER, reg & DEVERROR_CARD, 1);

sys/arch/evbarm/g42xxeb/gb225_pcic.c

255

uint8_t reg;

sys/arch/evbarm/g42xxeb/gb225_pcic.c

257

reg = opcic_read_card_status(so);

sys/arch/evbarm/g42xxeb/gb225_pcic.c

261

return HAVE_CARD(reg) ?

sys/arch/evbarm/g42xxeb/gb225_pcic.c

265

return (reg & CARDDET_NVS1) == 0;

sys/arch/evbarm/g42xxeb/gb225_pcic.c

268

return (reg & CARDDET_NVS2) == 0;

sys/arch/evbarm/g42xxeb/gb225_slhci.c

83

uint32_t reg;

sys/arch/evbarm/g42xxeb/gb225_slhci.c

90

reg = bus_space_read_4(psc->saip.sc_iot, psc->sc_memctl_ioh,

sys/arch/evbarm/g42xxeb/obio.c

211

uint16_t reg;

sys/arch/evbarm/g42xxeb/obio.c

259

reg = bus_space_read_2(iot, sc->sc_obioreg_ioh, G42XXEB_PLDVER);

sys/arch/evbarm/g42xxeb/obio.c

260

aprint_normal(": board %d version %x\n", reg>>8, reg & 0xff);

sys/arch/evbarm/g42xxeb/obio.c

296

uint16_t reg;

sys/arch/evbarm/g42xxeb/obio.c

327

reg = bus_space_read_2(sc->sc_iot, sc->sc_obioreg_ioh, regidx);

sys/arch/evbarm/g42xxeb/obio.c

329

(reg & ~(7<<sft)) | (ist_code[type] << sft));

sys/arch/evbarm/g42xxeb/obio.c

418

uint16_t reg;

sys/arch/evbarm/g42xxeb/obio.c

420

reg = bus_space_read_2(bsc->sc_iot, bsc->sc_obioreg_ioh,

sys/arch/evbarm/g42xxeb/obio.c

423

onoff ? (reg & ~RST_EXT(no)) : (reg | RST_EXT(no)));

sys/arch/evbarm/gumstix/gxmci.c

77

u_int reg;

sys/arch/evbarm/gumstix/gxmci.c

90

reg = pxa2x0_gpio_get_function(gpioconf[i].pin);

sys/arch/evbarm/gumstix/gxmci.c

91

if (GPIO_FN(reg) != GPIO_FN(gpioconf[i].value) ||

sys/arch/evbarm/gumstix/gxmci.c

92

GPIO_FN_IS_OUT(reg) != GPIO_FN_IS_OUT(gpioconf[i].value))

sys/arch/evbarm/gumstix/gxpcic.c

130

u_int reg;

sys/arch/evbarm/gumstix/gxpcic.c

143

reg = pxa2x0_gpio_get_function(gpioconf[i].pin);

sys/arch/evbarm/gumstix/gxpcic.c

144

if (GPIO_FN(reg) != GPIO_FN(gpioconf[i].value) ||

sys/arch/evbarm/gumstix/gxpcic.c

145

GPIO_FN_IS_OUT(reg) != GPIO_FN_IS_OUT(gpioconf[i].value)) {

sys/arch/evbarm/gumstix/gxpcic.c

205

int reg;

sys/arch/evbarm/gumstix/gxpcic.c

209

reg = pxa2x0_gpio_get_function(so->sc->sc_irqcfpin[so->socket]);

sys/arch/evbarm/gumstix/gxpcic.c

210

return (HAVE_CARD(reg) ?

sys/arch/evbarm/gumstix/gxpcic.c

214

reg = pxa2x0_gpio_get_function(so->sc->sc_irqpin[so->socket]);

sys/arch/evbarm/gumstix/gxpcic.c

215

return (reg & GPIO_SET ? 1 : 0);

sys/arch/evbarm/ifpga/ifpga_pci.c

202

ifpga_pci_conf_read(void *pcv, pcitag_t tag, int reg)

sys/arch/evbarm/ifpga/ifpga_pci.c

209

if ((unsigned int)reg >= PCI_CONF_SIZE)

sys/arch/evbarm/ifpga/ifpga_pci.c

221

address = (1 << (device + 11)) | reg;

sys/arch/evbarm/ifpga/ifpga_pci.c

235

tag | reg);

sys/arch/evbarm/ifpga/ifpga_pci.c

247

pcv, tag, reg, data);

sys/arch/evbarm/ifpga/ifpga_pci.c

253

ifpga_pci_conf_write(void *pcv, pcitag_t tag, int reg, pcireg_t data)

sys/arch/evbarm/ifpga/ifpga_pci.c

261

pcv, tag, reg, data);

sys/arch/evbarm/ifpga/ifpga_pci.c

264

if ((unsigned int)reg >= PCI_CONF_SIZE)

sys/arch/evbarm/ifpga/ifpga_pci.c

276

address = (1 << (device + 11)) | reg;

sys/arch/evbarm/ifpga/ifpga_pci.c

289

bus_space_write_4(sc->sc_iot, sc->sc_conf_ioh, tag | reg,

sys/arch/evbarm/imx31/imx31lk_pcic.c

141

imx31lk_pcic_read(struct imx_pcic_socket *so, int reg)

sys/arch/evbarm/imx31/imx31lk_pcic.c

150

switch (reg) {

sys/arch/evbarm/imx31/imx31lk_pcic.c

171

imx31lk_pcic_write(struct imx_pcic_socket *so, int reg, u_int val)

sys/arch/evbarm/imx31/imx31lk_pcic.c

181

switch (reg) {

sys/arch/evbarm/imx31/imx31lk_pcic.c

215

uint16_t reg;

sys/arch/evbarm/imx31/imx31lk_pcic.c

224

reg = bus_space_read_2(iot, ioh, SCOOP_GPWR);

sys/arch/evbarm/imx31/imx31lk_pcic.c

226

reg & ~(1 << SCOOP0_CF_POWER_C3000));

sys/arch/evbarm/imx31/imx31lk_pcic.c

234

reg = bus_space_read_2(iot, ioh, SCOOP_GPWR);

sys/arch/evbarm/imx31/imx31lk_pcic.c

236

reg | (1 << SCOOP0_CF_POWER_C3000));

sys/arch/evbarm/iq80310/iq80310_machdep.c

350

uint32_t reg;

sys/arch/evbarm/iq80310/iq80310_machdep.c

355

reg = bus_space_read_4(&obio_bs_tag,

sys/arch/evbarm/iq80310/iq80310_machdep.c

359

reg | PCI_BRIDGE_CONTROL_SECBR);

sys/arch/evbarm/iq80310/iq80310_machdep.c

363

reg);

sys/arch/evbarm/iq80310/iq80310_pci.c

131

pcireg_t reg;

sys/arch/evbarm/iq80310/iq80310_pci.c

152

reg = bus_space_read_4(sc->sc_st, sc->sc_ppb_sh, PCI_BRIDGE_BUS_REG);

sys/arch/evbarm/iq80310/iq80310_pci.c

153

pbus = PCI_BRIDGE_BUS_NUM_PRIMARY(reg);

sys/arch/evbarm/iq80310/iq80310_pci.c

154

sbus = PCI_BRIDGE_BUS_NUM_SECONDARY(reg);

sys/arch/evbarm/iq80310/iq80310_pci.c

169

reg = pci_conf_read(pa->pa_pc, tag, PCI_ID_REG);

sys/arch/evbarm/iq80310/iq80310_pci.c

170

if (PCI_VENDOR(reg) == PCI_VENDOR_INVALID ||

sys/arch/evbarm/iq80310/iq80310_pci.c

171

PCI_VENDOR(reg) == 0) {

sys/arch/evbarm/iq80310/iq80310_pci.c

182

reg = pci_conf_read(pa->pa_pc, tag, PCI_CLASS_REG);

sys/arch/evbarm/iq80310/iq80310_pci.c

183

if (PCI_CLASS(reg) != PCI_CLASS_BRIDGE ||

sys/arch/evbarm/iq80310/iq80310_pci.c

184

PCI_SUBCLASS(reg) != PCI_SUBCLASS_BRIDGE_PCI) {

sys/arch/evbarm/iq80310/iq80310_pci.c

195

reg = pci_conf_read(pa->pa_pc, tag, PCI_BRIDGE_BUS_REG);

sys/arch/evbarm/iq80310/iq80310_pci.c

196

sbus = PCI_BRIDGE_BUS_NUM_SECONDARY(reg);

sys/arch/evbarm/iq80310/iq80310_pci.c

86

pcireg_t reg;

sys/arch/evbarm/iq80310/iq80310_pci.c

98

reg = bus_space_read_4(sc->sc_st, sc->sc_ppb_sh, PCI_BRIDGE_BUS_REG);

sys/arch/evbarm/iq80310/iq80310_pci.c

99

sbus = PCI_BRIDGE_BUS_NUM_SECONDARY(reg);

sys/arch/evbarm/ixdp425/ixdp425_machdep.c

212

uint32_t reg;

sys/arch/evbarm/ixdp425/ixdp425_machdep.c

279

reg = EXP_CSR_READ_4(ixpsip_softc, EXP_CNFG0_OFFSET);

sys/arch/evbarm/ixdp425/ixdp425_machdep.c

280

reg |= EXP_CNFG0_MEM_MAP;

sys/arch/evbarm/ixdp425/ixdp425_machdep.c

281

EXP_CSR_WRITE_4(ixpsip_softc, EXP_CNFG0_OFFSET, reg);

sys/arch/evbarm/ixdp425/ixdp425_pci.c

104

reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPCLKR);

sys/arch/evbarm/ixdp425/ixdp425_pci.c

105

GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPCLKR, reg |

sys/arch/evbarm/ixdp425/ixdp425_pci.c

109

reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPCLKR);

sys/arch/evbarm/ixdp425/ixdp425_pci.c

110

GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPCLKR, reg | GPCLKR_MUX14);

sys/arch/evbarm/ixdp425/ixdp425_pci.c

118

reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPOUTR);

sys/arch/evbarm/ixdp425/ixdp425_pci.c

119

GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPOUTR, reg | (1U << GPIO_PCI_RESET));

sys/arch/evbarm/ixdp425/ixdp425_pci.c

65

uint32_t reg;

sys/arch/evbarm/ixdp425/ixdp425_pci.c

78

reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPOUTR);

sys/arch/evbarm/ixdp425/ixdp425_pci.c

79

GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPOUTR, reg & ~(1U << GPIO_PCI_RESET));

sys/arch/evbarm/ixdp425/ixdp425_pci.c

82

reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPCLKR);

sys/arch/evbarm/ixdp425/ixdp425_pci.c

83

GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPCLKR, reg & ~GPCLKR_MUX14);

sys/arch/evbarm/ixdp425/ixdp425_pci.c

90

reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPOER);

sys/arch/evbarm/ixdp425/ixdp425_pci.c

91

reg &= ~(1U << GPIO_PCI_CLK);

sys/arch/evbarm/ixdp425/ixdp425_pci.c

92

reg &= ~(1U << GPIO_PCI_RESET);

sys/arch/evbarm/ixdp425/ixdp425_pci.c

93

reg |= ((1U << GPIO_PCI_INTA) | (1U << GPIO_PCI_INTB) |

sys/arch/evbarm/ixdp425/ixdp425_pci.c

95

GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPOER, reg);

sys/arch/evbarm/ixm1200/nappi_nppb.c

58

#define CSR_READ_1(sc, reg) \

sys/arch/evbarm/ixm1200/nappi_nppb.c

59

bus_space_read_1(sc->sc_st, sc->sc_sh, reg)

sys/arch/evbarm/ixm1200/nappi_nppb.c

60

#define CSR_READ_2(sc, reg) \

sys/arch/evbarm/ixm1200/nappi_nppb.c

61

bus_space_read_2(sc->sc_st, sc->sc_sh, reg)

sys/arch/evbarm/ixm1200/nappi_nppb.c

62

#define CSR_READ_4(sc, reg) \

sys/arch/evbarm/ixm1200/nappi_nppb.c

63

bus_space_read_4(sc->sc_st, sc->sc_sh, reg)

sys/arch/evbarm/ixm1200/nappi_nppb.c

65

#define CSR_WRITE_1(sc, reg, val) \

sys/arch/evbarm/ixm1200/nappi_nppb.c

66

bus_space_write_1(sc->sc_st, sc->sc_sh, reg, val)

sys/arch/evbarm/ixm1200/nappi_nppb.c

67

#define CSR_WRITE_2(sc, reg, val) \

sys/arch/evbarm/ixm1200/nappi_nppb.c

68

bus_space_write_2(sc->sc_st, sc->sc_sh, reg, val)

sys/arch/evbarm/ixm1200/nappi_nppb.c

69

#define CSR_WRITE_4(sc, reg, val) \

sys/arch/evbarm/ixm1200/nappi_nppb.c

70

bus_space_write_4(sc->sc_st, sc->sc_sh, reg, val)

sys/arch/evbarm/kobo/kobo_machdep.c

222

uint16_t reg;

sys/arch/evbarm/kobo/kobo_machdep.c

238

.reg = (offset), \

sys/arch/evbarm/kobo/kobo_machdep.c

380

ioreg_write(KOBO_IOMUXC_VBASE + p->reg,

sys/arch/evbarm/kobo/kobo_usb.c

127

uint32_t reg;

sys/arch/evbarm/kobo/kobo_usb.c

129

reg = bus_space_read_4(usbc->sc_iot, usbc->sc_ioh, USBOH3_USB_CLKONOFF_CTRL);

sys/arch/evbarm/kobo/kobo_usb.c

130

reg &= ~USB_CLKONOFF_CTRL_OTG_AHBCLK_OFF;

sys/arch/evbarm/kobo/kobo_usb.c

131

bus_space_write_4(usbc->sc_iot, usbc->sc_ioh, USBOH3_USB_CLKONOFF_CTRL, reg);

sys/arch/evbarm/kobo/kobo_usb.c

137

reg = bus_space_read_4(usbc->sc_iot, usbc->sc_ioh, USBOH3_PHYCTRL0);

sys/arch/evbarm/kobo/kobo_usb.c

138

reg |= PHYCTRL0_OTG_OVER_CUR_DIS | PHYCTRL0_SUSPENDM;

sys/arch/evbarm/kobo/kobo_usb.c

139

bus_space_write_4(usbc->sc_iot, usbc->sc_ioh, USBOH3_PHYCTRL0, reg);

sys/arch/evbarm/kobo/kobo_usb.c

141

reg = bus_space_read_4(usbc->sc_iot, usbc->sc_ioh, USBOH3_USBCTRL);

sys/arch/evbarm/kobo/kobo_usb.c

142

reg &= ~USBCTRL_OWIR;

sys/arch/evbarm/kobo/kobo_usb.c

143

bus_space_write_4(usbc->sc_iot, usbc->sc_ioh, USBOH3_USBCTRL, reg);

sys/arch/evbarm/kobo/kobo_usb.c

145

reg = bus_space_read_4(usbc->sc_iot, usbc->sc_ioh, USBOH3_PHYCTRL1);

sys/arch/evbarm/kobo/kobo_usb.c

146

reg = (reg & ~PHYCTRL1_PLLDIVVALUE_MASK) | PHYCTRL1_PLLDIVVALUE_24MHZ;

sys/arch/evbarm/kobo/kobo_usb.c

147

bus_space_write_4(usbc->sc_iot, usbc->sc_ioh, USBOH3_PHYCTRL1, reg);

sys/arch/evbarm/kobo/kobo_usb.c

154

uint32_t reg;

sys/arch/evbarm/kobo/kobo_usb.c

156

reg = bus_space_read_4(usbc->sc_iot, usbc->sc_ioh, USBOH3_USB_CLKONOFF_CTRL);

sys/arch/evbarm/kobo/kobo_usb.c

157

reg &= ~USB_CLKONOFF_CTRL_H1_AHBCLK_OFF;

sys/arch/evbarm/kobo/kobo_usb.c

158

bus_space_write_4(usbc->sc_iot, usbc->sc_ioh, USBOH3_USB_CLKONOFF_CTRL, reg);

sys/arch/evbarm/kobo/kobo_usb.c

165

reg = bus_space_read_4(usbc->sc_iot, usbc->sc_ioh,

sys/arch/evbarm/kobo/kobo_usb.c

167

reg |= USBCTRL_H1PM;

sys/arch/evbarm/kobo/kobo_usb.c

168

reg &= ~(USBCTRL_H1WIE);

sys/arch/evbarm/kobo/kobo_usb.c

169

reg &= ~(USBCTRL_H1UIE);

sys/arch/evbarm/kobo/kobo_usb.c

171

USBOH3_USBCTRL, reg);

sys/arch/evbarm/kobo/kobo_usb.c

173

reg = bus_space_read_4(usbc->sc_iot, usbc->sc_ioh, USBOH3_PHYCTRL0);

sys/arch/evbarm/kobo/kobo_usb.c

174

reg &= ~PHYCTRL0_H1_OVER_CUR_DIS;

sys/arch/evbarm/kobo/kobo_usb.c

175

reg |= PHYCTRL0_H1_OVER_CUR_POL;

sys/arch/evbarm/kobo/kobo_usb.c

176

bus_space_write_4(usbc->sc_iot, usbc->sc_ioh,USBOH3_PHYCTRL0 , reg);

sys/arch/evbarm/kobo/kobo_usb.c

180

reg = bus_space_read_4(usbc->sc_iot, usbc->sc_ioh, USBOH3_UH1_PHY_CTRL_1);

sys/arch/evbarm/kobo/kobo_usb.c

181

reg &= ~PHYCTRL1_PLLDIVVALUE_MASK;

sys/arch/evbarm/kobo/kobo_usb.c

182

reg |= PHYCTRL1_PLLDIVVALUE_24MHZ;

sys/arch/evbarm/kobo/kobo_usb.c

183

bus_space_write_4(usbc->sc_iot, usbc->sc_ioh, USBOH3_UH1_PHY_CTRL_1, reg);

sys/arch/evbarm/kobo/kobo_usb.c

185

reg = bus_space_read_4(usbc->sc_iot, usbc->sc_ioh, USBOH3_UH1_PHY_CTRL_0);

sys/arch/evbarm/kobo/kobo_usb.c

186

reg &= ~PHYCTRL0_CHGRDETON;

sys/arch/evbarm/kobo/kobo_usb.c

187

reg &= ~PHYCTRL0_CHGRDETEN;

sys/arch/evbarm/kobo/kobo_usb.c

188

bus_space_write_4(usbc->sc_iot, usbc->sc_ioh, USBOH3_UH1_PHY_CTRL_0, reg);

sys/arch/evbarm/lubbock/lubbock_lcd.c

240

uint16_t reg;

sys/arch/evbarm/lubbock/lubbock_lcd.c

244

reg = bus_space_read_2( osc->sc_iot, osc->sc_obioreg_ioh,

sys/arch/evbarm/lubbock/lubbock_lcd.c

247

reg |= MISCWR_LCDDISP;

sys/arch/evbarm/lubbock/lubbock_lcd.c

249

reg &= ~MISCWR_LCDDISP;

sys/arch/evbarm/lubbock/lubbock_lcd.c

251

LUBBOCK_MISCWR, reg );

sys/arch/evbarm/mini2440/audio_mini2440.c

153

uint32_t reg;

sys/arch/evbarm/mini2440/audio_mini2440.c

176

reg = bus_space_read_4(s3sc->sc_iot, s3sc->sc_gpio_ioh, GPIO_PBCON);

sys/arch/evbarm/mini2440/audio_mini2440.c

177

reg = GPIO_SET_FUNC(reg, 2, 1);

sys/arch/evbarm/mini2440/audio_mini2440.c

178

reg = GPIO_SET_FUNC(reg, 3, 1);

sys/arch/evbarm/mini2440/audio_mini2440.c

179

reg = GPIO_SET_FUNC(reg, 4, 1);

sys/arch/evbarm/mini2440/audio_mini2440.c

180

bus_space_write_4(s3sc->sc_iot, s3sc->sc_gpio_ioh, GPIO_PBCON, reg);

sys/arch/evbarm/mini2440/audio_mini2440.c

182

reg = bus_space_read_4(s3sc->sc_iot, s3sc->sc_gpio_ioh, GPIO_PBDAT);

sys/arch/evbarm/mini2440/audio_mini2440.c

183

reg = GPIO_SET_DATA(reg, 4, 1);

sys/arch/evbarm/mini2440/audio_mini2440.c

184

reg = GPIO_SET_DATA(reg, 3, 0);

sys/arch/evbarm/mini2440/audio_mini2440.c

185

reg = GPIO_SET_DATA(reg, 2, 1);

sys/arch/evbarm/mini2440/audio_mini2440.c

186

bus_space_write_4(s3sc->sc_iot, s3sc->sc_gpio_ioh, GPIO_PBDAT, reg);

sys/arch/evbarm/mini2440/audio_mini2440.c

414

uint32_t reg;

sys/arch/evbarm/mini2440/audio_mini2440.c

427

reg = READ_GPIO();

sys/arch/evbarm/mini2440/audio_mini2440.c

428

reg = GPIO_SET_DATA(reg, L3CLOCK, 1);

sys/arch/evbarm/mini2440/audio_mini2440.c

429

reg = GPIO_SET_DATA(reg, L3MODE, mode);

sys/arch/evbarm/mini2440/audio_mini2440.c

430

reg = GPIO_SET_DATA(reg, L3DATA, 0);

sys/arch/evbarm/mini2440/audio_mini2440.c

431

WRITE_GPIO(reg);

sys/arch/evbarm/mini2440/audio_mini2440.c

434

reg = READ_GPIO();

sys/arch/evbarm/mini2440/audio_mini2440.c

435

reg = GPIO_SET_DATA(reg, L3MODE, 1);

sys/arch/evbarm/mini2440/audio_mini2440.c

436

WRITE_GPIO(reg);

sys/arch/evbarm/mini2440/audio_mini2440.c

444

reg = READ_GPIO();

sys/arch/evbarm/mini2440/audio_mini2440.c

445

reg = GPIO_SET_DATA(reg, L3CLOCK, 0);

sys/arch/evbarm/mini2440/audio_mini2440.c

446

reg = GPIO_SET_DATA(reg, L3DATA, bval);

sys/arch/evbarm/mini2440/audio_mini2440.c

447

WRITE_GPIO(reg);

sys/arch/evbarm/mini2440/audio_mini2440.c

451

reg = READ_GPIO();

sys/arch/evbarm/mini2440/audio_mini2440.c

452

reg = GPIO_SET_DATA(reg, L3CLOCK, 1);

sys/arch/evbarm/mini2440/audio_mini2440.c

453

reg = GPIO_SET_DATA(reg, L3DATA, bval);

sys/arch/evbarm/mini2440/audio_mini2440.c

454

WRITE_GPIO(reg);

sys/arch/evbarm/mini2440/audio_mini2440.c

459

reg = READ_GPIO();

sys/arch/evbarm/mini2440/audio_mini2440.c

460

reg = GPIO_SET_DATA(reg, L3MODE, 1);

sys/arch/evbarm/mini2440/audio_mini2440.c

461

reg = GPIO_SET_DATA(reg, L3CLOCK, 1);

sys/arch/evbarm/mini2440/audio_mini2440.c

462

reg = GPIO_SET_DATA(reg, L3DATA, 0);

sys/arch/evbarm/mini2440/audio_mini2440.c

463

WRITE_GPIO(reg);

sys/arch/evbarm/netwalker/netwalker_lcd.c

130

uint32_t reg;

sys/arch/evbarm/netwalker/netwalker_lcd.c

137

reg = bus_space_read_4(iot, mipi_ioh, 0x800);

sys/arch/evbarm/netwalker/netwalker_lcd.c

138

bus_space_write_4(iot, mipi_ioh, 0x800, reg | 0x0ff);

sys/arch/evbarm/netwalker/netwalker_lcd.c

140

reg = bus_space_read_4(iot, mipi_ioh, 0x800);

sys/arch/evbarm/netwalker/netwalker_lcd.c

141

bus_space_write_4(iot, mipi_ioh, 0x800, reg | 0x10000);

sys/arch/evbarm/netwalker/netwalker_machdep.c

361

uint16_t reg;

sys/arch/evbarm/netwalker/netwalker_machdep.c

378

.reg = (offset), \

sys/arch/evbarm/netwalker/netwalker_machdep.c

624

ioreg_write(NETWALKER_IOMUXC_VBASE + p->reg,

sys/arch/evbarm/netwalker/netwalker_usb.c

125

uint32_t reg;

sys/arch/evbarm/netwalker/netwalker_usb.c

131

reg = bus_space_read_4(usbc->sc_iot, usbc->sc_ioh, USBOH3_PHYCTRL0);

sys/arch/evbarm/netwalker/netwalker_usb.c

132

reg |= PHYCTRL0_OTG_OVER_CUR_DIS;

sys/arch/evbarm/netwalker/netwalker_usb.c

133

bus_space_write_4(usbc->sc_iot, usbc->sc_ioh, USBOH3_PHYCTRL0, reg);

sys/arch/evbarm/netwalker/netwalker_usb.c

135

reg = bus_space_read_4(usbc->sc_iot, usbc->sc_ioh, USBOH3_USBCTRL);

sys/arch/evbarm/netwalker/netwalker_usb.c

136

reg &= ~(USBCTRL_OWIR|USBCTRL_OPM);

sys/arch/evbarm/netwalker/netwalker_usb.c

137

bus_space_write_4(usbc->sc_iot, usbc->sc_ioh, USBOH3_USBCTRL, reg);

sys/arch/evbarm/netwalker/netwalker_usb.c

139

reg = bus_space_read_4(usbc->sc_iot, usbc->sc_ioh, USBOH3_PHYCTRL1);

sys/arch/evbarm/netwalker/netwalker_usb.c

140

reg = (reg & ~PHYCTRL1_PLLDIVVALUE_MASK) | PHYCTRL1_PLLDIVVALUE_24MHZ;

sys/arch/evbarm/netwalker/netwalker_usb.c

141

bus_space_write_4(usbc->sc_iot, usbc->sc_ioh, USBOH3_PHYCTRL1, reg);

sys/arch/evbarm/netwalker/netwalker_usb.c

148

uint32_t reg;

sys/arch/evbarm/netwalker/netwalker_usb.c

163

reg = bus_space_read_4(usbc->sc_iot, usbc->sc_ioh,

sys/arch/evbarm/netwalker/netwalker_usb.c

165

reg |= USBCTRL1_UH1_EXT_CLK_EN;

sys/arch/evbarm/netwalker/netwalker_usb.c

167

USBOH3_USBCTRL1, reg);

sys/arch/evbarm/netwalker/netwalker_usb.c

173

reg = bus_space_read_4(usbc->sc_iot, usbc->sc_ioh,

sys/arch/evbarm/netwalker/netwalker_usb.c

175

reg &= ~(USBCTRL_H1PM);

sys/arch/evbarm/netwalker/netwalker_usb.c

176

reg |= USBCTRL_H1UIE|USBCTRL_H1WIE;

sys/arch/evbarm/netwalker/netwalker_usb.c

178

USBOH3_USBCTRL, reg);

sys/arch/evbarm/nslu2/nslu2_buttons.c

113

uint32_t reg;

sys/arch/evbarm/nslu2/nslu2_buttons.c

118

reg = GPIO_CONF_READ_4(ixsc, IXP425_GPIO_GPOER);

sys/arch/evbarm/nslu2/nslu2_buttons.c

119

reg |= SLUGBUTT_PWR_BIT | SLUGBUTT_RST_BIT;

sys/arch/evbarm/nslu2/nslu2_buttons.c

120

GPIO_CONF_WRITE_4(ixsc, IXP425_GPIO_GPOER, reg);

sys/arch/evbarm/nslu2/nslu2_buttons.c

123

reg = GPIO_CONF_READ_4(ixsc, GPIO_TYPE_REG(GPIO_BUTTON_PWR));

sys/arch/evbarm/nslu2/nslu2_buttons.c

124

reg &= ~GPIO_TYPE(GPIO_BUTTON_PWR, GPIO_TYPE_MASK);

sys/arch/evbarm/nslu2/nslu2_buttons.c

125

reg |= GPIO_TYPE(GPIO_BUTTON_PWR, GPIO_TYPE_EDG_FALLING);

sys/arch/evbarm/nslu2/nslu2_buttons.c

126

GPIO_CONF_WRITE_4(ixsc, GPIO_TYPE_REG(GPIO_BUTTON_PWR), reg);

sys/arch/evbarm/nslu2/nslu2_buttons.c

128

reg = GPIO_CONF_READ_4(ixsc, GPIO_TYPE_REG(GPIO_BUTTON_RST));

sys/arch/evbarm/nslu2/nslu2_buttons.c

129

reg &= ~GPIO_TYPE(GPIO_BUTTON_RST, GPIO_TYPE_MASK);

sys/arch/evbarm/nslu2/nslu2_buttons.c

130

reg |= GPIO_TYPE(GPIO_BUTTON_RST, GPIO_TYPE_EDG_FALLING);

sys/arch/evbarm/nslu2/nslu2_buttons.c

131

GPIO_CONF_WRITE_4(ixsc, GPIO_TYPE_REG(GPIO_BUTTON_RST), reg);

sys/arch/evbarm/nslu2/nslu2_iic.c

109

reg = GPIO_CONF_READ_4(ixp425_softc, IXP425_GPIO_GPOUTR);

sys/arch/evbarm/nslu2/nslu2_iic.c

110

if ((reg & GPIO_I2C_SDA_BIT) == 0) {

sys/arch/evbarm/nslu2/nslu2_iic.c

111

reg = GPIO_CONF_READ_4(ixp425_softc, IXP425_GPIO_GPOER);

sys/arch/evbarm/nslu2/nslu2_iic.c

112

reg &= ~GPIO_I2C_SDA_BIT;

sys/arch/evbarm/nslu2/nslu2_iic.c

113

GPIO_CONF_WRITE_4(ixp425_softc, IXP425_GPIO_GPOER, reg);

sys/arch/evbarm/nslu2/nslu2_iic.c

117

reg = GPIO_CONF_READ_4(ixp425_softc, IXP425_GPIO_GPOER);

sys/arch/evbarm/nslu2/nslu2_iic.c

118

reg |= GPIO_I2C_SDA_BIT;

sys/arch/evbarm/nslu2/nslu2_iic.c

119

GPIO_CONF_WRITE_4(ixp425_softc, IXP425_GPIO_GPOER, reg);

sys/arch/evbarm/nslu2/nslu2_iic.c

167

uint32_t reg;

sys/arch/evbarm/nslu2/nslu2_iic.c

169

reg = GPIO_CONF_READ_4(ixp425_softc, IXP425_GPIO_GPINR);

sys/arch/evbarm/nslu2/nslu2_iic.c

170

return (reg & (GPIO_I2C_SDA_BIT | GPIO_I2C_SCL_BIT));

sys/arch/evbarm/nslu2/nslu2_iic.c

177

uint32_t reg;

sys/arch/evbarm/nslu2/nslu2_iic.c

179

reg = GPIO_CONF_READ_4(ixp425_softc, IXP425_GPIO_GPOUTR);

sys/arch/evbarm/nslu2/nslu2_iic.c

180

reg |= GPIO_I2C_SDA_BIT | GPIO_I2C_SCL_BIT;

sys/arch/evbarm/nslu2/nslu2_iic.c

181

GPIO_CONF_WRITE_4(ixp425_softc, IXP425_GPIO_GPOUTR, reg);

sys/arch/evbarm/nslu2/nslu2_iic.c

183

reg = GPIO_CONF_READ_4(ixp425_softc, IXP425_GPIO_GPOER);

sys/arch/evbarm/nslu2/nslu2_iic.c

184

reg &= ~GPIO_I2C_SCL_BIT;

sys/arch/evbarm/nslu2/nslu2_iic.c

185

reg |= GPIO_I2C_SDA_BIT;

sys/arch/evbarm/nslu2/nslu2_iic.c

186

GPIO_CONF_WRITE_4(ixp425_softc, IXP425_GPIO_GPOER, reg);

sys/arch/evbarm/nslu2/nslu2_iic.c

97

uint32_t reg;

sys/arch/evbarm/nslu2/nslu2_leds.c

100

GPIO_CONF_WRITE_4(ixp425_softc, IXP425_GPIO_GPOUTR, reg);

sys/arch/evbarm/nslu2/nslu2_leds.c

112

uint32_t reg;

sys/arch/evbarm/nslu2/nslu2_leds.c

116

reg = GPIO_CONF_READ_4(ixp425_softc, IXP425_GPIO_GPOUTR);

sys/arch/evbarm/nslu2/nslu2_leds.c

117

reg &= ~LEDBITS_USB1;

sys/arch/evbarm/nslu2/nslu2_leds.c

118

GPIO_CONF_WRITE_4(ixp425_softc, IXP425_GPIO_GPOUTR, reg);

sys/arch/evbarm/nslu2/nslu2_leds.c

130

uint32_t reg;

sys/arch/evbarm/nslu2/nslu2_leds.c

134

reg = GPIO_CONF_READ_4(ixp425_softc, IXP425_GPIO_GPOUTR);

sys/arch/evbarm/nslu2/nslu2_leds.c

135

reg &= ~(LEDBITS_USB0 | LEDBITS_USB1);

sys/arch/evbarm/nslu2/nslu2_leds.c

136

GPIO_CONF_WRITE_4(ixp425_softc, IXP425_GPIO_GPOUTR, reg);

sys/arch/evbarm/nslu2/nslu2_leds.c

148

uint32_t reg, bit;

sys/arch/evbarm/nslu2/nslu2_leds.c

158

reg = GPIO_CONF_READ_4(ixp425_softc, IXP425_GPIO_GPOUTR);

sys/arch/evbarm/nslu2/nslu2_leds.c

159

reg &= ~LEDBITS_STATUS;

sys/arch/evbarm/nslu2/nslu2_leds.c

160

GPIO_CONF_WRITE_4(ixp425_softc, IXP425_GPIO_GPOUTR, reg | bit);

sys/arch/evbarm/nslu2/nslu2_leds.c

170

uint32_t reg;

sys/arch/evbarm/nslu2/nslu2_leds.c

185

reg = GPIO_CONF_READ_4(ixp425_softc,IXP425_GPIO_GPOUTR);

sys/arch/evbarm/nslu2/nslu2_leds.c

186

reg |= LEDBITS_USB0 | LEDBITS_USB1 | LEDBITS_STATUS | LEDBITS_READY;

sys/arch/evbarm/nslu2/nslu2_leds.c

187

GPIO_CONF_WRITE_4(ixp425_softc,IXP425_GPIO_GPOUTR, reg);

sys/arch/evbarm/nslu2/nslu2_leds.c

196

uint32_t reg;

sys/arch/evbarm/nslu2/nslu2_leds.c

202

reg = GPIO_CONF_READ_4(ixsc, IXP425_GPIO_GPOER);

sys/arch/evbarm/nslu2/nslu2_leds.c

203

reg &= ~(LEDBITS_USB0 | LEDBITS_USB1);

sys/arch/evbarm/nslu2/nslu2_leds.c

204

reg &= ~(LEDBITS_READY | LEDBITS_STATUS);

sys/arch/evbarm/nslu2/nslu2_leds.c

205

GPIO_CONF_WRITE_4(ixsc, IXP425_GPIO_GPOER, reg);

sys/arch/evbarm/nslu2/nslu2_leds.c

208

reg = GPIO_CONF_READ_4(ixsc, IXP425_GPIO_GPOUTR);

sys/arch/evbarm/nslu2/nslu2_leds.c

209

reg |= LEDBITS_USB0 | LEDBITS_USB1;

sys/arch/evbarm/nslu2/nslu2_leds.c

210

reg &= ~(LEDBITS_STATUS | LEDBITS_READY);

sys/arch/evbarm/nslu2/nslu2_leds.c

211

GPIO_CONF_WRITE_4(ixsc, IXP425_GPIO_GPOUTR, reg);

sys/arch/evbarm/nslu2/nslu2_leds.c

79

uint32_t reg, bit;

sys/arch/evbarm/nslu2/nslu2_leds.c

85

reg = GPIO_CONF_READ_4(ixp425_softc, IXP425_GPIO_GPOUTR);

sys/arch/evbarm/nslu2/nslu2_leds.c

86

GPIO_CONF_WRITE_4(ixp425_softc, IXP425_GPIO_GPOUTR, reg | bit);

sys/arch/evbarm/nslu2/nslu2_leds.c

94

uint32_t reg;

sys/arch/evbarm/nslu2/nslu2_leds.c

98

reg = GPIO_CONF_READ_4(ixp425_softc, IXP425_GPIO_GPOUTR);

sys/arch/evbarm/nslu2/nslu2_leds.c

99

reg &= ~LEDBITS_USB0;

sys/arch/evbarm/nslu2/nslu2_machdep.c

301

uint32_t reg;

sys/arch/evbarm/nslu2/nslu2_machdep.c

313

reg = GPRD(IXP425_GPIO_GPOUTR);

sys/arch/evbarm/nslu2/nslu2_machdep.c

314

reg |= 1u << GPIO_POWER_OFF;

sys/arch/evbarm/nslu2/nslu2_machdep.c

315

GPWR(IXP425_GPIO_GPOUTR, reg);

sys/arch/evbarm/nslu2/nslu2_machdep.c

319

reg = GPRD(IXP425_GPIO_GPOUTR);

sys/arch/evbarm/nslu2/nslu2_machdep.c

320

reg &= ~(1u << GPIO_POWER_OFF);

sys/arch/evbarm/nslu2/nslu2_machdep.c

321

GPWR(IXP425_GPIO_GPOUTR, reg);

sys/arch/evbarm/nslu2/nslu2_machdep.c

420

uint32_t reg;

sys/arch/evbarm/nslu2/nslu2_machdep.c

427

reg = GPRD(IXP425_GPIO_GPOUTR);

sys/arch/evbarm/nslu2/nslu2_machdep.c

428

reg &= ~(1u << GPIO_POWER_OFF);

sys/arch/evbarm/nslu2/nslu2_machdep.c

429

GPWR(IXP425_GPIO_GPOUTR, reg);

sys/arch/evbarm/nslu2/nslu2_machdep.c

432

reg = GPRD(IXP425_GPIO_GPOER);

sys/arch/evbarm/nslu2/nslu2_machdep.c

433

reg &= ~(1u << GPIO_POWER_OFF);

sys/arch/evbarm/nslu2/nslu2_machdep.c

434

GPWR(IXP425_GPIO_GPOER, reg);

sys/arch/evbarm/nslu2/nslu2_pci.c

162

uint32_t reg;

sys/arch/evbarm/nslu2/nslu2_pci.c

172

reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPOUTR);

sys/arch/evbarm/nslu2/nslu2_pci.c

173

reg &= ~(1u << GPIO_PCI_RESET);

sys/arch/evbarm/nslu2/nslu2_pci.c

174

GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPOUTR, reg);

sys/arch/evbarm/nslu2/nslu2_pci.c

177

reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPCLKR);

sys/arch/evbarm/nslu2/nslu2_pci.c

178

reg &= ~GPCLKR_MUX14;

sys/arch/evbarm/nslu2/nslu2_pci.c

179

GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPCLKR, reg);

sys/arch/evbarm/nslu2/nslu2_pci.c

186

reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPOER);

sys/arch/evbarm/nslu2/nslu2_pci.c

187

reg &= ~((1u << GPIO_PCI_CLK) | (1u << GPIO_PCI_RESET));

sys/arch/evbarm/nslu2/nslu2_pci.c

188

reg |= (1u << GPIO_PCI_INTA) | (1u << GPIO_PCI_INTB) |

sys/arch/evbarm/nslu2/nslu2_pci.c

190

GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPOER, reg);

sys/arch/evbarm/nslu2/nslu2_pci.c

196

reg = GPIO_CONF_READ_4(sc, GPIO_TYPE_REG(GPIO_PCI_INTA));

sys/arch/evbarm/nslu2/nslu2_pci.c

197

reg &= ~GPIO_TYPE(GPIO_PCI_INTA, GPIO_TYPE_MASK);

sys/arch/evbarm/nslu2/nslu2_pci.c

198

reg |= GPIO_TYPE(GPIO_PCI_INTA, GPIO_TYPE_ACT_LOW);

sys/arch/evbarm/nslu2/nslu2_pci.c

199

GPIO_CONF_WRITE_4(sc, GPIO_TYPE_REG(GPIO_PCI_INTA), reg);

sys/arch/evbarm/nslu2/nslu2_pci.c

201

reg = GPIO_CONF_READ_4(sc, GPIO_TYPE_REG(GPIO_PCI_INTB));

sys/arch/evbarm/nslu2/nslu2_pci.c

202

reg &= ~GPIO_TYPE(GPIO_PCI_INTB, GPIO_TYPE_MASK);

sys/arch/evbarm/nslu2/nslu2_pci.c

203

reg |= GPIO_TYPE(GPIO_PCI_INTB, GPIO_TYPE_ACT_LOW);

sys/arch/evbarm/nslu2/nslu2_pci.c

204

GPIO_CONF_WRITE_4(sc, GPIO_TYPE_REG(GPIO_PCI_INTB), reg);

sys/arch/evbarm/nslu2/nslu2_pci.c

206

reg = GPIO_CONF_READ_4(sc, GPIO_TYPE_REG(GPIO_PCI_INTC));

sys/arch/evbarm/nslu2/nslu2_pci.c

207

reg &= ~GPIO_TYPE(GPIO_PCI_INTC, GPIO_TYPE_MASK);

sys/arch/evbarm/nslu2/nslu2_pci.c

208

reg |= GPIO_TYPE(GPIO_PCI_INTC, GPIO_TYPE_ACT_LOW);

sys/arch/evbarm/nslu2/nslu2_pci.c

209

GPIO_CONF_WRITE_4(sc, GPIO_TYPE_REG(GPIO_PCI_INTC), reg);

sys/arch/evbarm/nslu2/nslu2_pci.c

217

reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPCLKR);

sys/arch/evbarm/nslu2/nslu2_pci.c

218

reg |= (0xf << GPCLKR_CLK0DC_SHIFT) | (0xf << GPCLKR_CLK0TC_SHIFT);

sys/arch/evbarm/nslu2/nslu2_pci.c

219

GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPCLKR, reg);

sys/arch/evbarm/nslu2/nslu2_pci.c

222

reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPCLKR);

sys/arch/evbarm/nslu2/nslu2_pci.c

223

reg |= GPCLKR_MUX14;

sys/arch/evbarm/nslu2/nslu2_pci.c

224

GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPCLKR, reg);

sys/arch/evbarm/nslu2/nslu2_pci.c

232

reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPOUTR);

sys/arch/evbarm/nslu2/nslu2_pci.c

233

reg |= 1u << GPIO_PCI_RESET;

sys/arch/evbarm/nslu2/nslu2_pci.c

234

GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPOUTR, reg);

sys/arch/evbarm/nslu2/nslu2_pci.c

248

reg = (AHB_OFFSET + 0x00000000) >> 0;

sys/arch/evbarm/nslu2/nslu2_pci.c

249

reg |= (AHB_OFFSET + 0x01000000) >> 8;

sys/arch/evbarm/nslu2/nslu2_pci.c

250

reg |= (AHB_OFFSET + 0x02000000) >> 16;

sys/arch/evbarm/nslu2/nslu2_pci.c

251

reg |= (AHB_OFFSET + 0x03000000) >> 24;

sys/arch/evbarm/nslu2/nslu2_pci.c

252

PCI_CSR_WRITE_4(sc, PCI_AHBMEMBASE, reg);

sys/arch/evbarm/smdk2xx0/smdk2410_kbd.c

267

uint32_t reg;

sys/arch/evbarm/smdk2xx0/smdk2410_kbd.c

281

reg = bus_space_read_2(iot, gpioh, GPIO_PGUP);

sys/arch/evbarm/smdk2xx0/smdk2410_kbd.c

282

bus_space_write_2(iot, gpioh, GPIO_PGUP, reg & ~(1<<5));

sys/arch/evbarm/smdk2xx0/smdk2410_kbd.c

288

reg = bus_space_read_4(iot, gpioh, GPIO_PBCON);

sys/arch/evbarm/smdk2xx0/smdk2410_kbd.c

289

reg = GPIO_SET_FUNC(reg, SSKBD_WUP, PCON_OUTPUT);

sys/arch/evbarm/smdk2xx0/smdk2410_kbd.c

290

reg = GPIO_SET_FUNC(reg, SSKBD_SS, PCON_OUTPUT);

sys/arch/evbarm/smdk2xx0/smdk2410_kbd.c

291

bus_space_write_4(iot, gpioh, GPIO_PBCON, reg);

sys/arch/evbarm/smdk2xx0/smdk2410_kbd.c

294

reg = bus_space_read_4(iot, gpioh, GPIO_PFCON);

sys/arch/evbarm/smdk2xx0/smdk2410_kbd.c

295

reg = GPIO_SET_FUNC(reg, 1, PCON_ALTFUN);

sys/arch/evbarm/smdk2xx0/smdk2410_kbd.c

296

bus_space_write_4(iot, gpioh, GPIO_PFCON, reg);

sys/arch/evbarm/smdk2xx0/smdk2410_kbd.c

301

reg = bus_space_read_4(iot, gpioh, GPIO_PBDAT);

sys/arch/evbarm/smdk2xx0/smdk2410_kbd.c

302

reg &= ~(1<<SSKBD_WUP);

sys/arch/evbarm/smdk2xx0/smdk2410_kbd.c

303

bus_space_write_4(iot, gpioh, GPIO_PBDAT, reg);

sys/arch/evbarm/smdk2xx0/smdk2410_kbd.c

305

reg |= (1<<SSKBD_WUP);

sys/arch/evbarm/smdk2xx0/smdk2410_kbd.c

306

bus_space_write_4(iot, gpioh, GPIO_PBDAT, reg);

sys/arch/evbarm/smdk2xx0/smdk2410_kbd.c

355

uint32_t reg;

sys/arch/evbarm/smdk2xx0/smdk2410_kbd.c

371

reg = bus_space_read_2(sc->iot, sc->gpioh, GPIO_PBDAT);

sys/arch/evbarm/smdk2xx0/smdk2410_kbd.c

373

reg & ~(1<<SSKBD_SS));

sys/arch/evbarm/smdk2xx0/smdk2410_kbd.c

391

uint32_t reg;

sys/arch/evbarm/smdk2xx0/smdk2410_kbd.c

401

reg = bus_space_read_2(sc->iot, sc->gpioh, GPIO_PBDAT);

sys/arch/evbarm/smdk2xx0/smdk2410_kbd.c

403

reg | (1<<SSKBD_SS));

sys/arch/evbarm/smdk2xx0/smdk2410_machdep.c

414

#define gpio_read8(reg) ioreg_read8(GPIO_VBASE + (reg))

sys/arch/evbarm/smdk2xx0/smdk2800_machdep.c

355

#define gpio8(reg) (*(volatile uint8_t *)(ioreg_vaddr(S3C2800_GPIO_BASE) + (reg)))

sys/arch/evbarm/stand/board/becc_mem.c

65

uint32_t start, size, reg, save, heap;

sys/arch/evbarm/stand/board/becc_mem.c

76

reg = BECC_PCICORE_READ(PCI_CLASS_REG);

sys/arch/evbarm/stand/board/becc_mem.c

78

if (PCI_REVISION(reg) <= BECC_REV_V7)

sys/arch/evbarm/stand/board/becc_mem.c

84

reg = BECC_PCICORE_READ(BECC_SDRAM_BAR);

sys/arch/evbarm/stand/board/becc_mem.c

88

size = PCI_MAPREG_MEM_SIZE(reg);

sys/arch/evbarm/stand/boot2440/dm9000.c

134

CSR_READ_1(struct local *l, int reg)

sys/arch/evbarm/stand/boot2440/dm9000.c

136

*(volatile uint8_t *)(l->csr) = reg;

sys/arch/evbarm/stand/boot2440/dm9000.c

141

CSR_READ_2(struct local *l, int reg)

sys/arch/evbarm/stand/boot2440/dm9000.c

143

*(volatile uint8_t *)(l->csr) = reg;

sys/arch/evbarm/stand/boot2440/dm9000.c

148

CSR_WRITE_1(struct local *l, int reg, int data)

sys/arch/evbarm/stand/boot2440/dm9000.c

150

*(volatile uint8_t *)(l->csr) = reg;

sys/arch/evbarm/stand/boot2440/dm9000.c

155

CSR_WRITE_2(struct local *l, int reg, int data)

sys/arch/evbarm/stand/boot2440/dm9000.c

157

*(volatile uint8_t *)(l->csr) = reg;

sys/arch/evbarm/stand/boot2440/dm9000.c

386

mii_read(struct local *l, int phy, int reg)

sys/arch/evbarm/stand/boot2440/dm9000.c

390

CSR_WRITE_1(l, EPAR, phy << 6 | reg);

sys/arch/evbarm/stand/boot2440/dm9000.c

401

mii_write(struct local *l, int phy, int reg, int data)

sys/arch/evbarm/stand/boot2440/dm9000.c

405

CSR_WRITE_1(l, EPAR, phy << 6 | reg);

sys/arch/evbarm/stand/boot2440/main.c

44

#define CSR_READ(reg) \

sys/arch/evbarm/stand/boot2440/main.c

45

*(volatile uint32_t *)(reg)

sys/arch/evbarm/stand/boot2440/main.c

46

#define CSR_WRITE(reg, val) do { \

sys/arch/evbarm/stand/boot2440/main.c

47

*(volatile uint32_t *)((reg)) = val; \

sys/arch/evbarm/stand/boot2440/s3csdi.c

40

#define SDI_REG(reg) (*(volatile uint32_t*)(S3C2440_SDI_BASE+reg))

sys/arch/evbarm/tsarm/tsrtc.c

138

tsrtc_write(struct mc146818_softc *mc_sc, u_int reg, u_int datum)

sys/arch/evbarm/tsarm/tsrtc.c

142

bus_space_write_1(sc->sc_iot, sc->sc_idxh, 0, reg);

sys/arch/evbarm/tsarm/tsrtc.c

147

tsrtc_read(struct mc146818_softc *mc_sc, u_int reg)

sys/arch/evbarm/tsarm/tsrtc.c

152

bus_space_write_1(sc->sc_iot, sc->sc_idxh, 0, reg);

sys/arch/evbmips/gdium/gdium_genfb.c

69

pcireg_t reg;

sys/arch/evbmips/gdium/gdium_genfb.c

80

reg = pci_conf_read(&gc->gc_pc, pci_make_tag(&gc->gc_pc, 0, 14, 0),

sys/arch/evbmips/gdium/gdium_genfb.c

83

ri->ri_bits = (char *)MIPS_PHYS_TO_KSEG1(BONITO_PCILO_BASE + reg);

sys/arch/evbmips/ingenic/cpu.c

81

uint32_t vec, reg;

sys/arch/evbmips/ingenic/cpu.c

89

reg = mips_cp0_corereim_read();

sys/arch/evbmips/ingenic/cpu.c

90

reg &= ~REIM_ENTRY_M;

sys/arch/evbmips/ingenic/cpu.c

91

reg |= vec;

sys/arch/evbmips/ingenic/cpu.c

92

mips_cp0_corereim_write(reg);

sys/arch/evbmips/ingenic/cpu.c

94

reg = mips_cp0_corectrl_read();

sys/arch/evbmips/ingenic/cpu.c

95

reg |= CC_RPC1; /* use our exception vector */

sys/arch/evbmips/ingenic/cpu.c

96

reg &= ~CC_SW_RST1; /* get core 1 out of reset */

sys/arch/evbmips/ingenic/cpu.c

97

mips_cp0_corectrl_write(reg);

sys/arch/evbmips/ingenic/intr.c

108

uint32_t reg;

sys/arch/evbmips/ingenic/intr.c

131

reg = mips_cp0_corereim_read();

sys/arch/evbmips/ingenic/intr.c

132

reg &= 0xffff0000;

sys/arch/evbmips/ingenic/intr.c

133

reg |= REIM_IRQ0_M | REIM_MIRQ0_M;

sys/arch/evbmips/ingenic/intr.c

135

reg |= REIM_MIRQ1_M;

sys/arch/evbmips/ingenic/intr.c

137

mips_cp0_corereim_write(reg);

sys/arch/evbmips/ingenic/intr.c

140

DPRINTF("%s %08x\n", __func__, reg);

sys/arch/evbmips/ingenic/intr.c

168

uint32_t reg;

sys/arch/evbmips/ingenic/intr.c

172

reg = mips_cp0_corestatus_read();

sys/arch/evbmips/ingenic/intr.c

174

if (reg & CS_MIRQ0_P) {

sys/arch/evbmips/ingenic/intr.c

186

reg &= (~CS_MIRQ0_P);

sys/arch/evbmips/ingenic/intr.c

188

mips_cp0_corestatus_write(reg);

sys/arch/evbmips/ingenic/intr.c

191

if (reg & CS_MIRQ1_P) {

sys/arch/evbmips/ingenic/intr.c

205

reg &= (~CS_MIRQ1_P);

sys/arch/evbmips/ingenic/intr.c

207

mips_cp0_corestatus_write(reg);

sys/arch/evbmips/ingenic/machdep.c

132

uint32_t reg;

sys/arch/evbmips/ingenic/machdep.c

135

reg = mips_cp0_corereim_read();

sys/arch/evbmips/ingenic/machdep.c

137

reg |= REIM_MIRQ1_M;

sys/arch/evbmips/ingenic/machdep.c

139

reg |= REIM_MIRQ0_M;

sys/arch/evbmips/ingenic/machdep.c

140

mips_cp0_corereim_write(reg);

sys/arch/evbmips/ingenic/machdep.c

141

printf("%s %d %08x\n", __func__, cpu_index(ci), reg);

sys/arch/evbmips/isa/mcclock_isa.c

133

mcclock_isa_write(struct mc146818_softc *sc, u_int reg, u_int datum)

sys/arch/evbmips/isa/mcclock_isa.c

138

bus_space_write_1(iot, ioh, 0, reg);

sys/arch/evbmips/isa/mcclock_isa.c

143

mcclock_isa_read(struct mc146818_softc *sc, u_int reg)

sys/arch/evbmips/isa/mcclock_isa.c

148

bus_space_write_1(iot, ioh, 0, reg);

sys/arch/evbmips/loongson/dev/glx.c

358

glx_fn0_read(int reg)

sys/arch/evbmips/loongson/dev/glx.c

364

switch (reg) {

sys/arch/evbmips/loongson/dev/glx.c

395

index = (reg - PCI_MAPREG_START) / 4;

sys/arch/evbmips/loongson/dev/glx.c

422

glx_fn0_write(int reg, pcireg_t data)

sys/arch/evbmips/loongson/dev/glx.c

427

switch (reg) {

sys/arch/evbmips/loongson/dev/glx.c

459

index = (reg - PCI_MAPREG_START) / 4;

sys/arch/evbmips/loongson/dev/glx.c

485

glx_fn2_read(int reg)

sys/arch/evbmips/loongson/dev/glx.c

490

switch (reg) {

sys/arch/evbmips/loongson/dev/glx.c

544

DPRINTF(("unimplemented pciide reg 0x%x\n", reg));

sys/arch/evbmips/loongson/dev/glx.c

553

glx_fn2_write(int reg, pcireg_t data)

sys/arch/evbmips/loongson/dev/glx.c

557

switch (reg) {

sys/arch/evbmips/loongson/dev/glx.c

598

DPRINTF(("unimplemented pciide reg 0x%x\n", reg));

sys/arch/evbmips/loongson/dev/glx.c

610

glx_fn3_read(int reg)

sys/arch/evbmips/loongson/dev/glx.c

615

switch (reg) {

sys/arch/evbmips/loongson/dev/glx.c

665

glx_fn3_write(int reg, pcireg_t data)

sys/arch/evbmips/loongson/dev/glx.c

669

switch (reg) {

sys/arch/evbmips/loongson/dev/glx.c

712

glx_fn4_read(int reg)

sys/arch/evbmips/loongson/dev/glx.c

717

switch (reg) {

sys/arch/evbmips/loongson/dev/glx.c

773

glx_fn4_write(int reg, pcireg_t data)

sys/arch/evbmips/loongson/dev/glx.c

777

switch (reg) {

sys/arch/evbmips/loongson/dev/glx.c

832

glx_fn5_read(int reg)

sys/arch/evbmips/loongson/dev/glx.c

837

switch (reg) {

sys/arch/evbmips/loongson/dev/glx.c

898

glx_fn5_write(int reg, pcireg_t data)

sys/arch/evbmips/loongson/dev/glx.c

902

switch (reg) {

sys/arch/evbmips/loongson/dev/kb3310.c

208

ykbec_write(struct ykbec_softc *mcsc, u_int reg, u_int datum)

sys/arch/evbmips/loongson/dev/kb3310.c

214

bus_space_write_1(iot, ioh, 0, (reg >> 8) & 0xff);

sys/arch/evbmips/loongson/dev/kb3310.c

215

bus_space_write_1(iot, ioh, 1, (reg >> 0) & 0xff);

sys/arch/evbmips/loongson/dev/kb3310.c

220

ykbec_read(struct ykbec_softc *mcsc, u_int reg)

sys/arch/evbmips/loongson/dev/kb3310.c

226

bus_space_write_1(iot, ioh, 0, (reg >> 8) & 0xff);

sys/arch/evbmips/loongson/dev/kb3310.c

227

bus_space_write_1(iot, ioh, 1, (reg >> 0) & 0xff);

sys/arch/evbmips/loongson/dev/kb3310.c

232

ykbec_read16(struct ykbec_softc *mcsc, u_int reg)

sys/arch/evbmips/loongson/dev/kb3310.c

236

val = ykbec_read(mcsc, reg);

sys/arch/evbmips/loongson/dev/kb3310.c

237

return (val << 8) | ykbec_read(mcsc, reg + 1);

sys/arch/evbmips/loongson/dev/stvii.c

146

uint8_t ver, reg;

sys/arch/evbmips/loongson/dev/stvii.c

167

reg = stvii_readreg(sc, ST7_CONTROL);

sys/arch/evbmips/loongson/dev/stvii.c

168

reg |= STC_RADIO_ENABLE;

sys/arch/evbmips/loongson/dev/stvii.c

169

stvii_writereg(sc, ST7_CONTROL, reg);

sys/arch/evbmips/loongson/dev/stvii.c

170

sc->sc_control = reg;

sys/arch/evbmips/loongson/dev/stvii.c

171

reg = stvii_readreg(sc, ST7_CONTROL);

sys/arch/evbmips/loongson/dev/stvii.c

202

stvii_writereg(struct stvii_softc *sc, int reg, uint8_t val)

sys/arch/evbmips/loongson/dev/stvii.c

204

uint8_t out[2] = {reg, val};

sys/arch/evbmips/loongson/dev/stvii.c

206

if ((reg < 0) || (reg > 5))

sys/arch/evbmips/loongson/dev/stvii.c

215

stvii_readreg(struct stvii_softc *sc, int reg)

sys/arch/evbmips/loongson/dev/stvii.c

220

if ((reg < 0) || (reg > 5))

sys/arch/evbmips/loongson/dev/stvii.c

223

outreg[0] = reg;

sys/arch/evbmips/loongson/gdium_machdep.c

106

pcireg_t reg;

sys/arch/evbmips/loongson/gdium_machdep.c

150

reg = pci_conf_read(pc, tag, 0xe0);

sys/arch/evbmips/loongson/gdium_machdep.c

152

reg |= 0x00000003;

sys/arch/evbmips/loongson/gdium_machdep.c

153

pci_conf_write(pc, tag, 0xe0, reg);

sys/arch/evbmips/loongson/gdium_machdep.c

164

reg = pci_conf_read(pc, tag, 0xe0);

sys/arch/evbmips/loongson/gdium_machdep.c

166

reg &= ~0x00000007;

sys/arch/evbmips/loongson/gdium_machdep.c

167

reg |= 0x00000005;

sys/arch/evbmips/loongson/gdium_machdep.c

168

pci_conf_write(pc, tag, 0xe0, reg);

sys/arch/evbmips/loongson/gdium_machdep.c

335

pcireg_t reg;

sys/arch/evbmips/loongson/gdium_machdep.c

355

reg = pci_conf_read(pc, tag, PCI_MAPREG_START);

sys/arch/evbmips/loongson/gdium_machdep.c

356

fb_addr = reg;

sys/arch/evbmips/loongson/gdium_machdep.c

358

ri->ri_bits = (char *)MIPS_PHYS_TO_KSEG1(BONITO_PCILO_BASE + reg);

sys/arch/evbmips/loongson/generic2e_machdep.c

505

pcireg_t reg;

sys/arch/evbmips/loongson/generic2e_machdep.c

514

reg = pci_conf_read(pc, tag, VIA686_ISA_ROM_CONTROL);

sys/arch/evbmips/loongson/generic2e_machdep.c

515

reg |= VIA686_IO_RECOVERY_TIME | VIA686_ISA_REFRESH;

sys/arch/evbmips/loongson/generic2e_machdep.c

516

pci_conf_write(pc, tag, VIA686_ISA_ROM_CONTROL, reg);

sys/arch/evbmips/loongson/generic2e_machdep.c

518

reg = pci_conf_read(pc, tag, VIA686_KBC_DMA_MISC12);

sys/arch/evbmips/loongson/generic2e_machdep.c

519

reg |= VIA686_CPU_RESET_SOURCE_INIT |

sys/arch/evbmips/loongson/generic2e_machdep.c

526

reg &= ~VIA686_ISA_MASTER_TO_LINE_BUFFER;

sys/arch/evbmips/loongson/generic2e_machdep.c

527

pci_conf_write(pc, tag, VIA686_KBC_DMA_MISC12, reg);

sys/arch/evbmips/loongson/generic2e_machdep.c

533

reg = pci_conf_read(pc, tag, VIA686_MISC3_IDE_INTR);

sys/arch/evbmips/loongson/generic2e_machdep.c

534

reg &= ~(VIA686_IDE_PRIMARY_CHAN_MASK | VIA686_IDE_SECONDARY_CHAN_MASK);

sys/arch/evbmips/loongson/generic2e_machdep.c

535

reg |= (VIA686_IDE_IRQ14 << VIA686_IDE_PRIMARY_CHAN_SHIFT);

sys/arch/evbmips/loongson/generic2e_machdep.c

536

reg |= (VIA686_IDE_IRQ15 << VIA686_IDE_SECONDARY_CHAN_SHIFT);

sys/arch/evbmips/loongson/generic2e_machdep.c

537

reg |= VIA686_IDE_PGNT;

sys/arch/evbmips/loongson/generic2e_machdep.c

538

pci_conf_write(pc, tag, VIA686_MISC3_IDE_INTR, reg);

sys/arch/evbmips/loongson/generic2e_machdep.c

540

reg = pci_conf_read(pc, tag, VIA686_PNP_DMA_IRQ);

sys/arch/evbmips/loongson/generic2e_machdep.c

541

reg &= ~(VIA686_DMA_FDC_MASK | VIA686_DMA_LPT_MASK);

sys/arch/evbmips/loongson/generic2e_machdep.c

542

reg |= (2 << VIA686_DMA_FDC_SHIFT) | (3 << VIA686_DMA_LPT_SHIFT);

sys/arch/evbmips/loongson/generic2e_machdep.c

543

reg &= ~(VIA686_IRQ_FDC_MASK | VIA686_IRQ_LPT_MASK);

sys/arch/evbmips/loongson/generic2e_machdep.c

544

reg |= (6 << VIA686_IRQ_FDC_SHIFT) | (7 << VIA686_IRQ_LPT_SHIFT);

sys/arch/evbmips/loongson/generic2e_machdep.c

545

reg &= ~(VIA686_IRQ_COM0_MASK | VIA686_IRQ_COM1_MASK);

sys/arch/evbmips/loongson/generic2e_machdep.c

546

reg |= (4 << VIA686_IRQ_COM0_SHIFT) | (3 << VIA686_IRQ_COM1_SHIFT);

sys/arch/evbmips/loongson/generic2e_machdep.c

548

reg = pci_conf_read(pc, tag, VIA686_PCI_LEVEL_PNP_IRQ2);

sys/arch/evbmips/loongson/generic2e_machdep.c

549

reg &= ~(VIA686_PCI_IRQA_EDGE | VIA686_PCI_IRQB_EDGE |

sys/arch/evbmips/loongson/generic2e_machdep.c

551

reg &= ~(VIA686_IRQ_PCIA_MASK | VIA686_IRQ_PCIB_MASK |

sys/arch/evbmips/loongson/generic2e_machdep.c

553

reg |= (VIA686_IRQ_PCIA << VIA686_IRQ_PCIA_SHIFT) |

sys/arch/evbmips/loongson/generic2e_machdep.c

606

reg = pci_conf_read(pc, tag, PCI_INTERRUPT_REG);

sys/arch/evbmips/loongson/generic2e_machdep.c

607

reg &= ~(PCI_INTERRUPT_LINE_MASK << PCI_INTERRUPT_LINE_SHIFT);

sys/arch/evbmips/loongson/generic2e_machdep.c

608

reg |= VIA686_IRQ_PCIB << PCI_INTERRUPT_LINE_SHIFT;

sys/arch/evbmips/loongson/generic2e_machdep.c

609

pci_conf_write(pc, tag, PCI_INTERRUPT_REG, reg);

sys/arch/evbmips/loongson/generic2e_machdep.c

612

reg = pci_conf_read(pc, tag, PCI_INTERRUPT_REG);

sys/arch/evbmips/loongson/generic2e_machdep.c

613

reg &= ~(PCI_INTERRUPT_LINE_MASK << PCI_INTERRUPT_LINE_SHIFT);

sys/arch/evbmips/loongson/generic2e_machdep.c

614

reg |= VIA686_IRQ_PCIC << PCI_INTERRUPT_LINE_SHIFT;

sys/arch/evbmips/loongson/generic2e_machdep.c

615

pci_conf_write(pc, tag, PCI_INTERRUPT_REG, reg);

sys/arch/evbmips/loongson/generic2e_machdep.c

618

reg = pci_conf_read(pc, tag, PCI_INTERRUPT_REG);

sys/arch/evbmips/loongson/generic2e_machdep.c

619

reg &= ~(PCI_INTERRUPT_LINE_MASK << PCI_INTERRUPT_LINE_SHIFT);

sys/arch/evbmips/loongson/generic2e_machdep.c

620

reg |= VIA686_IRQ_PCIA << PCI_INTERRUPT_LINE_SHIFT;

sys/arch/evbmips/loongson/generic2e_machdep.c

621

pci_conf_write(pc, tag, PCI_INTERRUPT_REG, reg);

sys/arch/evbmips/loongson/machdep.c

264

pcireg_t reg;

sys/arch/evbmips/loongson/machdep.c

530

reg = pci_conf_read(&bonito_pc, pcitag, PCI_CLASS_REG);

sys/arch/evbmips/loongson/machdep.c

531

DPRINTF(("dev %d class 0x%x", i, reg));

sys/arch/evbmips/loongson/machdep.c

532

reg = pci_conf_read(&bonito_pc, pcitag, PCI_ID_REG);

sys/arch/evbmips/loongson/machdep.c

533

DPRINTF((" id 0x%x; ", reg));

sys/arch/evbmips/loongson/machdep.c

537

pcitag, reg);

sys/arch/evbmips/loongson/machdep.c

542

pcitag, reg);

sys/arch/evbmips/loongson/machdep.c

546

pcitag, reg);

sys/arch/evbmips/malta/pci/pcib.c

437

int reg;

sys/arch/evbmips/malta/pci/pcib.c

441

reg = bus_space_read_1(sc->sc_iot, sc->sc_ioh_icu1,

sys/arch/evbmips/malta/pci/pcib.c

443

if (!(reg & (1 << 7)))

sys/arch/evbmips/sbmips/rtc.c

426

uint32_t reg;

sys/arch/evbmips/sbmips/rtc.c

428

reg = A_SMB_REGISTER(chan, R_SMB_FREQ);

sys/arch/evbmips/sbmips/rtc.c

429

WRITE_REG(reg, K_SMB_FREQ_100KHZ);

sys/arch/evbmips/sbmips/rtc.c

430

reg = A_SMB_REGISTER(chan, R_SMB_CONTROL);

sys/arch/evbmips/sbmips/rtc.c

431

WRITE_REG(reg, 0); /* not in direct mode, no interrupts, will poll */

sys/arch/evbmips/sbmips/rtc.c

437

uint32_t reg;

sys/arch/evbmips/sbmips/rtc.c

440

reg = A_SMB_REGISTER(chan, R_SMB_STATUS);

sys/arch/evbmips/sbmips/rtc.c

443

status = READ_REG(reg);

sys/arch/evbmips/sbmips/rtc.c

450

WRITE_REG(reg, (status & M_SMB_ERROR));

sys/arch/evbmips/sbmips/rtc.c

459

uint32_t reg;

sys/arch/evbmips/sbmips/rtc.c

477

reg = A_SMB_REGISTER(chan, R_SMB_CMD);

sys/arch/evbmips/sbmips/rtc.c

478

WRITE_REG(reg, (devaddr >> 8) & 0x7);

sys/arch/evbmips/sbmips/rtc.c

484

reg = A_SMB_REGISTER(chan, R_SMB_DATA);

sys/arch/evbmips/sbmips/rtc.c

485

WRITE_REG(reg, (devaddr & 0xff) & 0xff);

sys/arch/evbmips/sbmips/rtc.c

491

reg = A_SMB_REGISTER(chan, R_SMB_CMD);

sys/arch/evbmips/sbmips/rtc.c

492

WRITE_REG(reg, devaddr & 0xff);

sys/arch/evbmips/sbmips/rtc.c

499

reg = A_SMB_REGISTER(chan, R_SMB_START);

sys/arch/evbmips/sbmips/rtc.c

501

WRITE_REG(reg, V_SMB_TT(K_SMB_TT_WR2BYTE) | V_SMB_ADDR(slaveaddr));

sys/arch/evbmips/sbmips/rtc.c

503

WRITE_REG(reg, V_SMB_TT(K_SMB_TT_WR1BYTE) | V_SMB_ADDR(slaveaddr));

sys/arch/evbmips/sbmips/rtc.c

517

WRITE_REG(reg, V_SMB_TT(K_SMB_TT_RD1BYTE) | V_SMB_ADDR(slaveaddr));

sys/arch/evbmips/sbmips/rtc.c

523

reg = A_SMB_REGISTER(chan, R_SMB_DATA);

sys/arch/evbmips/sbmips/rtc.c

524

err = READ_REG(reg);

sys/arch/evbmips/sbmips/rtc.c

532

uint32_t reg;

sys/arch/evbmips/sbmips/rtc.c

549

reg = A_SMB_REGISTER(chan, R_SMB_CMD);

sys/arch/evbmips/sbmips/rtc.c

551

WRITE_REG(reg, (devaddr >> 8) & 0x7);

sys/arch/evbmips/sbmips/rtc.c

553

WRITE_REG(reg, devaddr & 0xff);

sys/arch/evbmips/sbmips/rtc.c

559

reg = A_SMB_REGISTER(chan, R_SMB_DATA);

sys/arch/evbmips/sbmips/rtc.c

561

WRITE_REG(reg, (devaddr & 0xff) | ((b & 0xff) << 8));

sys/arch/evbmips/sbmips/rtc.c

563

WRITE_REG(reg, b & 0xff);

sys/arch/evbmips/sbmips/rtc.c

571

reg = A_SMB_REGISTER(chan, R_SMB_START);

sys/arch/evbmips/sbmips/rtc.c

573

WRITE_REG(reg, V_SMB_TT(K_SMB_TT_WR3BYTE) | V_SMB_ADDR(slaveaddr));

sys/arch/evbmips/sbmips/rtc.c

575

WRITE_REG(reg, V_SMB_TT(K_SMB_TT_WR2BYTE) | V_SMB_ADDR(slaveaddr));

sys/arch/evbmips/sbmips/rtc.c

594

WRITE_REG(reg, V_SMB_TT(K_SMB_TT_RD1BYTE) | V_SMB_ADDR(slaveaddr));

sys/arch/evbppc/explora/dev/le_elb.c

190

le_rdcsr(struct lance_softc *sc, uint16_t reg)

sys/arch/evbppc/explora/dev/le_elb.c

197

bus_space_write_4(iot, ioh, LE_RAP, reg);

sys/arch/evbppc/explora/dev/le_elb.c

207

le_wrcsr(struct lance_softc *sc, uint16_t reg, uint16_t val)

sys/arch/evbppc/explora/dev/le_elb.c

213

bus_space_write_4(iot, ioh, LE_RAP, reg);

sys/arch/evbppc/nintendo/dev/ahb.c

48

#define WR4(reg, val) out32(reg, val)

sys/arch/evbppc/nintendo/dev/ahb.c

49

#define RD4(reg) in32(reg)

sys/arch/evbppc/nintendo/dev/ahcisata_ahb.c

52

#define RD4(sc, reg) \

sys/arch/evbppc/nintendo/dev/ahcisata_ahb.c

53

bus_space_read_4((sc)->sc_ahcit, (sc)->sc_ahcih, (reg))

sys/arch/evbppc/nintendo/dev/ahcisata_ahb.c

54

#define WR4(sc, reg, val) \

sys/arch/evbppc/nintendo/dev/ahcisata_ahb.c

55

bus_space_write_4((sc)->sc_ahcit, (sc)->sc_ahcih, (reg), (val))

sys/arch/evbppc/nintendo/dev/avenc.c

106

iic_exec(tag, I2C_OP_WRITE_WITH_STOP, addr, &reg, 1,

sys/arch/evbppc/nintendo/dev/avenc.c

111

avenc_write_4(i2c_tag_t tag, i2c_addr_t addr, uint8_t reg, uint32_t val)

sys/arch/evbppc/nintendo/dev/avenc.c

120

iic_exec(tag, I2C_OP_WRITE_WITH_STOP, addr, &reg, 1,

sys/arch/evbppc/nintendo/dev/avenc.c

125

avenc_write_buf(i2c_tag_t tag, i2c_addr_t addr, uint8_t reg, uint8_t *buf,

sys/arch/evbppc/nintendo/dev/avenc.c

128

iic_exec(tag, I2C_OP_WRITE_WITH_STOP, addr, &reg, 1,

sys/arch/evbppc/nintendo/dev/avenc.c

171

unsigned int reg;

sys/arch/evbppc/nintendo/dev/avenc.c

175

for (reg = 0; reg < sizeof(regdump); reg++) {

sys/arch/evbppc/nintendo/dev/avenc.c

176

regdump[reg] = RD1(tag, addr, reg);

sys/arch/evbppc/nintendo/dev/avenc.c

68

avenc_read_1(i2c_tag_t tag, i2c_addr_t addr, uint8_t reg)

sys/arch/evbppc/nintendo/dev/avenc.c

72

if (iic_smbus_read_byte(tag, addr, reg, &val, 0) != 0) {

sys/arch/evbppc/nintendo/dev/avenc.c

80

avenc_read_2(i2c_tag_t tag, i2c_addr_t addr, uint8_t reg)

sys/arch/evbppc/nintendo/dev/avenc.c

84

if (iic_exec(tag, I2C_OP_READ_WITH_STOP, addr, &reg, 1,

sys/arch/evbppc/nintendo/dev/avenc.c

93

avenc_write_1(i2c_tag_t tag, i2c_addr_t addr, uint8_t reg, uint8_t val)

sys/arch/evbppc/nintendo/dev/avenc.c

95

iic_smbus_write_byte(tag, addr, reg, val, 0);

sys/arch/evbppc/nintendo/dev/avenc.c

99

avenc_write_2(i2c_tag_t tag, i2c_addr_t addr, uint8_t reg, uint16_t val)

sys/arch/evbppc/nintendo/dev/bwai.c

84

#define RD4(sc, reg) \

sys/arch/evbppc/nintendo/dev/bwai.c

85

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/evbppc/nintendo/dev/bwai.c

86

#define WR4(sc, reg, val) \

sys/arch/evbppc/nintendo/dev/bwai.c

87

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/evbppc/nintendo/dev/bwdsp.c

91

#define WR2(sc, reg, val) \

sys/arch/evbppc/nintendo/dev/bwdsp.c

92

bus_space_write_2((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/evbppc/nintendo/dev/di.c

140

#define WR4(sc, reg, val) \

sys/arch/evbppc/nintendo/dev/di.c

141

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/evbppc/nintendo/dev/di.c

142

#define RD4(sc, reg) \

sys/arch/evbppc/nintendo/dev/di.c

143

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/evbppc/nintendo/dev/exi.c

77

#define RD4(sc, reg) \

sys/arch/evbppc/nintendo/dev/exi.c

78

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/evbppc/nintendo/dev/exi.c

79

#define WR4(sc, reg, val) \

sys/arch/evbppc/nintendo/dev/exi.c

80

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/evbppc/nintendo/dev/gecko.c

66

#define RD4(reg) in32(EXI_BASE + (reg))

sys/arch/evbppc/nintendo/dev/gecko.c

67

#define WR4(reg, val) out32(EXI_BASE + (reg), val)

sys/arch/evbppc/nintendo/dev/hwaes.c

102

#define WR4(sc, reg, val) \

sys/arch/evbppc/nintendo/dev/hwaes.c

103

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/evbppc/nintendo/dev/hwaes.c

104

#define RD4(sc, reg) \

sys/arch/evbppc/nintendo/dev/hwaes.c

105

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/evbppc/nintendo/dev/hwgpio.c

131

#define RD4(sc, reg) \

sys/arch/evbppc/nintendo/dev/hwgpio.c

132

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/evbppc/nintendo/dev/hwgpio.c

133

#define WR4(sc, reg, val) \

sys/arch/evbppc/nintendo/dev/hwgpio.c

134

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/evbppc/nintendo/dev/si.c

126

#define RD4(sc, reg) \

sys/arch/evbppc/nintendo/dev/si.c

127

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/evbppc/nintendo/dev/si.c

128

#define WR4(sc, reg, val) \

sys/arch/evbppc/nintendo/dev/si.c

129

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/evbppc/nintendo/dev/wiifb.c

156

#define RD2(sc, reg) \

sys/arch/evbppc/nintendo/dev/wiifb.c

157

bus_space_read_2((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/evbppc/nintendo/dev/wiifb.c

158

#define RD4(sc, reg) \

sys/arch/evbppc/nintendo/dev/wiifb.c

159

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/evbppc/nintendo/dev/wiifb.c

160

#define WR2(sc, reg, val) \

sys/arch/evbppc/nintendo/dev/wiifb.c

161

bus_space_write_2((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/evbppc/nintendo/dev/wiifb.c

162

#define WR4(sc, reg, val) \

sys/arch/evbppc/nintendo/dev/wiifb.c

163

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/evbppc/nintendo/dev/wiiufb.c

535

wiiufb_gpu_write(uint16_t reg, uint32_t data)

sys/arch/evbppc/nintendo/dev/wiiufb.c

539

reg, data);

sys/arch/evbppc/nintendo/dev/wiiufb.c

541

out32(LT_GPUINDADDR, LT_GPUINDADDR_REGSPACE_GPU | reg);

sys/arch/evbppc/nintendo/dev/wiiufb.c

548

wiiufb_gpu_read(uint16_t reg)

sys/arch/evbppc/nintendo/dev/wiiufb.c

552

reg);

sys/arch/evbppc/nintendo/dev/wiiufb.c

554

out32(LT_GPUINDADDR, LT_GPUINDADDR_REGSPACE_GPU | reg);

sys/arch/evbppc/nintendo/dev/wiiufb.c

560

wiiufb_gpu_set(uint16_t reg, uint32_t mask)

sys/arch/evbppc/nintendo/dev/wiiufb.c

562

wiiufb_gpu_write(reg, wiiufb_gpu_read(reg) | mask);

sys/arch/evbppc/nintendo/dev/wiiufb.c

566

wiiufb_gpu_clear(uint16_t reg, uint32_t mask)

sys/arch/evbppc/nintendo/dev/wiiufb.c

568

wiiufb_gpu_write(reg, wiiufb_gpu_read(reg) & ~mask);

sys/arch/evbppc/nintendo/pic_pi.c

65

#define WR4(reg, val) out32(reg, val)

sys/arch/evbppc/nintendo/pic_pi.c

66

#define RD4(reg) in32(reg)

sys/arch/evbppc/pmppc/dev/ds17485.c

218

rtc_read(struct mc146818_softc *sc, u_int reg)

sys/arch/evbppc/pmppc/dev/ds17485.c

221

return (bus_space_read_1(sc->sc_bst, sc->sc_bsh, reg));

sys/arch/evbppc/pmppc/dev/ds17485.c

225

rtc_write(struct mc146818_softc *sc, u_int reg, u_int datum)

sys/arch/evbppc/pmppc/dev/ds17485.c

228

bus_space_write_1(sc->sc_bst, sc->sc_bsh, reg, datum);

sys/arch/evbppc/sam460ex/sam460ex_fdt.c

145

uint32_t reg[4];

sys/arch/evbppc/sam460ex/sam460ex_fdt.c

147

if (of_getprop_uint32_array(node, "reg", reg, ac + sc) == 0)

sys/arch/evbppc/sam460ex/sam460ex_fdt.c

148

info->fi_memsize = reg[ac + sc - 1];

sys/arch/evbppc/virtex/dev/if_temac.c

820

temac_mii_readreg(device_t self, int phy, int reg, uint16_t *val)

sys/arch/evbppc/virtex/dev/if_temac.c

824

mtidcr(IDCR_HIF_ARG0, (phy << 5) | reg);

sys/arch/evbppc/virtex/dev/if_temac.c

835

temac_mii_writereg(device_t self, int phy, int reg, uint16_t val)

sys/arch/evbppc/virtex/dev/if_temac.c

839

mtidcr(IDCR_HIF_ARG0, (phy << 5) | reg);

sys/arch/evbppc/virtex/dev/pstwo.c

139

#define PRINTREG(name, reg) \

sys/arch/evbppc/virtex/dev/pstwo.c

141

reg, name, bus_space_read_4(sc->sc_iot, sc->sc_ioh, reg))

sys/arch/evbsh3/ap_ms104_sh4/ap_ms104_sh4.c

105

reg = _reg_read_2(SH4_GPIOIC);

sys/arch/evbsh3/ap_ms104_sh4/ap_ms104_sh4.c

106

reg |= 1 << pin;

sys/arch/evbsh3/ap_ms104_sh4/ap_ms104_sh4.c

107

_reg_write_2(SH4_GPIOIC, reg);

sys/arch/evbsh3/ap_ms104_sh4/ap_ms104_sh4.c

119

uint16_t reg;

sys/arch/evbsh3/ap_ms104_sh4/ap_ms104_sh4.c

127

reg = _reg_read_2(SH4_GPIOIC);

sys/arch/evbsh3/ap_ms104_sh4/ap_ms104_sh4.c

128

reg &= ~(1 << pin);

sys/arch/evbsh3/ap_ms104_sh4/ap_ms104_sh4.c

129

_reg_write_2(SH4_GPIOIC, reg);

sys/arch/evbsh3/ap_ms104_sh4/ap_ms104_sh4.c

144

uint32_t reg;

sys/arch/evbsh3/ap_ms104_sh4/ap_ms104_sh4.c

148

reg = _reg_read_4(SH4_PCTRA);

sys/arch/evbsh3/ap_ms104_sh4/ap_ms104_sh4.c

150

if (reg & (1 << pin)) {

sys/arch/evbsh3/ap_ms104_sh4/ap_ms104_sh4.c

61

uint32_t reg;

sys/arch/evbsh3/ap_ms104_sh4/ap_ms104_sh4.c

76

reg = _reg_read_4(SH4_PCTRA);

sys/arch/evbsh3/ap_ms104_sh4/ap_ms104_sh4.c

77

reg &= ~(3 << (GPIO_PIN_CARD_CD * 2)); /* input */

sys/arch/evbsh3/ap_ms104_sh4/ap_ms104_sh4.c

78

reg &= ~(3 << (GPIO_PIN_CARD_PON * 2));

sys/arch/evbsh3/ap_ms104_sh4/ap_ms104_sh4.c

79

reg |= (1 << (GPIO_PIN_CARD_PON * 2)); /* output */

sys/arch/evbsh3/ap_ms104_sh4/ap_ms104_sh4.c

80

reg &= ~(3 << (GPIO_PIN_CARD_RESET * 2));

sys/arch/evbsh3/ap_ms104_sh4/ap_ms104_sh4.c

81

reg |= (1 << (GPIO_PIN_CARD_RESET * 2)); /* output */

sys/arch/evbsh3/ap_ms104_sh4/ap_ms104_sh4.c

82

reg &= ~(3 << (GPIO_PIN_CARD_ENABLE * 2));

sys/arch/evbsh3/ap_ms104_sh4/ap_ms104_sh4.c

83

reg |= (1 << (GPIO_PIN_CARD_ENABLE * 2)); /* output */

sys/arch/evbsh3/ap_ms104_sh4/ap_ms104_sh4.c

84

_reg_write_4(SH4_PCTRA, reg);

sys/arch/evbsh3/ap_ms104_sh4/ap_ms104_sh4.c

90

uint32_t reg;

sys/arch/evbsh3/ap_ms104_sh4/ap_ms104_sh4_intr.c

157

uint8_t reg;

sys/arch/evbsh3/ap_ms104_sh4/ap_ms104_sh4_intr.c

162

reg = _reg_read_1(EXTINTR_MASK4);

sys/arch/evbsh3/ap_ms104_sh4/ap_ms104_sh4_intr.c

163

reg |= 1 << (2 - irq);

sys/arch/evbsh3/ap_ms104_sh4/ap_ms104_sh4_intr.c

164

_reg_write_1(EXTINTR_MASK4, reg);

sys/arch/evbsh3/ap_ms104_sh4/ap_ms104_sh4_intr.c

168

reg = _reg_read_1(EXTINTR_MASK3);

sys/arch/evbsh3/ap_ms104_sh4/ap_ms104_sh4_intr.c

169

reg |= 1 << (6 - irq);

sys/arch/evbsh3/ap_ms104_sh4/ap_ms104_sh4_intr.c

170

_reg_write_1(EXTINTR_MASK3, reg);

sys/arch/evbsh3/ap_ms104_sh4/ap_ms104_sh4_intr.c

174

reg = _reg_read_1(EXTINTR_MASK2);

sys/arch/evbsh3/ap_ms104_sh4/ap_ms104_sh4_intr.c

175

reg |= 1 << (10 - irq);

sys/arch/evbsh3/ap_ms104_sh4/ap_ms104_sh4_intr.c

176

_reg_write_1(EXTINTR_MASK2, reg);

sys/arch/evbsh3/ap_ms104_sh4/ap_ms104_sh4_intr.c

180

reg = _reg_read_1(EXTINTR_MASK1);

sys/arch/evbsh3/ap_ms104_sh4/ap_ms104_sh4_intr.c

181

reg |= 1 << (14 - irq);

sys/arch/evbsh3/ap_ms104_sh4/ap_ms104_sh4_intr.c

182

_reg_write_1(EXTINTR_MASK1, reg);

sys/arch/evbsh3/ap_ms104_sh4/ap_ms104_sh4_intr.c

229

uint8_t reg;

sys/arch/evbsh3/ap_ms104_sh4/ap_ms104_sh4_intr.c

237

reg = _reg_read_1(EXTINTR_MASK4);

sys/arch/evbsh3/ap_ms104_sh4/ap_ms104_sh4_intr.c

238

reg &= ~(1 << (2 - irq));

sys/arch/evbsh3/ap_ms104_sh4/ap_ms104_sh4_intr.c

239

_reg_write_1(EXTINTR_MASK4, reg);

sys/arch/evbsh3/ap_ms104_sh4/ap_ms104_sh4_intr.c

243

reg = _reg_read_1(EXTINTR_MASK3);

sys/arch/evbsh3/ap_ms104_sh4/ap_ms104_sh4_intr.c

244

reg &= ~(1 << (6 - irq));

sys/arch/evbsh3/ap_ms104_sh4/ap_ms104_sh4_intr.c

245

_reg_write_1(EXTINTR_MASK3, reg);

sys/arch/evbsh3/ap_ms104_sh4/ap_ms104_sh4_intr.c

249

reg = _reg_read_1(EXTINTR_MASK2);

sys/arch/evbsh3/ap_ms104_sh4/ap_ms104_sh4_intr.c

250

reg &= ~(1 << (10 - irq));

sys/arch/evbsh3/ap_ms104_sh4/ap_ms104_sh4_intr.c

251

_reg_write_1(EXTINTR_MASK2, reg);

sys/arch/evbsh3/ap_ms104_sh4/ap_ms104_sh4_intr.c

255

reg = _reg_read_1(EXTINTR_MASK1);

sys/arch/evbsh3/ap_ms104_sh4/ap_ms104_sh4_intr.c

256

reg &= ~(1 << (14 - irq));

sys/arch/evbsh3/ap_ms104_sh4/ap_ms104_sh4_intr.c

257

_reg_write_1(EXTINTR_MASK1, reg);

sys/arch/evbsh3/ap_ms104_sh4/rs5c316_mainbus.c

100

reg &= ~(3 << (GPIO_PIN_RTC_SIO * 2));

sys/arch/evbsh3/ap_ms104_sh4/rs5c316_mainbus.c

101

reg |= (1 << (GPIO_PIN_RTC_SIO * 2)); /* output */

sys/arch/evbsh3/ap_ms104_sh4/rs5c316_mainbus.c

102

_reg_write_4(SH4_PCTRA, reg);

sys/arch/evbsh3/ap_ms104_sh4/rs5c316_mainbus.c

119

reg = _reg_read_2(SH4_PDTRA);

sys/arch/evbsh3/ap_ms104_sh4/rs5c316_mainbus.c

121

reg |= (1 << GPIO_PIN_RTC_CE);

sys/arch/evbsh3/ap_ms104_sh4/rs5c316_mainbus.c

123

reg &= ~(1 << GPIO_PIN_RTC_CE);

sys/arch/evbsh3/ap_ms104_sh4/rs5c316_mainbus.c

125

_reg_write_2(SH4_PDTRA, reg);

sys/arch/evbsh3/ap_ms104_sh4/rs5c316_mainbus.c

132

uint16_t reg;

sys/arch/evbsh3/ap_ms104_sh4/rs5c316_mainbus.c

134

reg = _reg_read_2(SH4_PDTRA);

sys/arch/evbsh3/ap_ms104_sh4/rs5c316_mainbus.c

136

reg |= (1 << GPIO_PIN_RTC_SCLK);

sys/arch/evbsh3/ap_ms104_sh4/rs5c316_mainbus.c

138

reg &= ~(1 << GPIO_PIN_RTC_SCLK);

sys/arch/evbsh3/ap_ms104_sh4/rs5c316_mainbus.c

140

_reg_write_2(SH4_PDTRA, reg);

sys/arch/evbsh3/ap_ms104_sh4/rs5c316_mainbus.c

146

uint32_t reg;

sys/arch/evbsh3/ap_ms104_sh4/rs5c316_mainbus.c

148

reg = _reg_read_4(SH4_PCTRA);

sys/arch/evbsh3/ap_ms104_sh4/rs5c316_mainbus.c

149

reg &= ~(3 << (GPIO_PIN_RTC_SIO * 2)); /* input */

sys/arch/evbsh3/ap_ms104_sh4/rs5c316_mainbus.c

151

reg |= (1 << (GPIO_PIN_RTC_SIO * 2)); /* output */

sys/arch/evbsh3/ap_ms104_sh4/rs5c316_mainbus.c

153

_reg_write_4(SH4_PCTRA, reg);

sys/arch/evbsh3/ap_ms104_sh4/rs5c316_mainbus.c

175

uint16_t reg;

sys/arch/evbsh3/ap_ms104_sh4/rs5c316_mainbus.c

177

reg = _reg_read_2(SH4_PDTRA);

sys/arch/evbsh3/ap_ms104_sh4/rs5c316_mainbus.c

179

reg |= (1 << GPIO_PIN_RTC_SIO);

sys/arch/evbsh3/ap_ms104_sh4/rs5c316_mainbus.c

181

reg &= ~(1 << GPIO_PIN_RTC_SIO);

sys/arch/evbsh3/ap_ms104_sh4/rs5c316_mainbus.c

182

_reg_write_2(SH4_PDTRA, reg);

sys/arch/evbsh3/ap_ms104_sh4/rs5c316_mainbus.c

88

uint32_t reg;

sys/arch/evbsh3/ap_ms104_sh4/rs5c316_mainbus.c

95

reg = _reg_read_4(SH4_PCTRA);

sys/arch/evbsh3/ap_ms104_sh4/rs5c316_mainbus.c

96

reg &= ~(3 << (GPIO_PIN_RTC_CE * 2));

sys/arch/evbsh3/ap_ms104_sh4/rs5c316_mainbus.c

97

reg |= (1 << (GPIO_PIN_RTC_CE * 2)); /* output */

sys/arch/evbsh3/ap_ms104_sh4/rs5c316_mainbus.c

98

reg &= ~(3 << (GPIO_PIN_RTC_SCLK * 2));

sys/arch/evbsh3/ap_ms104_sh4/rs5c316_mainbus.c

99

reg |= (1 << (GPIO_PIN_RTC_SCLK * 2)); /* output */

sys/arch/evbsh3/ap_ms104_sh4/shpcmcia.c

231

uint32_t reg;

sys/arch/evbsh3/ap_ms104_sh4/shpcmcia.c

242

reg = _reg_read_4(SH4_WCR1);

sys/arch/evbsh3/ap_ms104_sh4/shpcmcia.c

243

reg |= 0x00700000;

sys/arch/evbsh3/ap_ms104_sh4/shpcmcia.c

244

_reg_write_4(SH4_WCR1, reg);

sys/arch/evbsh3/ap_ms104_sh4/shpcmcia.c

245

reg = _reg_read_4(SH4_WCR2);

sys/arch/evbsh3/ap_ms104_sh4/shpcmcia.c

246

reg |= 0xfff00000;

sys/arch/evbsh3/ap_ms104_sh4/shpcmcia.c

247

_reg_write_4(SH4_WCR2, reg);

sys/arch/evbsh3/ap_ms104_sh4/shpcmcia.c

248

reg = _reg_read_4(SH4_WCR3);

sys/arch/evbsh3/ap_ms104_sh4/shpcmcia.c

249

reg |= 0x07700000;

sys/arch/evbsh3/ap_ms104_sh4/shpcmcia.c

250

_reg_write_4(SH4_WCR3, reg);

sys/arch/evbsh3/ap_ms104_sh4/shpcmcia.c

251

reg = _reg_read_4(SH4_PCR);

sys/arch/evbsh3/ap_ms104_sh4/shpcmcia.c

252

reg |= 0xffffffff;

sys/arch/evbsh3/ap_ms104_sh4/shpcmcia.c

253

_reg_write_4(SH4_PCR, reg);

sys/arch/evbsh3/ap_ms104_sh4/shpcmcia.c

336

uint16_t reg;

sys/arch/evbsh3/ap_ms104_sh4/shpcmcia.c

347

reg = _reg_read_2(SH4_PDTRA);

sys/arch/evbsh3/ap_ms104_sh4/shpcmcia.c

348

if (!(reg & (1 << GPIO_PIN_CARD_CD))) {

sys/arch/evbsh3/ap_ms104_sh4/shpcmcia.c

525

uint16_t reg;

sys/arch/evbsh3/ap_ms104_sh4/shpcmcia.c

529

reg = _reg_read_2(SH4_PDTRA);

sys/arch/evbsh3/ap_ms104_sh4/shpcmcia.c

530

if (reg & (1 << GPIO_PIN_CARD_CD)) {

sys/arch/evbsh3/ap_ms104_sh4/shpcmcia.c

556

uint16_t reg;

sys/arch/evbsh3/ap_ms104_sh4/shpcmcia.c

560

reg = _reg_read_2(SH4_PDTRA);

sys/arch/evbsh3/ap_ms104_sh4/shpcmcia.c

561

if (reg & (1 << GPIO_PIN_CARD_CD)) {

sys/arch/evbsh3/ap_ms104_sh4/shpcmcia.c

808

uint16_t reg;

sys/arch/evbsh3/ap_ms104_sh4/shpcmcia.c

813

reg = _reg_read_2(SH4_PDTRA);

sys/arch/evbsh3/ap_ms104_sh4/shpcmcia.c

814

reg &= ~(1 << GPIO_PIN_CARD_PON);

sys/arch/evbsh3/ap_ms104_sh4/shpcmcia.c

815

_reg_write_2(SH4_PDTRA, reg);

sys/arch/evbsh3/ap_ms104_sh4/shpcmcia.c

822

reg = _reg_read_2(SH4_PDTRA);

sys/arch/evbsh3/ap_ms104_sh4/shpcmcia.c

823

reg &= ~(1 << GPIO_PIN_CARD_ENABLE);

sys/arch/evbsh3/ap_ms104_sh4/shpcmcia.c

824

_reg_write_2(SH4_PDTRA, reg);

sys/arch/evbsh3/ap_ms104_sh4/shpcmcia.c

827

reg = _reg_read_2(SH4_PDTRA);

sys/arch/evbsh3/ap_ms104_sh4/shpcmcia.c

828

reg &= ~(1 << GPIO_PIN_CARD_RESET);

sys/arch/evbsh3/ap_ms104_sh4/shpcmcia.c

829

_reg_write_2(SH4_PDTRA, reg);

sys/arch/evbsh3/ap_ms104_sh4/shpcmcia.c

837

uint16_t reg;

sys/arch/evbsh3/ap_ms104_sh4/shpcmcia.c

842

reg = _reg_read_2(SH4_PDTRA);

sys/arch/evbsh3/ap_ms104_sh4/shpcmcia.c

843

reg |= (1 << GPIO_PIN_CARD_RESET);

sys/arch/evbsh3/ap_ms104_sh4/shpcmcia.c

844

_reg_write_2(SH4_PDTRA, reg);

sys/arch/evbsh3/ap_ms104_sh4/shpcmcia.c

847

reg = _reg_read_2(SH4_PDTRA);

sys/arch/evbsh3/ap_ms104_sh4/shpcmcia.c

848

reg |= (1 << GPIO_PIN_CARD_PON);

sys/arch/evbsh3/ap_ms104_sh4/shpcmcia.c

849

_reg_write_2(SH4_PDTRA, reg);

sys/arch/evbsh3/ap_ms104_sh4/shpcmcia.c

852

reg = _reg_read_2(SH4_PDTRA);

sys/arch/evbsh3/ap_ms104_sh4/shpcmcia.c

853

reg |= (1 << GPIO_PIN_CARD_ENABLE);

sys/arch/evbsh3/ap_ms104_sh4/shpcmcia.c

854

_reg_write_2(SH4_PDTRA, reg);

sys/arch/evbsh3/t_sh7706lan/scimci.c

103

#define CSR_SET_1(reg,set,mask) \

sys/arch/evbsh3/t_sh7706lan/scimci.c

106

_r = _reg_read_1((reg)); \

sys/arch/evbsh3/t_sh7706lan/scimci.c

109

_reg_write_1((reg), _r); \

sys/arch/evbsh3/t_sh7706lan/scimci.c

112

#define CSR_SET_2(reg,set,mask) \

sys/arch/evbsh3/t_sh7706lan/scimci.c

115

_r = _reg_read_2((reg)); \

sys/arch/evbsh3/t_sh7706lan/scimci.c

118

_reg_write_2((reg), _r); \

sys/arch/evbsh3/t_sh7706lan/scimci.c

121

#define CSR_CLR_1(reg,clr) \

sys/arch/evbsh3/t_sh7706lan/scimci.c

124

_r = _reg_read_1((reg)); \

sys/arch/evbsh3/t_sh7706lan/scimci.c

126

_reg_write_1((reg), _r); \

sys/arch/evbsh3/t_sh7706lan/scimci.c

129

#define CSR_CLR_2(reg,clr) \

sys/arch/evbsh3/t_sh7706lan/scimci.c

132

_r = _reg_read_2((reg)); \

sys/arch/evbsh3/t_sh7706lan/scimci.c

134

_reg_write_2((reg), _r); \

sys/arch/evbsh3/t_sh7706lan/scimci.c

345

uint8_t reg;

sys/arch/evbsh3/t_sh7706lan/scimci.c

350

reg = _reg_read_1(SH7709_PGDR);

sys/arch/evbsh3/t_sh7706lan/scimci.c

353

return !(reg & PGDR_EJECT);

sys/arch/evbsh3/t_sh7706lan/ssumci.c

105

#define CSR_SET_1(reg,set,mask) \

sys/arch/evbsh3/t_sh7706lan/ssumci.c

108

_r = _reg_read_1((reg)); \

sys/arch/evbsh3/t_sh7706lan/ssumci.c

111

_reg_write_1((reg), _r); \

sys/arch/evbsh3/t_sh7706lan/ssumci.c

114

#define CSR_SET_2(reg,set,mask) \

sys/arch/evbsh3/t_sh7706lan/ssumci.c

117

_r = _reg_read_2((reg)); \

sys/arch/evbsh3/t_sh7706lan/ssumci.c

120

_reg_write_2((reg), _r); \

sys/arch/evbsh3/t_sh7706lan/ssumci.c

123

#define CSR_CLR_1(reg,clr) \

sys/arch/evbsh3/t_sh7706lan/ssumci.c

126

_r = _reg_read_1((reg)); \

sys/arch/evbsh3/t_sh7706lan/ssumci.c

128

_reg_write_1((reg), _r); \

sys/arch/evbsh3/t_sh7706lan/ssumci.c

131

#define CSR_CLR_2(reg,clr) \

sys/arch/evbsh3/t_sh7706lan/ssumci.c

134

_r = _reg_read_2((reg)); \

sys/arch/evbsh3/t_sh7706lan/ssumci.c

136

_reg_write_2((reg), _r); \

sys/arch/evbsh3/t_sh7706lan/ssumci.c

282

uint8_t reg;

sys/arch/evbsh3/t_sh7706lan/ssumci.c

287

reg = _reg_read_1(SH7709_SCPDR);

sys/arch/evbsh3/t_sh7706lan/ssumci.c

290

return !(reg & SCPDR_EJECT);

sys/arch/evbsh3/t_sh7706lan/t_sh7706lan.c

44

uint16_t reg;

sys/arch/evbsh3/t_sh7706lan/t_sh7706lan.c

50

reg = _reg_read_2(SH7709_SCPCR);

sys/arch/evbsh3/t_sh7706lan/t_sh7706lan.c

51

reg &= 0x3ff;

sys/arch/evbsh3/t_sh7706lan/t_sh7706lan.c

52

_reg_write_2(SH7709_SCPCR, reg);

sys/arch/evbsh3/t_sh7706lan/t_sh7706lan.c

58

reg = _reg_read_2(SH3_BCR2);

sys/arch/evbsh3/t_sh7706lan/t_sh7706lan.c

59

reg &= ~(BCR2_AREA_WIDTH_MASK << BCR2_AREA4_SHIFT);

sys/arch/evbsh3/t_sh7706lan/t_sh7706lan.c

60

reg |= (BCR2_AREA_WIDTH_8 << BCR2_AREA4_SHIFT);

sys/arch/evbsh3/t_sh7706lan/t_sh7706lan.c

61

_reg_write_2(SH3_BCR2, reg);

sys/arch/ews4800mips/dev/zs.c

185

zs_read_reg(struct zs_chanstate *cs, uint8_t reg)

sys/arch/ews4800mips/dev/zs.c

189

*cs->cs_reg_csr = reg;

sys/arch/ews4800mips/dev/zs.c

197

zs_write_reg(struct zs_chanstate *cs, uint8_t reg, uint8_t val)

sys/arch/ews4800mips/dev/zs.c

200

*cs->cs_reg_csr = reg;

sys/arch/ews4800mips/include/z8530var.h

101

void zs_write_reg(struct zs_chanstate *cs, uint8_t reg, uint8_t val);

sys/arch/ews4800mips/include/z8530var.h

97

uint8_t zs_read_reg(struct zs_chanstate *cs, uint8_t reg);

sys/arch/ews4800mips/sbd/fb_sbdio.c

241

fb_sbdio_cnattach(uint32_t mem, uint32_t reg, int flags)

sys/arch/ews4800mips/sbd/fb_sbdio.c

251

ga->reg_paddr = reg;

sys/arch/ews4800mips/sbd/fb_sbdio.c

253

fb_pmap_enter((paddr_t)mem, (paddr_t)reg, &memva, &regva);

sys/arch/ews4800mips/sbd/kbms_sbdio.c

143

struct kbms_reg *reg = &sc->sc_reg;

sys/arch/ews4800mips/sbd/kbms_sbdio.c

150

reg->kbd_csr = base + 0x00; /* port B */

sys/arch/ews4800mips/sbd/kbms_sbdio.c

151

reg->kbd_data = base + 0x04;

sys/arch/ews4800mips/sbd/kbms_sbdio.c

152

reg->mouse_csr = base + 0x08; /* port A */

sys/arch/ews4800mips/sbd/kbms_sbdio.c

153

reg->mouse_data = base + 0x0c;

sys/arch/ews4800mips/sbd/kbms_sbdio.c

155

if (reg->kbd_csr == kbms_consreg.kbd_csr &&

sys/arch/ews4800mips/sbd/kbms_sbdio.c

156

reg->kbd_data == kbms_consreg.kbd_data)

sys/arch/ews4800mips/sbd/kbms_sbdio.c

191

struct kbms_reg *reg = &sc->sc_reg;

sys/arch/ews4800mips/sbd/kbms_sbdio.c

194

if (*reg->kbd_csr & ZSRR0_RX_READY) {

sys/arch/ews4800mips/sbd/kbms_sbdio.c

195

v = *reg->kbd_data;

sys/arch/ews4800mips/sbd/kbms_sbdio.c

201

while (*reg->mouse_csr & ZSRR0_RX_READY) {

sys/arch/ews4800mips/sbd/kbms_sbdio.c

203

*reg->mouse_csr = 1;

sys/arch/ews4800mips/sbd/kbms_sbdio.c

204

if (((v = *reg->mouse_csr) &

sys/arch/ews4800mips/sbd/kbms_sbdio.c

210

v = *reg->mouse_data;

sys/arch/ews4800mips/sbd/kbms_sbdio.c

241

*reg->mouse_csr = ZSWR1_REQ_RX | ZSWR1_RIE | ZSWR1_RIE_FIRST;

sys/arch/ews4800mips/sbd/kbms_sbdio.c

242

(void)*reg->mouse_csr;

sys/arch/ews4800mips/sbd/kbms_sbdio.c

259

struct kbms_reg *reg = &sc->sc_reg;

sys/arch/ews4800mips/sbd/kbms_sbdio.c

260

volatile uint8_t *csr = reg->kbd_csr;

sys/arch/ews4800mips/sbd/kbms_sbdio.c

305

struct kbms_reg *reg = &sc->sc_reg;

sys/arch/ews4800mips/sbd/kbms_sbdio.c

306

volatile uint8_t *csr = reg->kbd_csr;

sys/arch/ews4800mips/sbd/kbms_sbdio.c

307

volatile uint8_t *data = reg->kbd_data;

sys/arch/ews4800mips/sbd/kbms_sbdio.c

325

(void)*reg->kbd_data;

sys/arch/ews4800mips/sbd/kbms_sbdio.c

336

struct kbms_reg *reg = &sc->sc_reg;

sys/arch/ews4800mips/sbd/kbms_sbdio.c

337

volatile uint8_t *csr = reg->mouse_csr;

sys/arch/ews4800mips/sbd/kbms_sbdio.c

338

volatile uint8_t *data = reg->mouse_data;

sys/arch/ews4800mips/sbd/kbms_sbdio.c

387

struct kbms_reg *reg = &sc->sc_reg;

sys/arch/ews4800mips/sbd/kbms_sbdio.c

391

*reg->kbd_data = 0x92;

sys/arch/ews4800mips/sbd/kbms_sbdio.c

393

*reg->kbd_data = 0x90;

sys/arch/ews4800mips/sbd/kbms_sbdio.c

422

struct kbms_reg *reg;

sys/arch/ews4800mips/sbd/kbms_sbdio.c

430

reg = &sc->sc_reg;

sys/arch/ews4800mips/sbd/kbms_sbdio.c

431

reg->kbd_csr = (void *)csr;

sys/arch/ews4800mips/sbd/kbms_sbdio.c

432

reg->kbd_data = (void *)data;

sys/arch/ews4800mips/sbd/kbms_sbdio.c

444

struct kbms_reg *reg = (void *)arg;

sys/arch/ews4800mips/sbd/kbms_sbdio.c

447

while ((*reg->kbd_csr & ZSRR0_RX_READY) == 0)

sys/arch/ews4800mips/sbd/kbms_sbdio.c

449

v = *reg->kbd_data;

sys/arch/ews4800mips/stand/common/cons_zs.c

63

#define ZS_WRITE_REG(zs, reg, val) \

sys/arch/ews4800mips/stand/common/cons_zs.c

65

*zs.csr = reg; \

sys/arch/hp300/dev/dnkbd.c

860

uint8_t reg;

sys/arch/hp300/dev/dnkbd.c

865

reg = bus_space_read_1(bst, bsh, com_lctl);

sys/arch/hp300/dev/dnkbd.c

867

reg |= LCR_SBREAK;

sys/arch/hp300/dev/dnkbd.c

869

reg &= ~LCR_SBREAK;

sys/arch/hp300/dev/dnkbd.c

870

bus_space_write_1(bst, bsh, com_lctl, reg);

sys/arch/hp300/dev/frodoreg.h

79

#define FRODO_READ(sc, reg) ((sc)->sc_regs[(reg)])

sys/arch/hp300/dev/frodoreg.h

80

#define FRODO_WRITE(sc, reg, val) (sc)->sc_regs[(reg)] = (val)

sys/arch/hp300/dev/mcclock_frodo.c

115

mcclock_frodo_write(struct mc146818_softc *sc, u_int reg, u_int datum)

sys/arch/hp300/dev/mcclock_frodo.c

123

bus_space_write_1(iot, ioh, 0, reg);

sys/arch/hp300/dev/mcclock_frodo.c

128

mcclock_frodo_read(struct mc146818_softc *sc, u_int reg)

sys/arch/hp300/dev/mcclock_frodo.c

137

bus_space_write_1(iot, ioh, 0, reg);

sys/arch/hp300/dev/rtc.c

194

rtc_readreg(struct rtc_softc *sc, int reg)

sys/arch/hp300/dev/rtc.c

201

data = reg;

sys/arch/hp300/dev/rtc.c

210

rtc_writereg(struct rtc_softc *sc, int reg, uint8_t data)

sys/arch/hp300/dev/rtc.c

217

tmp = (data << 4) | reg;

sys/arch/hp300/stand/common/clock.c

206

read_bbc_reg(int reg)

sys/arch/hp300/stand/common/clock.c

208

uint8_t data = reg;

sys/arch/hp300/stand/common/clock.c

229

mc_read(u_int reg)

sys/arch/hp300/stand/common/clock.c

233

mcclock[0] = (uint8_t)reg;

sys/arch/hpc/hpc/debug_subr.c

91

dbg_bitmask_print(uint32_t reg, uint32_t mask, const char *name)

sys/arch/hpc/hpc/debug_subr.c

94

printf("%s[%c] ", name, onoff[reg & mask ? 1 : 0]);

sys/arch/hpc/stand/hpcboot/arm/arm_mmu.cpp

50

uint32_t reg;

sys/arch/hpc/stand/hpcboot/arm/arm_mmu.cpp

62

reg = GetCop15Reg2();

sys/arch/hpc/stand/hpcboot/arm/arm_mmu.cpp

63

_table_base = reg & ARM_MMU_TABLEBASE_MASK;

sys/arch/hpc/stand/hpcboot/arm/arm_mmu.cpp

65

_table_base, readPhysical4(_table_base), reg));

sys/arch/hpc/stand/hpcboot/arm/arm_pxa2x0.cpp

382

uint32_t reg;

sys/arch/hpc/stand/hpcboot/arm/arm_pxa2x0.cpp

397

reg = VOLATILE_REF(gpio + GPIO_OFFSET(i, 0x00));

sys/arch/hpc/stand/hpcboot/arm/arm_pxa2x0.cpp

398

DPRINTF((TEXT("GPLR%d: 0x%08x\n"), i, reg));

sys/arch/hpc/stand/hpcboot/arm/arm_pxa2x0.cpp

401

reg = VOLATILE_REF(gpio + GPIO_OFFSET(i, 0x0c));

sys/arch/hpc/stand/hpcboot/arm/arm_pxa2x0.cpp

402

DPRINTF((TEXT("GPDR%d: 0x%08x\n"), i, reg));

sys/arch/hpc/stand/hpcboot/arm/arm_pxa2x0.cpp

406

reg = VOLATILE_REF(gpio + GPIO_OFFSET(i, 0x18));

sys/arch/hpc/stand/hpcboot/arm/arm_pxa2x0.cpp

407

DPRINTF((TEXT("GPSR%d: 0x%08x\n"), reg));

sys/arch/hpc/stand/hpcboot/arm/arm_pxa2x0.cpp

410

reg = VOLATILE_REF(gpio + GPIO_OFFSET(i, 0x24));

sys/arch/hpc/stand/hpcboot/arm/arm_pxa2x0.cpp

411

DPRINTF((TEXT("GPCR%d: 0x%08x\n"), reg));

sys/arch/hpc/stand/hpcboot/arm/arm_pxa2x0.cpp

415

reg = VOLATILE_REF(gpio + GPIO_OFFSET(i, 0x30));

sys/arch/hpc/stand/hpcboot/arm/arm_pxa2x0.cpp

416

DPRINTF((TEXT("GRER%d: 0x%08x\n"), i, reg));

sys/arch/hpc/stand/hpcboot/arm/arm_pxa2x0.cpp

419

reg = VOLATILE_REF(gpio + GPIO_OFFSET(i, 0x3c));

sys/arch/hpc/stand/hpcboot/arm/arm_pxa2x0.cpp

420

DPRINTF((TEXT("GFER%d: 0x%08x\n"), i, reg));

sys/arch/hpc/stand/hpcboot/arm/arm_pxa2x0.cpp

423

reg = VOLATILE_REF(gpio + GPIO_OFFSET(i, 0x48));

sys/arch/hpc/stand/hpcboot/arm/arm_pxa2x0.cpp

424

DPRINTF((TEXT("GEDR%d: 0x%08x\n"), i, reg));

sys/arch/hpc/stand/hpcboot/arm/arm_pxa2x0.cpp

427

reg = VOLATILE_REF(gpio + 0x54 + (i * 8));

sys/arch/hpc/stand/hpcboot/arm/arm_pxa2x0.cpp

428

DPRINTF((TEXT("GAFR%d_L: 0x%08x\n"), i, reg));

sys/arch/hpc/stand/hpcboot/arm/arm_pxa2x0.cpp

429

reg = VOLATILE_REF(gpio + 0x58 + (i * 8));

sys/arch/hpc/stand/hpcboot/arm/arm_pxa2x0.cpp

430

DPRINTF((TEXT("GAFR%d_U: 0x%08x\n"), i, reg));

sys/arch/hpc/stand/hpcboot/arm/arm_pxa2x0.cpp

495

reg = VOLATILE_REF(lcdc + 0x00);

sys/arch/hpc/stand/hpcboot/arm/arm_pxa2x0.cpp

496

DPRINTF((TEXT("LCCR0: 0x%08x\n"), reg));

sys/arch/hpc/stand/hpcboot/arm/arm_pxa2x0.cpp

499

if (reg & (1U << 26)) {

sys/arch/hpc/stand/hpcboot/arm/arm_pxa2x0.cpp

503

if (reg & (1U << 25)) {

sys/arch/hpc/stand/hpcboot/arm/arm_pxa2x0.cpp

507

if (reg & (1U << 22)) {

sys/arch/hpc/stand/hpcboot/arm/arm_pxa2x0.cpp

511

if (reg & (1U << 9)) {

sys/arch/hpc/stand/hpcboot/arm/arm_pxa2x0.cpp

515

if (reg & (1U << 7)) {

sys/arch/hpc/stand/hpcboot/arm/arm_pxa2x0.cpp

519

if (reg & (1U << 2)) {

sys/arch/hpc/stand/hpcboot/arm/arm_pxa2x0.cpp

523

if (reg & (1U << 1)) {

sys/arch/hpc/stand/hpcboot/arm/arm_pxa2x0.cpp

527

if (reg & (1U << 0)) {

sys/arch/hpc/stand/hpcboot/arm/arm_pxa2x0.cpp

532

DPRINTF((TEXT("-> PDD = 0x%02x\n"), (reg >> 12) & 0xff));

sys/arch/hpc/stand/hpcboot/arm/arm_pxa2x0.cpp

533

reg = VOLATILE_REF(lcdc + 0x04);

sys/arch/hpc/stand/hpcboot/arm/arm_pxa2x0.cpp

534

DPRINTF((TEXT("LCCR1: 0x%08x\n"), reg));

sys/arch/hpc/stand/hpcboot/arm/arm_pxa2x0.cpp

536

(reg >> 24) & 0xff, (reg >> 16) & 0xff, (reg >> 10) & 0x3f,

sys/arch/hpc/stand/hpcboot/arm/arm_pxa2x0.cpp

537

reg & 0x3ff));

sys/arch/hpc/stand/hpcboot/arm/arm_pxa2x0.cpp

538

reg = VOLATILE_REF(lcdc + 0x08);

sys/arch/hpc/stand/hpcboot/arm/arm_pxa2x0.cpp

539

DPRINTF((TEXT("LCCR2: 0x%08x\n"), reg));

sys/arch/hpc/stand/hpcboot/arm/arm_pxa2x0.cpp

541

(reg >> 24) & 0xff, (reg >> 16) & 0xff, (reg >> 10) & 0x3f,

sys/arch/hpc/stand/hpcboot/arm/arm_pxa2x0.cpp

542

reg & 0x3ff));

sys/arch/hpc/stand/hpcboot/arm/arm_pxa2x0.cpp

543

reg = VOLATILE_REF(lcdc + 0x0c);

sys/arch/hpc/stand/hpcboot/arm/arm_pxa2x0.cpp

544

DPRINTF((TEXT("LCCR3: 0x%08x\n"), reg));

sys/arch/hpc/stand/hpcboot/arm/arm_pxa2x0.cpp

547

if (reg & (1U << 27)) {

sys/arch/hpc/stand/hpcboot/arm/arm_pxa2x0.cpp

551

if (reg & (1U << 23)) {

sys/arch/hpc/stand/hpcboot/arm/arm_pxa2x0.cpp

555

if (reg & (1U << 22)) {

sys/arch/hpc/stand/hpcboot/arm/arm_pxa2x0.cpp

559

if (reg & (1U << 21)) {

sys/arch/hpc/stand/hpcboot/arm/arm_pxa2x0.cpp

563

if (reg & (1U << 20)) {

sys/arch/hpc/stand/hpcboot/arm/arm_pxa2x0.cpp

567

if (reg & (1U << 19)) {

sys/arch/hpc/stand/hpcboot/arm/arm_pxa2x0.cpp

572

DPRINTF((TEXT("-> PDFOR = %d\n"), (reg >> 30) & 3));

sys/arch/hpc/stand/hpcboot/arm/arm_pxa2x0.cpp

573

DPRINTF((TEXT("-> BPP = 0x%02x\n"), ((reg >> 29) & 1 << 3) | ((reg >> 24) & 7)));

sys/arch/hpc/stand/hpcboot/arm/arm_pxa2x0.cpp

574

DPRINTF((TEXT("-> API = 0x%x\n"), (reg >> 16) & 0xf));

sys/arch/hpc/stand/hpcboot/arm/arm_pxa2x0.cpp

575

DPRINTF((TEXT("-> ACB = 0x%02x\n"), (reg >> 8) & 0xff));

sys/arch/hpc/stand/hpcboot/arm/arm_pxa2x0.cpp

576

DPRINTF((TEXT("-> PCD = 0x%02x\n"), reg & 0xff));

sys/arch/hpc/stand/hpcboot/arm/arm_pxa2x0.cpp

577

reg = VOLATILE_REF(lcdc + 0x10);

sys/arch/hpc/stand/hpcboot/arm/arm_pxa2x0.cpp

578

DPRINTF((TEXT("LCCR4: 0x%08x\n"), reg));

sys/arch/hpc/stand/hpcboot/arm/arm_pxa2x0.cpp

579

DPRINTF((TEXT("-> PCDDIV = %d\n"), (reg >> 31) & 1));

sys/arch/hpc/stand/hpcboot/arm/arm_pxa2x0.cpp

580

DPRINTF((TEXT("-> PAL_FOR = %d\n"), (reg >> 15) & 3));

sys/arch/hpc/stand/hpcboot/arm/arm_pxa2x0.cpp

582

(reg >> 6) & 7, (reg >> 3) & 7, reg & 7));

sys/arch/hpc/stand/hpcboot/arm/arm_pxa2x0.cpp

583

reg = VOLATILE_REF(lcdc + 0x14);

sys/arch/hpc/stand/hpcboot/arm/arm_pxa2x0.cpp

584

DPRINTF((TEXT("LCCR5: 0x%08x\n"), reg));

sys/arch/hpc/stand/hpcboot/arm/arm_pxa2x0.cpp

585

reg = VOLATILE_REF(lcdc + 0x54);

sys/arch/hpc/stand/hpcboot/arm/arm_pxa2x0.cpp

586

DPRINTF((TEXT("LCDBSCNTR: 0x%08x\n"), reg));

sys/arch/hpc/stand/hpcboot/arm/arm_pxa2x0_console.h

54

uint8_t reg;

sys/arch/hpc/stand/hpcboot/arm/arm_pxa2x0_console.h

56

reg = VOLATILE_REF8(_uart_base + 0x14);

sys/arch/hpc/stand/hpcboot/arm/arm_pxa2x0_console.h

57

while (!(reg & 0x20));

sys/arch/hpc/stand/hpcboot/arm/arm_pxa2x0_console.h

61

uint8_t reg = VOLATILE_REF8(_uart_base + 0x08);

sys/arch/hpc/stand/hpcboot/arm/arm_sa1100_console.h

54

uint8_t reg;

sys/arch/hpc/stand/hpcboot/arm/arm_sa1100_console.h

56

reg = VOLATILE_REF8(_uart_base + 0x20);

sys/arch/hpc/stand/hpcboot/arm/arm_sa1100_console.h

57

while ((reg & 0x1) == 0x1 ||(reg & 0x4) == 0);

sys/arch/hpc/stand/hpcboot/hpcboot.cpp

333

_dbg_bit_print(uint32_t reg, uint32_t mask, const char *name)

sys/arch/hpc/stand/hpcboot/hpcboot.cpp

339

DPRINTF((TEXT("%S[%c] "), name, onoff[reg & mask ? 1 : 0]));

sys/arch/hpc/stand/hpcboot/sh3/dev/sh_dev.cpp

167

(_reg_read_2(tab->reg) >> tab->shift) & SH_IPR_MASK));

sys/arch/hpc/stand/hpcboot/sh3/dev/sh_dev.cpp

51

uint32_t reg = 0;

sys/arch/hpc/stand/hpcboot/sh3/dev/sh_dev.cpp

66

"mov.l r0, @r4", &reg);

sys/arch/hpc/stand/hpcboot/sh3/dev/sh_dev.cpp

69

bitdisp(reg);

sys/arch/hpc/stand/hpcboot/sh3/dev/sh_dev.h

43

paddr_t reg;

sys/arch/hpcarm/dev/ipaq_pcic.c

173

ipaqpcic_read(struct sapcic_socket *so, int reg)

sys/arch/hpcarm/dev/ipaq_pcic.c

180

switch (reg) {

sys/arch/hpcarm/dev/ipaq_pcic.c

200

ipaqpcic_write(struct sapcic_socket *so, int reg, int arg)

sys/arch/hpcarm/dev/ipaq_pcic.c

206

switch (reg) {

sys/arch/hpcarm/dev/j720lcd.c

222

uint32_t reg;

sys/arch/hpcarm/dev/j720lcd.c

235

reg = bus_space_read_4(psc->sc_iot, psc->sc_ppch, SAPPC_PSR);

sys/arch/hpcarm/dev/j720lcd.c

236

reg |= 0x1;

sys/arch/hpcarm/dev/j720lcd.c

237

bus_space_write_4(psc->sc_iot, psc->sc_ppch, SAPPC_PSR, reg);

sys/arch/hpcarm/dev/j720lcd.c

244

reg = bus_space_read_4(psc->sc_iot, psc->sc_ppch, SAPPC_PSR);

sys/arch/hpcarm/dev/j720lcd.c

245

reg |= 0x4;

sys/arch/hpcarm/dev/j720lcd.c

246

bus_space_write_4(psc->sc_iot, psc->sc_ppch, SAPPC_PSR, reg);

sys/arch/hpcarm/dev/j720lcd.c

251

reg = bus_space_read_4(psc->sc_iot, psc->sc_ppch, SAPPC_PSR);

sys/arch/hpcarm/dev/j720lcd.c

252

reg |= 0x2;

sys/arch/hpcarm/dev/j720lcd.c

253

bus_space_write_4(psc->sc_iot, psc->sc_ppch, SAPPC_PSR, reg);

sys/arch/hpcarm/dev/j720lcd.c

255

reg = bus_space_read_4(psc->sc_iot, psc->sc_ppch, SAPPC_PSR);

sys/arch/hpcarm/dev/j720lcd.c

256

reg &= ~0x2;

sys/arch/hpcarm/dev/j720lcd.c

257

bus_space_write_4(psc->sc_iot, psc->sc_ppch, SAPPC_PSR, reg);

sys/arch/hpcarm/dev/j720lcd.c

258

reg &= ~0x4;

sys/arch/hpcarm/dev/j720lcd.c

259

bus_space_write_4(psc->sc_iot, psc->sc_ppch, SAPPC_PSR, reg);

sys/arch/hpcarm/dev/j720lcd.c

268

reg = bus_space_read_4(psc->sc_iot, psc->sc_ppch, SAPPC_PSR);

sys/arch/hpcarm/dev/j720lcd.c

269

reg &= ~0x1;

sys/arch/hpcarm/dev/j720lcd.c

270

bus_space_write_4(psc->sc_iot, psc->sc_ppch, SAPPC_PSR, reg);

sys/arch/hpcarm/dev/nbppcic.c

108

int reg;

sys/arch/hpcarm/dev/nbppcic.c

112

reg = pxa2x0_gpio_get_function(sc->sc_irqcfpin[so->socket]);

sys/arch/hpcarm/dev/nbppcic.c

113

return (HAVE_CARD(reg) ?

sys/arch/hpcarm/dev/nbppcic.c

117

reg = pxa2x0_gpio_get_function(sc->sc_irqpin[so->socket]);

sys/arch/hpcarm/dev/nbppcic.c

118

return (reg & GPIO_SET) ? 1 : 0;

sys/arch/hpcarm/dev/uda1341.c

106

#define GPIO_WRITE(sc, reg, val) \

sys/arch/hpcarm/dev/uda1341.c

107

bus_space_write_4(sc->sc_iot, sc->sc_parent->sc_gpioh, reg, val)

sys/arch/hpcarm/dev/uda1341.c

108

#define GPIO_READ(sc, reg) \

sys/arch/hpcarm/dev/uda1341.c

109

bus_space_read_4(sc->sc_iot, sc->sc_parent->sc_gpioh, reg)

sys/arch/hpcarm/dev/uda1341.c

113

#define SSP_WRITE(sc, reg, val) \

sys/arch/hpcarm/dev/uda1341.c

114

bus_space_write_4(sc->sc_iot, sc->sc_parent->sc_ssph, reg, val)

sys/arch/hpcmips/dev/it8368.c

170

u_int16_t oreg, reg;

sys/arch/hpcmips/dev/it8368.c

178

reg = it8368_reg_read(csregt, csregh, IT8368_CTRL_REG);

sys/arch/hpcmips/dev/it8368.c

179

oreg = reg;

sys/arch/hpcmips/dev/it8368.c

180

dbg_bit_print(reg);

sys/arch/hpcmips/dev/it8368.c

182

reg &= ~IT8368_CTRL_BYTESWAP;

sys/arch/hpcmips/dev/it8368.c

183

it8368_reg_write(csregt, csregh, IT8368_CTRL_REG, reg);

sys/arch/hpcmips/dev/it8368.c

184

reg = it8368_reg_read(csregt, csregh, IT8368_CTRL_REG);

sys/arch/hpcmips/dev/it8368.c

185

if (reg & IT8368_CTRL_BYTESWAP)

sys/arch/hpcmips/dev/it8368.c

188

reg |= IT8368_CTRL_BYTESWAP;

sys/arch/hpcmips/dev/it8368.c

189

it8368_reg_write(csregt, csregh, IT8368_CTRL_REG, reg);

sys/arch/hpcmips/dev/it8368.c

190

reg = it8368_reg_read(csregt, csregh, IT8368_CTRL_REG);

sys/arch/hpcmips/dev/it8368.c

191

if (!(reg & IT8368_CTRL_BYTESWAP))

sys/arch/hpcmips/dev/it8368.c

221

u_int16_t reg;

sys/arch/hpcmips/dev/it8368.c

239

reg = it8368_reg_read(csregt, csregh, IT8368_CTRL_REG);

sys/arch/hpcmips/dev/it8368.c

240

reg &= ~IT8368_CTRL_ADDRSEL;

sys/arch/hpcmips/dev/it8368.c

241

it8368_reg_write(csregt, csregh, IT8368_CTRL_REG, reg);

sys/arch/hpcmips/dev/it8368.c

244

reg = it8368_reg_read(csregt, csregh, IT8368_MFIODIR_REG);

sys/arch/hpcmips/dev/it8368.c

245

reg |= IT8368_MFIODIR_MASK;

sys/arch/hpcmips/dev/it8368.c

246

it8368_reg_write(csregt, csregh, IT8368_MFIODIR_REG, reg);

sys/arch/hpcmips/dev/it8368.c

249

reg = it8368_reg_read(csregt, csregh, IT8368_MFIOSEL_REG);

sys/arch/hpcmips/dev/it8368.c

250

reg &= ~IT8368_MFIOSEL_MASK;

sys/arch/hpcmips/dev/it8368.c

251

it8368_reg_write(csregt, csregh, IT8368_MFIOSEL_REG, reg);

sys/arch/hpcmips/dev/it8368.c

254

reg = it8368_reg_read(csregt, csregh, IT8368_MFIOPOSINTEN_REG);

sys/arch/hpcmips/dev/it8368.c

255

reg &= ~IT8368_MFIOPOSINTEN_MASK;

sys/arch/hpcmips/dev/it8368.c

256

it8368_reg_write(csregt, csregh, IT8368_MFIOPOSINTEN_REG, reg);

sys/arch/hpcmips/dev/it8368.c

257

reg = it8368_reg_read(csregt, csregh, IT8368_MFIONEGINTEN_REG);

sys/arch/hpcmips/dev/it8368.c

258

reg &= ~IT8368_MFIONEGINTEN_MASK;

sys/arch/hpcmips/dev/it8368.c

259

it8368_reg_write(csregt, csregh, IT8368_MFIONEGINTEN_REG, reg);

sys/arch/hpcmips/dev/it8368.c

262

reg = IT8368_PIN_CRDVCCON1 | IT8368_PIN_CRDVCCON0 |

sys/arch/hpcmips/dev/it8368.c

265

it8368_reg_write(csregt, csregh, IT8368_GPIODIR_REG, reg);

sys/arch/hpcmips/dev/it8368.c

271

reg = it8368_reg_read(csregt, csregh, IT8368_CTRL_REG);

sys/arch/hpcmips/dev/it8368.c

273

reg |= IT8368_CTRL_FIXATTRIO;

sys/arch/hpcmips/dev/it8368.c

274

it8368_reg_write(csregt, csregh, IT8368_CTRL_REG, reg);

sys/arch/hpcmips/dev/it8368.c

294

reg = it8368_reg_read(csregt, csregh, IT8368_CTRL_REG);

sys/arch/hpcmips/dev/it8368.c

295

reg |= (IT8368_CTRL_GLOBALEN | IT8368_CTRL_CARDEN);

sys/arch/hpcmips/dev/it8368.c

297

reg |= IT8368_CTRL_FIXATTRIO;

sys/arch/hpcmips/dev/it8368.c

298

it8368_reg_write(csregt, csregh, IT8368_CTRL_REG, reg);

sys/arch/hpcmips/dev/it8368.c

330

u_int16_t reg;

sys/arch/hpcmips/dev/it8368.c

332

reg = it8368_reg_read(csregt, csregh, IT8368_GPIONEGINTSTAT_REG);

sys/arch/hpcmips/dev/it8368.c

334

if (reg & IT8368_PIN_BCRDRDY) {

sys/arch/hpcmips/dev/it8368.c

344

} else if (reg & IT8368_PIN_CRDDET2) {

sys/arch/hpcmips/dev/it8368.c

355

reg2 = reg & ~(IT8368_PIN_BCRDRDY|IT8368_PIN_CRDDET2);

sys/arch/hpcmips/dev/it8368.c

359

reg);

sys/arch/hpcmips/dev/it8368.c

395

u_int16_t reg;

sys/arch/hpcmips/dev/it8368.c

400

reg = IT8368_PIN_CRDDET2; /* CSC */

sys/arch/hpcmips/dev/it8368.c

402

it8368_reg_write(csregt, csregh, IT8368_GPIONEGINTEN_REG, reg);

sys/arch/hpcmips/dev/it8368.c

417

reg = it8368_reg_read(csregt, csregh, IT8368_GPIODATAIN_REG);

sys/arch/hpcmips/dev/it8368.c

419

if (reg & (IT8368_PIN_CRDDET2|IT8368_PIN_CRDDET1)) {

sys/arch/hpcmips/dev/it8368.c

434

u_int16_t reg;

sys/arch/hpcmips/dev/it8368.c

448

reg = it8368_reg_read(csregt, csregh, IT8368_GPIONEGINTEN_REG);

sys/arch/hpcmips/dev/it8368.c

449

reg |= IT8368_PIN_BCRDRDY;

sys/arch/hpcmips/dev/it8368.c

450

it8368_reg_write(csregt, csregh, IT8368_GPIONEGINTEN_REG, reg);

sys/arch/hpcmips/dev/it8368.c

461

u_int16_t reg;

sys/arch/hpcmips/dev/it8368.c

472

reg = it8368_reg_read(csregt, csregh, IT8368_GPIONEGINTEN_REG);

sys/arch/hpcmips/dev/it8368.c

473

reg &= ~IT8368_PIN_BCRDRDY;

sys/arch/hpcmips/dev/it8368.c

474

it8368_reg_write(csregt, csregh, IT8368_GPIONEGINTEN_REG, reg);

sys/arch/hpcmips/dev/it8368.c

656

volatile u_int16_t reg;

sys/arch/hpcmips/dev/it8368.c

659

reg = it8368_reg_read(csregt, csregh, IT8368_GPIODATAOUT_REG);

sys/arch/hpcmips/dev/it8368.c

660

reg &= ~(IT8368_PIN_CRDVCCMASK | IT8368_PIN_CRDVPPMASK);

sys/arch/hpcmips/dev/it8368.c

661

reg |= (IT8368_PIN_CRDVCC_0V | IT8368_PIN_CRDVPP_0V);

sys/arch/hpcmips/dev/it8368.c

662

it8368_reg_write(csregt, csregh, IT8368_GPIODATAOUT_REG, reg);

sys/arch/hpcmips/dev/it8368.c

672

reg = it8368_reg_read(csregt, csregh, IT8368_GPIODATAOUT_REG);

sys/arch/hpcmips/dev/it8368.c

673

reg &= ~(IT8368_PIN_CRDVCCMASK | IT8368_PIN_CRDVPPMASK);

sys/arch/hpcmips/dev/it8368.c

674

reg |= IT8368_PIN_CRDVCC_5V; /* XXX */

sys/arch/hpcmips/dev/it8368.c

675

it8368_reg_write(csregt, csregh, IT8368_GPIODATAOUT_REG, reg);

sys/arch/hpcmips/dev/it8368.c

687

reg = it8368_reg_read(csregt, csregh, IT8368_GPIODATAOUT_REG);

sys/arch/hpcmips/dev/it8368.c

688

reg |= IT8368_PIN_BCRDRST;

sys/arch/hpcmips/dev/it8368.c

689

it8368_reg_write(csregt, csregh, IT8368_GPIODATAOUT_REG, reg);

sys/arch/hpcmips/dev/it8368.c

697

reg = it8368_reg_read(csregt, csregh, IT8368_GPIODATAOUT_REG);

sys/arch/hpcmips/dev/it8368.c

698

reg &= ~IT8368_PIN_BCRDRST;

sys/arch/hpcmips/dev/it8368.c

699

it8368_reg_write(csregt, csregh, IT8368_GPIODATAOUT_REG, reg);

sys/arch/hpcmips/dev/it8368.c

713

u_int16_t reg;

sys/arch/hpcmips/dev/it8368.c

716

reg = it8368_reg_read(csregt, csregh, IT8368_GPIODATAOUT_REG);

sys/arch/hpcmips/dev/it8368.c

717

reg &= ~(IT8368_PIN_CRDVCCMASK | IT8368_PIN_CRDVPPMASK);

sys/arch/hpcmips/dev/it8368.c

718

reg |= (IT8368_PIN_CRDVCC_0V | IT8368_PIN_CRDVPP_0V);

sys/arch/hpcmips/dev/it8368.c

719

it8368_reg_write(csregt, csregh, IT8368_GPIODATAOUT_REG, reg);

sys/arch/hpcmips/dev/mq200debug.c

102

reg, FIXEDFLOAT1000(sc->sc_baseclock), m, n);

sys/arch/hpcmips/dev/mq200debug.c

110

reg = mq200_read(sc, MQ200_PLL3R);

sys/arch/hpcmips/dev/mq200debug.c

111

m = (((reg & MQ200_PLL_M_MASK) >> MQ200_PLL_M_SHIFT) + 1);

sys/arch/hpcmips/dev/mq200debug.c

112

n = ((((reg & MQ200_PLL_N_MASK) >> MQ200_PLL_N_SHIFT) + 1) <<

sys/arch/hpcmips/dev/mq200debug.c

113

((reg & MQ200_PLL_P_MASK) >> MQ200_PLL_P_SHIFT));

sys/arch/hpcmips/dev/mq200debug.c

117

reg, FIXEDFLOAT1000(sc->sc_baseclock), m, n);

sys/arch/hpcmips/dev/mq200debug.c

131

reg = mq200_read(sc, MQ200_GCCR(MQ200_GC1));

sys/arch/hpcmips/dev/mq200debug.c

132

if (reg & MQ200_GCC_ENABLE) {

sys/arch/hpcmips/dev/mq200debug.c

134

rc = (reg&MQ200_GCC_RCLK_MASK)>>MQ200_GCC_RCLK_SHIFT;

sys/arch/hpcmips/dev/mq200debug.c

135

fd = (reg&MQ200_GCC_MCLK_FD_MASK)>>MQ200_GCC_MCLK_FD_SHIFT;

sys/arch/hpcmips/dev/mq200debug.c

136

sd = (reg&MQ200_GCC_MCLK_SD_MASK)>>MQ200_GCC_MCLK_SD_SHIFT;

sys/arch/hpcmips/dev/mq200debug.c

141

reg = mq200_read(sc, MQ200_GC1CRTCR);

sys/arch/hpcmips/dev/mq200debug.c

142

if (reg&MQ200_GC1CRTC_DACEN)

sys/arch/hpcmips/dev/mq200debug.c

144

reg = mq200_read(sc, MQ200_FPCR);

sys/arch/hpcmips/dev/mq200debug.c

145

if ((reg & MQ200_FPC_ENABLE) && !(reg & MQ200_FPC_GC2))

sys/arch/hpcmips/dev/mq200debug.c

153

reg = mq200_read(sc, MQ200_GCCR(MQ200_GC2));

sys/arch/hpcmips/dev/mq200debug.c

154

if (reg & MQ200_GCC_ENABLE) {

sys/arch/hpcmips/dev/mq200debug.c

156

rc = (reg&MQ200_GCC_RCLK_MASK)>>MQ200_GCC_RCLK_SHIFT;

sys/arch/hpcmips/dev/mq200debug.c

157

fd = (reg&MQ200_GCC_MCLK_FD_MASK)>>MQ200_GCC_MCLK_FD_SHIFT;

sys/arch/hpcmips/dev/mq200debug.c

158

sd = (reg&MQ200_GCC_MCLK_SD_MASK)>>MQ200_GCC_MCLK_SD_SHIFT;

sys/arch/hpcmips/dev/mq200debug.c

162

reg = mq200_read(sc, MQ200_FPCR);

sys/arch/hpcmips/dev/mq200debug.c

163

if ((reg & MQ200_FPC_ENABLE) && (reg & MQ200_FPC_GC2))

sys/arch/hpcmips/dev/mq200debug.c

235

u_int32_t reg;

sys/arch/hpcmips/dev/mq200debug.c

260

reg = mq200_read(sc, MQ200_GCCR(gc));

sys/arch/hpcmips/dev/mq200debug.c

261

printf("GC00R=0x%08x: ", reg);

sys/arch/hpcmips/dev/mq200debug.c

263

ENABLE(reg & MQ200_GCC_ENABLE),

sys/arch/hpcmips/dev/mq200debug.c

264

(reg & MQ200_GCC_HCRESET)?"HC_reset ":"",

sys/arch/hpcmips/dev/mq200debug.c

265

(reg & MQ200_GCC_VCRESET)?"VC_reset ":"",

sys/arch/hpcmips/dev/mq200debug.c

266

(reg & MQ200_GCC_HCEN)?"cursor_enable ":"",

sys/arch/hpcmips/dev/mq200debug.c

267

(reg & MQ200_GCC_TESTMODE0)?"test_mode0 ":"",

sys/arch/hpcmips/dev/mq200debug.c

268

(reg & MQ200_GCC_TESTMODE1)?"test_mode1 ":"");

sys/arch/hpcmips/dev/mq200debug.c

270

ENABLE(reg & MQ200_GCC_WINEN),

sys/arch/hpcmips/dev/mq200debug.c

271

depth_names[(reg&MQ200_GCC_DEPTH_MASK)>>MQ200_GCC_DEPTH_SHIFT]);

sys/arch/hpcmips/dev/mq200debug.c

273

ENABLE(reg & MQ200_GCC_ALTEN),

sys/arch/hpcmips/dev/mq200debug.c

274

depth_names[(reg&MQ200_GCC_ALTDEPTH_MASK)>>MQ200_GCC_ALTDEPTH_SHIFT]);

sys/arch/hpcmips/dev/mq200debug.c

276

rc_names[(reg&MQ200_GCC_RCLK_MASK)>>MQ200_GCC_RCLK_SHIFT],

sys/arch/hpcmips/dev/mq200debug.c

277

fd_names[(reg&MQ200_GCC_MCLK_FD_MASK)>>MQ200_GCC_MCLK_FD_SHIFT],

sys/arch/hpcmips/dev/mq200debug.c

278

(reg&MQ200_GCC_MCLK_SD_MASK)>>MQ200_GCC_MCLK_SD_SHIFT);

sys/arch/hpcmips/dev/mq200debug.c

284

reg = mq200_read(sc, MQ200_GC1CRTCR);

sys/arch/hpcmips/dev/mq200debug.c

285

printf("GC01R=0x%08x:\n", reg);

sys/arch/hpcmips/dev/mq200debug.c

287

ENABLE(reg&MQ200_GC1CRTC_DACEN));

sys/arch/hpcmips/dev/mq200debug.c

290

switch (reg & MQ200_GC1CRTC_HSYNC_PMMASK) {

sys/arch/hpcmips/dev/mq200debug.c

292

if (reg & MQ200_GC1CRTC_HSYNC_PMCLK)

sys/arch/hpcmips/dev/mq200debug.c

309

switch (reg & MQ200_GC1CRTC_VSYNC_PMMASK) {

sys/arch/hpcmips/dev/mq200debug.c

311

if (reg & MQ200_GC1CRTC_VSYNC_PMCLK)

sys/arch/hpcmips/dev/mq200debug.c

329

(reg & MQ200_GC1CRTC_HSYNC_ACTVLOW)?"low":"high",

sys/arch/hpcmips/dev/mq200debug.c

330

(reg & MQ200_GC1CRTC_VSYNC_ACTVLOW)?"low":"high");

sys/arch/hpcmips/dev/mq200debug.c

332

if (reg & MQ200_GC1CRTC_SYNC_PEDESTAL_EN)

sys/arch/hpcmips/dev/mq200debug.c

334

if (reg & MQ200_GC1CRTC_BLANK_PEDESTAL_EN)

sys/arch/hpcmips/dev/mq200debug.c

336

if (reg & MQ200_GC1CRTC_COMPOSITE_SYNC_EN)

sys/arch/hpcmips/dev/mq200debug.c

338

if (reg & MQ200_GC1CRTC_VREF_EXTR)

sys/arch/hpcmips/dev/mq200debug.c

340

if (reg & MQ200_GC1CRTC_MONITOR_SENCE_EN) {

sys/arch/hpcmips/dev/mq200debug.c

341

if (reg & MQ200_GC1CRTC_CONSTANT_OUTPUT_EN)

sys/arch/hpcmips/dev/mq200debug.c

343

(reg & MQ200_GC1CRTC_BLUE_NOTLOADED)?"":"B",

sys/arch/hpcmips/dev/mq200debug.c

344

(reg & MQ200_GC1CRTC_RED_NOTLOADED)?"":"R",

sys/arch/hpcmips/dev/mq200debug.c

345

(reg & MQ200_GC1CRTC_GREEN_NOTLOADED)?"":"G");

sys/arch/hpcmips/dev/mq200debug.c

348

(reg & MQ200_GC1CRTC_BLUE_NOTLOADED)?"":"B",

sys/arch/hpcmips/dev/mq200debug.c

349

(reg & MQ200_GC1CRTC_RED_NOTLOADED)?"":"R",

sys/arch/hpcmips/dev/mq200debug.c

350

(reg & MQ200_GC1CRTC_GREEN_NOTLOADED)?"":"G",

sys/arch/hpcmips/dev/mq200debug.c

351

(reg & MQ200_GC1CRTC_OUTPUT_LEVEL_MASK)>>MQ200_GC1CRTC_OUTPUT_LEVEL_SHIFT);

sys/arch/hpcmips/dev/mq200debug.c

353

if (reg & MQ200_GC1CRTC_MONO)

sys/arch/hpcmips/dev/mq200debug.c

361

reg = mq200_read(sc, MQ200_GCHDCR(gc));

sys/arch/hpcmips/dev/mq200debug.c

363

printf("GC02R=0x%08x: Horizontal display total=%03d end=%03d\n", reg,

sys/arch/hpcmips/dev/mq200debug.c

364

(reg&MQ200_GC1HDC_TOTAL_MASK)>>MQ200_GC1HDC_TOTAL_SHIFT,

sys/arch/hpcmips/dev/mq200debug.c

365

(reg&MQ200_GCHDC_END_MASK)>>MQ200_GCHDC_END_SHIFT);

sys/arch/hpcmips/dev/mq200debug.c

367

printf("GC02R=0x%08x: Horizontal display end=%03d\n", reg,

sys/arch/hpcmips/dev/mq200debug.c

368

(reg&MQ200_GCHDC_END_MASK)>>MQ200_GCHDC_END_SHIFT);

sys/arch/hpcmips/dev/mq200debug.c

374

reg = mq200_read(sc, MQ200_GCVDCR(gc));

sys/arch/hpcmips/dev/mq200debug.c

376

printf("GC03R=0x%08x: Vertical display total=%03d end=%03d\n", reg,

sys/arch/hpcmips/dev/mq200debug.c

377

(reg&MQ200_GC1VDC_TOTAL_MASK)>>MQ200_GC1VDC_TOTAL_SHIFT,

sys/arch/hpcmips/dev/mq200debug.c

378

(reg&MQ200_GCVDC_END_MASK)>>MQ200_GCVDC_END_SHIFT);

sys/arch/hpcmips/dev/mq200debug.c

380

printf("GC03R=0x%08x: Vertical display end=%03d\n", reg,

sys/arch/hpcmips/dev/mq200debug.c

381

(reg&MQ200_GCVDC_END_MASK)>>MQ200_GCVDC_END_SHIFT);

sys/arch/hpcmips/dev/mq200debug.c

387

reg = mq200_read(sc, MQ200_GCHSCR(gc));

sys/arch/hpcmips/dev/mq200debug.c

388

printf("GC04R=0x%08x: Horizontal sync start=%03d end=%03d\n", reg,

sys/arch/hpcmips/dev/mq200debug.c

389

(reg&MQ200_GCHSC_START_MASK)>>MQ200_GCHSC_START_SHIFT,

sys/arch/hpcmips/dev/mq200debug.c

390

(reg&MQ200_GCHSC_END_MASK)>>MQ200_GCHSC_END_SHIFT);

sys/arch/hpcmips/dev/mq200debug.c

395

reg = mq200_read(sc, MQ200_GCVSCR(gc));

sys/arch/hpcmips/dev/mq200debug.c

396

printf("GC05R=0x%08x: Vertical sync start=%03d end=%03d\n", reg,

sys/arch/hpcmips/dev/mq200debug.c

397

(reg&MQ200_GCVSC_START_MASK)>>MQ200_GCVSC_START_SHIFT,

sys/arch/hpcmips/dev/mq200debug.c

398

(reg&MQ200_GCVSC_END_MASK)>>MQ200_GCVSC_END_SHIFT);

sys/arch/hpcmips/dev/mq200debug.c

404

reg = mq200_read(sc, MQ200_GC1VDCNTR);

sys/arch/hpcmips/dev/mq200debug.c

405

printf("GC07R=0x%08x: Vertical Display Count=%d\n", reg,

sys/arch/hpcmips/dev/mq200debug.c

406

(reg&MQ200_GC1VDCNT_MASK));

sys/arch/hpcmips/dev/mq200debug.c

412

reg = mq200_read(sc, MQ200_GCWHCR(gc));

sys/arch/hpcmips/dev/mq200debug.c

414

reg,

sys/arch/hpcmips/dev/mq200debug.c

415

(reg&MQ200_GCWHC_START_MASK)>> MQ200_GCWHC_START_SHIFT,

sys/arch/hpcmips/dev/mq200debug.c

416

(reg&MQ200_GCWHC_WIDTH_MASK)>> MQ200_GCWHC_WIDTH_SHIFT);

sys/arch/hpcmips/dev/mq200debug.c

419

(reg&MQ200_GC1WHC_ALD_MASK)>> MQ200_GC1WHC_ALD_SHIFT);

sys/arch/hpcmips/dev/mq200debug.c

426

reg = mq200_read(sc, MQ200_GCWVCR(gc));

sys/arch/hpcmips/dev/mq200debug.c

428

reg,

sys/arch/hpcmips/dev/mq200debug.c

429

(reg&MQ200_GCWVC_START_MASK)>> MQ200_GCWVC_START_SHIFT,

sys/arch/hpcmips/dev/mq200debug.c

430

(reg&MQ200_GCWVC_HEIGHT_MASK)>> MQ200_GCWVC_HEIGHT_SHIFT);

sys/arch/hpcmips/dev/mq200debug.c

435

reg = mq200_read(sc, MQ200_GCAWHCR(gc));

sys/arch/hpcmips/dev/mq200debug.c

437

reg,

sys/arch/hpcmips/dev/mq200debug.c

438

(reg&MQ200_GCAWHC_START_MASK)>> MQ200_GCAWHC_START_SHIFT,

sys/arch/hpcmips/dev/mq200debug.c

439

(reg&MQ200_GCAWHC_WIDTH_MASK)>> MQ200_GCAWHC_WIDTH_SHIFT);

sys/arch/hpcmips/dev/mq200debug.c

442

(reg&MQ200_GC1AWHC_ALD_MASK)>> MQ200_GC1AWHC_ALD_SHIFT);

sys/arch/hpcmips/dev/mq200debug.c

449

reg = mq200_read(sc, MQ200_GCAWVCR(gc));

sys/arch/hpcmips/dev/mq200debug.c

451

reg,

sys/arch/hpcmips/dev/mq200debug.c

452

(reg&MQ200_GCAWVC_START_MASK)>> MQ200_GCAWVC_START_SHIFT,

sys/arch/hpcmips/dev/mq200debug.c

453

(reg&MQ200_GCAWVC_HEIGHT_MASK)>> MQ200_GCAWVC_HEIGHT_SHIFT);

sys/arch/hpcmips/dev/mq200debug.c

458

reg = mq200_read(sc, MQ200_GCWSAR(gc));

sys/arch/hpcmips/dev/mq200debug.c

460

reg, (reg&MQ200_GCWSA_MASK));

sys/arch/hpcmips/dev/mq200debug.c

465

reg = mq200_read(sc, MQ200_GCAWSAR(gc));

sys/arch/hpcmips/dev/mq200debug.c

467

reg, (reg&MQ200_GCAWSA_MASK),

sys/arch/hpcmips/dev/mq200debug.c

468

(reg&MQ200_GCAWPI_MASK)>>MQ200_GCAWPI_SHIFT);

sys/arch/hpcmips/dev/mq200debug.c

473

reg = mq200_read(sc, MQ200_GCWSTR(gc));

sys/arch/hpcmips/dev/mq200debug.c

475

reg,

sys/arch/hpcmips/dev/mq200debug.c

476

(reg&MQ200_GCWST_MASK)>>MQ200_GCWST_SHIFT,

sys/arch/hpcmips/dev/mq200debug.c

477

(reg&MQ200_GCAWST_MASK)>>MQ200_GCAWST_SHIFT);

sys/arch/hpcmips/dev/mq200debug.c

482

reg = mq200_read(sc, MQ200_GCHCPR(gc));

sys/arch/hpcmips/dev/mq200debug.c

484

reg,

sys/arch/hpcmips/dev/mq200debug.c

485

(reg&MQ200_GCHCP_HSTART_MASK)>>MQ200_GCHCP_HSTART_SHIFT,

sys/arch/hpcmips/dev/mq200debug.c

486

(reg&MQ200_GCHCP_VSTART_MASK)>>MQ200_GCHCP_VSTART_SHIFT);

sys/arch/hpcmips/dev/mq200debug.c

491

reg = mq200_read(sc, MQ200_GCHCAOR(gc));

sys/arch/hpcmips/dev/mq200debug.c

493

reg);

sys/arch/hpcmips/dev/mq200debug.c

498

reg = mq200_read(sc, MQ200_GCHCFCR(gc));

sys/arch/hpcmips/dev/mq200debug.c

499

printf("GC12R=0x%08x: Hardware Cursor Foreground Color\n", reg);

sys/arch/hpcmips/dev/mq200debug.c

504

reg = mq200_read(sc, MQ200_GCHCBCR(gc));

sys/arch/hpcmips/dev/mq200debug.c

505

printf("GC13R=0x%08x: Hardware Cursor Background Color\n", reg);

sys/arch/hpcmips/dev/mq200debug.c

512

u_int32_t reg;

sys/arch/hpcmips/dev/mq200debug.c

531

reg = mq200_read(sc, MQ200_FPCR);

sys/arch/hpcmips/dev/mq200debug.c

532

printf("FP00R=0x%08x: Flat Panel Control\n", reg);

sys/arch/hpcmips/dev/mq200debug.c

534

ENABLE(reg & MQ200_FPC_ENABLE),

sys/arch/hpcmips/dev/mq200debug.c

535

(reg & MQ200_FPC_GC2) ? "GC2" : "GC1",

sys/arch/hpcmips/dev/mq200debug.c

536

panel_type_names[(reg & MQ200_FPC_TYPE_MASK) >> MQ200_FPC_TYPE_SHIFT]);

sys/arch/hpcmips/dev/mq200debug.c

537

reg = mq200_read(sc, MQ200_FPPCR);

sys/arch/hpcmips/dev/mq200debug.c

538

printf("FP01R=0x%08x: Flat Panel Output Pin Control\n", reg);

sys/arch/hpcmips/dev/mq200debug.c

544

u_int32_t reg;

sys/arch/hpcmips/dev/mq200debug.c

546

reg = 0;

sys/arch/hpcmips/dev/mq200debug.c

63

u_int32_t reg, pm00r;

sys/arch/hpcmips/dev/mq200debug.c

76

reg = mq200_read(sc, MQ200_MMR(1));

sys/arch/hpcmips/dev/mq200debug.c

77

memclock = (reg & MQ200_MM01_CLK_PLL2) ? 2 : 1;

sys/arch/hpcmips/dev/mq200debug.c

83

reg = mq200_read(sc, MQ200_DCMISCR);

sys/arch/hpcmips/dev/mq200debug.c

84

m = ((reg & MQ200_PLL_M_MASK) >> MQ200_PLL_M_SHIFT) + 1;

sys/arch/hpcmips/dev/mq200debug.c

85

n = ((((reg & MQ200_PLL_N_MASK) >> MQ200_PLL_N_SHIFT) + 1) |

sys/arch/hpcmips/dev/mq200debug.c

87

n <<= ((reg & MQ200_PLL_P_MASK) >> MQ200_PLL_P_SHIFT);

sys/arch/hpcmips/dev/mq200debug.c

90

reg, FIXEDFLOAT1000(sc->sc_baseclock), m, n);

sys/arch/hpcmips/dev/mq200debug.c

95

reg = mq200_read(sc, MQ200_PLL2R);

sys/arch/hpcmips/dev/mq200debug.c

96

m = ((reg & MQ200_PLL_M_MASK) >> MQ200_PLL_M_SHIFT) + 1;

sys/arch/hpcmips/dev/mq200debug.c

97

n = ((((reg & MQ200_PLL_N_MASK) >> MQ200_PLL_N_SHIFT) +1) <<

sys/arch/hpcmips/dev/mq200debug.c

98

((reg & MQ200_PLL_P_MASK) >> MQ200_PLL_P_SHIFT));

sys/arch/hpcmips/dev/mq200machdep.c

213

u_int32_t reg, mask, accum;

sys/arch/hpcmips/dev/mq200machdep.c

221

reg = mq200_read(sc, ops[0]);

sys/arch/hpcmips/dev/mq200machdep.c

222

reg = (reg & ~mask) | (ops[1] & mask);

sys/arch/hpcmips/dev/mq200machdep.c

223

mq200_write(sc, ops[0], reg);

sys/arch/hpcmips/dev/mq200machdep.c

237

reg = mq200_read(sc, ops[1]);

sys/arch/hpcmips/dev/mq200machdep.c

238

accum = (accum & ~mask) | (reg & mask);

sys/arch/hpcmips/dev/mq200machdep.c

244

reg = mq200_read(sc, ops[1]);

sys/arch/hpcmips/dev/mq200machdep.c

245

reg = (reg & ~mask) | (accum & mask);

sys/arch/hpcmips/dev/mq200machdep.c

246

mq200_write(sc, ops[1], reg);

sys/arch/hpcmips/dev/mq200priv.h

122

mq200_write2(struct mq200_softc *sc, struct mq200_regctx *reg, u_int32_t data)

sys/arch/hpcmips/dev/mq200priv.h

124

reg->val = data;

sys/arch/hpcmips/dev/mq200priv.h

125

mq200_writex(sc, reg->offset, reg->val);

sys/arch/hpcmips/dev/mq200priv.h

139

mq200_mod(struct mq200_softc *sc, struct mq200_regctx *reg, u_int32_t mask, u_int32_t data)

sys/arch/hpcmips/dev/mq200priv.h

141

reg->val &= ~mask;

sys/arch/hpcmips/dev/mq200priv.h

142

reg->val |= data;

sys/arch/hpcmips/dev/mq200priv.h

143

mq200_writex(sc, reg->offset, reg->val);

sys/arch/hpcmips/dev/mq200priv.h

147

mq200_on(struct mq200_softc *sc, struct mq200_regctx *reg, unsigned long data)

sys/arch/hpcmips/dev/mq200priv.h

149

mq200_mod(sc, reg, data, data);

sys/arch/hpcmips/dev/mq200priv.h

153

mq200_off(struct mq200_softc *sc, struct mq200_regctx *reg, unsigned long data)

sys/arch/hpcmips/dev/mq200priv.h

155

mq200_mod(sc, reg, data, 0);

sys/arch/hpcmips/dev/plum.c

130

plumreg_t reg;

sys/arch/hpcmips/dev/plum.c

137

reg = plum_conf_read(regt, regh, PLUM_ID_REG);

sys/arch/hpcmips/dev/plum.c

140

return (reg);

sys/arch/hpcmips/dev/plum.c

172

plumreg_t reg;

sys/arch/hpcmips/dev/plum.c

174

reg = bus_space_read_4(t, h, o);

sys/arch/hpcmips/dev/plum.c

176

return (reg);

sys/arch/hpcmips/dev/plum.c

88

plumreg_t reg;

sys/arch/hpcmips/dev/plum.c

95

switch (reg = plum_idcheck(sc->sc_csregt)) {

sys/arch/hpcmips/dev/plum.c

97

printf(": unknown revision %#x\n", reg);

sys/arch/hpcmips/dev/plumicu.c

175

plumreg_t reg;

sys/arch/hpcmips/dev/plumicu.c

196

reg = plum_conf_read(regt, regh, pic->ic_ienreg);

sys/arch/hpcmips/dev/plumicu.c

197

reg &= ~pic->ic_ienpat;

sys/arch/hpcmips/dev/plumicu.c

198

plum_conf_write(regt, regh, pic->ic_ienreg, reg);

sys/arch/hpcmips/dev/plumicu.c

201

reg = plum_conf_read(regt, regh, pic->ic_senreg);

sys/arch/hpcmips/dev/plumicu.c

202

reg &= ~pic->ic_senpat;

sys/arch/hpcmips/dev/plumicu.c

203

plum_conf_write(regt, regh, pic->ic_senreg, reg);

sys/arch/hpcmips/dev/plumicu.c

245

plumreg_t reg;

sys/arch/hpcmips/dev/plumicu.c

262

reg = plum_conf_read(regt, regh, pi->pi_ctrl->ic_senreg);

sys/arch/hpcmips/dev/plumicu.c

263

reg |= pi->pi_ctrl->ic_senpat;

sys/arch/hpcmips/dev/plumicu.c

264

plum_conf_write(regt, regh, pi->pi_ctrl->ic_senreg, reg);

sys/arch/hpcmips/dev/plumicu.c

268

reg = plum_conf_read(regt, regh, pi->pi_ctrl->ic_ienreg);

sys/arch/hpcmips/dev/plumicu.c

269

reg |= pi->pi_ctrl->ic_ienpat;

sys/arch/hpcmips/dev/plumicu.c

270

plum_conf_write(regt, regh, pi->pi_ctrl->ic_ienreg, reg);

sys/arch/hpcmips/dev/plumicu.c

291

plumreg_t reg;

sys/arch/hpcmips/dev/plumicu.c

311

reg = plum_conf_read(regt, regh, pi->pi_ctrl->ic_ienreg);

sys/arch/hpcmips/dev/plumicu.c

312

reg &= ~(pi->pi_ctrl->ic_ienpat);

sys/arch/hpcmips/dev/plumicu.c

313

plum_conf_write(regt, regh, pi->pi_ctrl->ic_ienreg, reg);

sys/arch/hpcmips/dev/plumicu.c

316

reg = plum_conf_read(regt, regh, pi->pi_ctrl->ic_senreg);

sys/arch/hpcmips/dev/plumicu.c

317

reg &= ~(pi->pi_ctrl->ic_senpat);

sys/arch/hpcmips/dev/plumicu.c

318

plum_conf_write(regt, regh, pi->pi_ctrl->ic_senreg, reg);

sys/arch/hpcmips/dev/plumicu.c

379

plumreg_t reg;

sys/arch/hpcmips/dev/plumicu.c

382

reg = plum_conf_read(regt, regh, PLUM_INT_INTSTA_REG);

sys/arch/hpcmips/dev/plumicu.c

383

dbg_bit_print(reg);

sys/arch/hpcmips/dev/plumicu.c

386

reg = plum_conf_read(regt, regh, PLUM_INT_EXTINTS_REG);

sys/arch/hpcmips/dev/plumicu.c

387

dbg_bit_print(reg);

sys/arch/hpcmips/dev/plumicu.c

389

reg = plum_conf_read(regt, regh, PLUM_INT_EXTIEN_REG);

sys/arch/hpcmips/dev/plumicu.c

390

dbg_bit_print(reg);

sys/arch/hpcmips/dev/plumiobus.c

225

plumreg_t reg;

sys/arch/hpcmips/dev/plumiobus.c

228

reg = plum_conf_read(regt, regh, PLUM_IOBUS_IOXBSZ_REG);

sys/arch/hpcmips/dev/plumiobus.c

231

if (reg & (1 << i)) {

sys/arch/hpcmips/dev/plumiobus.c

237

reg = PLUM_IOBUS_IOXCCNT_MASK &

sys/arch/hpcmips/dev/plumiobus.c

240

reg + 1);

sys/arch/hpcmips/dev/plumiobus.c

241

reg = plum_conf_read(regt, regh, PLUM_IOBUS_IOXACNT_REG);

sys/arch/hpcmips/dev/plumiobus.c

244

wait = (reg >> (i * PLUM_IOBUS_IOXACNT_SHIFT))

sys/arch/hpcmips/dev/plumiobus.c

250

reg = PLUM_IOBUS_IOXSCNT_MASK &

sys/arch/hpcmips/dev/plumiobus.c

252

printf(" # of wait during access by I/O bus : %d clock\n", reg + 1);

sys/arch/hpcmips/dev/plumiobus.c

254

reg = plum_conf_read(regt, regh, PLUM_IOBUS_IDEMODE_REG);

sys/arch/hpcmips/dev/plumiobus.c

255

if (reg & PLUM_IOBUS_IDEMODE) {

sys/arch/hpcmips/dev/plumpcmcia.c

1007

__memareadump(plumreg_t reg)

sys/arch/hpcmips/dev/plumpcmcia.c

1011

maparea = PLUM_PCMCIA_MEMWINCTRL_MAP(reg);

sys/arch/hpcmips/dev/plumpcmcia.c

1033

plumreg_t reg;

sys/arch/hpcmips/dev/plumpcmcia.c

1049

reg = plum_conf_read(sc->sc_regt, sc->sc_regh,

sys/arch/hpcmips/dev/plumpcmcia.c

1051

printf("%03x %08x", i, reg);

sys/arch/hpcmips/dev/plumpcmcia.c

1052

dbg_bit_print(reg);

sys/arch/hpcmips/dev/plumpcmcia.c

445

plumreg_t reg, addr, offset, size;

sys/arch/hpcmips/dev/plumpcmcia.c

456

reg = ph->ph_mem[win].pm_kind == PCMCIA_MEM_ATTR ?

sys/arch/hpcmips/dev/plumpcmcia.c

460

reg = PLUM_PCMCIA_MEMWINCTRL_MAP_SET(reg, ph->ph_memarea);

sys/arch/hpcmips/dev/plumpcmcia.c

463

reg |= (PLUM_PCMCIA_MEMWINCTRL_ZERO_WS |

sys/arch/hpcmips/dev/plumpcmcia.c

465

plum_conf_write(regt, regh, PLUM_PCMCIA_MEMWINCTRL(win), reg);

sys/arch/hpcmips/dev/plumpcmcia.c

479

reg = plum_conf_read(regt, regh, PLUM_PCMCIA_WINEN);

sys/arch/hpcmips/dev/plumpcmcia.c

480

reg |= PLUM_PCMCIA_WINEN_MEM(win);

sys/arch/hpcmips/dev/plumpcmcia.c

481

plum_conf_write(regt, regh, PLUM_PCMCIA_WINEN, reg);

sys/arch/hpcmips/dev/plumpcmcia.c

495

plumreg_t reg;

sys/arch/hpcmips/dev/plumpcmcia.c

497

reg = plum_conf_read(regt, regh, PLUM_PCMCIA_WINEN);

sys/arch/hpcmips/dev/plumpcmcia.c

498

reg &= ~PLUM_PCMCIA_WINEN_MEM(window);

sys/arch/hpcmips/dev/plumpcmcia.c

499

plum_conf_write(regt, regh, PLUM_PCMCIA_WINEN, reg);

sys/arch/hpcmips/dev/plumpcmcia.c

594

plumreg_t reg;

sys/arch/hpcmips/dev/plumpcmcia.c

621

reg = plum_conf_read(regt, regh, PLUM_PCMCIA_IOWINCTRL);

sys/arch/hpcmips/dev/plumpcmcia.c

625

reg &= ~(PLUM_PCMCIA_IOWINCTRL_WINMASK << shift);

sys/arch/hpcmips/dev/plumpcmcia.c

626

reg |= ((ioctlbits[ph->ph_io[win].pi_width] |

sys/arch/hpcmips/dev/plumpcmcia.c

628

plum_conf_write(regt, regh, PLUM_PCMCIA_IOWINCTRL, reg);

sys/arch/hpcmips/dev/plumpcmcia.c

631

reg = plum_conf_read(regt, regh, PLUM_PCMCIA_WINEN);

sys/arch/hpcmips/dev/plumpcmcia.c

632

reg |= (win == 0 ? PLUM_PCMCIA_WINEN_IO0 :

sys/arch/hpcmips/dev/plumpcmcia.c

634

plum_conf_write(regt, regh, PLUM_PCMCIA_WINEN, reg);

sys/arch/hpcmips/dev/plumpcmcia.c

659

plumreg_t reg;

sys/arch/hpcmips/dev/plumpcmcia.c

661

reg = plum_conf_read(regt, regh, PLUM_PCMCIA_WINEN);

sys/arch/hpcmips/dev/plumpcmcia.c

666

reg &= ~PLUM_PCMCIA_WINEN_IO0;

sys/arch/hpcmips/dev/plumpcmcia.c

669

reg &= ~PLUM_PCMCIA_WINEN_IO1;

sys/arch/hpcmips/dev/plumpcmcia.c

672

plum_conf_write(regt, regh, PLUM_PCMCIA_WINEN, reg);

sys/arch/hpcmips/dev/plumpcmcia.c

705

plumreg_t reg, power;

sys/arch/hpcmips/dev/plumpcmcia.c

711

reg = plum_conf_read(regt, regh, PLUM_PCMCIA_GENCTRL);

sys/arch/hpcmips/dev/plumpcmcia.c

712

reg &= ~PLUM_PCMCIA_GENCTRL_CARDTYPE_MASK;

sys/arch/hpcmips/dev/plumpcmcia.c

713

plum_conf_write(regt, regh, PLUM_PCMCIA_GENCTRL, reg);

sys/arch/hpcmips/dev/plumpcmcia.c

731

reg = plum_conf_read(regt, regh, PLUM_PCMCIA_GENCTRL2);

sys/arch/hpcmips/dev/plumpcmcia.c

732

if ((reg & PLUM_PCMCIA_GENCTRL2_VCC5V) ==

sys/arch/hpcmips/dev/plumpcmcia.c

796

plumreg_t reg;

sys/arch/hpcmips/dev/plumpcmcia.c

800

reg = plum_conf_read(regt, regh, PLUM_PCMCIA_GENCTRL);

sys/arch/hpcmips/dev/plumpcmcia.c

801

reg &= ~PLUM_PCMCIA_GENCTRL_CARDTYPE_MASK;

sys/arch/hpcmips/dev/plumpcmcia.c

803

reg |= PLUM_PCMCIA_GENCTRL_CARDTYPE_IO;

sys/arch/hpcmips/dev/plumpcmcia.c

805

reg |= PLUM_PCMCIA_GENCTRL_CARDTYPE_MEM;

sys/arch/hpcmips/dev/plumpcmcia.c

809

((type == PCMCIA_IFTYPE_IO) ? "io" : "mem"), reg);

sys/arch/hpcmips/dev/plumpcmcia.c

811

plum_conf_write(regt, regh, PLUM_PCMCIA_GENCTRL, reg);

sys/arch/hpcmips/dev/plumpcmcia.c

820

plumreg_t reg;

sys/arch/hpcmips/dev/plumpcmcia.c

823

reg = plum_conf_read(regt, regh, PLUM_PCMCIA_GENCTRL);

sys/arch/hpcmips/dev/plumpcmcia.c

824

reg &= ~PLUM_PCMCIA_GENCTRL_CARDTYPE_MASK;

sys/arch/hpcmips/dev/plumpcmcia.c

825

plum_conf_write(regt, regh, PLUM_PCMCIA_GENCTRL, reg);

sys/arch/hpcmips/dev/plumpcmcia.c

845

plumreg_t reg;

sys/arch/hpcmips/dev/plumpcmcia.c

853

reg = plum_conf_read(regt, regh, PLUM_PCMCIA_GLOBALCTRL);

sys/arch/hpcmips/dev/plumpcmcia.c

854

reg &= ~PLUM_PCMCIA_GLOBALCTRL_EXPLICIT_WB_CSC_INT;

sys/arch/hpcmips/dev/plumpcmcia.c

855

plum_conf_write(regt, regh, PLUM_PCMCIA_GLOBALCTRL, reg);

sys/arch/hpcmips/dev/plumpcmcia.c

871

plumreg_t reg;

sys/arch/hpcmips/dev/plumpcmcia.c

875

reg = plum_conf_read(regt, regh, PLUM_PCMCIA_CSCINT_STAT);

sys/arch/hpcmips/dev/plumpcmcia.c

876

if (reg & PLUM_PCMCIA_CSCINT_CARD_DETECT) {

sys/arch/hpcmips/dev/plumpcmcia.c

880

__func__, reg);

sys/arch/hpcmips/dev/plumpcmcia.c

885

reg = plum_conf_read(regt, regh, PLUM_PCMCIA_STATUS);

sys/arch/hpcmips/dev/plumpcmcia.c

886

reg &= (PLUM_PCMCIA_STATUS_CD1 | PLUM_PCMCIA_STATUS_CD2);

sys/arch/hpcmips/dev/plumpcmcia.c

887

if (reg == (PLUM_PCMCIA_STATUS_CD1 | PLUM_PCMCIA_STATUS_CD2)) {

sys/arch/hpcmips/dev/plumpcmcia.c

996

__ioareadump(plumreg_t reg)

sys/arch/hpcmips/dev/plumpcmcia.c

999

if (reg & PLUM_PCMCIA_IOWINADDRCTRL_AREA2) {

sys/arch/hpcmips/dev/plumpower.c

268

plumreg_t reg;

sys/arch/hpcmips/dev/plumpower.c

270

reg = plum_conf_read(regt, regh, PLUM_POWER_PWRCONT_REG);

sys/arch/hpcmips/dev/plumpower.c

272

ISPOWERSUPPLY(reg, USBEN);

sys/arch/hpcmips/dev/plumpower.c

273

ISPOWERSUPPLY(reg, IO5OE);

sys/arch/hpcmips/dev/plumpower.c

274

ISPOWERSUPPLY(reg, LCDOE);

sys/arch/hpcmips/dev/plumpower.c

275

ISPOWERSUPPLY(reg, EXTPW2);

sys/arch/hpcmips/dev/plumpower.c

276

ISPOWERSUPPLY(reg, EXTPW1);

sys/arch/hpcmips/dev/plumpower.c

277

ISPOWERSUPPLY(reg, EXTPW0);

sys/arch/hpcmips/dev/plumpower.c

278

ISPOWERSUPPLY(reg, IO5PWR);

sys/arch/hpcmips/dev/plumpower.c

279

ISPOWERSUPPLY(reg, BKLIGHT);

sys/arch/hpcmips/dev/plumpower.c

280

ISPOWERSUPPLY(reg, LCDPWR);

sys/arch/hpcmips/dev/plumpower.c

281

ISPOWERSUPPLY(reg, LCDDSP);

sys/arch/hpcmips/dev/plumpower.c

282

reg = plum_conf_read(regt, regh, PLUM_POWER_CLKCONT_REG);

sys/arch/hpcmips/dev/plumpower.c

284

ISCLOCKSUPPLY(reg, USBCLK2);

sys/arch/hpcmips/dev/plumpower.c

285

ISCLOCKSUPPLY(reg, USBCLK1);

sys/arch/hpcmips/dev/plumpower.c

286

ISCLOCKSUPPLY(reg, IO5CLK);

sys/arch/hpcmips/dev/plumpower.c

287

ISCLOCKSUPPLY(reg, SMCLK);

sys/arch/hpcmips/dev/plumpower.c

288

ISCLOCKSUPPLY(reg, PCCCLK2);

sys/arch/hpcmips/dev/plumpower.c

289

ISCLOCKSUPPLY(reg, PCCCLK1);

sys/arch/hpcmips/dev/plumpower.c

290

reg = plum_conf_read(regt, regh, PLUM_POWER_INPENA_REG);

sys/arch/hpcmips/dev/plumpower.c

292

reg & PLUM_POWER_INPENA ? "en" : "dis");

sys/arch/hpcmips/dev/plumpower.c

293

reg = plum_conf_read(regt, regh, PLUM_POWER_RESETC_REG);

sys/arch/hpcmips/dev/plumpower.c

295

reg & PLUM_POWER_RESETC_IO5CL0 ? "CLRL" : "",

sys/arch/hpcmips/dev/plumpower.c

296

reg & PLUM_POWER_RESETC_IO5CL1 ? "CLRH" : "");

sys/arch/hpcmips/dev/plumvideo.c

310

plumreg_t reg;

sys/arch/hpcmips/dev/plumvideo.c

326

reg = plum_conf_read(regt, regh, PLUM_VIDEO_PLGMD_REG);

sys/arch/hpcmips/dev/plumvideo.c

328

switch (reg & PLUM_VIDEO_PLGMD_GMODE_MASK) {

sys/arch/hpcmips/dev/plumvideo.c

338

reg &= ~PLUM_VIDEO_PLGMD_GMODE_MASK;

sys/arch/hpcmips/dev/plumvideo.c

339

plum_conf_write(regt, regh, PLUM_VIDEO_PLGMD_REG, reg);

sys/arch/hpcmips/dev/plumvideo.c

340

reg |= PLUM_VIDEO_PLGMD_8BPP;

sys/arch/hpcmips/dev/plumvideo.c

341

plum_conf_write(regt, regh, PLUM_VIDEO_PLGMD_REG, reg);

sys/arch/hpcmips/dev/plumvideo.c

400

reg = plum_conf_read(regt, regh, PLUM_VIDEO_PLGMD_REG);

sys/arch/hpcmips/dev/plumvideo.c

855

plumreg_t reg;

sys/arch/hpcmips/dev/plumvideo.c

859

reg = plum_conf_read(regt, regh, i);

sys/arch/hpcmips/dev/plumvideo.c

860

printf("0x%03x %08x", i, reg);

sys/arch/hpcmips/dev/plumvideo.c

861

dbg_bit_print(reg);

sys/arch/hpcmips/dev/teliosio.c

228

txreg_t reg;

sys/arch/hpcmips/dev/teliosio.c

230

reg = tx_conf_read(tc, TX392X_IODATAINOUT_REG);

sys/arch/hpcmips/dev/teliosio.c

231

return (reg & TELIOSIO_AC_STATE) ? APM_AC_OFF : APM_AC_ON;

sys/arch/hpcmips/dev/teliosio.c

253

txreg_t reg;

sys/arch/hpcmips/dev/teliosio.c

259

reg = tx_conf_read(tc, TX392X_IODATAINOUT_REG);

sys/arch/hpcmips/dev/teliosio.c

260

reg |= TELIOSIO_BMU_CLOCK;

sys/arch/hpcmips/dev/teliosio.c

262

reg |= TELIOSIO_BMU_DATAOUT;

sys/arch/hpcmips/dev/teliosio.c

264

reg &= ~TELIOSIO_BMU_DATAOUT;

sys/arch/hpcmips/dev/teliosio.c

265

tx_conf_write(tc, TX392X_IODATAINOUT_REG, reg);

sys/arch/hpcmips/dev/teliosio.c

270

reg = tx_conf_read(tc, TX392X_IODATAINOUT_REG);

sys/arch/hpcmips/dev/teliosio.c

271

reg &= ~TELIOSIO_BMU_CLOCK;

sys/arch/hpcmips/dev/teliosio.c

272

tx_conf_write(tc, TX392X_IODATAINOUT_REG, reg);

sys/arch/hpcmips/dev/teliosio.c

281

txreg_t reg;

sys/arch/hpcmips/dev/teliosio.c

288

reg = tx_conf_read(tc, TX392X_IODATAINOUT_REG);

sys/arch/hpcmips/dev/teliosio.c

289

reg |= TELIOSIO_BMU_CLOCK;

sys/arch/hpcmips/dev/teliosio.c

290

tx_conf_write(tc, TX392X_IODATAINOUT_REG, reg);

sys/arch/hpcmips/dev/teliosio.c

295

reg = tx_conf_read(tc, TX392X_IODATAINOUT_REG);

sys/arch/hpcmips/dev/teliosio.c

296

if (!(reg & TELIOSIO_BMU_DATAIN))

sys/arch/hpcmips/dev/teliosio.c

298

reg &= ~TELIOSIO_BMU_CLOCK;

sys/arch/hpcmips/dev/teliosio.c

299

tx_conf_write(tc, TX392X_IODATAINOUT_REG, reg);

sys/arch/hpcmips/dev/ucb1200.c

103

u_int16_t reg;

sys/arch/hpcmips/dev/ucb1200.c

107

reg = txsibsf0_reg_read(sa->sa_tc, UCB1200_ID_REG);

sys/arch/hpcmips/dev/ucb1200.c

109

return (ucb1200_check_id(reg, 0));

sys/arch/hpcmips/dev/ucb1200.c

117

u_int16_t reg;

sys/arch/hpcmips/dev/ucb1200.c

132

reg = txsibsf0_reg_read(sa->sa_tc, UCB1200_ID_REG);

sys/arch/hpcmips/dev/ucb1200.c

133

(void)ucb1200_check_id(reg, 1);

sys/arch/hpcmips/dev/ucb1200.c

232

u_int16_t reg;

sys/arch/hpcmips/dev/ucb1200.c

239

reg = txsibsf0_reg_read(tc, i);

sys/arch/hpcmips/dev/ucb1200.c

240

printf("%s(%02d) 0x%04x ", regname[i], i, reg);

sys/arch/hpcmips/dev/ucb1200.c

241

dbg_bit_print(reg);

sys/arch/hpcmips/dev/ucbio.c

127

txreg_t reg, pos;

sys/arch/hpcmips/dev/ucbio.c

130

reg = txsibsf0_reg_read(tc, UCB1200_IO_DATA_REG);

sys/arch/hpcmips/dev/ucbio.c

132

reg |= pos;

sys/arch/hpcmips/dev/ucbio.c

134

reg &= ~pos;

sys/arch/hpcmips/dev/ucbio.c

135

txsibsf0_reg_write(tc, UCB1200_IO_DATA_REG, reg);

sys/arch/hpcmips/dev/ucbio.c

143

txreg_t reg = txsibsf0_reg_read(tc, UCB1200_IO_DATA_REG);

sys/arch/hpcmips/dev/ucbio.c

145

return (reg & (1 << port));

sys/arch/hpcmips/dev/ucbsnd.c

247

txreg_t reg;

sys/arch/hpcmips/dev/ucbsnd.c

271

reg = TX39_SIBSF0_WRITE;

sys/arch/hpcmips/dev/ucbsnd.c

272

reg = TX39_SIBSF0_REGADDR_SET(reg, UCB1200_AUDIOCTRLA_REG);

sys/arch/hpcmips/dev/ucbsnd.c

273

reg = TX39_SIBSF0_REGDATA_SET(reg, sc->sa_snd_rate);

sys/arch/hpcmips/dev/ucbsnd.c

274

tx_conf_write(tc, TX39_SIBSF0CTRL_REG, reg);

sys/arch/hpcmips/dev/ucbsnd.c

281

reg = TX39_SIBSF0_WRITE;

sys/arch/hpcmips/dev/ucbsnd.c

282

reg = TX39_SIBSF0_REGADDR_SET(reg, UCB1200_AUDIOCTRLB_REG);

sys/arch/hpcmips/dev/ucbsnd.c

283

reg = TX39_SIBSF0_REGDATA_SET(reg, sc->sa_snd_attenuation |

sys/arch/hpcmips/dev/ucbsnd.c

285

tx_conf_write(tc, TX39_SIBSF0CTRL_REG, reg);

sys/arch/hpcmips/dev/ucbsnd.c

288

reg = tx_conf_read(tc, TX39_SIBCTRL_REG);

sys/arch/hpcmips/dev/ucbsnd.c

290

reg | TX39_SIBCTRL_ENSND);

sys/arch/hpcmips/dev/ucbsnd.c

298

reg = TX39_SIBSF0_REGADDR_SET(0, UCB1200_IO_DATA_REG);

sys/arch/hpcmips/dev/ucbsnd.c

299

tx_conf_write(tc, TX39_SIBSF0CTRL_REG, reg);

sys/arch/hpcmips/dev/ucbsnd.c

305

reg = tx_conf_read(tc, TX39_SIBSF0STAT_REG);

sys/arch/hpcmips/dev/ucbsnd.c

306

if ((TX39_SIBSF0_REGADDR(reg) != UCB1200_IO_DATA_REG) &&

sys/arch/hpcmips/dev/ucbsnd.c

320

reg |= TX39_SIBSF0_WRITE;

sys/arch/hpcmips/dev/ucbsnd.c

321

reg |= UCB1200_IO_DATA_SPEAKER;

sys/arch/hpcmips/dev/ucbsnd.c

322

tx_conf_write(tc, TX39_SIBSF0CTRL_REG, reg);

sys/arch/hpcmips/dev/ucbsnd.c

372

reg = tx_conf_read(tc, TX39_SIBDMACTRL_REG);

sys/arch/hpcmips/dev/ucbsnd.c

373

reg |= TX39_SIBDMACTRL_ENDMATXSND;

sys/arch/hpcmips/dev/ucbsnd.c

374

tx_conf_write(tc, TX39_SIBDMACTRL_REG, reg);

sys/arch/hpcmips/dev/ucbsnd.c

425

reg = TX39_SIBSF0_WRITE;

sys/arch/hpcmips/dev/ucbsnd.c

426

reg = TX39_SIBSF0_REGADDR_SET(reg, UCB1200_AUDIOCTRLB_REG);

sys/arch/hpcmips/dev/ucbsnd.c

427

reg = TX39_SIBSF0_REGDATA_SET(reg, UCB1200_AUDIOCTRLB_MUTE);

sys/arch/hpcmips/dev/ucbsnd.c

428

tx_conf_write(tc, TX39_SIBSF0CTRL_REG, reg);

sys/arch/hpcmips/dev/ucbsnd.c

436

reg = TX39_SIBSF0_REGADDR_SET(0, UCB1200_IO_DATA_REG);

sys/arch/hpcmips/dev/ucbsnd.c

437

tx_conf_write(tc, TX39_SIBSF0CTRL_REG, reg);

sys/arch/hpcmips/dev/ucbsnd.c

443

reg = tx_conf_read(tc, TX39_SIBSF0STAT_REG);

sys/arch/hpcmips/dev/ucbsnd.c

444

if ((TX39_SIBSF0_REGADDR(reg) != UCB1200_IO_DATA_REG) &&

sys/arch/hpcmips/dev/ucbsnd.c

458

reg |= TX39_SIBSF0_WRITE;

sys/arch/hpcmips/dev/ucbsnd.c

459

reg &= ~UCB1200_IO_DATA_SPEAKER;

sys/arch/hpcmips/dev/ucbsnd.c

460

tx_conf_write(tc, TX39_SIBSF0CTRL_REG, reg);

sys/arch/hpcmips/dev/ucbsnd.c

467

reg = tx_conf_read(tc, TX39_SIBCTRL_REG);

sys/arch/hpcmips/dev/ucbsnd.c

468

reg &= ~TX39_SIBCTRL_ENSND;

sys/arch/hpcmips/dev/ucbsnd.c

469

tx_conf_write(tc, TX39_SIBCTRL_REG, reg);

sys/arch/hpcmips/dev/ucbtp.c

371

#define REGWRITE(addr, reg, ret) ( \

sys/arch/hpcmips/dev/ucbtp.c

373

sc->sm_reg = (reg), \

sys/arch/hpcmips/dev/ucbtp.c

386

txreg_t reg;

sys/arch/hpcmips/dev/ucbtp.c

572

reg = TX39_SIBSF0_REGADDR_SET(0, sc->sm_addr);

sys/arch/hpcmips/dev/ucbtp.c

573

tx_conf_write(tc, TX39_SIBSF0CTRL_REG, reg);

sys/arch/hpcmips/dev/ucbtp.c

578

reg = tx_conf_read(tc, TX39_SIBSF0STAT_REG);

sys/arch/hpcmips/dev/ucbtp.c

579

if ((TX39_SIBSF0_REGADDR(reg) != sc->sm_addr) &&

sys/arch/hpcmips/dev/ucbtp.c

588

sc->sm_reg = reg;

sys/arch/hpcmips/dev/ucbtp.c

590

DPRINTFN(9, "%08x\n", reg);

sys/arch/hpcmips/dev/ucbtp.c

619

reg = sc->sm_reg;

sys/arch/hpcmips/dev/ucbtp.c

620

reg |= TX39_SIBSF0_WRITE;

sys/arch/hpcmips/dev/ucbtp.c

621

TX39_SIBSF0_REGDATA_CLR(reg);

sys/arch/hpcmips/dev/ucbtp.c

622

reg = TX39_SIBSF0_REGDATA_SET(reg, sc->sm_write_val);

sys/arch/hpcmips/dev/ucbtp.c

623

tx_conf_write(tc, TX39_SIBSF0CTRL_REG, reg);

sys/arch/hpcmips/isa/isa_machdep.c

291

u_int8_t reg;

sys/arch/hpcmips/isa/isa_machdep.c

298

reg = *((volatile u_int8_t *)(addr + 1));

sys/arch/hpcmips/isa/isa_machdep.c

300

if (reg == 0x82 || reg == 0x83) {

sys/arch/hpcmips/isa/isa_machdep.c

302

if ((reg & 0xc0) == 0x80) {

sys/arch/hpcmips/stand/lcboot/extern.h

79

#define __REG_1(reg) *((volatile u_int8_t*) (reg))

sys/arch/hpcmips/stand/lcboot/extern.h

80

#define __REG_2(reg) *((volatile u_int16_t*) (reg))

sys/arch/hpcmips/stand/lcboot/extern.h

81

#define __REG_4(reg) *((volatile u_int32_t*) (reg))

sys/arch/hpcmips/stand/pbsdboot/tx39xx.c

51

tx_conf_read(tx_chipset_tag_t t, int reg)

sys/arch/hpcmips/stand/pbsdboot/tx39xx.c

53

return *((u_int32_t*)(__tx39conf_addr + reg));

sys/arch/hpcmips/stand/pbsdboot/tx39xx.c

57

tx_conf_write(tx_chipset_tag_t t, int reg, u_int32_t val)

sys/arch/hpcmips/stand/pbsdboot/tx39xx.c

60

*((u_int32_t*)(__tx39conf_addr +reg)) = val;

sys/arch/hpcmips/tx/tx3912video.c

302

txreg_t reg;

sys/arch/hpcmips/tx/tx3912video.c

308

reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG);

sys/arch/hpcmips/tx/tx3912video.c

309

fbdepth = 1 << (TX3912_VIDEOCTRL1_BITSEL(reg));

sys/arch/hpcmips/tx/tx3912video.c

319

reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG);

sys/arch/hpcmips/tx/tx3912video.c

320

TX3912_VIDEOCTRL1_BITSEL_CLR(reg);

sys/arch/hpcmips/tx/tx3912video.c

321

reg = TX3912_VIDEOCTRL1_BITSEL_SET(reg,

sys/arch/hpcmips/tx/tx3912video.c

323

tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg);

sys/arch/hpcmips/tx/tx3912video.c

398

txreg_t reg;

sys/arch/hpcmips/tx/tx3912video.c

406

reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG);

sys/arch/hpcmips/tx/tx3912video.c

407

reg &= ~TX3912_VIDEOCTRL1_DFMODE;

sys/arch/hpcmips/tx/tx3912video.c

408

tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg);

sys/arch/hpcmips/tx/tx3912video.c

414

reg = TX3912_VIDEOCTRL3_VIDBANK_SET(0, bank);

sys/arch/hpcmips/tx/tx3912video.c

416

reg = TX3912_VIDEOCTRL3_VIDBASEHI_SET(reg, base);

sys/arch/hpcmips/tx/tx3912video.c

417

tx_conf_write(tc, TX3912_VIDEOCTRL3_REG, reg);

sys/arch/hpcmips/tx/tx3912video.c

421

reg = TX3912_VIDEOCTRL4_VIDBASELO_SET(0, base);

sys/arch/hpcmips/tx/tx3912video.c

424

reg = TX3912_VIDEOCTRL4_DFVAL_SET(reg, 0); /* XXX not yet*/

sys/arch/hpcmips/tx/tx3912video.c

428

tx_conf_write(tc, TX3912_VIDEOCTRL4_REG, reg);

sys/arch/hpcmips/tx/tx3912video.c

440

txreg_t reg;

sys/arch/hpcmips/tx/tx3912video.c

445

reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG);

sys/arch/hpcmips/tx/tx3912video.c

446

split = reg & TX3912_VIDEOCTRL1_DISPSPLIT;

sys/arch/hpcmips/tx/tx3912video.c

447

val = TX3912_VIDEOCTRL1_BITSEL(reg);

sys/arch/hpcmips/tx/tx3912video.c

461

reg = TX3912_VIDEOCTRL2_VIDRATE_SET(0, horzval + 1);

sys/arch/hpcmips/tx/tx3912video.c

463

reg = TX3912_VIDEOCTRL2_HORZVAL_SET(reg, horzval);

sys/arch/hpcmips/tx/tx3912video.c

465

reg = TX3912_VIDEOCTRL2_LINEVAL_SET(reg, lineval);

sys/arch/hpcmips/tx/tx3912video.c

467

tx_conf_write(tc, TX3912_VIDEOCTRL2_REG, reg);

sys/arch/hpcmips/tx/tx3912video.c

474

txreg_t reg;

sys/arch/hpcmips/tx/tx3912video.c

476

reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG);

sys/arch/hpcmips/tx/tx3912video.c

479

reg |= TX3912_VIDEOCTRL1_ENFREEZEFRAME;

sys/arch/hpcmips/tx/tx3912video.c

480

tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg);

sys/arch/hpcmips/tx/tx3912video.c

486

reg &= ~TX3912_VIDEOCTRL1_ENVID;

sys/arch/hpcmips/tx/tx3912video.c

487

tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg);

sys/arch/hpcmips/tx/tx3912video.c

492

reg &= ~TX3912_VIDEOCTRL1_ENFREEZEFRAME;

sys/arch/hpcmips/tx/tx3912video.c

493

reg |= TX3912_VIDEOCTRL1_ENVID;

sys/arch/hpcmips/tx/tx3912video.c

494

tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg);

sys/arch/hpcmips/tx/tx39biu.c

101

reg = tx_conf_read(tc, TX39_MEMCONFIG4_REG);

sys/arch/hpcmips/tx/tx39biu.c

102

reg |= TX39_MEMCONFIG4_ENWATCH;

sys/arch/hpcmips/tx/tx39biu.c

103

reg = TX39_MEMCONFIG4_WATCHTIMEVAL_SET(reg, 0xf);

sys/arch/hpcmips/tx/tx39biu.c

104

tx_conf_write(tc, TX39_MEMCONFIG4_REG, reg);

sys/arch/hpcmips/tx/tx39biu.c

106

reg = tx_conf_read(tc, TX39_MEMCONFIG4_REG);

sys/arch/hpcmips/tx/tx39biu.c

107

if (reg & TX39_MEMCONFIG4_ENWATCH) {

sys/arch/hpcmips/tx/tx39biu.c

109

i = TX39_MEMCONFIG4_WATCHTIMEVAL(reg);

sys/arch/hpcmips/tx/tx39biu.c

147

txreg_t reg;

sys/arch/hpcmips/tx/tx39biu.c

154

reg = tx_conf_read(tc, TX39_MEMCONFIG4_REG);

sys/arch/hpcmips/tx/tx39biu.c

155

reg |= TX39_MEMCONFIG4_CLRWRBUSERRINT;

sys/arch/hpcmips/tx/tx39biu.c

156

tx_conf_write(tc, TX39_MEMCONFIG4_REG, reg);

sys/arch/hpcmips/tx/tx39biu.c

157

reg = tx_conf_read(tc, TX39_MEMCONFIG4_REG);

sys/arch/hpcmips/tx/tx39biu.c

158

reg &= ~TX39_MEMCONFIG4_CLRWRBUSERRINT;

sys/arch/hpcmips/tx/tx39biu.c

159

tx_conf_write(tc, TX39_MEMCONFIG4_REG, reg);

sys/arch/hpcmips/tx/tx39biu.c

174

txreg_t reg;

sys/arch/hpcmips/tx/tx39biu.c

179

reg = tx_conf_read(tc, TX39_MEMCONFIG0_REG);

sys/arch/hpcmips/tx/tx39biu.c

181

ISSETPRINT(reg, 0, ENDCLKOUTTRI);

sys/arch/hpcmips/tx/tx39biu.c

182

ISSETPRINT(reg, 0, DISDQMINIT);

sys/arch/hpcmips/tx/tx39biu.c

183

ISSETPRINT(reg, 0, ENSDRAMPD);

sys/arch/hpcmips/tx/tx39biu.c

184

ISSETPRINT(reg, 0, SHOWDINO);

sys/arch/hpcmips/tx/tx39biu.c

185

ISSETPRINT(reg, 0, ENRMAP2);

sys/arch/hpcmips/tx/tx39biu.c

186

ISSETPRINT(reg, 0, ENRMAP1);

sys/arch/hpcmips/tx/tx39biu.c

187

ISSETPRINT(reg, 0, ENWRINPAGE);

sys/arch/hpcmips/tx/tx39biu.c

188

ISSETPRINT(reg, 0, ENCS3USER);

sys/arch/hpcmips/tx/tx39biu.c

189

ISSETPRINT(reg, 0, ENCS2USER);

sys/arch/hpcmips/tx/tx39biu.c

190

ISSETPRINT(reg, 0, ENCS1USER);

sys/arch/hpcmips/tx/tx39biu.c

191

ISSETPRINT(reg, 0, ENCS1DRAM);

sys/arch/hpcmips/tx/tx39biu.c

192

ISSETPRINT(reg, 0, CS3SIZE);

sys/arch/hpcmips/tx/tx39biu.c

193

ISSETPRINT(reg, 0, CS2SIZE);

sys/arch/hpcmips/tx/tx39biu.c

194

ISSETPRINT(reg, 0, CS1SIZE);

sys/arch/hpcmips/tx/tx39biu.c

195

ISSETPRINT(reg, 0, CS0SIZE);

sys/arch/hpcmips/tx/tx39biu.c

200

switch (i ? TX39_MEMCONFIG0_BANK1CONF(reg)

sys/arch/hpcmips/tx/tx39biu.c

201

: TX39_MEMCONFIG0_BANK0CONF(reg)) {

sys/arch/hpcmips/tx/tx39biu.c

216

r = TX39_MEMCONFIG0_ROWSEL1(reg);

sys/arch/hpcmips/tx/tx39biu.c

217

c = TX39_MEMCONFIG0_COLSEL1(reg);

sys/arch/hpcmips/tx/tx39biu.c

219

r = TX39_MEMCONFIG0_ROWSEL0(reg);

sys/arch/hpcmips/tx/tx39biu.c

220

c = TX39_MEMCONFIG0_COLSEL0(reg);

sys/arch/hpcmips/tx/tx39biu.c

229

reg = tx_conf_read(tc, TX39_MEMCONFIG3_REG);

sys/arch/hpcmips/tx/tx39biu.c

231

ISSETPRINT(reg, 3, ENMCS3PAGE);

sys/arch/hpcmips/tx/tx39biu.c

232

ISSETPRINT(reg, 3, ENMCS2PAGE);

sys/arch/hpcmips/tx/tx39biu.c

233

ISSETPRINT(reg, 3, ENMCS1PAGE);

sys/arch/hpcmips/tx/tx39biu.c

234

ISSETPRINT(reg, 3, ENMCS0PAGE);

sys/arch/hpcmips/tx/tx39biu.c

236

ISSETPRINT(reg, 3, ENCS3PAGE);

sys/arch/hpcmips/tx/tx39biu.c

237

ISSETPRINT(reg, 3, ENCS2PAGE);

sys/arch/hpcmips/tx/tx39biu.c

238

ISSETPRINT(reg, 3, ENCS1PAGE);

sys/arch/hpcmips/tx/tx39biu.c

239

ISSETPRINT(reg, 3, ENCS0PAGE);

sys/arch/hpcmips/tx/tx39biu.c

240

ISSETPRINT(reg, 3, CARD2WAITEN);

sys/arch/hpcmips/tx/tx39biu.c

241

ISSETPRINT(reg, 3, CARD1WAITEN);

sys/arch/hpcmips/tx/tx39biu.c

242

ISSETPRINT(reg, 3, CARD2IOEN);

sys/arch/hpcmips/tx/tx39biu.c

243

ISSETPRINT(reg, 3, CARD1IOEN);

sys/arch/hpcmips/tx/tx39biu.c

245

ISSETPRINT(reg, 3, PORT8SEL);

sys/arch/hpcmips/tx/tx39biu.c

248

ISSETPRINT(reg, 3, CARD2_8SEL);

sys/arch/hpcmips/tx/tx39biu.c

249

ISSETPRINT(reg, 3, CARD1_8SEL);

sys/arch/hpcmips/tx/tx39biu.c

257

reg = tx_conf_read(tc, TX39_MEMCONFIG4_REG);

sys/arch/hpcmips/tx/tx39biu.c

259

ISSETPRINT(reg, 4, ENBANK1HDRAM);

sys/arch/hpcmips/tx/tx39biu.c

260

ISSETPRINT(reg, 4, ENBANK0HDRAM);

sys/arch/hpcmips/tx/tx39biu.c

261

ISSETPRINT(reg, 4, ENARB);

sys/arch/hpcmips/tx/tx39biu.c

262

ISSETPRINT(reg, 4, DISSNOOP);

sys/arch/hpcmips/tx/tx39biu.c

263

ISSETPRINT(reg, 4, CLRWRBUSERRINT);

sys/arch/hpcmips/tx/tx39biu.c

264

ISSETPRINT(reg, 4, ENBANK1OPT);

sys/arch/hpcmips/tx/tx39biu.c

265

ISSETPRINT(reg, 4, ENBANK0OPT);

sys/arch/hpcmips/tx/tx39biu.c

266

ISSETPRINT(reg, 4, ENWATCH);

sys/arch/hpcmips/tx/tx39biu.c

267

ISSETPRINT(reg, 4, MEMPOWERDOWN);

sys/arch/hpcmips/tx/tx39biu.c

268

ISSETPRINT(reg, 4, ENRFSH1);

sys/arch/hpcmips/tx/tx39biu.c

269

ISSETPRINT(reg, 4, ENRFSH0);

sys/arch/hpcmips/tx/tx39biu.c

270

if (reg & TX39_MEMCONFIG4_ENWATCH) {

sys/arch/hpcmips/tx/tx39biu.c

271

i = TX39_MEMCONFIG4_WATCHTIMEVAL(reg);

sys/arch/hpcmips/tx/tx39biu.c

88

txreg_t reg;

sys/arch/hpcmips/tx/tx39clock.c

114

txreg_t reg;

sys/arch/hpcmips/tx/tx39clock.c

123

reg = tx_conf_read(tc, TX39_TIMERCONTROL_REG);

sys/arch/hpcmips/tx/tx39clock.c

124

reg |= TX39_TIMERCONTROL_ENPERTIMER;

sys/arch/hpcmips/tx/tx39clock.c

125

tx_conf_write(tc, TX39_TIMERCONTROL_REG, reg);

sys/arch/hpcmips/tx/tx39clock.c

178

txreg_t reg;

sys/arch/hpcmips/tx/tx39clock.c

180

reg = tx_conf_read(tc, TX39_TIMERCONTROL_REG);

sys/arch/hpcmips/tx/tx39clock.c

183

reg |= TX39_TIMERCONTROL_FREEZEPRE; /* Upper 8bit */

sys/arch/hpcmips/tx/tx39clock.c

184

reg |= TX39_TIMERCONTROL_FREEZERTC; /* Lower 32bit */

sys/arch/hpcmips/tx/tx39clock.c

187

reg |= TX39_TIMERCONTROL_FREEZETIMER;

sys/arch/hpcmips/tx/tx39clock.c

188

reg &= ~TX39_TIMERCONTROL_ENPERTIMER;

sys/arch/hpcmips/tx/tx39clock.c

189

tx_conf_write(tc, TX39_TIMERCONTROL_REG, reg);

sys/arch/hpcmips/tx/tx39clock.c

222

txreg_t reg;

sys/arch/hpcmips/tx/tx39clock.c

224

reg = tx_conf_read(tc, TX39_TIMERCONTROL_REG);

sys/arch/hpcmips/tx/tx39clock.c

227

reg |= TX39_TIMERCONTROL_RTCCLR;

sys/arch/hpcmips/tx/tx39clock.c

228

tx_conf_write(tc, TX39_TIMERCONTROL_REG, reg);

sys/arch/hpcmips/tx/tx39clock.c

231

reg &= ~TX39_TIMERCONTROL_RTCCLR;

sys/arch/hpcmips/tx/tx39clock.c

232

tx_conf_write(tc, TX39_TIMERCONTROL_REG, reg);

sys/arch/hpcmips/tx/tx39clock.c

254

txreg_t reg;

sys/arch/hpcmips/tx/tx39clock.c

261

reg = tx_conf_read(tc, TX39_TIMERPERIODIC_REG);

sys/arch/hpcmips/tx/tx39clock.c

262

TX39_TIMERPERIODIC_PERVAL_CLR(reg);

sys/arch/hpcmips/tx/tx39clock.c

263

reg = TX39_TIMERPERIODIC_PERVAL_SET(reg, pcnt);

sys/arch/hpcmips/tx/tx39clock.c

264

tx_conf_write(tc, TX39_TIMERPERIODIC_REG, reg);

sys/arch/hpcmips/tx/tx39clock.c

269

reg = tx_conf_read(tc, TX39_INTRENABLE6_REG);

sys/arch/hpcmips/tx/tx39clock.c

270

reg |= TX39_INTRPRI13_TIMER_PERIODIC_BIT;

sys/arch/hpcmips/tx/tx39clock.c

271

tx_conf_write(tc, TX39_INTRENABLE6_REG, reg);

sys/arch/hpcmips/tx/tx39clock.c

316

txreg_t reg;

sys/arch/hpcmips/tx/tx39clock.c

318

reg = tx_conf_read(tc, TX39_CLOCKCTRL_REG);

sys/arch/hpcmips/tx/tx39clock.c

321

ISSETPRINT(reg, CHIM);

sys/arch/hpcmips/tx/tx39clock.c

323

ISSETPRINT(reg, VID);

sys/arch/hpcmips/tx/tx39clock.c

324

ISSETPRINT(reg, MBUS);

sys/arch/hpcmips/tx/tx39clock.c

327

ISSETPRINT(reg, IRDA);

sys/arch/hpcmips/tx/tx39clock.c

329

ISSETPRINT(reg, SPI);

sys/arch/hpcmips/tx/tx39clock.c

330

ISSETPRINT(reg, TIMER);

sys/arch/hpcmips/tx/tx39clock.c

331

ISSETPRINT(reg, FASTTIMER);

sys/arch/hpcmips/tx/tx39clock.c

333

ISSETPRINT(reg, C48MOUT);

sys/arch/hpcmips/tx/tx39clock.c

335

ISSETPRINT(reg, SIBM);

sys/arch/hpcmips/tx/tx39clock.c

336

ISSETPRINT(reg, CSER);

sys/arch/hpcmips/tx/tx39clock.c

337

ISSETPRINT(reg, IR);

sys/arch/hpcmips/tx/tx39clock.c

338

ISSETPRINT(reg, UARTA);

sys/arch/hpcmips/tx/tx39clock.c

339

ISSETPRINT(reg, UARTB);

sys/arch/hpcmips/tx/tx39icu.c

227

txreg_t reg, *regs;

sys/arch/hpcmips/tx/tx39icu.c

264

reg = tx_conf_read(tc, TX39_INTRENABLE6_REG);

sys/arch/hpcmips/tx/tx39icu.c

265

reg &= ~TX39_INTRENABLE6_PRIORITYMASK_MASK;

sys/arch/hpcmips/tx/tx39icu.c

266

tx_conf_write(tc, TX39_INTRENABLE6_REG, reg);

sys/arch/hpcmips/tx/tx39icu.c

288

reg = tx_conf_read(tc, TX39_INTRENABLE6_REG);

sys/arch/hpcmips/tx/tx39icu.c

289

reg |= TX39_INTRENABLE6_GLOBALEN;

sys/arch/hpcmips/tx/tx39icu.c

290

tx_conf_write(tc, TX39_INTRENABLE6_REG, reg);

sys/arch/hpcmips/tx/tx39icu.c

312

txreg_t reg, pend, *regs;

sys/arch/hpcmips/tx/tx39icu.c

359

reg = sc->sc_le_mask[i] & pend;

sys/arch/hpcmips/tx/tx39icu.c

361

tx_conf_write(tc, ofs, reg);

sys/arch/hpcmips/tx/tx39icu.c

364

if ((reg & (1 << j)) &&

sys/arch/hpcmips/tx/tx39icu.c

380

pend &= ~reg;

sys/arch/hpcmips/tx/tx39icu.c

414

reg = tx_conf_read(tc, TX39_INTRENABLE6_REG);

sys/arch/hpcmips/tx/tx39icu.c

415

reg = TX39_INTRENABLE6_PRIORITYMASK_SET(reg, 0xffff);

sys/arch/hpcmips/tx/tx39icu.c

416

tx_conf_write(tc, TX39_INTRENABLE6_REG, reg);

sys/arch/hpcmips/tx/tx39icu.c

504

txreg_t reg;

sys/arch/hpcmips/tx/tx39icu.c

519

reg = tx_conf_read(tc, TX39_INTRENABLE6_REG);

sys/arch/hpcmips/tx/tx39icu.c

520

reg = TX39_INTRENABLE6_PRIORITYMASK_SET(reg, (1 << pri));

sys/arch/hpcmips/tx/tx39icu.c

521

tx_conf_write(tc, TX39_INTRENABLE6_REG, reg);

sys/arch/hpcmips/tx/tx39icu.c

529

txreg_t reg;

sys/arch/hpcmips/tx/tx39icu.c

541

reg = tx_conf_read(tc, TX39_INTRENABLE6_REG);

sys/arch/hpcmips/tx/tx39icu.c

542

reg &= ~(1 << pri);

sys/arch/hpcmips/tx/tx39icu.c

543

tx_conf_write(tc, TX39_INTRENABLE6_REG, reg);

sys/arch/hpcmips/tx/tx39icu.c

553

txreg_t reg;

sys/arch/hpcmips/tx/tx39icu.c

573

reg = tx_conf_read(tc, ofs);

sys/arch/hpcmips/tx/tx39icu.c

574

reg |= (1 << bit);

sys/arch/hpcmips/tx/tx39icu.c

575

tx_conf_write(tc, ofs, reg);

sys/arch/hpcmips/tx/tx39icu.c

587

txreg_t reg;

sys/arch/hpcmips/tx/tx39icu.c

602

reg = tx_conf_read(tc, ofs);

sys/arch/hpcmips/tx/tx39icu.c

603

reg &= ~(1 << bit);

sys/arch/hpcmips/tx/tx39icu.c

604

tx_conf_write(tc, ofs, reg);

sys/arch/hpcmips/tx/tx39icu.c

727

txreg_t reg;

sys/arch/hpcmips/tx/tx39icu.c

735

for (reg = j = 0; j < 32; j++) {

sys/arch/hpcmips/tx/tx39icu.c

737

reg |= (1 << j);

sys/arch/hpcmips/tx/tx39icu.c

741

dbg_bit_print_msg(reg, msg);

sys/arch/hpcmips/tx/tx39icu.c

745

reg = tx_conf_read(tc, ofs);

sys/arch/hpcmips/tx/tx39icu.c

747

dbg_bit_print_msg(reg, msg);

sys/arch/hpcmips/tx/tx39icu.c

749

reg = sc->sc_regs[0];

sys/arch/hpcmips/tx/tx39icu.c

751

reg & TX39_INTRSTATUS6_IRQHIGH ? "HI" : "--",

sys/arch/hpcmips/tx/tx39icu.c

752

reg & TX39_INTRSTATUS6_IRQLOW ? "LO" : "--",

sys/arch/hpcmips/tx/tx39icu.c

753

TX39_INTRSTATUS6_INTVECT(reg));

sys/arch/hpcmips/tx/tx39icu.c

754

reg = tx_conf_read(tc, TX39_INTRENABLE6_REG);

sys/arch/hpcmips/tx/tx39icu.c

755

__dbg_bit_print(reg, sizeof(reg), 0, 18, "6 enable",

sys/arch/hpcmips/tx/tx39io.c

218

txreg_t reg, pos;

sys/arch/hpcmips/tx/tx39io.c

230

reg = tx_conf_read(tc, TX39_IOMFIODATAOUT_REG);

sys/arch/hpcmips/tx/tx39io.c

232

reg |= pos;

sys/arch/hpcmips/tx/tx39io.c

234

reg &= ~pos;

sys/arch/hpcmips/tx/tx39io.c

235

tx_conf_write(tc, TX39_IOMFIODATAOUT_REG, reg);

sys/arch/hpcmips/tx/tx39io.c

287

txreg_t reg = tx_conf_read(sc->sc_tc, TX39_IOCTRL_REG);

sys/arch/hpcmips/tx/tx39io.c

290

return (TX391X_IOCTRL_IODIN(reg) & (1 << port));

sys/arch/hpcmips/tx/tx39io.c

298

txreg_t reg, pos, iostat;

sys/arch/hpcmips/tx/tx39io.c

312

reg = tx_conf_read(tc, TX39_IOCTRL_REG);

sys/arch/hpcmips/tx/tx39io.c

313

iostat = TX391X_IOCTRL_IODOUT(reg);

sys/arch/hpcmips/tx/tx39io.c

318

TX391X_IOCTRL_IODOUT_CLR(reg);

sys/arch/hpcmips/tx/tx39io.c

319

reg = TX391X_IOCTRL_IODOUT_SET(reg, iostat);

sys/arch/hpcmips/tx/tx39io.c

320

tx_conf_write(tc, TX39_IOCTRL_REG, reg);

sys/arch/hpcmips/tx/tx39io.c

329

txreg_t reg;

sys/arch/hpcmips/tx/tx39io.c

333

reg = tx_conf_read(tc, TX39_IOCTRL_REG);

sys/arch/hpcmips/tx/tx39io.c

334

stat_io->dir = TX391X_IOCTRL_IODIREC(reg);

sys/arch/hpcmips/tx/tx39io.c

335

stat_io->in = TX391X_IOCTRL_IODIN(reg);

sys/arch/hpcmips/tx/tx39io.c

336

stat_io->out = TX391X_IOCTRL_IODOUT(reg);

sys/arch/hpcmips/tx/tx39io.c

337

stat_io->u.debounce = TX391X_IOCTRL_IODEBSEL(reg);

sys/arch/hpcmips/tx/tx39io.c

338

reg = tx_conf_read(tc, TX39_IOIOPOWERDWN_REG);

sys/arch/hpcmips/tx/tx39io.c

339

stat_io->power = TX391X_IOIOPOWERDWN_IOPD(reg);

sys/arch/hpcmips/tx/tx39io.c

368

txreg_t reg = tx_conf_read(sc->sc_tc, TX392X_IODATAINOUT_REG);

sys/arch/hpcmips/tx/tx39io.c

372

return (TX392X_IODATAINOUT_DIN(reg) & (1 << port));

sys/arch/hpcmips/tx/tx39io.c

383

txreg_t reg, pos, iostat;

sys/arch/hpcmips/tx/tx39io.c

392

reg = tx_conf_read(tc, TX392X_IODATAINOUT_REG);

sys/arch/hpcmips/tx/tx39io.c

393

iostat = TX392X_IODATAINOUT_DOUT(reg);

sys/arch/hpcmips/tx/tx39io.c

398

TX392X_IODATAINOUT_DOUT_CLR(reg);

sys/arch/hpcmips/tx/tx39io.c

399

reg = TX392X_IODATAINOUT_DOUT_SET(reg, iostat);

sys/arch/hpcmips/tx/tx39io.c

400

tx_conf_write(tc, TX392X_IODATAINOUT_REG, reg);

sys/arch/hpcmips/tx/tx39io.c

426

txreg_t reg;

sys/arch/hpcmips/tx/tx39io.c

430

reg = tx_conf_read(tc, TX39_IOCTRL_REG);

sys/arch/hpcmips/tx/tx39io.c

431

stat_io->dir = TX392X_IOCTRL_IODIREC(reg);

sys/arch/hpcmips/tx/tx39io.c

432

stat_io->u.debounce = TX392X_IOCTRL_IODEBSEL(reg);

sys/arch/hpcmips/tx/tx39io.c

433

reg = tx_conf_read(tc, TX392X_IODATAINOUT_REG);

sys/arch/hpcmips/tx/tx39io.c

434

stat_io->in = TX392X_IODATAINOUT_DIN(reg);

sys/arch/hpcmips/tx/tx39io.c

435

stat_io->out = TX392X_IODATAINOUT_DOUT(reg);

sys/arch/hpcmips/tx/tx39io.c

436

reg = tx_conf_read(tc, TX39_IOIOPOWERDWN_REG);

sys/arch/hpcmips/tx/tx39io.c

437

stat_io->power = TX392X_IOIOPOWERDWN_IOPD(reg);

sys/arch/hpcmips/tx/tx39ir.c

102

reg = tx_conf_read(tc, TX39_CLOCKCTRL_REG);

sys/arch/hpcmips/tx/tx39ir.c

103

reg |= TX39_CLOCK_ENIRCLK | TX39_CLOCK_ENUARTBCLK;

sys/arch/hpcmips/tx/tx39ir.c

104

tx_conf_write(tc, TX39_CLOCKCTRL_REG, reg);

sys/arch/hpcmips/tx/tx39ir.c

128

txreg_t reg;

sys/arch/hpcmips/tx/tx39ir.c

130

reg = tx_conf_read(tc, TX39_IRCTRL1_REG);

sys/arch/hpcmips/tx/tx39ir.c

133

ISSETPRINT(reg, CARDET);

sys/arch/hpcmips/tx/tx39ir.c

134

ISSETPRINT(reg, TESTIR);

sys/arch/hpcmips/tx/tx39ir.c

135

ISSETPRINT(reg, DTINVERT);

sys/arch/hpcmips/tx/tx39ir.c

136

ISSETPRINT(reg, RXPWR);

sys/arch/hpcmips/tx/tx39ir.c

137

ISSETPRINT(reg, ENSTATE);

sys/arch/hpcmips/tx/tx39ir.c

138

ISSETPRINT(reg, ENCOMSM);

sys/arch/hpcmips/tx/tx39ir.c

140

printf("baudval %d\n", TX39_IRCTRL1_BAUDVAL(reg));

sys/arch/hpcmips/tx/tx39ir.c

89

txreg_t reg;

sys/arch/hpcmips/tx/tx39ir.c

97

reg = tx_conf_read(tc, TX39_IRCTRL1_REG);

sys/arch/hpcmips/tx/tx39ir.c

98

reg |= TX39_IRCTRL1_RXPWR;

sys/arch/hpcmips/tx/tx39ir.c

99

tx_conf_write(tc, TX39_IRCTRL1_REG, reg);

sys/arch/hpcmips/tx/tx39power.c

101

txreg_t reg;

sys/arch/hpcmips/tx/tx39power.c

111

reg = tx_conf_read(tc, TX39_POWERCTRL_REG);

sys/arch/hpcmips/tx/tx39power.c

112

reg |= TX39_POWERCTRL_DBNCONBUTN;

sys/arch/hpcmips/tx/tx39power.c

113

tx_conf_write(tc, TX39_POWERCTRL_REG, reg);

sys/arch/hpcmips/tx/tx39power.c

116

reg = tx_conf_read(tc, TX39_POWERCTRL_REG);

sys/arch/hpcmips/tx/tx39power.c

117

reg &= ~(TX39_POWERCTRL_STPTIMERVAL_MASK <<

sys/arch/hpcmips/tx/tx39power.c

119

reg = TX39_POWERCTRL_STPTIMERVAL_SET(reg,

sys/arch/hpcmips/tx/tx39power.c

121

reg |= TX39_POWERCTRL_ENSTPTIMER;

sys/arch/hpcmips/tx/tx39power.c

122

tx_conf_write(tc, TX39_POWERCTRL_REG, reg);

sys/arch/hpcmips/tx/tx39power.c

153

txreg_t reg, *iregs = sc->sc_icu_state;

sys/arch/hpcmips/tx/tx39power.c

157

reg = tx_conf_read(tc, TX39_POWERCTRL_REG);

sys/arch/hpcmips/tx/tx39power.c

158

reg |= TX39_POWERCTRL_STOPCPU;

sys/arch/hpcmips/tx/tx39power.c

187

tx_conf_write(tc, TX39_POWERCTRL_REG, reg);

sys/arch/hpcmips/tx/tx39power.c

194

reg = tx_conf_read(tc, TX39_POWERCTRL_REG);

sys/arch/hpcmips/tx/tx39power.c

195

reg &= ~TX39_POWERCTRL_WARMSTART;

sys/arch/hpcmips/tx/tx39power.c

196

tx_conf_write(tc, TX39_POWERCTRL_REG, reg);

sys/arch/hpcmips/tx/tx39power.c

283

txreg_t reg;

sys/arch/hpcmips/tx/tx39power.c

285

reg = tx_conf_read(tc, TX39_POWERCTRL_REG);

sys/arch/hpcmips/tx/tx39power.c

286

ISSETPRINT(reg, ONBUTN);

sys/arch/hpcmips/tx/tx39power.c

287

ISSETPRINT(reg, PWRINT);

sys/arch/hpcmips/tx/tx39power.c

288

ISSETPRINT(reg, PWROK);

sys/arch/hpcmips/tx/tx39power.c

290

ISSETPRINT(reg, PWROKNMI);

sys/arch/hpcmips/tx/tx39power.c

292

ISSETPRINT(reg, SLOWBUS);

sys/arch/hpcmips/tx/tx39power.c

294

ISSETPRINT(reg, DIVMOD);

sys/arch/hpcmips/tx/tx39power.c

296

ISSETPRINT(reg, ENSTPTIMER);

sys/arch/hpcmips/tx/tx39power.c

297

ISSETPRINT(reg, ENFORCESHUTDWN);

sys/arch/hpcmips/tx/tx39power.c

298

ISSETPRINT(reg, FORCESHUTDWN);

sys/arch/hpcmips/tx/tx39power.c

299

ISSETPRINT(reg, FORCESHUTDWNOCC);

sys/arch/hpcmips/tx/tx39power.c

300

ISSETPRINT(reg, SELC2MS);

sys/arch/hpcmips/tx/tx39power.c

302

ISSETPRINT(reg, WARMSTART);

sys/arch/hpcmips/tx/tx39power.c

304

ISSETPRINT(reg, BPDBVCC3);

sys/arch/hpcmips/tx/tx39power.c

305

ISSETPRINT(reg, STOPCPU);

sys/arch/hpcmips/tx/tx39power.c

306

ISSETPRINT(reg, DBNCONBUTN);

sys/arch/hpcmips/tx/tx39power.c

307

ISSETPRINT(reg, COLDSTART);

sys/arch/hpcmips/tx/tx39power.c

308

ISSETPRINT(reg, PWRCS);

sys/arch/hpcmips/tx/tx39power.c

309

ISSETPRINT(reg, VCCON);

sys/arch/hpcmips/tx/tx39power.c

311

printf("VIDRF=%d ", TX39_POWERCTRL_VIDRF(reg));

sys/arch/hpcmips/tx/tx39power.c

313

printf("STPTIMERVAL=%d ", TX39_POWERCTRL_STPTIMERVAL(reg));

sys/arch/hpcmips/tx/tx39sib.c

188

txreg_t reg;

sys/arch/hpcmips/tx/tx39sib.c

194

reg = 0;

sys/arch/hpcmips/tx/tx39sib.c

196

reg = TX39_SIBCTRL_SCLKDIV_SET(reg, param->sp_clock);

sys/arch/hpcmips/tx/tx39sib.c

198

reg = TX39_SIBCTRL_SNDFSDIV_SET(reg, param->sp_snd_rate - 1);

sys/arch/hpcmips/tx/tx39sib.c

200

reg = TX39_SIBCTRL_TELFSDIV_SET(reg, param->sp_tel_rate - 1);

sys/arch/hpcmips/tx/tx39sib.c

202

reg |= param->sp_sf0sndmode;

sys/arch/hpcmips/tx/tx39sib.c

203

reg |= param->sp_sf0telmode;

sys/arch/hpcmips/tx/tx39sib.c

204

tx_conf_write(tc, TX39_SIBCTRL_REG, reg);

sys/arch/hpcmips/tx/tx39sib.c

207

reg = tx_conf_read(tc, TX39_SIBDMACTRL_REG);

sys/arch/hpcmips/tx/tx39sib.c

208

reg &= ~(TX39_SIBDMACTRL_ENDMARXSND |

sys/arch/hpcmips/tx/tx39sib.c

212

tx_conf_write(tc, TX39_SIBDMACTRL_REG, reg);

sys/arch/hpcmips/tx/tx39sib.c

217

reg = tx_conf_read(tc, TX39_SIBCTRL_REG);

sys/arch/hpcmips/tx/tx39sib.c

218

reg |= TX39_SIBCTRL_ENSF0;

sys/arch/hpcmips/tx/tx39sib.c

219

tx_conf_write(tc, TX39_SIBCTRL_REG, reg);

sys/arch/hpcmips/tx/tx39sib.c

227

txreg_t reg;

sys/arch/hpcmips/tx/tx39sib.c

229

reg = tx_conf_read(tc, TX39_SIBCTRL_REG);

sys/arch/hpcmips/tx/tx39sib.c

230

reg |= TX39_SIBCTRL_ENSIB;

sys/arch/hpcmips/tx/tx39sib.c

231

tx_conf_write(tc, TX39_SIBCTRL_REG, reg);

sys/arch/hpcmips/tx/tx39sib.c

239

txreg_t reg;

sys/arch/hpcmips/tx/tx39sib.c

244

reg = tx_conf_read(tc, TX39_SIBCTRL_REG);

sys/arch/hpcmips/tx/tx39sib.c

245

reg &= ~(TX39_SIBCTRL_ENTEL | TX39_SIBCTRL_ENSND);

sys/arch/hpcmips/tx/tx39sib.c

246

tx_conf_write(tc, TX39_SIBCTRL_REG, reg);

sys/arch/hpcmips/tx/tx39sib.c

251

reg = tx_conf_read(tc, TX39_SIBCTRL_REG);

sys/arch/hpcmips/tx/tx39sib.c

252

reg &= ~TX39_SIBCTRL_ENSF0;

sys/arch/hpcmips/tx/tx39sib.c

253

reg &= ~(TX39_SIBCTRL_ENSF1 | TX39_SIBCTRL_SELTELSF1 |

sys/arch/hpcmips/tx/tx39sib.c

255

tx_conf_write(tc, TX39_SIBCTRL_REG, reg);

sys/arch/hpcmips/tx/tx39sib.c

258

reg &= ~TX39_SIBCTRL_ENSIB;

sys/arch/hpcmips/tx/tx39sib.c

259

tx_conf_write(tc, TX39_SIBCTRL_REG, reg);

sys/arch/hpcmips/tx/tx39sib.c

333

txreg_t reg;

sys/arch/hpcmips/tx/tx39sib.c

335

reg = txsibsf0_read(tc, addr);

sys/arch/hpcmips/tx/tx39sib.c

336

reg |= TX39_SIBSF0_WRITE;

sys/arch/hpcmips/tx/tx39sib.c

337

TX39_SIBSF0_REGDATA_CLR(reg);

sys/arch/hpcmips/tx/tx39sib.c

338

reg = TX39_SIBSF0_REGDATA_SET(reg, val);

sys/arch/hpcmips/tx/tx39sib.c

341

tx_conf_write(tc, TX39_SIBSF0CTRL_REG, reg);

sys/arch/hpcmips/tx/tx39sib.c

353

txreg_t reg;

sys/arch/hpcmips/tx/tx39sib.c

357

reg = TX39_SIBSF0_REGADDR_SET(0, addr);

sys/arch/hpcmips/tx/tx39sib.c

359

tx_conf_write(tc, TX39_SIBSF0CTRL_REG, reg);

sys/arch/hpcmips/tx/tx39sib.c

362

reg = tx_conf_read(tc, TX39_SIBSF0STAT_REG);

sys/arch/hpcmips/tx/tx39sib.c

364

} while ((TX39_SIBSF0_REGADDR(reg) != addr) && --retry > 0);

sys/arch/hpcmips/tx/tx39sib.c

369

return (reg);

sys/arch/hpcmips/tx/tx39sib.c

382

txreg_t reg;

sys/arch/hpcmips/tx/tx39sib.c

384

reg = tx_conf_read(tc, TX39_SIBCTRL_REG);

sys/arch/hpcmips/tx/tx39sib.c

385

ISSETPRINT_CTRL(reg, SIBIRQ);

sys/arch/hpcmips/tx/tx39sib.c

386

ISSETPRINT_CTRL(reg, ENCNTTEST);

sys/arch/hpcmips/tx/tx39sib.c

387

ISSETPRINT_CTRL(reg, ENDMATEST);

sys/arch/hpcmips/tx/tx39sib.c

388

ISSETPRINT_CTRL(reg, SNDMONO);

sys/arch/hpcmips/tx/tx39sib.c

389

ISSETPRINT_CTRL(reg, RMONOSNDIN);

sys/arch/hpcmips/tx/tx39sib.c

390

ISSETPRINT_CTRL(reg, TEL16);

sys/arch/hpcmips/tx/tx39sib.c

391

ISSETPRINT_CTRL(reg, SND16);

sys/arch/hpcmips/tx/tx39sib.c

392

ISSETPRINT_CTRL(reg, SELTELSF1);

sys/arch/hpcmips/tx/tx39sib.c

393

ISSETPRINT_CTRL(reg, SELSNDSF1);

sys/arch/hpcmips/tx/tx39sib.c

394

ISSETPRINT_CTRL(reg, ENTEL);

sys/arch/hpcmips/tx/tx39sib.c

395

ISSETPRINT_CTRL(reg, ENSND);

sys/arch/hpcmips/tx/tx39sib.c

396

ISSETPRINT_CTRL(reg, SIBLOOP);

sys/arch/hpcmips/tx/tx39sib.c

397

ISSETPRINT_CTRL(reg, ENSF1);

sys/arch/hpcmips/tx/tx39sib.c

398

ISSETPRINT_CTRL(reg, ENSF0);

sys/arch/hpcmips/tx/tx39sib.c

399

ISSETPRINT_CTRL(reg, ENSIB);

sys/arch/hpcmips/tx/tx39sib.c

401

printf("SCLKDIV %d\n", TX39_SIBCTRL_SCLKDIV(reg));

sys/arch/hpcmips/tx/tx39sib.c

402

printf("TELFSDIV %d\n", TX39_SIBCTRL_TELFSDIV(reg));

sys/arch/hpcmips/tx/tx39sib.c

403

printf("SNDFSDIV %d\n", TX39_SIBCTRL_SNDFSDIV(reg));

sys/arch/hpcmips/tx/tx39sib.c

405

reg = tx_conf_read(tc, TX39_SIBDMACTRL_REG);

sys/arch/hpcmips/tx/tx39sib.c

406

ISSETPRINT_DMACTRL(reg, SNDBUFF1TIME);

sys/arch/hpcmips/tx/tx39sib.c

407

ISSETPRINT_DMACTRL(reg, SNDDMALOOP);

sys/arch/hpcmips/tx/tx39sib.c

408

ISSETPRINT_DMACTRL(reg, ENDMARXSND);

sys/arch/hpcmips/tx/tx39sib.c

409

ISSETPRINT_DMACTRL(reg, ENDMATXSND);

sys/arch/hpcmips/tx/tx39sib.c

410

ISSETPRINT_DMACTRL(reg, TELBUFF1TIME);

sys/arch/hpcmips/tx/tx39sib.c

411

ISSETPRINT_DMACTRL(reg, TELDMALOOP);

sys/arch/hpcmips/tx/tx39sib.c

412

ISSETPRINT_DMACTRL(reg, ENDMARXTEL);

sys/arch/hpcmips/tx/tx39sib.c

413

ISSETPRINT_DMACTRL(reg, ENDMATXTEL);

sys/arch/hpcmips/tx/tx39sib.c

415

printf("SNDDMAPTR %d\n", TX39_SIBDMACTRL_TELDMAPTR(reg));

sys/arch/hpcmips/tx/tx39sib.c

416

printf("TELDMAPTR %d\n", TX39_SIBDMACTRL_SNDDMAPTR(reg));

sys/arch/hpcmips/tx/tx39spi.c

169

txreg_t reg = tx_conf_read(tc, TX39_SPICTRL_REG);

sys/arch/hpcmips/tx/tx39spi.c

171

reg |= (TX39_SPICTRL_ENSPI);

sys/arch/hpcmips/tx/tx39spi.c

173

reg &= ~(TX39_SPICTRL_ENSPI);

sys/arch/hpcmips/tx/tx39spi.c

174

tx_conf_write(tc, TX39_SPICTRL_REG, reg);

sys/arch/hpcmips/tx/tx39spi.c

181

txreg_t reg = tx_conf_read(tc, TX39_SPICTRL_REG);

sys/arch/hpcmips/tx/tx39spi.c

182

tx_conf_write(tc, TX39_SPICTRL_REG, TX39_SPICTRL_DELAYVAL_SET(reg, n));

sys/arch/hpcmips/tx/tx39spi.c

189

txreg_t reg = tx_conf_read(tc, TX39_SPICTRL_REG);

sys/arch/hpcmips/tx/tx39spi.c

190

tx_conf_write(tc, TX39_SPICTRL_REG, TX39_SPICTRL_BAUDRATE_SET(reg, n));

sys/arch/hpcmips/tx/tx39spi.c

197

txreg_t reg = tx_conf_read(tc, TX39_SPICTRL_REG);

sys/arch/hpcmips/tx/tx39spi.c

199

reg |= (TX39_SPICTRL_WORD);

sys/arch/hpcmips/tx/tx39spi.c

201

reg &= ~(TX39_SPICTRL_WORD);

sys/arch/hpcmips/tx/tx39spi.c

202

tx_conf_write(tc, TX39_SPICTRL_REG, reg);

sys/arch/hpcmips/tx/tx39spi.c

209

txreg_t reg = tx_conf_read(tc, TX39_SPICTRL_REG);

sys/arch/hpcmips/tx/tx39spi.c

211

reg |= (TX39_SPICTRL_PHAPOL);

sys/arch/hpcmips/tx/tx39spi.c

213

reg &= ~(TX39_SPICTRL_PHAPOL);

sys/arch/hpcmips/tx/tx39spi.c

214

tx_conf_write(tc, TX39_SPICTRL_REG, reg);

sys/arch/hpcmips/tx/tx39spi.c

221

txreg_t reg = tx_conf_read(tc, TX39_SPICTRL_REG);

sys/arch/hpcmips/tx/tx39spi.c

223

reg |= (TX39_SPICTRL_CLKPOL);

sys/arch/hpcmips/tx/tx39spi.c

225

reg &= ~(TX39_SPICTRL_CLKPOL);

sys/arch/hpcmips/tx/tx39spi.c

226

tx_conf_write(tc, TX39_SPICTRL_REG, reg);

sys/arch/hpcmips/tx/tx39spi.c

233

txreg_t reg = tx_conf_read(tc, TX39_SPICTRL_REG);

sys/arch/hpcmips/tx/tx39spi.c

235

reg |= (TX39_SPICTRL_LSB);

sys/arch/hpcmips/tx/tx39spi.c

237

reg &= ~(TX39_SPICTRL_LSB);

sys/arch/hpcmips/tx/tx39spi.c

238

tx_conf_write(tc, TX39_SPICTRL_REG, reg);

sys/arch/hpcmips/tx/tx39spi.c

74

txreg_t reg;

sys/arch/hpcmips/tx/tx39spi.c

76

reg = tx_conf_read(tc, TX39_SPICTRL_REG);

sys/arch/hpcmips/tx/tx39spi.c

77

reg &= ~(TX39_SPICTRL_ENSPI);

sys/arch/hpcmips/tx/tx39spi.c

78

tx_conf_write(tc, TX39_SPICTRL_REG, reg);

sys/arch/hpcmips/tx/tx39var.h

95

#define tx_conf_read(t, reg) ( \

sys/arch/hpcmips/tx/tx39var.h

96

(*((volatile txreg_t *)(TX39_SYSADDR_CONFIG_REG_KSEG1 + (reg)))))

sys/arch/hpcmips/tx/tx39var.h

97

#define tx_conf_write(t, reg, val) ( \

sys/arch/hpcmips/tx/tx39var.h

98

(*((volatile txreg_t *)(TX39_SYSADDR_CONFIG_REG_KSEG1 + (reg))) \

sys/arch/hpcmips/tx/txcom.c

1191

txreg_t reg;

sys/arch/hpcmips/tx/txcom.c

1193

reg = tx_conf_read(tc, TX39_UARTCTRL1_REG(slot));

sys/arch/hpcmips/tx/txcom.c

1196

ISSETPRINT(reg, UARTON);

sys/arch/hpcmips/tx/txcom.c

1197

ISSETPRINT(reg, EMPTY);

sys/arch/hpcmips/tx/txcom.c

1198

ISSETPRINT(reg, PRXHOLDFULL);

sys/arch/hpcmips/tx/txcom.c

1199

ISSETPRINT(reg, RXHOLDFULL);

sys/arch/hpcmips/tx/txcom.c

1200

ISSETPRINT(reg, ENDMARX);

sys/arch/hpcmips/tx/txcom.c

1201

ISSETPRINT(reg, ENDMATX);

sys/arch/hpcmips/tx/txcom.c

1202

ISSETPRINT(reg, TESTMODE);

sys/arch/hpcmips/tx/txcom.c

1203

ISSETPRINT(reg, ENBREAHALT);

sys/arch/hpcmips/tx/txcom.c

1204

ISSETPRINT(reg, ENDMATEST);

sys/arch/hpcmips/tx/txcom.c

1205

ISSETPRINT(reg, ENDMALOOP);

sys/arch/hpcmips/tx/txcom.c

1206

ISSETPRINT(reg, PULSEOPT2);

sys/arch/hpcmips/tx/txcom.c

1207

ISSETPRINT(reg, PULSEOPT1);

sys/arch/hpcmips/tx/txcom.c

1208

ISSETPRINT(reg, DTINVERT);

sys/arch/hpcmips/tx/txcom.c

1209

ISSETPRINT(reg, DISTXD);

sys/arch/hpcmips/tx/txcom.c

1210

ISSETPRINT(reg, TWOSTOP);

sys/arch/hpcmips/tx/txcom.c

1211

ISSETPRINT(reg, LOOPBACK);

sys/arch/hpcmips/tx/txcom.c

1212

ISSETPRINT(reg, BIT7);

sys/arch/hpcmips/tx/txcom.c

1213

ISSETPRINT(reg, EVENPARITY);

sys/arch/hpcmips/tx/txcom.c

1214

ISSETPRINT(reg, ENPARITY);

sys/arch/hpcmips/tx/txcom.c

1215

ISSETPRINT(reg, ENUART);

sys/arch/hpcmips/tx/txcom.c

311

txreg_t reg;

sys/arch/hpcmips/tx/txcom.c

318

reg = tx_conf_read(tc, TX39_CLOCKCTRL_REG);

sys/arch/hpcmips/tx/txcom.c

319

reg |= (slot ? TX39_CLOCK_ENUARTBCLK : TX39_CLOCK_ENUARTACLK);

sys/arch/hpcmips/tx/txcom.c

320

tx_conf_write(tc, TX39_CLOCKCTRL_REG, reg);

sys/arch/hpcmips/tx/txcom.c

330

txreg_t reg;

sys/arch/hpcmips/tx/txcom.c

348

reg = tx_conf_read(tc, TX39_CLOCKCTRL_REG);

sys/arch/hpcmips/tx/txcom.c

349

reg |= (slot ? TX39_CLOCK_ENUARTBCLK : TX39_CLOCK_ENUARTACLK);

sys/arch/hpcmips/tx/txcom.c

350

tx_conf_write(tc, TX39_CLOCKCTRL_REG, reg);

sys/arch/hpcmips/tx/txcom.c

355

reg = tx_conf_read(tc, ofs);

sys/arch/hpcmips/tx/txcom.c

356

reg &= ~(TX39_UARTCTRL1_ENDMARX | TX39_UARTCTRL1_ENDMATX);

sys/arch/hpcmips/tx/txcom.c

357

tx_conf_write(tc, ofs, reg);

sys/arch/hpcmips/tx/txcom.c

360

reg = tx_conf_read(tc, ofs);

sys/arch/hpcmips/tx/txcom.c

361

reg |= TX39_UARTCTRL1_ENUART;

sys/arch/hpcmips/tx/txcom.c

362

reg &= ~TX39_UARTCTRL1_ENBREAHALT;

sys/arch/hpcmips/tx/txcom.c

363

tx_conf_write(tc, ofs, reg);

sys/arch/hpcmips/tx/txcom.c

383

txreg_t reg;

sys/arch/hpcmips/tx/txcom.c

389

reg = tx_conf_read(tc, TX39_UARTCTRL1_REG(slot));

sys/arch/hpcmips/tx/txcom.c

391

reg &= ~(TX39_UARTCTRL1_ENDMARX | TX39_UARTCTRL1_ENDMATX);

sys/arch/hpcmips/tx/txcom.c

394

reg &= ~TX39_UARTCTRL1_ENUART;

sys/arch/hpcmips/tx/txcom.c

395

tx_conf_write(tc, TX39_UARTCTRL1_REG(slot), reg);

sys/arch/hpcmips/tx/txcom.c

398

reg = tx_conf_read(tc, TX39_CLOCKCTRL_REG);

sys/arch/hpcmips/tx/txcom.c

399

reg &= ~(slot ? TX39_CLOCK_ENUARTBCLK : TX39_CLOCK_ENUARTACLK);

sys/arch/hpcmips/tx/txcom.c

400

tx_conf_write(tc, TX39_CLOCKCTRL_REG, reg);

sys/arch/hpcmips/tx/txcom.c

425

txreg_t reg;

sys/arch/hpcmips/tx/txcom.c

429

reg = tx_conf_read(tc, ofs);

sys/arch/hpcmips/tx/txcom.c

431

reg |= TX39_UARTCTRL1_PULSEOPT1;

sys/arch/hpcmips/tx/txcom.c

432

reg &= ~TX39_UARTCTRL1_PULSEOPT2;

sys/arch/hpcmips/tx/txcom.c

433

reg |= TX39_UARTCTRL1_DTINVERT;

sys/arch/hpcmips/tx/txcom.c

435

tx_conf_write(tc, ofs, reg);

sys/arch/hpcmips/tx/txcom.c

496

txreg_t reg;

sys/arch/hpcmips/tx/txcom.c

498

reg = tx_conf_read(chip->sc_tc, ofs);

sys/arch/hpcmips/tx/txcom.c

499

reg &= ~TX39_UARTCTRL1_ENUART;

sys/arch/hpcmips/tx/txcom.c

500

tx_conf_write(chip->sc_tc, ofs, reg);

sys/arch/hpcmips/tx/txcom.c

507

reg |= TX39_UARTCTRL1_BIT7;

sys/arch/hpcmips/tx/txcom.c

510

reg &= ~TX39_UARTCTRL1_BIT7;

sys/arch/hpcmips/tx/txcom.c

515

reg |= TX39_UARTCTRL1_ENPARITY;

sys/arch/hpcmips/tx/txcom.c

517

reg &= ~TX39_UARTCTRL1_EVENPARITY;

sys/arch/hpcmips/tx/txcom.c

519

reg |= TX39_UARTCTRL1_EVENPARITY;

sys/arch/hpcmips/tx/txcom.c

522

reg &= ~TX39_UARTCTRL1_ENPARITY;

sys/arch/hpcmips/tx/txcom.c

526

reg |= TX39_UARTCTRL1_TWOSTOP;

sys/arch/hpcmips/tx/txcom.c

528

reg &= ~TX39_UARTCTRL1_TWOSTOP;

sys/arch/hpcmips/tx/txcom.c

530

reg |= TX39_UARTCTRL1_ENUART;

sys/arch/hpcmips/tx/txcom.c

531

tx_conf_write(chip->sc_tc, ofs, reg);

sys/arch/hpcmips/tx/txcom.c

539

txreg_t reg, reg1;

sys/arch/hpcmips/tx/txcom.c

552

reg = TX39_UARTCTRL2_BAUDRATE_SET(0, baudrate);

sys/arch/hpcmips/tx/txcom.c

554

tx_conf_write(chip->sc_tc, TX39_UARTCTRL2_REG(chip->sc_slot), reg);

sys/arch/hpcmips/tx/txcom.c

600

txreg_t reg;

sys/arch/hpcmips/tx/txcom.c

609

reg = tx_conf_read(tc, TX39_UARTCTRL1_REG(slot));

sys/arch/hpcmips/tx/txcom.c

610

reg &= ~TX39_UARTCTRL1_ENUART;

sys/arch/hpcmips/tx/txcom.c

611

tx_conf_write(tc, TX39_UARTCTRL1_REG(slot), reg);

sys/arch/hpcmips/tx/txcom.c

614

reg &= ~TX39_UARTCTRL1_DISTXD;

sys/arch/hpcmips/tx/txcom.c

616

reg |= TX39_UARTCTRL1_DISTXD; /* low UARTTXD */

sys/arch/hpcmips/tx/txcom.c

619

reg |= TX39_UARTCTRL1_ENUART;

sys/arch/hpcmips/tx/txcom.c

620

tx_conf_write(tc, TX39_UARTCTRL1_REG(slot), reg);

sys/arch/hpcmips/tx/txcsbus.c

254

txreg_t reg;

sys/arch/hpcmips/tx/txcsbus.c

278

reg = tx_conf_read(tc, TX39_MEMCONFIG0_REG);

sys/arch/hpcmips/tx/txcsbus.c

279

reg |= (1 << cs);

sys/arch/hpcmips/tx/txcsbus.c

280

tx_conf_write(tc, TX39_MEMCONFIG0_REG, reg);

sys/arch/hpcmips/tx/txcsbus.c

286

reg = tx_conf_read(tc, TX39_MEMCONFIG1_REG);

sys/arch/hpcmips/tx/txcsbus.c

287

reg |= ((cs == TX39_MCS0) ?

sys/arch/hpcmips/tx/txcsbus.c

290

tx_conf_write(tc, TX39_MEMCONFIG1_REG, reg);

sys/arch/hpcmips/tx/txcsbus.c

297

reg = tx_conf_read(tc, TX39_MEMCONFIG0_REG);

sys/arch/hpcmips/tx/txcsbus.c

298

reg &= ~(1 << cs);

sys/arch/hpcmips/tx/txcsbus.c

299

tx_conf_write(tc, TX39_MEMCONFIG0_REG, reg);

sys/arch/hpcmips/tx/txcsbus.c

303

reg = tx_conf_read(tc, TX39_MEMCONFIG1_REG);

sys/arch/hpcmips/tx/txcsbus.c

304

reg &= ~((cs == TX39_MCS0) ?

sys/arch/hpcmips/tx/txcsbus.c

307

tx_conf_write(tc, TX39_MEMCONFIG1_REG, reg);

sys/arch/hpcmips/tx/txcsbus.c

311

reg = tx_conf_read(tc, TX39_MEMCONFIG3_REG);

sys/arch/hpcmips/tx/txcsbus.c

314

reg |= (cs == TX39_CARD1) ?

sys/arch/hpcmips/tx/txcsbus.c

319

reg &= ~((cs == TX39_CARD1) ?

sys/arch/hpcmips/tx/txcsbus.c

324

reg &= ~TX39_MEMCONFIG3_PORT8SEL;

sys/arch/hpcmips/tx/txcsbus.c

326

tx_conf_write(tc, TX39_MEMCONFIG3_REG, reg);

sys/arch/hpcmips/tx/txcsbus.c

332

reg = tx_conf_read(tc, TX39_MEMCONFIG3_REG);

sys/arch/hpcmips/tx/txcsbus.c

335

reg |= (cs == TX39_CARD1) ?

sys/arch/hpcmips/tx/txcsbus.c

340

reg |= (cs == TX39_CARD1) ?

sys/arch/hpcmips/tx/txcsbus.c

345

reg |= TX39_MEMCONFIG3_PORT8SEL;

sys/arch/hpcmips/tx/txcsbus.c

347

tx_conf_write(tc, TX39_MEMCONFIG3_REG, reg);

sys/arch/hpcmips/vr/bcu_vrip.c

155

int reg;

sys/arch/hpcmips/vr/bcu_vrip.c

271

reg = vrbcu_read(sc, BCUCNT1_REG_W);

sys/arch/hpcmips/vr/bcu_vrip.c

272

printf("vrbcu: CNT1 %x: ", reg);

sys/arch/hpcmips/vr/bcu_vrip.c

273

dbg_bit_print(reg);

sys/arch/hpcmips/vr/bcu_vrip.c

278

reg = vrbcu_read(sc, BCUCNT2_REG_W);

sys/arch/hpcmips/vr/bcu_vrip.c

279

printf("vrbcu: CNT2 %x: ", reg);

sys/arch/hpcmips/vr/bcu_vrip.c

280

dbg_bit_print(reg);

sys/arch/hpcmips/vr/bcu_vrip.c

287

reg = vrbcu_read(sc, BCUSPEED_REG_W);

sys/arch/hpcmips/vr/bcu_vrip.c

288

printf("vrbcu: SPEED %x: ", reg);

sys/arch/hpcmips/vr/bcu_vrip.c

289

dbg_bit_print(reg);

sys/arch/hpcmips/vr/bcu_vrip.c

290

reg = vrbcu_read(sc, BCUERRST_REG_W);

sys/arch/hpcmips/vr/bcu_vrip.c

291

printf("vrbcu: ERRST %x: ", reg);

sys/arch/hpcmips/vr/bcu_vrip.c

292

dbg_bit_print(reg);

sys/arch/hpcmips/vr/bcu_vrip.c

293

reg = vrbcu_read(sc, BCURFCNT_REG_W);

sys/arch/hpcmips/vr/bcu_vrip.c

294

printf("vrbcu: RFCNT %x\n", reg);

sys/arch/hpcmips/vr/bcu_vrip.c

295

reg = vrbcu_read(sc, BCUREFCOUNT_REG_W);

sys/arch/hpcmips/vr/bcu_vrip.c

296

printf("vrbcu: RFCOUNT %x\n", reg);

sys/arch/hpcmips/vr/bcu_vrip.c

304

reg = vrbcu_read(sc, BCUCNT3_REG_W);

sys/arch/hpcmips/vr/bcu_vrip.c

305

printf("vrbcu: CNT3 %x: ", reg);

sys/arch/hpcmips/vr/bcu_vrip.c

306

dbg_bit_print(reg);

sys/arch/hpcmips/vr/cmu.c

110

u_int16_t reg;

sys/arch/hpcmips/vr/cmu.c

112

reg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, 0);

sys/arch/hpcmips/vr/cmu.c

115

dbg_bit_print(reg);

sys/arch/hpcmips/vr/cmu.c

118

reg |= mask;

sys/arch/hpcmips/vr/cmu.c

120

reg &= ~mask;

sys/arch/hpcmips/vr/cmu.c

121

bus_space_write_2(sc->sc_iot, sc->sc_ioh, 0, reg);

sys/arch/hpcmips/vr/cmu.c

124

dbg_bit_print(reg);

sys/arch/hpcmips/vr/vraiu.c

368

uint32_t reg;

sys/arch/hpcmips/vr/vraiu.c

376

vrip_intr_getstatus2(sc->sc_vrip, sc->sc_handler, &reg);

sys/arch/hpcmips/vr/vraiu.c

377

if (reg & AIUINT_INTSEND) {

sys/arch/hpcmips/vr/vrc4172gpio.c

484

u_int32_t reg, mask, mask2;

sys/arch/hpcmips/vr/vrc4172gpio.c

519

reg = read_4(sc, VRC2_EXGPDIR);

sys/arch/hpcmips/vr/vrc4172gpio.c

520

reg &= ~mask;

sys/arch/hpcmips/vr/vrc4172gpio.c

521

write_4(sc, VRC2_EXGPDIR, reg);

sys/arch/hpcmips/vr/vrc4172gpio.c

524

reg = read_4(sc, VRC2_EXGPINTTYP);

sys/arch/hpcmips/vr/vrc4172gpio.c

526

reg |= mask; /* edge */

sys/arch/hpcmips/vr/vrc4172gpio.c

528

reg &= ~mask; /* level */

sys/arch/hpcmips/vr/vrc4172gpio.c

529

write_4(sc, VRC2_EXGPINTTYP, reg);

sys/arch/hpcmips/vr/vrc4172gpio.c

532

reg = read_4(sc, intlv_reg);

sys/arch/hpcmips/vr/vrc4172gpio.c

536

reg &= ~(mask2 << 8);

sys/arch/hpcmips/vr/vrc4172gpio.c

537

reg |= mask2;

sys/arch/hpcmips/vr/vrc4172gpio.c

540

reg &= ~(mask2 << 8);

sys/arch/hpcmips/vr/vrc4172gpio.c

541

reg &= ~mask2;

sys/arch/hpcmips/vr/vrc4172gpio.c

545

reg |= (mask2 << 8);

sys/arch/hpcmips/vr/vrc4172gpio.c

550

reg |= mask2; /* high */

sys/arch/hpcmips/vr/vrc4172gpio.c

552

reg &= ~mask2; /* low */

sys/arch/hpcmips/vr/vrc4172gpio.c

554

write_4(sc, intlv_reg, reg);

sys/arch/hpcmips/vr/vrc4172gpio.c

632

u_int32_t reg;

sys/arch/hpcmips/vr/vrc4172gpio.c

635

reg = read_4(sc, VRC2_EXGPINTST);

sys/arch/hpcmips/vr/vrc4172gpio.c

636

DPRINTF(DBG_INTR, "%s: EXGPINTST=%06x\n", __func__, reg);

sys/arch/hpcmips/vr/vrc4172gpio.c

638

if (reg & (1 << i)) {

sys/arch/hpcmips/vr/vrc4172pci.c

259

vrc4172pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg)

sys/arch/hpcmips/vr/vrc4172pci.c

264

if ((unsigned int)reg >= PCI_CONF_SIZE)

sys/arch/hpcmips/vr/vrc4172pci.c

270

reg == PCI_MAPREG_START) {

sys/arch/hpcmips/vr/vrc4172pci.c

278

vrc4172pci_write(sc, VRC4172PCI_CONFAREG, tag | reg);

sys/arch/hpcmips/vr/vrc4172pci.c

285

device_xname(sc->sc_dev), (u_int32_t)tag, reg, val));

sys/arch/hpcmips/vr/vrc4172pci.c

291

vrc4172pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg,

sys/arch/hpcmips/vr/vrc4172pci.c

297

device_xname(sc->sc_dev), (u_int32_t)tag, reg, (u_int32_t)data));

sys/arch/hpcmips/vr/vrc4172pci.c

299

if ((unsigned int)reg >= PCI_CONF_SIZE)

sys/arch/hpcmips/vr/vrc4172pci.c

305

reg == PCI_MAPREG_START) {

sys/arch/hpcmips/vr/vrc4172pci.c

313

vrc4172pci_write(sc, VRC4172PCI_CONFAREG, tag | reg);

sys/arch/hpcmips/vr/vrc4173bcu.c

253

u_int16_t reg;

sys/arch/hpcmips/vr/vrc4173bcu.c

326

reg = bus_space_read_2(sc->sc_iot, sc->sc_cmuh,

sys/arch/hpcmips/vr/vrc4173bcu.c

329

device_xname(self), reg);

sys/arch/hpcmips/vr/vrc4173bcu.c

343

reg = bus_space_read_2(sc->sc_iot, sc->sc_icuh, VRC4173ICU_SYSINT1);

sys/arch/hpcmips/vr/vrc4173bcu.c

346

"\11GIU\12AC97\13AC97-1\14B11\15B12\16DOZEPIU\17B14\20B15", reg);

sys/arch/hpcmips/vr/vrc4173bcu.c

349

reg = bus_space_read_2(sc->sc_iot, sc->sc_icuh, VRC4173ICU_MKIUINT);

sys/arch/hpcmips/vr/vrc4173bcu.c

352

"\11B8\12B9\13B10\14B11\15B12\16B13\17B14\20B15", reg);

sys/arch/hpcmips/vr/vrc4173bcu.c

355

reg = bus_space_read_2(sc->sc_iot, sc->sc_icuh, VRC4173ICU_MSYSINT1);

sys/arch/hpcmips/vr/vrc4173bcu.c

358

"\11GIU\12AC97\13AC97-1\14B11\15B12\16DOZEPIU\17B14\20B15", reg);

sys/arch/hpcmips/vr/vrc4173bcu.c

362

reg = VRC4173ICU_USBINTR | VRC4173ICU_PIUINTR | VRC4173ICU_KIUINTR |

sys/arch/hpcmips/vr/vrc4173bcu.c

364

bus_space_write_2(sc->sc_iot, sc->sc_icuh, VRC4173ICU_MSYSINT1, reg);

sys/arch/hpcmips/vr/vrc4173bcu.c

366

reg = bus_space_read_2(sc->sc_iot, sc->sc_icuh, VRC4173ICU_MSYSINT1);

sys/arch/hpcmips/vr/vrc4173bcu.c

369

"\11GIU\12AC97\13AC97-1\14B11\15B12\16DOZEPIU\17B14\20B15", reg);

sys/arch/hpcmips/vr/vrc4173bcu.c

481

u_int16_t reg;

sys/arch/hpcmips/vr/vrc4173bcu.c

485

reg = bus_space_read_2(sc->sc_iot, sc->sc_icuh, VRC4173ICU_SYSINT1);

sys/arch/hpcmips/vr/vrc4173bcu.c

486

reg &= sc->sc_intrmask;

sys/arch/hpcmips/vr/vrc4173bcu.c

487

if (reg == 0)

sys/arch/hpcmips/vr/vrc4173bcu.c

495

"\11GIU\12AC97\13AC97-1\14B11\15B12\16DOZEPIU\17B14\20B15", reg);

sys/arch/hpcmips/vr/vrc4173bcu.c

500

if ((reg & (1 << i)) && ih->ih_fun != NULL)

sys/arch/hpcmips/vr/vrc4173bcu.c

522

u_int32_t reg;

sys/arch/hpcmips/vr/vrc4173bcu.c

526

reg = bus_space_read_2(sc->sc_iot, sc->sc_icuh, vu->vu_mlreg);

sys/arch/hpcmips/vr/vrc4173bcu.c

528

reg |= (bus_space_read_2(sc->sc_iot, sc->sc_icuh,

sys/arch/hpcmips/vr/vrc4173bcu.c

530

dbg_bit_print(reg);

sys/arch/hpcmips/vr/vrc4173bcu.c

532

dbg_bit_print(reg);

sys/arch/hpcmips/vr/vrc4173bcu.c

625

u_int32_t reg;

sys/arch/hpcmips/vr/vrc4173bcu.c

627

reg = bus_space_read_2(sc->sc_iot, sc->sc_icuh, vu->vu_lreg);

sys/arch/hpcmips/vr/vrc4173bcu.c

628

reg |= (bus_space_read_2(sc->sc_iot, sc->sc_icuh, vu->vu_hreg) << 16);

sys/arch/hpcmips/vr/vrc4173bcu.c

629

*status = reg;

sys/arch/hpcmips/vr/vrc4173bcu.c

640

u_int16_t reg;

sys/arch/hpcmips/vr/vrc4173bcu.c

648

reg = bus_space_read_2(sc->sc_iot, sc->sc_icuh, vu->vu_mlreg);

sys/arch/hpcmips/vr/vrc4173bcu.c

650

reg |= (mask & 0xffff);

sys/arch/hpcmips/vr/vrc4173bcu.c

652

reg &= ~(mask & 0xffff);

sys/arch/hpcmips/vr/vrc4173bcu.c

653

bus_space_write_2(sc->sc_iot, sc->sc_ioh, vu->vu_mlreg, reg);

sys/arch/hpcmips/vr/vrc4173bcu.c

656

reg = bus_space_read_2(sc->sc_iot, sc->sc_icuh, vu->vu_mhreg);

sys/arch/hpcmips/vr/vrc4173bcu.c

658

reg |= ((mask >> 16) & 0xffff);

sys/arch/hpcmips/vr/vrc4173bcu.c

660

reg &= ~((mask >> 16) & 0xffff);

sys/arch/hpcmips/vr/vrc4173bcu.c

661

bus_space_write_2(sc->sc_iot, sc->sc_icuh, vu->vu_mhreg, reg);

sys/arch/hpcmips/vr/vrc4173bcu.c

675

u_int16_t reg;

sys/arch/hpcmips/vr/vrc4173bcu.c

677

reg = bus_space_read_2(sc->sc_iot, sc->sc_cmuh, VRC4173CMU_CLKMSK);

sys/arch/hpcmips/vr/vrc4173bcu.c

680

dbg_bit_print(reg);

sys/arch/hpcmips/vr/vrc4173bcu.c

683

reg |= mask;

sys/arch/hpcmips/vr/vrc4173bcu.c

685

reg &= ~mask;

sys/arch/hpcmips/vr/vrc4173bcu.c

686

bus_space_write_2(sc->sc_iot, sc->sc_cmuh, VRC4173CMU_CLKMSK, reg);

sys/arch/hpcmips/vr/vrc4173bcu.c

689

dbg_bit_print(reg);

sys/arch/hpcmips/vr/vrgiu.c

420

u_int16_t reg[2];

sys/arch/hpcmips/vr/vrgiu.c

422

bus_space_read_region_2 (sc->sc_iot, sc->sc_ioh, offs, reg, 2);

sys/arch/hpcmips/vr/vrgiu.c

424

return (reg[0] | (reg[1] << 16));

sys/arch/hpcmips/vr/vrgiu.c

437

u_int16_t reg[2];

sys/arch/hpcmips/vr/vrgiu.c

439

reg[0] = data & 0xffff;

sys/arch/hpcmips/vr/vrgiu.c

440

reg[1] = (data>>16)&0xffff;

sys/arch/hpcmips/vr/vrgiu.c

441

bus_space_write_region_2 (sc->sc_iot, sc->sc_ioh, offs, reg, 2);

sys/arch/hpcmips/vr/vrgiu.c

475

u_int32_t reg[2];

sys/arch/hpcmips/vr/vrgiu.c

481

reg[0] = vrgiu_regread_4(sc, GIUPIOD_REG);

sys/arch/hpcmips/vr/vrgiu.c

482

reg[1] = vrgiu_regread_4(sc, GIUPODAT_REG);

sys/arch/hpcmips/vr/vrgiu.c

488

reg[bank] |= (1<<port);

sys/arch/hpcmips/vr/vrgiu.c

490

reg[bank] &= ~(1<<port);

sys/arch/hpcmips/vr/vrgiu.c

491

vrgiu_regwrite_4(sc, GIUPIOD_REG, reg[0]);

sys/arch/hpcmips/vr/vrgiu.c

492

vrgiu_regwrite_4(sc, GIUPODAT_REG, reg[1]);

sys/arch/hpcmips/vr/vrgiu.c

526

u_int32_t reg, mask;

sys/arch/hpcmips/vr/vrgiu.c

552

reg = vrgiu_regread_4(sc, GIUIOSEL_REG);

sys/arch/hpcmips/vr/vrgiu.c

553

reg &= ~mask;

sys/arch/hpcmips/vr/vrgiu.c

554

vrgiu_regwrite_4(sc, GIUIOSEL_REG, reg);

sys/arch/hpcmips/vr/vrgiu.c

557

reg = vrgiu_regread_4(sc, GIUINTTYP_REG);

sys/arch/hpcmips/vr/vrgiu.c

558

DPRINTF(DEBUG_INTR, ("[%s->",reg & mask ? "edge" : "level"));

sys/arch/hpcmips/vr/vrgiu.c

561

reg |= mask; /* edge */

sys/arch/hpcmips/vr/vrgiu.c

564

reg &= ~mask; /* level */

sys/arch/hpcmips/vr/vrgiu.c

566

vrgiu_regwrite_4(sc, GIUINTTYP_REG, reg);

sys/arch/hpcmips/vr/vrgiu.c

570

reg = vrgiu_regread_4(sc, GIUINTALSEL_REG);

sys/arch/hpcmips/vr/vrgiu.c

571

DPRINTF(DEBUG_INTR, ("[%s->",reg & mask ? "high" : "low"));

sys/arch/hpcmips/vr/vrgiu.c

574

reg |= mask; /* high */

sys/arch/hpcmips/vr/vrgiu.c

577

reg &= ~mask; /* low */

sys/arch/hpcmips/vr/vrgiu.c

579

vrgiu_regwrite_4(sc, GIUINTALSEL_REG, reg);

sys/arch/hpcmips/vr/vrgiu.c

582

reg = vrgiu_regread_4(sc, GIUINTHTSEL_REG);

sys/arch/hpcmips/vr/vrgiu.c

583

DPRINTF(DEBUG_INTR, ("[%s->",reg & mask ? "hold" : "through"));

sys/arch/hpcmips/vr/vrgiu.c

586

reg |= mask; /* hold */

sys/arch/hpcmips/vr/vrgiu.c

589

reg &= ~mask; /* through */

sys/arch/hpcmips/vr/vrgiu.c

591

vrgiu_regwrite_4(sc, GIUINTHTSEL_REG, reg);

sys/arch/hpcmips/vr/vrgiu.c

596

reg = vrgiu_regread_4(sc, GIUINTSTAT_REG);

sys/arch/hpcmips/vr/vrgiu.c

597

reg &= ~mask;

sys/arch/hpcmips/vr/vrgiu.c

598

vrgiu_regwrite_4(sc, GIUINTSTAT_REG, reg);

sys/arch/hpcmips/vr/vrgiu.c

654

u_int32_t reg;

sys/arch/hpcmips/vr/vrgiu.c

656

reg = vrgiu_regread_4(sc, GIUINTSTAT_REG);

sys/arch/hpcmips/vr/vrgiu.c

657

vrgiu_regwrite_4(sc, GIUINTSTAT_REG, reg & ~(1 << ihe->ih_port));

sys/arch/hpcmips/vr/vrgiu.c

678

u_int32_t reg;

sys/arch/hpcmips/vr/vrgiu.c

682

vrip_intr_getstatus2 (sc->sc_vc, sc->sc_ih, &reg);

sys/arch/hpcmips/vr/vrgiu.c

688

printf ("%c" , reg&j ? '|' : '.');

sys/arch/hpcmips/vr/vrgiu.c

689

uedge = (reg ^ oreg) & reg;

sys/arch/hpcmips/vr/vrgiu.c

690

dedge = (reg ^ oreg) & ~reg;

sys/arch/hpcmips/vr/vrgiu.c

699

oreg = reg;

sys/arch/hpcmips/vr/vrgiu.c

708

if (reg & (1 << i)) {

sys/arch/hpcmips/vr/vrip.c

380

u_int32_t reg = sc->sc_intrmask;

sys/arch/hpcmips/vr/vrip.c

384

bus_space_write_2 (iot, ioh, MSYSINT1_REG_W, reg & 0xffff);

sys/arch/hpcmips/vr/vrip.c

385

bus_space_write_2 (iot, ioh, sc->sc_msysint2, (reg >> 16) & 0xffff);

sys/arch/hpcmips/vr/vrip.c

398

u_int32_t reg = sc->sc_intrmask;

sys/arch/hpcmips/vr/vrip.c

402

reg = (bus_space_read_2 (iot, ioh, MSYSINT1_REG_W)&0xffff) |

sys/arch/hpcmips/vr/vrip.c

405

reg |= (1 << level1);

sys/arch/hpcmips/vr/vrip.c

407

reg &= ~(1 << level1);

sys/arch/hpcmips/vr/vrip.c

409

sc->sc_intrmask = reg;

sys/arch/hpcmips/vr/vrip.c

410

bus_space_write_2 (iot, ioh, MSYSINT1_REG_W, reg & 0xffff);

sys/arch/hpcmips/vr/vrip.c

411

bus_space_write_2 (iot, ioh, sc->sc_msysint2, (reg >> 16) & 0xffff);

sys/arch/hpcmips/vr/vrip.c

412

DBG_BIT_PRINT(reg);

sys/arch/hpcmips/vr/vrip.c

423

u_int32_t reg;

sys/arch/hpcmips/vr/vrip.c

427

reg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, vu->vu_mlreg);

sys/arch/hpcmips/vr/vrip.c

429

reg |= (bus_space_read_2(sc->sc_iot, sc->sc_ioh,

sys/arch/hpcmips/vr/vrip.c

431

dbg_bit_print(reg);

sys/arch/hpcmips/vr/vrip.c

433

dbg_bit_print(reg);

sys/arch/hpcmips/vr/vrip.c

445

u_int32_t reg;

sys/arch/hpcmips/vr/vrip.c

447

reg = bus_space_read_2(sc->sc_iot, sc->sc_ioh,

sys/arch/hpcmips/vr/vrip.c

449

reg |= ((bus_space_read_2(sc->sc_iot, sc->sc_ioh,

sys/arch/hpcmips/vr/vrip.c

452

*mask = reg;

sys/arch/hpcmips/vr/vrip.c

463

u_int16_t reg;

sys/arch/hpcmips/vr/vrip.c

471

reg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, vu->vu_mlreg);

sys/arch/hpcmips/vr/vrip.c

473

reg |= (mask&0xffff);

sys/arch/hpcmips/vr/vrip.c

475

reg &= ~(mask&0xffff);

sys/arch/hpcmips/vr/vrip.c

476

bus_space_write_2(sc->sc_iot, sc->sc_ioh, vu->vu_mlreg, reg);

sys/arch/hpcmips/vr/vrip.c

478

reg = bus_space_read_2(sc->sc_iot, sc->sc_ioh,

sys/arch/hpcmips/vr/vrip.c

481

reg |= ((mask >> 16) & 0xffff);

sys/arch/hpcmips/vr/vrip.c

483

reg &= ~((mask >> 16) & 0xffff);

sys/arch/hpcmips/vr/vrip.c

485

vu->vu_mhreg, reg);

sys/arch/hpcmips/vr/vrip.c

501

u_int32_t reg, mask;

sys/arch/hpcmips/vr/vrip.c

505

reg = (bus_space_read_2 (iot, ioh, SYSINT1_REG_W)&0xffff) |

sys/arch/hpcmips/vr/vrip.c

509

reg &= mask;

sys/arch/hpcmips/vr/vrip.c

516

if (ih->ih_fun && (reg & (1 << i))) {

sys/arch/hpcmips/vr/vrip.c

68

#define DBG_BIT_PRINT(reg) if (vrip_debug) dbg_bit_print(reg);

sys/arch/hpcmips/vr/vrpciu.c

149

u_int32_t reg;

sys/arch/hpcmips/vr/vrpciu.c

179

#define DUMP_MAW(sc, name, reg) do { \

sys/arch/hpcmips/vr/vrpciu.c

181

(name), (reg)); \

sys/arch/hpcmips/vr/vrpciu.c

184

reg & VRPCIU_MAW_IBAMASK, VRPCIU_MAW_ADDRMASK(reg), \

sys/arch/hpcmips/vr/vrpciu.c

185

VRPCIU_MAW_ADDR(reg), \

sys/arch/hpcmips/vr/vrpciu.c

186

VRPCIU_MAW_ADDR(reg) + VRPCIU_MAW_SIZE(reg)); \

sys/arch/hpcmips/vr/vrpciu.c

188

reg & VRPCIU_MAW_WINEN); \

sys/arch/hpcmips/vr/vrpciu.c

190

VRPCIU_MAW_PCIADDR(reg)); \

sys/arch/hpcmips/vr/vrpciu.c

192

#define DUMP_TAW(sc, name, reg) do { \

sys/arch/hpcmips/vr/vrpciu.c

194

(name), (reg)); \

sys/arch/hpcmips/vr/vrpciu.c

196

VRPCIU_TAW_ADDRMASK(reg)); \

sys/arch/hpcmips/vr/vrpciu.c

198

reg & VRPCIU_TAW_WINEN); \

sys/arch/hpcmips/vr/vrpciu.c

200

VRPCIU_TAW_IBA(reg)); \

sys/arch/hpcmips/vr/vrpciu.c

202

reg = vrpciu_read(sc, VRPCIU_MMAW1REG);

sys/arch/hpcmips/vr/vrpciu.c

203

DUMP_MAW(sc, "MMAW1", reg);

sys/arch/hpcmips/vr/vrpciu.c

204

reg = vrpciu_read(sc, VRPCIU_MMAW2REG);

sys/arch/hpcmips/vr/vrpciu.c

205

DUMP_MAW(sc, "MMAW2", reg);

sys/arch/hpcmips/vr/vrpciu.c

206

reg = vrpciu_read(sc, VRPCIU_TAW1REG);

sys/arch/hpcmips/vr/vrpciu.c

207

DUMP_TAW(sc, "TAW1", reg);

sys/arch/hpcmips/vr/vrpciu.c

208

reg = vrpciu_read(sc, VRPCIU_TAW2REG);

sys/arch/hpcmips/vr/vrpciu.c

209

DUMP_TAW(sc, "TAW2", reg);

sys/arch/hpcmips/vr/vrpciu.c

210

reg = vrpciu_read(sc, VRPCIU_MIOAWREG);

sys/arch/hpcmips/vr/vrpciu.c

211

DUMP_MAW(sc, "MIOAW", reg);

sys/arch/hpcmips/vr/vrpciu.c

230

reg = vrpciu_read(sc, VRPCIU_CONF_BASE + PCI_COMMAND_STATUS_REG);

sys/arch/hpcmips/vr/vrpciu.c

231

printf("%s: CSR =\t\t0x%08x\n", device_xname(sc->sc_dev), reg);

sys/arch/hpcmips/vr/vrpciu.c

232

vrpciu_write(sc, VRPCIU_CONF_BASE + PCI_COMMAND_STATUS_REG, reg);

sys/arch/hpcmips/vr/vrpciu.c

287

reg = vrpciu_read(sc, VRPCIU_MIOAWREG);

sys/arch/hpcmips/vr/vrpciu.c

291

tmpbuf, VRPCIU_MAW_ADDR(reg), VRPCIU_MAW_SIZE(reg));

sys/arch/hpcmips/vr/vrpciu.c

310

reg = pci_conf_read(pc, pci_make_tag(pc, 0, 16, 0),

sys/arch/hpcmips/vr/vrpciu.c

312

reg |= PCIIDE_INTERFACE_PCI(0) << PCI_INTERFACE_SHIFT;

sys/arch/hpcmips/vr/vrpciu.c

313

reg |= PCIIDE_INTERFACE_PCI(1) << PCI_INTERFACE_SHIFT;

sys/arch/hpcmips/vr/vrpciu.c

315

reg);

sys/arch/hpcmips/vr/vrpciu.c

421

vrpciu_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg)

sys/arch/hpcmips/vr/vrpciu.c

427

if ((unsigned int)reg >= PCI_CONF_SIZE)

sys/arch/hpcmips/vr/vrpciu.c

438

vrpciu_write(sc, VRPCIU_CONFAREG, tag | reg);

sys/arch/hpcmips/vr/vrpciu.c

442

device_xname(sc->sc_dev), (u_int32_t)tag, reg, val);

sys/arch/hpcmips/vr/vrpciu.c

448

vrpciu_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg,

sys/arch/hpcmips/vr/vrpciu.c

456

device_xname(sc->sc_dev), (u_int32_t)tag, reg, (u_int32_t)data);

sys/arch/hpcmips/vr/vrpciu.c

459

if ((unsigned int)reg >= PCI_CONF_SIZE)

sys/arch/hpcmips/vr/vrpciu.c

470

vrpciu_write(sc, VRPCIU_CONFAREG, tag | reg);

sys/arch/hpcmips/vr/vrpciureg.h

39

#define VRPCIU_MAW_ADDRMASK(reg) \

sys/arch/hpcmips/vr/vrpciureg.h

40

((((reg) >> 13) & 0x7f) << 24) /* Address Mask */

sys/arch/hpcmips/vr/vrpciureg.h

41

#define VRPCIU_MAW_ADDR(reg) \

sys/arch/hpcmips/vr/vrpciureg.h

42

(((reg) & VRPCIU_MAW_IBAMASK) & VRPCIU_MAW_ADDRMASK(reg))

sys/arch/hpcmips/vr/vrpciureg.h

43

#define VRPCIU_MAW_SIZE(reg) (~(VRPCIU_MAW_ADDRMASK(reg) | 0x80000000))

sys/arch/hpcmips/vr/vrpciureg.h

45

#define VRPCIU_MAW_PCIADDR(reg) (((reg) & 0xff) << 24) /* PCI Address */

sys/arch/hpcmips/vr/vrpciureg.h

53

#define VRPCIU_TAW_ADDRMASK(reg) \

sys/arch/hpcmips/vr/vrpciureg.h

54

((((reg) >> 13) & 0x7f) << 21) /* Address Mask */

sys/arch/hpcmips/vr/vrpciureg.h

56

#define VRPCIU_TAW_IBA(reg) (((reg) & 0x7ff) << 21) /* Internal Bus Address */

sys/arch/hpcmips/vr/vrpmu.c

222

unsigned int reg;

sys/arch/hpcmips/vr/vrpmu.c

226

reg = vrpmu_read(sc, PMUINT_REG_W);

sys/arch/hpcmips/vr/vrpmu.c

227

reg = vrpmu_read(sc, PMUINT2_REG_W);

sys/arch/hpcmips/vr/vrpmu.c

230

reg = vrpmu_read(sc, PMUCNT_REG_W);

sys/arch/hpcmips/vr/vrpmu.c

231

printf("vrpmu: cnt 0x%x: ", reg);

sys/arch/hpcmips/vr/vrpmu.c

232

dbg_bit_print(reg);

sys/arch/hpcmips/vr/vrpmu.c

233

reg = vrpmu_read(sc, PMUCNT2_REG_W);

sys/arch/hpcmips/vr/vrpmu.c

234

printf("vrpmu: cnt2 0x%x: ", reg);

sys/arch/hpcmips/vr/vrpmu.c

235

dbg_bit_print(reg);

sys/arch/hpcmips/vr/vrpmu.c

239

reg = vrpmu_read(sc, PMUWAIT_REG_W);

sys/arch/hpcmips/vr/vrpmu.c

240

printf("vrpmu: wait 0x%x", reg);

sys/arch/hpcmips/vr/vrpmu.c

243

reg = vrpmu_read(sc, PMUDIV_REG_W);

sys/arch/hpcmips/vr/vrpmu.c

244

printf(" div 0x%x", reg);

sys/arch/hppa/dev/apic.c

128

pcireg_t reg;

sys/arch/hppa/dev/apic.c

131

reg = pci_conf_read(pc, tag, PCI_INTERRUPT_REG);

sys/arch/hppa/dev/apic.c

133

printf(" pin=%d line=%d ", PCI_INTERRUPT_PIN(reg),

sys/arch/hppa/dev/apic.c

134

PCI_INTERRUPT_LINE(reg));

sys/arch/hppa/dev/apic.c

136

line = PCI_INTERRUPT_LINE(reg);

sys/arch/hppa/dev/apic.c

78

uint32_t apic_read(volatile struct elroy_regs *, uint32_t reg);

sys/arch/hppa/dev/apic.c

87

apic_write(volatile struct elroy_regs *r, uint32_t reg, uint32_t val)

sys/arch/hppa/dev/apic.c

89

elroy_write32(&r->apic_addr, htole32(reg));

sys/arch/hppa/dev/apic.c

95

apic_read(volatile struct elroy_regs *r, uint32_t reg)

sys/arch/hppa/dev/apic.c

97

elroy_write32(&r->apic_addr, htole32(reg));

sys/arch/hppa/dev/dino.c

343

dino_conf_read(void *v, pcitag_t tag, int reg)

sys/arch/hppa/dev/dino.c

350

if ((unsigned int)reg >= PCI_CONF_SIZE)

sys/arch/hppa/dev/dino.c

375

r->pci_addr = tag | reg;

sys/arch/hppa/dev/dino.c

385

dino_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data)

sys/arch/hppa/dev/dino.c

391

if ((unsigned int)reg >= PCI_CONF_SIZE)

sys/arch/hppa/dev/dino.c

403

r->pci_addr = tag | reg;

sys/arch/hppa/dev/dino.c

506

uint32_t reg;

sys/arch/hppa/dev/dino.c

509

reg = r->io_addr_en;

sys/arch/hppa/dev/dino.c

510

reg |= 1 << ((bpa >> 23) & 0x1f);

sys/arch/hppa/dev/dino.c

512

if (reg & 0x80000001)

sys/arch/hppa/dev/dino.c

519

if (reg != r->io_addr_en)

sys/arch/hppa/dev/dino.c

520

r->io_addr_en = reg;

sys/arch/hppa/dev/dino.c

564

uint32_t reg;

sys/arch/hppa/dev/dino.c

573

reg = r->io_addr_en;

sys/arch/hppa/dev/dino.c

574

if (rstart < 0xf0800000 || rend >= 0xff800000 || reg == 0)

sys/arch/hppa/dev/dino.c

578

if ((reg & 1 << i) != 0) {

sys/arch/hppa/dev/elroy.c

257

elroy_conf_read(void *v, pcitag_t tag, int reg)

sys/arch/hppa/dev/elroy.c

266

if ((unsigned int)reg >= PCI_CONF_SIZE)

sys/arch/hppa/dev/elroy.c

279

elroy_write32(&r->pci_conf_addr, htole32(tag | reg));

sys/arch/hppa/dev/elroy.c

296

elroy_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data)

sys/arch/hppa/dev/elroy.c

304

if ((unsigned int)reg >= PCI_CONF_SIZE)

sys/arch/hppa/dev/elroy.c

322

elroy_write32(&r->pci_conf_addr, htole32(tag | reg));

sys/arch/hppa/dev/gftfb.c

223

uint32_t reg;

sys/arch/hppa/dev/gftfb.c

226

reg = gftfb_read4(sc, NGLE_FIFO);

sys/arch/hppa/dev/gftfb.c

227

} while (reg < slots);

sys/arch/hppa/dev/hyperfb.c

1001

hyperfb_write4(sc, NGLE_HCRX_MISCVID, reg & ~HCRX_VIDEO_ENABLE);

sys/arch/hppa/dev/hyperfb.c

202

uint32_t reg;

sys/arch/hppa/dev/hyperfb.c

205

reg = hyperfb_read4(sc, NGLE_FIFO);

sys/arch/hppa/dev/hyperfb.c

206

} while (reg < slots);

sys/arch/hppa/dev/hyperfb.c

987

uint32_t reg;

sys/arch/hppa/dev/hyperfb.c

996

reg = hyperfb_read4(sc, NGLE_HCRX_MISCVID);

sys/arch/hppa/dev/hyperfb.c

999

hyperfb_write4(sc, NGLE_HCRX_MISCVID, reg | HCRX_VIDEO_ENABLE);

sys/arch/hppa/dev/siop_sgc.c

164

uint16_t reg;

sys/arch/hppa/dev/siop_sgc.c

166

reg = siop_sgc_r1(v, h, SIOP_SIST0);

sys/arch/hppa/dev/siop_sgc.c

167

reg |= siop_sgc_r1(v, h, SIOP_SIST1) << 8;

sys/arch/hppa/dev/siop_sgc.c

168

return reg;

sys/arch/hppa/dev/ssio.c

176

pcireg_t reg;

sys/arch/hppa/dev/ssio.c

228

reg = pci_conf_read(pa->pa_pc, pa->pa_tag, SSIO_PCI_DMA_RC2);

sys/arch/hppa/dev/ssio.c

229

reg &= ~(SSIO_PCI_INT_TC1_MASK << SSIO_PCI_INT_TC1_SHIFT);

sys/arch/hppa/dev/ssio.c

230

reg |= 0x22 << SSIO_PCI_INT_TC1_SHIFT;

sys/arch/hppa/dev/ssio.c

231

pci_conf_write(pa->pa_pc, pa->pa_tag, SSIO_PCI_DMA_RC2, reg);

sys/arch/hppa/dev/ssio.c

233

reg = 0;

sys/arch/hppa/dev/ssio.c

234

reg |= 0x34 << SSIO_PCI_INT_RC1_SHIFT; /* SP1, SP2 */

sys/arch/hppa/dev/ssio.c

235

reg |= 0x07 << SSIO_PCI_INT_RC2_SHIFT; /* PP */

sys/arch/hppa/dev/ssio.c

236

reg |= 0x05 << SSIO_PCI_INT_RC3_SHIFT; /* IDE1 */

sys/arch/hppa/dev/ssio.c

237

pci_conf_write(pa->pa_pc, pa->pa_tag, SSIO_PCI_INT_TC2, reg);

sys/arch/hppa/dev/ssio.c

239

reg = 0;

sys/arch/hppa/dev/ssio.c

240

reg |= 0x10 << SSIO_PCI_INT_RC5_SHIFT; /* INTD# (USB) */

sys/arch/hppa/dev/ssio.c

241

pci_conf_write(pa->pa_pc, pa->pa_tag, SSIO_PCI_INT_RC4, reg);

sys/arch/hppa/dev/ssio.c

296

reg = pci_conf_read(pa->pa_pc, tag, PCI_CBMEM);

sys/arch/hppa/dev/ssio.c

300

PAGE0->mem_kbd.pz_hpa == (struct iomod *)reg)

sys/arch/hppa/dev/summitfb.c

895

uint32_t reg;

sys/arch/hppa/dev/summitfb.c

898

reg = summitfb_read4(sc, VISFX_FIFO);

sys/arch/hppa/dev/summitfb.c

899

} while (reg < slots);

sys/arch/hppa/gsc/harmony.c

487

uint32_t reg;

sys/arch/hppa/gsc/harmony.c

492

reg = READ_REG(sc, HARMONY_CNTL);

sys/arch/hppa/gsc/harmony.c

493

if ((reg & CNTL_C) == 0)

sys/arch/hppa/gsc/harmony.c

506

uint32_t reg;

sys/arch/hppa/gsc/harmony.c

517

reg = READ_REG(sc, HARMONY_DSTATUS);

sys/arch/hppa/gsc/harmony.c

518

if ((reg & (DSTATUS_PC | DSTATUS_RC)) == 0)

sys/arch/hppa/gsc/harmonyvar.h

113

#define READ_REG(sc, reg) \

sys/arch/hppa/gsc/harmonyvar.h

114

bus_space_read_4((sc)->sc_bt, (sc)->sc_bh, (reg))

sys/arch/hppa/gsc/harmonyvar.h

115

#define WRITE_REG(sc, reg, val) \

sys/arch/hppa/gsc/harmonyvar.h

116

bus_space_write_4((sc)->sc_bt, (sc)->sc_bh, (reg), (val))

sys/arch/hppa/gsc/harmonyvar.h

117

#define SYNC_REG(sc, reg, flags) \

sys/arch/hppa/gsc/harmonyvar.h

118

bus_space_barrier((sc)->sc_bt, (sc)->sc_bh, (reg), sizeof(uint32_t), \

sys/arch/hppa/gsc/siop_gsc.c

153

uint16_t reg;

sys/arch/hppa/gsc/siop_gsc.c

155

reg = siop_gsc_r1(v, h, SIOP_SIST0);

sys/arch/hppa/gsc/siop_gsc.c

156

reg |= siop_gsc_r1(v, h, SIOP_SIST1) << 8;

sys/arch/hppa/gsc/siop_gsc.c

157

return reg;

sys/arch/hppa/hppa/fpu.c

97

#define FRAME_REG(f, reg, r0) \

sys/arch/hppa/hppa/fpu.c

98

((reg) == 0 ? (&r0) : ((&(f)->tf_t1) + _frame_reg_positions[reg]))

sys/arch/hppa/hppa/intr.c

495

int reg = ir->ir_bits_map[31 ^ idx] & ~IR_BIT_MASK;

sys/arch/hppa/hppa/intr.c

497

nir = hppa_interrupt_registers[reg];

sys/arch/hppa/hppa/process_machdep.c

121

process_write_regs(struct lwp *l, const struct reg *regs)

sys/arch/hppa/hppa/process_machdep.c

49

process_read_regs(struct lwp *l, struct reg *regs)

sys/arch/hppa/include/pcb.h

45

struct reg md_reg;

sys/arch/i386/i386/process_machdep.c

109

process_read_regs(struct lwp *l, struct reg *regs)

sys/arch/i386/i386/process_machdep.c

154

process_write_regs(struct lwp *l, const struct reg *regs)

sys/arch/i386/include/frameasm.h

100

movl CPUVAR(CURLWP),reg; \

sys/arch/i386/include/frameasm.h

101

incl L_NOPREEMPT(reg); \

sys/arch/i386/include/frameasm.h

104

decl L_NOPREEMPT(reg);

sys/arch/i386/include/frameasm.h

106

#define PUSHFCLI(reg, reg2) \

sys/arch/i386/include/frameasm.h

107

movl CPUVAR(CURLWP),reg; \

sys/arch/i386/include/frameasm.h

108

incl L_NOPREEMPT(reg); \

sys/arch/i386/include/frameasm.h

114

decl L_NOPREEMPT(reg);

sys/arch/i386/include/frameasm.h

116

#define POPF(reg) call _C_LABEL(xen_write_psl); \

sys/arch/i386/include/frameasm.h

119

#define CLI(reg) cli

sys/arch/i386/include/frameasm.h

120

#define CLI2(reg, reg2) cli

sys/arch/i386/include/frameasm.h

121

#define STI(reg) sti

sys/arch/i386/include/frameasm.h

122

#define PUSHFCLI(reg, reg2) pushf ; cli

sys/arch/i386/include/frameasm.h

123

#define POPF(reg) popf

sys/arch/i386/include/frameasm.h

187

#define CHECK_ASTPENDING(reg) movl CPUVAR(CURLWP),reg ; \

sys/arch/i386/include/frameasm.h

188

cmpl $0, L_MD_ASTPENDING(reg)

sys/arch/i386/include/frameasm.h

189

#define CLEAR_ASTPENDING(reg) movl $0, L_MD_ASTPENDING(reg)

sys/arch/i386/include/frameasm.h

26

#define CLI(reg) \

sys/arch/i386/include/frameasm.h

27

movl CPUVAR(CURLWP),reg ; \

sys/arch/i386/include/frameasm.h

28

cmpl $0, L_NOPREEMPT(reg); \

sys/arch/i386/include/frameasm.h

32

movl CPUVAR(IDEPTH), reg; \

sys/arch/i386/include/frameasm.h

33

test reg, reg; \

sys/arch/i386/include/frameasm.h

35

movl $panicstr,reg ; \

sys/arch/i386/include/frameasm.h

36

cmpl $0, 0(reg); \

sys/arch/i386/include/frameasm.h

39

movl $_C_LABEL(cli_panic), reg; \

sys/arch/i386/include/frameasm.h

40

pushl 0(reg); \

sys/arch/i386/include/frameasm.h

43

199: movl CPUVAR(VCPU),reg ; \

sys/arch/i386/include/frameasm.h

44

movb $1,EVTCHN_UPCALL_MASK(reg)

sys/arch/i386/include/frameasm.h

46

#define STI(reg) \

sys/arch/i386/include/frameasm.h

47

movl CPUVAR(VCPU),reg ; \

sys/arch/i386/include/frameasm.h

48

cmpb $0, EVTCHN_UPCALL_MASK(reg) ; \

sys/arch/i386/include/frameasm.h

50

movl $panicstr,reg ; \

sys/arch/i386/include/frameasm.h

51

cmpl $0, 0(reg); \

sys/arch/i386/include/frameasm.h

54

movl $_C_LABEL(sti_panic), reg; \

sys/arch/i386/include/frameasm.h

55

pushl 0(reg); \

sys/arch/i386/include/frameasm.h

58

198: movb $0,EVTCHN_UPCALL_MASK(reg)

sys/arch/i386/include/frameasm.h

68

#define STIC(reg) \

sys/arch/i386/include/frameasm.h

69

movl CPUVAR(VCPU),reg ; \

sys/arch/i386/include/frameasm.h

70

cmpb $0, EVTCHN_UPCALL_MASK(reg) ; \

sys/arch/i386/include/frameasm.h

72

movl $panicstr,reg ; \

sys/arch/i386/include/frameasm.h

73

cmpl $0, 0(reg); \

sys/arch/i386/include/frameasm.h

76

movl $_C_LABEL(sti_panic), reg; \

sys/arch/i386/include/frameasm.h

77

pushl 0(reg); \

sys/arch/i386/include/frameasm.h

80

197: movl CPUVAR(VCPU),reg ; \

sys/arch/i386/include/frameasm.h

81

movb $0,EVTCHN_UPCALL_MASK(reg); \

sys/arch/i386/include/frameasm.h

82

testb $0xff,EVTCHN_UPCALL_PENDING(reg)

sys/arch/i386/include/frameasm.h

85

#define CLI(reg) \

sys/arch/i386/include/frameasm.h

86

movl CPUVAR(VCPU),reg ; \

sys/arch/i386/include/frameasm.h

87

movb $1,EVTCHN_UPCALL_MASK(reg)

sys/arch/i386/include/frameasm.h

89

#define STI(reg) \

sys/arch/i386/include/frameasm.h

90

movl CPUVAR(VCPU),reg ; \

sys/arch/i386/include/frameasm.h

91

movb $0,EVTCHN_UPCALL_MASK(reg)

sys/arch/i386/include/frameasm.h

93

#define STIC(reg) \

sys/arch/i386/include/frameasm.h

94

movl CPUVAR(VCPU),reg ; \

sys/arch/i386/include/frameasm.h

95

movb $0,EVTCHN_UPCALL_MASK(reg); \

sys/arch/i386/include/frameasm.h

96

testb $0xff,EVTCHN_UPCALL_PENDING(reg)

sys/arch/i386/include/frameasm.h

99

#define CLI2(reg, reg2) \

sys/arch/i386/include/xen/hypercalls.h

143

HYPERVISOR_set_debugreg(int reg, unsigned long value)

sys/arch/i386/include/xen/hypercalls.h

148

_hypercall(__HYPERVISOR_set_debugreg, _harg("1" (reg), "2" (value)),

sys/arch/i386/include/xen/hypercalls.h

155

HYPERVISOR_get_debugreg(int reg)

sys/arch/i386/include/xen/hypercalls.h

160

_hypercall(__HYPERVISOR_get_debugreg, _harg("1" (reg)),

sys/arch/i386/mca/mca_machdep.c

161

mca_conf_read(mca_chipset_tag_t mc, int slot, int reg)

sys/arch/i386/mca/mca_machdep.c

168

data = inb(MCA_POS_REG(reg));

sys/arch/i386/mca/mca_machdep.c

179

mca_conf_write(mca_chipset_tag_t mc, int slot, int reg, int data)

sys/arch/i386/mca/mca_machdep.c

184

outb(MCA_POS_REG(reg), data);

sys/arch/i386/pci/ali1543.c

148

#define ALI1543_INTR_PIRQ_IRQ(reg, clink) \

sys/arch/i386/pci/ali1543.c

149

(((reg) >> ((clink)*4)) & 0x0f)

sys/arch/i386/pci/ali1543.c

150

#define ALI1543_PIRQ(reg, clink) \

sys/arch/i386/pci/ali1543.c

151

ali1543_intr_shuffle_get[ALI1543_INTR_PIRQ_IRQ((reg), (clink))]

sys/arch/i386/pci/ali1543.c

184

pcireg_t reg;

sys/arch/i386/pci/ali1543.c

190

reg = pci_conf_read(ph->ph_pc, ph->ph_tag, ALI1543_INTR_CFG_REG);

sys/arch/i386/pci/ali1543.c

192

printf("ali1543: PIRQ reg 0x%08x\n", reg); /* XXX debug */

sys/arch/i386/pci/ali1543.c

194

val = ALI1543_PIRQ(reg, clink);

sys/arch/i386/pci/ali1543.c

206

pcireg_t reg;

sys/arch/i386/pci/ali1543.c

211

reg = pci_conf_read(ph->ph_pc, ph->ph_tag, ALI1543_INTR_CFG_REG);

sys/arch/i386/pci/ali1543.c

214

reg &= ~(0x0f << shift);

sys/arch/i386/pci/ali1543.c

215

reg |= (ali1543_intr_shuffle_set[irq] << shift);

sys/arch/i386/pci/ali1543.c

216

pci_conf_write(ph->ph_pc, ph->ph_tag, ALI1543_INTR_CFG_REG, reg);

sys/arch/i386/pci/amd756.c

144

pcireg_t reg;

sys/arch/i386/pci/amd756.c

150

reg = AMD756_GET_PIIRQSEL(ph);

sys/arch/i386/pci/amd756.c

151

val = (reg >> (4 * clink)) & 0x0f;

sys/arch/i386/pci/amd756.c

163

pcireg_t reg;

sys/arch/i386/pci/amd756.c

168

reg = AMD756_GET_PIIRQSEL(ph);

sys/arch/i386/pci/amd756.c

170

reg &= ~(0x000f << (4 * clink));

sys/arch/i386/pci/amd756.c

171

reg |= irq << (4 * clink);

sys/arch/i386/pci/amd756.c

172

AMD756_SET_PIIRQSEL(ph, reg);

sys/arch/i386/pci/amd756.c

182

pcireg_t reg;

sys/arch/i386/pci/amd756.c

190

reg = AMD756_GET_EDGESEL(ph);

sys/arch/i386/pci/amd756.c

191

if (reg & (1 << i))

sys/arch/i386/pci/amd756.c

207

pcireg_t reg;

sys/arch/i386/pci/amd756.c

215

reg = AMD756_GET_PIIRQSEL(ph);

sys/arch/i386/pci/amd756.c

217

reg &= ~(1 << (4 * i));

sys/arch/i386/pci/amd756.c

219

reg |= 1 << (4 * i);

sys/arch/i386/pci/amd756.c

220

AMD756_SET_PIIRQSEL(ph, reg);

sys/arch/i386/pci/elan520.c

1268

int pin, reg, shift;

sys/arch/i386/pci/elan520.c

1373

reg = (pin < 16 ? MMCR_PIODIR15_0 : MMCR_PIODIR31_16);

sys/arch/i386/pci/elan520.c

1375

data = bus_space_read_2(sc->sc_memt, sc->sc_memh, reg);

sys/arch/i386/pci/elan520.c

1496

int reg, shift;

sys/arch/i386/pci/elan520.c

1499

reg = (pin < 16 ? MMCR_PIODATA15_0 : MMCR_PIODATA31_16);

sys/arch/i386/pci/elan520.c

1503

data = bus_space_read_2(sc->sc_memt, sc->sc_memh, reg);

sys/arch/i386/pci/elan520.c

1513

int reg, shift;

sys/arch/i386/pci/elan520.c

1516

reg = (pin < 16 ? MMCR_PIODATA15_0 : MMCR_PIODATA31_16);

sys/arch/i386/pci/elan520.c

1520

data = bus_space_read_2(sc->sc_memt, sc->sc_memh, reg);

sys/arch/i386/pci/elan520.c

1526

bus_space_write_2(sc->sc_memt, sc->sc_memh, reg, data);

sys/arch/i386/pci/elan520.c

1534

int reg, shift;

sys/arch/i386/pci/elan520.c

1537

reg = (pin < 16 ? MMCR_PIODIR15_0 : MMCR_PIODIR31_16);

sys/arch/i386/pci/elan520.c

1540

data = bus_space_read_2(sc->sc_memt, sc->sc_memh, reg);

sys/arch/i386/pci/elan520.c

1546

bus_space_write_2(sc->sc_memt, sc->sc_memh, reg, data);

sys/arch/i386/pci/gcscide.c

195

uint64_t reg = 0;

sys/arch/i386/pci/gcscide.c

205

reg = rdmsr(drive ? GCSCIDE_ATAC_CH0D1_DMA :

sys/arch/i386/pci/gcscide.c

213

reg |= GCSCIDE_ATAC_DMA_SEL;

sys/arch/i386/pci/gcscide.c

215

reg |= gcscide_udma_timings[drvp->UDMA_mode];

sys/arch/i386/pci/gcscide.c

218

GCSCIDE_ATAC_CH0D0_DMA, reg);

sys/arch/i386/pci/gcscide.c

222

reg &= ~GCSCIDE_ATAC_DMA_SEL;

sys/arch/i386/pci/gcscide.c

224

reg |= gcscide_mdma_timings[drvp->DMA_mode];

sys/arch/i386/pci/gcscide.c

227

GCSCIDE_ATAC_CH0D0_DMA, reg);

sys/arch/i386/pci/gcscide.c

232

GCSCIDE_ATAC_CH0D0_DMA, reg | GCSCIDE_ATAC_PIO_FORMAT);

sys/arch/i386/pci/gscpcib.c

202

int reg, shift;

sys/arch/i386/pci/gscpcib.c

205

reg = (pin < 32 ? GSCGPIO_GPDI0 : GSCGPIO_GPDI1);

sys/arch/i386/pci/gscpcib.c

207

data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg);

sys/arch/i386/pci/gscpcib.c

216

int reg, shift;

sys/arch/i386/pci/gscpcib.c

219

reg = (pin < 32 ? GSCGPIO_GPDO0 : GSCGPIO_GPDO1);

sys/arch/i386/pci/gscpcib.c

221

data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg);

sys/arch/i386/pci/gscpcib.c

227

bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg, data);

sys/arch/i386/pci/opti82c558.c

156

pcireg_t reg;

sys/arch/i386/pci/opti82c558.c

162

reg = pci_conf_read(ph->ph_pc, ph->ph_tag, VIPER_CFG_PIRQ);

sys/arch/i386/pci/opti82c558.c

163

val = VIPER_PIRQ(reg, clink);

sys/arch/i386/pci/opti82c558.c

175

pcireg_t reg;

sys/arch/i386/pci/opti82c558.c

180

reg = pci_conf_read(ph->ph_pc, ph->ph_tag, VIPER_CFG_PIRQ);

sys/arch/i386/pci/opti82c558.c

182

reg &= ~(VIPER_PIRQ_SELECT_MASK << shift);

sys/arch/i386/pci/opti82c558.c

183

reg |= (viper_pirq_encode[irq] << shift);

sys/arch/i386/pci/opti82c558.c

184

pci_conf_write(ph->ph_pc, ph->ph_tag, VIPER_CFG_PIRQ, reg);

sys/arch/i386/pci/opti82c558.c

193

pcireg_t reg;

sys/arch/i386/pci/opti82c558.c

201

reg = pci_conf_read(ph->ph_pc, ph->ph_tag, VIPER_CFG_PIRQ);

sys/arch/i386/pci/opti82c558.c

202

if ((reg >> (VIPER_CFG_TRIGGER_SHIFT + viper_pirq_encode[irq])) & 1)

sys/arch/i386/pci/opti82c558.c

215

pcireg_t reg;

sys/arch/i386/pci/opti82c558.c

222

reg = pci_conf_read(ph->ph_pc, ph->ph_tag, VIPER_CFG_PIRQ);

sys/arch/i386/pci/opti82c558.c

225

reg |= (1 << shift);

sys/arch/i386/pci/opti82c558.c

227

reg &= ~(1 << shift);

sys/arch/i386/pci/opti82c558.c

228

pci_conf_write(ph->ph_pc, ph->ph_tag, VIPER_CFG_PIRQ, reg);

sys/arch/i386/pci/opti82c558reg.h

64

#define VIPER_PIRQ(reg, x) (((reg) >> ((x) * VIPER_PIRQ_SELECT_SHIFT)) \

sys/arch/i386/pci/opti82c700.c

198

pcireg_t reg;

sys/arch/i386/pci/opti82c700.c

204

reg = pci_conf_read(ph->ph_pc, ph->ph_tag, addrofs);

sys/arch/i386/pci/opti82c700.c

205

val = (reg >> ofs) & FIRESTAR_CFG_PIRQ_MASK;

sys/arch/i386/pci/opti82c700.c

218

pcireg_t reg;

sys/arch/i386/pci/opti82c700.c

226

reg = pci_conf_read(ph->ph_pc, ph->ph_tag, addrofs);

sys/arch/i386/pci/opti82c700.c

227

reg &= ~(FIRESTAR_CFG_PIRQ_MASK << ofs);

sys/arch/i386/pci/opti82c700.c

228

reg |= (irq << ofs);

sys/arch/i386/pci/opti82c700.c

229

pci_conf_write(ph->ph_pc, ph->ph_tag, addrofs, reg);

sys/arch/i386/pci/opti82c700.c

239

pcireg_t reg;

sys/arch/i386/pci/opti82c700.c

253

reg = pci_conf_read(ph->ph_pc, ph->ph_tag, addrofs);

sys/arch/i386/pci/opti82c700.c

254

val = (reg >> ofs) & FIRESTAR_CFG_PIRQ_MASK;

sys/arch/i386/pci/opti82c700.c

257

val = ((reg >> ofs) >> FIRESTAR_TRIGGER_SHIFT) &

sys/arch/i386/pci/opti82c700.c

269

reg = pci_conf_read(ph->ph_pc, ph->ph_tag, addrofs);

sys/arch/i386/pci/opti82c700.c

270

val = (reg >> ofs) & FIRESTAR_CFG_PIRQ_MASK;

sys/arch/i386/pci/opti82c700.c

285

pcireg_t reg;

sys/arch/i386/pci/opti82c700.c

298

reg = pci_conf_read(ph->ph_pc, ph->ph_tag, addrofs);

sys/arch/i386/pci/opti82c700.c

299

val = (reg >> ofs) & FIRESTAR_CFG_PIRQ_MASK;

sys/arch/i386/pci/opti82c700.c

303

reg |= (FIRESTAR_TRIGGER_MASK <<

sys/arch/i386/pci/opti82c700.c

306

reg &= ~(FIRESTAR_TRIGGER_MASK <<

sys/arch/i386/pci/opti82c700.c

308

pci_conf_write(ph->ph_pc, ph->ph_tag, addrofs, reg);

sys/arch/i386/pci/opti82c700.c

318

reg = pci_conf_read(ph->ph_pc, ph->ph_tag, addrofs);

sys/arch/i386/pci/opti82c700.c

319

val = (reg >> ofs) & FIRESTAR_CFG_PIRQ_MASK;

sys/arch/i386/pci/pci_intr_fixup.c

603

int reg;

sys/arch/i386/pci/pci_intr_fixup.c

614

pciintr_icu_handle, i, &reg);

sys/arch/i386/pci/pci_intr_fixup.c

615

if (reg == IST_LEVEL)

sys/arch/i386/pci/pci_intr_fixup.c

628

reg = IST_EDGE;

sys/arch/i386/pci/pci_intr_fixup.c

630

reg = IST_LEVEL;

sys/arch/i386/pci/pci_intr_fixup.c

632

pciintr_icu_handle, i, reg);

sys/arch/i386/pci/piix.c

235

pcireg_t reg;

sys/arch/i386/pci/piix.c

244

reg = pci_conf_read(ph->ph_pc, ph->ph_tag, cfgreg);

sys/arch/i386/pci/piix.c

246

if ((reg >> shift) & PIIX_CFG_PIRQ_NONE)

sys/arch/i386/pci/piix.c

249

*irqp = PIIX_PIRQ(reg, clink);

sys/arch/i386/pci/piix.c

259

pcireg_t reg;

sys/arch/i386/pci/piix.c

268

reg = pci_conf_read(ph->ph_pc, ph->ph_tag, cfgreg);

sys/arch/i386/pci/piix.c

270

reg &= ~((PIIX_CFG_PIRQ_NONE | PIIX_CFG_PIRQ_MASK) << shift);

sys/arch/i386/pci/piix.c

271

reg |= irq << shift;

sys/arch/i386/pci/piix.c

272

pci_conf_write(ph->ph_pc, ph->ph_tag, cfgreg, reg);

sys/arch/i386/pci/piixreg.h

51

#define PIIX_PIRQ(reg, x) (((reg) >> ((x) << 3)) & 0xff)

sys/arch/i386/pci/sis85c503.c

129

pcireg_t reg;

sys/arch/i386/pci/sis85c503.c

134

reg = pci_conf_read(ph->ph_pc, ph->ph_tag,

sys/arch/i386/pci/sis85c503.c

136

reg = SIS85C503_CFG_PIRQ_REG(reg, clink);

sys/arch/i386/pci/sis85c503.c

138

if (reg & SIS85C503_CFG_PIRQ_ROUTE_DISABLE)

sys/arch/i386/pci/sis85c503.c

141

*irqp = reg & SIS85C503_CFG_PIRQ_INTR_MASK;

sys/arch/i386/pci/sis85c503.c

151

pcireg_t reg;

sys/arch/i386/pci/sis85c503.c

156

reg = pci_conf_read(ph->ph_pc, ph->ph_tag,

sys/arch/i386/pci/sis85c503.c

159

reg &= ~((SIS85C503_CFG_PIRQ_ROUTE_DISABLE |

sys/arch/i386/pci/sis85c503.c

161

reg |= (irq << shift);

sys/arch/i386/pci/sis85c503.c

163

reg);

sys/arch/i386/pci/sis85c503reg.h

45

#define SIS85C503_CFG_PIRQ_REG(reg, regofs) \

sys/arch/i386/pci/sis85c503reg.h

46

(((reg) >> SIS85C503_CFG_PIRQ_SHIFT(regofs)) & SIS85C503_CFG_PIRQ_MASK)

sys/arch/i386/pci/via8231.c

124

#define VIA8231_GET_TRIGGER_CNFG(reg, pirq) \

sys/arch/i386/pci/via8231.c

125

((reg) & (1 << (3 - (clink & 3))))

sys/arch/i386/pci/via8231.c

126

#define VIA8231_SET_TRIGGER_CNFG(reg, clink, cfg) \

sys/arch/i386/pci/via8231.c

127

(((reg) & ~(1 << (3 - (clink & 3)))) | ((cfg) << (3 - (clink & 3))))

sys/arch/i386/pci/via8231.c

129

#define VIA8231_GET_ROUTING_CNFG(reg, pirq) \

sys/arch/i386/pci/via8231.c

130

(((reg) >> via8231_routing_cnfg[(pirq)].shft) & \

sys/arch/i386/pci/via8231.c

133

#define VIA8231_SET_ROUTING_CNFG(reg, pirq, cfg) \

sys/arch/i386/pci/via8231.c

134

(((reg) & ~(via8231_routing_cnfg[(pirq)].mask << \

sys/arch/i386/pci/via8231.c

186

int reg, val;

sys/arch/i386/pci/via8231.c

192

reg = VIA8231_GET_ROUTING(ph);

sys/arch/i386/pci/via8231.c

193

val = VIA8231_GET_ROUTING_CNFG(reg, clink);

sys/arch/i386/pci/via8231.c

195

reg = VIA8237_GET_ROUTING(ph);

sys/arch/i386/pci/via8231.c

196

val = (reg >> ((clink & 3) * 4)) & 0xf;

sys/arch/i386/pci/via8231.c

209

int reg;

sys/arch/i386/pci/via8231.c

220

reg = VIA8231_GET_ROUTING(ph);

sys/arch/i386/pci/via8231.c

222

VIA8231_SET_ROUTING_CNFG(reg, clink, irq));

sys/arch/i386/pci/via8231.c

224

reg = VIA8237_GET_ROUTING(ph);

sys/arch/i386/pci/via8231.c

225

VIA8237_SET_ROUTING(ph, (reg & ~(0xf << (clink & 3))) |

sys/arch/i386/pci/via8231.c

236

int reg, clink, m, pciirq = 0; /* XXX: GCC */

sys/arch/i386/pci/via8231.c

245

reg = VIA8231_LINK_LEGAL(clink)?

sys/arch/i386/pci/via8231.c

248

*triggerp = VIA8231_GET_TRIGGER_CNFG(reg, clink)?

sys/arch/i386/pci/via8231.c

261

int reg, clink, pciirq;

sys/arch/i386/pci/via8231.c

274

reg = VIA8231_LINK_LEGAL(clink)?

sys/arch/i386/pci/via8231.c

279

reg = VIA8231_SET_TRIGGER_CNFG(reg, clink,

sys/arch/i386/pci/via8231.c

283

reg = VIA8231_SET_TRIGGER_CNFG(reg, clink,

sys/arch/i386/pci/via8231.c

290

VIA8231_SET_TRIGGER(ph, reg);

sys/arch/i386/pci/via8231.c

292

VIA8237_SET_TRIGGER(ph, reg);

sys/arch/i386/pci/via82c586.c

101

#define VP3_TRIGGER(reg, pirq) (((reg) >> vp3_cfg_trigger_shift[(pirq)]) & \

sys/arch/i386/pci/via82c586.c

114

#define VP3_PIRQ(reg, pirq) (((reg) >> vp3_cfg_intr_shift[(pirq)]) & \

sys/arch/i386/pci/via82c586.c

121

pcireg_t reg;

sys/arch/i386/pci/via82c586.c

129

reg = pci_conf_read(pc, tag, VP3_CFG_KBDMISCCTRL12_REG);

sys/arch/i386/pci/via82c586.c

130

reg |= VP3_CFG_MISCCTRL2_EISA4D04D1PORT_ENABLE <<

sys/arch/i386/pci/via82c586.c

132

pci_conf_write(pc, tag, VP3_CFG_KBDMISCCTRL12_REG, reg);

sys/arch/i386/pci/via82c586.c

156

pcireg_t reg;

sys/arch/i386/pci/via82c586.c

162

reg = pci_conf_read(ph->ph_pc, ph->ph_tag, VP3_CFG_PIRQ_REG);

sys/arch/i386/pci/via82c586.c

163

val = VP3_PIRQ(reg, clink);

sys/arch/i386/pci/via82c586.c

175

pcireg_t reg;

sys/arch/i386/pci/via82c586.c

180

reg = pci_conf_read(ph->ph_pc, ph->ph_tag, VP3_CFG_PIRQ_REG);

sys/arch/i386/pci/via82c586.c

183

reg &= ~(VP3_CFG_INTR_MASK << shift);

sys/arch/i386/pci/via82c586.c

184

reg |= (irq << shift);

sys/arch/i386/pci/via82c586.c

185

pci_conf_write(ph->ph_pc, ph->ph_tag, VP3_CFG_PIRQ_REG, reg);

sys/arch/i386/pci/via82c586.c

198

pcireg_t reg;

sys/arch/i386/pci/via82c586.c

207

reg = pci_conf_read(ph->ph_pc, ph->ph_tag,

sys/arch/i386/pci/via82c586.c

209

if (VP3_TRIGGER(reg, i) == VP3_CFG_TRIGGER_EDGE)

sys/arch/i386/pci/via82c586.c

229

pcireg_t reg;

sys/arch/i386/pci/via82c586.c

237

reg = pci_conf_read(ph->ph_pc, ph->ph_tag,

sys/arch/i386/pci/via82c586.c

241

reg &= ~(VP3_CFG_TRIGGER_MASK << shift);

sys/arch/i386/pci/via82c586.c

243

reg |= (VP3_CFG_TRIGGER_EDGE << shift);

sys/arch/i386/pci/via82c586.c

245

VP3_CFG_PIRQ_REG, reg);

sys/arch/i386/pci/via82c586reg.h

39

#define VP3_CFG_MISCCTRL2_REG(reg) \

sys/arch/i386/pci/via82c586reg.h

40

(((reg) >> VP3_CFG_MISCCTRL2_SHIFT) & VP3_CFG_MISCCTRL2_MASK)

sys/arch/i386/pnpbios/lm_pnpbios.c

153

lm_pnpbios_readreg(struct lm_softc *sc, int reg)

sys/arch/i386/pnpbios/lm_pnpbios.c

155

bus_space_write_1(sc->lm_iot, sc->lm_ioh, LMC_ADDR, reg);

sys/arch/i386/pnpbios/lm_pnpbios.c

161

lm_pnpbios_writereg(struct lm_softc *sc, int reg, int val)

sys/arch/i386/pnpbios/lm_pnpbios.c

163

bus_space_write_1(sc->lm_iot, sc->lm_ioh, LMC_ADDR, reg);

sys/arch/ia64/ia64/db_interface.c

128

uint64_t *reg;

sys/arch/ia64/ia64/db_interface.c

136

reg = (uint64_t*)((uintptr_t) f + (uintptr_t)vp->valuep);

sys/arch/ia64/ia64/db_interface.c

140

*valuep = *reg;

sys/arch/ia64/ia64/db_interface.c

143

*reg = *valuep;

sys/arch/ia64/ia64/db_interface.c

188

u_int64_t *reg;

sys/arch/ia64/ia64/db_interface.c

207

reg = (void*)(bsp - ((sof - regno + nats) << 3));

sys/arch/ia64/ia64/db_interface.c

212

*valuep = *reg;

sys/arch/ia64/ia64/db_interface.c

215

*reg = *valuep;

sys/arch/ia64/ia64/process_machdep.c

40

process_read_regs(struct lwp *l, struct reg *regs)

sys/arch/ia64/ia64/process_machdep.c

48

process_write_regs(struct lwp *l, const struct reg *regs)

sys/arch/ia64/ia64/sapic.c

197

vaddr_t reg = sa->sa_registers;

sys/arch/ia64/ia64/sapic.c

199

*(volatile uint32_t *)(reg + SAPIC_APIC_EOI) = vector;

sys/arch/ia64/ia64/sapic.c

85

vaddr_t reg = sa->sa_registers;

sys/arch/ia64/ia64/sapic.c

87

*(volatile uint32_t *) (reg + SAPIC_IO_SELECT) = which;

sys/arch/ia64/ia64/sapic.c

89

return *((volatile uint32_t *)(reg + SAPIC_IO_WINDOW));

sys/arch/ia64/ia64/sapic.c

95

vaddr_t reg = sa->sa_registers;

sys/arch/ia64/ia64/sapic.c

97

*(volatile uint32_t *) (reg + SAPIC_IO_SELECT) = which;

sys/arch/ia64/ia64/sapic.c

99

*(volatile uint32_t *) (reg + SAPIC_IO_WINDOW) = value;

sys/arch/ia64/include/asm.h

151

#define MSG(msg,reg,label) \

sys/arch/ia64/include/asm.h

152

addl reg,@ltoff(label),gp;; \

sys/arch/ia64/include/asm.h

153

ld8 reg=[reg];; \

sys/arch/ia64/include/md_var.h

67

struct reg;

sys/arch/ia64/pci/pci_machdep.c

101

tag | reg, sizeof(pcireg_t), val, 0, 0, 0, 0);

sys/arch/ia64/pci/pci_machdep.c

77

pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg)

sys/arch/ia64/pci/pci_machdep.c

81

if ((unsigned int)reg >= PCI_CONF_SIZE)

sys/arch/ia64/pci/pci_machdep.c

85

tag | reg, sizeof(pcireg_t), 0, 0, 0, 0, 0);

sys/arch/ia64/pci/pci_machdep.c

93

pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t val)

sys/arch/ia64/pci/pci_machdep.c

97

if ((unsigned int)reg >= PCI_CONF_SIZE)

sys/arch/ia64/unwind/decode.c

275

uwd->X1.reg = (buf[1] & 0x1f);

sys/arch/ia64/unwind/decode.c

294

uwd->X2.reg = (buf[1] & 0x1f);

sys/arch/ia64/unwind/decode.c

314

uwd->X3.reg = (buf[1] & 0x1f);

sys/arch/ia64/unwind/decode.c

333

uwd->X4.reg = (buf[2] & 0x1f);

sys/arch/ia64/unwind/decode.h

124

u_int reg;

sys/arch/ia64/unwind/decode.h

133

u_int reg;

sys/arch/ia64/unwind/decode.h

146

u_int reg;

sys/arch/ia64/unwind/decode.h

156

u_int reg;

sys/arch/ibmnws/ibmnws/machdep.c

240

u_char reg;

sys/arch/ibmnws/ibmnws/machdep.c

246

reg = *(volatile u_char *)(PREP_BUS_SPACE_IO + 0x92);

sys/arch/ibmnws/ibmnws/machdep.c

247

reg &= ~1UL;

sys/arch/ibmnws/ibmnws/machdep.c

248

*(volatile u_char *)(PREP_BUS_SPACE_IO + 0x92) = reg;

sys/arch/ibmnws/ibmnws/machdep.c

252

reg = *(volatile u_char *)(PREP_BUS_SPACE_IO + 0x92);

sys/arch/ibmnws/ibmnws/machdep.c

253

reg |= 1;

sys/arch/ibmnws/ibmnws/machdep.c

254

*(volatile u_char *)(PREP_BUS_SPACE_IO + 0x92) = reg;

sys/arch/landisk/include/pci_machdep.h

77

#define pci_conf_read(v, tag, reg) \

sys/arch/landisk/include/pci_machdep.h

78

shpcic_conf_read(v, tag, reg)

sys/arch/landisk/include/pci_machdep.h

79

#define pci_conf_write(v, tag, reg, data) \

sys/arch/landisk/include/pci_machdep.h

80

shpcic_conf_write(v, tag, reg, data)

sys/arch/luna68k/stand/boot/if_le.c

115

void *reg, *mem;

sys/arch/luna68k/stand/boot/if_le.c

118

reg = addr;

sys/arch/luna68k/stand/boot/if_le.c

123

cookie = lance_attach(unit, reg, mem, eaddr);

sys/arch/luna68k/stand/boot/lance.c

295

uint16_t reg;

sys/arch/luna68k/stand/boot/lance.c

309

reg = lereg->ler_rdp;

sys/arch/luna68k/stand/boot/lance.c

311

printf("le: init timeout (CSR=0x%x)\n", reg);

sys/arch/luna68k/stand/boot/lance.c

315

} while ((reg & LE_C0_IDON) == 0);

sys/arch/luna68k/stand/boot/lance.c

77

lance_attach(int unit, void *reg, void *mem, uint8_t *eaddr)

sys/arch/luna68k/stand/boot/lance.c

91

sc->sc_reg = reg;

sys/arch/luna68k/stand/boot/sio.c

256

sioreg(int reg, int val)

sys/arch/luna68k/stand/boot/sio.c

260

chan = CHANNEL(reg);

sys/arch/luna68k/stand/boot/sio.c

262

if (isStatusReg(reg)) {

sys/arch/luna68k/stand/boot/sio.c

263

if (REGNO(reg) != 0)

sys/arch/luna68k/stand/boot/sio.c

264

sio_addr[chan]->sio_cmd = REGNO(reg);

sys/arch/luna68k/stand/boot/sio.c

267

if (REGNO(reg) != 0)

sys/arch/luna68k/stand/boot/sio.c

268

sio_addr[chan]->sio_cmd = REGNO(reg);

sys/arch/m68k/fpe/fpu_calcea.c

301

int *reg;

sys/arch/m68k/fpe/fpu_calcea.c

382

reg = NULL;

sys/arch/m68k/fpe/fpu_calcea.c

395

reg = &frame->f_regs[ea->ea_regnum];

sys/arch/m68k/fpe/fpu_calcea.c

400

*reg -= step;

sys/arch/m68k/fpe/fpu_calcea.c

405

src = (char *)*reg;

sys/arch/m68k/fpe/fpu_calcea.c

422

*reg += step;

sys/arch/m68k/fpe/fpu_calcea.c

442

int *reg;

sys/arch/m68k/fpe/fpu_calcea.c

517

reg = &(frame->f_regs[ea->ea_regnum]);

sys/arch/m68k/fpe/fpu_calcea.c

523

*reg -= step;

sys/arch/m68k/fpe/fpu_calcea.c

528

sig = calc_ea(ea, (char *)*reg, &dst);

sys/arch/m68k/fpe/fpu_calcea.c

537

*reg += step;

sys/arch/m68k/fpsp/fpsp.h

163

FPSR_SHADOW equ LV-64 ;fpsr shadow reg

sys/arch/m68k/fpsp/fpsp.h

165

FPIARCU equ LV-60 ;Instr. addr. reg. for CU (4 bytes)

sys/arch/m68k/fpsp/fpsp.h

167

CMDREG2B equ LV-52 ;cmd reg for machine 2

sys/arch/m68k/fpsp/fpsp.h

168

CMDREG3B equ LV-48 ;cmd reg for E3 exceptions (2 bytes)

sys/arch/m68k/fpsp/fpsp.h

198

CMDREG1B equ LV-36 ;cmd reg for E1 exceptions (2 bytes)

sys/arch/m68k/include/asm.h

262

#define EXTBL(reg) \

sys/arch/m68k/include/asm.h

263

extw reg ; \

sys/arch/m68k/include/asm.h

264

extl reg

sys/arch/m68k/include/asm.h

266

#define EXTBL(reg) \

sys/arch/m68k/include/asm.h

267

extbl reg

sys/arch/m68k/include/asm.h

81

#define LEA_LCL(name,reg) \

sys/arch/m68k/include/asm.h

82

movl __IMMEDIATE name - .,reg ; \

sys/arch/m68k/include/asm.h

83

lea (-6,%pc,reg),reg

sys/arch/m68k/include/asm.h

84

#define GOT_SETUP(reg) \

sys/arch/m68k/include/asm.h

85

movl __IMMEDIATE _GLOBAL_OFFSET_TABLE_@GOTPC,reg ; \

sys/arch/m68k/include/asm.h

86

lea (-6,%pc,reg),reg

sys/arch/m68k/include/asm.h

88

#define LEA_LCL(name,reg) lea (name,%pc),reg

sys/arch/m68k/include/asm.h

89

#define GOT_SETUP(reg) lea (_GLOBAL_OFFSET_TABLE_@GOTPC,%pc),reg

sys/arch/m68k/include/asm.h

93

#define LEA_LCL(name,reg) movl __IMMEDIATE name,reg

sys/arch/m68k/include/asm.h

94

#define GOT_SETUP(reg) /* nothing */

sys/arch/m68k/include/reg.h

103

int process_read_regs(struct lwp *, struct reg *);

sys/arch/m68k/m68k/core_machdep.c

65

struct reg intreg;

sys/arch/m68k/m68k/db_disasm.c

1837

const char *reg;

sys/arch/m68k/m68k/db_disasm.c

1840

reg = "???";

sys/arch/m68k/m68k/db_disasm.c

1854

reg = "tt0";

sys/arch/m68k/m68k/db_disasm.c

1857

reg = "tt1";

sys/arch/m68k/m68k/db_disasm.c

1865

reg = "tc";

sys/arch/m68k/m68k/db_disasm.c

1869

reg = "drp";

sys/arch/m68k/m68k/db_disasm.c

1873

reg = "srp";

sys/arch/m68k/m68k/db_disasm.c

1877

reg = "crp";

sys/arch/m68k/m68k/db_disasm.c

1881

reg = "cal";

sys/arch/m68k/m68k/db_disasm.c

1885

reg = "val";

sys/arch/m68k/m68k/db_disasm.c

1889

reg = "scc";

sys/arch/m68k/m68k/db_disasm.c

1893

reg = "ac";

sys/arch/m68k/m68k/db_disasm.c

1900

reg = "mmusr";

sys/arch/m68k/m68k/db_disasm.c

1903

reg = "pcsr";

sys/arch/m68k/m68k/db_disasm.c

1906

reg = "bad";

sys/arch/m68k/m68k/db_disasm.c

1909

reg = "bac";

sys/arch/m68k/m68k/db_disasm.c

1935

addstr(dbuf, reg);

sys/arch/m68k/m68k/db_disasm.c

2329

int disp, odisp, bd, od, reg;

sys/arch/m68k/m68k/db_disasm.c

2335

reg = BITFIELD(*dbuf->val, bit, bit-2);

sys/arch/m68k/m68k/db_disasm.c

2338

reg = BITFIELD(*dbuf->val, bit-3, bit-5);

sys/arch/m68k/m68k/db_disasm.c

2340

reg = BITFIELD(*dbuf->val, bit, bit-2);

sys/arch/m68k/m68k/db_disasm.c

2347

PRINT_DREG(dbuf, reg);

sys/arch/m68k/m68k/db_disasm.c

2349

PRINT_AREG(dbuf, reg);

sys/arch/m68k/m68k/db_disasm.c

2352

print_disp(dbuf, *(dbuf->val + 1 + dd), SIZE_WORD,reg);

sys/arch/m68k/m68k/db_disasm.c

2361

PRINT_AREG(dbuf, reg);

sys/arch/m68k/m68k/db_disasm.c

2368

if (reg == 0) {

sys/arch/m68k/m68k/db_disasm.c

2375

} else if (reg == 1) {

sys/arch/m68k/m68k/db_disasm.c

2382

} else if (reg == 2) {

sys/arch/m68k/m68k/db_disasm.c

2389

} else if (reg == 4) {

sys/arch/m68k/m68k/db_disasm.c

2483

PRINT_AREG(dbuf,reg);

sys/arch/m68k/m68k/db_disasm.c

2489

PRINT_AREG(dbuf, reg);

sys/arch/m68k/m68k/db_disasm.c

2534

int disp, odisp, bd, od, reg;

sys/arch/m68k/m68k/db_disasm.c

2539

reg = BITFIELD(*dbuf->val, bit, bit-2);

sys/arch/m68k/m68k/db_disasm.c

2542

reg = BITFIELD(*dbuf->val, bit-3, bit-5);

sys/arch/m68k/m68k/db_disasm.c

2544

reg = BITFIELD(*dbuf->val, bit, bit-2);

sys/arch/m68k/m68k/db_disasm.c

2551

PRINT_DREG(dbuf, reg);

sys/arch/m68k/m68k/db_disasm.c

2553

PRINT_AREG(dbuf, reg);

sys/arch/m68k/m68k/db_disasm.c

2562

PRINT_AREG(dbuf, reg);

sys/arch/m68k/m68k/db_disasm.c

2570

print_disp(dbuf, disp, SIZE_WORD, reg);

sys/arch/m68k/m68k/db_disasm.c

2576

if (reg == 0) {

sys/arch/m68k/m68k/db_disasm.c

2581

} else if (reg == 1) {

sys/arch/m68k/m68k/db_disasm.c

2586

} else if (reg == 2) {

sys/arch/m68k/m68k/db_disasm.c

2593

} else if (reg == 4) {

sys/arch/m68k/m68k/db_disasm.c

2678

PRINT_AREG(dbuf, reg);

sys/arch/m68k/m68k/db_disasm.c

2909

get_areg_val(int reg)

sys/arch/m68k/m68k/db_disasm.c

84

static u_long get_areg_val(int reg);

sys/arch/m68k/m68k/db_disasm.h

424

#define PRINT_FPREG(dbuf, reg) addstr(dbuf, fpregs[reg])

sys/arch/m68k/m68k/db_disasm.h

425

#define PRINT_DREG(dbuf, reg) addstr(dbuf, dregs[reg])

sys/arch/m68k/m68k/db_disasm.h

426

#define PRINT_AREG(dbuf, reg) addstr(dbuf, aregs[reg])

sys/arch/m68k/m68k/process_machdep.c

112

process_write_regs(struct lwp *l, const struct reg *regs)

sys/arch/m68k/m68k/process_machdep.c

87

process_read_regs(struct lwp *l, struct reg *regs)

sys/arch/mac68k/dev/adbvar.h

83

#define ADBLISTEN(dev, reg) ((((u_int8_t)dev & 0x0f) << 4) | 0x08 | reg)

sys/arch/mac68k/dev/adbvar.h

84

#define ADBTALK(dev, reg) ((((u_int8_t)dev & 0x0f) << 4) | 0x0c | reg)

sys/arch/mac68k/dev/if_mcvar.h

41

#define NIC_GET(sc, reg) (bus_space_read_1((sc)->sc_regt, \

sys/arch/mac68k/dev/if_mcvar.h

42

(sc)->sc_regh, MACE_REG(reg)))

sys/arch/mac68k/dev/if_mcvar.h

44

#define NIC_PUT(sc, reg, val) (bus_space_write_1((sc)->sc_regt, \

sys/arch/mac68k/dev/if_mcvar.h

45

(sc)->sc_regh, MACE_REG(reg), (val)))

sys/arch/mac68k/dev/zs.c

734

zs_read_reg(struct zs_chanstate *cs, uint8_t reg)

sys/arch/mac68k/dev/zs.c

738

*cs->cs_reg_csr = reg;

sys/arch/mac68k/dev/zs.c

746

zs_write_reg(struct zs_chanstate *cs, uint8_t reg, uint8_t val)

sys/arch/mac68k/dev/zs.c

748

*cs->cs_reg_csr = reg;

sys/arch/mac68k/include/adbsys.h

160

int reg; /* register to which to send bytes */

sys/arch/mac68k/nubus/cpi_nubus.c

637

uint8_t reg;

sys/arch/mac68k/nubus/cpi_nubus.c

644

reg = z8536_reg_get(sc->sc_bst, sc->sc_bsh, Z8536_MCCR);

sys/arch/mac68k/nubus/cpi_nubus.c

646

reg & ~(MCCR_CT1E | MCCR_CT2E));

sys/arch/mac68k/nubus/cpi_nubus.c

664

reg = z8536_reg_get(sc->sc_bst, sc->sc_bsh, Z8536_MCCR);

sys/arch/mac68k/nubus/cpi_nubus.c

665

z8536_reg_set(sc->sc_bst, sc->sc_bsh, Z8536_MCCR, reg | MCCR_CT1CT2);

sys/arch/mac68k/nubus/cpi_nubus.c

668

reg = z8536_reg_get(sc->sc_bst, sc->sc_bsh, Z8536_MCCR);

sys/arch/mac68k/nubus/cpi_nubus.c

670

reg | (MCCR_CT1E | MCCR_CT2E));

sys/arch/mac68k/nubus/cpi_nubus.c

673

reg = z8536_reg_get(sc->sc_bst, sc->sc_bsh, Z8536_CTCSR1);

sys/arch/mac68k/nubus/cpi_nubus.c

675

CTCSR_MASK(reg | CTCS_TCB | CTCS_GCB));

sys/arch/mac68k/nubus/cpi_nubus.c

679

reg = z8536_reg_get(sc->sc_bst, sc->sc_bsh, Z8536_CTCSR1);

sys/arch/mac68k/nubus/cpi_nubus.c

680

printf("Counter 1 CTCSR setup bits are 0x%03x\n", reg);

sys/arch/mac68k/nubus/cpi_nubus.c

683

reg = z8536_reg_get(sc->sc_bst, sc->sc_bsh, Z8536_CTCSR2);

sys/arch/mac68k/nubus/cpi_nubus.c

684

printf("Counter 2 CTCSR setup bits are 0x%03x\n", reg);

sys/arch/mac68k/nubus/cpi_nubus.c

710

reg = z8536_reg_get(sc->sc_bst, sc->sc_bsh, Z8536_CTCSR1);

sys/arch/mac68k/nubus/cpi_nubus.c

711

printf("Counter 1 CTCSR setup bits are 0x%03x\n", reg);

sys/arch/mac68k/nubus/cpi_nubus.c

714

reg = z8536_reg_get(sc->sc_bst, sc->sc_bsh, Z8536_CTCSR2);

sys/arch/mac68k/nubus/cpi_nubus.c

715

printf("Counter 2 CTCSR setup bits are 0x%03x\n", reg);

sys/arch/mac68k/nubus/cpi_nubus.c

726

uint8_t reg;

sys/arch/mac68k/nubus/cpi_nubus.c

760

reg = bus_space_read_1(bst, bsh, CIO_CTRL);

sys/arch/mac68k/nubus/cpi_nubus.c

762

bus_space_write_1(bst, bsh, CIO_CTRL, CTCSR_MASK(reg | CTCS_RCC));

sys/arch/mac68k/nubus/cpi_nubus.c

775

reg = bus_space_read_1(bst, bsh, CIO_CTRL);

sys/arch/mac68k/nubus/cpi_nubus.c

777

bus_space_write_1(bst, bsh, CIO_CTRL, CTCSR_MASK(reg |CTCS_RCC));

sys/arch/mac68k/nubus/cpi_nubus.c

790

reg = bus_space_read_1(bst, bsh, CIO_CTRL);

sys/arch/mac68k/nubus/cpi_nubus.c

792

bus_space_write_1(bst, bsh, CIO_CTRL, CTCSR_MASK(reg | CTCS_RCC));

sys/arch/mac68k/nubus/cpi_nubus.c

817

uint8_t reg;

sys/arch/mac68k/nubus/cpi_nubus.c

826

reg = bus_space_read_1(bst, bsh, CIO_CTRL);

sys/arch/mac68k/nubus/cpi_nubus.c

828

bus_space_write_1(bst, bsh, CIO_CTRL, CTCSR_MASK(reg | CTCS_RCC));

sys/arch/mac68k/nubus/cpi_nubus.c

846

uint8_t reg;

sys/arch/mac68k/nubus/cpi_nubus.c

855

reg = bus_space_read_1(bst, bsh, CIO_CTRL);

sys/arch/mac68k/nubus/cpi_nubus.c

857

bus_space_write_1(bst, bsh, CIO_CTRL, CTCSR_MASK(reg | CTCS_RCC));

sys/arch/mac68k/nubus/cpi_nubus.c

874

uint8_t reg, uint8_t val)

sys/arch/mac68k/nubus/cpi_nubus.c

879

bus_space_write_1(bspace, bhandle, CIO_CTRL, reg);

sys/arch/mac68k/nubus/cpi_nubus.c

886

z8536_reg_get(bus_space_tag_t bspace, bus_space_handle_t bhandle, uint8_t reg)

sys/arch/mac68k/nubus/cpi_nubus.c

892

bus_space_write_1(bspace, bhandle, CIO_CTRL, reg);

sys/arch/mac68k/obio/esp.c

421

esp_read_reg(struct ncr53c9x_softc *sc, int reg)

sys/arch/mac68k/obio/esp.c

425

return esc->sc_reg[reg * 16];

sys/arch/mac68k/obio/esp.c

429

esp_write_reg(struct ncr53c9x_softc *sc, int reg, uint8_t val)

sys/arch/mac68k/obio/esp.c

434

if (reg == NCR_CMD && v == (NCRCMD_TRANS|NCRCMD_DMA)) {

sys/arch/mac68k/obio/esp.c

437

esc->sc_reg[reg * 16] = v;

sys/arch/mac68k/obio/esp.c

575

esp_dma_write_reg(struct ncr53c9x_softc *sc, int reg, uint8_t val)

sys/arch/mac68k/obio/esp.c

579

esc->sc_reg[reg * 16] = val;

sys/arch/mac68k/obio/iwm_fd.c

474

int reg, flags, spl;

sys/arch/mac68k/obio/iwm_fd.c

478

for (reg = 0; reg < 0x10; reg++) {

sys/arch/mac68k/obio/iwm_fd.c

479

flags = iwmQueryDrvFlag(fd->unit, reg);

sys/arch/mac68k/obio/iwm_fd.c

480

printf("iwm: Drive register 0x%x = 0x%x\n", reg, flags);

sys/arch/macppc/dev/adb_direct.c

334

uint8_t reg;

sys/arch/macppc/dev/adb_direct.c

339

reg = read_via_reg(VIA1, vIFR); /* Read the interrupts */

sys/arch/macppc/dev/adb_direct.c

340

if ((reg & 0x80) == 0) {

sys/arch/macppc/dev/adb_direct.c

345

write_via_reg(VIA1, vIFR, reg & 0x7f); /* Clear 'em */

sys/arch/macppc/dev/adbvar.h

89

#define ADBLISTEN(dev, reg) ((((u_int8_t)(dev) & 0x0f) << 4) | 0x08 | (reg))

sys/arch/macppc/dev/adbvar.h

90

#define ADBTALK(dev, reg) ((((u_int8_t)(dev) & 0x0f) << 4) | 0x0c | (reg))

sys/arch/macppc/dev/awacs.c

1249

uint32_t reg;

sys/arch/macppc/dev/awacs.c

1250

reg = awacs_read_reg(sc, AWACS_CODEC_STATUS);

sys/arch/macppc/dev/awacs.c

1251

DPRINTF("%s: codec status reg %08x\n", device_xname(sc->sc_dev), reg);

sys/arch/macppc/dev/awacs.c

1252

return ((reg & sc->sc_headphones_mask) == sc->sc_headphones_in);

sys/arch/macppc/dev/awacs.c

575

awacs_read_reg(struct awacs_softc *sc, int reg)

sys/arch/macppc/dev/awacs.c

578

return bus_space_read_4(sc->sc_tag, sc->sc_regh, reg);

sys/arch/macppc/dev/awacs.c

582

awacs_write_reg(struct awacs_softc *sc, int reg, int val)

sys/arch/macppc/dev/awacs.c

585

bus_space_write_4(sc->sc_tag, sc->sc_regh, reg, val);

sys/arch/macppc/dev/battery.c

118

uint32_t reg;

sys/arch/macppc/dev/battery.c

124

reg = in32rb(0xf3000034);

sys/arch/macppc/dev/battery.c

125

DPRINTF("reg: %08x\n", reg);

sys/arch/macppc/dev/battery.c

126

if (reg & 0x20000000) {

sys/arch/macppc/dev/cuda.c

327

uint8_t reg;

sys/arch/macppc/dev/cuda.c

329

reg = cuda_read_reg(sc, vDirB);

sys/arch/macppc/dev/cuda.c

330

reg |= 0x30; /* register B bits 4 and 5: outputs */

sys/arch/macppc/dev/cuda.c

331

cuda_write_reg(sc, vDirB, reg);

sys/arch/macppc/dev/cuda.c

333

reg = cuda_read_reg(sc, vDirB);

sys/arch/macppc/dev/cuda.c

334

reg &= 0xf7; /* register B bit 3: input */

sys/arch/macppc/dev/cuda.c

335

cuda_write_reg(sc, vDirB, reg);

sys/arch/macppc/dev/cuda.c

337

reg = cuda_read_reg(sc, vACR);

sys/arch/macppc/dev/cuda.c

338

reg &= ~vSR_OUT; /* make sure SR is set to IN */

sys/arch/macppc/dev/cuda.c

339

cuda_write_reg(sc, vACR, reg);

sys/arch/macppc/dev/cuda.c

485

uint8_t reg;

sys/arch/macppc/dev/cuda.c

487

reg = cuda_read_reg(sc, vBufB);

sys/arch/macppc/dev/cuda.c

488

reg |= (vPB4 | vPB5);

sys/arch/macppc/dev/cuda.c

489

cuda_write_reg(sc, vBufB, reg);

sys/arch/macppc/dev/cuda.c

495

uint8_t reg;

sys/arch/macppc/dev/cuda.c

497

reg = cuda_read_reg(sc, vBufB);

sys/arch/macppc/dev/cuda.c

498

reg &= ~vPB5;

sys/arch/macppc/dev/cuda.c

499

cuda_write_reg(sc, vBufB, reg);

sys/arch/macppc/dev/cuda.c

505

uint8_t reg;

sys/arch/macppc/dev/cuda.c

507

reg = cuda_read_reg(sc, vBufB);

sys/arch/macppc/dev/cuda.c

508

reg |= vPB5;

sys/arch/macppc/dev/cuda.c

509

cuda_write_reg(sc, vBufB, reg);

sys/arch/macppc/dev/cuda.c

515

uint8_t reg;

sys/arch/macppc/dev/cuda.c

517

reg = cuda_read_reg(sc, vACR);

sys/arch/macppc/dev/cuda.c

518

reg &= ~vSR_OUT;

sys/arch/macppc/dev/cuda.c

519

cuda_write_reg(sc, vACR, reg);

sys/arch/macppc/dev/cuda.c

525

uint8_t reg;

sys/arch/macppc/dev/cuda.c

527

reg = cuda_read_reg(sc, vACR);

sys/arch/macppc/dev/cuda.c

528

reg |= vSR_OUT;

sys/arch/macppc/dev/cuda.c

529

cuda_write_reg(sc, vACR, reg);

sys/arch/macppc/dev/cuda.c

535

uint8_t reg;

sys/arch/macppc/dev/cuda.c

537

reg = cuda_read_reg(sc, vBufB);

sys/arch/macppc/dev/cuda.c

538

reg ^= vPB4;

sys/arch/macppc/dev/cuda.c

539

cuda_write_reg(sc, vBufB, reg);

sys/arch/macppc/dev/cuda.c

545

uint8_t reg;

sys/arch/macppc/dev/cuda.c

547

reg = cuda_read_reg(sc, vBufB);

sys/arch/macppc/dev/cuda.c

548

reg |= vPB4;

sys/arch/macppc/dev/cuda.c

549

cuda_write_reg(sc, vBufB, reg);

sys/arch/macppc/dev/cuda.c

563

uint8_t reg;

sys/arch/macppc/dev/cuda.c

565

reg = cuda_read_reg(sc, vIFR); /* Read the interrupts */

sys/arch/macppc/dev/cuda.c

567

if ((reg & 0x80) == 0) {

sys/arch/macppc/dev/cuda.c

568

DPRINTF("irq %02x]", reg);

sys/arch/macppc/dev/drivebay.c

214

drivebay_writereg(struct drivebay_softc *sc, int reg, uint32_t val)

sys/arch/macppc/dev/drivebay.c

220

cmd = reg;

sys/arch/macppc/dev/drivebay.c

224

if (reg == PCAGPIO_OUTPUT) sc->sc_state = val;

sys/arch/macppc/dev/drivebay.c

229

drivebay_readreg(struct drivebay_softc *sc, int reg)

sys/arch/macppc/dev/drivebay.c

235

if (reg == PCAGPIO_INPUT) {

sys/arch/macppc/dev/drivebay.c

241

cmd = reg;

sys/arch/macppc/dev/drivebay.c

246

if (reg == PCAGPIO_INPUT) {

sys/arch/macppc/dev/drivebay.c

258

int reg = drivebay_readreg(sc, PCAGPIO_INPUT);

sys/arch/macppc/dev/drivebay.c

259

int power = (reg & I_POWER) != 0;

sys/arch/macppc/dev/drivebay.c

267

reg = sc->sc_state;

sys/arch/macppc/dev/drivebay.c

268

if (power != 0) reg |= O_POWER;

sys/arch/macppc/dev/drivebay.c

269

else reg &= ~O_POWER;

sys/arch/macppc/dev/drivebay.c

271

if (reg != sc->sc_state) {

sys/arch/macppc/dev/drivebay.c

272

drivebay_writereg(sc, PCAGPIO_OUTPUT, reg);

sys/arch/macppc/dev/drivebay.c

273

sc->sc_state = reg;

sys/arch/macppc/dev/drivebay.c

293

int reg = drivebay_readreg(sc, PCAGPIO_INPUT);

sys/arch/macppc/dev/drivebay.c

294

int inuse = (reg & I_INUSE) != 0;

sys/arch/macppc/dev/drivebay.c

302

reg = sc->sc_state;

sys/arch/macppc/dev/drivebay.c

303

if (inuse != 0) reg |= O_INUSE;

sys/arch/macppc/dev/drivebay.c

304

else reg &= ~O_INUSE;

sys/arch/macppc/dev/drivebay.c

306

if (reg != sc->sc_state) {

sys/arch/macppc/dev/drivebay.c

307

drivebay_writereg(sc, PCAGPIO_OUTPUT, reg);

sys/arch/macppc/dev/drivebay.c

308

sc->sc_state = reg;

sys/arch/macppc/dev/drivebay.c

328

int reg = sc->sc_state;

sys/arch/macppc/dev/drivebay.c

329

int fail = (reg & O_FAIL) != 0;

sys/arch/macppc/dev/drivebay.c

337

reg = sc->sc_state;

sys/arch/macppc/dev/drivebay.c

338

if (fail != 0) reg |= O_FAIL;

sys/arch/macppc/dev/drivebay.c

339

else reg &= ~O_FAIL;

sys/arch/macppc/dev/drivebay.c

341

if (reg != sc->sc_state) {

sys/arch/macppc/dev/drivebay.c

342

drivebay_writereg(sc, PCAGPIO_OUTPUT, reg);

sys/arch/macppc/dev/drivebay.c

343

sc->sc_state = reg;

sys/arch/macppc/dev/drivebay.c

363

int reg = drivebay_readreg(sc, PCAGPIO_INPUT);

sys/arch/macppc/dev/drivebay.c

364

int present = (reg & I_PRESENT) == 0;

sys/arch/macppc/dev/drivebay.c

384

int reg = drivebay_readreg(sc, PCAGPIO_INPUT);

sys/arch/macppc/dev/drivebay.c

385

int sw = (reg & I_SWITCH) == 0;

sys/arch/macppc/dev/esp.c

162

u_int *reg;

sys/arch/macppc/dev/esp.c

178

reg = ca->ca_reg;

sys/arch/macppc/dev/esp.c

179

esc->sc_reg = mapiodev(ca->ca_baseaddr + reg[0], reg[1], false);

sys/arch/macppc/dev/esp.c

180

esc->sc_dmareg = mapiodev(ca->ca_baseaddr + reg[2], reg[3], false);

sys/arch/macppc/dev/esp.c

252

esp_read_reg(struct ncr53c9x_softc *sc, int reg)

sys/arch/macppc/dev/esp.c

256

return in8(&esc->sc_reg[reg * 16]);

sys/arch/macppc/dev/esp.c

261

esp_write_reg(struct ncr53c9x_softc *sc, int reg, uint8_t val)

sys/arch/macppc/dev/esp.c

266

out8(&esc->sc_reg[reg * 16], v);

sys/arch/macppc/dev/fcu.c

207

uint32_t reg_rpm = 0x10, reg_pwm = 0x32, reg;

sys/arch/macppc/dev/fcu.c

222

reg = reg_rpm;

sys/arch/macppc/dev/fcu.c

226

reg = reg_pwm;

sys/arch/macppc/dev/fcu.c

230

s->private = reg;

sys/arch/macppc/dev/fcu.c

246

uint32_t reg;

sys/arch/macppc/dev/fcu.c

272

if (OF_getprop(ch, "reg", &reg, sizeof(reg)) <= 0)

sys/arch/macppc/dev/fcu.c

274

s->private = reg;

sys/arch/macppc/dev/fcu.c

326

fan->reg = s->private;

sys/arch/macppc/dev/fcu.c

476

cmd = f->reg + 1;

sys/arch/macppc/dev/fcu.c

496

if (f->reg < 0x30) {

sys/arch/macppc/dev/fcu.c

502

cmd = f->reg;

sys/arch/macppc/dev/fcu.c

522

cmd = f->reg;

sys/arch/macppc/dev/fcu.c

68

int reg;

sys/arch/macppc/dev/gpio.c

112

ca2.ca_nreg = OF_getprop(child, "reg", reg, sizeof(reg));

sys/arch/macppc/dev/gpio.c

119

ca2.ca_reg = reg;

sys/arch/macppc/dev/gpio.c

91

u_int reg[20];

sys/arch/macppc/dev/if_bm.c

847

bmac_mii_readreg(device_t self, int phy, int reg, uint16_t *val)

sys/arch/macppc/dev/if_bm.c

849

return mii_bitbang_readreg(self, &bmac_mbo, phy, reg, val);

sys/arch/macppc/dev/if_bm.c

853

bmac_mii_writereg(device_t self, int phy, int reg, uint16_t val)

sys/arch/macppc/dev/if_bm.c

855

return mii_bitbang_writereg(self, &bmac_mbo, phy, reg, val);

sys/arch/macppc/dev/if_gm.c

153

uint32_t reg[10];

sys/arch/macppc/dev/if_gm.c

170

OF_getprop(node, "assigned-addresses", reg, sizeof reg);

sys/arch/macppc/dev/if_gm.c

173

sc->sc_reg = reg[2];

sys/arch/macppc/dev/if_gm.c

257

gmac_read_reg(struct gmac_softc *sc, int reg)

sys/arch/macppc/dev/if_gm.c

259

return in32rb(sc->sc_reg + reg);

sys/arch/macppc/dev/if_gm.c

263

gmac_write_reg(struct gmac_softc *sc, int reg, u_int val)

sys/arch/macppc/dev/if_gm.c

265

out32rb(sc->sc_reg + reg, val);

sys/arch/macppc/dev/if_gm.c

836

gmac_mii_readreg(device_t self, int phy, int reg, uint16_t *val)

sys/arch/macppc/dev/if_gm.c

842

0x60020000 | (phy << 23) | (reg << 18));

sys/arch/macppc/dev/if_gm.c

859

gmac_mii_writereg(device_t self, int phy, int reg, uint16_t val)

sys/arch/macppc/dev/if_gm.c

865

0x50020000 | (phy << 23) | (reg << 18) | (val & 0xffff));

sys/arch/macppc/dev/if_mc.c

110

u_int *reg;

sys/arch/macppc/dev/if_mc.c

117

reg = ca->ca_reg;

sys/arch/macppc/dev/if_mc.c

118

reg[0] += ca->ca_baseaddr;

sys/arch/macppc/dev/if_mc.c

119

reg[2] += ca->ca_baseaddr;

sys/arch/macppc/dev/if_mc.c

120

reg[4] += ca->ca_baseaddr;

sys/arch/macppc/dev/if_mc.c

122

sc->sc_txdma = mapiodev(reg[2], reg[3], false);

sys/arch/macppc/dev/if_mc.c

123

sc->sc_rxdma = mapiodev(reg[4], reg[5], false);

sys/arch/macppc/dev/if_mc.c

124

bus_space_map(sc->sc_regt, reg[0], reg[1], 0, &sc->sc_regh);

sys/arch/macppc/dev/if_mcvar.h

42

#define NIC_GET(sc, reg) (bus_space_read_1((sc)->sc_regt, \

sys/arch/macppc/dev/if_mcvar.h

43

(sc)->sc_regh, MACE_REG(reg)))

sys/arch/macppc/dev/if_mcvar.h

44

#define NIC_PUT(sc, reg, val) (bus_space_write_1((sc)->sc_regt, \

sys/arch/macppc/dev/if_mcvar.h

45

(sc)->sc_regh, MACE_REG(reg), (val)))

sys/arch/macppc/dev/kauai.c

113

int node, reg[5], i;

sys/arch/macppc/dev/kauai.c

126

if (OF_getprop(node, "assigned-addresses", reg, sizeof reg) < 12) {

sys/arch/macppc/dev/kauai.c

130

regbase = reg[2] + 0x2000;

sys/arch/macppc/dev/kauai.c

131

dmabase = reg[2] + 0x1000;

sys/arch/macppc/dev/ki2c.c

263

ki2c_readreg(struct ki2c_softc *sc, int reg)

sys/arch/macppc/dev/ki2c.c

266

return bus_space_read_1(sc->sc_tag, sc->sc_bh, sc->sc_regstep * reg);

sys/arch/macppc/dev/ki2c.c

270

ki2c_writereg(struct ki2c_softc *sc, int reg, uint8_t val)

sys/arch/macppc/dev/ki2c.c

273

bus_space_write_1(sc->sc_tag, sc->sc_bh, reg * sc->sc_regstep, val);

sys/arch/macppc/dev/lightbar.c

111

uint32_t reg[6], x;

sys/arch/macppc/dev/lightbar.c

132

OF_getprop(sc->sc_node, "reg", reg, sizeof(reg));

sys/arch/macppc/dev/lightbar.c

133

reg[0] += ca->ca_baseaddr;

sys/arch/macppc/dev/lightbar.c

134

reg[2] += ca->ca_baseaddr;

sys/arch/macppc/dev/lightbar.c

136

bus_space_map(sc->sc_tag, reg[0], reg[1], 0, &sc->sc_bsh);

sys/arch/macppc/dev/lightbar.c

137

obio_space_map(reg[2], reg[3], &sc->sc_odmah);

sys/arch/macppc/dev/lmu.c

269

lmu_get_brightness(struct lmu_softc *sc, int reg)

sys/arch/macppc/dev/lmu.c

275

if (reg > 1) return -1;

sys/arch/macppc/dev/lmu.c

277

return sc->sc_lux[reg];

sys/arch/macppc/dev/lmu.c

290

DPRINTF("<%d %04x %04x>", reg, buf[0], buf[1]);

sys/arch/macppc/dev/lmu.c

292

return (sc->sc_lux[reg]);

sys/arch/macppc/dev/mediabay.c

167

u_int reg[20], intr[5];

sys/arch/macppc/dev/mediabay.c

238

ca.ca_nreg = OF_getprop(child, "reg", reg, sizeof(reg));

sys/arch/macppc/dev/mediabay.c

244

ca.ca_reg = reg;

sys/arch/macppc/dev/mesh.c

207

u_int *reg;

sys/arch/macppc/dev/mesh.c

210

reg = ca->ca_reg;

sys/arch/macppc/dev/mesh.c

211

reg[0] += ca->ca_baseaddr;

sys/arch/macppc/dev/mesh.c

212

reg[2] += ca->ca_baseaddr;

sys/arch/macppc/dev/mesh.c

213

sc->sc_reg = mapiodev(reg[0], reg[1], false);

sys/arch/macppc/dev/mesh.c

215

sc->sc_dmareg = mapiodev(reg[2], reg[3], false);

sys/arch/macppc/dev/mesh.c

280

mesh_read_reg(struct mesh_softc *sc, int reg)

sys/arch/macppc/dev/mesh.c

282

return in8(sc->sc_reg + reg);

sys/arch/macppc/dev/mesh.c

286

mesh_set_reg(struct mesh_softc *sc, int reg, int val)

sys/arch/macppc/dev/mesh.c

288

out8(sc->sc_reg + reg, val);

sys/arch/macppc/dev/nvram.c

107

int *reg = ca->ca_reg;

sys/arch/macppc/dev/nvram.c

115

sc->nv_data = mapiodev(ca->ca_baseaddr + reg[0], reg[1], false);

sys/arch/macppc/dev/nvram.c

120

sc->nv_port = mapiodev(ca->ca_baseaddr + reg[0], reg[1], false);

sys/arch/macppc/dev/nvram.c

121

sc->nv_data = mapiodev(ca->ca_baseaddr + reg[2], reg[3], false);

sys/arch/macppc/dev/obio.c

1017

uint32_t reg;

sys/arch/macppc/dev/obio.c

1019

reg = obio_read_4(OBIO_PUSHBUTTON);

sys/arch/macppc/dev/obio.c

1020

DPRINTF("PB %08x\n", reg);

sys/arch/macppc/dev/obio.c

1026

if (reg & OBIO_BUTTON_1) {

sys/arch/macppc/dev/obio.c

1028

} else if (reg & OBIO_BUTTON_0)

sys/arch/macppc/dev/obio.c

1039

uint32_t reg;

sys/arch/macppc/dev/obio.c

1041

reg = obio_read_4(OBIO_PUSHBUTTON);

sys/arch/macppc/dev/obio.c

1043

obio_write_4(OBIO_PUSHBUTTON, reg | 0xf);

sys/arch/macppc/dev/obio.c

1044

if ((reg & 0xf) != 0)

sys/arch/macppc/dev/obio.c

168

u_int reg[20];

sys/arch/macppc/dev/obio.c

214

if (OF_getprop(node, "assigned-addresses", reg, sizeof(reg)) < 20)

sys/arch/macppc/dev/obio.c

219

if (OF_getprop(node, "assigned-addresses", reg, sizeof(reg)) < 12)

sys/arch/macppc/dev/obio.c

234

ca.ca_baseaddr = reg[2];

sys/arch/macppc/dev/obio.c

294

ca.ca_nreg = OF_getprop(child, "reg", reg, sizeof(reg));

sys/arch/macppc/dev/obio.c

306

ca.ca_reg = reg;

sys/arch/macppc/dev/obio.c

452

uint32_t gpio_base, reg[6];

sys/arch/macppc/dev/obio.c

461

if (OF_getprop(node, "reg", reg, sizeof(reg)) < 4)

sys/arch/macppc/dev/obio.c

464

gpio_base = reg[0];

sys/arch/macppc/dev/obio.c

519

if (OF_getprop(child, "reg", reg, sizeof(reg)) < 4)

sys/arch/macppc/dev/obio.c

528

if (reg[0] >= gpio_base)

sys/arch/macppc/dev/obio.c

529

reg[0] -= gpio_base;

sys/arch/macppc/dev/obio.c

532

DPRINTF("found frequency_gpio at %02x\n", reg[0]);

sys/arch/macppc/dev/obio.c

533

sc->sc_busspeed = gpio_base + reg[0];

sys/arch/macppc/dev/obio.c

536

DPRINTF("found voltage_gpio at %02x\n", reg[0]);

sys/arch/macppc/dev/obio.c

537

sc->sc_voltage = gpio_base + reg[0];

sys/arch/macppc/dev/obio.c

540

DPRINTF("found cpu-vcore-select at %02x\n", reg[0]);

sys/arch/macppc/dev/obio.c

541

sc->sc_voltage = gpio_base + reg[0];

sys/arch/macppc/dev/obio.c

545

led_attach("indicator", (void *)(gpio_base + reg[0]),

sys/arch/macppc/dev/obio.c

551

sysctl_gpio, 1, (void *)(reg[0] + gpio_base), 0, CTL_HW,

sys/arch/macppc/dev/obio.c

793

int reg = (int)node.sysctl_data;

sys/arch/macppc/dev/obio.c

795

DPRINTF("%s: reg %x\n", __func__, reg);

sys/arch/macppc/dev/obio.c

796

val = obio_read_1(reg);

sys/arch/macppc/dev/obio.c

811

int reg = (int)node.sysctl_data;

sys/arch/macppc/dev/obio.c

813

val = obio_read_4(reg);

sys/arch/macppc/dev/obio.c

814

DPRINTF("%s: reg %x %08x\n", __func__, reg, val);

sys/arch/macppc/dev/obio.c

864

uint32_t reg = (uint32_t)cookie;

sys/arch/macppc/dev/obio.c

866

return ((obio_read_1(reg) & GPIO_LEVEL) != 0);

sys/arch/macppc/dev/obio.c

872

uint32_t reg = (uint32_t)cookie;

sys/arch/macppc/dev/obio.c

873

uint8_t gpio = obio_read_1(reg);

sys/arch/macppc/dev/obio.c

879

obio_write_1(reg, gpio);

sys/arch/macppc/dev/obio.c

927

uint32_t reg, mask;

sys/arch/macppc/dev/obio.c

932

reg = obio_read_4(0x30);

sys/arch/macppc/dev/obio.c

933

return (reg & mask) >> shift;

sys/arch/macppc/dev/obio.c

939

uint32_t reg, mask;

sys/arch/macppc/dev/obio.c

944

reg = obio_read_4(0x30);

sys/arch/macppc/dev/obio.c

945

reg &= ~mask;

sys/arch/macppc/dev/obio.c

946

reg |= (pwm & 0xff) << shift;

sys/arch/macppc/dev/obio.c

947

obio_write_4(0x30, reg);

sys/arch/macppc/dev/ofw_i2c_machdep.c

58

uint32_t reg;

sys/arch/macppc/dev/ofw_i2c_machdep.c

68

if (OF_getprop(node, "reg", &reg, sizeof(reg)) != sizeof(reg)) {

sys/arch/macppc/dev/ofw_i2c_machdep.c

73

if (OF_getprop(node, "i2c-address", &reg,

sys/arch/macppc/dev/ofw_i2c_machdep.c

74

sizeof(reg)) != sizeof(reg)) {

sys/arch/macppc/dev/ofw_i2c_machdep.c

82

addr = __SHIFTOUT(reg, OFW_I2C_ADDRESS_MASK);

sys/arch/macppc/dev/ofw_i2c_machdep.c

83

channel = __SHIFTOUT(reg, OFW_I2C_ADDRESS_CHMASK);

sys/arch/macppc/dev/platinumfb.c

285

platinumfb_write_reg(struct platinumfb_softc *sc, int reg, uint32_t val)

sys/arch/macppc/dev/platinumfb.c

287

out32(sc->sc_reg + PLATINUM_REG_OFFSET_ADDR(reg), val);

sys/arch/macppc/dev/platinumfb.c

292

platinumfb_read_reg(struct platinumfb_softc *sc, int reg)

sys/arch/macppc/dev/platinumfb.c

294

return in32(sc->sc_reg + PLATINUM_REG_OFFSET_ADDR(reg));

sys/arch/macppc/dev/platinumfb.c

321

uint8_t reg, uint8_t r, uint8_t g, uint8_t b)

sys/arch/macppc/dev/platinumfb.c

323

platinumfb_write_cmap_reg(sc, PLATINUM_CMAP_ADDR_OFFSET, reg);

sys/arch/macppc/dev/platinumfb.c

471

u_int *reg = ca->ca_reg;

sys/arch/macppc/dev/platinumfb.c

476

sc->sc_reg = (uint8_t *)reg[0];

sys/arch/macppc/dev/platinumfb.c

477

sc->sc_reg_size = reg[1];

sys/arch/macppc/dev/platinumfb.c

479

sc->sc_fb = (uint8_t *)reg[2];

sys/arch/macppc/dev/pmu.c

581

volatile uint8_t reg;

sys/arch/macppc/dev/pmu.c

583

reg = pmu_read_reg(sc, vACR);

sys/arch/macppc/dev/pmu.c

584

reg &= ~vSR_OUT;

sys/arch/macppc/dev/pmu.c

585

reg |= 0x0c;

sys/arch/macppc/dev/pmu.c

586

pmu_write_reg(sc, vACR, reg);

sys/arch/macppc/dev/pmu.c

592

volatile uint8_t reg;

sys/arch/macppc/dev/pmu.c

594

reg = pmu_read_reg(sc, vACR);

sys/arch/macppc/dev/pmu.c

595

reg |= vSR_OUT;

sys/arch/macppc/dev/pmu.c

596

reg |= 0x0c;

sys/arch/macppc/dev/pmu.c

597

pmu_write_reg(sc, vACR, reg);

sys/arch/macppc/dev/pmu.c

603

volatile uint8_t reg;

sys/arch/macppc/dev/pmu.c

605

reg = pmu_read_reg(sc, vBufB);

sys/arch/macppc/dev/pmu.c

606

reg &= ~vPB4;

sys/arch/macppc/dev/pmu.c

607

pmu_write_reg(sc, vBufB, reg);

sys/arch/macppc/dev/pmu.c

613

volatile uint8_t reg;

sys/arch/macppc/dev/pmu.c

615

reg = pmu_read_reg(sc, vBufB);

sys/arch/macppc/dev/pmu.c

616

reg |= vPB4;

sys/arch/macppc/dev/pmu.c

617

pmu_write_reg(sc, vBufB, reg);

sys/arch/macppc/dev/smu.c

244

int node, parent, reg[4], gpio_base, irq;

sys/arch/macppc/dev/smu.c

259

reg, sizeof(reg)) < sizeof(reg))

sys/arch/macppc/dev/smu.c

262

sc->sc_dbell_mbox = reg[3];

sys/arch/macppc/dev/smu.c

275

if (OF_getprop(node, "reg", reg, sizeof(reg)) <= 0)

sys/arch/macppc/dev/smu.c

281

sc->sc_dbell_gpio = gpio_base + reg[0];

sys/arch/macppc/dev/smu.c

313

if (OF_getprop(node, "reg", &fan->reg,

sys/arch/macppc/dev/smu.c

314

sizeof(fan->reg)) <= 0)

sys/arch/macppc/dev/smu.c

342

fan->location, fan->reg, fan->zone, fan->rpm_ctl,

sys/arch/macppc/dev/smu.c

384

if (OF_getprop(node, "reg", &iicbus->reg, sizeof(iicbus->reg)) <= 0)

sys/arch/macppc/dev/smu.c

387

DPRINTF("iicbus: reg %x\n", iicbus->reg);

sys/arch/macppc/dev/smu.c

408

int i, sensors, child, reg;

sys/arch/macppc/dev/smu.c

433

if (OF_getprop(child, "reg", &reg, 4) == 0) goto next;

sys/arch/macppc/dev/smu.c

438

sme_sensor->private = reg;

sys/arch/macppc/dev/smu.c

441

printf("%s: %s@%x\n", loc, type, reg);

sys/arch/macppc/dev/smu.c

65

int reg;

sys/arch/macppc/dev/smu.c

661

cmd.data[1] = fan->reg;

sys/arch/macppc/dev/smu.c

675

fan->current_rpm = (cmd.data[1 + fan->reg * 2] << 8) |

sys/arch/macppc/dev/smu.c

676

cmd.data[2 + fan->reg * 2];

sys/arch/macppc/dev/smu.c

721

cmd.data[1] = fan->reg;

sys/arch/macppc/dev/smu.c

730

cmd.data[1] = 1 << fan->reg;

sys/arch/macppc/dev/smu.c

731

cmd.data[2] = cmd.data[2 + fan->reg * 2] = (rpm >> 8) & 0xff;

sys/arch/macppc/dev/smu.c

732

cmd.data[3] = cmd.data[3 + fan->reg * 2] = rpm & 0xff;

sys/arch/macppc/dev/smu.c

771

cmd.data[0] = iicbus->reg;

sys/arch/macppc/dev/smu.c

80

int reg;

sys/arch/macppc/dev/smusat.c

159

if (OF_getprop(node, "reg", &sensor->reg,

sys/arch/macppc/dev/smusat.c

160

sizeof(sensor->reg)) <= 0)

sys/arch/macppc/dev/smusat.c

163

if ((sensor->reg < 0x30) || (sensor->reg > 0x37))

sys/arch/macppc/dev/smusat.c

165

sensor->reg -= 0x30;

sys/arch/macppc/dev/smusat.c

189

sensor->location, sensor->reg, sensor->zone, type);

sys/arch/macppc/dev/smusat.c

341

u_char reg = 0x3f;

sys/arch/macppc/dev/smusat.c

345

ret = iic_exec(sc->sc_i2c, I2C_OP_READ, sc->sc_addr, &reg, 1, sc->sc_cache, 16, 0);

sys/arch/macppc/dev/smusat.c

360

int ret, reg;

sys/arch/macppc/dev/smusat.c

368

reg = sensor->reg << 1;

sys/arch/macppc/dev/smusat.c

369

sensor->current_value = (sc->sc_cache[reg] << 8) + sc->sc_cache[reg + 1];

sys/arch/macppc/dev/smusat.c

63

int reg;

sys/arch/macppc/dev/snapper.c

1525

uint8_t reg;

sys/arch/macppc/dev/snapper.c

1535

reg = snapper_basstab[i];

sys/arch/macppc/dev/snapper.c

1543

reg = (reg >> 1) + 5; // map 0x72 -> 0x3E (0 dB)

sys/arch/macppc/dev/snapper.c

1546

tas3004_write(sc, mode, &reg);

sys/arch/macppc/dev/snapper.c

1644

u_int reg = 0, x;

sys/arch/macppc/dev/snapper.c

1656

reg = CLKSRC_45MHz;

sys/arch/macppc/dev/snapper.c

1664

reg = CLKSRC_49MHz;

sys/arch/macppc/dev/snapper.c

1679

reg |= MCLK_DIV1;

sys/arch/macppc/dev/snapper.c

1682

reg |= MCLK_DIV3;

sys/arch/macppc/dev/snapper.c

1685

reg |= MCLK_DIV5;

sys/arch/macppc/dev/snapper.c

1688

reg |= ((mdiv / 2 - 1) << 24) & 0x1f000000;

sys/arch/macppc/dev/snapper.c

1694

reg |= SCLK_DIV1;

sys/arch/macppc/dev/snapper.c

1697

reg |= SCLK_DIV3;

sys/arch/macppc/dev/snapper.c

1700

reg |= ((sdiv / 2 - 1) << 20) & 0x00f00000;

sys/arch/macppc/dev/snapper.c

1704

reg |= SCLK_MASTER; /* XXX master mode */

sys/arch/macppc/dev/snapper.c

1706

reg |= SERIAL_64x;

sys/arch/macppc/dev/snapper.c

1743

if (x == reg)

sys/arch/macppc/dev/snapper.c

1747

bus_space_read_4(sc->sc_tag, sc->sc_bsh, + I2S_FORMAT), reg);

sys/arch/macppc/dev/snapper.c

1765

bus_space_write_4(sc->sc_tag, sc->sc_bsh, I2S_FORMAT, reg);

sys/arch/macppc/dev/snapper.c

1846

tas3004_write(struct snapper_softc *sc, u_int reg, const void *data)

sys/arch/macppc/dev/snapper.c

1854

KASSERT(reg < sizeof tas3004_regsize);

sys/arch/macppc/dev/snapper.c

1855

size = tas3004_regsize[reg];

sys/arch/macppc/dev/snapper.c

1858

DPRINTF("reg: %x, %d %d\n", reg, size, ((const char*)data)[0]);

sys/arch/macppc/dev/snapper.c

1860

regblock[0] = reg;

sys/arch/macppc/dev/snapper.c

1863

if (reg == DEQ_MIXER_L || reg == DEQ_MIXER_R)

sys/arch/macppc/dev/snapper.c

1865

else if (reg == DEQ_DRC || reg == DEQ_ACR ||

sys/arch/macppc/dev/snapper.c

1866

reg == DEQ_MCR2) {

sys/arch/macppc/dev/snapper.c

2008

#define DEQ_WRITE(sc, reg, addr) \

sys/arch/macppc/dev/snapper.c

2009

if (tas3004_write(sc, reg, addr)) goto err

sys/arch/macppc/dev/snapper.c

2071

uint32_t gpio_base, reg[1], fcreg, buf[8];

sys/arch/macppc/dev/snapper.c

2087

if (OF_getprop(gpio, "reg", reg, sizeof(reg)) == sizeof(reg))

sys/arch/macppc/dev/snapper.c

2088

gpio_base = reg[0];

sys/arch/macppc/dev/snapper.c

2106

if (OF_getprop(gpio, "reg", reg, sizeof reg)

sys/arch/macppc/dev/snapper.c

2107

== sizeof reg)

sys/arch/macppc/dev/snapper.c

2108

addr = gpio_base + reg[0];

sys/arch/macppc/dev/snapper.c

674

uint32_t intr[6], reg[6];

sys/arch/macppc/dev/snapper.c

703

OF_getprop(soundbus, "reg", reg, sizeof reg);

sys/arch/macppc/dev/snapper.c

705

if (reg[0] == 0) {

sys/arch/macppc/dev/snapper.c

706

reg[0] += ca->ca_reg[0];

sys/arch/macppc/dev/snapper.c

707

reg[2] += ca->ca_reg[2];

sys/arch/macppc/dev/snapper.c

708

reg[4] += ca->ca_reg[2];

sys/arch/macppc/dev/snapper.c

710

reg[0] += ca->ca_baseaddr;

sys/arch/macppc/dev/snapper.c

711

reg[2] += ca->ca_baseaddr;

sys/arch/macppc/dev/snapper.c

712

reg[4] += ca->ca_baseaddr;

sys/arch/macppc/dev/snapper.c

722

printf(" %08x", reg[i]);

sys/arch/macppc/dev/snapper.c

728

bus_space_map(sc->sc_tag, reg[0], reg[1], 0, &sc->sc_bsh);

sys/arch/macppc/dev/snapper.c

729

obio_space_map(reg[2], reg[3], &sc->sc_odmah);

sys/arch/macppc/dev/snapper.c

730

obio_space_map(reg[4], reg[5], &sc->sc_idmah);

sys/arch/macppc/dev/uni-n.c

109

u_int reg[20];

sys/arch/macppc/dev/uni-n.c

157

ca.ca_nreg = OF_getprop(child, "reg", reg, sizeof(reg));

sys/arch/macppc/dev/uni-n.c

164

ca.ca_reg = reg;

sys/arch/macppc/dev/valkyriefb.c

161

valkyriefb_write_reg(struct valkyriefb_softc *sc, int reg, uint8_t val)

sys/arch/macppc/dev/valkyriefb.c

163

*(sc->sc_base + VAL_REGS_OFFSET + reg) = val;

sys/arch/macppc/dev/valkyriefb.c

169

valkyriefb_read_reg(struct valkyriefb_softc *sc, int reg)

sys/arch/macppc/dev/valkyriefb.c

171

return *(sc->sc_base + VAL_REGS_OFFSET + reg);

sys/arch/macppc/dev/valkyriefb.c

177

int reg, uint8_t r, uint8_t g, uint8_t b)

sys/arch/macppc/dev/valkyriefb.c

179

*(sc->sc_base + VAL_CMAP_OFFSET + VAL_CMAP_ADDR) = reg;

sys/arch/macppc/dev/viareg.h

204

via_reg_and(int ign, int reg, int val)

sys/arch/macppc/dev/viareg.h

206

volatile uint8_t *addr = Via1Base + reg;

sys/arch/macppc/dev/viareg.h

212

via_reg_or(int ign, int reg, int val)

sys/arch/macppc/dev/viareg.h

214

volatile uint8_t *addr = Via1Base + reg;

sys/arch/macppc/dev/viareg.h

220

via_reg_xor(int ign, int reg, int val)

sys/arch/macppc/dev/viareg.h

222

volatile uint8_t *addr = Via1Base + reg;

sys/arch/macppc/dev/viareg.h

228

read_via_reg(int ign, int reg)

sys/arch/macppc/dev/viareg.h

230

volatile uint8_t *addr = Via1Base + reg;

sys/arch/macppc/dev/viareg.h

236

write_via_reg(int ign, int reg, int val)

sys/arch/macppc/dev/viareg.h

238

volatile uint8_t *addr = Via1Base + reg;

sys/arch/macppc/dev/zs.c

1027

u_int32_t reg[5];

sys/arch/macppc/dev/zs.c

1039

if (OF_getprop(escc_ch, "reg", reg, sizeof(reg)) < 4)

sys/arch/macppc/dev/zs.c

1041

zs_offset = reg[0];

sys/arch/macppc/dev/zs.c

1046

if (OF_getprop(obio, "assigned-addresses", reg, sizeof(reg)) < 12)

sys/arch/macppc/dev/zs.c

1048

zs_conschan = (void *)(reg[2] + zs_offset);

sys/arch/macppc/dev/zs.c

789

zs_read_reg(struct zs_chanstate *cs, uint8_t reg)

sys/arch/macppc/dev/zs.c

793

out8(cs->cs_reg_csr, reg);

sys/arch/macppc/dev/zs.c

801

zs_write_reg(struct zs_chanstate *cs, uint8_t reg, uint8_t val)

sys/arch/macppc/dev/zs.c

803

out8(cs->cs_reg_csr, reg);

sys/arch/macppc/dev/zs_kgdb.c

126

u_int32_t reg[5];

sys/arch/macppc/dev/zs_kgdb.c

146

if (OF_getprop(escc_ch, "reg", reg, sizeof(reg)) < 4)

sys/arch/macppc/dev/zs_kgdb.c

148

zs_offset = reg[0];

sys/arch/macppc/dev/zs_kgdb.c

153

if (OF_getprop(obio, "assigned-addresses", reg, sizeof(reg)) < 12)

sys/arch/macppc/dev/zs_kgdb.c

155

zc = (struct zschan *)(reg[2] + zs_offset);

sys/arch/macppc/include/adbsys.h

167

int reg; /* register to which to send bytes */

sys/arch/macppc/include/z8530var.h

158

uint8_t zs_read_reg(struct zs_chanstate *cs, uint8_t reg);

sys/arch/macppc/include/z8530var.h

162

void zs_write_reg(struct zs_chanstate *cs, uint8_t reg,uint8_t val);

sys/arch/macppc/macppc/autoconf.c

118

int reg;

sys/arch/macppc/macppc/autoconf.c

120

if (OF_getprop(snode, "reg", &reg, sizeof(reg)) < sizeof(reg)) {

sys/arch/macppc/macppc/autoconf.c

127

sensor_prop_name(num, sizeof(num), reg), descr);

sys/arch/macppc/macppc/cpu.c

104

int *reg = ca->ca_reg;

sys/arch/macppc/macppc/cpu.c

116

if (l == 4 && reg[0] == cpunum)

sys/arch/macppc/macppc/cpu.c

120

switch (reg[0]) {

sys/arch/macppc/macppc/interrupts.c

100

pic_base = obio_base + reg[0];

sys/arch/macppc/macppc/interrupts.c

69

uint32_t reg[5];

sys/arch/macppc/macppc/interrupts.c

91

if (OF_getprop(macio, "assigned-addresses", reg, sizeof(reg)) != 20)

sys/arch/macppc/macppc/interrupts.c

94

obio_base = reg[2];

sys/arch/macppc/macppc/interrupts.c

97

if (OF_getprop(pic, "reg", reg, 8) < 8)

sys/arch/macppc/macppc/mainbus.c

100

ca.ca_reg = reg;

sys/arch/macppc/macppc/mainbus.c

101

ca.ca_nreg = OF_getprop(node, "reg", reg, sizeof(reg));

sys/arch/macppc/macppc/mainbus.c

110

ca.ca_reg = reg;

sys/arch/macppc/macppc/mainbus.c

111

reg[0] = i;

sys/arch/macppc/macppc/mainbus.c

133

ca.ca_nreg = OF_getprop(node, "reg", reg, sizeof(reg));

sys/arch/macppc/macppc/mainbus.c

134

ca.ca_reg = reg;

sys/arch/macppc/macppc/mainbus.c

71

u_int32_t reg[4];

sys/arch/macppc/macppc/pic_heathrow.c

81

uint32_t reg[5];

sys/arch/macppc/macppc/pic_heathrow.c

94

if (OF_getprop(heathrow, "assigned-addresses", reg, sizeof(reg)) != 20)

sys/arch/macppc/macppc/pic_heathrow.c

97

obio_base = reg[2];

sys/arch/macppc/macppc/pic_ohare.c

105

obio_base = reg[2];

sys/arch/macppc/macppc/pic_ohare.c

74

uint32_t reg[5];

sys/arch/macppc/macppc/pic_ohare.c

86

if (OF_getprop(ohare, "assigned-addresses", reg, sizeof(reg)) != 20)

sys/arch/macppc/macppc/pic_ohare.c

89

obio_base = reg[2];

sys/arch/macppc/macppc/pic_ohare.c

99

if (OF_getprop(ohare2, "assigned-addresses", reg, sizeof(reg)) < 20)

sys/arch/macppc/macppc/pic_u3_ht.c

134

uint32_t reg[2];

sys/arch/macppc/macppc/pic_u3_ht.c

158

if (OF_getprop(u4, "reg", reg, sizeof(reg)) != 8)

sys/arch/macppc/macppc/pic_u3_ht.c

161

base = reg[1];

sys/arch/macppc/macppc/pic_u3_ht.c

172

if (OF_getprop(pic, "big-endian", reg, 4) > -1)

sys/arch/macppc/macppc/pic_u3_ht.c

175

if (OF_getprop(pic, "reg", reg, 8) != 8)

sys/arch/macppc/macppc/pic_u3_ht.c

178

base = reg[0];

sys/arch/macppc/macppc/pic_u3_ht.c

179

len = reg[1];

sys/arch/macppc/macppc/pic_u3_ht.c

181

if (OF_getprop(pic, "interrupts", reg, 8) > 4) {

sys/arch/macppc/macppc/pic_u3_ht.c

183

irq = reg[0];

sys/arch/macppc/macppc/pic_u3_ht.c

306

uint32_t reg[5], tmp;

sys/arch/macppc/macppc/pic_u3_ht.c

316

if (OF_getprop(parent, "reg", reg, 12) != 12)

sys/arch/macppc/macppc/pic_u3_ht.c

319

ht_reg = mapiodev(reg[1], reg[2], false);

sys/arch/macppc/macppc/pic_u3_ht.c

325

if (OF_getprop(child, "reg", reg, 4) != 4)

sys/arch/macppc/macppc/pic_u3_ht.c

328

dev_reg = ht_reg + (reg[0] & (OFW_PCI_PHYS_HI_DEVICEMASK |

sys/arch/macppc/macppc/pic_u3_ht.c

590

u3_ht_read_be(struct u3_ht_ops *u3_ht, u_int reg)

sys/arch/macppc/macppc/pic_u3_ht.c

592

volatile uint8_t *addr = u3_ht->ht_base + reg;

sys/arch/macppc/macppc/pic_u3_ht.c

598

u3_ht_write_be(struct u3_ht_ops *u3_ht, u_int reg, uint32_t val)

sys/arch/macppc/macppc/pic_u3_ht.c

600

volatile uint8_t *addr = u3_ht->ht_base + reg;

sys/arch/macppc/macppc/pic_u3_ht.c

606

u3_ht_read_le(struct u3_ht_ops *u3_ht, u_int reg)

sys/arch/macppc/macppc/pic_u3_ht.c

608

volatile uint8_t *addr = u3_ht->ht_base + reg;

sys/arch/macppc/macppc/pic_u3_ht.c

614

u3_ht_write_le(struct u3_ht_ops *u3_ht, u_int reg, uint32_t val)

sys/arch/macppc/macppc/pic_u3_ht.c

616

volatile uint8_t *addr = u3_ht->ht_base + reg;

sys/arch/macppc/macppc/pic_u3_ht.c

79

#define u3_ht_read(ptr,reg) (ptr)->ht_read(ptr, reg)

sys/arch/macppc/macppc/pic_u3_ht.c

80

#define u3_ht_write(ptr,reg,val) (ptr)->ht_write(ptr, reg, val)

sys/arch/macppc/macppc/rbus_machdep.c

100

OF_getprop(node, "assigned-addresses", reg, sizeof(reg));

sys/arch/macppc/macppc/rbus_machdep.c

102

if (reg[4] < 0x10000) {

sys/arch/macppc/macppc/rbus_machdep.c

107

start = reg[2];

sys/arch/macppc/macppc/rbus_machdep.c

108

size = reg[4];

sys/arch/macppc/macppc/rbus_machdep.c

79

int node, reg[5];

sys/arch/macppc/pci/bandit.c

134

pc->pc_addr = mapiodev(reg[0] + 0x800000, 4, false);

sys/arch/macppc/pci/bandit.c

135

pc->pc_data = mapiodev(reg[0] + 0xc00000, 8, false);

sys/arch/macppc/pci/bandit.c

160

bandit_conf_read(void *cookie, pcitag_t tag, int reg)

sys/arch/macppc/pci/bandit.c

167

if ((unsigned int)reg >= PCI_CONF_SIZE)

sys/arch/macppc/pci/bandit.c

182

x = (1 << dev) | (func << 8) | reg;

sys/arch/macppc/pci/bandit.c

184

x = tag | reg | 1;

sys/arch/macppc/pci/bandit.c

203

bandit_conf_write(void *cookie, pcitag_t tag, int reg, pcireg_t data)

sys/arch/macppc/pci/bandit.c

209

if ((unsigned int)reg >= PCI_CONF_SIZE)

sys/arch/macppc/pci/bandit.c

220

x = (1 << dev) | (func << 8) | reg;

sys/arch/macppc/pci/bandit.c

222

x = tag | reg | 1;

sys/arch/macppc/pci/bandit.c

241

chaos_conf_write(void *cookie, pcitag_t tag, int reg, pcireg_t data)

sys/arch/macppc/pci/bandit.c

84

uint32_t reg[2], busrange[2];

sys/arch/macppc/pci/bandit.c

97

if (OF_getprop(node, "reg", reg, sizeof(reg)) < 8)

sys/arch/macppc/pci/grackle.c

153

grackle_conf_read(void *cookie, pcitag_t tag, int reg)

sys/arch/macppc/pci/grackle.c

159

if ((unsigned int)reg >= PCI_CONF_SIZE)

sys/arch/macppc/pci/grackle.c

164

out32rb(pc->pc_addr, tag | reg);

sys/arch/macppc/pci/grackle.c

176

grackle_conf_write(void *cookie, pcitag_t tag, int reg, pcireg_t data)

sys/arch/macppc/pci/grackle.c

181

if ((unsigned int)reg >= PCI_CONF_SIZE)

sys/arch/macppc/pci/grackle.c

186

out32rb(pc->pc_addr, tag | reg);

sys/arch/macppc/pci/pci_machdep.c

181

pcireg_t isp, reg;

sys/arch/macppc/pci/pci_machdep.c

199

reg = pci_conf_read(pc, tag,

sys/arch/macppc/pci/pci_machdep.c

201

reg |= PCI_COMMAND_MEM_ENABLE |

sys/arch/macppc/pci/pci_machdep.c

204

reg);

sys/arch/macppc/pci/pci_machdep.c

207

reg = pci_conf_read(pc, tag, PCI_INTERRUPT_REG);

sys/arch/macppc/pci/pci_machdep.c

208

reg &= ~PCI_INTERRUPT_LINE_MASK;

sys/arch/macppc/pci/pci_machdep.c

209

reg |= 23;

sys/arch/macppc/pci/pci_machdep.c

210

pci_conf_write(pc, tag, PCI_INTERRUPT_REG, reg);

sys/arch/macppc/pci/u3.c

100

uint32_t reg[6], busrange[2], i;

sys/arch/macppc/pci/u3.c

108

if (OF_getprop(node, "reg", reg, sizeof(reg)) < 24) {

sys/arch/macppc/pci/u3.c

112

reg[1], reg[2]);

sys/arch/macppc/pci/u3.c

113

pc_data = mapiodev(reg[1], reg[2], false);

sys/arch/macppc/pci/u3.c

176

ibmcpc_conf_read(void *cookie, pcitag_t tag, int reg)

sys/arch/macppc/pci/u3.c

184

if ((unsigned int)reg >= PCI_CONF_SIZE)

sys/arch/macppc/pci/u3.c

204

x = daddr + ((devfn << 8) | reg);

sys/arch/macppc/pci/u3.c

206

x = daddr + ((devfn << 8) | reg) + (bus << 16) + 0x01000000UL;

sys/arch/macppc/pci/u3.c

215

ibmcpc_conf_write(void *cookie, pcitag_t tag, int reg, pcireg_t data)

sys/arch/macppc/pci/u3.c

223

if ((unsigned int)reg >= PCI_CONF_SIZE)

sys/arch/macppc/pci/u3.c

238

x = (u_int32_t) daddr + ((devfn << 8) | reg);

sys/arch/macppc/pci/u3.c

240

x = (u_int32_t) daddr + ((devfn << 8) | reg) + (bus << 16) +

sys/arch/macppc/pci/uninorth.c

111

if (OF_getprop(node, "reg", reg, sizeof(reg)) < 8)

sys/arch/macppc/pci/uninorth.c

165

pc->pc_addr = oea_mapiodev(reg[0] + 0x800000, 4);

sys/arch/macppc/pci/uninorth.c

166

pc->pc_data = oea_mapiodev(reg[0] + 0xc00000, 8);

sys/arch/macppc/pci/uninorth.c

170

pc->pc_addr = oea_mapiodev(reg[1] + 0x800000, 4);

sys/arch/macppc/pci/uninorth.c

171

pc->pc_data = oea_mapiodev(reg[1] + 0xc00000, 8);

sys/arch/macppc/pci/uninorth.c

191

uninorth_conf_read(void *cookie, pcitag_t tag, int reg)

sys/arch/macppc/pci/uninorth.c

199

if ((unsigned int)reg >= PCI_CONF_SIZE)

sys/arch/macppc/pci/uninorth.c

203

if (reg & 0x04)

sys/arch/macppc/pci/uninorth.c

218

x = (1 << dev) | (func << 8) | reg;

sys/arch/macppc/pci/uninorth.c

220

x = tag | reg | 1;

sys/arch/macppc/pci/uninorth.c

237

uninorth_conf_write(void *cookie, pcitag_t tag, int reg, pcireg_t data)

sys/arch/macppc/pci/uninorth.c

244

if ((unsigned int)reg >= PCI_CONF_SIZE)

sys/arch/macppc/pci/uninorth.c

248

if (reg & 0x04)

sys/arch/macppc/pci/uninorth.c

259

x = (1 << dev) | (func << 8) | reg;

sys/arch/macppc/pci/uninorth.c

261

x = tag | reg | 1;

sys/arch/macppc/pci/uninorth.c

275

uninorth_conf_read_v3(void *cookie, pcitag_t tag, int reg)

sys/arch/macppc/pci/uninorth.c

283

if ((unsigned int)reg >= PCI_CONF_SIZE)

sys/arch/macppc/pci/uninorth.c

287

if (reg & 0x04)

sys/arch/macppc/pci/uninorth.c

294

x = (1 << dev) | (func << 8) | reg;

sys/arch/macppc/pci/uninorth.c

296

x = (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) | 1;

sys/arch/macppc/pci/uninorth.c

298

x |= (reg >> 8) << 28;

sys/arch/macppc/pci/uninorth.c

316

uninorth_conf_write_v3(void *cookie, pcitag_t tag, int reg, pcireg_t data)

sys/arch/macppc/pci/uninorth.c

323

if ((unsigned int)reg >= PCI_CONF_SIZE)

sys/arch/macppc/pci/uninorth.c

327

if (reg & 0x04)

sys/arch/macppc/pci/uninorth.c

334

x = (1 << dev) | (func << 8) | reg;

sys/arch/macppc/pci/uninorth.c

336

x = (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) | 1;

sys/arch/macppc/pci/uninorth.c

338

x |= (reg >> 8) << 28;

sys/arch/macppc/pci/uninorth.c

89

uint32_t reg[2], busrange[2];

sys/arch/mips/adm5120/dev/admpci.c

317

admpci_tag_to_addr(void *v, pcitag_t tag, int reg, bus_addr_t *addrp)

sys/arch/mips/adm5120/dev/admpci.c

323

if ((unsigned int)reg >= PCI_CONF_SIZE)

sys/arch/mips/adm5120/dev/admpci.c

328

if (reg > __SHIFTOUT_MASK(ADMPCI_TAG_REGISTER_MASK))

sys/arch/mips/adm5120/dev/admpci.c

331

*addrp = 0x80000000 | tag | __SHIFTIN(reg, ADMPCI_TAG_REGISTER_MASK);

sys/arch/mips/adm5120/dev/admpci.c

337

admpci_conf_read(void *v, pcitag_t tag, int reg)

sys/arch/mips/adm5120/dev/admpci.c

345

reg);

sys/arch/mips/adm5120/dev/admpci.c

347

if (admpci_tag_to_addr(v, tag, reg, &addr) == -1)

sys/arch/mips/adm5120/dev/admpci.c

363

admpci_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data)

sys/arch/mips/adm5120/dev/admpci.c

370

reg);

sys/arch/mips/adm5120/dev/admpci.c

372

if (admpci_tag_to_addr(v, tag, reg, &addr) == -1)

sys/arch/mips/alchemy/au_timer.c

58

#define SET_PC_REG(reg, wait, val) \

sys/arch/mips/alchemy/au_timer.c

64

bus_space_write_4(st, sh, (reg), (val)); \

sys/arch/mips/alchemy/au_timer.c

66

while (bus_space_read_4(st, sh, (reg)) & (wait)) \

sys/arch/mips/alchemy/dev/augpio.c

177

bus_addr_t reg;

sys/arch/mips/alchemy/dev/augpio.c

182

reg = AUGPIO_TRIOUTCLR;

sys/arch/mips/alchemy/dev/augpio.c

186

reg = pin & out ? AUGPIO_OUTPUTSET : AUGPIO_OUTPUTCLR;

sys/arch/mips/alchemy/dev/augpio.c

191

PUTGPIO(reg, pin);

sys/arch/mips/alchemy/dev/aupci.c

328

aupci_conf_access(void *v, int dir, pcitag_t tag, int reg, pcireg_t *datap)

sys/arch/mips/alchemy/dev/aupci.c

337

if ((unsigned int)reg >= PCI_CONF_SIZE)

sys/arch/mips/alchemy/dev/aupci.c

361

bus_space_write_4(sc->sc_cfgt, h, reg, *datap);

sys/arch/mips/alchemy/dev/aupci.c

363

*datap = bus_space_read_4(sc->sc_cfgt, h, reg);

sys/arch/mips/alchemy/dev/aupci.c

384

aupci_conf_read(void *v, pcitag_t tag, int reg)

sys/arch/mips/alchemy/dev/aupci.c

388

if (aupci_conf_access(v, PCI_CFG_READ, tag, reg, &data) == false)

sys/arch/mips/alchemy/dev/aupci.c

395

aupci_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data)

sys/arch/mips/alchemy/dev/aupci.c

398

aupci_conf_access(v, PCI_CFG_WRITE, tag, reg, &data);

sys/arch/mips/alchemy/dev/ausmbus_psc.c

67

#define ausmbus_reg_read(sc, reg) \

sys/arch/mips/alchemy/dev/ausmbus_psc.c

68

bus_space_read_4(sc->sc_ctrl.psc_bust, sc->sc_ctrl.psc_bush, reg)

sys/arch/mips/alchemy/dev/ausmbus_psc.c

69

#define ausmbus_reg_write(sc, reg, val) \

sys/arch/mips/alchemy/dev/ausmbus_psc.c

70

bus_space_write_4(sc->sc_ctrl.psc_bust, sc->sc_ctrl.psc_bush, reg, \

sys/arch/mips/alchemy/dev/auspi.c

170

uint32_t reg;

sys/arch/mips/alchemy/dev/auspi.c

175

reg = GETREG(sc, AUPSC_SPICFG);

sys/arch/mips/alchemy/dev/auspi.c

177

reg &= ~(SPICFG_BRG_MASK); /* clear BRG */

sys/arch/mips/alchemy/dev/auspi.c

178

reg &= ~(SPICFG_DIV_MASK); /* use pscn_mainclock/2 */

sys/arch/mips/alchemy/dev/auspi.c

179

reg &= ~(SPICFG_PSE); /* disable port swap */

sys/arch/mips/alchemy/dev/auspi.c

180

reg &= ~(SPICFG_BI); /* clear bit clock invert */

sys/arch/mips/alchemy/dev/auspi.c

181

reg &= ~(SPICFG_CDE); /* clear clock phase delay */

sys/arch/mips/alchemy/dev/auspi.c

182

reg &= ~(SPICFG_CGE); /* clear clock gate enable */

sys/arch/mips/alchemy/dev/auspi.c

184

reg |= SPICFG_DE; /* device enable */

sys/arch/mips/alchemy/dev/auspi.c

185

reg |= SPICFG_DD; /* disable DMA */

sys/arch/mips/alchemy/dev/auspi.c

186

reg |= SPICFG_RT_1; /* 1 byte rx fifo threshold */

sys/arch/mips/alchemy/dev/auspi.c

187

reg |= SPICFG_TT_1; /* 1 byte tx fifo threshold */

sys/arch/mips/alchemy/dev/auspi.c

188

reg |= ((8-1) << SPICFG_LEN_SHIFT);/* always work in 8-bit chunks */

sys/arch/mips/alchemy/dev/auspi.c

211

reg &= ~SPICFG_BRG_MASK;

sys/arch/mips/alchemy/dev/auspi.c

212

reg |= (brg << SPICFG_BRG_SHIFT);

sys/arch/mips/alchemy/dev/auspi.c

222

reg |= 0; /* CPHA = 0, CPOL = 0 */

sys/arch/mips/alchemy/dev/auspi.c

225

reg |= SPICFG_CDE; /* CPHA = 1, CPOL = 0 */

sys/arch/mips/alchemy/dev/auspi.c

228

reg |= SPICFG_BI; /* CPHA = 0, CPOL = 1 */

sys/arch/mips/alchemy/dev/auspi.c

231

reg |= SPICFG_CDE | SPICFG_BI; /* CPHA = 1, CPOL = 1 */

sys/arch/mips/alchemy/dev/auspi.c

237

PUTREG(sc, AUPSC_SPICFG, reg);

sys/arch/mips/alchemy/dev/if_aumac.c

1004

MIICTRL_PHYADDR(phy) | MIICTRL_MIIREG(reg));

sys/arch/mips/alchemy/dev/if_aumac.c

1020

aumac_mii_writereg(device_t self, int phy, int reg, uint16_t val)

sys/arch/mips/alchemy/dev/if_aumac.c

1030

MIICTRL_PHYADDR(phy) | MIICTRL_MIIREG(reg) | MIICTRL_MW);

sys/arch/mips/alchemy/dev/if_aumac.c

995

aumac_mii_readreg(device_t self, int phy, int reg, uint16_t *val)

sys/arch/mips/atheros/dev/aevar.h

262

#define AE_READ(sc, reg) \

sys/arch/mips/atheros/dev/aevar.h

263

bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))

sys/arch/mips/atheros/dev/aevar.h

265

#define AE_WRITE(sc, reg, val) \

sys/arch/mips/atheros/dev/aevar.h

266

bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))

sys/arch/mips/atheros/dev/aevar.h

268

#define AE_SET(sc, reg, mask) \

sys/arch/mips/atheros/dev/aevar.h

269

AE_WRITE((sc), (reg), AE_READ((sc), (reg)) | (mask))

sys/arch/mips/atheros/dev/aevar.h

271

#define AE_CLR(sc, reg, mask) \

sys/arch/mips/atheros/dev/aevar.h

272

AE_WRITE((sc), (reg), AE_READ((sc), (reg)) & ~(mask))

sys/arch/mips/atheros/dev/aevar.h

274

#define AE_ISSET(sc, reg, mask) \

sys/arch/mips/atheros/dev/aevar.h

275

(AE_READ((sc), (reg)) & (mask))

sys/arch/mips/atheros/dev/argpio.c

112

uint32_t reg;

sys/arch/mips/atheros/dev/argpio.c

168

reg = GETREG(sc, GPIO_CR);

sys/arch/mips/atheros/dev/argpio.c

178

reg &= ~SERIAL(i);

sys/arch/mips/atheros/dev/argpio.c

179

reg |= INPUT(i);

sys/arch/mips/atheros/dev/argpio.c

182

reg |= INTR(i);

sys/arch/mips/atheros/dev/argpio.c

187

reg &= ~SERIAL(i);

sys/arch/mips/atheros/dev/argpio.c

188

reg &= ~INPUT(i);

sys/arch/mips/atheros/dev/argpio.c

189

reg &= ~INTR(i);

sys/arch/mips/atheros/dev/argpio.c

192

if (reg & SERIAL(i)) {

sys/arch/mips/atheros/dev/argpio.c

202

PUTREG(sc, GPIO_CR, reg);

sys/arch/mips/atheros/dev/argpio.c

215

uint32_t reg;

sys/arch/mips/atheros/dev/argpio.c

217

reg = GETREG(sc, GPIO_CR);

sys/arch/mips/atheros/dev/argpio.c

218

if (reg & (SERIAL(pin) | INTR(pin))) {

sys/arch/mips/atheros/dev/argpio.c

224

reg |= INPUT(pin);

sys/arch/mips/atheros/dev/argpio.c

226

reg &= ~INPUT(pin);

sys/arch/mips/atheros/dev/argpio.c

229

PUTREG(sc, GPIO_CR, reg);

sys/arch/mips/atheros/dev/argpio.c

237

uint32_t reg;

sys/arch/mips/atheros/dev/argpio.c

239

reg = GETREG(sc, GPIO_DO);

sys/arch/mips/atheros/dev/argpio.c

241

reg &= ~(1 << pin);

sys/arch/mips/atheros/dev/argpio.c

243

reg |= (1 << pin);

sys/arch/mips/atheros/dev/argpio.c

244

PUTREG(sc, GPIO_DO, reg);

sys/arch/mips/atheros/dev/arpci.c

131

arpci_conf_read(void *v, pcitag_t tag, int reg)

sys/arch/mips/atheros/dev/arpci.c

136

if ((unsigned int)reg >= PCI_CONF_SIZE)

sys/arch/mips/atheros/dev/arpci.c

148

tag |= reg & -4;

sys/arch/mips/atheros/dev/arpci.c

178

arpci_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data)

sys/arch/mips/atheros/dev/arpci.c

182

if ((unsigned int)reg >= PCI_CONF_SIZE)

sys/arch/mips/atheros/dev/arpci.c

194

tag |= reg & -4;

sys/arch/mips/atheros/dev/ehci_arbus.c

157

uint32_t reg = old;

sys/arch/mips/atheros/dev/ehci_arbus.c

159

reg &= ~USBMODE_CM;

sys/arch/mips/atheros/dev/ehci_arbus.c

160

reg |= USBMODE_CM_HOST;

sys/arch/mips/atheros/dev/ehci_arbus.c

161

if (reg != old)

sys/arch/mips/atheros/dev/ehci_arbus.c

162

bus_space_write_4(sc->iot, sc->ioh, ARBUS_USBMODE, reg);

sys/arch/mips/atheros/dev/if_ae.c

1858

ae_mii_readreg(device_t self, int phy, int reg, uint16_t *val)

sys/arch/mips/atheros/dev/if_ae.c

1864

addr = (phy << MIIADDR_PHY_SHIFT) | (reg << MIIADDR_REG_SHIFT);

sys/arch/mips/atheros/dev/if_ae.c

1885

ae_mii_writereg(device_t self, int phy, int reg, uint16_t val)

sys/arch/mips/atheros/dev/if_ae.c

1895

addr = (phy << MIIADDR_PHY_SHIFT) | (reg << MIIADDR_REG_SHIFT) |

sys/arch/mips/atheros/include/ar5315reg.h

147

#define AR5315_PLLC_REF_DIV(reg) ((reg) & 0x3)

sys/arch/mips/atheros/include/ar5315reg.h

148

#define AR5315_PLLC_FB_DIV(reg) (((reg) & 0x7c) >> 2)

sys/arch/mips/atheros/include/ar5315reg.h

149

#define AR5315_PLLC_DIV_2(reg) (((reg) & 0x80) >> 7)

sys/arch/mips/atheros/include/ar5315reg.h

150

#define AR5315_PLLC_CLKC(reg) (((reg) & 0x1c000) >> 14)

sys/arch/mips/atheros/include/ar5315reg.h

151

#define AR5315_PLLC_CLKM(reg) (((reg) & 0x700000) >> 20)

sys/arch/mips/atheros/include/ar5315reg.h

153

#define AR5315_CLOCKCTL_SELECT(reg) ((reg) & 0x3)

sys/arch/mips/atheros/include/ar5315reg.h

154

#define AR5315_CLOCKCTL_DIV(reg) (((reg) & 0xc) >> 2)

sys/arch/mips/cavium/dev/if_cnmac.c

435

cnmac_mii_readreg(device_t self, int phy_addr, int reg, uint16_t *val)

sys/arch/mips/cavium/dev/if_cnmac.c

439

return octsmi_read(sc->sc_smi, phy_addr, reg, val);

sys/arch/mips/cavium/dev/if_cnmac.c

443

cnmac_mii_writereg(device_t self, int phy_addr, int reg, uint16_t val)

sys/arch/mips/cavium/dev/if_cnmac.c

447

return octsmi_write(sc->sc_smi, phy_addr, reg, val);

sys/arch/mips/cavium/dev/octeon_fau.c

78

octfau_op_load_paddr(int incval, int tagwait, int reg)

sys/arch/mips/cavium/dev/octeon_fau.c

83

__SHIFTIN(reg, POW_LOAD_REG);

sys/arch/mips/cavium/dev/octeon_fau.c

93

octfau_op_store_paddr(int noadd, int reg, int64_t value)

sys/arch/mips/cavium/dev/octeon_fau.c

95

uint64_t args = POW_STORE_NOADD | __SHIFTIN(reg, POW_STORE_REG);

sys/arch/mips/cavium/dev/octeon_fauvar.h

106

int size, int reg)

sys/arch/mips/cavium/dev/octeon_fauvar.h

112

__SHIFTIN(reg, POW_IOBDMA_REG);

sys/arch/mips/cavium/dev/octeon_gmx.c

100

#define PCS_READ_8(sc, reg) \

sys/arch/mips/cavium/dev/octeon_gmx.c

101

bus_space_read_8((sc)->sc_port_gmx->sc_regt, (sc)->sc_port_pcs_regh, (reg))

sys/arch/mips/cavium/dev/octeon_gmx.c

102

#define PCS_WRITE_8(sc, reg, val) \

sys/arch/mips/cavium/dev/octeon_gmx.c

103

bus_space_write_8((sc)->sc_port_gmx->sc_regt, (sc)->sc_port_pcs_regh, (reg), (val))

sys/arch/mips/cavium/dev/octeon_gpio.c

199

bus_size_t reg;

sys/arch/mips/cavium/dev/octeon_gpio.c

202

reg = octgpio_cfg_reg(sc, pin);

sys/arch/mips/cavium/dev/octeon_gpio.c

205

value = GPIO_RD_8(sc, reg);

sys/arch/mips/cavium/dev/octeon_gpio.c

219

GPIO_WR_8(sc, reg, value);

sys/arch/mips/cavium/dev/octeon_gpio.c

58

#define GPIO_RD_8(sc, reg) \

sys/arch/mips/cavium/dev/octeon_gpio.c

59

bus_space_read_8((sc)->sc_iot, (sc)->sc_ioh, (reg))

sys/arch/mips/cavium/dev/octeon_gpio.c

60

#define GPIO_WR_8(sc, reg, val) \

sys/arch/mips/cavium/dev/octeon_gpio.c

61

bus_space_write_8((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))

sys/arch/mips/cavium/dev/octeon_intc.c

123

const u_int reg = be32toh(specifier[0]);

sys/arch/mips/cavium/dev/octeon_intc.c

125

const u_int irq = (reg * 64) + bit;

sys/arch/mips/cavium/dev/octeon_intc.c

129

sc->sc_descr, irq, reg, bit);

sys/arch/mips/cavium/dev/octeon_intc.c

151

const u_int reg = be32toh(specifier[0]);

sys/arch/mips/cavium/dev/octeon_intc.c

153

const u_int irq = (reg * 64) + bit;

sys/arch/mips/cavium/dev/octeon_smi.c

195

octsmi_read(struct octsmi_softc *sc, int phy_addr, int reg, uint16_t *val)

sys/arch/mips/cavium/dev/octeon_smi.c

203

__SHIFTIN(reg, SMI_CMD_REG_ADR));

sys/arch/mips/cavium/dev/octeon_smi.c

223

octsmi_write(struct octsmi_softc *sc, int phy_addr, int reg, uint16_t value)

sys/arch/mips/cavium/dev/octeon_smi.c

235

__SHIFTIN(reg, SMI_CMD_REG_ADR));

sys/arch/mips/cavium/dev/octeon_smi.c

249

phy_addr, reg, value);

sys/arch/mips/cavium/dev/octeon_twsi.c

102

#define _CONTROL_READ(sc, reg) \

sys/arch/mips/cavium/dev/octeon_twsi.c

103

octeon_twsi_control_read((sc), MIO_TWS_SW_TWSI_EOP_IA_##reg)

sys/arch/mips/cavium/dev/octeon_twsi.c

104

#define _CONTROL_WRITE(sc, reg, value) \

sys/arch/mips/cavium/dev/octeon_twsi.c

105

octeon_twsi_control_write((sc), MIO_TWS_SW_TWSI_EOP_IA_##reg, value)

sys/arch/mips/cavium/dev/octeon_twsi.c

511

const struct octeon_twsi_reg *reg;

sys/arch/mips/cavium/dev/octeon_twsi.c

513

reg = NULL;

sys/arch/mips/cavium/dev/octeon_twsi.c

516

reg = &octeon_twsi_regs[i];

sys/arch/mips/cavium/dev/octeon_twsi.c

519

KASSERT(reg != NULL);

sys/arch/mips/cavium/dev/octeon_twsi.c

521

octeon_twsi_debug_dumpreg(sc, reg);

sys/arch/mips/cavium/dev/octeon_twsi.c

535

const struct octeon_twsi_reg *reg)

sys/arch/mips/cavium/dev/octeon_twsi.c

540

value = octeon_twsi_reg_rd(sc, reg->offset);

sys/arch/mips/cavium/dev/octeon_twsi.c

541

snprintb(buf, sizeof(buf), reg->format, value);

sys/arch/mips/cavium/dev/octeon_twsi.c

542

printf("\t%-24s: %s\n", reg->name, buf);

sys/arch/mips/cavium/dev/octeon_xhci.c

42

#define XCTL_RD_8(sc, reg) \

sys/arch/mips/cavium/dev/octeon_xhci.c

43

bus_space_read_8((sc)->sc_iot, (sc)->sc_ioh, (reg))

sys/arch/mips/cavium/dev/octeon_xhci.c

44

#define XCTL_WR_8(sc, reg, val) \

sys/arch/mips/cavium/dev/octeon_xhci.c

45

bus_space_write_8((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))

sys/arch/mips/include/cpu.h

263

struct reg;

sys/arch/mips/include/db_machdep.h

58

typedef struct reg db_regs_t;

sys/arch/mips/include/db_machdep.h

94

int kdb_trap(int, struct reg *);

sys/arch/mips/include/db_machdep.h

97

db_set_ddb_regs(int type, struct reg *regs)

sys/arch/mips/include/locore.h

647

void cpu_pause(struct reg *);

sys/arch/mips/include/locore.h

809

#define TF_NREGS (sizeof(struct reg) / sizeof(mips_reg_t))

sys/arch/mips/include/locore.h

813

struct reg tf_registers;

sys/arch/mips/include/mipsNN.h

39

#define _MIPSNN_SHIFT(reg) __MIPSNN_SHIFT(reg)

sys/arch/mips/include/mipsNN.h

40

#define __MIPSNN_SHIFT(reg) MIPSNN_ ## reg ## _SHIFT

sys/arch/mips/include/mipsNN.h

41

#define _MIPSNN_MASK(reg) __MIPSNN_MASK(reg)

sys/arch/mips/include/mipsNN.h

42

#define __MIPSNN_MASK(reg) MIPSNN_ ## reg ## _MASK

sys/arch/mips/include/mipsNN.h

44

#define MIPSNN_GET(reg, x) \

sys/arch/mips/include/mipsNN.h

45

((unsigned)((x) & _MIPSNN_MASK(reg)) >> _MIPSNN_SHIFT(reg))

sys/arch/mips/include/mipsNN.h

46

#define MIPSNN_PUT(reg, val) \

sys/arch/mips/include/mipsNN.h

47

(((x) << _MIPSNN_SHIFT(reg)) & _MIPSNN_MASK(reg))

sys/arch/mips/ingenic/apbus.c

129

uint32_t reg, mpll, m, n, p, mclk, pclk, pdiv, cclk, cdiv;

sys/arch/mips/ingenic/apbus.c

150

reg = readreg(JZ_CPCCR);

sys/arch/mips/ingenic/apbus.c

151

pdiv = ((reg & JZ_PDIV_M) >> JZ_PDIV_S) + 1;

sys/arch/mips/ingenic/apbus.c

153

cdiv = (reg & JZ_CDIV_M) + 1;

sys/arch/mips/ingenic/apbus.c

161

reg = readreg(JZ_CLKGR1);

sys/arch/mips/ingenic/apbus.c

162

reg &= ~CLK_AHB_MON; /* AHB_MON clock */

sys/arch/mips/ingenic/apbus.c

163

writereg(JZ_CLKGR1, reg);

sys/arch/mips/ingenic/apbus.c

169

reg = readreg(JZ_OPCR);

sys/arch/mips/ingenic/apbus.c

170

reg |= OPCR_SPENDN0 | OPCR_SPENDN1;

sys/arch/mips/ingenic/apbus.c

171

writereg(JZ_OPCR, reg);

sys/arch/mips/ingenic/apbus.c

257

reg = readreg(JZ_CLKGR0);

sys/arch/mips/ingenic/apbus.c

258

reg &= ~adv->clk0;

sys/arch/mips/ingenic/apbus.c

259

writereg(JZ_CLKGR0, reg);

sys/arch/mips/ingenic/apbus.c

263

reg = readreg(JZ_CLKGR1);

sys/arch/mips/ingenic/apbus.c

264

reg &= ~adv->clk1;

sys/arch/mips/ingenic/apbus.c

265

writereg(JZ_CLKGR1, reg);

sys/arch/mips/ingenic/ingenic_dme.c

162

uint32_t reg;

sys/arch/mips/ingenic/ingenic_dme.c

166

reg = readreg(JZ_GPIO_E_BASE + JZ_GPIO_FLAG);

sys/arch/mips/ingenic/ingenic_dme.c

167

if (reg & GPIO_DME_INT_MASK) {

sys/arch/mips/ingenic/ingenic_dwctwo.c

119

uint32_t reg;

sys/arch/mips/ingenic/ingenic_dwctwo.c

147

reg = readreg(JZ_USBPCR);

sys/arch/mips/ingenic/ingenic_dwctwo.c

148

reg |= PCR_VBUSVLDEXTSEL;

sys/arch/mips/ingenic/ingenic_dwctwo.c

149

reg |= PCR_VBUSVLDEXT;

sys/arch/mips/ingenic/ingenic_dwctwo.c

150

reg |= PCR_USB_MODE;

sys/arch/mips/ingenic/ingenic_dwctwo.c

151

reg |= PCR_COMMONONN;

sys/arch/mips/ingenic/ingenic_dwctwo.c

152

reg &= ~PCR_OTG_DISABLE;

sys/arch/mips/ingenic/ingenic_dwctwo.c

153

writereg(JZ_USBPCR, reg);

sys/arch/mips/ingenic/ingenic_dwctwo.c

155

printf("JZ_USBPCR %08x\n", reg);

sys/arch/mips/ingenic/ingenic_dwctwo.c

158

reg = readreg(JZ_USBPCR1);

sys/arch/mips/ingenic/ingenic_dwctwo.c

160

printf("JZ_USBPCR1 %08x\n", reg);

sys/arch/mips/ingenic/ingenic_dwctwo.c

162

reg &= ~0xf0000000;

sys/arch/mips/ingenic/ingenic_dwctwo.c

163

reg |= PCR_SYNOPSYS;

sys/arch/mips/ingenic/ingenic_dwctwo.c

164

reg |= PCR_REFCLK_CORE;

sys/arch/mips/ingenic/ingenic_dwctwo.c

165

reg &= ~PCR_CLK_M;

sys/arch/mips/ingenic/ingenic_dwctwo.c

166

reg |= PCR_CLK_48;

sys/arch/mips/ingenic/ingenic_dwctwo.c

167

reg |= PCR_WORD_I_F0;

sys/arch/mips/ingenic/ingenic_dwctwo.c

168

reg |= PCR_WORD_I_F1;

sys/arch/mips/ingenic/ingenic_dwctwo.c

169

writereg(JZ_USBPCR1, reg);

sys/arch/mips/ingenic/ingenic_dwctwo.c

171

printf("JZ_USBPCR1 %08x\n", reg);

sys/arch/mips/ingenic/ingenic_dwctwo.c

178

reg = readreg(JZ_USBPCR);

sys/arch/mips/ingenic/ingenic_dwctwo.c

179

reg |= PCR_POR;

sys/arch/mips/ingenic/ingenic_dwctwo.c

180

writereg(JZ_USBPCR, reg);

sys/arch/mips/ingenic/ingenic_dwctwo.c

182

reg &= ~PCR_POR;

sys/arch/mips/ingenic/ingenic_dwctwo.c

183

writereg(JZ_USBPCR, reg);

sys/arch/mips/ingenic/ingenic_dwctwo.c

188

reg = readreg(JZ_OPCR);

sys/arch/mips/ingenic/ingenic_dwctwo.c

189

reg |= OPCR_SPENDN0;

sys/arch/mips/ingenic/ingenic_dwctwo.c

190

writereg(JZ_OPCR, reg);

sys/arch/mips/ingenic/ingenic_ehci.c

100

reg &= ~PCR_CLK_M;

sys/arch/mips/ingenic/ingenic_ehci.c

101

reg |= PCR_CLK_48;

sys/arch/mips/ingenic/ingenic_ehci.c

102

writereg(JZ_USBPCR1, reg);

sys/arch/mips/ingenic/ingenic_ehci.c

105

reg = readreg(JZ_OPCR);

sys/arch/mips/ingenic/ingenic_ehci.c

106

reg |= OPCR_SPENDN1;

sys/arch/mips/ingenic/ingenic_ehci.c

107

writereg(JZ_OPCR, reg);

sys/arch/mips/ingenic/ingenic_ehci.c

110

reg = readreg(JZ_USBPCR1);

sys/arch/mips/ingenic/ingenic_ehci.c

111

reg |= PCR_DMPD1;

sys/arch/mips/ingenic/ingenic_ehci.c

112

writereg(JZ_USBPCR1, reg);

sys/arch/mips/ingenic/ingenic_ehci.c

115

reg = readreg(JZ_USBPCR1);

sys/arch/mips/ingenic/ingenic_ehci.c

116

reg |= PCR_DPPD1;

sys/arch/mips/ingenic/ingenic_ehci.c

117

writereg(JZ_USBPCR1, reg);

sys/arch/mips/ingenic/ingenic_ehci.c

120

reg = readreg(JZ_USBPCR1);

sys/arch/mips/ingenic/ingenic_ehci.c

121

reg |= PCR_WORD_I_F1 | PCR_WORD_I_F0;

sys/arch/mips/ingenic/ingenic_ehci.c

122

writereg(JZ_USBPCR1, reg);

sys/arch/mips/ingenic/ingenic_ehci.c

125

reg = readreg(JZ_USBPCR);

sys/arch/mips/ingenic/ingenic_ehci.c

126

reg |= PCR_POR;

sys/arch/mips/ingenic/ingenic_ehci.c

127

writereg(JZ_USBPCR, reg);

sys/arch/mips/ingenic/ingenic_ehci.c

129

reg = readreg(JZ_USBPCR);

sys/arch/mips/ingenic/ingenic_ehci.c

130

reg &= ~(PCR_POR);

sys/arch/mips/ingenic/ingenic_ehci.c

131

writereg(JZ_USBPCR, reg);

sys/arch/mips/ingenic/ingenic_ehci.c

134

reg = readreg(JZ_SRBC);

sys/arch/mips/ingenic/ingenic_ehci.c

135

reg |= (1 << 14);

sys/arch/mips/ingenic/ingenic_ehci.c

136

writereg(JZ_SRBC, reg);

sys/arch/mips/ingenic/ingenic_ehci.c

140

reg = readreg(JZ_SRBC);

sys/arch/mips/ingenic/ingenic_ehci.c

141

reg &= ~(1 << 14);

sys/arch/mips/ingenic/ingenic_ehci.c

142

writereg(JZ_SRBC, reg);

sys/arch/mips/ingenic/ingenic_ehci.c

158

uint32_t reg;

sys/arch/mips/ingenic/ingenic_ehci.c

215

reg = bus_space_read_4(sc->iot, sc->ioh, 0xb0);

sys/arch/mips/ingenic/ingenic_ehci.c

216

reg |= 1 << 6;

sys/arch/mips/ingenic/ingenic_ehci.c

217

bus_space_write_4(sc->iot, sc->ioh, 0xb0, reg);

sys/arch/mips/ingenic/ingenic_ehci.c

80

uint32_t reg;

sys/arch/mips/ingenic/ingenic_ehci.c

89

reg = readreg(JZ_USBPCR);

sys/arch/mips/ingenic/ingenic_ehci.c

90

reg &= ~(PCR_OTG_DISABLE);

sys/arch/mips/ingenic/ingenic_ehci.c

91

writereg(JZ_USBPCR, reg);

sys/arch/mips/ingenic/ingenic_ehci.c

94

reg = readreg(JZ_USBPCR1);

sys/arch/mips/ingenic/ingenic_ehci.c

95

reg |= PCR_REFCLK_CORE;

sys/arch/mips/ingenic/ingenic_ehci.c

96

writereg(JZ_USBPCR1, reg);

sys/arch/mips/ingenic/ingenic_ehci.c

99

reg = readreg(JZ_USBPCR1);

sys/arch/mips/ingenic/ingenic_regs.h

119

writereg(uint32_t reg, uint32_t val)

sys/arch/mips/ingenic/ingenic_regs.h

121

*(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(reg) = val;

sys/arch/mips/ingenic/ingenic_regs.h

126

readreg(uint32_t reg)

sys/arch/mips/ingenic/ingenic_regs.h

129

return *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(reg);

sys/arch/mips/ingenic/ingenic_regs.h

402

uint32_t reg = JZ_GPIO_A_BASE + (g << 8);

sys/arch/mips/ingenic/ingenic_regs.h

404

writereg(reg + JZ_GPIO_INTC, mask); /* use as gpio */

sys/arch/mips/ingenic/ingenic_regs.h

405

writereg(reg + JZ_GPIO_MASKS, mask);

sys/arch/mips/ingenic/ingenic_regs.h

406

writereg(reg + JZ_GPIO_PAT1C, mask); /* make output */

sys/arch/mips/ingenic/ingenic_regs.h

413

uint32_t reg = JZ_GPIO_A_BASE + (g << 8);

sys/arch/mips/ingenic/ingenic_regs.h

415

reg += (level == 0) ? JZ_GPIO_PAT0C : JZ_GPIO_PAT0S;

sys/arch/mips/ingenic/ingenic_regs.h

416

writereg(reg, mask);

sys/arch/mips/ingenic/ingenic_regs.h

423

uint32_t reg = JZ_GPIO_A_BASE + (g << 8);

sys/arch/mips/ingenic/ingenic_regs.h

425

writereg(reg + JZ_GPIO_INTC, mask); /* use as gpio */

sys/arch/mips/ingenic/ingenic_regs.h

426

writereg(reg + JZ_GPIO_MASKC, mask); /* device mode */

sys/arch/mips/ingenic/ingenic_regs.h

427

writereg(reg + JZ_GPIO_PAT1C, mask); /* select 0 */

sys/arch/mips/ingenic/ingenic_regs.h

428

writereg(reg + JZ_GPIO_PAT0C, mask);

sys/arch/mips/ingenic/ingenic_regs.h

435

uint32_t reg = JZ_GPIO_A_BASE + (g << 8);

sys/arch/mips/ingenic/ingenic_regs.h

437

writereg(reg + JZ_GPIO_INTC, mask); /* use as gpio */

sys/arch/mips/ingenic/ingenic_regs.h

438

writereg(reg + JZ_GPIO_MASKC, mask); /* device mode */

sys/arch/mips/ingenic/ingenic_regs.h

439

writereg(reg + JZ_GPIO_PAT1C, mask); /* select 1 */

sys/arch/mips/ingenic/ingenic_regs.h

440

writereg(reg + JZ_GPIO_PAT0S, mask);

sys/arch/mips/ingenic/ingenic_regs.h

447

uint32_t reg = JZ_GPIO_A_BASE + (g << 8);

sys/arch/mips/ingenic/ingenic_regs.h

449

writereg(reg + JZ_GPIO_INTC, mask); /* use as gpio */

sys/arch/mips/ingenic/ingenic_regs.h

450

writereg(reg + JZ_GPIO_MASKC, mask); /* device mode */

sys/arch/mips/ingenic/ingenic_regs.h

451

writereg(reg + JZ_GPIO_PAT1S, mask); /* select 2 */

sys/arch/mips/ingenic/ingenic_regs.h

452

writereg(reg + JZ_GPIO_PAT0C, mask);

sys/arch/mips/ingenic/ingenic_regs.h

459

uint32_t reg = JZ_GPIO_A_BASE + (g << 8);

sys/arch/mips/ingenic/ingenic_regs.h

461

writereg(reg + JZ_GPIO_INTC, mask); /* use as gpio */

sys/arch/mips/ingenic/ingenic_regs.h

462

writereg(reg + JZ_GPIO_MASKC, mask); /* device mode */

sys/arch/mips/ingenic/ingenic_regs.h

463

writereg(reg + JZ_GPIO_PAT1S, mask); /* select 3 */

sys/arch/mips/ingenic/ingenic_regs.h

464

writereg(reg + JZ_GPIO_PAT0S, mask);

sys/arch/mips/ingenic/ingenic_regs.h

471

uint32_t reg = JZ_GPIO_A_BASE + (g << 8);

sys/arch/mips/ingenic/ingenic_regs.h

473

writereg(reg + JZ_GPIO_MASKS, mask); /* mask it */

sys/arch/mips/ingenic/ingenic_regs.h

474

writereg(reg + JZ_GPIO_INTS, mask); /* use as interrupt */

sys/arch/mips/ingenic/ingenic_regs.h

475

writereg(reg + JZ_GPIO_PAT1C, mask); /* level trigger */

sys/arch/mips/ingenic/ingenic_regs.h

476

writereg(reg + JZ_GPIO_PAT0S, mask); /* trigger on high */

sys/arch/mips/ingenic/ingenic_regs.h

477

writereg(reg + JZ_GPIO_FLAGC, mask); /* clear it */

sys/arch/mips/ingenic/ingenic_regs.h

478

writereg(reg + JZ_GPIO_MASKC, mask); /* enable it */

sys/arch/mips/ingenic/ingenic_regs.h

485

uint32_t reg = JZ_GPIO_A_BASE + (g << 8);

sys/arch/mips/ingenic/ingenic_regs.h

487

writereg(reg + JZ_GPIO_MASKS, mask); /* mask it */

sys/arch/mips/ingenic/ingenic_regs.h

488

writereg(reg + JZ_GPIO_INTS, mask); /* use as interrupt */

sys/arch/mips/ingenic/ingenic_regs.h

489

writereg(reg + JZ_GPIO_PAT1C, mask); /* level trigger */

sys/arch/mips/ingenic/ingenic_regs.h

490

writereg(reg + JZ_GPIO_PAT0C, mask); /* trigger on low */

sys/arch/mips/ingenic/ingenic_regs.h

491

writereg(reg + JZ_GPIO_FLAGC, mask); /* clear it */

sys/arch/mips/ingenic/ingenic_regs.h

492

writereg(reg + JZ_GPIO_MASKC, mask); /* enable it */

sys/arch/mips/ingenic/ingenic_regs.h

499

uint32_t reg = JZ_GPIO_A_BASE + (g << 8);

sys/arch/mips/ingenic/ingenic_regs.h

501

writereg(reg + JZ_GPIO_MASKS, mask); /* mask it */

sys/arch/mips/ingenic/ingenic_regs.h

502

writereg(reg + JZ_GPIO_INTC, mask); /* not an interrupt */

sys/arch/mips/ingenic/ingenic_regs.h

503

writereg(reg + JZ_GPIO_PAT1S, mask); /* use as input */

sys/arch/mips/ingenic/ingenic_regs.h

504

writereg(reg + JZ_GPIO_FLAGC, mask); /* clear it just in case */

sys/arch/mips/ingenic/jziic.c

193

uint32_t reg;

sys/arch/mips/ingenic/jziic.c

196

reg = bus_space_read_4(sc->sc_memt, sc->sc_memh, JZ_SMBENBST);

sys/arch/mips/ingenic/jziic.c

197

DPRINTF("status: %02x\n", reg);

sys/arch/mips/ingenic/jziic.c

198

while ((bail > 0) && (reg == 0)) {

sys/arch/mips/ingenic/jziic.c

200

reg = bus_space_read_4(sc->sc_memt, sc->sc_memh, JZ_SMBENBST);

sys/arch/mips/ingenic/jziic.c

203

return (reg != 0);

sys/arch/mips/ingenic/jziic.c

210

uint32_t reg;

sys/arch/mips/ingenic/jziic.c

213

reg = bus_space_read_4(sc->sc_memt, sc->sc_memh, JZ_SMBENBST);

sys/arch/mips/ingenic/jziic.c

214

DPRINTF("status: %02x\n", reg);

sys/arch/mips/ingenic/jziic.c

215

while ((bail > 0) && (reg != 0)) {

sys/arch/mips/ingenic/jziic.c

217

reg = bus_space_read_4(sc->sc_memt, sc->sc_memh, JZ_SMBENBST);

sys/arch/mips/ingenic/jziic.c

225

uint32_t reg;

sys/arch/mips/ingenic/jziic.c

227

reg = bus_space_read_4(sc->sc_memt, sc->sc_memh, JZ_SMBST);

sys/arch/mips/ingenic/jziic.c

228

while ((reg & JZ_MSTACT) && (bail > 0)) {

sys/arch/mips/ingenic/jziic.c

230

reg = bus_space_read_4(sc->sc_memt, sc->sc_memh, JZ_SMBST);

sys/arch/mips/ingenic/jziic.c

233

return ((reg & JZ_MSTACT) == 0);

sys/arch/mips/mips/cpu_subr.c

759

cpu_pause(struct reg *regsp)

sys/arch/mips/mips/db_interface.c

107

CTASSERT(sizeof(ddb_regs) == sizeof(struct reg));

sys/arch/mips/mips/db_interface.c

111

kdb_trap(int type, struct reg *regs)

sys/arch/mips/mips/db_interface.c

340

#define SHOW32(reg, name) SHOW32SELECT(reg, 0, name)

sys/arch/mips/mips/db_interface.c

341

#define SHOW64(reg, name) SHOW64SELECT(reg, 0, name)

sys/arch/mips/mips/db_interface.c

342

#define SHOW32SEL(reg, name) SHOW32SELECT(reg, name)

sys/arch/mips/mips/db_interface.c

343

#define SHOW64SEL(reg, name) SHOW64SELECT(reg, name)

sys/arch/mips/mips/db_interface.c

376

#define SET32(reg, name, val) \

sys/arch/mips/mips/db_interface.c

379

__asm volatile("mtc0 %0,$" ___STRING(reg) :: "r"(val)); \

sys/arch/mips/mips/db_interface.c

385

#define SET64(reg, name) MIPS64_SET64(reg, 0, name)

sys/arch/mips/mips/db_trace.c

148

struct reg * regs = &ddb_regs;

sys/arch/mips/mips/process_machdep.c

117

process_read_regs(struct lwp *l, struct reg *regs)

sys/arch/mips/mips/process_machdep.c

125

process_write_regs(struct lwp *l, const struct reg *regs)

sys/arch/mips/mips/syscall.c

121

struct reg *reg = &tf->tf_registers;

sys/arch/mips/mips/syscall.c

122

mips_reg_t *fargs = &reg->r_regs[_R_A0];

sys/arch/mips/mips/syscall.c

144

reg->r_regs[_R_PC] = mips_emul_branch(tf, pc, 0, false);

sys/arch/mips/mips/syscall.c

146

reg->r_regs[_R_PC] = pc + sizeof(uint32_t);

sys/arch/mips/mips/syscall.c

149

const mips_reg_t saved_v0 = reg->r_regs[_R_V0];

sys/arch/mips/mips/syscall.c

197

usp = reg->r_regs[_R_SP] + nsaved * sizeof(register_t);

sys/arch/mips/mips/syscall.c

237

usp = reg->r_regs[_R_SP] + 4 * sizeof(int32_t);

sys/arch/mips/mips/syscall.c

315

error = sy_invoke(callp, l, args, &reg->r_regs[_R_V0], code);

sys/arch/mips/mips/syscall.c

325

mips_reg_t tmp = reg->r_regs[_R_V0];

sys/arch/mips/mips/syscall.c

326

reg->r_regs[_R_V0 + _QUAD_LOWWORD] = (int32_t) tmp;

sys/arch/mips/mips/syscall.c

327

reg->r_regs[_R_V0 + _QUAD_HIGHWORD] = tmp >> 32;

sys/arch/mips/mips/syscall.c

336

reg->r_regs[_R_V0] =

sys/arch/mips/mips/syscall.c

337

(int32_t)(int64_t)reg->r_regs[_R_V0];

sys/arch/mips/mips/syscall.c

338

reg->r_regs[_R_V1] =

sys/arch/mips/mips/syscall.c

339

(int32_t)(int64_t)reg->r_regs[_R_V1];

sys/arch/mips/mips/syscall.c

348

reg->r_regs[_R_V0], reg->r_regs[_R_V1]);

sys/arch/mips/mips/syscall.c

350

reg->r_regs[_R_A3] = 0;

sys/arch/mips/mips/syscall.c

353

reg->r_regs[_R_V0] = saved_v0; /* restore syscall code */

sys/arch/mips/mips/syscall.c

354

reg->r_regs[_R_PC] = pc;

sys/arch/mips/mips/syscall.c

362

reg->r_regs[_R_V0] = error;

sys/arch/mips/mips/syscall.c

363

reg->r_regs[_R_A3] = 1;

sys/arch/mips/mips/trap.c

275

struct reg *regs = &ddb_regs;

sys/arch/mips/mips/trap.c

569

struct reg *regs = &ddb_regs;

sys/arch/mips/ralink/ralink_gpio.c

1443

r = gp_read(sc, ptp->pin_rise.reg);

sys/arch/mips/ralink/ralink_gpio.c

1445

gp_write(sc, ptp->pin_rise.reg, r);

sys/arch/mips/ralink/ralink_gpio.c

1447

r = gp_read(sc, ptp->pin_fall.reg);

sys/arch/mips/ralink/ralink_gpio.c

1449

gp_write(sc, ptp->pin_fall.reg, r);

sys/arch/mips/ralink/ralink_gpio.c

1469

r = gp_read(sc, ptp->pin_rise.reg);

sys/arch/mips/ralink/ralink_gpio.c

1471

gp_write(sc, ptp->pin_rise.reg, r);

sys/arch/mips/ralink/ralink_gpio.c

1475

r = gp_read(sc, ptp->pin_fall.reg);

sys/arch/mips/ralink/ralink_gpio.c

1477

gp_write(sc, ptp->pin_fall.reg, r);

sys/arch/mips/ralink/ralink_gpio.c

269

var = gp_read(sc, ptp->regname.reg); \

sys/arch/mips/ralink/ralink_gpio.c

275

gp_write(sc, ptp->regname.reg, var); \

sys/arch/mips/ralink/ralink_gpio.c

282

var = gp_read(sc, ptp->pin_dir.reg); \

sys/arch/mips/ralink/ralink_gpio.c

290

gp_write(sc, ptp->pin_dir.reg, var); \

sys/arch/mips/ralink/ralink_gpio.c

353

u_int reg;

sys/arch/mips/rmi/rmixl_gpio.c

76

#define GPIO_READ(gpio, reg) \

sys/arch/mips/rmi/rmixl_gpio.c

77

bus_space_read_4((gpio)->gpio_memt, (gpio)->gpio_memh, (reg))

sys/arch/mips/rmi/rmixl_gpio.c

78

#define GPIO_WRITE(gpio, reg, val) \

sys/arch/mips/rmi/rmixl_gpio.c

79

bus_space_write_4((gpio)->gpio_memt, (gpio)->gpio_memh, (reg), (val))

sys/arch/mips/rmi/rmixl_pcie.c

215

#define RMIXL_PCIE_BAR_INIT(reg, bar, size, align) { \

sys/arch/mips/rmi/rmixl_pcie.c

229

bar = RMIXL_PCIE_CONCAT3(RMIXL_PCIE_,reg,_BAR)(ba, 1); \

sys/arch/mips/rmi/rmixl_pcie.c

232

__STRING(reg), __STRING(reg), ba, size)); \

sys/arch/mips/rmi/rmixl_pcie.c

234

RMIXL_PCIE_CONCAT3(RMIXLS_SBC_PCIE_,reg,_BAR), bar); \

sys/arch/mips/rmi/rmixl_pcie.c

236

RMIXL_PCIE_CONCAT3(RMIXLS_SBC_PCIE_,reg,_BAR)); \

sys/arch/mips/rmi/rmixl_pcie.c

237

DPRINTF(("%s: %s BAR %#x\n", __func__, __STRING(reg), bar)); \

sys/arch/mips/rmi/rmixl_pcix.c

193

#define RMIXL_PCIX_BAR_INIT(reg, bar, size, align) { \

sys/arch/mips/rmi/rmixl_pcix.c

207

bar = RMIXL_PCIX_CONCAT3(RMIXL_PCIX_,reg,_BAR)(ba, 1); \

sys/arch/mips/rmi/rmixl_pcix.c

210

__STRING(reg), __STRING(reg), ba, size)); \

sys/arch/mips/rmi/rmixl_pcix.c

212

RMIXL_PCIX_CONCAT3(RMIXLR_SBC_PCIX_,reg,_BAR), bar); \

sys/arch/mips/rmi/rmixl_pcix.c

214

RMIXL_PCIX_CONCAT3(RMIXLR_SBC_PCIX_,reg,_BAR)); \

sys/arch/mips/rmi/rmixl_pcix.c

215

DPRINTF(("%s: %s BAR %#x\n", __func__, __STRING(reg), bar)); \

sys/arch/mips/sibyte/dev/sbjcn.c

1046

uint64_t reg;

sys/arch/mips/sibyte/dev/sbjcn.c

1051

while (((reg = READ_REG(ch->ch_input_reg)) != 0) && --timo)

sys/arch/mips/sibyte/dev/sbjcn.c

1057

"sbjcn_iflush timeout %02x\n", reg);

sys/arch/mips/sibyte/dev/sbmac.c

1127

uint64_t reg;

sys/arch/mips/sibyte/dev/sbmac.c

1218

reg = sbmac_addr2reg(sc->sbm_hwaddr);

sys/arch/mips/sibyte/dev/sbmac.c

1221

SBMAC_WRITECSR(port, reg);

sys/arch/mips/sibyte/dev/sbmac.c

1426

uint64_t reg;

sys/arch/mips/sibyte/dev/sbmac.c

1432

reg = SBMAC_READCSR(sc->sbm_rxfilter);

sys/arch/mips/sibyte/dev/sbmac.c

1433

reg |= M_MAC_ALLPKT_EN;

sys/arch/mips/sibyte/dev/sbmac.c

1434

SBMAC_WRITECSR(sc->sbm_rxfilter, reg);

sys/arch/mips/sibyte/dev/sbmac.c

1436

reg = SBMAC_READCSR(sc->sbm_rxfilter);

sys/arch/mips/sibyte/dev/sbmac.c

1437

reg &= ~M_MAC_ALLPKT_EN;

sys/arch/mips/sibyte/dev/sbmac.c

1438

SBMAC_WRITECSR(sc->sbm_rxfilter, reg);

sys/arch/mips/sibyte/dev/sbmac.c

1483

uint64_t reg = 0;

sys/arch/mips/sibyte/dev/sbmac.c

1487

reg |= (uint64_t) *(--ptr);

sys/arch/mips/sibyte/dev/sbmac.c

1488

reg <<= 8;

sys/arch/mips/sibyte/dev/sbmac.c

1489

reg |= (uint64_t) *(--ptr);

sys/arch/mips/sibyte/dev/sbmac.c

1490

reg <<= 8;

sys/arch/mips/sibyte/dev/sbmac.c

1491

reg |= (uint64_t) *(--ptr);

sys/arch/mips/sibyte/dev/sbmac.c

1492

reg <<= 8;

sys/arch/mips/sibyte/dev/sbmac.c

1493

reg |= (uint64_t) *(--ptr);

sys/arch/mips/sibyte/dev/sbmac.c

1494

reg <<= 8;

sys/arch/mips/sibyte/dev/sbmac.c

1495

reg |= (uint64_t) *(--ptr);

sys/arch/mips/sibyte/dev/sbmac.c

1496

reg <<= 8;

sys/arch/mips/sibyte/dev/sbmac.c

1497

reg |= (uint64_t) *(--ptr);

sys/arch/mips/sibyte/dev/sbmac.c

1499

return reg;

sys/arch/mips/sibyte/dev/sbmac.c

1831

uint64_t reg;

sys/arch/mips/sibyte/dev/sbmac.c

1859

reg = SBMAC_READCSR(sc->sbm_rxfilter);

sys/arch/mips/sibyte/dev/sbmac.c

1860

reg &= ~(M_MAC_MCAST_INV | M_MAC_MCAST_EN);

sys/arch/mips/sibyte/dev/sbmac.c

1861

SBMAC_WRITECSR(sc->sbm_rxfilter, reg);

sys/arch/mips/sibyte/dev/sbmac.c

1868

reg = SBMAC_READCSR(sc->sbm_rxfilter);

sys/arch/mips/sibyte/dev/sbmac.c

1869

reg |= (M_MAC_MCAST_INV | M_MAC_MCAST_EN);

sys/arch/mips/sibyte/dev/sbmac.c

1870

SBMAC_WRITECSR(sc->sbm_rxfilter, reg);

sys/arch/mips/sibyte/dev/sbmac.c

1889

reg = sbmac_addr2reg(enm->enm_addrlo);

sys/arch/mips/sibyte/dev/sbmac.c

1892

SBMAC_WRITECSR(port, reg);

sys/arch/mips/sibyte/dev/sbmac.c

1904

reg = SBMAC_READCSR(sc->sbm_rxfilter);

sys/arch/mips/sibyte/dev/sbmac.c

1905

reg |= M_MAC_MCAST_EN;

sys/arch/mips/sibyte/dev/sbmac.c

1906

SBMAC_WRITECSR(sc->sbm_rxfilter, reg);

sys/arch/mips/sibyte/dev/sbmac.c

282

sbmac_port_t reg;

sys/arch/mips/sibyte/dev/sbmac.c

284

reg = PKSEG1(sc->sbm_base + R_MAC_MDIO);

sys/arch/mips/sibyte/dev/sbmac.c

285

return (uint32_t) SBMAC_READCSR(reg);

sys/arch/mips/sibyte/dev/sbmac.c

292

sbmac_port_t reg;

sys/arch/mips/sibyte/dev/sbmac.c

294

reg = PKSEG1(sc->sbm_base + R_MAC_MDIO);

sys/arch/mips/sibyte/dev/sbmac.c

296

SBMAC_WRITECSR(reg, (val &

sys/arch/mips/sibyte/dev/sbmac.c

304

sbmac_mii_readreg(device_t self, int phy, int reg, uint16_t *val)

sys/arch/mips/sibyte/dev/sbmac.c

307

return mii_bitbang_readreg(self, &sbmac_mii_bitbang_ops, phy, reg,

sys/arch/mips/sibyte/dev/sbmac.c

315

sbmac_mii_writereg(device_t self, int phy, int reg, uint16_t val)

sys/arch/mips/sibyte/dev/sbmac.c

318

return mii_bitbang_writereg(self, &sbmac_mii_bitbang_ops, phy, reg,

sys/arch/mips/sibyte/dev/sbscn.c

1130

int reg;

sys/arch/mips/sibyte/dev/sbscn.c

1135

reg = 0xffff;

sys/arch/mips/sibyte/dev/sbscn.c

1142

reg =

sys/arch/mips/sibyte/dev/sbscn.c

1150

"sbscn_iflush timeout %02x\n", reg & 0xff);

sys/arch/mips/sibyte/include/bcm1480_regs.h

106

#define A_BCM1480_MC_REGISTER(ctlid,reg) (A_BCM1480_MC_BASE(ctlid)+(reg))

sys/arch/mips/sibyte/include/bcm1480_regs.h

239

#define A_BCM1480_DUART_CHANREG(chan,reg) (A_BCM1480_DUART(chan) \

sys/arch/mips/sibyte/include/bcm1480_regs.h

241

+ (reg))

sys/arch/mips/sibyte/include/bcm1480_regs.h

242

#define R_BCM1480_DUART_CHANREG(chan,reg) (BCM1480_DUART_CHANREG_SPACING*((chan)&1) + (reg))

sys/arch/mips/sibyte/include/bcm1480_regs.h

378

#define A_BCM1480_IMR_REGISTER(cpu,reg) (A_BCM1480_IMR_MAPPER(cpu)+(reg))

sys/arch/mips/sibyte/include/bcm1480_regs.h

419

#define A_BCM1480_IMR_ALIAS_MAILBOX_REGISTER(cpu,reg) (A_BCM1480_IMR_ALIAS_MAILBOX(cpu)+(reg))

sys/arch/mips/sibyte/include/bcm1480_regs.h

433

#define A_BCM1480_MAILBOX_REGISTER(num,reg,cpu) \

sys/arch/mips/sibyte/include/bcm1480_regs.h

437

(R_BCM1480_IMR_MAILBOX_0_CPU + reg))

sys/arch/mips/sibyte/include/bcm1480_regs.h

556

#define A_BCM1480_HR_REGISTER(idx,reg) (A_BCM1480_HR_BASE(idx) + (reg))

sys/arch/mips/sibyte/include/bcm1480_regs.h

605

#define A_BCM1480_PMI_LCL_REGISTER(idx,reg) (A_BCM1480_PMI_LCL_BASE(idx) + (reg))

sys/arch/mips/sibyte/include/bcm1480_regs.h

607

#define A_BCM1480_PMO_LCL_REGISTER(idx,reg) (A_BCM1480_PMO_LCL_BASE(idx) + (reg))

sys/arch/mips/sibyte/include/bcm1480_regs.h

727

#define A_BCM1480_HSP_REGISTER(idx,reg) (A_BCM1480_HSP_BASE(idx) + (reg))

sys/arch/mips/sibyte/include/sb1250_regs.h

185

#define A_MAC_REGISTER(macnum,reg) \

sys/arch/mips/sibyte/include/sb1250_regs.h

187

MAC_SPACING*(macnum) + (reg))

sys/arch/mips/sibyte/include/sb1250_regs.h

203

#define A_MAC_DMA_REGISTER(macnum,txrx,chan,reg) \

sys/arch/mips/sibyte/include/sb1250_regs.h

205

(reg))

sys/arch/mips/sibyte/include/sb1250_regs.h

207

#define R_MAC_DMA_REGISTER(txrx,chan,reg) \

sys/arch/mips/sibyte/include/sb1250_regs.h

209

(reg))

sys/arch/mips/sibyte/include/sb1250_regs.h

297

#define A_DUART_CHANREG(chan,reg) (A_DUART + DUART_CHANREG_SPACING*(chan) + (reg))

sys/arch/mips/sibyte/include/sb1250_regs.h

298

#define R_DUART_CHANREG(chan,reg) (DUART_CHANREG_SPACING*(chan) + (reg))

sys/arch/mips/sibyte/include/sb1250_regs.h

413

#define A_SER_REGISTER(sernum,reg) \

sys/arch/mips/sibyte/include/sb1250_regs.h

415

SER_SPACING*(sernum) + (reg))

sys/arch/mips/sibyte/include/sb1250_regs.h

425

#define A_SER_DMA_REGISTER(sernum,txrx,reg) \

sys/arch/mips/sibyte/include/sb1250_regs.h

427

(reg))

sys/arch/mips/sibyte/include/sb1250_regs.h

509

#define R_IO_EXT_REG(reg,cs) ((cs)*IO_EXT_REGISTER_SPACING + (reg))

sys/arch/mips/sibyte/include/sb1250_regs.h

597

#define A_SMB_REGISTER(idx,reg) (A_SMB_BASE(idx)+(reg))

sys/arch/mips/sibyte/include/sb1250_regs.h

724

#define A_IMR_REGISTER(cpu,reg) (A_IMR_MAPPER(cpu)+(reg))

sys/arch/mips/sibyte/include/sb1250_regs.h

749

#define A_MAILBOX_REGISTER(reg,cpu) \

sys/arch/mips/sibyte/include/sb1250_regs.h

750

(A_IMR_CPU0_BASE + (cpu * IMR_REGISTER_SPACING) + reg)

sys/arch/mips/sibyte/include/sb1250_regs.h

831

#define A_DM_REGISTER(idx,reg) (A_DM_BASE(idx) + (reg))

sys/arch/mips/sibyte/include/sb1250_regs.h

85

#define A_MC_REGISTER(ctlid,reg) (A_MC_BASE(ctlid)+(reg))

sys/arch/mips/sibyte/include/sb1250_regs.h

853

#define A_DM_CRC_REGISTER(idx,reg) (A_DM_CRC_BASE(idx) + (reg))

sys/arch/mipsco/include/z8530var.h

111

uint8_t zs_read_reg(struct zs_chanstate *cs, uint8_t reg);

sys/arch/mipsco/include/z8530var.h

115

void zs_write_reg(struct zs_chanstate *cs, uint8_t reg, uint8_t val);

sys/arch/mipsco/obio/asc.c

205

asc_read_reg(struct ncr53c9x_softc *sc, int reg)

sys/arch/mipsco/obio/asc.c

209

return bus_space_read_1(esc->sc_bst, esc->sc_bsh, reg * 4 + 3);

sys/arch/mipsco/obio/asc.c

213

asc_write_reg(struct ncr53c9x_softc *sc, int reg, uint8_t val)

sys/arch/mipsco/obio/asc.c

217

bus_space_write_1(esc->sc_bst, esc->sc_bsh, reg * 4 + 3, val);

sys/arch/mipsco/obio/mkclock.c

100

mk_read(struct mkclock_softc *sc, int reg)

sys/arch/mipsco/obio/mkclock.c

104

val = bus_space_read_1(sc->sc_bst, sc->sc_bsh, DATA_PORT + reg*4);

sys/arch/mipsco/obio/mkclock.c

109

mk_write(struct mkclock_softc *sc, int reg, int val)

sys/arch/mipsco/obio/mkclock.c

112

DATA_PORT + reg*4, bintobcd(val));

sys/arch/mipsco/obio/zs.c

481

zs_read_reg(struct zs_chanstate *cs, uint8_t reg)

sys/arch/mipsco/obio/zs.c

486

bus_space_write_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_CSR, reg);

sys/arch/mipsco/obio/zs.c

494

zs_write_reg(struct zs_chanstate *cs, uint8_t reg, uint8_t val)

sys/arch/mipsco/obio/zs.c

498

bus_space_write_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_CSR, reg);

sys/arch/mmeye/dev/mmeyepcmcia.c

464

int reg;

sys/arch/mmeye/dev/mmeyepcmcia.c

476

reg = mmeyepcmcia_read(h, MMEYEPCMCIA_IF_STATUS);

sys/arch/mmeye/dev/mmeyepcmcia.c

477

reg &= ~MMEYEPCMCIA_IF_STATUS_BUSWIDTH; /* Set bus width to 16bit */

sys/arch/mmeye/dev/mmeyepcmcia.c

479

if ((reg & MMEYEPCMCIA_IF_STATUS_CARDDETECT_MASK) ==

sys/arch/mmeye/dev/mmeyepcmcia.c

484

mmeyepcmcia_write(h, MMEYEPCMCIA_IF_STATUS, reg|MMEYEPCMCIA_IF_STATUS_RESET);

sys/arch/mmeye/dev/mmeyepcmcia.c

487

reg & ~MMEYEPCMCIA_IF_STATUS_RESET);

sys/arch/mmeye/dev/rtciic.c

191

uint16_t reg;

sys/arch/mmeye/dev/rtciic.c

197

reg = RTCIIC_READ(sc);

sys/arch/mmeye/dev/rtciic.c

198

reg &= ~RTCIIC_RW;

sys/arch/mmeye/dev/rtciic.c

199

reg |= bits;

sys/arch/mmeye/dev/rtciic.c

200

RTCIIC_WRITE(sc, reg);

sys/arch/mmeye/stand/boot/com.c

102

#define CSR_READ(base, reg) (*(volatile uint8_t *)((base) + (reg)))

sys/arch/mmeye/stand/boot/com.c

103

#define CSR_WRITE(base, reg, val) \

sys/arch/mmeye/stand/boot/com.c

105

*(volatile uint8_t *)((base) + (reg)) = (val); \

sys/arch/mmeye/stand/boot/wdvar.h

60

#define WDC_READ_REG(chp, reg) *(chp)->c_cmdreg[(reg)]

sys/arch/mmeye/stand/boot/wdvar.h

61

#define WDC_WRITE_REG(chp, reg, val) *(chp)->c_cmdreg[(reg)] = (val)

sys/arch/mmeye/stand/boot/wdvar.h

62

#define WDC_READ_CTLREG(chp, reg) (chp)->c_ctlbase[(reg)]

sys/arch/mmeye/stand/boot/wdvar.h

63

#define WDC_WRITE_CTLREG(chp, reg, val) (chp)->c_ctlbase[(reg)] = (val)

sys/arch/mmeye/stand/boot/wdvar.h

73

#define WDC_READ_REG(chp, reg) ({ \

sys/arch/mmeye/stand/boot/wdvar.h

75

*(chp)->c_cmdreg[(reg)]; \

sys/arch/mmeye/stand/boot/wdvar.h

77

#define WDC_WRITE_REG(chp, reg, val) do { \

sys/arch/mmeye/stand/boot/wdvar.h

79

*(chp)->c_cmdreg[(reg)] = (val); \

sys/arch/mmeye/stand/boot/wdvar.h

81

#define WDC_READ_CTLREG(chp, reg) ({ \

sys/arch/mmeye/stand/boot/wdvar.h

83

(chp)->c_ctlbase[(reg)]; \

sys/arch/mmeye/stand/boot/wdvar.h

85

#define WDC_WRITE_CTLREG(chp, reg, val) do { \

sys/arch/mmeye/stand/boot/wdvar.h

87

(chp)->c_ctlbase[(reg)] = (val); \

sys/arch/mvme68k/dev/pcc.c

163

uint8_t reg;

sys/arch/mvme68k/dev/pcc.c

198

reg = pcc_reg_read(sc, PCCREG_GENERAL_CONTROL) | PCC_GENCR_IEN;

sys/arch/mvme68k/dev/pcc.c

199

pcc_reg_write(sc, PCCREG_GENERAL_CONTROL, reg);

sys/arch/mvme68k/dev/pcc.c

206

reg = pcc_reg_read(sc, PCCREG_SLAVE_BASE_ADDR) & PCC_SLAVE_BASE_MASK;

sys/arch/mvme68k/dev/pcc.c

207

pcc_slave_base_addr = (bus_addr_t)reg * phys_seg_list[0].ps_end;

sys/arch/mvme68k/dev/sbic.c

115

#define SCSI_PHASE(reg) (reg&0x07)

sys/arch/mvme68k/dev/vme_pcc.c

153

uint8_t reg;

sys/arch/mvme68k/dev/vme_pcc.c

175

reg = vme1_reg_read(sc, VME1REG_SCON) & ~VME1_SCON_SYSFAIL;

sys/arch/mvme68k/dev/vme_pcc.c

176

vme1_reg_write(sc, VME1REG_SCON, reg);

sys/arch/mvme68k/dev/vme_pcc.c

179

(reg & VME1_SCON_SWITCH) ? "enabled" : "disabled");

sys/arch/mvme68k/dev/vme_pcc.c

195

reg = vme1_reg_read(sc, VME1REG_SLADDRMOD);

sys/arch/mvme68k/dev/vme_pcc.c

196

if ((reg & VME1_SLMOD_DATA) != 0)

sys/arch/mvme68k/dev/vme_pcc.c

198

if ((reg & VME1_SLMOD_PRGRM) != 0)

sys/arch/mvme68k/dev/vme_pcc.c

200

if ((reg & VME1_SLMOD_SUPER) != 0)

sys/arch/mvme68k/dev/vme_pcc.c

202

if ((reg & VME1_SLMOD_USER) != 0)

sys/arch/mvme68k/dev/vme_pcc.c

204

if ((reg & VME1_SLMOD_BLOCK) != 0)

sys/arch/mvme68k/dev/vme_pcc.c

208

if ((reg & VME1_SLMOD_SHORT) != 0) {

sys/arch/mvme68k/dev/vme_pcc.c

215

if (pcc_slave_base_addr < 0x01000000u && (reg & VME1_SLMOD_STND) != 0) {

sys/arch/mvme68k/dev/vme_pcc.c

227

if ((reg & VME1_SLMOD_EXTED) != 0) {

sys/arch/mvme68k/dev/zs.c

377

zs_read_reg(struct zs_chanstate *cs, uint8_t reg)

sys/arch/mvme68k/dev/zs.c

381

*cs->cs_reg_csr = reg;

sys/arch/mvme68k/dev/zs.c

389

zs_write_reg(struct zs_chanstate *cs, uint8_t reg, uint8_t val)

sys/arch/mvme68k/dev/zs.c

392

*cs->cs_reg_csr = reg;

sys/arch/mvme68k/include/z8530var.h

105

uint8_t zs_read_reg(struct zs_chanstate *cs, uint8_t reg);

sys/arch/mvme68k/include/z8530var.h

109

void zs_write_reg(struct zs_chanstate *cs, uint8_t reg, uint8_t val);

sys/arch/netwinder/netwinder/netwinder_machdep.c

296

#define PUTBYTE(reg, val) \

sys/arch/netwinder/netwinder/netwinder_machdep.c

297

*((volatile u_int8_t *)(base + (reg))) = (val)

sys/arch/news68k/dev/zs.c

417

zs_read_reg(struct zs_chanstate *cs, uint8_t reg)

sys/arch/news68k/dev/zs.c

421

*cs->cs_reg_csr = reg;

sys/arch/news68k/dev/zs.c

429

zs_write_reg(struct zs_chanstate *cs, uint8_t reg, uint8_t val)

sys/arch/news68k/dev/zs.c

432

*cs->cs_reg_csr = reg;

sys/arch/news68k/include/z8530var.h

104

uint8_t zs_read_reg(struct zs_chanstate *cs, uint8_t reg);

sys/arch/news68k/include/z8530var.h

108

void zs_write_reg(struct zs_chanstate *cs, uint8_t reg, uint8_t val);

sys/arch/newsmips/apbus/dmac3.c

130

struct dmac3reg *reg = sc->sc_reg;

sys/arch/newsmips/apbus/dmac3.c

132

reg->csr = DMAC3_CSR_RESET;

sys/arch/newsmips/apbus/dmac3.c

133

reg->csr = 0;

sys/arch/newsmips/apbus/dmac3.c

134

reg->intr = DMAC3_INTR_EOPIE | DMAC3_INTR_INTEN;

sys/arch/newsmips/apbus/dmac3.c

135

reg->conf = sc->sc_conf;

sys/arch/newsmips/apbus/dmac3.c

141

struct dmac3reg *reg = sc->sc_reg;

sys/arch/newsmips/apbus/dmac3.c

146

if (reg->csr & DMAC3_CSR_ENABLE)

sys/arch/newsmips/apbus/dmac3.c

164

reg->len = len;

sys/arch/newsmips/apbus/dmac3.c

165

reg->addr = addr;

sys/arch/newsmips/apbus/dmac3.c

166

reg->intr = DMAC3_INTR_EOPIE | DMAC3_INTR_INTEN;

sys/arch/newsmips/apbus/dmac3.c

167

reg->csr = DMAC3_CSR_ENABLE | direction | BURST_MODE | APAD_MODE;

sys/arch/newsmips/apbus/dmac3.c

174

struct dmac3reg *reg = sc->sc_reg;

sys/arch/newsmips/apbus/dmac3.c

177

intr = reg->intr;

sys/arch/newsmips/apbus/dmac3.c

182

conf = reg->conf;

sys/arch/newsmips/apbus/dmac3.c

183

reg->conf = conf;

sys/arch/newsmips/apbus/dmac3.c

184

reg->intr = intr;

sys/arch/newsmips/apbus/dmac3.c

194

printf("DMA address = 0x%x\n", reg->addr);

sys/arch/newsmips/apbus/dmac3.c

206

struct dmac3reg *reg = sc->sc_reg;

sys/arch/newsmips/apbus/dmac3.c

211

reg->conf = conf;

sys/arch/newsmips/apbus/dmac3.c

88

struct dmac3reg *reg;

sys/arch/newsmips/apbus/dmac3.c

93

reg = (void *)apa->apa_hwbase;

sys/arch/newsmips/apbus/dmac3.c

94

sc->sc_reg = reg;

sys/arch/newsmips/apbus/if_sn_ap.c

182

volatile uint32_t *reg =

sys/arch/newsmips/apbus/if_sn_ap.c

185

*reg = APSONIC_INT_MASK;

sys/arch/newsmips/apbus/if_snvar.h

27

#define NIC_GET(sc, reg) ((sc)->sc_regbase[(reg) * 4 + 3])

sys/arch/newsmips/apbus/if_snvar.h

28

#define NIC_PUT(sc, reg, val) ((sc)->sc_regbase[(reg) * 4 + 3] = val)

sys/arch/newsmips/apbus/kb_ap.c

122

struct kbreg *reg = (void *)apa->apa_hwbase;

sys/arch/newsmips/apbus/kb_ap.c

130

sc->sc_reg = reg;

sys/arch/newsmips/apbus/kb_ap.c

138

reg->kb_rx_reset = 0x03;

sys/arch/newsmips/apbus/kb_ap.c

139

reg->kb_tx_reset = 0x03;

sys/arch/newsmips/apbus/kb_ap.c

141

reg->kb_rx_speed = 0x04;

sys/arch/newsmips/apbus/kb_ap.c

142

reg->kb_tx_speed = 0x04;

sys/arch/newsmips/apbus/kb_ap.c

144

reg->kb_rx_intr_en = 1;

sys/arch/newsmips/apbus/kb_ap.c

145

reg->kb_tx_intr_en = 0;

sys/arch/newsmips/apbus/kb_ap.c

162

struct kbreg *reg = sc->sc_reg;

sys/arch/newsmips/apbus/kb_ap.c

166

while (reg->kb_rx_stat & RX_KBRDY) {

sys/arch/newsmips/apbus/kb_ap.c

167

key = reg->kb_rx_data;

sys/arch/newsmips/apbus/kb_ap.c

191

struct kbreg *reg = v;

sys/arch/newsmips/apbus/kb_ap.c

195

ointr = reg->kb_rx_intr_en;

sys/arch/newsmips/apbus/kb_ap.c

196

reg->kb_rx_intr_en = 0;

sys/arch/newsmips/apbus/kb_ap.c

199

while ((reg->kb_rx_stat & RX_KBRDY) == 0)

sys/arch/newsmips/apbus/kb_ap.c

202

key = reg->kb_rx_data;

sys/arch/newsmips/apbus/kb_ap.c

207

reg->kb_rx_intr_en = ointr;

sys/arch/newsmips/apbus/ms_ap.c

100

reg->ms_speed = 0x01;

sys/arch/newsmips/apbus/ms_ap.c

101

reg->ms_intr_en = 0;

sys/arch/newsmips/apbus/ms_ap.c

115

struct msreg *reg = sc->sc_reg;

sys/arch/newsmips/apbus/ms_ap.c

120

reg->ms_intr_en = 0;

sys/arch/newsmips/apbus/ms_ap.c

122

while (reg->ms_stat & RX_MSRDY) {

sys/arch/newsmips/apbus/ms_ap.c

124

code = reg->ms_data;

sys/arch/newsmips/apbus/ms_ap.c

174

reg->ms_intr_en = 1;

sys/arch/newsmips/apbus/ms_ap.c

182

struct msreg *reg = sc->sc_reg;

sys/arch/newsmips/apbus/ms_ap.c

184

reg->ms_intr_en = 1;

sys/arch/newsmips/apbus/ms_ap.c

192

struct msreg *reg = sc->sc_reg;

sys/arch/newsmips/apbus/ms_ap.c

194

reg->ms_intr_en = 0;

sys/arch/newsmips/apbus/ms_ap.c

91

struct msreg *reg = (void *)apa->apa_hwbase;

sys/arch/newsmips/apbus/ms_ap.c

97

sc->sc_reg = reg;

sys/arch/newsmips/apbus/ms_ap.c

99

reg->ms_reset = 0x03;

sys/arch/newsmips/apbus/spifi.c

385

spifi_read_count(struct spifi_reg *reg)

sys/arch/newsmips/apbus/spifi.c

389

count = (reg->count_hi & 0xff) << 16 |

sys/arch/newsmips/apbus/spifi.c

390

(reg->count_mid & 0xff) << 8 |

sys/arch/newsmips/apbus/spifi.c

391

(reg->count_low & 0xff);

sys/arch/newsmips/apbus/spifi.c

396

spifi_write_count(struct spifi_reg *reg, int count)

sys/arch/newsmips/apbus/spifi.c

399

reg->count_hi = count >> 16;

sys/arch/newsmips/apbus/spifi.c

400

reg->count_mid = count >> 8;

sys/arch/newsmips/apbus/spifi.c

401

reg->count_low = count;

sys/arch/newsmips/apbus/spifi.c

416

struct spifi_reg *reg = sc->sc_reg;

sys/arch/newsmips/apbus/spifi.c

432

reg->prcmd = PRC_TRPAD;

sys/arch/newsmips/apbus/spifi.c

441

intr = reg->intr & 0xff;

sys/arch/newsmips/apbus/spifi.c

450

state = reg->spstat;

sys/arch/newsmips/apbus/spifi.c

451

icond = reg->icond;

sys/arch/newsmips/apbus/spifi.c

454

reg->intr = ~intr;

sys/arch/newsmips/apbus/spifi.c

459

scsi_phase_name[(reg->prstat >> 3) & 7]);

sys/arch/newsmips/apbus/spifi.c

465

scb->status = reg->cmbuf[scb->target].status;

sys/arch/newsmips/apbus/spifi.c

466

scb->resid = spifi_read_count(reg);

sys/arch/newsmips/apbus/spifi.c

470

DPRINTF("msg = 0x%x\n", reg->cmbuf[sc->sc_id].cdb[0]);

sys/arch/newsmips/apbus/spifi.c

502

if (reg->fifoctrl & FIFOC_RQOVRN)

sys/arch/newsmips/apbus/spifi.c

512

reg->exstat = reg->exstat & ~EXS_UBF;

sys/arch/newsmips/apbus/spifi.c

522

(reg->prstat & PRS_PHASE) == SPIFI_DATAOUT) {

sys/arch/newsmips/apbus/spifi.c

523

reg->prcmd = PRC_DATAOUT;

sys/arch/newsmips/apbus/spifi.c

526

if ((reg->prstat & PRS_Z) == 0) {

sys/arch/newsmips/apbus/spifi.c

542

struct spifi_reg *reg = sc->sc_reg;

sys/arch/newsmips/apbus/spifi.c

545

phase = (reg->prstat & PRS_PHASE);

sys/arch/newsmips/apbus/spifi.c

574

struct spifi_reg *reg = sc->sc_reg;

sys/arch/newsmips/apbus/spifi.c

579

if (reg->loopdata || reg->intr)

sys/arch/newsmips/apbus/spifi.c

589

reg->exctrl = EXC_IPLOCK;

sys/arch/newsmips/apbus/spifi.c

594

reg->select = sel;

sys/arch/newsmips/apbus/spifi.c

605

struct spifi_reg *reg = sc->sc_reg;

sys/arch/newsmips/apbus/spifi.c

633

reg->cmlen = CML_AMSG_EN | len;

sys/arch/newsmips/apbus/spifi.c

635

reg->cmbuf[id].cdb[i] = sc->sc_omsg[i];

sys/arch/newsmips/apbus/spifi.c

642

struct spifi_reg *reg = sc->sc_reg;

sys/arch/newsmips/apbus/spifi.c

649

reg->cmdpage = scb->lun_targ;

sys/arch/newsmips/apbus/spifi.c

651

if (reg->init_status & IST_ACK) {

sys/arch/newsmips/apbus/spifi.c

653

reg->prcmd = PRC_NJMP | PRC_CLRACK | PRC_COMMAND;

sys/arch/newsmips/apbus/spifi.c

654

reg->prcmd = PRC_NJMP | PRC_COMMAND;

sys/arch/newsmips/apbus/spifi.c

657

reg->cmlen = CML_AMSG_EN | len;

sys/arch/newsmips/apbus/spifi.c

660

reg->cmbuf[sc->sc_id].cdb[i] = *cmdp++;

sys/arch/newsmips/apbus/spifi.c

662

reg->prcmd = PRC_COMMAND;

sys/arch/newsmips/apbus/spifi.c

669

struct spifi_reg *reg = sc->sc_reg;

sys/arch/newsmips/apbus/spifi.c

674

phase = reg->prstat & PRS_PHASE;

sys/arch/newsmips/apbus/spifi.c

677

spifi_write_count(reg, scb->resid);

sys/arch/newsmips/apbus/spifi.c

678

reg->cmlen = CML_AMSG_EN | 1;

sys/arch/newsmips/apbus/spifi.c

679

reg->data_xfer = 0;

sys/arch/newsmips/apbus/spifi.c

683

if (reg->fifoctrl & FIFOC_SSTKACT) {

sys/arch/newsmips/apbus/spifi.c

688

reg->fifoctrl = FIFOC_CLREVEN;

sys/arch/newsmips/apbus/spifi.c

689

reg->fifoctrl = FIFOC_LOAD;

sys/arch/newsmips/apbus/spifi.c

691

reg->autodata = ADATA_IN | scb->lun_targ;

sys/arch/newsmips/apbus/spifi.c

693

reg->prcmd = PRC_DATAIN;

sys/arch/newsmips/apbus/spifi.c

695

reg->fifoctrl = FIFOC_CLREVEN;

sys/arch/newsmips/apbus/spifi.c

696

reg->autodata = scb->lun_targ;

sys/arch/newsmips/apbus/spifi.c

698

reg->prcmd = PRC_DATAOUT;

sys/arch/newsmips/apbus/spifi.c

705

struct spifi_reg *reg = sc->sc_reg;

sys/arch/newsmips/apbus/spifi.c

709

reg->cmlen = CML_AMSG_EN | 1;

sys/arch/newsmips/apbus/spifi.c

710

reg->prcmd = PRC_STATUS;

sys/arch/newsmips/apbus/spifi.c

743

struct spifi_reg *reg = sc->sc_reg;

sys/arch/newsmips/apbus/spifi.c

751

fifoctrl = reg->fifoctrl;

sys/arch/newsmips/apbus/spifi.c

758

reg->fifoctrl = FIFOC_FLUSH;

sys/arch/newsmips/apbus/spifi.c

762

reg->fifoctrl = FIFOC_CLREVEN;

sys/arch/newsmips/apbus/spifi.c

768

struct spifi_reg *reg = sc->sc_reg;

sys/arch/newsmips/apbus/spifi.c

773

reg->auxctrl = AUXCTRL_SRST;

sys/arch/newsmips/apbus/spifi.c

774

reg->auxctrl = AUXCTRL_CRST;

sys/arch/newsmips/apbus/spifi.c

778

reg->auxctrl = AUXCTRL_SRST;

sys/arch/newsmips/apbus/spifi.c

779

reg->auxctrl = AUXCTRL_CRST;

sys/arch/newsmips/apbus/spifi.c

780

reg->auxctrl = AUXCTRL_DMAEDGE;

sys/arch/newsmips/apbus/spifi.c

783

reg->imask = INTR_TGSEL | INTR_COMRECV;

sys/arch/newsmips/apbus/spifi.c

785

reg->config = CONFIG_DMABURST | CONFIG_PCHKEN | CONFIG_PGENEN | id;

sys/arch/newsmips/apbus/spifi.c

786

reg->fastwide = FAST_FASTEN;

sys/arch/newsmips/apbus/spifi.c

787

reg->prctrl = 0;

sys/arch/newsmips/apbus/spifi.c

788

reg->loopctrl = 0;

sys/arch/newsmips/apbus/spifi.c

791

reg->autostat = ~(1 << id);

sys/arch/newsmips/apbus/spifi.c

793

reg->fifoctrl = FIFOC_CLREVEN;

sys/arch/newsmips/apbus/spifi.c

794

spifi_write_count(reg, 0);

sys/arch/newsmips/apbus/spifi.c

797

(void)reg->spstat;

sys/arch/newsmips/apbus/spifi.c

803

struct spifi_reg *reg = sc->sc_reg;

sys/arch/newsmips/apbus/spifi.c

809

reg->auxctrl = AUXCTRL_SETRST;

sys/arch/newsmips/apbus/spifi.c

811

reg->auxctrl = 0;

sys/arch/newsmips/apbus/spifi.c

825

reg->data_xfer = 0;

sys/arch/newsmips/apbus/spifi.c

835

reg->data_xfer = 0; /* XXX */

sys/arch/newsmips/apbus/spifi.c

837

reg->data_xfer = v << 4 | offset;

sys/arch/newsmips/apbus/xafb.c

196

volatile struct xafb_reg *reg = dc->dc_reg;

sys/arch/newsmips/apbus/xafb.c

198

reg->index = index;

sys/arch/newsmips/apbus/xafb.c

199

reg->zero = 0;

sys/arch/newsmips/apbus/xafb.c

200

reg->rgb = r;

sys/arch/newsmips/apbus/xafb.c

201

reg->rgb = g;

sys/arch/newsmips/apbus/xafb.c

202

reg->rgb = b;

sys/arch/newsmips/dev/kb_hb.c

107

struct kbreg *reg;

sys/arch/newsmips/dev/kb_hb.c

114

reg = (struct kbreg *)ha->ha_addr;

sys/arch/newsmips/dev/kb_hb.c

120

sc->sc_reg = reg;

sys/arch/newsmips/dev/kb_hb.c

121

reg->kb_reset = 0x01;

sys/arch/newsmips/dev/kb_hb.c

122

reg->kb_init = 0xf0; /* 9600 bps */

sys/arch/newsmips/dev/kb_hb.c

145

struct kbreg *reg = sc->sc_reg;

sys/arch/newsmips/dev/kb_hb.c

152

while (reg->kb_stat & RX_KBRDY) {

sys/arch/newsmips/dev/kb_hb.c

153

code = reg->kb_data;

sys/arch/newsmips/dev/kb_hb.c

179

struct kbreg *reg = v;

sys/arch/newsmips/dev/kb_hb.c

187

while ((reg->kb_stat & RX_KBRDY) == 0);

sys/arch/newsmips/dev/kb_hb.c

189

code = reg->kb_data;

sys/arch/newsmips/dev/ms_hb.c

103

sc->sc_reg = reg;

sys/arch/newsmips/dev/ms_hb.c

105

reg->ms_reset = 0x01;

sys/arch/newsmips/dev/ms_hb.c

106

reg->ms_init = 0x80; /* 1200 bps */

sys/arch/newsmips/dev/ms_hb.c

121

struct msreg *reg = sc->sc_reg;

sys/arch/newsmips/dev/ms_hb.c

129

while (reg->ms_stat & RX_MSRDY) {

sys/arch/newsmips/dev/ms_hb.c

131

code = reg->ms_data;

sys/arch/newsmips/dev/ms_hb.c

91

struct msreg *reg;

sys/arch/newsmips/dev/ms_hb.c

97

reg = (struct msreg *)ha->ha_addr;

sys/arch/newsmips/dev/zs.c

193

zs_read_reg(struct zs_chanstate *cs, uint8_t reg)

sys/arch/newsmips/dev/zs.c

197

*cs->cs_reg_csr = reg;

sys/arch/newsmips/dev/zs.c

205

zs_write_reg(struct zs_chanstate *cs, uint8_t reg, uint8_t val)

sys/arch/newsmips/dev/zs.c

208

*cs->cs_reg_csr = reg;

sys/arch/newsmips/include/z8530var.h

104

uint8_t zs_read_reg(struct zs_chanstate *cs, uint8_t reg);

sys/arch/newsmips/include/z8530var.h

108

void zs_write_reg(struct zs_chanstate *cs, uint8_t reg, uint8_t val);

sys/arch/next68k/dev/esp.c

181

#define nd_bsr4(reg) \

sys/arch/next68k/dev/esp.c

182

bus_space_read_4(nsc->sc_bst, nsc->sc_bsh, (reg))

sys/arch/next68k/dev/esp.c

183

#define nd_bsw4(reg, val) \

sys/arch/next68k/dev/esp.c

184

bus_space_write_4(nsc->sc_bst, nsc->sc_bsh, (reg), (val))

sys/arch/next68k/dev/esp.c

420

esp_read_reg(struct ncr53c9x_softc *sc, int reg)

sys/arch/next68k/dev/esp.c

424

return bus_space_read_1(esc->sc_bst, esc->sc_bsh, reg);

sys/arch/next68k/dev/esp.c

428

esp_write_reg(struct ncr53c9x_softc *sc, int reg, uint8_t val)

sys/arch/next68k/dev/esp.c

432

bus_space_write_1(esc->sc_bst, esc->sc_bsh, reg, val);

sys/arch/next68k/dev/esp.c

446

volatile uint8_t *reg = (volatile uint8_t *)IIOV(xADDR);

sys/arch/next68k/dev/esp.c

455

(*reg) = 0;

sys/arch/next68k/dev/esp.c

456

(*reg) = 0;

sys/arch/next68k/dev/esp.c

458

save1 = (*reg);

sys/arch/next68k/dev/esp.c

459

tmp2 = *(reg + 3);

sys/arch/next68k/dev/if_xe.c

294

xe_read_reg(struct mb8795_softc *sc, int reg)

sys/arch/next68k/dev/if_xe.c

298

return bus_space_read_1(xsc->sc_bst, xsc->sc_bsh, reg);

sys/arch/next68k/dev/if_xe.c

302

xe_write_reg(struct mb8795_softc *sc, int reg, u_char val)

sys/arch/next68k/dev/if_xe.c

306

bus_space_write_1(xsc->sc_bst, xsc->sc_bsh, reg, val);

sys/arch/next68k/dev/mb8795var.h

78

#define MB_READ_REG(sc, reg) \

sys/arch/next68k/dev/mb8795var.h

79

(*(sc)->sc_glue->gl_read_reg)((sc), (reg))

sys/arch/next68k/dev/mb8795var.h

80

#define MB_WRITE_REG(sc, reg, val) \

sys/arch/next68k/dev/mb8795var.h

81

(*(sc)->sc_glue->gl_write_reg)((sc), (reg), (val))

sys/arch/next68k/dev/nextdma.c

160

#define nd_bsr4(reg) \

sys/arch/next68k/dev/nextdma.c

161

bus_space_read_4(nsc->sc_bst, nsc->sc_bsh, (reg))

sys/arch/next68k/dev/nextdma.c

162

#define nd_bsw4(reg,val) \

sys/arch/next68k/dev/nextdma.c

163

bus_space_write_4(nsc->sc_bst, nsc->sc_bsh, (reg), (val))

sys/arch/next68k/dev/zs.c

432

zs_read_reg(struct zs_chanstate *cs, uint8_t reg)

sys/arch/next68k/dev/zs.c

436

*cs->cs_reg_csr = reg;

sys/arch/next68k/dev/zs.c

444

zs_write_reg(struct zs_chanstate *cs, uint8_t reg, uint8_t val)

sys/arch/next68k/dev/zs.c

446

*cs->cs_reg_csr = reg;

sys/arch/next68k/next68k/rtc.c

145

rtc_read(uint8_t reg)

sys/arch/next68k/next68k/rtc.c

154

val = reg;

sys/arch/next68k/next68k/rtc.c

192

rtc_write(uint8_t reg, uint8_t v)

sys/arch/next68k/next68k/rtc.c

201

val = reg | RTC_WRITE;

sys/arch/next68k/next68k/rtc.c

242

int reg, t;

sys/arch/next68k/next68k/rtc.c

245

reg = RTC_CNTR3;

sys/arch/next68k/next68k/rtc.c

247

reg = RTC_CNTR0;

sys/arch/next68k/next68k/rtc.c

250

t = rtc_read(reg); /* seconds */

sys/arch/next68k/next68k/rtc.c

252

while(t == rtc_read(reg))

sys/arch/next68k/next68k/rtc.c

258

reg = RTC_CONTROL;

sys/arch/next68k/next68k/rtc.c

260

reg = RTC_INTRCTL;

sys/arch/next68k/next68k/rtc.c

263

rtc_write(reg, rtc_read(reg)|(RTC_PDOWN));

sys/arch/next68k/stand/boot/rtc.c

46

rtc_read(u_char reg)

sys/arch/next68k/stand/boot/rtc.c

55

val = reg;

sys/arch/ofppc/ofppc/cpu.c

103

if (l == 4 && reg[0] == cpunum)

sys/arch/ofppc/ofppc/cpu.c

107

if (reg[0] == 0)

sys/arch/ofppc/ofppc/cpu.c

90

int *reg = ca->ca_reg;

sys/arch/ofppc/ofppc/machdep.c

385

uint32_t reg[2], comfreq;

sys/arch/ofppc/ofppc/machdep.c

419

if (OF_getprop(com_node, "reg", reg, sizeof(reg)) == -1)

sys/arch/ofppc/ofppc/machdep.c

432

if (bus_space_map(&genppc_isa_io_space_tag, reg[1], 8, 0, &comh) != 0)

sys/arch/ofppc/ofppc/machdep.c

452

if (comcnattach(&genppc_isa_io_space_tag, reg[1],

sys/arch/ofppc/ofppc/mainbus.c

104

uint32_t reg[12];

sys/arch/ofppc/ofppc/mainbus.c

155

len = OF_getprop(node, "reg", &reg, sizeof(reg));

sys/arch/ofppc/ofppc/mainbus.c

160

aprint_verbose("Found openpic at %08x\n", reg[0]);

sys/arch/ofppc/ofppc/mainbus.c

162

baseaddr = (unsigned char *)mapiodev(reg[0], reg[1], false);

sys/arch/ofppc/ofppc/mainbus.c

187

baseaddr = (unsigned char *)mapiodev(reg[0], 0x40000, false);

sys/arch/ofppc/ofppc/mainbus.c

188

aprint_verbose("Found openpic at %08x\n", reg[0]);

sys/arch/ofppc/ofppc/mainbus.c

191

isu[j] = (unsigned char *)mapiodev(reg[(j+1)*2],

sys/arch/ofppc/ofppc/mainbus.c

192

reg[(j+1)*2+1], false);

sys/arch/ofppc/ofppc/mainbus.c

193

isumap[j] = reg[(j+1)*2+1];

sys/arch/ofppc/ofppc/mainbus.c

231

u_int32_t reg[4];

sys/arch/ofppc/ofppc/mainbus.c

245

ca.ca_nreg = OF_getprop(rtnode, "reg", reg,

sys/arch/ofppc/ofppc/mainbus.c

246

sizeof(reg));

sys/arch/ofppc/ofppc/mainbus.c

247

ca.ca_reg = reg;

sys/arch/ofppc/ofppc/mainbus.c

255

ca.ca_reg = reg;

sys/arch/ofppc/ofppc/mainbus.c

256

reg[0] = i;

sys/arch/ofppc/ofppc/mainbus.c

290

ca.ca_nreg = OF_getprop(node, "reg", reg, sizeof(reg));

sys/arch/ofppc/ofppc/mainbus.c

291

ca.ca_reg = reg;

sys/arch/or1k/include/frame.h

38

struct reg tf_regs __aligned(8);

sys/arch/or1k/include/pcb.h

42

struct reg reg;

sys/arch/playstation2/dev/emac3.c

316

emac3_phy_writereg(device_t self, int phy, int reg, uint16_t val)

sys/arch/playstation2/dev/emac3.c

325

((reg << STACR_PRASHIFT) & STACR_PRA) | /* register addr */

sys/arch/playstation2/dev/emac3.c

332

emac3_phy_readreg(device_t self, int phy, int reg, uint16_t *val)

sys/arch/playstation2/dev/emac3.c

341

((reg << STACR_PRASHIFT) & STACR_PRA)); /* register addr */

sys/arch/pmax/ibus/sii.c

88

#define SII_WAIT_UNTIL(var, reg, expr, spincount, cntr) { \

sys/arch/pmax/ibus/sii.c

89

u_int tmp = reg; \

sys/arch/pmax/ibus/sii.c

91

while (tmp != (var = reg)) \

sys/arch/pmax/include/z8530var.h

70

u_int zs_read_reg(struct zs_chanstate *cs, u_int reg);

sys/arch/pmax/include/z8530var.h

74

void zs_write_reg(struct zs_chanstate *cs, u_int reg, u_int val);

sys/arch/pmax/tc/asc_ioasic.c

419

asc_read_reg(struct ncr53c9x_softc *sc, int reg)

sys/arch/pmax/tc/asc_ioasic.c

423

return ASC_READ_REG(asc, reg);

sys/arch/pmax/tc/asc_ioasic.c

427

asc_write_reg(struct ncr53c9x_softc *sc, int reg, uint8_t val)

sys/arch/pmax/tc/asc_ioasic.c

431

ASC_WRITE_REG(asc, reg, val);

sys/arch/pmax/tc/asc_ioasic.c

71

#define ASC_READ_REG(asc, reg) \

sys/arch/pmax/tc/asc_ioasic.c

73

(reg) * sizeof(uint32_t)))

sys/arch/pmax/tc/asc_ioasic.c

74

#define ASC_WRITE_REG(asc, reg, val) \

sys/arch/pmax/tc/asc_ioasic.c

76

(reg) * sizeof(uint32_t), (uint8_t)(val))

sys/arch/powerpc/booke/dev/pq3ehci.c

185

uint32_t reg = old;

sys/arch/powerpc/booke/dev/pq3ehci.c

187

reg &= ~USBMODE_CM;

sys/arch/powerpc/booke/dev/pq3ehci.c

188

reg |= USBMODE_CM_HOST;

sys/arch/powerpc/booke/dev/pq3ehci.c

189

if (reg != old)

sys/arch/powerpc/booke/dev/pq3ehci.c

190

bus_space_write_4(hsc->iot, hsc->ioh, PQ3_USBMODE, reg);

sys/arch/powerpc/booke/dev/pq3etsec.c

2589

uint32_t reg;

sys/arch/powerpc/booke/dev/pq3etsec.c

2592

reg = RXIC_ICEN;

sys/arch/powerpc/booke/dev/pq3etsec.c

2593

reg |= RXIC_ICFT_SET(sc->sc_ic_rx_count);

sys/arch/powerpc/booke/dev/pq3etsec.c

2594

reg |= RXIC_ICTT_SET(sc->sc_ic_rx_time);

sys/arch/powerpc/booke/dev/pq3etsec.c

2597

reg = 0;

sys/arch/powerpc/booke/dev/pq3etsec.c

2600

etsec_write(sc, RXIC, reg);

sys/arch/powerpc/booke/dev/pq3etsec.c

2606

uint32_t reg;

sys/arch/powerpc/booke/dev/pq3etsec.c

2609

reg = TXIC_ICEN;

sys/arch/powerpc/booke/dev/pq3etsec.c

2610

reg |= TXIC_ICFT_SET(sc->sc_ic_tx_count);

sys/arch/powerpc/booke/dev/pq3etsec.c

2611

reg |= TXIC_ICTT_SET(sc->sc_ic_tx_time);

sys/arch/powerpc/booke/dev/pq3etsec.c

2614

reg = 0;

sys/arch/powerpc/booke/dev/pq3etsec.c

2617

etsec_write(sc, TXIC, reg);

sys/arch/powerpc/booke/dev/pq3etsec.c

411

pq3mdio_mii_readreg(device_t self, int phy, int reg, uint16_t *val)

sys/arch/powerpc/booke/dev/pq3etsec.c

417

__SHIFTIN(phy, MIIMADD_PHY) | __SHIFTIN(reg, MIIMADD_REG));

sys/arch/powerpc/booke/dev/pq3etsec.c

432

__func__, phy, reg, data);

sys/arch/powerpc/booke/dev/pq3etsec.c

438

pq3mdio_mii_writereg(device_t self, int phy, int reg, uint16_t data)

sys/arch/powerpc/booke/dev/pq3etsec.c

445

__func__, phy, reg, data);

sys/arch/powerpc/booke/dev/pq3etsec.c

449

__SHIFTIN(phy, MIIMADD_PHY) | __SHIFTIN(reg, MIIMADD_REG));

sys/arch/powerpc/booke/dev/pq3gpio.c

204

bus_size_t reg, uint32_t pinmask, int pincaps,

sys/arch/powerpc/booke/dev/pq3gpio.c

211

gc->gc_reg = reg;

sys/arch/powerpc/booke/dev/pq3gpio.c

221

u_int data = bus_space_read_4(gc->gc_bst, gc->gc_bsh, reg);

sys/arch/powerpc/booke/pci/pq3pci.c

1069

pq3pci_conf_read(void *v, pcitag_t tag, int reg)

sys/arch/powerpc/booke/pci/pq3pci.c

1074

if (reg < 0)

sys/arch/powerpc/booke/pci/pq3pci.c

1076

if (reg >= PCI_CONF_SIZE) {

sys/arch/powerpc/booke/pci/pq3pci.c

1077

if (!sc->sc_pcie || reg >= PCI_EXTCONF_SIZE)

sys/arch/powerpc/booke/pci/pq3pci.c

1079

reg = (reg & 0xff) | ((reg & 0xf00) << 16);

sys/arch/powerpc/booke/pci/pq3pci.c

1091

pq3pci_config_addr_write(pc, tag | reg | PEX_CONFIG_ADDR_EN);

sys/arch/powerpc/booke/pci/pq3pci.c

1100

__func__, tag, reg, pq3pci_config_addr_read(pc));

sys/arch/powerpc/booke/pci/pq3pci.c

1109

pq3pci_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data)

sys/arch/powerpc/booke/pci/pq3pci.c

1114

if (reg < 0)

sys/arch/powerpc/booke/pci/pq3pci.c

1116

if (reg >= PCI_CONF_SIZE) {

sys/arch/powerpc/booke/pci/pq3pci.c

1117

if (!sc->sc_pcie || reg >= PCI_EXTCONF_SIZE)

sys/arch/powerpc/booke/pci/pq3pci.c

1119

reg = (reg & 0xff) | ((reg & 0xf00) << 16);

sys/arch/powerpc/booke/pci/pq3pci.c

1126

__func__, tag, reg, data);

sys/arch/powerpc/booke/pci/pq3pci.c

1128

pq3pci_config_addr_write(pc, tag | reg | PEX_CONFIG_ADDR_EN);

sys/arch/powerpc/fpu/fpu_emu.c

162

#define FR(reg) (fs->fpreg[reg])

sys/arch/powerpc/fpu/fpu_emu.c

306

fpu_to_single(uint64_t reg)

sys/arch/powerpc/fpu/fpu_emu.c

311

sign = (reg & __BIT(63)) >> 32;

sys/arch/powerpc/fpu/fpu_emu.c

312

exp = __SHIFTOUT(reg, __BITS(62, 52)) - 1023;

sys/arch/powerpc/fpu/fpu_emu.c

313

if (exp > -127 || (reg & ~__BIT(63)) == 0) {

sys/arch/powerpc/fpu/fpu_emu.c

321

word = ((reg & __BIT(62)) >> 32) |

sys/arch/powerpc/fpu/fpu_emu.c

322

__SHIFTOUT(reg, __BITS(58, 52) | __BITS(51, 29));

sys/arch/powerpc/fpu/fpu_emu.c

326

frac = __SHIFTOUT(__BIT(52) | reg, __BITS(52, 29 + shift));

sys/arch/powerpc/ibm4xx/dev/dwcsata.c

224

dwcdmac_read(struct dwcsata_softc *sc, bus_size_t reg)

sys/arch/powerpc/ibm4xx/dev/dwcsata.c

227

return bus_space_read_4(sc->sc_iot, sc->sc_dmac_ioh, reg);

sys/arch/powerpc/ibm4xx/dev/dwcsata.c

231

dwcdmac_write(struct dwcsata_softc *sc, bus_size_t reg, uint32_t val)

sys/arch/powerpc/ibm4xx/dev/dwcsata.c

234

bus_space_write_4(sc->sc_iot, sc->sc_dmac_ioh, reg, val);

sys/arch/powerpc/ibm4xx/dev/dwcsata.c

580

uint32_t reg;

sys/arch/powerpc/ibm4xx/dev/dwcsata.c

583

reg = mfsdr(SATA_PESDR0_PHY_CTL_RST);

sys/arch/powerpc/ibm4xx/dev/dwcsata.c

584

mtsdr(SATA_PESDR0_PHY_CTL_RST, (reg & 0xeffffffc) | 0x00000001);

sys/arch/powerpc/ibm4xx/dev/dwcsata.c

585

reg = mfsdr(SATA_PESDR0_L0CLK);

sys/arch/powerpc/ibm4xx/dev/dwcsata.c

586

mtsdr(SATA_PESDR0_L0CLK, (reg & 0xfffffff8) | 0x00000007);

sys/arch/powerpc/ibm4xx/dev/dwcsata.c

591

reg = mfsdr(DCR_SDR0_AHB_CFG); /* errata is lost across the reset */

sys/arch/powerpc/ibm4xx/dev/dwcsata.c

593

(reg | SDR0_AHB_CFG_A2P_INCR4) & ~SDR0_AHB_CFG_A2P_PROT2);

sys/arch/powerpc/ibm4xx/dev/if_emac.c

1899

uint32_t rmr, crc, mask, tmp, reg, gaht[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };

sys/arch/powerpc/ibm4xx/dev/if_emac.c

1903

reg = EMAC_GAHT256(0);

sys/arch/powerpc/ibm4xx/dev/if_emac.c

1906

reg = EMAC_GAHT64(0);

sys/arch/powerpc/ibm4xx/dev/if_emac.c

1954

EMAC_WRITE(sc, reg + (i << 2), gaht[i]);

sys/arch/powerpc/ibm4xx/dev/if_emac.c

2189

emac_mii_readreg(device_t self, int phy, int reg, uint16_t *val)

sys/arch/powerpc/ibm4xx/dev/if_emac.c

2204

(reg << STACR_PRA_SHIFT) |

sys/arch/powerpc/ibm4xx/dev/if_emac.c

2226

emac_mii_writereg(device_t self, int phy, int reg, uint16_t val)

sys/arch/powerpc/ibm4xx/dev/if_emac.c

2242

(reg << STACR_PRA_SHIFT) |

sys/arch/powerpc/ibm4xx/dev/if_emac.c

346

#define EMAC_WRITE(sc, reg, val) \

sys/arch/powerpc/ibm4xx/dev/if_emac.c

347

bus_space_write_stream_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))

sys/arch/powerpc/ibm4xx/dev/if_emac.c

348

#define EMAC_READ(sc, reg) \

sys/arch/powerpc/ibm4xx/dev/if_emac.c

349

bus_space_read_stream_4((sc)->sc_st, (sc)->sc_sh, (reg))

sys/arch/powerpc/ibm4xx/dev/if_emac.c

352

#define TAH_WRITE(sc, reg, val) \

sys/arch/powerpc/ibm4xx/dev/if_emac.c

353

bus_space_write_stream_4((sc)->sc_st, (sc)->sc_tahh, (reg), (val))

sys/arch/powerpc/ibm4xx/dev/if_emac.c

354

#define TAH_READ(sc, reg) \

sys/arch/powerpc/ibm4xx/dev/if_emac.c

355

bus_space_read_stream_4((sc)->sc_st, (sc)->sc_tahh, (reg))

sys/arch/powerpc/ibm4xx/pci/pci_machdep.c

138

ibm4xx_pci_conf_read(void *v, pcitag_t tag, int reg)

sys/arch/powerpc/ibm4xx/pci/pci_machdep.c

142

if ((unsigned int)reg >= PCI_CONF_SIZE)

sys/arch/powerpc/ibm4xx/pci/pci_machdep.c

146

bus_space_write_4(&pci_iot, pci_ioh, PCIC_CFGADDR, tag | reg);

sys/arch/powerpc/ibm4xx/pci/pci_machdep.c

154

ibm4xx_pci_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data)

sys/arch/powerpc/ibm4xx/pci/pci_machdep.c

157

if ((unsigned int)reg >= PCI_CONF_SIZE)

sys/arch/powerpc/ibm4xx/pci/pci_machdep.c

160

bus_space_write_4(&pci_iot, pci_ioh, PCIC_CFGADDR, tag | reg);

sys/arch/powerpc/ibm4xx/pci/pciex.c

237

pciex_conf_read(void *v, pcitag_t tag, int reg)

sys/arch/powerpc/ibm4xx/pci/pciex.c

243

if ((unsigned int)reg >= PCI_CONF_SIZE)

sys/arch/powerpc/ibm4xx/pci/pciex.c

253

(tag << 4) | reg);

sys/arch/powerpc/ibm4xx/pci/pciex.c

259

pciex_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data)

sys/arch/powerpc/ibm4xx/pci/pciex.c

264

if ((unsigned int)reg >= PCI_CONF_SIZE)

sys/arch/powerpc/ibm4xx/pci/pciex.c

274

(tag << 4) | reg, data);

sys/arch/powerpc/ibm4xx/pci/pcix.c

185

pcix_cfg_addr(pcitag_t tag, int reg)

sys/arch/powerpc/ibm4xx/pci/pcix.c

187

uint32_t addr = (tag & 0x00ffff00) | (reg & 0xfc);

sys/arch/powerpc/ibm4xx/pci/pcix.c

195

pcix_conf_read(void *v, pcitag_t tag, int reg)

sys/arch/powerpc/ibm4xx/pci/pcix.c

199

if ((unsigned int)reg >= PCI_CONF_SIZE)

sys/arch/powerpc/ibm4xx/pci/pcix.c

203

pcix_cfg_addr(tag, reg));

sys/arch/powerpc/ibm4xx/pci/pcix.c

210

pcix_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data)

sys/arch/powerpc/ibm4xx/pci/pcix.c

213

if ((unsigned int)reg >= PCI_CONF_SIZE)

sys/arch/powerpc/ibm4xx/pci/pcix.c

217

pcix_cfg_addr(tag, reg));

sys/arch/powerpc/ibm4xx/pci/pcix.c

222

#define PCIX_REG_WRITE(reg, val) \

sys/arch/powerpc/ibm4xx/pci/pcix.c

223

bus_space_write_4(&pcix_reg_tag, pcix_reg_ioh, (reg), (val))

sys/arch/powerpc/include/asm.h

58

# define PIC_TOCSETUP(name, reg) \

sys/arch/powerpc/include/asm.h

63

1001: mflr reg ;\

sys/arch/powerpc/include/asm.h

64

addis reg,reg,PIC_TOCNAME(name)-1001b@ha ;\

sys/arch/powerpc/include/asm.h

65

addi reg,reg,PIC_TOCNAME(name)-1001b@l

sys/arch/powerpc/include/asm.h

66

# define PIC_GOTSETUP(reg) \

sys/arch/powerpc/include/asm.h

68

2002: mflr reg ;\

sys/arch/powerpc/include/asm.h

69

addis reg,reg,_GLOBAL_OFFSET_TABLE_-2002b@ha ;\

sys/arch/powerpc/include/asm.h

70

addi reg,reg,_GLOBAL_OFFSET_TABLE_-2002b@l

sys/arch/powerpc/include/ibm4xx/cpu.h

100

mfdcr(const int reg)

sys/arch/powerpc/include/ibm4xx/cpu.h

104

__asm volatile("mfdcr %0,%1" : "=r"(val) : "K"(reg));

sys/arch/powerpc/include/ibm4xx/cpu.h

109

mtcpr(int reg, uint32_t val)

sys/arch/powerpc/include/ibm4xx/cpu.h

111

mtdcr(DCR_CPR0_CFGADDR, reg);

sys/arch/powerpc/include/ibm4xx/cpu.h

116

mfcpr(int reg)

sys/arch/powerpc/include/ibm4xx/cpu.h

118

mtdcr(DCR_CPR0_CFGADDR, reg);

sys/arch/powerpc/include/ibm4xx/cpu.h

123

mtsdr(int reg, uint32_t val)

sys/arch/powerpc/include/ibm4xx/cpu.h

125

mtdcr(DCR_SDR0_CFGADDR, reg);

sys/arch/powerpc/include/ibm4xx/cpu.h

130

mfsdr(int reg)

sys/arch/powerpc/include/ibm4xx/cpu.h

132

mtdcr(DCR_SDR0_CFGADDR, reg);

sys/arch/powerpc/include/ibm4xx/cpu.h

94

mtdcr(const int reg, uint32_t val)

sys/arch/powerpc/include/ibm4xx/cpu.h

96

__asm volatile("mtdcr %0,%1" : : "K"(reg), "r"(val));

sys/arch/powerpc/include/ibm4xx/spr.h

277

#define MFPID(reg) "mfspr "#reg","___STRING(SPR_PID)";"

sys/arch/powerpc/include/ibm4xx/spr.h

278

#define MTPID(reg) "mtspr "___STRING(SPR_PID)","#reg";"

sys/arch/powerpc/include/ibm4xx/spr.h

280

#define MFMMUCR(reg) "mfspr "#reg","___STRING(SPR_MMUCR)";"

sys/arch/powerpc/include/ibm4xx/spr.h

281

#define MTMMUCR(reg) "mtspr "___STRING(SPR_MMUCR)","#reg";"

sys/arch/powerpc/include/openpic.h

41

openpic_read(u_int reg)

sys/arch/powerpc/include/openpic.h

43

volatile uint8_t *addr = openpic_base + reg;

sys/arch/powerpc/include/openpic.h

49

openpic_write(u_int reg, uint32_t val)

sys/arch/powerpc/include/openpic.h

51

volatile uint8_t *addr = openpic_base + reg;

sys/arch/powerpc/include/pci_machdep.h

222

pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg)

sys/arch/powerpc/include/pci_machdep.h

224

return (*pc->pc_conf_read)(pc->pc_conf_v, tag, reg);

sys/arch/powerpc/include/pci_machdep.h

228

pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t val)

sys/arch/powerpc/include/pci_machdep.h

230

(*pc->pc_conf_write)(pc->pc_conf_v, tag, reg, val);

sys/arch/powerpc/include/spr.h

101

#define mtspr(reg, val) \

sys/arch/powerpc/include/spr.h

104

mtspr64(reg, (uint64_t)val); \

sys/arch/powerpc/include/spr.h

106

mtspr32(reg, val); \

sys/arch/powerpc/include/spr.h

41

mfspr64(int reg)

sys/arch/powerpc/include/spr.h

48

: "=r"(l), "=r"(hi) : "K"(reg));

sys/arch/powerpc/include/spr.h

54

#define mtspr64(reg, v) \

sys/arch/powerpc/include/spr.h

71

: : "K"(reg), "r"(l), "r"(hi)); \

sys/arch/powerpc/include/spr.h

76

mfspr32(const int reg)

sys/arch/powerpc/include/spr.h

80

__asm volatile("mfspr %0,%1" : "=r"(val) : "K"(reg));

sys/arch/powerpc/include/spr.h

85

mtspr32(const int reg, uint32_t val)

sys/arch/powerpc/include/spr.h

88

__asm volatile("mtspr %0,%1" : : "K"(reg), "r"(val));

sys/arch/powerpc/include/spr.h

93

mfspr(int reg)

sys/arch/powerpc/include/spr.h

96

return mfspr64(reg);

sys/arch/powerpc/include/spr.h

97

return mfspr32(reg);

sys/arch/powerpc/mpc5200/fec.c

241

fec_miibus_readreg(device_t self, int phy, int reg, uint16_t *val)

sys/arch/powerpc/mpc5200/fec.c

246

FEC_WRITE(sc, FEC_MII_DATA, FEC_MII_READ(phy, reg));

sys/arch/powerpc/mpc5200/fec.c

255

fec_miibus_writereg(device_t self, int phy, int reg, uint16_t val)

sys/arch/powerpc/mpc5200/fec.c

260

FEC_WRITE(sc, FEC_MII_DATA, FEC_MII_WRITE(phy, reg, val));

sys/arch/powerpc/mpc5200/fec.c

399

bus_size_t reg;

sys/arch/powerpc/mpc5200/fec.c

425

sc->sc_mib_prev[i] = FEC_READ(sc, fec_mibtab[i].reg);

sys/arch/powerpc/mpc5200/fec.c

431

uint32_t cur = FEC_READ(sc, fec_mibtab[i].reg);

sys/arch/powerpc/mpc5200/mpc5200_ac97.c

380

mpcac97_ac97_read(void *arg, uint8_t reg, uint16_t *valp)

sys/arch/powerpc/mpc5200/mpc5200_ac97.c

387

WR4(sc, PSC_AC97CMD, AC97CMD_READ | AC97CMD_INDEX(reg));

sys/arch/powerpc/mpc5200/mpc5200_ac97.c

402

mpcac97_ac97_write(void *arg, uint8_t reg, uint16_t val)

sys/arch/powerpc/mpc5200/mpc5200_ac97.c

407

WR4(sc, PSC_AC97CMD, AC97CMD_WRITE(reg, val));

sys/arch/powerpc/mpc5200/mpc5200_ac97reg.h

69

#define AC97CMD_INDEX(reg) ((uint32_t)((reg) & 0x7f) << 24)

sys/arch/powerpc/mpc5200/mpc5200_ac97reg.h

71

#define AC97CMD_WRITE(reg, val) (AC97CMD_INDEX(reg) | AC97CMD_DATA(val))

sys/arch/powerpc/mpc5200/mpc5200_pci.c

100

if ((unsigned int)reg >= PCI_CONF_SIZE)

sys/arch/powerpc/mpc5200/mpc5200_pci.c

104

out32(pc->pc_addr, tag | reg); /* PCICAR: big-endian */

sys/arch/powerpc/mpc5200/mpc5200_pci.c

113

mpcpci_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data)

sys/arch/powerpc/mpc5200/mpc5200_pci.c

118

if ((unsigned int)reg >= PCI_CONF_SIZE)

sys/arch/powerpc/mpc5200/mpc5200_pci.c

122

out32(pc->pc_addr, tag | reg); /* PCICAR: big-endian */

sys/arch/powerpc/mpc5200/mpc5200_pci.c

94

mpcpci_conf_read(void *v, pcitag_t tag, int reg)

sys/arch/powerpc/mpc5200/obio.c

104

uint32_t reg[2];

sys/arch/powerpc/mpc5200/obio.c

123

len = OF_getprop(ca->ca_node, "reg", reg, sizeof(reg));

sys/arch/powerpc/mpc5200/obio.c

124

if (len >= (int)sizeof(reg)) {

sys/arch/powerpc/mpc5200/obio.c

125

mbar = reg[0];

sys/arch/powerpc/mpc5200/obio.c

126

mbarsz = reg[1];

sys/arch/powerpc/mpc5200/obio.c

155

len = OF_getprop(node, "reg", reg, sizeof(reg));

sys/arch/powerpc/mpc5200/obio.c

156

if (len >= (int)sizeof(reg)) {

sys/arch/powerpc/mpc5200/obio.c

157

oba.obio_addr = reg[0];

sys/arch/powerpc/mpc5200/obio.c

158

oba.obio_size = reg[1];

sys/arch/powerpc/oea/ofw_autoconf.c

565

u_int reg[5];

sys/arch/powerpc/oea/ofw_autoconf.c

572

l = OF_getprop(q, "assigned-addresses", reg, sizeof(reg));

sys/arch/powerpc/oea/ofw_autoconf.c

574

b = (reg[0] >> 16) & 0xff;

sys/arch/powerpc/oea/ofw_autoconf.c

575

d = (reg[0] >> 11) & 0x1f;

sys/arch/powerpc/oea/ofw_autoconf.c

576

f = (reg[0] >> 8) & 0x07;

sys/arch/powerpc/pci/pci_machdep_ofw.c

136

irgot = OF_getprop(node, "reg", reg, sizeof(reg));

sys/arch/powerpc/pci/pci_machdep_ofw.c

158

reg[7] == 0x4d0)

sys/arch/powerpc/pci/pci_machdep_ofw.c

288

uint32_t irqs[4], reg[5];

sys/arch/powerpc/pci/pci_machdep_ofw.c

296

if (OF_getprop(node, "reg", reg, 5) > 0) {

sys/arch/powerpc/pci/pci_machdep_ofw.c

297

dev = ((reg[0] & 0x0000ff00) >> 8) / 0x8;

sys/arch/powerpc/pci/pci_machdep_ofw.c

298

func = ((reg[0] & 0x0000ff00) >> 8) % 0x8;

sys/arch/powerpc/pci/pci_machdep_ofw.c

300

reg, 5) > 0) {

sys/arch/powerpc/pci/pci_machdep_ofw.c

301

dev = ((reg[0] & 0x0000ff00) >> 8) / 0x8;

sys/arch/powerpc/pci/pci_machdep_ofw.c

302

func = ((reg[0] & 0x0000ff00) >> 8) % 0x8;

sys/arch/powerpc/pci/pci_machdep_ofw.c

331

uint32_t reg[5], irq;

sys/arch/powerpc/pci/pci_machdep_ofw.c

337

if (OF_getprop(node, "reg", reg, 5) > 0) {

sys/arch/powerpc/pci/pci_machdep_ofw.c

338

dev = ((reg[0] & 0x0000ff00) >> 8) / 0x8;

sys/arch/powerpc/pci/pci_machdep_ofw.c

339

func = ((reg[0] & 0x0000ff00) >> 8) % 0x8;

sys/arch/powerpc/pci/pci_machdep_ofw.c

366

uint32_t reg;

sys/arch/powerpc/pci/pci_machdep_ofw.c

369

sz = OF_getprop(node, "reg", &reg, sizeof(reg));

sys/arch/powerpc/pci/pci_machdep_ofw.c

370

if (sz != sizeof(reg))

sys/arch/powerpc/pci/pci_machdep_ofw.c

372

if (OFW_PCI_PHYS_HI_BUS(reg) == bus &&

sys/arch/powerpc/pci/pci_machdep_ofw.c

373

OFW_PCI_PHYS_HI_DEVICE(reg) == dev &&

sys/arch/powerpc/pci/pci_machdep_ofw.c

374

OFW_PCI_PHYS_HI_FUNCTION(reg) == func)

sys/arch/powerpc/pci/pci_machdep_ofw.c

84

uint32_t reg[12];

sys/arch/powerpc/pci/pciconf_indirect.c

100

genppc_pci_indirect_conf_read(void *v, pcitag_t tag, int reg)

sys/arch/powerpc/pci/pciconf_indirect.c

106

if ((unsigned int)reg >= PCI_CONF_SIZE)

sys/arch/powerpc/pci/pciconf_indirect.c

110

out32rb(pc->pc_addr, tag | reg);

sys/arch/powerpc/pci/pciconf_indirect.c

119

genppc_pci_indirect_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data)

sys/arch/powerpc/pci/pciconf_indirect.c

124

if ((unsigned int)reg >= PCI_CONF_SIZE)

sys/arch/powerpc/pci/pciconf_indirect.c

128

out32rb(pc->pc_addr, tag | reg);

sys/arch/powerpc/pci/pciconf_ofmethod.c

102

if ((unsigned int)reg >= PCI_CONF_SIZE)

sys/arch/powerpc/pci/pciconf_ofmethod.c

107

tag |= reg & OFW_PCI_PHYS_HI_REGISTERMASK;

sys/arch/powerpc/pci/pciconf_ofmethod.c

115

genppc_pci_ofmethod_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data)

sys/arch/powerpc/pci/pciconf_ofmethod.c

119

if ((unsigned int)reg >= PCI_CONF_SIZE)

sys/arch/powerpc/pci/pciconf_ofmethod.c

124

tag |= reg & OFW_PCI_PHYS_HI_REGISTERMASK;

sys/arch/powerpc/pci/pciconf_ofmethod.c

97

genppc_pci_ofmethod_conf_read(void *v, pcitag_t tag, int reg)

sys/arch/powerpc/powerpc/db_disasm.c

416

unsigned reg;

sys/arch/powerpc/powerpc/db_disasm.c

811

if (spr == regs[i].reg)

sys/arch/powerpc/powerpc/db_disasm.c

958

const char *reg;

sys/arch/powerpc/powerpc/db_disasm.c

965

reg = "tbl";

sys/arch/powerpc/powerpc/db_disasm.c

968

reg = "tbu";

sys/arch/powerpc/powerpc/db_disasm.c

971

reg = 0;

sys/arch/powerpc/powerpc/db_disasm.c

973

if (reg == 0)

sys/arch/powerpc/powerpc/db_disasm.c

976

db_printf(", %s", reg);

sys/arch/powerpc/powerpc/db_interface.c

735

db_ppc4xx_mfdcr(db_expr_t reg)

sys/arch/powerpc/powerpc/db_interface.c

739

reg = (((reg & 0x1f) << 5) | ((reg >> 5) & 0x1f)) << 11;

sys/arch/powerpc/powerpc/db_interface.c

742

db_ppc4xx_dcrfunc[2] = 0x7c600286 | reg; /* mfdcr reg, r3 */

sys/arch/powerpc/powerpc/db_interface.c

752

db_ppc4xx_mtdcr(db_expr_t reg, db_expr_t val)

sys/arch/powerpc/powerpc/db_interface.c

756

reg = (((reg & 0x1f) << 5) | ((reg >> 5) & 0x1f)) << 11;

sys/arch/powerpc/powerpc/db_interface.c

759

db_ppc4xx_dcrfunc[2] = 0x7c600386 | reg; /* mtdcr r3, reg */

sys/arch/powerpc/powerpc/process_machdep.c

58

process_read_regs(struct lwp *l, struct reg *regs)

sys/arch/powerpc/powerpc/process_machdep.c

73

process_write_regs(struct lwp *l, const struct reg *regs)

sys/arch/powerpc/powerpc/trap.c

809

const int reg = EXC_ALI_RST(tf->tf_dsisr);

sys/arch/powerpc/powerpc/trap.c

811

uint64_t * const fpreg = &pcb->pcb_fpu.fpreg[reg];

sys/arch/powerpc/powerpc/trap.c

855

const int reg = EXC_ALI_RST(tf->tf_dsisr);

sys/arch/powerpc/powerpc/trap.c

857

uint64_t * const fpreg = &pcb->pcb_fpu.fpreg[reg];

sys/arch/prep/pci/prep_pciconf_direct.c

166

prep_pci_direct_conf_read(void *v, pcitag_t tag, int reg)

sys/arch/prep/pci/prep_pciconf_direct.c

172

if ((unsigned int)reg >= PCI_CONF_SIZE)

sys/arch/prep/pci/prep_pciconf_direct.c

187

data = in32rb(PCI_DCONF_BASE | tag | reg);

sys/arch/prep/pci/prep_pciconf_direct.c

195

prep_pci_direct_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data)

sys/arch/prep/pci/prep_pciconf_direct.c

201

(unsigned long)v, tag, reg, (unsigned long)data));

sys/arch/prep/pci/prep_pciconf_direct.c

203

if ((unsigned int)reg >= PCI_CONF_SIZE)

sys/arch/prep/pci/prep_pciconf_direct.c

219

out32rb(PCI_DCONF_BASE | tag | reg, data);

sys/arch/prep/pnpbus/mcclock_pnpbus.c

178

mcclock_pnpbus_write(struct mc146818_softc *sc, u_int reg, u_int datum)

sys/arch/prep/pnpbus/mcclock_pnpbus.c

186

bus_space_write_1(iot, ioh, 0, reg);

sys/arch/prep/pnpbus/mcclock_pnpbus.c

191

mcclock_pnpbus_read(struct mc146818_softc *sc, u_int reg)

sys/arch/prep/pnpbus/mcclock_pnpbus.c

200

bus_space_write_1(iot, ioh, 0, reg);

sys/arch/prep/prep/platform.c

102

u_int8_t reg;

sys/arch/prep/prep/platform.c

114

reg = inb(PREP_BUS_SPACE_IO + 0x92);

sys/arch/prep/prep/platform.c

115

reg &= ~1UL;

sys/arch/prep/prep/platform.c

116

outb(PREP_BUS_SPACE_IO + 0x92, reg);

sys/arch/prep/prep/platform.c

117

reg = inb(PREP_BUS_SPACE_IO + 0x92);

sys/arch/prep/prep/platform.c

118

reg |= 1;

sys/arch/prep/prep/platform.c

119

outb(PREP_BUS_SPACE_IO + 0x92, reg);

sys/arch/prep/stand/boot/siop.c

1136

uint32_t reg;

sys/arch/prep/stand/boot/siop.c

1174

reg = readb(addr + SIOP_SCNTL1);

sys/arch/prep/stand/boot/siop.c

1175

writeb(addr + SIOP_SCNTL1, reg | SCNTL1_RST);

sys/arch/prep/stand/boot/siop.c

1177

writeb(addr + SIOP_SCNTL1, reg);

sys/arch/riscv/dev/plic.c

155

uint32_t reg = PLIC_READ(sc, addr);

sys/arch/riscv/dev/plic.c

156

reg |= mask;

sys/arch/riscv/dev/plic.c

158

PLIC_WRITE(sc, addr, reg);

sys/arch/riscv/dev/plic.c

168

uint32_t reg = PLIC_READ(sc, addr);

sys/arch/riscv/dev/plic.c

169

reg &= ~mask;

sys/arch/riscv/dev/plic.c

170

PLIC_WRITE(sc, addr, reg);

sys/arch/riscv/dev/plic.c

59

#define PLIC_READ(sc, reg) \

sys/arch/riscv/dev/plic.c

60

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/riscv/dev/plic.c

61

#define PLIC_WRITE(sc, reg, val) \

sys/arch/riscv/dev/plic.c

62

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/riscv/fdt/clint_fdt.c

72

#define CLINT_READ(sc, reg) \

sys/arch/riscv/fdt/clint_fdt.c

73

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/riscv/fdt/clint_fdt.c

74

#define CLINT_WRITE(sc, reg, val) \

sys/arch/riscv/fdt/clint_fdt.c

75

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/riscv/fdt/cpu_fdt.c

137

uint64_t reg;

sys/arch/riscv/fdt/cpu_fdt.c

138

if (fdtbus_get_reg64(child, 0, &reg, NULL) != 0)

sys/arch/riscv/fdt/cpu_fdt.c

141

const cpuid_t hartid = reg;

sys/arch/riscv/fdt/cpu_fdt.c

82

uint64_t reg;

sys/arch/riscv/fdt/cpu_fdt.c

83

if (fdtbus_get_reg64(child, 0, &reg, NULL) != 0)

sys/arch/riscv/fdt/cpu_fdt.c

86

const cpuid_t hartid = reg;

sys/arch/riscv/fdt/pcihost_fdt.c

399

u_int reg;

sys/arch/riscv/fdt/pcihost_fdt.c

409

reg = (b << 16) | (d << 11) | (f << 8) | offset;

sys/arch/riscv/fdt/pcihost_fdt.c

413

reg = (b << 20) | (d << 15) | (f << 12) | offset;

sys/arch/riscv/fdt/pcihost_fdt.c

418

return bus_space_read_4(sc->sc_bst, sc->sc_bsh, reg);

sys/arch/riscv/fdt/pcihost_fdt.c

426

u_int reg;

sys/arch/riscv/fdt/pcihost_fdt.c

436

reg = (b << 16) | (d << 11) | (f << 8) | offset;

sys/arch/riscv/fdt/pcihost_fdt.c

440

reg = (b << 20) | (d << 15) | (f << 12) | offset;

sys/arch/riscv/fdt/pcihost_fdt.c

445

bus_space_write_4(sc->sc_bst, sc->sc_bsh, reg, val);

sys/arch/riscv/include/frame.h

38

struct reg tf_regs;

sys/arch/riscv/include/pcb.h

51

struct reg reg;

sys/arch/riscv/riscv/db_disasm.c

986

db_print_riscv_reg(unsigned reg, bool isfreg)

sys/arch/riscv/riscv/db_disasm.c

989

db_printf("f%d", reg);

sys/arch/riscv/riscv/db_disasm.c

992

db_printf("%s", riscv_registers[reg]);

sys/arch/riscv/riscv/process_machdep.c

45

process_read_regs(struct lwp *l, struct reg *regs)

sys/arch/riscv/riscv/process_machdep.c

55

process_write_regs(struct lwp *l, const struct reg *regs)

sys/arch/riscv/riscv/riscv_machdep.c

237

CTASSERT(sizeof(struct reg) == sizeof(__gregset_t));

sys/arch/riscv/riscv/riscv_machdep.c

247

*(struct reg *)mcp->__gregs = tf->tf_regs;

sys/arch/riscv/riscv/riscv_machdep.c

298

tf->tf_regs = *(const struct reg *)gr;

sys/arch/riscv/riscv/trap.c

293

for (unsigned reg = 1; reg < 32; reg++) {

sys/arch/riscv/riscv/trap.c

295

regname[reg - 1],

sys/arch/riscv/riscv/trap.c

296

tf->tf_regs.r_reg[reg - 1]);

sys/arch/riscv/riscv/trap.c

297

if (reg % 4 == 3)

sys/arch/riscv/sifive/fu540_ccache.c

100

#define WR4(sc, reg, val) \

sys/arch/riscv/sifive/fu540_ccache.c

101

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/riscv/sifive/fu540_ccache.c

102

#define WR8(sc, reg, val) \

sys/arch/riscv/sifive/fu540_ccache.c

103

bus_space_write_8((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/riscv/sifive/fu540_ccache.c

98

#define RD4(sc, reg) \

sys/arch/riscv/sifive/fu540_ccache.c

99

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/riscv/sifive/fu540_prci.c

115

fu540_prci_clk_get_rate_pll(struct fu540_prci_softc *sc, u_int reg)

sys/arch/riscv/sifive/fu540_prci.c

120

val = RD4(sc, reg);

sys/arch/riscv/sifive/fu540_prci.c

86

#define RD4(sc, reg) \

sys/arch/riscv/sifive/fu540_prci.c

87

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/riscv/sifive/fu540_prci.c

88

#define WR4(sc, reg, val) \

sys/arch/riscv/sifive/fu540_prci.c

89

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/riscv/starfive/jh7100_pinctrl.c

135

uint32_t reg = PCTLRD4(sc, regoff);

sys/arch/riscv/starfive/jh7100_pinctrl.c

136

uint32_t oreg = reg;

sys/arch/riscv/starfive/jh7100_pinctrl.c

137

reg &= ~regmask;

sys/arch/riscv/starfive/jh7100_pinctrl.c

138

reg |= regval;

sys/arch/riscv/starfive/jh7100_pinctrl.c

139

PCTLWR4(sc, regoff, reg);

sys/arch/riscv/starfive/jh7100_pinctrl.c

144

oreg, reg, regoff);

sys/arch/riscv/starfive/jh7100_pinctrl.c

58

#define GPIORD4(sc, reg) \

sys/arch/riscv/starfive/jh7100_pinctrl.c

59

bus_space_read_4((sc)->sc_bst, (sc)->sc_gpio_bsh, (reg))

sys/arch/riscv/starfive/jh7100_pinctrl.c

60

#define GPIOWR4(sc, reg, val) \

sys/arch/riscv/starfive/jh7100_pinctrl.c

61

bus_space_write_4((sc)->sc_bst, (sc)->sc_gpio_bsh, (reg), (val))

sys/arch/riscv/starfive/jh7100_pinctrl.c

77

#define PCTLRD4(sc, reg) \

sys/arch/riscv/starfive/jh7100_pinctrl.c

78

bus_space_read_4((sc)->sc_bst, (sc)->sc_padctl_bsh, (reg))

sys/arch/riscv/starfive/jh7100_pinctrl.c

79

#define PCTLWR4(sc, reg, val) \

sys/arch/riscv/starfive/jh7100_pinctrl.c

80

bus_space_write_4((sc)->sc_bst, (sc)->sc_padctl_bsh, (reg), (val))

sys/arch/riscv/starfive/jh7110_clkc.c

967

#define RD4(sc, reg) \

sys/arch/riscv/starfive/jh7110_clkc.c

968

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/riscv/starfive/jh7110_clkc.c

969

#define WR4(sc, reg, val) \

sys/arch/riscv/starfive/jh7110_clkc.c

970

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/riscv/starfive/jh7110_pcie.c

242

bus_size_t reg =

sys/arch/riscv/starfive/jh7110_pcie.c

248

return bus_space_read_4(sc->sc_bst, sc->sc_cfg_bsh, reg);

sys/arch/riscv/starfive/jh7110_pcie.c

267

bus_size_t reg =

sys/arch/riscv/starfive/jh7110_pcie.c

273

bus_space_write_4(sc->sc_bst, sc->sc_cfg_bsh, reg, data);

sys/arch/riscv/starfive/jh7110_pcie.c

489

uint32_t reg;

sys/arch/riscv/starfive/jh7110_pcie.c

491

reg = SCRD4(sc->sc_syscon,

sys/arch/riscv/starfive/jh7110_pcie.c

493

if (reg & DATA_LINK_ACTIVE)

sys/arch/riscv/starfive/jh7110_pcie.c

500

if ((reg & DATA_LINK_ACTIVE) == 0) {

sys/arch/riscv/starfive/jh7110_pcie.c

79

#define RD4(sc, reg) \

sys/arch/riscv/starfive/jh7110_pcie.c

80

bus_space_read_4((sc)->sc_bst, (sc)->sc_apb_bsh, (reg))

sys/arch/riscv/starfive/jh7110_pcie.c

81

#define WR4(sc, reg, val) \

sys/arch/riscv/starfive/jh7110_pcie.c

82

bus_space_write_4((sc)->sc_bst, (sc)->sc_apb_bsh, (reg), (val))

sys/arch/riscv/starfive/jh7110_pciephy.c

57

#define RD4(sc, reg) \

sys/arch/riscv/starfive/jh7110_pciephy.c

58

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/riscv/starfive/jh7110_pciephy.c

59

#define WR4(sc, reg, val) \

sys/arch/riscv/starfive/jh7110_pciephy.c

60

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/riscv/starfive/jh7110_pinctrl.c

102

#define RD4(sc, reg) \

sys/arch/riscv/starfive/jh7110_pinctrl.c

103

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/riscv/starfive/jh7110_pinctrl.c

104

#define WR4(sc, reg, val) \

sys/arch/riscv/starfive/jh7110_pinctrl.c

105

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/riscv/starfive/jh7110_syscon.c

52

#define RD4(sc, reg) \

sys/arch/riscv/starfive/jh7110_syscon.c

53

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/riscv/starfive/jh7110_syscon.c

54

#define WR4(sc, reg, val) \

sys/arch/riscv/starfive/jh7110_syscon.c

55

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/riscv/starfive/jh7110_syscon.c

75

jh7110_syscon_read_4(void *priv, bus_size_t reg)

sys/arch/riscv/starfive/jh7110_syscon.c

81

return RD4(sc, reg);

sys/arch/riscv/starfive/jh7110_syscon.c

85

jh7110_syscon_write_4(void *priv, bus_size_t reg, uint32_t val)

sys/arch/riscv/starfive/jh7110_syscon.c

91

WR4(sc, reg, val);

sys/arch/riscv/starfive/jh7110_trng.c

144

#define RD4(sc, reg) \

sys/arch/riscv/starfive/jh7110_trng.c

145

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/riscv/starfive/jh7110_trng.c

146

#define WR4(sc, reg, val) \

sys/arch/riscv/starfive/jh7110_trng.c

147

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/riscv/starfive/jh7110_trng.c

62

#define RD4(sc, reg) \

sys/arch/riscv/starfive/jh7110_trng.c

63

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/riscv/starfive/jh7110_trng.c

64

#define WR4(sc, reg, val) \

sys/arch/riscv/starfive/jh7110_trng.c

65

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/riscv/starfive/jh71x0_clkc.c

46

#define RD4(sc, reg) \

sys/arch/riscv/starfive/jh71x0_clkc.c

47

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/riscv/starfive/jh71x0_clkc.c

48

#define WR4(sc, reg, val) \

sys/arch/riscv/starfive/jh71x0_clkc.c

49

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/riscv/starfive/jh71x0_eth.c

66

const uint32_t reg = jh_sc->sc_phy_syscon_reg;

sys/arch/riscv/starfive/jh71x0_eth.c

70

uint32_t val = syscon_read_4(jh_sc->sc_syscon, reg);

sys/arch/riscv/starfive/jh71x0_eth.c

73

syscon_write_4(jh_sc->sc_syscon, reg, val);

sys/arch/riscv/starfive/jh71x0_temp.c

51

#define RD4(sc, reg) \

sys/arch/riscv/starfive/jh71x0_temp.c

52

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/riscv/starfive/jh71x0_temp.c

53

#define WR4(sc, reg, val) \

sys/arch/riscv/starfive/jh71x0_temp.c

54

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/riscv/starfive/jh71x0_usb.c

52

#define RD4(sc, reg) \

sys/arch/riscv/starfive/jh71x0_usb.c

53

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/arch/riscv/starfive/jh71x0_usb.c

54

#define WR4(sc, reg, val) \

sys/arch/riscv/starfive/jh71x0_usb.c

55

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/arch/rs6000/mca/mca_machdep.c

134

mca_conf_read(mca_chipset_tag_t mc, int slot, int reg)

sys/arch/rs6000/mca/mca_machdep.c

139

data = inb(RS6000_BUS_SPACE_IO + MCA_POS_REG(reg) + (slot<<16));

sys/arch/rs6000/mca/mca_machdep.c

149

mca_conf_write(mca_chipset_tag_t mc, int slot, int reg, int data)

sys/arch/rs6000/mca/mca_machdep.c

152

outb(RS6000_BUS_SPACE_IO + MCA_POS_REG(reg) + (slot<<16), data);

sys/arch/sandpoint/isa/mcclock_isa.c

149

mcclock_isa_read(struct mc146818_softc *sc, unsigned reg)

sys/arch/sandpoint/isa/mcclock_isa.c

152

bus_space_write_1(sc->sc_bst, sc->sc_bsh, 0, reg);

sys/arch/sandpoint/isa/mcclock_isa.c

157

mcclock_isa_write(struct mc146818_softc *sc, unsigned reg, unsigned datum)

sys/arch/sandpoint/isa/mcclock_isa.c

160

bus_space_write_1(sc->sc_bst, sc->sc_bsh, 0, reg);

sys/arch/sandpoint/pci/pci_machdep.c

212

pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg)

sys/arch/sandpoint/pci/pci_machdep.c

216

if ((unsigned int)reg >= PCI_CONF_SIZE)

sys/arch/sandpoint/pci/pci_machdep.c

219

out32rb(SANDPOINT_PCI_CONFIG_ADDR, tag | reg);

sys/arch/sandpoint/pci/pci_machdep.c

226

pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data)

sys/arch/sandpoint/pci/pci_machdep.c

229

if ((unsigned int)reg >= PCI_CONF_SIZE)

sys/arch/sandpoint/pci/pci_machdep.c

232

out32rb(SANDPOINT_PCI_CONFIG_ADDR, tag | reg);

sys/arch/sandpoint/stand/altboot/fxp.c

409

uint16_t reg;

sys/arch/sandpoint/stand/altboot/fxp.c

415

reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;

sys/arch/sandpoint/stand/altboot/fxp.c

417

reg = FXP_EEPROM_EECS;

sys/arch/sandpoint/stand/altboot/fxp.c

418

CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);

sys/arch/sandpoint/stand/altboot/fxp.c

421

reg | FXP_EEPROM_EESK);

sys/arch/sandpoint/stand/altboot/fxp.c

423

CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);

sys/arch/sandpoint/stand/altboot/fxp.c

467

uint16_t reg;

sys/arch/sandpoint/stand/altboot/fxp.c

478

reg = FXP_EEPROM_EECS;

sys/arch/sandpoint/stand/altboot/fxp.c

485

reg | FXP_EEPROM_EESK);

sys/arch/sandpoint/stand/altboot/fxp.c

490

CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);

sys/arch/sandpoint/stand/altboot/fxp.c

512

fxp_mdi_read(struct local *sc, int phy, int reg)

sys/arch/sandpoint/stand/altboot/fxp.c

518

(FXP_MDI_READ << 26) | (reg << 16) | (phy << 21));

sys/arch/sandpoint/stand/altboot/nvt.c

344

mii_read(struct local *l, int phy, int reg)

sys/arch/sandpoint/stand/altboot/nvt.c

350

CSR_WRITE_1(l, VR_MIIADR, reg);

sys/arch/sandpoint/stand/altboot/nvt.c

361

mii_write(struct local *l, int phy, int reg, int data)

sys/arch/sandpoint/stand/altboot/nvt.c

368

CSR_WRITE_1(l, VR_MIIADR, reg);

sys/arch/sandpoint/stand/altboot/pcn.c

297

pcn_mii_read(struct local *l, int phy, int reg)

sys/arch/sandpoint/stand/altboot/pcn.c

299

pcn_bcr_write(l, PCN_BCR33, MREG(reg) | MPHY(phy));

sys/arch/sandpoint/stand/altboot/pcn.c

304

pcn_mii_write(struct local *l, int phy, int reg, int val)

sys/arch/sandpoint/stand/altboot/pcn.c

306

pcn_bcr_write(l, PCN_BCR33, MREG(reg) | MPHY(phy));

sys/arch/sandpoint/stand/altboot/rge.c

152

uint32_t reg;

sys/arch/sandpoint/stand/altboot/rge.c

172

reg = en[0] | (en[1] << 8) | (en[2] << 16) | (en[3] << 24);

sys/arch/sandpoint/stand/altboot/rge.c

173

CSR_WRITE_4(l, RGE_IDR0, reg);

sys/arch/sandpoint/stand/altboot/rge.c

174

reg = en[4] | (en[5] << 8);

sys/arch/sandpoint/stand/altboot/rge.c

175

CSR_WRITE_4(l, RGE_IDR4, reg);

sys/arch/sandpoint/stand/altboot/rge.c

314

mii_read(struct local *l, int phy, int reg)

sys/arch/sandpoint/stand/altboot/rge.c

318

v = reg << 16;

sys/arch/sandpoint/stand/altboot/rge.c

329

mii_write(struct local *l, int phy, int reg, int data)

sys/arch/sandpoint/stand/altboot/rge.c

333

v = (reg << 16) | (data & 0xffff) | (1U << 31);

sys/arch/sandpoint/stand/altboot/sip.c

356

mii_read(struct local *l, int phy, int reg)

sys/arch/sandpoint/stand/altboot/sip.c

361

val = CSR_READ(l, SIP_BMCR + (reg << 2));

sys/arch/sandpoint/stand/altboot/sip.c

362

} while (reg == MII_BMSR && val == 0);

sys/arch/sandpoint/stand/altboot/sip.c

367

mii_write(struct local *l, int phy, int reg, int val)

sys/arch/sandpoint/stand/altboot/sip.c

370

CSR_WRITE(l, SIP_BMCR + (reg << 2), val);

sys/arch/sandpoint/stand/altboot/skg.c

210

uint16_t reg;

sys/arch/sandpoint/stand/altboot/skg.c

321

reg = CSR_READ_2(l, YUKON_GPCR);

sys/arch/sandpoint/stand/altboot/skg.c

322

reg |= GPCR_TXEN | GPCR_RXEN;

sys/arch/sandpoint/stand/altboot/skg.c

323

CSR_WRITE_2(l, YUKON_GPCR, reg);

sys/arch/sandpoint/stand/altboot/skg.c

399

mii_read(struct local *l, int phy, int reg)

sys/arch/sandpoint/stand/altboot/skg.c

403

CSR_WRITE_2(l, YUKON_SMICR, SMICR_PHYAD(phy) | SMICR_REGAD(reg) |

sys/arch/sandpoint/stand/altboot/skg.c

418

mii_write(struct local *l, int phy, int reg, int data)

sys/arch/sandpoint/stand/altboot/skg.c

423

CSR_WRITE_2(l, YUKON_SMICR, SMICR_PHYAD(phy) | SMICR_REGAD(reg) |

sys/arch/sandpoint/stand/altboot/sme.c

276

mii_read(struct local *l, int phy, int reg)

sys/arch/sandpoint/stand/altboot/sme.c

283

ctl = (phy << 11) | (reg << 6) | (0 << 1); /* READ op */

sys/arch/sandpoint/stand/altboot/sme.c

292

mii_write(struct local *l, int phy, int reg, int val)

sys/arch/sandpoint/stand/altboot/sme.c

299

ctl = (phy << 11) | (reg << 6) | (1 << 1); /* WRITE op */

sys/arch/sandpoint/stand/altboot/stg.c

165

uint32_t macctl, reg;

sys/arch/sandpoint/stand/altboot/stg.c

255

reg = CSR_READ_1(l, STGE_PhyCtrl);

sys/arch/sandpoint/stand/altboot/stg.c

256

switch (PC_LinkSpeed(reg)) {

sys/arch/sandpoint/stand/altboot/stg.c

267

if (reg & PC_PhyDuplexStatus) {

sys/arch/sandpoint/stand/altboot/stg.c

360

uint32_t reg;

sys/arch/sandpoint/stand/altboot/stg.c

363

reg = CSR_READ_4(l, STGE_AsicCtrl);

sys/arch/sandpoint/stand/altboot/stg.c

364

CSR_WRITE_4(l, STGE_AsicCtrl, reg | AC_GlobalReset | AC_RxReset |

sys/arch/sandpoint/stand/altboot/stg.c

366

AC_AutoInit | ((reg & AC_PhyMedia) ? AC_RstOut : 0));

sys/arch/sandpoint/stand/altboot/stg.c

384

mii_read(struct local *l, int phy, int reg)

sys/arch/sandpoint/stand/altboot/stg.c

391

data = (R0110 << 10) | (phy << 5) | reg;

sys/arch/sandpoint/stand/altboot/stg.c

412

mii_write(struct local *l, int phy, int reg, int val)

sys/arch/sandpoint/stand/altboot/stg.c

416

data = (W0101 << 28) | (phy << 23) | (reg << 18) | (A10 << 16);

sys/arch/sandpoint/stand/altboot/tlp.c

285

mii_read(struct local *l, int phy, int reg)

sys/arch/sandpoint/stand/altboot/tlp.c

289

data = (R110 << 10) | (phy << 5) | reg;

sys/arch/sandpoint/stand/altboot/tlp.c

324

mii_write(struct local *l, int phy, int reg, int val)

sys/arch/sandpoint/stand/altboot/tlp.c

328

data = (W101 << 28) | (phy << 23) | (reg << 18) | (02 << 16);

sys/arch/sandpoint/stand/altboot/vge.c

426

mii_read(struct local *l, int phy, int reg)

sys/arch/sandpoint/stand/altboot/vge.c

432

CSR_WRITE_1(l, VR_MIIADR, reg);

sys/arch/sandpoint/stand/altboot/vge.c

443

mii_write(struct local *l, int phy, int reg, int data)

sys/arch/sandpoint/stand/altboot/vge.c

450

CSR_WRITE_1(l, VR_MIIADR, reg);

sys/arch/sandpoint/stand/altboot/wm.c

354

mii_read(struct local *l, int phy, int reg)

sys/arch/sandpoint/stand/altboot/wm.c

358

data = (2U << 26) | MPHY(phy) | MREG(reg);

sys/arch/sandpoint/stand/altboot/wm.c

367

mii_write(struct local *l, int phy, int reg, int val)

sys/arch/sandpoint/stand/altboot/wm.c

371

data = (1U << 26) | MPHY(phy) | MREG(reg) | (val & 0xffff);

sys/arch/sbmips/sbmips/rtc.c

426

uint32_t reg;

sys/arch/sbmips/sbmips/rtc.c

428

reg = A_SMB_REGISTER(chan, R_SMB_FREQ);

sys/arch/sbmips/sbmips/rtc.c

429

WRITE_REG(reg, K_SMB_FREQ_100KHZ);

sys/arch/sbmips/sbmips/rtc.c

430

reg = A_SMB_REGISTER(chan, R_SMB_CONTROL);

sys/arch/sbmips/sbmips/rtc.c

431

WRITE_REG(reg, 0); /* not in direct mode, no interrupts, will poll */

sys/arch/sbmips/sbmips/rtc.c

437

uint32_t reg;

sys/arch/sbmips/sbmips/rtc.c

440

reg = A_SMB_REGISTER(chan, R_SMB_STATUS);

sys/arch/sbmips/sbmips/rtc.c

443

status = READ_REG(reg);

sys/arch/sbmips/sbmips/rtc.c

450

WRITE_REG(reg, (status & M_SMB_ERROR));

sys/arch/sbmips/sbmips/rtc.c

459

uint32_t reg;

sys/arch/sbmips/sbmips/rtc.c

477

reg = A_SMB_REGISTER(chan, R_SMB_CMD);

sys/arch/sbmips/sbmips/rtc.c

478

WRITE_REG(reg, (devaddr >> 8) & 0x7);

sys/arch/sbmips/sbmips/rtc.c

484

reg = A_SMB_REGISTER(chan, R_SMB_DATA);

sys/arch/sbmips/sbmips/rtc.c

485

WRITE_REG(reg, (devaddr & 0xff) & 0xff);

sys/arch/sbmips/sbmips/rtc.c

491

reg = A_SMB_REGISTER(chan, R_SMB_CMD);

sys/arch/sbmips/sbmips/rtc.c

492

WRITE_REG(reg, devaddr & 0xff);

sys/arch/sbmips/sbmips/rtc.c

499

reg = A_SMB_REGISTER(chan, R_SMB_START);

sys/arch/sbmips/sbmips/rtc.c

501

WRITE_REG(reg, V_SMB_TT(K_SMB_TT_WR2BYTE) | V_SMB_ADDR(slaveaddr));

sys/arch/sbmips/sbmips/rtc.c

503

WRITE_REG(reg, V_SMB_TT(K_SMB_TT_WR1BYTE) | V_SMB_ADDR(slaveaddr));

sys/arch/sbmips/sbmips/rtc.c

517

WRITE_REG(reg, V_SMB_TT(K_SMB_TT_RD1BYTE) | V_SMB_ADDR(slaveaddr));

sys/arch/sbmips/sbmips/rtc.c

523

reg = A_SMB_REGISTER(chan, R_SMB_DATA);

sys/arch/sbmips/sbmips/rtc.c

524

err = READ_REG(reg);

sys/arch/sbmips/sbmips/rtc.c

532

uint32_t reg;

sys/arch/sbmips/sbmips/rtc.c

549

reg = A_SMB_REGISTER(chan, R_SMB_CMD);

sys/arch/sbmips/sbmips/rtc.c

551

WRITE_REG(reg, (devaddr >> 8) & 0x7);

sys/arch/sbmips/sbmips/rtc.c

553

WRITE_REG(reg, devaddr & 0xff);

sys/arch/sbmips/sbmips/rtc.c

559

reg = A_SMB_REGISTER(chan, R_SMB_DATA);

sys/arch/sbmips/sbmips/rtc.c

561

WRITE_REG(reg, (devaddr & 0xff) | ((b & 0xff) << 8));

sys/arch/sbmips/sbmips/rtc.c

563

WRITE_REG(reg, b & 0xff);

sys/arch/sbmips/sbmips/rtc.c

571

reg = A_SMB_REGISTER(chan, R_SMB_START);

sys/arch/sbmips/sbmips/rtc.c

573

WRITE_REG(reg, V_SMB_TT(K_SMB_TT_WR3BYTE) | V_SMB_ADDR(slaveaddr));

sys/arch/sbmips/sbmips/rtc.c

575

WRITE_REG(reg, V_SMB_TT(K_SMB_TT_WR2BYTE) | V_SMB_ADDR(slaveaddr));

sys/arch/sbmips/sbmips/rtc.c

594

WRITE_REG(reg, V_SMB_TT(K_SMB_TT_RD1BYTE) | V_SMB_ADDR(slaveaddr));

sys/arch/sgimips/dev/crime.c

337

uint64_t reg;

sys/arch/sgimips/dev/crime.c

340

reg = bus_space_read_8(crm_iot, crm_ioh, CRIME_CONTROL)

sys/arch/sgimips/dev/crime.c

342

bus_space_write_8(crm_iot, crm_ioh, CRIME_CONTROL, reg);

sys/arch/sgimips/dev/crmfb.c

1071

reg = 0;

sys/arch/sgimips/dev/crmfb.c

1076

reg |= (((uint64_t)(v | 0x8000)) << shift);

sys/arch/sgimips/dev/crmfb.c

1081

reg);

sys/arch/sgimips/dev/crmfb.c

1082

DPRINTF("%04x: %016"PRIx64"\n", tlbptr + lptr, reg);

sys/arch/sgimips/dev/crmfb.c

1083

reg = 0;

sys/arch/sgimips/dev/crmfb.c

1090

CRIME_RE_TLB_A + tlbptr + lptr, reg);

sys/arch/sgimips/dev/crmfb.c

1091

DPRINTF("%04x: %016"PRIx64"\n", tlbptr + lptr, reg);

sys/arch/sgimips/dev/crmfb.c

1100

reg = ((uint64_t)page << 32) | (page + 1);

sys/arch/sgimips/dev/crmfb.c

1102

CRIME_RE_LINEAR_A + tlbptr, reg);

sys/arch/sgimips/dev/crmfb.c

729

crmfb_set_palette(struct crmfb_softc *sc, int reg, uint8_t r, uint8_t g,

sys/arch/sgimips/dev/crmfb.c

734

if (reg > 255 || sc->sc_depth != 8)

sys/arch/sgimips/dev/crmfb.c

741

crmfb_write_reg(sc, CRMFB_CMAP + (reg * 4), val);

sys/arch/sgimips/dev/crmfb.c

926

uint64_t reg;

sys/arch/sgimips/dev/ctl.c

147

uint32_t reg;

sys/arch/sgimips/dev/ctl.c

152

reg = bus_space_read_2(sc->iot, sc->ioh, CTL_CPUCTRL);

sys/arch/sgimips/dev/ctl.c

153

reg |= CTL_CPUCTRL_WDOG;

sys/arch/sgimips/dev/ctl.c

154

bus_space_write_2(sc->iot, sc->ioh, CTL_CPUCTRL, reg);

sys/arch/sgimips/dev/ctl.c

161

uint16_t reg;

sys/arch/sgimips/dev/ctl.c

166

reg = bus_space_read_2(sc->iot, sc->ioh, CTL_CPUCTRL_WDOG);

sys/arch/sgimips/dev/ctl.c

167

reg &= ~(CTL_CPUCTRL_WDOG);

sys/arch/sgimips/dev/ctl.c

168

bus_space_write_2(sc->iot, sc->ioh, CTL_CPUCTRL, reg);

sys/arch/sgimips/dev/dpclock.c

101

readreg(struct dpclock_softc *sc, uint32_t reg)

sys/arch/sgimips/dev/dpclock.c

104

(reg << 2) + sc->sc_offset);

sys/arch/sgimips/dev/dpclock.c

94

writereg(struct dpclock_softc *sc, uint32_t reg, uint8_t val)

sys/arch/sgimips/dev/dpclock.c

97

(reg << 2) + sc->sc_offset, val);

sys/arch/sgimips/dev/dsclock.c

74

#define ds1286_write(sc, reg, datum) \

sys/arch/sgimips/dev/dsclock.c

75

bus_space_write_1((sc)->sc_rtct, (sc)->sc_rtch, (reg << 2) + 3, (datum))

sys/arch/sgimips/dev/dsclock.c

76

#define ds1286_read(sc, reg) \

sys/arch/sgimips/dev/dsclock.c

77

bus_space_read_1((sc)->sc_rtct, (sc)->sc_rtch, (reg << 2) + 3)

sys/arch/sgimips/dev/imc.c

101

uint32_t reg;

sys/arch/sgimips/dev/imc.c

145

reg = bus_space_read_4(isc.iot, isc.ioh, IMC_CPUCTRL0);

sys/arch/sgimips/dev/imc.c

146

reg &= ~IMC_CPUCTRL0_NCHKMEMPAR;

sys/arch/sgimips/dev/imc.c

147

reg |= (IMC_CPUCTRL0_GPR | IMC_CPUCTRL0_MPR | IMC_CPUCTRL0_INTENA);

sys/arch/sgimips/dev/imc.c

148

bus_space_write_4(isc.iot, isc.ioh, IMC_CPUCTRL0, reg);

sys/arch/sgimips/dev/imc.c

151

reg = bus_space_read_4(isc.iot, isc.ioh, IMC_CPUCTRL1);

sys/arch/sgimips/dev/imc.c

152

reg = (reg & ~IMC_CPUCTRL1_MCHWMSK) | 13;

sys/arch/sgimips/dev/imc.c

161

reg |= IMC_CPUCTRL1_HPCFX;

sys/arch/sgimips/dev/imc.c

162

reg |= IMC_CPUCTRL1_EXP0FX;

sys/arch/sgimips/dev/imc.c

163

reg |= IMC_CPUCTRL1_EXP1FX;

sys/arch/sgimips/dev/imc.c

164

reg &= ~IMC_CPUCTRL1_HPCLITTLE;

sys/arch/sgimips/dev/imc.c

165

reg &= ~IMC_CPUCTRL1_EXP0LITTLE;

sys/arch/sgimips/dev/imc.c

166

reg &= ~IMC_CPUCTRL1_EXP1LITTLE;

sys/arch/sgimips/dev/imc.c

168

bus_space_write_4(isc.iot, isc.ioh, IMC_CPUCTRL1, reg);

sys/arch/sgimips/dev/imc.c

178

reg = bus_space_read_4(isc.iot, isc.ioh, IMC_GIO64ARB);

sys/arch/sgimips/dev/imc.c

179

reg &= (IMC_GIO64ARB_GRX64 | IMC_GIO64ARB_GRXRT | IMC_GIO64ARB_GRXMST);

sys/arch/sgimips/dev/imc.c

183

reg |= IMC_GIO64ARB_ONEGIO;

sys/arch/sgimips/dev/imc.c

184

reg |= (IMC_GIO64ARB_EXP0RT | IMC_GIO64ARB_EXP1RT);

sys/arch/sgimips/dev/imc.c

185

reg |= (IMC_GIO64ARB_EXP0MST | IMC_GIO64ARB_EXP1MST);

sys/arch/sgimips/dev/imc.c

186

reg &= ~(IMC_GIO64ARB_HPC64 |

sys/arch/sgimips/dev/imc.c

195

reg |= IMC_GIO64ARB_ONEGIO | IMC_GIO64ARB_HPC64;

sys/arch/sgimips/dev/imc.c

200

reg |= (IMC_GIO64ARB_EXP0RT | IMC_GIO64ARB_EXP1RT);

sys/arch/sgimips/dev/imc.c

201

reg |= (IMC_GIO64ARB_EXP0MST | IMC_GIO64ARB_EXP1MST);

sys/arch/sgimips/dev/imc.c

204

reg |= (IMC_GIO64ARB_EISAMST | IMC_GIO64ARB_EISA64);

sys/arch/sgimips/dev/imc.c

212

reg |= (IMC_GIO64ARB_HPCEXP64 | IMC_GIO64ARB_EXP0PIPE);

sys/arch/sgimips/dev/imc.c

216

reg |= (IMC_GIO64ARB_EXP0RT |

sys/arch/sgimips/dev/imc.c

220

reg |= (IMC_GIO64ARB_EXP1PIPE |

sys/arch/sgimips/dev/imc.c

227

bus_space_write_4(isc.iot, isc.ioh, IMC_GIO64ARB, reg);

sys/arch/sgimips/dev/imc.c

286

uint32_t reg;

sys/arch/sgimips/dev/imc.c

289

reg = bus_space_read_4(isc.iot, isc.ioh, IMC_CPUCTRL0);

sys/arch/sgimips/dev/imc.c

290

reg &= ~(IMC_CPUCTRL0_WDOG);

sys/arch/sgimips/dev/imc.c

291

bus_space_write_4(isc.iot, isc.ioh, IMC_CPUCTRL0, reg);

sys/arch/sgimips/dev/imc.c

297

uint32_t reg;

sys/arch/sgimips/dev/imc.c

300

reg = bus_space_read_4(isc.iot, isc.ioh, IMC_CPUCTRL0);

sys/arch/sgimips/dev/imc.c

301

reg |= IMC_CPUCTRL0_WDOG;

sys/arch/sgimips/dev/imc.c

302

bus_space_write_4(isc.iot, isc.ioh, IMC_CPUCTRL0, reg);

sys/arch/sgimips/dev/imc.c

310

uint32_t reg;

sys/arch/sgimips/dev/imc.c

329

reg = bus_space_read_4(isc.iot, isc.ioh, IMC_GIO64ARB);

sys/arch/sgimips/dev/imc.c

333

reg |= IMC_GIO64ARB_EXP0RT;

sys/arch/sgimips/dev/imc.c

335

reg |= IMC_GIO64ARB_EXP1RT;

sys/arch/sgimips/dev/imc.c

337

reg |= IMC_GIO64ARB_GRXRT;

sys/arch/sgimips/dev/imc.c

342

reg |= IMC_GIO64ARB_EXP0MST;

sys/arch/sgimips/dev/imc.c

344

reg |= IMC_GIO64ARB_EXP1MST;

sys/arch/sgimips/dev/imc.c

346

reg |= IMC_GIO64ARB_GRXMST;

sys/arch/sgimips/dev/imc.c

351

reg |= IMC_GIO64ARB_EXP0PIPE;

sys/arch/sgimips/dev/imc.c

353

reg |= IMC_GIO64ARB_EXP1PIPE;

sys/arch/sgimips/dev/imc.c

358

reg &= ~IMC_GIO64ARB_EXP0RT;

sys/arch/sgimips/dev/imc.c

360

reg &= ~IMC_GIO64ARB_EXP1RT;

sys/arch/sgimips/dev/imc.c

362

reg &= ~IMC_GIO64ARB_GRXRT;

sys/arch/sgimips/dev/imc.c

367

reg &= ~IMC_GIO64ARB_EXP0MST;

sys/arch/sgimips/dev/imc.c

369

reg &= ~IMC_GIO64ARB_EXP1MST;

sys/arch/sgimips/dev/imc.c

371

reg &= ~IMC_GIO64ARB_GRXMST;

sys/arch/sgimips/dev/imc.c

376

reg &= ~IMC_GIO64ARB_EXP0PIPE;

sys/arch/sgimips/dev/imc.c

378

reg &= ~IMC_GIO64ARB_EXP1PIPE;

sys/arch/sgimips/dev/imc.c

383

reg &= ~IMC_GIO64ARB_EXP064;

sys/arch/sgimips/dev/imc.c

385

reg &= ~IMC_GIO64ARB_EXP164;

sys/arch/sgimips/dev/imc.c

390

reg |= IMC_GIO64ARB_EXP064;

sys/arch/sgimips/dev/imc.c

392

reg |= IMC_GIO64ARB_EXP164;

sys/arch/sgimips/dev/imc.c

396

reg &= ~IMC_GIO64ARB_HPCEXP64;

sys/arch/sgimips/dev/imc.c

399

reg |= IMC_GIO64ARB_HPCEXP64;

sys/arch/sgimips/dev/imc.c

401

bus_space_write_4(isc.iot, isc.ioh, IMC_GIO64ARB, reg);

sys/arch/sgimips/dev/imc.c

415

uint32_t reg;

sys/arch/sgimips/dev/imc.c

420

reg = bus_space_read_4(isc.iot, isc.ioh, IMC_CPUCTRL0);

sys/arch/sgimips/dev/imc.c

421

reg |= IMC_CPUCTRL0_NCHKMEMPAR;

sys/arch/sgimips/dev/imc.c

422

bus_space_write_4(isc.iot, isc.ioh, IMC_CPUCTRL0, reg);

sys/arch/sgimips/dev/imc.c

428

uint32_t reg;

sys/arch/sgimips/dev/imc.c

433

reg = bus_space_read_4(isc.iot, isc.ioh, IMC_CPUCTRL0);

sys/arch/sgimips/dev/imc.c

434

reg &= ~IMC_CPUCTRL0_NCHKMEMPAR;

sys/arch/sgimips/dev/imc.c

435

bus_space_write_4(isc.iot, isc.ioh, IMC_CPUCTRL0, reg);

sys/arch/sgimips/dev/imc.c

441

uint32_t reg;

sys/arch/sgimips/dev/imc.c

446

reg = bus_space_read_4(isc.iot, isc.ioh, IMC_CPUCTRL0);

sys/arch/sgimips/dev/imc.c

448

return reg & IMC_CPUCTRL0_NCHKMEMPAR;

sys/arch/sgimips/dev/pic.c

108

reg = bus_space_read_4(psc.iot, psc.ioh, PIC_SYSID);

sys/arch/sgimips/dev/pic.c

109

reg = (reg >> PIC_SYSID_REVSHIFT) & PIC_SYSID_REVMASK;

sys/arch/sgimips/dev/pic.c

110

printf("\npic0: Revision %c", reg + 64);

sys/arch/sgimips/dev/pic.c

113

reg = bus_space_read_4(psc.iot, psc.ioh, PIC_CPUCTRL);

sys/arch/sgimips/dev/pic.c

114

reg |= (PIC_CPUCTRL_REFRESH | PIC_CPUCTRL_BIGENDIAN | PIC_CPUCTRL_MPR |

sys/arch/sgimips/dev/pic.c

116

bus_space_write_4(psc.iot, psc.ioh, PIC_CPUCTRL, reg);

sys/arch/sgimips/dev/pic.c

119

reg = bus_space_read_4(psc.iot, psc.ioh, PIC_MODE);

sys/arch/sgimips/dev/pic.c

120

printf(": dblk (0x%x), iblk (0x%x)\n", reg & PIC_MODE_DBSIZ,

sys/arch/sgimips/dev/pic.c

121

reg & PIC_MODE_IBSIZ);

sys/arch/sgimips/dev/pic.c

147

if (reg & PIC_MODE_NOCACHE)

sys/arch/sgimips/dev/pic.c

152

if (reg & PIC_MODE_ISTREAM)

sys/arch/sgimips/dev/pic.c

155

if (reg & PIC_MODE_STOREPARTIAL)

sys/arch/sgimips/dev/pic.c

158

if (reg & PIC_MODE_BUSDRIVE)

sys/arch/sgimips/dev/pic.c

162

reg = bus_space_read_4(psc.iot, psc.ioh, PIC_GIO32ARB_SLOT0);

sys/arch/sgimips/dev/pic.c

163

reg &= ~(PIC_GIO32ARB_SLOT_SLAVE | PIC_GIO32ARB_SLOT_LONG);

sys/arch/sgimips/dev/pic.c

164

bus_space_write_4(psc.iot, psc.ioh, PIC_GIO32ARB_SLOT0, reg);

sys/arch/sgimips/dev/pic.c

166

reg = bus_space_read_4(psc.iot, psc.ioh, PIC_GIO32ARB_SLOT1);

sys/arch/sgimips/dev/pic.c

167

reg &= ~(PIC_GIO32ARB_SLOT_SLAVE | PIC_GIO32ARB_SLOT_LONG);

sys/arch/sgimips/dev/pic.c

168

bus_space_write_4(psc.iot, psc.ioh, PIC_GIO32ARB_SLOT1, reg);

sys/arch/sgimips/dev/pic.c

222

uint32_t reg;

sys/arch/sgimips/dev/pic.c

224

reg = bus_space_read_4(psc.iot, psc.ioh, PIC_CPUCTRL);

sys/arch/sgimips/dev/pic.c

225

reg |= PIC_CPUCTRL_WDOG;

sys/arch/sgimips/dev/pic.c

226

bus_space_write_4(psc.iot, psc.ioh, PIC_CPUCTRL, reg);

sys/arch/sgimips/dev/pic.c

232

uint32_t reg;

sys/arch/sgimips/dev/pic.c

234

reg = bus_space_read_4(psc.iot, psc.ioh, PIC_CPUCTRL);

sys/arch/sgimips/dev/pic.c

235

reg &= ~(PIC_CPUCTRL_WDOG);

sys/arch/sgimips/dev/pic.c

236

bus_space_write_4(psc.iot, psc.ioh, PIC_CPUCTRL, reg);

sys/arch/sgimips/dev/pic.c

251

uint32_t reg;

sys/arch/sgimips/dev/pic.c

262

reg = bus_space_read_4(psc.iot, psc.ioh, (slot == GIO_SLOT_EXP0) ?

sys/arch/sgimips/dev/pic.c

266

reg &= ~PIC_GIO32ARB_SLOT_LONG;

sys/arch/sgimips/dev/pic.c

269

reg |= PIC_GIO32ARB_SLOT_LONG;

sys/arch/sgimips/dev/pic.c

272

reg &= ~PIC_GIO32ARB_SLOT_SLAVE;

sys/arch/sgimips/dev/pic.c

275

reg |= PIC_GIO32ARB_SLOT_SLAVE;

sys/arch/sgimips/dev/pic.c

278

PIC_GIO32ARB_SLOT0 : PIC_GIO32ARB_SLOT1, reg);

sys/arch/sgimips/dev/pic.c

94

uint32_t reg;

sys/arch/sgimips/dev/zs.c

532

zs_read_reg(struct zs_chanstate *cs, uint8_t reg)

sys/arch/sgimips/dev/zs.c

538

(ZS_REG_CSR << 2) + 3, reg);

sys/arch/sgimips/dev/zs.c

547

zs_write_reg(struct zs_chanstate *cs, uint8_t reg, uint8_t val)

sys/arch/sgimips/dev/zs.c

552

(ZS_REG_CSR << 2) + 3, reg);

sys/arch/sgimips/gio/newport.c

674

cmap_reg_read(struct newport_devconfig *dc, uint8_t id, uint8_t reg)

sys/arch/sgimips/gio/newport.c

684

(reg << REX3_DCBMODE_DCBCRS_SHIFT) |

sys/arch/sgimips/gio/pci_gio.c

250

giopci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg)

sys/arch/sgimips/gio/pci_gio.c

256

if ((unsigned int)reg >= PCI_CONF_SIZE)

sys/arch/sgimips/gio/pci_gio.c

264

if (reg >= sc->sc_pci_len) {

sys/arch/sgimips/gio/pci_gio.c

265

DPRINTF(("giopci_conf_read: reg 0x%x out of bounds\n", reg));

sys/arch/sgimips/gio/pci_gio.c

269

DPRINTF(("giopci_conf_read: reg 0x%x = 0x", reg));

sys/arch/sgimips/gio/pci_gio.c

270

data = bus_space_read_4(sc->sc_iot, sc->sc_ioh, reg);

sys/arch/sgimips/gio/pci_gio.c

277

giopci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data)

sys/arch/sgimips/gio/pci_gio.c

282

if ((unsigned int)reg >= PCI_CONF_SIZE)

sys/arch/sgimips/gio/pci_gio.c

290

if (reg >= sc->sc_pci_len) {

sys/arch/sgimips/gio/pci_gio.c

292

"(val = 0x%08x)\n", reg, data));

sys/arch/sgimips/gio/pci_gio.c

296

DPRINTF(("giopci_conf_write: reg 0x%x = 0x%08x\n", reg, data));

sys/arch/sgimips/gio/pci_gio.c

297

bus_space_write_4(sc->sc_iot, sc->sc_ioh, reg, data);

sys/arch/sgimips/hpc/button.c

127

uint8_t reg;

sys/arch/sgimips/hpc/button.c

129

reg = bus_space_read_4(sc->sc_tag, sc->sc_hreg, 0);

sys/arch/sgimips/hpc/button.c

132

if ((reg & IOC_PANEL_POWER_IRQ) == 0) {

sys/arch/sgimips/hpc/button.c

140

if ((reg & IOC_PANEL_VDOWN_HOLD) == 0)

sys/arch/sgimips/hpc/button.c

142

if ((reg & IOC_PANEL_VUP_HOLD) == 0)

sys/arch/sgimips/hpc/hpc.c

595

uint32_t reg;

sys/arch/sgimips/hpc/hpc.c

599

reg = *(uint32_t *)MIPS_PHYS_TO_KSEG1(ga->ga_addr +

sys/arch/sgimips/hpc/hpc.c

602

if (((reg >> HPC1_REVSHIFT) & HPC1_REVMASK) ==

sys/arch/sgimips/hpc/if_sq.c

972

uint32_t reg;

sys/arch/sgimips/hpc/if_sq.c

974

reg = sq_hpc_read(sc, sc->hpc_regs->enetr_ctl);

sys/arch/sgimips/hpc/if_sq.c

976

device_xname(sc->sc_dev), i, reg));

sys/arch/sgimips/hpc/pi1ppc.c

682

r_reg(int reg, struct pi1ppc_softc *pi1ppc)

sys/arch/sgimips/hpc/pi1ppc.c

687

if(reg == AT_STAT_REG) {

sys/arch/sgimips/hpc/pi1ppc.c

702

if(reg == AT_CTL_REG) {

sys/arch/sgimips/hpc/pi1ppc.c

719

if(reg == AT_DATA_REG) {

sys/arch/sgimips/hpc/pi1ppc.c

731

w_reg(int reg, struct pi1ppc_softc *pi1ppc, uint8_t byte)

sys/arch/sgimips/hpc/pi1ppc.c

736

if(reg == AT_CTL_REG) {

sys/arch/sgimips/hpc/pi1ppc.c

750

if(reg == AT_DATA_REG) {

sys/arch/sgimips/hpc/pi1ppc.c

764

register int reg;

sys/arch/sgimips/hpc/pi1ppc.c

77

static uint8_t r_reg(int reg, struct pi1ppc_softc *pi1ppc);

sys/arch/sgimips/hpc/pi1ppc.c

78

static void w_reg(int reg, struct pi1ppc_softc *pi1ppc, uint8_t byte);

sys/arch/sgimips/hpc/pi1ppc.c

786

reg = mi->arg[1].i;

sys/arch/sgimips/hpc/pi1ppc.c

792

w_reg(reg, pi1ppc, *ptr++);

sys/arch/sgimips/hpc/pi1ppc.c

798

w_reg(reg, pi1ppc, *ptr++);

sys/arch/sgimips/hpc/pi1ppc.c

808

reg = mi->arg[1].i;

sys/arch/sgimips/hpc/pi1ppc.c

815

*ptr++ = r_reg(reg, pi1ppc) & mask;

sys/arch/sgimips/hpc/pi1ppc.c

821

*ptr++ = r_reg(reg, pi1ppc) & mask;

sys/arch/sgimips/hpc/pi1ppc.c

861

reg = mi->arg[0].i;

sys/arch/sgimips/hpc/pi1ppc.c

867

w_reg(reg, pi1ppc, *p++);

sys/arch/sgimips/hpc/wdsc.c

102

vaddr_t reset, asr, reg;

sys/arch/sgimips/hpc/wdsc.c

121

reg = *(volatile uint32_t *)asr;

sys/arch/sgimips/hpc/wdsc.c

123

if ((reg & 0xff) == SBIC_ASR_INT)

sys/arch/sgimips/hpc/wdsc.c

126

if (((reg >> 8) & 0xff) == SBIC_ASR_INT)

sys/arch/sgimips/mace/if_mec.c

746

mec_mii_readreg(device_t self, int phy, int reg, uint16_t *val)

sys/arch/sgimips/mace/if_mec.c

758

(phy << MEC_PHY_ADDR_DEVSHIFT) | (reg & MEC_PHY_ADDR_REGISTER));

sys/arch/sgimips/mace/if_mec.c

778

mec_mii_writereg(device_t self, int phy, int reg, uint16_t val)

sys/arch/sgimips/mace/if_mec.c

786

printf("timed out writing %x: %hx\n", reg, val);

sys/arch/sgimips/mace/if_mec.c

791

(phy << MEC_PHY_ADDR_DEVSHIFT) | (reg & MEC_PHY_ADDR_REGISTER));

sys/arch/sgimips/mace/mavb.c

336

ad1843_addr_t reg;

sys/arch/sgimips/mace/mavb.c

389

reg = AD1843_DAC2_TO_MIXER + mc->dev - AD1843_DAC2_GAIN;

sys/arch/sgimips/mace/mavb.c

390

value = ad1843_reg_read(sc, reg);

sys/arch/sgimips/mace/mavb.c

394

ad1843_reg_write(sc, reg, value);

sys/arch/sgimips/mace/mavb.c

410

reg = AD1843_DAC2_TO_MIXER + mc->dev - AD1843_DAC2_MUTE;

sys/arch/sgimips/mace/mavb.c

411

value = ad1843_reg_read(sc, reg);

sys/arch/sgimips/mace/mavb.c

416

ad1843_reg_write(sc, reg, value);

sys/arch/sgimips/mace/mavb.c

459

ad1843_addr_t reg;

sys/arch/sgimips/mace/mavb.c

499

reg = AD1843_DAC2_TO_MIXER + mc->dev - AD1843_DAC2_GAIN;

sys/arch/sgimips/mace/mavb.c

500

value = ad1843_reg_read(sc, reg);

sys/arch/sgimips/mace/mavb.c

523

reg = AD1843_DAC2_TO_MIXER + mc->dev - AD1843_DAC2_MUTE;

sys/arch/sgimips/mace/mavb.c

524

value = ad1843_reg_read(sc, reg);

sys/arch/sgimips/mace/pci_mace.c

222

macepci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg)

sys/arch/sgimips/mace/pci_mace.c

226

if ((unsigned int)reg >= PCI_CONF_SIZE)

sys/arch/sgimips/mace/pci_mace.c

229

bus_space_write_4(pc->iot, pc->ioh, MACE_PCI_CONFIG_ADDR, (tag | reg));

sys/arch/sgimips/mace/pci_mace.c

237

macepci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data)

sys/arch/sgimips/mace/pci_mace.c

240

if ((unsigned int)reg >= PCI_CONF_SIZE)

sys/arch/sgimips/mace/pci_mace.c

243

bus_space_write_4(pc->iot, pc->ioh, MACE_PCI_CONFIG_ADDR, (tag | reg));

sys/arch/sgimips/pci/pci_machdep.c

103

pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg)

sys/arch/sgimips/pci/pci_machdep.c

106

return (*pc->pc_conf_read)(pc, tag, reg);

sys/arch/sgimips/pci/pci_machdep.c

110

pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data)

sys/arch/sgimips/pci/pci_machdep.c

113

(*pc->pc_conf_write)(pc, tag, reg, data);

sys/arch/sgimips/stand/common/iris_scsireg.h

385

#define SCSI_PHASE(reg) ((reg) & PHASE_MASK)

sys/arch/sgimips/stand/common/iris_zs.c

102

zs_write(dev, reg);

sys/arch/sgimips/stand/common/iris_zs.c

99

zs_write_reg(void *dev, uint8_t reg, uint8_t val)

sys/arch/sh3/dev/shpcic.c

287

shpcic_conf_read(void *v, pcitag_t tag, int reg)

sys/arch/sh3/dev/shpcic.c

292

if ((unsigned int)reg >= PCI_CONF_SIZE)

sys/arch/sh3/dev/shpcic.c

296

_reg_write_4(SH4_PCIPAR, tag | reg);

sys/arch/sh3/dev/shpcic.c

305

shpcic_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data)

sys/arch/sh3/dev/shpcic.c

309

if ((unsigned int)reg >= PCI_CONF_SIZE)

sys/arch/sh3/dev/shpcic.c

313

_reg_write_4(SH4_PCIPAR, tag | reg);

sys/arch/sh3/dev/shpcicvar.h

40

pcireg_t shpcic_conf_read(void *v, pcitag_t tag, int reg);

sys/arch/sh3/dev/shpcicvar.h

41

void shpcic_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data);

sys/arch/sh3/sh3/core_machdep.c

101

struct reg intreg;

sys/arch/sh3/sh3/process_machdep.c

113

process_read_regs(struct lwp *l, struct reg *regs)

sys/arch/sh3/sh3/process_machdep.c

146

process_write_regs(struct lwp *l, const struct reg *regs)

sys/arch/shark/isa/clock.c

197

mc146818_read(void *sc, unsigned reg)

sys/arch/shark/isa/clock.c

200

outb(IO_RTC, reg);

sys/arch/shark/isa/clock.c

205

mc146818_write(void *sc, unsigned reg, unsigned datum)

sys/arch/shark/isa/clock.c

208

outb(IO_RTC, reg);

sys/arch/shark/ofw/vlpci.c

124

uint8_t reg;

sys/arch/shark/ofw/vlpci.c

129

reg = bus_space_read_1(&isa_io_bs_tag, sc->sc_reg_ioh,

sys/arch/shark/ofw/vlpci.c

132

return reg;

sys/arch/shark/shark/ns87307reg.h

203

#define NSIO_READ_REG( iot, ioh, reg, value ) \

sys/arch/shark/shark/ns87307reg.h

205

bus_space_write_1(iot, ioh, NSIO_OFFSET_INDEX, reg ); \

sys/arch/shark/shark/ns87307reg.h

219

#define NSIO_WRITE_REG( iot, ioh, reg, value ) \

sys/arch/shark/shark/ns87307reg.h

221

bus_space_write_1(iot, ioh, NSIO_OFFSET_INDEX, reg ); \

sys/arch/shark/shark/sequoia.c

632

void sequoiaWrite(int reg,u_int16_t seqReg)

sys/arch/shark/shark/sequoia.c

642

if (reg == PMC_FOMPCR_REG) {

sys/arch/shark/shark/sequoia.c

643

bus_space_write_2(&isa_io_bs_tag,sequoia_ioh,SEQUOIA_INDEX_OFFSET,reg);

sys/arch/shark/shark/sequoia.c

653

if(sequoia_index_cache != reg)

sys/arch/shark/shark/sequoia.c

655

sequoia_index_cache = reg;

sys/arch/shark/shark/sequoia.c

656

bus_space_write_2(&isa_io_bs_tag,sequoia_ioh,SEQUOIA_INDEX_OFFSET,reg);

sys/arch/shark/shark/sequoia.c

662

void sequoiaRead (int reg,u_int16_t * seqReg_ptr)

sys/arch/shark/shark/sequoia.c

667

if(sequoia_index_cache != reg)

sys/arch/shark/shark/sequoia.c

669

sequoia_index_cache = reg;

sys/arch/shark/shark/sequoia.c

670

bus_space_write_2(&isa_io_bs_tag,sequoia_ioh,SEQUOIA_INDEX_OFFSET,reg);

sys/arch/shark/shark/sequoia.h

5070

void sequoiaWrite(int reg,u_int16_t value);

sys/arch/shark/shark/sequoia.h

5071

void sequoiaRead(int reg,u_int16_t * value_ptr);

sys/arch/sparc/dev/audioamd.c

254

audioamd_codec_dread(struct am7930_softc *amsc, int reg)

sys/arch/sparc/dev/audioamd.c

258

return bus_space_read_1(sc->sc_bt, sc->sc_bh, reg);

sys/arch/sparc/dev/audioamd.c

263

audioamd_codec_dwrite(struct am7930_softc *amsc, int reg, uint8_t val)

sys/arch/sparc/dev/audioamd.c

267

bus_space_write_1(sc->sc_bt, sc->sc_bh, reg, val);

sys/arch/sparc/dev/cgfourteen.c

1386

int line, cnt, pre, words, pwrds = 0, post, reg;

sys/arch/sparc/dev/cgfourteen.c

1413

reg = 8;

sys/arch/sparc/dev/cgfourteen.c

1417

reg++;

sys/arch/sparc/dev/cgfourteen.c

1422

sxi(SX_ROP, reg, reg, reg + 32, cnt - 1);

sys/arch/sparc/dev/cgfourteen.c

1423

reg += cnt;

sys/arch/sparc/dev/cgfourteen.c

1427

sxi(SX_ROPB, reg, 7, reg + 32, 0);

sys/arch/sparc/dev/cgfourteen.c

1428

reg++;

sys/arch/sparc/dev/cgfourteen.c

1436

cg14_slurp(int reg, uint32_t addr, int cnt)

sys/arch/sparc/dev/cgfourteen.c

1441

sxm(SX_LD, addr, reg, num - 1);

sys/arch/sparc/dev/cgfourteen.c

1443

reg += num;

sys/arch/sparc/dev/cgfourteen.c

1449

cg14_spit(int reg, uint32_t addr, int cnt)

sys/arch/sparc/dev/cgfourteen.c

1454

sxm(SX_ST, addr, reg, num - 1);

sys/arch/sparc/dev/cgfourteen.c

1456

reg += num;

sys/arch/sparc/dev/cgfourteen.c

1642

uint32_t reg;

sys/arch/sparc/dev/cgfourteen.c

1644

reg = *data8;

sys/arch/sparc/dev/cgfourteen.c

1645

cg14_set_mask(sc, reg << 24);

sys/arch/sparc/dev/cgfourteen.c

1654

uint32_t reg;

sys/arch/sparc/dev/cgfourteen.c

1656

reg = *data16;

sys/arch/sparc/dev/cgfourteen.c

1657

cg14_set_mask(sc, reg << 16);

sys/arch/sparc/dev/cgfourteen.c

1726

int i, j, x, y, wi, he, r, g, b, aval, cnt, reg;

sys/arch/sparc/dev/cgfourteen.c

1803

reg = 8;

sys/arch/sparc/dev/cgfourteen.c

1809

reg = 8 + in;

sys/arch/sparc/dev/cgfourteen.c

1814

sxm(SX_STUQ0, next, reg, q - 1);

sys/arch/sparc/dev/cgfourteen.c

1817

reg += (q << 2);

sys/arch/sparc/dev/cgfourteen.c

1820

sxm(SX_STB, next, reg, cnt - 1);

sys/arch/sparc/dev/cgfourteen.c

183

#define sxm(inst, addr, reg, count) sta((addr) & ~7, ASI_SX, inst((reg), (count), (addr) & 7))

sys/arch/sparc/dev/cgtwo.c

191

offsetof(struct cg2fb, status.reg),

sys/arch/sparc/dev/esp_obio.c

262

esp_read_reg(struct ncr53c9x_softc *sc, int reg)

sys/arch/sparc/dev/esp_obio.c

266

return bus_space_read_1(esc->sc_bustag, esc->sc_reg, reg * 4);

sys/arch/sparc/dev/esp_obio.c

270

esp_write_reg(struct ncr53c9x_softc *sc, int reg, uint8_t v)

sys/arch/sparc/dev/esp_obio.c

274

bus_space_write_1(esc->sc_bustag, esc->sc_reg, reg * 4, v);

sys/arch/sparc/dev/rtc.c

82

mc146818_read(void *cookie, u_int reg)

sys/arch/sparc/dev/rtc.c

86

bus_space_write_1(sc->sc_bt, sc->sc_bh, RTC_ADDR, reg);

sys/arch/sparc/dev/rtc.c

91

mc146818_write(void *cookie, u_int reg, u_int datum)

sys/arch/sparc/dev/rtc.c

95

bus_space_write_1(sc->sc_bt, sc->sc_bh, RTC_ADDR, reg);

sys/arch/sparc/dev/sxreg.h

236

#define SX_STBS(reg, cnt, o) (0x80000000 | ((cnt) << 23) | SX_STORE_SELECT \

sys/arch/sparc/dev/sxreg.h

237

| SX_UBYTE_0 | (reg << 7) | (o))

sys/arch/sparc/dev/sxvar.h

66

uint32_t reg;

sys/arch/sparc/dev/sxvar.h

69

reg = bus_space_read_4(sc->sc_tag, sc->sc_regh,

sys/arch/sparc/dev/sxvar.h

71

} while ((reg & SX_MT) == 0);

sys/arch/sparc/dev/ts102.c

1000

uint32_t reg;

sys/arch/sparc/dev/ts102.c

1014

reg=TSLOT_READ(td, TS102_REG_CARD_A_STS);

sys/arch/sparc/dev/ts102.c

1015

TSPRINTF("status: %x\n", reg);

sys/arch/sparc/dev/zs.c

731

zs_read_reg(struct zs_chanstate *cs, uint8_t reg)

sys/arch/sparc/dev/zs.c

735

*cs->cs_reg_csr = reg;

sys/arch/sparc/dev/zs.c

743

zs_write_reg(struct zs_chanstate *cs, uint8_t reg, uint8_t val)

sys/arch/sparc/dev/zs.c

746

*cs->cs_reg_csr = reg;

sys/arch/sparc/fpu/fpu_explode.c

237

fpu_explode(struct fpemu *fe, struct fpn *fp, int type, int reg)

sys/arch/sparc/fpu/fpu_explode.c

243

xspace = (uint64_t *)&fe->fe_fpstate->fs_regs[reg & ~1];

sys/arch/sparc/fpu/fpu_explode.c

246

space = &fe->fe_fpstate->fs_regs[reg];

sys/arch/sparc/fpu/fpu_explode.c

295

reg));

sys/arch/sparc/include/cgtworeg.h

139

u_short reg;

sys/arch/sparc/include/cgtworeg.h

147

} reg;

sys/arch/sparc/include/cgtworeg.h

156

} reg;

sys/arch/sparc/include/cgtworeg.h

161

u_short reg;

sys/arch/sparc/include/cgtworeg.h

172

struct dblbufreg reg;

sys/arch/sparc/include/cgtworeg.h

177

u_short reg;

sys/arch/sparc/include/cgtworeg.h

181

u_short reg; /* actually 8 bits. reg*16 == size */

sys/arch/sparc/include/cgtworeg.h

185

u_short reg; /* actually 8 bits only. r/o */

sys/arch/sparc/include/cgtworeg.h

234

struct cg2statusreg reg;

sys/arch/sparc/include/cgtworeg.h

239

u_short reg; /* 8 bit mask register - set means plane r/w */

sys/arch/sparc/include/cgtworeg.h

247

u_short reg;

sys/arch/sparc/include/cgtworeg.h

251

u_short reg;

sys/arch/sparc/include/cgtworeg.h

255

struct cg2_extstatus reg;

sys/arch/sparc/include/cgtworeg.h

260

u_short reg;

sys/arch/sparc/include/z8530var.h

74

uint8_t zs_read_reg(struct zs_chanstate *cs, uint8_t reg);

sys/arch/sparc/include/z8530var.h

78

void zs_write_reg(struct zs_chanstate *cs, uint8_t reg, uint8_t val);

sys/arch/sparc/sparc/memecc.c

100

reg = bus_space_read_4(sc->sc_bt, sc->sc_bh, ECC_EN_REG);

sys/arch/sparc/sparc/memecc.c

103

(reg & ECC_EN_VER) >> 24,

sys/arch/sparc/sparc/memecc.c

104

(reg & ECC_EN_IMPL) >> 28);

sys/arch/sparc/sparc/memecc.c

107

reg |= ECC_EN_EE | ECC_EN_EI;

sys/arch/sparc/sparc/memecc.c

108

bus_space_write_4(sc->sc_bt, sc->sc_bh, ECC_EN_REG, reg);

sys/arch/sparc/sparc/memecc.c

78

uint32_t reg;

sys/arch/sparc/sparc/msiiep.c

250

uint32_t reg;

sys/arch/sparc/sparc/msiiep.c

254

reg = *msiiep_mid;

sys/arch/sparc/sparc/msiiep.c

255

*msiiep_mid = (reg & MID_MASK) | MID_STANDBY;

sys/arch/sparc/sparc/msiiepreg.h

237

#define mspcic_read_1(reg) \

sys/arch/sparc/sparc/msiiepreg.h

238

(((volatile struct msiiep_pcic_reg *)MSIIEP_PCIC_VA)->reg)

sys/arch/sparc/sparc/msiiepreg.h

239

#define mspcic_read_2(reg) \

sys/arch/sparc/sparc/msiiepreg.h

240

(le16toh(((volatile struct msiiep_pcic_reg *)MSIIEP_PCIC_VA)->reg))

sys/arch/sparc/sparc/msiiepreg.h

241

#define mspcic_read_4(reg) \

sys/arch/sparc/sparc/msiiepreg.h

242

(le32toh(((volatile struct msiiep_pcic_reg *)MSIIEP_PCIC_VA)->reg))

sys/arch/sparc/sparc/msiiepreg.h

244

#define mspcic_read_stream_1(reg) \

sys/arch/sparc/sparc/msiiepreg.h

245

(((volatile struct msiiep_pcic_reg *)MSIIEP_PCIC_VA)->reg)

sys/arch/sparc/sparc/msiiepreg.h

246

#define mspcic_read_stream_2(reg) \

sys/arch/sparc/sparc/msiiepreg.h

247

(((volatile struct msiiep_pcic_reg *)MSIIEP_PCIC_VA)->reg)

sys/arch/sparc/sparc/msiiepreg.h

248

#define mspcic_read_stream_4(reg) \

sys/arch/sparc/sparc/msiiepreg.h

249

(((volatile struct msiiep_pcic_reg *)MSIIEP_PCIC_VA)->reg)

sys/arch/sparc/sparc/msiiepreg.h

251

#define mspcic_write_1(reg, val) \

sys/arch/sparc/sparc/msiiepreg.h

252

(((volatile struct msiiep_pcic_reg *)MSIIEP_PCIC_VA)->reg) = (val)

sys/arch/sparc/sparc/msiiepreg.h

253

#define mspcic_write_2(reg, val) \

sys/arch/sparc/sparc/msiiepreg.h

254

(((volatile struct msiiep_pcic_reg *)MSIIEP_PCIC_VA)->reg) = (htole16(val))

sys/arch/sparc/sparc/msiiepreg.h

255

#define mspcic_write_4(reg, val) \

sys/arch/sparc/sparc/msiiepreg.h

256

(((volatile struct msiiep_pcic_reg *)MSIIEP_PCIC_VA)->reg) = (htole32(val))

sys/arch/sparc/sparc/msiiepreg.h

258

#define mspcic_write_stream_1(reg, val) \

sys/arch/sparc/sparc/msiiepreg.h

259

(((volatile struct msiiep_pcic_reg *)MSIIEP_PCIC_VA)->reg) = (val)

sys/arch/sparc/sparc/msiiepreg.h

260

#define mspcic_write_stream_2(reg, val) \

sys/arch/sparc/sparc/msiiepreg.h

261

(((volatile struct msiiep_pcic_reg *)MSIIEP_PCIC_VA)->reg) = (val)

sys/arch/sparc/sparc/msiiepreg.h

262

#define mspcic_write_stream_4(reg, val) \

sys/arch/sparc/sparc/msiiepreg.h

263

(((volatile struct msiiep_pcic_reg *)MSIIEP_PCIC_VA)->reg) = (val)

sys/arch/sparc/sparc/pci_fixup.c

114

if (len < sizeof(reg))

sys/arch/sparc/sparc/pci_fixup.c

116

if (OF_getprop(node, "reg", (void *)&reg, sizeof(reg)) != len)

sys/arch/sparc/sparc/pci_fixup.c

118

bus = OFW_PCI_PHYS_HI_BUS(reg.phys_hi);

sys/arch/sparc/sparc/pci_fixup.c

119

dev = OFW_PCI_PHYS_HI_DEVICE(reg.phys_hi);

sys/arch/sparc/sparc/pci_fixup.c

120

fun = OFW_PCI_PHYS_HI_FUNCTION(reg.phys_hi);

sys/arch/sparc/sparc/pci_fixup.c

260

if (len < sizeof(reg))

sys/arch/sparc/sparc/pci_fixup.c

262

if (OF_getprop(node, "reg", (void *)&reg, sizeof(reg)) != len)

sys/arch/sparc/sparc/pci_fixup.c

264

bus = OFW_PCI_PHYS_HI_BUS(reg.phys_hi);

sys/arch/sparc/sparc/pci_fixup.c

265

dev = OFW_PCI_PHYS_HI_DEVICE(reg.phys_hi);

sys/arch/sparc/sparc/pci_fixup.c

266

fun = OFW_PCI_PHYS_HI_FUNCTION(reg.phys_hi);

sys/arch/sparc/sparc/pci_fixup.c

74

struct ofw_pci_register reg;

sys/arch/sparc/sparc/pci_machdep.c

249

struct ofw_pci_register reg;

sys/arch/sparc/sparc/pci_machdep.c

288

OF_getprop(node, "reg", (void *)&reg, sizeof(reg));

sys/arch/sparc/sparc/pci_machdep.c

302

OFW_PCI_PHYS_HI_BUS(reg.phys_hi),

sys/arch/sparc/sparc/pci_machdep.c

303

OFW_PCI_PHYS_HI_DEVICE(reg.phys_hi),

sys/arch/sparc/sparc/pci_machdep.c

304

OFW_PCI_PHYS_HI_FUNCTION(reg.phys_hi));

sys/arch/sparc/sparc/pci_machdep.c

321

if (b != OFW_PCI_PHYS_HI_BUS(reg.phys_hi))

sys/arch/sparc/sparc/pci_machdep.c

323

if (d != OFW_PCI_PHYS_HI_DEVICE(reg.phys_hi))

sys/arch/sparc/sparc/pci_machdep.c

325

if (f != OFW_PCI_PHYS_HI_FUNCTION(reg.phys_hi))

sys/arch/sparc/sparc/pci_machdep.c

355

pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg)

sys/arch/sparc/sparc/pci_machdep.c

365

reg));

sys/arch/sparc/sparc/pci_machdep.c

368

if (reg & 0x3)

sys/arch/sparc/sparc/pci_machdep.c

369

panic("pci_conf_read: reg %x unaligned", reg);

sys/arch/sparc/sparc/pci_machdep.c

377

if ((unsigned int)reg >= PCI_CONF_SIZE)

sys/arch/sparc/sparc/pci_machdep.c

380

mode1_addr = PCITAG_OFFSET(tag) | reg;

sys/arch/sparc/sparc/pci_machdep.c

382

| (reg & PCI_MODE1_DATA_REG_MASK);

sys/arch/sparc/sparc/pci_machdep.c

394

pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data)

sys/arch/sparc/sparc/pci_machdep.c

403

reg));

sys/arch/sparc/sparc/pci_machdep.c

406

if (reg & 0x3)

sys/arch/sparc/sparc/pci_machdep.c

407

panic("pci_conf_write: reg %x unaligned", reg);

sys/arch/sparc/sparc/pci_machdep.c

415

if ((unsigned int)reg >= PCI_CONF_SIZE)

sys/arch/sparc/sparc/pci_machdep.c

418

mode1_addr = PCITAG_OFFSET(tag) | reg;

sys/arch/sparc/sparc/pci_machdep.c

420

| (reg & PCI_MODE1_DATA_REG_MASK);

sys/arch/sparc/sparc/pci_machdep.c

478

struct ofw_pci_register reg;

sys/arch/sparc/sparc/pci_machdep.c

480

OF_getprop(node, "reg", (void *)&reg, sizeof(reg));

sys/arch/sparc/sparc/pci_machdep.c

481

if (OFW_PCI_PHYS_HI_BUS(reg.phys_hi) == w->mpiw_bus

sys/arch/sparc/sparc/pci_machdep.c

482

&& OFW_PCI_PHYS_HI_DEVICE(reg.phys_hi)

sys/arch/sparc/sparc/pci_machdep.c

484

&& OFW_PCI_PHYS_HI_FUNCTION(reg.phys_hi)

sys/arch/sparc/sparc/pmap.c

3528

int reg, seg;

sys/arch/sparc/sparc/pmap.c

3732

for (reg = 0; reg < NKREG; reg++) {

sys/arch/sparc/sparc/pmap.c

3740

rp = &pmap_kernel()->pm_regmap[reg + VA_VREG(KERNBASE)];

sys/arch/sparc/sparc/pmap.c

3743

&kernel_segtable_store[reg * SRMMU_L2SIZE];

sys/arch/sparc/sparc/pmap.c

3745

setpgt4m(&pmap_kernel()->pm_reg_ptps[0][reg + VA_VREG(KERNBASE)],

sys/arch/sparc/sparc/pmap.c

3760

[((reg * NSEGRG) + seg) * SRMMU_L3SIZE];

sys/arch/sparc/sparc/pmap.c

7973

test_region(int reg, int start, int stop)

sys/arch/sparc/sparc/pmap.c

7983

addr = (reg << RGSHIFT) | i;

sys/arch/sparc/sparc/pmap.c

7997

if (reg == VA_VREG(KERNBASE))

sys/arch/sparc/sparc/process_machdep.c

114

process_read_regs(struct lwp *l, struct reg *regs)

sys/arch/sparc/sparc/process_machdep.c

123

process_write_regs(struct lwp *l, const struct reg *regs)

sys/arch/sparc64/dev/bq4802_ebus.c

76

#define bq4802_read(sc, reg) \

sys/arch/sparc64/dev/bq4802_ebus.c

77

bus_space_read_1(sc->sc_bst, sc->sc_bsh, reg)

sys/arch/sparc64/dev/bq4802_ebus.c

78

#define bq4802_write(sc, reg, val) \

sys/arch/sparc64/dev/bq4802_ebus.c

79

bus_space_write_1(sc->sc_bst, sc->sc_bsh, reg, val)

sys/arch/sparc64/dev/cbus.c

87

int reg;

sys/arch/sparc64/dev/cbus.c

92

if (OF_getprop(va->va_node, "reg", &reg, sizeof(reg)) != sizeof(reg))

sys/arch/sparc64/dev/cbus.c

94

sc->sc_devhandle = reg;

sys/arch/sparc64/dev/ebus_mainbus.c

283

struct upa_reg reg;

sys/arch/sparc64/dev/ebus_mainbus.c

298

if (OF_getprop(node, "reg", &reg, sizeof(reg)) != sizeof(reg))

sys/arch/sparc64/dev/ebus_mainbus.c

300

devhandle = (reg.ur_paddr >> 32) & 0x0fffffff;

sys/arch/sparc64/dev/ffb.c

1080

uint32_t reg;

sys/arch/sparc64/dev/ffb.c

1082

reg = *data8;

sys/arch/sparc64/dev/ffb.c

1083

reg |= reg >> 1;

sys/arch/sparc64/dev/ffb.c

1084

FBC_WRITE(sc, FFB_FBC_FONT, reg << 24);

sys/arch/sparc64/dev/ffb.c

1091

uint32_t reg;

sys/arch/sparc64/dev/ffb.c

1093

reg = *data16;

sys/arch/sparc64/dev/ffb.c

1094

reg |= reg >> 1;

sys/arch/sparc64/dev/ffb.c

1095

FBC_WRITE(sc, FFB_FBC_FONT, reg << 16);

sys/arch/sparc64/dev/ffb.c

1105

uint32_t reg;

sys/arch/sparc64/dev/ffb.c

1107

reg = *data8;

sys/arch/sparc64/dev/ffb.c

1108

FBC_WRITE(sc, FFB_FBC_FONT, reg << 24);

sys/arch/sparc64/dev/ffb.c

1115

uint32_t reg;

sys/arch/sparc64/dev/ffb.c

1117

reg = *data16;

sys/arch/sparc64/dev/ffb.c

1118

FBC_WRITE(sc, FFB_FBC_FONT, reg << 16);

sys/arch/sparc64/dev/ffb.c

904

int i, reg;

sys/arch/sparc64/dev/ffb.c

913

static struct { unsigned long voff; int reg; long flags; } map[] = {

sys/arch/sparc64/dev/ffb.c

951

reg = map[i].reg;

sys/arch/sparc64/dev/ffb.c

953

if (reg < sc->sc_nreg) {

sys/arch/sparc64/dev/ffb.c

955

sc->sc_sizes[reg]);

sys/arch/sparc64/dev/ffb.c

960

sc->sc_addrs[reg], o, prot,

sys/arch/sparc64/dev/fire_i2c.c

526

firei2c_reg_read(struct firei2c_softc *sc, bus_size_t reg)

sys/arch/sparc64/dev/fire_i2c.c

529

bus_space_barrier(sc->sc_bustag, sc->sc_regh, reg, 8,

sys/arch/sparc64/dev/fire_i2c.c

531

val = bus_space_read_8(sc->sc_bustag, sc->sc_regh, reg);

sys/arch/sparc64/dev/fire_i2c.c

536

firei2c_reg_write(struct firei2c_softc *sc, bus_size_t reg, uint8_t val)

sys/arch/sparc64/dev/fire_i2c.c

538

bus_space_write_8(sc->sc_bustag, sc->sc_regh, reg, val);

sys/arch/sparc64/dev/fire_i2c.c

539

bus_space_barrier(sc->sc_bustag, sc->sc_regh, reg, 8,

sys/arch/sparc64/dev/iommureg.h

83

#define IOMMUREG_READ(is, reg) \

sys/arch/sparc64/dev/iommureg.h

86

IOMMUREG(reg))

sys/arch/sparc64/dev/iommureg.h

88

#define IOMMUREG_WRITE(is, reg, v) \

sys/arch/sparc64/dev/iommureg.h

91

IOMMUREG(reg), \

sys/arch/sparc64/dev/jbus-i2c.c

186

jbusi2c_write(struct jbusi2c_softc *sc, int reg, uint64_t bits)

sys/arch/sparc64/dev/jbus-i2c.c

188

bus_space_write_8(sc->sc_bustag, sc->sc_regh, reg, bits);

sys/arch/sparc64/dev/jbus-i2c.c

192

jbusi2c_read(struct jbusi2c_softc *sc, int reg)

sys/arch/sparc64/dev/jbus-i2c.c

194

return bus_space_read_8(sc->sc_bustag, sc->sc_regh, reg);

sys/arch/sparc64/dev/lom.c

266

uint8_t reg, fw_rev, config, config2, config3;

sys/arch/sparc64/dev/lom.c

293

if (lom_read(sc, LOM_IDX_PROBE55, &reg) || reg != 0x55 ||

sys/arch/sparc64/dev/lom.c

294

lom_read(sc, LOM_IDX_PROBEAA, &reg) || reg != 0xaa ||

sys/arch/sparc64/dev/lom.c

452

lom_read(struct lom_softc *sc, uint8_t reg, uint8_t *val)

sys/arch/sparc64/dev/lom.c

455

return lom1_read(sc, reg, val);

sys/arch/sparc64/dev/lom.c

457

return lom2_read(sc, reg, val);

sys/arch/sparc64/dev/lom.c

461

lom_write(struct lom_softc *sc, uint8_t reg, uint8_t val)

sys/arch/sparc64/dev/lom.c

464

return lom1_write(sc, reg, val);

sys/arch/sparc64/dev/lom.c

466

return lom2_write(sc, reg, val);

sys/arch/sparc64/dev/lom.c

494

lom1_read(struct lom_softc *sc, uint8_t reg, uint8_t *val)

sys/arch/sparc64/dev/lom.c

500

return lom1_read_polled(sc, reg, val);

sys/arch/sparc64/dev/lom.c

502

lc.lc_cmd = reg;

sys/arch/sparc64/dev/lom.c

516

lom1_write(struct lom_softc *sc, uint8_t reg, uint8_t val)

sys/arch/sparc64/dev/lom.c

522

return lom1_write_polled(sc, reg, val);

sys/arch/sparc64/dev/lom.c

524

lc.lc_cmd = reg | LOM_IDX_WRITE;

sys/arch/sparc64/dev/lom.c

536

lom1_read_polled(struct lom_softc *sc, uint8_t reg, uint8_t *val)

sys/arch/sparc64/dev/lom.c

551

bus_space_write_1(sc->sc_iot, sc->sc_ioh, LOM1_CMD, reg);

sys/arch/sparc64/dev/lom.c

568

lom1_write_polled(struct lom_softc *sc, uint8_t reg, uint8_t val)

sys/arch/sparc64/dev/lom.c

583

reg |= LOM_IDX_WRITE;

sys/arch/sparc64/dev/lom.c

584

bus_space_write_1(sc->sc_iot, sc->sc_ioh, LOM1_CMD, reg);

sys/arch/sparc64/dev/lom.c

690

lom2_read(struct lom_softc *sc, uint8_t reg, uint8_t *val)

sys/arch/sparc64/dev/lom.c

696

return lom2_read_polled(sc, reg, val);

sys/arch/sparc64/dev/lom.c

698

lc.lc_cmd = reg;

sys/arch/sparc64/dev/lom.c

712

lom2_read_polled(struct lom_softc *sc, uint8_t reg, uint8_t *val)

sys/arch/sparc64/dev/lom.c

727

bus_space_write_1(sc->sc_iot, sc->sc_ioh, LOM2_CMD, reg);

sys/arch/sparc64/dev/lom.c

744

lom2_write(struct lom_softc *sc, uint8_t reg, uint8_t val)

sys/arch/sparc64/dev/lom.c

750

return lom2_write_polled(sc, reg, val);

sys/arch/sparc64/dev/lom.c

752

lc.lc_cmd = reg | LOM_IDX_WRITE;

sys/arch/sparc64/dev/lom.c

764

lom2_write_polled(struct lom_softc *sc, uint8_t reg, uint8_t val)

sys/arch/sparc64/dev/lom.c

779

if (sc->sc_space == LOM_IDX_CMD_GENERIC && reg != LOM_IDX_CMD)

sys/arch/sparc64/dev/lom.c

780

reg |= LOM_IDX_WRITE;

sys/arch/sparc64/dev/lom.c

782

bus_space_write_1(sc->sc_iot, sc->sc_ioh, LOM2_CMD, reg);

sys/arch/sparc64/dev/lom.c

821

if (reg == LOM_IDX_CMD)

sys/arch/sparc64/dev/pci_machdep.c

137

struct ofw_pci_register reg;

sys/arch/sparc64/dev/pci_machdep.c

235

if (len < sizeof(reg))

sys/arch/sparc64/dev/pci_machdep.c

237

if (OF_getprop(node, "reg", (void *)&reg, sizeof(reg)) != len)

sys/arch/sparc64/dev/pci_machdep.c

240

if (b != OFW_PCI_PHYS_HI_BUS(reg.phys_hi))

sys/arch/sparc64/dev/pci_machdep.c

242

if (d != OFW_PCI_PHYS_HI_DEVICE(reg.phys_hi))

sys/arch/sparc64/dev/pci_machdep.c

244

if (f != OFW_PCI_PHYS_HI_FUNCTION(reg.phys_hi))

sys/arch/sparc64/dev/pci_machdep.c

273

struct ofw_pci_register reg;

sys/arch/sparc64/dev/pci_machdep.c

333

if (OF_getprop(node, "reg", &reg, sizeof(reg)) < sizeof(reg)) {

sys/arch/sparc64/dev/pci_machdep.c

338

b = OFW_PCI_PHYS_HI_BUS(reg.phys_hi);

sys/arch/sparc64/dev/pci_machdep.c

339

d = OFW_PCI_PHYS_HI_DEVICE(reg.phys_hi);

sys/arch/sparc64/dev/pci_machdep.c

340

f = OFW_PCI_PHYS_HI_FUNCTION(reg.phys_hi);

sys/arch/sparc64/dev/pci_machdep.c

79

pcireg_t reg;

sys/arch/sparc64/dev/pci_machdep.c

88

reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);

sys/arch/sparc64/dev/pci_machdep.c

89

reg |= PCI_COMMAND_MEM_ENABLE|PCI_COMMAND_MASTER_ENABLE|

sys/arch/sparc64/dev/pci_machdep.c

91

pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg);

sys/arch/sparc64/dev/psycho.c

1382

psycho_pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg)

sys/arch/sparc64/dev/psycho.c

1390

(long)tag, reg));

sys/arch/sparc64/dev/psycho.c

1391

if (PCITAG_NODE(tag) != -1 && (unsigned int)reg < PCI_CONF_SIZE) {

sys/arch/sparc64/dev/psycho.c

1396

PCITAG_OFFSET(tag) + reg),

sys/arch/sparc64/dev/psycho.c

1397

(int)PCITAG_OFFSET(tag) + reg));

sys/arch/sparc64/dev/psycho.c

1404

PCITAG_OFFSET(tag) + reg);

sys/arch/sparc64/dev/psycho.c

1421

psycho_pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data)

sys/arch/sparc64/dev/psycho.c

1427

(long)PCITAG_OFFSET(tag), reg, (int)data));

sys/arch/sparc64/dev/psycho.c

1430

(long long)(sc->sc_configaddr._ptr + PCITAG_OFFSET(tag) + reg),

sys/arch/sparc64/dev/psycho.c

1431

(int)PCITAG_OFFSET(tag) + reg));

sys/arch/sparc64/dev/psycho.c

1439

if ((unsigned int)reg >= PCI_CONF_SIZE)

sys/arch/sparc64/dev/psycho.c

1443

PCITAG_OFFSET(tag) + reg, data);

sys/arch/sparc64/dev/pyro.c

284

pyro_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg)

sys/arch/sparc64/dev/pyro.c

290

DPRINTF(PDB_CONF, ("%s: tag %lx reg %x ", __func__, (long)tag, reg));

sys/arch/sparc64/dev/pyro.c

291

if (PCITAG_NODE(tag) != -1 && (unsigned int)reg < PCI_CONF_SIZE) {

sys/arch/sparc64/dev/pyro.c

297

(PCITAG_OFFSET(tag) << 4) + reg);

sys/arch/sparc64/dev/pyro.c

309

pyro_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data)

sys/arch/sparc64/dev/pyro.c

314

(long)tag, reg, (int)data));

sys/arch/sparc64/dev/pyro.c

322

if ((unsigned int)reg >= PCI_CONF_SIZE)

sys/arch/sparc64/dev/pyro.c

326

(PCITAG_OFFSET(tag) << 4) + reg, data);

sys/arch/sparc64/dev/rtc.c

116

rtc_read_reg(struct mc146818_softc *sc, u_int reg)

sys/arch/sparc64/dev/rtc.c

119

bus_space_write_1(sc->sc_bst, sc->sc_bsh, RTC_ADDR, reg);

sys/arch/sparc64/dev/rtc.c

123

rtc_write_reg(struct mc146818_softc *sc, u_int reg, u_int val)

sys/arch/sparc64/dev/rtc.c

126

bus_space_write_1(sc->sc_bst, sc->sc_bsh, RTC_ADDR, reg);

sys/arch/sparc64/dev/schizo.c

1015

reg = schizo_pbm_read(pbm, r->offset + i);

sys/arch/sparc64/dev/schizo.c

1017

" (%s", r->offset + i, reg, r->name);

sys/arch/sparc64/dev/schizo.c

1029

reg = schizo_pbm_read(pbm, r->offset + i);

sys/arch/sparc64/dev/schizo.c

1031

" (%s", r->offset + i, reg, r->name);

sys/arch/sparc64/dev/schizo.c

1048

reg = schizo_pbm_readintr(pbm, r->offset + i);

sys/arch/sparc64/dev/schizo.c

1050

" (%s", r->offset + i, reg, r->name);

sys/arch/sparc64/dev/schizo.c

1065

reg = tomatillo_pbm_readichip(pbm,

sys/arch/sparc64/dev/schizo.c

1068

" (%s", r->offset + i, reg, r->name);

sys/arch/sparc64/dev/schizo.c

150

uint64_t reg, eccctrl, ino_bitmap;

sys/arch/sparc64/dev/schizo.c

302

reg = schizo_pbm_read(pbm, SCZ_PCI_CTRL);

sys/arch/sparc64/dev/schizo.c

304

reg |= SCZ_PCICTRL_EEN | SCZ_PCICTRL_MMU_INT;

sys/arch/sparc64/dev/schizo.c

306

reg &= ~SCZ_PCICTRL_SBH_INT;

sys/arch/sparc64/dev/schizo.c

307

reg |= TOM_PCICTRL_ARB;

sys/arch/sparc64/dev/schizo.c

308

reg |= TOM_PCICTRL_PRM | TOM_PCICTRL_PRO |

sys/arch/sparc64/dev/schizo.c

311

reg |= TOM_PCICTRL_DTO_INT;

sys/arch/sparc64/dev/schizo.c

313

reg |= SCZ_PCICTRL_PTO;

sys/arch/sparc64/dev/schizo.c

315

reg |= SCZ_PCICTRL_SBH_INT | SCZ_PCICTRL_ARB;

sys/arch/sparc64/dev/schizo.c

317

reg |= SCZ_PCICTRL_PARK;

sys/arch/sparc64/dev/schizo.c

318

schizo_pbm_write(pbm, SCZ_PCI_CTRL, reg);

sys/arch/sparc64/dev/schizo.c

320

reg = schizo_pbm_read(pbm, SCZ_PCI_DIAG);

sys/arch/sparc64/dev/schizo.c

321

reg &= ~(SCZ_PCIDIAG_D_RTRYARB | SCZ_PCIDIAG_D_RETRY |

sys/arch/sparc64/dev/schizo.c

323

schizo_pbm_write(pbm, SCZ_PCI_DIAG, reg);

sys/arch/sparc64/dev/schizo.c

527

schizo_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg)

sys/arch/sparc64/dev/schizo.c

533

DPRINTF(SDB_CONF, ("%s: tag %lx reg %x ", __func__, (long)tag, reg));

sys/arch/sparc64/dev/schizo.c

534

if (PCITAG_NODE(tag) != -1 && (unsigned int)reg < PCI_CONF_SIZE) {

sys/arch/sparc64/dev/schizo.c

540

PCITAG_OFFSET(tag) + reg);

sys/arch/sparc64/dev/schizo.c

552

schizo_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data)

sys/arch/sparc64/dev/schizo.c

557

(long)tag, reg, (int)data));

sys/arch/sparc64/dev/schizo.c

565

if ((unsigned int)reg >= PCI_CONF_SIZE)

sys/arch/sparc64/dev/schizo.c

569

PCITAG_OFFSET(tag) + reg, data);

sys/arch/sparc64/dev/schizo.c

917

u_int64_t reg;

sys/arch/sparc64/dev/schizo.c

951

reg = schizo_read_1(sc, r->offset + i);

sys/arch/sparc64/dev/schizo.c

956

reg = schizo_read(sc, r->offset + i);

sys/arch/sparc64/dev/schizo.c

960

r->offset + i, reg, r->name);

sys/arch/sparc64/dev/schizo.c

982

reg = schizo_pbm_read(pbm, r->offset + i);

sys/arch/sparc64/dev/schizo.c

984

" (%s", r->offset + i, reg, r->name);

sys/arch/sparc64/dev/schizo.c

996

reg = schizo_pbm_read(pbm, r->offset + i);

sys/arch/sparc64/dev/schizo.c

998

" (%s", r->offset + i, reg, r->name);

sys/arch/sparc64/dev/vbus.c

142

int *reg = NULL, nreg;

sys/arch/sparc64/dev/vbus.c

169

if (prom_getprop(node, "reg", sizeof(*reg), &nreg, (void **)&reg))

sys/arch/sparc64/dev/vbus.c

175

if (vbus_cmp_cells(imap, reg, imap_mask, address_cells) &&

sys/arch/sparc64/dev/vbus.c

181

free(reg, M_DEVBUF);

sys/arch/sparc64/dev/vbus.c

182

reg = NULL;

sys/arch/sparc64/dev/vbus.c

184

if (prom_getprop(node, "reg", sizeof(*reg), &nreg, (void **)&reg))

sys/arch/sparc64/dev/vbus.c

187

devhandle = reg[0] & 0x0fffffff;

sys/arch/sparc64/dev/vpci.c

333

vpci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg)

sys/arch/sparc64/dev/vpci.c

339

DPRINTF(VDB_CONF_READ, ("%s: tag %lx reg %x ", __func__, (long)tag, reg));

sys/arch/sparc64/dev/vpci.c

340

hv_rc = hv_pci_config_get(pbm->vp_devhandle, PCITAG_OFFSET(tag), reg, 4,

sys/arch/sparc64/dev/vpci.c

352

vpci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data)

sys/arch/sparc64/dev/vpci.c

359

(long)tag, reg, (int)data));

sys/arch/sparc64/dev/vpci.c

360

hv_rc = hv_pci_config_put(pbm->vp_devhandle, PCITAG_OFFSET(tag), reg, 4,

sys/arch/sparc64/dev/zs.c

646

zs_read_reg(struct zs_chanstate *cs, u_char reg)

sys/arch/sparc64/dev/zs.c

650

*cs->cs_reg_csr = reg;

sys/arch/sparc64/dev/zs.c

658

zs_write_reg(struct zs_chanstate *cs, u_char reg, u_char val)

sys/arch/sparc64/dev/zs.c

660

*cs->cs_reg_csr = reg;

sys/arch/sparc64/include/locore.h

111

#define LOAD_ASCIZ(reg, s) \

sys/arch/sparc64/include/locore.h

112

set 99f, reg ; \

sys/arch/sparc64/include/pci_machdep.h

103

#define pci_conf_read(pc, tag, reg) \

sys/arch/sparc64/include/pci_machdep.h

104

((pc)->spc_conf_read(pc, tag, reg))

sys/arch/sparc64/include/pci_machdep.h

105

#define pci_conf_write(pc, tag, reg, val) \

sys/arch/sparc64/include/pci_machdep.h

106

((pc)->spc_conf_write(pc, tag, reg, val))

sys/arch/sparc64/include/psl.h

314

#define SPARC64_RDCONST_DEF(rd, name, reg, type) \

sys/arch/sparc64/include/psl.h

318

__asm(#rd " %" #reg ",%0" : "=r" (_val) : : constasm_clobbers); \

sys/arch/sparc64/include/psl.h

321

#define SPARC64_RD_DEF(rd, name, reg, type) \

sys/arch/sparc64/include/psl.h

325

__asm volatile(#rd " %" #reg ",%0" : "=r" (_val)); \

sys/arch/sparc64/include/psl.h

328

#define SPARC64_WR_DEF(wr, name, reg, type) \

sys/arch/sparc64/include/psl.h

331

__asm volatile(#wr " %0,0,%" #reg : : "r" (_val) : "memory"); \

sys/arch/sparc64/include/psl.h

335

#define SPARC64_RDCONST64_DEF(rd, name, reg) \

sys/arch/sparc64/include/psl.h

336

SPARC64_RDCONST_DEF(rd, name, reg, uint64_t)

sys/arch/sparc64/include/psl.h

337

#define SPARC64_RD64_DEF(rd, name, reg) SPARC64_RD_DEF(rd, name, reg, uint64_t)

sys/arch/sparc64/include/psl.h

338

#define SPARC64_WR64_DEF(wr, name, reg) SPARC64_WR_DEF(wr, name, reg, uint64_t)

sys/arch/sparc64/include/psl.h

340

#define SPARC64_RDCONST64_DEF(rd, name, reg) \

sys/arch/sparc64/include/psl.h

344

__asm(#rd " %" #reg ",%0; srl %0,0,%1; srlx %0,32,%0" \

sys/arch/sparc64/include/psl.h

348

#define SPARC64_RD64_DEF(rd, name, reg) \

sys/arch/sparc64/include/psl.h

352

__asm volatile(#rd " %" #reg ",%0; srl %0,0,%1; srlx %0,32,%0" \

sys/arch/sparc64/include/psl.h

356

#define SPARC64_WR64_DEF(wr, name, reg) \

sys/arch/sparc64/include/psl.h

360

__asm volatile("sllx %1,32,%0; or %0,%2,%0; " #wr " %0,0,%" #reg\

sys/arch/sparc64/include/psl.h

366

#define SPARC64_RDPR_DEF(name, reg, type) SPARC64_RD_DEF(rdpr, name, reg, type)

sys/arch/sparc64/include/psl.h

367

#define SPARC64_WRPR_DEF(name, reg, type) SPARC64_WR_DEF(wrpr, name, reg, type)

sys/arch/sparc64/include/psl.h

368

#define SPARC64_RDPR64_DEF(name, reg) SPARC64_RD64_DEF(rdpr, name, reg)

sys/arch/sparc64/include/psl.h

369

#define SPARC64_WRPR64_DEF(name, reg) SPARC64_WR64_DEF(wrpr, name, reg)

sys/arch/sparc64/include/psl.h

370

#define SPARC64_RDASR64_DEF(name, reg) SPARC64_RD64_DEF(rd, name, reg)

sys/arch/sparc64/include/psl.h

371

#define SPARC64_WRASR64_DEF(name, reg) SPARC64_WR64_DEF(wr, name, reg)

sys/arch/sparc64/include/z8530var.h

88

uint8_t zs_read_reg(struct zs_chanstate *cs, uint8_t reg);

sys/arch/sparc64/include/z8530var.h

92

void zs_write_reg(struct zs_chanstate *cs, uint8_t reg, uint8_t val);

sys/arch/sparc64/sparc64/clock.c

344

volatile struct timer_4u *reg = creg;

sys/arch/sparc64/sparc64/clock.c

347

(void)reg->t_limit;

sys/arch/sparc64/sparc64/clock.c

348

reg->t_limit = 0;

sys/arch/sparc64/sparc64/cpu.c

144

int reg[4];

sys/arch/sparc64/sparc64/cpu.c

145

int* regp=reg;

sys/arch/sparc64/sparc64/cpu.c

152

id = reg[0] & 0x0fffffff;

sys/arch/sparc64/sparc64/ofw_machdep.c

1007

if ((len = OF_getprop(node, "reg", &reg, sizeof(reg))) <= 0) {

sys/arch/sparc64/sparc64/ofw_machdep.c

806

int reg[10];

sys/arch/sparc64/sparc64/ofw_machdep.c

843

if ((len = OF_getprop(node, "reg", &reg, sizeof(reg))) <= 0) {

sys/arch/sparc64/sparc64/ofw_machdep.c

874

OFW_PCI_PHYS_HI_DEVICE(reg[0]) - 1) & 3) + 1;

sys/arch/sparc64/sparc64/ofw_machdep.c

876

ointerrupt, *interrupt, reg[0]));

sys/arch/sparc64/sparc64/ofw_machdep.c

880

reg[0] = 0;

sys/arch/sparc64/sparc64/ofw_machdep.c

881

OF_getprop(node, "reg", &reg, sizeof(reg));

sys/arch/sparc64/sparc64/ofw_machdep.c

933

DPRINTF(("%x.", reg[i]));

sys/arch/sparc64/sparc64/ofw_machdep.c

965

if (compare_cells(imap, reg,

sys/arch/sparc64/sparc64/process_machdep.c

113

process_read_regs(struct lwp *l, struct reg *regs)

sys/arch/sparc64/sparc64/process_machdep.c

147

process_write_regs(struct lwp *l, const struct reg *regs)

sys/arch/sparc64/sparc64/rbus_machdep.c

124

pcireg_t reg;

sys/arch/sparc64/sparc64/rbus_machdep.c

160

reg = pci_conf_read(pc, pa->pa_tag, PCI_BRIDGE_BUS_REG);

sys/arch/sparc64/sparc64/rbus_machdep.c

161

reg &= 0xff000000;

sys/arch/sparc64/sparc64/rbus_machdep.c

162

reg |= pa->pa_bus | (bus << 8) | (bus << 16);

sys/arch/sparc64/sparc64/rbus_machdep.c

163

pci_conf_write(pc, pa->pa_tag, PCI_BRIDGE_BUS_REG, reg);

sys/arch/sun2/dev/if_ie_mbmem.c

247

#define read_iev(sc, reg) \

sys/arch/sun2/dev/if_ie_mbmem.c

248

bus_space_read_2(sc->ievt, sc->ievh, offsetof(struct iembmem, reg))

sys/arch/sun2/dev/if_ie_mbmem.c

249

#define write_iev(sc, reg, val) \

sys/arch/sun2/dev/if_ie_mbmem.c

250

bus_space_write_2(sc->ievt, sc->ievh, offsetof(struct iembmem, reg), val)

sys/arch/sun2/dev/zs.c

485

zs_read_reg(struct zs_chanstate *cs, uint8_t reg)

sys/arch/sun2/dev/zs.c

489

*cs->cs_reg_csr = reg;

sys/arch/sun2/dev/zs.c

497

zs_write_reg(struct zs_chanstate *cs, uint8_t reg, uint8_t val)

sys/arch/sun2/dev/zs.c

499

*cs->cs_reg_csr = reg;

sys/arch/sun2/sun2/machdep.h

98

struct reg;

sys/arch/sun3/dev/cg2.c

185

sc->sc_ctlreg->intrptvec.reg = ca->ca_intvec;

sys/arch/sun3/dev/cg2.c

275

*on = sc->sc_ctlreg->status.reg.video_enab;

sys/arch/sun3/dev/cg2.c

286

sc->sc_ctlreg->status.reg.video_enab = (*on) & 1;

sys/arch/sun3/dev/cg2.c

381

sc->sc_ctlreg->status.reg.inten = 0;

sys/arch/sun3/dev/esp.c

254

esp_read_reg(struct ncr53c9x_softc *sc, int reg)

sys/arch/sun3/dev/esp.c

258

return bus_space_read_1(esc->sc_bst, esc->sc_bsh, reg * 4);

sys/arch/sun3/dev/esp.c

262

esp_write_reg(struct ncr53c9x_softc *sc, int reg, uint8_t val)

sys/arch/sun3/dev/esp.c

266

bus_space_write_1(esc->sc_bst, esc->sc_bsh, reg * 4, val);

sys/arch/sun3/dev/zs.c

487

zs_read_reg(struct zs_chanstate *cs, uint8_t reg)

sys/arch/sun3/dev/zs.c

491

*cs->cs_reg_csr = reg;

sys/arch/sun3/dev/zs.c

499

zs_write_reg(struct zs_chanstate *cs, uint8_t reg, uint8_t val)

sys/arch/sun3/dev/zs.c

501

*cs->cs_reg_csr = reg;

sys/arch/sun3/include/cg2reg.h

125

u_short reg;

sys/arch/sun3/include/cg2reg.h

133

} reg;

sys/arch/sun3/include/cg2reg.h

142

} reg;

sys/arch/sun3/include/cg2reg.h

147

u_short reg;

sys/arch/sun3/include/cg2reg.h

158

struct dblbufreg reg;

sys/arch/sun3/include/cg2reg.h

163

u_short reg;

sys/arch/sun3/include/cg2reg.h

167

u_short reg; /* actually 8 bits. reg*16 == size */

sys/arch/sun3/include/cg2reg.h

171

u_short reg; /* actually 8 bits only. r/o */

sys/arch/sun3/include/cg2reg.h

225

struct cg2statusreg reg;

sys/arch/sun3/include/cg2reg.h

230

u_short reg; /* 8 bit mask register - set means plane r/w */

sys/arch/sun3/include/cg2reg.h

238

u_short reg;

sys/arch/sun3/include/cg2reg.h

242

u_short reg;

sys/arch/sun3/include/cg2reg.h

246

struct cg2_extstatus reg;

sys/arch/sun3/include/cg2reg.h

251

u_short reg;

sys/arch/sun3/sun3/machdep.h

97

struct reg;

sys/arch/usermode/target/arm/cpu_arm.c

102

unsigned int *reg = (unsigned int *)&ucp->uc_mcontext;

sys/arch/usermode/target/arm/cpu_arm.c

103

return reg[15];

sys/arch/usermode/target/arm/cpu_arm.c

109

unsigned int *reg = (unsigned int *)&ucp->uc_mcontext;

sys/arch/usermode/target/arm/cpu_arm.c

110

return reg[13];

sys/arch/usermode/target/i386/cpu_i386.c

105

register_t *reg;

sys/arch/usermode/target/i386/cpu_i386.c

111

reg = (register_t *) &ucp->uc_mcontext.__gregs;

sys/arch/usermode/target/i386/cpu_i386.c

126

fp = (void *) reg[17]; /* ESP */

sys/arch/usermode/target/i386/cpu_i386.c

166

reg[17] = (register_t) fp; /* ESP */

sys/arch/usermode/target/i386/cpu_i386.c

167

reg[14] = (register_t) catcher; /* EIP */

sys/arch/usermode/target/i386/cpu_i386.c

179

uint *reg, i;

sys/arch/usermode/target/i386/cpu_i386.c

193

reg = (int *) &ucp->uc_mcontext.__gregs;

sys/arch/usermode/target/i386/cpu_i386.c

195

reg[i] = 0;

sys/arch/usermode/target/i386/cpu_i386.c

204

reg[ 8] = l->l_proc->p_psstrp; /* _REG_EBX */

sys/arch/usermode/target/i386/cpu_i386.c

205

reg[17] = (stack); /* _REG_UESP */

sys/arch/usermode/target/i386/cpu_i386.c

223

uint *reg = (int *) &ucp->uc_mcontext.__gregs;

sys/arch/usermode/target/i386/cpu_i386.c

224

*code = reg[11]; /* EAX */

sys/arch/usermode/target/i386/cpu_i386.c

231

uint *reg = (int *) &ucp->uc_mcontext.__gregs;

sys/arch/usermode/target/i386/cpu_i386.c

232

register_t *sp = (register_t *) reg[17];/* ESP */

sys/arch/usermode/target/i386/cpu_i386.c

245

register_t *reg = (register_t *) &ucp->uc_mcontext.__gregs;

sys/arch/usermode/target/i386/cpu_i386.c

247

reg[16] &= ~PSL_C; /* EFL */

sys/arch/usermode/target/i386/cpu_i386.c

250

reg[16] |= PSL_C; /* EFL */

sys/arch/usermode/target/i386/cpu_i386.c

254

reg[11] = rval[0]; /* EAX */

sys/arch/usermode/target/i386/cpu_i386.c

256

reg[ 9] = rval[1]; /* EDX */

sys/arch/usermode/target/i386/cpu_i386.c

265

register_t *reg = (register_t *) &ucp->uc_mcontext.__gregs;

sys/arch/usermode/target/i386/cpu_i386.c

267

return reg[14]; /* EIP */

sys/arch/usermode/target/i386/cpu_i386.c

274

register_t *reg = (register_t *) &ucp->uc_mcontext.__gregs;

sys/arch/usermode/target/i386/cpu_i386.c

276

return reg[17]; /* ESP */

sys/arch/usermode/target/i386/cpu_i386.c

302

register_t *reg = (register_t *) &ucp->uc_mcontext.__gregs;

sys/arch/usermode/target/i386/cpu_i386.c

304

uint16_t *p16 = (uint16_t*) (reg[14]); /* EIP */

sys/arch/usermode/target/i386/cpu_i386.c

323

uint *reg = (int *) &ucp->uc_mcontext.__gregs;

sys/arch/usermode/target/i386/cpu_i386.c

332

reg[14] += 2; /* EIP */

sys/arch/usermode/target/i386/cpu_i386.c

344

uint *reg = (int *) &ucp->uc_mcontext.__gregs;

sys/arch/usermode/target/i386/cpu_i386.c

352

reg[14] -= 2; /* EIP */

sys/arch/usermode/target/i386/cpu_i386.c

57

static void dump_regs(register_t *reg);

sys/arch/usermode/target/i386/cpu_i386.c

60

dump_regs(register_t *reg)

sys/arch/usermode/target/i386/cpu_i386.c

70

printf("reg[%02d] (%6s) = %"PRIx32"\n", i, name[i], (uint32_t) reg[i]);

sys/arch/usermode/target/x86_64/cpu_x86_64.c

101

register_t *reg;

sys/arch/usermode/target/x86_64/cpu_x86_64.c

108

reg = (register_t *) &ucp->uc_mcontext.__gregs;

sys/arch/usermode/target/x86_64/cpu_x86_64.c

123

sp = ((char *) reg[24] - 128);/* why -128?*//* RSP */

sys/arch/usermode/target/x86_64/cpu_x86_64.c

163

reg[24] = (register_t) fp; /* RSP */

sys/arch/usermode/target/x86_64/cpu_x86_64.c

164

reg[21] = (register_t) catcher; /* RIP */

sys/arch/usermode/target/x86_64/cpu_x86_64.c

166

reg[ 0] = sig; /* RDI */

sys/arch/usermode/target/x86_64/cpu_x86_64.c

167

reg[ 1] = (uint64_t) &fp->sf_si; /* RSI */

sys/arch/usermode/target/x86_64/cpu_x86_64.c

168

reg[ 2] = (uint64_t) &fp->sf_uc; /* RDX */

sys/arch/usermode/target/x86_64/cpu_x86_64.c

169

reg[11] = reg[ 2]; /* R15 = RDX */

sys/arch/usermode/target/x86_64/cpu_x86_64.c

181

register_t *reg;

sys/arch/usermode/target/x86_64/cpu_x86_64.c

186

reg = (register_t *) &ucp->uc_mcontext.__gregs;

sys/arch/usermode/target/x86_64/cpu_x86_64.c

188

reg[i] = 0;

sys/arch/usermode/target/x86_64/cpu_x86_64.c

190

reg[13] = l->l_proc->p_psstrp; /* RBX */

sys/arch/usermode/target/x86_64/cpu_x86_64.c

191

reg[21] = pack->ep_entry; /* RIP */

sys/arch/usermode/target/x86_64/cpu_x86_64.c

192

reg[24] = (register_t) stack; /* RSP */

sys/arch/usermode/target/x86_64/cpu_x86_64.c

204

register_t *reg = (register_t *) &ucp->uc_mcontext.__gregs;

sys/arch/usermode/target/x86_64/cpu_x86_64.c

205

*code = reg[14]; /* RAX */

sys/arch/usermode/target/x86_64/cpu_x86_64.c

212

register_t *reg = (register_t *) &ucp->uc_mcontext.__gregs;

sys/arch/usermode/target/x86_64/cpu_x86_64.c

213

register_t *sp = (register_t *) reg[24];/* RSP */

sys/arch/usermode/target/x86_64/cpu_x86_64.c

222

args[0] = reg[ 0]; /* RDI */

sys/arch/usermode/target/x86_64/cpu_x86_64.c

223

args[1] = reg[ 1]; /* RSI */

sys/arch/usermode/target/x86_64/cpu_x86_64.c

224

args[2] = reg[ 2]; /* RDX */

sys/arch/usermode/target/x86_64/cpu_x86_64.c

225

args[3] = reg[ 6]; /* R10 (RCX got clobbered) */

sys/arch/usermode/target/x86_64/cpu_x86_64.c

226

args[4] = reg[ 4]; /* R8 */

sys/arch/usermode/target/x86_64/cpu_x86_64.c

227

args[5] = reg[ 5]; /* R9 */

sys/arch/usermode/target/x86_64/cpu_x86_64.c

242

register_t *reg = (register_t *) &ucp->uc_mcontext.__gregs;

sys/arch/usermode/target/x86_64/cpu_x86_64.c

244

reg[23] &= ~PSL_C; /* RFLAGS */

sys/arch/usermode/target/x86_64/cpu_x86_64.c

247

reg[23] |= PSL_C; /* RFLAGS */

sys/arch/usermode/target/x86_64/cpu_x86_64.c

251

reg[14] = rval[0]; /* RAX */

sys/arch/usermode/target/x86_64/cpu_x86_64.c

253

reg[ 2] = rval[1]; /* RDX */

sys/arch/usermode/target/x86_64/cpu_x86_64.c

261

register_t *reg = (register_t *) &ucp->uc_mcontext.__gregs;

sys/arch/usermode/target/x86_64/cpu_x86_64.c

263

return reg[21]; /* RIP */

sys/arch/usermode/target/x86_64/cpu_x86_64.c

269

register_t *reg = (register_t *) &ucp->uc_mcontext.__gregs;

sys/arch/usermode/target/x86_64/cpu_x86_64.c

271

return reg[24]; /* RSP */

sys/arch/usermode/target/x86_64/cpu_x86_64.c

297

register_t *reg = (register_t *) &ucp->uc_mcontext.__gregs;

sys/arch/usermode/target/x86_64/cpu_x86_64.c

299

uint16_t *p16 = (uint16_t*) (reg[21]); /* RIP */

sys/arch/usermode/target/x86_64/cpu_x86_64.c

317

register_t *reg = (register_t *) &ucp->uc_mcontext.__gregs;

sys/arch/usermode/target/x86_64/cpu_x86_64.c

326

reg[21] += 2; /* RIP */

sys/arch/usermode/target/x86_64/cpu_x86_64.c

337

register_t *reg = (register_t *) &ucp->uc_mcontext.__gregs;

sys/arch/usermode/target/x86_64/cpu_x86_64.c

345

reg[21] -= 2; /* RIP */

sys/arch/usermode/target/x86_64/cpu_x86_64.c

55

static void dump_regs(register_t *reg);

sys/arch/usermode/target/x86_64/cpu_x86_64.c

58

dump_regs(register_t *reg)

sys/arch/usermode/target/x86_64/cpu_x86_64.c

70

i, name[i], (uint32_t) reg[i]);

sys/arch/usermode/usermode/process_machdep.c

108

register_t *reg;

sys/arch/usermode/usermode/process_machdep.c

111

reg = (register_t *) &ucp->uc_mcontext.__fpregs;

sys/arch/usermode/usermode/process_machdep.c

114

memcpy(regs, reg, *sz);

sys/arch/usermode/usermode/process_machdep.c

120

process_write_regs(struct lwp *l, const struct reg *regs)

sys/arch/usermode/usermode/process_machdep.c

89

process_read_regs(struct lwp *l, struct reg *regs)

sys/arch/usermode/usermode/process_machdep.c

93

register_t *reg;

sys/arch/usermode/usermode/process_machdep.c

96

reg = (register_t *) &ucp->uc_mcontext.__gregs;

sys/arch/usermode/usermode/process_machdep.c

98

memcpy(regs, reg, sizeof(__gregset_t));

sys/arch/vax/boot/boot/hp.c

60

#define MBA_WCSR(reg, val) \

sys/arch/vax/boot/boot/hp.c

61

((void)(*(volatile u_int32_t *)((adpadr) + (reg)) = (val)));

sys/arch/vax/boot/boot/hp.c

62

#define MBA_RCSR(reg) \

sys/arch/vax/boot/boot/hp.c

63

(*(volatile u_int32_t *)((adpadr) + (reg)))

sys/arch/vax/boot/boot/hp.c

64

#define HP_WCSR(reg, val) \

sys/arch/vax/boot/boot/hp.c

65

((void)(*(volatile u_int32_t *)((unitadr) + (reg)) = (val)));

sys/arch/vax/boot/boot/hp.c

66

#define HP_RCSR(reg) \

sys/arch/vax/boot/boot/hp.c

67

(*(volatile u_int32_t *)((unitadr) + (reg)))

sys/arch/vax/boot/boot/if_ni.c

111

failtest(int reg, int mask, int test, char *str)

sys/arch/vax/boot/boot/if_ni.c

117

} while (((NI_RREG(reg) & mask) != test) && --i);

sys/arch/vax/boot/xxboot/bootxx.c

315

#define MBA_WCSR(reg, val) \

sys/arch/vax/boot/xxboot/bootxx.c

316

((void)(*(volatile u_int32_t *)((adpadr) + (reg)) = (val)));

sys/arch/vax/boot/xxboot/bootxx.c

317

#define MBA_RCSR(reg) \

sys/arch/vax/boot/xxboot/bootxx.c

318

(*(volatile u_int32_t *)((adpadr) + (reg)))

sys/arch/vax/boot/xxboot/bootxx.c

319

#define HP_WCSR(reg, val) \

sys/arch/vax/boot/xxboot/bootxx.c

320

((void)(*(volatile u_int32_t *)((unitadr) + (reg)) = (val)));

sys/arch/vax/boot/xxboot/bootxx.c

321

#define HP_RCSR(reg) \

sys/arch/vax/boot/xxboot/bootxx.c

322

(*(volatile u_int32_t *)((unitadr) + (reg)))

sys/arch/vax/include/macros.h

40

vax_ffs(int reg)

sys/arch/vax/include/macros.h

50

: "r" (reg) );

sys/arch/vax/include/mtpr.h

165

mtpr(register_t val, int reg)

sys/arch/vax/include/mtpr.h

170

: "g" (val), "g" (reg)

sys/arch/vax/include/mtpr.h

175

mfpr(int reg)

sys/arch/vax/include/mtpr.h

181

: "g" (reg));

sys/arch/vax/mba/hp.c

117

#define HP_WCSR(reg, val) \

sys/arch/vax/mba/hp.c

118

bus_space_write_4(sc->sc_iot, sc->sc_ioh, (reg), (val))

sys/arch/vax/mba/hp.c

119

#define HP_RCSR(reg) \

sys/arch/vax/mba/hp.c

120

bus_space_read_4(sc->sc_iot, sc->sc_ioh, (reg))

sys/arch/vax/mba/mba.c

84

#define MBA_WCSR(reg, val) \

sys/arch/vax/mba/mba.c

85

bus_space_write_4(sc->sc_iot, sc->sc_ioh, (reg), (val))

sys/arch/vax/mba/mba.c

86

#define MBA_RCSR(reg) \

sys/arch/vax/mba/mba.c

87

bus_space_read_4(sc->sc_iot, sc->sc_ioh, (reg))

sys/arch/vax/mba/mbareg.h

62

#define MUREG(dev,reg) (1024+(dev)*128+(reg))

sys/arch/vax/vax/db_disasm.c

309

int reg = c & 0x0F;

sys/arch/vax/vax/db_disasm.c

325

snprintf(buf, sizeof(buf), "[%s]", my_db_regs[reg].name);

sys/arch/vax/vax/db_disasm.c

331

add_str(ib, my_db_regs[reg].name);

sys/arch/vax/vax/db_disasm.c

336

add_str(ib, my_db_regs[reg].name);

sys/arch/vax/vax/db_disasm.c

343

add_str(ib, my_db_regs[reg].name);

sys/arch/vax/vax/db_disasm.c

345

if (reg == 0x0F) { /* pc is not allowed in this mode */

sys/arch/vax/vax/db_disasm.c

352

if (reg == 0x0F) { /* pc: immediate deferred */

sys/arch/vax/vax/db_disasm.c

362

if (reg == 0x0F) { /* pc: immediate ==> special syntax */

sys/arch/vax/vax/db_disasm.c

383

add_str(ib, my_db_regs[reg].name);

sys/arch/vax/vax/db_disasm.c

392

if (reg == 0x0F) {

sys/arch/vax/vax/db_disasm.c

399

add_str(ib, my_db_regs[reg].name);

sys/arch/vax/vax/db_disasm.c

407

if (reg == 0x0F) {

sys/arch/vax/vax/db_disasm.c

414

add_str(ib, my_db_regs[reg].name);

sys/arch/vax/vax/db_disasm.c

422

if (reg == 0x0F) {

sys/arch/vax/vax/db_disasm.c

429

add_str(ib, my_db_regs[reg].name);

sys/arch/vax/vax/disksubr.c

253

disk_reallymapin(struct buf *bp, struct pte *map, int reg, int flag)

sys/arch/vax/vax/disksubr.c

284

io = &map[reg];

sys/arch/vax/vax/ka6400.c

172

#define MEMRD(reg) bus_space_read_4(sc->sc_iot, sc->sc_ioh, (reg))

sys/arch/vax/vax/ka6400.c

173

#define MEMWR(reg, val) bus_space_write_4(sc->sc_iot, sc->sc_ioh, (reg), (val))

sys/arch/vax/vax/ka820.c

240

#define MEMRD(reg) bus_space_read_4(sc->sc_iot, sc->sc_ioh, (reg))

sys/arch/vax/vax/ka820.c

241

#define MEMWR(reg, val) bus_space_write_4(sc->sc_iot, sc->sc_ioh, (reg), (val))

sys/arch/vax/vax/machdep.c

467

process_read_regs(struct lwp *l, struct reg *regs)

sys/arch/vax/vax/machdep.c

481

process_write_regs(struct lwp *l, const struct reg *regs)

sys/arch/vax/vsa/asc_vsbus.c

305

asc_vsbus_read_reg(struct ncr53c9x_softc *sc, int reg)

sys/arch/vax/vsa/asc_vsbus.c

310

reg * sizeof(uint32_t));

sys/arch/vax/vsa/asc_vsbus.c

314

asc_vsbus_write_reg(struct ncr53c9x_softc *sc, int reg, uint8_t val)

sys/arch/vax/vsa/asc_vsbus.c

319

reg * sizeof(uint32_t), val);

sys/arch/vax/vsa/gpx.c

677

gpx_viper_write(struct gpx_screen *ss, u_int reg, uint16_t val)

sys/arch/vax/vsa/gpx.c

682

ss->ss_adder->command = ID_LOAD | reg;

sys/arch/vax/vsa/gpx.c

687

printf("gpx_viper_write failure, reg %x val %x\n", reg, val);

sys/arch/vax/vsa/lcg.c

88

#define LCG_REG(reg) regaddr[(reg / 4)]

sys/arch/vax/vsa/spx.c

109

#define SPX_REG(reg) regaddr[(reg - 0x2000) / 4]

sys/arch/vax/vsa/spx.c

110

#define SPXg_REG(reg) regaddr[(reg - 0x2000) / 2]

sys/arch/vax/vsa/spx.c

112

#define SPX_REG1(reg) regaddr1[(reg) / 4]

sys/arch/vax/vsa/spx.c

113

#define SPXg_REG1(reg) regaddr1[(reg) / 4]

sys/arch/vax/vsa/vsaudio.c

227

vsaudio_codec_dread(struct am7930_softc *amsc, int reg)

sys/arch/vax/vsa/vsaudio.c

231

return bus_space_read_1(sc->sc_bt, sc->sc_bh, reg << 2);

sys/arch/vax/vsa/vsaudio.c

236

vsaudio_codec_dwrite(struct am7930_softc *amsc, int reg, uint8_t val)

sys/arch/vax/vsa/vsaudio.c

240

bus_space_write_1(sc->sc_bt, sc->sc_bh, reg << 2, val);

sys/arch/x68k/dev/mfp.h

194

#define mfp_bit_set(reg,bits) (mfp_base[(reg)] |= (bits))

sys/arch/x68k/dev/mfp.h

195

#define mfp_bit_clear(reg,bits) (mfp_base[(reg)] &= (~(bits)))

sys/arch/x68k/dev/opm.c

129

writeopm(int reg, int dat)

sys/arch/x68k/dev/opm.c

132

bus_space_write_1(opm0->sc_bst, opm0->sc_bht, OPM_REG, reg);

sys/arch/x68k/dev/opm.c

135

opm0->sc_regs[reg] = dat;

sys/arch/x68k/dev/opm.c

139

readopm(int reg)

sys/arch/x68k/dev/opm.c

141

return opm0->sc_regs[reg];

sys/arch/x68k/dev/opm.c

191

opm_set_voice_sub(int reg, struct opm_operator *op)

sys/arch/x68k/dev/opm.c

194

writeopm(reg, (op->dt1 & 0x7) << 3 | (op->mul & 0x7));

sys/arch/x68k/dev/opm.c

197

writeopm(reg + 0x20, op->tl & 0x7f);

sys/arch/x68k/dev/opm.c

200

writeopm(reg + 0x40, (op->ks & 0x3) << 6 | (op->ar & 0x1f));

sys/arch/x68k/dev/opm.c

203

writeopm(reg + 0x60, (op->ame & 0x1) << 7 | (op->d1r & 0x1f));

sys/arch/x68k/dev/opm.c

206

writeopm(reg + 0x80, (op->dt2 & 0x3) << 6 | (op->d2r & 0x1f));

sys/arch/x68k/dev/opm.c

209

writeopm(reg + 0xa0, (op->d1l & 0xf) << 4 | (op->rr & 0xf));

sys/arch/x68k/dev/zs.c

437

zs_read_reg(struct zs_chanstate *cs, uint8_t reg)

sys/arch/x68k/dev/zs.c

441

*cs->cs_reg_csr = reg;

sys/arch/x68k/dev/zs.c

449

zs_write_reg(struct zs_chanstate *cs, uint8_t reg, uint8_t val)

sys/arch/x68k/dev/zs.c

451

*cs->cs_reg_csr = reg;

sys/arch/x68k/stand/boot/dp8390.c

50

#define NIC_GET(reg) inb(WE_IOBASE + (reg) * 2)

sys/arch/x68k/stand/boot/dp8390.c

51

#define NIC_PUT(reg, val) outb(WE_IOBASE + (reg) * 2, val)

sys/arch/x68k/x68k/iodevice.h

207

char pad0; unsigned char reg;

sys/arch/x86/isa/rtc.c

161

mc146818_read(void *sc, u_int reg)

sys/arch/x86/isa/rtc.c

164

outb(IO_RTC, reg);

sys/arch/x86/isa/rtc.c

169

mc146818_write(void *sc, u_int reg, u_int datum)

sys/arch/x86/isa/rtc.c

172

outb(IO_RTC, reg);

sys/arch/x86/pci/aapic.c

47

pcireg_t reg;

sys/arch/x86/pci/aapic.c

61

reg = pci_conf_read(pa->pa_pc, pa->pa_tag, AMD8131_IOAPIC_CTL);

sys/arch/x86/pci/aapic.c

62

reg |= AMD8131_IOAEN;

sys/arch/x86/pci/aapic.c

63

pci_conf_write(pa->pa_pc, pa->pa_tag, AMD8131_IOAPIC_CTL, reg);

sys/arch/x86/pci/aapic.c

68

reg = pci_conf_read(pa->pa_pc, tag, AMD8131_PCIX_MISC);

sys/arch/x86/pci/aapic.c

69

reg &= ~AMD8131_NIOAMODE;

sys/arch/x86/pci/aapic.c

70

pci_conf_write(pa->pa_pc, tag, AMD8131_PCIX_MISC, reg);

sys/arch/x86/pci/ichlpcib.c

1000

int reg, shift;

sys/arch/x86/pci/ichlpcib.c

1002

reg = (pin < 32) ? LPCIB_GPIO_GP_LVL : LPCIB_GPIO_GP_LVL2;

sys/arch/x86/pci/ichlpcib.c

1007

data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg);

sys/arch/x86/pci/ichlpcib.c

1014

bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg, data);

sys/arch/x86/pci/ichlpcib.c

1024

int reg, shift;

sys/arch/x86/pci/ichlpcib.c

1027

reg = (pin < 32) ? LPCIB_GPIO_GP_IO_SEL : LPCIB_GPIO_GP_IO_SEL2;

sys/arch/x86/pci/ichlpcib.c

1031

data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg);

sys/arch/x86/pci/ichlpcib.c

1039

bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg, data);

sys/arch/x86/pci/ichlpcib.c

1043

reg = LPCIB_GPIO_GPO_BLINK;

sys/arch/x86/pci/ichlpcib.c

1044

data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg);

sys/arch/x86/pci/ichlpcib.c

1051

bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg, data);

sys/arch/x86/pci/ichlpcib.c

661

#define SS_READ(sc, reg) \

sys/arch/x86/pci/ichlpcib.c

662

bus_space_read_1((sc)->sc_pmt, (sc)->sc_pmh, (reg))

sys/arch/x86/pci/ichlpcib.c

663

#define SS_WRITE(sc, reg, val) \

sys/arch/x86/pci/ichlpcib.c

664

bus_space_write_1((sc)->sc_pmt, (sc)->sc_pmh, (reg), (val))

sys/arch/x86/pci/ichlpcib.c

880

int pin, shift, base_reg, cntl_reg, reg;

sys/arch/x86/pci/ichlpcib.c

909

reg = pci_conf_read(sc->sc_pa.pa_pc, sc->sc_pa.pa_tag, base_reg);

sys/arch/x86/pci/ichlpcib.c

910

rv = bus_space_map(sc->sc_gpio_iot, PCI_MAPREG_IO_ADDR(reg),

sys/arch/x86/pci/ichlpcib.c

923

reg = (pin < 32) ? LPCIB_GPIO_GPIO_USE_SEL : LPCIB_GPIO_GPIO_USE_SEL2;

sys/arch/x86/pci/ichlpcib.c

924

use = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg);

sys/arch/x86/pci/ichlpcib.c

925

reg = (pin < 32) ? LPCIB_GPIO_GP_IO_SEL : LPCIB_GPIO_GP_IO_SEL;

sys/arch/x86/pci/ichlpcib.c

983

int reg, shift;

sys/arch/x86/pci/ichlpcib.c

985

reg = (pin < 32) ? LPCIB_GPIO_GP_LVL : LPCIB_GPIO_GP_LVL2;

sys/arch/x86/pci/ichlpcib.c

989

data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg);

sys/arch/x86/pci/pchb.c

57

#define PCISET_BRIDGE_NUMBER(reg) (((reg) >> 8) & 0xff)

sys/arch/x86/pci/pchb.c

58

#define PCISET_PCI_BUS_NUMBER(reg) (((reg) >> 16) & 0xff)

sys/arch/x86/pci/pci_bus_fixup.c

100

reg = pci_conf_read(pc, tag, PCI_ID_REG);

sys/arch/x86/pci/pci_bus_fixup.c

103

if (PCI_VENDOR(reg) == PCI_VENDOR_INVALID)

sys/arch/x86/pci/pci_bus_fixup.c

106

if (PCI_VENDOR(reg) == 0)

sys/arch/x86/pci/pci_bus_fixup.c

110

PCI_VENDOR(reg), PCI_PRODUCT(reg));

sys/arch/x86/pci/pci_bus_fixup.c

112

reg = pci_conf_read(pc, tag, PCI_CLASS_REG);

sys/arch/x86/pci/pci_bus_fixup.c

113

if (PCI_CLASS(reg) == PCI_CLASS_BRIDGE &&

sys/arch/x86/pci/pci_bus_fixup.c

114

(PCI_SUBCLASS(reg) == PCI_SUBCLASS_BRIDGE_PCI ||

sys/arch/x86/pci/pci_bus_fixup.c

115

PCI_SUBCLASS(reg) == PCI_SUBCLASS_BRIDGE_CARDBUS)) {

sys/arch/x86/pci/pci_bus_fixup.c

122

reg = pci_conf_read(pc, tag,

sys/arch/x86/pci/pci_bus_fixup.c

124

reg &= 0xff000000;

sys/arch/x86/pci/pci_bus_fixup.c

125

reg |= bus | (bus_max << 8) | (0xff << 16);

sys/arch/x86/pci/pci_bus_fixup.c

127

reg);

sys/arch/x86/pci/pci_bus_fixup.c

133

reg &= 0xff000000;

sys/arch/x86/pci/pci_bus_fixup.c

134

reg |= bus | (bus_max << 8) | (bus_sub << 16);

sys/arch/x86/pci/pci_bus_fixup.c

136

reg);

sys/arch/x86/pci/pci_bus_fixup.c

161

pcireg_t reg;

sys/arch/x86/pci/pci_bus_fixup.c

163

reg = pci_conf_read(pc, tag, PCI_BRIDGE_BUS_REG);

sys/arch/x86/pci/pci_bus_fixup.c

164

reg &= 0xff000000;

sys/arch/x86/pci/pci_bus_fixup.c

165

reg |= 0x00ffffff; /* max bus # */

sys/arch/x86/pci/pci_bus_fixup.c

166

pci_conf_write(pc, tag, PCI_BRIDGE_BUS_REG, reg);

sys/arch/x86/pci/pci_bus_fixup.c

63

pcireg_t reg;

sys/arch/x86/pci/pci_bus_fixup.c

79

reg = pci_conf_read(pc, tag, PCI_ID_REG);

sys/arch/x86/pci/pci_bus_fixup.c

82

if (PCI_VENDOR(reg) == PCI_VENDOR_INVALID)

sys/arch/x86/pci/pci_bus_fixup.c

85

if (PCI_VENDOR(reg) == 0)

sys/arch/x86/pci/pci_bus_fixup.c

88

qd = pci_lookup_quirkdata(PCI_VENDOR(reg), PCI_PRODUCT(reg));

sys/arch/x86/pci/pci_bus_fixup.c

90

reg = pci_conf_read(pc, tag, PCI_BHLC_REG);

sys/arch/x86/pci/pci_bus_fixup.c

91

if (PCI_HDRTYPE_MULTIFN(reg) ||

sys/arch/x86/pci/pci_machdep.c

387

pci_conf_selector(pcitag_t tag, int reg)

sys/arch/x86/pci/pci_machdep.c

398

return tag.mode1 | reg;

sys/arch/x86/pci/pci_machdep.c

407

pci_conf_port(pcitag_t tag, int reg)

sys/arch/x86/pci/pci_machdep.c

413

return tag.mode2.port | reg;

sys/arch/x86/pci/pci_machdep.c

669

pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg)

sys/arch/x86/pci/pci_machdep.c

676

KASSERT((reg & 0x3) == 0);

sys/arch/x86/pci/pci_machdep.c

681

return (*ipc->pc_ov->ov_conf_read)(ipc->pc_ctx, pc, tag, reg);

sys/arch/x86/pci/pci_machdep.c

688

if (reg < 0)

sys/arch/x86/pci/pci_machdep.c

690

if (reg >= PCI_CONF_SIZE) {

sys/arch/x86/pci/pci_machdep.c

692

if (reg >= PCI_EXTCONF_SIZE)

sys/arch/x86/pci/pci_machdep.c

694

acpimcfg_conf_read(pc, tag, reg, &data);

sys/arch/x86/pci/pci_machdep.c

701

pci_conf_lock(&ocl, pci_conf_selector(tag, reg));

sys/arch/x86/pci/pci_machdep.c

702

data = inl(pci_conf_port(tag, reg));

sys/arch/x86/pci/pci_machdep.c

708

pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data)

sys/arch/x86/pci/pci_machdep.c

714

KASSERT((reg & 0x3) == 0);

sys/arch/x86/pci/pci_machdep.c

719

(*ipc->pc_ov->ov_conf_write)(ipc->pc_ctx, pc, tag, reg,

sys/arch/x86/pci/pci_machdep.c

729

if (reg < 0)

sys/arch/x86/pci/pci_machdep.c

731

if (reg >= PCI_CONF_SIZE) {

sys/arch/x86/pci/pci_machdep.c

733

if (reg >= PCI_EXTCONF_SIZE)

sys/arch/x86/pci/pci_machdep.c

735

acpimcfg_conf_write(pc, tag, reg, data);

sys/arch/x86/pci/pci_machdep.c

740

pci_conf_lock(&ocl, pci_conf_selector(tag, reg));

sys/arch/x86/pci/pci_machdep.c

741

outl(pci_conf_port(tag, reg), data);

sys/arch/x86/pci/pci_machdep.c

747

pci_conf_write16(pci_chipset_tag_t pc, pcitag_t tag, int reg, uint16_t data)

sys/arch/x86/pci/pci_machdep.c

753

KASSERT((reg & 0x1) == 0);

sys/arch/x86/pci/pci_machdep.c

766

if (reg < 0)

sys/arch/x86/pci/pci_machdep.c

768

if (reg >= PCI_CONF_SIZE) {

sys/arch/x86/pci/pci_machdep.c

770

if (reg >= PCI_EXTCONF_SIZE)

sys/arch/x86/pci/pci_machdep.c

777

pci_conf_lock(&ocl, pci_conf_selector(tag, reg & ~0x3));

sys/arch/x86/pci/pci_machdep.c

778

outl(pci_conf_port(tag, reg & ~0x3) + (reg & 0x3), data);

sys/arch/x86/pci/pci_machdep.c

972

pcireg_t reg;

sys/arch/x86/pci/pci_machdep.c

974

reg = pci_conf_read(pc, tag, PCI_CLASS_REG);

sys/arch/x86/pci/pci_machdep.c

975

if (PCI_CLASS(reg) == PCI_CLASS_BRIDGE &&

sys/arch/x86/pci/pci_machdep.c

976

(PCI_SUBCLASS(reg) == PCI_SUBCLASS_BRIDGE_PCI ||

sys/arch/x86/pci/pci_machdep.c

977

PCI_SUBCLASS(reg) == PCI_SUBCLASS_BRIDGE_CARDBUS)) {

sys/arch/x86/pci/pci_ranges.c

736

prop_dictionary_t reg;

sys/arch/x86/pci/pci_ranges.c

769

ok = (reg = prop_dictionary_create()) != NULL;

sys/arch/x86/pci/pci_ranges.c

773

ok = prop_dictionary_set_uint16(reg, "offset",

sys/arch/x86/pci/pci_ranges.c

775

prop_dictionary_set_uint32(reg, "val", r->r_val) &&

sys/arch/x86/pci/pci_ranges.c

776

prop_dictionary_set_uint32(reg, "mask",

sys/arch/x86/pci/pci_ranges.c

777

r->r_mask) && prop_array_add(regs, reg);

sys/arch/x86/pci/pci_ranges.c

779

prop_object_release(reg);

sys/arch/x86/pci/rdcpcib.c

205

uint8_t reg;

sys/arch/x86/pci/rdcpcib.c

237

reg = rdc_ind_read(sc, RDC_WDT0_CTRL1);

sys/arch/x86/pci/rdcpcib.c

238

if (reg & RDC_WDT0_CRTL1_FIRE) {

sys/arch/x86/pci/rdcpcib.c

240

rdc_ind_write(sc, RDC_WDT0_CTRL1, reg & ~RDC_WDT0_CRTL1_FIRE);

sys/arch/x86/pci/rdcpcib.c

302

uint8_t reg;

sys/arch/x86/pci/rdcpcib.c

304

reg = rdc_ind_read(sc, RDC_WDT0_CTRL1);

sys/arch/x86/pci/rdcpcib.c

305

rdc_ind_write(sc, RDC_WDT0_CTRL1, reg | RDC_WDT0_CTRL1_RELOAD);

sys/arch/x86/pci/rdcpcib.c

312

uint8_t reg;

sys/arch/x86/pci/rdcpcib.c

313

reg = rdc_ind_read(sc, RDC_WDT0_CTRL);

sys/arch/x86/pci/rdcpcib.c

314

rdc_ind_write(sc, RDC_WDT0_CTRL, reg & ~RDC_WDT0_CTRL_EN);

sys/arch/x86/pci/rdcpcib.c

320

uint8_t reg;

sys/arch/x86/pci/rdcpcib.c

322

reg = rdc_ind_read(sc, RDC_WDT0_CTRL);

sys/arch/x86/pci/rdcpcib.c

323

rdc_ind_write(sc, RDC_WDT0_CTRL, reg | RDC_WDT0_CTRL_EN);

sys/arch/x86/pci/tcpcib.c

196

uint32_t reg, wdtbase;

sys/arch/x86/pci/tcpcib.c

208

reg = pci_conf_read(pa->pa_pc, pa->pa_tag, E600_LPC_WDTBA);

sys/arch/x86/pci/tcpcib.c

209

wdtbase = reg & 0xffff;

sys/arch/x86/pci/tcpcib.c

211

if (reg & (1 << 31) && wdtbase) {

sys/arch/x86/pci/tcpcib.c

222

reg = bus_space_read_1(sc->sc_wdt_iot, sc->sc_wdt_ioh,

sys/arch/x86/pci/tcpcib.c

224

if (reg & E600_WDT_RR1_TIMEOUT) {

sys/arch/x86/pci/tcpcib.c

234

reg = bus_space_read_1(sc->sc_wdt_iot, sc->sc_wdt_ioh,

sys/arch/x86/pci/tcpcib.c

236

if (reg & E600_WDT_WDTLR_LOCK) {

sys/arch/x86/x86/core_machdep.c

109

struct reg intreg;

sys/arch/x86/x86/cpu.c

388

uint32_t reg;

sys/arch/x86/x86/cpu.c

393

reg = lapic_readreg(LAPIC_ID);

sys/arch/x86/x86/cpu.c

394

lapic_writereg(LAPIC_ID, (reg & ~LAPIC_ID_MASK) |

sys/arch/x86/x86/cpu_topology.c

175

const uint64_t reg = rdmsr(MSR_NB_CFG);

sys/arch/x86/x86/cpu_topology.c

176

if ((reg & NB_CFG_INITAPICCPUIDLO) == 0) {

sys/arch/x86/x86/identcpu.c

386

cyrix_read_reg(uint8_t reg)

sys/arch/x86/x86/identcpu.c

389

outb(0x22, reg);

sys/arch/x86/x86/identcpu.c

394

cyrix_write_reg(uint8_t reg, uint8_t data)

sys/arch/x86/x86/identcpu.c

397

outb(0x22, reg);

sys/arch/x86/x86/identcpu.c

710

uint32_t reg, idx;

sys/arch/x86/x86/identcpu.c

722

reg = inl(PCI_MODE1_DATA_REG);

sys/arch/x86/x86/identcpu.c

724

if ((reg & 0xf0ffffff) != 0x30504d44) {

sys/arch/x86/x86/identcpu.c

727

idx = (reg >> 24) & 0xf;

sys/arch/x86/x86/ioapic.c

607

uint32_t reg;

sys/arch/x86/x86/ioapic.c

615

reg = ioapic_read(sc, i);

sys/arch/x86/x86/ioapic.c

616

printf(" %08x", (u_int)reg);

sys/arch/x86/x86/lapic.c

139

i82489_readreg(u_int reg)

sys/arch/x86/x86/lapic.c

141

return *((volatile uint32_t *)(local_apic_va + reg));

sys/arch/x86/x86/lapic.c

145

i82489_writereg(u_int reg, uint32_t val)

sys/arch/x86/x86/lapic.c

147

*((volatile uint32_t *)(local_apic_va + reg)) = val;

sys/arch/x86/x86/lapic.c

157

x2apic_readreg(u_int reg)

sys/arch/x86/x86/lapic.c

159

return rdmsr(MSR_X2APIC_BASE + (reg >> 4));

sys/arch/x86/x86/lapic.c

163

x2apic_writereg(u_int reg, uint32_t val)

sys/arch/x86/x86/lapic.c

166

wrmsr(MSR_X2APIC_BASE + (reg >> 4), val);

sys/arch/x86/x86/lapic.c

170

x2apic_writereg64(u_int reg, uint64_t val)

sys/arch/x86/x86/lapic.c

172

KDASSERT(reg == LAPIC_ICRLO);

sys/arch/x86/x86/lapic.c

174

wrmsr(MSR_X2APIC_BASE + (reg >> 4), val);

sys/arch/x86/x86/lapic.c

190

lapic_readreg(u_int reg)

sys/arch/x86/x86/lapic.c

193

return x2apic_readreg(reg);

sys/arch/x86/x86/lapic.c

194

return i82489_readreg(reg);

sys/arch/x86/x86/lapic.c

198

lapic_writereg(u_int reg, uint32_t val)

sys/arch/x86/x86/lapic.c

201

x2apic_writereg(reg, val);

sys/arch/x86/x86/lapic.c

203

i82489_writereg(reg, val);

sys/arch/x86/x86/lapic.c

547

uint16_t reg = LAPIC_IRR + LAPIC_TIMER_VECTOR / 32 * 16;

sys/arch/x86/x86/lapic.c

549

if (lapic_readreg(reg) & (1 << (LAPIC_TIMER_VECTOR % 32))) {

sys/arch/x86/x86/lapic.c

971

int reg;

sys/arch/x86/x86/lapic.c

974

reg = LAPIC_LVT_TIMER + (pin << 4);

sys/arch/x86/x86/lapic.c

975

val = lapic_readreg(reg);

sys/arch/x86/x86/lapic.c

977

lapic_writereg(reg, val);

sys/arch/x86/x86/lapic.c

983

int reg;

sys/arch/x86/x86/lapic.c

986

reg = LAPIC_LVT_TIMER + (pin << 4);

sys/arch/x86/x86/lapic.c

987

val = lapic_readreg(reg);

sys/arch/x86/x86/lapic.c

989

lapic_writereg(reg, val);

sys/arch/x86/x86/odcm.c

344

if ((int)msr == state[i].reg) {

sys/arch/x86/x86/odcm.c

374

if (state[i].reg != 0) /* bit 0 reserved */

sys/arch/x86/x86/odcm.c

375

msr.msr_value = (state[i].reg << ODCM_REGOFFSET) | ODCM_ENABLE;

sys/arch/x86/x86/odcm.c

62

int reg;

sys/arch/x86/x86/odcm.c

65

{ .level = 7, .reg = 0, .errata = 0 },

sys/arch/x86/x86/odcm.c

66

{ .level = 6, .reg = 7, .errata = 0 },

sys/arch/x86/x86/odcm.c

67

{ .level = 5, .reg = 6, .errata = 0 },

sys/arch/x86/x86/odcm.c

68

{ .level = 4, .reg = 5, .errata = 0 },

sys/arch/x86/x86/odcm.c

69

{ .level = 3, .reg = 4, .errata = 0 },

sys/arch/x86/x86/odcm.c

70

{ .level = 2, .reg = 3, .errata = 0 },

sys/arch/x86/x86/odcm.c

71

{ .level = 1, .reg = 2, .errata = 0 },

sys/arch/x86/x86/odcm.c

72

{ .level = 0, .reg = 1, .errata = 0 }

sys/arch/x86/x86/procfs_machdep.c

243

procfs_getonefeatreg(uint32_t reg, const char * const *table, char *p,

sys/arch/x86/x86/procfs_machdep.c

249

if ((reg & (1U << i)) && table[i]) {

sys/arch/x86/x86/viac7temp.c

178

uint32_t reg;

sys/arch/x86/x86/viac7temp.c

180

reg = 0;

sys/arch/x86/x86/viac7temp.c

185

reg = MSR_TEMP_NANO;

sys/arch/x86/x86/viac7temp.c

187

reg = MSR_TEMP_C7;

sys/arch/x86/x86/viac7temp.c

189

return reg;

sys/arch/xen/include/i82093var.h

18

apic_op.reg = regid;

sys/arch/xen/include/i82093var.h

34

apic_op.reg = regid;

sys/arch/xen/xen/pciback.c

137

pciback_read_byte(pci_chipset_tag_t pc, pcitag_t pa, int reg)

sys/arch/xen/xen/pciback.c

140

return (pci_conf_read(pc, pa, (reg & ~0x03)) >>

sys/arch/xen/xen/pciback.c

141

((reg & 0x03) * 8) & 0xff);

sys/arch/xen/xen/pciback.c

145

pciback_read_word(pci_chipset_tag_t pc, pcitag_t pa, int reg)

sys/arch/xen/xen/pciback.c

147

return (pci_conf_read(pc, pa, (reg & ~0x03)) >>

sys/arch/xen/xen/pciback.c

148

((reg & 0x03) * 8) & 0xffff);

sys/arch/xen/xen/pciback.c

152

pciback_write_byte(pci_chipset_tag_t pc, pcitag_t pa, int reg, uint8_t val)

sys/arch/xen/xen/pciback.c

156

pcival = pci_conf_read(pc, pa, (reg & ~0x03));

sys/arch/xen/xen/pciback.c

157

pcival &= ~(0xff << ((reg & 0x03) * 8));

sys/arch/xen/xen/pciback.c

158

pcival |= (val << ((reg & 0x03) * 8));

sys/arch/xen/xen/pciback.c

159

pci_conf_write(pc, pa, (reg & ~0x03), pcival);

sys/arch/xen/xen/pciback.c

163

pciback_write_word(pci_chipset_tag_t pc, pcitag_t pa, int reg, uint16_t val)

sys/arch/xen/xen/pciback.c

167

pcival = pci_conf_read(pc, pa, (reg & ~0x03));

sys/arch/xen/xen/pciback.c

168

pcival &= ~(0xffff << ((reg & 0x03) * 8));

sys/arch/xen/xen/pciback.c

169

pcival |= (val << ((reg & 0x03) * 8));

sys/arch/xen/xen/pciback.c

170

pci_conf_write(pc, pa, (reg & ~0x03), pcival);

sys/arch/xen/xen/pciback.c

225

pcireg_t reg;

sys/arch/xen/xen/pciback.c

275

reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_INTERRUPT_REG);

sys/arch/xen/xen/pciback.c

276

reg &= ~ (PCI_INTERRUPT_LINE_MASK << PCI_INTERRUPT_LINE_SHIFT);

sys/arch/xen/xen/pciback.c

277

reg |= (sc->sc_irq << PCI_INTERRUPT_LINE_SHIFT);

sys/arch/xen/xen/pciback.c

278

pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_INTERRUPT_REG, reg);

sys/arch/xen/xen/xpci_xenbus.c

429

xpci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg, int size,

sys/arch/xen/xen/xpci_xenbus.c

439

DPRINTF(("pci_conf_read %d:%d:%d reg 0x%x", bus, dev, func, reg));

sys/arch/xen/xen/xpci_xenbus.c

443

op.offset = reg;

sys/arch/xen/xen/xpci_xenbus.c

454

pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg)

sys/arch/xen/xen/xpci_xenbus.c

458

xpci_conf_read(pc, tag, reg, 4, &v);

sys/arch/xen/xen/xpci_xenbus.c

463

xpci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, int size,

sys/arch/xen/xen/xpci_xenbus.c

473

DPRINTF(("pci_conf_write %d:%d:%d reg 0x%x val 0x%x", bus, dev, func, reg, data));

sys/arch/xen/xen/xpci_xenbus.c

477

op.offset = reg;

sys/arch/xen/xen/xpci_xenbus.c

488

pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data)

sys/arch/xen/xen/xpci_xenbus.c

490

xpci_conf_write(pc, tag, reg, 4, data);

sys/arch/xen/xen/xpci_xenbus.c

578

int reg;

sys/arch/xen/xen/xpci_xenbus.c

595

for (reg = PCI_MAPREG_START;

sys/arch/xen/xen/xpci_xenbus.c

596

reg < PCI_MAPREG_END;

sys/arch/xen/xen/xpci_xenbus.c

597

reg += 4) {

sys/arch/xen/xen/xpci_xenbus.c

598

if (xpci_conf_read(pc, tag, reg, 4,

sys/arch/xen/xen/xpci_xenbus.c

604

reg);

sys/arch/zaurus/dev/ioexp.c

269

uint8_t reg = ioexp_gpio_pin_get(sc, IOEXP_IR_ON);

sys/arch/zaurus/dev/ioexp.c

270

if (onoff && reg) {

sys/arch/zaurus/dev/ioexp.c

273

} else if (!onoff && !reg) {

sys/arch/zaurus/dev/ioexp.c

301

uint8_t reg = ioexp_gpio_pin_get(sc, IOEXP_MIC_BIAS);

sys/arch/zaurus/dev/ioexp.c

302

if (onoff && !reg) {

sys/arch/zaurus/dev/ioexp.c

305

} else if (!onoff && reg) {

sys/arch/zaurus/dev/ioexp.c

333

uint8_t reg = ioexp_gpio_pin_get(sc, IOEXP_AKIN_PULLUP);

sys/arch/zaurus/dev/ioexp.c

334

if (onoff && !reg) {

sys/arch/zaurus/dev/ioexp.c

337

} else if (!onoff && reg) {

sys/arch/zaurus/dev/ioexp.c

72

ioexp_write(struct ioexp_softc *sc, uint8_t reg, uint8_t val)

sys/arch/zaurus/dev/ioexp.c

78

cmd = reg;

sys/arch/zaurus/dev/scoop_pcic.c

163

scoop_pcic_read(struct pxapcic_socket *so, int reg)

sys/arch/zaurus/dev/scoop_pcic.c

171

switch (reg) {

sys/arch/zaurus/dev/scoop_pcic.c

189

scoop_pcic_write(struct pxapcic_socket *so, int reg, u_int val)

sys/arch/zaurus/dev/scoop_pcic.c

198

switch (reg) {

sys/arch/zaurus/dev/scoop_pcic.c

228

u_int16_t reg;

sys/arch/zaurus/dev/scoop_pcic.c

237

reg = bus_space_read_2(iot, ioh, SCOOP_GPWR);

sys/arch/zaurus/dev/scoop_pcic.c

239

reg & ~(1 << SCOOP0_CF_POWER_C3000));

sys/arch/zaurus/dev/scoop_pcic.c

247

reg = bus_space_read_2(iot, ioh, SCOOP_GPWR);

sys/arch/zaurus/dev/scoop_pcic.c

249

reg | (1 << SCOOP0_CF_POWER_C3000));

sys/arch/zaurus/dev/wm8731_zaudio.c

175

wm8731_write(struct zaudio_softc *sc, int reg, int val)

sys/arch/zaurus/dev/wm8731_zaudio.c

181

tmp = (reg << 9) | (val & 0x1ff);

sys/arch/zaurus/dev/wm8750_zaudio.c

207

wm8750_write(struct zaudio_softc *sc, int reg, int val)

sys/arch/zaurus/dev/wm8750_zaudio.c

213

tmp = (reg << 9) | (val & 0x1ff);

sys/arch/zaurus/dev/ztp.c

347

pxa2x0_ccnt_enable(uint32_t reg)

sys/arch/zaurus/dev/ztp.c

352

__asm volatile("mcr p14, 0, %0, c0, c1, 0" : : "r" (reg));

sys/compat/linux/arch/alpha/linux_machdep.c

157

frametoreg(tf, (struct reg *)sigframe.uc.uc_mcontext.sc_regs);

sys/compat/linux/arch/alpha/linux_machdep.c

247

frametoreg(tf, (struct reg *)sigframe.sf_sc.sc_regs);

sys/compat/linux/arch/alpha/linux_machdep.c

395

regtoframe((struct reg *)context.sc_regs, l->l_md.md_tf);

sys/compat/linux/arch/arm/linux_ptrace.c

108

struct reg *regs = NULL;

sys/compat/linux/arch/arm/linux_ptrace.c

117

regs = kmem_alloc(sizeof(struct reg), KM_SLEEP);

sys/compat/linux/arch/i386/linux_machdep.h

54

uint32_t reg[4];

sys/compat/linux/arch/i386/linux_ptrace.c

132

struct reg *regs = NULL;

sys/compat/linux/arch/i386/linux_ptrace.c

152

regs = kmem_alloc(sizeof(struct reg), KM_SLEEP);

sys/compat/linux/arch/powerpc/linux_ptrace.c

110

struct reg *regs = NULL;

sys/compat/linux/arch/powerpc/linux_ptrace.c

125

regs = kmem_alloc(sizeof(struct reg), KM_SLEEP);

sys/compat/linux/arch/powerpc/linux_ptrace.c

129

regs = kmem_alloc(sizeof(struct reg), KM_SLEEP);

sys/dev/acpi/acpi_cpu.h

287

acpicpu_readreg(struct acpicpu_reg *reg)

sys/dev/acpi/acpi_cpu.h

294

KASSERT(reg->reg_spaceid == ACPI_ADR_SPACE_SYSTEM_IO ||

sys/dev/acpi/acpi_cpu.h

295

reg->reg_spaceid == ACPI_ADR_SPACE_SYSTEM_MEMORY);

sys/dev/acpi/acpi_cpu.h

298

__BITS(reg->reg_bitoffset + reg->reg_bitwidth - 1,

sys/dev/acpi/acpi_cpu.h

299

reg->reg_bitoffset);

sys/dev/acpi/acpi_cpu.h

302

if (reg->reg_spaceid == ACPI_ADR_SPACE_SYSTEM_IO) {

sys/dev/acpi/acpi_cpu.h

303

AcpiOsReadPort(reg->reg_addr, &val.u32,

sys/dev/acpi/acpi_cpu.h

304

ACPI_ACCESS_BIT_WIDTH(reg->reg_accesssize));

sys/dev/acpi/acpi_cpu.h

306

AcpiOsReadMemory(reg->reg_addr, &val.u64,

sys/dev/acpi/acpi_cpu.h

307

ACPI_ACCESS_BIT_WIDTH(reg->reg_accesssize));

sys/dev/acpi/acpi_cpu.h

322

acpicpu_writereg(struct acpicpu_reg *reg, uint32_t newval)

sys/dev/acpi/acpi_cpu.h

329

KASSERT(reg->reg_spaceid == ACPI_ADR_SPACE_SYSTEM_IO ||

sys/dev/acpi/acpi_cpu.h

330

reg->reg_spaceid == ACPI_ADR_SPACE_SYSTEM_MEMORY);

sys/dev/acpi/acpi_cpu.h

333

__BITS(reg->reg_bitoffset + reg->reg_bitwidth - 1,

sys/dev/acpi/acpi_cpu.h

334

reg->reg_bitoffset);

sys/dev/acpi/acpi_cpu.h

337

if (reg->reg_spaceid == ACPI_ADR_SPACE_SYSTEM_IO) {

sys/dev/acpi/acpi_cpu.h

338

AcpiOsReadPort(reg->reg_addr, &val.u32,

sys/dev/acpi/acpi_cpu.h

339

ACPI_ACCESS_BIT_WIDTH(reg->reg_accesssize));

sys/dev/acpi/acpi_cpu.h

341

AcpiOsReadMemory(reg->reg_addr, &val.u64,

sys/dev/acpi/acpi_cpu.h

342

ACPI_ACCESS_BIT_WIDTH(reg->reg_accesssize));

sys/dev/acpi/acpi_cpu.h

346

if (reg->reg_spaceid == ACPI_ADR_SPACE_SYSTEM_IO) {

sys/dev/acpi/acpi_cpu.h

347

AcpiOsWritePort(reg->reg_addr, val.u32,

sys/dev/acpi/acpi_cpu.h

348

ACPI_ACCESS_BIT_WIDTH(reg->reg_accesssize));

sys/dev/acpi/acpi_cpu.h

350

AcpiOsWriteMemory(reg->reg_addr, val.u64,

sys/dev/acpi/acpi_cpu.h

351

ACPI_ACCESS_BIT_WIDTH(reg->reg_accesssize));

sys/dev/acpi/acpi_cpu_cstate.c

238

struct acpicpu_reg *reg;

sys/dev/acpi/acpi_cpu_cstate.c

313

reg = (struct acpicpu_reg *)obj->Buffer.Pointer;

sys/dev/acpi/acpi_cpu_cstate.c

315

switch (reg->reg_spaceid) {

sys/dev/acpi/acpi_cpu_cstate.c

320

if (reg->reg_addr == 0) {

sys/dev/acpi/acpi_cpu_cstate.c

325

if (reg->reg_bitwidth != 8) {

sys/dev/acpi/acpi_cpu_cstate.c

330

state.cs_addr = reg->reg_addr;

sys/dev/acpi/acpi_cpu_cstate.c

370

if ((reg->reg_accesssize & ACPICPU_PDC_GAS_BM) == 0)

sys/dev/acpi/acpi_cpu_cstate.c

579

const uint32_t reg = AcpiGbl_FADT.Pm2ControlBlock;

sys/dev/acpi/acpi_cpu_cstate.c

595

if (reg != 0 && len != 0) {

sys/dev/acpi/acpi_cpu_pstate.c

476

struct acpicpu_reg *reg[2];

sys/dev/acpi/acpi_cpu_pstate.c

515

reg[i] = (struct acpicpu_reg *)elm->Buffer.Pointer;

sys/dev/acpi/acpi_cpu_pstate.c

517

switch (reg[i]->reg_spaceid) {

sys/dev/acpi/acpi_cpu_pstate.c

522

if (reg[i]->reg_addr == 0) {

sys/dev/acpi/acpi_cpu_pstate.c

527

width = reg[i]->reg_bitwidth;

sys/dev/acpi/acpi_cpu_pstate.c

529

if (width + reg[i]->reg_bitoffset > 32) {

sys/dev/acpi/acpi_cpu_pstate.c

545

if (reg[i]->reg_bitwidth != 64) {

sys/dev/acpi/acpi_cpu_pstate.c

550

if (reg[i]->reg_bitoffset != 0) {

sys/dev/acpi/acpi_cpu_pstate.c

571

if (reg[0]->reg_spaceid != reg[1]->reg_spaceid) {

sys/dev/acpi/acpi_cpu_pstate.c

576

(void)memcpy(&sc->sc_pstate_control, reg[0], size);

sys/dev/acpi/acpi_cpu_pstate.c

577

(void)memcpy(&sc->sc_pstate_status, reg[1], size);

sys/dev/acpi/acpi_cpu_tstate.c

353

struct acpicpu_reg *reg[2];

sys/dev/acpi/acpi_cpu_tstate.c

390

reg[i] = (struct acpicpu_reg *)elm->Buffer.Pointer;

sys/dev/acpi/acpi_cpu_tstate.c

392

switch (reg[i]->reg_spaceid) {

sys/dev/acpi/acpi_cpu_tstate.c

396

if (reg[i]->reg_addr == 0) {

sys/dev/acpi/acpi_cpu_tstate.c

405

if (reg[i]->reg_addr == 0) {

sys/dev/acpi/acpi_cpu_tstate.c

417

if (reg[i]->reg_bitwidth != 4) {

sys/dev/acpi/acpi_cpu_tstate.c

422

if (reg[i]->reg_bitoffset != 1) {

sys/dev/acpi/acpi_cpu_tstate.c

445

if (reg[0]->reg_spaceid != reg[1]->reg_spaceid) {

sys/dev/acpi/acpi_cpu_tstate.c

450

(void)memcpy(&sc->sc_tstate_control, reg[0], size);

sys/dev/acpi/acpi_cpu_tstate.c

451

(void)memcpy(&sc->sc_tstate_status, reg[1], size);

sys/dev/acpi/acpi_ec.c

1003

if ((reg & EC_STATUS_IBF) != 0)

sys/dev/acpi/acpi_ec.c

1010

if ((reg & EC_STATUS_OBF) == 0)

sys/dev/acpi/acpi_ec.c

1017

if ((reg & EC_STATUS_IBF) != 0)

sys/dev/acpi/acpi_ec.c

1024

if ((reg & EC_STATUS_IBF) != 0)

sys/dev/acpi/acpi_ec.c

1031

if ((reg & EC_STATUS_IBF) != 0)

sys/dev/acpi/acpi_ec.c

1051

if (reg & EC_STATUS_SCI) {

sys/dev/acpi/acpi_ec.c

908

uint8_t reg;

sys/dev/acpi/acpi_ec.c

940

reg = sc->sc_cur_val;

sys/dev/acpi/acpi_ec.c

941

DPRINTF(ACPIEC_DEBUG_QUERY, sc, "SCI query: 0x%"PRIx8"\n", reg);

sys/dev/acpi/acpi_ec.c

946

if (reg == 0)

sys/dev/acpi/acpi_ec.c

952

snprintf(qxx, sizeof(qxx), "_Q%02X", (unsigned int)reg);

sys/dev/acpi/acpi_ec.c

965

uint8_t reg;

sys/dev/acpi/acpi_ec.c

969

reg = acpiec_read_status(sc);

sys/dev/acpi/acpi_ec.c

975

snprintb(buf, sizeof(buf), EC_STATUS_FMT, reg);

sys/dev/acpi/acpi_ec.c

982

if ((reg & EC_STATUS_IBF) != 0)

sys/dev/acpi/acpi_ec.c

989

if ((reg & EC_STATUS_OBF) == 0)

sys/dev/acpi/acpi_ec.c

996

if ((reg & EC_STATUS_IBF) != 0)

sys/dev/acpi/acpi_mcfg.c

472

pcireg_t reg;

sys/dev/acpi/acpi_mcfg.c

505

reg = pci_conf_read(pc, tag, PCI_ID_REG);

sys/dev/acpi/acpi_mcfg.c

506

qd = pci_lookup_quirkdata(PCI_VENDOR(reg), PCI_PRODUCT(reg));

sys/dev/acpi/acpi_mcfg.c

514

((reg = pci_conf_read(pc, tag, PCI_CONF_SIZE)) == (pcireg_t)-1)

sys/dev/acpi/acpi_mcfg.c

515

|| (reg == 0)

sys/dev/acpi/acpi_mcfg.c

520

PCI_CONF_SIZE, reg, alias ? "true" : "false");

sys/dev/acpi/acpi_mcfg.c

526

bus, dev, func, PCI_CONF_SIZE, reg,

sys/dev/acpi/acpi_mcfg.c

555

pcireg_t reg;

sys/dev/acpi/acpi_mcfg.c

610

reg = pci_conf_read(pc, tag, PCI_ID_REG);

sys/dev/acpi/acpi_mcfg.c

611

is_e7520_mch = (reg ==

sys/dev/acpi/acpi_mcfg.c

614

reg = pci_conf_read(pc, tag, 0x54);

sys/dev/acpi/acpi_mcfg.c

615

pci_conf_write(pc, tag, 0x54, reg | 0x20);

sys/dev/acpi/acpi_mcfg.c

621

pci_conf_write(pc, tag, 0x54, reg);

sys/dev/acpi/acpi_mcfg.c

895

acpimcfg_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t *data)

sys/dev/acpi/acpi_mcfg.c

901

KASSERT(reg < PCI_EXTCONF_SIZE);

sys/dev/acpi/acpi_mcfg.c

902

KASSERT((reg & 3) == 0);

sys/dev/acpi/acpi_mcfg.c

922

if (!EXTCONF_IS_VALID(mb, dev, func) && reg >= PCI_CONF_SIZE) {

sys/dev/acpi/acpi_mcfg.c

927

*data = mcfg_ops->ao_read(seg->ms_bst, mb->bsh[dev][func], reg);

sys/dev/acpi/acpi_mcfg.c

932

acpimcfg_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data)

sys/dev/acpi/acpi_mcfg.c

938

KASSERT(reg < PCI_EXTCONF_SIZE);

sys/dev/acpi/acpi_mcfg.c

939

KASSERT((reg & 3) == 0);

sys/dev/acpi/acpi_mcfg.c

953

if (!EXTCONF_IS_VALID(mb, dev, func) && reg >= PCI_CONF_SIZE)

sys/dev/acpi/acpi_mcfg.c

956

mcfg_ops->ao_write(seg->ms_bst, mb->bsh[dev][func], reg, data);

sys/dev/acpi/acpi_mcfg.c

961

acpimcfg_conf_valid(pci_chipset_tag_t pc, pcitag_t tag, int reg)

sys/dev/acpi/acpi_mcfg.c

979

if (!EXTCONF_IS_VALID(mb, dev, func) && reg >= PCI_CONF_SIZE)

sys/dev/acpi/acpi_pcc.c

243

pcc_doorbell(struct pcc_register *reg)

sys/dev/acpi/acpi_pcc.c

248

rv = AcpiRead(&val, &reg->reg_addr);

sys/dev/acpi/acpi_pcc.c

252

val &= reg->reg_preserve;

sys/dev/acpi/acpi_pcc.c

253

val |= reg->reg_set;

sys/dev/acpi/acpi_pcc.c

254

return AcpiWrite(val, &reg->reg_addr);

sys/dev/acpi/acpi_pcc.c

263

pcc_send_command(struct pcc_subspace *ss, ACPI_GENERIC_ADDRESS *reg,

sys/dev/acpi/acpi_pcc.c

277

mask = __BITS(reg->BitOffset + reg->BitWidth - 1,

sys/dev/acpi/acpi_pcc.c

278

reg->BitOffset);

sys/dev/acpi/acpi_pcc.c

279

ACPI_MOVE_64_TO_64(&tmp, data + reg->Address);

sys/dev/acpi/acpi_pcc.c

282

ACPI_MOVE_64_TO_64(data + reg->Address, &tmp);

sys/dev/acpi/acpi_pcc.c

298

pcc_receive_response(struct pcc_subspace *ss, ACPI_GENERIC_ADDRESS *reg,

sys/dev/acpi/acpi_pcc.c

316

mask = __BITS(reg->BitOffset + reg->BitWidth - 1,

sys/dev/acpi/acpi_pcc.c

317

reg->BitOffset);

sys/dev/acpi/acpi_pcc.c

318

ACPI_MOVE_64_TO_64(&tmp, data + reg->Address);

sys/dev/acpi/acpi_pcc.c

331

pcc_message(ACPI_GENERIC_ADDRESS *reg, uint32_t command, int flags,

sys/dev/acpi/acpi_pcc.c

340

ss_id = reg->AccessWidth;

sys/dev/acpi/acpi_pcc.c

368

rv = pcc_send_command(ss, reg, command, flags, *val);

sys/dev/acpi/acpi_pcc.c

380

rv = pcc_receive_response(ss, reg, flags, val);

sys/dev/acpi/acpi_pci_link.c

1032

pcireg_t reg;

sys/dev/acpi/acpi_pci_link.c

1077

reg = pci_conf_read(pc, link->l_devices[i],

sys/dev/acpi/acpi_pci_link.c

1079

reg &= ~(PCI_INTERRUPT_LINE_MASK << PCI_INTERRUPT_LINE_SHIFT);

sys/dev/acpi/acpi_pci_link.c

1080

reg |= link->l_irq << PCI_INTERRUPT_LINE_SHIFT;

sys/dev/acpi/acpi_pci_link.c

1082

PCI_INTERRUPT_REG, reg);

sys/dev/acpi/amdgpio.c

77

#define RD4(sc, reg) \

sys/dev/acpi/amdgpio.c

78

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/dev/acpi/amdgpio.c

79

#define WR4(sc, reg, val) \

sys/dev/acpi/amdgpio.c

80

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/dev/acpi/apei_einj.c

410

ACPI_GENERIC_ADDRESS *const reg = &header->RegisterRegion;

sys/dev/acpi/apei_einj.c

422

reg->Address,

sys/dev/acpi/apei_einj.c

436

M->y = apei_read_register(reg, map, Mask);

sys/dev/acpi/apei_einj.c

441

v = apei_read_register(reg, map, Mask);

sys/dev/acpi/apei_einj.c

446

apei_write_register(reg, map, Mask, preserve_register, M->x);

sys/dev/acpi/apei_einj.c

449

apei_write_register(reg, map, Mask, preserve_register, Value);

sys/dev/acpi/apei_erst.c

387

ACPI_GENERIC_ADDRESS *const reg = &header->RegisterRegion;

sys/dev/acpi/apei_erst.c

399

reg->Address,

sys/dev/acpi/apei_erst.c

413

M->y = apei_read_register(reg, map, Mask);

sys/dev/acpi/apei_erst.c

418

v = apei_read_register(reg, map, Mask);

sys/dev/acpi/apei_erst.c

423

apei_write_register(reg, map, Mask, preserve_register, M->x);

sys/dev/acpi/apei_erst.c

426

apei_write_register(reg, map, Mask, preserve_register, Value);

sys/dev/acpi/apei_erst.c

431

M->var1 = apei_read_register(reg, map, Mask);

sys/dev/acpi/apei_erst.c

434

M->var2 = apei_read_register(reg, map, Mask);

sys/dev/acpi/apei_erst.c

437

apei_write_register(reg, map, Mask, preserve_register,

sys/dev/acpi/apei_erst.c

462

v = apei_read_register(reg, map, Mask);

sys/dev/acpi/apei_erst.c

464

apei_write_register(reg, map, Mask, preserve_register, v);

sys/dev/acpi/apei_erst.c

470

v = apei_read_register(reg, map, Mask);

sys/dev/acpi/apei_erst.c

472

apei_write_register(reg, map, Mask, preserve_register, v);

sys/dev/acpi/apei_erst.c

480

if (apei_read_register(reg, map, Mask) != Value)

sys/dev/acpi/apei_erst.c

491

if (apei_read_register(reg, map, Mask) == Value) {

sys/dev/acpi/apei_erst.c

503

M->src_base = apei_read_register(reg, map, Mask);

sys/dev/acpi/apei_erst.c

506

M->src_base = apei_read_register(reg, map, Mask);

sys/dev/acpi/apei_erst.c

509

const uint64_t v = apei_read_register(reg, map, Mask);

sys/dev/acpi/apei_mapreg.c

101

if (reg->BitWidth % (8*(1 << (reg->AccessWidth - 1))))

sys/dev/acpi/apei_mapreg.c

107

switch (reg->SpaceId) {

sys/dev/acpi/apei_mapreg.c

113

return (struct apei_mapreg *)__UNCONST(reg);

sys/dev/acpi/apei_mapreg.c

115

return AcpiOsMapMemory(reg->Address,

sys/dev/acpi/apei_mapreg.c

116

1 << (reg->AccessWidth - 1));

sys/dev/acpi/apei_mapreg.c

128

apei_mapreg_unmap(const ACPI_GENERIC_ADDRESS *reg,

sys/dev/acpi/apei_mapreg.c

132

switch (reg->SpaceId) {

sys/dev/acpi/apei_mapreg.c

134

KASSERT(map == __UNCONST(reg));

sys/dev/acpi/apei_mapreg.c

137

AcpiOsUnmapMemory(map, 1 << (reg->AccessWidth - 1));

sys/dev/acpi/apei_mapreg.c

150

apei_mapreg_read(const ACPI_GENERIC_ADDRESS *reg,

sys/dev/acpi/apei_mapreg.c

153

unsigned chunkbits = NBBY*(1 << (reg->AccessWidth - 1));

sys/dev/acpi/apei_mapreg.c

154

unsigned i, n = reg->BitWidth / chunkbits;

sys/dev/acpi/apei_mapreg.c

160

switch (reg->SpaceId) {

sys/dev/acpi/apei_mapreg.c

166

switch (reg->AccessWidth) {

sys/dev/acpi/apei_mapreg.c

168

addr = reg->Address + i;

sys/dev/acpi/apei_mapreg.c

171

addr = reg->Address + 2*i;

sys/dev/acpi/apei_mapreg.c

174

addr = reg->Address + 4*i;

sys/dev/acpi/apei_mapreg.c

181

NBBY*(1 << (reg->AccessWidth - 1)));

sys/dev/acpi/apei_mapreg.c

188

switch (reg->AccessWidth) {

sys/dev/acpi/apei_mapreg.c

221

apei_mapreg_write(const ACPI_GENERIC_ADDRESS *reg, struct apei_mapreg *map,

sys/dev/acpi/apei_mapreg.c

224

unsigned chunkbits = NBBY*(1 << (reg->AccessWidth - 1));

sys/dev/acpi/apei_mapreg.c

225

unsigned i, n = reg->BitWidth / chunkbits;

sys/dev/acpi/apei_mapreg.c

231

switch (reg->SpaceId) {

sys/dev/acpi/apei_mapreg.c

236

switch (reg->AccessWidth) {

sys/dev/acpi/apei_mapreg.c

238

addr = reg->Address + i;

sys/dev/acpi/apei_mapreg.c

241

addr = reg->Address + 2*i;

sys/dev/acpi/apei_mapreg.c

244

addr = reg->Address + 4*i;

sys/dev/acpi/apei_mapreg.c

251

NBBY*(1 << (reg->AccessWidth - 1)));

sys/dev/acpi/apei_mapreg.c

257

switch (reg->AccessWidth) {

sys/dev/acpi/apei_mapreg.c

53

apei_mapreg_map(const ACPI_GENERIC_ADDRESS *reg)

sys/dev/acpi/apei_mapreg.c

59

switch (reg->BitWidth) {

sys/dev/acpi/apei_mapreg.c

72

switch (reg->AccessWidth) {

sys/dev/acpi/apei_mapreg.c

78

if (reg->SpaceId == ACPI_ADR_SPACE_SYSTEM_IO)

sys/dev/acpi/apei_mapreg.c

90

switch (reg->BitOffset) {

sys/dev/acpi/hpacel_acpi.c

359

hpacel_reg_read(ACPI_HANDLE hdl, ACPI_INTEGER reg, uint8_t *valp)

sys/dev/acpi/hpacel_acpi.c

367

obj.Integer.Value = reg;

sys/dev/acpi/hpacel_acpi.c

390

hpacel_reg_write(ACPI_HANDLE hdl, ACPI_INTEGER reg, uint8_t val)

sys/dev/acpi/hpacel_acpi.c

397

obj[0].Integer.Value = reg;

sys/dev/acpi/hpacel_acpi.c

409

ACPI_INTEGER reg[2];

sys/dev/acpi/hpacel_acpi.c

416

reg[0] = OUTX_L;

sys/dev/acpi/hpacel_acpi.c

417

reg[1] = OUTX_H;

sys/dev/acpi/hpacel_acpi.c

421

reg[0] = OUTY_L;

sys/dev/acpi/hpacel_acpi.c

422

reg[1] = OUTY_H;

sys/dev/acpi/hpacel_acpi.c

426

reg[0] = OUTZ_L;

sys/dev/acpi/hpacel_acpi.c

427

reg[1] = OUTZ_H;

sys/dev/acpi/hpacel_acpi.c

434

rv[0] = hpacel_reg_read(hdl, reg[0], &lo);

sys/dev/acpi/hpacel_acpi.c

435

rv[1] = hpacel_reg_read(hdl, reg[1], &hi);

sys/dev/acpi/qcomgpio.c

103

#define RD4(sc, reg) \

sys/dev/acpi/qcomgpio.c

104

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/dev/acpi/qcomgpio.c

105

#define WR4(sc, reg, val) \

sys/dev/acpi/qcomgpio.c

106

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/dev/acpi/qcomgpioreg.h

23

#define _TLMM_GPIO_PIN_OFFSET(pin, reg) ((pin) * 0x1000 + (reg))

sys/dev/acpi/qcomiic.c

48

#define HREAD4(sc, reg) \

sys/dev/acpi/qcomiic.c

49

bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg))

sys/dev/acpi/qcomiic.c

50

#define HWRITE4(sc, reg, val) \

sys/dev/acpi/qcomiic.c

51

bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))

sys/dev/acpi/qcomipcc.c

154

uint32_t reg;

sys/dev/acpi/qcomipcc.c

157

while ((reg = HREAD4(sc, IPCC_RECV_ID)) != ~0) {

sys/dev/acpi/qcomipcc.c

158

HWRITE4(sc, IPCC_RECV_SIGNAL_CLEAR, reg);

sys/dev/acpi/qcomipcc.c

160

client_id = __SHIFTOUT(reg, IPCC_CLIENT_ID_MASK);

sys/dev/acpi/qcomipcc.c

161

signal_id = __SHIFTOUT(reg, IPCC_SIGNAL_ID_MASK);

sys/dev/acpi/qcomipcc.c

37

#define HREAD4(sc, reg) \

sys/dev/acpi/qcomipcc.c

38

bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg))

sys/dev/acpi/qcomipcc.c

39

#define HWRITE4(sc, reg, val) \

sys/dev/acpi/qcomipcc.c

40

bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))

sys/dev/acpi/qcompep.c

298

uint32_t reg;

sys/dev/acpi/qcompep.c

310

memcpy(&reg, data + i, sizeof(reg));

sys/dev/acpi/qcompep.c

311

AOSSWRITE4(sc, sc->sc_aoss_offset + sizeof(uint32_t) + i, reg);

sys/dev/acpi/qcompep.c

54

#define AOSSREAD4(sc, reg) \

sys/dev/acpi/qcompep.c

55

bus_space_read_4((sc)->sc_iot, (sc)->sc_aoss_ioh, (reg))

sys/dev/acpi/qcompep.c

56

#define AOSSWRITE4(sc, reg, val) \

sys/dev/acpi/qcompep.c

57

bus_space_write_4((sc)->sc_iot, (sc)->sc_aoss_ioh, (reg), (val))

sys/dev/acpi/qcompep.c

66

#define RXREAD8(sc, reg) \

sys/dev/acpi/qcompep.c

67

(bus_space_read_8((sc)->sc_iot, (sc)->sc_cpucp_rx_ioh, (reg)))

sys/dev/acpi/qcompep.c

68

#define RXWRITE8(sc, reg, val) \

sys/dev/acpi/qcompep.c

69

bus_space_write_8((sc)->sc_iot, (sc)->sc_cpucp_rx_ioh, (reg), (val))

sys/dev/acpi/qcompep.c

71

#define TXWRITE4(sc, reg, val) \

sys/dev/acpi/qcompep.c

72

bus_space_write_4((sc)->sc_iot, (sc)->sc_cpucp_tx_ioh, (reg), (val))

sys/dev/acpi/qcomsmem.c

132

#define MTXREAD4(sc, reg) \

sys/dev/acpi/qcomsmem.c

133

bus_space_read_4((sc)->sc_iot, (sc)->sc_mtx_ioh, (reg))

sys/dev/acpi/qcomsmem.c

134

#define MTXWRITE4(sc, reg, val) \

sys/dev/acpi/qcomsmem.c

135

bus_space_write_4((sc)->sc_iot, (sc)->sc_mtx_ioh, (reg), (val))

sys/dev/acpi/qcomspmi.c

102

#define HREAD4(sc, obj, reg) \

sys/dev/acpi/qcomspmi.c

104

(sc)->sc_data->regs[obj] + (reg))

sys/dev/acpi/qcomspmi.c

105

#define HWRITE4(sc, obj, reg, val) \

sys/dev/acpi/qcomspmi.c

107

(sc)->sc_data->regs[obj] + (reg), (val))

sys/dev/acpi/qcomspmi.c

277

uint32_t reg;

sys/dev/acpi/qcomspmi.c

300

reg = HREAD4(sc, QCSPMI_REG_OBSRVR,

sys/dev/acpi/qcomspmi.c

302

if (reg & SPMI_STATUS_DONE)

sys/dev/acpi/qcomspmi.c

304

if (reg & SPMI_STATUS_FAILURE) {

sys/dev/acpi/qcomspmi.c

308

if (reg & SPMI_STATUS_DENIED) {

sys/dev/acpi/qcomspmi.c

312

if (reg & SPMI_STATUS_DROPPED) {

sys/dev/acpi/qcomspmi.c

323

reg = HREAD4(sc, QCSPMI_REG_OBSRVR,

sys/dev/acpi/qcomspmi.c

325

memcpy(cbuf, &reg, MIN(len, 4));

sys/dev/acpi/qcomspmi.c

330

reg = HREAD4(sc, QCSPMI_REG_OBSRVR,

sys/dev/acpi/qcomspmi.c

332

memcpy(cbuf, &reg, MIN(len, 4));

sys/dev/acpi/qcomspmi.c

345

uint32_t reg;

sys/dev/acpi/qcomspmi.c

366

memcpy(&reg, cbuf, MIN(len, 4));

sys/dev/acpi/qcomspmi.c

368

SPMI_WDATA0, reg);

sys/dev/acpi/qcomspmi.c

373

memcpy(&reg, cbuf, MIN(len, 4));

sys/dev/acpi/qcomspmi.c

375

SPMI_WDATA1, reg);

sys/dev/acpi/qcomspmi.c

385

reg = HREAD4(sc, QCSPMI_REG_CHNLS, SPMI_CHAN_OFF(sc, apid) +

sys/dev/acpi/qcomspmi.c

387

if (reg & SPMI_STATUS_DONE)

sys/dev/acpi/qcomspmi.c

393

if (reg & SPMI_STATUS_FAILURE ||

sys/dev/acpi/qcomspmi.c

394

reg & SPMI_STATUS_DENIED ||

sys/dev/acpi/qcomspmi.c

395

reg & SPMI_STATUS_DROPPED)

sys/dev/acpi/sdhc_acpi.c

361

uint8_t reg;

sys/dev/acpi/sdhc_acpi.c

365

reg = sdhc_host_read_1(hp, SDHC_POWER_CTL);

sys/dev/acpi/sdhc_acpi.c

366

reg |= 0x10;

sys/dev/acpi/sdhc_acpi.c

367

sdhc_host_write_1(hp, SDHC_POWER_CTL, reg);

sys/dev/acpi/sdhc_acpi.c

371

reg &= ~0x10;

sys/dev/acpi/sdhc_acpi.c

372

sdhc_host_write_1(hp, SDHC_POWER_CTL, reg);

sys/dev/acpi/vald_acpi.c

316

uint32_t reg, uint32_t *value, uint32_t *result)

sys/dev/acpi/vald_acpi.c

331

Arg[1].Integer.Value = reg;

sys/dev/acpi/vald_acpi.c

373

uint32_t reg, uint32_t value, uint32_t *result)

sys/dev/acpi/vald_acpi.c

389

Arg[1].Integer.Value = reg;

sys/dev/acpi/valz_acpi.c

433

uint32_t reg, uint32_t *value, uint32_t *result)

sys/dev/acpi/valz_acpi.c

441

input[HCI_REG_BX] = reg;

sys/dev/acpi/valz_acpi.c

462

uint32_t reg, uint32_t value, uint32_t *result)

sys/dev/acpi/valz_acpi.c

470

input[HCI_REG_BX] = reg;

sys/dev/adb/adb_kbd.c

793

int reg;

sys/dev/adb/adb_kbd.c

796

reg = sc->sc_trans[1];

sys/dev/adb/adb_kbd.c

799

node.sysctl_data = ®

sys/dev/adb/adb_kbd.c

807

node.sysctl_data = ®

sys/dev/adb/adb_kbd.c

819

int reg;

sys/dev/adb/adb_kbd.c

822

reg = sc->sc_trans[2];

sys/dev/adb/adb_kbd.c

825

node.sysctl_data = ®

sys/dev/adb/adb_kbd.c

833

node.sysctl_data = ®

sys/dev/adb/adb_kbd.c

847

int reg;

sys/dev/adb/adb_kbd.c

850

reg = sc->sc_emul_usb;

sys/dev/adb/adb_kbd.c

853

node.sysctl_data = ®

sys/dev/adb/adb_kbd.c

881

node.sysctl_data = ®

sys/dev/adb/adb_kbd.c

882

node.sysctl_size = sizeof(reg);

sys/dev/adb/adb_kbd.c

893

bool reg;

sys/dev/adb/adb_kbd.c

896

reg = sc->sc_power_dbg;

sys/dev/adb/adb_kbd.c

899

node.sysctl_data = ®

sys/dev/adb/adb_kbd.c

907

node.sysctl_data = ®

sys/dev/adb/adb_kbd.c

908

node.sysctl_size = sizeof(reg);

sys/dev/adb/adb_ktm.c

166

uint8_t reg;

sys/dev/adb/adb_ktm.c

168

reg = button_to_reg[sc->sc_right] |

sys/dev/adb/adb_ktm.c

170

sc->sc_config[1] = reg;

sys/dev/adb/adb_ktm.c

236

int i, reg;

sys/dev/adb/adb_ktm.c

237

for (reg = 1; reg < 4; reg++) {

sys/dev/adb/adb_ktm.c

238

ktm_send_sync(sc, ADBTALK(addr, reg), 0, NULL);

sys/dev/adb/adb_ktm.c

239

printf("reg %d", reg);

sys/dev/adb/adb_ktm.c

416

int reg = sc->sc_left;

sys/dev/adb/adb_ktm.c

421

node.sysctl_data = ®

sys/dev/adb/adb_ktm.c

424

reg = *(int *)node.sysctl_data;

sys/dev/adb/adb_ktm.c

425

if ((reg != sc->sc_left) &&

sys/dev/adb/adb_ktm.c

426

(reg >= 0) &&

sys/dev/adb/adb_ktm.c

427

(reg < 4)) {

sys/dev/adb/adb_ktm.c

428

sc->sc_left = reg;

sys/dev/adb/adb_ktm.c

437

node.sysctl_data = ®

sys/dev/adb/adb_ktm.c

450

int reg = sc->sc_right;

sys/dev/adb/adb_ktm.c

455

node.sysctl_data = ®

sys/dev/adb/adb_ktm.c

458

reg = *(int *)node.sysctl_data;

sys/dev/adb/adb_ktm.c

459

if ((reg != sc->sc_right) &&

sys/dev/adb/adb_ktm.c

460

(reg >= 0) &&

sys/dev/adb/adb_ktm.c

461

(reg < 4)) {

sys/dev/adb/adb_ktm.c

462

sc->sc_right = reg;

sys/dev/adb/adb_ktm.c

471

node.sysctl_data = ®

sys/dev/adb/adb_ms.c

387

int i, reg;

sys/dev/adb/adb_ms.c

388

for (reg = 1; reg < 4; reg++) {

sys/dev/adb/adb_ms.c

389

adbms_send_sync(sc, ADBTALK(addr, reg), 0, NULL);

sys/dev/adb/adb_ms.c

390

printf("reg %d", reg);

sys/dev/adb/adbvar.h

37

#define ADBLISTEN(dev, reg) ((((u_int8_t)(dev) & 0x0f) << 4) | 0x08 | (reg))

sys/dev/adb/adbvar.h

38

#define ADBTALK(dev, reg) ((((u_int8_t)(dev) & 0x0f) << 4) | 0x0c | (reg))

sys/dev/ata/satapmp_subr.c

105

satapmp_read(struct ata_channel *chp, int port, int reg, uint32_t *value,

sys/dev/ata/satapmp_subr.c

111

ret = satapmp_read_8(chp, port, reg, &value64, xfer);

sys/dev/ata/satapmp_subr.c

120

satapmp_write_8(struct ata_channel *chp, int port, int reg, uint64_t value,

sys/dev/ata/satapmp_subr.c

128

KASSERT(reg < PMP_GSCR_NREGS);

sys/dev/ata/satapmp_subr.c

136

xfer->c_ata_c.r_features = reg;

sys/dev/ata/satapmp_subr.c

155

port, reg, xfer->c_ata_c.flags);

sys/dev/ata/satapmp_subr.c

162

port, reg, xfer->c_ata_c.r_error);

sys/dev/ata/satapmp_subr.c

173

satapmp_write(struct ata_channel *chp, int port, int reg, uint32_t value,

sys/dev/ata/satapmp_subr.c

176

return satapmp_write_8(chp, port, reg, value, xfer);

sys/dev/ata/satapmp_subr.c

51

satapmp_read_8(struct ata_channel *chp, int port, int reg, uint64_t *value,

sys/dev/ata/satapmp_subr.c

59

KASSERT(reg < PMP_GSCR_NREGS);

sys/dev/ata/satapmp_subr.c

67

xfer->c_ata_c.r_features = reg;

sys/dev/ata/satapmp_subr.c

82

port, reg, xfer->c_ata_c.flags);

sys/dev/ata/satapmp_subr.c

89

port, reg, xfer->c_ata_c.r_error);

sys/dev/audio/audio.c

5244

const audio_format2_t *hwfmt, const audio_filter_reg_t *reg)

sys/dev/audio/audio.c

5260

KASSERT(reg != NULL);

sys/dev/audio/audio.c

5400

} else if (reg->codec == NULL) {

sys/dev/audio/audio.c

5411

if (reg->codec) {

sys/dev/audio/audio.c

5412

mixer->codec = reg->codec;

sys/dev/audio/audio.c

5413

mixer->codecarg.context = reg->context;

sys/dev/bi/if_ni.c

204

failtest(struct ni_softc *sc, int reg, int mask, int test, const char *str)

sys/dev/bi/if_ni.c

210

} while (((NI_RREG(reg) & mask) != test) && --i);

sys/dev/bluetooth/bcsp.c

862

uint16_t reg = *crc;

sys/dev/bluetooth/bcsp.c

864

reg = (reg >> 4) ^ crctbl[(reg ^ d) & 0x000f];

sys/dev/bluetooth/bcsp.c

865

reg = (reg >> 4) ^ crctbl[(reg ^ (d >> 4)) & 0x000f];

sys/dev/bluetooth/bcsp.c

867

*crc = reg;

sys/dev/bluetooth/bth5.c

906

uint16_t reg = *crc;

sys/dev/bluetooth/bth5.c

908

reg = (reg >> 4) ^ crctbl[(reg ^ d) & 0x000f];

sys/dev/bluetooth/bth5.c

909

reg = (reg >> 4) ^ crctbl[(reg ^ (d >> 4)) & 0x000f];

sys/dev/bluetooth/bth5.c

911

*crc = reg;

sys/dev/cadence/if_cemac.c

684

cemac_mii_readreg(device_t self, int phy, int reg, uint16_t *val)

sys/dev/cadence/if_cemac.c

690

| ((reg << ETH_MAN_REGA_SHIFT) & ETH_MAN_REGA)

sys/dev/cadence/if_cemac.c

700

cemac_mii_writereg(device_t self, int phy, int reg, uint16_t val)

sys/dev/cadence/if_cemac.c

706

| ((reg << ETH_MAN_REGA_SHIFT) & ETH_MAN_REGA)

sys/dev/cadence/if_cemac.c

721

uint32_t reg;

sys/dev/cadence/if_cemac.c

727

reg = CEMAC_READ(ETH_CFG);

sys/dev/cadence/if_cemac.c

728

reg &= ~ETH_CFG_FD;

sys/dev/cadence/if_cemac.c

730

reg |= ETH_CFG_FD;

sys/dev/cadence/if_cemac.c

732

reg &= ~ETH_CFG_SPD;

sys/dev/cadence/if_cemac.c

734

reg &= ~GEM_CFG_GEN;

sys/dev/cadence/if_cemac.c

739

reg |= ETH_CFG_SPD;

sys/dev/cadence/if_cemac.c

742

reg |= ETH_CFG_SPD | GEM_CFG_GEN;

sys/dev/cadence/if_cemac.c

747

CEMAC_WRITE(ETH_CFG, reg);

sys/dev/cardbus/adv_cardbus.c

111

pcireg_t reg;

sys/dev/cardbus/adv_cardbus.c

182

reg = Cardbus_conf_read(ct, ca->ca_tag, PCI_COMMAND_STATUS_REG);

sys/dev/cardbus/adv_cardbus.c

183

reg &= ~(PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE);

sys/dev/cardbus/adv_cardbus.c

184

reg |= csc->sc_csr;

sys/dev/cardbus/adv_cardbus.c

185

Cardbus_conf_write(ct, ca->ca_tag, PCI_COMMAND_STATUS_REG, reg);

sys/dev/cardbus/adv_cardbus.c

191

reg = Cardbus_conf_read(ct, ca->ca_tag, PCI_BHLC_REG);

sys/dev/cardbus/adv_cardbus.c

192

if (PCI_LATTIMER(reg) < latency) {

sys/dev/cardbus/adv_cardbus.c

193

reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT);

sys/dev/cardbus/adv_cardbus.c

194

reg |= (latency << PCI_LATTIMER_SHIFT);

sys/dev/cardbus/adv_cardbus.c

195

Cardbus_conf_write(ct, ca->ca_tag, PCI_BHLC_REG, reg);

sys/dev/cardbus/ahc_cardbus.c

115

pcireg_t reg;

sys/dev/cardbus/ahc_cardbus.c

147

reg = Cardbus_conf_read(ct, ca->ca_tag, PCI_COMMAND_STATUS_REG);

sys/dev/cardbus/ahc_cardbus.c

148

reg &= ~(PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE);

sys/dev/cardbus/ahc_cardbus.c

149

reg |= csc->sc_csr;

sys/dev/cardbus/ahc_cardbus.c

150

Cardbus_conf_write(ct, ca->ca_tag, PCI_COMMAND_STATUS_REG, reg);

sys/dev/cardbus/ahc_cardbus.c

156

reg = Cardbus_conf_read(ct, ca->ca_tag, PCI_BHLC_REG);

sys/dev/cardbus/ahc_cardbus.c

157

if (PCI_LATTIMER(reg) < 0x20) {

sys/dev/cardbus/ahc_cardbus.c

158

reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT);

sys/dev/cardbus/ahc_cardbus.c

159

reg |= (0x20 << PCI_LATTIMER_SHIFT);

sys/dev/cardbus/ahc_cardbus.c

160

Cardbus_conf_write(ct, ca->ca_tag, PCI_BHLC_REG, reg);

sys/dev/cardbus/cardbus.c

1143

pcs->reg[off] = cardbus_conf_read(cc, cf, tag, (off * 4));

sys/dev/cardbus/cardbus.c

1155

if (val != pcs->reg[off])

sys/dev/cardbus/cardbus.c

1156

cardbus_conf_write(cc, cf,tag, (off * 4), pcs->reg[off]);

sys/dev/cardbus/cardbus.c

1227

pcireg_t reg;

sys/dev/cardbus/cardbus.c

1240

PCI_CAP_PWRMGMT, &off, &reg)) {

sys/dev/cardbus/cardbus.c

1243

priv->p_pm_cap = reg;

sys/dev/cardbus/cardbus.c

163

pcireg_t reg;

sys/dev/cardbus/cardbus.c

199

reg = CARDBUS_ROM_REG;

sys/dev/cardbus/cardbus.c

203

reg = CARDBUS_CIS_ASI_BAR(cardbus_space);

sys/dev/cardbus/cardbus.c

212

cardbus_conf_write(cc, cf, tag, reg, 0);

sys/dev/cardbus/cardbus.c

213

if (Cardbus_mapreg_map(ca->ca_ct, reg,

sys/dev/cardbus/cardbus.c

230

exrom = cardbus_conf_read(cc, cf, tag, reg);

sys/dev/cardbus/cardbus.c

231

cardbus_conf_write(cc, cf, tag, reg, exrom | 1);

sys/dev/cardbus/cardbus.c

257

exrom = cardbus_conf_read(cc, cf, tag, reg);

sys/dev/cardbus/cardbus.c

258

cardbus_conf_write(cc, cf, tag, reg, exrom & ~1);

sys/dev/cardbus/cardbus.c

294

cardbus_conf_write(cc, cf, tag, reg, 0);

sys/dev/cardbus/cardbus.c

296

Cardbus_mapreg_unmap(ca->ca_ct, reg, bar_tag, bar_memh,

sys/dev/cardbus/cardbus.c

884

pcireg_t reg;

sys/dev/cardbus/cardbus.c

887

reg = cardbus_conf_read(cc, cf, tag, PCI_COMMAND_STATUS_REG);

sys/dev/cardbus/cardbus.c

888

if (!(reg & PCI_STATUS_CAPLIST_SUPPORT))

sys/dev/cardbus/cardbus.c

898

reg = cardbus_conf_read(cc, cf, tag, ofs);

sys/dev/cardbus/cardbus.c

899

if (PCI_CAPLIST_CAP(reg) == capid) {

sys/dev/cardbus/cardbus.c

903

*value = reg;

sys/dev/cardbus/cardbus.c

906

ofs = PCI_CAPLIST_NEXT(reg);

sys/dev/cardbus/cardbus_map.c

103

address = cardbus_conf_read(cc, cf, tag, reg);

sys/dev/cardbus/cardbus_map.c

104

cardbus_conf_write(cc, cf, tag, reg, 0xffffffff);

sys/dev/cardbus/cardbus_map.c

105

mask = cardbus_conf_read(cc, cf, tag, reg);

sys/dev/cardbus/cardbus_map.c

106

cardbus_conf_write(cc, cf, tag, reg, address);

sys/dev/cardbus/cardbus_map.c

142

cardbus_mem_find(cardbus_chipset_tag_t cc, cardbus_function_tag_t cf, pcitag_t tag, int reg, pcireg_t type, bus_addr_t *basep, bus_size_t *sizep, int *flagsp)

sys/dev/cardbus/cardbus_map.c

147

if (reg != CARDBUS_ROM_REG &&

sys/dev/cardbus/cardbus_map.c

148

(reg < PCI_MAPREG_START || reg >= PCI_MAPREG_END || (reg & 3))) {

sys/dev/cardbus/cardbus_map.c

163

address = cardbus_conf_read(cc, cf, tag, reg);

sys/dev/cardbus/cardbus_map.c

164

cardbus_conf_write(cc, cf, tag, reg, 0xffffffff);

sys/dev/cardbus/cardbus_map.c

165

mask = cardbus_conf_read(cc, cf, tag, reg);

sys/dev/cardbus/cardbus_map.c

166

cardbus_conf_write(cc, cf, tag, reg, address);

sys/dev/cardbus/cardbus_map.c

169

if (reg != CARDBUS_ROM_REG) {

sys/dev/cardbus/cardbus_map.c

229

cardbus_mapreg_map(struct cardbus_softc *sc, int func, int reg, pcireg_t type, int busflags, bus_space_tag_t *tagp, bus_space_handle_t *handlep, bus_addr_t *basep, bus_size_t *sizep)

sys/dev/cardbus/cardbus_map.c

251

if (cardbus_io_find(cc, cf, tag, reg, type, &base, &size, &flags)) {

sys/dev/cardbus/cardbus_map.c

257

if (cardbus_mem_find(cc, cf, tag, reg, type, &base, &size, &flags)){

sys/dev/cardbus/cardbus_map.c

273

cardbus_conf_write(cc, cf, tag, reg, base);

sys/dev/cardbus/cardbus_map.c

311

cardbus_mapreg_unmap(struct cardbus_softc *sc, int func, int reg, bus_space_tag_t tag, bus_space_handle_t handle, bus_size_t size)

sys/dev/cardbus/cardbus_map.c

333

cardbus_conf_write(cc, cf, cardbustag, reg, 0);

sys/dev/cardbus/cardbus_map.c

74

int reg,

sys/dev/cardbus/cardbus_map.c

84

if (reg == CARDBUS_ROM_REG) {

sys/dev/cardbus/cardbus_map.c

88

if(reg < PCI_MAPREG_START || reg >= PCI_MAPREG_END || (reg & 3)) {

sys/dev/cardbus/cardbusvar.h

153

pcireg_t reg[16];

sys/dev/cardbus/cardbusvar.h

286

#define Cardbus_mapreg_map(ct, reg, type, busflags, tagp, handlep, basep, sizep) \

sys/dev/cardbus/cardbusvar.h

287

cardbus_mapreg_map((ct)->ct_sc, (ct->ct_func), (reg), (type),\

sys/dev/cardbus/cardbusvar.h

289

#define Cardbus_mapreg_unmap(ct, reg, tag, handle, size) \

sys/dev/cardbus/cardbusvar.h

290

cardbus_mapreg_unmap((ct)->ct_sc, (ct->ct_func), (reg), (tag), (handle), (size))

sys/dev/cardbus/com_cardbus.c

146

csc->cc_reg = cp->reg;

sys/dev/cardbus/com_cardbus.c

265

pcireg_t reg;

sys/dev/cardbus/com_cardbus.c

270

reg = Cardbus_conf_read(ct, csc->cc_tag, PCI_COMMAND_STATUS_REG);

sys/dev/cardbus/com_cardbus.c

271

reg &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE);

sys/dev/cardbus/com_cardbus.c

272

reg |= csc->cc_csr;

sys/dev/cardbus/com_cardbus.c

273

Cardbus_conf_write(ct, csc->cc_tag, PCI_COMMAND_STATUS_REG, reg);

sys/dev/cardbus/com_cardbus.c

279

reg = Cardbus_conf_read(ct, csc->cc_tag, PCI_BHLC_REG);

sys/dev/cardbus/com_cardbus.c

280

if (PCI_LATTIMER(reg) < 0x20) {

sys/dev/cardbus/com_cardbus.c

281

reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT);

sys/dev/cardbus/com_cardbus.c

282

reg |= (0x20 << PCI_LATTIMER_SHIFT);

sys/dev/cardbus/com_cardbus.c

283

Cardbus_conf_write(ct, csc->cc_tag, PCI_BHLC_REG, reg);

sys/dev/cardbus/com_cardbus.c

87

pcireg_t reg;

sys/dev/cardbus/if_ath_cardbus.c

243

pcireg_t reg;

sys/dev/cardbus/if_ath_cardbus.c

252

reg = Cardbus_conf_read(ct, csc->sc_tag,

sys/dev/cardbus/if_ath_cardbus.c

254

reg |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_MEM_ENABLE;

sys/dev/cardbus/if_ath_cardbus.c

255

Cardbus_conf_write(ct, csc->sc_tag, PCI_COMMAND_STATUS_REG, reg);

sys/dev/cardbus/if_athn_cardbus.c

222

pcireg_t reg;

sys/dev/cardbus/if_athn_cardbus.c

237

reg = Cardbus_conf_read(ct, csc->csc_tag, PCI_COMMAND_STATUS_REG);

sys/dev/cardbus/if_athn_cardbus.c

238

reg |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_MEM_ENABLE;

sys/dev/cardbus/if_athn_cardbus.c

239

Cardbus_conf_write(ct, csc->csc_tag, PCI_COMMAND_STATUS_REG, reg);

sys/dev/cardbus/if_athn_cardbus.c

246

reg = Cardbus_conf_read(ct, csc->csc_tag, 0x40);

sys/dev/cardbus/if_athn_cardbus.c

247

if (reg & 0xff00)

sys/dev/cardbus/if_athn_cardbus.c

248

Cardbus_conf_write(ct, csc->csc_tag, 0x40, reg & ~0xff00);

sys/dev/cardbus/if_athn_cardbus.c

251

reg = Cardbus_conf_read(ct, csc->csc_tag, PCI_BHLC_REG);

sys/dev/cardbus/if_athn_cardbus.c

252

reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT);

sys/dev/cardbus/if_athn_cardbus.c

253

reg |= 168 << PCI_LATTIMER_SHIFT;

sys/dev/cardbus/if_athn_cardbus.c

254

Cardbus_conf_write(ct, csc->csc_tag, PCI_BHLC_REG, reg);

sys/dev/cardbus/if_bwi_cardbus.c

119

pcireg_t reg;

sys/dev/cardbus/if_bwi_cardbus.c

152

reg = (sc->sc_conf_read)(sc, PCI_SUBSYS_ID_REG);

sys/dev/cardbus/if_bwi_cardbus.c

156

sc->sc_pci_subvid = PCI_VENDOR(reg);

sys/dev/cardbus/if_bwi_cardbus.c

157

sc->sc_pci_subdid = PCI_PRODUCT(reg);

sys/dev/cardbus/if_bwi_cardbus.c

204

pcireg_t reg;

sys/dev/cardbus/if_bwi_cardbus.c

210

reg = Cardbus_conf_read(ct, csc->csc_tag, PCI_COMMAND_STATUS_REG);

sys/dev/cardbus/if_bwi_cardbus.c

211

reg |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_MEM_ENABLE;

sys/dev/cardbus/if_bwi_cardbus.c

212

Cardbus_conf_write(ct, csc->csc_tag, PCI_COMMAND_STATUS_REG, reg);

sys/dev/cardbus/if_bwi_cardbus.c

261

bwi_cardbus_conf_write(void *sc, uint32_t reg, uint32_t val)

sys/dev/cardbus/if_bwi_cardbus.c

265

Cardbus_conf_write(csc->csc_ct, csc->csc_tag, reg, val);

sys/dev/cardbus/if_bwi_cardbus.c

269

bwi_cardbus_conf_read(void *sc, uint32_t reg)

sys/dev/cardbus/if_bwi_cardbus.c

273

return Cardbus_conf_read(csc->csc_ct, csc->csc_tag, reg);

sys/dev/cardbus/if_ex_cardbus.c

367

pcireg_t reg;

sys/dev/cardbus/if_ex_cardbus.c

386

reg = Cardbus_conf_read(ct, csc->sc_tag, PCI_COMMAND_STATUS_REG);

sys/dev/cardbus/if_ex_cardbus.c

387

reg |= csc->sc_csr;

sys/dev/cardbus/if_ex_cardbus.c

388

Cardbus_conf_write(ct, csc->sc_tag, PCI_COMMAND_STATUS_REG, reg);

sys/dev/cardbus/if_ex_cardbus.c

393

reg = Cardbus_conf_read(ct, csc->sc_tag, PCI_BHLC_REG);

sys/dev/cardbus/if_ex_cardbus.c

394

if (PCI_LATTIMER(reg) < 0x20) {

sys/dev/cardbus/if_ex_cardbus.c

397

PCI_LATTIMER(reg)));

sys/dev/cardbus/if_ex_cardbus.c

398

reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT);

sys/dev/cardbus/if_ex_cardbus.c

399

reg |= (0x20 << PCI_LATTIMER_SHIFT);

sys/dev/cardbus/if_ex_cardbus.c

400

Cardbus_conf_write(ct, csc->sc_tag, PCI_BHLC_REG, reg);

sys/dev/cardbus/if_fxp_cardbus.c

240

int rv, reg;

sys/dev/cardbus/if_fxp_cardbus.c

258

reg = PCI_BAR0;

sys/dev/cardbus/if_fxp_cardbus.c

260

reg = PCI_BAR1;

sys/dev/cardbus/if_fxp_cardbus.c

261

Cardbus_mapreg_unmap(ct, reg, sc->sc_st, sc->sc_sh, sc->sc_size);

sys/dev/cardbus/if_malo_cardbus.c

178

pcireg_t reg;

sys/dev/cardbus/if_malo_cardbus.c

189

reg = Cardbus_conf_read(ct, csc->sc_tag, PCI_COMMAND_STATUS_REG);

sys/dev/cardbus/if_malo_cardbus.c

190

reg |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_MEM_ENABLE;

sys/dev/cardbus/if_malo_cardbus.c

191

Cardbus_conf_write(ct, csc->sc_tag, PCI_COMMAND_STATUS_REG, reg);

sys/dev/cardbus/if_ral_cardbus.c

240

pcireg_t reg;

sys/dev/cardbus/if_ral_cardbus.c

246

reg = Cardbus_conf_read(ct, csc->sc_tag, PCI_COMMAND_STATUS_REG);

sys/dev/cardbus/if_ral_cardbus.c

247

reg |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_MEM_ENABLE;

sys/dev/cardbus/if_ral_cardbus.c

248

Cardbus_conf_write(ct, csc->sc_tag, PCI_COMMAND_STATUS_REG, reg);

sys/dev/cardbus/if_re_cardbus.c

243

pcireg_t reg, command;

sys/dev/cardbus/if_re_cardbus.c

286

reg = Cardbus_conf_read(ct, csc->sc_tag, PCI_COMMAND_STATUS_REG);

sys/dev/cardbus/if_re_cardbus.c

287

reg &= ~(PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE);

sys/dev/cardbus/if_re_cardbus.c

288

reg |= csc->sc_csr;

sys/dev/cardbus/if_re_cardbus.c

289

Cardbus_conf_write(ct, csc->sc_tag, PCI_COMMAND_STATUS_REG, reg);

sys/dev/cardbus/if_re_cardbus.c

295

reg = Cardbus_conf_read(ct, csc->sc_tag, PCI_BHLC_REG);

sys/dev/cardbus/if_re_cardbus.c

296

if (PCI_LATTIMER(reg) < 0x40) {

sys/dev/cardbus/if_re_cardbus.c

297

reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT);

sys/dev/cardbus/if_re_cardbus.c

298

reg |= (0x40 << PCI_LATTIMER_SHIFT);

sys/dev/cardbus/if_re_cardbus.c

299

Cardbus_conf_write(ct, csc->sc_tag, PCI_BHLC_REG, reg);

sys/dev/cardbus/if_rtk_cardbus.c

274

pcireg_t reg, command;

sys/dev/cardbus/if_rtk_cardbus.c

317

reg = Cardbus_conf_read(ct, csc->sc_tag, PCI_COMMAND_STATUS_REG);

sys/dev/cardbus/if_rtk_cardbus.c

318

reg &= ~(PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE);

sys/dev/cardbus/if_rtk_cardbus.c

319

reg |= csc->sc_csr;

sys/dev/cardbus/if_rtk_cardbus.c

320

Cardbus_conf_write(ct, csc->sc_tag, PCI_COMMAND_STATUS_REG, reg);

sys/dev/cardbus/if_rtk_cardbus.c

326

reg = Cardbus_conf_read(ct, csc->sc_tag, PCI_BHLC_REG);

sys/dev/cardbus/if_rtk_cardbus.c

327

if (PCI_LATTIMER(reg) < 0x20) {

sys/dev/cardbus/if_rtk_cardbus.c

328

reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT);

sys/dev/cardbus/if_rtk_cardbus.c

329

reg |= (0x20 << PCI_LATTIMER_SHIFT);

sys/dev/cardbus/if_rtk_cardbus.c

330

Cardbus_conf_write(ct, csc->sc_tag, PCI_BHLC_REG, reg);

sys/dev/cardbus/if_rtw_cardbus.c

185

u_int32_t reg;

sys/dev/cardbus/if_rtw_cardbus.c

187

reg = RTW_READ(regs, RTW_CONFIG3);

sys/dev/cardbus/if_rtw_cardbus.c

189

RTW_WRITE(regs, RTW_CONFIG3, reg | RTW_CONFIG3_FUNCREGEN);

sys/dev/cardbus/if_rtw_cardbus.c

191

RTW_WRITE(regs, RTW_CONFIG3, reg & ~RTW_CONFIG3_FUNCREGEN);

sys/dev/cardbus/if_tlp_cardbus.c

232

pcireg_t reg;

sys/dev/cardbus/if_tlp_cardbus.c

276

reg = Cardbus_conf_read(ct, csc->sc_tag, 0x80);

sys/dev/cardbus/if_tlp_cardbus.c

277

switch (reg) {

sys/dev/cardbus/if_tlp_cardbus.c

532

pcireg_t reg;

sys/dev/cardbus/if_tlp_cardbus.c

545

reg = Cardbus_conf_read(ct, csc->sc_tag, TULIP_PCI_CFDA);

sys/dev/cardbus/if_tlp_cardbus.c

546

if (reg & (CFDA_SLEEP|CFDA_SNOOZE))

sys/dev/cardbus/if_tlp_cardbus.c

548

reg & ~(CFDA_SLEEP|CFDA_SNOOZE));

sys/dev/cardbus/if_tlp_cardbus.c

562

reg = Cardbus_conf_read(ct, csc->sc_tag, PCI_COMMAND_STATUS_REG);

sys/dev/cardbus/if_tlp_cardbus.c

563

reg &= ~(PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE);

sys/dev/cardbus/if_tlp_cardbus.c

564

reg |= csc->sc_csr;

sys/dev/cardbus/if_tlp_cardbus.c

565

Cardbus_conf_write(ct, csc->sc_tag, PCI_COMMAND_STATUS_REG, reg);

sys/dev/cardbus/if_tlp_cardbus.c

571

reg = Cardbus_conf_read(ct, csc->sc_tag, PCI_BHLC_REG);

sys/dev/cardbus/if_tlp_cardbus.c

572

if (PCI_LATTIMER(reg) < 0x20) {

sys/dev/cardbus/if_tlp_cardbus.c

573

reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT);

sys/dev/cardbus/if_tlp_cardbus.c

574

reg |= (0x20 << PCI_LATTIMER_SHIFT);

sys/dev/cardbus/if_tlp_cardbus.c

575

Cardbus_conf_write(ct, csc->sc_tag, PCI_BHLC_REG, reg);

sys/dev/cardbus/if_tlp_cardbus.c

582

u_int32_t reg;

sys/dev/cardbus/if_tlp_cardbus.c

584

reg = TULIP_READ(sc, CSR_SIAGEN);

sys/dev/cardbus/if_tlp_cardbus.c

587

TULIP_WRITE(sc, CSR_SIAGEN, (reg & ~SIAGEN_MD) | SIAGEN_CWE |

sys/dev/cardbus/if_tlp_cardbus.c

589

TULIP_WRITE(sc, CSR_SIAGEN, (reg & ~SIAGEN_CWE) | SIAGEN_MD);

sys/dev/cardbus/njata_cardbus.c

130

pcireg_t reg;

sys/dev/cardbus/njata_cardbus.c

191

reg = Cardbus_conf_read(ct, ca->ca_tag, PCI_COMMAND_STATUS_REG);

sys/dev/cardbus/njata_cardbus.c

192

reg &= ~(PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE);

sys/dev/cardbus/njata_cardbus.c

193

reg |= csr;

sys/dev/cardbus/njata_cardbus.c

194

Cardbus_conf_write(ct, ca->ca_tag, PCI_COMMAND_STATUS_REG, reg);

sys/dev/cardbus/njata_cardbus.c

200

reg = Cardbus_conf_read(ct, ca->ca_tag, PCI_BHLC_REG);

sys/dev/cardbus/njata_cardbus.c

201

if (PCI_LATTIMER(reg) < latency) {

sys/dev/cardbus/njata_cardbus.c

202

reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT);

sys/dev/cardbus/njata_cardbus.c

203

reg |= (latency << PCI_LATTIMER_SHIFT);

sys/dev/cardbus/njata_cardbus.c

204

Cardbus_conf_write(ct, ca->ca_tag, PCI_BHLC_REG, reg);

sys/dev/cardbus/njs_cardbus.c

127

pcireg_t csr, reg;

sys/dev/cardbus/njs_cardbus.c

184

reg = Cardbus_conf_read(ct, ca->ca_tag, PCI_COMMAND_STATUS_REG);

sys/dev/cardbus/njs_cardbus.c

185

reg &= ~(PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE);

sys/dev/cardbus/njs_cardbus.c

186

reg |= csr;

sys/dev/cardbus/njs_cardbus.c

187

Cardbus_conf_write(ct, ca->ca_tag, PCI_COMMAND_STATUS_REG, reg);

sys/dev/cardbus/njs_cardbus.c

193

reg = Cardbus_conf_read(ct, ca->ca_tag, PCI_BHLC_REG);

sys/dev/cardbus/njs_cardbus.c

194

if (PCI_LATTIMER(reg) < latency) {

sys/dev/cardbus/njs_cardbus.c

195

reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT);

sys/dev/cardbus/njs_cardbus.c

196

reg |= (latency << PCI_LATTIMER_SHIFT);

sys/dev/cardbus/njs_cardbus.c

197

Cardbus_conf_write(ct, ca->ca_tag, PCI_BHLC_REG, reg);

sys/dev/cardbus/rbus_ppb.c

228

u_int32_t reg;

sys/dev/cardbus/rbus_ppb.c

371

reg = pci_conf_read(pc, pci_bus_tag[busnum],

sys/dev/cardbus/rbus_ppb.c

373

reg |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE;

sys/dev/cardbus/rbus_ppb.c

375

PCI_COMMAND_STATUS_REG, reg);

sys/dev/cardbus/rbus_ppb.c

407

reg = pci_conf_read(pc, pci_bus_tag[busnum],

sys/dev/cardbus/rbus_ppb.c

409

reg |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE;

sys/dev/cardbus/rbus_ppb.c

411

PCI_COMMAND_STATUS_REG, reg);

sys/dev/dec/mcclock.c

62

#define mc146818_write(sc, reg, datum) \

sys/dev/dec/mcclock.c

63

(*(sc)->sc_busfns->mc_bf_write)(sc, reg, datum)

sys/dev/dec/mcclock.c

64

#define mc146818_read(sc, reg) \

sys/dev/dec/mcclock.c

65

(*(sc)->sc_busfns->mc_bf_read)(sc, reg)

sys/dev/dec/mcclock_pad32.c

70

mcclock_pad32_write(struct mcclock_softc *dev, u_int reg, u_int datum)

sys/dev/dec/mcclock_pad32.c

74

sc->sc_dp[reg].datum = datum;

sys/dev/dec/mcclock_pad32.c

78

mcclock_pad32_read(struct mcclock_softc *dev, u_int reg)

sys/dev/dec/mcclock_pad32.c

82

return (sc->sc_dp[reg].datum);

sys/dev/ebus/ebusreg.h

79

#define EBUS_ADDR_FROM_REG(reg) BUS_ADDR((reg)->hi, (reg)->lo)

sys/dev/fdt/cdns3_fdt.c

53

#define OTGRD4(sc, reg) \

sys/dev/fdt/cdns3_fdt.c

54

bus_space_read_4((sc)->sc_otg_bst, (sc)->sc_otg_bsh, (reg))

sys/dev/fdt/cdns3_fdt.c

55

#define OTGWR4(sc, reg, val) \

sys/dev/fdt/cdns3_fdt.c

56

bus_space_write_4((sc)->sc_otg_bst, (sc)->sc_otg_bsh, (reg), (val))

sys/dev/fdt/dwc3_fdt.c

90

#define RD4(sc, reg) \

sys/dev/fdt/dwc3_fdt.c

91

bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg))

sys/dev/fdt/dwc3_fdt.c

92

#define WR4(sc, reg, val) \

sys/dev/fdt/dwc3_fdt.c

93

bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))

sys/dev/fdt/dwc3_fdt.c

94

#define SET4(sc, reg, mask) \

sys/dev/fdt/dwc3_fdt.c

95

WR4((sc), (reg), RD4((sc), (reg)) | (mask))

sys/dev/fdt/dwc3_fdt.c

96

#define CLR4(sc, reg, mask) \

sys/dev/fdt/dwc3_fdt.c

97

WR4((sc), (reg), RD4((sc), (reg)) & ~(mask))

sys/dev/fdt/fdt_regulator.c

117

fdtbus_regulator_release(struct fdtbus_regulator *reg)

sys/dev/fdt/fdt_regulator.c

119

struct fdtbus_regulator_controller *rc = REGULATOR_TO_RC(reg);

sys/dev/fdt/fdt_regulator.c

125

fdtbus_regulator_enable(struct fdtbus_regulator *reg)

sys/dev/fdt/fdt_regulator.c

127

struct fdtbus_regulator_controller *rc = REGULATOR_TO_RC(reg);

sys/dev/fdt/fdt_regulator.c

141

fdtbus_regulator_disable(struct fdtbus_regulator *reg)

sys/dev/fdt/fdt_regulator.c

143

struct fdtbus_regulator_controller *rc = REGULATOR_TO_RC(reg);

sys/dev/fdt/fdt_regulator.c

152

fdtbus_regulator_set_voltage(struct fdtbus_regulator *reg, u_int min_uvol,

sys/dev/fdt/fdt_regulator.c

155

struct fdtbus_regulator_controller *rc = REGULATOR_TO_RC(reg);

sys/dev/fdt/fdt_regulator.c

164

fdtbus_regulator_get_voltage(struct fdtbus_regulator *reg, u_int *puvol)

sys/dev/fdt/fdt_regulator.c

166

struct fdtbus_regulator_controller *rc = REGULATOR_TO_RC(reg);

sys/dev/fdt/fdt_regulator.c

175

fdtbus_regulator_supports_voltage(struct fdtbus_regulator *reg, u_int min_uvol,

sys/dev/fdt/fdt_regulator.c

178

struct fdtbus_regulator_controller *rc = REGULATOR_TO_RC(reg);

sys/dev/fdt/syscon.c

81

syscon_generic_read_4(void *priv, bus_size_t reg)

sys/dev/fdt/syscon.c

87

return bus_space_read_4(sc->sc_bst, sc->sc_bsh, reg);

sys/dev/fdt/syscon.c

91

syscon_generic_write_4(void *priv, bus_size_t reg, uint32_t val)

sys/dev/fdt/syscon.c

97

bus_space_write_4(sc->sc_bst, sc->sc_bsh, reg, val);

sys/dev/goldfish/gfrtc.c

58

#define GOLDFISH_RTC_READ(sc, reg) \

sys/dev/goldfish/gfrtc.c

59

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/dev/goldfish/gfrtc.c

60

#define GOLDFISH_RTC_WRITE(sc, reg, val) \

sys/dev/goldfish/gfrtc.c

61

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/dev/i2c/ac100.c

201

ac100_read(struct ac100_softc *sc, uint8_t reg, uint16_t *val)

sys/dev/i2c/ac100.c

203

return iic_smbus_read_word(sc->sc_i2c, sc->sc_addr, reg, val, 0);

sys/dev/i2c/ac100.c

207

ac100_write(struct ac100_softc *sc, uint8_t reg, uint16_t val)

sys/dev/i2c/ac100.c

209

return iic_smbus_write_word(sc->sc_i2c, sc->sc_addr, reg, val, 0);

sys/dev/i2c/act8846.c

186

act8846_read(struct act8846_softc *sc, uint8_t reg, uint8_t *val)

sys/dev/i2c/act8846.c

188

return iic_smbus_read_byte(sc->sc_i2c, sc->sc_addr, reg, val, 0);

sys/dev/i2c/act8846.c

192

act8846_write(struct act8846_softc *sc, uint8_t reg, uint8_t val)

sys/dev/i2c/act8846.c

194

return iic_smbus_write_byte(sc->sc_i2c, sc->sc_addr, reg, val, 0);

sys/dev/i2c/adadc.c

158

int len, idx = 0, reg = 0;

sys/dev/i2c/adadc.c

171

switch (reg) {

sys/dev/i2c/adadc.c

190

s->private = reg;

sys/dev/i2c/adadc.c

195

reg++;

sys/dev/i2c/adadc.c

200

int reg = 0;

sys/dev/i2c/adadc.c

201

OF_getprop(ch, "reg", &reg, sizeof(reg));

sys/dev/i2c/adadc.c

208

switch (reg) {

sys/dev/i2c/adadc.c

227

s->private = reg;

sys/dev/i2c/adm1026.c

197

adm1026_read_reg(struct adm1026_softc *sc, uint8_t reg, uint8_t *val)

sys/dev/i2c/adm1026.c

199

return adm1026_read_reg_int(sc->sc_tag, sc->sc_address, reg, val);

sys/dev/i2c/adm1026.c

230

uint8_t reg, val;

sys/dev/i2c/adm1026.c

234

reg = ADM1026_ID;

sys/dev/i2c/adm1026.c

235

err = adm1026_read_reg_int(tag, addr, reg, &val);

sys/dev/i2c/adm1026.c

242

reg = ADM1026_REV;

sys/dev/i2c/adm1026.c

243

err = adm1026_read_reg_int(tag, addr, reg, rev);

sys/dev/i2c/adm1026.c

259

uint8_t reg, val, rev, fan_div2, fan_mask;

sys/dev/i2c/adm1026.c

296

reg = ADM1026_CONF1;

sys/dev/i2c/adm1026.c

297

if (adm1026_read_reg(sc, reg, &val) != 0) {

sys/dev/i2c/adm1026.c

394

uint8_t reg, val;

sys/dev/i2c/adm1026.c

396

reg = ADM1026_CONF1;

sys/dev/i2c/adm1026.c

398

if (adm1026_read_reg(sc, reg, &val) != 0) {

sys/dev/i2c/adm1026.c

407

if (adm1026_write_reg(sc, reg, val) != 0) {

sys/dev/i2c/adm1026.c

419

uint8_t reg, val;

sys/dev/i2c/adm1026.c

421

reg = ADM1026_CONF1;

sys/dev/i2c/adm1026.c

422

if (adm1026_read_reg(sc, reg, &val) != 0) {

sys/dev/i2c/adm1026.c

428

if (adm1026_write_reg(sc, reg, val) != 0) {

sys/dev/i2c/adm1026.c

439

uint8_t reg, div1, div2, val;

sys/dev/i2c/adm1026.c

442

reg = ADM1026_CONF2;

sys/dev/i2c/adm1026.c

443

if (adm1026_read_reg(sc, reg, &sc->sc_cfg[1]) != 0) {

sys/dev/i2c/adm1026.c

447

reg = ADM1026_FAN_DIV1;

sys/dev/i2c/adm1026.c

448

if (adm1026_read_reg(sc, reg, &div1) != 0) {

sys/dev/i2c/adm1026.c

457

reg = ADM1026_FAN_DIV2;

sys/dev/i2c/adm1026.c

458

if (adm1026_read_reg(sc, reg, &div2) != 0) {

sys/dev/i2c/adm1026.c

489

reg = ADM1026_FAN_HIGH(i);

sys/dev/i2c/adm1026.c

490

if (adm1026_read_reg(sc, reg, &val) != 0) {

sys/dev/i2c/adm1026.c

521

uint8_t reg, val;

sys/dev/i2c/adm1026.c

532

reg = adm1026_temps_table[i].t_reg;

sys/dev/i2c/adm1026.c

533

if (adm1026_read_reg(sc, reg, &val) != 0) {

sys/dev/i2c/adm1026.c

540

reg = adm1026_temps_table[i].h_reg;

sys/dev/i2c/adm1026.c

541

if (adm1026_read_reg(sc, reg, &val) != 0) {

sys/dev/i2c/adm1026.c

548

reg = adm1026_temps_table[i].l_reg;

sys/dev/i2c/adm1026.c

549

if (adm1026_read_reg(sc, reg, &val) != 0) {

sys/dev/i2c/adm1026.c

581

uint8_t reg, val;

sys/dev/i2c/adm1026.c

592

reg = adm1026_volts_table[i].h_reg;

sys/dev/i2c/adm1026.c

593

if (adm1026_read_reg(sc, reg, &val) != 0) {

sys/dev/i2c/adm1026.c

600

reg = adm1026_volts_table[i].l_reg;

sys/dev/i2c/adm1026.c

601

if (adm1026_read_reg(sc, reg, &val) != 0) {

sys/dev/i2c/adm1026.c

644

uint8_t reg, val;

sys/dev/i2c/adm1026.c

646

reg = ADM1026_FAN_VAL(fan);

sys/dev/i2c/adm1026.c

647

if (adm1026_read_reg(sc, reg, &val) != 0) {

sys/dev/i2c/adm1026.c

662

uint8_t reg, val;

sys/dev/i2c/adm1026.c

664

reg = adm1026_temps_table[temp].v_reg;

sys/dev/i2c/adm1026.c

665

if (adm1026_read_reg(sc, reg, &val) != 0) {

sys/dev/i2c/adm1026.c

678

uint8_t reg, val;

sys/dev/i2c/adm1026.c

680

reg = adm1026_volts_table[volt].v_reg;

sys/dev/i2c/adm1026.c

681

if (adm1026_read_reg(sc, reg, &val) != 0) {

sys/dev/i2c/adm1026.c

711

uint8_t reg, val;

sys/dev/i2c/adm1026.c

716

reg = ADM1026_FAN_HIGH(fan);

sys/dev/i2c/adm1026.c

717

if (adm1026_read_reg(sc, reg, &val) != 0)

sys/dev/i2c/adm1026.c

730

uint8_t reg, val;

sys/dev/i2c/adm1026.c

734

reg = adm1026_temps_table[temp].t_reg;

sys/dev/i2c/adm1026.c

735

if (adm1026_read_reg(sc, reg, &val) != 0)

sys/dev/i2c/adm1026.c

740

reg = adm1026_temps_table[temp].h_reg;

sys/dev/i2c/adm1026.c

741

if (adm1026_read_reg(sc, reg, &val) != 0)

sys/dev/i2c/adm1026.c

746

reg = adm1026_temps_table[temp].l_reg;

sys/dev/i2c/adm1026.c

747

if (adm1026_read_reg(sc, reg, &val) != 0)

sys/dev/i2c/adm1026.c

758

uint8_t reg, val;

sys/dev/i2c/adm1026.c

762

reg = adm1026_volts_table[volt].h_reg;

sys/dev/i2c/adm1026.c

763

if (adm1026_read_reg(sc, reg, &val) != 0)

sys/dev/i2c/adm1026.c

768

reg = adm1026_volts_table[volt].l_reg;

sys/dev/i2c/adm1026.c

769

if (adm1026_read_reg(sc, reg, &val) != 0)

sys/dev/i2c/adm1026.c

794

uint8_t reg, val;

sys/dev/i2c/adm1026.c

809

reg = ADM1026_FAN_HIGH(fan);

sys/dev/i2c/adm1026.c

810

adm1026_write_reg(sc, reg, val);

sys/dev/i2c/adm1026.c

819

uint8_t reg, val;

sys/dev/i2c/adm1026.c

830

reg = adm1026_temps_table[temp].h_reg;

sys/dev/i2c/adm1026.c

831

adm1026_write_reg(sc, reg, val);

sys/dev/i2c/adm1026.c

840

reg = adm1026_temps_table[temp].t_reg;

sys/dev/i2c/adm1026.c

841

adm1026_write_reg(sc, reg, val);

sys/dev/i2c/adm1026.c

850

reg = adm1026_temps_table[temp].l_reg;

sys/dev/i2c/adm1026.c

851

adm1026_write_reg(sc, reg, val);

sys/dev/i2c/adm1026.c

860

uint8_t reg, val;

sys/dev/i2c/adm1026.c

871

reg = adm1026_volts_table[volt].h_reg;

sys/dev/i2c/adm1026.c

872

adm1026_write_reg(sc, reg, val);

sys/dev/i2c/adm1026.c

881

reg = adm1026_volts_table[volt].l_reg;

sys/dev/i2c/adm1026.c

882

adm1026_write_reg(sc, reg, val);

sys/dev/i2c/adm1026.c

887

adm1026_read_reg_int(i2c_tag_t tag, i2c_addr_t addr, uint8_t reg, uint8_t *val)

sys/dev/i2c/adm1026.c

893

err = iic_exec(tag, I2C_OP_READ_WITH_STOP, addr, &reg, 1, val, 1, 0);

sys/dev/i2c/adm1026.c

899

adm1026_write_reg(struct adm1026_softc *sc, uint8_t reg, uint8_t val)

sys/dev/i2c/adm1026.c

906

&reg, 1, &val, 1, 0);

sys/dev/i2c/adt7462.c

1017

uint8_t reg, lsb, msb;

sys/dev/i2c/adt7462.c

1020

reg = ADT7462_TACH_VAL_LSB(fan);

sys/dev/i2c/adt7462.c

1021

if (adt7462_read_reg(sc->sc_tag, sc->sc_address, reg, &lsb) != 0) {

sys/dev/i2c/adt7462.c

1025

reg += 1; /* MSB register is always LSB register + 1 */

sys/dev/i2c/adt7462.c

1026

if (adt7462_read_reg(sc->sc_tag, sc->sc_address, reg, &msb) != 0) {

sys/dev/i2c/adt7462.c

1042

uint8_t reg, lsb, msb;

sys/dev/i2c/adt7462.c

1045

reg = ADT7462_TEMP_LSB(temp);

sys/dev/i2c/adt7462.c

1046

if (adt7462_read_reg(sc->sc_tag, sc->sc_address, reg, &lsb) != 0) {

sys/dev/i2c/adt7462.c

1050

reg += 1; /* MSB register is always LSB register + 1 */

sys/dev/i2c/adt7462.c

1051

if (adt7462_read_reg(sc->sc_tag, sc->sc_address, reg, &msb) != 0) {

sys/dev/i2c/adt7462.c

1064

uint8_t reg, val;

sys/dev/i2c/adt7462.c

1066

reg = adt7462_volts_table[volt].v_reg;

sys/dev/i2c/adt7462.c

1067

if (adt7462_read_reg(sc->sc_tag, sc->sc_address, reg, &val) != 0) {

sys/dev/i2c/adt7462.c

1078

uint8_t reg, val;

sys/dev/i2c/adt7462.c

1082

reg = ADT7462_FAN_STAT_H;

sys/dev/i2c/adt7462.c

1083

if (adt7462_read_reg(sc->sc_tag, sc->sc_address, reg, &val) != 0) {

sys/dev/i2c/adt7462.c

1130

uint8_t reg, val;

sys/dev/i2c/adt7462.c

1135

reg = ADT7462_TACH_LIMIT(fan);

sys/dev/i2c/adt7462.c

1136

if (adt7462_read_reg(sc->sc_tag, sc->sc_address, reg, &val) != 0)

sys/dev/i2c/adt7462.c

1149

uint8_t reg, val;

sys/dev/i2c/adt7462.c

1157

reg = ADT7462_TEMP_THERM1(temp);

sys/dev/i2c/adt7462.c

1159

reg = ADT7462_TEMP_THERM2(temp);

sys/dev/i2c/adt7462.c

1160

if (adt7462_read_reg(sc->sc_tag, sc->sc_address, reg, &val) != 0)

sys/dev/i2c/adt7462.c

1165

reg = ADT7462_TEMP_HIGH(temp);

sys/dev/i2c/adt7462.c

1166

if (adt7462_read_reg(sc->sc_tag, sc->sc_address, reg, &val) != 0)

sys/dev/i2c/adt7462.c

1171

reg = ADT7462_TEMP_LOW(temp);

sys/dev/i2c/adt7462.c

1172

if (adt7462_read_reg(sc->sc_tag, sc->sc_address, reg, &val) != 0)

sys/dev/i2c/adt7462.c

1183

uint8_t reg, val;

sys/dev/i2c/adt7462.c

1187

reg = adt7462_volts_table[volt].h_reg;

sys/dev/i2c/adt7462.c

1188

if (adt7462_read_reg(sc->sc_tag, sc->sc_address, reg, &val) != 0)

sys/dev/i2c/adt7462.c

1193

reg = adt7462_volts_table[volt].l_reg;

sys/dev/i2c/adt7462.c

1194

if (adt7462_read_reg(sc->sc_tag, sc->sc_address, reg, &val) != 0)

sys/dev/i2c/adt7462.c

1219

uint8_t reg, val;

sys/dev/i2c/adt7462.c

1233

reg = ADT7462_TACH_LIMIT(fan);

sys/dev/i2c/adt7462.c

1234

adt7462_write_reg(sc->sc_tag, sc->sc_address, reg, val);

sys/dev/i2c/adt7462.c

1243

uint8_t reg, val;

sys/dev/i2c/adt7462.c

1259

reg = ADT7462_TEMP_THERM1(temp);

sys/dev/i2c/adt7462.c

1264

reg = ADT7462_TEMP_THERM2(temp);

sys/dev/i2c/adt7462.c

1269

adt7462_write_reg(sc->sc_tag, sc->sc_address, reg, val);

sys/dev/i2c/adt7462.c

1278

reg = ADT7462_TEMP_HIGH(temp);

sys/dev/i2c/adt7462.c

1279

adt7462_write_reg(sc->sc_tag, sc->sc_address, reg, val);

sys/dev/i2c/adt7462.c

1288

reg = ADT7462_TEMP_LOW(temp);

sys/dev/i2c/adt7462.c

1289

adt7462_write_reg(sc->sc_tag, sc->sc_address, reg, val);

sys/dev/i2c/adt7462.c

1298

uint8_t reg, val;

sys/dev/i2c/adt7462.c

1310

reg = adt7462_volts_table[volt].h_reg;

sys/dev/i2c/adt7462.c

1311

adt7462_write_reg(sc->sc_tag, sc->sc_address, reg, val);

sys/dev/i2c/adt7462.c

1321

reg = adt7462_volts_table[volt].l_reg;

sys/dev/i2c/adt7462.c

1322

adt7462_write_reg(sc->sc_tag, sc->sc_address, reg, val);

sys/dev/i2c/adt7462.c

1331

uint8_t reg, val;

sys/dev/i2c/adt7462.c

1336

reg = ADT7462_PWM_DUTY(val);

sys/dev/i2c/adt7462.c

1338

if (adt7462_read_reg(sc->sc_tag, sc->sc_address, reg, &val) != 0) {

sys/dev/i2c/adt7462.c

1354

if (adt7462_write_reg(sc->sc_tag, sc->sc_address, reg, val) != 0) {

sys/dev/i2c/adt7462.c

1367

uint8_t reg, val, old, new;

sys/dev/i2c/adt7462.c

1372

reg = ADT7462_HYST_TRANGE(val);

sys/dev/i2c/adt7462.c

1374

if (adt7462_read_reg(sc->sc_tag, sc->sc_address, reg, &val) != 0) {

sys/dev/i2c/adt7462.c

1397

if (adt7462_write_reg(sc->sc_tag, sc->sc_address, reg, new) != 0) {

sys/dev/i2c/adt7462.c

1409

uint8_t reg, val;

sys/dev/i2c/adt7462.c

1414

reg = ADT7462_TMIN(temp);

sys/dev/i2c/adt7462.c

1416

if (adt7462_read_reg(sc->sc_tag, sc->sc_address, reg, &val) != 0) {

sys/dev/i2c/adt7462.c

1440

if (adt7462_write_reg(sc->sc_tag, sc->sc_address, reg, val) != 0) {

sys/dev/i2c/adt7462.c

1452

uint8_t reg, val, mreg, mval;

sys/dev/i2c/adt7462.c

1457

reg = ADT7462_OP_POINT(temp);

sys/dev/i2c/adt7462.c

1459

if (adt7462_read_reg(sc->sc_tag, sc->sc_address, reg, &val) != 0) {

sys/dev/i2c/adt7462.c

1490

if (adt7462_write_reg(sc->sc_tag, sc->sc_address, reg, val) != 0) {

sys/dev/i2c/adt7462.c

1498

adt7462_read_reg(i2c_tag_t tag, i2c_addr_t addr, uint8_t reg, uint8_t *val)

sys/dev/i2c/adt7462.c

1504

err = iic_exec(tag, I2C_OP_READ_WITH_STOP, addr, &reg, 1, val, 1, 0);

sys/dev/i2c/adt7462.c

1510

adt7462_write_reg(i2c_tag_t tag, i2c_addr_t addr, uint8_t reg, uint8_t val)

sys/dev/i2c/adt7462.c

1516

err = iic_exec(tag, I2C_OP_WRITE_WITH_STOP, addr, &reg, 1, &val, 1, 0);

sys/dev/i2c/adt7462.c

230

uint8_t reg, val;

sys/dev/i2c/adt7462.c

234

reg = ADT7462_DEV_ID;

sys/dev/i2c/adt7462.c

235

err = adt7462_read_reg(tag, addr, reg, &val);

sys/dev/i2c/adt7462.c

242

reg = ADT7462_COMP_ID;

sys/dev/i2c/adt7462.c

243

err = adt7462_read_reg(tag, addr, reg, &val);

sys/dev/i2c/adt7462.c

250

reg = ADT7462_REV_ID;

sys/dev/i2c/adt7462.c

251

err = adt7462_read_reg(tag, addr, reg, rev);

sys/dev/i2c/adt7462.c

267

uint8_t reg, rev, val, pin_cfg[4];

sys/dev/i2c/adt7462.c

285

reg = ADT7462_PIN_CONF1;

sys/dev/i2c/adt7462.c

286

if (adt7462_read_reg(sc->sc_tag, sc->sc_address, reg, &val) != 0) {

sys/dev/i2c/adt7462.c

291

reg = ADT7462_PIN_CONF2;

sys/dev/i2c/adt7462.c

292

if (adt7462_read_reg(sc->sc_tag, sc->sc_address, reg, &val) != 0) {

sys/dev/i2c/adt7462.c

297

reg = ADT7462_PIN_CONF3;

sys/dev/i2c/adt7462.c

298

if (adt7462_read_reg(sc->sc_tag, sc->sc_address, reg, &val) != 0) {

sys/dev/i2c/adt7462.c

303

reg = ADT7462_PIN_CONF4;

sys/dev/i2c/adt7462.c

304

if (adt7462_read_reg(sc->sc_tag, sc->sc_address, reg, &val) != 0) {

sys/dev/i2c/adt7462.c

406

uint8_t reg, val;

sys/dev/i2c/adt7462.c

412

reg = ADT7462_CONF1;

sys/dev/i2c/adt7462.c

413

if (adt7462_read_reg(sc->sc_tag, sc->sc_address, reg, &val) != 0) {

sys/dev/i2c/adt7462.c

421

reg, val) != 0) {

sys/dev/i2c/adt7462.c

439

uint8_t reg, val;

sys/dev/i2c/adt7462.c

441

reg = ADT7462_CONF1;

sys/dev/i2c/adt7462.c

442

if (adt7462_read_reg(sc->sc_tag, sc->sc_address, reg, &val) != 0) {

sys/dev/i2c/adt7462.c

448

if (adt7462_write_reg(sc->sc_tag, sc->sc_address, reg, val) != 0) {

sys/dev/i2c/adt7462.c

459

uint8_t reg, val;

sys/dev/i2c/adt7462.c

471

reg = ADT7462_TACH_LIMIT(i);

sys/dev/i2c/adt7462.c

473

reg, &val) != 0) {

sys/dev/i2c/adt7462.c

503

uint8_t reg, val, val2;

sys/dev/i2c/adt7462.c

513

reg = ADT7462_TEMP_THERM1(i);

sys/dev/i2c/adt7462.c

515

reg, &val) != 0) {

sys/dev/i2c/adt7462.c

521

reg = ADT7462_TEMP_THERM2(i);

sys/dev/i2c/adt7462.c

523

reg, &val2) != 0) {

sys/dev/i2c/adt7462.c

535

reg = ADT7462_TEMP_HIGH(i);

sys/dev/i2c/adt7462.c

537

reg, &val) != 0) {

sys/dev/i2c/adt7462.c

544

reg = ADT7462_TEMP_LOW(i);

sys/dev/i2c/adt7462.c

546

reg, &val) != 0) {

sys/dev/i2c/adt7462.c

578

uint8_t reg, val;

sys/dev/i2c/adt7462.c

713

reg = adt7462_volts_table[i].h_reg;

sys/dev/i2c/adt7462.c

715

reg, &val) != 0) {

sys/dev/i2c/adt7462.c

722

reg = adt7462_volts_table[i].l_reg;

sys/dev/i2c/adt7462.c

724

reg, &val) != 0) {

sys/dev/i2c/adt7462.c

779

uint8_t reg, val, val2, rw;

sys/dev/i2c/adt7462.c

818

reg = ADT7462_PWM_CFG(i);

sys/dev/i2c/adt7462.c

820

reg, &val) != 0) {

sys/dev/i2c/adt7462.c

879

reg = ADT7462_TMIN_CAL1;

sys/dev/i2c/adt7462.c

881

reg, &val2) != 0) {

sys/dev/i2c/aht20.c

196

uint8_t reg = AHT20_GET_STATUS;

sys/dev/i2c/aht20.c

200

error = aht20_cmd(tag, addr, &reg, 1, buf, 1, 10);

sys/dev/i2c/am2315.c

123

uint8_t reg = dir == AM2315_READ_REGISTERS ?

sys/dev/i2c/am2315.c

126

return iic_exec(tag, reg, addr, command,

sys/dev/i2c/anxedp.c

101

anxedp_read(struct anxedp_softc *sc, u_int off, uint8_t reg)

sys/dev/i2c/anxedp.c

105

if (iic_smbus_read_byte(sc->sc_i2c, sc->sc_addr + off, reg, &val, 0) != 0)

sys/dev/i2c/anxedp.c

112

anxedp_write(struct anxedp_softc *sc, u_int off, uint8_t reg, uint8_t val)

sys/dev/i2c/anxedp.c

114

(void)iic_smbus_write_byte(sc->sc_i2c, sc->sc_addr + off, reg, val, 0);

sys/dev/i2c/as3722.c

236

uint8_t reg, id1;

sys/dev/i2c/as3722.c

246

reg = AS3722_ASIC_ID1_REG;

sys/dev/i2c/as3722.c

248

&reg, 1, &id1, 1, 0);

sys/dev/i2c/as3722.c

342

as3722_read(struct as3722_softc *sc, uint8_t reg, uint8_t *val, int flags)

sys/dev/i2c/as3722.c

345

&reg, 1, val, 1, flags);

sys/dev/i2c/as3722.c

349

as3722_write(struct as3722_softc *sc, uint8_t reg, uint8_t val, int flags)

sys/dev/i2c/as3722.c

351

uint8_t buf[2] = { reg, val };

sys/dev/i2c/as3722.c

357

as3722_set_clear(struct as3722_softc *sc, uint8_t reg, uint8_t set,

sys/dev/i2c/as3722.c

363

error = as3722_read(sc, reg, &old, flags);

sys/dev/i2c/as3722.c

369

return as3722_write(sc, reg, new, flags);

sys/dev/i2c/au8522.c

325

au8522_write_1(au, modtab[n].reg, modtab[n].val);

sys/dev/i2c/au8522.c

66

au8522_read_1(struct au8522 *au, uint16_t reg, uint8_t *val)

sys/dev/i2c/au8522.c

71

cmd[0] = (reg >> 8) | 0x40;

sys/dev/i2c/au8522.c

72

cmd[1] = reg & 0xff;

sys/dev/i2c/au8522.c

82

au8522_write_1(struct au8522 *au, uint16_t reg, uint8_t val)

sys/dev/i2c/au8522.c

86

data[0] = (reg >> 8) | 0x80;

sys/dev/i2c/au8522.c

87

data[1] = reg & 0xff;

sys/dev/i2c/au8522mod.h

33

uint16_t reg;

sys/dev/i2c/axp20x.c

420

axp20x_sensors_refresh_volt(struct axp20x_softc *sc, int reg,

sys/dev/i2c/axp20x.c

426

error = axp20x_read(sc, reg, buf, sizeof(buf));

sys/dev/i2c/axp20x.c

437

axp20x_sensors_refresh_amp(struct axp20x_softc *sc, int reg,

sys/dev/i2c/axp20x.c

443

error = axp20x_read(sc, reg, buf, sizeof(buf));

sys/dev/i2c/axp20x.c

560

axp20x_read(struct axp20x_softc *sc, uint8_t reg, uint8_t *val, size_t len)

sys/dev/i2c/axp20x.c

567

&reg, 1, val, len, 0);

sys/dev/i2c/axp20x.c

576

axp20x_write(struct axp20x_softc *sc, uint8_t reg, uint8_t *val, size_t len)

sys/dev/i2c/axp20x.c

583

&reg, 1, val, len, 0);

sys/dev/i2c/axp20x.c

596

uint8_t reg;

sys/dev/i2c/axp20x.c

605

reg = value & AXP_DCDC2_VOLT_MASK;

sys/dev/i2c/axp20x.c

606

ret = axp20x_write(sc, AXP_DCDC2, &reg, 1);

sys/dev/i2c/axp20x.c

609

if (axp20x_read(sc, AXP_DCDC2, &reg, 1) == 0) {

sys/dev/i2c/axp20x.c

612

(int)(700 + (reg & AXP_DCDC2_VOLT_MASK) * 25));

sys/dev/i2c/axp20x.c

620

reg = value & AXP_DCDC3_VOLT_MASK;

sys/dev/i2c/axp20x.c

621

ret = axp20x_write(sc, AXP_DCDC3, &reg, 1);

sys/dev/i2c/axp20x.c

624

if (axp20x_read(sc, AXP_DCDC3, &reg, 1) == 0) {

sys/dev/i2c/axp20x.c

627

(int)(700 + (reg & AXP_DCDC3_VOLT_MASK) * 25));

sys/dev/i2c/axp20x.c

640

uint8_t reg;

sys/dev/i2c/axp20x.c

645

error = axp20x_read(sc, AXP_DCDC2, &reg, 1);

sys/dev/i2c/axp20x.c

648

*pmvolt = __SHIFTOUT(reg, AXP_DCDC2_VOLT_MASK) * 25 + 700;

sys/dev/i2c/axp20x.c

651

error = axp20x_read(sc, AXP_DCDC3, &reg, 1);

sys/dev/i2c/axp20x.c

654

*pmvolt = __SHIFTOUT(reg, AXP_DCDC3_VOLT_MASK) * 25 + 700;

sys/dev/i2c/axp20x.c

665

uint8_t reg = AXP_SHUTDOWN_CTRL;

sys/dev/i2c/axp20x.c

668

error = axp20x_write(sc, AXP_SHUTDOWN, &reg, 1);

sys/dev/i2c/axp20x.c

761

const struct axp20xreg_attach_args *reg = aux;

sys/dev/i2c/axp20x.c

763

return axp20xreg_lookup(reg->reg_phandle) != NULL;

sys/dev/i2c/axp20x.c

770

const struct axp20xreg_attach_args *reg = aux;

sys/dev/i2c/axp20x.c

774

sc->sc_phandle = reg->reg_phandle;

sys/dev/i2c/axp20x.c

775

sc->sc_regdef = axp20xreg_lookup(reg->reg_phandle);

sys/dev/i2c/axp20x.c

777

regulator_name = fdtbus_get_string(reg->reg_phandle, "regulator-name");

sys/dev/i2c/axp20x.c

815

struct axp20xreg_attach_args reg = { .reg_phandle = child };

sys/dev/i2c/axp20x.c

816

config_found(sc->sc_dev, &reg, NULL, CFARGS_NONE);

sys/dev/i2c/axp22x.c

132

axp22x_read(struct axp22x_softc *sc, uint8_t reg, uint8_t *val, size_t len)

sys/dev/i2c/axp22x.c

139

reg + i, &val[i], 0);

sys/dev/i2c/axp809.c

148

axp809_read(struct axp809_softc *sc, uint8_t reg, uint8_t *val)

sys/dev/i2c/axp809.c

150

return iic_smbus_read_byte(sc->sc_i2c, sc->sc_addr, reg, val, 0);

sys/dev/i2c/axp809.c

154

axp809_write(struct axp809_softc *sc, uint8_t reg, uint8_t val)

sys/dev/i2c/axp809.c

156

return iic_smbus_write_byte(sc->sc_i2c, sc->sc_addr, reg, val, 0);

sys/dev/i2c/axppmic.c

1001

if (n == c->poklirq.reg && (stat & c->poklirq.mask) != 0)

sys/dev/i2c/axppmic.c

1003

if (n == c->acinirq.reg && (stat & c->acinirq.mask) != 0)

sys/dev/i2c/axppmic.c

1005

if (n == c->vbusirq.reg && (stat & c->vbusirq.mask) != 0)

sys/dev/i2c/axppmic.c

1007

if (n == c->battirq.reg && (stat & c->battirq.mask) != 0)

sys/dev/i2c/axppmic.c

1009

if (n == c->chargeirq.reg && (stat & c->chargeirq.mask) != 0)

sys/dev/i2c/axppmic.c

1011

if (n == c->chargestirq.reg && (stat & c->chargestirq.mask) != 0)

sys/dev/i2c/axppmic.c

1252

if (i == c->poklirq.reg)

sys/dev/i2c/axppmic.c

1254

if (i == c->acinirq.reg)

sys/dev/i2c/axppmic.c

1256

if (i == c->vbusirq.reg)

sys/dev/i2c/axppmic.c

1258

if (i == c->battirq.reg)

sys/dev/i2c/axppmic.c

1260

if (i == c->chargeirq.reg)

sys/dev/i2c/axppmic.c

1262

if (i == c->chargestirq.reg)

sys/dev/i2c/axppmic.c

405

u_int reg;

sys/dev/i2c/axppmic.c

410

{ .reg = (_reg), .mask = (_mask) }

sys/dev/i2c/axppmic.c

582

axppmic_read(i2c_tag_t tag, i2c_addr_t addr, uint8_t reg, uint8_t *val, int flags)

sys/dev/i2c/axppmic.c

584

return iic_smbus_read_byte(tag, addr, reg, val, flags);

sys/dev/i2c/axppmic.c

588

axppmic_write(i2c_tag_t tag, i2c_addr_t addr, uint8_t reg, uint8_t val, int flags)

sys/dev/i2c/axppmic.c

590

return iic_smbus_write_byte(tag, addr, reg, val, flags);

sys/dev/i2c/bmx280thpi2c.c

147

uint8_t reg = BMX280_REGISTER_ID;

sys/dev/i2c/bmx280thpi2c.c

151

error = bmx280thpi2c_read_register_direct(tag, addr, reg, buf, 1);

sys/dev/i2c/bmx280thpi2c.c

70

bmx280thpi2c_read_register_direct(i2c_tag_t tag, i2c_addr_t addr, uint8_t reg,

sys/dev/i2c/bmx280thpi2c.c

75

error = iic_exec(tag,I2C_OP_WRITE,addr,&reg,1,NULL,0,0);

sys/dev/i2c/bmx280thpi2c.c

86

bmx280thpi2c_read_register(struct bmx280_sc *sc, uint8_t reg,

sys/dev/i2c/bmx280thpi2c.c

95

reg, buf, blen);

sys/dev/i2c/cwfg.c

123

cwfg_read(struct cwfg_softc *sc, uint8_t reg, uint8_t *val)

sys/dev/i2c/cwfg.c

125

return iic_smbus_read_byte(sc->sc_i2c, sc->sc_addr, reg, val, 0);

sys/dev/i2c/cwfg.c

129

cwfg_write(struct cwfg_softc *sc, uint8_t reg, uint8_t val)

sys/dev/i2c/cwfg.c

131

return iic_smbus_write_byte(sc->sc_i2c, sc->sc_addr, reg, val, 0);

sys/dev/i2c/cx24227.c

106

cx24227_writereg(struct cx24227 *sc, uint8_t reg, uint16_t data)

sys/dev/i2c/cx24227.c

114

r[0] = reg;

sys/dev/i2c/cx24227.c

126

cx24227_readreg(struct cx24227 *sc, uint8_t reg, uint16_t *data)

sys/dev/i2c/cx24227.c

137

&reg, 1, r, 2, 0);

sys/dev/i2c/cx24227.c

160

uint16_t reg;

sys/dev/i2c/cx24227.c

163

cx24227_readreg(sc, 0xf1, &reg);

sys/dev/i2c/cx24227.c

165

if(reg & 0x1000)

sys/dev/i2c/cx24227.c

167

if(reg & 0x8000)

sys/dev/i2c/cx24227.c

287

uint16_t reg;

sys/dev/i2c/cx24227.c

295

cx24227_readreg(sc, 0xab, &reg);

sys/dev/i2c/cx24227.c

296

reg |= 0x0100;

sys/dev/i2c/cx24227.c

297

cx24227_writereg(sc, 0xab, reg);

sys/dev/i2c/cx24227.c

308

cx24227_readreg(sc, 0xe3, &reg);

sys/dev/i2c/cx24227.c

309

reg |= 0x1100;

sys/dev/i2c/cx24227.c

310

cx24227_writereg(sc, 0xe3, reg);

sys/dev/i2c/cx24227.c

313

cx24227_readreg(sc, 0xac, &reg);

sys/dev/i2c/cx24227.c

314

reg &= ~0x3000;

sys/dev/i2c/cx24227.c

315

reg |= 0x1000;

sys/dev/i2c/cx24227.c

316

cx24227_writereg(sc, 0xac, reg);

sys/dev/i2c/dbcool.c

1007

dbcool_read_rpm(struct dbcool_softc *sc, uint8_t reg)

sys/dev/i2c/dbcool.c

1012

rpm_lo = sc->sc_dc.dc_readreg(&sc->sc_dc, reg);

sys/dev/i2c/dbcool.c

1016

rpm_hi = sc->sc_dc.dc_readreg(&sc->sc_dc, reg + 1);

sys/dev/i2c/dbcool.c

1049

dbcool_read_volt(struct dbcool_softc *sc, uint8_t reg, int nom_idx, bool extres)

sys/dev/i2c/dbcool.c

1061

val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg);

sys/dev/i2c/dbcool.c

1069

val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg);

sys/dev/i2c/dbcool.c

1070

else if (reg == DBCOOL_12VIN) {

sys/dev/i2c/dbcool.c

1072

val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg);

sys/dev/i2c/dbcool.c

1074

} else if (reg == DBCOOL_VTT || reg == DBCOOL_IMON) {

sys/dev/i2c/dbcool.c

1078

if (reg == DBCOOL_IMON) {

sys/dev/i2c/dbcool.c

1093

switch (reg) {

sys/dev/i2c/dbcool.c

1133

int reg, error;

sys/dev/i2c/dbcool.c

1142

reg = sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg);

sys/dev/i2c/dbcool.c

1143

reg -= sc->sc_temp_offset;

sys/dev/i2c/dbcool.c

1145

reg = (int8_t)sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg);

sys/dev/i2c/dbcool.c

1147

node.sysctl_data = ®

sys/dev/i2c/dbcool.c

1169

int reg, error;

sys/dev/i2c/dbcool.c

1177

reg = (oldreg >> 1) & ~0x03;

sys/dev/i2c/dbcool.c

1179

node.sysctl_data = ®

sys/dev/i2c/dbcool.c

1202

int reg, error, newval;

sys/dev/i2c/dbcool.c

1210

reg = oldreg & 0x07;

sys/dev/i2c/dbcool.c

1212

node.sysctl_data = ®

sys/dev/i2c/dbcool.c

1244

int reg, error;

sys/dev/i2c/dbcool.c

1252

reg = (uint32_t)oldreg;

sys/dev/i2c/dbcool.c

1254

reg = ((reg & 0x0f) * 100) / 15;

sys/dev/i2c/dbcool.c

1256

reg = (reg * 100) / 255;

sys/dev/i2c/dbcool.c

1257

node.sysctl_data = ®

sys/dev/i2c/dbcool.c

1281

int i, reg, error;

sys/dev/i2c/dbcool.c

1292

reg = 4;

sys/dev/i2c/dbcool.c

1294

reg = 7;

sys/dev/i2c/dbcool.c

1296

reg = 4;

sys/dev/i2c/dbcool.c

1298

reg = 6;

sys/dev/i2c/dbcool.c

1300

reg = (oldreg >> 5) & 0x07;

sys/dev/i2c/dbcool.c

1302

strlcpy(dbcool_cur_behav, behavior[reg], sizeof(dbcool_cur_behav));

sys/dev/i2c/dbcool.c

1354

int reg, error;

sys/dev/i2c/dbcool.c

1362

reg = (sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg) >> 4) & 0x0f;

sys/dev/i2c/dbcool.c

1363

node.sysctl_data = ®

sys/dev/i2c/dbcool.c

1384

int reg, error;

sys/dev/i2c/dbcool.c

1395

reg = newreg >> 4;

sys/dev/i2c/dbcool.c

1397

reg = newreg;

sys/dev/i2c/dbcool.c

1398

reg = reg & 0x0f;

sys/dev/i2c/dbcool.c

1400

node.sysctl_data = ®

sys/dev/i2c/dbcool.c

1440

int reg, error;

sys/dev/i2c/dbcool.c

1445

reg = sc->sc_user_reg;

sys/dev/i2c/dbcool.c

1446

node.sysctl_data = ®

sys/dev/i2c/dbcool.c

1461

int reg, error;

sys/dev/i2c/dbcool.c

1469

reg = sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg);

sys/dev/i2c/dbcool.c

1470

node.sysctl_data = ®

sys/dev/i2c/dbcool.c

1486

#define DBC_PWM_SYSCTL(seq, reg) ((seq << 8) | reg)

sys/dev/i2c/dbcool.c

1633

(chip->table[i].reg.val_reg == DBCOOL_12VIN) &&

sys/dev/i2c/dbcool.c

1657

vid_reg = chip->table[i].reg.val_reg;

sys/dev/i2c/dbcool.c

1696

snprintf(name, 7, "s%02x", sc->sc_dc.dc_chip->table[idx].reg.val_reg);

sys/dev/i2c/dbcool.c

1702

sc->sc_regs[idx] = &sc->sc_dc.dc_chip->table[idx].reg;

sys/dev/i2c/dbcool.c

1746

sysctl_reg = chip->table[idx].reg.val_reg;

sys/dev/i2c/dbcool.c

1815

struct reg_list *reg;

sys/dev/i2c/dbcool.c

1818

reg = sc->sc_regs[i];

sys/dev/i2c/dbcool.c

1824

cur = dbcool_read_temp(sc, reg->val_reg, true);

sys/dev/i2c/dbcool.c

1828

cur = dbcool_read_volt(sc, reg->val_reg, nom_volt_idx,

sys/dev/i2c/dbcool.c

1832

cur = dbcool_read_rpm(sc, reg->val_reg);

sys/dev/i2c/dbcool.c

1950

struct reg_list *reg = sc->sc_regs[idx];

sys/dev/i2c/dbcool.c

1953

lo_lim = sc->sc_dc.dc_readreg(&sc->sc_dc, reg->lo_lim_reg);

sys/dev/i2c/dbcool.c

1954

hi_lim = sc->sc_dc.dc_readreg(&sc->sc_dc, reg->hi_lim_reg);

sys/dev/i2c/dbcool.c

1988

struct reg_list *reg = sc->sc_regs[idx];

sys/dev/i2c/dbcool.c

1997

limit = sc->sc_dc.dc_readreg(&sc->sc_dc, reg->lo_lim_reg);

sys/dev/i2c/dbcool.c

2004

limit = sc->sc_dc.dc_readreg(&sc->sc_dc, reg->hi_lim_reg);

sys/dev/i2c/dbcool.c

2017

struct reg_list *reg = sc->sc_regs[idx];

sys/dev/i2c/dbcool.c

2020

limit = dbcool_read_rpm(sc, reg->lo_lim_reg);

sys/dev/i2c/dbcool.c

2062

struct reg_list *reg = sc->sc_regs[idx];

sys/dev/i2c/dbcool.c

2080

sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg,

sys/dev/i2c/dbcool.c

2087

sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg,

sys/dev/i2c/dbcool.c

2106

sc->sc_dc.dc_writereg(&sc->sc_dc, reg->hi_lim_reg,

sys/dev/i2c/dbcool.c

2113

sc->sc_dc.dc_writereg(&sc->sc_dc, reg->hi_lim_reg,

sys/dev/i2c/dbcool.c

2122

struct reg_list *reg = sc->sc_regs[idx];

sys/dev/i2c/dbcool.c

2139

sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg, limit);

sys/dev/i2c/dbcool.c

2141

sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg, 0);

sys/dev/i2c/dbcool.c

2151

sc->sc_dc.dc_writereg(&sc->sc_dc, reg->hi_lim_reg, limit);

sys/dev/i2c/dbcool.c

2153

sc->sc_dc.dc_writereg(&sc->sc_dc, reg->hi_lim_reg, 0xff);

sys/dev/i2c/dbcool.c

2160

struct reg_list *reg = sc->sc_regs[idx];

sys/dev/i2c/dbcool.c

2176

sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg,

sys/dev/i2c/dbcool.c

2179

sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg + 1,

sys/dev/i2c/dbcool.c

2182

sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg, 0xff);

sys/dev/i2c/dbcool.c

2183

sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg + 1, 0xff);

sys/dev/i2c/dbcool.c

837

uint8_t reg, bit, cfg;

sys/dev/i2c/dbcool.c

843

reg = DBCOOL_ADT7466_CONFIG2;

sys/dev/i2c/dbcool.c

846

reg = DBCOOL_CONFIG2_REG;

sys/dev/i2c/dbcool.c

849

cfg = sc->sc_dc.dc_readreg(&sc->sc_dc, reg);

sys/dev/i2c/dbcool.c

856

sc->sc_dc.dc_writereg(&sc->sc_dc, reg, cfg);

sys/dev/i2c/dbcool.c

876

dbcool_readreg(struct dbcool_chipset *dc, uint8_t reg)

sys/dev/i2c/dbcool.c

885

if (iic_smbus_send_byte(dc->dc_tag, dc->dc_addr, reg, 0) != 0)

sys/dev/i2c/dbcool.c

889

(void)iic_smbus_read_byte(dc->dc_tag, dc->dc_addr, reg, &data,

sys/dev/i2c/dbcool.c

898

dbcool_writereg(struct dbcool_chipset *dc, uint8_t reg, uint8_t val)

sys/dev/i2c/dbcool.c

903

(void)iic_smbus_write_byte(dc->dc_tag, dc->dc_addr, reg, val, 0);

sys/dev/i2c/dbcool.c

928

dbcool_read_temp(struct dbcool_softc *sc, uint8_t reg, bool extres)

sys/dev/i2c/dbcool.c

938

val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg);

sys/dev/i2c/dbcool.c

940

ext = sc->sc_dc.dc_readreg(&sc->sc_dc, reg + 1);

sys/dev/i2c/dbcool.c

947

if (reg == DBCOOL_ADM1030_L_TEMP)

sys/dev/i2c/dbcool.c

949

else if (reg == DBCOOL_ADM1031_R2_TEMP)

sys/dev/i2c/dbcool.c

955

val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg);

sys/dev/i2c/dbcool.c

964

switch (reg) {

sys/dev/i2c/dbcool.c

984

val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg);

sys/dev/i2c/dbcool_reg.h

368

#define DBCOOL_VOLT_LOLIM(reg) ((reg - DBCOOL_25VIN) * 2 + DBCOOL_25VIN_LOWLIM)

sys/dev/i2c/dbcool_reg.h

369

#define DBCOOL_VOLT_HILIM(reg) (DBCOOL_VOLT_LOLIM(reg) + 1)

sys/dev/i2c/dbcool_reg.h

370

#define DBCOOL_TEMP_LOLIM(reg) \

sys/dev/i2c/dbcool_reg.h

371

((reg - DBCOOL_LOCAL_TEMP) * 2 + DBCOOL_LOCAL_LOWLIM)

sys/dev/i2c/dbcool_reg.h

372

#define DBCOOL_TEMP_HILIM(reg) (DBCOOL_TEMP_LOLIM(reg) + 1)

sys/dev/i2c/dbcool_reg.h

373

#define DBCOOL_TACH_LOLIM(reg) \

sys/dev/i2c/dbcool_reg.h

374

(reg - DBCOOL_FAN1_TACH_LSB + DBCOOL_TACH1_MIN_LSB)

sys/dev/i2c/dbcool_reg.h

375

#define ADM1030_TEMP_HILIM(reg) \

sys/dev/i2c/dbcool_reg.h

376

((reg - DBCOOL_ADM1030_L_TEMP) * 3 + DBCOOL_ADM1030_L_HI_LIM)

sys/dev/i2c/dbcool_reg.h

377

#define ADM1030_TEMP_LOLIM(reg) \

sys/dev/i2c/dbcool_reg.h

378

((reg - DBCOOL_ADM1030_L_TEMP) * 3 + DBCOOL_ADM1030_L_LO_LIM)

sys/dev/i2c/dbcool_reg.h

379

#define ADT7466_LIM_OFFSET(reg) \

sys/dev/i2c/dbcool_reg.h

380

((reg - DBCOOL_AIN1) * 2 + DBCOOL_AIN1_LOWLIM)

sys/dev/i2c/dbcool_reg.h

381

#define ADT7466_FAN_LIM_OFFSET(reg) \

sys/dev/i2c/dbcool_reg.h

382

(reg - DBCOOL_FANA_LSB + DBCOOL_FANA_LOWLIM_LSB)

sys/dev/i2c/dbcool_var.h

92

struct reg_list reg;

sys/dev/i2c/ds1307.c

730

uint8_t reg = dm->dm_rtc_start;

sys/dev/i2c/ds1307.c

732

&reg, 1, buf, 4, 0);

sys/dev/i2c/ds1307.c

740

__func__, reg, error);

sys/dev/i2c/ds1307.c

800

uint8_t reg = DS3232_TEMP_MSB;

sys/dev/i2c/ds1307.c

815

&reg, 1, buf, 2, 0);

sys/dev/i2c/ds2482ow.c

510

uint8_t reg = DS2482_SET_READ_POINTER;

sys/dev/i2c/ds2482ow.c

515

error = ds2482_cmd(tag, addr, &reg, &rbuf, &obuf, 1,

sys/dev/i2c/em3027.c

117

uint8_t reg;

sys/dev/i2c/em3027.c

133

EM3027_ONOFF, &reg, 0);

sys/dev/i2c/em3027.c

326

em3027rtc_iic_exec(struct em3027rtc_softc *sc, i2c_op_t op, uint8_t reg,

sys/dev/i2c/em3027.c

337

&reg, 1,

sys/dev/i2c/em3027.c

342

if (reg == EM3027_WATCH_BASE)

sys/dev/i2c/em3027.c

351

em3027rtc_read(struct em3027rtc_softc *sc, uint8_t reg, void *buf, size_t len)

sys/dev/i2c/em3027.c

354

return em3027rtc_iic_exec(sc, I2C_OP_READ_WITH_STOP, reg, buf, len);

sys/dev/i2c/em3027.c

359

em3027rtc_read_byte(struct em3027rtc_softc *sc, uint8_t reg, uint8_t *valp)

sys/dev/i2c/em3027.c

362

return em3027rtc_read(sc, reg, valp, 1);

sys/dev/i2c/em3027.c

367

em3027rtc_write(struct em3027rtc_softc *sc, uint8_t reg, void *buf, size_t len)

sys/dev/i2c/em3027.c

370

return em3027rtc_iic_exec(sc, I2C_OP_WRITE_WITH_STOP, reg, buf, len);

sys/dev/i2c/em3027.c

375

em3027rtc_write_byte(struct em3027rtc_softc *sc, uint8_t reg, uint8_t val)

sys/dev/i2c/em3027.c

378

return em3027rtc_write(sc, reg, &val, 1);

sys/dev/i2c/emcfan.c

108

emcfan_read_registerr(i2c_tag_t tag, i2c_addr_t addr, uint8_t reg,

sys/dev/i2c/emcfan.c

113

error = iic_exec(tag, I2C_OP_READ_WITH_STOP, addr, &reg, 1, res, 1, 0);

sys/dev/i2c/emcfan.c

119

emcfan_read_register(struct emcfan_sc *sc, uint8_t reg, uint8_t *res)

sys/dev/i2c/emcfan.c

121

if (emcfan_reg_is_real(sc,reg))

sys/dev/i2c/emcfan.c

122

return(emcfan_read_registerr(sc->sc_tag, sc->sc_addr, reg, res));

sys/dev/i2c/emcfan.c

129

emcfan_write_registerr(i2c_tag_t tag, i2c_addr_t addr, uint8_t reg,

sys/dev/i2c/emcfan.c

134

error = iic_exec(tag, I2C_OP_WRITE_WITH_STOP, addr, &reg, 1, &value, 1, 0);

sys/dev/i2c/emcfan.c

140

emcfan_write_register(struct emcfan_sc *sc, uint8_t reg, uint8_t value)

sys/dev/i2c/emcfan.c

142

if (emcfan_reg_is_real(sc,reg))

sys/dev/i2c/emcfan.c

143

return(emcfan_write_registerr(sc->sc_tag, sc->sc_addr, reg, value));

sys/dev/i2c/emcfan.c

91

emcfan_reg_is_real(struct emcfan_sc *sc, uint8_t reg)

sys/dev/i2c/emcfan.c

96

segment = reg / 64;

sys/dev/i2c/emcfan.c

97

index = reg % 64;

sys/dev/i2c/emcfan.c

99

DPRINTF(sc, 10, ("%s: void check 1: reg=%02x, segment=%d, index=%jd, sc_info_info=%d\n", __func__, reg,

sys/dev/i2c/es8316ac.c

136

escodec_read(struct escodec_softc *sc, uint8_t reg)

sys/dev/i2c/es8316ac.c

140

if (iic_smbus_read_byte(sc->sc_i2c, sc->sc_addr, reg, &val, 0) != 0)

sys/dev/i2c/es8316ac.c

147

escodec_write(struct escodec_softc *sc, uint8_t reg, uint8_t val)

sys/dev/i2c/es8316ac.c

149

(void)iic_smbus_write_byte(sc->sc_i2c, sc->sc_addr, reg, val, 0);

sys/dev/i2c/es8316ac.c

179

u_int reg[2];

sys/dev/i2c/es8316ac.c

215

.reg = {

sys/dev/i2c/es8316ac.c

231

.reg = {

sys/dev/i2c/es8316ac.c

248

.reg = {

sys/dev/i2c/es8316ac.c

267

.reg = {

sys/dev/i2c/es8316ac.c

287

.reg = {

sys/dev/i2c/es8316ac.c

357

val = escodec_read(sc, mix->reg[ch]);

sys/dev/i2c/es8316ac.c

367

escodec_write(sc, mix->reg[ch], val);

sys/dev/i2c/es8316ac.c

376

val = escodec_read(sc, mix->reg[0]);

sys/dev/i2c/es8316ac.c

381

escodec_write(sc, mix->reg[0], val);

sys/dev/i2c/es8316ac.c

411

val = escodec_read(sc, mix->reg[ch]);

sys/dev/i2c/es8316ac.c

424

val = escodec_read(sc, mix->reg[0]);

sys/dev/i2c/fan53555.c

105

&reg, 1, &val, 1, flags);

sys/dev/i2c/fan53555.c

107

aprint_error_dev(sc->sc_dev, "error reading reg %#x: %d\n", reg, error);

sys/dev/i2c/fan53555.c

113

fan53555_write(struct fan53555_softc *sc, uint8_t reg, uint8_t val, int flags)

sys/dev/i2c/fan53555.c

118

buf[0] = reg;

sys/dev/i2c/fan53555.c

124

aprint_error_dev(sc->sc_dev, "error writing reg %#x: %d\n", reg, error);

sys/dev/i2c/fan53555.c

127

#define I2C_READ(sc, reg) fan53555_read((sc), (reg), 0)

sys/dev/i2c/fan53555.c

128

#define I2C_WRITE(sc, reg, val) fan53555_write((sc), (reg), (val), 0)

sys/dev/i2c/fan53555.c

99

fan53555_read(struct fan53555_softc *sc, uint8_t reg, int flags)

sys/dev/i2c/fusbtc.c

254

uint8_t reg;

sys/dev/i2c/fusbtc.c

308

reg = fusbtc_read_reg(sc, FUSB_CONTROL3);

sys/dev/i2c/fusbtc.c

309

reg |= FUSB_CONTROL3_AUTO_RETRY;

sys/dev/i2c/fusbtc.c

310

reg |= FUSB_CONTROL3_N_RETRIES(3);

sys/dev/i2c/fusbtc.c

311

fusbtc_write_reg(sc, FUSB_CONTROL3, reg);

sys/dev/i2c/fusbtc.c

318

reg = fusbtc_read_reg(sc, FUSB_CONTROL0);

sys/dev/i2c/fusbtc.c

319

reg &= ~FUSB_CONTROL0_INT_MASK;

sys/dev/i2c/fusbtc.c

320

fusbtc_write_reg(sc, FUSB_CONTROL0, reg);

sys/dev/i2c/fusbtc.c

331

reg = fusbtc_read_reg(sc, FUSB_CONTROL0);

sys/dev/i2c/fusbtc.c

332

reg |= FUSB_CONTROL0_HOST_CUR0;

sys/dev/i2c/fusbtc.c

333

reg &= ~FUSB_CONTROL0_HOST_CUR1;

sys/dev/i2c/fusbtc.c

334

fusbtc_write_reg(sc, FUSB_CONTROL0, reg);

sys/dev/i2c/fusbtc.c

336

reg = fusbtc_read_reg(sc, FUSB_SWITCHES0);

sys/dev/i2c/fusbtc.c

337

reg &= ~(FUSB_SWITCHES0_VCONN_CC1 | FUSB_SWITCHES0_VCONN_CC2);

sys/dev/i2c/fusbtc.c

338

fusbtc_write_reg(sc, FUSB_SWITCHES0, reg);

sys/dev/i2c/fusbtc.c

341

reg = fusbtc_read_reg(sc, FUSB_CONTROL2);

sys/dev/i2c/fusbtc.c

342

reg |= FUSB_CONTROL2_TOGGLE;

sys/dev/i2c/fusbtc.c

343

fusbtc_write_reg(sc, FUSB_CONTROL2, reg);

sys/dev/i2c/fusbtc.c

420

uint8_t reg;

sys/dev/i2c/fusbtc.c

429

reg = fusbtc_read_reg(sc, FUSB_CONTROL0);

sys/dev/i2c/fusbtc.c

430

reg |= FUSB_CONTROL0_HOST_CUR0;

sys/dev/i2c/fusbtc.c

431

reg &= ~FUSB_CONTROL0_HOST_CUR1;

sys/dev/i2c/fusbtc.c

432

fusbtc_write_reg(sc, FUSB_CONTROL0, reg);

sys/dev/i2c/fusbtc.c

433

reg = fusbtc_read_reg(sc, FUSB_SWITCHES0);

sys/dev/i2c/fusbtc.c

434

reg &= ~(FUSB_SWITCHES0_VCONN_CC1 | FUSB_SWITCHES0_VCONN_CC2);

sys/dev/i2c/fusbtc.c

435

fusbtc_write_reg(sc, FUSB_SWITCHES0, reg);

sys/dev/i2c/fusbtc.c

458

uint8_t cc, reg;

sys/dev/i2c/fusbtc.c

479

reg = fusbtc_read_reg(sc, FUSB_STATUS0);

sys/dev/i2c/fusbtc.c

481

if ((reg & FUSB_STATUS0_COMP) == 0) {

sys/dev/i2c/fusbtc.c

485

reg = fusbtc_read_reg(sc, FUSB_STATUS0);

sys/dev/i2c/fusbtc.c

487

if ((reg & FUSB_STATUS0_COMP) == 0)

sys/dev/i2c/fusbtc.c

507

reg = fusbtc_read_reg(sc, FUSB_STATUS0);

sys/dev/i2c/fusbtc.c

508

reg &= FUSB_STATUS0_BC_LVL_MASK;

sys/dev/i2c/fusbtc.c

509

if (fusbtc_bclvl_to_typec(reg) == TYPEC_CC_OPEN) {

sys/dev/i2c/fusbtc.c

581

uint8_t reg;

sys/dev/i2c/fusbtc.c

586

reg = fusbtc_read_reg(sc, FUSB_STATUS0);

sys/dev/i2c/fusbtc.c

587

if ((reg & FUSB_STATUS0_COMP) == 0)

sys/dev/i2c/fusbtc.c

600

uint8_t reg;

sys/dev/i2c/fusbtc.c

602

reg = fusbtc_read_reg(sc, FUSB_SWITCHES1);

sys/dev/i2c/fusbtc.c

603

reg &= ~(FUSB_SWITCHES1_POWERROLE | FUSB_SWITCHES1_DATAROLE);

sys/dev/i2c/fusbtc.c

605

reg |= FUSB_SWITCHES1_POWERROLE;

sys/dev/i2c/fusbtc.c

607

reg |= FUSB_SWITCHES1_DATAROLE;

sys/dev/i2c/fusbtc.c

608

fusbtc_write_reg(sc, FUSB_SWITCHES1, reg);

sys/dev/i2c/fusbtc.c

622

uint8_t reg;

sys/dev/i2c/fusbtc.c

624

reg = fusbtc_read_reg(sc, FUSB_SWITCHES0);

sys/dev/i2c/fusbtc.c

625

reg &= ~(FUSB_SWITCHES0_PU_EN1 | FUSB_SWITCHES0_PU_EN2);

sys/dev/i2c/fusbtc.c

626

reg &= ~(FUSB_SWITCHES0_PD_EN1 | FUSB_SWITCHES0_PD_EN2);

sys/dev/i2c/fusbtc.c

629

reg |= FUSB_SWITCHES0_PU_EN1;

sys/dev/i2c/fusbtc.c

631

reg |= FUSB_SWITCHES0_PU_EN2;

sys/dev/i2c/fusbtc.c

635

reg |= FUSB_SWITCHES0_PD_EN1;

sys/dev/i2c/fusbtc.c

637

reg |= FUSB_SWITCHES0_PD_EN2;

sys/dev/i2c/fusbtc.c

639

fusbtc_write_reg(sc, FUSB_SWITCHES0, reg);

sys/dev/i2c/fusbtc.c

645

uint8_t reg;

sys/dev/i2c/fusbtc.c

647

reg = fusbtc_read_reg(sc, FUSB_SWITCHES0);

sys/dev/i2c/fusbtc.c

648

reg &= ~(FUSB_SWITCHES0_MEAS_CC1 | FUSB_SWITCHES0_MEAS_CC2);

sys/dev/i2c/fusbtc.c

649

reg &= ~(FUSB_SWITCHES0_VCONN_CC1 | FUSB_SWITCHES0_VCONN_CC2);

sys/dev/i2c/fusbtc.c

651

reg |= FUSB_SWITCHES0_MEAS_CC1;

sys/dev/i2c/fusbtc.c

653

reg |= FUSB_SWITCHES0_MEAS_CC2;

sys/dev/i2c/fusbtc.c

654

fusbtc_write_reg(sc, FUSB_SWITCHES0, reg);

sys/dev/i2c/fusbtc.c

656

reg = fusbtc_read_reg(sc, FUSB_SWITCHES1);

sys/dev/i2c/fusbtc.c

657

reg &= ~(FUSB_SWITCHES1_TXCC1 | FUSB_SWITCHES1_TXCC2);

sys/dev/i2c/fusbtc.c

659

reg |= FUSB_SWITCHES1_TXCC1;

sys/dev/i2c/fusbtc.c

661

reg |= FUSB_SWITCHES1_TXCC2;

sys/dev/i2c/fusbtc.c

662

fusbtc_write_reg(sc, FUSB_SWITCHES1, reg);

sys/dev/i2c/fusbtc.c

686

uint8_t reg;

sys/dev/i2c/fusbtc.c

687

reg = fusbtc_read_reg(sc, off);

sys/dev/i2c/fusbtc.c

688

reg |= val;

sys/dev/i2c/fusbtc.c

689

fusbtc_write_reg(sc, off, reg);

sys/dev/i2c/fusbtc.c

695

uint8_t reg;

sys/dev/i2c/fusbtc.c

696

reg = fusbtc_read_reg(sc, off);

sys/dev/i2c/fusbtc.c

697

reg &= ~val;

sys/dev/i2c/fusbtc.c

698

fusbtc_write_reg(sc, off, reg);

sys/dev/i2c/fusbtc.c

702

fusbtc_read_reg(struct fusbtc_softc *sc, uint8_t reg)

sys/dev/i2c/fusbtc.c

708

sc->sc_addr, &reg, sizeof(reg), &val, sizeof(val), 0)) {

sys/dev/i2c/fusbtc.c

710

reg);

sys/dev/i2c/fusbtc.c

718

fusbtc_write_reg(struct fusbtc_softc *sc, uint8_t reg, uint8_t val)

sys/dev/i2c/fusbtc.c

722

sc->sc_addr, &reg, sizeof(reg), &val, sizeof(val), 0)) {

sys/dev/i2c/fusbtc.c

724

reg);

sys/dev/i2c/g760a.c

119

g760a_readreg(struct g760a_softc* sc, uint8_t reg)

sys/dev/i2c/g760a.c

128

iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, sc->sc_addr, &reg, 1,

sys/dev/i2c/g760a.c

137

g760a_writereg(struct g760a_softc* sc, uint8_t reg, uint8_t data)

sys/dev/i2c/g760a.c

145

iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, sc->sc_addr, &reg, 1,

sys/dev/i2c/gttwsi_core.c

101

printf("I2C:R:[%" PRIu32 "]%02" PRIxBUSSIZE ":%02" PRIx32 "\n", reg, sc->sc_regmap[reg], val);

sys/dev/i2c/gttwsi_core.c

109

gttwsi_write_4(struct gttwsi_softc *sc, uint32_t reg, uint32_t val)

sys/dev/i2c/gttwsi_core.c

112

bus_space_write_4(sc->sc_bust, sc->sc_bush, sc->sc_regmap[reg], val);

sys/dev/i2c/gttwsi_core.c

114

printf("I2C:W:[%" PRIu32 "]%02" PRIxBUSSIZE ":%02" PRIx32 "\n", reg, sc->sc_regmap[reg], val);

sys/dev/i2c/gttwsi_core.c

96

gttwsi_read_4(struct gttwsi_softc *sc, uint32_t reg)

sys/dev/i2c/gttwsi_core.c

99

sc->sc_regmap[reg]);

sys/dev/i2c/lg3303.c

131

lg3303_read(struct lg3303 *lg, uint8_t reg, uint8_t *buf, size_t len)

sys/dev/i2c/lg3303.c

136

&reg, sizeof(reg), NULL, 0, 0);

sys/dev/i2c/lg3303.c

244

uint8_t reg = 0, value = 0x00;

sys/dev/i2c/lg3303.c

263

reg = 0x38;

sys/dev/i2c/lg3303.c

269

reg = 0x8a;

sys/dev/i2c/lg3303.c

281

error = lg3303_read(lg, reg, &value, sizeof(value));

sys/dev/i2c/lm75.c

328

lmtemp_temp_write(struct lmtemp_softc *sc, uint8_t reg, uint32_t val, int degc)

sys/dev/i2c/lm75.c

332

cmdbuf[0] = reg;

sys/dev/i2c/lm95221.c

103

uint8_t reg, val;

sys/dev/i2c/lm95221.c

122

reg = LM95221_STATUS;

sys/dev/i2c/lm95221.c

124

sc->sc_address, &reg, 1, &val, 1, 0)) {

sys/dev/i2c/lm95221.c

134

reg = LM95221_CONFIG;

sys/dev/i2c/lm95221.c

136

sc->sc_address, &reg, 1, &val, 1, 0)) {

sys/dev/i2c/lm95221.c

150

sc->sc_address, &reg, 1, &val, 1, 0)) {

sys/dev/i2c/lm_i2c.c

117

lm_i2c_readreg(struct lm_softc *lmsc, int reg)

sys/dev/i2c/lm_i2c.c

125

cmd = reg;

sys/dev/i2c/lm_i2c.c

136

lm_i2c_writereg(struct lm_softc *lmsc, int reg, uint8_t val)

sys/dev/i2c/lm_i2c.c

144

cmd = reg;

sys/dev/i2c/max77620.c

100

#define I2C_READ(sc, reg) max77620_read((sc), (reg), 0)

sys/dev/i2c/max77620.c

101

#define I2C_WRITE(sc, reg, val) max77620_write((sc), (reg), (val), 0)

sys/dev/i2c/max77620.c

76

max77620_read(struct max77620_softc *sc, uint8_t reg, int flags)

sys/dev/i2c/max77620.c

82

&reg, 1, &val, 1, flags);

sys/dev/i2c/max77620.c

84

aprint_error_dev(sc->sc_dev, "error reading reg %#x: %d\n", reg, error);

sys/dev/i2c/max77620.c

90

max77620_write(struct max77620_softc *sc, uint8_t reg, uint8_t val, int flags)

sys/dev/i2c/max77620.c

95

&reg, 1, &val, 1, flags);

sys/dev/i2c/max77620.c

97

aprint_error_dev(sc->sc_dev, "error writing reg %#x: %d\n", reg, error);

sys/dev/i2c/mcp23xxxgpio_i2c.c

106

uint8_t reg, uint8_t *valp)

sys/dev/i2c/mcp23xxxgpio_i2c.c

114

&reg, 1, valp, 1, 0);

sys/dev/i2c/mcp23xxxgpio_i2c.c

119

uint8_t reg, uint8_t val)

sys/dev/i2c/mcp23xxxgpio_i2c.c

127

&reg, 1, &val, 1, 0);

sys/dev/i2c/mcp980x.c

142

mcp980x_reg_read_2(struct mcp980x_softc *sc, uint8_t reg)

sys/dev/i2c/mcp980x.c

151

if (iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, sc->sc_addr, &reg,

sys/dev/i2c/mcp980x.c

163

mcp980x_reg_read_1(struct mcp980x_softc *sc, uint8_t reg)

sys/dev/i2c/mcp980x.c

172

if (iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, sc->sc_addr, &reg,

sys/dev/i2c/mcp980x.c

184

mcp980x_reg_write_2(struct mcp980x_softc *sc, uint8_t reg, uint16_t val)

sys/dev/i2c/mcp980x.c

195

if (iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, sc->sc_addr, &reg,

sys/dev/i2c/mcp980x.c

205

mcp980x_reg_write_1(struct mcp980x_softc *sc, uint8_t reg, uint8_t val)

sys/dev/i2c/mcp980x.c

212

if (iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, sc->sc_addr, &reg,

sys/dev/i2c/mcp980x.c

246

mcp980x_s8b_get(struct mcp980x_softc *sc, uint8_t reg)

sys/dev/i2c/mcp980x.c

248

return mcp980x_reg_read_2(sc, reg) >> MCP980X_TEMP_HYSTLIMIT_INT_SHIFT;

sys/dev/i2c/mcp980x.c

252

mcp980x_s8b_set(struct mcp980x_softc *sc, uint8_t reg, int8_t val)

sys/dev/i2c/mcp980x.c

254

mcp980x_reg_write_2(sc, reg, val << MCP980X_TEMP_HYSTLIMIT_INT_SHIFT);

sys/dev/i2c/mpl115a.c

155

mpl115a_reg_write_1(struct mpl115a_softc *sc, uint8_t reg, uint8_t val)

sys/dev/i2c/mpl115a.c

162

if (iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, sc->sc_addr, &reg, 1,

sys/dev/i2c/mpl115a.c

170

mpl115a_reg_read_1(struct mpl115a_softc *sc, uint8_t reg)

sys/dev/i2c/mpl115a.c

181

wbuf[0] = reg;

sys/dev/i2c/mt2131.c

100

if ((reg & 0xfe) != 0x3e) {

sys/dev/i2c/mt2131.c

102

__func__, reg);

sys/dev/i2c/mt2131.c

83

uint8_t cmd, reg;

sys/dev/i2c/mt2131.c

85

cmd = reg = 0;

sys/dev/i2c/mt2131.c

90

ret = iic_exec(t, I2C_OP_READ_WITH_STOP, a, &cmd, 1, &reg, 1,

sys/dev/i2c/nxp75a.c

114

reg = NXP75A_OVERTEMP;

sys/dev/i2c/nxp75a.c

115

if (nxp75a_read_temp(sc, reg, &tval)) {

sys/dev/i2c/nxp75a.c

122

reg = NXP75A_THYST;

sys/dev/i2c/nxp75a.c

123

if (nxp75a_read_temp(sc, reg, &tval)) {

sys/dev/i2c/nxp75a.c

132

reg = NXP75A_CONFIG;

sys/dev/i2c/nxp75a.c

134

sc->sc_address, &reg, 1, &val, 1, 0)) {

sys/dev/i2c/nxp75a.c

144

sc->sc_address, &reg, 1, &val, 1, 0)) {

sys/dev/i2c/nxp75a.c

199

uint8_t reg;

sys/dev/i2c/nxp75a.c

205

reg = NXP75A_TEMP;

sys/dev/i2c/nxp75a.c

206

if (nxp75a_read_temp(sc, reg, &val) == 0) {

sys/dev/i2c/nxp75a.c

221

uint8_t reg;

sys/dev/i2c/nxp75a.c

229

reg = NXP75A_OVERTEMP;

sys/dev/i2c/nxp75a.c

230

if (nxp75a_read_temp(sc, reg, &val) == 0) {

sys/dev/i2c/nxp75a.c

243

uint8_t reg;

sys/dev/i2c/nxp75a.c

258

reg = NXP75A_OVERTEMP;

sys/dev/i2c/nxp75a.c

259

if (nxp75a_write_temp(sc, reg, otemp) == 0) {

sys/dev/i2c/nxp75a.c

260

reg = NXP75A_THYST;

sys/dev/i2c/nxp75a.c

261

nxp75a_write_temp(sc, reg, hyst);

sys/dev/i2c/nxp75a.c

269

nxp75a_read_temp(struct nxp75a_softc *sc, uint8_t reg, uint32_t *valp)

sys/dev/i2c/nxp75a.c

275

sc->sc_address, &reg, 1, buf, NXP75A_TEMP_LEN, 0);

sys/dev/i2c/nxp75a.c

291

nxp75a_write_temp(struct nxp75a_softc *sc, uint8_t reg, uint32_t val)

sys/dev/i2c/nxp75a.c

302

sc->sc_address, &reg, 1, buf, NXP75A_TEMP_LEN, 0);

sys/dev/i2c/nxp75a.c

98

uint8_t reg, val;

sys/dev/i2c/nxt2k.c

100

&reg, 1, data, len, 0);

sys/dev/i2c/nxt2k.c

108

nxt2k_writereg(struct nxt2k *nxt, uint8_t reg, uint8_t *data, size_t len)

sys/dev/i2c/nxt2k.c

112

nxt2k_writedata(nxt, 0x35, &reg, 1);

sys/dev/i2c/nxt2k.c

117

if (reg & 0x80) {

sys/dev/i2c/nxt2k.c

119

if (reg & 0x04)

sys/dev/i2c/nxt2k.c

138

nxt2k_readreg(struct nxt2k *nxt, uint8_t reg, uint8_t *data, size_t len)

sys/dev/i2c/nxt2k.c

143

nxt2k_writedata(nxt, 0x35, &reg, 1);

sys/dev/i2c/nxt2k.c

146

if (reg & 0x80) {

sys/dev/i2c/nxt2k.c

148

if (reg & 0x04)

sys/dev/i2c/nxt2k.c

550

uint8_t reg;

sys/dev/i2c/nxt2k.c

553

nxt2k_readdata(nxt, 0x31, &reg, 1);

sys/dev/i2c/nxt2k.c

554

if (reg & 0x20) {

sys/dev/i2c/nxt2k.c

566

uint8_t reg[3];

sys/dev/i2c/nxt2k.c

568

nxt2k_readreg(nxt, 0xe6, reg, 3);

sys/dev/i2c/nxt2k.c

569

*ucblk = reg[2];

sys/dev/i2c/nxt2k.c

577

uint8_t reg[3];

sys/dev/i2c/nxt2k.c

579

nxt2k_readreg(nxt, 0xe6, reg, 3);

sys/dev/i2c/nxt2k.c

581

*ber = ((reg[0] << 8) + reg[1]) * 8;

sys/dev/i2c/nxt2k.c

70

nxt2k_writedata(struct nxt2k *nxt, uint8_t reg, uint8_t *data, size_t len)

sys/dev/i2c/nxt2k.c

80

buffer[0] = reg;

sys/dev/i2c/nxt2k.c

92

nxt2k_readdata(struct nxt2k *nxt, uint8_t reg, uint8_t *data, size_t len)

sys/dev/i2c/pca9685.c

100

sc->sc_addr, &reg, sizeof(reg),

sys/dev/i2c/pca9685.c

105

pcapwm_write1(struct pcapwm_softc * const sc, uint8_t reg, uint8_t val)

sys/dev/i2c/pca9685.c

109

sc->sc_addr, &reg, sizeof(reg),

sys/dev/i2c/pca9685.c

114

pcapwm_read_LEDn(struct pcapwm_softc * const sc, uint8_t reg, uint8_t *buf,

sys/dev/i2c/pca9685.c

120

sc->sc_addr, &reg, sizeof(reg),

sys/dev/i2c/pca9685.c

125

pcapwm_write_LEDn(struct pcapwm_softc * const sc, uint8_t reg, uint8_t *buf,

sys/dev/i2c/pca9685.c

131

sc->sc_addr, &reg, sizeof(reg),

sys/dev/i2c/pca9685.c

140

const uint8_t reg = chan->ch_number == PCA9685_ALL_CHANNELS ?

sys/dev/i2c/pca9685.c

157

error = pcapwm_write_LEDn(sc, reg, regs, sizeof(regs));

sys/dev/i2c/pca9685.c

169

const uint8_t reg = chan->ch_number == PCA9685_ALL_CHANNELS ?

sys/dev/i2c/pca9685.c

181

error = pcapwm_read_LEDn(sc, reg, regs, sizeof(regs));

sys/dev/i2c/pca9685.c

96

pcapwm_read1(struct pcapwm_softc * const sc, uint8_t reg, uint8_t *valp)

sys/dev/i2c/pcagpio.c

256

pcagpio_writereg(struct pcagpio_softc *sc, int reg, uint32_t val)

sys/dev/i2c/pcagpio.c

263

cmd = reg << 1;

sys/dev/i2c/pcagpio.c

269

cmd = reg;

sys/dev/i2c/pcagpio.c

274

if (reg == PCAGPIO_OUTPUT) sc->sc_state = val;

sys/dev/i2c/pcagpio.c

278

static uint32_t pcagpio_readreg(struct pcagpio_softc *sc, int reg)

sys/dev/i2c/pcagpio.c

286

cmd = reg << 1;

sys/dev/i2c/pcagpio.c

292

cmd = reg;

sys/dev/i2c/pcf8563.c

138

uint8_t reg = PCF8563_R_SECOND;

sys/dev/i2c/pcf8563.c

147

&reg, 1, &bcd[reg], PCF8563_R_YEAR - reg + 1,

sys/dev/i2c/pcf8563.c

177

uint8_t reg = PCF8563_R_SECOND;

sys/dev/i2c/pcf8563.c

195

if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, sc->sc_addr, &reg, 1, &bcd[reg], PCF8563_R_YEAR - reg + 1, 0)) != 0) {

sys/dev/i2c/r2025.c

204

r2025rtc_reg_write(struct r2025rtc_softc *sc, int reg, uint8_t *val, int len)

sys/dev/i2c/r2025.c

218

cmdbuf[0] = (((reg + i) << 4) & 0xf0);

sys/dev/i2c/r2025.c

236

r2025rtc_reg_read(struct r2025rtc_softc *sc, int reg, uint8_t *val, int len)

sys/dev/i2c/r2025.c

250

cmdbuf[0] = (((reg + i) << 4) & 0xf0);

sys/dev/i2c/rkpmic.c

238

rkpmic_read(struct rkpmic_softc *sc, uint8_t reg, int flags)

sys/dev/i2c/rkpmic.c

243

error = iic_smbus_read_byte(sc->sc_i2c, sc->sc_addr, reg, &val, flags);

sys/dev/i2c/rkpmic.c

245

device_printf(sc->sc_dev, "error reading reg %#x: %d\n", reg, error);

sys/dev/i2c/rkpmic.c

251

rkpmic_write(struct rkpmic_softc *sc, uint8_t reg, uint8_t val, int flags)

sys/dev/i2c/rkpmic.c

255

error = iic_smbus_write_byte(sc->sc_i2c, sc->sc_addr, reg, val, flags);

sys/dev/i2c/rkpmic.c

257

device_printf(sc->sc_dev, "error writing reg %#x: %d\n", reg, error);

sys/dev/i2c/rkpmic.c

260

#define I2C_READ(sc, reg) rkpmic_read((sc), (reg), 0)

sys/dev/i2c/rkpmic.c

261

#define I2C_WRITE(sc, reg, val) rkpmic_write((sc), (reg), (val), 0)

sys/dev/i2c/rs5c372.c

126

rs5c372rtc_reg_write(struct rs5c372rtc_softc *sc, int reg, uint8_t val)

sys/dev/i2c/rs5c372.c

137

reg &= 0xf;

sys/dev/i2c/rs5c372.c

138

cmdbuf[0] = (reg << 4);

sys/dev/i2c/rs5c372.c

145

"rs5c372rtc_reg_write: failed to write reg%d\n", reg);

sys/dev/i2c/s390.c

101

if (s390rtc_read(sc, S390_STATUS1, reg, sizeof(reg)))

sys/dev/i2c/s390.c

103

if (reg[0] & (S390_ST1_POC | S390_ST1_BLD)) {

sys/dev/i2c/s390.c

104

reg[0] |= S390_ST1_24H | S390_ST1_RESET;

sys/dev/i2c/s390.c

105

if (s390rtc_write(sc, S390_STATUS1, reg, sizeof(reg)))

sys/dev/i2c/s390.c

110

if (s390rtc_read(sc, S390_STATUS2, reg, sizeof(reg)))

sys/dev/i2c/s390.c

112

if ((reg[0] & S390_ST2_TEST)) {

sys/dev/i2c/s390.c

113

reg[0] &= ~S390_ST2_TEST;

sys/dev/i2c/s390.c

114

if (s390rtc_write(sc, S390_STATUS2, reg, sizeof(reg)))

sys/dev/i2c/s390.c

170

s390rtc_read(struct s390rtc_softc *sc, int reg, uint8_t *buf, size_t len)

sys/dev/i2c/s390.c

181

sc->sc_addr + reg, NULL, 0, buf, len, 0)) != 0) {

sys/dev/i2c/s390.c

184

"%s: failed to read reg%d\n", __func__, reg);

sys/dev/i2c/s390.c

198

s390rtc_write(struct s390rtc_softc *sc, int reg, uint8_t *buf, size_t len)

sys/dev/i2c/s390.c

213

sc->sc_addr + reg, NULL, 0, buf, len, 0)) != 0) {

sys/dev/i2c/s390.c

216

"%s: failed to write reg%d\n", __func__, reg);

sys/dev/i2c/s390.c

91

uint8_t reg[1];

sys/dev/i2c/sc16is7xxi2c.c

102

sc16is7xxi2c_read_register(struct sc16is7xx_sc *sc, uint8_t reg, int channel,

sys/dev/i2c/sc16is7xxi2c.c

111

reg, channel, buf, blen);

sys/dev/i2c/sc16is7xxi2c.c

117

sc16is7xxi2c_write_register(struct sc16is7xx_sc *sc, uint8_t reg, int channel,

sys/dev/i2c/sc16is7xxi2c.c

126

reg, channel, buf, blen);

sys/dev/i2c/sc16is7xxi2c.c

145

sc16is7xx_i2c_com_read_1(struct com_regs *regs, u_int reg)

sys/dev/i2c/sc16is7xxi2c.c

156

reg, regs->cr_channel, &buf, 1);

sys/dev/i2c/sc16is7xxi2c.c

176

sc16is7xx_i2c_com_write_1(struct com_regs *regs, u_int reg, uint8_t val)

sys/dev/i2c/sc16is7xxi2c.c

186

reg, regs->cr_channel, &val, 1);

sys/dev/i2c/sc16is7xxi2c.c

201

sc16is7xx_i2c_com_write_multi_1(struct com_regs *regs, u_int reg, const uint8_t *datap,

sys/dev/i2c/sc16is7xxi2c.c

212

reg, regs->cr_channel, __UNCONST(datap), count);

sys/dev/i2c/sc16is7xxi2c.c

235

uint8_t reg = SC16IS7XX_REGISTER_SPR;

sys/dev/i2c/sc16is7xxi2c.c

239

error = sc16is7xxi2c_read_register_direct(tag, addr, reg, 0, buf, 1);

sys/dev/i2c/sc16is7xxi2c.c

63

sc16is7xxi2c_read_register_direct(i2c_tag_t tag, i2c_addr_t addr, uint8_t reg,

sys/dev/i2c/sc16is7xxi2c.c

69

xreg = (reg << 3) | (channel << 1);

sys/dev/i2c/sc16is7xxi2c.c

82

sc16is7xxi2c_write_register_direct(i2c_tag_t tag, i2c_addr_t addr, uint8_t reg,

sys/dev/i2c/sc16is7xxi2c.c

88

xreg = (reg << 3) | (channel << 1);

sys/dev/i2c/scmdi2c.c

100

return scmdi2c_write_reg_direct(sc->sc_tag, sc->sc_addr, reg, buf);

sys/dev/i2c/scmdi2c.c

118

uint8_t reg = SCMD_REG_ID;

sys/dev/i2c/scmdi2c.c

122

error = scmdi2c_read_reg_direct(tag, addr, reg, &buf);

sys/dev/i2c/scmdi2c.c

76

scmdi2c_read_reg_direct(i2c_tag_t tag, i2c_addr_t addr, uint8_t reg,

sys/dev/i2c/scmdi2c.c

79

return iic_exec(tag, I2C_OP_READ_WITH_STOP, addr, &reg, 1, buf,

sys/dev/i2c/scmdi2c.c

84

scmdi2c_read_reg(struct scmd_sc *sc, uint8_t reg, uint8_t *buf)

sys/dev/i2c/scmdi2c.c

86

return scmdi2c_read_reg_direct(sc->sc_tag, sc->sc_addr, reg, buf);

sys/dev/i2c/scmdi2c.c

90

scmdi2c_write_reg_direct(i2c_tag_t tag, i2c_addr_t addr, uint8_t reg,

sys/dev/i2c/scmdi2c.c

93

return iic_exec(tag, I2C_OP_WRITE_WITH_STOP, addr, &reg, 1, &buf,

sys/dev/i2c/scmdi2c.c

98

scmdi2c_write_reg(struct scmd_sc *sc, uint8_t reg, uint8_t buf)

sys/dev/i2c/sdtemp.c

504

sdtemp_read_8(struct sdtemp_softc *sc, uint8_t reg, uint8_t *valp)

sys/dev/i2c/sdtemp.c

509

sc->sc_address, &reg, 1, valp, sizeof(*valp), 0);

sys/dev/i2c/sdtemp.c

515

sdtemp_write_8(struct sdtemp_softc *sc, uint8_t reg, uint8_t val)

sys/dev/i2c/sdtemp.c

518

sc->sc_address, &reg, 1, &val, sizeof(val), 0);

sys/dev/i2c/sdtemp.c

524

sdtemp_read_16(struct sdtemp_softc *sc, uint8_t reg, uint16_t *valp)

sys/dev/i2c/sdtemp.c

529

sc->sc_address, &reg, 1, valp, sizeof(*valp), 0);

sys/dev/i2c/sdtemp.c

539

sdtemp_write_16(struct sdtemp_softc *sc, uint8_t reg, uint16_t val)

sys/dev/i2c/sdtemp.c

545

sc->sc_address, &reg, 1, &temp, sizeof(temp), 0);

sys/dev/i2c/sgp40.c

456

uint8_t reg[2];

sys/dev/i2c/sgp40.c

464

reg[0] = SGP40_GET_SERIAL_NUMBER >> 8;

sys/dev/i2c/sgp40.c

465

reg[1] = SGP40_GET_SERIAL_NUMBER & 0x00ff;

sys/dev/i2c/sgp40.c

467

error = sgp40_cmd(tag, addr, reg, 2, buf, 9, 10);

sys/dev/i2c/sgsmix.c

146

sgsmix_writereg(struct sgsmix_softc *sc, int reg, uint8_t val)

sys/dev/i2c/sgsmix.c

148

uint8_t out[2] = {reg, val};

sys/dev/i2c/sgsmix.c

150

if ((reg < 0) || (reg >= 7))

sys/dev/i2c/sgsmix.c

153

if (sc->sc_regs[reg] == val)

sys/dev/i2c/sgsmix.c

158

sc->sc_regs[reg] = val;

sys/dev/i2c/sht3x.c

359

sht3x_get_status_register(void *aux, uint16_t *reg, bool have_bus)

sys/dev/i2c/sht3x.c

383

*reg = buf[0] << 8 | buf[1];

sys/dev/i2c/sht3x.c

931

uint16_t reg = SHT3X_GET_STATUS_REGISTER;

sys/dev/i2c/sht3x.c

935

error = sht3x_cmd(tag, addr, &reg, 2, buf, 3, 10);

sys/dev/i2c/sht4x.c

408

uint8_t reg = SHT4X_READ_SERIAL;

sys/dev/i2c/sht4x.c

412

error = sht4x_cmd(tag, addr, &reg, 1, buf, 6, 10);

sys/dev/i2c/si70xx.c

474

uint8_t reg = SI70XX_READ_USER_REG_1;

sys/dev/i2c/si70xx.c

478

error = si70xx_cmd(tag, addr, &reg, 1, &buf, 1);

sys/dev/i2c/smscmon.c

106

.reg = 0x25,

sys/dev/i2c/smscmon.c

114

.reg = 0x50,

sys/dev/i2c/smscmon.c

122

.reg = 0x51,

sys/dev/i2c/smscmon.c

130

.reg = 0x26,

sys/dev/i2c/smscmon.c

138

.reg = 0x27,

sys/dev/i2c/smscmon.c

146

.reg = 0x52,

sys/dev/i2c/smscmon.c

251

smscmon_readreg(struct smscmon_sc *sc, int reg)

sys/dev/i2c/smscmon.c

257

cmd = reg;

sys/dev/i2c/smscmon.c

266

smscmon_writereg(struct smscmon_sc *sc, int reg, int val)

sys/dev/i2c/smscmon.c

272

cmd = reg;

sys/dev/i2c/smscmon.c

300

data = (*sc->smscmon_readreg)(sc, sens->reg);

sys/dev/i2c/smscmon.c

316

data = (*sc->smscmon_readreg)(sc, sens->reg);

sys/dev/i2c/smscmon.c

66

.reg = 0x20,

sys/dev/i2c/smscmon.c

74

.reg = 0x21,

sys/dev/i2c/smscmon.c

82

.reg = 0x22,

sys/dev/i2c/smscmon.c

90

.reg = 0x23,

sys/dev/i2c/smscmon.c

98

.reg = 0x24,

sys/dev/i2c/smscmonvar.h

62

uint8_t reg;

sys/dev/i2c/spdmem_i2c.c

104

uint8_t reg, byte0, byte2;

sys/dev/i2c/spdmem_i2c.c

108

reg = 0;

sys/dev/i2c/spdmem_i2c.c

118

rv = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, sc->sc_addr, &reg, 1,

sys/dev/i2c/spdmem_i2c.c

123

reg = 2;

sys/dev/i2c/spdmem_i2c.c

124

rv = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, sc->sc_addr, &reg, 1,

sys/dev/i2c/spdmem_i2c.c

152

&reg, 1, &dummy, 1, 0);

sys/dev/i2c/spdmem_i2c.c

162

sc->sc_page0, &reg, 1, &dummy, 1, 0);

sys/dev/i2c/spdmem_i2c.c

267

uint8_t reg;

sys/dev/i2c/spdmem_i2c.c

272

reg = addr & 0xff;

sys/dev/i2c/spdmem_i2c.c

282

&reg, 1, val, 1, 0);

sys/dev/i2c/spdmem_i2c.c

287

&reg, 1, val, 1, 0);

sys/dev/i2c/sy8106a.c

68

sy8106a_read(struct sy8106a_softc *sc, uint8_t reg, int flags)

sys/dev/i2c/sy8106a.c

74

&reg, 1, &val, 1, flags);

sys/dev/i2c/sy8106a.c

76

aprint_error_dev(sc->sc_dev, "error reading reg %#x: %d\n", reg, error);

sys/dev/i2c/sy8106a.c

82

sy8106a_write(struct sy8106a_softc *sc, uint8_t reg, uint8_t val, int flags)

sys/dev/i2c/sy8106a.c

87

buf[0] = reg;

sys/dev/i2c/sy8106a.c

93

aprint_error_dev(sc->sc_dev, "error writing reg %#x: %d\n", reg, error);

sys/dev/i2c/sy8106a.c

96

#define I2C_READ(sc, reg) sy8106a_read((sc), (reg), 0)

sys/dev/i2c/sy8106a.c

97

#define I2C_WRITE(sc, reg, val) sy8106a_write((sc), (reg), (val), 0)

sys/dev/i2c/tcagpio.c

102

aprint_error_dev(sc->sc_dev, "error writing reg %#x: %d\n", reg, error);

sys/dev/i2c/tcagpio.c

105

#define I2C_READ(sc, reg) tcagpio_read((sc), (reg), 0)

sys/dev/i2c/tcagpio.c

106

#define I2C_WRITE(sc, reg, val) tcagpio_write((sc), (reg), (val), 0)

sys/dev/i2c/tcagpio.c

77

tcagpio_read(struct tcagpio_softc *sc, uint8_t reg, int flags)

sys/dev/i2c/tcagpio.c

83

&reg, 1, &val, 1, flags);

sys/dev/i2c/tcagpio.c

85

aprint_error_dev(sc->sc_dev, "error reading reg %#x: %d\n", reg, error);

sys/dev/i2c/tcagpio.c

91

tcagpio_write(struct tcagpio_softc *sc, uint8_t reg, uint8_t val, int flags)

sys/dev/i2c/tcagpio.c

96

buf[0] = reg;

sys/dev/i2c/tcakp.c

444

tcakp_read(struct tcakp_softc *sc, uint8_t reg, uint8_t *val)

sys/dev/i2c/tcakp.c

447

&reg, 1, val, 1, 0);

sys/dev/i2c/tcakp.c

451

tcakp_write(struct tcakp_softc *sc, uint8_t reg, uint8_t val)

sys/dev/i2c/tcakp.c

453

uint8_t buf[2] = { reg, val };

sys/dev/i2c/tda19988.c

312

uint8_t reg;

sys/dev/i2c/tda19988.c

314

reg = REGADDR(addr);

sys/dev/i2c/tda19988.c

319

return iic_exec(sc->sc_i2c, I2C_OP_READ_WITH_STOP, sc->sc_addr, &reg, 1, data, len, 0);

sys/dev/i2c/tda19988.c

325

uint8_t reg;

sys/dev/i2c/tda19988.c

327

reg = REGADDR(addr);

sys/dev/i2c/tda19988.c

332

return iic_exec(sc->sc_i2c, I2C_OP_READ_WITH_STOP, sc->sc_addr, &reg, 1, data, 1, 0);

sys/dev/i2c/tda19988.c

405

uint8_t reg, div;

sys/dev/i2c/tda19988.c

490

reg = VIP_CNTRL_3_SYNC_HS;

sys/dev/i2c/tda19988.c

492

reg |= VIP_CNTRL_3_H_TGL;

sys/dev/i2c/tda19988.c

494

reg |= VIP_CNTRL_3_V_TGL;

sys/dev/i2c/tda19988.c

495

tda19988_reg_write(sc, TDA_VIP_CNTRL_3, reg);

sys/dev/i2c/tda19988.c

497

reg = TBG_CNTRL_1_TGL_EN;

sys/dev/i2c/tda19988.c

499

reg |= TBG_CNTRL_1_H_TGL;

sys/dev/i2c/tda19988.c

501

reg |= TBG_CNTRL_1_V_TGL;

sys/dev/i2c/tda19988.c

502

tda19988_reg_write(sc, TDA_TBG_CNTRL_1, reg);

sys/dev/i2c/tda19988.c

65

#define REGPAGE(reg) (((reg) >> 8) & 0xff)

sys/dev/i2c/tda19988.c

66

#define REGADDR(reg) ((reg) & 0xff)

sys/dev/i2c/tea5767.c

150

tea5767_write(struct tea5767_softc *sc, uint8_t *reg)

sys/dev/i2c/tea5767.c

160

sc->sc_addr, NULL, 0, reg, 5, 0);

sys/dev/i2c/tea5767.c

176

tea5767_read(struct tea5767_softc *sc, uint8_t *reg)

sys/dev/i2c/tea5767.c

186

sc->sc_addr, NULL, 0, reg, 5, 0);

sys/dev/i2c/tea5767.c

224

tea5767_set_properties(struct tea5767_softc *sc, uint8_t *reg)

sys/dev/i2c/tea5767.c

226

memset(reg,0,5);

sys/dev/i2c/tea5767.c

228

tea5767_freq_to_pll(sc->tune, reg);

sys/dev/i2c/tea5767.c

231

reg[0] |= TEA5767_MUTE;

sys/dev/i2c/tea5767.c

232

reg[2] |=TEA5767_MUTE_R | TEA5767_MUTE_L;

sys/dev/i2c/tea5767.c

235

reg[3] |= TEA5767_SNC;

sys/dev/i2c/tea5767.c

238

reg[2] |= TEA5767_MONO;

sys/dev/i2c/tea5767.c

240

reg[3] |= TEA5767_FM_BAND;

sys/dev/i2c/tea5767.c

246

uint8_t reg[5];

sys/dev/i2c/tea5767.c

248

tea5767_set_properties(sc, reg);

sys/dev/i2c/tea5767.c

249

tea5767_write(sc, reg);

sys/dev/i2c/tea5767.c

251

memset(reg,0,5);

sys/dev/i2c/tea5767.c

253

tea5767_read(sc,reg);

sys/dev/i2c/tea5767.c

255

if ((reg[2] & 0x7f) == 0x37)

sys/dev/i2c/tea5767.c

276

uint8_t reg[5];

sys/dev/i2c/tea5767.c

277

tea5767_read(sc, reg);

sys/dev/i2c/tea5767.c

279

tea5767_pll_to_freq(&sc->tune, reg);

sys/dev/i2c/tea5767.c

295

uint8_t reg[5];

sys/dev/i2c/tea5767.c

313

tea5767_set_properties(sc, reg);

sys/dev/i2c/tea5767.c

314

tea5767_write(sc, reg);

sys/dev/i2c/tea5767.c

322

uint8_t reg[5];

sys/dev/i2c/tea5767.c

326

tea5767_set_properties(sc, reg);

sys/dev/i2c/tea5767.c

329

reg[0] |= TEA5767_SEARCH;

sys/dev/i2c/tea5767.c

335

reg[2] |= TEA5767_SUD;

sys/dev/i2c/tea5767.c

337

reg[2] |= sc->tune.adc_stop_level; /* Stop level for search. */

sys/dev/i2c/tea5767.c

339

tea5767_write(sc, reg);

sys/dev/i2c/tea5767.c

341

memset(reg, 0, 5);

sys/dev/i2c/tea5767.c

343

while (tea5767_read(sc, reg), !(reg[0] & TEA5767_READY_FLAG)) {

sys/dev/i2c/titemp.c

188

titemp_read(struct titemp_softc *sc, uint8_t reg, uint8_t *val)

sys/dev/i2c/titemp.c

190

return iic_smbus_read_byte(sc->sc_i2c, sc->sc_addr, reg, val, 0);

sys/dev/i2c/tps65217pmic.c

763

tps65217pmic_reg_read(struct tps65217pmic_softc *sc, uint8_t reg)

sys/dev/i2c/tps65217pmic.c

768

wbuf[0] = reg;

sys/dev/i2c/tps65217pmic.c

782

uint8_t reg, uint8_t data)

sys/dev/i2c/tps65217pmic.c

786

wbuf[0] = reg;

sys/dev/i2c/tps65217pmic.c

797

uint8_t reg, uint8_t data)

sys/dev/i2c/tps65217pmic.c

799

uint8_t regpw = reg ^ TPS65217PMIC_PASSWORD_XOR;

sys/dev/i2c/tps65217pmic.c

805

tps65217pmic_reg_write(sc, reg, data);

sys/dev/i2c/tps65217pmic.c

807

tps65217pmic_reg_write(sc, reg, data);

sys/dev/i2c/tsllux.c

483

tsllux_read1(struct tsllux_softc *sc, uint8_t reg, uint8_t *valp)

sys/dev/i2c/tsllux.c

485

reg = (reg & REGMASK6x) | COMMAND6x_CMD;

sys/dev/i2c/tsllux.c

486

return (iic_smbus_read_byte(sc->sc_i2c, sc->sc_addr, reg, valp, 0));

sys/dev/i2c/tsllux.c

490

tsllux_read2(struct tsllux_softc *sc, uint8_t reg, uint16_t *valp)

sys/dev/i2c/tsllux.c

492

reg = (reg & REGMASK6x) | COMMAND6x_CMD | COMMAND6x_WORD;

sys/dev/i2c/tsllux.c

493

return (iic_smbus_read_word(sc->sc_i2c, sc->sc_addr, reg, valp, 0));

sys/dev/i2c/tsllux.c

497

tsllux_write1(struct tsllux_softc *sc, uint8_t reg, uint8_t val)

sys/dev/i2c/tsllux.c

499

reg = (reg & REGMASK6x) | COMMAND6x_CMD;

sys/dev/i2c/tsllux.c

500

return (iic_smbus_write_byte(sc->sc_i2c, sc->sc_addr, reg, val, 0));

sys/dev/i2c/tsllux.c

505

tsllux_write2(struct tsllux_softc *sc, uint8_t reg, uint16_t val)

sys/dev/i2c/tsllux.c

507

reg = (reg & REGMASK6x) | COMMAND6x_CMD | COMMAND6x_WORD;

sys/dev/i2c/tsllux.c

508

return (iic_smbus_write_word(sc->sc_i2c, sc->sc_addr, reg, val, 0));

sys/dev/i2c/twl4030.c

119

twl_read(struct twl_softc *sc, uint8_t mod, uint8_t reg, int flags)

sys/dev/i2c/twl4030.c

125

&reg, 1, &val, 1, flags);

sys/dev/i2c/twl4030.c

127

aprint_error_dev(sc->sc_dev, "error reading reg %#x: %d\n", reg, error);

sys/dev/i2c/twl4030.c

133

twl_write(struct twl_softc *sc, uint8_t mod, uint8_t reg, uint8_t val, int flags)

sys/dev/i2c/twl4030.c

138

buf[0] = reg;

sys/dev/i2c/twl4030.c

144

aprint_error_dev(sc->sc_dev, "error writing reg %#x: %d\n", reg, error);

sys/dev/i2c/twl4030.c

150

#define INT_READ(sc, reg) twl_read((sc), ADDR_INT, (reg), I2C_F_POLL)

sys/dev/i2c/twl4030.c

151

#define INT_WRITE(sc, reg, val) twl_write((sc), ADDR_INT, (reg), (val), I2C_F_POLL)

sys/dev/i2c/twl4030.c

153

#define POWER_READ(sc, reg) twl_read((sc), ADDR_POWER, (reg), I2C_F_POLL)

sys/dev/i2c/twl4030.c

154

#define POWER_WRITE(sc, reg, val) twl_write((sc), ADDR_POWER, (reg), (val), I2C_F_POLL)

sys/dev/i2c/w83795g.c

169

uint8_t conf, rev, reg, gpiom, en_reg;

sys/dev/i2c/w83795g.c

213

iic_smbus_read_byte(sc->sc_tag, sc->sc_addr, i % 256, &reg, 0);

sys/dev/i2c/w83795g.c

214

aprint_debug("%02x", reg);

sys/dev/i2c/xc3028.c

441

xc3028_read_2(struct xc3028 *xc, uint16_t reg, uint16_t *val)

sys/dev/i2c/xc3028.c

446

cmd[0] = reg >> 8;

sys/dev/i2c/xc3028.c

447

cmd[1] = reg & 0xff;

sys/dev/i2c/xc3028.c

472

xc3028_write_2(struct xc3028 *xc, uint16_t reg, uint16_t val)

sys/dev/i2c/xc3028.c

476

data[0] = reg >> 8;

sys/dev/i2c/xc3028.c

477

data[1] = reg & 0xff;

sys/dev/i2c/xc5k.c

196

xc5k_read_2(struct xc5k *xc, uint16_t reg, uint16_t *val)

sys/dev/i2c/xc5k.c

201

cmd[0] = reg >> 8;

sys/dev/i2c/xc5k.c

202

cmd[1] = reg & 0xff;

sys/dev/i2c/xc5k.c

226

xc5k_write_2(struct xc5k *xc, uint16_t reg, uint16_t val)

sys/dev/i2c/xc5k.c

232

data[0] = reg >> 8;

sys/dev/i2c/xc5k.c

233

data[1] = reg & 0xff;

sys/dev/i2c/zl10353.c

139

zl10353_read(struct zl10353 *zl, uint8_t reg, uint8_t *valp)

sys/dev/i2c/zl10353.c

147

rv = iic_exec(zl->zl_i2c, op, zl->zl_i2c_addr, &reg, 1, valp, 1, 0);

sys/dev/i2c/zl10353.c

154

zl10353_write(struct zl10353 *zl, uint8_t reg, uint8_t val)

sys/dev/i2c/zl10353.c

157

const uint8_t cmd[2] = { reg, val };

sys/dev/i2c/zl10353.c

176

uint8_t reg;

sys/dev/i2c/zl10353.c

196

if ((rv = zl10353_write(zl, reset[i].reg, reset[i].val)) != 0)

sys/dev/ic/aacvar.h

239

#define AAC_SETREG4(sc, reg, val) \

sys/dev/ic/aacvar.h

240

bus_space_write_4((sc)->sc_memt, (sc)->sc_memh, (reg), (val))

sys/dev/ic/aacvar.h

241

#define AAC_GETREG4(sc, reg) \

sys/dev/ic/aacvar.h

242

bus_space_read_4((sc)->sc_memt, (sc)->sc_memh, (reg))

sys/dev/ic/aacvar.h

243

#define AAC_SETREG2(sc, reg, val) \

sys/dev/ic/aacvar.h

244

bus_space_write_2((sc)->sc_memt, (sc)->sc_memh, (reg), (val))

sys/dev/ic/aacvar.h

245

#define AAC_GETREG2(sc, reg) \

sys/dev/ic/aacvar.h

246

bus_space_read_2((sc)->sc_memt, (sc)->sc_memh, (reg))

sys/dev/ic/aacvar.h

247

#define AAC_SETREG1(sc, reg, val) \

sys/dev/ic/aacvar.h

248

bus_space_write_1((sc)->sc_memt, (sc)->sc_memh, (reg), (val))

sys/dev/ic/aacvar.h

249

#define AAC_GETREG1(sc, reg) \

sys/dev/ic/aacvar.h

250

bus_space_read_1((sc)->sc_memt, (sc)->sc_memh, (reg))

sys/dev/ic/ac97.c

1038

if (si->reg != AC97_REG_RESET)

sys/dev/ic/ac97.c

1039

ac97_write(as, si->reg, as->shadow_reg[si->reg >> 1]);

sys/dev/ic/ac97.c

1120

ac97_read(as, si->reg, &value1);

sys/dev/ic/ac97.c

1124

ac97_write(as, si->reg, value2);

sys/dev/ic/ac97.c

1126

ac97_read(as, si->reg, &value3);

sys/dev/ic/ac97.c

1133

__func__, si->reg, si->bits));

sys/dev/ic/ac97.c

1134

ac97_write(as, si->reg, value1);

sys/dev/ic/ac97.c

1439

uint16_t xval, reg;

sys/dev/ic/ac97.c

1500

ac97_read(as, AC97_REG_EXT_MODEM_CTRL, &reg);

sys/dev/ic/ac97.c

1501

if ((reg & /*XXXval*/0xf) == /*XXXval*/0xf)

sys/dev/ic/ac97.c

1508

device_xname(sc_dev), reg);

sys/dev/ic/ac97.c

1514

ac97_read(as, AC97_REG_GPIO_CFG, &reg);

sys/dev/ic/ac97.c

1515

reg &= ~AC97_GPIO_LINE1_OH;

sys/dev/ic/ac97.c

1516

ac97_write(as, AC97_REG_GPIO_CFG, reg);

sys/dev/ic/ac97.c

1517

ac97_read(as, AC97_REG_GPIO_POLARITY, &reg);

sys/dev/ic/ac97.c

1518

reg &= ~AC97_GPIO_LINE1_OH;

sys/dev/ic/ac97.c

1519

ac97_write(as, AC97_REG_GPIO_POLARITY, reg);

sys/dev/ic/ac97.c

1536

ac97_read(as, AC97_REG_GPIO_CFG, &reg);

sys/dev/ic/ac97.c

1537

reg &= ~AC97_GPIO_LINE2_OH;

sys/dev/ic/ac97.c

1538

ac97_write(as, AC97_REG_GPIO_CFG, reg);

sys/dev/ic/ac97.c

1539

ac97_read(as, AC97_REG_GPIO_POLARITY, &reg);

sys/dev/ic/ac97.c

1540

reg &= ~AC97_GPIO_LINE2_OH;

sys/dev/ic/ac97.c

1541

ac97_write(as, AC97_REG_GPIO_POLARITY, reg);

sys/dev/ic/ac97.c

1732

spdif = si->req_feature == CHECK_SPDIF && si->reg == AC97_REG_EXT_AUDIO_CTRL;

sys/dev/ic/ac97.c

1739

ac97_read(as, si->reg, &val);

sys/dev/ic/ac97.c

1741

DPRINTFN(5, ("read(%x) = %x\n", si->reg, val));

sys/dev/ic/ac97.c

1751

if (si->reg == AC97_REG_RECORD_SELECT) {

sys/dev/ic/ac97.c

1755

} else if (si->reg == AC97_REG_SURR_MASTER) {

sys/dev/ic/ac97.c

1815

error = ac97_write(as, si->reg, (val & ~mask) | newval);

sys/dev/ic/ac97.c

1867

ac97_read(as, si->reg, &val);

sys/dev/ic/ac97.c

1869

DPRINTFN(5, ("read(%x) = %x\n", si->reg, val));

sys/dev/ic/ac97.c

2148

if (as->source_info[i].reg == AC97_REG_MASTER_VOLUME)

sys/dev/ic/ac97.c

2149

as->source_info[i].reg = AC97_REG_SURR_MASTER;

sys/dev/ic/ac97.c

2150

else if (as->source_info[i].reg == AC97_REG_SURR_MASTER)

sys/dev/ic/ac97.c

2151

as->source_info[i].reg = AC97_REG_MASTER_VOLUME;

sys/dev/ic/ac97.c

275

uint8_t reg;

sys/dev/ic/ac97.c

935

ac97_read(struct ac97_softc *as, uint8_t reg, uint16_t *val)

sys/dev/ic/ac97.c

940

(reg != AC97_REG_VENDOR_ID1 && reg != AC97_REG_VENDOR_ID2 &&

sys/dev/ic/ac97.c

941

reg != AC97_REG_RESET)) {

sys/dev/ic/ac97.c

942

*val = as->shadow_reg[reg >> 1];

sys/dev/ic/ac97.c

946

if (as->host_if->read(as->host_if->arg, reg, val)) {

sys/dev/ic/ac97.c

947

*val = as->shadow_reg[reg >> 1];

sys/dev/ic/ac97.c

952

ac97_write(struct ac97_softc *as, uint8_t reg, uint16_t val)

sys/dev/ic/ac97.c

957

as->shadow_reg[reg >> 1] = val;

sys/dev/ic/ac97.c

958

return as->host_if->write(as->host_if->arg, reg, val);

sys/dev/ic/ac97.c

963

as->shadow_reg[reg >> 1] = val;

sys/dev/ic/ac97.c

964

ret = as->host_if->write(as->host_if->arg, reg, val);

sys/dev/ic/ac97.c

965

as->host_if->read(as->host_if->arg, reg, &actual);

sys/dev/ic/ac97.c

966

if (val != actual && reg < 0x80) {

sys/dev/ic/ac97.c

968

ac97_register_names[reg / 2], val, actual);

sys/dev/ic/ac97.c

987

ac97_write(as, si->reg, si->default_value);

sys/dev/ic/ac97.c

992

ac97_write(as, si->reg, si->default_value);

sys/dev/ic/ac97reg.h

43

#define AC97_CAPS_ENHANCEMENT(reg) (((reg) >> 10) & 0x1f)

sys/dev/ic/ad1848.c

1104

u_char reg;

sys/dev/ic/ad1848.c

1108

reg = ad_read(sc, SP_INTERFACE_CONFIG);

sys/dev/ic/ad1848.c

1109

ad_write(sc, SP_INTERFACE_CONFIG, reg & ~PLAYBACK_ENABLE);

sys/dev/ic/ad1848.c

1118

u_char reg;

sys/dev/ic/ad1848.c

1122

reg = ad_read(sc, SP_INTERFACE_CONFIG);

sys/dev/ic/ad1848.c

1123

ad_write(sc, SP_INTERFACE_CONFIG, reg & ~CAPTURE_ENABLE);

sys/dev/ic/ad1848.c

233

ad_read(struct ad1848_softc *sc, int reg)

sys/dev/ic/ad1848.c

237

ADWRITE(sc, AD1848_IADDR, (reg & 0xff) | sc->MCE_bit);

sys/dev/ic/ad1848.c

244

ad_write(struct ad1848_softc *sc, int reg, int data)

sys/dev/ic/ad1848.c

247

ADWRITE(sc, AD1848_IADDR, (reg & 0xff) | sc->MCE_bit);

sys/dev/ic/ad1848.c

258

ad_xread(struct ad1848_softc *sc, int reg)

sys/dev/ic/ad1848.c

263

ADWRITE(sc, AD1848_IDATA, (reg | ALT_F3_XRAE) & 0xff);

sys/dev/ic/ad1848.c

270

ad_xwrite(struct ad1848_softc *sc, int reg, int val)

sys/dev/ic/ad1848.c

274

ADWRITE(sc, AD1848_IDATA, (reg | ALT_F3_XRAE) & 0xff);

sys/dev/ic/ad1848.c

468

u_char reg;

sys/dev/ic/ad1848.c

470

reg = ad_read(sc, mixer_channel_info[device].left_reg);

sys/dev/ic/ad1848.c

477

reg & ~DIGITAL_MIX1_ENABLE);

sys/dev/ic/ad1848.c

480

reg | MONO_OUTPUT_MUTE);

sys/dev/ic/ad1848.c

483

reg | 0x80);

sys/dev/ic/ad1848.c

487

reg | DIGITAL_MIX1_ENABLE);

sys/dev/ic/ad1848.c

492

reg & ~MONO_OUTPUT_MUTE);

sys/dev/ic/ad1848.c

495

reg & ~0x80);

sys/dev/ic/ad1848.c

501

reg = ad_read(sc, mixer_channel_info[device].right_reg);

sys/dev/ic/ad1848.c

504

ad_write(sc, mixer_channel_info[device].right_reg, reg | 0x80);

sys/dev/ic/ad1848.c

506

ad_write(sc, mixer_channel_info[device].right_reg, reg &~0x80);

sys/dev/ic/ad1848.c

515

u_char reg;

sys/dev/ic/ad1848.c

524

reg = ad_read(sc, info->left_reg) & (info->atten_mask);

sys/dev/ic/ad1848.c

526

reg |= ((atten & info->atten_bits) << 2);

sys/dev/ic/ad1848.c

528

reg |= ((atten & info->atten_bits));

sys/dev/ic/ad1848.c

530

ad_write(sc, info->left_reg, reg);

sys/dev/ic/ad1848.c

537

reg = ad_read(sc, info->right_reg);

sys/dev/ic/ad1848.c

538

reg &= info->atten_mask;

sys/dev/ic/ad1848.c

539

ad_write(sc, info->right_reg, (atten & info->atten_bits) | reg);

sys/dev/ic/ad1848.c

564

u_char reg, gain;

sys/dev/ic/ad1848.c

571

reg = ad_read(sc, SP_LEFT_INPUT_CONTROL);

sys/dev/ic/ad1848.c

572

reg &= INPUT_GAIN_MASK;

sys/dev/ic/ad1848.c

573

ad_write(sc, SP_LEFT_INPUT_CONTROL, (gain & 0x0f) | reg);

sys/dev/ic/ad1848.c

576

reg = ad_read(sc, SP_RIGHT_INPUT_CONTROL);

sys/dev/ic/ad1848.c

577

reg &= INPUT_GAIN_MASK;

sys/dev/ic/ad1848.c

578

ad_write(sc, SP_RIGHT_INPUT_CONTROL, (gain & 0x0f) | reg);

sys/dev/ic/ad1848.c

609

u_char reg;

sys/dev/ic/ad1848.c

615

reg = ad_read(sc, SP_LEFT_INPUT_CONTROL);

sys/dev/ic/ad1848.c

617

reg | INPUT_MIC_GAIN_ENABLE);

sys/dev/ic/ad1848.c

620

reg = ad_read(sc, SP_LEFT_INPUT_CONTROL);

sys/dev/ic/ad1848.c

622

reg & ~INPUT_MIC_GAIN_ENABLE);

sys/dev/ic/ad1848.c

831

u_char inp, reg;

sys/dev/ic/ad1848.c

846

reg = ad_read(sc, SP_LEFT_INPUT_CONTROL);

sys/dev/ic/ad1848.c

847

reg &= INPUT_SOURCE_MASK;

sys/dev/ic/ad1848.c

848

ad_write(sc, SP_LEFT_INPUT_CONTROL, (inp|reg));

sys/dev/ic/ad1848.c

850

reg = ad_read(sc, SP_RIGHT_INPUT_CONTROL);

sys/dev/ic/ad1848.c

851

reg &= INPUT_SOURCE_MASK;

sys/dev/ic/ad1848.c

852

ad_write(sc, SP_RIGHT_INPUT_CONTROL, (inp|reg));

sys/dev/ic/ad1848.c

869

u_char reg;

sys/dev/ic/ad1848.c

878

reg = ad_read(sc, SP_PIN_CONTROL);

sys/dev/ic/ad1848.c

879

ad_write(sc, SP_PIN_CONTROL, reg | INTERRUPT_ENABLE);

sys/dev/ic/ad1848.c

897

u_char reg;

sys/dev/ic/ad1848.c

906

reg = ad_read(sc, SP_PIN_CONTROL);

sys/dev/ic/ad1848.c

907

ad_write(sc, SP_PIN_CONTROL, reg & ~INTERRUPT_ENABLE);

sys/dev/ic/ahcisatavar.h

113

#define AHCI_READ(sc, reg) bus_space_read_4((sc)->sc_ahcit, \

sys/dev/ic/ahcisatavar.h

114

(sc)->sc_ahcih, (reg))

sys/dev/ic/ahcisatavar.h

115

#define AHCI_WRITE(sc, reg, val) bus_space_write_4((sc)->sc_ahcit, \

sys/dev/ic/ahcisatavar.h

116

(sc)->sc_ahcih, (reg), (val))

sys/dev/ic/aic6915.c

102

reg);

sys/dev/ic/aic6915.c

107

return (bus_space_read_4(sc->sc_st, sc->sc_sh, reg));

sys/dev/ic/aic6915.c

111

sf_reg_write(struct sf_softc *sc, bus_addr_t reg, uint32_t val)

sys/dev/ic/aic6915.c

116

reg);

sys/dev/ic/aic6915.c

1177

uint32_t reg;

sys/dev/ic/aic6915.c

1179

reg = sf_genreg_read(sc, SF_EEPROM_BASE + (offset & ~3));

sys/dev/ic/aic6915.c

1181

return ((reg >> (8 * (offset & 3))) & 0xff);

sys/dev/ic/aic6915.c

122

bus_space_write_4(sc->sc_st, sc->sc_sh, reg, val);

sys/dev/ic/aic6915.c

1246

uint32_t hash, slot, reg;

sys/dev/ic/aic6915.c

125

#define sf_genreg_read(sc, reg) \

sys/dev/ic/aic6915.c

1251

reg = sf_genreg_read(sc, SF_HASH_BASE + (slot * 0x10));

sys/dev/ic/aic6915.c

1252

reg |= 1 << (hash & 0xf);

sys/dev/ic/aic6915.c

1253

sf_genreg_write(sc, SF_HASH_BASE + (slot * 0x10), reg);

sys/dev/ic/aic6915.c

126

sf_reg_read((sc), (reg) + SF_GENREG_OFFSET)

sys/dev/ic/aic6915.c

127

#define sf_genreg_write(sc, reg, val) \

sys/dev/ic/aic6915.c

128

sf_reg_write((sc), (reg) + SF_GENREG_OFFSET, (val))

sys/dev/ic/aic6915.c

1357

sf_mii_read(device_t self, int phy, int reg, uint16_t *data)

sys/dev/ic/aic6915.c

1364

v = sf_genreg_read(sc, SF_MII_PHY_REG(phy, reg));

sys/dev/ic/aic6915.c

1386

sf_mii_write(device_t self, int phy, int reg, uint16_t val)

sys/dev/ic/aic6915.c

1391

sf_genreg_write(sc, SF_MII_PHY_REG(phy, reg), val);

sys/dev/ic/aic6915.c

1394

if ((sf_genreg_read(sc, SF_MII_PHY_REG(phy, reg)) &

sys/dev/ic/aic6915.c

91

#define sf_funcreg_read(sc, reg) \

sys/dev/ic/aic6915.c

92

bus_space_read_4((sc)->sc_st, (sc)->sc_sh_func, (reg))

sys/dev/ic/aic6915.c

93

#define sf_funcreg_write(sc, reg, val) \

sys/dev/ic/aic6915.c

94

bus_space_write_4((sc)->sc_st, (sc)->sc_sh_func, (reg), (val))

sys/dev/ic/aic6915.c

97

sf_reg_read(struct sf_softc *sc, bus_addr_t reg)

sys/dev/ic/aic79xx_osm.h

479

ahd_pci_read_config(ahd_dev_softc_t pci, int reg, int width)

sys/dev/ic/aic79xx_osm.h

481

return (pci_read_config(pci, reg, width));

sys/dev/ic/aic79xx_osm.h

485

ahd_pci_write_config(ahd_dev_softc_t pci, int reg, uint32_t value, int width)

sys/dev/ic/aic79xx_osm.h

487

pci_write_config(pci, reg, value, width);

sys/dev/ic/aic7xxx_osm.h

459

ahc_pci_read_config(ahc_dev_softc_t pci, int reg, int width)

sys/dev/ic/aic7xxx_osm.h

461

return (pci_read_config(pci, reg, width));

sys/dev/ic/aic7xxx_osm.h

465

ahc_pci_write_config(ahc_dev_softc_t pci, int reg, uint32_t value, int width)

sys/dev/ic/aic7xxx_osm.h

467

pci_write_config(pci, reg, value, width);

sys/dev/ic/am7930.c

157

am7930_iwrite(struct am7930_softc *sc, int reg, uint8_t val)

sys/dev/ic/am7930.c

160

AM7930_DWRITE(sc, AM7930_DREG_CR, reg);

sys/dev/ic/am7930.c

165

am7930_iread(struct am7930_softc *sc, int reg)

sys/dev/ic/am7930.c

168

AM7930_DWRITE(sc, AM7930_DREG_CR, reg);

sys/dev/ic/am7930.c

173

am7930_iwrite16(struct am7930_softc *sc, int reg, uint16_t val)

sys/dev/ic/am7930.c

176

AM7930_DWRITE(sc, AM7930_DREG_CR, reg);

sys/dev/ic/am7930.c

182

am7930_iread16(struct am7930_softc *sc, int reg)

sys/dev/ic/am7930.c

186

AM7930_DWRITE(sc, AM7930_DREG_CR, reg);

sys/dev/ic/anvar.h

50

#define CSR_WRITE_2(sc, reg, val) \

sys/dev/ic/anvar.h

51

bus_space_write_2(sc->sc_iot, sc->sc_ioh, reg, val)

sys/dev/ic/anvar.h

53

#define CSR_READ_2(sc, reg) \

sys/dev/ic/anvar.h

54

bus_space_read_2(sc->sc_iot, sc->sc_ioh, reg)

sys/dev/ic/anvar.h

61

#define CSR_WRITE_MULTI_STREAM_2(sc, reg, val, count) \

sys/dev/ic/anvar.h

62

bus_space_write_multi_stream_2(sc->sc_iot, sc->sc_ioh, reg, val, count)

sys/dev/ic/anvar.h

63

#define CSR_READ_MULTI_STREAM_2(sc, reg, buf, count) \

sys/dev/ic/anvar.h

64

bus_space_read_multi_stream_2(sc->sc_iot, sc->sc_ioh, reg, buf, count)

sys/dev/ic/apple_smc.c

165

apple_smc_bus_read_1(struct apple_smc_tag *smc, bus_size_t reg)

sys/dev/ic/apple_smc.c

168

return bus_space_read_1(smc->smc_bst, smc->smc_bsh, reg);

sys/dev/ic/apple_smc.c

172

apple_smc_bus_write_1(struct apple_smc_tag *smc, bus_size_t reg, uint8_t v)

sys/dev/ic/apple_smc.c

175

bus_space_write_1(smc->smc_bst, smc->smc_bsh, reg, v);

sys/dev/ic/apple_smc.c

208

apple_smc_write(struct apple_smc_tag *smc, bus_size_t reg, uint8_t byte)

sys/dev/ic/apple_smc.c

219

apple_smc_bus_write_1(smc, reg, byte);

sys/dev/ic/apple_smc.c

228

apple_smc_bus_write_1(smc, reg, byte);

sys/dev/ic/arn5008.c

1034

uint32_t reg;

sys/dev/ic/arn5008.c

1039

reg = AR_READ(sc, AR_ISR_S0_S);

sys/dev/ic/arn5008.c

1040

mask |= MS(reg, AR_ISR_S0_QCU_TXOK);

sys/dev/ic/arn5008.c

1041

mask |= MS(reg, AR_ISR_S0_QCU_TXDESC);

sys/dev/ic/arn5008.c

1043

reg = AR_READ(sc, AR_ISR_S1_S);

sys/dev/ic/arn5008.c

1044

mask |= MS(reg, AR_ISR_S1_QCU_TXERR);

sys/dev/ic/arn5008.c

1045

mask |= MS(reg, AR_ISR_S1_QCU_TXEOL);

sys/dev/ic/arn5008.c

1678

uint32_t reg;

sys/dev/ic/arn5008.c

1680

reg = IEEE80211_IS_CHAN_2GHZ(c) ?

sys/dev/ic/arn5008.c

1683

reg |= IEEE80211_IS_CHAN_2GHZ(c) ?

sys/dev/ic/arn5008.c

1688

reg |= AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE;

sys/dev/ic/arn5008.c

1690

AR_WRITE(sc, AR_PHY_MODE, reg);

sys/dev/ic/arn5008.c

1770

uint32_t coeff, exp, man, reg;

sys/dev/ic/arn5008.c

1777

reg = AR_READ(sc, AR_PHY_TIMING3);

sys/dev/ic/arn5008.c

1778

reg = RW(reg, AR_PHY_TIMING3_DSC_EXP, exp);

sys/dev/ic/arn5008.c

1779

reg = RW(reg, AR_PHY_TIMING3_DSC_MAN, man);

sys/dev/ic/arn5008.c

1780

AR_WRITE(sc, AR_PHY_TIMING3, reg);

sys/dev/ic/arn5008.c

1787

reg = AR_READ(sc, AR_PHY_HALFGI);

sys/dev/ic/arn5008.c

1788

reg = RW(reg, AR_PHY_HALFGI_DSC_EXP, exp);

sys/dev/ic/arn5008.c

1789

reg = RW(reg, AR_PHY_HALFGI_DSC_MAN, man);

sys/dev/ic/arn5008.c

1790

AR_WRITE(sc, AR_PHY_HALFGI, reg);

sys/dev/ic/arn5008.c

1861

uint32_t reg;

sys/dev/ic/arn5008.c

1865

reg = AR_READ(sc, AR_PHY_CCA(i));

sys/dev/ic/arn5008.c

1867

nf[i] = MS(reg, AR9280_PHY_MINCCA_PWR);

sys/dev/ic/arn5008.c

1869

nf[i] = MS(reg, AR_PHY_MINCCA_PWR);

sys/dev/ic/arn5008.c

1872

reg = AR_READ(sc, AR_PHY_EXT_CCA(i));

sys/dev/ic/arn5008.c

1874

nf_ext[i] = MS(reg, AR9280_PHY_EXT_MINCCA_PWR);

sys/dev/ic/arn5008.c

1876

nf_ext[i] = MS(reg, AR_PHY_EXT_MINCCA_PWR);

sys/dev/ic/arn5008.c

1887

uint32_t reg;

sys/dev/ic/arn5008.c

1891

reg = AR_READ(sc, AR_PHY_CCA(i));

sys/dev/ic/arn5008.c

1892

reg = RW(reg, AR_PHY_MAXCCA_PWR, nf[i]);

sys/dev/ic/arn5008.c

1893

AR_WRITE(sc, AR_PHY_CCA(i), reg);

sys/dev/ic/arn5008.c

1895

reg = AR_READ(sc, AR_PHY_EXT_CCA(i));

sys/dev/ic/arn5008.c

1896

reg = RW(reg, AR_PHY_EXT_MAXCCA_PWR, nf_ext[i]);

sys/dev/ic/arn5008.c

1897

AR_WRITE(sc, AR_PHY_EXT_CCA(i), reg);

sys/dev/ic/arn5008.c

1986

uint32_t mode, reg;

sys/dev/ic/arn5008.c

1989

reg = AR_READ(sc, AR_PHY_TIMING_CTRL4_0);

sys/dev/ic/arn5008.c

1991

reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX, log);

sys/dev/ic/arn5008.c

1992

AR_WRITE(sc, AR_PHY_TIMING_CTRL4_0, reg);

sys/dev/ic/arn5008.c

2030

uint32_t reg, i_coff_denom, q_coff_denom;

sys/dev/ic/arn5008.c

2078

reg = AR_READ(sc, AR_PHY_TIMING_CTRL4(i));

sys/dev/ic/arn5008.c

2079

reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF, i_coff);

sys/dev/ic/arn5008.c

2080

reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, q_coff);

sys/dev/ic/arn5008.c

2081

AR_WRITE(sc, AR_PHY_TIMING_CTRL4(i), reg);

sys/dev/ic/arn5008.c

2098

uint32_t reg, gain_mismatch_i, gain_mismatch_q;

sys/dev/ic/arn5008.c

2129

reg = AR_READ(sc, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));

sys/dev/ic/arn5008.c

2130

reg = RW(reg, AR_PHY_NEW_ADC_DC_GAIN_IGAIN, gain_mismatch_i);

sys/dev/ic/arn5008.c

2131

reg = RW(reg, AR_PHY_NEW_ADC_DC_GAIN_QGAIN, gain_mismatch_q);

sys/dev/ic/arn5008.c

2132

AR_WRITE(sc, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), reg);

sys/dev/ic/arn5008.c

2150

uint32_t reg;

sys/dev/ic/arn5008.c

2182

reg = AR_READ(sc, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));

sys/dev/ic/arn5008.c

2183

reg = RW(reg, AR_PHY_NEW_ADC_DC_GAIN_QDC,

sys/dev/ic/arn5008.c

2185

reg = RW(reg, AR_PHY_NEW_ADC_DC_GAIN_IDC,

sys/dev/ic/arn5008.c

2187

AR_WRITE(sc, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), reg);

sys/dev/ic/arn5008.c

2257

uint32_t mask[4], reg;

sys/dev/ic/arn5008.c

2293

reg =

sys/dev/ic/arn5008.c

2298

AR_WRITE(sc, AR_PHY_BIN_MASK_1, reg);

sys/dev/ic/arn5008.c

2299

AR_WRITE(sc, AR_PHY_VIT_MASK2_M_46_61, reg);

sys/dev/ic/arn5008.c

2302

reg = m[31] << 28 | m[32] << 26 | m[33] << 24 |

sys/dev/ic/arn5008.c

2306

AR_WRITE(sc, AR_PHY_BIN_MASK_2, reg);

sys/dev/ic/arn5008.c

2307

AR_WRITE(sc, AR_PHY_VIT_MASK2_M_31_45, reg);

sys/dev/ic/arn5008.c

2310

reg =

sys/dev/ic/arn5008.c

2315

AR_WRITE(sc, AR_PHY_BIN_MASK_3, reg);

sys/dev/ic/arn5008.c

2316

AR_WRITE(sc, AR_PHY_VIT_MASK2_M_16_30, reg);

sys/dev/ic/arn5008.c

2318

reg =

sys/dev/ic/arn5008.c

2323

AR_WRITE(sc, AR_PHY_MASK_CTL, reg);

sys/dev/ic/arn5008.c

2324

AR_WRITE(sc, AR_PHY_VIT_MASK2_M_00_15, reg);

sys/dev/ic/arn5008.c

2326

reg = p[15] << 28 | p[14] << 26 | p[13] << 24 |

sys/dev/ic/arn5008.c

2330

AR_WRITE(sc, AR_PHY_BIN_MASK2_1, reg);

sys/dev/ic/arn5008.c

2331

AR_WRITE(sc, AR_PHY_VIT_MASK2_P_15_01, reg);

sys/dev/ic/arn5008.c

2333

reg = p[30] << 28 | p[29] << 26 | p[28] << 24 |

sys/dev/ic/arn5008.c

2337

AR_WRITE(sc, AR_PHY_BIN_MASK2_2, reg);

sys/dev/ic/arn5008.c

2338

AR_WRITE(sc, AR_PHY_VIT_MASK2_P_30_16, reg);

sys/dev/ic/arn5008.c

2340

reg = p[45] << 28 | p[44] << 26 | p[43] << 24 |

sys/dev/ic/arn5008.c

2344

AR_WRITE(sc, AR_PHY_BIN_MASK2_3, reg);

sys/dev/ic/arn5008.c

2345

AR_WRITE(sc, AR_PHY_VIT_MASK2_P_45_31, reg);

sys/dev/ic/arn5008.c

2347

reg =

sys/dev/ic/arn5008.c

2352

AR_WRITE(sc, AR_PHY_BIN_MASK2_4, reg);

sys/dev/ic/arn5008.c

2353

AR_WRITE(sc, AR_PHY_VIT_MASK2_P_61_46, reg);

sys/dev/ic/arn5008.c

2364

uint32_t reg;

sys/dev/ic/arn5008.c

2465

reg = AR_READ(sc, AR_PCU_MISC_MODE2);

sys/dev/ic/arn5008.c

2467

reg &= ~AR_PCU_MISC_MODE2_HWWAR1;

sys/dev/ic/arn5008.c

2469

reg &= ~AR_PCU_MISC_MODE2_HWWAR2;

sys/dev/ic/arn5008.c

2470

AR_WRITE(sc, AR_PCU_MISC_MODE2, reg);

sys/dev/ic/arn5008.c

2702

uint32_t reg;

sys/dev/ic/arn5008.c

2704

reg = AR_READ(sc, AR_PHY_DESIRED_SZ);

sys/dev/ic/arn5008.c

2705

reg = RW(reg, AR_PHY_DESIRED_SZ_TOT_DES, high ? -62 : -55);

sys/dev/ic/arn5008.c

2706

AR_WRITE(sc, AR_PHY_DESIRED_SZ, reg);

sys/dev/ic/arn5008.c

2708

reg = AR_READ(sc, AR_PHY_AGC_CTL1);

sys/dev/ic/arn5008.c

2709

reg = RW(reg, AR_PHY_AGC_CTL1_COARSE_LOW, high ? -70 : -64);

sys/dev/ic/arn5008.c

2710

reg = RW(reg, AR_PHY_AGC_CTL1_COARSE_HIGH, high ? -12 : -14);

sys/dev/ic/arn5008.c

2711

AR_WRITE(sc, AR_PHY_AGC_CTL1, reg);

sys/dev/ic/arn5008.c

2713

reg = AR_READ(sc, AR_PHY_FIND_SIG);

sys/dev/ic/arn5008.c

2714

reg = RW(reg, AR_PHY_FIND_SIG_FIRPWR, high ? -80 : -78);

sys/dev/ic/arn5008.c

2715

AR_WRITE(sc, AR_PHY_FIND_SIG, reg);

sys/dev/ic/arn5008.c

2723

uint32_t reg;

sys/dev/ic/arn5008.c

2725

reg = AR_READ(sc, AR_PHY_SFCORR_LOW);

sys/dev/ic/arn5008.c

2726

reg = RW(reg, AR_PHY_SFCORR_LOW_M1_THRESH_LOW, 50);

sys/dev/ic/arn5008.c

2727

reg = RW(reg, AR_PHY_SFCORR_LOW_M2_THRESH_LOW, 40);

sys/dev/ic/arn5008.c

2728

reg = RW(reg, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, 48);

sys/dev/ic/arn5008.c

2729

AR_WRITE(sc, AR_PHY_SFCORR_LOW, reg);

sys/dev/ic/arn5008.c

2731

reg = AR_READ(sc, AR_PHY_SFCORR);

sys/dev/ic/arn5008.c

2732

reg = RW(reg, AR_PHY_SFCORR_M1_THRESH, 77);

sys/dev/ic/arn5008.c

2733

reg = RW(reg, AR_PHY_SFCORR_M2_THRESH, 64);

sys/dev/ic/arn5008.c

2734

reg = RW(reg, AR_PHY_SFCORR_M2COUNT_THR, 16);

sys/dev/ic/arn5008.c

2735

AR_WRITE(sc, AR_PHY_SFCORR, reg);

sys/dev/ic/arn5008.c

2737

reg = AR_READ(sc, AR_PHY_SFCORR_EXT);

sys/dev/ic/arn5008.c

2738

reg = RW(reg, AR_PHY_SFCORR_EXT_M1_THRESH_LOW, 50);

sys/dev/ic/arn5008.c

2739

reg = RW(reg, AR_PHY_SFCORR_EXT_M2_THRESH_LOW, 40);

sys/dev/ic/arn5008.c

2740

reg = RW(reg, AR_PHY_SFCORR_EXT_M1_THRESH, 77);

sys/dev/ic/arn5008.c

2741

reg = RW(reg, AR_PHY_SFCORR_EXT_M2_THRESH, 64);

sys/dev/ic/arn5008.c

2742

AR_WRITE(sc, AR_PHY_SFCORR_EXT, reg);

sys/dev/ic/arn5008.c

275

uint32_t reg;

sys/dev/ic/arn5008.c

2752

uint32_t reg;

sys/dev/ic/arn5008.c

2754

reg = AR_READ(sc, AR_PHY_SFCORR_LOW);

sys/dev/ic/arn5008.c

2755

reg = RW(reg, AR_PHY_SFCORR_LOW_M1_THRESH_LOW, 127);

sys/dev/ic/arn5008.c

2756

reg = RW(reg, AR_PHY_SFCORR_LOW_M2_THRESH_LOW, 127);

sys/dev/ic/arn5008.c

2757

reg = RW(reg, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, 63);

sys/dev/ic/arn5008.c

2758

AR_WRITE(sc, AR_PHY_SFCORR_LOW, reg);

sys/dev/ic/arn5008.c

2760

reg = AR_READ(sc, AR_PHY_SFCORR);

sys/dev/ic/arn5008.c

2761

reg = RW(reg, AR_PHY_SFCORR_M1_THRESH, 127);

sys/dev/ic/arn5008.c

2762

reg = RW(reg, AR_PHY_SFCORR_M2_THRESH, 127);

sys/dev/ic/arn5008.c

2763

reg = RW(reg, AR_PHY_SFCORR_M2COUNT_THR, 31);

sys/dev/ic/arn5008.c

2764

AR_WRITE(sc, AR_PHY_SFCORR, reg);

sys/dev/ic/arn5008.c

2766

reg = AR_READ(sc, AR_PHY_SFCORR_EXT);

sys/dev/ic/arn5008.c

2767

reg = RW(reg, AR_PHY_SFCORR_EXT_M1_THRESH_LOW, 127);

sys/dev/ic/arn5008.c

2768

reg = RW(reg, AR_PHY_SFCORR_EXT_M2_THRESH_LOW, 127);

sys/dev/ic/arn5008.c

2769

reg = RW(reg, AR_PHY_SFCORR_EXT_M1_THRESH, 127);

sys/dev/ic/arn5008.c

2770

reg = RW(reg, AR_PHY_SFCORR_EXT_M2_THRESH, 127);

sys/dev/ic/arn5008.c

2771

AR_WRITE(sc, AR_PHY_SFCORR_EXT, reg);

sys/dev/ic/arn5008.c

278

reg = AR_READ(sc, AR_EEPROM_OFFSET(addr));

sys/dev/ic/arn5008.c

2781

uint32_t reg;

sys/dev/ic/arn5008.c

2783

reg = AR_READ(sc, AR_PHY_CCK_DETECT);

sys/dev/ic/arn5008.c

2784

reg = RW(reg, AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK, high ? 6 : 8);

sys/dev/ic/arn5008.c

2785

AR_WRITE(sc, AR_PHY_CCK_DETECT, reg);

sys/dev/ic/arn5008.c

2792

uint32_t reg;

sys/dev/ic/arn5008.c

2794

reg = AR_READ(sc, AR_PHY_FIND_SIG);

sys/dev/ic/arn5008.c

2795

reg = RW(reg, AR_PHY_FIND_SIG_FIRSTEP, level * 4);

sys/dev/ic/arn5008.c

2796

AR_WRITE(sc, AR_PHY_FIND_SIG, reg);

sys/dev/ic/arn5008.c

280

reg = AR_READ(sc, AR_EEPROM_STATUS_DATA);

sys/dev/ic/arn5008.c

2803

uint32_t reg;

sys/dev/ic/arn5008.c

2805

reg = AR_READ(sc, AR_PHY_TIMING5);

sys/dev/ic/arn5008.c

2806

reg = RW(reg, AR_PHY_TIMING5_CYCPWR_THR1, (level + 1) * 2);

sys/dev/ic/arn5008.c

2807

AR_WRITE(sc, AR_PHY_TIMING5, reg);

sys/dev/ic/arn5008.c

281

if (!(reg & (AR_EEPROM_STATUS_DATA_BUSY |

sys/dev/ic/arn5008.c

283

*val = MS(reg, AR_EEPROM_STATUS_DATA_VAL);

sys/dev/ic/arn5008.c

376

uint32_t reg;

sys/dev/ic/arn5008.c

385

reg = AR_READ(sc, AR7010_GPIO_OUT);

sys/dev/ic/arn5008.c

387

reg |= 1 << pin;

sys/dev/ic/arn5008.c

389

reg &= ~(1 << pin);

sys/dev/ic/arn5008.c

390

AR_WRITE(sc, AR7010_GPIO_OUT, reg);

sys/dev/ic/arn5008.c

393

reg = AR_READ(sc, AR_GPIO_IN_OUT);

sys/dev/ic/arn5008.c

395

reg |= 1 << pin;

sys/dev/ic/arn5008.c

397

reg &= ~(1 << pin);

sys/dev/ic/arn5008.c

398

AR_WRITE(sc, AR_GPIO_IN_OUT, reg);

sys/dev/ic/arn5008.c

406

uint32_t reg;

sys/dev/ic/arn5008.c

413

reg = AR_READ(sc, AR_GPIO_OE_OUT);

sys/dev/ic/arn5008.c

414

reg &= ~(AR_GPIO_OE_OUT_DRV_M << (pin * 2));

sys/dev/ic/arn5008.c

415

reg |= AR_GPIO_OE_OUT_DRV_NO << (pin * 2);

sys/dev/ic/arn5008.c

416

AR_WRITE(sc, AR_GPIO_OE_OUT, reg);

sys/dev/ic/arn5008.c

424

uint32_t reg;

sys/dev/ic/arn5008.c

436

reg = AR_READ(sc, AR_GPIO_OUTPUT_MUX(mux));

sys/dev/ic/arn5008.c

438

reg = (reg & ~0x1f0) | (reg & 0x1f0) << 1;

sys/dev/ic/arn5008.c

439

reg &= ~(0x1f << (off * 5));

sys/dev/ic/arn5008.c

440

reg |= (type & 0x1f) << (off * 5);

sys/dev/ic/arn5008.c

441

AR_WRITE(sc, AR_GPIO_OUTPUT_MUX(mux), reg);

sys/dev/ic/arn5008.c

443

reg = AR_READ(sc, AR_GPIO_OE_OUT);

sys/dev/ic/arn5008.c

444

reg &= ~(AR_GPIO_OE_OUT_DRV_M << (pin * 2));

sys/dev/ic/arn5008.c

445

reg |= AR_GPIO_OE_OUT_DRV_ALL << (pin * 2);

sys/dev/ic/arn5008.c

446

AR_WRITE(sc, AR_GPIO_OE_OUT, reg);

sys/dev/ic/arn5008.c

453

uint32_t reg;

sys/dev/ic/arn5008.c

457

reg = AR_READ(sc, AR_GPIO_INPUT_MUX2);

sys/dev/ic/arn5008.c

458

reg = RW(reg, AR_GPIO_INPUT_MUX2_RFSILENT, 0);

sys/dev/ic/arn5008.c

459

AR_WRITE(sc, AR_GPIO_INPUT_MUX2, reg);

sys/dev/ic/arn5008reg.h

47

#define AR_IS_ANALOG_REG(reg) ((reg) >= 0x7800 && (reg) <= 0x78b4)

sys/dev/ic/arn5416.c

166

uint32_t phy, reg;

sys/dev/ic/arn5416.c

183

reg = AR_READ(sc, AR_PHY_CCK_TX_CTRL);

sys/dev/ic/arn5416.c

185

reg |= AR_PHY_CCK_TX_CTRL_JAPAN;

sys/dev/ic/arn5416.c

187

reg &= ~AR_PHY_CCK_TX_CTRL_JAPAN;

sys/dev/ic/arn5416.c

188

AR_WRITE(sc, AR_PHY_CCK_TX_CTRL, reg);

sys/dev/ic/arn5416.c

229

uint32_t reg, offset;

sys/dev/ic/arn5416.c

247

reg = AR_READ(sc, AR_PHY_TIMING_CTRL4_0 + offset);

sys/dev/ic/arn5416.c

248

reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF,

sys/dev/ic/arn5416.c

250

reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF,

sys/dev/ic/arn5416.c

252

AR_WRITE(sc, AR_PHY_TIMING_CTRL4_0 + offset, reg);

sys/dev/ic/arn5416.c

258

reg = AR_READ(sc, AR_PHY_GAIN_2GHZ + offset);

sys/dev/ic/arn5416.c

259

reg = RW(reg, AR_PHY_GAIN_2GHZ_BSW_MARGIN,

sys/dev/ic/arn5416.c

261

reg = RW(reg, AR_PHY_GAIN_2GHZ_BSW_ATTEN,

sys/dev/ic/arn5416.c

263

AR_WRITE(sc, AR_PHY_GAIN_2GHZ + offset, reg);

sys/dev/ic/arn5416.c

269

reg = AR_READ(sc, AR_PHY_RXGAIN + offset);

sys/dev/ic/arn5416.c

270

reg = RW(reg, AR_PHY_RXGAIN_TXRX_ATTEN, txRxAtten);

sys/dev/ic/arn5416.c

271

AR_WRITE(sc, AR_PHY_RXGAIN + offset, reg);

sys/dev/ic/arn5416.c

273

reg = AR_READ(sc, AR_PHY_GAIN_2GHZ + offset);

sys/dev/ic/arn5416.c

274

reg = RW(reg, AR_PHY_GAIN_2GHZ_RXTX_MARGIN,

sys/dev/ic/arn5416.c

276

AR_WRITE(sc, AR_PHY_GAIN_2GHZ + offset, reg);

sys/dev/ic/arn5416.c

278

reg = AR_READ(sc, AR_PHY_SETTLING);

sys/dev/ic/arn5416.c

279

reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->switchSettling);

sys/dev/ic/arn5416.c

280

AR_WRITE(sc, AR_PHY_SETTLING, reg);

sys/dev/ic/arn5416.c

282

reg = AR_READ(sc, AR_PHY_DESIRED_SZ);

sys/dev/ic/arn5416.c

283

reg = RW(reg, AR_PHY_DESIRED_SZ_ADC, modal->adcDesiredSize);

sys/dev/ic/arn5416.c

284

reg = RW(reg, AR_PHY_DESIRED_SZ_PGA, modal->pgaDesiredSize);

sys/dev/ic/arn5416.c

285

AR_WRITE(sc, AR_PHY_DESIRED_SZ, reg);

sys/dev/ic/arn5416.c

287

reg = SM(AR_PHY_RF_CTL4_TX_END_XPAA_OFF, modal->txEndToXpaOff);

sys/dev/ic/arn5416.c

288

reg |= SM(AR_PHY_RF_CTL4_TX_END_XPAB_OFF, modal->txEndToXpaOff);

sys/dev/ic/arn5416.c

289

reg |= SM(AR_PHY_RF_CTL4_FRAME_XPAA_ON, modal->txFrameToXpaOn);

sys/dev/ic/arn5416.c

290

reg |= SM(AR_PHY_RF_CTL4_FRAME_XPAB_ON, modal->txFrameToXpaOn);

sys/dev/ic/arn5416.c

291

AR_WRITE(sc, AR_PHY_RF_CTL4, reg);

sys/dev/ic/arn5416.c

293

reg = AR_READ(sc, AR_PHY_RF_CTL3);

sys/dev/ic/arn5416.c

294

reg = RW(reg, AR_PHY_TX_END_TO_A2_RX_ON, modal->txEndToRxOn);

sys/dev/ic/arn5416.c

295

AR_WRITE(sc, AR_PHY_RF_CTL3, reg);

sys/dev/ic/arn5416.c

297

reg = AR_READ(sc, AR_PHY_CCA(0));

sys/dev/ic/arn5416.c

298

reg = RW(reg, AR_PHY_CCA_THRESH62, modal->thresh62);

sys/dev/ic/arn5416.c

299

AR_WRITE(sc, AR_PHY_CCA(0), reg);

sys/dev/ic/arn5416.c

301

reg = AR_READ(sc, AR_PHY_EXT_CCA(0));

sys/dev/ic/arn5416.c

302

reg = RW(reg, AR_PHY_EXT_CCA_THRESH62, modal->thresh62);

sys/dev/ic/arn5416.c

303

AR_WRITE(sc, AR_PHY_EXT_CCA(0), reg);

sys/dev/ic/arn5416.c

306

reg = AR_READ(sc, AR_PHY_RF_CTL2);

sys/dev/ic/arn5416.c

307

reg = RW(reg, AR_PHY_TX_END_DATA_START,

sys/dev/ic/arn5416.c

309

reg = RW(reg, AR_PHY_TX_END_PA_ON, modal->txFrameToPaOn);

sys/dev/ic/arn5416.c

310

AR_WRITE(sc, AR_PHY_RF_CTL2, reg);

sys/dev/ic/arn5416.c

315

reg = AR_READ(sc, AR_PHY_SETTLING);

sys/dev/ic/arn5416.c

316

reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->swSettleHt40);

sys/dev/ic/arn5416.c

317

AR_WRITE(sc, AR_PHY_SETTLING, reg);

sys/dev/ic/arn5416.c

425

uint32_t reg, offset;

sys/dev/ic/arn5416.c

452

reg = AR_READ(sc, AR_PHY_TPCRG1);

sys/dev/ic/arn5416.c

453

reg = RW(reg, AR_PHY_TPCRG1_NUM_PD_GAIN, nxpdgains - 1);

sys/dev/ic/arn5416.c

454

reg = RW(reg, AR_PHY_TPCRG1_PD_GAIN_1, xpdgains[0]);

sys/dev/ic/arn5416.c

455

reg = RW(reg, AR_PHY_TPCRG1_PD_GAIN_2, xpdgains[1]);

sys/dev/ic/arn5416.c

456

reg = RW(reg, AR_PHY_TPCRG1_PD_GAIN_3, xpdgains[2]);

sys/dev/ic/arn5416.c

457

AR_WRITE(sc, AR_PHY_TPCRG1, reg);

sys/dev/ic/arn5416.c

473

reg = AR_READ(sc, AR_PHY_TX_PWRCTRL6_0);

sys/dev/ic/arn5416.c

474

reg = RW(reg, AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3);

sys/dev/ic/arn5416.c

475

AR_WRITE(sc, AR_PHY_TX_PWRCTRL6_0, reg);

sys/dev/ic/arn5416.c

477

reg = AR_READ(sc, AR_PHY_TX_PWRCTRL6_1);

sys/dev/ic/arn5416.c

478

reg = RW(reg, AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3);

sys/dev/ic/arn5416.c

479

AR_WRITE(sc, AR_PHY_TX_PWRCTRL6_1, reg);

sys/dev/ic/arn5416.c

481

reg = AR_READ(sc, AR_PHY_TX_PWRCTRL7);

sys/dev/ic/arn5416.c

482

reg = RW(reg, AR_PHY_TX_PWRCTRL_INIT_TX_GAIN, txgain);

sys/dev/ic/arn5416.c

483

AR_WRITE(sc, AR_PHY_TX_PWRCTRL7, reg);

sys/dev/ic/arn5416.c

493

reg = SM(AR_PHY_TPCRG5_PD_GAIN_OVERLAP,

sys/dev/ic/arn5416.c

495

reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1,

sys/dev/ic/arn5416.c

497

reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2,

sys/dev/ic/arn5416.c

499

reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3,

sys/dev/ic/arn5416.c

501

reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4,

sys/dev/ic/arn5416.c

503

AR_WRITE(sc, AR_PHY_TPCRG5 + offset, reg);

sys/dev/ic/arn5416.c

739

uint8_t rev, reg;

sys/dev/ic/arn5416.c

748

reg = (AR_READ(sc, AR_PHY(256)) >> 24) & 0xff;

sys/dev/ic/arn5416.c

749

reg = (reg & 0xf0) >> 4 | (reg & 0x0f) << 4;

sys/dev/ic/arn5416.c

751

rev = ar5416_reverse_bits(reg, 8);

sys/dev/ic/arn9003.c

1859

uint32_t reg;

sys/dev/ic/arn9003.c

1861

reg = IEEE80211_IS_CHAN_2GHZ(c) ?

sys/dev/ic/arn9003.c

1865

reg |= AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE;

sys/dev/ic/arn9003.c

1867

AR_WRITE(sc, AR_PHY_MODE, reg);

sys/dev/ic/arn9003.c

1945

uint32_t coeff, exp, man, reg;

sys/dev/ic/arn9003.c

1952

reg = AR_READ(sc, AR_PHY_TIMING3);

sys/dev/ic/arn9003.c

1953

reg = RW(reg, AR_PHY_TIMING3_DSC_EXP, exp);

sys/dev/ic/arn9003.c

1954

reg = RW(reg, AR_PHY_TIMING3_DSC_MAN, man);

sys/dev/ic/arn9003.c

1955

AR_WRITE(sc, AR_PHY_TIMING3, reg);

sys/dev/ic/arn9003.c

1962

reg = AR_READ(sc, AR_PHY_SGI_DELTA);

sys/dev/ic/arn9003.c

1963

reg = RW(reg, AR_PHY_SGI_DSC_EXP, exp);

sys/dev/ic/arn9003.c

1964

reg = RW(reg, AR_PHY_SGI_DSC_MAN, man);

sys/dev/ic/arn9003.c

1965

AR_WRITE(sc, AR_PHY_SGI_DELTA, reg);

sys/dev/ic/arn9003.c

2034

uint32_t reg;

sys/dev/ic/arn9003.c

2038

reg = AR_READ(sc, AR_PHY_CCA(i));

sys/dev/ic/arn9003.c

2039

nf[i] = MS(reg, AR_PHY_MINCCA_PWR);

sys/dev/ic/arn9003.c

2042

reg = AR_READ(sc, AR_PHY_EXT_CCA(i));

sys/dev/ic/arn9003.c

2043

nf_ext[i] = MS(reg, AR_PHY_EXT_MINCCA_PWR);

sys/dev/ic/arn9003.c

2054

uint32_t reg;

sys/dev/ic/arn9003.c

2058

reg = AR_READ(sc, AR_PHY_CCA(i));

sys/dev/ic/arn9003.c

2059

reg = RW(reg, AR_PHY_MAXCCA_PWR, nf[i]);

sys/dev/ic/arn9003.c

2060

AR_WRITE(sc, AR_PHY_CCA(i), reg);

sys/dev/ic/arn9003.c

2062

reg = AR_READ(sc, AR_PHY_EXT_CCA(i));

sys/dev/ic/arn9003.c

2063

reg = RW(reg, AR_PHY_EXT_MAXCCA_PWR, nf_ext[i]);

sys/dev/ic/arn9003.c

2064

AR_WRITE(sc, AR_PHY_EXT_CCA(i), reg);

sys/dev/ic/arn9003.c

2170

uint32_t reg;

sys/dev/ic/arn9003.c

2195

reg = AR_READ(sc, AR_PHY_AGC_CONTROL);

sys/dev/ic/arn9003.c

2196

if (!(reg & AR_PHY_AGC_CONTROL_CAL))

sys/dev/ic/arn9003.c

2214

uint32_t reg;

sys/dev/ic/arn9003.c

2217

reg = AR_READ(sc, AR_PHY_TIMING4);

sys/dev/ic/arn9003.c

2218

reg = RW(reg, AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX, 10);

sys/dev/ic/arn9003.c

2219

AR_WRITE(sc, AR_PHY_TIMING4, reg);

sys/dev/ic/arn9003.c

2249

uint32_t reg, i_coff_denom, q_coff_denom;

sys/dev/ic/arn9003.c

2295

reg = AR_READ(sc, AR_PHY_RX_IQCAL_CORR_B(i));

sys/dev/ic/arn9003.c

2296

reg = RW(reg, AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF, i_coff);

sys/dev/ic/arn9003.c

2297

reg = RW(reg, AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF, q_coff);

sys/dev/ic/arn9003.c

2298

AR_WRITE(sc, AR_PHY_RX_IQCAL_CORR_B(i), reg);

sys/dev/ic/arn9003.c

2435

uint32_t reg;

sys/dev/ic/arn9003.c

2439

reg = AR_READ(sc, AR_PHY_TX_IQCAL_CONTROL_1);

sys/dev/ic/arn9003.c

2440

reg = RW(reg, AR_PHY_TX_IQCAQL_CONTROL_1_IQCORR_I_Q_COFF_DELPT, DELPT);

sys/dev/ic/arn9003.c

2441

AR_WRITE(sc, AR_PHY_TX_IQCAL_CONTROL_1, reg);

sys/dev/ic/arn9003.c

2447

reg = AR_READ(sc, AR_PHY_TX_IQCAL_START);

sys/dev/ic/arn9003.c

2448

if (!(reg & AR_PHY_TX_IQCAL_START_DO_CAL))

sys/dev/ic/arn9003.c

2457

reg = AR_READ(sc, AR_PHY_TX_IQCAL_STATUS_B(i));

sys/dev/ic/arn9003.c

2458

if (reg & AR_PHY_TX_IQCAL_STATUS_FAILED)

sys/dev/ic/arn9003.c

2467

reg = AR_READ(sc, AR_PHY_CHAN_INFO_TAB(i, j));

sys/dev/ic/arn9003.c

2468

res[j * 2 + 0] = reg;

sys/dev/ic/arn9003.c

2472

reg = AR_READ(sc, AR_PHY_CHAN_INFO_TAB(i, j));

sys/dev/ic/arn9003.c

2473

res[j * 2 + 1] = reg & 0xffff;

sys/dev/ic/arn9003.c

2481

reg = AR_READ(sc, AR_PHY_TX_IQCAL_CORR_COEFF_01_B(i));

sys/dev/ic/arn9003.c

2482

reg = RW(reg, AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE,

sys/dev/ic/arn9003.c

2484

AR_WRITE(sc, AR_PHY_TX_IQCAL_CORR_COEFF_01_B(i), reg);

sys/dev/ic/arn9003.c

2486

reg = AR_READ(sc, AR_PHY_RX_IQCAL_CORR_B(i));

sys/dev/ic/arn9003.c

2487

reg = RW(reg, AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_Q_COFF,

sys/dev/ic/arn9003.c

2489

reg = RW(reg, AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_I_COFF,

sys/dev/ic/arn9003.c

2491

AR_WRITE(sc, AR_PHY_RX_IQCAL_CORR_B(i), reg);

sys/dev/ic/arn9003.c

2526

uint32_t reg, ht20mask, ht40mask;

sys/dev/ic/arn9003.c

2533

reg = AR_READ(sc, AR_PHY_PAPRD_AM2AM);

sys/dev/ic/arn9003.c

2534

reg = RW(reg, AR_PHY_PAPRD_AM2AM_MASK, ht20mask);

sys/dev/ic/arn9003.c

2535

AR_WRITE(sc, AR_PHY_PAPRD_AM2AM, reg);

sys/dev/ic/arn9003.c

2538

reg = AR_READ(sc, AR_PHY_PAPRD_AM2PM);

sys/dev/ic/arn9003.c

2539

reg = RW(reg, AR_PHY_PAPRD_AM2PM_MASK, ht20mask);

sys/dev/ic/arn9003.c

2540

AR_WRITE(sc, AR_PHY_PAPRD_AM2PM, reg);

sys/dev/ic/arn9003.c

2542

reg = AR_READ(sc, AR_PHY_PAPRD_HT40);

sys/dev/ic/arn9003.c

2543

reg = RW(reg, AR_PHY_PAPRD_HT40_MASK, ht40mask);

sys/dev/ic/arn9003.c

2544

AR_WRITE(sc, AR_PHY_PAPRD_HT40, reg);

sys/dev/ic/arn9003.c

2550

reg = AR_READ(sc, AR_PHY_PAPRD_CTRL1_B(i));

sys/dev/ic/arn9003.c

2551

reg = RW(reg, AR_PHY_PAPRD_CTRL1_PA_GAIN_SCALE_FACT, 181);

sys/dev/ic/arn9003.c

2552

reg = RW(reg, AR_PHY_PAPRD_CTRL1_MAG_SCALE_FACT, 361);

sys/dev/ic/arn9003.c

2553

reg &= ~AR_PHY_PAPRD_CTRL1_ADAPTIVE_SCALING_ENA;

sys/dev/ic/arn9003.c

2554

reg |= AR_PHY_PAPRD_CTRL1_ADAPTIVE_AM2AM_ENA;

sys/dev/ic/arn9003.c

2555

reg |= AR_PHY_PAPRD_CTRL1_ADAPTIVE_AM2PM_ENA;

sys/dev/ic/arn9003.c

2556

AR_WRITE(sc, AR_PHY_PAPRD_CTRL1_B(i), reg);

sys/dev/ic/arn9003.c

2558

reg = AR_READ(sc, AR_PHY_PAPRD_CTRL0_B(i));

sys/dev/ic/arn9003.c

2559

reg = RW(reg, AR_PHY_PAPRD_CTRL0_PAPRD_MAG_THRSH, 3);

sys/dev/ic/arn9003.c

256

uint32_t reg;

sys/dev/ic/arn9003.c

2560

AR_WRITE(sc, AR_PHY_PAPRD_CTRL0_B(i), reg);

sys/dev/ic/arn9003.c

2573

reg = AR_READ(sc, AR_PHY_PAPRD_TRAINER_CNTL1);

sys/dev/ic/arn9003.c

2574

reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL1_AGC2_SETTLING, 28);

sys/dev/ic/arn9003.c

2575

reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL1_LB_SKIP, 0x30);

sys/dev/ic/arn9003.c

2576

reg &= ~AR_PHY_PAPRD_TRAINER_CNTL1_RX_BB_GAIN_FORCE;

sys/dev/ic/arn9003.c

2577

reg &= ~AR_PHY_PAPRD_TRAINER_CNTL1_IQCORR_ENABLE;

sys/dev/ic/arn9003.c

2578

reg |= AR_PHY_PAPRD_TRAINER_CNTL1_LB_ENABLE;

sys/dev/ic/arn9003.c

2579

reg |= AR_PHY_PAPRD_TRAINER_CNTL1_TX_GAIN_FORCE;

sys/dev/ic/arn9003.c

2580

reg |= AR_PHY_PAPRD_TRAINER_CNTL1_TRAIN_ENABLE;

sys/dev/ic/arn9003.c

2581

AR_WRITE(sc, AR_PHY_PAPRD_TRAINER_CNTL1, reg);

sys/dev/ic/arn9003.c

2585

reg = AR_READ(sc, AR_PHY_PAPRD_TRAINER_CNTL3);

sys/dev/ic/arn9003.c

2586

reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL3_FINE_CORR_LEN, 4);

sys/dev/ic/arn9003.c

2587

reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL3_COARSE_CORR_LEN, 4);

sys/dev/ic/arn9003.c

2588

reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL3_NUM_CORR_STAGES, 7);

sys/dev/ic/arn9003.c

2589

reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL3_MIN_LOOPBACK_DEL, 1);

sys/dev/ic/arn9003.c

259

reg = AR_READ(sc, AR_EEPROM_OFFSET(addr));

sys/dev/ic/arn9003.c

2591

reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL3_QUICK_DROP, -3);

sys/dev/ic/arn9003.c

2593

reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL3_QUICK_DROP, -6);

sys/dev/ic/arn9003.c

2594

reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL3_ADC_DESIRED_SIZE, -15);

sys/dev/ic/arn9003.c

2595

reg |= AR_PHY_PAPRD_TRAINER_CNTL3_BBTXMIX_DISABLE;

sys/dev/ic/arn9003.c

2596

AR_WRITE(sc, AR_PHY_PAPRD_TRAINER_CNTL3, reg);

sys/dev/ic/arn9003.c

2598

reg = AR_READ(sc, AR_PHY_PAPRD_TRAINER_CNTL4);

sys/dev/ic/arn9003.c

2599

reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL4_SAFETY_DELTA, 0);

sys/dev/ic/arn9003.c

2600

reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL4_MIN_CORR, 400);

sys/dev/ic/arn9003.c

2601

reg = RW(reg, AR_PHY_PAPRD_TRAINER_CNTL4_NUM_TRAIN_SAMPLES, 100);

sys/dev/ic/arn9003.c

2602

AR_WRITE(sc, AR_PHY_PAPRD_TRAINER_CNTL4, reg);

sys/dev/ic/arn9003.c

2605

reg = AR_READ(sc, AR_PHY_PAPRD_PRE_POST_SCALE_B0(i));

sys/dev/ic/arn9003.c

2606

reg = RW(reg, AR_PHY_PAPRD_PRE_POST_SCALING, scaling[i]);

sys/dev/ic/arn9003.c

2607

AR_WRITE(sc, AR_PHY_PAPRD_PRE_POST_SCALE_B0(i), reg);

sys/dev/ic/arn9003.c

261

reg = AR_READ(sc, AR_EEPROM_STATUS_DATA);

sys/dev/ic/arn9003.c

262

if (!(reg & (AR_EEPROM_STATUS_DATA_BUSY |

sys/dev/ic/arn9003.c

264

*val = MS(reg, AR_EEPROM_STATUS_DATA_VAL);

sys/dev/ic/arn9003.c

2641

uint32_t reg;

sys/dev/ic/arn9003.c

2647

reg = AR_READ(sc, AR_PHY_TPC_19);

sys/dev/ic/arn9003.c

2648

atemp = MS(reg, AR_PHY_TPC_19_ALPHA_THERM);

sys/dev/ic/arn9003.c

2649

avolt = MS(reg, AR_PHY_TPC_19_ALPHA_VOLT);

sys/dev/ic/arn9003.c

2651

reg = AR_READ(sc, AR_PHY_TPC_18);

sys/dev/ic/arn9003.c

2652

tempcal = MS(reg, AR_PHY_TPC_18_THERM_CAL);

sys/dev/ic/arn9003.c

2653

voltcal = MS(reg, AR_PHY_TPC_18_VOLT_CAL);

sys/dev/ic/arn9003.c

2655

reg = AR_READ(sc, AR_PHY_BB_THERM_ADC_4);

sys/dev/ic/arn9003.c

2656

temp = MS(reg, AR_PHY_BB_THERM_ADC_4_LATEST_THERM);

sys/dev/ic/arn9003.c

2657

volt = MS(reg, AR_PHY_BB_THERM_ADC_4_LATEST_VOLT);

sys/dev/ic/arn9003.c

2673

uint32_t reg;

sys/dev/ic/arn9003.c

2675

reg = AR_READ(sc, AR_PHY_TX_FORCED_GAIN);

sys/dev/ic/arn9003.c

2676

reg = RW(reg, AR_PHY_TX_FORCED_GAIN_TXBB1DBGAIN,

sys/dev/ic/arn9003.c

2678

reg = RW(reg, AR_PHY_TX_FORCED_GAIN_TXBB6DBGAIN,

sys/dev/ic/arn9003.c

2680

reg = RW(reg, AR_PHY_TX_FORCED_GAIN_TXMXRGAIN,

sys/dev/ic/arn9003.c

2682

reg = RW(reg, AR_PHY_TX_FORCED_GAIN_PADRVGNA,

sys/dev/ic/arn9003.c

2684

reg = RW(reg, AR_PHY_TX_FORCED_GAIN_PADRVGNB,

sys/dev/ic/arn9003.c

2686

reg = RW(reg, AR_PHY_TX_FORCED_GAIN_PADRVGNC,

sys/dev/ic/arn9003.c

2688

reg = RW(reg, AR_PHY_TX_FORCED_GAIN_PADRVGND,

sys/dev/ic/arn9003.c

2690

reg &= ~AR_PHY_TX_FORCED_GAIN_ENABLE_PAL;

sys/dev/ic/arn9003.c

2691

reg &= ~AR_PHY_TX_FORCED_GAIN_FORCE_TX_GAIN;

sys/dev/ic/arn9003.c

2692

AR_WRITE(sc, AR_PHY_TX_FORCED_GAIN, reg);

sys/dev/ic/arn9003.c

2694

reg = AR_READ(sc, AR_PHY_TPC_1);

sys/dev/ic/arn9003.c

2695

reg = RW(reg, AR_PHY_TPC_1_FORCED_DAC_GAIN, 0);

sys/dev/ic/arn9003.c

2696

reg &= ~AR_PHY_TPC_1_FORCE_DAC_GAIN;

sys/dev/ic/arn9003.c

2697

AR_WRITE(sc, AR_PHY_TPC_1, reg);

sys/dev/ic/arn9003.c

3022

uint32_t reg;

sys/dev/ic/arn9003.c

3032

reg = AR_READ(sc, AR_PHY_PA_GAIN123_B(chain));

sys/dev/ic/arn9003.c

3033

reg = RW(reg, AR_PHY_PA_GAIN123_PA_GAIN1, sc->sc_gain1[chain]);

sys/dev/ic/arn9003.c

3034

AR_WRITE(sc, AR_PHY_PA_GAIN123_B(chain), reg);

sys/dev/ic/arn9003.c

3037

reg = AR_READ(sc, AR_PHY_PAPRD_CTRL1_B(chain));

sys/dev/ic/arn9003.c

3038

reg = RW(reg, AR_PHY_PAPRD_CTRL1_POWER_AT_AM2AM_CAL, sc->sc_trainpow);

sys/dev/ic/arn9003.c

3039

AR_WRITE(sc, AR_PHY_PAPRD_CTRL1_B(chain), reg);

sys/dev/ic/arn9003.c

318

uint32_t reg;

sys/dev/ic/arn9003.c

321

reg = AR_READ(sc, AR_OTP_BASE(addr));

sys/dev/ic/arn9003.c

3214

uint32_t reg;

sys/dev/ic/arn9003.c

323

reg = AR_READ(sc, AR_OTP_STATUS);

sys/dev/ic/arn9003.c

324

if (MS(reg, AR_OTP_STATUS_TYPE) == AR_OTP_STATUS_VALID) {

sys/dev/ic/arn9003.c

3288

reg = AR_READ(sc, AR_PCU_MISC_MODE2);

sys/dev/ic/arn9003.c

3289

reg &= ~AR_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE;

sys/dev/ic/arn9003.c

3290

reg |= AR_PCU_MISC_MODE2_AGG_WEP_ENABLE_FIX;

sys/dev/ic/arn9003.c

3291

reg |= AR_PCU_MISC_MODE2_ENABLE_AGGWEP;

sys/dev/ic/arn9003.c

3292

AR_WRITE(sc, AR_PCU_MISC_MODE2, reg);

sys/dev/ic/arn9003.c

3373

uint32_t reg;

sys/dev/ic/arn9003.c

3375

reg = AR_READ(sc, AR_PHY_DESIRED_SZ);

sys/dev/ic/arn9003.c

3376

reg = RW(reg, AR_PHY_DESIRED_SZ_TOT_DES, high ? -62 : -55);

sys/dev/ic/arn9003.c

3377

AR_WRITE(sc, AR_PHY_DESIRED_SZ, reg);

sys/dev/ic/arn9003.c

3379

reg = AR_READ(sc, AR_PHY_AGC);

sys/dev/ic/arn9003.c

3380

reg = RW(reg, AR_PHY_AGC_COARSE_LOW, high ? -70 : -64);

sys/dev/ic/arn9003.c

3381

reg = RW(reg, AR_PHY_AGC_COARSE_HIGH, high ? -12 : -14);

sys/dev/ic/arn9003.c

3382

AR_WRITE(sc, AR_PHY_AGC, reg);

sys/dev/ic/arn9003.c

3384

reg = AR_READ(sc, AR_PHY_FIND_SIG);

sys/dev/ic/arn9003.c

3385

reg = RW(reg, AR_PHY_FIND_SIG_FIRPWR, high ? -80 : -78);

sys/dev/ic/arn9003.c

3386

AR_WRITE(sc, AR_PHY_FIND_SIG, reg);

sys/dev/ic/arn9003.c

3393

uint32_t reg;

sys/dev/ic/arn9003.c

3395

reg = AR_READ(sc, AR_PHY_SFCORR_LOW);

sys/dev/ic/arn9003.c

3396

reg = RW(reg, AR_PHY_SFCORR_LOW_M1_THRESH_LOW, 50);

sys/dev/ic/arn9003.c

3397

reg = RW(reg, AR_PHY_SFCORR_LOW_M2_THRESH_LOW, 40);

sys/dev/ic/arn9003.c

3398

reg = RW(reg, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, 48);

sys/dev/ic/arn9003.c

3399

AR_WRITE(sc, AR_PHY_SFCORR_LOW, reg);

sys/dev/ic/arn9003.c

3401

reg = AR_READ(sc, AR_PHY_SFCORR);

sys/dev/ic/arn9003.c

3402

reg = RW(reg, AR_PHY_SFCORR_M1_THRESH, 77);

sys/dev/ic/arn9003.c

3403

reg = RW(reg, AR_PHY_SFCORR_M2_THRESH, 64);

sys/dev/ic/arn9003.c

3404

reg = RW(reg, AR_PHY_SFCORR_M2COUNT_THR, 16);

sys/dev/ic/arn9003.c

3405

AR_WRITE(sc, AR_PHY_SFCORR, reg);

sys/dev/ic/arn9003.c

3407

reg = AR_READ(sc, AR_PHY_SFCORR_EXT);

sys/dev/ic/arn9003.c

3408

reg = RW(reg, AR_PHY_SFCORR_EXT_M1_THRESH_LOW, 50);

sys/dev/ic/arn9003.c

3409

reg = RW(reg, AR_PHY_SFCORR_EXT_M2_THRESH_LOW, 40);

sys/dev/ic/arn9003.c

3410

reg = RW(reg, AR_PHY_SFCORR_EXT_M1_THRESH, 77);

sys/dev/ic/arn9003.c

3411

reg = RW(reg, AR_PHY_SFCORR_EXT_M2_THRESH, 64);

sys/dev/ic/arn9003.c

3412

AR_WRITE(sc, AR_PHY_SFCORR_EXT, reg);

sys/dev/ic/arn9003.c

3422

uint32_t reg;

sys/dev/ic/arn9003.c

3424

reg = AR_READ(sc, AR_PHY_SFCORR_LOW);

sys/dev/ic/arn9003.c

3425

reg = RW(reg, AR_PHY_SFCORR_LOW_M1_THRESH_LOW, 127);

sys/dev/ic/arn9003.c

3426

reg = RW(reg, AR_PHY_SFCORR_LOW_M2_THRESH_LOW, 127);

sys/dev/ic/arn9003.c

3427

reg = RW(reg, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, 63);

sys/dev/ic/arn9003.c

3428

AR_WRITE(sc, AR_PHY_SFCORR_LOW, reg);

sys/dev/ic/arn9003.c

3430

reg = AR_READ(sc, AR_PHY_SFCORR);

sys/dev/ic/arn9003.c

3431

reg = RW(reg, AR_PHY_SFCORR_M1_THRESH, 127);

sys/dev/ic/arn9003.c

3432

reg = RW(reg, AR_PHY_SFCORR_M2_THRESH, 127);

sys/dev/ic/arn9003.c

3433

reg = RW(reg, AR_PHY_SFCORR_M2COUNT_THR, 31);

sys/dev/ic/arn9003.c

3434

AR_WRITE(sc, AR_PHY_SFCORR, reg);

sys/dev/ic/arn9003.c

3436

reg = AR_READ(sc, AR_PHY_SFCORR_EXT);

sys/dev/ic/arn9003.c

3437

reg = RW(reg, AR_PHY_SFCORR_EXT_M1_THRESH_LOW, 127);

sys/dev/ic/arn9003.c

3438

reg = RW(reg, AR_PHY_SFCORR_EXT_M2_THRESH_LOW, 127);

sys/dev/ic/arn9003.c

3439

reg = RW(reg, AR_PHY_SFCORR_EXT_M1_THRESH, 127);

sys/dev/ic/arn9003.c

3440

reg = RW(reg, AR_PHY_SFCORR_EXT_M2_THRESH, 127);

sys/dev/ic/arn9003.c

3441

AR_WRITE(sc, AR_PHY_SFCORR_EXT, reg);

sys/dev/ic/arn9003.c

3451

uint32_t reg;

sys/dev/ic/arn9003.c

3453

reg = AR_READ(sc, AR_PHY_CCK_DETECT);

sys/dev/ic/arn9003.c

3454

reg = RW(reg, AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK, high ? 6 : 8);

sys/dev/ic/arn9003.c

3455

AR_WRITE(sc, AR_PHY_CCK_DETECT, reg);

sys/dev/ic/arn9003.c

3462

uint32_t reg;

sys/dev/ic/arn9003.c

3464

reg = AR_READ(sc, AR_PHY_FIND_SIG);

sys/dev/ic/arn9003.c

3465

reg = RW(reg, AR_PHY_FIND_SIG_FIRSTEP, level * 4);

sys/dev/ic/arn9003.c

3466

AR_WRITE(sc, AR_PHY_FIND_SIG, reg);

sys/dev/ic/arn9003.c

3473

uint32_t reg;

sys/dev/ic/arn9003.c

3475

reg = AR_READ(sc, AR_PHY_TIMING5);

sys/dev/ic/arn9003.c

3476

reg = RW(reg, AR_PHY_TIMING5_CYCPWR_THR1, (level + 1) * 2);

sys/dev/ic/arn9003.c

3477

AR_WRITE(sc, AR_PHY_TIMING5, reg);

sys/dev/ic/arn9003.c

535

uint32_t reg;

sys/dev/ic/arn9003.c

538

reg = AR_READ(sc, AR_GPIO_IN_OUT);

sys/dev/ic/arn9003.c

540

reg |= 1 << pin;

sys/dev/ic/arn9003.c

542

reg &= ~(1 << pin);

sys/dev/ic/arn9003.c

543

AR_WRITE(sc, AR_GPIO_IN_OUT, reg);

sys/dev/ic/arn9003.c

550

uint32_t reg;

sys/dev/ic/arn9003.c

552

reg = AR_READ(sc, AR_GPIO_OE_OUT);

sys/dev/ic/arn9003.c

553

reg &= ~(AR_GPIO_OE_OUT_DRV_M << (pin * 2));

sys/dev/ic/arn9003.c

554

reg |= AR_GPIO_OE_OUT_DRV_NO << (pin * 2);

sys/dev/ic/arn9003.c

555

AR_WRITE(sc, AR_GPIO_OE_OUT, reg);

sys/dev/ic/arn9003.c

562

uint32_t reg;

sys/dev/ic/arn9003.c

568

reg = AR_READ(sc, AR_GPIO_OUTPUT_MUX(mux));

sys/dev/ic/arn9003.c

569

reg &= ~(0x1f << (off * 5));

sys/dev/ic/arn9003.c

570

reg |= (type & 0x1f) << (off * 5);

sys/dev/ic/arn9003.c

571

AR_WRITE(sc, AR_GPIO_OUTPUT_MUX(mux), reg);

sys/dev/ic/arn9003.c

573

reg = AR_READ(sc, AR_GPIO_OE_OUT);

sys/dev/ic/arn9003.c

574

reg &= ~(AR_GPIO_OE_OUT_DRV_M << (pin * 2));

sys/dev/ic/arn9003.c

575

reg |= AR_GPIO_OE_OUT_DRV_ALL << (pin * 2);

sys/dev/ic/arn9003.c

576

AR_WRITE(sc, AR_GPIO_OE_OUT, reg);

sys/dev/ic/arn9003.c

583

uint32_t reg;

sys/dev/ic/arn9003.c

587

reg = AR_READ(sc, AR_GPIO_INPUT_MUX2);

sys/dev/ic/arn9003.c

588

reg = RW(reg, AR_GPIO_INPUT_MUX2_RFSILENT, 0);

sys/dev/ic/arn9003.c

589

AR_WRITE(sc, AR_GPIO_INPUT_MUX2, reg);

sys/dev/ic/arn9003.c

840

uint32_t reg;

sys/dev/ic/arn9003.c

843

reg = AR_READ(sc, AR_RXBP_THRESH);

sys/dev/ic/arn9003.c

844

reg = RW(reg, AR_RXBP_THRESH_HP, 1);

sys/dev/ic/arn9003.c

845

reg = RW(reg, AR_RXBP_THRESH_LP, 1);

sys/dev/ic/arn9003.c

846

AR_WRITE(sc, AR_RXBP_THRESH, reg);

sys/dev/ic/arn9003reg.h

228

#define AR_IS_ANALOG_REG(reg) ((reg) >= 0x16000 && (reg) <= 0x17000)

sys/dev/ic/arn9280.c

167

uint32_t phy, reg, ndiv = 0;

sys/dev/ic/arn9280.c

191

reg = AR_READ(sc, AR_PHY_CCK_TX_CTRL);

sys/dev/ic/arn9280.c

193

reg |= AR_PHY_CCK_TX_CTRL_JAPAN;

sys/dev/ic/arn9280.c

195

reg &= ~AR_PHY_CCK_TX_CTRL_JAPAN;

sys/dev/ic/arn9280.c

196

AR_WRITE(sc, AR_PHY_CCK_TX_CTRL, reg);

sys/dev/ic/arn9280.c

220

reg = AR_READ(sc, AR_AN_SYNTH9);

sys/dev/ic/arn9280.c

221

reg = RW(reg, AR_AN_SYNTH9_REFDIVA, 1);

sys/dev/ic/arn9280.c

222

AR_WRITE(sc, AR_AN_SYNTH9, reg);

sys/dev/ic/arn9280.c

239

uint32_t reg, offset;

sys/dev/ic/arn9280.c

256

reg = AR_READ(sc, AR_PHY_TIMING_CTRL4_0 + offset);

sys/dev/ic/arn9280.c

257

reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF,

sys/dev/ic/arn9280.c

259

reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF,

sys/dev/ic/arn9280.c

261

AR_WRITE(sc, AR_PHY_TIMING_CTRL4_0 + offset, reg);

sys/dev/ic/arn9280.c

264

reg = AR_READ(sc, AR_PHY_GAIN_2GHZ + offset);

sys/dev/ic/arn9280.c

265

reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,

sys/dev/ic/arn9280.c

267

reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_DB,

sys/dev/ic/arn9280.c

269

reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,

sys/dev/ic/arn9280.c

271

reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_DB,

sys/dev/ic/arn9280.c

273

AR_WRITE(sc, AR_PHY_GAIN_2GHZ + offset, reg);

sys/dev/ic/arn9280.c

279

reg = AR_READ(sc, AR_PHY_RXGAIN + offset);

sys/dev/ic/arn9280.c

280

reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_ATTEN,

sys/dev/ic/arn9280.c

282

reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_MARGIN,

sys/dev/ic/arn9280.c

284

AR_WRITE(sc, AR_PHY_RXGAIN + offset, reg);

sys/dev/ic/arn9280.c

287

reg = AR_READ(sc, AR_AN_RF2G1_CH0);

sys/dev/ic/arn9280.c

288

reg = RW(reg, AR_AN_RF2G1_CH0_OB, modal->ob);

sys/dev/ic/arn9280.c

289

reg = RW(reg, AR_AN_RF2G1_CH0_DB, modal->db);

sys/dev/ic/arn9280.c

290

AR_WRITE(sc, AR_AN_RF2G1_CH0, reg);

sys/dev/ic/arn9280.c

294

reg = AR_READ(sc, AR_AN_RF2G1_CH1);

sys/dev/ic/arn9280.c

295

reg = RW(reg, AR_AN_RF2G1_CH1_OB, modal->ob_ch1);

sys/dev/ic/arn9280.c

296

reg = RW(reg, AR_AN_RF2G1_CH1_DB, modal->db_ch1);

sys/dev/ic/arn9280.c

297

AR_WRITE(sc, AR_AN_RF2G1_CH1, reg);

sys/dev/ic/arn9280.c

302

reg = AR_READ(sc, AR_AN_RF5G1_CH0);

sys/dev/ic/arn9280.c

303

reg = RW(reg, AR_AN_RF5G1_CH0_OB5, modal->ob);

sys/dev/ic/arn9280.c

304

reg = RW(reg, AR_AN_RF5G1_CH0_DB5, modal->db);

sys/dev/ic/arn9280.c

305

AR_WRITE(sc, AR_AN_RF5G1_CH0, reg);

sys/dev/ic/arn9280.c

309

reg = AR_READ(sc, AR_AN_RF5G1_CH1);

sys/dev/ic/arn9280.c

310

reg = RW(reg, AR_AN_RF5G1_CH1_OB5, modal->ob_ch1);

sys/dev/ic/arn9280.c

311

reg = RW(reg, AR_AN_RF5G1_CH1_DB5, modal->db_ch1);

sys/dev/ic/arn9280.c

312

AR_WRITE(sc, AR_AN_RF5G1_CH1, reg);

sys/dev/ic/arn9280.c

316

reg = AR_READ(sc, AR_AN_TOP2);

sys/dev/ic/arn9280.c

323

reg = RW(reg, AR_AN_TOP2_XPABIAS_LVL, 0);

sys/dev/ic/arn9280.c

326

reg = RW(reg, AR_AN_TOP2_XPABIAS_LVL, modal->xpaBiasLvl);

sys/dev/ic/arn9280.c

328

reg |= AR_AN_TOP2_LOCALBIAS;

sys/dev/ic/arn9280.c

330

reg &= ~AR_AN_TOP2_LOCALBIAS;

sys/dev/ic/arn9280.c

331

AR_WRITE(sc, AR_AN_TOP2, reg);

sys/dev/ic/arn9280.c

335

reg = AR_READ(sc, AR_PHY_XPA_CFG);

sys/dev/ic/arn9280.c

337

reg |= AR_PHY_FORCE_XPA_CFG;

sys/dev/ic/arn9280.c

339

reg &= ~AR_PHY_FORCE_XPA_CFG;

sys/dev/ic/arn9280.c

340

AR_WRITE(sc, AR_PHY_XPA_CFG, reg);

sys/dev/ic/arn9280.c

342

reg = AR_READ(sc, AR_PHY_SETTLING);

sys/dev/ic/arn9280.c

343

reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->switchSettling);

sys/dev/ic/arn9280.c

344

AR_WRITE(sc, AR_PHY_SETTLING, reg);

sys/dev/ic/arn9280.c

346

reg = AR_READ(sc, AR_PHY_DESIRED_SZ);

sys/dev/ic/arn9280.c

347

reg = RW(reg, AR_PHY_DESIRED_SZ_ADC, modal->adcDesiredSize);

sys/dev/ic/arn9280.c

348

AR_WRITE(sc, AR_PHY_DESIRED_SZ, reg);

sys/dev/ic/arn9280.c

350

reg = SM(AR_PHY_RF_CTL4_TX_END_XPAA_OFF, modal->txEndToXpaOff);

sys/dev/ic/arn9280.c

351

reg |= SM(AR_PHY_RF_CTL4_TX_END_XPAB_OFF, modal->txEndToXpaOff);

sys/dev/ic/arn9280.c

352

reg |= SM(AR_PHY_RF_CTL4_FRAME_XPAA_ON, modal->txFrameToXpaOn);

sys/dev/ic/arn9280.c

353

reg |= SM(AR_PHY_RF_CTL4_FRAME_XPAB_ON, modal->txFrameToXpaOn);

sys/dev/ic/arn9280.c

354

AR_WRITE(sc, AR_PHY_RF_CTL4, reg);

sys/dev/ic/arn9280.c

356

reg = AR_READ(sc, AR_PHY_RF_CTL3);

sys/dev/ic/arn9280.c

357

reg = RW(reg, AR_PHY_TX_END_TO_A2_RX_ON, modal->txEndToRxOn);

sys/dev/ic/arn9280.c

358

AR_WRITE(sc, AR_PHY_RF_CTL3, reg);

sys/dev/ic/arn9280.c

360

reg = AR_READ(sc, AR_PHY_CCA(0));

sys/dev/ic/arn9280.c

361

reg = RW(reg, AR9280_PHY_CCA_THRESH62, modal->thresh62);

sys/dev/ic/arn9280.c

362

AR_WRITE(sc, AR_PHY_CCA(0), reg);

sys/dev/ic/arn9280.c

364

reg = AR_READ(sc, AR_PHY_EXT_CCA0);

sys/dev/ic/arn9280.c

365

reg = RW(reg, AR_PHY_EXT_CCA0_THRESH62, modal->thresh62);

sys/dev/ic/arn9280.c

366

AR_WRITE(sc, AR_PHY_EXT_CCA0, reg);

sys/dev/ic/arn9280.c

369

reg = AR_READ(sc, AR_PHY_RF_CTL2);

sys/dev/ic/arn9280.c

370

reg = RW(reg, AR_PHY_TX_END_DATA_START,

sys/dev/ic/arn9280.c

372

reg = RW(reg, AR_PHY_TX_END_PA_ON, modal->txFrameToPaOn);

sys/dev/ic/arn9280.c

373

AR_WRITE(sc, AR_PHY_RF_CTL2, reg);

sys/dev/ic/arn9280.c

378

reg = AR_READ(sc, AR_PHY_SETTLING);

sys/dev/ic/arn9280.c

379

reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->swSettleHt40);

sys/dev/ic/arn9280.c

380

AR_WRITE(sc, AR_PHY_SETTLING, reg);

sys/dev/ic/arn9280.c

384

reg = AR_READ(sc, AR_PHY_CCK_TX_CTRL);

sys/dev/ic/arn9280.c

385

reg = RW(reg, AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK,

sys/dev/ic/arn9280.c

387

AR_WRITE(sc, AR_PHY_CCK_TX_CTRL, reg);

sys/dev/ic/arn9280.c

391

reg = AR_READ(sc, AR_AN_TOP1);

sys/dev/ic/arn9280.c

395

reg |= AR_AN_TOP1_DACLPMODE;

sys/dev/ic/arn9280.c

397

reg &= ~AR_AN_TOP1_DACLPMODE;

sys/dev/ic/arn9280.c

398

AR_WRITE(sc, AR_AN_TOP1, reg);

sys/dev/ic/arn9280.c

402

reg = AR_READ(sc, AR_PHY_FRAME_CTL);

sys/dev/ic/arn9280.c

403

reg = RW(reg, AR_PHY_FRAME_CTL_TX_CLIP,

sys/dev/ic/arn9280.c

405

AR_WRITE(sc, AR_PHY_FRAME_CTL, reg);

sys/dev/ic/arn9280.c

407

reg = AR_READ(sc, AR_PHY_TX_PWRCTRL9);

sys/dev/ic/arn9280.c

408

reg = RW(reg, AR_PHY_TX_DESIRED_SCALE_CCK,

sys/dev/ic/arn9280.c

410

AR_WRITE(sc, AR_PHY_TX_PWRCTRL9, reg);

sys/dev/ic/arn9280.c

578

uint32_t reg;

sys/dev/ic/arn9280.c

583

reg = AR_READ(sc, AR_PHY_TX_GAIN_TBL(i));

sys/dev/ic/arn9280.c

584

sc->sc_tx_gain_tbl[i] = MS(reg, AR_PHY_TX_GAIN);

sys/dev/ic/arn9280.c

595

uint32_t reg;

sys/dev/ic/arn9280.c

598

reg = AR_READ(sc, AR_PHY_TX_PWRCTRL4);

sys/dev/ic/arn9280.c

599

pdadc = MS(reg, AR_PHY_TX_PWRCTRL_PD_AVG_OUT);

sys/dev/ic/arn9280.c

622

reg = AR_READ(sc, AR_PHY_TX_GAIN_TBL(i));

sys/dev/ic/arn9280.c

623

reg = RW(reg, AR_PHY_TX_GAIN, txgain);

sys/dev/ic/arn9280.c

624

AR_WRITE(sc, AR_PHY_TX_GAIN_TBL(i), reg);

sys/dev/ic/arn9285.c

187

uint32_t reg, offset = 0x1000;

sys/dev/ic/arn9285.c

194

reg = AR_READ(sc, AR_PHY_TIMING_CTRL4_0);

sys/dev/ic/arn9285.c

195

reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF, modal->iqCalI);

sys/dev/ic/arn9285.c

196

reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, modal->iqCalQ);

sys/dev/ic/arn9285.c

197

AR_WRITE(sc, AR_PHY_TIMING_CTRL4_0, reg);

sys/dev/ic/arn9285.c

200

reg = AR_READ(sc, AR_PHY_GAIN_2GHZ);

sys/dev/ic/arn9285.c

201

reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,

sys/dev/ic/arn9285.c

203

reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_DB,

sys/dev/ic/arn9285.c

205

reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,

sys/dev/ic/arn9285.c

207

reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_DB,

sys/dev/ic/arn9285.c

209

AR_WRITE(sc, AR_PHY_GAIN_2GHZ, reg);

sys/dev/ic/arn9285.c

212

reg = AR_READ(sc, AR_PHY_GAIN_2GHZ + offset);

sys/dev/ic/arn9285.c

213

reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,

sys/dev/ic/arn9285.c

215

reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_DB,

sys/dev/ic/arn9285.c

217

reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,

sys/dev/ic/arn9285.c

219

reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_DB,

sys/dev/ic/arn9285.c

221

AR_WRITE(sc, AR_PHY_GAIN_2GHZ + offset, reg);

sys/dev/ic/arn9285.c

227

reg = AR_READ(sc, AR_PHY_RXGAIN);

sys/dev/ic/arn9285.c

228

reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAtten);

sys/dev/ic/arn9285.c

229

reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_MARGIN, modal->rxTxMargin);

sys/dev/ic/arn9285.c

230

AR_WRITE(sc, AR_PHY_RXGAIN, reg);

sys/dev/ic/arn9285.c

233

reg = AR_READ(sc, AR_PHY_RXGAIN + offset);

sys/dev/ic/arn9285.c

234

reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAtten);

sys/dev/ic/arn9285.c

235

reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_MARGIN, modal->rxTxMargin);

sys/dev/ic/arn9285.c

236

AR_WRITE(sc, AR_PHY_RXGAIN + offset, reg);

sys/dev/ic/arn9285.c

240

reg = AR_READ(sc, AR_PHY_MULTICHAIN_GAIN_CTL);

sys/dev/ic/arn9285.c

241

reg = RW(reg, AR9285_PHY_ANT_DIV_CTL_ALL, 0);

sys/dev/ic/arn9285.c

242

reg = RW(reg, AR9285_PHY_ANT_DIV_CTL,

sys/dev/ic/arn9285.c

244

reg = RW(reg, AR9285_PHY_ANT_DIV_ALT_LNACONF,

sys/dev/ic/arn9285.c

246

reg = RW(reg, AR9285_PHY_ANT_DIV_MAIN_LNACONF,

sys/dev/ic/arn9285.c

248

reg = RW(reg, AR9285_PHY_ANT_DIV_ALT_GAINTB,

sys/dev/ic/arn9285.c

250

reg = RW(reg, AR9285_PHY_ANT_DIV_MAIN_GAINTB,

sys/dev/ic/arn9285.c

252

AR_WRITE(sc, AR_PHY_MULTICHAIN_GAIN_CTL, reg);

sys/dev/ic/arn9285.c

253

reg = AR_READ(sc, AR_PHY_MULTICHAIN_GAIN_CTL); /* Flush. */

sys/dev/ic/arn9285.c

255

reg = AR_READ(sc, AR_PHY_CCK_DETECT);

sys/dev/ic/arn9285.c

257

reg |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;

sys/dev/ic/arn9285.c

259

reg &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;

sys/dev/ic/arn9285.c

260

AR_WRITE(sc, AR_PHY_CCK_DETECT, reg);

sys/dev/ic/arn9285.c

261

reg = AR_READ(sc, AR_PHY_CCK_DETECT); /* Flush. */

sys/dev/ic/arn9285.c

313

reg = AR_READ(sc, AR9285_AN_RF2G3);

sys/dev/ic/arn9285.c

314

reg = RW(reg, AR9271_AN_RF2G3_OB_CCK, ob [0]);

sys/dev/ic/arn9285.c

315

reg = RW(reg, AR9271_AN_RF2G3_OB_PSK, ob [1]);

sys/dev/ic/arn9285.c

316

reg = RW(reg, AR9271_AN_RF2G3_OB_QAM, ob [2]);

sys/dev/ic/arn9285.c

317

reg = RW(reg, AR9271_AN_RF2G3_DB1, db1[0]);

sys/dev/ic/arn9285.c

318

AR_WRITE(sc, AR9285_AN_RF2G3, reg);

sys/dev/ic/arn9285.c

321

reg = AR_READ(sc, AR9285_AN_RF2G4);

sys/dev/ic/arn9285.c

322

reg = RW(reg, AR9271_AN_RF2G4_DB2, (uint32_t)db2[0]);

sys/dev/ic/arn9285.c

323

AR_WRITE(sc, AR9285_AN_RF2G4, reg);

sys/dev/ic/arn9285.c

330

reg = AR_READ(sc, AR9285_AN_RF2G3);

sys/dev/ic/arn9285.c

331

reg = RW(reg, AR9285_AN_RF2G3_OB_0, ob [0]);

sys/dev/ic/arn9285.c

332

reg = RW(reg, AR9285_AN_RF2G3_OB_1, ob [1]);

sys/dev/ic/arn9285.c

333

reg = RW(reg, AR9285_AN_RF2G3_OB_2, ob [2]);

sys/dev/ic/arn9285.c

334

reg = RW(reg, AR9285_AN_RF2G3_OB_3, ob [3]);

sys/dev/ic/arn9285.c

335

reg = RW(reg, AR9285_AN_RF2G3_OB_4, ob [4]);

sys/dev/ic/arn9285.c

336

reg = RW(reg, AR9285_AN_RF2G3_DB1_0, db1[0]);

sys/dev/ic/arn9285.c

337

reg = RW(reg, AR9285_AN_RF2G3_DB1_1, db1[1]);

sys/dev/ic/arn9285.c

338

reg = RW(reg, AR9285_AN_RF2G3_DB1_2, db1[2]);

sys/dev/ic/arn9285.c

339

AR_WRITE(sc, AR9285_AN_RF2G3, reg);

sys/dev/ic/arn9285.c

342

reg = AR_READ(sc, AR9285_AN_RF2G4);

sys/dev/ic/arn9285.c

343

reg = RW(reg, AR9285_AN_RF2G4_DB1_3, db1[3]);

sys/dev/ic/arn9285.c

344

reg = RW(reg, AR9285_AN_RF2G4_DB1_4, db1[4]);

sys/dev/ic/arn9285.c

345

reg = RW(reg, AR9285_AN_RF2G4_DB2_0, db2[0]);

sys/dev/ic/arn9285.c

346

reg = RW(reg, AR9285_AN_RF2G4_DB2_1, db2[1]);

sys/dev/ic/arn9285.c

347

reg = RW(reg, AR9285_AN_RF2G4_DB2_2, db2[2]);

sys/dev/ic/arn9285.c

348

reg = RW(reg, AR9285_AN_RF2G4_DB2_3, db2[3]);

sys/dev/ic/arn9285.c

349

reg = RW(reg, AR9285_AN_RF2G4_DB2_4, db2[4]);

sys/dev/ic/arn9285.c

350

AR_WRITE(sc, AR9285_AN_RF2G4, reg);

sys/dev/ic/arn9285.c

355

reg = AR_READ(sc, AR_PHY_SETTLING);

sys/dev/ic/arn9285.c

356

reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->switchSettling);

sys/dev/ic/arn9285.c

357

AR_WRITE(sc, AR_PHY_SETTLING, reg);

sys/dev/ic/arn9285.c

359

reg = AR_READ(sc, AR_PHY_DESIRED_SZ);

sys/dev/ic/arn9285.c

360

reg = RW(reg, AR_PHY_DESIRED_SZ_ADC, modal->adcDesiredSize);

sys/dev/ic/arn9285.c

361

AR_WRITE(sc, AR_PHY_DESIRED_SZ, reg);

sys/dev/ic/arn9285.c

363

reg = SM(AR_PHY_RF_CTL4_TX_END_XPAA_OFF, modal->txEndToXpaOff);

sys/dev/ic/arn9285.c

364

reg |= SM(AR_PHY_RF_CTL4_TX_END_XPAB_OFF, modal->txEndToXpaOff);

sys/dev/ic/arn9285.c

365

reg |= SM(AR_PHY_RF_CTL4_FRAME_XPAA_ON, modal->txFrameToXpaOn);

sys/dev/ic/arn9285.c

366

reg |= SM(AR_PHY_RF_CTL4_FRAME_XPAB_ON, modal->txFrameToXpaOn);

sys/dev/ic/arn9285.c

367

AR_WRITE(sc, AR_PHY_RF_CTL4, reg);

sys/dev/ic/arn9285.c

369

reg = AR_READ(sc, AR_PHY_RF_CTL3);

sys/dev/ic/arn9285.c

370

reg = RW(reg, AR_PHY_TX_END_TO_A2_RX_ON, modal->txEndToRxOn);

sys/dev/ic/arn9285.c

371

AR_WRITE(sc, AR_PHY_RF_CTL3, reg);

sys/dev/ic/arn9285.c

373

reg = AR_READ(sc, AR_PHY_CCA(0));

sys/dev/ic/arn9285.c

374

reg = RW(reg, AR9280_PHY_CCA_THRESH62, modal->thresh62);

sys/dev/ic/arn9285.c

375

AR_WRITE(sc, AR_PHY_CCA(0), reg);

sys/dev/ic/arn9285.c

377

reg = AR_READ(sc, AR_PHY_EXT_CCA0);

sys/dev/ic/arn9285.c

378

reg = RW(reg, AR_PHY_EXT_CCA0_THRESH62, modal->thresh62);

sys/dev/ic/arn9285.c

379

AR_WRITE(sc, AR_PHY_EXT_CCA0, reg);

sys/dev/ic/arn9285.c

382

reg = AR_READ(sc, AR_PHY_RF_CTL2);

sys/dev/ic/arn9285.c

383

reg = RW(reg, AR_PHY_TX_END_PA_ON,

sys/dev/ic/arn9285.c

385

reg = RW(reg, AR_PHY_TX_END_DATA_START,

sys/dev/ic/arn9285.c

387

AR_WRITE(sc, AR_PHY_RF_CTL2, reg);

sys/dev/ic/arn9285.c

391

reg = AR_READ(sc, AR_PHY_SETTLING);

sys/dev/ic/arn9285.c

392

reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->swSettleHt40);

sys/dev/ic/arn9285.c

393

AR_WRITE(sc, AR_PHY_SETTLING, reg);

sys/dev/ic/arn9285.c

412

uint32_t svg[7], reg, ccomp_svg;

sys/dev/ic/arn9285.c

440

reg = AR_READ(sc, AR9285_AN_RF2G8);

sys/dev/ic/arn9285.c

441

reg = RW(reg, AR9285_AN_RF2G8_PADRVGN2TAB0, 7);

sys/dev/ic/arn9285.c

442

AR_WRITE(sc, AR9285_AN_RF2G8, reg);

sys/dev/ic/arn9285.c

444

reg = AR_READ(sc, AR9285_AN_RF2G7);

sys/dev/ic/arn9285.c

445

reg = RW(reg, AR9285_AN_RF2G7_PADRVGN2TAB0, 0);

sys/dev/ic/arn9285.c

446

AR_WRITE(sc, AR9285_AN_RF2G7, reg);

sys/dev/ic/arn9285.c

448

reg = AR_READ(sc, AR9285_AN_RF2G6);

sys/dev/ic/arn9285.c

450

ccomp_svg = MS(reg, AR9285_AN_RF2G6_CCOMP);

sys/dev/ic/arn9285.c

452

reg = RW(reg, AR9285_AN_RF2G6_CCOMP, 0xf);

sys/dev/ic/arn9285.c

453

AR_WRITE(sc, AR9285_AN_RF2G6, reg);

sys/dev/ic/arn9285.c

496

reg = AR_READ(sc, AR9285_AN_RF2G6);

sys/dev/ic/arn9285.c

497

reg = RW(reg, AR9285_AN_RF2G6_CCOMP, ccomp_svg);

sys/dev/ic/arn9285.c

498

AR_WRITE(sc, AR9285_AN_RF2G6, reg);

sys/dev/ic/arn9285.c

516

uint32_t svg[7], reg, rf2g3_svg;

sys/dev/ic/arn9285.c

538

reg = AR_READ(sc, AR9285_AN_RF2G8);

sys/dev/ic/arn9285.c

539

reg = RW(reg, AR9285_AN_RF2G8_PADRVGN2TAB0, 7);

sys/dev/ic/arn9285.c

540

AR_WRITE(sc, AR9285_AN_RF2G8, reg);

sys/dev/ic/arn9285.c

542

reg = AR_READ(sc, AR9285_AN_RF2G7);

sys/dev/ic/arn9285.c

543

reg = RW(reg, AR9285_AN_RF2G7_PADRVGN2TAB0, 0);

sys/dev/ic/arn9285.c

544

AR_WRITE(sc, AR9285_AN_RF2G7, reg);

sys/dev/ic/arn9285.c

547

reg = rf2g3_svg = AR_READ(sc, AR9285_AN_RF2G3);

sys/dev/ic/arn9285.c

549

reg = RW(reg, AR9271_AN_RF2G3_CCOMP, 0xfff);

sys/dev/ic/arn9285.c

550

AR_WRITE(sc, AR9285_AN_RF2G3, reg);

sys/dev/ic/arn9285.c

560

reg = AR_READ(sc, AR9285_AN_RF2G6);

sys/dev/ic/arn9285.c

561

reg |= AR9271_AN_RF2G6_OFFS(i);

sys/dev/ic/arn9285.c

562

AR_WRITE(sc, AR9285_AN_RF2G6, reg);

sys/dev/ic/arn9285.c

566

reg &= ~AR9271_AN_RF2G6_OFFS(i);

sys/dev/ic/arn9285.c

567

AR_WRITE(sc, AR9285_AN_RF2G6, reg);

sys/dev/ic/arn9285.c

656

uint32_t reg, mask, clcgain, rf2g5_svg;

sys/dev/ic/arn9285.c

669

reg = AR_READ(sc, AR_PHY_TX_PWRCTRL7);

sys/dev/ic/arn9285.c

670

maxgain = MS(reg, AR_PHY_TX_PWRCTRL_TX_GAIN_TAB_MAX);

sys/dev/ic/arn9285.c

672

reg = AR_READ(sc, AR_PHY_TX_GAIN_TBL(i));

sys/dev/ic/arn9285.c

673

clcgain = MS(reg, AR_PHY_TX_GAIN_CLC);

sys/dev/ic/arn9285.c

682

reg = AR_READ(sc, AR_PHY_CLC_TBL(i));

sys/dev/ic/arn9285.c

683

if (MS(reg, AR_PHY_CLC_I0) == 0)

sys/dev/ic/arn9285.c

685

if (MS(reg, AR_PHY_CLC_Q0) == 0)

sys/dev/ic/arn9285.c

693

rf2g5_svg = reg = AR_READ(sc, AR9285_AN_RF2G5);

sys/dev/ic/arn9285.c

695

reg = RW(reg, AR9285_AN_RF2G5_IC50TX, 0x5);

sys/dev/ic/arn9285.c

697

reg = RW(reg, AR9285_AN_RF2G5_IC50TX, 0x4);

sys/dev/ic/arn9285.c

698

AR_WRITE(sc, AR9285_AN_RF2G5, reg);

sys/dev/ic/arn9285.c

745

uint32_t reg;

sys/dev/ic/arn9285.c

763

reg = AR_READ(sc, AR_PHY_TPCRG1);

sys/dev/ic/arn9285.c

764

reg = RW(reg, AR_PHY_TPCRG1_NUM_PD_GAIN, nxpdgains - 1);

sys/dev/ic/arn9285.c

765

reg = RW(reg, AR_PHY_TPCRG1_PD_GAIN_1, xpdgains[0]);

sys/dev/ic/arn9285.c

766

reg = RW(reg, AR_PHY_TPCRG1_PD_GAIN_2, xpdgains[1]);

sys/dev/ic/arn9285.c

767

AR_WRITE(sc, AR_PHY_TPCRG1, reg);

sys/dev/ic/arn9285.c

773

reg = SM(AR_PHY_TPCRG5_PD_GAIN_OVERLAP, overlap);

sys/dev/ic/arn9285.c

774

reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1, boundaries[0]);

sys/dev/ic/arn9285.c

775

reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2, boundaries[1]);

sys/dev/ic/arn9285.c

776

reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3, boundaries[2]);

sys/dev/ic/arn9285.c

777

reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4, boundaries[3]);

sys/dev/ic/arn9285.c

778

AR_WRITE(sc, AR_PHY_TPCRG5, reg);

sys/dev/ic/arn9287.c

164

uint32_t reg, offset;

sys/dev/ic/arn9287.c

175

reg = AR_READ(sc, AR_PHY_TIMING_CTRL4_0 + offset);

sys/dev/ic/arn9287.c

176

reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF,

sys/dev/ic/arn9287.c

178

reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF,

sys/dev/ic/arn9287.c

180

AR_WRITE(sc, AR_PHY_TIMING_CTRL4_0 + offset, reg);

sys/dev/ic/arn9287.c

182

reg = AR_READ(sc, AR_PHY_GAIN_2GHZ + offset);

sys/dev/ic/arn9287.c

183

reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,

sys/dev/ic/arn9287.c

185

reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_DB,

sys/dev/ic/arn9287.c

187

AR_WRITE(sc, AR_PHY_GAIN_2GHZ + offset, reg);

sys/dev/ic/arn9287.c

189

reg = AR_READ(sc, AR_PHY_RXGAIN + offset);

sys/dev/ic/arn9287.c

190

reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_MARGIN,

sys/dev/ic/arn9287.c

192

reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_ATTEN,

sys/dev/ic/arn9287.c

194

AR_WRITE(sc, AR_PHY_RXGAIN + offset, reg);

sys/dev/ic/arn9287.c

197

reg = AR_READ(sc, AR_PHY_SETTLING);

sys/dev/ic/arn9287.c

200

reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->swSettleHt40);

sys/dev/ic/arn9287.c

203

reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->switchSettling);

sys/dev/ic/arn9287.c

204

AR_WRITE(sc, AR_PHY_SETTLING, reg);

sys/dev/ic/arn9287.c

206

reg = AR_READ(sc, AR_PHY_DESIRED_SZ);

sys/dev/ic/arn9287.c

207

reg = RW(reg, AR_PHY_DESIRED_SZ_ADC, modal->adcDesiredSize);

sys/dev/ic/arn9287.c

208

AR_WRITE(sc, AR_PHY_DESIRED_SZ, reg);

sys/dev/ic/arn9287.c

210

reg = SM(AR_PHY_RF_CTL4_TX_END_XPAA_OFF, modal->txEndToXpaOff);

sys/dev/ic/arn9287.c

211

reg |= SM(AR_PHY_RF_CTL4_TX_END_XPAB_OFF, modal->txEndToXpaOff);

sys/dev/ic/arn9287.c

212

reg |= SM(AR_PHY_RF_CTL4_FRAME_XPAA_ON, modal->txFrameToXpaOn);

sys/dev/ic/arn9287.c

213

reg |= SM(AR_PHY_RF_CTL4_FRAME_XPAB_ON, modal->txFrameToXpaOn);

sys/dev/ic/arn9287.c

214

AR_WRITE(sc, AR_PHY_RF_CTL4, reg);

sys/dev/ic/arn9287.c

216

reg = AR_READ(sc, AR_PHY_RF_CTL3);

sys/dev/ic/arn9287.c

217

reg = RW(reg, AR_PHY_TX_END_TO_A2_RX_ON, modal->txEndToRxOn);

sys/dev/ic/arn9287.c

218

AR_WRITE(sc, AR_PHY_RF_CTL3, reg);

sys/dev/ic/arn9287.c

220

reg = AR_READ(sc, AR_PHY_CCA(0));

sys/dev/ic/arn9287.c

221

reg = RW(reg, AR9280_PHY_CCA_THRESH62, modal->thresh62);

sys/dev/ic/arn9287.c

222

AR_WRITE(sc, AR_PHY_CCA(0), reg);

sys/dev/ic/arn9287.c

224

reg = AR_READ(sc, AR_PHY_EXT_CCA0);

sys/dev/ic/arn9287.c

225

reg = RW(reg, AR_PHY_EXT_CCA0_THRESH62, modal->thresh62);

sys/dev/ic/arn9287.c

226

AR_WRITE(sc, AR_PHY_EXT_CCA0, reg);

sys/dev/ic/arn9287.c

228

reg = AR_READ(sc, AR9287_AN_RF2G3_CH0);

sys/dev/ic/arn9287.c

229

reg = RW(reg, AR9287_AN_RF2G3_DB1, modal->db1);

sys/dev/ic/arn9287.c

230

reg = RW(reg, AR9287_AN_RF2G3_DB2, modal->db2);

sys/dev/ic/arn9287.c

231

reg = RW(reg, AR9287_AN_RF2G3_OB_CCK, modal->ob_cck);

sys/dev/ic/arn9287.c

232

reg = RW(reg, AR9287_AN_RF2G3_OB_PSK, modal->ob_psk);

sys/dev/ic/arn9287.c

233

reg = RW(reg, AR9287_AN_RF2G3_OB_QAM, modal->ob_qam);

sys/dev/ic/arn9287.c

234

reg = RW(reg, AR9287_AN_RF2G3_OB_PAL_OFF, modal->ob_pal_off);

sys/dev/ic/arn9287.c

235

AR_WRITE(sc, AR9287_AN_RF2G3_CH0, reg);

sys/dev/ic/arn9287.c

239

reg = AR_READ(sc, AR9287_AN_RF2G3_CH1);

sys/dev/ic/arn9287.c

240

reg = RW(reg, AR9287_AN_RF2G3_DB1, modal->db1);

sys/dev/ic/arn9287.c

241

reg = RW(reg, AR9287_AN_RF2G3_DB2, modal->db2);

sys/dev/ic/arn9287.c

242

reg = RW(reg, AR9287_AN_RF2G3_OB_CCK, modal->ob_cck);

sys/dev/ic/arn9287.c

243

reg = RW(reg, AR9287_AN_RF2G3_OB_PSK, modal->ob_psk);

sys/dev/ic/arn9287.c

244

reg = RW(reg, AR9287_AN_RF2G3_OB_QAM, modal->ob_qam);

sys/dev/ic/arn9287.c

245

reg = RW(reg, AR9287_AN_RF2G3_OB_PAL_OFF, modal->ob_pal_off);

sys/dev/ic/arn9287.c

246

AR_WRITE(sc, AR9287_AN_RF2G3_CH1, reg);

sys/dev/ic/arn9287.c

250

reg = AR_READ(sc, AR_PHY_RF_CTL2);

sys/dev/ic/arn9287.c

251

reg = RW(reg, AR_PHY_TX_END_DATA_START, modal->txFrameToDataStart);

sys/dev/ic/arn9287.c

252

reg = RW(reg, AR_PHY_TX_END_PA_ON, modal->txFrameToPaOn);

sys/dev/ic/arn9287.c

253

AR_WRITE(sc, AR_PHY_RF_CTL2, reg);

sys/dev/ic/arn9287.c

255

reg = AR_READ(sc, AR9287_AN_TOP2);

sys/dev/ic/arn9287.c

256

reg = RW(reg, AR9287_AN_TOP2_XPABIAS_LVL, modal->xpaBiasLvl);

sys/dev/ic/arn9287.c

257

AR_WRITE(sc, AR9287_AN_TOP2, reg);

sys/dev/ic/arn9287.c

342

uint32_t reg, offset;

sys/dev/ic/arn9287.c

367

reg = AR_READ(sc, AR_PHY_TPCRG1);

sys/dev/ic/arn9287.c

368

reg = RW(reg, AR_PHY_TPCRG1_NUM_PD_GAIN, nxpdgains - 1);

sys/dev/ic/arn9287.c

369

reg = RW(reg, AR_PHY_TPCRG1_PD_GAIN_1, xpdgains[0]);

sys/dev/ic/arn9287.c

370

reg = RW(reg, AR_PHY_TPCRG1_PD_GAIN_2, xpdgains[1]);

sys/dev/ic/arn9287.c

371

AR_WRITE(sc, AR_PHY_TPCRG1, reg);

sys/dev/ic/arn9287.c

383

reg = AR_READ(sc, AR_PHY_TX_PWRCTRL6_0);

sys/dev/ic/arn9287.c

384

reg = RW(reg, AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3);

sys/dev/ic/arn9287.c

385

AR_WRITE(sc, AR_PHY_TX_PWRCTRL6_0, reg);

sys/dev/ic/arn9287.c

387

reg = AR_READ(sc, AR_PHY_TX_PWRCTRL6_1);

sys/dev/ic/arn9287.c

388

reg = RW(reg, AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3);

sys/dev/ic/arn9287.c

389

AR_WRITE(sc, AR_PHY_TX_PWRCTRL6_1, reg);

sys/dev/ic/arn9287.c

392

reg = AR_READ(sc, AR_PHY_CH0_TX_PWRCTRL11 + offset);

sys/dev/ic/arn9287.c

393

reg = RW(reg, AR_PHY_TX_PWRCTRL_OLPC_PWR, txpower);

sys/dev/ic/arn9287.c

394

AR_WRITE(sc, AR_PHY_CH0_TX_PWRCTRL11 + offset, reg);

sys/dev/ic/arn9287.c

406

reg = SM(AR_PHY_TPCRG5_PD_GAIN_OVERLAP,

sys/dev/ic/arn9287.c

408

reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1,

sys/dev/ic/arn9287.c

410

reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2,

sys/dev/ic/arn9287.c

412

reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3,

sys/dev/ic/arn9287.c

414

reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4,

sys/dev/ic/arn9287.c

416

AR_WRITE(sc, AR_PHY_TPCRG5 + offset, reg);

sys/dev/ic/arn9287.c

544

uint32_t reg;

sys/dev/ic/arn9287.c

548

reg = AR_READ(sc, AR9287_AN_TXPC0);

sys/dev/ic/arn9287.c

549

reg = RW(reg, AR9287_AN_TXPC0_TXPCMODE,

sys/dev/ic/arn9287.c

551

AR_WRITE(sc, AR9287_AN_TXPC0, reg);

sys/dev/ic/arn9287.c

561

uint32_t reg;

sys/dev/ic/arn9287.c

563

reg = AR_READ(sc, AR_PHY_TX_PWRCTRL4);

sys/dev/ic/arn9287.c

564

pdadc = MS(reg, AR_PHY_TX_PWRCTRL_PD_AVG_OUT);

sys/dev/ic/arn9287.c

582

reg = AR_READ(sc, AR_PHY_CH0_TX_PWRCTRL11);

sys/dev/ic/arn9287.c

583

reg = RW(reg, AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP, tcomp);

sys/dev/ic/arn9287.c

584

AR_WRITE(sc, AR_PHY_CH0_TX_PWRCTRL11, reg);

sys/dev/ic/arn9287.c

586

reg = AR_READ(sc, AR_PHY_CH1_TX_PWRCTRL11);

sys/dev/ic/arn9287.c

587

reg = RW(reg, AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP, tcomp);

sys/dev/ic/arn9287.c

588

AR_WRITE(sc, AR_PHY_CH1_TX_PWRCTRL11, reg);

sys/dev/ic/arn9287.c

610

uint32_t reg;

sys/dev/ic/arn9287.c

626

reg = AR_READ(sc, AR_AHB_MODE);

sys/dev/ic/arn9287.c

627

reg = RW(reg, AR_AHB_CUSTOM_BURST, AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);

sys/dev/ic/arn9287.c

628

AR_WRITE(sc, AR_AHB_MODE, reg);

sys/dev/ic/arn9380.c

306

uint32_t reg;

sys/dev/ic/arn9380.c

316

reg = AR_READ(sc, AR9485_PHY_65NM_CH0_TOP2);

sys/dev/ic/arn9380.c

317

reg = RW(reg, AR9485_PHY_65NM_CH0_TOP2_XPABIASLVL,

sys/dev/ic/arn9380.c

319

AR_WRITE(sc, AR9485_PHY_65NM_CH0_TOP2, reg);

sys/dev/ic/arn9380.c

322

reg = AR_READ(sc, AR_PHY_65NM_CH0_TOP);

sys/dev/ic/arn9380.c

323

reg = RW(reg, AR_PHY_65NM_CH0_TOP_XPABIASLVL,

sys/dev/ic/arn9380.c

325

AR_WRITE(sc, AR_PHY_65NM_CH0_TOP, reg);

sys/dev/ic/arn9380.c

326

reg = AR_READ(sc, AR_PHY_65NM_CH0_THERM);

sys/dev/ic/arn9380.c

327

reg = RW(reg, AR_PHY_65NM_CH0_THERM_XPABIASLVL_MSB,

sys/dev/ic/arn9380.c

329

reg |= AR_PHY_65NM_CH0_THERM_XPASHORT2GND;

sys/dev/ic/arn9380.c

330

AR_WRITE(sc, AR_PHY_65NM_CH0_THERM, reg);

sys/dev/ic/arn9380.c

334

reg = AR_READ(sc, AR_PHY_SWITCH_COM);

sys/dev/ic/arn9380.c

335

reg = RW(reg, AR_SWITCH_TABLE_COM_ALL, modal->antCtrlCommon);

sys/dev/ic/arn9380.c

336

AR_WRITE(sc, AR_PHY_SWITCH_COM, reg);

sys/dev/ic/arn9380.c

337

reg = AR_READ(sc, AR_PHY_SWITCH_COM_2);

sys/dev/ic/arn9380.c

338

reg = RW(reg, AR_SWITCH_TABLE_COM_2_ALL, modal->antCtrlCommon2);

sys/dev/ic/arn9380.c

339

AR_WRITE(sc, AR_PHY_SWITCH_COM_2, reg);

sys/dev/ic/arn9380.c

343

reg = AR_READ(sc, AR_PHY_SWITCH_CHAIN(i));

sys/dev/ic/arn9380.c

344

reg = RW(reg, AR_SWITCH_TABLE_ALL, modal->antCtrlChain[i]);

sys/dev/ic/arn9380.c

345

AR_WRITE(sc, AR_PHY_SWITCH_CHAIN(i), reg);

sys/dev/ic/arn9380.c

350

reg = AR_READ(sc, AR_PHY_MC_GAIN_CTRL);

sys/dev/ic/arn9380.c

351

reg = RW(reg, AR_PHY_MC_GAIN_CTRL_ANT_DIV_CTRL_ALL,

sys/dev/ic/arn9380.c

354

reg |= AR_PHY_MC_GAIN_CTRL_ENABLE_ANT_DIV;

sys/dev/ic/arn9380.c

356

reg &= ~AR_PHY_MC_GAIN_CTRL_ENABLE_ANT_DIV;

sys/dev/ic/arn9380.c

357

AR_WRITE(sc, AR_PHY_MC_GAIN_CTRL, reg);

sys/dev/ic/arn9380.c

358

reg = AR_READ(sc, AR_PHY_CCK_DETECT);

sys/dev/ic/arn9380.c

360

reg |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;

sys/dev/ic/arn9380.c

362

reg &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;

sys/dev/ic/arn9380.c

363

AR_WRITE(sc, AR_PHY_CCK_DETECT, reg);

sys/dev/ic/arn9380.c

368

reg = AR_READ(sc, AR_PHY_65NM_CH0_BIAS1);

sys/dev/ic/arn9380.c

369

reg = RW(reg, AR_PHY_65NM_CH0_BIAS1_0, 5);

sys/dev/ic/arn9380.c

370

reg = RW(reg, AR_PHY_65NM_CH0_BIAS1_1, 5);

sys/dev/ic/arn9380.c

371

reg = RW(reg, AR_PHY_65NM_CH0_BIAS1_2, 5);

sys/dev/ic/arn9380.c

372

reg = RW(reg, AR_PHY_65NM_CH0_BIAS1_3, 5);

sys/dev/ic/arn9380.c

373

reg = RW(reg, AR_PHY_65NM_CH0_BIAS1_4, 5);

sys/dev/ic/arn9380.c

374

reg = RW(reg, AR_PHY_65NM_CH0_BIAS1_5, 5);

sys/dev/ic/arn9380.c

375

AR_WRITE(sc, AR_PHY_65NM_CH0_BIAS1, reg);

sys/dev/ic/arn9380.c

377

reg = AR_READ(sc, AR_PHY_65NM_CH0_BIAS2);

sys/dev/ic/arn9380.c

378

reg = RW(reg, AR_PHY_65NM_CH0_BIAS2_0, 5);

sys/dev/ic/arn9380.c

379

reg = RW(reg, AR_PHY_65NM_CH0_BIAS2_1, 5);

sys/dev/ic/arn9380.c

380

reg = RW(reg, AR_PHY_65NM_CH0_BIAS2_2, 5);

sys/dev/ic/arn9380.c

381

reg = RW(reg, AR_PHY_65NM_CH0_BIAS2_3, 5);

sys/dev/ic/arn9380.c

382

reg = RW(reg, AR_PHY_65NM_CH0_BIAS2_4, 5);

sys/dev/ic/arn9380.c

383

reg = RW(reg, AR_PHY_65NM_CH0_BIAS2_5, 5);

sys/dev/ic/arn9380.c

384

reg = RW(reg, AR_PHY_65NM_CH0_BIAS2_6, 5);

sys/dev/ic/arn9380.c

385

reg = RW(reg, AR_PHY_65NM_CH0_BIAS2_7, 5);

sys/dev/ic/arn9380.c

386

reg = RW(reg, AR_PHY_65NM_CH0_BIAS2_8, 5);

sys/dev/ic/arn9380.c

387

AR_WRITE(sc, AR_PHY_65NM_CH0_BIAS2, reg);

sys/dev/ic/arn9380.c

389

reg = AR_READ(sc, AR_PHY_65NM_CH0_BIAS4);

sys/dev/ic/arn9380.c

390

reg = RW(reg, AR_PHY_65NM_CH0_BIAS4_0, 5);

sys/dev/ic/arn9380.c

391

reg = RW(reg, AR_PHY_65NM_CH0_BIAS4_1, 5);

sys/dev/ic/arn9380.c

392

reg = RW(reg, AR_PHY_65NM_CH0_BIAS4_2, 5);

sys/dev/ic/arn9380.c

393

AR_WRITE(sc, AR_PHY_65NM_CH0_BIAS4, reg);

sys/dev/ic/arn9380.c

429

reg = AR_READ(sc, AR_PHY_EXT_ATTEN_CTL(i));

sys/dev/ic/arn9380.c

430

reg = RW(reg, AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB, db);

sys/dev/ic/arn9380.c

431

reg = RW(reg, AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN, margin);

sys/dev/ic/arn9380.c

432

AR_WRITE(sc, AR_PHY_EXT_ATTEN_CTL(i), reg);

sys/dev/ic/arn9380.c

444

reg = AR_READ(sc, AR9485_PHY_CH0_XTAL);

sys/dev/ic/arn9380.c

445

reg = RW(reg, AR9485_PHY_CH0_XTAL_CAPINDAC,

sys/dev/ic/arn9380.c

447

reg = RW(reg, AR9485_PHY_CH0_XTAL_CAPOUTDAC,

sys/dev/ic/arn9380.c

449

AR_WRITE(sc, AR9485_PHY_CH0_XTAL, reg);

sys/dev/ic/arn9380.c

495

uint32_t reg;

sys/dev/ic/arn9380.c

503

reg = ar9485_pmu_read(sc, AR_PHY_PMU2);

sys/dev/ic/arn9380.c

504

reg = (reg & ~0xffc00000) | 0x10000000;

sys/dev/ic/arn9380.c

505

ar9485_pmu_write(sc, AR_PHY_PMU2, reg);

sys/dev/ic/arn9380.c

526

uint32_t reg;

sys/dev/ic/arn9380.c

535

reg = AR_READ(sc, AR_PHY_AGC_CONTROL);

sys/dev/ic/arn9380.c

536

reg = RW(reg, AR_PHY_AGC_CONTROL_YCOK_MAX, 0x5);

sys/dev/ic/arn9380.c

537

AR_WRITE(sc, AR_PHY_AGC_CONTROL, reg);

sys/dev/ic/arn9380.c

538

reg = AR_READ(sc, AR_PHY_CCK_SPUR_MIT);

sys/dev/ic/arn9380.c

539

reg = RW(reg, AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, 0);

sys/dev/ic/arn9380.c

540

reg &= ~AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT;

sys/dev/ic/arn9380.c

541

AR_WRITE(sc, AR_PHY_CCK_SPUR_MIT, reg);

sys/dev/ic/arn9380.c

547

reg = AR_READ(sc, AR_PHY_AGC_CONTROL);

sys/dev/ic/arn9380.c

548

reg = RW(reg, AR_PHY_AGC_CONTROL_YCOK_MAX, 0x7);

sys/dev/ic/arn9380.c

549

AR_WRITE(sc, AR_PHY_AGC_CONTROL, reg);

sys/dev/ic/arn9380.c

551

reg = AR_READ(sc, AR_PHY_CCK_SPUR_MIT);

sys/dev/ic/arn9380.c

552

reg = RW(reg, AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, freq);

sys/dev/ic/arn9380.c

553

reg = RW(reg, AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR, 0x7f);

sys/dev/ic/arn9380.c

554

reg = RW(reg, AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE, 0x2);

sys/dev/ic/arn9380.c

555

reg |= AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT;

sys/dev/ic/arn9380.c

556

AR_WRITE(sc, AR_PHY_CCK_SPUR_MIT, reg);

sys/dev/ic/arn9380.c

566

uint32_t reg;

sys/dev/ic/arn9380.c

580

reg = AR_READ(sc, AR_PHY_TIMING11);

sys/dev/ic/arn9380.c

581

reg = RW(reg, AR_PHY_TIMING11_SPUR_FREQ_SD, 0);

sys/dev/ic/arn9380.c

582

reg = RW(reg, AR_PHY_TIMING11_SPUR_DELTA_PHASE, 0);

sys/dev/ic/arn9380.c

583

reg &= ~AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC;

sys/dev/ic/arn9380.c

584

reg &= ~AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR;

sys/dev/ic/arn9380.c

585

AR_WRITE(sc, AR_PHY_TIMING11, reg);

sys/dev/ic/arn9380.c

592

reg = AR_READ(sc, AR_PHY_SPUR_REG);

sys/dev/ic/arn9380.c

593

reg = RW(reg, AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0);

sys/dev/ic/arn9380.c

594

reg &= ~AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI;

sys/dev/ic/arn9380.c

595

reg &= ~AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT;

sys/dev/ic/arn9380.c

596

reg &= ~AR_PHY_SPUR_REG_ENABLE_MASK_PPM;

sys/dev/ic/arn9380.c

597

AR_WRITE(sc, AR_PHY_SPUR_REG, reg);

sys/dev/ic/arn9380.c

632

reg = AR_READ(sc, AR_PHY_GEN_CTRL);

sys/dev/ic/arn9380.c

635

(reg & AR_PHY_GC_DYN2040_PRI_CH) == 0;

sys/dev/ic/arn9380.c

640

(reg & AR_PHY_GC_DYN2040_PRI_CH) != 0;

sys/dev/ic/arn9380.c

655

reg = AR_READ(sc, AR_PHY_TIMING11);

sys/dev/ic/arn9380.c

656

reg = RW(reg, AR_PHY_TIMING11_SPUR_FREQ_SD, spur_freq_sd);

sys/dev/ic/arn9380.c

657

reg = RW(reg, AR_PHY_TIMING11_SPUR_DELTA_PHASE, spur_delta_phase);

sys/dev/ic/arn9380.c

658

reg |= AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC;

sys/dev/ic/arn9380.c

659

reg |= AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR;

sys/dev/ic/arn9380.c

660

AR_WRITE(sc, AR_PHY_TIMING11, reg);

sys/dev/ic/arn9380.c

662

reg = AR_READ(sc, AR_PHY_SFCORR_EXT);

sys/dev/ic/arn9380.c

664

reg |= AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD;

sys/dev/ic/arn9380.c

666

reg &= ~AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD;

sys/dev/ic/arn9380.c

667

AR_WRITE(sc, AR_PHY_SFCORR_EXT, reg);

sys/dev/ic/arn9380.c

671

reg = AR_READ(sc, AR_PHY_SPUR_REG);

sys/dev/ic/arn9380.c

672

reg = RW(reg, AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0xff);

sys/dev/ic/arn9380.c

673

reg = RW(reg, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, 34);

sys/dev/ic/arn9380.c

674

reg |= AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI;

sys/dev/ic/arn9380.c

676

reg |= AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT;

sys/dev/ic/arn9380.c

677

reg |= AR_PHY_SPUR_REG_ENABLE_MASK_PPM;

sys/dev/ic/arn9380.c

678

AR_WRITE(sc, AR_PHY_SPUR_REG, reg);

sys/dev/ic/arn9380.c

689

reg = AR_READ(sc, AR_PHY_PILOT_SPUR_MASK);

sys/dev/ic/arn9380.c

690

reg = RW(reg, AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, idx);

sys/dev/ic/arn9380.c

691

reg = RW(reg, AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0x0c);

sys/dev/ic/arn9380.c

692

AR_WRITE(sc, AR_PHY_PILOT_SPUR_MASK, reg);

sys/dev/ic/arn9380.c

694

reg = AR_READ(sc, AR_PHY_SPUR_MASK_A);

sys/dev/ic/arn9380.c

695

reg = RW(reg, AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, idx);

sys/dev/ic/arn9380.c

696

reg = RW(reg, AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0);

sys/dev/ic/arn9380.c

697

AR_WRITE(sc, AR_PHY_SPUR_MASK_A, reg);

sys/dev/ic/arn9380.c

699

reg = AR_READ(sc, AR_PHY_CHAN_SPUR_MASK);

sys/dev/ic/arn9380.c

700

reg = RW(reg, AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, idx);

sys/dev/ic/arn9380.c

701

reg = RW(reg, AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0x0c);

sys/dev/ic/arn9380.c

702

AR_WRITE(sc, AR_PHY_CHAN_SPUR_MASK, reg);

sys/dev/ic/arn9380.c

867

uint32_t reg;

sys/dev/ic/arn9380.c

882

reg = AR_READ(sc, AR_PHY_TPC_11_B(i));

sys/dev/ic/arn9380.c

883

reg = RW(reg, AR_PHY_TPC_11_OLPC_GAIN_DELTA, corr);

sys/dev/ic/arn9380.c

884

AR_WRITE(sc, AR_PHY_TPC_11_B(i), reg);

sys/dev/ic/arn9380.c

887

reg = AR_READ(sc, AR_PHY_TPC_6_B(i));

sys/dev/ic/arn9380.c

888

reg = RW(reg, AR_PHY_TPC_6_ERROR_EST_MODE, 3);

sys/dev/ic/arn9380.c

889

AR_WRITE(sc, AR_PHY_TPC_6_B(i), reg);

sys/dev/ic/arn9380.c

909

reg = AR_READ(sc, AR_PHY_TPC_19);

sys/dev/ic/arn9380.c

910

reg = RW(reg, AR_PHY_TPC_19_ALPHA_THERM, slope);

sys/dev/ic/arn9380.c

911

AR_WRITE(sc, AR_PHY_TPC_19, reg);

sys/dev/ic/arn9380.c

913

reg = AR_READ(sc, AR_PHY_TPC_18);

sys/dev/ic/arn9380.c

914

reg = RW(reg, AR_PHY_TPC_18_THERM_CAL, temp0);

sys/dev/ic/arn9380.c

915

AR_WRITE(sc, AR_PHY_TPC_18, reg);

sys/dev/ic/athn.c

1182

uint32_t reg;

sys/dev/ic/athn.c

1192

reg = AR_READ(sc, AR_GPIO_INPUT_MUX1);

sys/dev/ic/athn.c

1193

reg = RW(reg, AR_GPIO_INPUT_MUX1_BT_ACTIVE,

sys/dev/ic/athn.c

1195

AR_WRITE(sc, AR_GPIO_INPUT_MUX1, reg);

sys/dev/ic/athn.c

1204

reg = AR_READ(sc, AR_GPIO_INPUT_MUX1);

sys/dev/ic/athn.c

1205

reg = RW(reg, AR_GPIO_INPUT_MUX1_BT_ACTIVE,

sys/dev/ic/athn.c

1207

reg = RW(reg, AR_GPIO_INPUT_MUX1_BT_PRIORITY,

sys/dev/ic/athn.c

1209

AR_WRITE(sc, AR_GPIO_INPUT_MUX1, reg);

sys/dev/ic/athn.c

1221

uint32_t reg;

sys/dev/ic/athn.c

1249

reg = AR_READ(sc, AR_GPIO_PDPU);

sys/dev/ic/athn.c

1250

reg &= ~(0x3 << (AR_GPIO_WLANACTIVE_PIN * 2));

sys/dev/ic/athn.c

1251

reg |= 0x2 << (AR_GPIO_WLANACTIVE_PIN * 2);

sys/dev/ic/athn.c

1252

AR_WRITE(sc, AR_GPIO_PDPU, reg);

sys/dev/ic/athn.c

1717

uint32_t reg;

sys/dev/ic/athn.c

1723

reg = AR_READ(sc, AR_TXCFG);

sys/dev/ic/athn.c

1725

reg = RW(reg, AR_TXCFG_DMASZ, AR_DMASZ_128B);

sys/dev/ic/athn.c

1729

reg = RW(reg, AR_TXCFG_FTRIG, AR_TXCFG_FTRIG_256B);

sys/dev/ic/athn.c

1731

reg = RW(reg, AR_TXCFG_FTRIG, AR_TXCFG_FTRIG_512B);

sys/dev/ic/athn.c

1732

AR_WRITE(sc, AR_TXCFG, reg);

sys/dev/ic/athn.c

1735

reg = AR_READ(sc, AR_RXCFG);

sys/dev/ic/athn.c

1736

reg = RW(reg, AR_RXCFG_DMASZ, AR_DMASZ_128B);

sys/dev/ic/athn.c

1737

AR_WRITE(sc, AR_RXCFG, reg);

sys/dev/ic/athn.c

1760

uint32_t reg, ftrig;

sys/dev/ic/athn.c

1762

reg = AR_READ(sc, AR_TXCFG);

sys/dev/ic/athn.c

1763

ftrig = MS(reg, AR_TXCFG_FTRIG);

sys/dev/ic/athn.c

1770

reg = RW(reg, AR_TXCFG_FTRIG, ftrig + 1);

sys/dev/ic/athn.c

1771

AR_WRITE(sc, AR_TXCFG, reg);

sys/dev/ic/athn.c

1972

uint32_t tsfhi, tsflo, tsftu, reg;

sys/dev/ic/athn.c

2008

reg = AR_READ(sc, AR_RSSI_THR);

sys/dev/ic/athn.c

2009

reg = RW(reg, AR_RSSI_THR_BM_THR, 10);

sys/dev/ic/athn.c

2010

AR_WRITE(sc, AR_RSSI_THR, reg);

sys/dev/ic/athn.c

2068

uint32_t reg;

sys/dev/ic/athn.c

2073

reg = AR_READ(sc, AR_STA_ID1);

sys/dev/ic/athn.c

2074

reg &= ~AR_STA_ID1_ADHOC;

sys/dev/ic/athn.c

2075

reg |= AR_STA_ID1_STA_AP | AR_STA_ID1_KSRCH_MODE;

sys/dev/ic/athn.c

2076

AR_WRITE(sc, AR_STA_ID1, reg);

sys/dev/ic/athn.c

2082

reg = AR_READ(sc, AR_STA_ID1);

sys/dev/ic/athn.c

2083

reg &= ~AR_STA_ID1_STA_AP;

sys/dev/ic/athn.c

2084

reg |= AR_STA_ID1_ADHOC | AR_STA_ID1_KSRCH_MODE;

sys/dev/ic/athn.c

2085

AR_WRITE(sc, AR_STA_ID1, reg);

sys/dev/ic/athn.c

2091

reg = AR_READ(sc, AR_STA_ID1);

sys/dev/ic/athn.c

2092

reg &= ~(AR_STA_ID1_ADHOC | AR_STA_ID1_STA_AP);

sys/dev/ic/athn.c

2093

reg |= AR_STA_ID1_KSRCH_MODE;

sys/dev/ic/athn.c

2094

AR_WRITE(sc, AR_STA_ID1, reg);

sys/dev/ic/athn.c

2187

uint32_t reg, def_ant, sta_id1, cfg_led, tsflo, tsfhi;

sys/dev/ic/athn.c

2241

reg = ops->gpio_read(sc, sc->sc_rfsilent_pin);

sys/dev/ic/athn.c

2243

reg = !reg;

sys/dev/ic/athn.c

2244

if (!reg) {

sys/dev/ic/athn.c

2275

reg = AR_READ(sc, AR_AES_MUTE_MASK1);

sys/dev/ic/athn.c

2277

reg = RW(reg, AR_AES_MUTE_MASK1_FC0_MGMT, 0xff);

sys/dev/ic/athn.c

2278

reg = RW(reg, AR_AES_MUTE_MASK1_FC1_MGMT,

sys/dev/ic/athn.c

2281

AR_WRITE(sc, AR_AES_MUTE_MASK1, reg);

sys/dev/ic/athn.c

2494

uint32_t reg;

sys/dev/ic/athn.c

2543

reg = AR_READ(sc, AR_RX_FILTER);

sys/dev/ic/athn.c

2544

reg = (reg & ~AR_RX_FILTER_BEACON) |

sys/dev/ic/athn.c

2546

AR_WRITE(sc, AR_RX_FILTER, reg);

sys/dev/ic/athn.c

528

reg = AR_READ(sc, AR_PHY_ERR);

sys/dev/ic/athn.c

529

reg &= (AR_PHY_ERR_RADAR | AR_PHY_ERR_OFDM_TIMING |

sys/dev/ic/athn.c

531

AR_WRITE(sc, AR_PHY_ERR, reg);

sys/dev/ic/athn.c

532

if (reg != 0)

sys/dev/ic/athn.c

597

uint32_t reg;

sys/dev/ic/athn.c

599

reg = AR_READ(sc, AR_SREV);

sys/dev/ic/athn.c

600

if (MS(reg, AR_SREV_ID) == 0xff) {

sys/dev/ic/athn.c

601

sc->sc_mac_ver = MS(reg, AR_SREV_VERSION2);

sys/dev/ic/athn.c

602

sc->sc_mac_rev = MS(reg, AR_SREV_REVISION2);

sys/dev/ic/athn.c

603

if (!(reg & AR_SREV_TYPE2_HOST_MODE))

sys/dev/ic/athn.c

606

sc->sc_mac_ver = MS(reg, AR_SREV_VERSION);

sys/dev/ic/athn.c

607

sc->sc_mac_rev = MS(reg, AR_SREV_REVISION);

sys/dev/ic/athnreg.h

1459

#define AR_READ(sc, reg) \

sys/dev/ic/athnreg.h

1460

(sc)->sc_ops.read((sc), (reg))

sys/dev/ic/athnreg.h

1462

#define AR_WRITE(sc, reg, val) \

sys/dev/ic/athnreg.h

1463

(sc)->sc_ops.write((sc), (reg), (val))

sys/dev/ic/athnreg.h

1468

#define AR_SETBITS(sc, reg, mask) \

sys/dev/ic/athnreg.h

1469

AR_WRITE(sc, reg, AR_READ(sc, reg) | (mask))

sys/dev/ic/athnreg.h

1471

#define AR_CLRBITS(sc, reg, mask) \

sys/dev/ic/athnreg.h

1472

AR_WRITE(sc, reg, AR_READ(sc, reg) & ~(mask))

sys/dev/ic/atppc.c

1135

register int reg;

sys/dev/ic/atppc.c

1164

reg = mi->arg[1].i;

sys/dev/ic/atppc.c

1170

w_reg(reg, atppc, *ptr++);

sys/dev/ic/atppc.c

1176

w_reg(reg, atppc, *ptr++);

sys/dev/ic/atppc.c

1186

reg = mi->arg[1].i;

sys/dev/ic/atppc.c

1193

*ptr++ = r_reg(reg, atppc) & mask;

sys/dev/ic/atppc.c

1199

*ptr++ = r_reg(reg, atppc) & mask;

sys/dev/ic/atppc.c

1240

reg = mi->arg[0].i;

sys/dev/ic/atppc.c

1246

w_reg(reg, atppc, *p++);

sys/dev/ic/atw.c

1716

uint32_t reg;

sys/dev/ic/atw.c

1772

reg = ATW_READ(sc, ATW_PLCPHD);

sys/dev/ic/atw.c

1773

reg &= ~ATW_PLCPHD_SERVICE_MASK;

sys/dev/ic/atw.c

1774

reg |= __SHIFTIN(__SHIFTIN(txpower, RF3000_GAINCTL_TXVGC_MASK),

sys/dev/ic/atw.c

1776

ATW_WRITE(sc, ATW_PLCPHD, reg);

sys/dev/ic/atw.c

1790

uint32_t reg;

sys/dev/ic/atw.c

1793

reg = sc->sc_bbpctl_wr |

sys/dev/ic/atw.c

1798

ATW_WRITE(sc, ATW_BBPCTL, reg);

sys/dev/ic/atw.c

1828

uint32_t reg;

sys/dev/ic/atw.c

1844

reg = sc->sc_bbpctl_rd | __SHIFTIN(addr & 0x7f, ATW_BBPCTL_ADDR_MASK);

sys/dev/ic/atw.c

1846

ATW_WRITE(sc, ATW_BBPCTL, reg);

sys/dev/ic/atw.c

1858

device_xname(sc->sc_dev), reg);

sys/dev/ic/atw.c

1862

*val = __SHIFTOUT(reg, ATW_BBPCTL_DATA_MASK);

sys/dev/ic/atw.c

1877

uint32_t bits, mask, reg;

sys/dev/ic/atw.c

1886

reg = ATW_SYNRF_SELSYN;

sys/dev/ic/atw.c

1890

ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_LEIF);

sys/dev/ic/atw.c

1891

ATW_WRITE(sc, ATW_SYNRF, reg);

sys/dev/ic/atw.c

1895

reg |= ATW_SYNRF_SYNDATA;

sys/dev/ic/atw.c

1897

reg &= ~ATW_SYNRF_SYNDATA;

sys/dev/ic/atw.c

1898

ATW_WRITE(sc, ATW_SYNRF, reg);

sys/dev/ic/atw.c

1899

ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_SYNCLK);

sys/dev/ic/atw.c

1900

ATW_WRITE(sc, ATW_SYNRF, reg);

sys/dev/ic/atw.c

1902

ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_LEIF);

sys/dev/ic/atw.c

1916

uint32_t reg;

sys/dev/ic/atw.c

1934

reg = sc->sc_synctl_rd | __SHIFTIN(addr, ATW_SYNCTL_DATA_MASK);

sys/dev/ic/atw.c

1936

ATW_WRITE(sc, ATW_SYNCTL, reg);

sys/dev/ic/atw.c

1948

device_xname(sc->sc_dev), reg);

sys/dev/ic/atw.c

2180

uint32_t reg;

sys/dev/ic/atw.c

2207

reg = ATW_READ(sc, ATW_MACTEST);

sys/dev/ic/atw.c

2208

reg |= ATW_MACTEST_MMI_USETXCLK | ATW_MACTEST_FORCE_KEYID;

sys/dev/ic/atw.c

2209

reg &= ~ATW_MACTEST_KEYID_MASK;

sys/dev/ic/atw.c

2210

reg |= __SHIFTIN(ic->ic_def_txkey, ATW_MACTEST_KEYID_MASK);

sys/dev/ic/atw.c

2211

ATW_WRITE(sc, ATW_MACTEST, reg);

sys/dev/ic/atw.c

422

#define PRINTREG(sc, reg) \

sys/dev/ic/atw.c

423

ATW_DPRINTF2(("%s: reg[ " #reg " / %03x ] = %08x\n", \

sys/dev/ic/atw.c

424

device_xname(sc->sc_dev), reg, ATW_READ(sc, reg)))

sys/dev/ic/atw.c

512

uint32_t reg;

sys/dev/ic/atw.c

642

reg = __SHIFTIN(sc->sc_rftype, ATW_SYNCTL_RFTYPE_MASK);

sys/dev/ic/atw.c

646

reg |= ATW_SYNCTL_CS1;

sys/dev/ic/atw.c

649

reg |= ATW_SYNCTL_CS0;

sys/dev/ic/atw.c

655

sc->sc_synctl_rd = reg | ATW_SYNCTL_RD;

sys/dev/ic/atw.c

656

sc->sc_synctl_wr = reg | ATW_SYNCTL_WR;

sys/dev/ic/atw.c

658

reg = __SHIFTIN(sc->sc_bbptype, ATW_BBPCTL_TYPE_MASK);

sys/dev/ic/atw.c

662

reg |= ATW_BBPCTL_TWI;

sys/dev/ic/atw.c

665

reg |= ATW_BBPCTL_RF3KADDR_ADDR | ATW_BBPCTL_NEGEDGE_DO |

sys/dev/ic/atw.c

676

sc->sc_bbpctl_wr = reg | ATW_BBPCTL_WR;

sys/dev/ic/atw.c

677

sc->sc_bbpctl_rd = reg | ATW_BBPCTL_RD;

sys/dev/ic/atw.c

744

reg = ATW_READ(sc, ATW_PAR0);

sys/dev/ic/atw.c

745

ic->ic_myaddr[0] = __SHIFTOUT(reg, ATW_PAR0_PAB0_MASK);

sys/dev/ic/atw.c

746

ic->ic_myaddr[1] = __SHIFTOUT(reg, ATW_PAR0_PAB1_MASK);

sys/dev/ic/atw.c

747

ic->ic_myaddr[2] = __SHIFTOUT(reg, ATW_PAR0_PAB2_MASK);

sys/dev/ic/atw.c

748

ic->ic_myaddr[3] = __SHIFTOUT(reg, ATW_PAR0_PAB3_MASK);

sys/dev/ic/atw.c

749

reg = ATW_READ(sc, ATW_PAR1);

sys/dev/ic/atw.c

750

ic->ic_myaddr[4] = __SHIFTOUT(reg, ATW_PAR1_PAB4_MASK);

sys/dev/ic/atw.c

751

ic->ic_myaddr[5] = __SHIFTOUT(reg, ATW_PAR1_PAB5_MASK);

sys/dev/ic/atwvar.h

433

#define ATW_READ(sc, reg) \

sys/dev/ic/atwvar.h

434

bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))

sys/dev/ic/atwvar.h

436

#define ATW_WRITE(sc, reg, val) \

sys/dev/ic/atwvar.h

437

bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))

sys/dev/ic/atwvar.h

439

#define ATW_SET(sc, reg, mask) \

sys/dev/ic/atwvar.h

440

ATW_WRITE((sc), (reg), ATW_READ((sc), (reg)) | (mask))

sys/dev/ic/atwvar.h

442

#define ATW_CLR(sc, reg, mask) \

sys/dev/ic/atwvar.h

443

ATW_WRITE((sc), (reg), ATW_READ((sc), (reg)) & ~(mask))

sys/dev/ic/atwvar.h

445

#define ATW_ISSET(sc, reg, mask) \

sys/dev/ic/atwvar.h

446

(ATW_READ((sc), (reg)) & (mask))

sys/dev/ic/ax88190.c

184

ax88190_mii_readreg(device_t self, int phy, int reg, uint16_t *val)

sys/dev/ic/ax88190.c

187

return mii_bitbang_readreg(self, &ax88190_mii_bitbang_ops, phy, reg,

sys/dev/ic/ax88190.c

192

ax88190_mii_writereg(device_t self, int phy, int reg, uint16_t val)

sys/dev/ic/ax88190.c

195

return mii_bitbang_writereg(self, &ax88190_mii_bitbang_ops, phy, reg,

sys/dev/ic/bcmgenet.c

101

__SHIFTIN(reg, GENET_MDIO_REG));

sys/dev/ic/bcmgenet.c

112

phy, reg);

sys/dev/ic/bcmgenet.c

120

genet_mii_writereg(device_t dev, int phy, int reg, uint16_t val)

sys/dev/ic/bcmgenet.c

128

__SHIFTIN(reg, GENET_MDIO_REG));

sys/dev/ic/bcmgenet.c

137

phy, reg);

sys/dev/ic/bcmgenet.c

87

#define RD4(sc, reg) \

sys/dev/ic/bcmgenet.c

88

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/dev/ic/bcmgenet.c

89

#define WR4(sc, reg, val) \

sys/dev/ic/bcmgenet.c

90

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/dev/ic/bcmgenet.c

93

genet_mii_readreg(device_t dev, int phy, int reg, uint16_t *val)

sys/dev/ic/bmx280.c

397

uint8_t reg, chip_id;

sys/dev/ic/bmx280.c

451

reg = BMX280_REGISTER_ID;

sys/dev/ic/bmx280.c

452

error = sc->sc_funcs->read_reg(sc, reg, &chip_id, 1);

sys/dev/ic/bmx280.c

468

reg = BMX280_REGISTER_DIG_T1;

sys/dev/ic/bmx280.c

469

error = sc->sc_funcs->read_reg(sc, reg, raw_blob_tp, 24);

sys/dev/ic/bmx280.c

487

reg = BMX280_REGISTER_DIG_H1;

sys/dev/ic/bmx280.c

488

error = sc->sc_funcs->read_reg(sc, reg, raw_blob_h, 1);

sys/dev/ic/bmx280.c

494

reg = BMX280_REGISTER_DIG_H2;

sys/dev/ic/bmx280.c

495

error = sc->sc_funcs->read_reg(sc, reg, &raw_blob_h[1], 7);

sys/dev/ic/bmx280.c

732

uint8_t reg;

sys/dev/ic/bmx280.c

737

reg = BMX280_REGISTER_STATUS;

sys/dev/ic/bmx280.c

740

ierror = sc->sc_funcs->read_reg(sc, reg, &running, 1);

sys/dev/ic/bmx280.c

767

uint8_t raw_press_temp_hum[8], reg;

sys/dev/ic/bmx280.c

775

reg = BMX280_REGISTER_TEMP_MSB;

sys/dev/ic/bmx280.c

781

reg = BMX280_REGISTER_PRESS_MSB;

sys/dev/ic/bmx280.c

793

device_xname(sc->sc_dev), reg, rlen, rtstart, rpstart));

sys/dev/ic/bmx280.c

795

ierror = sc->sc_funcs->read_reg(sc, reg, raw_press_temp_hum, rlen);

sys/dev/ic/bwfm.c

1518

uint32_t reg;

sys/dev/ic/bwfm.c

1530

reg = sc->sc_buscore_ops->bc_read(sc, core->co_base +

sys/dev/ic/bwfm.c

1532

return (reg & (1 << 2)) != 0;

sys/dev/ic/bwfm.c

1539

reg = sc->sc_buscore_ops->bc_read(sc, core->co_base +

sys/dev/ic/bwfm.c

1541

return reg != 0;

sys/dev/ic/bwfm.c

1544

reg = sc->sc_buscore_ops->bc_read(sc, core->co_base +

sys/dev/ic/bwfm.c

1546

return reg != 0;

sys/dev/ic/bwfm.c

1549

reg = sc->sc_buscore_ops->bc_read(sc, core->co_base +

sys/dev/ic/bwfm.c

1551

if ((reg & BWFM_CHIP_REG_PMUCAPABILITIES_SR_SUPP) == 0)

sys/dev/ic/bwfm.c

1553

reg = sc->sc_buscore_ops->bc_read(sc, core->co_base +

sys/dev/ic/bwfm.c

1555

return (reg & (BWFM_CHIP_REG_RETENTION_CTL_MACPHY_DIS |

sys/dev/ic/bwivar.h

100

CSR_WRITE_4((sc), (reg), (CSR_READ_4((sc), (reg)) & (filt)) | (bits))

sys/dev/ic/bwivar.h

101

#define CSR_FILT_SETBITS_2(sc, reg, filt, bits) \

sys/dev/ic/bwivar.h

102

CSR_WRITE_2((sc), (reg), (CSR_READ_2((sc), (reg)) & (filt)) | (bits))

sys/dev/ic/bwivar.h

104

#define CSR_CLRBITS_4(sc, reg, bits) \

sys/dev/ic/bwivar.h

105

CSR_WRITE_4((sc), (reg), CSR_READ_4((sc), (reg)) & ~(bits))

sys/dev/ic/bwivar.h

106

#define CSR_CLRBITS_2(sc, reg, bits) \

sys/dev/ic/bwivar.h

107

CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) & ~(bits))

sys/dev/ic/bwivar.h

714

_bwi_read_multi_4(struct bwi_softc *sc, bus_size_t reg, uint32_t *datap,

sys/dev/ic/bwivar.h

718

return sc->sc_reg_read_multi_4(sc, reg, datap, count);

sys/dev/ic/bwivar.h

721

reg, datap, count);

sys/dev/ic/bwivar.h

726

_bwi_read_2(struct bwi_softc *sc, bus_size_t reg)

sys/dev/ic/bwivar.h

729

return sc->sc_reg_read_2(sc, reg);

sys/dev/ic/bwivar.h

731

return bus_space_read_2(sc->sc_mem_bt, sc->sc_mem_bh, reg);

sys/dev/ic/bwivar.h

736

_bwi_read_4(struct bwi_softc *sc, bus_size_t reg)

sys/dev/ic/bwivar.h

739

return sc->sc_reg_read_4(sc, reg);

sys/dev/ic/bwivar.h

741

return bus_space_read_4(sc->sc_mem_bt, sc->sc_mem_bh, reg);

sys/dev/ic/bwivar.h

746

_bwi_write_multi_4(struct bwi_softc *sc, bus_size_t reg, const uint32_t *datap,

sys/dev/ic/bwivar.h

750

return sc->sc_reg_write_multi_4(sc, reg, datap, count);

sys/dev/ic/bwivar.h

753

reg, datap, count);

sys/dev/ic/bwivar.h

758

_bwi_write_2(struct bwi_softc *sc, bus_size_t reg, uint16_t val)

sys/dev/ic/bwivar.h

761

sc->sc_reg_write_2(sc, reg, val);

sys/dev/ic/bwivar.h

763

bus_space_write_2(sc->sc_mem_bt, sc->sc_mem_bh, reg, val);

sys/dev/ic/bwivar.h

768

_bwi_write_4(struct bwi_softc *sc, bus_size_t reg, uint32_t val)

sys/dev/ic/bwivar.h

771

sc->sc_reg_write_4(sc, reg, val);

sys/dev/ic/bwivar.h

773

bus_space_write_4(sc->sc_mem_bt, sc->sc_mem_bh, reg, val);

sys/dev/ic/bwivar.h

80

#define CSR_READ_4(sc, reg) \

sys/dev/ic/bwivar.h

81

_bwi_read_4(sc, reg)

sys/dev/ic/bwivar.h

82

#define CSR_READ_2(sc, reg) \

sys/dev/ic/bwivar.h

83

_bwi_read_2(sc, reg)

sys/dev/ic/bwivar.h

84

#define CSR_READ_MULTI_4(sc, reg, datap, count) \

sys/dev/ic/bwivar.h

85

_bwi_read_multi_4(sc, reg, datap, count)

sys/dev/ic/bwivar.h

87

#define CSR_WRITE_4(sc, reg, val) \

sys/dev/ic/bwivar.h

88

_bwi_write_4(sc, reg, val)

sys/dev/ic/bwivar.h

89

#define CSR_WRITE_2(sc, reg, val) \

sys/dev/ic/bwivar.h

90

_bwi_write_2(sc, reg, val)

sys/dev/ic/bwivar.h

91

#define CSR_WRITE_MULTI_4(sc, reg, datap, count) \

sys/dev/ic/bwivar.h

92

_bwi_write_multi_4(sc, reg, datap, count)

sys/dev/ic/bwivar.h

94

#define CSR_SETBITS_4(sc, reg, bits) \

sys/dev/ic/bwivar.h

95

CSR_WRITE_4((sc), (reg), CSR_READ_4((sc), (reg)) | (bits))

sys/dev/ic/bwivar.h

96

#define CSR_SETBITS_2(sc, reg, bits) \

sys/dev/ic/bwivar.h

97

CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) | (bits))

sys/dev/ic/bwivar.h

99

#define CSR_FILT_SETBITS_4(sc, reg, filt, bits) \

sys/dev/ic/cdnsiic.c

88

#define RD4(sc, reg) \

sys/dev/ic/cdnsiic.c

89

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/dev/ic/cdnsiic.c

90

#define WR4(sc, reg, val) \

sys/dev/ic/cdnsiic.c

91

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/dev/ic/clmpcc.c

1073

u_char reg;

sys/dev/ic/clmpcc.c

1078

reg = clmpcc_rdreg(sc, CLMPCC_REG_COR4);

sys/dev/ic/clmpcc.c

1079

clmpcc_wrreg(sc, CLMPCC_REG_COR4, reg & ~CLMPCC_COR4_FIFO_MASK);

sys/dev/ic/clmpcc.c

1080

reg = clmpcc_rdreg(sc, CLMPCC_REG_IER);

sys/dev/ic/clmpcc.c

1081

clmpcc_wrreg(sc, CLMPCC_REG_IER, reg & ~CLMPCC_IER_RET);

sys/dev/ic/clmpcc.c

1161

u_char reg;

sys/dev/ic/clmpcc.c

1166

reg = clmpcc_rdreg(sc, CLMPCC_REG_COR4);

sys/dev/ic/clmpcc.c

1167

reg = (reg & ~CLMPCC_COR4_FIFO_MASK) | ch->ch_cor4;

sys/dev/ic/clmpcc.c

1168

clmpcc_wrreg(sc, CLMPCC_REG_COR4, reg);

sys/dev/ic/clmpcc.c

1169

reg = clmpcc_rdreg(sc, CLMPCC_REG_IER);

sys/dev/ic/clmpcc.c

1170

clmpcc_wrreg(sc, CLMPCC_REG_IER, reg | CLMPCC_IER_RET);

sys/dev/ic/clmpcc.c

1341

u_char reg;

sys/dev/ic/clmpcc.c

1397

reg = clmpcc_rd_msvr(sc) & CLMPCC_MSVR_CD;

sys/dev/ic/clmpcc.c

1398

(*tp->t_linesw->l_modem)(tp, reg != 0);

sys/dev/ic/com.c

1874

int reg;

sys/dev/ic/com.c

1879

reg = 0xffff;

sys/dev/ic/com.c

1886

reg =

sys/dev/ic/com.c

1893

aprint_error_dev(sc->sc_dev, "com_iflush timeout %02x\n", reg);

sys/dev/ic/com.c

322

com_read_1(struct com_regs *regs, u_int reg)

sys/dev/ic/com.c

324

return bus_space_read_1(regs->cr_iot, regs->cr_ioh, reg);

sys/dev/ic/com.c

332

com_write_1(struct com_regs *regs, u_int reg, uint8_t val)

sys/dev/ic/com.c

334

bus_space_write_1(regs->cr_iot, regs->cr_ioh, reg, val);

sys/dev/ic/com.c

342

com_write_multi_1(struct com_regs *regs, u_int reg, const uint8_t *datap,

sys/dev/ic/com.c

345

bus_space_write_multi_1(regs->cr_iot, regs->cr_ioh, reg, datap, count);

sys/dev/ic/com.c

353

com_read_4(struct com_regs *regs, u_int reg)

sys/dev/ic/com.c

355

return bus_space_read_4(regs->cr_iot, regs->cr_ioh, reg) & 0xff;

sys/dev/ic/com.c

363

com_write_4(struct com_regs *regs, u_int reg, uint8_t val)

sys/dev/ic/com.c

365

bus_space_write_4(regs->cr_iot, regs->cr_ioh, reg, val);

sys/dev/ic/com.c

373

com_write_multi_4(struct com_regs *regs, u_int reg, const uint8_t *datap,

sys/dev/ic/com.c

377

bus_space_write_4(regs->cr_iot, regs->cr_ioh, reg, *datap++);

sys/dev/ic/cpc700.c

264

u_int32_t reg;

sys/dev/ic/cpc700.c

266

reg = INL(CPC_UIC_ER);

sys/dev/ic/cpc700.c

267

reg &= ~CPC_INTR_MASK(irq);

sys/dev/ic/cpc700.c

268

OUTL(CPC_UIC_ER, reg);

sys/dev/ic/cpc700.c

274

u_int32_t reg;

sys/dev/ic/cpc700.c

276

reg = INL(CPC_UIC_ER);

sys/dev/ic/cpc700.c

277

reg |= CPC_INTR_MASK(irq);

sys/dev/ic/cpc700.c

278

OUTL(CPC_UIC_ER, reg);

sys/dev/ic/cs4231.c

115

int reg;

sys/dev/ic/cs4231.c

148

reg = ad_read(&sc->sc_ad1848, SP_MISC_INFO);

sys/dev/ic/cs4231.c

149

ad_write(&sc->sc_ad1848, SP_MISC_INFO, reg | MODE2);

sys/dev/ic/cs4231.c

152

reg = ad_read(&sc->sc_ad1848, CS_VERSION_ID);

sys/dev/ic/cs4231.c

153

switch (reg & (CS_VERSION_NUMBER | CS_VERSION_CHIPID)) {

sys/dev/ic/cs4231.c

169

reg&0xe0, reg&7);

sys/dev/ic/cs89x0.c

332

uint16_t reg;

sys/dev/ic/cs89x0.c

340

reg = CS_READ_PACKET_PAGE(sc, PKTPG_EISA_NUM);

sys/dev/ic/cs89x0.c

341

if (reg == EISA_NUM_CRYSTAL)

sys/dev/ic/cs89x0.c

345

aprint_error_dev(sc->sc_dev, "wrong id(0x%x)\n", reg);

sys/dev/ic/cs89x0.c

349

reg = CS_READ_PACKET_PAGE(sc, PKTPG_PRODUCT_ID);

sys/dev/ic/cs89x0.c

350

sc->sc_prodid = reg & PROD_ID_MASK;

sys/dev/ic/cs89x0.c

351

sc->sc_prodrev = (reg & PROD_REV_MASK) >> 8;

sys/dev/ic/ct65550.c

1001

uint8_t reg;

sys/dev/ic/ct65550.c

1009

reg = chipsfb_read_indexed(sc, CT_CONF_INDEX, XR_PIXEL_PIPELINE_CTL_0);

sys/dev/ic/ct65550.c

1010

reg |= ENABLE_8BIT_DAC;

sys/dev/ic/ct65550.c

1011

chipsfb_write_indexed(sc, CT_CONF_INDEX, XR_PIXEL_PIPELINE_CTL_0, reg);

sys/dev/ic/ct65550.c

132

chipsfb_write32(struct chipsfb_softc *sc, uint32_t reg, uint32_t val)

sys/dev/ic/ct65550.c

134

bus_space_write_4(sc->sc_memt, sc->sc_mmregh, reg, val);

sys/dev/ic/ct65550.c

138

chipsfb_read32(struct chipsfb_softc *sc, uint32_t reg)

sys/dev/ic/ct65550.c

140

return bus_space_read_4(sc->sc_memt, sc->sc_mmregh, reg);

sys/dev/ic/ct65550.c

144

chipsfb_write_vga(struct chipsfb_softc *sc, uint32_t reg, uint8_t val)

sys/dev/ic/ct65550.c

146

bus_space_write_1(sc->sc_iot, sc->sc_ioregh, reg, val);

sys/dev/ic/ct65550.c

150

chipsfb_read_vga(struct chipsfb_softc *sc, uint32_t reg)

sys/dev/ic/ct65550.c

152

return bus_space_read_1(sc->sc_iot, sc->sc_ioregh, reg);

sys/dev/ic/ct65550.c

156

chipsfb_read_indexed(struct chipsfb_softc *sc, uint32_t reg, uint8_t index)

sys/dev/ic/ct65550.c

159

chipsfb_write_vga(sc, reg & 0xfffe, index);

sys/dev/ic/ct65550.c

160

return chipsfb_read_vga(sc, reg | 0x0001);

sys/dev/ic/ct65550.c

164

chipsfb_write_indexed(struct chipsfb_softc *sc, uint32_t reg, uint8_t index,

sys/dev/ic/ct65550.c

168

chipsfb_write_vga(sc, reg & 0xfffe, index);

sys/dev/ic/ct65550.c

169

chipsfb_write_vga(sc, reg | 0x0001, val);

sys/dev/ic/cyvar.h

33

#define cd_read_reg(sc,chip,reg) bus_space_read_1(sc->sc_memt, \

sys/dev/ic/cyvar.h

35

(((reg << 1)) << sc->sc_bustype))

sys/dev/ic/cyvar.h

37

#define cd_write_reg(sc,chip,reg,val) bus_space_write_1(sc->sc_memt, \

sys/dev/ic/cyvar.h

39

(((reg << 1))<< sc->sc_bustype), (val))

sys/dev/ic/dl10019.c

226

dl10019_mii_readreg(device_t self, int phy, int reg, uint16_t *val)

sys/dev/ic/dl10019.c

234

return mii_bitbang_readreg(self, ops, phy, reg, val);

sys/dev/ic/dl10019.c

238

dl10019_mii_writereg(device_t self, int phy, int reg, uint16_t val)

sys/dev/ic/dl10019.c

246

return mii_bitbang_writereg(self, ops, phy, reg, val);

sys/dev/ic/dm9000.c

1074

uint16_t i, reg;

sys/dev/ic/dm9000.c

1077

reg = bus_space_read_1(sc->sc_iot, sc->sc_ioh, sc->dme_data);

sys/dev/ic/dm9000.c

1078

reg |= bus_space_read_1(sc->sc_iot, sc->sc_ioh, sc->dme_data) << 8;

sys/dev/ic/dm9000.c

1079

rx_status = reg & 0xFF;

sys/dev/ic/dm9000.c

1081

reg = bus_space_read_1(sc->sc_iot, sc->sc_ioh, sc->dme_data);

sys/dev/ic/dm9000.c

1082

reg |= bus_space_read_1(sc->sc_iot, sc->sc_ioh, sc->dme_data) << 8;

sys/dev/ic/dm9000.c

1083

frame_length = reg;

sys/dev/ic/dm9000.c

514

mii_readreg(device_t self, int phy, int reg, uint16_t *val)

sys/dev/ic/dm9000.c

523

(reg & DM9000_EPAR_EROA_MASK));

sys/dev/ic/dm9000.c

539

mii_writereg(device_t self, int phy, int reg, uint16_t val)

sys/dev/ic/dm9000.c

548

(reg & DM9000_EPAR_EROA_MASK));

sys/dev/ic/dm9000var.h

119

dme_read(struct dme_softc *sc, int reg)

sys/dev/ic/dm9000var.h

121

bus_space_write_1(sc->sc_iot, sc->sc_ioh, sc->dme_io, reg);

sys/dev/ic/dm9000var.h

126

dme_write(struct dme_softc *sc, int reg, uint8_t value)

sys/dev/ic/dm9000var.h

128

bus_space_write_1(sc->sc_iot, sc->sc_ioh, sc->dme_io, reg);

sys/dev/ic/dm9000var.h

133

dme_write2(struct dme_softc *sc, int reg, uint16_t value)

sys/dev/ic/dm9000var.h

135

bus_space_write_1(sc->sc_iot, sc->sc_ioh, sc->dme_io, reg);

sys/dev/ic/dm9000var.h

140

dme_write_c(struct dme_softc *sc, int reg, const uint8_t value[], uint count)

sys/dev/ic/dm9000var.h

143

dme_write(sc, reg+i, value[i]);

sys/dev/ic/dm9000var.h

148

dme_read_c(struct dme_softc *sc, int reg, uint8_t *value, uint count)

sys/dev/ic/dm9000var.h

151

value[i] = dme_read(sc, reg+i);

sys/dev/ic/dp8390var.h

151

#define NIC_GET(t, h, reg) bus_space_read_1(t, h, \

sys/dev/ic/dp8390var.h

152

((sc)->sc_reg_map[reg]))

sys/dev/ic/dp8390var.h

153

#define NIC_PUT(t, h, reg, val) bus_space_write_1(t, h, \

sys/dev/ic/dp8390var.h

154

((sc)->sc_reg_map[reg]), (val))

sys/dev/ic/dp83932.c

900

uint16_t reg;

sys/dev/ic/dp83932.c

918

reg = sc->sc_dcr;

sys/dev/ic/dp83932.c

920

reg |= DCR_DW;

sys/dev/ic/dp83932.c

922

CSR_WRITE(sc, SONIC_DCR, reg);

sys/dev/ic/dp83932var.h

207

#define CSR_READ(sc, reg) \

sys/dev/ic/dp83932var.h

209

(sc)->sc_regmap[(reg)])

sys/dev/ic/dp83932var.h

211

#define CSR_WRITE(sc, reg, val) \

sys/dev/ic/dp83932var.h

213

(sc)->sc_regmap[(reg)], (val))

sys/dev/ic/dw_hdmi.c

318

dwhdmi_read(struct dwhdmi_softc *sc, bus_size_t reg)

sys/dev/ic/dw_hdmi.c

324

val = bus_space_read_1(sc->sc_bst, sc->sc_bsh, reg);

sys/dev/ic/dw_hdmi.c

327

val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, reg * 4) & 0xff;

sys/dev/ic/dw_hdmi.c

338

dwhdmi_write(struct dwhdmi_softc *sc, bus_size_t reg, uint8_t val)

sys/dev/ic/dw_hdmi.c

342

bus_space_write_1(sc->sc_bst, sc->sc_bsh, reg, val);

sys/dev/ic/dw_hdmi.c

345

bus_space_write_4(sc->sc_bst, sc->sc_bsh, reg * 4, val);

sys/dev/ic/dw_hdmi_phy.c

183

uint8_t reg;

sys/dev/ic/dw_hdmi_phy.c

185

reg = dwhdmi_read(sc, HDMI_PHY_CONF0);

sys/dev/ic/dw_hdmi_phy.c

186

reg &= ~HDMI_PHY_CONF0_PDZ_MASK;

sys/dev/ic/dw_hdmi_phy.c

187

reg |= (enable << HDMI_PHY_CONF0_PDZ_OFFSET);

sys/dev/ic/dw_hdmi_phy.c

188

dwhdmi_write(sc, HDMI_PHY_CONF0, reg);

sys/dev/ic/dw_hdmi_phy.c

194

uint8_t reg;

sys/dev/ic/dw_hdmi_phy.c

196

reg = dwhdmi_read(sc, HDMI_PHY_CONF0);

sys/dev/ic/dw_hdmi_phy.c

197

reg &= ~HDMI_PHY_CONF0_ENTMDS_MASK;

sys/dev/ic/dw_hdmi_phy.c

198

reg |= (enable << HDMI_PHY_CONF0_ENTMDS_OFFSET);

sys/dev/ic/dw_hdmi_phy.c

199

dwhdmi_write(sc, HDMI_PHY_CONF0, reg);

sys/dev/ic/dw_hdmi_phy.c

205

uint8_t reg;

sys/dev/ic/dw_hdmi_phy.c

207

reg = dwhdmi_read(sc, HDMI_PHY_CONF0);

sys/dev/ic/dw_hdmi_phy.c

208

reg &= ~HDMI_PHY_CONF0_GEN2_PDDQ_MASK;

sys/dev/ic/dw_hdmi_phy.c

209

reg |= (enable << HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET);

sys/dev/ic/dw_hdmi_phy.c

210

dwhdmi_write(sc, HDMI_PHY_CONF0, reg);

sys/dev/ic/dw_hdmi_phy.c

216

uint8_t reg;

sys/dev/ic/dw_hdmi_phy.c

218

reg = dwhdmi_read(sc, HDMI_PHY_CONF0);

sys/dev/ic/dw_hdmi_phy.c

219

reg &= ~HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;

sys/dev/ic/dw_hdmi_phy.c

220

reg |= (enable << HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET);

sys/dev/ic/dw_hdmi_phy.c

221

dwhdmi_write(sc, HDMI_PHY_CONF0, reg);

sys/dev/ic/dw_hdmi_phy.c

227

uint8_t reg;

sys/dev/ic/dw_hdmi_phy.c

229

reg = dwhdmi_read(sc, HDMI_PHY_CONF0);

sys/dev/ic/dw_hdmi_phy.c

230

reg &= ~HDMI_PHY_CONF0_SELDATAENPOL_MASK;

sys/dev/ic/dw_hdmi_phy.c

231

reg |= (enable << HDMI_PHY_CONF0_SELDATAENPOL_OFFSET);

sys/dev/ic/dw_hdmi_phy.c

232

dwhdmi_write(sc, HDMI_PHY_CONF0, reg);

sys/dev/ic/dw_hdmi_phy.c

238

uint8_t reg;

sys/dev/ic/dw_hdmi_phy.c

240

reg = dwhdmi_read(sc, HDMI_PHY_CONF0);

sys/dev/ic/dw_hdmi_phy.c

241

reg &= ~HDMI_PHY_CONF0_SELDIPIF_MASK;

sys/dev/ic/dw_hdmi_phy.c

242

reg |= (enable << HDMI_PHY_CONF0_SELDIPIF_OFFSET);

sys/dev/ic/dw_hdmi_phy.c

243

dwhdmi_write(sc, HDMI_PHY_CONF0, reg);

sys/dev/ic/dw_hdmi_phy.c

249

uint8_t reg;

sys/dev/ic/dw_hdmi_phy.c

251

reg = dwhdmi_read(sc, HDMI_PHY_CONF0);

sys/dev/ic/dw_hdmi_phy.c

252

reg &= ~HDMI_PHY_CONF0_SVSRET_MASK;

sys/dev/ic/dw_hdmi_phy.c

253

reg |= (enable << HDMI_PHY_CONF0_SVSRET_OFFSET);

sys/dev/ic/dw_hdmi_phy.c

254

dwhdmi_write(sc, HDMI_PHY_CONF0, reg);

sys/dev/ic/dwc_eqos.c

116

#define RD4(sc, reg) \

sys/dev/ic/dwc_eqos.c

117

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/dev/ic/dwc_eqos.c

118

#define WR4(sc, reg, val) \

sys/dev/ic/dwc_eqos.c

119

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/dev/ic/dwc_eqos.c

142

eqos_mii_readreg(device_t dev, int phy, int reg, uint16_t *val)

sys/dev/ic/dwc_eqos.c

150

(reg << GMAC_MAC_MDIO_ADDRESS_RDA_SHIFT) |

sys/dev/ic/dwc_eqos.c

164

phy, reg);

sys/dev/ic/dwc_eqos.c

172

eqos_mii_writereg(device_t dev, int phy, int reg, uint16_t val)

sys/dev/ic/dwc_eqos.c

182

(reg << GMAC_MAC_MDIO_ADDRESS_RDA_SHIFT) |

sys/dev/ic/dwc_eqos.c

195

phy, reg);

sys/dev/ic/dwc_eqos.c

2064

uint32_t reg, index;

sys/dev/ic/dwc_eqos.c

2066

reg = RD4(sc, GMAC_DMA_CHAN0_CUR_TX_DESC);

sys/dev/ic/dwc_eqos.c

2069

printf("cdesc = %08x\n", reg);

sys/dev/ic/dwc_eqos.c

2071

(reg - (uint32_t)sc->sc_tx.desc_ring_paddr) /

sys/dev/ic/dwc_eqos.c

2074

if (reg == 0)

sys/dev/ic/dwc_eqos.c

2077

index = (reg - (uint32_t)sc->sc_tx.desc_ring_paddr) /

sys/dev/ic/dwc_eqos.c

2090

uint32_t reg, index;

sys/dev/ic/dwc_eqos.c

2092

reg = RD4(sc, GMAC_DMA_CHAN0_TX_END_ADDR);

sys/dev/ic/dwc_eqos.c

2093

if (reg == 0)

sys/dev/ic/dwc_eqos.c

2096

index = (reg - (uint32_t)sc->sc_tx.desc_ring_paddr) /

sys/dev/ic/dwc_eqos.c

2109

uint32_t reg, index;

sys/dev/ic/dwc_eqos.c

2111

reg = RD4(sc, GMAC_DMA_CHAN0_CUR_RX_DESC);

sys/dev/ic/dwc_eqos.c

2112

if (reg == 0)

sys/dev/ic/dwc_eqos.c

2115

index = (reg - (uint32_t)sc->sc_rx.desc_ring_paddr) /

sys/dev/ic/dwc_eqos.c

2128

uint32_t reg, index;

sys/dev/ic/dwc_eqos.c

2130

reg = RD4(sc, GMAC_DMA_CHAN0_RX_END_ADDR);

sys/dev/ic/dwc_eqos.c

2131

if (reg == 0)

sys/dev/ic/dwc_eqos.c

2134

index = (reg - (uint32_t)sc->sc_rx.desc_ring_paddr) /

sys/dev/ic/dwc_gmac.c

413

dwc_gmac_miibus_read_reg(device_t self, int phy, int reg, uint16_t *val)

sys/dev/ic/dwc_gmac.c

420

| __SHIFTIN(reg, GMAC_MII_REG_MASK)

sys/dev/ic/dwc_gmac.c

446

dwc_gmac_miibus_write_reg(device_t self, int phy, int reg, uint16_t val)

sys/dev/ic/dwc_gmac.c

453

| __SHIFTIN(reg, GMAC_MII_REG_MASK)

sys/dev/ic/dwc_mmc.c

598

u_int reg;

sys/dev/ic/dwc_mmc.c

630

reg = (cmd->c_arg >> SD_ARG_CMD52_REG_SHIFT) &

sys/dev/ic/dwc_mmc.c

632

if (reg != 0x6) /* func abort / card reset */

sys/dev/ic/dwc_mmc.c

80

#define MMC_WRITE(sc, reg, val) \

sys/dev/ic/dwc_mmc.c

81

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/dev/ic/dwc_mmc.c

82

#define MMC_READ(sc, reg) \

sys/dev/ic/dwc_mmc.c

83

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/dev/ic/dwc_wdt.c

84

#define RD4(sc, reg) \

sys/dev/ic/dwc_wdt.c

85

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/dev/ic/dwc_wdt.c

86

#define WR4(sc, reg, val) \

sys/dev/ic/dwc_wdt.c

87

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/dev/ic/dwiic.c

273

uint32_t reg;

sys/dev/ic/dwiic.c

276

reg = dwiic_read(sc, DW_IC_COMP_TYPE);

sys/dev/ic/dwiic.c

277

if (reg != DW_IC_COMP_TYPE_VALUE) {

sys/dev/ic/dwiic.c

279

device_xname(sc->sc_dev), reg));

sys/dev/ic/dwiic.c

295

reg = dwiic_read(sc, DW_IC_COMP_VERSION);

sys/dev/ic/dwiic.c

296

if (reg >= DW_IC_SDA_HOLD_MIN_VERS)

sys/dev/ic/elink3.c

2037

ep_mii_readreg(device_t self, int phy, int reg, uint16_t *val)

sys/dev/ic/elink3.c

2044

rv = mii_bitbang_readreg(self, &ep_mii_bitbang_ops, phy, reg, val);

sys/dev/ic/elink3.c

2052

ep_mii_writereg(device_t self, int phy, int reg, uint16_t val)

sys/dev/ic/elink3.c

2059

rv = mii_bitbang_writereg(self, &ep_mii_bitbang_ops, phy, reg, val);

sys/dev/ic/elink3.c

237

ep_w1_reg(struct ep_softc *sc, int reg)

sys/dev/ic/elink3.c

242

return (reg + 0x10);

sys/dev/ic/elink3.c

245

switch (reg) {

sys/dev/ic/elink3.c

249

return (reg);

sys/dev/ic/elink3.c

251

return (reg + 0x10);

sys/dev/ic/elink3.c

254

return (reg);

sys/dev/ic/elinkxl.c

1893

ex_mii_readreg(device_t v, int phy, int reg, uint16_t *val)

sys/dev/ic/elinkxl.c

1903

rv = mii_bitbang_readreg(v, &ex_mii_bitbang_ops, phy, reg, val);

sys/dev/ic/elinkxl.c

1911

ex_mii_writereg(device_t v, int phy, int reg, uint16_t val)

sys/dev/ic/elinkxl.c

1918

rv = mii_bitbang_writereg(v, &ex_mii_bitbang_ops, phy, reg, val);

sys/dev/ic/gcscpcib.c

361

int reg;

sys/dev/ic/gcscpcib.c

363

reg = AMD553X_GPIO_OUT_VAL;

sys/dev/ic/gcscpcib.c

366

reg += AMD553X_GPIOH_OFFSET;

sys/dev/ic/gcscpcib.c

368

data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg);

sys/dev/ic/gcscpcib.c

378

int reg;

sys/dev/ic/gcscpcib.c

380

reg = AMD553X_GPIO_OUT_VAL;

sys/dev/ic/gcscpcib.c

383

reg += AMD553X_GPIOH_OFFSET;

sys/dev/ic/gcscpcib.c

390

bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg, data);

sys/dev/ic/gcscpcib.c

397

int n, reg[7], val[7], nreg = 0, off = 0;

sys/dev/ic/gcscpcib.c

404

reg[nreg] = AMD553X_GPIO_IN_EN + off;

sys/dev/ic/gcscpcib.c

410

reg[nreg] = AMD553X_GPIO_OUT_EN + off;

sys/dev/ic/gcscpcib.c

416

reg[nreg] = AMD553X_GPIO_OD_EN + off;

sys/dev/ic/gcscpcib.c

422

reg[nreg] = AMD553X_GPIO_PU_EN + off;

sys/dev/ic/gcscpcib.c

428

reg[nreg] = AMD553X_GPIO_PD_EN + off;

sys/dev/ic/gcscpcib.c

434

reg[nreg] = AMD553X_GPIO_IN_INVRT_EN + off;

sys/dev/ic/gcscpcib.c

440

reg[nreg] = AMD553X_GPIO_OUT_INVRT_EN + off;

sys/dev/ic/gcscpcib.c

448

bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg[n],

sys/dev/ic/gem.c

2366

gem_mii_readreg(device_t self, int phy, int reg, uint16_t *val)

sys/dev/ic/gem.c

2376

printf("gem_mii_readreg: PHY %d reg %d\n", phy, reg);

sys/dev/ic/gem.c

2380

v = (reg << GEM_MIF_REG_SHIFT) | (phy << GEM_MIF_PHY_SHIFT) |

sys/dev/ic/gem.c

2398

gem_mii_writereg(device_t self, int phy, int reg, uint16_t val)

sys/dev/ic/gem.c

2409

phy, reg, val);

sys/dev/ic/gem.c

2415

(reg << GEM_MIF_REG_SHIFT) |

sys/dev/ic/gem.c

658

uint32_t reg;

sys/dev/ic/gem.c

661

reg = bus_space_read_4(sc->sc_bustag, h, r);

sys/dev/ic/gem.c

662

if ((reg & clr) == 0 && (reg & set) == set)

sys/dev/ic/hd44780_subr.c

697

hd44780_writereg(struct hd44780_chip *sc, uint32_t en, uint32_t reg,

sys/dev/ic/hd44780_subr.c

706

if (reg == 0)

sys/dev/ic/hd44780_subr.c

719

hd44780_readreg(struct hd44780_chip *sc, uint32_t en, uint32_t reg)

sys/dev/ic/hd44780_subr.c

727

if (reg == 0)

sys/dev/ic/hd44780_subr.c

740

hd44780_writereg(struct hd44780_chip *sc, uint32_t en, uint32_t reg,

sys/dev/ic/hd44780_subr.c

749

if (reg == 0)

sys/dev/ic/hd44780_subr.c

764

hd44780_readreg(struct hd44780_chip *sc, uint32_t en, uint32_t reg)

sys/dev/ic/hd44780_subr.c

773

if (reg == 0)

sys/dev/ic/hd64570.c

174

#define sca_read_1(sc, reg) (sc)->sc_read_1(sc, reg)

sys/dev/ic/hd64570.c

175

#define sca_read_2(sc, reg) (sc)->sc_read_2(sc, reg)

sys/dev/ic/hd64570.c

176

#define sca_write_1(sc, reg, val) (sc)->sc_write_1(sc, reg, val)

sys/dev/ic/hd64570.c

177

#define sca_write_2(sc, reg, val) (sc)->sc_write_2(sc, reg, val)

sys/dev/ic/hd64570.c

182

msci_write_1(sca_port_t *scp, u_int reg, u_int8_t val)

sys/dev/ic/hd64570.c

184

sca_write_1(scp->sca, scp->msci_off + reg, val);

sys/dev/ic/hd64570.c

188

msci_read_1(sca_port_t *scp, u_int reg)

sys/dev/ic/hd64570.c

190

return sca_read_1(scp->sca, scp->msci_off + reg);

sys/dev/ic/hd64570.c

194

dmac_write_1(sca_port_t *scp, u_int reg, u_int8_t val)

sys/dev/ic/hd64570.c

196

sca_write_1(scp->sca, scp->dmac_off + reg, val);

sys/dev/ic/hd64570.c

200

dmac_write_2(sca_port_t *scp, u_int reg, u_int16_t val)

sys/dev/ic/hd64570.c

202

sca_write_2(scp->sca, scp->dmac_off + reg, val);

sys/dev/ic/hd64570.c

206

dmac_read_1(sca_port_t *scp, u_int reg)

sys/dev/ic/hd64570.c

208

return sca_read_1(scp->sca, scp->dmac_off + reg);

sys/dev/ic/hd64570.c

212

dmac_read_2(sca_port_t *scp, u_int reg)

sys/dev/ic/hd64570.c

214

return sca_read_2(scp->sca, scp->dmac_off + reg);

sys/dev/ic/hme.c

1210

hme_mii_readreg(device_t self, int phy, int reg, uint16_t *val)

sys/dev/ic/hme.c

1259

(reg << HME_MIF_FO_REGAD_SHIFT);

sys/dev/ic/hme.c

1284

hme_mii_writereg(device_t self, int phy, int reg, uint16_t val)

sys/dev/ic/hme.c

1333

(reg << HME_MIF_FO_REGAD_SHIFT) |

sys/dev/ic/i82365.c

1038

int reg;

sys/dev/ic/i82365.c

1043

reg = pcic_read(h, PCIC_ADDRWIN_ENABLE);

sys/dev/ic/i82365.c

1044

reg &= ~mem_map_index[window].memenable;

sys/dev/ic/i82365.c

1045

pcic_write(h, PCIC_ADDRWIN_ENABLE, reg);

sys/dev/ic/i82365.c

1152

int reg;

sys/dev/ic/i82365.c

1167

reg = pcic_read(h, PCIC_IOCTL);

sys/dev/ic/i82365.c

1168

reg &= ~io_map_index[win].ioctlmask;

sys/dev/ic/i82365.c

1169

reg |= io_map_index[win].ioctlbits[h->io[win].width];

sys/dev/ic/i82365.c

1170

pcic_write(h, PCIC_IOCTL, reg);

sys/dev/ic/i82365.c

1172

reg = pcic_read(h, PCIC_ADDRWIN_ENABLE);

sys/dev/ic/i82365.c

1173

reg |= io_map_index[win].ioenable;

sys/dev/ic/i82365.c

1174

pcic_write(h, PCIC_ADDRWIN_ENABLE, reg);

sys/dev/ic/i82365.c

1233

int reg;

sys/dev/ic/i82365.c

1238

reg = pcic_read(h, PCIC_ADDRWIN_ENABLE);

sys/dev/ic/i82365.c

1239

reg &= ~io_map_index[window].ioenable;

sys/dev/ic/i82365.c

1240

pcic_write(h, PCIC_ADDRWIN_ENABLE, reg);

sys/dev/ic/i82365.c

1303

int reg;

sys/dev/ic/i82365.c

1380

reg = pcic_read(h, PCIC_IF_STATUS);

sys/dev/ic/i82365.c

1381

if ((reg & PCIC_IF_STATUS_POWERACTIVE) == 0)

sys/dev/ic/i82365.c

1382

printf("pcic_chip_socket_enable: no power, status=%x\n", reg);

sys/dev/ic/i82365.c

140

int reg;

sys/dev/ic/i82365.c

143

reg = pcic_read(h, PCIC_IDENT);

sys/dev/ic/i82365.c

145

if ((reg & PCIC_IDENT_REV_MASK) == 0)

sys/dev/ic/i82365.c

148

switch (reg) {

sys/dev/ic/i82365.c

181

reg = pcic_read(h, -1);

sys/dev/ic/i82365.c

182

if ((reg & PCIC_CIRRUS_CHIP_INFO_CHIP_ID) ==

sys/dev/ic/i82365.c

184

reg = pcic_read(h, -1);

sys/dev/ic/i82365.c

185

if ((reg & PCIC_CIRRUS_CHIP_INFO_CHIP_ID) == 0)

sys/dev/ic/i82365.c

192

reg = pcic_read(h, PCIC_RICOH_REG_CHIP_ID);

sys/dev/ic/i82365.c

193

switch (reg) {

sys/dev/ic/i82365.c

233

int i, reg, chip, socket;

sys/dev/ic/i82365.c

272

reg = pcic_read(h, PCIC_CIRRUS_CHIP_INFO);

sys/dev/ic/i82365.c

274

(reg & PCIC_CIRRUS_CHIP_INFO_SLOTS))

sys/dev/ic/i82365.c

284

reg = pcic_read(h, PCIC_IDENT);

sys/dev/ic/i82365.c

285

DPRINTF(("socket %d ident reg 0x%02x\n", i, reg));

sys/dev/ic/i82365.c

286

reg = pcic_read(h, PCIC_IDENT);

sys/dev/ic/i82365.c

287

DPRINTF(("socket %d ident reg 0x%02x\n", i, reg));

sys/dev/ic/i82365.c

288

if (pcic_ident_ok(reg))

sys/dev/ic/i82365.c

355

int reg;

sys/dev/ic/i82365.c

365

reg = PCIC_CSC_INTR_CD_ENABLE;

sys/dev/ic/i82365.c

367

reg |= sc->irq << PCIC_CSC_INTR_IRQ_SHIFT;

sys/dev/ic/i82365.c

368

pcic_write(h, PCIC_CSC_INTR, reg);

sys/dev/ic/i82365.c

446

int reg;

sys/dev/ic/i82365.c

461

reg = PCIC_CSC_INTR_CD_ENABLE;

sys/dev/ic/i82365.c

469

reg |= sc->irq << PCIC_CSC_INTR_IRQ_SHIFT;

sys/dev/ic/i82365.c

470

pcic_write(h, PCIC_CSC_INTR, reg);

sys/dev/ic/i82365.c

484

reg = pcic_read(h, PCIC_CIRRUS_MISC_CTL_2);

sys/dev/ic/i82365.c

485

if (reg & PCIC_CIRRUS_MISC_CTL_2_SUSPEND) {

sys/dev/ic/i82365.c

488

reg &= ~PCIC_CIRRUS_MISC_CTL_2_SUSPEND;

sys/dev/ic/i82365.c

489

pcic_write(h, PCIC_CIRRUS_MISC_CTL_2, reg);

sys/dev/ic/i82365.c

494

reg = pcic_read(h, PCIC_IF_STATUS);

sys/dev/ic/i82365.c

495

if ((reg & PCIC_IF_STATUS_CARDDETECT_MASK) ==

sys/dev/ic/i82365.c

911

int reg;

sys/dev/ic/i82365.c

944

reg = pcic_read(h, PCIC_ADDRWIN_ENABLE);

sys/dev/ic/i82365.c

945

reg |= (mem_map_index[win].memenable | PCIC_ADDRWIN_ENABLE_MEMCS16);

sys/dev/ic/i82365.c

946

pcic_write(h, PCIC_ADDRWIN_ENABLE, reg);

sys/dev/ic/i82557.c

2114

fxp_mdi_read(device_t self, int phy, int reg, uint16_t *value)

sys/dev/ic/i82557.c

2121

(FXP_MDI_READ << 26) | (reg << 16) | (phy << 21));

sys/dev/ic/i82557.c

2145

fxp_mdi_write(device_t self, int phy, int reg, uint16_t value)

sys/dev/ic/i82557.c

2151

(FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | value);

sys/dev/ic/i82557.c

604

uint16_t reg;

sys/dev/ic/i82557.c

610

reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;

sys/dev/ic/i82557.c

612

reg = FXP_EEPROM_EECS;

sys/dev/ic/i82557.c

613

CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);

sys/dev/ic/i82557.c

616

reg | FXP_EEPROM_EESK);

sys/dev/ic/i82557.c

618

CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);

sys/dev/ic/i82557.c

699

uint16_t reg;

sys/dev/ic/i82557.c

711

reg = FXP_EEPROM_EECS;

sys/dev/ic/i82557.c

717

reg | FXP_EEPROM_EESK);

sys/dev/ic/i82557.c

722

CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);

sys/dev/ic/i82557var.h

352

#define CSR_READ_1(sc, reg) \

sys/dev/ic/i82557var.h

353

bus_space_read_1((sc)->sc_st, (sc)->sc_sh, (reg))

sys/dev/ic/i82557var.h

354

#define CSR_READ_2(sc, reg) \

sys/dev/ic/i82557var.h

355

bus_space_read_2((sc)->sc_st, (sc)->sc_sh, (reg))

sys/dev/ic/i82557var.h

356

#define CSR_READ_4(sc, reg) \

sys/dev/ic/i82557var.h

357

bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))

sys/dev/ic/i82557var.h

358

#define CSR_WRITE_1(sc, reg, val) \

sys/dev/ic/i82557var.h

359

bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))

sys/dev/ic/i82557var.h

360

#define CSR_WRITE_2(sc, reg, val) \

sys/dev/ic/i82557var.h

361

bus_space_write_2((sc)->sc_st, (sc)->sc_sh, (reg), (val))

sys/dev/ic/i82557var.h

362

#define CSR_WRITE_4(sc, reg, val) \

sys/dev/ic/i82557var.h

363

bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))

sys/dev/ic/ibm561.c

478

ibm561_regcont10bit(struct ibm561data *data, u_int16_t reg, u_int16_t val)

sys/dev/ic/ibm561.c

485

ibm561_regbegin(struct ibm561data *data, u_int16_t reg)

sys/dev/ic/ibm561.c

487

data->ramdac_wr(data->cookie, IBM561_ADDR_LOW, reg & 0xff);

sys/dev/ic/ibm561.c

488

data->ramdac_wr(data->cookie, IBM561_ADDR_HIGH, (reg >> 8) & 0xff);

sys/dev/ic/ibm561.c

492

ibm561_regcont(struct ibm561data *data, u_int16_t reg, u_int8_t val)

sys/dev/ic/ibm561.c

494

data->ramdac_wr(data->cookie, reg, val);

sys/dev/ic/ibm561.c

498

ibm561_regwr(struct ibm561data *data, u_int16_t reg, u_int8_t val)

sys/dev/ic/ibm561.c

500

ibm561_regbegin(data, reg);

sys/dev/ic/igpio.c

238

bus_size_t reg;

sys/dev/ic/igpio.c

255

reg = IGPIO_REVID;

sys/dev/ic/igpio.c

256

val = bus_space_read_4(sc->sc_bst, sc->sc_bsh[i], reg);

sys/dev/ic/igpio.c

270

reg = IGPIO_CAPLIST;

sys/dev/ic/igpio.c

273

val = bus_space_read_4(sc->sc_bst, sc->sc_bsh[i], reg);

sys/dev/ic/igpio.c

275

reg = val & 0xffff;

sys/dev/ic/igpio.c

295

} while (reg);

sys/dev/ic/igpio.c

298

reg = IGPIO_PADBAR;

sys/dev/ic/igpio.c

299

val = bus_space_read_4(sc->sc_bst, sc->sc_bsh[i], reg);

sys/dev/ic/igpio.c

403

igpio_pincfg(struct igpio_bank *ib, int pin, int reg)

sys/dev/ic/igpio.c

408

pincfg = ib->ib_padbar + reg + (pin * nregs * 4);

sys/dev/ic/igpio.c

411

__func__, ib->ib_barno, pin, reg, (void *)pincfg));

sys/dev/ic/igsfb.c

1193

uint8_t reg;

sys/dev/ic/igsfb.c

1198

reg = bus_space_read_1(t, h, IGS_COP_CTL_REG);

sys/dev/ic/igsfb.c

1199

if ((reg & IGS_COP_CTL_BUSY) == 0)

sys/dev/ic/igsfb_subr.c

348

uint8_t reg;

sys/dev/ic/igsfb_subr.c

351

reg = igs_ext_read(iot, ioh, IGS_EXT_SPRITE_CTL);

sys/dev/ic/igsfb_subr.c

353

reg | IGS_EXT_SPRITE_DAC_PEL);

sys/dev/ic/igsfb_subr.c

359

igs_ext_write(iot, ioh, IGS_EXT_SPRITE_CTL, reg);

sys/dev/ic/igsfb_subr.c

489

uint8_t vclk1, vclk2, vclk3, overflow, reg, seq_mode;

sys/dev/ic/igsfb_subr.c

524

reg = igs_ext_read(iot, ioh, IGS_EXT_SPRITE_CTL);

sys/dev/ic/igsfb_subr.c

526

reg | IGS_EXT_SPRITE_DAC_PEL);

sys/dev/ic/igsfb_subr.c

536

igs_ext_write(iot, ioh, IGS_EXT_SPRITE_CTL, reg);

sys/dev/ic/iha.c

503

int i, error, reg;

sys/dev/ic/iha.c

572

reg = 0;

sys/dev/ic/iha.c

574

reg |= ENTMW;

sys/dev/ic/iha.c

576

reg |= ENTM;

sys/dev/ic/iha.c

577

bus_space_write_1(iot, ioh, TUL_DCTRL0, reg);

sys/dev/ic/iha.c

579

reg = bus_space_read_1(iot, ioh, TUL_GCTRL1) & ~ATDEN;

sys/dev/ic/iha.c

581

reg |= ATDEN;

sys/dev/ic/iha.c

582

bus_space_write_1(iot, ioh, TUL_GCTRL1, reg);

sys/dev/ic/interwave.c

1002

IW_READ_CODEC_1(CLDACI, reg);

sys/dev/ic/interwave.c

1003

IW_WRITE_CODEC_1(CLDACI, reg & 0x7f);

sys/dev/ic/interwave.c

1004

IW_READ_CODEC_1(CRDACI, reg);

sys/dev/ic/interwave.c

1005

IW_WRITE_CODEC_1(CRDACI, reg & 0x7f);

sys/dev/ic/interwave.c

1009

IW_READ_CODEC_1(CLDACI, reg);

sys/dev/ic/interwave.c

1010

IW_WRITE_CODEC_1(CLDACI, reg | 0x80);

sys/dev/ic/interwave.c

1011

IW_READ_CODEC_1(CRDACI, reg);

sys/dev/ic/interwave.c

1012

IW_WRITE_CODEC_1(CRDACI, reg | 0x80);

sys/dev/ic/interwave.c

375

u_char reg, cmode, val, mixer_image;

sys/dev/ic/interwave.c

379

reg = 0; /* XXX gcc -Wall */

sys/dev/ic/interwave.c

392

IW_READ_GENERAL_1(IVERI, reg);

sys/dev/ic/interwave.c

393

IW_WRITE_GENERAL_1(IVERI, reg | 0x01); /* hidden reg lock disable */

sys/dev/ic/interwave.c

429

IW_READ_CODEC_1(CMODEI, reg);

sys/dev/ic/interwave.c

431

DPRINTF(("cmode %x\n", reg));

sys/dev/ic/interwave.c

433

sc->revision = ((reg & 0x80) >> 3) | (reg & 0x0f);

sys/dev/ic/interwave.c

457

IW_READ_GENERAL_1(IVERI, reg);

sys/dev/ic/interwave.c

459

sc->vers = reg >> 4;

sys/dev/ic/interwave.c

520

u_char var, cfig3, reg;

sys/dev/ic/interwave.c

591

IW_READ_CODEC_1(CPDFI, reg);

sys/dev/ic/interwave.c

593

DPRINTF((" CPDFI %x ", reg));

sys/dev/ic/interwave.c

595

IW_READ_CODEC_1(CRDFI, reg);

sys/dev/ic/interwave.c

597

DPRINTF((" CRDFI %x ", reg));

sys/dev/ic/interwave.c

598

__USE(reg);

sys/dev/ic/interwave.c

806

u_char reg;

sys/dev/ic/interwave.c

808

IW_READ_CODEC_1(CSR3I, reg);

sys/dev/ic/interwave.c

809

IW_WRITE_CODEC_1(CSR3I, reg & ~(io == IW_DMA_PLAYBACK ? 0x10 : 0x20));

sys/dev/ic/interwave.c

811

IW_READ_CODEC_1(CFIG1I, reg);

sys/dev/ic/interwave.c

813

IW_WRITE_CODEC_1(CFIG1I, reg | io);

sys/dev/ic/interwave.c

816

IW_READ_CODEC_1(CFIG2I, reg);

sys/dev/ic/interwave.c

817

IW_WRITE_CODEC_1(CFIG2I, reg & ~(io << 4));

sys/dev/ic/interwave.c

823

u_char reg;

sys/dev/ic/interwave.c

826

IW_READ_CODEC_1(CFIG2I, reg);

sys/dev/ic/interwave.c

827

IW_WRITE_CODEC_1(CFIG2I, (reg | (io << 4)));

sys/dev/ic/interwave.c

831

IW_READ_CODEC_1(CFIG1I, reg);

sys/dev/ic/interwave.c

832

IW_WRITE_CODEC_1(CFIG1I, reg & ~io);

sys/dev/ic/interwave.c

997

u_char reg;

sys/dev/ic/interwavereg.h

358

#define IW_WRITE_CODEC_1(reg, val) \

sys/dev/ic/interwavereg.h

360

bus_space_write_1(sc->sc_iot, sc->codec_index_h, 0, (u_char)(reg));\

sys/dev/ic/interwavereg.h

365

#define IW_READ_CODEC_1(reg, ret) \

sys/dev/ic/interwavereg.h

367

bus_space_write_1(sc->sc_iot, sc->codec_index_h, sc->codec_index, (u_char)(reg));\

sys/dev/ic/interwavereg.h

374

#define IW_WRITE_DIRECT_1(reg, h, val) \

sys/dev/ic/interwavereg.h

376

bus_space_write_1(sc->sc_iot, h, reg, (u_char)val);\

sys/dev/ic/interwavereg.h

379

#define IW_READ_DIRECT_1(reg, h, ret) \

sys/dev/ic/interwavereg.h

381

ret = bus_space_read_1(sc->sc_iot, h, (u_char)reg);\

sys/dev/ic/interwavereg.h

386

#define IW_WRITE_GENERAL_1(reg, val) \

sys/dev/ic/interwavereg.h

388

bus_space_write_1(sc->sc_iot, sc->p3xr_h, 3, (u_char)reg);\

sys/dev/ic/interwavereg.h

392

#define IW_WRITE_GENERAL_2(reg, val) \

sys/dev/ic/interwavereg.h

394

bus_space_write_1(sc->sc_iot, sc->p3xr_h, 3, (u_char)reg);\

sys/dev/ic/interwavereg.h

398

#define IW_READ_GENERAL_1(reg, ret) \

sys/dev/ic/interwavereg.h

400

bus_space_write_1(sc->sc_iot, sc->p3xr_h, 3, (u_char)reg);\

sys/dev/ic/interwavereg.h

404

#define IW_READ_GENERAL_2(reg, ret) \

sys/dev/ic/interwavereg.h

406

bus_space_write_1(sc->sc_iot, sc->p3xr_h, 3, (u_char)reg);\

sys/dev/ic/ispvar.h

120

#define ISP_READ(isp, reg) \

sys/dev/ic/ispvar.h

121

(*(isp)->isp_mdvec->dv_rd_reg)((isp), (reg))

sys/dev/ic/ispvar.h

123

#define ISP_WRITE(isp, reg, val) \

sys/dev/ic/ispvar.h

124

(*(isp)->isp_mdvec->dv_wr_reg)((isp), (reg), (val))

sys/dev/ic/ispvar.h

143

#define ISP_SETBITS(isp, reg, val) \

sys/dev/ic/ispvar.h

144

(*(isp)->isp_mdvec->dv_wr_reg)((isp), (reg), ISP_READ((isp), (reg)) | (val))

sys/dev/ic/ispvar.h

146

#define ISP_CLRBITS(isp, reg, val) \

sys/dev/ic/ispvar.h

147

(*(isp)->isp_mdvec->dv_wr_reg)((isp), (reg), ISP_READ((isp), (reg)) & ~(val))

sys/dev/ic/lan9118.c

534

uint32_t reg, hw_cfg, mac_cr, irq_cfg;

sys/dev/ic/lan9118.c

558

reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, LAN9118_HW_CFG);

sys/dev/ic/lan9118.c

559

if (reg & LAN9118_HW_CFG_SRST_TO) {

sys/dev/ic/lan9118.c

565

} while (reg & LAN9118_HW_CFG_SRST);

sys/dev/ic/lan9118.c

763

lan9118_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val)

sys/dev/ic/lan9118.c

766

return lan9118_mii_readreg(device_private(dev), phy, reg, val);

sys/dev/ic/lan9118.c

769

lan9118_miibus_writereg(device_t dev, int phy, int reg, uint16_t val)

sys/dev/ic/lan9118.c

772

return lan9118_mii_writereg(device_private(dev), phy, reg, val);

sys/dev/ic/lan9118.c

794

lan9118_mii_readreg(struct lan9118_softc *sc, int phy, int reg, uint16_t *val)

sys/dev/ic/lan9118.c

800

acc = LAN9118_MII_ACC_PHYA(phy) | LAN9118_MII_ACC_MIIRINDA(reg);

sys/dev/ic/lan9118.c

809

lan9118_mii_writereg(struct lan9118_softc *sc, int phy, int reg, uint16_t val)

sys/dev/ic/lan9118.c

815

acc = LAN9118_MII_ACC_PHYA(phy) | LAN9118_MII_ACC_MIIRINDA(reg) |

sys/dev/ic/lan9118.c

826

lan9118_mac_readreg(struct lan9118_softc *sc, int reg)

sys/dev/ic/lan9118.c

832

LAN9118_MAC_CSR_CMD_BUSY | LAN9118_MAC_CSR_CMD_R | reg);

sys/dev/ic/lan9118.c

846

lan9118_mac_writereg(struct lan9118_softc *sc, int reg, uint32_t val)

sys/dev/ic/lan9118.c

853

LAN9118_MAC_CSR_CMD_BUSY | LAN9118_MAC_CSR_CMD_W | reg);

sys/dev/ic/mcp23xxxgpio.c

132

uint8_t bank, uint8_t reg, uint8_t *valp)

sys/dev/ic/mcp23xxxgpio.c

135

uint8_t regaddr = mcpgpio_regaddr(sc, bank, reg);

sys/dev/ic/mcp23xxxgpio.c

141

mcpgpio_regname(reg), mcpgpio_bankname(sc, bank),

sys/dev/ic/mcp23xxxgpio.c

152

uint8_t bank, uint8_t reg, uint8_t val)

sys/dev/ic/mcp23xxxgpio.c

155

uint8_t regaddr = mcpgpio_regaddr(sc, bank, reg);

sys/dev/ic/mcp23xxxgpio.c

161

mcpgpio_regname(reg), mcpgpio_bankname(sc, bank),

sys/dev/ic/mcp23xxxgpio.c

65

mcpgpio_regaddr(struct mcpgpio_softc *sc, uint8_t bank, uint8_t reg)

sys/dev/ic/mcp23xxxgpio.c

69

return reg;

sys/dev/ic/mcp23xxxgpio.c

72

return REGADDR_BANK1(bank & 1, reg);

sys/dev/ic/mcp23xxxgpio.c

74

return REGADDR_BANK0(bank & 1, reg);

sys/dev/ic/mcp23xxxgpio.c

78

mcpgpio_regname(uint8_t reg)

sys/dev/ic/mcp23xxxgpio.c

93

KASSERT(reg <= REG_OLAT);

sys/dev/ic/mcp23xxxgpio.c

94

return regnames[reg];

sys/dev/ic/mcp23xxxgpioreg.h

104

#define REGADDR_BANK1(bank, reg) (((bank) << 4) | (reg))

sys/dev/ic/mcp23xxxgpioreg.h

107

#define REGADDR_BANK0(bank, reg) (((reg) << 1) | (bank))

sys/dev/ic/mpt_netbsd.h

248

#define mpt_read(mpt, reg) \

sys/dev/ic/mpt_netbsd.h

249

bus_space_read_4((mpt)->sc_st, (mpt)->sc_sh, (reg))

sys/dev/ic/mpt_netbsd.h

250

#define mpt_write(mpt, reg, val) \

sys/dev/ic/mpt_netbsd.h

251

bus_space_write_4((mpt)->sc_st, (mpt)->sc_sh, (reg), (val))

sys/dev/ic/msm6242b.c

179

msm6242b_read(struct msm6242b_softc *sc, uint8_t reg)

sys/dev/ic/msm6242b.c

182

r = bus_space_read_1(sc->sc_iot, sc->sc_ioh, reg) & MSM6242B_MASK;

sys/dev/ic/msm6242b.c

187

msm6242b_write(struct msm6242b_softc *sc, uint8_t reg, uint8_t val)

sys/dev/ic/msm6242b.c

189

bus_space_write_1(sc->sc_iot, sc->sc_ioh, reg, val);

sys/dev/ic/msm6242b.c

193

msm6242b_set(struct msm6242b_softc *sc, uint8_t reg, uint8_t bits)

sys/dev/ic/msm6242b.c

196

v = msm6242b_read(sc, reg) | bits;

sys/dev/ic/msm6242b.c

197

msm6242b_write(sc, reg, v);

sys/dev/ic/msm6242b.c

201

msm6242b_unset(struct msm6242b_softc *sc, uint8_t reg, uint8_t bits)

sys/dev/ic/msm6242b.c

204

v = msm6242b_read(sc, reg) & ~bits;

sys/dev/ic/msm6242b.c

205

msm6242b_write(sc, reg, v);

sys/dev/ic/mtd803.c

100

#define MTD_SETBIT(sc, reg, x) \

sys/dev/ic/mtd803.c

101

MTD_WRITE_4((sc), (reg), MTD_READ_4((sc), (reg)) | (x))

sys/dev/ic/mtd803.c

102

#define MTD_CLRBIT(sc, reg, x) \

sys/dev/ic/mtd803.c

103

MTD_WRITE_4((sc), (reg), MTD_READ_4((sc), (reg)) & ~(x))

sys/dev/ic/mtd803.c

407

mtd_mii_readreg(device_t self, int phy, int reg, uint16_t *val)

sys/dev/ic/mtd803.c

411

*val = MTD_READ_2(sc, MTD_PHYBASE + reg * 2);

sys/dev/ic/mtd803.c

418

mtd_mii_writereg(device_t self, int phy, int reg, uint16_t val)

sys/dev/ic/mtd803.c

422

MTD_WRITE_2(sc, MTD_PHYBASE + reg * 2, val);

sys/dev/ic/mtd803.c

85

#define MTD_READ_1(sc, reg) \

sys/dev/ic/mtd803.c

86

bus_space_read_1((sc)->bus_tag, (sc)->bus_handle, (reg))

sys/dev/ic/mtd803.c

87

#define MTD_WRITE_1(sc, reg, data) \

sys/dev/ic/mtd803.c

88

bus_space_write_1((sc)->bus_tag, (sc)->bus_handle, (reg), (data))

sys/dev/ic/mtd803.c

90

#define MTD_READ_2(sc, reg) \

sys/dev/ic/mtd803.c

91

bus_space_read_2((sc)->bus_tag, (sc)->bus_handle, (reg))

sys/dev/ic/mtd803.c

92

#define MTD_WRITE_2(sc, reg, data) \

sys/dev/ic/mtd803.c

93

bus_space_write_2((sc)->bus_tag, (sc)->bus_handle, (reg), (data))

sys/dev/ic/mtd803.c

95

#define MTD_READ_4(sc, reg) \

sys/dev/ic/mtd803.c

96

bus_space_read_4((sc)->bus_tag, (sc)->bus_handle, (reg))

sys/dev/ic/mtd803.c

97

#define MTD_WRITE_4(sc, reg, data) \

sys/dev/ic/mtd803.c

98

bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, (reg), (data))

sys/dev/ic/mvsata.c

2642

uint32_t reg;

sys/dev/ic/mvsata.c

2650

reg = MVSATA_EDMA_READ_4(mvport, EDMA_REQQOP);

sys/dev/ic/mvsata.c

2651

erqqop = (reg & EDMA_REQQP_ERQQP_MASK) >> EDMA_REQQP_ERQQP_SHIFT;

sys/dev/ic/mvsata.c

2652

reg = MVSATA_EDMA_READ_4(mvport, EDMA_REQQIP);

sys/dev/ic/mvsata.c

2653

erqqip = (reg & EDMA_REQQP_ERQQP_MASK) >> EDMA_REQQP_ERQQP_SHIFT;

sys/dev/ic/mvsata.c

2718

uint32_t reg;

sys/dev/ic/mvsata.c

2723

reg = MVSATA_EDMA_READ_4(mvport, EDMA_REQQOP);

sys/dev/ic/mvsata.c

2724

erqqop = (reg & EDMA_REQQP_ERQQP_MASK) >> EDMA_REQQP_ERQQP_SHIFT;

sys/dev/ic/mvsata.c

2745

reg = MVSATA_EDMA_READ_4(mvport, EDMA_RESQIP);

sys/dev/ic/mvsata.c

2746

erpqip = (reg & EDMA_RESQP_ERPQP_MASK) >> EDMA_RESQP_ERPQP_SHIFT;

sys/dev/ic/mvsata.c

2747

reg = MVSATA_EDMA_READ_4(mvport, EDMA_RESQOP);

sys/dev/ic/mvsata.c

2748

erpqop = (reg & EDMA_RESQP_ERPQP_MASK) >> EDMA_RESQP_ERPQP_SHIFT;

sys/dev/ic/mvsata.c

2831

reg &= ~EDMA_RESQP_ERPQP_MASK;

sys/dev/ic/mvsata.c

2832

reg |= (erpqop << EDMA_RESQP_ERPQP_SHIFT);

sys/dev/ic/mvsata.c

2833

MVSATA_EDMA_WRITE_4(mvport, EDMA_RESQOP, reg);

sys/dev/ic/mvsata.c

3442

uint32_t reg;

sys/dev/ic/mvsata.c

3444

reg = MVSATA_EDMA_READ_4(mvport, EDMA_CFG);

sys/dev/ic/mvsata.c

3445

reg |= EDMA_CFG_RESERVED;

sys/dev/ic/mvsata.c

3453

reg |= EDMA_CFG_EDEVERR;

sys/dev/ic/mvsata.c

3454

reg |= EDMA_CFG_ESATANATVCMDQUE;

sys/dev/ic/mvsata.c

3456

reg &= ~EDMA_CFG_ESATANATVCMDQUE;

sys/dev/ic/mvsata.c

3457

reg |= EDMA_CFG_EQUE;

sys/dev/ic/mvsata.c

3459

reg &= ~(EDMA_CFG_ESATANATVCMDQUE | EDMA_CFG_EQUE);

sys/dev/ic/mvsata.c

3462

reg |= EDMA_CFG_ERDBSZ;

sys/dev/ic/mvsata.c

3464

reg |= (EDMA_CFG_ERDBSZEXT | EDMA_CFG_EWRBUFFERLEN);

sys/dev/ic/mvsata.c

3468

reg |= (EDMA_CFG_EMASKRXPM | EDMA_CFG_EHOSTQUEUECACHEEN);

sys/dev/ic/mvsata.c

3469

reg &= ~(EDMA_CFG_EEDMAFBS | EDMA_CFG_EEDMAQUELEN);

sys/dev/ic/mvsata.c

3472

reg |= (

sys/dev/ic/mvsata.c

3480

MVSATA_EDMA_WRITE_4(mvport, EDMA_CFG, reg);

sys/dev/ic/mvsata.c

3482

reg = (

sys/dev/ic/mvsata.c

3488

reg |= (

sys/dev/ic/mvsata.c

3509

reg |= EDMA_IE_EDEVERR;

sys/dev/ic/mvsata.c

3510

MVSATA_EDMA_WRITE_4(mvport, EDMA_IEM, reg);

sys/dev/ic/mvsata.c

3511

reg = MVSATA_EDMA_READ_4(mvport, EDMA_HC);

sys/dev/ic/mvsata.c

3512

reg &= ~EDMA_IE_EDEVERR;

sys/dev/ic/mvsata.c

3514

reg |= EDMA_IE_EDEVERR;

sys/dev/ic/mvsata.c

3515

MVSATA_EDMA_WRITE_4(mvport, EDMA_HC, reg);

sys/dev/ic/mvsata.c

3522

reg = MVSATA_EDMA_READ_4(mvport, SATA_FISC);

sys/dev/ic/mvsata.c

3523

reg &= ~(SATA_FISC_FISWAIT4HOSTRDYEN_B0 |

sys/dev/ic/mvsata.c

3525

MVSATA_EDMA_WRITE_4(mvport, SATA_FISC, reg);

sys/dev/ic/mvsata.c

3620

uint32_t reg;

sys/dev/ic/mvsata.c

3622

reg = MVSATA_HC_READ_4(hc, SATAHC_I_PHYMODE(mvport->port));

sys/dev/ic/mvsata.c

3627

return reg & 0x000018e0;

sys/dev/ic/mvsata.c

3635

uint32_t reg;

sys/dev/ic/mvsata.c

3651

reg = MVSATA_HC_READ_4(mvhc, SATAHC_I_LTMODE(port));

sys/dev/ic/mvsata.c

3652

reg |= (1 << 19);

sys/dev/ic/mvsata.c

3653

MVSATA_HC_WRITE_4(mvhc, SATAHC_I_LTMODE(port), reg);

sys/dev/ic/mvsata.c

3659

reg = MVSATA_HC_READ_4(mvhc, SATAHC_I_PHYCONTROL(port));

sys/dev/ic/mvsata.c

3660

reg &= ~0x3;

sys/dev/ic/mvsata.c

3661

reg |= 0x1;

sys/dev/ic/mvsata.c

3662

MVSATA_HC_WRITE_4(mvhc, SATAHC_I_PHYCONTROL(port), reg);

sys/dev/ic/mvsata.c

3666

reg = MVSATA_HC_READ_4(mvhc, SATAHC_I_PHYMODE(port));

sys/dev/ic/mvsata.c

3667

reg &= ~0x000018e0; /* pre and amps mask */

sys/dev/ic/mvsata.c

3668

reg |= mvport->_fix_phy_param.pre_amps;

sys/dev/ic/mvsata.c

3669

MVSATA_HC_WRITE_4(mvhc, SATAHC_I_PHYMODE(port), reg);

sys/dev/ic/mvsata.c

3689

uint32_t reg;

sys/dev/ic/mvsata.c

3691

reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM2);

sys/dev/ic/mvsata.c

3696

return reg & 0x000007e0;

sys/dev/ic/mvsata.c

3703

uint32_t reg;

sys/dev/ic/mvsata.c

3714

reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM2);

sys/dev/ic/mvsata.c

3715

reg &= ~(1 << 16);

sys/dev/ic/mvsata.c

3716

reg |= (1 << 31);

sys/dev/ic/mvsata.c

3717

MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM2, reg);

sys/dev/ic/mvsata.c

3721

reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM2);

sys/dev/ic/mvsata.c

3722

reg &= ~((1 << 16) | (1 << 31));

sys/dev/ic/mvsata.c

3723

MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM2, reg);

sys/dev/ic/mvsata.c

3729

reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM3);

sys/dev/ic/mvsata.c

3730

reg &= ~0x7F900000;

sys/dev/ic/mvsata.c

3731

reg |= 0x2A800000;

sys/dev/ic/mvsata.c

3736

reg &= ~0x0000001c;

sys/dev/ic/mvsata.c

3737

MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM3, reg);

sys/dev/ic/mvsata.c

3753

reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM4);

sys/dev/ic/mvsata.c

3754

reg |= (1 << 0);

sys/dev/ic/mvsata.c

3755

reg &= ~(1 << 1);

sys/dev/ic/mvsata.c

3758

reg &= ~0x5de3fffc;

sys/dev/ic/mvsata.c

3759

reg |= (1 << 2);

sys/dev/ic/mvsata.c

3761

MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM4, reg);

sys/dev/ic/mvsata.c

3769

reg = MVSATA_EDMA_READ_4(mvport, SATA_PHYM2);

sys/dev/ic/mvsata.c

3770

reg &= ~0x000007e0; /* pre and amps mask */

sys/dev/ic/mvsata.c

3771

reg |= mvport->_fix_phy_param.pre_amps;

sys/dev/ic/mvsata.c

3772

reg &= ~(1 << 16);

sys/dev/ic/mvsata.c

3778

reg &= ~0xC30FF01F;

sys/dev/ic/mvsata.c

3779

reg |= 0x0000900F;

sys/dev/ic/mvsata.c

3781

MVSATA_EDMA_WRITE_4(mvport, SATA_PHYM2, reg);

sys/dev/ic/mvsata.c

78

#define MVSATA_HC_READ_4(hc, reg) \

sys/dev/ic/mvsata.c

79

bus_space_read_4((hc)->hc_iot, (hc)->hc_ioh, (reg))

sys/dev/ic/mvsata.c

80

#define MVSATA_HC_WRITE_4(hc, reg, val) \

sys/dev/ic/mvsata.c

81

bus_space_write_4((hc)->hc_iot, (hc)->hc_ioh, (reg), (val))

sys/dev/ic/mvsata.c

82

#define MVSATA_EDMA_READ_4(mvport, reg) \

sys/dev/ic/mvsata.c

83

bus_space_read_4((mvport)->port_iot, (mvport)->port_ioh, (reg))

sys/dev/ic/mvsata.c

84

#define MVSATA_EDMA_WRITE_4(mvport, reg, val) \

sys/dev/ic/mvsata.c

85

bus_space_write_4((mvport)->port_iot, (mvport)->port_ioh, (reg), (val))

sys/dev/ic/mvsata.c

86

#define MVSATA_WDC_READ_2(mvport, reg) \

sys/dev/ic/mvsata.c

88

SHADOW_REG_BLOCK_OFFSET + (reg))

sys/dev/ic/mvsata.c

89

#define MVSATA_WDC_READ_1(mvport, reg) \

sys/dev/ic/mvsata.c

91

SHADOW_REG_BLOCK_OFFSET + (reg))

sys/dev/ic/mvsata.c

92

#define MVSATA_WDC_WRITE_2(mvport, reg, val) \

sys/dev/ic/mvsata.c

94

SHADOW_REG_BLOCK_OFFSET + (reg), (val))

sys/dev/ic/mvsata.c

95

#define MVSATA_WDC_WRITE_1(mvport, reg, val) \

sys/dev/ic/mvsata.c

97

SHADOW_REG_BLOCK_OFFSET + (reg), (val))

sys/dev/ic/mvsatareg.h

284

#define CRQB_ATACOMMAND(reg, val) \

sys/dev/ic/mvsatareg.h

285

((reg << 8) | (val & 0xff))

sys/dev/ic/mvsatareg.h

287

#define CRQB_ATACOMMAND_REG(reg) (((reg) >> 2) + 0x10)

sys/dev/ic/ncr5380var.h

66

# define NCR5380_READ(sc, reg) bus_space_read_1(sc->sc_regt, \

sys/dev/ic/ncr5380var.h

67

sc->sc_regh, sc->reg)

sys/dev/ic/ncr5380var.h

68

# define NCR5380_WRITE(sc, reg, val) bus_space_write_1(sc->sc_regt, \

sys/dev/ic/ncr5380var.h

69

sc->sc_regh, sc->reg, val)

sys/dev/ic/ncr5380var.h

72

# define NCR5380_READ(sc, reg) (*sc->reg)

sys/dev/ic/ncr5380var.h

73

# define NCR5380_WRITE(sc, reg, val) do { *(sc->reg) = val; } while (0)

sys/dev/ic/ncr53c9xvar.h

403

#define NCR_READ_REG(sc, reg) \

sys/dev/ic/ncr53c9xvar.h

404

(*(sc)->sc_glue->gl_read_reg)((sc), (reg))

sys/dev/ic/ncr53c9xvar.h

405

#define NCR_WRITE_REG(sc, reg, val) \

sys/dev/ic/ncr53c9xvar.h

406

(*(sc)->sc_glue->gl_write_reg)((sc), (reg), (val))

sys/dev/ic/ninjascsi32.c

1536

u_int8_t reg;

sys/dev/ic/ninjascsi32.c

1538

reg = njsc32_read_1(sc, NJSC32_REG_SCSI_BUS_CONTROL);

sys/dev/ic/ninjascsi32.c

1539

reg |= NJSC32_SBCTL_ACK | NJSC32_SBCTL_ACK_ENABLE;

sys/dev/ic/ninjascsi32.c

1541

reg |= NJSC32_SBCTL_AUTODIRECTION;

sys/dev/ic/ninjascsi32.c

1543

njsc32_write_1(sc, NJSC32_REG_SCSI_BUS_CONTROL, reg);

sys/dev/ic/ninjascsi32.c

1549

u_int8_t reg;

sys/dev/ic/ninjascsi32.c

1551

reg = njsc32_read_1(sc, NJSC32_REG_SCSI_BUS_CONTROL);

sys/dev/ic/ninjascsi32.c

1553

reg |= NJSC32_SBCTL_ACK_ENABLE;

sys/dev/ic/ninjascsi32.c

1554

reg |= NJSC32_SBCTL_AUTODIRECTION;

sys/dev/ic/ninjascsi32.c

1556

reg &= ~NJSC32_SBCTL_ACK;

sys/dev/ic/ninjascsi32.c

1557

njsc32_write_1(sc, NJSC32_REG_SCSI_BUS_CONTROL, reg);

sys/dev/ic/ninjascsi32.c

550

int reg;

sys/dev/ic/ninjascsi32.c

565

if ((reg = njsc32_read_2(sc, NJSC32_REG_TRANSFER)) == 0xffff) {

sys/dev/ic/ninjascsi32.c

569

} else if (reg & NJSC32_XFR_DUALEDGE_ENABLE) {

sys/dev/ic/nslm7x.c

1007

.reg = 0x24,

sys/dev/ic/nslm7x.c

1015

.reg = 0x25,

sys/dev/ic/nslm7x.c

1023

.reg = 0x26,

sys/dev/ic/nslm7x.c

1031

.reg = 0x50,

sys/dev/ic/nslm7x.c

1039

.reg = 0x51,

sys/dev/ic/nslm7x.c

1049

.reg = 0x27,

sys/dev/ic/nslm7x.c

1057

.reg = 0x50,

sys/dev/ic/nslm7x.c

1065

.reg = 0x50,

sys/dev/ic/nslm7x.c

1075

.reg = 0x28,

sys/dev/ic/nslm7x.c

1083

.reg = 0x29,

sys/dev/ic/nslm7x.c

1091

.reg = 0x2a,

sys/dev/ic/nslm7x.c

1106

.reg = 0x20,

sys/dev/ic/nslm7x.c

1114

.reg = 0x22,

sys/dev/ic/nslm7x.c

1122

.reg = 0x23,

sys/dev/ic/nslm7x.c

1130

.reg = 0x24,

sys/dev/ic/nslm7x.c

1138

.reg = 0x25,

sys/dev/ic/nslm7x.c

1146

.reg = 0x26,

sys/dev/ic/nslm7x.c

1156

.reg = 0x27,

sys/dev/ic/nslm7x.c

1164

.reg = 0x50,

sys/dev/ic/nslm7x.c

1174

.reg = 0x28,

sys/dev/ic/nslm7x.c

1182

.reg = 0x29,

sys/dev/ic/nslm7x.c

1190

.reg = 0x2a,

sys/dev/ic/nslm7x.c

1205

.reg = 0x20,

sys/dev/ic/nslm7x.c

1213

.reg = 0x21,

sys/dev/ic/nslm7x.c

1221

.reg = 0x22,

sys/dev/ic/nslm7x.c

1229

.reg = 0x23,

sys/dev/ic/nslm7x.c

1237

.reg = 0x24,

sys/dev/ic/nslm7x.c

124

.reg = 0x20,

sys/dev/ic/nslm7x.c

1245

.reg = 0x25,

sys/dev/ic/nslm7x.c

1253

.reg = 0x26,

sys/dev/ic/nslm7x.c

1261

.reg = 0xb0,

sys/dev/ic/nslm7x.c

1269

.reg = 0xb1,

sys/dev/ic/nslm7x.c

1277

.reg = 0xb2,

sys/dev/ic/nslm7x.c

1287

.reg = 0x27,

sys/dev/ic/nslm7x.c

1295

.reg = 0xc0,

sys/dev/ic/nslm7x.c

1303

.reg = 0xc8,

sys/dev/ic/nslm7x.c

1313

.reg = 0x28,

sys/dev/ic/nslm7x.c

132

.reg = 0x21,

sys/dev/ic/nslm7x.c

1321

.reg = 0x29,

sys/dev/ic/nslm7x.c

1329

.reg = 0x2a,

sys/dev/ic/nslm7x.c

1337

.reg = 0xba,

sys/dev/ic/nslm7x.c

1345

.reg = 0xbb,

sys/dev/ic/nslm7x.c

1360

.reg = 0x20,

sys/dev/ic/nslm7x.c

1368

.reg = 0x21,

sys/dev/ic/nslm7x.c

1376

.reg = 0x22,

sys/dev/ic/nslm7x.c

1384

.reg = 0x23,

sys/dev/ic/nslm7x.c

1392

.reg = 0x24,

sys/dev/ic/nslm7x.c

140

.reg = 0x22,

sys/dev/ic/nslm7x.c

1400

.reg = 0x25,

sys/dev/ic/nslm7x.c

1408

.reg = 0x26,

sys/dev/ic/nslm7x.c

1416

.reg = 0xb0,

sys/dev/ic/nslm7x.c

1424

.reg = 0xb1,

sys/dev/ic/nslm7x.c

1434

.reg = 0x27,

sys/dev/ic/nslm7x.c

1442

.reg = 0xc0,

sys/dev/ic/nslm7x.c

1450

.reg = 0xc8,

sys/dev/ic/nslm7x.c

1460

.reg = 0x28,

sys/dev/ic/nslm7x.c

1468

.reg = 0x29,

sys/dev/ic/nslm7x.c

1476

.reg = 0x2a,

sys/dev/ic/nslm7x.c

148

.reg = 0x23,

sys/dev/ic/nslm7x.c

1484

.reg = 0xb8,

sys/dev/ic/nslm7x.c

1492

.reg = 0xb9,

sys/dev/ic/nslm7x.c

1500

.reg = 0xba,

sys/dev/ic/nslm7x.c

1508

.reg = 0xbe,

sys/dev/ic/nslm7x.c

1523

.reg = 0x20,

sys/dev/ic/nslm7x.c

1531

.reg = 0x21,

sys/dev/ic/nslm7x.c

1539

.reg = 0x22,

sys/dev/ic/nslm7x.c

1547

.reg = 0x23,

sys/dev/ic/nslm7x.c

1555

.reg = 0x24,

sys/dev/ic/nslm7x.c

156

.reg = 0x24,

sys/dev/ic/nslm7x.c

1563

.reg = 0x25,

sys/dev/ic/nslm7x.c

1571

.reg = 0x26,

sys/dev/ic/nslm7x.c

1581

.reg = 0x27,

sys/dev/ic/nslm7x.c

1589

.reg = 0x50,

sys/dev/ic/nslm7x.c

1597

.reg = 0x50,

sys/dev/ic/nslm7x.c

1607

.reg = 0x28,

sys/dev/ic/nslm7x.c

1615

.reg = 0x29,

sys/dev/ic/nslm7x.c

1623

.reg = 0x2a,

sys/dev/ic/nslm7x.c

1638

.reg = 0x20,

sys/dev/ic/nslm7x.c

164

.reg = 0x25,

sys/dev/ic/nslm7x.c

1646

.reg = 0x21,

sys/dev/ic/nslm7x.c

1654

.reg = 0x22,

sys/dev/ic/nslm7x.c

1662

.reg = 0x23,

sys/dev/ic/nslm7x.c

1670

.reg = 0x24,

sys/dev/ic/nslm7x.c

1678

.reg = 0x25,

sys/dev/ic/nslm7x.c

1686

.reg = 0x26,

sys/dev/ic/nslm7x.c

1694

.reg = 0x50,

sys/dev/ic/nslm7x.c

1702

.reg = 0x51,

sys/dev/ic/nslm7x.c

1712

.reg = 0x27,

sys/dev/ic/nslm7x.c

172

.reg = 0x26,

sys/dev/ic/nslm7x.c

1720

.reg = 0x50,

sys/dev/ic/nslm7x.c

1728

.reg = 0x50,

sys/dev/ic/nslm7x.c

1738

.reg = 0x56,

sys/dev/ic/nslm7x.c

1746

.reg = 0x58,

sys/dev/ic/nslm7x.c

1754

.reg = 0x5a,

sys/dev/ic/nslm7x.c

1762

.reg = 0x5c,

sys/dev/ic/nslm7x.c

1771

.reg = 0x5e,

sys/dev/ic/nslm7x.c

1786

.reg = 0x00,

sys/dev/ic/nslm7x.c

1794

.reg = 0x01,

sys/dev/ic/nslm7x.c

1802

.reg = 0x02,

sys/dev/ic/nslm7x.c

1810

.reg = 0x03,

sys/dev/ic/nslm7x.c

1818

.reg = 0x04,

sys/dev/ic/nslm7x.c

182

.reg = 0x27,

sys/dev/ic/nslm7x.c

1826

.reg = 0x05,

sys/dev/ic/nslm7x.c

1834

.reg = 0x07,

sys/dev/ic/nslm7x.c

1842

.reg = 0x08,

sys/dev/ic/nslm7x.c

1850

.reg = 0x09,

sys/dev/ic/nslm7x.c

1860

.reg = 0x18,

sys/dev/ic/nslm7x.c

1868

.reg = 0x19,

sys/dev/ic/nslm7x.c

1876

.reg = 0x1a,

sys/dev/ic/nslm7x.c

1886

.reg = 0x30,

sys/dev/ic/nslm7x.c

1894

.reg = 0x32,

sys/dev/ic/nslm7x.c

1902

.reg = 0x34,

sys/dev/ic/nslm7x.c

1917

.reg = 0x80,

sys/dev/ic/nslm7x.c

192

.reg = 0x28,

sys/dev/ic/nslm7x.c

1925

.reg = 0x81,

sys/dev/ic/nslm7x.c

1933

.reg = 0x82,

sys/dev/ic/nslm7x.c

1941

.reg = 0x83,

sys/dev/ic/nslm7x.c

1949

.reg = 0x84,

sys/dev/ic/nslm7x.c

1957

.reg = 0x85,

sys/dev/ic/nslm7x.c

1965

.reg = 0x86,

sys/dev/ic/nslm7x.c

1973

.reg = 0x87,

sys/dev/ic/nslm7x.c

1981

.reg = 0x88,

sys/dev/ic/nslm7x.c

1989

.reg = 0x89,

sys/dev/ic/nslm7x.c

1997

.reg = 0x8a,

sys/dev/ic/nslm7x.c

200

.reg = 0x29,

sys/dev/ic/nslm7x.c

2005

.reg = 0x8b,

sys/dev/ic/nslm7x.c

2013

.reg = 0x8c,

sys/dev/ic/nslm7x.c

2021

.reg = 0x8d,

sys/dev/ic/nslm7x.c

2029

.reg = 0x8e,

sys/dev/ic/nslm7x.c

2039

.reg = 0x90,

sys/dev/ic/nslm7x.c

2047

.reg = 0x91,

sys/dev/ic/nslm7x.c

2055

.reg = 0x92,

sys/dev/ic/nslm7x.c

2063

.reg = 0x93,

sys/dev/ic/nslm7x.c

2071

.reg = 0x94,

sys/dev/ic/nslm7x.c

2079

.reg = 0x95,

sys/dev/ic/nslm7x.c

208

.reg = 0x2a,

sys/dev/ic/nslm7x.c

2089

.reg = 0xc0,

sys/dev/ic/nslm7x.c

2097

.reg = 0xc2,

sys/dev/ic/nslm7x.c

2105

.reg = 0xc4,

sys/dev/ic/nslm7x.c

2113

.reg = 0xc6,

sys/dev/ic/nslm7x.c

2121

.reg = 0xc8,

sys/dev/ic/nslm7x.c

2129

.reg = 0xca,

sys/dev/ic/nslm7x.c

2137

.reg = 0xce,

sys/dev/ic/nslm7x.c

223

.reg = 0x20,

sys/dev/ic/nslm7x.c

231

.reg = 0x21,

sys/dev/ic/nslm7x.c

239

.reg = 0x22,

sys/dev/ic/nslm7x.c

247

.reg = 0x23,

sys/dev/ic/nslm7x.c

255

.reg = 0x24,

sys/dev/ic/nslm7x.c

263

.reg = 0x25,

sys/dev/ic/nslm7x.c

2690

data = (*sc->lm_readreg)(sc, sc->lm_sensors[n].reg);

sys/dev/ic/nslm7x.c

271

.reg = 0x26,

sys/dev/ic/nslm7x.c

2719

data = (*sc->lm_readreg)(sc, sc->lm_sensors[n].reg);

sys/dev/ic/nslm7x.c

2744

if (sc->lm_sensors[n].reg == LMD_FAN1 ||

sys/dev/ic/nslm7x.c

2745

sc->lm_sensors[n].reg == LMD_FAN2) {

sys/dev/ic/nslm7x.c

2747

if (sc->lm_sensors[n].reg == LMD_FAN1)

sys/dev/ic/nslm7x.c

2753

data = (*sc->lm_readreg)(sc, sc->lm_sensors[n].reg);

sys/dev/ic/nslm7x.c

2789

data = (*sc->lm_readreg)(sc, sc->lm_sensors[n].reg);

sys/dev/ic/nslm7x.c

279

.reg = 0x50,

sys/dev/ic/nslm7x.c

2810

data = (*sc->lm_readreg)(sc, sc->lm_sensors[n].reg);

sys/dev/ic/nslm7x.c

2829

data = (*sc->lm_readreg)(sc, sc->lm_sensors[n].reg);

sys/dev/ic/nslm7x.c

2855

data = (*sc->lm_readreg)(sc, sc->lm_sensors[n].reg) << 1;

sys/dev/ic/nslm7x.c

2856

data += (*sc->lm_readreg)(sc, sc->lm_sensors[n].reg + 1) >> 7;

sys/dev/ic/nslm7x.c

287

.reg = 0x51,

sys/dev/ic/nslm7x.c

2879

if (sc->lm_sensors[n].reg == LMD_FAN1 ||

sys/dev/ic/nslm7x.c

2880

sc->lm_sensors[n].reg == LMD_FAN2 ||

sys/dev/ic/nslm7x.c

2881

sc->lm_sensors[n].reg == LMD_FAN3) {

sys/dev/ic/nslm7x.c

2883

fan = (sc->lm_sensors[n].reg - LMD_FAN1);

sys/dev/ic/nslm7x.c

2888

if (sc->lm_sensors[n].reg == LMD_FAN1 ||

sys/dev/ic/nslm7x.c

2889

sc->lm_sensors[n].reg == LMD_FAN2) {

sys/dev/ic/nslm7x.c

2891

if (sc->lm_sensors[n].reg == LMD_FAN1)

sys/dev/ic/nslm7x.c

2895

} else if (sc->lm_sensors[n].reg == LMD_FAN3) {

sys/dev/ic/nslm7x.c

2898

} else if (sc->lm_sensors[n].reg == WB_BANK0_FAN4 ||

sys/dev/ic/nslm7x.c

2899

sc->lm_sensors[n].reg == WB_BANK0_FAN5) {

sys/dev/ic/nslm7x.c

2901

if (sc->lm_sensors[n].reg == WB_BANK0_FAN4)

sys/dev/ic/nslm7x.c

2907

data = (*sc->lm_readreg)(sc, sc->lm_sensors[n].reg);

sys/dev/ic/nslm7x.c

2923

datah = (*sc->lm_readreg)(sc, sc->lm_sensors[n].reg);

sys/dev/ic/nslm7x.c

2924

datal = (*sc->lm_readreg)(sc, sc->lm_sensors[n].reg + 1);

sys/dev/ic/nslm7x.c

2938

uint8_t reg;

sys/dev/ic/nslm7x.c

2942

switch (sc->lm_sensors[n].reg) {

sys/dev/ic/nslm7x.c

2944

reg = 0x47; shift = 0;

sys/dev/ic/nslm7x.c

2947

reg = 0x47; shift = 4;

sys/dev/ic/nslm7x.c

2950

reg = 0x5b; shift = 0;

sys/dev/ic/nslm7x.c

2953

reg = 0x5b; shift = 4;

sys/dev/ic/nslm7x.c

2956

reg = 0x5c; shift = 0;

sys/dev/ic/nslm7x.c

2959

reg = 0x5c; shift = 4;

sys/dev/ic/nslm7x.c

2962

reg = 0x9e; shift = 0;

sys/dev/ic/nslm7x.c

2965

reg = 0;

sys/dev/ic/nslm7x.c

2969

data = (*sc->lm_readreg)(sc, sc->lm_sensors[n].reg);

sys/dev/ic/nslm7x.c

297

.reg = 0x27,

sys/dev/ic/nslm7x.c

2973

if (reg != 0)

sys/dev/ic/nslm7x.c

2974

divisor = ((*sc->lm_readreg)(sc, reg) >> shift) & 0x7;

sys/dev/ic/nslm7x.c

2991

data = (*sc->lm_readreg)(sc, sc->lm_sensors[n].reg) << 1;

sys/dev/ic/nslm7x.c

2992

data += (*sc->lm_readreg)(sc, sc->lm_sensors[n].reg + 1) >> 7;

sys/dev/ic/nslm7x.c

305

.reg = 0x50,

sys/dev/ic/nslm7x.c

313

.reg = 0x50,

sys/dev/ic/nslm7x.c

323

.reg = 0x28,

sys/dev/ic/nslm7x.c

331

.reg = 0x29,

sys/dev/ic/nslm7x.c

339

.reg = 0x2a,

sys/dev/ic/nslm7x.c

362

.reg = 0x20,

sys/dev/ic/nslm7x.c

370

.reg = 0x21,

sys/dev/ic/nslm7x.c

378

.reg = 0x22,

sys/dev/ic/nslm7x.c

386

.reg = 0x23,

sys/dev/ic/nslm7x.c

394

.reg = 0x24,

sys/dev/ic/nslm7x.c

402

.reg = 0x25,

sys/dev/ic/nslm7x.c

410

.reg = 0x26,

sys/dev/ic/nslm7x.c

418

.reg = 0x50,

sys/dev/ic/nslm7x.c

426

.reg = 0x51,

sys/dev/ic/nslm7x.c

434

.reg = 0x52,

sys/dev/ic/nslm7x.c

444

.reg = 0x27,

sys/dev/ic/nslm7x.c

452

.reg = 0x50,

sys/dev/ic/nslm7x.c

460

.reg = 0x50,

sys/dev/ic/nslm7x.c

470

.reg = 0x28,

sys/dev/ic/nslm7x.c

478

.reg = 0x29,

sys/dev/ic/nslm7x.c

486

.reg = 0x2a,

sys/dev/ic/nslm7x.c

501

.reg = 0x20,

sys/dev/ic/nslm7x.c

509

.reg = 0x21,

sys/dev/ic/nslm7x.c

517

.reg = 0x22,

sys/dev/ic/nslm7x.c

525

.reg = 0x23,

sys/dev/ic/nslm7x.c

533

.reg = 0x24,

sys/dev/ic/nslm7x.c

541

.reg = 0x25,

sys/dev/ic/nslm7x.c

549

.reg = 0x26,

sys/dev/ic/nslm7x.c

557

.reg = 0x50,

sys/dev/ic/nslm7x.c

565

.reg = 0x51,

sys/dev/ic/nslm7x.c

575

.reg = 0x27,

sys/dev/ic/nslm7x.c

583

.reg = 0x50,

sys/dev/ic/nslm7x.c

591

.reg = 0x50,

sys/dev/ic/nslm7x.c

601

.reg = 0x28,

sys/dev/ic/nslm7x.c

609

.reg = 0x29,

sys/dev/ic/nslm7x.c

617

.reg = 0x2a,

sys/dev/ic/nslm7x.c

632

.reg = 0x20,

sys/dev/ic/nslm7x.c

640

.reg = 0x21,

sys/dev/ic/nslm7x.c

648

.reg = 0x22,

sys/dev/ic/nslm7x.c

656

.reg = 0x23,

sys/dev/ic/nslm7x.c

664

.reg = 0x24,

sys/dev/ic/nslm7x.c

672

.reg = 0x50,

sys/dev/ic/nslm7x.c

680

.reg = 0x51,

sys/dev/ic/nslm7x.c

690

.reg = 0x27,

sys/dev/ic/nslm7x.c

698

.reg = 0x50,

sys/dev/ic/nslm7x.c

706

.reg = 0x50,

sys/dev/ic/nslm7x.c

716

.reg = 0x28,

sys/dev/ic/nslm7x.c

724

.reg = 0x29,

sys/dev/ic/nslm7x.c

732

.reg = 0x2a,

sys/dev/ic/nslm7x.c

747

.reg = 0x20,

sys/dev/ic/nslm7x.c

755

.reg = 0x22,

sys/dev/ic/nslm7x.c

763

.reg = 0x23,

sys/dev/ic/nslm7x.c

771

.reg = 0x24,

sys/dev/ic/nslm7x.c

779

.reg = 0x25,

sys/dev/ic/nslm7x.c

787

.reg = 0x26,

sys/dev/ic/nslm7x.c

795

.reg = 0x50,

sys/dev/ic/nslm7x.c

803

.reg = 0x51,

sys/dev/ic/nslm7x.c

813

.reg = 0x27,

sys/dev/ic/nslm7x.c

821

.reg = 0x50,

sys/dev/ic/nslm7x.c

831

.reg = 0x28,

sys/dev/ic/nslm7x.c

839

.reg = 0x29,

sys/dev/ic/nslm7x.c

860

.reg = 0x20,

sys/dev/ic/nslm7x.c

868

.reg = 0x21,

sys/dev/ic/nslm7x.c

876

.reg = 0x22,

sys/dev/ic/nslm7x.c

884

.reg = 0x23,

sys/dev/ic/nslm7x.c

892

.reg = 0x24,

sys/dev/ic/nslm7x.c

900

.reg = 0x25,

sys/dev/ic/nslm7x.c

908

.reg = 0x26,

sys/dev/ic/nslm7x.c

918

.reg = 0x27,

sys/dev/ic/nslm7x.c

926

.reg = 0x50,

sys/dev/ic/nslm7x.c

934

.reg = 0x50,

sys/dev/ic/nslm7x.c

944

.reg = 0x28,

sys/dev/ic/nslm7x.c

952

.reg = 0x29,

sys/dev/ic/nslm7x.c

960

.reg = 0x2a,

sys/dev/ic/nslm7x.c

975

.reg = 0x20,

sys/dev/ic/nslm7x.c

983

.reg = 0x21,

sys/dev/ic/nslm7x.c

991

.reg = 0x22,

sys/dev/ic/nslm7x.c

999

.reg = 0x23,

sys/dev/ic/nslm7xvar.h

182

uint8_t reg;

sys/dev/ic/nvme.c

357

uint32_t reg;

sys/dev/ic/nvme.c

367

reg = nvme_read4(sc, NVME_VS);

sys/dev/ic/nvme.c

368

if (reg == 0xffffffff) {

sys/dev/ic/nvme.c

373

if (NVME_VS_TER(reg) == 0)

sys/dev/ic/nvme.c

374

aprint_normal_dev(sc->sc_dev, "NVMe %d.%d\n", NVME_VS_MJR(reg),

sys/dev/ic/nvme.c

375

NVME_VS_MNR(reg));

sys/dev/ic/nvme.c

377

aprint_normal_dev(sc->sc_dev, "NVMe %d.%d.%d\n", NVME_VS_MJR(reg),

sys/dev/ic/nvme.c

378

NVME_VS_MNR(reg), NVME_VS_TER(reg));

sys/dev/ic/osiopvar.h

61

#define osiop_read_1(sc, reg) \

sys/dev/ic/osiopvar.h

62

bus_space_read_1((sc)->sc_bst, (sc)->sc_reg, reg)

sys/dev/ic/osiopvar.h

63

#define osiop_write_1(sc, reg, val) \

sys/dev/ic/osiopvar.h

64

bus_space_write_1((sc)->sc_bst, (sc)->sc_reg, reg, val)

sys/dev/ic/osiopvar.h

66

#define osiop_read_4(sc, reg) \

sys/dev/ic/osiopvar.h

67

bus_space_read_4((sc)->sc_bst, (sc)->sc_reg, reg)

sys/dev/ic/osiopvar.h

68

#define osiop_write_4(sc, reg, val) \

sys/dev/ic/osiopvar.h

69

bus_space_write_4((sc)->sc_bst, (sc)->sc_reg, reg, val)

sys/dev/ic/pca9564var.h

32

uint8_t (*read_byte)(device_t, int reg);

sys/dev/ic/pca9564var.h

33

void (*write_byte)(device_t, int reg, uint8_t val);

sys/dev/ic/pcdisplayvar.h

60

static __inline u_int8_t _pcdisplay_6845_read(struct pcdisplay_handle *ph, int reg)

sys/dev/ic/pcdisplayvar.h

62

bus_space_write_1(ph->ph_iot, ph->ph_ioh_6845, MC6845_INDEX, reg);

sys/dev/ic/pcdisplayvar.h

67

int reg, uint8_t val)

sys/dev/ic/pcdisplayvar.h

69

bus_space_write_1(ph->ph_iot, ph->ph_ioh_6845, MC6845_INDEX, reg);

sys/dev/ic/pcdisplayvar.h

73

#define pcdisplay_6845_read(ph, reg) \

sys/dev/ic/pcdisplayvar.h

74

_pcdisplay_6845_read(ph, offsetof(struct reg_mc6845, reg))

sys/dev/ic/pcdisplayvar.h

75

#define pcdisplay_6845_write(ph, reg, val) \

sys/dev/ic/pcdisplayvar.h

76

_pcdisplay_6845_write(ph, offsetof(struct reg_mc6845, reg), val)

sys/dev/ic/pl031.c

47

#define RTC_READ(sc, reg) \

sys/dev/ic/pl031.c

48

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/dev/ic/pl031.c

49

#define RTC_WRITE(sc, reg, val) \

sys/dev/ic/pl031.c

50

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/dev/ic/pl041.c

247

aaci_ac97_read(void *priv, uint8_t reg, uint16_t *val)

sys/dev/ic/pl041.c

251

AACI_WRITE(sc, AACISL1TX, (reg << 12) | (1 << 19));

sys/dev/ic/pl041.c

253

if (AACI_READ(sc, AACISL1RX) != (reg << 12))

sys/dev/ic/pl041.c

261

aaci_ac97_write(void *priv, uint8_t reg, uint16_t val)

sys/dev/ic/pl041.c

266

AACI_WRITE(sc, AACISL1TX, (reg << 12) | (0 << 19));

sys/dev/ic/pl041.c

80

#define AACI_READ(sc, reg) \

sys/dev/ic/pl041.c

81

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/dev/ic/pl041.c

82

#define AACI_WRITE(sc, reg, val) \

sys/dev/ic/pl041.c

83

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/dev/ic/pl041.c

84

#define AACI_WRITE_MULTI(sc, reg, val, cnt) \

sys/dev/ic/pl041.c

85

bus_space_write_multi_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val), (cnt))

sys/dev/ic/pl050.c

53

#define PLKMI_READ(sc, reg) \

sys/dev/ic/pl050.c

54

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/dev/ic/pl050.c

55

#define PLKMI_WRITE(sc, reg, val) \

sys/dev/ic/pl050.c

56

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/dev/ic/pl061var.h

49

#define PLGPIO_WRITE(sc, reg, val) \

sys/dev/ic/pl061var.h

50

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/dev/ic/pl061var.h

51

#define PLGPIO_READ(sc, reg) \

sys/dev/ic/pl061var.h

52

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/dev/ic/pl181.c

101

#define MMCI_WRITE(sc, reg, val) \

sys/dev/ic/pl181.c

102

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/dev/ic/pl181.c

103

#define MMCI_WRITE_MULTI(sc, reg, datap, cnt) \

sys/dev/ic/pl181.c

104

bus_space_write_multi_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (datap), (cnt))

sys/dev/ic/pl181.c

105

#define MMCI_READ(sc, reg) \

sys/dev/ic/pl181.c

106

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/dev/ic/pl181.c

107

#define MMCI_READ_MULTI(sc, reg, datap, cnt) \

sys/dev/ic/pl181.c

108

bus_space_read_multi_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (datap), (cnt))

sys/dev/ic/rt2560.c

149

uint32_t reg;

sys/dev/ic/rt2560.c

186

uint8_t reg;

sys/dev/ic/rt2560.c

2258

rt2560_bbp_write(struct rt2560_softc *sc, uint8_t reg, uint8_t val)

sys/dev/ic/rt2560.c

2273

tmp = RT2560_BBP_WRITE | RT2560_BBP_BUSY | reg << 8 | val;

sys/dev/ic/rt2560.c

2276

DPRINTFN(15, ("BBP R%u <- 0x%02x\n", reg, val));

sys/dev/ic/rt2560.c

2280

rt2560_bbp_read(struct rt2560_softc *sc, uint8_t reg)

sys/dev/ic/rt2560.c

2285

val = RT2560_BBP_BUSY | reg << 8;

sys/dev/ic/rt2560.c

2300

rt2560_rf_write(struct rt2560_softc *sc, uint8_t reg, uint32_t val)

sys/dev/ic/rt2560.c

2316

(reg & 0x3);

sys/dev/ic/rt2560.c

2320

sc->rf_regs[reg] = val;

sys/dev/ic/rt2560.c

2322

DPRINTFN(15, ("RF R[%u] <- 0x%05x\n", reg & 0x3, val & 0xfffff));

sys/dev/ic/rt2560.c

2712

sc->bbp_prom[i].reg = val >> 8;

sys/dev/ic/rt2560.c

2743

rt2560_bbp_write(sc, rt2560_def_bbp[i].reg,

sys/dev/ic/rt2560.c

2749

if (sc->bbp_prom[i].reg == 0xff)

sys/dev/ic/rt2560.c

2751

rt2560_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val);

sys/dev/ic/rt2560.c

2800

RAL_WRITE(sc, rt2560_def_mac[i].reg, rt2560_def_mac[i].val);

sys/dev/ic/rt2560reg.h

304

#define RAL_READ(sc, reg) \

sys/dev/ic/rt2560reg.h

305

bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))

sys/dev/ic/rt2560reg.h

307

#define RAL_WRITE(sc, reg, val) \

sys/dev/ic/rt2560reg.h

308

bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))

sys/dev/ic/rt2560var.h

141

uint8_t reg;

sys/dev/ic/rt2661.c

171

uint32_t reg;

sys/dev/ic/rt2661.c

178

uint8_t reg;

sys/dev/ic/rt2661.c

1989

rt2661_bbp_write(struct rt2661_softc *sc, uint8_t reg, uint8_t val)

sys/dev/ic/rt2661.c

2004

tmp = RT2661_BBP_BUSY | (reg & 0x7f) << 8 | val;

sys/dev/ic/rt2661.c

2007

DPRINTFN(15, ("BBP R%u <- 0x%02x\n", reg, val));

sys/dev/ic/rt2661.c

2011

rt2661_bbp_read(struct rt2661_softc *sc, uint8_t reg)

sys/dev/ic/rt2661.c

2026

val = RT2661_BBP_BUSY | RT2661_BBP_READ | reg << 8;

sys/dev/ic/rt2661.c

2041

rt2661_rf_write(struct rt2661_softc *sc, uint8_t reg, uint32_t val)

sys/dev/ic/rt2661.c

2056

(reg & 3);

sys/dev/ic/rt2661.c

2060

sc->rf_regs[reg] = val;

sys/dev/ic/rt2661.c

2062

DPRINTFN(15, ("RF R[%u] <- 0x%05x\n", reg & 3, val & 0x1fffff));

sys/dev/ic/rt2661.c

2503

sc->bbp_prom[i].reg = val >> 8;

sys/dev/ic/rt2661.c

2505

DPRINTF(("BBP R%d=%02x\n", sc->bbp_prom[i].reg,

sys/dev/ic/rt2661.c

2531

rt2661_bbp_write(sc, rt2661_def_bbp[i].reg,

sys/dev/ic/rt2661.c

2537

if (sc->bbp_prom[i].reg == 0)

sys/dev/ic/rt2661.c

2539

rt2661_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val);

sys/dev/ic/rt2661.c

2659

RAL_WRITE(sc, rt2661_def_mac[i].reg, rt2661_def_mac[i].val);

sys/dev/ic/rt2661reg.h

325

#define RAL_READ(sc, reg) \

sys/dev/ic/rt2661reg.h

326

bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))

sys/dev/ic/rt2661reg.h

332

#define RAL_WRITE(sc, reg, val) \

sys/dev/ic/rt2661reg.h

333

bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))

sys/dev/ic/rt2661reg.h

335

#define RAL_WRITE_1(sc, reg, val) \

sys/dev/ic/rt2661reg.h

336

bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))

sys/dev/ic/rt2661reg.h

338

#define RAL_RW_BARRIER_1(sc, reg) \

sys/dev/ic/rt2661reg.h

339

bus_space_barrier((sc)->sc_st, (sc)->sc_sh, (reg), 1, \

sys/dev/ic/rt2661var.h

136

uint8_t reg;

sys/dev/ic/rt2860.c

1101

uint16_t reg;

sys/dev/ic/rt2860.c

1129

reg = RT3070_EFUSE_DATA3 - (addr & 0xc);

sys/dev/ic/rt2860.c

1130

tmp = RAL_READ(sc, reg);

sys/dev/ic/rt2860.c

177

uint32_t reg;

sys/dev/ic/rt2860.c

184

uint8_t reg;

sys/dev/ic/rt2860.c

2027

rt2860_mcu_bbp_write(struct rt2860_softc *sc, uint8_t reg, uint8_t val)

sys/dev/ic/rt2860.c

2043

RT2860_BBP_CSR_KICK | reg << 8 | val);

sys/dev/ic/rt2860.c

2051

rt2860_mcu_bbp_read(struct rt2860_softc *sc, uint8_t reg)

sys/dev/ic/rt2860.c

206

uint8_t reg;

sys/dev/ic/rt2860.c

2068

RT2860_BBP_CSR_KICK | RT2860_BBP_CSR_READ | reg << 8);

sys/dev/ic/rt2860.c

2089

rt2860_rf_write(struct rt2860_softc *sc, uint8_t reg, uint32_t val)

sys/dev/ic/rt2860.c

2106

(val & 0x3fffff) << 2 | (reg & 3);

sys/dev/ic/rt2860.c

2111

rt3090_rf_read(struct rt2860_softc *sc, uint8_t reg)

sys/dev/ic/rt2860.c

2125

tmp = RT3070_RF_KICK | reg << 8;

sys/dev/ic/rt2860.c

2142

rt3090_rf_write(struct rt2860_softc *sc, uint8_t reg, uint8_t val)

sys/dev/ic/rt2860.c

2157

tmp = RT3070_RF_WRITE | RT3070_RF_KICK | reg << 8 | val;

sys/dev/ic/rt2860.c

2609

rt3090_rf_write(sc, rt3572_def_rf[i].reg,

sys/dev/ic/rt2860.c

2614

rt3090_rf_write(sc, rt3090_def_rf[i].reg,

sys/dev/ic/rt2860.c

2709

rt3090_rf_write(sc, rt5392_def_rf[i].reg,

sys/dev/ic/rt2860.c

2714

rt3090_rf_write(sc, rt5390_def_rf[i].reg,

sys/dev/ic/rt2860.c

2955

if (sc->rf[i].reg == 0 || sc->rf[i].reg == 0xff)

sys/dev/ic/rt2860.c

2957

rt3090_rf_write(sc, sc->rf[i].reg, sc->rf[i].val);

sys/dev/ic/rt2860.c

3351

sc->bbp[i].reg = val >> 8;

sys/dev/ic/rt2860.c

3352

DPRINTF(("BBP%d=0x%02x\n", sc->bbp[i].reg, sc->bbp[i].val));

sys/dev/ic/rt2860.c

3359

sc->rf[i].reg = val >> 8;

sys/dev/ic/rt2860.c

3360

DPRINTF(("RF%d=0x%02x\n", sc->rf[i].reg,

sys/dev/ic/rt2860.c

3490

uint32_t reg;

sys/dev/ic/rt2860.c

3493

reg = val;

sys/dev/ic/rt2860.c

3495

reg |= (uint32_t)val << 16;

sys/dev/ic/rt2860.c

3497

sc->txpow20mhz[ridx] = reg;

sys/dev/ic/rt2860.c

3498

sc->txpow40mhz_2ghz[ridx] = b4inc(reg, delta_2ghz);

sys/dev/ic/rt2860.c

3499

sc->txpow40mhz_5ghz[ridx] = b4inc(reg, delta_5ghz);

sys/dev/ic/rt2860.c

3635

rt2860_mcu_bbp_write(sc, rt2860_def_bbp[i].reg,

sys/dev/ic/rt2860.c

3673

rt2860_mcu_bbp_write(sc, rt5390_def_bbp[i].reg,

sys/dev/ic/rt2860.c

3839

RAL_WRITE(sc, rt2860_def_mac[i].reg, rt2860_def_mac[i].val);

sys/dev/ic/rt2860.c

3932

if (sc->bbp[i].reg == 0 || sc->bbp[i].reg == 0xff)

sys/dev/ic/rt2860.c

3934

rt2860_mcu_bbp_write(sc, sc->bbp[i].reg, sc->bbp[i].val);

sys/dev/ic/rt2860reg.h

1075

#define RAL_READ(sc, reg) \

sys/dev/ic/rt2860reg.h

1076

bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))

sys/dev/ic/rt2860reg.h

1078

#define RAL_WRITE(sc, reg, val) \

sys/dev/ic/rt2860reg.h

1079

bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))

sys/dev/ic/rt2860var.h

186

uint8_t reg;

sys/dev/ic/rtl80x9.c

110

uint8_t reg;

sys/dev/ic/rtl80x9.c

120

reg = NIC_GET(sc->sc_regt, sc->sc_regh, NERTL_RTL3_CONFIG2);

sys/dev/ic/rtl80x9.c

121

reg &= ~(RTL3_CONFIG2_PL1 | RTL3_CONFIG2_PL0);

sys/dev/ic/rtl80x9.c

136

reg |= RTL3_CONFIG2_PL1 | RTL3_CONFIG2_PL0;

sys/dev/ic/rtl80x9.c

139

NIC_PUT(sc->sc_regt, sc->sc_regh, NERTL_RTL3_CONFIG2, reg);

sys/dev/ic/rtl80x9.c

142

reg = NIC_GET(sc->sc_regt, sc->sc_regh, NERTL_RTL3_CONFIG3);

sys/dev/ic/rtl80x9.c

144

reg |= RTL3_CONFIG3_FUDUP;

sys/dev/ic/rtl80x9.c

146

reg &= ~RTL3_CONFIG3_FUDUP;

sys/dev/ic/rtl80x9.c

147

NIC_PUT(sc->sc_regt, sc->sc_regh, NERTL_RTL3_CONFIG3, reg);

sys/dev/ic/rtl8169.c

1950

uint32_t reg;

sys/dev/ic/rtl8169.c

2011

reg = enaddr[0] | (enaddr[1] << 8) |

sys/dev/ic/rtl8169.c

2013

CSR_WRITE_4(sc, RTK_IDR0, reg);

sys/dev/ic/rtl8169.c

2014

reg = enaddr[4] | (enaddr[5] << 8);

sys/dev/ic/rtl8169.c

2015

CSR_WRITE_4(sc, RTK_IDR4, reg);

sys/dev/ic/rtl8169.c

244

re_gmii_readreg(device_t dev, int phy, int reg, uint16_t *val)

sys/dev/ic/rtl8169.c

255

if (reg == RTK_GMEDIASTAT) {

sys/dev/ic/rtl8169.c

260

CSR_WRITE_4(sc, RTK_PHYAR, reg << 16);

sys/dev/ic/rtl8169.c

280

re_gmii_writereg(device_t dev, int phy, int reg, uint16_t val)

sys/dev/ic/rtl8169.c

286

CSR_WRITE_4(sc, RTK_PHYAR, (reg << 16) |

sys/dev/ic/rtl8169.c

299

device_xname(sc->sc_dev), reg, val);

sys/dev/ic/rtl8169.c

307

re_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val)

sys/dev/ic/rtl8169.c

314

rv = re_gmii_readreg(dev, phy, reg, val);

sys/dev/ic/rtl8169.c

322

switch (reg) {

sys/dev/ic/rtl8169.c

364

re_miibus_writereg(device_t dev, int phy, int reg, uint16_t val)

sys/dev/ic/rtl8169.c

371

rv = re_gmii_writereg(dev, phy, reg, val);

sys/dev/ic/rtl8169.c

379

switch (reg) {

sys/dev/ic/rtl81x9.c

413

rtk_phy_readreg(device_t self, int phy, int reg, uint16_t *val)

sys/dev/ic/rtl81x9.c

424

switch (reg) {

sys/dev/ic/rtl81x9.c

457

frame.mii_regaddr = reg;

sys/dev/ic/rtl81x9.c

465

rtk_phy_writereg(device_t self, int phy, int reg, uint16_t val)

sys/dev/ic/rtl81x9.c

475

switch (reg) {

sys/dev/ic/rtl81x9.c

504

frame.mii_regaddr = reg;

sys/dev/ic/rtl81x9var.h

283

#define CSR_WRITE_4(sc, reg, val) \

sys/dev/ic/rtl81x9var.h

284

bus_space_write_4(sc->rtk_btag, sc->rtk_bhandle, reg, val)

sys/dev/ic/rtl81x9var.h

285

#define CSR_WRITE_2(sc, reg, val) \

sys/dev/ic/rtl81x9var.h

286

bus_space_write_2(sc->rtk_btag, sc->rtk_bhandle, reg, val)

sys/dev/ic/rtl81x9var.h

287

#define CSR_WRITE_1(sc, reg, val) \

sys/dev/ic/rtl81x9var.h

288

bus_space_write_1(sc->rtk_btag, sc->rtk_bhandle, reg, val)

sys/dev/ic/rtl81x9var.h

290

#define CSR_READ_4(sc, reg) \

sys/dev/ic/rtl81x9var.h

291

bus_space_read_4(sc->rtk_btag, sc->rtk_bhandle, reg)

sys/dev/ic/rtl81x9var.h

292

#define CSR_READ_2(sc, reg) \

sys/dev/ic/rtl81x9var.h

293

bus_space_read_2(sc->rtk_btag, sc->rtk_bhandle, reg)

sys/dev/ic/rtl81x9var.h

294

#define CSR_READ_1(sc, reg) \

sys/dev/ic/rtl81x9var.h

295

bus_space_read_1(sc->rtk_btag, sc->rtk_bhandle, reg)

sys/dev/ic/rtsx.c

100

#define RTSX_BITOP(sc, reg, mask, bits) \

sys/dev/ic/rtsx.c

102

int err = rtsx_write((sc), (reg), (mask), (bits));\

sys/dev/ic/rtsx.c

1091

rtsx_hostcmd(uint32_t *cmdbuf, int *n, uint8_t cmd, uint16_t reg,

sys/dev/ic/rtsx.c

1098

((uint32_t)(reg & 0x3fff) << 16) |

sys/dev/ic/rtsx.c

1107

uint16_t reg;

sys/dev/ic/rtsx.c

1112

for (reg = 0xFDA0; reg < 0xFDAE; reg++)

sys/dev/ic/rtsx.c

1113

(void)rtsx_read(sc, reg, &sc->sc_regs[i++]);

sys/dev/ic/rtsx.c

1114

for (reg = 0xFD52; reg < 0xFD69; reg++)

sys/dev/ic/rtsx.c

1115

(void)rtsx_read(sc, reg, &sc->sc_regs[i++]);

sys/dev/ic/rtsx.c

1116

for (reg = 0xFE20; reg < 0xFE34; reg++)

sys/dev/ic/rtsx.c

1117

(void)rtsx_read(sc, reg, &sc->sc_regs[i++]);

sys/dev/ic/rtsx.c

1134

uint16_t reg;

sys/dev/ic/rtsx.c

1147

for (reg = 0xFDA0; reg < 0xFDAE; reg++)

sys/dev/ic/rtsx.c

1148

(void)rtsx_write(sc, reg, 0xff, sc->sc_regs[i++]);

sys/dev/ic/rtsx.c

1149

for (reg = 0xFD52; reg < 0xFD69; reg++)

sys/dev/ic/rtsx.c

1150

(void)rtsx_write(sc, reg, 0xff, sc->sc_regs[i++]);

sys/dev/ic/rtsx.c

1151

for (reg = 0xFE20; reg < 0xFE34; reg++)

sys/dev/ic/rtsx.c

1152

(void)rtsx_write(sc, reg, 0xff, sc->sc_regs[i++]);

sys/dev/ic/rtsx.c

1208

uint16_t reg;

sys/dev/ic/rtsx.c

1215

reg = RTSX_PPBUF_BASE2;

sys/dev/ic/rtsx.c

1221

rtsx_hostcmd(cmdbuf, &ncmd, RTSX_READ_REG_CMD, reg++,

sys/dev/ic/rtsx.c

1238

rtsx_hostcmd(cmdbuf, &ncmd, RTSX_READ_REG_CMD, reg++,

sys/dev/ic/rtsx.c

1260

uint16_t reg;

sys/dev/ic/rtsx.c

1267

reg = RTSX_PPBUF_BASE2;

sys/dev/ic/rtsx.c

1273

rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, reg++,

sys/dev/ic/rtsx.c

1286

rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, reg++,

sys/dev/ic/rtsx.c

330

uint8_t reg;

sys/dev/ic/rtsx.c

336

RTSX_READ(sc, RTSX_DUMMY_REG, &reg);

sys/dev/ic/rtsx.c

337

switch (reg & 0x0f) {

sys/dev/ic/rtsx.c

347

"unknown RTS5229 version 0x%02x\n", reg);

sys/dev/ic/rtsx.c

351

RTSX_READ(sc, RTSX_RTL8411B_PACKAGE, &reg);

sys/dev/ic/rtsx.c

352

if (reg & RTSX_RTL8411B_QFN48)

sys/dev/ic/rtsx.c

67

#define READ4(sc, reg) \

sys/dev/ic/rtsx.c

68

(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))

sys/dev/ic/rtsx.c

69

#define WRITE4(sc, reg, val) \

sys/dev/ic/rtsx.c

70

bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))

sys/dev/ic/rtsx.c

72

#define RTSX_READ(sc, reg, val) \

sys/dev/ic/rtsx.c

74

int err = rtsx_read((sc), (reg), (val)); \

sys/dev/ic/rtsx.c

79

#define RTSX_WRITE(sc, reg, val) \

sys/dev/ic/rtsx.c

81

int err = rtsx_write((sc), (reg), 0xff, (val)); \

sys/dev/ic/rtsx.c

86

#define RTSX_CLR(sc, reg, bits) \

sys/dev/ic/rtsx.c

88

int err = rtsx_write((sc), (reg), (bits), 0); \

sys/dev/ic/rtsx.c

93

#define RTSX_SET(sc, reg, bits) \

sys/dev/ic/rtsx.c

938

uint32_t reg = 0 /* XXXGCC12 */;

sys/dev/ic/rtsx.c

944

reg = READ4(sc, RTSX_HAIMR);

sys/dev/ic/rtsx.c

945

if (!(reg & RTSX_HAIMR_BUSY))

sys/dev/ic/rtsx.c

949

*val = (reg & 0xff);

sys/dev/ic/rtsx.c

95

int err = rtsx_write((sc), (reg), (bits), 0xff);\

sys/dev/ic/rtsx.c

957

uint32_t reg;

sys/dev/ic/rtsx.c

965

reg = READ4(sc, RTSX_HAIMR);

sys/dev/ic/rtsx.c

966

if (!(reg & RTSX_HAIMR_BUSY)) {

sys/dev/ic/rtsx.c

967

if (val != (reg & 0xff))

sys/dev/ic/rtw.c

238

#define PRINTREG32(sc, reg) \

sys/dev/ic/rtw.c

240

("%s: reg[ " #reg " / %03x ] = %08x\n", \

sys/dev/ic/rtw.c

241

dvname, reg, RTW_READ(regs, reg)))

sys/dev/ic/rtw.c

243

#define PRINTREG16(sc, reg) \

sys/dev/ic/rtw.c

245

("%s: reg[ " #reg " / %03x ] = %04x\n", \

sys/dev/ic/rtw.c

246

dvname, reg, RTW_READ16(regs, reg)))

sys/dev/ic/rtw.c

248

#define PRINTREG8(sc, reg) \

sys/dev/ic/rtw.c

250

("%s: reg[ " #reg " / %03x ] = %02x\n", \

sys/dev/ic/rtw.c

251

dvname, reg, RTW_READ8(regs, reg)))

sys/dev/ic/rtwn_data.h

29

uint16_t reg;

sys/dev/ic/rtwphy.c

94

#define RTW_BBP_WRITE_OR_RETURN(reg, val) \

sys/dev/ic/rtwphy.c

95

if ((rc = rtw_bbp_write(regs, reg, val)) != 0) \

sys/dev/ic/rtwphyio.c

122

uint32_t mask, reg;

sys/dev/ic/rtwphyio.c

130

reg = RTW_PHYCFG_HST;

sys/dev/ic/rtwphyio.c

131

RTW_WRITE(regs, RTW_PHYCFG, reg);

sys/dev/ic/rtwphyio.c

145

reg |= RTW_PHYCFG_HST_DATA;

sys/dev/ic/rtwphyio.c

147

reg &= ~RTW_PHYCFG_HST_DATA;

sys/dev/ic/rtwphyio.c

149

reg |= RTW_PHYCFG_HST_CLK;

sys/dev/ic/rtwphyio.c

150

RTW_WRITE(regs, RTW_PHYCFG, reg);

sys/dev/ic/rtwphyio.c

155

reg &= ~RTW_PHYCFG_HST_CLK;

sys/dev/ic/rtwphyio.c

156

RTW_WRITE(regs, RTW_PHYCFG, reg);

sys/dev/ic/rtwphyio.c

165

reg |= RTW_PHYCFG_HST_EN;

sys/dev/ic/rtwphyio.c

166

KASSERT((reg & RTW_PHYCFG_HST_CLK) == 0);

sys/dev/ic/rtwphyio.c

167

RTW_WRITE(regs, RTW_PHYCFG, reg);

sys/dev/ic/rtwphyio.c

175

rtw_rf_macbangbits(struct rtw_regs *regs, uint32_t reg)

sys/dev/ic/rtwphyio.c

179

RTW_DPRINTF(RTW_DEBUG_PHY, ("%s: %#08x\n", __func__, reg));

sys/dev/ic/rtwphyio.c

181

RTW_WRITE(regs, RTW_PHYCFG, RTW_PHYCFG_MAC_POLL | reg);

sys/dev/ic/rtwphyio.c

319

uint32_t reg;

sys/dev/ic/rtwphyio.c

326

reg = rtw_grf5101_mac_crypt(addr, val);

sys/dev/ic/rtwphyio.c

329

reg = rtw_maxim_swizzle(addr, val);

sys/dev/ic/rtwphyio.c

338

reg = __SHIFTIN(addr, RTW_PHYCFG_MAC_PHILIPS_ADDR_MASK) |

sys/dev/ic/rtwphyio.c

346

reg |= RTW_PHYCFG_MAC_RFTYPE_RFMD;

sys/dev/ic/rtwphyio.c

349

reg |= RTW_PHYCFG_MAC_RFTYPE_INTERSIL;

sys/dev/ic/rtwphyio.c

352

reg |= RTW_PHYCFG_MAC_RFTYPE_PHILIPS;

sys/dev/ic/rtwphyio.c

359

return rtw_rf_macbangbits(regs, reg);

sys/dev/ic/rtwreg.h

988

#define RTW_ISSET(regs, reg, mask) \

sys/dev/ic/rtwreg.h

989

(RTW_READ((regs), (reg)) & (mask))

sys/dev/ic/rtwreg.h

991

#define RTW_CLR(regs, reg, mask) \

sys/dev/ic/rtwreg.h

992

RTW_WRITE((regs), (reg), RTW_READ((regs), (reg)) & ~(mask))

sys/dev/ic/scmd.c

307

scmd_set_view_port(struct scmd_sc *sc, int reg)

sys/dev/ic/scmd.c

310

int loc = reg / SCMD_REG_SIZE;

sys/dev/ic/scmd.c

311

uint8_t vpi2creg = reg % SCMD_REG_SIZE;

sys/dev/ic/scmd.c

315

device_xname(sc->sc_dev), vpi2caddr, vpi2creg, reg));

sys/dev/ic/scmd.c

328

scmd_local_read(struct scmd_sc *sc, uint8_t reg, uint8_t *buf)

sys/dev/ic/scmd.c

330

if (SCMD_IS_HOLE(reg)) {

sys/dev/ic/scmd.c

335

return (*(sc->sc_func_read_register))(sc, reg, buf);

sys/dev/ic/scmd.c

339

scmd_remote_read(struct scmd_sc *sc, int reg, uint8_t *buf)

sys/dev/ic/scmd.c

345

if (SCMD_IS_HOLE(reg % SCMD_REG_SIZE)) {

sys/dev/ic/scmd.c

350

err = scmd_set_view_port(sc, reg);

sys/dev/ic/scmd.c

440

scmd_local_write(struct scmd_sc *sc, uint8_t reg, uint8_t buf)

sys/dev/ic/scmd.c

442

if (SCMD_IS_HOLE(reg))

sys/dev/ic/scmd.c

445

return (*(sc->sc_func_write_register))(sc, reg, buf);

sys/dev/ic/scmd.c

449

scmd_remote_write(struct scmd_sc *sc, int reg, uint8_t buf)

sys/dev/ic/scmd.c

455

if (SCMD_IS_HOLE(reg % SCMD_REG_SIZE)) {

sys/dev/ic/scmd.c

459

err = scmd_set_view_port(sc, reg);

sys/dev/ic/seeq8005.c

114

#define SEEQ_READ16(sc, iot, ioh, reg) \

sys/dev/ic/seeq8005.c

116

(bus_space_read_1((iot), (ioh), (reg)) | \

sys/dev/ic/seeq8005.c

117

(bus_space_read_1((iot), (ioh), (reg) + 1) << 8)) : \

sys/dev/ic/seeq8005.c

118

(bus_space_read_2((iot), (ioh), (reg))))

sys/dev/ic/seeq8005.c

120

#define SEEQ_WRITE16(sc, iot, ioh, reg, val) do { \

sys/dev/ic/seeq8005.c

122

bus_space_write_1((iot), (ioh), (reg), (val) & 0xff); \

sys/dev/ic/seeq8005.c

123

bus_space_write_1((iot), (ioh), (reg) + 1, (val) >> 8); \

sys/dev/ic/seeq8005.c

125

bus_space_write_2((iot), (ioh), (reg), (val)); \

sys/dev/ic/sgec.c

654

int j, idx, reg;

sys/dev/ic/sgec.c

701

reg = ZE_RCSR(ZE_CSR6);

sys/dev/ic/sgec.c

703

ZE_WCSR(ZE_CSR6, reg & ~ZE_NICSR6_SR); /* Stop rx */

sys/dev/ic/sgec.c

704

reg &= ~ZE_NICSR6_AF;

sys/dev/ic/sgec.c

706

reg |= ZE_NICSR6_AF_PROM;

sys/dev/ic/sgec.c

708

reg |= ZE_NICSR6_AF_ALLM;

sys/dev/ic/sgec.c

710

ZE_WCSR(ZE_CSR6, reg);

sys/dev/ic/sgec.c

759

int reg, i;

sys/dev/ic/sgec.c

773

reg = ZE_NICSR0_IPL14 | sc->sc_intvec | 0x1fff0003; /* SYNC/ASYNC??? */

sys/dev/ic/sgec.c

781

ZE_WCSR(ZE_CSR0, reg);

sys/dev/ic/sgec.c

782

} while (ZE_RCSR(ZE_CSR0) != reg);

sys/dev/ic/siisatavar.h

107

#define GRREAD(sc, reg) bus_space_read_4((sc)->sc_grt, (sc)->sc_grh, (reg))

sys/dev/ic/siisatavar.h

108

#define GRWRITE(sc, reg, val) bus_space_write_4((sc)->sc_grt, (sc)->sc_grh, (reg), (val))

sys/dev/ic/siisatavar.h

109

#define PRREAD(sc, reg) bus_space_read_4((sc)->sc_prt, (sc)->sc_prh, (reg))

sys/dev/ic/siisatavar.h

110

#define PRWRITE(sc, reg, val) bus_space_write_4((sc)->sc_prt, (sc)->sc_prh, (reg), (val))

sys/dev/ic/smc83c170.c

1077

uint32_t reg;

sys/dev/ic/smc83c170.c

1094

reg = bus_space_read_4(st, sh, EPIC_GENCTL);

sys/dev/ic/smc83c170.c

1095

bus_space_write_4(st, sh, EPIC_GENCTL, reg & ~GENCTL_INTENA);

sys/dev/ic/smc83c170.c

1134

uint16_t reg;

sys/dev/ic/smc83c170.c

1155

reg = EECTL_ENABLE | EECTL_EECS;

sys/dev/ic/smc83c170.c

1157

reg |= EECTL_EEDI;

sys/dev/ic/smc83c170.c

1158

bus_space_write_4(st, sh, EPIC_EECTL, reg);

sys/dev/ic/smc83c170.c

1160

bus_space_write_4(st, sh, EPIC_EECTL, reg |EECTL_EESK);

sys/dev/ic/smc83c170.c

1162

bus_space_write_4(st, sh, EPIC_EECTL, reg);

sys/dev/ic/smc83c170.c

1168

reg = EECTL_ENABLE | EECTL_EECS;

sys/dev/ic/smc83c170.c

1170

reg |= EECTL_EEDI;

sys/dev/ic/smc83c170.c

1171

bus_space_write_4(st, sh, EPIC_EECTL, reg);

sys/dev/ic/smc83c170.c

1173

bus_space_write_4(st, sh, EPIC_EECTL, reg |EECTL_EESK);

sys/dev/ic/smc83c170.c

1175

bus_space_write_4(st, sh, EPIC_EECTL, reg);

sys/dev/ic/smc83c170.c

1180

reg = EECTL_ENABLE | EECTL_EECS;

sys/dev/ic/smc83c170.c

1183

bus_space_write_4(st, sh, EPIC_EECTL, reg |EECTL_EESK);

sys/dev/ic/smc83c170.c

1187

bus_space_write_4(st, sh, EPIC_EECTL, reg);

sys/dev/ic/smc83c170.c

1346

epic_mii_read(device_t self, int phy, int reg, uint16_t *val)

sys/dev/ic/smc83c170.c

1355

MMCTL_ARG(phy, reg, MMCTL_READ));

sys/dev/ic/smc83c170.c

1369

epic_mii_write(device_t self, int phy, int reg, uint16_t val)

sys/dev/ic/smc83c170.c

1379

MMCTL_ARG(phy, reg, MMCTL_WRITE));

sys/dev/ic/smc83c170reg.h

273

#define MMCTL_ARG(phy, reg, cmd) (((phy) << 9) | ((reg) << 4) | (cmd))

sys/dev/ic/smc91cxx.c

1419

smc91cxx_mii_readreg(device_t self, int phy, int reg, uint16_t *val)

sys/dev/ic/smc91cxx.c

1426

rv = mii_bitbang_readreg(self, &smc91cxx_mii_bitbang_ops, phy, reg,

sys/dev/ic/smc91cxx.c

1435

smc91cxx_mii_writereg(device_t self, int phy, int reg, uint16_t val)

sys/dev/ic/smc91cxx.c

1442

rv = mii_bitbang_writereg(self, &smc91cxx_mii_bitbang_ops, phy, reg,

sys/dev/ic/sunscpalvar.h

60

#define SUNSCPAL_READ_1(sc, reg) bus_space_read_1(sc->sunscpal_regt, \

sys/dev/ic/sunscpalvar.h

61

sc->sunscpal_regh, sc->reg)

sys/dev/ic/sunscpalvar.h

62

#define SUNSCPAL_WRITE_1(sc, reg, val) bus_space_write_1(sc->sunscpal_regt, \

sys/dev/ic/sunscpalvar.h

63

sc->sunscpal_regh, sc->reg, val)

sys/dev/ic/sunscpalvar.h

64

#define SUNSCPAL_READ_2(sc, reg) bus_space_read_2(sc->sunscpal_regt, \

sys/dev/ic/sunscpalvar.h

65

sc->sunscpal_regh, sc->reg)

sys/dev/ic/sunscpalvar.h

66

#define SUNSCPAL_WRITE_2(sc, reg, val) bus_space_write_2(sc->sunscpal_regt, \

sys/dev/ic/sunscpalvar.h

67

sc->sunscpal_regh, sc->reg, val)

sys/dev/ic/sunscpalvar.h

70

# define SUNSCPAL_READ_1(sc, reg) (*sc->reg)

sys/dev/ic/sunscpalvar.h

71

# define SUNSCPAL_WRITE_1(sc, reg, val) do { *(sc->reg) = val; } while(0)

sys/dev/ic/tcic2.c

1023

int reg, size2, iotiny, wbase, hwwin, wscnt;

sys/dev/ic/tcic2.c

1050

reg = TCIC_ICTL_ENA | TCIC_ICTL_QUIET;

sys/dev/ic/tcic2.c

1051

reg |= (h->sock << TCIC_ICTL_SS_SHIFT) & TCIC_ICTL_SS_MASK;

sys/dev/ic/tcic2.c

1052

reg |= iotiny | tcic_iowidth_map[h->io[win].width];

sys/dev/ic/tcic2.c

1054

reg |= TCIC_ICTL_PASS16;

sys/dev/ic/tcic2.c

1060

reg |= wscnt & TCIC_ICTL_WSCNT_MASK;

sys/dev/ic/tcic2.c

1061

tcic_write_ind_2(h, TCIC_WR_ICTL_N(hwwin), reg);

sys/dev/ic/tcic2.c

1145

int reg, win;

sys/dev/ic/tcic2.c

1155

reg = tcic_read_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK);

sys/dev/ic/tcic2.c

1156

reg |= TCIC_ILOCK_CWAIT;

sys/dev/ic/tcic2.c

1157

reg &= ~(TCIC_ILOCK_CRESET|TCIC_ILOCK_CRESENA);

sys/dev/ic/tcic2.c

1158

tcic_write_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK, reg);

sys/dev/ic/tcic2.c

1176

reg = TCIC_PWR_VCC_N(h->sock) | TCIC_PWR_VPP_N(h->sock) | h->sc->pwrena;

sys/dev/ic/tcic2.c

1178

reg |= TCIC_PWR_VCC5V;

sys/dev/ic/tcic2.c

1179

tcic_write_1(h, TCIC_R_PWR, reg);

sys/dev/ic/tcic2.c

1183

reg = tcic_read_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK);

sys/dev/ic/tcic2.c

1184

reg |= TCIC_ILOCK_CRESENA;

sys/dev/ic/tcic2.c

1185

tcic_write_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK, reg);

sys/dev/ic/tcic2.c

1187

reg |= TCIC_ILOCK_CRESET;

sys/dev/ic/tcic2.c

1188

tcic_write_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK, reg);

sys/dev/ic/tcic2.c

1194

reg = tcic_read_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK);

sys/dev/ic/tcic2.c

1195

reg &= ~(TCIC_ILOCK_CRESET);

sys/dev/ic/tcic2.c

1196

tcic_write_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK, reg);

sys/dev/ic/tcic2.c

1221

int reg;

sys/dev/ic/tcic2.c

1227

reg = 0;

sys/dev/ic/tcic2.c

1229

reg |= TCIC_SCF1_IOSTS;

sys/dev/ic/tcic2.c

1230

reg |= tcic_irqmap[h->ih_irq]; /* enable interrupts */

sys/dev/ic/tcic2.c

1232

tcic_write_ind_2(h, TCIC_IR_SCF1_N(h->sock), reg);

sys/dev/ic/tcic2.c

1236

((type == PCMCIA_IFTYPE_IO) ? "io" : "mem"), reg));

sys/dev/ic/tcic2.c

309

int i, reg;

sys/dev/ic/tcic2.c

324

reg = TCIC_WAIT_SYNC | TCIC_WAIT_CCLK | TCIC_WAIT_RISING;

sys/dev/ic/tcic2.c

325

reg |= (tcic_ns2wscnt(250) & TCIC_WAIT_COUNT_MASK);

sys/dev/ic/tcic2.c

326

tcic_write_aux_1(sc->iot, sc->ioh, TCIC_AR_WCTL, TCIC_R_WCTL_WAIT, reg);

sys/dev/ic/tcic2.c

327

reg = TCIC_SYSCFG_MPSEL_RI | TCIC_SYSCFG_MCSFULL;

sys/dev/ic/tcic2.c

328

tcic_write_aux_2(sc->iot, sc->ioh, TCIC_AR_SYSCFG, reg);

sys/dev/ic/tcic2.c

329

reg = tcic_read_aux_2(sc->iot, sc->ioh, TCIC_AR_ILOCK);

sys/dev/ic/tcic2.c

330

reg |= TCIC_ILOCK_HOLD_CCLK;

sys/dev/ic/tcic2.c

331

tcic_write_aux_2(sc->iot, sc->ioh, TCIC_AR_ILOCK, reg);

sys/dev/ic/tcic2.c

344

reg = tcic_read_1(&sc->handle[0], TCIC_R_IENA);

sys/dev/ic/tcic2.c

346

(reg & ~TCIC_IENA_CFG_MASK) | TCIC_IENA_CFG_HIGH);

sys/dev/ic/tcic2.c

347

reg = tcic_read_aux_2(sc->iot, sc->ioh, TCIC_AR_SYSCFG);

sys/dev/ic/tcic2.c

349

(reg & ~TCIC_SYSCFG_IRQ_MASK) | tcic_irqmap[sc->irq]);

sys/dev/ic/tcic2.c

365

reg = tcic_read_aux_2(sc->iot, sc->ioh, TCIC_AR_SYSCFG);

sys/dev/ic/tcic2.c

366

reg &= ~TCIC_SYSCFG_AUTOBUSY;

sys/dev/ic/tcic2.c

367

tcic_write_aux_2(sc->iot, sc->ioh, TCIC_AR_SYSCFG, reg);

sys/dev/ic/tcic2.c

500

int reg;

sys/dev/ic/tcic2.c

506

reg = tcic_read_ind_2(h, TCIC_IR_SCF2_N(h->sock));

sys/dev/ic/tcic2.c

507

tcic_write_ind_2(h, TCIC_IR_SCF2_N(h->sock), reg & ~TCIC_SCF2_MCD);

sys/dev/ic/tcic2.c

510

reg = tcic_read_2(h, TCIC_R_IENA);

sys/dev/ic/tcic2.c

511

tcic_write_2(h, TCIC_R_IENA, reg |= TCIC_IENA_CDCHG);

sys/dev/ic/tcic2.c

514

h->sstat = reg = tcic_read_1(h, TCIC_R_SSTAT) & TCIC_SSTAT_STAT_MASK;

sys/dev/ic/tcic2.c

515

if (reg & TCIC_SSTAT_CD)

sys/dev/ic/tcic2.c

681

int val, reg;

sys/dev/ic/tcic2.c

699

reg = TCIC_IR_SCF1_N(h->sock);

sys/dev/ic/tcic2.c

700

val = tcic_read_ind_2(h, reg);

sys/dev/ic/tcic2.c

701

tcic_write_ind_2(h, reg, (val & ~TCIC_SCF1_IRQ_MASK)|TCIC_SCF1_IRQOFF);

sys/dev/ic/tcic2.c

702

reg = TCIC_IR_SCF2_N(h->sock);

sys/dev/ic/tcic2.c

703

val = tcic_read_ind_2(h, reg);

sys/dev/ic/tcic2.c

704

tcic_write_ind_2(h, reg,

sys/dev/ic/tcic2.c

785

int reg, hwwin, wscnt;

sys/dev/ic/tcic2.c

803

reg = ((h->mem[win].addr >> TCIC_MEM_SHIFT) &

sys/dev/ic/tcic2.c

806

reg = ((h->mem[win].addr >> TCIC_MEM_SHIFT) &

sys/dev/ic/tcic2.c

809

tcic_write_ind_2(h, TCIC_WR_MBASE_N(hwwin), reg);

sys/dev/ic/tcic2.c

812

reg = 0;

sys/dev/ic/tcic2.c

813

reg = ((h->mem[win].offset >> TCIC_MEM_SHIFT) & TCIC_MMAP_ADDR_MASK);

sys/dev/ic/tcic2.c

814

reg |= (kind == PCMCIA_MEM_ATTR) ? TCIC_MMAP_ATTR : 0;

sys/dev/ic/tcic2.c

816

win, hwwin, reg));

sys/dev/ic/tcic2.c

817

tcic_write_ind_2(h, TCIC_WR_MMAP_N(hwwin), reg);

sys/dev/ic/tcic2.c

822

reg = tcic_read_ind_2(h, TCIC_WR_MCTL_N(hwwin)) & TCIC_MCTL_WSCNT_MASK;

sys/dev/ic/tcic2.c

823

reg |= TCIC_MCTL_ENA|TCIC_MCTL_QUIET;

sys/dev/ic/tcic2.c

824

reg |= mem8 ? TCIC_MCTL_B8 : 0;

sys/dev/ic/tcic2.c

825

reg |= (h->sock << TCIC_MCTL_SS_SHIFT) & TCIC_MCTL_SS_MASK;

sys/dev/ic/tcic2.c

842

reg |= wscnt & TCIC_MCTL_WSCNT_MASK;

sys/dev/ic/tcic2.c

844

tcic_write_ind_2(h, TCIC_WR_MCTL_N(hwwin), reg);

sys/dev/ic/tcic2var.h

187

tcic_read_1(struct tcic_handle *h, int reg)

sys/dev/ic/tcic2var.h

189

return (bus_space_read_1(h->sc->iot, h->sc->ioh, reg));

sys/dev/ic/tcic2var.h

194

tcic_read_2(struct tcic_handle *h, int reg)

sys/dev/ic/tcic2var.h

196

return (bus_space_read_2(h->sc->iot, h->sc->ioh, reg));

sys/dev/ic/tcic2var.h

201

tcic_read_4(struct tcic_handle *h, int reg)

sys/dev/ic/tcic2var.h

204

val = bus_space_read_2(h->sc->iot, h->sc->ioh, reg);

sys/dev/ic/tcic2var.h

205

val |= bus_space_read_2(h->sc->iot, h->sc->ioh, reg+2) << 16;

sys/dev/ic/tcic2var.h

211

tcic_write_1(struct tcic_handle *h, int reg, int data)

sys/dev/ic/tcic2var.h

213

bus_space_write_1(h->sc->iot, h->sc->ioh, reg, (data));

sys/dev/ic/tcic2var.h

218

tcic_write_2(struct tcic_handle *h, int reg, int data)

sys/dev/ic/tcic2var.h

220

bus_space_write_2(h->sc->iot, h->sc->ioh, reg, (data));

sys/dev/ic/tcic2var.h

225

tcic_write_4(struct tcic_handle *h, int reg, int data)

sys/dev/ic/tcic2var.h

227

bus_space_write_2(h->sc->iot, h->sc->ioh, reg, (data));

sys/dev/ic/tcic2var.h

228

bus_space_write_2(h->sc->iot, h->sc->ioh, reg+2, (data)>>16);

sys/dev/ic/tcic2var.h

233

tcic_read_ind_2(struct tcic_handle *h, int reg)

sys/dev/ic/tcic2var.h

237

tcic_write_4(h, TCIC_R_ADDR, reg|TCIC_ADDR_INDREG);

sys/dev/ic/tcic2var.h

245

tcic_write_ind_2(struct tcic_handle *h, int reg, int data)

sys/dev/ic/tcic2var.h

249

tcic_write_4(h, TCIC_R_ADDR, reg|TCIC_ADDR_INDREG);

sys/dev/ic/tcic2var.h

284

tcic_read_aux_1(bus_space_tag_t iot, bus_space_handle_t ioh, int auxreg, int reg)

sys/dev/ic/tcic2var.h

289

val = bus_space_read_1(iot, ioh, reg);

sys/dev/ic/tcic2var.h

306

tcic_write_aux_1(bus_space_tag_t iot, bus_space_handle_t ioh, int auxreg, int reg, int val)

sys/dev/ic/tcic2var.h

311

bus_space_write_1(iot, ioh, reg, val);

sys/dev/ic/tea5757.c

107

u_int32_t reg;

sys/dev/ic/tea5757.c

110

reg = stereo | lock | TEA5757_SEARCH_START;

sys/dev/ic/tea5757.c

111

reg |= dir ? TEA5757_SEARCH_UP : TEA5757_SEARCH_DOWN;

sys/dev/ic/tea5757.c

112

tea5757_hardware_write(tea, reg);

sys/dev/ic/tea5757.c

118

reg = tea->read(tea->iot, tea->ioh, tea->offset);

sys/dev/ic/tea5757.c

119

} while ((reg & TEA5757_FREQ) == 0 && ++co < 200);

sys/dev/ic/tpm.c

456

uint8_t reg;

sys/dev/ic/tpm.c

470

while ((reg = bus_space_read_1(bt, bh, TPM_ACCESS) &

sys/dev/ic/tpm.c

475

if ((reg & (TPM_ACCESS_VALID | TPM_ACCESS_ACTIVE_LOCALITY)) !=

sys/dev/ic/tulip.c

1877

uint32_t reg;

sys/dev/ic/tulip.c

1880

reg = enaddr[0] |

sys/dev/ic/tulip.c

1884

bus_space_write_4(sc->sc_st, sc->sc_sh, CSR_ADM_PAR0, reg);

sys/dev/ic/tulip.c

1886

reg = enaddr[4] |

sys/dev/ic/tulip.c

1888

bus_space_write_4(sc->sc_st, sc->sc_sh, CSR_ADM_PAR1, reg);

sys/dev/ic/tulip.c

1895

uint32_t reg;

sys/dev/ic/tulip.c

1898

reg = enaddr[0] |

sys/dev/ic/tulip.c

1903

TULIP_WRITE(sc, CSR_AX_FILTDATA, reg);

sys/dev/ic/tulip.c

1905

reg = enaddr[4] | (enaddr[5] << 8);

sys/dev/ic/tulip.c

1907

TULIP_WRITE(sc, CSR_AX_FILTDATA, reg);

sys/dev/ic/tulip.c

3370

tlp_bitbang_mii_readreg(device_t self, int phy, int reg, uint16_t *val)

sys/dev/ic/tulip.c

3374

return mii_bitbang_readreg(self, sc->sc_bitbang_ops, phy, reg, val);

sys/dev/ic/tulip.c

3383

tlp_bitbang_mii_writereg(device_t self, int phy, int reg, uint16_t val)

sys/dev/ic/tulip.c

3387

return mii_bitbang_writereg(self, sc->sc_bitbang_ops, phy, reg, val);

sys/dev/ic/tulip.c

3422

tlp_pnic_mii_readreg(device_t self, int phy, int reg, uint16_t *val)

sys/dev/ic/tulip.c

3431

(reg << PNIC_MII_REGSHIFT));

sys/dev/ic/tulip.c

3455

tlp_pnic_mii_writereg(device_t self, int phy, int reg, uint16_t val)

sys/dev/ic/tulip.c

3463

(reg << PNIC_MII_REGSHIFT) | val);

sys/dev/ic/tulip.c

3497

tlp_al981_mii_readreg(device_t self, int phy, int reg, uint16_t *val)

sys/dev/ic/tulip.c

3505

if (reg >= tlp_al981_phy_regmap_size)

sys/dev/ic/tulip.c

3509

tlp_al981_phy_regmap[reg]) & 0xffff;

sys/dev/ic/tulip.c

3519

tlp_al981_mii_writereg(device_t self, int phy, int reg, uint16_t val)

sys/dev/ic/tulip.c

3527

if (reg >= tlp_al981_phy_regmap_size)

sys/dev/ic/tulip.c

3531

tlp_al981_phy_regmap[reg], val);

sys/dev/ic/tulip.c

5747

uint32_t reg;

sys/dev/ic/tulip.c

5756

reg = TULIP_READ(sc, CSR_PNIC_NWAY);

sys/dev/ic/tulip.c

5757

if (reg & PNIC_NWAY_LPAR_MASK) {

sys/dev/ic/tulip.c

5764

if ((reg & PNIC_NWAY_LPAR_MASK) == 0)

sys/dev/ic/tulip.c

5802

if ((reg & PNIC_NWAY_LPAR_MASK) == 0)

sys/dev/ic/tulip.c

5818

uint32_t reg;

sys/dev/ic/tulip.c

5823

reg = TULIP_READ(sc, CSR_PNIC_NWAY);

sys/dev/ic/tulip.c

5828

if (reg & PNIC_NWAY_NW) {

sys/dev/ic/tulip.c

5829

if ((reg & PNIC_NWAY_LPAR_MASK) == 0) {

sys/dev/ic/tulip.c

5836

if (reg & PNIC_NWAY_LPAR100T4)

sys/dev/ic/tulip.c

5840

if (reg & PNIC_NWAY_LPAR100TXFDX)

sys/dev/ic/tulip.c

5842

else if (reg & PNIC_NWAY_LPAR100TX)

sys/dev/ic/tulip.c

5844

else if (reg & PNIC_NWAY_LPAR10TFDX)

sys/dev/ic/tulip.c

5846

else if (reg & PNIC_NWAY_LPAR10T)

sys/dev/ic/tulip.c

5851

if (reg & PNIC_NWAY_100)

sys/dev/ic/tulip.c

5855

if (reg & PNIC_NWAY_FD)

sys/dev/ic/tulip.c

5863

uint32_t reg;

sys/dev/ic/tulip.c

5865

reg = TULIP_READ(sc, CSR_PNIC_NWAY);

sys/dev/ic/tulip.c

5866

reg &= ~(PNIC_NWAY_FD | PNIC_NWAY_100 | PNIC_NWAY_RN);

sys/dev/ic/tulip.c

5868

if (reg & (PNIC_NWAY_LPAR100TXFDX | PNIC_NWAY_LPAR100TX))

sys/dev/ic/tulip.c

5869

reg |= PNIC_NWAY_100;

sys/dev/ic/tulip.c

5870

if (reg & (PNIC_NWAY_LPAR10TFDX | PNIC_NWAY_LPAR100TXFDX))

sys/dev/ic/tulip.c

5871

reg |= PNIC_NWAY_FD;

sys/dev/ic/tulip.c

5873

TULIP_WRITE(sc, CSR_PNIC_NWAY, reg);

sys/dev/ic/tulipvar.h

547

#define TULIP_READ(sc, reg) \

sys/dev/ic/tulipvar.h

549

TULIP_CSR_OFFSET((sc), (reg)))

sys/dev/ic/tulipvar.h

551

#define TULIP_WRITE(sc, reg, val) \

sys/dev/ic/tulipvar.h

553

TULIP_CSR_OFFSET((sc), (reg)), (val))

sys/dev/ic/tulipvar.h

555

#define TULIP_SET(sc, reg, mask) \

sys/dev/ic/tulipvar.h

556

TULIP_WRITE((sc), (reg), TULIP_READ((sc), (reg)) | (mask))

sys/dev/ic/tulipvar.h

558

#define TULIP_CLR(sc, reg, mask) \

sys/dev/ic/tulipvar.h

559

TULIP_WRITE((sc), (reg), TULIP_READ((sc), (reg)) & ~(mask))

sys/dev/ic/tulipvar.h

561

#define TULIP_ISSET(sc, reg, mask) \

sys/dev/ic/tulipvar.h

562

(TULIP_READ((sc), (reg)) & (mask))

sys/dev/ic/vga_subr.c

223

uint8_t reg;

sys/dev/ic/vga_subr.c

228

reg = vga_raw_read(vh, VGA_MISC_DATAR);

sys/dev/ic/vga_subr.c

229

vh->vh_mono = !(reg & 0x01);

sys/dev/ic/vgavar.h

105

_vga_attr_read(struct vga_handle *vh, int reg)

sys/dev/ic/vgavar.h

112

vga_raw_write(vh, VGA_ATC_INDEX, reg);

sys/dev/ic/vgavar.h

124

_vga_attr_write(struct vga_handle *vh, int reg, u_int8_t val)

sys/dev/ic/vgavar.h

129

vga_raw_write(vh, VGA_ATC_INDEX, reg);

sys/dev/ic/vgavar.h

139

_vga_ts_read(struct vga_handle *vh, int reg)

sys/dev/ic/vgavar.h

142

vga_raw_write(vh, VGA_TS_INDEX, reg);

sys/dev/ic/vgavar.h

147

_vga_ts_write(struct vga_handle *vh, int reg, u_int8_t val)

sys/dev/ic/vgavar.h

150

vga_raw_write(vh, VGA_TS_INDEX, reg);

sys/dev/ic/vgavar.h

155

_vga_gdc_read(struct vga_handle *vh, int reg)

sys/dev/ic/vgavar.h

158

vga_raw_write(vh, VGA_GDC_INDEX, reg);

sys/dev/ic/vgavar.h

163

_vga_gdc_write(struct vga_handle *vh, int reg, u_int8_t val)

sys/dev/ic/vgavar.h

166

vga_raw_write(vh, VGA_GDC_INDEX, reg);

sys/dev/ic/vgavar.h

170

#define vga_attr_read(vh, reg) \

sys/dev/ic/vgavar.h

171

_vga_attr_read(vh, offsetof(struct reg_vgaattr, reg))

sys/dev/ic/vgavar.h

172

#define vga_attr_write(vh, reg, val) \

sys/dev/ic/vgavar.h

173

_vga_attr_write(vh, offsetof(struct reg_vgaattr, reg), val)

sys/dev/ic/vgavar.h

174

#define vga_ts_read(vh, reg) \

sys/dev/ic/vgavar.h

175

_vga_ts_read(vh, offsetof(struct reg_vgats, reg))

sys/dev/ic/vgavar.h

176

#define vga_ts_write(vh, reg, val) \

sys/dev/ic/vgavar.h

177

_vga_ts_write(vh, offsetof(struct reg_vgats, reg), val)

sys/dev/ic/vgavar.h

178

#define vga_gdc_read(vh, reg) \

sys/dev/ic/vgavar.h

179

_vga_gdc_read(vh, offsetof(struct reg_vgagdc, reg))

sys/dev/ic/vgavar.h

180

#define vga_gdc_write(vh, reg, val) \

sys/dev/ic/vgavar.h

181

_vga_gdc_write(vh, offsetof(struct reg_vgagdc, reg), val)

sys/dev/ic/vgavar.h

183

#define vga_6845_read(vh, reg) \

sys/dev/ic/vgavar.h

184

pcdisplay_6845_read(&(vh)->vh_ph, reg)

sys/dev/ic/vgavar.h

185

#define vga_6845_write(vh, reg, val) \

sys/dev/ic/vgavar.h

186

pcdisplay_6845_write(&(vh)->vh_ph, reg, val)

sys/dev/ic/vgavar.h

187

#define _vga_6845_read(vh, reg) \

sys/dev/ic/vgavar.h

188

_pcdisplay_6845_read(&(vh)->vh_ph, reg)

sys/dev/ic/vgavar.h

189

#define _vga_6845_write(vh, reg, val) \

sys/dev/ic/vgavar.h

190

_pcdisplay_6845_write(&(vh)->vh_ph, reg, val)

sys/dev/ic/vgavar.h

93

#define vga_raw_read(vh, reg) \

sys/dev/ic/vgavar.h

94

bus_space_read_1(vh->vh_iot, vh->vh_ioh_vga, reg)

sys/dev/ic/vgavar.h

95

#define vga_raw_write(vh, reg, value) \

sys/dev/ic/vgavar.h

96

bus_space_write_1(vh->vh_iot, vh->vh_ioh_vga, reg, value)

sys/dev/ic/w83l518d.c

47

wb_idx_read(struct wb_softc *wb, uint8_t reg)

sys/dev/ic/w83l518d.c

49

bus_space_write_1(wb->wb_iot, wb->wb_ioh, WB_SD_INDEX, reg);

sys/dev/ic/w83l518d.c

54

wb_idx_write(struct wb_softc *wb, uint8_t reg, uint8_t val)

sys/dev/ic/w83l518d.c

56

bus_space_write_1(wb->wb_iot, wb->wb_ioh, WB_SD_INDEX, reg);

sys/dev/ic/w83l518d.c

61

wb_read(struct wb_softc *wb, uint8_t reg)

sys/dev/ic/w83l518d.c

63

return bus_space_read_1(wb->wb_iot, wb->wb_ioh, reg);

sys/dev/ic/w83l518d.c

67

wb_write(struct wb_softc *wb, uint8_t reg, uint8_t val)

sys/dev/ic/w83l518d.c

69

bus_space_write_1(wb->wb_iot, wb->wb_ioh, reg, val);

sys/dev/ic/wd33c93.c

295

u_char csr, reg;

sys/dev/ic/wd33c93.c

331

GET_SBIC_queue_tag(sc, reg);

sys/dev/ic/wd33c93.c

332

sc->sc_chip = (reg == 0x55) ?

sys/dev/ic/wd33c93reg.h

360

#define SCSI_PHASE(reg) ((reg) & PHASE_MASK)

sys/dev/ic/wivar.h

230

#define CSR_WRITE_4(sc, reg, val) \

sys/dev/ic/wivar.h

232

(sc->sc_pci? reg * 2: reg) , htole32(val))

sys/dev/ic/wivar.h

233

#define CSR_WRITE_2(sc, reg, val) \

sys/dev/ic/wivar.h

235

(sc->sc_pci? reg * 2: reg), htole16(val))

sys/dev/ic/wivar.h

236

#define CSR_WRITE_1(sc, reg, val) \

sys/dev/ic/wivar.h

238

(sc->sc_pci? reg * 2: reg), val)

sys/dev/ic/wivar.h

240

#define CSR_READ_4(sc, reg) \

sys/dev/ic/wivar.h

242

(sc->sc_pci? reg * 2: reg)))

sys/dev/ic/wivar.h

243

#define CSR_READ_2(sc, reg) \

sys/dev/ic/wivar.h

245

(sc->sc_pci? reg * 2: reg)))

sys/dev/ic/wivar.h

246

#define CSR_READ_1(sc, reg) \

sys/dev/ic/wivar.h

248

(sc->sc_pci? reg * 2: reg))

sys/dev/ic/wivar.h

252

#define CSR_WRITE_4(sc, reg, val) \

sys/dev/ic/wivar.h

254

(sc->sc_pci? reg * 2: reg) , val)

sys/dev/ic/wivar.h

255

#define CSR_WRITE_2(sc, reg, val) \

sys/dev/ic/wivar.h

257

(sc->sc_pci? reg * 2: reg), val)

sys/dev/ic/wivar.h

258

#define CSR_WRITE_1(sc, reg, val) \

sys/dev/ic/wivar.h

260

(sc->sc_pci? reg * 2: reg), val)

sys/dev/ic/wivar.h

262

#define CSR_READ_4(sc, reg) \

sys/dev/ic/wivar.h

264

(sc->sc_pci? reg * 2: reg))

sys/dev/ic/wivar.h

265

#define CSR_READ_2(sc, reg) \

sys/dev/ic/wivar.h

267

(sc->sc_pci? reg * 2: reg))

sys/dev/ic/wivar.h

268

#define CSR_READ_1(sc, reg) \

sys/dev/ic/wivar.h

270

(sc->sc_pci? reg * 2: reg))

sys/dev/ic/wivar.h

280

#define CSR_WRITE_STREAM_2(sc, reg, val) \

sys/dev/ic/wivar.h

282

(sc->sc_pci? reg * 2: reg), val)

sys/dev/ic/wivar.h

283

#define CSR_WRITE_MULTI_STREAM_2(sc, reg, val, count) \

sys/dev/ic/wivar.h

285

(sc->sc_pci? reg * 2: reg), val, count)

sys/dev/ic/wivar.h

286

#define CSR_READ_STREAM_2(sc, reg) \

sys/dev/ic/wivar.h

288

(sc->sc_pci? reg * 2: reg))

sys/dev/ic/wivar.h

289

#define CSR_READ_MULTI_STREAM_2(sc, reg, buf, count) \

sys/dev/ic/wivar.h

291

(sc->sc_pci? reg * 2: reg), buf, count)

sys/dev/ic/z8530sc.c

169

uint8_t *reg, v;

sys/dev/ic/z8530sc.c

192

reg = cs->cs_creg; /* current regs */

sys/dev/ic/z8530sc.c

195

zs_write_reg(cs, 1, reg[1] & ~ZSWR1_IMASK);

sys/dev/ic/z8530sc.c

198

zs_write_reg(cs, 4, reg[4]);

sys/dev/ic/z8530sc.c

201

zs_write_reg(cs, 10, reg[10]);

sys/dev/ic/z8530sc.c

204

zs_write_reg(cs, 3, reg[3] & ~ZSWR3_RX_ENABLE);

sys/dev/ic/z8530sc.c

205

zs_write_reg(cs, 5, reg[5] & ~ZSWR5_TX_ENABLE);

sys/dev/ic/z8530sc.c

208

zs_write_reg(cs, 6, reg[6]);

sys/dev/ic/z8530sc.c

209

zs_write_reg(cs, 7, reg[7]);

sys/dev/ic/z8530sc.c

220

zs_write_reg(cs, 2, reg[2]);

sys/dev/ic/z8530sc.c

222

zs_write_reg(cs, 9, reg[9]);

sys/dev/ic/z8530sc.c

226

zs_write_reg(cs, 14, reg[14] & ~ZSWR14_BAUD_ENA);

sys/dev/ic/z8530sc.c

234

zs_write_reg(cs, 11, reg[11]);

sys/dev/ic/z8530sc.c

237

zs_write_reg(cs, 12, reg[12]);

sys/dev/ic/z8530sc.c

238

zs_write_reg(cs, 13, reg[13]);

sys/dev/ic/z8530sc.c

241

zs_write_reg(cs, 14, reg[14]);

sys/dev/ic/z8530sc.c

244

zs_write_reg(cs, 15, reg[15]);

sys/dev/ic/z8530sc.c

256

zs_write_reg(cs, 3, reg[3]);

sys/dev/ic/z8530sc.c

257

zs_write_reg(cs, 5, reg[5]);

sys/dev/ic/z8530sc.c

267

zs_write_reg(cs, 1, reg[1]);

sys/dev/ieee1394/firewire.c

1669

struct csrreg *reg;

sys/dev/ieee1394/firewire.c

1679

reg = (struct csrreg *)&fwdev->csrrom[offset / sizeof(uint32_t)];

sys/dev/ieee1394/firewire.c

1680

err = fw_explore_read_quads(fwdev, CSRROMOFF + offset, (uint32_t *)reg,

sys/dev/ieee1394/firewire.c

1695

if ((reg[i].key & CSRTYPE_MASK) == CSRTYPE_D)

sys/dev/ieee1394/firewire.c

1697

else if ((reg[i].key & CSRTYPE_MASK) == CSRTYPE_L)

sys/dev/ieee1394/firewire.c

1702

off = offset + reg[i].val * sizeof(uint32_t);

sys/dev/ieee1394/firewire.c

1979

struct csrreg *reg;

sys/dev/ieee1394/firewire.c

1982

reg = crom_search_key(&cc, CSRKEY_VER);

sys/dev/ieee1394/firewire.c

1983

if (reg == NULL)

sys/dev/ieee1394/firewire.c

1986

switch (reg->val) {

sys/dev/ieee1394/firewire.c

2010

__func__, reg->val);

sys/dev/ieee1394/fwcrom.c

105

ptr->dir = (struct csrdirectory *)(reg + reg->val);

sys/dev/ieee1394/fwcrom.c

132

struct csrreg *reg;

sys/dev/ieee1394/fwcrom.c

135

reg = crom_get(cc);

sys/dev/ieee1394/fwcrom.c

136

if (reg->key == key)

sys/dev/ieee1394/fwcrom.c

137

return reg;

sys/dev/ieee1394/fwcrom.c

146

struct csrreg *reg;

sys/dev/ieee1394/fwcrom.c

153

reg = crom_get(cc);

sys/dev/ieee1394/fwcrom.c

155

if (reg->key == CSRKEY_SPEC && reg->val == spec)

sys/dev/ieee1394/fwcrom.c

160

if (reg->key == CSRKEY_VER && reg->val == ver)

sys/dev/ieee1394/fwcrom.c

173

struct csrreg *reg;

sys/dev/ieee1394/fwcrom.c

182

reg = crom_get(cc);

sys/dev/ieee1394/fwcrom.c

183

switch (reg->key) {

sys/dev/ieee1394/fwcrom.c

188

if ((char *)(reg + reg->val) > CROM_END(cc)) {

sys/dev/ieee1394/fwcrom.c

194

textleaf = (struct csrtext *)(reg + reg->val);

sys/dev/ieee1394/fwcrom.c

290

struct csrreg *reg;

sys/dev/ieee1394/fwcrom.c

296

reg = crom_get(cc);

sys/dev/ieee1394/fwcrom.c

297

switch (reg->key & CSRTYPE_MASK) {

sys/dev/ieee1394/fwcrom.c

300

l += snprintf(buf + l, len - l, "0x%x", reg->val);

sys/dev/ieee1394/fwcrom.c

307

reg->val, reg->val);

sys/dev/ieee1394/fwcrom.c

312

dir = (struct csrdirectory *) (reg + reg->val);

sys/dev/ieee1394/fwcrom.c

327

switch (reg->key) {

sys/dev/ieee1394/fwcrom.c

342

crom_desc_specver(0, reg->val, buf, len);

sys/dev/ieee1394/fwcrom.c

419

struct csrreg reg;

sys/dev/ieee1394/fwcrom.c

423

foo.reg.key = key;

sys/dev/ieee1394/fwcrom.c

424

foo.reg.val = val;

sys/dev/ieee1394/fwcrom.c

510

struct csrreg *reg;

sys/dev/ieee1394/fwcrom.c

513

reg = (struct csrreg *)&parent->data.buf[ref_index];

sys/dev/ieee1394/fwcrom.c

514

reg->val =

sys/dev/ieee1394/fwcrom.c

92

struct csrreg *reg;

sys/dev/ieee1394/fwcrom.c

96

reg = crom_get(cc);

sys/dev/ieee1394/fwcrom.c

97

if ((reg->key & CSRTYPE_MASK) == CSRTYPE_D) {

sys/dev/ieee1394/fwohci.c

1144

uint32_t reg, reg2;

sys/dev/ieee1394/fwohci.c

1157

reg = fwphy_rddata(sc, FW_PHY_SPD_REG);

sys/dev/ieee1394/fwohci.c

1159

if ((reg >> 5) != 7) {

sys/dev/ieee1394/fwohci.c

1161

sc->fc.nport = reg & FW_PHY_NP;

sys/dev/ieee1394/fwohci.c

1162

sc->fc.speed = reg & FW_PHY_SPD >> 6;

sys/dev/ieee1394/fwohci.c

1174

sc->fc.nport = reg & FW_PHY_NP;

sys/dev/ieee1394/fwohci.c

1210

reg = fwphy_rddata(sc, FW_PHY_SPD_REG);

sys/dev/ieee1394/fwohci.c

1211

if ((reg >> 5) == 7) {

sys/dev/ieee1394/fwohci.c

1212

reg = fwphy_rddata(sc, 4);

sys/dev/ieee1394/fwohci.c

1213

reg |= 1 << 6;

sys/dev/ieee1394/fwohci.c

1214

fwphy_wrdata(sc, 4, reg);

sys/dev/ieee1394/fwohci.c

1215

reg = fwphy_rddata(sc, 4);

sys/dev/ieee1394/fwohci.c

1224

uint32_t reg, reg2;

sys/dev/ieee1394/fwohci.c

1259

reg = OREAD(sc, OHCI_BUS_OPT);

sys/dev/ieee1394/fwohci.c

1260

reg2 = reg | OHCI_BUSFNC;

sys/dev/ieee1394/fwohci.c

1261

max_rec = (reg & 0x0000f000) >> 12;

sys/dev/ieee1394/fwohci.c

1262

speed = (reg & 0x00000007);

sys/dev/ieee1394/fwohci.c

1273

printf("BUS_OPT 0x%x -> 0x%x\n", reg, reg2);

sys/dev/ieee1394/fwohci.c

402

uint32_t reg;

sys/dev/ieee1394/fwohci.c

407

reg = OREAD(sc, OHCI_VERSION);

sys/dev/ieee1394/fwohci.c

408

mver = (reg >> 16) & 0xff;

sys/dev/ieee1394/fwohci.c

410

mver, reg & 0xff, (reg >> 24) & 1);

sys/dev/ieee1394/fwohci.c

419

reg = OREAD(sc, OHCI_IT_MASK) & OREAD(sc, OHCI_IR_MASK);

sys/dev/ieee1394/fwohci.c

423

if ((reg & (1 << i)) == 0)

sys/dev/ieee1394/fwohci.c

661

struct fw_reg_req_t *reg = (struct fw_reg_req_t *)data;

sys/dev/ieee1394/fwohci.c

675

if (reg->addr <= OHCI_MAX_REG) {

sys/dev/ieee1394/fwohci.c

676

OWRITE(sc, reg->addr, reg->data);

sys/dev/ieee1394/fwohci.c

677

reg->data = OREAD(sc, reg->addr);

sys/dev/ieee1394/fwohci.c

683

if (reg->addr <= OHCI_MAX_REG)

sys/dev/ieee1394/fwohci.c

684

reg->data = OREAD(sc, reg->addr);

sys/dev/ieee1394/fwohci.c

701

if (reg->addr <= OHCI_MAX_PHY_REG)

sys/dev/ieee1394/fwohci.c

702

reg->data = fwphy_rddata(sc, reg->addr);

sys/dev/ieee1394/fwohci.c

708

if (reg->addr <= OHCI_MAX_PHY_REG)

sys/dev/ieee1394/fwohci.c

709

reg->data = fwphy_wrdata(sc, reg->addr, reg->data);

sys/dev/ieee1394/sbp.c

668

struct csrreg *reg;

sys/dev/ieee1394/sbp.c

678

reg = crom_search_key(&cc, CROM_LUN);

sys/dev/ieee1394/sbp.c

679

if (reg == NULL)

sys/dev/ieee1394/sbp.c

681

lun = reg->val & 0xffff;

sys/dev/ieee1394/sbp.c

736

reg = crom_search_key(&cc, CROM_LUN);

sys/dev/ieee1394/sbp.c

737

if (reg == NULL)

sys/dev/ieee1394/sbp.c

739

lun = reg->val & 0xffff;

sys/dev/ieee1394/sbp.c

773

sdev->type = (reg->val & 0xff0000) >> 16;

sys/dev/ieee1394/sbp.c

825

struct csrreg *reg;

sys/dev/ieee1394/sbp.c

850

reg = crom_search_key(&cc, CROM_MGM);

sys/dev/ieee1394/sbp.c

851

if (reg == NULL || reg->val == 0) {

sys/dev/ieee1394/sbp.c

858

target->mgm_lo = 0xf0000000 | (reg->val << 2);

sys/dev/ieee1394/sbp.c

868

struct csrreg *reg;

sys/dev/ieee1394/sbp.c

880

while ((reg = crom_search_key(cc, CSRKEY_VER)) != NULL) {

sys/dev/ieee1394/sbp.c

881

if (reg->val == CSRVAL_T10SBP2)

sys/dev/ieee1394/sbp.c

886

reg = crom_search_key(cc, CSRKEY_FIRM_VER);

sys/dev/ieee1394/sbp.c

887

if (reg != NULL)

sys/dev/ieee1394/sbp.c

889

reg->val);

sys/dev/ipmi.c

427

bt_read(struct ipmi_softc *sc, int reg)

sys/dev/ipmi.c

429

return bmc_read(sc, reg);

sys/dev/ipmi.c

433

bt_write(struct ipmi_softc *sc, int reg, uint8_t data)

sys/dev/ipmi.c

438

bmc_write(sc, reg, data);

sys/dev/isa/ad1848_isa.c

571

uint8_t reg;

sys/dev/isa/ad1848_isa.c

603

reg = ad_read(sc, SP_INTERFACE_CONFIG);

sys/dev/isa/ad1848_isa.c

604

ad_write(sc, SP_INTERFACE_CONFIG, CAPTURE_ENABLE|reg);

sys/dev/isa/ad1848_isa.c

620

uint8_t reg;

sys/dev/isa/ad1848_isa.c

645

reg = ad_read(sc, SP_INTERFACE_CONFIG);

sys/dev/isa/ad1848_isa.c

646

ad_write(sc, SP_INTERFACE_CONFIG, PLAYBACK_ENABLE|reg);

sys/dev/isa/aztech.c

214

u_int32_t reg;

sys/dev/isa/aztech.c

225

reg = lm700x_encode_freq(nfreq, sc->rf);

sys/dev/isa/aztech.c

226

reg |= sc->stereo | sc->rf | LM700X_DIVIDER_FM;

sys/dev/isa/aztech.c

228

lm700x_hardware_write(&sc->lm, reg, vol);

sys/dev/isa/cms.c

226

u_int8_t reg;

sys/dev/isa/cms.c

256

reg = CMS_READ(sc, chip, CMS_IREG_OCTAVE_1_0 + OCTAVE_OFFSET(voice));

sys/dev/isa/cms.c

257

reg &= ~(0x0f<<OCTAVE_SHIFT(voice));

sys/dev/isa/cms.c

258

reg |= ((octave&0x7)<<OCTAVE_SHIFT(voice));

sys/dev/isa/cms.c

259

CMS_WRITE(sc, chip, CMS_IREG_OCTAVE_1_0 + OCTAVE_OFFSET(voice), reg);

sys/dev/isa/cms.c

267

reg = CMS_READ(sc, chip, CMS_IREG_FREQ_CTL);

sys/dev/isa/cms.c

268

reg |= (1<<voice);

sys/dev/isa/cms.c

269

CMS_WRITE(sc, chip, CMS_IREG_FREQ_CTL, reg);

sys/dev/isa/cms.c

278

u_int8_t reg;

sys/dev/isa/cms.c

281

reg = CMS_READ(sc, chip, CMS_IREG_FREQ_CTL);

sys/dev/isa/cms.c

282

reg &= ~(1<<voice);

sys/dev/isa/cms.c

283

CMS_WRITE(sc, chip, CMS_IREG_FREQ_CTL, reg);

sys/dev/isa/cmsreg.h

130

#define CMS_WRITE(sc, chip, reg, val) \

sys/dev/isa/cmsreg.h

132

(sc)->sc_shadowregs[((chip)<<5) + (reg)] = val; \

sys/dev/isa/cmsreg.h

134

CMS_ADDR0 + ((chip)<<1), (reg)); \

sys/dev/isa/cmsreg.h

139

#define CMS_READ(sc, chip, reg) ((sc)->sc_shadowregs[((chip)<<5) + (reg)])

sys/dev/isa/esp_isa.c

417

esp_isa_read_reg(struct ncr53c9x_softc *sc, int reg)

sys/dev/isa/esp_isa.c

422

v = bus_space_read_1(esc->sc_iot, esc->sc_ioh, reg);

sys/dev/isa/esp_isa.c

426

NCRCFG4_CRS1) ? '1' : '0', reg, v));

sys/dev/isa/esp_isa.c

432

esp_isa_write_reg(struct ncr53c9x_softc *sc, int reg, uint8_t val)

sys/dev/isa/esp_isa.c

437

if (reg == NCR_CMD && v == (NCRCMD_TRANS|NCRCMD_DMA)) {

sys/dev/isa/esp_isa.c

443

NCRCFG4_CRS1) ? '1' : '0', reg, v));

sys/dev/isa/esp_isa.c

445

bus_space_write_1(esc->sc_iot, esc->sc_ioh, reg, v);

sys/dev/isa/ess.c

1166

u_int8_t reg;

sys/dev/isa/ess.c

1187

reg = ess_read_x_reg(sc, ESS_XCMD_AUDIO_CTRL);

sys/dev/isa/ess.c

1189

reg &= ~ESS_AUDIO_CTRL_MONO;

sys/dev/isa/ess.c

1190

reg |= ESS_AUDIO_CTRL_STEREO;

sys/dev/isa/ess.c

1192

reg |= ESS_AUDIO_CTRL_MONO;

sys/dev/isa/ess.c

1193

reg &= ~ESS_AUDIO_CTRL_STEREO;

sys/dev/isa/ess.c

1195

ess_write_x_reg(sc, ESS_XCMD_AUDIO_CTRL, reg);

sys/dev/isa/ess.c

1197

reg = ess_read_x_reg(sc, ESS_XCMD_AUDIO1_CTRL1);

sys/dev/isa/ess.c

1199

reg |= ESS_AUDIO1_CTRL1_FIFO_SIZE;

sys/dev/isa/ess.c

1201

reg &= ~ESS_AUDIO1_CTRL1_FIFO_SIZE;

sys/dev/isa/ess.c

1203

reg |= ESS_AUDIO1_CTRL1_FIFO_STEREO;

sys/dev/isa/ess.c

1205

reg &= ~ESS_AUDIO1_CTRL1_FIFO_STEREO;

sys/dev/isa/ess.c

1208

reg |= ESS_AUDIO1_CTRL1_FIFO_SIGNED;

sys/dev/isa/ess.c

1210

reg &= ~ESS_AUDIO1_CTRL1_FIFO_SIGNED;

sys/dev/isa/ess.c

1211

reg |= ESS_AUDIO1_CTRL1_FIFO_CONNECT;

sys/dev/isa/ess.c

1212

ess_write_x_reg(sc, ESS_XCMD_AUDIO1_CTRL1, reg);

sys/dev/isa/ess.c

1228

reg = ess_read_x_reg(sc, ESS_XCMD_AUDIO1_CTRL2);

sys/dev/isa/ess.c

1229

reg &= ~(ESS_AUDIO1_CTRL2_DMA_READ | ESS_AUDIO1_CTRL2_ADC_ENABLE);

sys/dev/isa/ess.c

1230

reg |= ESS_AUDIO1_CTRL2_FIFO_ENABLE | ESS_AUDIO1_CTRL2_AUTO_INIT;

sys/dev/isa/ess.c

1231

ess_write_x_reg(sc, ESS_XCMD_AUDIO1_CTRL2, reg);

sys/dev/isa/ess.c

1246

u_int8_t reg;

sys/dev/isa/ess.c

1267

reg = ess_read_mix_reg(sc, ESS_MREG_AUDIO2_CTRL2);

sys/dev/isa/ess.c

1269

reg |= ESS_AUDIO2_CTRL2_FIFO_SIZE;

sys/dev/isa/ess.c

1271

reg &= ~ESS_AUDIO2_CTRL2_FIFO_SIZE;

sys/dev/isa/ess.c

1273

reg |= ESS_AUDIO2_CTRL2_CHANNELS;

sys/dev/isa/ess.c

1275

reg &= ~ESS_AUDIO2_CTRL2_CHANNELS;

sys/dev/isa/ess.c

1278

reg |= ESS_AUDIO2_CTRL2_FIFO_SIGNED;

sys/dev/isa/ess.c

1280

reg &= ~ESS_AUDIO2_CTRL2_FIFO_SIGNED;

sys/dev/isa/ess.c

1281

ess_write_mix_reg(sc, ESS_MREG_AUDIO2_CTRL2, reg);

sys/dev/isa/ess.c

1294

reg = ess_read_mix_reg(sc, ESS_MREG_AUDIO2_CTRL1);

sys/dev/isa/ess.c

1296

reg |= ESS_AUDIO2_CTRL1_XFER_SIZE;

sys/dev/isa/ess.c

1298

reg &= ~ESS_AUDIO2_CTRL1_XFER_SIZE;

sys/dev/isa/ess.c

1299

reg |= ESS_AUDIO2_CTRL1_DEMAND_8;

sys/dev/isa/ess.c

1300

reg |= ESS_AUDIO2_CTRL1_DAC_ENABLE | ESS_AUDIO2_CTRL1_FIFO_ENABLE |

sys/dev/isa/ess.c

1302

ess_write_mix_reg(sc, ESS_MREG_AUDIO2_CTRL1, reg);

sys/dev/isa/ess.c

1317

u_int8_t reg;

sys/dev/isa/ess.c

1338

reg = ess_read_x_reg(sc, ESS_XCMD_AUDIO_CTRL);

sys/dev/isa/ess.c

1340

reg &= ~ESS_AUDIO_CTRL_MONO;

sys/dev/isa/ess.c

1341

reg |= ESS_AUDIO_CTRL_STEREO;

sys/dev/isa/ess.c

1343

reg |= ESS_AUDIO_CTRL_MONO;

sys/dev/isa/ess.c

1344

reg &= ~ESS_AUDIO_CTRL_STEREO;

sys/dev/isa/ess.c

1346

ess_write_x_reg(sc, ESS_XCMD_AUDIO_CTRL, reg);

sys/dev/isa/ess.c

1348

reg = ess_read_x_reg(sc, ESS_XCMD_AUDIO1_CTRL1);

sys/dev/isa/ess.c

1350

reg |= ESS_AUDIO1_CTRL1_FIFO_SIZE;

sys/dev/isa/ess.c

1352

reg &= ~ESS_AUDIO1_CTRL1_FIFO_SIZE;

sys/dev/isa/ess.c

1354

reg |= ESS_AUDIO1_CTRL1_FIFO_STEREO;

sys/dev/isa/ess.c

1356

reg &= ~ESS_AUDIO1_CTRL1_FIFO_STEREO;

sys/dev/isa/ess.c

1359

reg |= ESS_AUDIO1_CTRL1_FIFO_SIGNED;

sys/dev/isa/ess.c

1361

reg &= ~ESS_AUDIO1_CTRL1_FIFO_SIGNED;

sys/dev/isa/ess.c

1362

reg |= ESS_AUDIO1_CTRL1_FIFO_CONNECT;

sys/dev/isa/ess.c

1363

ess_write_x_reg(sc, ESS_XCMD_AUDIO1_CTRL1, reg);

sys/dev/isa/ess.c

1379

reg = ess_read_x_reg(sc, ESS_XCMD_AUDIO1_CTRL2);

sys/dev/isa/ess.c

1380

reg |= ESS_AUDIO1_CTRL2_DMA_READ | ESS_AUDIO1_CTRL2_ADC_ENABLE;

sys/dev/isa/ess.c

1381

reg |= ESS_AUDIO1_CTRL2_FIFO_ENABLE | ESS_AUDIO1_CTRL2_AUTO_INIT;

sys/dev/isa/ess.c

1382

ess_write_x_reg(sc, ESS_XCMD_AUDIO1_CTRL2, reg);

sys/dev/isa/ess.c

1432

uint8_t reg;

sys/dev/isa/ess.c

1441

reg = EREAD1(sc->sc_iot, sc->sc_ioh, ESS_DSP_RW_STATUS);

sys/dev/isa/ess.c

1442

if ((reg & ESS_DSP_READ_OFLOW) == 0) {

sys/dev/isa/ess.c

1446

reg = EREAD1(sc->sc_iot, sc->sc_ioh, ESS_CLEAR_INTR);

sys/dev/isa/ess.c

1465

uint8_t reg;

sys/dev/isa/ess.c

1474

reg = ess_read_mix_reg(sc, ESS_MREG_AUDIO2_CTRL2);

sys/dev/isa/ess.c

1475

if ((reg & ESS_AUDIO2_CTRL2_IRQ_LATCH) == 0) {

sys/dev/isa/ess.c

1479

reg &= ~ESS_AUDIO2_CTRL2_IRQ_LATCH;

sys/dev/isa/ess.c

1480

ess_write_mix_reg(sc, ESS_MREG_AUDIO2_CTRL2, reg);

sys/dev/isa/ess.c

2556

ess_write_x_reg(struct ess_softc *sc, u_char reg, u_char val)

sys/dev/isa/ess.c

2560

DPRINTFN(2,("ess_write_x_reg: %02x=%02x\n", reg, val));

sys/dev/isa/ess.c

2561

if ((error = ess_wdsp(sc, reg)) == 0)

sys/dev/isa/ess.c

2571

ess_read_x_reg(struct ess_softc *sc, u_char reg)

sys/dev/isa/ess.c

2577

error = ess_wdsp(sc, reg);

sys/dev/isa/ess.c

2579

DPRINTF(("Error reading extended register 0x%02x\n", reg));

sys/dev/isa/ess.c

2583

DPRINTFN(2,("ess_read_x_reg: %02x=%02x\n", reg, val));

sys/dev/isa/ess.c

2588

ess_clear_xreg_bits(struct ess_softc *sc, u_char reg, u_char mask)

sys/dev/isa/ess.c

2590

if (ess_write_x_reg(sc, reg, ess_read_x_reg(sc, reg) & ~mask) == -1) {

sys/dev/isa/ess.c

2592

reg));

sys/dev/isa/ess.c

2597

ess_set_xreg_bits(struct ess_softc *sc, u_char reg, u_char mask)

sys/dev/isa/ess.c

2599

if (ess_write_x_reg(sc, reg, ess_read_x_reg(sc, reg) | mask) == -1) {

sys/dev/isa/ess.c

2601

reg));

sys/dev/isa/ess.c

2610

ess_write_mix_reg(struct ess_softc *sc, u_char reg, u_char val)

sys/dev/isa/ess.c

2615

DPRINTFN(2,("ess_write_mix_reg: %x=%x\n", reg, val));

sys/dev/isa/ess.c

2619

EWRITE1(iot, ioh, ESS_MIX_REG_SELECT, reg);

sys/dev/isa/ess.c

2627

ess_read_mix_reg(struct ess_softc *sc, u_char reg)

sys/dev/isa/ess.c

2635

EWRITE1(iot, ioh, ESS_MIX_REG_SELECT, reg);

sys/dev/isa/ess.c

2638

DPRINTFN(2,("ess_read_mix_reg: %x=%x\n", reg, val));

sys/dev/isa/ess.c

2643

ess_clear_mreg_bits(struct ess_softc *sc, u_char reg, u_char mask)

sys/dev/isa/ess.c

2646

ess_write_mix_reg(sc, reg, ess_read_mix_reg(sc, reg) & ~mask);

sys/dev/isa/ess.c

2650

ess_set_mreg_bits(struct ess_softc *sc, u_char reg, u_char mask)

sys/dev/isa/ess.c

2653

ess_write_mix_reg(sc, reg, ess_read_mix_reg(sc, reg) | mask);

sys/dev/isa/ess.c

2657

ess_read_multi_mix_reg(struct ess_softc *sc, u_char reg,

sys/dev/isa/ess.c

2665

EWRITE1(iot, ioh, ESS_MIX_REG_SELECT, reg);

sys/dev/isa/finsio_isa.c

607

finsio_readreg(bus_space_tag_t iot, bus_space_handle_t ioh, int reg)

sys/dev/isa/finsio_isa.c

609

bus_space_write_1(iot, ioh, FINSIO_ADDR, reg);

sys/dev/isa/finsio_isa.c

614

finsio_writereg(bus_space_tag_t iot, bus_space_handle_t ioh, int reg, int val)

sys/dev/isa/finsio_isa.c

616

bus_space_write_1(iot, ioh, FINSIO_ADDR, reg);

sys/dev/isa/i82365_isasubr.c

454

int reg;

sys/dev/isa/i82365_isasubr.c

478

reg = pcic_read(h, PCIC_INTR);

sys/dev/isa/i82365_isasubr.c

479

reg &= ~PCIC_INTR_IRQ_MASK;

sys/dev/isa/i82365_isasubr.c

480

pcic_write(h, PCIC_INTR, reg | irq);

sys/dev/isa/i82365_isasubr.c

497

int reg;

sys/dev/isa/i82365_isasubr.c

503

reg = pcic_read(h, PCIC_INTR);

sys/dev/isa/i82365_isasubr.c

504

reg &= ~PCIC_INTR_IRQ_MASK;

sys/dev/isa/i82365_isasubr.c

505

pcic_write(h, PCIC_INTR, reg);

sys/dev/isa/if_ntwoc_isa.c

116

ntwoc_isa_sca_write_1(struct sca_softc *sc, u_int reg, u_int8_t val)

sys/dev/isa/if_ntwoc_isa.c

118

bus_space_write_1(sc->sc_iot, sc->scu_sca_ioh[(reg & 0xf0) >> 4],

sys/dev/isa/if_ntwoc_isa.c

119

(reg & 0xf), val);

sys/dev/isa/if_ntwoc_isa.c

123

ntwoc_isa_sca_write_2(struct sca_softc *sc, u_int reg, u_int16_t val)

sys/dev/isa/if_ntwoc_isa.c

125

bus_space_write_2(sc->sc_iot, sc->scu_sca_ioh[(reg & 0xf0) >> 4],

sys/dev/isa/if_ntwoc_isa.c

126

(reg & 0xf), val);

sys/dev/isa/if_ntwoc_isa.c

130

ntwoc_isa_sca_read_1(struct sca_softc *sc, u_int reg)

sys/dev/isa/if_ntwoc_isa.c

133

bus_space_read_1(sc->sc_iot, sc->scu_sca_ioh[(reg & 0xf0) >> 4],

sys/dev/isa/if_ntwoc_isa.c

134

(reg & 0xf));

sys/dev/isa/if_ntwoc_isa.c

138

ntwoc_isa_sca_read_2(struct sca_softc *sc, u_int reg)

sys/dev/isa/if_ntwoc_isa.c

141

bus_space_read_2(sc->sc_iot, sc->scu_sca_ioh[(reg & 0xf0) >> 4],

sys/dev/isa/if_ntwoc_isa.c

142

(reg & 0xf));

sys/dev/isa/isv.c

123

isv_read(struct isv_regs *ir, bus_size_t reg)

sys/dev/isa/isv.c

125

return bus_space_read_2(ir->ir_bt, ir->ir_bh, reg);

sys/dev/isa/isv.c

129

isv_write(struct isv_regs *ir, bus_size_t reg, uint16_t val)

sys/dev/isa/isv.c

131

bus_space_write_2(ir->ir_bt, ir->ir_bh, reg, val);

sys/dev/isa/itesio_isa.c

406

itesio_ecreadreg(struct itesio_softc *sc, int reg)

sys/dev/isa/itesio_isa.c

408

bus_space_write_1(sc->sc_iot, sc->sc_ec_ioh, ITESIO_EC_ADDR, reg);

sys/dev/isa/itesio_isa.c

413

itesio_ecwritereg(struct itesio_softc *sc, int reg, int val)

sys/dev/isa/itesio_isa.c

415

bus_space_write_1(sc->sc_iot, sc->sc_ec_ioh, ITESIO_EC_ADDR, reg);

sys/dev/isa/itesio_isa.c

423

itesio_readreg(bus_space_tag_t iot, bus_space_handle_t ioh, int reg)

sys/dev/isa/itesio_isa.c

425

bus_space_write_1(iot, ioh, ITESIO_ADDR, reg);

sys/dev/isa/itesio_isa.c

430

itesio_writereg(bus_space_tag_t iot, bus_space_handle_t ioh, int reg, int val)

sys/dev/isa/itesio_isa.c

432

bus_space_write_1(iot, ioh, ITESIO_ADDR, reg);

sys/dev/isa/lm_isa_common.c

143

lm_isa_readreg(struct lm_softc *lmsc, int reg)

sys/dev/isa/lm_isa_common.c

147

bus_space_write_1(sc->lm_iot, sc->lm_ioh, LMC_ADDR, reg);

sys/dev/isa/lm_isa_common.c

152

lm_isa_writereg(struct lm_softc *lmsc, int reg, uint8_t val)

sys/dev/isa/lm_isa_common.c

156

bus_space_write_1(sc->lm_iot, sc->lm_ioh, LMC_ADDR, reg);

sys/dev/isa/nct.c

180

nct_outb(struct nct_softc *sc, int reg, u_int8_t data)

sys/dev/isa/nct.c

183

bus_space_write_1(sc->sc_iot, sc->sc_ioh, reg, data);

sys/dev/isa/nct.c

187

nct_inb(struct nct_softc *sc, int reg)

sys/dev/isa/nct.c

190

return bus_space_read_1(sc->sc_iot, sc->sc_ioh, reg);

sys/dev/isa/nct.c

464

nct_rd(struct nct_softc *sc, int reg)

sys/dev/isa/nct.c

470

dev = reg >> 8;

sys/dev/isa/nct.c

471

reg &= 0xff;

sys/dev/isa/nct.c

475

sc->sc_curreg = reg;

sys/dev/isa/nct.c

478

nct_outb(sc, NCT_PORT_SELECT, reg);

sys/dev/isa/nct.c

480

} else if (reg != sc->sc_curreg) {

sys/dev/isa/nct.c

481

sc->sc_curreg = reg;

sys/dev/isa/nct.c

482

nct_outb(sc, NCT_PORT_SELECT, reg);

sys/dev/isa/nct.c

493

nct_wr(struct nct_softc *sc, int reg, u_int8_t data)

sys/dev/isa/nct.c

499

dev = reg >> 8;

sys/dev/isa/nct.c

500

reg &= 0xff;

sys/dev/isa/nct.c

504

sc->sc_curreg = reg;

sys/dev/isa/nct.c

507

nct_outb(sc, NCT_PORT_SELECT, reg);

sys/dev/isa/nct.c

509

} else if (reg != sc->sc_curreg) {

sys/dev/isa/nct.c

510

sc->sc_curreg = reg;

sys/dev/isa/nct.c

511

nct_outb(sc, NCT_PORT_SELECT, reg);

sys/dev/isa/nsclpcsio_isa.c

191

#define GPIO_READ(sc, reg) \

sys/dev/isa/nsclpcsio_isa.c

193

(sc)->sc_ld_ioh[SIO_LDN_GPIO], (reg))

sys/dev/isa/nsclpcsio_isa.c

194

#define GPIO_WRITE(sc, reg, val) \

sys/dev/isa/nsclpcsio_isa.c

196

(sc)->sc_ld_ioh[SIO_LDN_GPIO], (reg), (val))

sys/dev/isa/nsclpcsio_isa.c

197

#define TMS_WRITE(sc, reg, val) \

sys/dev/isa/nsclpcsio_isa.c

199

(sc)->sc_ld_ioh[SIO_LDN_TMS], (reg), (val))

sys/dev/isa/nsclpcsio_isa.c

200

#define TMS_READ(sc, reg) \

sys/dev/isa/nsclpcsio_isa.c

202

(sc)->sc_ld_ioh[SIO_LDN_TMS], (reg))

sys/dev/isa/nsclpcsio_isa.c

203

#define VLM_WRITE(sc, reg, val) \

sys/dev/isa/nsclpcsio_isa.c

205

(sc)->sc_ld_ioh[SIO_LDN_VLM], (reg), (val))

sys/dev/isa/nsclpcsio_isa.c

206

#define VLM_READ(sc, reg) \

sys/dev/isa/nsclpcsio_isa.c

208

(sc)->sc_ld_ioh[SIO_LDN_VLM], (reg))

sys/dev/isa/nsclpcsio_isa.c

586

int port, shift, reg;

sys/dev/isa/nsclpcsio_isa.c

594

reg = SIO_GPDI0;

sys/dev/isa/nsclpcsio_isa.c

597

reg = SIO_GPDI1;

sys/dev/isa/nsclpcsio_isa.c

600

reg = SIO_GPDI2;

sys/dev/isa/nsclpcsio_isa.c

603

reg = SIO_GPDI3;

sys/dev/isa/nsclpcsio_isa.c

606

reg = SIO_GPDI0;

sys/dev/isa/nsclpcsio_isa.c

610

v = GPIO_READ(sc, reg);

sys/dev/isa/nsclpcsio_isa.c

619

int port, shift, reg;

sys/dev/isa/nsclpcsio_isa.c

627

reg = SIO_GPDO0;

sys/dev/isa/nsclpcsio_isa.c

630

reg = SIO_GPDO1;

sys/dev/isa/nsclpcsio_isa.c

633

reg = SIO_GPDO2;

sys/dev/isa/nsclpcsio_isa.c

636

reg = SIO_GPDO3;

sys/dev/isa/nsclpcsio_isa.c

639

reg = SIO_GPDO0;

sys/dev/isa/nsclpcsio_isa.c

643

d = GPIO_READ(sc, reg);

sys/dev/isa/nsclpcsio_isa.c

648

GPIO_WRITE(sc, reg, d);

sys/dev/isa/radiotrack.c

262

u_int32_t reg;

sys/dev/isa/radiotrack.c

271

reg = lm700x_encode_freq(nfreq, sc->rf);

sys/dev/isa/radiotrack.c

272

reg |= sc->stereo | sc->rf | LM700X_DIVIDER_FM;

sys/dev/isa/radiotrack.c

274

lm700x_hardware_write(&sc->lm, reg, RT_VOLUME_STEADY);

sys/dev/isa/smsc.c

194

#define INITSENSOR(index, string, reg, type) \

sys/dev/isa/smsc.c

199

sc->sc_regs[index] = reg; \

sys/dev/isa/smsc.c

270

smsc_readreg(bus_space_tag_t iot, bus_space_handle_t ioh, int reg)

sys/dev/isa/smsc.c

272

bus_space_write_1(iot, ioh, SMSC_ADDR, reg);

sys/dev/isa/smsc.c

280

smsc_writereg(bus_space_tag_t iot, bus_space_handle_t ioh, int reg, int val)

sys/dev/isa/smsc.c

282

bus_space_write_1(iot, ioh, SMSC_ADDR, reg);

sys/dev/isa/smsc.c

327

int reg;

sys/dev/isa/smsc.c

331

reg = sc->sc_regs[edata->sensor];

sys/dev/isa/smsc.c

336

smsc_temp2muk(smsc_readreg(sc->sc_iot, sc->sc_ioh, reg));

sys/dev/isa/smsc.c

341

lsb = smsc_readreg(sc->sc_iot, sc->sc_ioh, reg);

sys/dev/isa/smsc.c

342

msb = smsc_readreg(sc->sc_iot, sc->sc_ioh, reg + 1);

sys/dev/isa/tcic2_isa.c

378

int val, reg;

sys/dev/isa/tcic2_isa.c

385

reg = TCIC_IR_SCF1_N(h->sock);

sys/dev/isa/tcic2_isa.c

386

val = tcic_read_ind_2(h, reg);

sys/dev/isa/tcic2_isa.c

388

tcic_write_ind_2(h, reg, val);

sys/dev/isa/wbsio.c

567

wbsio_gpio_rt_read(struct wbsio_softc *sc, int port, int reg)

sys/dev/isa/wbsio.c

575

v = bus_space_read_1(sc->sc_iot, sc->sc_gpio_ioh, reg);

sys/dev/isa/wbsio.c

583

wbsio_gpio_rt_write(struct wbsio_softc *sc, int port, int reg, int value)

sys/dev/isa/wbsio.c

591

reg, value);

sys/dev/isa/wbsio.c

664

uint8_t reg, conf;

sys/dev/isa/wbsio.c

670

reg = WBSIO_GPIO_CONF;

sys/dev/isa/wbsio.c

671

conf = wbsio_conf_read(sc->sc_iot, sc->sc_ioh, reg);

sys/dev/isa/wbsio.c

676

wbsio_conf_write(sc->sc_iot, sc->sc_ioh, reg, conf);

sys/dev/isa/wbsio.c

679

reg = WBSIO_GPIO_CONF;

sys/dev/isa/wbsio.c

680

conf = wbsio_conf_read(sc->sc_iot, sc->sc_ioh, reg);

sys/dev/isa/wbsio.c

688

wbsio_conf_write(sc->sc_iot, sc->sc_ioh, reg, conf);

sys/dev/isa/weasel_isa.c

245

u_int8_t reg;

sys/dev/isa/weasel_isa.c

254

reg = bus_space_read_1(wh->wh_st, wh->wh_sh, WEASEL_WDT_TICKLE);

sys/dev/isa/weasel_isa.c

255

bus_space_write_1(wh->wh_st, wh->wh_sh, WEASEL_WDT_TICKLE, ~reg);

sys/dev/isa/weasel_isa.c

281

u_int8_t reg;

sys/dev/isa/weasel_isa.c

292

reg = bus_space_read_1(wh->wh_st, wh->wh_sh,

sys/dev/isa/weasel_isa.c

294

if (reg == WDT_OK)

sys/dev/isa/weasel_isa.c

304

reg = bus_space_read_1(wh->wh_st, wh->wh_sh,

sys/dev/isa/weasel_isa.c

306

if (reg != mode)

sys/dev/isa/weasel_isa.c

313

bus_space_write_1(wh->wh_st, wh->wh_sh, WEASEL_WDT_SEMAPHORE, ~reg);

sys/dev/isa/weasel_isa.c

316

reg = bus_space_read_1(wh->wh_st, wh->wh_sh,

sys/dev/isa/weasel_isa.c

318

if (reg == WDT_OK)

sys/dev/isa/weasel_isa.c

354

int timeout, reg;

sys/dev/isa/weasel_isa.c

360

reg = bus_space_read_1(wh->wh_st, wh->wh_sh,

sys/dev/isa/weasel_isa.c

362

if (reg == OS_READY)

sys/dev/isa/ym.c

323

ym_read(struct ym_softc *sc, int reg)

sys/dev/isa/ym.c

327

SA3_CTL_INDEX, (reg & 0xff));

sys/dev/isa/ym.c

332

ym_write(struct ym_softc *sc, int reg, int data)

sys/dev/isa/ym.c

336

SA3_CTL_INDEX, (reg & 0xff));

sys/dev/isa/ym.c

438

uint8_t reg;

sys/dev/isa/ym.c

440

reg = ym_read(sc, left_reg);

sys/dev/isa/ym.c

442

ym_write(sc, left_reg, reg | 0x80);

sys/dev/isa/ym.c

444

ym_write(sc, left_reg, reg & ~0x80);

sys/dev/isa/ym.c

521

struct ad1848_volume *val, int reg)

sys/dev/isa/ym.c

531

if (reg != SA3_3D_WIDE) {

sys/dev/isa/ym.c

548

ym_write(sc, reg, e);

sys/dev/marvell/ehci_mv.c

256

uint32_t reg;

sys/dev/marvell/ehci_mv.c

267

reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh,

sys/dev/marvell/ehci_mv.c

269

reg |= EHCI_CMD_HCRESET;

sys/dev/marvell/ehci_mv.c

271

MARVELL_USB_EHCI_BASE + opr_offs + EHCI_USBCMD, reg);

sys/dev/marvell/ehci_mv.c

279

reg =

sys/dev/marvell/ehci_mv.c

285

reg &= ~(0x7f << 8);

sys/dev/marvell/ehci_mv.c

286

reg |= (0x0c << 8);

sys/dev/marvell/ehci_mv.c

288

reg);

sys/dev/marvell/ehci_mv.c

291

reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, MARVELL_USB_PCR);

sys/dev/marvell/ehci_mv.c

292

reg &= ~MARVELL_USB_PCR_BGVSEL_MASK;

sys/dev/marvell/ehci_mv.c

293

reg |= MARVELL_USB_PCR_BGVSEL_CONNECT_ANAGRP;

sys/dev/marvell/ehci_mv.c

294

bus_space_write_4(sc->sc_iot, sc->sc_ioh, MARVELL_USB_PCR, reg);

sys/dev/marvell/ehci_mv.c

296

reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh,

sys/dev/marvell/ehci_mv.c

300

reg &= ~(1 << 21);

sys/dev/marvell/ehci_mv.c

302

reg |= (1 << 21);

sys/dev/marvell/ehci_mv.c

304

reg |= (1 << 13);

sys/dev/marvell/ehci_mv.c

306

reg &= ~(0xf << 3);

sys/dev/marvell/ehci_mv.c

307

reg |= (8 << 3);

sys/dev/marvell/ehci_mv.c

309

reg);

sys/dev/marvell/ehci_mv.c

311

reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh,

sys/dev/marvell/ehci_mv.c

318

reg &= ~(3 << 8);

sys/dev/marvell/ehci_mv.c

320

reg |= (3 << 8);

sys/dev/marvell/ehci_mv.c

323

reg |= (2 << 8);

sys/dev/marvell/ehci_mv.c

325

reg &= ~(1 << 21);

sys/dev/marvell/ehci_mv.c

327

reg &= ~(3 << 26);

sys/dev/marvell/ehci_mv.c

329

reg |= (3 << 30);

sys/dev/marvell/ehci_mv.c

331

reg &= ~(0xf << 4);

sys/dev/marvell/ehci_mv.c

332

reg |= (1 << 4);

sys/dev/marvell/ehci_mv.c

334

reg);

sys/dev/marvell/ehci_mv.c

336

reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh,

sys/dev/marvell/ehci_mv.c

339

reg &= ~(3 << 0);

sys/dev/marvell/ehci_mv.c

340

reg |= (2 << 0);

sys/dev/marvell/ehci_mv.c

342

reg &= ~(3 << 4);

sys/dev/marvell/ehci_mv.c

343

reg |= (3 << 4);

sys/dev/marvell/ehci_mv.c

345

reg &= ~(1 << 19);

sys/dev/marvell/ehci_mv.c

347

MARVELL_USB_PIVREFFCR, reg);

sys/dev/marvell/ehci_mv.c

349

reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh,

sys/dev/marvell/ehci_mv.c

352

reg &= ~(1 << 15);

sys/dev/marvell/ehci_mv.c

354

reg);

sys/dev/marvell/gtethreg.h

175

#define ETH_ESMIR_READ(phy, reg) (ETH__INS(phy, 16)|\

sys/dev/marvell/gtethreg.h

176

ETH__INS(reg, 21)|\

sys/dev/marvell/gtethreg.h

178

#define ETH_ESMIR_WRITE(phy, reg, val) (ETH__INS(phy, 16)|\

sys/dev/marvell/gtethreg.h

179

ETH__INS(reg, 21)|\

sys/dev/marvell/gtintrvar.h

39

bus_size_t reg;

sys/dev/marvell/gtintrvar.h

42

reg = (irq < 32) ? ICR_CIM_LO : ICR_CIM_HI;

sys/dev/marvell/gtintrvar.h

43

cim = bus_space_read_4(sc->sc_iot, sc->sc_ioh, reg);

sys/dev/marvell/gtintrvar.h

45

bus_space_write_4(sc->sc_iot, sc->sc_ioh, reg, cim);

sys/dev/marvell/gtintrvar.h

52

bus_size_t reg;

sys/dev/marvell/gtintrvar.h

55

reg = (irq < 32) ? ICR_CIM_LO : ICR_CIM_HI;

sys/dev/marvell/gtintrvar.h

56

cim = bus_space_read_4(sc->sc_iot, sc->sc_ioh, reg);

sys/dev/marvell/gtintrvar.h

58

bus_space_write_4(sc->sc_iot, sc->sc_ioh, reg, cim);

sys/dev/marvell/gtpci.c

234

uint32_t reg;

sys/dev/marvell/gtpci.c

240

reg = GTPCI_READ(sc, GTPCI_AC);

sys/dev/marvell/gtpci.c

241

reg |= GTPCI_AC_EN;

sys/dev/marvell/gtpci.c

242

GTPCI_WRITE(sc, GTPCI_AC, reg);

sys/dev/marvell/gtpci.c

248

reg = GTPCI_READ(sc, GTPCI_ADC);

sys/dev/marvell/gtpci.c

249

reg |= GTPCI_ADC_REMAPWRDIS;

sys/dev/marvell/gtpci.c

250

GTPCI_WRITE(sc, GTPCI_ADC, reg);

sys/dev/marvell/gtpci.c

253

reg = GTPCI_READ(sc, GTPCI_C);

sys/dev/marvell/gtpci.c

254

reg |= GTPCI_C_CPU2PCIORDERING;

sys/dev/marvell/gtpci.c

255

GTPCI_WRITE(sc, GTPCI_C, reg);

sys/dev/marvell/gtpci.c

334

pcireg_t reg;

sys/dev/marvell/gtpci.c

340

reg = gtpci_conf_read(sc, tag, maps[map].balow);

sys/dev/marvell/gtpci.c

341

reg &= ~GTPCI_BARLOW_MASK;

sys/dev/marvell/gtpci.c

342

reg |= GTPCI_BARLOW_BASE(base);

sys/dev/marvell/gtpci.c

343

gtpci_conf_write(sc, tag, maps[map].balow, reg);

sys/dev/marvell/gtpci.c

344

reg = gtpci_conf_read(sc, tag, maps[map].bahigh);

sys/dev/marvell/gtpci.c

345

reg = (base >> 16) >> 16;

sys/dev/marvell/gtpci.c

346

gtpci_conf_write(sc, tag, maps[map].bahigh, reg);

sys/dev/marvell/gtpci.c

557

gtpci_conf_read(void *v, pcitag_t tag, int reg)

sys/dev/marvell/gtpci.c

560

const pcireg_t addr = tag | reg;

sys/dev/marvell/gtpci.c

562

if ((unsigned int)reg >= PCI_CONF_SIZE)

sys/dev/marvell/gtpci.c

573

gtpci_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data)

sys/dev/marvell/gtpci.c

576

pcireg_t addr = tag | (reg & 0xfc);

sys/dev/marvell/gtpci.c

578

if ((unsigned int)reg >= PCI_CONF_SIZE)

sys/dev/marvell/if_gfe.c

298

gfec_mii_read(device_t dev, int phy, int reg, uint16_t *val)

sys/dev/marvell/if_gfe.c

313

"mii read for phy %d reg %d busied out\n", phy, reg);

sys/dev/marvell/if_gfe.c

319

ETH_ESMIR_READ(phy, reg));

sys/dev/marvell/if_gfe.c

331

"mii read for phy %d reg %d timed out\n", phy, reg);

sys/dev/marvell/if_gfe.c

336

phy, reg, data, ETH_ESMIR_Value_GET(data));

sys/dev/marvell/if_gfe.c

343

gfec_mii_write(device_t dev, int phy, int reg, uint16_t value)

sys/dev/marvell/if_gfe.c

359

phy, reg);

sys/dev/marvell/if_gfe.c

365

ETH_ESMIR_WRITE(phy, reg, value));

sys/dev/marvell/if_gfe.c

377

"mii write for phy %d reg %d timed out\n", phy, reg);

sys/dev/marvell/if_gfe.c

381

aprint_normal_dev(dev, "mii_write(%d, %d, %#hx)\n", phy, reg, value);

sys/dev/marvell/if_gfe.c

86

#define GE_READ(sc, reg) \

sys/dev/marvell/if_gfe.c

87

bus_space_read_4((sc)->sc_memt, (sc)->sc_memh, (reg))

sys/dev/marvell/if_gfe.c

88

#define GE_WRITE(sc, reg, v) \

sys/dev/marvell/if_gfe.c

89

bus_space_write_4((sc)->sc_memt, (sc)->sc_memh, (reg), (v))

sys/dev/marvell/if_mvgbe.c

1143

uint32_t reg;

sys/dev/marvell/if_mvgbe.c

1188

reg = MVGBE_READ(csc, MVGBE_PMACC2);

sys/dev/marvell/if_mvgbe.c

1189

reg &= MVGBE_PMACC2_PCSEN; /* keep PCSEN bit */

sys/dev/marvell/if_mvgbe.c

1191

reg | MVGBE_PMACC2_RESERVED | MVGBE_PMACC2_RGMIIEN);

sys/dev/marvell/if_mvgbe.c

1263

reg = MVGBE_READ(csc, MVGBE_PMACC0);

sys/dev/marvell/if_mvgbe.c

1264

MVGBE_WRITE(csc, MVGBE_PMACC0, reg | MVGBE_PMACC0_PORTEN);

sys/dev/marvell/if_mvgbe.c

1266

reg = MVGBE_READ(sc, MVGBE_PSC);

sys/dev/marvell/if_mvgbe.c

1267

MVGBE_WRITE(sc, MVGBE_PSC, reg | MVGBE_PSC_PORTEN);

sys/dev/marvell/if_mvgbe.c

1304

uint32_t reg, txinprog, txfifoemp;

sys/dev/marvell/if_mvgbe.c

1312

reg = MVGBE_READ(sc, MVGBE_RQC);

sys/dev/marvell/if_mvgbe.c

1313

if (reg & MVGBE_RQC_ENQ_MASK)

sys/dev/marvell/if_mvgbe.c

1315

MVGBE_WRITE(sc, MVGBE_RQC, MVGBE_RQC_DISQ_DISABLE(reg));

sys/dev/marvell/if_mvgbe.c

1323

reg = MVGBE_READ(csc, MVGBE_PANC);

sys/dev/marvell/if_mvgbe.c

1324

MVGBE_WRITE(csc, MVGBE_PANC, reg | MVGBE_PANC_FORCELINKFAIL);

sys/dev/marvell/if_mvgbe.c

1329

reg = MVGBE_READ(sc, MVGBE_PSC);

sys/dev/marvell/if_mvgbe.c

1330

MVGBE_WRITE(sc, MVGBE_PSC, reg & ~MVGBE_PSC_FLFAIL);

sys/dev/marvell/if_mvgbe.c

1343

"timeout for RX stopped. rqc 0x%x\n", reg);

sys/dev/marvell/if_mvgbe.c

1352

reg = MVGBE_READ(sc, MVGBE_RQC);

sys/dev/marvell/if_mvgbe.c

1353

} while (reg & 0xff);

sys/dev/marvell/if_mvgbe.c

1362

reg);

sys/dev/marvell/if_mvgbe.c

1367

reg = MVGBE_READ(sc, MVGBE_PS);

sys/dev/marvell/if_mvgbe.c

1368

} while (!(reg & txfifoemp) || reg & txinprog);

sys/dev/marvell/if_mvgbe.c

1374

reg = MVGBE_READ(sc, MVGBE_PS);

sys/dev/marvell/if_mvgbe.c

1375

if (reg & txfifoemp && !(reg & txinprog))

sys/dev/marvell/if_mvgbe.c

1380

" %d loops, status 0x%x\n", cnt, reg);

sys/dev/marvell/if_mvgbe.c

1385

reg = MVGBE_READ(csc, MVGBE_PMACC0);

sys/dev/marvell/if_mvgbe.c

1386

MVGBE_WRITE(csc, MVGBE_PMACC0, reg & ~MVGBE_PMACC0_PORTEN);

sys/dev/marvell/if_mvgbe.c

1388

reg = MVGBE_READ(sc, MVGBE_PSC);

sys/dev/marvell/if_mvgbe.c

1389

MVGBE_WRITE(sc, MVGBE_PSC, reg & ~MVGBE_PSC_PORTEN);

sys/dev/marvell/if_mvgbe.c

519

mvgbec_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val)

sys/dev/marvell/if_mvgbe.c

547

MVGBE_SMI_PHYAD(phy) | MVGBE_SMI_REGAD(reg) | MVGBE_SMI_OPCODE_READ;

sys/dev/marvell/if_mvgbe.c

567

phy, reg, *val));

sys/dev/marvell/if_mvgbe.c

573

mvgbec_miibus_writereg(device_t dev, int phy, int reg, uint16_t val)

sys/dev/marvell/if_mvgbe.c

588

phy, reg, val));

sys/dev/marvell/if_mvgbe.c

603

smi = MVGBE_SMI_PHYAD(phy) | MVGBE_SMI_REGAD(reg) |

sys/dev/marvell/if_mvgbe.c

80

#define MVGBE_READ(sc, reg) \

sys/dev/marvell/if_mvgbe.c

81

bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg))

sys/dev/marvell/if_mvgbe.c

82

#define MVGBE_WRITE(sc, reg, val) \

sys/dev/marvell/if_mvgbe.c

83

bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))

sys/dev/marvell/if_mvgbe.c

84

#define MVGBE_READ_FILTER(sc, reg, val, c) \

sys/dev/marvell/if_mvgbe.c

85

bus_space_read_region_4((sc)->sc_iot, (sc)->sc_dafh, (reg), (val), (c))

sys/dev/marvell/if_mvgbe.c

86

#define MVGBE_WRITE_FILTER(sc, reg, val, c) \

sys/dev/marvell/if_mvgbe.c

87

bus_space_write_region_4((sc)->sc_iot, (sc)->sc_dafh, (reg), (val), (c))

sys/dev/marvell/if_mvgbe.c

940

uint32_t reg;

sys/dev/marvell/if_mvgbe.c

941

reg = MVGBE_READ(sc, MVGBE_PTFUT);

sys/dev/marvell/if_mvgbe.c

946

reg &= ~MVGBE_PTFUT_IPGINTTX_V2_MASK;

sys/dev/marvell/if_mvgbe.c

947

reg |= MVGBE_PTFUT_IPGINTTX_V2(ipginttx);

sys/dev/marvell/if_mvgbe.c

951

reg &= ~MVGBE_PTFUT_IPGINTTX_V1_MASK;

sys/dev/marvell/if_mvgbe.c

952

reg |= MVGBE_PTFUT_IPGINTTX_V1(ipginttx);

sys/dev/marvell/if_mvgbe.c

954

MVGBE_WRITE(sc, MVGBE_PTFUT, reg);

sys/dev/marvell/if_mvgbe.c

963

uint32_t reg;

sys/dev/marvell/if_mvgbe.c

964

reg = MVGBE_READ(sc, MVGBE_SDC);

sys/dev/marvell/if_mvgbe.c

969

reg &= ~MVGBE_SDC_IPGINTRX_V2_MASK;

sys/dev/marvell/if_mvgbe.c

970

reg |= MVGBE_SDC_IPGINTRX_V2(ipgintrx);

sys/dev/marvell/if_mvgbe.c

974

reg &= ~MVGBE_SDC_IPGINTRX_V1_MASK;

sys/dev/marvell/if_mvgbe.c

975

reg |= MVGBE_SDC_IPGINTRX_V1(ipgintrx);

sys/dev/marvell/if_mvgbe.c

977

MVGBE_WRITE(sc, MVGBE_SDC, reg);

sys/dev/marvell/if_mvxpe.c

1222

uint32_t reg;

sys/dev/marvell/if_mvxpe.c

1231

reg = MVXPE_PRXDQS_BUFFERSIZE(mvxpbm_chunk_size(sc->sc_bm) >> 3);

sys/dev/marvell/if_mvxpe.c

1232

reg |= MVXPE_PRXDQS_DESCRIPTORSQUEUESIZE(MVXPE_RX_RING_CNT);

sys/dev/marvell/if_mvxpe.c

1233

MVXPE_WRITE(sc, MVXPE_PRXDQS(q), reg);

sys/dev/marvell/if_mvxpe.c

1238

reg = MVXPE_PRXC_PACKETOFFSET(mvxpbm_packet_offset(sc->sc_bm) >> 3);

sys/dev/marvell/if_mvxpe.c

1239

MVXPE_WRITE(sc, MVXPE_PRXC(q), reg);

sys/dev/marvell/if_mvxpe.c

1244

reg = MVXPE_PRXSNP_SNOOPNOOFBYTES(MVXPE_MRU);

sys/dev/marvell/if_mvxpe.c

1245

reg |= MVXPE_PRXSNP_L2DEPOSITNOOFBYTES(MVXPE_MRU);

sys/dev/marvell/if_mvxpe.c

1246

MVXPE_WRITE(sc, MVXPE_PRXSNP(q), reg);

sys/dev/marvell/if_mvxpe.c

1258

uint32_t reg;

sys/dev/marvell/if_mvxpe.c

1267

reg = MVXPE_PTXDQS_TBT(tx->tx_queue_th_free);

sys/dev/marvell/if_mvxpe.c

1268

reg |= MVXPE_PTXDQS_DQS(MVXPE_TX_RING_CNT);

sys/dev/marvell/if_mvxpe.c

1269

MVXPE_WRITE(sc, MVXPE_PTXDQS(q), reg);

sys/dev/marvell/if_mvxpe.c

1283

uint32_t reg;

sys/dev/marvell/if_mvxpe.c

1288

reg = MVXPE_PRXDQTH_ODT(rx->rx_queue_th_received);

sys/dev/marvell/if_mvxpe.c

1289

reg |= MVXPE_PRXDQTH_NODT(rx->rx_queue_th_free);

sys/dev/marvell/if_mvxpe.c

1290

MVXPE_WRITE(sc, MVXPE_PRXDQTH(q), reg);

sys/dev/marvell/if_mvxpe.c

1292

reg = MVXPE_PRXITTH_RITT(rx->rx_queue_th_time);

sys/dev/marvell/if_mvxpe.c

1293

MVXPE_WRITE(sc, MVXPE_PRXITTH(q), reg);

sys/dev/marvell/if_mvxpe.c

1296

reg = MVXPE_READ(sc, MVXPE_PRXTXTIM);

sys/dev/marvell/if_mvxpe.c

1297

reg |= MVXPE_PRXTXTI_RBICTAPQ(q); /* Rx Buffer Interrupt Coalesce */

sys/dev/marvell/if_mvxpe.c

1298

reg |= MVXPE_PRXTXTI_RDTAQ(q); /* Rx Descriptor Alert */

sys/dev/marvell/if_mvxpe.c

1299

MVXPE_WRITE(sc, MVXPE_PRXTXTIM, reg);

sys/dev/marvell/if_mvxpe.c

1302

reg = MVXPE_READ(sc, MVXPE_RQC) & MVXPE_RQC_EN_MASK;

sys/dev/marvell/if_mvxpe.c

1303

reg |= MVXPE_RQC_ENQ(q);

sys/dev/marvell/if_mvxpe.c

1304

MVXPE_WRITE(sc, MVXPE_RQC, reg);

sys/dev/marvell/if_mvxpe.c

1314

uint32_t reg;

sys/dev/marvell/if_mvxpe.c

1319

reg = MVXPE_READ(sc, MVXPE_PTXDQS(q));

sys/dev/marvell/if_mvxpe.c

1320

reg &= ~MVXPE_PTXDQS_TBT_MASK; /* keep queue size */

sys/dev/marvell/if_mvxpe.c

1321

reg |= MVXPE_PTXDQS_TBT(tx->tx_queue_th_free);

sys/dev/marvell/if_mvxpe.c

1322

MVXPE_WRITE(sc, MVXPE_PTXDQS(q), reg);

sys/dev/marvell/if_mvxpe.c

1325

reg = MVXPE_READ(sc, MVXPE_PRXTXTIM);

sys/dev/marvell/if_mvxpe.c

1326

reg |= MVXPE_PRXTXTI_TBTCQ(q); /* Tx Threshold cross */

sys/dev/marvell/if_mvxpe.c

1327

MVXPE_WRITE(sc, MVXPE_PRXTXTIM, reg);

sys/dev/marvell/if_mvxpe.c

1385

uint32_t reg;

sys/dev/marvell/if_mvxpe.c

1388

reg = MVXPE_READ(sc, MVXPE_PMIM);

sys/dev/marvell/if_mvxpe.c

1389

reg |= MVXPE_PMI_PHYSTATUSCHNG;

sys/dev/marvell/if_mvxpe.c

1390

reg |= MVXPE_PMI_LINKCHANGE;

sys/dev/marvell/if_mvxpe.c

1391

reg |= MVXPE_PMI_IAE;

sys/dev/marvell/if_mvxpe.c

1392

reg |= MVXPE_PMI_RXOVERRUN;

sys/dev/marvell/if_mvxpe.c

1393

reg |= MVXPE_PMI_RXCRCERROR;

sys/dev/marvell/if_mvxpe.c

1394

reg |= MVXPE_PMI_RXLARGEPACKET;

sys/dev/marvell/if_mvxpe.c

1395

reg |= MVXPE_PMI_TXUNDRN;

sys/dev/marvell/if_mvxpe.c

1401

reg |= MVXPE_PMI_PRBSERROR;

sys/dev/marvell/if_mvxpe.c

1402

reg |= MVXPE_PMI_SRSE;

sys/dev/marvell/if_mvxpe.c

1404

reg &= ~MVXPE_PMI_PRBSERROR;

sys/dev/marvell/if_mvxpe.c

1405

reg &= ~MVXPE_PMI_SRSE;

sys/dev/marvell/if_mvxpe.c

1407

reg |= MVXPE_PMI_TREQ_MASK;

sys/dev/marvell/if_mvxpe.c

1408

MVXPE_WRITE(sc, MVXPE_PMIM, reg);

sys/dev/marvell/if_mvxpe.c

1411

reg = MVXPE_READ(sc, MVXPE_PRXTXTIM);

sys/dev/marvell/if_mvxpe.c

1412

reg |= MVXPE_PRXTXTI_PMISCICSUMMARY;

sys/dev/marvell/if_mvxpe.c

1413

reg |= MVXPE_PRXTXTI_PTXERRORSUMMARY;

sys/dev/marvell/if_mvxpe.c

1414

reg |= MVXPE_PRXTXTI_PRXTXICSUMMARY;

sys/dev/marvell/if_mvxpe.c

1415

MVXPE_WRITE(sc, MVXPE_PRXTXTIM, reg);

sys/dev/marvell/if_mvxpe.c

1418

reg = MVXPE_READ(sc, MVXPE_PIE);

sys/dev/marvell/if_mvxpe.c

1419

reg |= MVXPE_PIE_RXPKTINTRPTENB_MASK;

sys/dev/marvell/if_mvxpe.c

1420

reg |= MVXPE_PIE_TXPKTINTRPTENB_MASK;

sys/dev/marvell/if_mvxpe.c

1421

MVXPE_WRITE(sc, MVXPE_PIE, reg);

sys/dev/marvell/if_mvxpe.c

1746

uint32_t reg;

sys/dev/marvell/if_mvxpe.c

1757

reg = MVXPE_READ(sc, MVXPE_PMACC0);

sys/dev/marvell/if_mvxpe.c

1758

reg |= MVXPE_PMACC0_PORTEN;

sys/dev/marvell/if_mvxpe.c

1759

MVXPE_WRITE(sc, MVXPE_PMACC0, reg);

sys/dev/marvell/if_mvxpe.c

1797

uint32_t reg;

sys/dev/marvell/if_mvxpe.c

1810

reg = MVXPE_READ(sc, MVXPE_PIE);

sys/dev/marvell/if_mvxpe.c

1811

reg &= ~MVXPE_PIE_RXPKTINTRPTENB_MASK;

sys/dev/marvell/if_mvxpe.c

1812

MVXPE_WRITE(sc, MVXPE_PIE, reg);

sys/dev/marvell/if_mvxpe.c

1814

reg = MVXPE_READ(sc, MVXPE_PRXTXTIM);

sys/dev/marvell/if_mvxpe.c

1815

reg &= ~MVXPE_PRXTXTI_RBICTAPQ_MASK;

sys/dev/marvell/if_mvxpe.c

1816

reg &= ~MVXPE_PRXTXTI_RDTAQ_MASK;

sys/dev/marvell/if_mvxpe.c

1817

MVXPE_WRITE(sc, MVXPE_PRXTXTIM, reg);

sys/dev/marvell/if_mvxpe.c

1820

reg = MVXPE_READ(sc, MVXPE_RQC) & MVXPE_RQC_EN_MASK;

sys/dev/marvell/if_mvxpe.c

1821

reg = MVXPE_RQC_DIS(reg);

sys/dev/marvell/if_mvxpe.c

1822

MVXPE_WRITE(sc, MVXPE_RQC, reg);

sys/dev/marvell/if_mvxpe.c

1827

"timeout for RX stopped. rqc 0x%x\n", reg);

sys/dev/marvell/if_mvxpe.c

1831

reg = MVXPE_READ(sc, MVXPE_RQC);

sys/dev/marvell/if_mvxpe.c

1832

} while (reg & MVXPE_RQC_EN_MASK);

sys/dev/marvell/if_mvxpe.c

1835

reg = MVXPE_READ(sc, MVXPE_PIE);

sys/dev/marvell/if_mvxpe.c

1836

reg &= ~MVXPE_PIE_TXPKTINTRPTENB_MASK;

sys/dev/marvell/if_mvxpe.c

1837

MVXPE_WRITE(sc, MVXPE_PIE, reg);

sys/dev/marvell/if_mvxpe.c

1839

reg = MVXPE_READ(sc, MVXPE_PRXTXTIM);

sys/dev/marvell/if_mvxpe.c

1840

reg &= ~MVXPE_PRXTXTI_TBTCQ_MASK;

sys/dev/marvell/if_mvxpe.c

1841

MVXPE_WRITE(sc, MVXPE_PRXTXTIM, reg);

sys/dev/marvell/if_mvxpe.c

1843

reg = MVXPE_READ(sc, MVXPE_TQC) & MVXPE_TQC_EN_MASK;

sys/dev/marvell/if_mvxpe.c

1844

reg = MVXPE_TQC_DIS(reg);

sys/dev/marvell/if_mvxpe.c

1845

MVXPE_WRITE(sc, MVXPE_TQC, reg);

sys/dev/marvell/if_mvxpe.c

1850

"timeout for TX stopped. tqc 0x%x\n", reg);

sys/dev/marvell/if_mvxpe.c

1854

reg = MVXPE_READ(sc, MVXPE_TQC);

sys/dev/marvell/if_mvxpe.c

1855

} while (reg & MVXPE_TQC_EN_MASK);

sys/dev/marvell/if_mvxpe.c

1862

"timeout for TX FIFO drained. ps0 0x%x\n", reg);

sys/dev/marvell/if_mvxpe.c

1866

reg = MVXPE_READ(sc, MVXPE_PS0);

sys/dev/marvell/if_mvxpe.c

1867

} while (!(reg & MVXPE_PS0_TXFIFOEMP) && (reg & MVXPE_PS0_TXINPROG));

sys/dev/marvell/if_mvxpe.c

1870

reg = MVXPE_READ(sc, MVXPE_PMACC0);

sys/dev/marvell/if_mvxpe.c

1871

reg &= ~MVXPE_PMACC0_PORTEN;

sys/dev/marvell/if_mvxpe.c

1872

MVXPE_WRITE(sc, MVXPE_PMACC0, reg);

sys/dev/marvell/if_mvxpe.c

1882

reg = MVXPE_PRXDQTH_ODT(rx->rx_queue_th_received);

sys/dev/marvell/if_mvxpe.c

1883

reg |= MVXPE_PRXDQTH_NODT(0);

sys/dev/marvell/if_mvxpe.c

1884

MVXPE_WRITE(sc, MVXPE_PRXITTH(q), reg);

sys/dev/marvell/if_mvxpe.c

2021

uint32_t reg;

sys/dev/marvell/if_mvxpe.c

2026

reg = MVXPE_READ(sc, MVXPE_LPIC1);

sys/dev/marvell/if_mvxpe.c

2028

reg |= MVXPE_LPIC1_LPIRE;

sys/dev/marvell/if_mvxpe.c

2030

reg &= ~MVXPE_LPIC1_LPIRE;

sys/dev/marvell/if_mvxpe.c

2031

MVXPE_WRITE(sc, MVXPE_LPIC1, reg);

sys/dev/marvell/if_mvxpe.c

2034

reg = MVXPE_READ(sc, MVXPE_PANC);

sys/dev/marvell/if_mvxpe.c

2037

reg |= MVXPE_PANC_PAUSEADV;

sys/dev/marvell/if_mvxpe.c

2038

reg |= MVXPE_PANC_ANFCEN;

sys/dev/marvell/if_mvxpe.c

2041

reg &= ~MVXPE_PANC_PAUSEADV;

sys/dev/marvell/if_mvxpe.c

2042

reg &= ~MVXPE_PANC_ANFCEN;

sys/dev/marvell/if_mvxpe.c

2044

reg &= ~MVXPE_PANC_FORCELINKFAIL;

sys/dev/marvell/if_mvxpe.c

2045

reg &= ~MVXPE_PANC_FORCELINKPASS;

sys/dev/marvell/if_mvxpe.c

2046

MVXPE_WRITE(sc, MVXPE_PANC, reg);

sys/dev/marvell/if_mvxpe.c

2055

uint32_t reg;

sys/dev/marvell/if_mvxpe.c

2060

reg = MVXPE_READ(sc, MVXPE_PANC);

sys/dev/marvell/if_mvxpe.c

2061

reg |= MVXPE_PANC_FORCELINKFAIL;

sys/dev/marvell/if_mvxpe.c

2062

reg &= MVXPE_PANC_FORCELINKPASS;

sys/dev/marvell/if_mvxpe.c

2063

MVXPE_WRITE(sc, MVXPE_PANC, reg);

sys/dev/marvell/if_mvxpe.c

2877

uint32_t reg;

sys/dev/marvell/if_mvxpe.c

2933

reg = MVXPE_PRXDQTH_ODT(rx->rx_queue_th_received);

sys/dev/marvell/if_mvxpe.c

2934

reg |= MVXPE_PRXDQTH_NODT(rx->rx_queue_th_free);

sys/dev/marvell/if_mvxpe.c

2935

MVXPE_WRITE(sc, MVXPE_PRXDQTH(arg->queue), reg);

sys/dev/marvell/if_mvxpe.c

2945

reg = MVXPE_PTXDQS_TBT(tx->tx_queue_th_free);

sys/dev/marvell/if_mvxpe.c

2946

reg |= MVXPE_PTXDQS_DQS(MVXPE_TX_RING_CNT);

sys/dev/marvell/if_mvxpe.c

2947

MVXPE_WRITE(sc, MVXPE_PTXDQS(arg->queue), reg);

sys/dev/marvell/if_mvxpe.c

2965

uint32_t reg, time_mvtclk;

sys/dev/marvell/if_mvxpe.c

3008

reg = MVXPE_PRXITTH_RITT(rx->rx_queue_th_time);

sys/dev/marvell/if_mvxpe.c

3009

MVXPE_WRITE(sc, MVXPE_PRXITTH(arg->queue), reg);

sys/dev/marvell/if_mvxpe.c

3010

DPRINTSC(sc, 1, "RXITTH(%d) => %#x\n", arg->queue, reg);

sys/dev/marvell/if_mvxpe.c

686

mvxpe_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val)

sys/dev/marvell/if_mvxpe.c

707

MVXPE_SMI_PHYAD(phy) | MVXPE_SMI_REGAD(reg) | MVXPE_SMI_OPCODE_READ;

sys/dev/marvell/if_mvxpe.c

725

DPRINTDEV(dev, 9, "phy=%d, reg=%#x, val=%#hx\n", phy, reg, *val);

sys/dev/marvell/if_mvxpe.c

731

mvxpe_miibus_writereg(device_t dev, int phy, int reg, uint16_t val)

sys/dev/marvell/if_mvxpe.c

738

DPRINTDEV(dev, 9, "phy=%d reg=%#x val=%#hx\n", phy, reg, val);

sys/dev/marvell/if_mvxpe.c

753

smi = MVXPE_SMI_PHYAD(phy) | MVXPE_SMI_REGAD(reg) |

sys/dev/marvell/if_mvxpe.c

844

uint32_t reg;

sys/dev/marvell/if_mvxpe.c

874

reg = MVXPE_READ(sc, MVXPE_PMACC0);

sys/dev/marvell/if_mvxpe.c

875

if ((reg & MVXPE_PMACC0_PORTTYPE) != 0)

sys/dev/marvell/if_mvxpe.c

879

reg = MVXPE_READ(sc, MVXPE_EUC);

sys/dev/marvell/if_mvxpe.c

880

reg |= MVXPE_EUC_POLLING;

sys/dev/marvell/if_mvxpe.c

881

MVXPE_WRITE(sc, MVXPE_EUC, reg);

sys/dev/marvell/if_mvxpe.c

884

reg = MVXPE_PANC_MUSTSET; /* must write 0x1 */

sys/dev/marvell/if_mvxpe.c

885

reg |= MVXPE_PANC_FORCELINKFAIL;/* force link state down */

sys/dev/marvell/if_mvxpe.c

886

reg |= MVXPE_PANC_ANSPEEDEN; /* interface speed negotiation */

sys/dev/marvell/if_mvxpe.c

887

reg |= MVXPE_PANC_ANDUPLEXEN; /* negotiate duplex mode */

sys/dev/marvell/if_mvxpe.c

889

reg |= MVXPE_PANC_INBANDANEN; /* In Band negotiation */

sys/dev/marvell/if_mvxpe.c

890

reg |= MVXPE_PANC_INBANDANBYPASSEN; /* bypass negotiation */

sys/dev/marvell/if_mvxpe.c

891

reg |= MVXPE_PANC_SETFULLDX; /* set full-duplex on failure */

sys/dev/marvell/if_mvxpe.c

893

MVXPE_WRITE(sc, MVXPE_PANC, reg);

sys/dev/marvell/if_mvxpe.c

896

reg = MVXPE_LPIC0_LILIMIT(MVXPE_LPI_LI);

sys/dev/marvell/if_mvxpe.c

897

reg |= MVXPE_LPIC0_TSLIMIT(MVXPE_LPI_TS);

sys/dev/marvell/if_mvxpe.c

898

MVXPE_WRITE(sc, MVXPE_LPIC0, reg);

sys/dev/marvell/if_mvxpe.c

900

reg = MVXPE_LPIC1_TWLIMIT(MVXPE_LPI_TS);

sys/dev/marvell/if_mvxpe.c

901

MVXPE_WRITE(sc, MVXPE_LPIC1, reg);

sys/dev/marvell/if_mvxpe.c

903

reg = MVXPE_LPIC2_MUSTSET;

sys/dev/marvell/if_mvxpe.c

904

MVXPE_WRITE(sc, MVXPE_LPIC2, reg);

sys/dev/marvell/if_mvxpe.c

907

reg = MVXPE_PMACC0_MUSTSET; /* must write 0x1 */

sys/dev/marvell/if_mvxpe.c

908

reg &= ~MVXPE_PMACC0_PORTEN; /* port is still disabled */

sys/dev/marvell/if_mvxpe.c

909

reg |= MVXPE_PMACC0_FRAMESIZELIMIT(MVXPE_MRU);

sys/dev/marvell/if_mvxpe.c

911

reg |= MVXPE_PMACC0_PORTTYPE;

sys/dev/marvell/if_mvxpe.c

912

MVXPE_WRITE(sc, MVXPE_PMACC0, reg);

sys/dev/marvell/if_mvxpe.c

917

reg = MVXPE_READ(sc, MVXPE_PMACC2);

sys/dev/marvell/if_mvxpe.c

918

reg &= (MVXPE_PMACC2_PCSEN | MVXPE_PMACC2_RGMIIEN);

sys/dev/marvell/if_mvxpe.c

919

reg |= MVXPE_PMACC2_MUSTSET;

sys/dev/marvell/if_mvxpe.c

920

MVXPE_WRITE(sc, MVXPE_PMACC2, reg);

sys/dev/marvell/if_mvxpe.c

928

reg = MVXPE_READ(sc, MVXPE_PXC);

sys/dev/marvell/if_mvxpe.c

929

reg &= ~(MVXPE_PXC_RXQ_MASK | MVXPE_PXC_RXQARP_MASK |

sys/dev/marvell/if_mvxpe.c

931

MVXPE_WRITE(sc, MVXPE_PXC, reg);

sys/dev/marvell/if_mvxpe.c

934

reg = MVXPE_READ(sc, MVXPE_PXCX);

sys/dev/marvell/if_mvxpe.c

935

reg &= ~MVXPE_PXCX_TXCRCDIS;

sys/dev/marvell/if_mvxpe.c

936

MVXPE_WRITE(sc, MVXPE_PXCX, reg);

sys/dev/marvell/if_mvxpe.c

943

reg = MVXPE_SDC_RXBSZ_16_64BITWORDS;

sys/dev/marvell/if_mvxpe.c

944

reg |= MVXPE_SDC_TXBSZ_16_64BITWORDS;

sys/dev/marvell/if_mvxpe.c

945

reg |= MVXPE_SDC_BLMR;

sys/dev/marvell/if_mvxpe.c

946

reg |= MVXPE_SDC_BLMT;

sys/dev/marvell/if_mvxpe.c

947

MVXPE_WRITE(sc, MVXPE_SDC, reg);

sys/dev/marvell/if_mvxpereg.h

317

#define MVXPE_PHYADDR_GET_PHYAD(reg) ((reg) & 0x1f)

sys/dev/marvell/if_mvxpereg.h

322

#define MVXPE_SMI_REGAD(reg) (((reg) & 0x1f) << 21)

sys/dev/marvell/if_mvxpereg.h

387

#define MVXPE_PV_GET_VERSION(reg) ((reg) & 0xff)

sys/dev/marvell/if_mvxpereg.h

445

#define MVXPE_PRXS_GET_ODC(reg) (((reg) >> 0) & 0x3fff)

sys/dev/marvell/if_mvxpereg.h

446

#define MVXPE_PRXS_GET_NODC(reg) (((reg) >> 16) & 0x3fff)

sys/dev/marvell/if_mvxpereg.h

486

#define MVXPE_PTXS_GET_TBC(reg) (((reg) >> 16) & 0x3fff)

sys/dev/marvell/if_mvxpereg.h

708

#define MVXPE_PRXTXTI_GET_TBTCQ(reg) (((reg) >> 0) & 0xff)

sys/dev/marvell/if_mvxpereg.h

712

#define MVXPE_PRXTXTI_GET_RBICTAPQ(reg) (((reg) >> 8) & 0xff)

sys/dev/marvell/if_mvxpereg.h

716

#define MVXPE_PRXTXTI_GET_RDTAQ(reg) (((reg) >> 16) & 0xff)

sys/dev/marvell/if_mvxpereg.h

725

#define MVXPE_PRXTXI_GET_TBRQ(reg) (((reg) >> 0) & 0xff)

sys/dev/marvell/if_mvxpereg.h

728

#define MVXPE_PRXTXI_GET_RPQ(reg) (((reg) >> 8) & 0xff)

sys/dev/marvell/if_mvxpereg.h

731

#define MVXPE_PRXTXI_GET_RREQ(reg) (((reg) >> 16) & 0xff)

sys/dev/marvell/if_mvxpereg.h

760

#define MVXPE_PEUIAE_GET_ADDR(reg) ((reg) & 0x3fff)

sys/dev/marvell/if_mvxpevar.h

348

#define DPRINTPRXS(level, reg)

sys/dev/marvell/if_mvxpevar.h

72

#define MVXPE_READ(sc, reg) \

sys/dev/marvell/if_mvxpevar.h

73

bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg))

sys/dev/marvell/if_mvxpevar.h

74

#define MVXPE_WRITE(sc, reg, val) \

sys/dev/marvell/if_mvxpevar.h

75

bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))

sys/dev/marvell/if_mvxpevar.h

77

#define MVXPE_READ_REGION(sc, reg, val, c) \

sys/dev/marvell/if_mvxpevar.h

78

bus_space_read_region_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val), (c))

sys/dev/marvell/if_mvxpevar.h

79

#define MVXPE_WRITE_REGION(sc, reg, val, c) \

sys/dev/marvell/if_mvxpevar.h

80

bus_space_write_region_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val), (c))

sys/dev/marvell/if_mvxpevar.h

82

#define MVXPE_READ_MIB(sc, reg) \

sys/dev/marvell/if_mvxpevar.h

83

bus_space_read_4((sc)->sc_iot, (sc)->sc_mibh, (reg))

sys/dev/marvell/mvgbereg.h

249

#define MVGBE_SMI_REGAD(reg) (((reg) & 0x1f) << 21)

sys/dev/marvell/mvpex.c

239

uint32_t reg;

sys/dev/marvell/mvpex.c

249

reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 0x1b00);

sys/dev/marvell/mvpex.c

251

reg &= ~0x7; /* Clear bits [2:0] */

sys/dev/marvell/mvpex.c

252

reg |= 0x4; /* Set the new value */

sys/dev/marvell/mvpex.c

253

reg &= ~0x80000000; /* Set "write" command */

sys/dev/marvell/mvpex.c

254

bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0x1b00, reg);

sys/dev/marvell/mvpex.c

496

mvpex_conf_read(void *v, pcitag_t tag, int reg)

sys/dev/marvell/mvpex.c

503

if ((unsigned int)reg >= PCI_EXTCONF_SIZE)

sys/dev/marvell/mvpex.c

527

addr = ((reg & 0xf00) << 24) | tag | (reg & 0xfc);

sys/dev/marvell/mvpex.c

544

mvpex_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data)

sys/dev/marvell/mvpex.c

551

if ((unsigned int)reg >= PCI_EXTCONF_SIZE)

sys/dev/marvell/mvpex.c

575

addr = ((reg & 0xf00) << 24) | tag | (reg & 0xfc);

sys/dev/marvell/mvsdio.c

424

uint32_t reg;

sys/dev/marvell/mvsdio.c

428

reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, MVSDIO_HC);

sys/dev/marvell/mvsdio.c

429

reg &= ~HC_PUSHPULLEN;

sys/dev/marvell/mvsdio.c

430

bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVSDIO_HC, reg);

sys/dev/marvell/mvsdio.c

440

uint32_t reg;

sys/dev/marvell/mvsdio.c

444

reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, MVSDIO_TM);

sys/dev/marvell/mvsdio.c

449

reg | TM_STOPCLKEN);

sys/dev/marvell/mvsdio.c

459

reg & ~TM_STOPCLKEN);

sys/dev/marvell/mvsdio.c

461

reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, MVSDIO_HC);

sys/dev/marvell/mvsdio.c

463

reg |= HC_HISPEEDEN;

sys/dev/marvell/mvsdio.c

465

reg &= ~HC_HISPEEDEN; /* up to 25 MHz */

sys/dev/marvell/mvsdio.c

466

bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVSDIO_HC, reg);

sys/dev/marvell/mvsdio.c

478

uint32_t reg, v;

sys/dev/marvell/mvsdio.c

496

reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, MVSDIO_HC);

sys/dev/marvell/mvsdio.c

497

reg &= ~HC_DATAWIDTH;

sys/dev/marvell/mvsdio.c

498

reg |= v;

sys/dev/marvell/mvsdio.c

499

bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVSDIO_HC, reg);

sys/dev/marvell/mvsdio.c

509

uint32_t reg;

sys/dev/marvell/mvsdio.c

513

reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, MVSDIO_HC);

sys/dev/marvell/mvsdio.c

515

reg &= ~HC_PUSHPULLEN;

sys/dev/marvell/mvsdio.c

517

reg |= HC_PUSHPULLEN;

sys/dev/marvell/mvsdio.c

518

bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVSDIO_HC, reg);

sys/dev/marvell/mvsdio.c

675

uint32_t reg;

sys/dev/marvell/mvsdio.c

678

reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, MVSDIO_NISIE);

sys/dev/marvell/mvsdio.c

679

reg |= NIS_CARDINT;

sys/dev/marvell/mvsdio.c

680

bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVSDIO_NISIE, reg);

sys/dev/marvell/mvxpsec.c

1222

uint32_t reg;

sys/dev/marvell/mvxpsec.c

1224

reg = MVXPSEC_READ(sc, MVXPSEC_INT_CAUSE);

sys/dev/marvell/mvxpsec.c

1225

reg &= MVXPSEC_DEFAULT_INT;

sys/dev/marvell/mvxpsec.c

1226

MVXPSEC_WRITE(sc, MVXPSEC_INT_CAUSE, ~reg);

sys/dev/marvell/mvxpsec.c

1227

MVXPSEC_PRINTF(MVXPSEC_DEBUG_INTR, "Int: %s\n", s_xpsecintr(reg));

sys/dev/marvell/mvxpsec.c

1229

return reg;

sys/dev/marvell/mvxpsec.c

1269

uint32_t reg;

sys/dev/marvell/mvxpsec.c

1271

reg = MVXPSEC_READ(sc, MV_TDMA_ERR_CAUSE);

sys/dev/marvell/mvxpsec.c

1272

reg &= MVXPSEC_DEFAULT_ERR;

sys/dev/marvell/mvxpsec.c

1273

MVXPSEC_WRITE(sc, MV_TDMA_ERR_CAUSE, ~reg);

sys/dev/marvell/mvxpsec.c

1274

MVXPSEC_PRINTF(MVXPSEC_DEBUG_INTR, "Int: %s\n", s_xpsecintr(reg));

sys/dev/marvell/mvxpsec.c

1276

return reg;

sys/dev/marvell/mvxpsec.c

3098

uint32_t reg;

sys/dev/marvell/mvxpsec.c

3102

reg = MV_ACC_CRYPTO_ENC_DES;

sys/dev/marvell/mvxpsec.c

3103

reg |= MV_ACC_CRYPTO_CBC;

sys/dev/marvell/mvxpsec.c

3106

reg = MV_ACC_CRYPTO_ENC_3DES;

sys/dev/marvell/mvxpsec.c

3107

reg |= MV_ACC_CRYPTO_3DES_EDE;

sys/dev/marvell/mvxpsec.c

3108

reg |= MV_ACC_CRYPTO_CBC;

sys/dev/marvell/mvxpsec.c

3111

reg = MV_ACC_CRYPTO_ENC_AES;

sys/dev/marvell/mvxpsec.c

3112

reg |= MV_ACC_CRYPTO_CBC;

sys/dev/marvell/mvxpsec.c

3115

reg = MV_ACC_CRYPTO_MAC_HMAC_SHA1;

sys/dev/marvell/mvxpsec.c

3116

reg |= MV_ACC_CRYPTO_MAC_96;

sys/dev/marvell/mvxpsec.c

3119

reg = MV_ACC_CRYPTO_MAC_HMAC_MD5;

sys/dev/marvell/mvxpsec.c

3120

reg |= MV_ACC_CRYPTO_MAC_96;

sys/dev/marvell/mvxpsec.c

3123

reg = 0;

sys/dev/marvell/mvxpsec.c

3127

return reg;

sys/dev/marvell/mvxpsec.c

3178

s_ctrlreg(uint32_t reg)

sys/dev/marvell/mvxpsec.c

3184

(reg & MV_TDMA_CONTROL_ENABLE) ? "ENABLE" : "DISABLE",

sys/dev/marvell/mvxpsec.c

3185

(reg & MV_TDMA_CONTROL_FETCH) ? "+" : "-",

sys/dev/marvell/mvxpsec.c

3186

MV_TDMA_CONTROL_GET_DST_BURST(reg),

sys/dev/marvell/mvxpsec.c

3187

MV_TDMA_CONTROL_GET_SRC_BURST(reg),

sys/dev/marvell/mvxpsec.c

3188

(reg & MV_TDMA_CONTROL_OUTS_EN) ? "+" : "-",

sys/dev/marvell/mvxpsec.c

3189

(reg & MV_TDMA_CONTROL_CHAIN_DIS) ? "-" : "+",

sys/dev/marvell/mvxpsec.c

3190

(reg & MV_TDMA_CONTROL_BSWAP_DIS) ? "-" : "+",

sys/dev/marvell/mvxpsec.c

3191

(reg & MV_TDMA_CONTROL_ACT) ? "+" : "-");

sys/dev/marvell/mvxpsec.c

3248

s_xpsec_op(uint32_t reg)

sys/dev/marvell/mvxpsec.c

3250

reg &= MV_ACC_CRYPTO_OP_MASK;

sys/dev/marvell/mvxpsec.c

3251

switch (reg) {

sys/dev/marvell/mvxpsec.c

3331

uint32_t reg;

sys/dev/marvell/mvxpsec.c

3338

reg = MVXPSEC_READ(sc, MVXPSEC_INT_CAUSE);

sys/dev/marvell/mvxpsec.c

3339

printf("MVXPSEC INT CAUSE: 0x%08x\n", reg);

sys/dev/marvell/mvxpsec.c

3340

printf("MVXPSEC INT CAUSE: %s\n", s_xpsecintr(reg));

sys/dev/marvell/mvxpsec.c

3341

reg = MVXPSEC_READ(sc, MVXPSEC_INT_MASK);

sys/dev/marvell/mvxpsec.c

3342

printf("MVXPSEC INT MASK: 0x%08x\n", reg);

sys/dev/marvell/mvxpsec.c

3343

printf("MVXPSEC INT MASKE: %s\n", s_xpsecintr(reg));

sys/dev/marvell/mvxpsec.c

3347

reg = MVXPSEC_READ(sc, MV_TDMA_BAR(i));

sys/dev/marvell/mvxpsec.c

3348

printf("TDMA BAR%d: 0x%08x\n", i, reg);

sys/dev/marvell/mvxpsec.c

3349

reg = MVXPSEC_READ(sc, MV_TDMA_ATTR(i));

sys/dev/marvell/mvxpsec.c

3350

printf("TDMA ATTR%d: 0x%08x\n", i, reg);

sys/dev/marvell/mvxpsec.c

3351

printf(" -> %s\n", s_winreg(reg));

sys/dev/marvell/mvxpsec.c

3356

reg = MVXPSEC_READ(sc, MV_TDMA_CONTROL);

sys/dev/marvell/mvxpsec.c

3357

printf("TDMA CONTROL: 0x%08x\n", reg);

sys/dev/marvell/mvxpsec.c

3358

printf(" -> %s\n", s_ctrlreg(reg));

sys/dev/marvell/mvxpsec.c

3362

reg = MVXPSEC_READ(sc, MV_TDMA_ERR_CAUSE);

sys/dev/marvell/mvxpsec.c

3363

printf("TDMA ERR CAUSE: 0x%08x\n", reg);

sys/dev/marvell/mvxpsec.c

3365

reg = MVXPSEC_READ(sc, MV_TDMA_ERR_MASK);

sys/dev/marvell/mvxpsec.c

3366

printf("TDMA ERR MASK: 0x%08x\n", reg);

sys/dev/marvell/mvxpsec.c

3368

reg = MVXPSEC_READ(sc, MV_TDMA_CNT);

sys/dev/marvell/mvxpsec.c

3370

(reg & MV_TDMA_CNT_OWN) ? "DMAC" : "CPU");

sys/dev/marvell/mvxpsec.c

3372

(reg & ~MV_TDMA_CNT_OWN), (reg & ~MV_TDMA_CNT_OWN));

sys/dev/marvell/mvxpsec.c

3374

reg = MVXPSEC_READ(sc, MV_TDMA_SRC);

sys/dev/marvell/mvxpsec.c

3375

printf("TDMA DATA SRC: 0x%08x\n", reg);

sys/dev/marvell/mvxpsec.c

3377

reg = MVXPSEC_READ(sc, MV_TDMA_DST);

sys/dev/marvell/mvxpsec.c

3378

printf("TDMA DATA DST: 0x%08x\n", reg);

sys/dev/marvell/mvxpsec.c

3380

reg = MVXPSEC_READ(sc, MV_TDMA_NXT);

sys/dev/marvell/mvxpsec.c

3381

printf("TDMA DATA NXT: 0x%08x\n", reg);

sys/dev/marvell/mvxpsec.c

3383

reg = MVXPSEC_READ(sc, MV_TDMA_CUR);

sys/dev/marvell/mvxpsec.c

3384

printf("TDMA DATA CUR: 0x%08x\n", reg);

sys/dev/marvell/mvxpsec.c

3387

reg = MVXPSEC_READ(sc, MV_ACC_COMMAND);

sys/dev/marvell/mvxpsec.c

3388

printf("ACC COMMAND: 0x%08x\n", reg);

sys/dev/marvell/mvxpsec.c

3390

(reg & MV_ACC_COMMAND_ACT) ? "+" : "-",

sys/dev/marvell/mvxpsec.c

3391

(reg & MV_ACC_COMMAND_STOP) ? "+" : "-");

sys/dev/marvell/mvxpsec.c

3393

reg = MVXPSEC_READ(sc, MV_ACC_CONFIG);

sys/dev/marvell/mvxpsec.c

3394

printf("ACC CONFIG: 0x%08x\n", reg);

sys/dev/marvell/mvxpsec.c

3395

reg = MVXPSEC_READ(sc, MV_ACC_DESC);

sys/dev/marvell/mvxpsec.c

3396

printf("ACC DESC: 0x%08x\n", reg);

sys/dev/marvell/mvxpsec.c

3399

reg = MVXPSEC_READ(sc, MV_CE_DES_KEY0L);

sys/dev/marvell/mvxpsec.c

3400

printf("DES KEY0 Low: 0x%08x\n", reg);

sys/dev/marvell/mvxpsec.c

3401

reg = MVXPSEC_READ(sc, MV_CE_DES_KEY0H);

sys/dev/marvell/mvxpsec.c

3402

printf("DES KEY0 High: 0x%08x\n", reg);

sys/dev/marvell/mvxpsec.c

3403

reg = MVXPSEC_READ(sc, MV_CE_DES_KEY1L);

sys/dev/marvell/mvxpsec.c

3404

printf("DES KEY1 Low: 0x%08x\n", reg);

sys/dev/marvell/mvxpsec.c

3405

reg = MVXPSEC_READ(sc, MV_CE_DES_KEY1H);

sys/dev/marvell/mvxpsec.c

3406

printf("DES KEY1 High: 0x%08x\n", reg);

sys/dev/marvell/mvxpsec.c

3407

reg = MVXPSEC_READ(sc, MV_CE_DES_KEY2L);

sys/dev/marvell/mvxpsec.c

3408

printf("DES KEY2 Low: 0x%08x\n", reg);

sys/dev/marvell/mvxpsec.c

3409

reg = MVXPSEC_READ(sc, MV_CE_DES_KEY2H);

sys/dev/marvell/mvxpsec.c

3410

printf("DES KEY2 High: 0x%08x\n", reg);

sys/dev/marvell/mvxpsec.c

3414

reg = MVXPSEC_READ(sc, MV_CE_AES_EKEY(i));

sys/dev/marvell/mvxpsec.c

3415

printf("AES ENC KEY COL%d: %08x\n", i, reg);

sys/dev/marvell/mvxpsec.c

3418

reg = MVXPSEC_READ(sc, MV_CE_AES_DKEY(i));

sys/dev/marvell/mvxpsec.c

3419

printf("AES DEC KEY COL%d: %08x\n", i, reg);

sys/dev/marvell/mvxpsec.c

3428

uint32_t reg;

sys/dev/marvell/mvxpsec.c

3441

reg = MVXPSEC_READ(sc, MV_TDMA_CONTROL);

sys/dev/marvell/mvxpsec.c

3442

if (reg & MV_TDMA_CONTROL_ACT) {

sys/dev/marvell/mvxpsec.c

3447

reg = MVXPSEC_READ(sc, MV_ACC_COMMAND);

sys/dev/marvell/mvxpsec.c

3448

if (reg & MV_ACC_COMMAND_ACT) {

sys/dev/marvell/mvxpsec.c

523

uint32_t size, reg;

sys/dev/marvell/mvxpsec.c

546

reg = MV_TDMA_BAR_BASE(base);

sys/dev/marvell/mvxpsec.c

547

MVXPSEC_WRITE(sc, MV_TDMA_BAR(window), reg);

sys/dev/marvell/mvxpsec.c

549

reg = MV_TDMA_ATTR_TARGET(target);

sys/dev/marvell/mvxpsec.c

550

reg |= MV_TDMA_ATTR_ATTR(attr);

sys/dev/marvell/mvxpsec.c

551

reg |= MV_TDMA_ATTR_SIZE(size);

sys/dev/marvell/mvxpsec.c

552

reg |= MV_TDMA_ATTR_ENABLE;

sys/dev/marvell/mvxpsec.c

553

MVXPSEC_WRITE(sc, MV_TDMA_ATTR(window), reg);

sys/dev/marvell/mvxpsec.c

569

uint32_t reg;

sys/dev/marvell/mvxpsec.c

611

reg = MV_TDMA_DEFAULT_CONTROL;

sys/dev/marvell/mvxpsec.c

612

reg |= MV_TDMA_CONTROL_ENABLE;

sys/dev/marvell/mvxpsec.c

613

MVXPSEC_WRITE(sc, MV_TDMA_CONTROL, reg);

sys/dev/marvell/mvxpsec.c

617

reg = MV_ACC_CONFIG_MULT_PKT;

sys/dev/marvell/mvxpsec.c

618

reg |= MV_ACC_CONFIG_WAIT_TDMA;

sys/dev/marvell/mvxpsec.c

619

reg |= MV_ACC_CONFIG_ACT_TDMA;

sys/dev/marvell/mvxpsec.c

620

MVXPSEC_WRITE(sc, MV_ACC_CONFIG, reg);

sys/dev/marvell/mvxpsecreg.h

212

#define MV_TDMA_ATTR_GET_SIZE(reg) (((reg) >> 16) & 0xffff)

sys/dev/marvell/mvxpsecreg.h

213

#define MV_TDMA_ATTR_GET_ATTR(reg) (((reg) >> 8) & 0xff)

sys/dev/marvell/mvxpsecreg.h

214

#define MV_TDMA_ATTR_GET_TARGET(reg) (((reg) >> 4) & 0xf)

sys/dev/marvell/mvxpsecreg.h

222

#define MV_TDMA_CONTROL_GET_DST_BURST(reg) \

sys/dev/marvell/mvxpsecreg.h

223

((uint32_t)(((reg) & MV_TDMA_CONTROL_DST_BURST_MASK) >> 0))

sys/dev/marvell/mvxpsecreg.h

228

#define MV_TDMA_CONTROL_GET_SRC_BURST(reg) \

sys/dev/marvell/mvxpsecreg.h

229

((uint32_t)(((reg) & MV_TDMA_CONTROL_SRC_BURST_MASK) >> 6))

sys/dev/mca/esp_mca.c

264

esp_read_reg(struct ncr53c9x_softc *sc, int reg)

sys/dev/mca/esp_mca.c

268

return bus_space_read_1(esc->sc_iot, esc->sc_esp_ioh, reg);

sys/dev/mca/esp_mca.c

272

esp_write_reg(struct ncr53c9x_softc *sc, int reg, uint8_t val)

sys/dev/mca/esp_mca.c

276

bus_space_write_1(esc->sc_iot, esc->sc_esp_ioh, reg, val);

sys/dev/mca/mca.c

136

int reg;

sys/dev/mca/mca.c

145

for(reg = 0; reg < 8; reg++)

sys/dev/mca/mca.c

146

ma.ma_pos[reg]=mca_conf_read(mc, slot, reg);

sys/dev/microcode/siop/ncr53cxxx.c

1107

int reg, size;

sys/dev/microcode/siop/ncr53cxxx.c

1109

reg = CheckRegister(i);

sys/dev/microcode/siop/ncr53cxxx.c

1110

if (reg < 0)

sys/dev/microcode/siop/ncr53cxxx.c

1113

inst0 |= reg << 16;

sys/dev/microcode/siop/ncr53cxxx.c

1114

if (reg == 8)

sys/dev/microcode/siop/ncr53cxxx.c

1124

if ((reg & 0x3) + size > 4)

sys/dev/microcode/siop/ncr53cxxx.c

1334

int reg;

sys/dev/microcode/siop/ncr53cxxx.c

1364

reg = CheckRegister (tokenix);

sys/dev/microcode/siop/ncr53cxxx.c

1365

if (reg < 0) { /* Not register, must be data */

sys/dev/microcode/siop/ncr53cxxx.c

1369

reg = CheckRegister (tokenix+2);

sys/dev/microcode/siop/ncr53cxxx.c

1370

if (reg < 0)

sys/dev/microcode/siop/ncr53cxxx.c

1372

inst0 = 0x78000000 | (data << 8) | reg << 16;

sys/dev/microcode/siop/ncr53cxxx.c

1374

fprintf (listfp, "Move data to register: %02x %d\n", data, reg);

sys/dev/microcode/siop/ncr53cxxx.c

1417

if (reg != data && reg != 8 && data != 8)

sys/dev/microcode/siop/ncr53cxxx.c

1419

if (reg == data) { /* A register read/modify/write */

sys/dev/microcode/siop/ncr53cxxx.c

1421

fprintf (listfp, "Read/modify register: %02x %d %d\n", inst0 >> 8, op, reg);

sys/dev/microcode/siop/ncr53cxxx.c

1423

inst0 |= 0x78000000 | (op << 24) | (reg << 16);

sys/dev/microcode/siop/ncr53cxxx.c

1426

if (reg == 8) { /* MOVE SFBR <> TO reg */

sys/dev/microcode/siop/ncr53cxxx.c

1434

fprintf (listfp, "Move register to SFBR: %02x %d %d\n", inst0 >> 8, op, reg);

sys/dev/microcode/siop/ncr53cxxx.c

1436

inst0 |= 0x70000000 | (op << 24) | (reg << 16);

sys/dev/microcode/siop/ncr53cxxx.c

1443

if (reg == 8) /* move SFBR to reg */

sys/dev/microcode/siop/ncr53cxxx.c

1446

inst0 = 0x72000000 | (reg << 16);

sys/dev/mii/acphy.c

147

uint16_t reg;

sys/dev/mii/acphy.c

164

PHY_READ(sc, MII_BMCR, &reg);

sys/dev/mii/acphy.c

165

PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);

sys/dev/mii/amhphy.c

125

uint16_t reg;

sys/dev/mii/amhphy.c

142

PHY_READ(sc, MII_BMCR, &reg);

sys/dev/mii/amhphy.c

143

PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);

sys/dev/mii/atphy.c

127

uint16_t reg = 0;

sys/dev/mii/atphy.c

137

PHY_READ(sc, 0x0e, &reg);

sys/dev/mii/atphy.c

138

PHY_WRITE(sc, 0x0e, reg | __SHIFTIN(data, __BITS(4, 3)));

sys/dev/mii/atphy.c

411

uint16_t reg;

sys/dev/mii/atphy.c

438

(void)PHY_READ(sc, ATPHY_SCR, &reg);

sys/dev/mii/atphy.c

440

PHY_READ(sc, ATPHY_SCR, &reg);

sys/dev/mii/atphy.c

442

reg |= ATPHY_SCR_AUTO_X_MODE;

sys/dev/mii/atphy.c

444

reg &= ~ATPHY_SCR_MAC_PDOWN;

sys/dev/mii/atphy.c

446

reg |= ATPHY_SCR_ASSERT_CRS_ON_TX;

sys/dev/mii/atphy.c

448

reg |= ATPHY_SCR_POLARITY_REVERSAL;

sys/dev/mii/atphy.c

449

PHY_WRITE(sc, ATPHY_SCR, reg);

sys/dev/mii/atphy.c

454

PHY_READ(sc, MII_BMCR, &reg);

sys/dev/mii/atphy.c

455

reg |= BMCR_RESET;

sys/dev/mii/atphy.c

456

PHY_WRITE(sc, MII_BMCR, reg);

sys/dev/mii/atphy.c

460

PHY_READ(sc, MII_BMCR, &reg);

sys/dev/mii/atphy.c

461

if ((reg & BMCR_RESET) == 0)

sys/dev/mii/bmtphy.c

156

uint16_t reg;

sys/dev/mii/bmtphy.c

173

PHY_READ(sc, MII_BMCR, &reg);

sys/dev/mii/bmtphy.c

174

PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);

sys/dev/mii/brgphy.c

1003

PHY_READ(sc, BRGPHY_MRBE_MSG_PG5_NP, &reg);

sys/dev/mii/brgphy.c

1005

reg | BRGPHY_MRBE_MSG_PG5_NP_MBRE |

sys/dev/mii/brgphy.c

1050

int reg;

sys/dev/mii/brgphy.c

1068

for (i = 0; dspcode[i].reg != 0; i++)

sys/dev/mii/brgphy.c

1069

PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);

sys/dev/mii/brgphy.c

1077

int reg;

sys/dev/mii/brgphy.c

1087

for (i = 0; dspcode[i].reg != 0; i++)

sys/dev/mii/brgphy.c

1088

PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);

sys/dev/mii/brgphy.c

1114

int reg;

sys/dev/mii/brgphy.c

1123

for (i = 0; dspcode[i].reg != 0; i++)

sys/dev/mii/brgphy.c

1124

PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);

sys/dev/mii/brgphy.c

1131

int reg;

sys/dev/mii/brgphy.c

1144

for (i = 0; dspcode[i].reg != 0; i++)

sys/dev/mii/brgphy.c

1145

PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);

sys/dev/mii/brgphy.c

1152

int reg;

sys/dev/mii/brgphy.c

1161

for (i = 0; dspcode[i].reg != 0; i++)

sys/dev/mii/brgphy.c

1162

PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);

sys/dev/mii/brgphy.c

1169

int reg;

sys/dev/mii/brgphy.c

1184

for (i = 0; dspcode[i].reg != 0; i++)

sys/dev/mii/brgphy.c

1185

PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);

sys/dev/mii/brgphy.c

1193

int reg;

sys/dev/mii/brgphy.c

1204

for (i = 0; dspcode[i].reg != 0; i++)

sys/dev/mii/brgphy.c

1205

PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);

sys/dev/mii/brgphy.c

312

uint16_t reg, speed, gig;

sys/dev/mii/brgphy.c

329

PHY_READ(sc, MII_BMCR, &reg);

sys/dev/mii/brgphy.c

330

PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);

sys/dev/mii/brgphy.c

410

PHY_READ(sc, MII_BMSR, &reg);

sys/dev/mii/brgphy.c

411

PHY_READ(sc, MII_BMSR, &reg);

sys/dev/mii/brgphy.c

412

if (reg & BMSR_LINK) {

sys/dev/mii/brgphy.c

810

uint16_t reg;

sys/dev/mii/brgphy.c

895

PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL, &reg);

sys/dev/mii/brgphy.c

897

reg & ~BRGPHY_PHY_EXTCTL_3_LED);

sys/dev/mii/brgphy.c

921

PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL1, &reg);

sys/dev/mii/brgphy.c

922

PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL1, reg |

sys/dev/mii/brgphy.c

927

PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL2, &reg);

sys/dev/mii/brgphy.c

929

reg | BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN);

sys/dev/mii/brgphy.c

937

&reg);

sys/dev/mii/brgphy.c

939

reg | BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G);

sys/dev/mii/brgphy.c

948

PHY_READ(sc, BRGPHY_5708S_PG5_TXACTL1, &reg);

sys/dev/mii/brgphy.c

950

reg & ~BRGPHY_5708S_PG5_TXACTL1_VCM);

sys/dev/mii/brgphy.c

975

PHY_READ(sc, BRGPHY_SERDES_DIG_1000X_CTL1, &reg);

sys/dev/mii/brgphy.c

977

(reg & ~BRGPHY_SD_DIG_1000X_CTL1_AUTODET) |

sys/dev/mii/brgphy.c

990

&reg);

sys/dev/mii/brgphy.c

992

reg | BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G);

sys/dev/mii/ciphy.c

140

uint16_t reg, speed, gig;

sys/dev/mii/ciphy.c

157

PHY_READ(sc, MII_BMCR, &reg);

sys/dev/mii/ciphy.c

158

PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);

sys/dev/mii/ciphy.c

172

PHY_READ(sc, MII_BMCR, &reg);

sys/dev/mii/ciphy.c

173

if (reg & BMCR_AUTOEN)

sys/dev/mii/ciphy.c

252

PHY_READ(sc, MII_BMSR, &reg);

sys/dev/mii/ciphy.c

253

PHY_READ(sc, MII_BMSR, &reg);

sys/dev/mii/ciphy.c

254

if (reg & BMSR_LINK) {

sys/dev/mii/ciphy.c

391

uint16_t reg;

sys/dev/mii/ciphy.c

393

PHY_READ(sc, MII_PHYIDR2, &reg);

sys/dev/mii/ciphy.c

394

model = MII_MODEL(reg);

sys/dev/mii/dmphy.c

151

uint16_t reg;

sys/dev/mii/dmphy.c

168

PHY_READ(sc, MII_BMCR, &reg);

sys/dev/mii/dmphy.c

169

PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);

sys/dev/mii/etphy.c

264

uint16_t reg;

sys/dev/mii/etphy.c

275

PHY_READ(sc, MII_PHYIDR1, &reg);

sys/dev/mii/etphy.c

276

PHY_READ(sc, MII_PHYIDR2, &reg);

sys/dev/mii/etphy.c

278

PHY_READ(sc, ETPHY_CTRL, &reg);

sys/dev/mii/etphy.c

282

PHY_READ(sc, ETPHY_DATA, &reg);

sys/dev/mii/etphy.c

287

PHY_READ(sc, MII_BMCR, &reg);

sys/dev/mii/etphy.c

288

PHY_READ(sc, ETPHY_CTRL, &reg);

sys/dev/mii/etphy.c

302

PHY_READ(sc, ETPHY_DATA, &reg);

sys/dev/mii/etphy.c

307

PHY_READ(sc, MII_BMCR, &reg);

sys/dev/mii/etphy.c

308

PHY_READ(sc, ETPHY_CTRL, &reg);

sys/dev/mii/gentbi.c

189

uint16_t reg;

sys/dev/mii/gentbi.c

206

PHY_READ(sc, MII_BMCR, &reg);

sys/dev/mii/gentbi.c

207

PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);

sys/dev/mii/glxtphy.c

147

uint16_t reg;

sys/dev/mii/glxtphy.c

164

PHY_READ(sc, MII_BMCR, &reg);

sys/dev/mii/glxtphy.c

165

PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);

sys/dev/mii/gphyter.c

178

uint16_t reg;

sys/dev/mii/gphyter.c

195

PHY_READ(sc, MII_BMCR, &reg);

sys/dev/mii/gphyter.c

196

PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);

sys/dev/mii/gphyter.c

303

uint16_t reg;

sys/dev/mii/gphyter.c

308

reg = BMCR_RESET;

sys/dev/mii/gphyter.c

310

reg = BMCR_RESET | BMCR_ISO;

sys/dev/mii/gphyter.c

311

PHY_WRITE(sc, MII_BMCR, reg);

sys/dev/mii/gphyter.c

325

PHY_READ(sc, MII_BMCR, &reg);

sys/dev/mii/gphyter.c

326

if ((reg & BMCR_RESET) == 0)

sys/dev/mii/gphyter.c

332

PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);

sys/dev/mii/icsphy.c

150

uint16_t reg;

sys/dev/mii/icsphy.c

167

PHY_READ(sc, MII_BMCR, &reg);

sys/dev/mii/icsphy.c

168

PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);

sys/dev/mii/igphy.c

176

int reg;

sys/dev/mii/igphy.c

240

uint16_t reg;

sys/dev/mii/igphy.c

264

IGPHY_READ(sc, 0x2f5b, &reg);

sys/dev/mii/igphy.c

276

for (i = 0; !((code[i].reg == 0) && (code[i].val == 0)); i++)

sys/dev/mii/igphy.c

277

IGPHY_WRITE(sc, code[i].reg, code[i].val);

sys/dev/mii/igphy.c

285

IGPHY_WRITE(sc, 0x2f5b, reg);

sys/dev/mii/igphy.c

294

for (i = 0; !((code[i].reg == 0) && (code[i].val == 0)); i++)

sys/dev/mii/igphy.c

295

IGPHY_WRITE(sc, code[i].reg, code[i].val);

sys/dev/mii/igphy.c

356

uint16_t reg;

sys/dev/mii/igphy.c

373

PHY_READ(sc, MII_BMCR, &reg);

sys/dev/mii/igphy.c

374

PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);

sys/dev/mii/igphy.c

382

PHY_READ(sc, IGPHY_PORT_CTRL, &reg);

sys/dev/mii/igphy.c

384

reg |= PSCR_AUTO_MDIX;

sys/dev/mii/igphy.c

385

reg &= ~PSCR_FORCE_MDI_MDIX;

sys/dev/mii/igphy.c

386

PHY_WRITE(sc, IGPHY_PORT_CTRL, reg);

sys/dev/mii/igphy.c

388

reg &= ~(PSCR_AUTO_MDIX | PSCR_FORCE_MDI_MDIX);

sys/dev/mii/igphy.c

389

PHY_WRITE(sc, IGPHY_PORT_CTRL, reg);

sys/dev/mii/igphy.c

490

uint16_t reg, gtsr, gtcr;

sys/dev/mii/igphy.c

504

PHY_READ(sc, MII_BMCR, &reg);

sys/dev/mii/igphy.c

505

if ((reg & BMCR_AUTOEN) == 0)

sys/dev/mii/igphy.c

510

PHY_READ(sc, MII_BMSR, &reg);

sys/dev/mii/igphy.c

511

PHY_READ(sc, MII_BMSR, &reg);

sys/dev/mii/igphy.c

512

if ((reg & BMSR_LINK) == 0) {

sys/dev/mii/igphyreg.h

168

#define IGP3_REG(page, reg) \

sys/dev/mii/igphyreg.h

169

(((page) << IGP3_PAGE_SHIFT) | ((reg) & MII_ADDRMASK))

sys/dev/mii/igphyreg.h

179

IGPHY_READ(struct mii_softc *sc, int reg, uint16_t *val)

sys/dev/mii/igphyreg.h

183

if ((rv = PHY_WRITE(sc, IGPHY_PAGE_SELECT, reg & ~0x1f)) != 0)

sys/dev/mii/igphyreg.h

185

return PHY_READ(sc, reg & 0x1f, val);

sys/dev/mii/igphyreg.h

188

IGPHY_WRITE(struct mii_softc *sc, int reg, uint16_t val)

sys/dev/mii/igphyreg.h

192

if ((rv = PHY_WRITE(sc, IGPHY_PAGE_SELECT, reg & ~0x1f)) != 0)

sys/dev/mii/igphyreg.h

195

return PHY_WRITE(sc, reg & 0x1f, val);

sys/dev/mii/ihphy.c

122

uint16_t reg;

sys/dev/mii/ihphy.c

153

PHY_READ(sc, IHPHY_MII_CFG, &reg);

sys/dev/mii/ihphy.c

154

reg |= IHPHY_CFG_TX_CRS;

sys/dev/mii/ihphy.c

155

reg |= IHPHY_CFG_DOWN_SHIFT;

sys/dev/mii/ihphy.c

156

PHY_WRITE(sc, IHPHY_MII_CFG, reg);

sys/dev/mii/ihphy.c

164

uint16_t reg;

sys/dev/mii/ihphy.c

181

PHY_READ(sc, MII_BMCR, &reg);

sys/dev/mii/ihphy.c

182

PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);

sys/dev/mii/ihphy.c

191

PHY_READ(sc, IHPHY_MII_ECR, &reg);

sys/dev/mii/ihphy.c

193

reg &= ~IHPHY_ECR_LNK_EN;

sys/dev/mii/ihphy.c

195

reg |= IHPHY_ECR_LNK_EN;

sys/dev/mii/ihphy.c

196

PHY_WRITE(sc, IHPHY_MII_ECR, reg);

sys/dev/mii/ihphy.c

291

uint16_t reg;

sys/dev/mii/ihphy.c

299

PHY_READ(sc, MII_BMCR, &reg);

sys/dev/mii/ihphy.c

300

if ((reg & BMCR_RESET) == 0)

sys/dev/mii/ihphy.c

306

PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);

sys/dev/mii/ikphy.c

150

uint16_t reg;

sys/dev/mii/ikphy.c

167

PHY_READ(sc, MII_BMCR, &reg);

sys/dev/mii/ikphy.c

168

PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);

sys/dev/mii/ikphyreg.h

43

#define GG82563_REG(page, reg) \

sys/dev/mii/ikphyreg.h

44

(((page) << GG82563_PAGE_SHIFT) | ((reg) & MII_ADDRMASK))

sys/dev/mii/inbmphyreg.h

48

#define BME1000_REG(page, reg) \

sys/dev/mii/inbmphyreg.h

49

(((reg) & MII_ADDRMASK) | \

sys/dev/mii/inbmphyreg.h

51

(((reg) & ~MII_ADDRMASK) << (BM_PHY_UPPER_SHIFT - BME1000_PAGE_SHIFT)))

sys/dev/mii/inphy.c

152

uint16_t reg;

sys/dev/mii/inphy.c

169

PHY_READ(sc, MII_BMCR, &reg);

sys/dev/mii/inphy.c

170

PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);

sys/dev/mii/iophy.c

144

uint16_t reg;

sys/dev/mii/iophy.c

161

PHY_READ(sc, MII_BMCR, &reg);

sys/dev/mii/iophy.c

162

PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);

sys/dev/mii/ipgphy.c

143

uint16_t reg, speed;

sys/dev/mii/ipgphy.c

160

PHY_READ(sc, MII_BMCR, &reg);

sys/dev/mii/ipgphy.c

161

PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);

sys/dev/mii/ipgphy.c

223

PHY_READ(sc, MII_BMSR, &reg);

sys/dev/mii/ipgphy.c

224

PHY_READ(sc, MII_BMSR, &reg);

sys/dev/mii/ipgphy.c

225

if (reg & BMSR_LINK) {

sys/dev/mii/ipgphy.c

326

uint16_t reg = 0;

sys/dev/mii/ipgphy.c

333

PHY_READ(sc, MII_ANAR, &reg);

sys/dev/mii/ipgphy.c

334

reg &= ~(ANAR_PAUSE_SYM | ANAR_PAUSE_ASYM);

sys/dev/mii/ipgphy.c

335

reg |= ANAR_NP;

sys/dev/mii/ipgphy.c

339

reg |= ANAR_10 | ANAR_10_FD | ANAR_TX | ANAR_TX_FD;

sys/dev/mii/ipgphy.c

342

reg |= ANAR_PAUSE_SYM | ANAR_PAUSE_ASYM;

sys/dev/mii/ipgphy.c

344

PHY_WRITE(sc, MII_ANAR, reg | ANAR_CSMA);

sys/dev/mii/ipgphy.c

347

reg = GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX;

sys/dev/mii/ipgphy.c

350

reg = GTCR_ADV_1000TFDX;

sys/dev/mii/ipgphy.c

352

reg = GTCR_ADV_1000THDX;

sys/dev/mii/ipgphy.c

354

reg = 0;

sys/dev/mii/ipgphy.c

356

PHY_WRITE(sc, MII_100T2CR, reg);

sys/dev/mii/ipgphy.c

382

uint16_t reg;

sys/dev/mii/ipgphy.c

389

PHY_READ(sc, MII_BMCR, &reg);

sys/dev/mii/ipgphy.c

390

reg &= ~(BMCR_AUTOEN | BMCR_FDX);

sys/dev/mii/ipgphy.c

391

PHY_WRITE(sc, MII_BMCR, reg);

sys/dev/mii/lxtphy.c

170

uint16_t reg;

sys/dev/mii/lxtphy.c

187

PHY_READ(sc, MII_BMCR, &reg);

sys/dev/mii/lxtphy.c

188

PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);

sys/dev/mii/makphy.c

162

uint16_t reg, model;

sys/dev/mii/makphy.c

239

rv = PHY_READ(sc, MAKPHY_ESSR, &reg);

sys/dev/mii/makphy.c

250

} else if ((reg & ESSR_AUTOSEL_DISABLE) != 0) {

sys/dev/mii/makphy.c

251

switch (reg & ESSR_HWCFG_MODE) {

sys/dev/mii/makphy.c

295

uint16_t reg;

sys/dev/mii/makphy.c

302

PHY_READ(sc, MAKPHY_PSCR, &reg);

sys/dev/mii/makphy.c

316

reg |= PSCR_CRS_ON_TX;

sys/dev/mii/makphy.c

324

reg &= ~E3016_PSCR_SCRAMBLE_DIS;

sys/dev/mii/makphy.c

331

reg |= E3016_PSCR_REG8NXTPG;

sys/dev/mii/makphy.c

333

PHY_WRITE(sc, MAKPHY_PSCR, reg);

sys/dev/mii/makphy.c

337

PHY_READ(sc, 0x16, &reg);

sys/dev/mii/makphy.c

338

if (reg == 0) {

sys/dev/mii/makphy.c

339

reg = (0x0b << 8) | (0x05 << 4) | 0x04; /* XXX */

sys/dev/mii/makphy.c

340

PHY_WRITE(sc, 0x16, reg);

sys/dev/mii/micphy.c

268

uint16_t reg;

sys/dev/mii/micphy.c

280

PHY_READ(sc, KSZ8051_PHYCTL2, &reg);

sys/dev/mii/micphy.c

283

PHY_WRITE(sc, KSZ8051_PHYCTL2, reg);

sys/dev/mii/micphy.c

290

uint16_t reg;

sys/dev/mii/micphy.c

307

PHY_READ(sc, MII_BMCR, &reg);

sys/dev/mii/micphy.c

308

PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);

sys/dev/mii/micphy.c

342

micphy_writexreg(struct mii_softc *sc, uint32_t reg, uint32_t wval)

sys/dev/mii/micphy.c

346

PHY_WRITE(sc, KSZ_XREG_CONTROL, KSZ_XREG_CTL_SEL_WRITE | reg);

sys/dev/mii/micphy.c

348

PHY_WRITE(sc, KSZ_XREG_CONTROL, KSZ_XREG_CTL_SEL_READ | reg);

sys/dev/mii/mii_bitbang.c

112

mii_bitbang_readreg(device_t sc, mii_bitbang_ops_t ops, int phy, int reg,

sys/dev/mii/mii_bitbang.c

123

mii_bitbang_sendbits(sc, ops, reg, 5);

sys/dev/mii/mii_bitbang.c

166

mii_bitbang_writereg(device_t sc, mii_bitbang_ops_t ops, int phy, int reg,

sys/dev/mii/mii_bitbang.c

175

mii_bitbang_sendbits(sc, ops, reg, 5);

sys/dev/mii/mii_physubr.c

288

uint16_t reg;

sys/dev/mii/mii_physubr.c

290

PHY_READ(sc, MII_BMCR, &reg);

sys/dev/mii/mii_physubr.c

291

reg |= BMCR_STARTNEG;

sys/dev/mii/mii_physubr.c

292

PHY_WRITE(sc, MII_BMCR, reg);

sys/dev/mii/mii_physubr.c

334

uint16_t reg;

sys/dev/mii/mii_physubr.c

358

PHY_READ(sc, MII_BMSR, &reg);

sys/dev/mii/mii_physubr.c

359

PHY_READ(sc, MII_BMSR, &reg);

sys/dev/mii/mii_physubr.c

360

if (reg & BMSR_LINK) {

sys/dev/mii/mii_physubr.c

399

uint16_t reg;

sys/dev/mii/mii_physubr.c

404

reg = BMCR_RESET;

sys/dev/mii/mii_physubr.c

406

reg = BMCR_RESET | BMCR_ISO;

sys/dev/mii/mii_physubr.c

407

PHY_WRITE(sc, MII_BMCR, reg);

sys/dev/mii/mii_physubr.c

411

PHY_READ(sc, MII_BMCR, &reg);

sys/dev/mii/mii_physubr.c

412

if ((reg & BMCR_RESET) == 0)

sys/dev/mii/mii_physubr.c

418

PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);

sys/dev/mii/mvphy.c

336

uint16_t reg;

sys/dev/mii/mvphy.c

344

MV_ATU_OPERATION, &reg);

sys/dev/mii/nsphy.c

146

uint16_t reg;

sys/dev/mii/nsphy.c

163

PHY_READ(sc, MII_BMCR, &reg);

sys/dev/mii/nsphy.c

164

PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);

sys/dev/mii/nsphy.c

172

PHY_READ(sc, MII_NSPHY_PCR, &reg);

sys/dev/mii/nsphy.c

178

reg |= PCR_LED4MODE;

sys/dev/mii/nsphy.c

185

reg |= PCR_CIMDIS;

sys/dev/mii/nsphy.c

191

reg |= PCR_FLINK100;

sys/dev/mii/nsphy.c

203

reg |= 0x0100 | 0x0400;

sys/dev/mii/nsphy.c

205

PHY_WRITE(sc, MII_NSPHY_PCR, reg);

sys/dev/mii/nsphy.c

314

uint16_t reg;

sys/dev/mii/nsphy.c

319

reg = BMCR_RESET;

sys/dev/mii/nsphy.c

321

reg = BMCR_RESET | BMCR_ISO;

sys/dev/mii/nsphy.c

322

PHY_WRITE(sc, MII_BMCR, reg);

sys/dev/mii/nsphy.c

340

PHY_READ(sc, MII_BMCR, &reg);

sys/dev/mii/nsphy.c

341

if (reg && ((reg & BMCR_RESET) == 0))

sys/dev/mii/nsphy.c

347

PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);

sys/dev/mii/nsphyter.c

152

uint16_t reg;

sys/dev/mii/nsphyter.c

169

PHY_READ(sc, MII_BMCR, &reg);

sys/dev/mii/nsphyter.c

170

PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);

sys/dev/mii/nsphyter.c

261

uint16_t reg;

sys/dev/mii/nsphyter.c

266

reg = BMCR_RESET;

sys/dev/mii/nsphyter.c

268

reg = BMCR_RESET | BMCR_ISO;

sys/dev/mii/nsphyter.c

269

PHY_WRITE(sc, MII_BMCR, reg);

sys/dev/mii/nsphyter.c

283

PHY_READ(sc, MII_BMCR, &reg);

sys/dev/mii/nsphyter.c

284

if ((reg & BMCR_RESET) == 0)

sys/dev/mii/nsphyter.c

290

PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);

sys/dev/mii/pnaphy.c

135

uint16_t reg;

sys/dev/mii/pnaphy.c

152

PHY_READ(sc, MII_BMCR, &reg);

sys/dev/mii/pnaphy.c

153

PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);

sys/dev/mii/qsphy.c

145

uint16_t reg;

sys/dev/mii/qsphy.c

162

PHY_READ(sc, MII_BMCR, &reg);

sys/dev/mii/qsphy.c

163

PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);

sys/dev/mii/rgephy.c

166

uint16_t reg, speed, gig, anar;

sys/dev/mii/rgephy.c

183

PHY_READ(sc, MII_BMCR, &reg);

sys/dev/mii/rgephy.c

184

PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);

sys/dev/mii/rgephy.c

201

PHY_READ(sc, MII_BMCR, &reg);

sys/dev/mii/rgephy.c

202

if (reg & BMCR_AUTOEN)

sys/dev/mii/rgephy.c

323

uint16_t reg;

sys/dev/mii/rgephy.c

326

PHY_READ(sc, RGEPHY_MII_PHYSR, &reg);

sys/dev/mii/rgephy.c

327

if (reg & RGEPHY_PHYSR_LINK)

sys/dev/mii/rgephy.c

330

PHY_READ(sc, RGEPHY_MII_SSR, &reg);

sys/dev/mii/rgephy.c

331

if (reg & RGEPHY_SSR_LINK)

sys/dev/mii/rgephy.c

334

PHY_READ(sc, RTK_GMEDIASTAT, &reg);

sys/dev/mii/rgephy.c

335

if ((reg & RTK_GMEDIASTAT_LINK) != 0)

sys/dev/mii/rlphy.c

212

uint16_t bmsr, bmcr, anar, anlpar, result, reg;

sys/dev/mii/rlphy.c

293

PHY_READ(sc, 0x0019, &reg);

sys/dev/mii/rlphy.c

294

if (reg & 0x01)

sys/dev/mii/rlphy.c

299

PHY_READ(sc, RTK_MEDIASTAT, &reg);

sys/dev/mii/rlphy.c

300

if (reg & RTK_MEDIASTAT_SPEED10)

sys/dev/mii/smscphy.c

145

uint16_t reg;

sys/dev/mii/smscphy.c

177

PHY_READ(sc, MII_BMSR, &reg);

sys/dev/mii/smscphy.c

178

PHY_READ(sc, MII_BMSR, &reg);

sys/dev/mii/smscphy.c

179

if (reg & BMSR_LINK) {

sys/dev/mii/sqphy.c

162

uint16_t reg;

sys/dev/mii/sqphy.c

179

PHY_READ(sc, MII_BMCR, &reg);

sys/dev/mii/sqphy.c

180

PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);

sys/dev/mii/sqphy.c

266

uint16_t reg;

sys/dev/mii/sqphy.c

286

PHY_READ(sc, MII_BMCR, &reg);

sys/dev/mii/sqphy.c

287

while ((reg & BMCR_ISO) != 0) {

sys/dev/mii/sqphy.c

289

PHY_WRITE(sc, MII_BMCR, reg & ~BMCR_ISO);

sys/dev/mii/sqphy.c

291

PHY_READ(sc, MII_BMCR, &reg);

sys/dev/mii/tlphy.c

211

uint16_t reg;

sys/dev/mii/tlphy.c

231

PHY_READ(sc, MII_BMCR, &reg);

sys/dev/mii/tlphy.c

232

PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);

sys/dev/mii/tlphy.c

276

PHY_READ(sc, MII_BMSR, &reg);

sys/dev/mii/tlphy.c

277

PHY_READ(sc, MII_BMSR, &reg);

sys/dev/mii/tlphy.c

278

if (reg & BMSR_LINK) {

sys/dev/mii/tqphy.c

156

uint16_t reg;

sys/dev/mii/tqphy.c

173

PHY_READ(sc, MII_BMCR, &reg);

sys/dev/mii/tqphy.c

174

PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);

sys/dev/mii/ukphy.c

155

uint16_t reg;

sys/dev/mii/ukphy.c

172

PHY_READ(sc, MII_BMCR, &reg);

sys/dev/mii/ukphy.c

173

PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);

sys/dev/mii/urlphy.c

138

uint16_t reg;

sys/dev/mii/urlphy.c

180

PHY_READ(sc, URLPHY_MSR, &reg);

sys/dev/mii/urlphy.c

181

PHY_READ(sc, URLPHY_MSR, &reg);

sys/dev/mii/urlphy.c

182

if (reg & URLPHY_MSR_LINK) {

sys/dev/mvme/if_ie_mvme.c

133

u_int8_t reg;

sys/dev/mvme/if_ie_mvme.c

136

reg = pcc2_reg_read(sys_pcctwo, PCC2REG_ETH_ICSR);

sys/dev/mvme/if_ie_mvme.c

137

reg |= PCCTWO_ICR_ICLR;

sys/dev/mvme/if_ie_mvme.c

138

pcc2_reg_write(sys_pcctwo, PCC2REG_ETH_ICSR, reg);

sys/dev/mvme/if_ie_mvme.c

147

u_int8_t reg;

sys/dev/mvme/if_ie_mvme.c

149

reg = pcc2_reg_read(sys_pcctwo, PCC2REG_ETH_ICSR);

sys/dev/mvme/if_ie_mvme.c

150

reg |= PCCTWO_ICR_IEN | PCCTWO_ICR_ICLR;

sys/dev/mvme/if_ie_mvme.c

151

pcc2_reg_write(sys_pcctwo, PCC2REG_ETH_ICSR, reg);

sys/dev/mvme/lpt_pcctwo.c

225

u_int8_t reg;

sys/dev/mvme/lpt_pcctwo.c

227

reg = pcc2_reg_read(sc, PCC2REG_PRT_CONTROL);

sys/dev/mvme/lpt_pcctwo.c

230

reg |= PCCTWO_PRT_CTRL_FAST;

sys/dev/mvme/lpt_pcctwo.c

232

reg &= ~PCCTWO_PRT_CTRL_FAST;

sys/dev/mvme/lpt_pcctwo.c

234

pcc2_reg_write(sc, PCC2REG_PRT_CONTROL, reg);

sys/dev/mvme/vme_two.c

100

if (reg & VME2_IO_CONTROL_I1D16)

sys/dev/mvme/vme_two.c

110

if (reg & VME2_IO_CONTROL_I2EN) {

sys/dev/mvme/vme_two.c

118

if (reg & VME2_IO_CONTROL_I2SU) {

sys/dev/mvme/vme_two.c

127

if (reg & VME2_IO_CONTROL_I2PD) {

sys/dev/mvme/vme_two.c

173

u_int32_t reg;

sys/dev/mvme/vme_two.c

178

reg = vme2_lcsr_read(sc, VME2LCSR_MASTER_ENABLE);

sys/dev/mvme/vme_two.c

179

if ((reg & VME2_MASTER_ENABLE(range)) == 0) {

sys/dev/mvme/vme_two.c

224

reg = vme2_lcsr_read(sc, VME2LCSR_MASTER_ADDRESS(range));

sys/dev/mvme/vme_two.c

225

start = (reg & VME2_MAST_ADDRESS_START_MASK);

sys/dev/mvme/vme_two.c

228

end = (reg & VME2_MAST_ADDRESS_END_MASK);

sys/dev/mvme/vme_two.c

237

if (range == 3 && (reg = vme2_lcsr_read(sc, VME2LCSR_MAST4_TRANS))!=0) {

sys/dev/mvme/vme_two.c

240

reg = vme2_lcsr_read(sc, VME2LCSR_MAST4_TRANS);

sys/dev/mvme/vme_two.c

241

reg &= VME2_MAST4_TRANS_SELECT_MASK;

sys/dev/mvme/vme_two.c

242

sel = reg << VME2_MAST4_TRANS_SELECT_SHIFT;

sys/dev/mvme/vme_two.c

244

reg = vme2_lcsr_read(sc, VME2LCSR_MAST4_TRANS);

sys/dev/mvme/vme_two.c

245

reg &= VME2_MAST4_TRANS_ADDRESS_MASK;

sys/dev/mvme/vme_two.c

246

addr = reg << VME2_MAST4_TRANS_ADDRESS_SHIFT;

sys/dev/mvme/vme_two.c

266

u_int32_t reg;

sys/dev/mvme/vme_two.c

273

reg = vme2_lcsr_read(sc, VME2LCSR_SLAVE_CTRL);

sys/dev/mvme/vme_two.c

275

if (am == VME_AM_A32 && (reg & VME2_SLAVE_AMSEL_A32(range))) {

sys/dev/mvme/vme_two.c

279

if (am == VME_AM_A24 && (reg & VME2_SLAVE_AMSEL_A24(range))) {

sys/dev/mvme/vme_two.c

288

if ((reg & VME2_SLAVE_AMSEL_DAT(range)) != 0)

sys/dev/mvme/vme_two.c

291

if ((reg & VME2_SLAVE_AMSEL_PGM(range)) != 0)

sys/dev/mvme/vme_two.c

294

if ((reg & VME2_SLAVE_AMSEL_USR(range)) != 0)

sys/dev/mvme/vme_two.c

297

if ((reg & VME2_SLAVE_AMSEL_SUP(range)) != 0)

sys/dev/mvme/vme_two.c

300

if ((reg & VME2_SLAVE_AMSEL_BLK(range)) != 0)

sys/dev/mvme/vme_two.c

303

if ((reg & VME2_SLAVE_AMSEL_BLKD64(range)) != 0)

sys/dev/mvme/vme_two.c

311

reg = vme2_lcsr_read(sc, VME2LCSR_SLAVE_ADDRESS(range));

sys/dev/mvme/vme_two.c

312

vr->vr_vmestart = reg & VME2_SLAVE_ADDRESS_START_MASK;

sys/dev/mvme/vme_two.c

315

vr->vr_vmeend = reg & VME2_SLAVE_ADDRESS_END_MASK;

sys/dev/mvme/vme_two.c

323

reg = vme2_lcsr_read(sc, VME2LCSR_SLAVE_CTRL);

sys/dev/mvme/vme_two.c

324

if ((reg & VME2_SLAVE_CTRL_ADDER(range)) != 0) {

sys/dev/mvme/vme_two.c

325

reg = vme2_lcsr_read(sc, VME2LCSR_SLAVE_TRANS(range));

sys/dev/mvme/vme_two.c

326

reg &= VME2_SLAVE_TRANS_ADDRESS_MASK;

sys/dev/mvme/vme_two.c

327

reg <<= VME2_SLAVE_TRANS_ADDRESS_SHIFT;

sys/dev/mvme/vme_two.c

328

vr->vr_locstart = vr->vr_vmestart + reg;

sys/dev/mvme/vme_two.c

332

reg = vme2_lcsr_read(sc, VME2LCSR_SLAVE_TRANS(range));

sys/dev/mvme/vme_two.c

333

sel = reg & VME2_SLAVE_TRANS_SELECT_MASK;

sys/dev/mvme/vme_two.c

335

addr = reg & VME2_SLAVE_TRANS_ADDRESS_MASK;

sys/dev/mvme/vme_two.c

64

u_int32_t reg;

sys/dev/mvme/vme_two.c

79

reg = vme2_lcsr_read(sc, VME2LCSR_BOARD_CONTROL);

sys/dev/mvme/vme_two.c

81

(reg & VME2_BOARD_CONTROL_SCON) ? "enabled" : "disabled");

sys/dev/mvme/vme_two.c

87

reg = vme2_lcsr_read(sc, VME2LCSR_IO_CONTROL);

sys/dev/mvme/vme_two.c

88

if (reg & VME2_IO_CONTROL_I1EN) {

sys/dev/mvme/vme_two.c

93

if (reg & VME2_IO_CONTROL_I1SU)

sys/dev/mvme/vme_two_isr.c

154

u_int32_t reg;

sys/dev/mvme/vme_two_isr.c

167

reg = vme2_lcsr_read(sc, VME2LCSR_MISC_STATUS) & ~VME2_MISC_STATUS_MIEN;

sys/dev/mvme/vme_two_isr.c

168

vme2_lcsr_write(sc, VME2LCSR_MISC_STATUS, reg);

sys/dev/mvme/vme_two_isr.c

178

reg = vme2_lcsr_read(sc, VME2LCSR_TIMER_CONTROL);

sys/dev/mvme/vme_two_isr.c

179

reg &= ~VME2_TIMER_CONTROL_EN(0);

sys/dev/mvme/vme_two_isr.c

180

reg &= ~VME2_TIMER_CONTROL_EN(1);

sys/dev/mvme/vme_two_isr.c

181

vme2_lcsr_write(sc, VME2LCSR_TIMER_CONTROL, reg);

sys/dev/mvme/vme_two_isr.c

184

reg = vme2_lcsr_read(sc, VME2LCSR_VECTOR_BASE);

sys/dev/mvme/vme_two_isr.c

185

reg &= ~VME2_VECTOR_BASE_MASK;

sys/dev/mvme/vme_two_isr.c

186

reg |= VME2_VECTOR_BASE_REG_VALUE;

sys/dev/mvme/vme_two_isr.c

187

vme2_lcsr_write(sc, VME2LCSR_VECTOR_BASE, reg);

sys/dev/mvme/vme_two_isr.c

190

reg = vme2_lcsr_read(sc, VME2LCSR_MISC_STATUS) | VME2_MISC_STATUS_MIEN;

sys/dev/mvme/vme_two_isr.c

191

vme2_lcsr_write(sc, VME2LCSR_MISC_STATUS, reg);

sys/dev/mvme/vme_two_isr.c

251

u_int32_t reg;

sys/dev/mvme/vme_two_isr.c

310

reg = vme2_lcsr_read(sc, iloffset);

sys/dev/mvme/vme_two_isr.c

311

reg &= ~(VME2_INTERRUPT_LEVEL_MASK << ilshift);

sys/dev/mvme/vme_two_isr.c

312

reg |= (prior << ilshift);

sys/dev/mvme/vme_two_isr.c

313

vme2_lcsr_write(sc, iloffset, reg);

sys/dev/mvme/vme_two_isr.c

320

reg = vme2_lcsr_read(sc, VME2LCSR_LOCAL_INTERRUPT_ENABLE);

sys/dev/mvme/vme_two_isr.c

321

reg |= VME2_LOCAL_INTERRUPT(bitoff);

sys/dev/mvme/vme_two_isr.c

322

vme2_lcsr_write(sc, VME2LCSR_LOCAL_INTERRUPT_ENABLE, reg);

sys/dev/mvme/vme_two_isr.c

332

reg = vme2_lcsr_read(sc, iloffset);

sys/dev/mvme/vme_two_isr.c

333

reg &= (VME2_INTERRUPT_LEVEL_MASK << ilshift);

sys/dev/mvme/vme_two_isr.c

335

if ((prior << ilshift) != reg)

sys/dev/mvme/vme_two_isr.c

347

u_int32_t reg;

sys/dev/mvme/vme_two_isr.c

389

reg = vme2_lcsr_read(sc, VME2LCSR_LOCAL_INTERRUPT_ENABLE);

sys/dev/mvme/vme_two_isr.c

390

reg &= ~VME2_LOCAL_INTERRUPT(bitoff);

sys/dev/mvme/vme_two_isr.c

391

vme2_lcsr_write(sc, VME2LCSR_LOCAL_INTERRUPT_ENABLE, reg);

sys/dev/mvme/vme_two_isr.c

394

reg = vme2_lcsr_read(sc, iloffset);

sys/dev/mvme/vme_two_isr.c

395

reg &= ~(VME2_INTERRUPT_LEVEL_MASK << ilshift);

sys/dev/mvme/vme_two_isr.c

396

vme2_lcsr_write(sc, iloffset, reg);

sys/dev/ofisa/atppc_ofisa.c

105

struct ofisa_reg_desc reg;

sys/dev/ofisa/atppc_ofisa.c

115

n = ofisa_reg_get(aa->oba.oba_phandle, &reg, 1);

sys/dev/ofisa/atppc_ofisa.c

117

n = lpt_ofisa_md_reg_fixup(parent, self, aux, &reg, 1, n);

sys/dev/ofisa/atppc_ofisa.c

143

sc->sc_iot = (reg.type == OFISA_REG_TYPE_IO) ? aa->iot : aa->memt;

sys/dev/ofisa/atppc_ofisa.c

149

if (bus_space_map(sc->sc_iot, reg.addr, reg.len, 0,

sys/dev/ofisa/com_ofisa.c

114

n = ofisa_reg_get(aa->oba.oba_phandle, &reg, 1);

sys/dev/ofisa/com_ofisa.c

116

n = com_ofisa_md_reg_fixup(parent, self, aux, &reg, 1, n);

sys/dev/ofisa/com_ofisa.c

122

if (reg.len != 8) {

sys/dev/ofisa/com_ofisa.c

124

(unsigned long)reg.len);

sys/dev/ofisa/com_ofisa.c

144

iot = (reg.type == OFISA_REG_TYPE_IO) ? aa->iot : aa->memt;

sys/dev/ofisa/com_ofisa.c

145

iobase = reg.addr;

sys/dev/ofisa/com_ofisa.c

149

bus_space_map(iot, iobase, reg.len, 0, &ioh)) {

sys/dev/ofisa/com_ofisa.c

162

ofisa_reg_print(&reg, 1);

sys/dev/ofisa/com_ofisa.c

96

struct ofisa_reg_desc reg;

sys/dev/ofisa/ess_ofisa.c

103

if (reg.type != OFISA_REG_TYPE_IO) {

sys/dev/ofisa/ess_ofisa.c

107

if (reg.len != ESS_NPORT) {

sys/dev/ofisa/ess_ofisa.c

109

(unsigned long)reg.len, ESS_NPORT);

sys/dev/ofisa/ess_ofisa.c

140

sc->sc_iobase = reg.addr;

sys/dev/ofisa/ess_ofisa.c

141

if (bus_space_map(sc->sc_iot, sc->sc_iobase, reg.len, 0,

sys/dev/ofisa/ess_ofisa.c

80

struct ofisa_reg_desc reg;

sys/dev/ofisa/ess_ofisa.c

98

n = ofisa_reg_get(aa->oba.oba_phandle, &reg, 1);

sys/dev/ofisa/if_cs_ofisa.c

123

n = ofisa_reg_get(aa->oba.oba_phandle, reg, 2);

sys/dev/ofisa/if_cs_ofisa.c

125

n = cs_ofisa_md_reg_fixup(parent, self, aux, reg, 2, n);

sys/dev/ofisa/if_cs_ofisa.c

133

if (reg[i].type == OFISA_REG_TYPE_IO) {

sys/dev/ofisa/if_cs_ofisa.c

138

if (reg[i].len != CS8900_IOSIZE) {

sys/dev/ofisa/if_cs_ofisa.c

140

(unsigned long)reg[i].len, CS8900_IOSIZE);

sys/dev/ofisa/if_cs_ofisa.c

143

io_addr = reg[i].addr;

sys/dev/ofisa/if_cs_ofisa.c

149

if (reg[i].len != CS8900_MEMSIZE) {

sys/dev/ofisa/if_cs_ofisa.c

151

(unsigned long)reg[i].len, CS8900_MEMSIZE);

sys/dev/ofisa/if_cs_ofisa.c

154

mem_addr = reg[i].addr;

sys/dev/ofisa/if_cs_ofisa.c

96

struct ofisa_reg_desc reg[2];

sys/dev/ofisa/joy_ofisa.c

101

if (reg.len != JOY_NPORTS) {

sys/dev/ofisa/joy_ofisa.c

103

(unsigned long)reg.len, JOY_NPORTS);

sys/dev/ofisa/joy_ofisa.c

110

if (bus_space_map(sc->sc_iot, reg.addr, reg.len, 0, &sc->sc_ioh)) {

sys/dev/ofisa/joy_ofisa.c

80

struct ofisa_reg_desc reg;

sys/dev/ofisa/joy_ofisa.c

92

n = ofisa_reg_get(aa->oba.oba_phandle, &reg, 1);

sys/dev/ofisa/joy_ofisa.c

97

if (reg.type != OFISA_REG_TYPE_IO) {

sys/dev/ofisa/lpt_ofisa.c

109

n = ofisa_reg_get(aa->oba.oba_phandle, &reg, 1);

sys/dev/ofisa/lpt_ofisa.c

111

n = lpt_ofisa_md_reg_fixup(parent, self, aux, &reg, 1, n);

sys/dev/ofisa/lpt_ofisa.c

117

if (reg.len != 4 && reg.len != 8) {

sys/dev/ofisa/lpt_ofisa.c

119

(unsigned long)reg.len);

sys/dev/ofisa/lpt_ofisa.c

132

sc->sc_iot = (reg.type == OFISA_REG_TYPE_IO) ? aa->iot : aa->memt;

sys/dev/ofisa/lpt_ofisa.c

133

if (bus_space_map(sc->sc_iot, reg.addr, reg.len, 0, &sc->sc_ioh)) {

sys/dev/ofisa/lpt_ofisa.c

147

ofisa_reg_print(&reg, 1);

sys/dev/ofisa/lpt_ofisa.c

96

struct ofisa_reg_desc reg;

sys/dev/ofisa/mcclock_ofisa.c

101

mcclock_ofisa_write(struct mc146818_softc *sc, u_int reg, u_int datum)

sys/dev/ofisa/mcclock_ofisa.c

103

bus_space_write_1(sc->sc_bst, sc->sc_bsh, 0, reg);

sys/dev/ofisa/mcclock_ofisa.c

127

struct ofisa_reg_desc reg;

sys/dev/ofisa/mcclock_ofisa.c

133

n = ofisa_reg_get(aa->oba.oba_phandle, &reg, 1);

sys/dev/ofisa/mcclock_ofisa.c

135

n = mcclock_ofisa_md_reg_fixup(parent, self, aux, &reg, 1, n);

sys/dev/ofisa/mcclock_ofisa.c

141

if (reg.len != 2) {

sys/dev/ofisa/mcclock_ofisa.c

143

(unsigned long)reg.len);

sys/dev/ofisa/mcclock_ofisa.c

154

sc->sc_bst = (reg.type == OFISA_REG_TYPE_IO) ? aa->iot : aa->memt;

sys/dev/ofisa/mcclock_ofisa.c

155

if (bus_space_map(sc->sc_bst, reg.addr, reg.len, 0, &sc->sc_bsh) != 0) {

sys/dev/ofisa/mcclock_ofisa.c

94

mcclock_ofisa_read(struct mc146818_softc *sc, u_int reg)

sys/dev/ofisa/mcclock_ofisa.c

96

bus_space_write_1(sc->sc_bst, sc->sc_bsh, 0, reg);

sys/dev/ofisa/sb_ofisa.c

104

n = ofisa_reg_get(aa->oba.oba_phandle, &reg, 1);

sys/dev/ofisa/sb_ofisa.c

109

if (reg.type != OFISA_REG_TYPE_IO) {

sys/dev/ofisa/sb_ofisa.c

113

if (reg.len != SB_NPORT && reg.len != SBP_NPORT) {

sys/dev/ofisa/sb_ofisa.c

115

(unsigned long)reg.len, SB_NPORT, SBP_NPORT);

sys/dev/ofisa/sb_ofisa.c

134

if (bus_space_map(sc->sc_iot, reg.addr, reg.len, 0, &sc->sc_ioh)) {

sys/dev/ofisa/sb_ofisa.c

140

sc->sc_iobase = reg.addr;

sys/dev/ofisa/sb_ofisa.c

86

struct ofisa_reg_desc reg;

sys/dev/ofisa/wdc_ofisa.c

113

n = ofisa_reg_get(aa->oba.oba_phandle, reg, 2);

sys/dev/ofisa/wdc_ofisa.c

115

n = wdc_ofisa_md_reg_fixup(parent, self, aux, reg, 2, n);

sys/dev/ofisa/wdc_ofisa.c

121

if (reg[0].len != 8 || reg[1].len != 2) {

sys/dev/ofisa/wdc_ofisa.c

123

(unsigned long)reg[0].len, (unsigned long)reg[1].len);

sys/dev/ofisa/wdc_ofisa.c

136

wdr->cmd_iot = (reg[0].type == OFISA_REG_TYPE_IO) ? aa->iot : aa->memt;

sys/dev/ofisa/wdc_ofisa.c

137

wdr->ctl_iot = (reg[1].type == OFISA_REG_TYPE_IO) ? aa->iot : aa->memt;

sys/dev/ofisa/wdc_ofisa.c

138

if (bus_space_map(wdr->cmd_iot, reg[0].addr, 8, 0, &ioh) ||

sys/dev/ofisa/wdc_ofisa.c

139

bus_space_map(wdr->ctl_iot, reg[1].addr, 1, 0,

sys/dev/ofisa/wdc_ofisa.c

172

ofisa_reg_print(reg, 2);

sys/dev/ofisa/wdc_ofisa.c

98

struct ofisa_reg_desc reg[2];

sys/dev/pci/acardide.c

173

u_int32_t reg;

sys/dev/pci/acardide.c

174

reg = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL);

sys/dev/pci/acardide.c

175

reg &= ~ATP860_CTRL_INT;

sys/dev/pci/acardide.c

176

pci_conf_write(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL, reg);

sys/dev/pci/aceride.c

234

u_int8_t reg;

sys/dev/pci/aceride.c

243

reg = pciide_pci_read(acer_sc->pcib_pa.pa_pc, acer_sc->pcib_pa.pa_tag,

sys/dev/pci/aceride.c

246

ACER_PCIB_CTRL, reg & ~ACER_PCIB_CTRL_ENCHAN(chp->ch_channel));

sys/dev/pci/aceride.c

249

ACER_PCIB_CTRL, reg);

sys/dev/pci/agp.c

393

agp_map_aperture(struct pci_attach_args *pa, struct agp_softc *sc, int reg)

sys/dev/pci/agp.c

399

if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, reg,

sys/dev/pci/agp_ali.c

116

reg = pci_conf_read(pa->pa_pc, pa->pa_tag, AGP_ALI_ATTBASE);

sys/dev/pci/agp_ali.c

117

reg = (reg & 0xfff) | (gatt->ag_physical & ~0xfff);

sys/dev/pci/agp_ali.c

118

pci_conf_write(pa->pa_pc, pa->pa_tag, AGP_ALI_ATTBASE, reg);

sys/dev/pci/agp_ali.c

121

reg = pci_conf_read(pa->pa_pc, pa->pa_tag, AGP_ALI_TLBCTRL);

sys/dev/pci/agp_ali.c

122

reg = (reg & ~0xff) | 0x10;

sys/dev/pci/agp_ali.c

123

pci_conf_write(pa->pa_pc, pa->pa_tag, AGP_ALI_TLBCTRL, reg);

sys/dev/pci/agp_ali.c

133

pcireg_t reg;

sys/dev/pci/agp_ali.c

141

reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_ALI_TLBCTRL);

sys/dev/pci/agp_ali.c

142

reg &= ~0xff;

sys/dev/pci/agp_ali.c

143

reg |= 0x90;

sys/dev/pci/agp_ali.c

144

pci_conf_write(sc->as_pc, sc->as_tag, AGP_ALI_TLBCTRL, reg);

sys/dev/pci/agp_ali.c

148

reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_ALI_ATTBASE);

sys/dev/pci/agp_ali.c

149

reg &= 0xf;

sys/dev/pci/agp_ali.c

150

pci_conf_write(sc->as_pc, sc->as_tag, AGP_ALI_ATTBASE, reg);

sys/dev/pci/agp_ali.c

193

pcireg_t reg;

sys/dev/pci/agp_ali.c

204

reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_ALI_ATTBASE);

sys/dev/pci/agp_ali.c

205

reg &= ~0xf;

sys/dev/pci/agp_ali.c

206

reg |= i;

sys/dev/pci/agp_ali.c

207

pci_conf_write(sc->as_pc, sc->as_tag, AGP_ALI_ATTBASE, reg);

sys/dev/pci/agp_ali.c

238

pcireg_t reg;

sys/dev/pci/agp_ali.c

240

reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_ALI_TLBCTRL);

sys/dev/pci/agp_ali.c

241

reg &= ~0xff;

sys/dev/pci/agp_ali.c

242

reg |= 0x90;

sys/dev/pci/agp_ali.c

243

pci_conf_write(sc->as_pc, sc->as_tag, AGP_ALI_TLBCTRL, reg);

sys/dev/pci/agp_ali.c

244

reg &= ~0xff;

sys/dev/pci/agp_ali.c

245

reg |= 0x10;

sys/dev/pci/agp_ali.c

246

pci_conf_write(sc->as_pc, sc->as_tag, AGP_ALI_TLBCTRL, reg);

sys/dev/pci/agp_ali.c

81

pcireg_t reg;

sys/dev/pci/agp_amd.c

173

pcireg_t reg;

sys/dev/pci/agp_amd.c

219

reg = pci_conf_read(pa->pa_pc, pa->pa_tag, AGP_AMD751_MODECTRL);

sys/dev/pci/agp_amd.c

220

reg &= ~0x00ff00ff;

sys/dev/pci/agp_amd.c

221

reg |= (AGP_AMD751_MODECTRL_SYNEN) | (AGP_AMD751_MODECTRL2_GPDCE << 16);

sys/dev/pci/agp_amd.c

222

pci_conf_write(pa->pa_pc, pa->pa_tag, AGP_AMD751_MODECTRL, reg);

sys/dev/pci/agp_amd.c

235

pcireg_t reg;

sys/dev/pci/agp_amd.c

243

reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_AMD751_MODECTRL);

sys/dev/pci/agp_amd.c

244

reg &= 0xffffff00;

sys/dev/pci/agp_amd.c

245

pci_conf_write(sc->as_pc, sc->as_tag, AGP_AMD751_MODECTRL, reg);

sys/dev/pci/agp_amd.c

278

pcireg_t reg;

sys/dev/pci/agp_amd.c

291

reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_AMD751_APCTRL);

sys/dev/pci/agp_amd.c

292

reg = (reg & ~0x06) | (vas << 1);

sys/dev/pci/agp_amd.c

293

pci_conf_write(sc->as_pc, sc->as_tag, AGP_AMD751_APCTRL, reg);

sys/dev/pci/agp_amd64.c

162

pcireg_t reg;

sys/dev/pci/agp_amd64.c

166

reg = pci_conf_read(pa->pa_pc, tag, PCI_CLASS_REG);

sys/dev/pci/agp_amd64.c

167

if (PCI_CLASS(reg) != PCI_CLASS_BRIDGE ||

sys/dev/pci/agp_amd64.c

168

PCI_SUBCLASS(reg) != PCI_SUBCLASS_BRIDGE_PCI)

sys/dev/pci/agp_amd64.c

171

reg = pci_conf_read(pa->pa_pc, tag, PCI_ID_REG);

sys/dev/pci/agp_amd64.c

172

if (PCI_VENDOR(reg) != PCI_VENDOR_NVIDIA || PCI_PRODUCT(reg) != devid)

sys/dev/pci/agp_amd64.c

182

pcireg_t reg;

sys/dev/pci/agp_amd64.c

186

reg = pci_conf_read(pa->pa_pc, tag, PCI_CLASS_REG);

sys/dev/pci/agp_amd64.c

187

if (PCI_CLASS(reg) != PCI_CLASS_BRIDGE ||

sys/dev/pci/agp_amd64.c

188

PCI_SUBCLASS(reg) != PCI_SUBCLASS_BRIDGE_PCI)

sys/dev/pci/agp_amd64.c

191

reg = pci_conf_read(pa->pa_pc, tag, PCI_ID_REG);

sys/dev/pci/agp_amd64.c

192

if (PCI_VENDOR(reg) != PCI_VENDOR_VIATECH ||

sys/dev/pci/agp_amd64.c

193

PCI_PRODUCT(reg) != PCI_PRODUCT_VIATECH_K8HTB_AGP)

sys/dev/pci/agp_apple.c

149

pcireg_t reg;

sys/dev/pci/agp_apple.c

152

reg = pci_conf_read(sc->as_pc, sc->as_tag, APPLE_UNINORTH_GART_BASE)

sys/dev/pci/agp_apple.c

154

reg |= ((aperture >> 22) & 0xfff);

sys/dev/pci/agp_apple.c

155

pci_conf_write(sc->as_pc, sc->as_tag, APPLE_UNINORTH_GART_BASE, reg);

sys/dev/pci/agp_i810.c

1144

pcireg_t reg;

sys/dev/pci/agp_i810.c

1152

reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I810_SMRAM);

sys/dev/pci/agp_i810.c

1153

miscc = (u_int16_t)(reg >> 16);

sys/dev/pci/agp_i810.c

1161

reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I830_GCC0);

sys/dev/pci/agp_i810.c

1162

gcc1 = (u_int16_t)(reg >> 16);

sys/dev/pci/agp_i810.c

295

agp_i965_map_aperture(struct pci_attach_args *pa, struct agp_softc *sc, int reg)

sys/dev/pci/agp_i810.c

301

if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, reg,

sys/dev/pci/agp_i810.c

840

pcireg_t reg;

sys/dev/pci/agp_i810.c

845

reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I830_GCC0);

sys/dev/pci/agp_i810.c

846

gcc1 = (u_int16_t)(reg >> 16);

sys/dev/pci/agp_i810.c

879

pcireg_t reg;

sys/dev/pci/agp_i810.c

883

reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I855_GCC1);

sys/dev/pci/agp_i810.c

884

gcc1 = (u_int16_t)(reg >> 16);

sys/dev/pci/agp_intel.c

195

pcireg_t reg;

sys/dev/pci/agp_intel.c

219

reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I840_MCHCFG);

sys/dev/pci/agp_intel.c

220

reg |= MCHCFG_AAGN;

sys/dev/pci/agp_intel.c

221

pci_conf_write(sc->as_pc, sc->as_tag, AGP_I840_MCHCFG, reg);

sys/dev/pci/agp_intel.c

227

reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCMD);

sys/dev/pci/agp_intel.c

228

reg |= AGPCMD_AGPEN;

sys/dev/pci/agp_intel.c

230

reg);

sys/dev/pci/agp_intel.c

231

reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I840_MCHCFG);

sys/dev/pci/agp_intel.c

232

reg |= MCHCFG_AAGN;

sys/dev/pci/agp_intel.c

234

reg);

sys/dev/pci/agp_intel.c

239

reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_NBXCFG);

sys/dev/pci/agp_intel.c

240

reg &= ~NBXCFG_APAE;

sys/dev/pci/agp_intel.c

241

reg |= NBXCFG_AAGN;

sys/dev/pci/agp_intel.c

242

pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_NBXCFG, reg);

sys/dev/pci/agp_intel.c

262

reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_ERRSTS);

sys/dev/pci/agp_intel.c

264

pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_ERRSTS, reg);

sys/dev/pci/agp_intel.c

276

pcireg_t reg;

sys/dev/pci/agp_intel.c

284

reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_NBXCFG);

sys/dev/pci/agp_intel.c

285

reg &= ~(1 << 9);

sys/dev/pci/agp_intel.c

286

printf("%s: set NBXCFG to %x\n", __func__, reg);

sys/dev/pci/agp_intel.c

287

pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_NBXCFG, reg);

sys/dev/pci/agp_intel.c

367

pcireg_t reg;

sys/dev/pci/agp_intel.c

376

reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL);

sys/dev/pci/agp_intel.c

377

reg &= ~AGPCTRL_GTLB;

sys/dev/pci/agp_intel.c

379

reg);

sys/dev/pci/agp_intel.c

381

reg | AGPCTRL_GTLB);

sys/dev/pci/agp_nvidia.c

241

pcireg_t reg;

sys/dev/pci/agp_nvidia.c

255

reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_NVIDIA_0_APSIZE);

sys/dev/pci/agp_nvidia.c

256

reg = (reg & ~AGP_NVIDIA_0_APSIZE_MASK) | apsize;

sys/dev/pci/agp_nvidia.c

257

pci_conf_write(sc->as_pc, sc->as_tag, AGP_NVIDIA_0_APSIZE, reg);

sys/dev/pci/agp_sis.c

118

reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_SIS_WINCTRL);

sys/dev/pci/agp_sis.c

119

reg |= (0x05 << 24) | 3;

sys/dev/pci/agp_sis.c

120

pci_conf_write(sc->as_pc, sc->as_tag, AGP_SIS_WINCTRL, reg);

sys/dev/pci/agp_sis.c

130

pcireg_t reg;

sys/dev/pci/agp_sis.c

137

reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_SIS_WINCTRL);

sys/dev/pci/agp_sis.c

138

reg &= ~3;

sys/dev/pci/agp_sis.c

139

reg &= 0x00ffffff;

sys/dev/pci/agp_sis.c

140

pci_conf_write(sc->as_pc, sc->as_tag, AGP_SIS_WINCTRL, reg);

sys/dev/pci/agp_sis.c

166

pcireg_t reg;

sys/dev/pci/agp_sis.c

179

reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_SIS_WINCTRL);

sys/dev/pci/agp_sis.c

180

reg &= ~0x00000070;

sys/dev/pci/agp_sis.c

181

reg |= gws << 4;

sys/dev/pci/agp_sis.c

182

pci_conf_write(sc->as_pc, sc->as_tag, AGP_SIS_WINCTRL, reg);

sys/dev/pci/agp_sis.c

214

pcireg_t reg;

sys/dev/pci/agp_sis.c

216

reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_SIS_TLBFLUSH);

sys/dev/pci/agp_sis.c

217

reg &= 0xffffff00;

sys/dev/pci/agp_sis.c

218

reg |= 0x02;

sys/dev/pci/agp_sis.c

219

pci_conf_write(sc->as_pc, sc->as_tag, AGP_SIS_TLBFLUSH, reg);

sys/dev/pci/agp_sis.c

80

pcireg_t reg;

sys/dev/pci/agp_via.c

235

pcireg_t reg;

sys/dev/pci/agp_via.c

249

reg = pci_conf_read(sc->as_pc, sc->as_tag,

sys/dev/pci/agp_via.c

251

reg &= ~0xff;

sys/dev/pci/agp_via.c

252

reg |= apsize;

sys/dev/pci/agp_via.c

254

asc->regs[REG_APSIZE], reg);

sys/dev/pci/agp_via.c

293

reg = pci_conf_read(sc->as_pc, sc->as_tag, asc->regs[REG_APSIZE]);

sys/dev/pci/agp_via.c

294

reg &= ~0xfff;

sys/dev/pci/agp_via.c

295

reg |= key;

sys/dev/pci/agp_via.c

296

pci_conf_write(sc->as_pc, sc->as_tag, asc->regs[REG_APSIZE], reg);

sys/dev/pci/ahcisata_pci.c

407

pcireg_t reg;

sys/dev/pci/ahcisata_pci.c

461

reg = pci_conf_read(psc->sc_pc, psc->sc_pcitag, PCI_COMMAND_STATUS_REG);

sys/dev/pci/ahcisata_pci.c

462

reg |= (PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE);

sys/dev/pci/ahcisata_pci.c

463

pci_conf_write(psc->sc_pc, psc->sc_pcitag, PCI_COMMAND_STATUS_REG, reg);

sys/dev/pci/ahd_pci.c

321

pcireg_t reg;

sys/dev/pci/ahd_pci.c

507

reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);

sys/dev/pci/ahd_pci.c

509

reg | PCI_COMMAND_MASTER_ENABLE);

sys/dev/pci/ahd_pci.c

957

u_int reg;

sys/dev/pci/ahd_pci.c

972

for (i = 0, reg = DF0PCISTAT; i < 8; i++, reg++) {

sys/dev/pci/ahd_pci.c

976

pci_status[i] = ahd_inb(ahd, reg);

sys/dev/pci/ahd_pci.c

978

ahd_outb(ahd, reg, pci_status[i]);

sys/dev/pci/alipm.c

136

pcireg_t iobase, reg;

sys/dev/pci/alipm.c

142

reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);

sys/dev/pci/alipm.c

143

if ((reg & PCI_STATUS_CAPLIST_SUPPORT) == 0) {

sys/dev/pci/alipm.c

157

reg = pci_conf_read(pa->pa_pc, pa->pa_tag, ALIPM_CONF);

sys/dev/pci/alipm.c

158

if ((reg & ALIPM_CONF_SMBEN) == 0) {

sys/dev/pci/alipm.c

163

reg = pci_conf_read(pa->pa_pc, pa->pa_tag, ALIPM_SMB_HOSTC);

sys/dev/pci/alipm.c

164

if ((reg & ALIPM_SMB_HOSTC_HSTEN) == 0) {

sys/dev/pci/alipm.c

176

reg = pci_conf_read(pa->pa_pc, pa->pa_tag, ALIPM_SMB_HOSTX);

sys/dev/pci/alipm.c

177

if ((reg & ALIPM_SMB_HOSTC_HSTEN) == 0) {

sys/dev/pci/alipm.c

183

switch (reg & ALIPM_SMB_HOSTC_CLOCK) {

sys/dev/pci/amr.c

280

pcireg_t reg;

sys/dev/pci/amr.c

303

reg = pci_conf_read(pc, pa->pa_tag, i);

sys/dev/pci/amr.c

304

switch (PCI_MAPREG_TYPE(reg)) {

sys/dev/pci/amr.c

306

if (PCI_MAPREG_MEM_SIZE(reg) != 0)

sys/dev/pci/amr.c

310

if (PCI_MAPREG_IO_SIZE(reg) != 0)

sys/dev/pci/amr.c

333

reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);

sys/dev/pci/amr.c

335

reg | PCI_COMMAND_MASTER_ENABLE);

sys/dev/pci/arcmsr.c

1595

uint32_t reg, rwlen;

sys/dev/pci/arcmsr.c

1627

reg = ARC_REG_OUTB_DOORBELL_READ_OK;

sys/dev/pci/arcmsr.c

1630

if ((reg & ARC_REG_OUTB_DOORBELL_READ_OK) && wdone < wlen) {

sys/dev/pci/arcmsr.c

1657

while ((reg = arc_read(sc, ARC_REG_OUTB_DOORBELL)) == 0)

sys/dev/pci/arcmsr.c

1660

arc_write(sc, ARC_REG_OUTB_DOORBELL, reg);

sys/dev/pci/arcmsr.c

1663

device_xname(sc->sc_dev), reg);

sys/dev/pci/arcmsr.c

1665

if ((reg & ARC_REG_OUTB_DOORBELL_WRITE_OK) && rdone < rlen) {

sys/dev/pci/arcmsr.c

334

uint32_t reg, intrstat;

sys/dev/pci/arcmsr.c

353

reg = arc_read(sc, ARC_REG_OUTB_DOORBELL);

sys/dev/pci/arcmsr.c

354

arc_write(sc, ARC_REG_OUTB_DOORBELL, reg);

sys/dev/pci/arcmsr.c

355

if (reg & ARC_REG_OUTB_DOORBELL_WRITE_OK)

sys/dev/pci/arcmsr.c

362

while ((reg = arc_pop(sc)) != 0xffffffff) {

sys/dev/pci/arcmsr.c

364

((reg << ARC_REG_REPLY_QUEUE_ADDR_SHIFT) -

sys/dev/pci/arcmsr.c

372

arc_scsi_cmd_done(sc, ccb, reg);

sys/dev/pci/arcmsr.c

388

uint32_t reg;

sys/dev/pci/arcmsr.c

439

reg = ccb->ccb_cmd_post;

sys/dev/pci/arcmsr.c

452

reg |= ARC_REG_POST_QUEUE_BIGFRAME;

sys/dev/pci/arcmsr.c

465

arc_push(sc, reg);

sys/dev/pci/arcmsr.c

518

arc_scsi_cmd_done(struct arc_softc *sc, struct arc_ccb *ccb, uint32_t reg)

sys/dev/pci/arcmsr.c

534

if (reg & ARC_REG_REPLY_QUEUE_ERR) {

sys/dev/pci/arcmsr.c

578

uint32_t reg;

sys/dev/pci/arcmsr.c

581

reg = arc_pop(sc);

sys/dev/pci/arcmsr.c

582

if (reg == 0xffffffff) {

sys/dev/pci/arcmsr.c

591

((reg << ARC_REG_REPLY_QUEUE_ADDR_SHIFT) -

sys/dev/pci/arcmsr.c

599

arc_scsi_cmd_done(sc, ccb, reg);

sys/dev/pci/auacer.c

382

auacer_read_codec(void *v, uint8_t reg, uint16_t *val)

sys/dev/pci/auacer.c

390

reg |= ALI_CPR_ADDR_READ;

sys/dev/pci/auacer.c

393

reg |= ALI_CPR_ADDR_SECONDARY;

sys/dev/pci/auacer.c

395

WRITE2(sc, ALI_CPR_ADDR, reg);

sys/dev/pci/auacer.c

401

reg, *val));

sys/dev/pci/auacer.c

407

auacer_write_codec(void *v, uint8_t reg, uint16_t val)

sys/dev/pci/auacer.c

412

reg, val));

sys/dev/pci/auacer.c

419

reg |= ALI_CPR_ADDR_SECONDARY;

sys/dev/pci/auacer.c

421

WRITE2(sc, ALI_CPR_ADDR, reg);

sys/dev/pci/auacer.c

440

uint32_t reg;

sys/dev/pci/auacer.c

445

reg = READ4(sc, ALI_SCR);

sys/dev/pci/auacer.c

446

if ((reg & 2) == 0) /* Cold required */

sys/dev/pci/auacer.c

447

reg |= 2;

sys/dev/pci/auacer.c

449

reg |= 1; /* Warm */

sys/dev/pci/auacer.c

450

reg &= ~0x80000000; /* ACLink on */

sys/dev/pci/auacer.c

451

WRITE4(sc, ALI_SCR, reg);

sys/dev/pci/auacer.c

464

reg = READ4(sc, ALI_RTSR);

sys/dev/pci/auacer.c

465

if (reg & 0x80) /* primary codec */

sys/dev/pci/auacer.c

467

WRITE4(sc, ALI_RTSR, reg | 0x80);

sys/dev/pci/auich.c

778

auich_read_codec(void *v, uint8_t reg, uint16_t *val)

sys/dev/pci/auich.c

805

reg + (sc->sc_codecnum * ICH_CODEC_OFFSET));

sys/dev/pci/auich.c

807

(sc->sc_dev, "%s(%x, %x)\n", __func__, reg, *val));

sys/dev/pci/auich.c

817

if (reg == AC97_REG_GPIO_STATUS)

sys/dev/pci/auich.c

821

if (reg == AC97_REG_GPIO_STATUS)

sys/dev/pci/auich.c

826

if (reg == AC97_REG_GPIO_STATUS)

sys/dev/pci/auich.c

833

auich_write_codec(void *v, uint8_t reg, uint16_t val)

sys/dev/pci/auich.c

840

__func__, reg, val));

sys/dev/pci/auich.c

854

reg + (sc->sc_codecnum * ICH_CODEC_OFFSET), val);

sys/dev/pci/auixp.c

1347

auixp_read_codec(void *aux, uint8_t reg, uint16_t *result)

sys/dev/pci/auixp.c

1364

data = (reg << ATI_REG_PHYS_OUT_ADDR_SHIFT) |

sys/dev/pci/auixp.c

1380

reg, data >> ATI_REG_PHYS_IN_DATA_SHIFT)

sys/dev/pci/auixp.c

1389

if (reg < 0x7c)

sys/dev/pci/auixp.c

1391

device_xname(sc->sc_dev), reg);

sys/dev/pci/auixp.c

1398

auixp_write_codec(void *aux, uint8_t reg, uint16_t data)

sys/dev/pci/auixp.c

1406

DPRINTF(("write ac'97 codec reg 0x%x = 0x%08x\n", reg, data));

sys/dev/pci/auixp.c

1416

(((uint32_t) reg) << ATI_REG_PHYS_OUT_ADDR_SHIFT) |

sys/dev/pci/autri.c

1065

uint32_t reg, cr[5];

sys/dev/pci/autri.c

1174

reg = TREAD4(sc,AUTRI_LFO_GC_CIR) & ~0x0000003f;

sys/dev/pci/autri.c

1175

TWRITE4(sc,AUTRI_LFO_GC_CIR, reg | channel);

sys/dev/pci/autri.c

1308

int reg;

sys/dev/pci/autri.c

1310

reg = (ch & 0x20) ? AUTRI_AINTEN_B : AUTRI_AINTEN_A;

sys/dev/pci/autri.c

1313

autri_reg_set_4(sc, reg, 1 << ch);

sys/dev/pci/autri.c

1319

int reg;

sys/dev/pci/autri.c

1321

reg = (ch & 0x20) ? AUTRI_AINTEN_B : AUTRI_AINTEN_A;

sys/dev/pci/autri.c

1324

autri_reg_clear_4(sc, reg, 1 << ch);

sys/dev/pci/autri.c

1330

int reg;

sys/dev/pci/autri.c

1333

reg = (ch & 0x20) ? AUTRI_START_B : AUTRI_START_A;

sys/dev/pci/autri.c

1338

autri_reg_set_4(sc, reg, chmask);

sys/dev/pci/autri.c

1344

int reg;

sys/dev/pci/autri.c

1347

reg = (ch & 0x20) ? AUTRI_STOP_B : AUTRI_STOP_A;

sys/dev/pci/autri.c

1352

autri_reg_set_4(sc, reg, chmask);

sys/dev/pci/autri.c

372

uint32_t reg, ready;

sys/dev/pci/autri.c

434

reg = TREAD4(sc, addr);

sys/dev/pci/autri.c

435

if (reg & ready)

sys/dev/pci/autri.c

506

uint32_t reg;

sys/dev/pci/autri.c

552

reg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);

sys/dev/pci/autri.c

553

reg |= (PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE);

sys/dev/pci/autri.c

554

pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, reg);

sys/dev/pci/autri.c

608

uint32_t reg;

sys/dev/pci/autri.c

623

reg = pci_conf_read(pc, pt, AUTRI_PCI_LEGACY_IOBASE);

sys/dev/pci/autri.c

624

pci_conf_write(pc, pt, AUTRI_PCI_LEGACY_IOBASE, reg & 0xffff0000);

sys/dev/pci/autri.c

627

reg = pci_conf_read(pc, pt, AUTRI_PCI_LEGACY_IOBASE);

sys/dev/pci/autri.c

628

pci_conf_write(pc, pt, AUTRI_PCI_LEGACY_IOBASE, reg | 0x00040000);

sys/dev/pci/autri.c

631

reg = pci_conf_read(pc, pt, AUTRI_PCI_LEGACY_IOBASE);

sys/dev/pci/autri.c

632

pci_conf_write(pc, pt, AUTRI_PCI_LEGACY_IOBASE, reg & ~0x00040000);

sys/dev/pci/autri.c

640

reg = pci_conf_read(pc, pt, AUTRI_PCI_LEGACY_IOBASE);

sys/dev/pci/autri.c

641

pci_conf_write(pc, pt, AUTRI_PCI_LEGACY_IOBASE, reg & 0xffff0000);

sys/dev/pci/autri.c

644

reg = pci_conf_read(pc, pt, AUTRI_PCI_LEGACY_IOBASE);

sys/dev/pci/autri.c

645

pci_conf_write(pc, pt, AUTRI_PCI_LEGACY_IOBASE, reg | 0x00010000);

sys/dev/pci/autri.c

648

reg = pci_conf_read(pc, pt, AUTRI_PCI_LEGACY_IOBASE);

sys/dev/pci/autri.c

649

pci_conf_write(pc, pt, AUTRI_PCI_LEGACY_IOBASE, reg & ~0x00010000);

sys/dev/pci/autri.c

657

reg = pci_conf_read(pc, pt, AUTRI_PCI_LEGACY_IOBASE);

sys/dev/pci/autri.c

658

pci_conf_write(pc, pt, AUTRI_PCI_LEGACY_IOBASE, reg & 0xffff0000);

sys/dev/pci/autri.c

661

reg = pci_conf_read(pc, pt, AUTRI_PCI_LEGACY_IOBASE);

sys/dev/pci/autri.c

662

pci_conf_write(pc, pt, AUTRI_PCI_LEGACY_IOBASE, reg | 0x000c0000);

sys/dev/pci/autri.c

665

reg = pci_conf_read(pc, pt, AUTRI_PCI_LEGACY_IOBASE);

sys/dev/pci/autri.c

666

pci_conf_write(pc, pt, AUTRI_PCI_LEGACY_IOBASE, reg & ~0x00040000);

sys/dev/pci/autri.c

676

reg = pci_conf_read(pc, pt, AUTRI_PCI_LEGACY_IOBASE);

sys/dev/pci/autri.c

677

pci_conf_write(pc, pt, AUTRI_PCI_LEGACY_IOBASE, reg & 0xffff0000);

sys/dev/pci/autri.c

680

reg = pci_conf_read(pc, pt, AUTRI_PCI_LEGACY_IOBASE);

sys/dev/pci/autri.c

681

pci_conf_write(pc, pt, AUTRI_PCI_LEGACY_IOBASE, reg | 0x000c0000);

sys/dev/pci/autri.c

684

reg = pci_conf_read(pc, pt, AUTRI_PCI_LEGACY_IOBASE);

sys/dev/pci/autri.c

685

pci_conf_write(pc, pt, AUTRI_PCI_LEGACY_IOBASE, reg & ~0x00040000);

sys/dev/pci/autri.c

729

uint32_t reg;

sys/dev/pci/autri.c

732

reg = ENDLP_IE;

sys/dev/pci/autri.c

735

reg |= BANK_B_EN;

sys/dev/pci/autri.c

737

autri_reg_set_4(sc, AUTRI_LFO_GC_CIR, reg);

sys/dev/pci/autri.c

745

uint32_t reg;

sys/dev/pci/autri.c

747

reg = (ENDLP_IE | MIDLP_IE);

sys/dev/pci/autri.c

749

autri_reg_clear_4(sc, AUTRI_LFO_GC_CIR, reg);

sys/dev/pci/autri.c

793

reg = TREAD4(sc,AUTRI_LFO_GC_CIR) & ~0x0000003f;

sys/dev/pci/autri.c

794

TWRITE4(sc,AUTRI_LFO_GC_CIR, reg | ch);

sys/dev/pci/auvia.c

565

auvia_write_codec(void *addr, u_int8_t reg, u_int16_t val)

sys/dev/pci/auvia.c

574

AUVIA_CODEC_PRIVALID | AUVIA_CODEC_INDEX(reg) | val);

sys/dev/pci/auvia.c

580

auvia_read_codec(void *addr, u_int8_t reg, u_int16_t *val)

sys/dev/pci/auvia.c

589

AUVIA_CODEC_PRIVALID | AUVIA_CODEC_READ | AUVIA_CODEC_INDEX(reg));

sys/dev/pci/auvia.c

694

int reg, mode;

sys/dev/pci/auvia.c

708

reg = AC97_REG_PCM_FRONT_DAC_RATE;

sys/dev/pci/auvia.c

712

reg = AC97_REG_PCM_LR_ADC_RATE;

sys/dev/pci/auvia.c

717

if (codec->vtbl->set_rate(codec, reg, &rate))

sys/dev/pci/auvia.c

719

reg = AC97_REG_PCM_SURR_DAC_RATE;

sys/dev/pci/auvia.c

722

&& codec->vtbl->set_rate(codec, reg, &rate))

sys/dev/pci/auvia.c

724

reg = AC97_REG_PCM_LFE_DAC_RATE;

sys/dev/pci/auvia.c

727

&& codec->vtbl->set_rate(codec, reg, &rate))

sys/dev/pci/bochsfb.c

303

bochsfb_write_dispi(struct bochsfb_softc *sc, uint16_t reg, uint16_t val)

sys/dev/pci/bochsfb.c

308

BOCHSFB_MMIO_DISPI_OFFSET + reg * 2, val);

sys/dev/pci/bochsfb.c

312

VBE_DISPI_IOPORT_INDEX - VBE_DISPI_IOPORT_INDEX, reg);

sys/dev/pci/bochsfb.c

322

bochsfb_read_dispi(struct bochsfb_softc *sc, uint16_t reg)

sys/dev/pci/bochsfb.c

327

BOCHSFB_MMIO_DISPI_OFFSET + reg * 2);

sys/dev/pci/bochsfb.c

331

VBE_DISPI_IOPORT_INDEX - VBE_DISPI_IOPORT_INDEX, reg);

sys/dev/pci/bochsfb.c

341

bochsfb_write_vga(struct bochsfb_softc *sc, uint16_t reg, uint8_t val)

sys/dev/pci/bochsfb.c

346

reg - VGA_IO_START + BOCHSFB_MMIO_VGA_OFFSET,

sys/dev/pci/bochsfb.c

351

bus_space_write_1(sc->sc_iot, sc->sc_ioh_vga, reg, val);

sys/dev/pci/bochsfb.c

358

bochsfb_read_vga(struct bochsfb_softc *sc, uint16_t reg)

sys/dev/pci/bochsfb.c

363

reg - VGA_IO_START + BOCHSFB_MMIO_VGA_OFFSET);

sys/dev/pci/bochsfb.c

366

return bus_space_read_1(sc->sc_iot, sc->sc_ioh_vga, reg);

sys/dev/pci/bochsfb.c

62

static void bochsfb_write_dispi(struct bochsfb_softc *sc, uint16_t reg,

sys/dev/pci/bochsfb.c

64

static uint16_t bochsfb_read_dispi(struct bochsfb_softc *sc, uint16_t reg);

sys/dev/pci/bochsfb.c

65

static void bochsfb_write_vga(struct bochsfb_softc *sc, uint16_t reg,

sys/dev/pci/bochsfb.c

67

static uint8_t bochsfb_read_vga(struct bochsfb_softc *sc, uint16_t reg);

sys/dev/pci/btvmeivar.h

69

#define read_csr_byte(sc, reg) \

sys/dev/pci/btvmeivar.h

70

bus_space_read_1(sc->csrt, sc->csrh, reg)

sys/dev/pci/btvmeivar.h

71

#define write_csr_byte(sc, reg, val) \

sys/dev/pci/btvmeivar.h

72

bus_space_write_1(sc->csrt, sc->csrh, reg, val)

sys/dev/pci/btvmeivar.h

73

#define read_csr_word(sc, reg) \

sys/dev/pci/btvmeivar.h

74

bus_space_read_2(sc->csrt, sc->csrh, reg)

sys/dev/pci/btvmeivar.h

75

#define write_csr_word(sc, reg, val) \

sys/dev/pci/btvmeivar.h

76

bus_space_write_2(sc->csrt, sc->csrh, reg, val)

sys/dev/pci/cac_pci.c

151

pcireg_t reg;

sys/dev/pci/cac_pci.c

170

reg = pci_conf_read(pa->pa_pc, pa->pa_tag, i);

sys/dev/pci/cac_pci.c

172

if (PCI_MAPREG_TYPE(reg) == PCI_MAPREG_TYPE_IO) {

sys/dev/pci/cac_pci.c

173

if (ior == -1 && PCI_MAPREG_IO_SIZE(reg) != 0)

sys/dev/pci/cac_pci.c

176

if (memr == -1 && PCI_MAPREG_MEM_SIZE(reg) != 0)

sys/dev/pci/cac_pci.c

200

reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);

sys/dev/pci/cac_pci.c

202

reg | PCI_COMMAND_MASTER_ENABLE);

sys/dev/pci/ciss_pci.c

135

pcireg_t reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG);

sys/dev/pci/ciss_pci.c

142

(PCI_VENDOR(reg) == ciss_pci_devices[i].vendor &&

sys/dev/pci/ciss_pci.c

143

PCI_PRODUCT(reg) == ciss_pci_devices[i].product))

sys/dev/pci/ciss_pci.c

159

pcireg_t reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG);

sys/dev/pci/ciss_pci.c

171

(PCI_VENDOR(reg) == ciss_pci_devices[i].vendor &&

sys/dev/pci/ciss_pci.c

172

PCI_PRODUCT(reg) == ciss_pci_devices[i].product))

sys/dev/pci/ciss_pci.c

193

reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG);

sys/dev/pci/ciss_pci.c

194

if (PCI_VENDOR(reg) == PCI_VENDOR_COMPAQ &&

sys/dev/pci/ciss_pci.c

195

(PCI_PRODUCT(reg) == PCI_PRODUCT_COMPAQ_CSA5i ||

sys/dev/pci/ciss_pci.c

196

PCI_PRODUCT(reg) == PCI_PRODUCT_COMPAQ_CSA532 ||

sys/dev/pci/ciss_pci.c

197

PCI_PRODUCT(reg) == PCI_PRODUCT_COMPAQ_CSA5312))

sys/dev/pci/cmdide.c

530

int interface, i, reg;

sys/dev/pci/cmdide.c

550

reg = 0xa2 + channel * 16;

sys/dev/pci/cmdide.c

552

pciide_pci_write(sc->sc_pc, sc->sc_tag, reg + i, init_val[i]);

sys/dev/pci/coram.c

163

pcireg_t reg;

sys/dev/pci/coram.c

174

reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG);

sys/dev/pci/coram.c

175

sc->sc_board = coram_board_lookup(PCI_VENDOR(reg), PCI_PRODUCT(reg));

sys/dev/pci/coram.c

204

reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);

sys/dev/pci/coram.c

205

reg |= PCI_COMMAND_MASTER_ENABLE;

sys/dev/pci/coram.c

206

pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, reg);

sys/dev/pci/cs4280.c

250

pcireg_t reg;

sys/dev/pci/cs4280.c

302

reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);

sys/dev/pci/cs4280.c

304

reg | PCI_COMMAND_MASTER_ENABLE);

sys/dev/pci/cs4280.c

807

cs4280_read_codec(void *addr, u_int8_t reg, u_int16_t *result)

sys/dev/pci/cs4280.c

813

rv = cs428x_read_codec(addr, reg, result);

sys/dev/pci/cs4280.c

820

cs4280_write_codec(void *addr, u_int8_t reg, u_int16_t data)

sys/dev/pci/cs4280.c

826

rv = cs428x_write_codec(addr, reg, data);

sys/dev/pci/cs4280.c

935

uint16_t reg;

sys/dev/pci/cs4280.c

945

reg = pci_conf_read(smbuspa.pa_pc, smbuspa.pa_tag, 0x40);

sys/dev/pci/cs4280.c

946

port = reg & 0xffc0;

sys/dev/pci/cs4281.c

189

pcireg_t reg;

sys/dev/pci/cs4281.c

227

reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);

sys/dev/pci/cs4281.c

229

reg | PCI_COMMAND_MASTER_ENABLE);

sys/dev/pci/cxdtv.c

162

pcireg_t reg;

sys/dev/pci/cxdtv.c

172

reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG);

sys/dev/pci/cxdtv.c

173

if (cxdtv_board_lookup(PCI_VENDOR(reg), PCI_PRODUCT(reg)) == NULL)

sys/dev/pci/cxdtv.c

185

pcireg_t reg;

sys/dev/pci/cxdtv.c

194

reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG);

sys/dev/pci/cxdtv.c

196

sc->sc_vendor = PCI_VENDOR(reg);

sys/dev/pci/cxdtv.c

197

sc->sc_product = PCI_PRODUCT(reg);

sys/dev/pci/cxdtv.c

229

reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);

sys/dev/pci/cxdtv.c

230

reg |= PCI_COMMAND_MASTER_ENABLE;

sys/dev/pci/cxdtv.c

231

pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, reg);

sys/dev/pci/cxgb/cxgb_adapter.h

445

t3_os_pci_read_config_4(adapter_t *adapter, int reg, uint32_t *val)

sys/dev/pci/cxgb/cxgb_adapter.h

447

*val = pci_conf_read(adapter->pa.pa_pc, adapter->pa.pa_tag, reg);

sys/dev/pci/cxgb/cxgb_adapter.h

451

t3_os_pci_write_config_4(adapter_t *adapter, int reg, uint32_t val)

sys/dev/pci/cxgb/cxgb_adapter.h

453

pci_conf_write(adapter->pa.pa_pc, adapter->pa.pa_tag, reg, val);

sys/dev/pci/cxgb/cxgb_adapter.h

457

t3_os_pci_read_config_2(adapter_t *adapter, int reg, uint16_t *val)

sys/dev/pci/cxgb/cxgb_adapter.h

460

temp = pci_conf_read(adapter->pa.pa_pc, adapter->pa.pa_tag, reg&0xfc);

sys/dev/pci/cxgb/cxgb_adapter.h

461

if (reg&0x2)

sys/dev/pci/cxgb/cxgb_adapter.h

468

t3_os_pci_write_config_2(adapter_t *adapter, int reg, uint16_t val)

sys/dev/pci/cxgb/cxgb_adapter.h

470

uint32_t temp = pci_conf_read(adapter->pa.pa_pc, adapter->pa.pa_tag, reg&0xfc);

sys/dev/pci/cxgb/cxgb_adapter.h

471

if (reg&0x2)

sys/dev/pci/cxgb/cxgb_adapter.h

475

pci_conf_write(adapter->pa.pa_pc, adapter->pa.pa_tag, reg&0xfc, temp);

sys/dev/pci/cxgb/cxgb_common.h

542

static __inline int mdio_read(struct cphy *phy, int mmd, int reg,

sys/dev/pci/cxgb/cxgb_common.h

545

return phy->mdio_read(phy->adapter, phy->addr, mmd, reg, valp);

sys/dev/pci/cxgb/cxgb_common.h

548

static __inline int mdio_write(struct cphy *phy, int mmd, int reg,

sys/dev/pci/cxgb/cxgb_common.h

551

return phy->mdio_write(phy->adapter, phy->addr, mmd, reg, val);

sys/dev/pci/cxgb/cxgb_common.h

635

int t3_wait_op_done_val(adapter_t *adapter, int reg, u32 mask, int polarity,

sys/dev/pci/cxgb/cxgb_common.h

638

static __inline int t3_wait_op_done(adapter_t *adapter, int reg, u32 mask,

sys/dev/pci/cxgb/cxgb_common.h

641

return t3_wait_op_done_val(adapter, reg, mask, polarity, attempts,

sys/dev/pci/cxgb/cxgb_common.h

645

int t3_mdio_change_bits(struct cphy *phy, int mmd, int reg, unsigned int clear,

sys/dev/pci/cxgb/cxgb_main.c

303

int reg;

sys/dev/pci/cxgb/cxgb_main.c

319

if (pci_find_extcap(dev, PCIY_EXPRESS, &reg) == 0) {

sys/dev/pci/cxgb/cxgb_main.c

321

lnk = pci_read_config(dev, reg + 0x12, 2);

sys/dev/pci/cxgb/cxgb_main.c

324

pectl = pci_read_config(dev, reg + 0x8, 2);

sys/dev/pci/cxgb/cxgb_main.c

326

pci_write_config(dev, reg + 0x8, pectl, 2);

sys/dev/pci/cxgb/cxgb_main.c

346

t3_os_pci_read_config_4(sc, PCI_MAPREG_START, &reg);

sys/dev/pci/cxgb/cxgb_main.c

349

sc->bar0 = reg&0xFFFFF000;

sys/dev/pci/cxgb/cxgb_osdep.c

202

uint32_t reg;

sys/dev/pci/cxgb/cxgb_osdep.c

204

t3_os_pci_read_config_4(sc, PCI_COMMAND_STATUS_REG, &reg);

sys/dev/pci/cxgb/cxgb_osdep.c

205

reg |= PCI_COMMAND_MASTER_ENABLE;

sys/dev/pci/cxgb/cxgb_osdep.c

206

t3_os_pci_write_config_4(sc, PCI_COMMAND_STATUS_REG, reg);

sys/dev/pci/cxgb/cxgb_t3_hw.c

1226

static int t3_handle_intr_status(adapter_t *adapter, unsigned int reg,

sys/dev/pci/cxgb/cxgb_t3_hw.c

1232

unsigned int status = t3_read_reg(adapter, reg) & mask;

sys/dev/pci/cxgb/cxgb_t3_hw.c

1247

t3_write_reg(adapter, reg, status);

sys/dev/pci/cxgb/cxgb_t3_hw.c

2423

#define mem_region(adap, start, size, reg) \

sys/dev/pci/cxgb/cxgb_t3_hw.c

2424

t3_write_reg((adap), A_ ## reg, (start)); \

sys/dev/pci/cxgb/cxgb_t3_hw.c

318

int t3_mdio_change_bits(struct cphy *phy, int mmd, int reg, unsigned int clear,

sys/dev/pci/cxgb/cxgb_t3_hw.c

324

ret = mdio_read(phy, mmd, reg, &val);

sys/dev/pci/cxgb/cxgb_t3_hw.c

327

ret = mdio_write(phy, mmd, reg, val | set);

sys/dev/pci/cxgb/cxgb_t3_hw.c

58

int t3_wait_op_done_val(adapter_t *adapter, int reg, u32 mask, int polarity,

sys/dev/pci/cxgb/cxgb_t3_hw.c

62

u32 val = t3_read_reg(adapter, reg);

sys/dev/pci/cxgb/cxgb_vsc7323.c

288

#define ELMR_STAT(port, reg) (ELMR_STATS + port * 0x40 + reg)

sys/dev/pci/cxgb/cxgb_vsc7323.c

54

#define VSC_REG(block, subblock, reg) \

sys/dev/pci/cxgb/cxgb_vsc7323.c

55

((reg) | ((subblock) << 8) | ((block) << 12))

sys/dev/pci/cxgb/cxgb_xgmac.c

267

unsigned int i, reg = mac->offset + A_XGM_RX_EXACT_MATCH_LOW_1;

sys/dev/pci/cxgb/cxgb_xgmac.c

269

for (i = 0; i < EXACT_ADDR_FILTERS; i++, reg += 8) {

sys/dev/pci/cxgb/cxgb_xgmac.c

270

u32 v = t3_read_reg(mac->adapter, reg);

sys/dev/pci/cxgb/cxgb_xgmac.c

271

t3_write_reg(mac->adapter, reg, v);

sys/dev/pci/cxgb/cxgb_xgmac.c

278

unsigned int i, reg = mac->offset + A_XGM_RX_EXACT_MATCH_HIGH_1;

sys/dev/pci/cxgb/cxgb_xgmac.c

280

for (i = 0; i < EXACT_ADDR_FILTERS; i++, reg += 8) {

sys/dev/pci/cxgb/cxgb_xgmac.c

281

u32 v = t3_read_reg(mac->adapter, reg);

sys/dev/pci/cxgb/cxgb_xgmac.c

282

t3_write_reg(mac->adapter, reg, v);

sys/dev/pci/cxgb/cxgb_xgmac.c

634

#define RMON_UPDATE(mac, name, reg) \

sys/dev/pci/cxgb/cxgb_xgmac.c

635

(mac)->stats.name += (u64)RMON_READ(mac, A_XGM_STAT_##reg)

sys/dev/pci/cy82c693.c

101

cy82c693_read(const struct cy82c693_handle *cyhc, int reg)

sys/dev/pci/cy82c693.c

110

bus_space_write_1(cyhc->cyhc_iot, cyhc->cyhc_ioh, 0, reg);

sys/dev/pci/cy82c693.c

119

cy82c693_write(const struct cy82c693_handle *cyhc, int reg, u_int8_t val)

sys/dev/pci/cy82c693.c

127

bus_space_write_1(cyhc->cyhc_iot, cyhc->cyhc_ioh, 0, reg);

sys/dev/pci/cz.c

196

#define CZ_PLX_READ(cz, reg) \

sys/dev/pci/cz.c

197

bus_space_read_4((cz)->cz_plx.plx_st, (cz)->cz_plx.plx_sh, (reg))

sys/dev/pci/cz.c

198

#define CZ_PLX_WRITE(cz, reg, val) \

sys/dev/pci/cz.c

200

(reg), (val))

sys/dev/pci/cz.c

206

#define CZ_FPGA_READ(cz, reg) \

sys/dev/pci/cz.c

207

bus_space_read_4((cz)->cz_win_st, (cz)->cz_win_sh, (reg))

sys/dev/pci/cz.c

208

#define CZ_FPGA_WRITE(cz, reg, val) \

sys/dev/pci/cz.c

209

bus_space_write_4((cz)->cz_win_st, (cz)->cz_win_sh, (reg), (val))

sys/dev/pci/cz.c

451

u_int32_t reg;

sys/dev/pci/cz.c

453

reg = CZ_PLX_READ(cz, PLX_CONTROL);

sys/dev/pci/cz.c

454

CZ_PLX_WRITE(cz, PLX_CONTROL, reg | CONTROL_SWR);

sys/dev/pci/cz.c

457

CZ_PLX_WRITE(cz, PLX_CONTROL, reg);

sys/dev/pci/cz.c

461

reg = CZ_PLX_READ(cz, PLX_CONTROL);

sys/dev/pci/cz.c

462

CZ_PLX_WRITE(cz, PLX_CONTROL, reg | CONTROL_RELOADCFG);

sys/dev/pci/cz.c

464

CZ_PLX_WRITE(cz, PLX_CONTROL, reg);

sys/dev/pci/czreg.h

220

#define ZFIRM_CHNCTL_OFF(chan, reg) \

sys/dev/pci/czreg.h

221

(ZFIRM_BRDCTL_SIZE + ((chan) * ZFIRM_CHNCTL_SIZE) + (reg))

sys/dev/pci/czreg.h

222

#define ZFIRM_BUFCTL_OFF(chan, reg) \

sys/dev/pci/czreg.h

224

((chan) * ZFIRM_BUFCTL_SIZE) + (reg))

sys/dev/pci/emuxki.c

1288

emuxki_ac97_read(void *hdl, uint8_t reg, uint16_t *val)

sys/dev/pci/emuxki.c

1293

emuxki_writeio_1(sc, EMU_AC97ADDR, reg);

sys/dev/pci/emuxki.c

1301

emuxki_ac97_write(void *hdl, uint8_t reg, uint16_t val)

sys/dev/pci/emuxki.c

1306

emuxki_writeio_1(sc, EMU_AC97ADDR, reg);

sys/dev/pci/emuxki.c

359

pcireg_t reg;

sys/dev/pci/emuxki.c

363

reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG);

sys/dev/pci/emuxki.c

365

PCI_PRODUCT(pa->pa_id), reg,

sys/dev/pci/emuxki.c

381

pcireg_t reg;

sys/dev/pci/emuxki.c

387

reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG);

sys/dev/pci/emuxki.c

389

PCI_PRODUCT(pa->pa_id), reg,

sys/dev/pci/emuxki.c

412

reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);

sys/dev/pci/emuxki.c

413

reg |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE |

sys/dev/pci/emuxki.c

415

pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, reg);

sys/dev/pci/emuxki.c

692

int reg;

sys/dev/pci/emuxki.c

695

reg = EMU_A_MICROCODEBASE;

sys/dev/pci/emuxki.c

702

reg = EMU_MICROCODEBASE;

sys/dev/pci/emuxki.c

710

reg += (*pc) * 2;

sys/dev/pci/emuxki.c

712

emuxki_write(sc, 0, reg, loword);

sys/dev/pci/emuxki.c

713

emuxki_write(sc, 0, reg + 1, hiword);

sys/dev/pci/emuxkireg.h

48

#define EMU_MKSUBREG(sz, idx, reg) (((sz) << 24) | ((idx) << 16) | (reg))

sys/dev/pci/esa.c

1182

esa_read_codec(void *aux, uint8_t reg, uint16_t *result)

sys/dev/pci/esa.c

1193

bus_space_write_1(iot, ioh, ESA_CODEC_COMMAND, (reg & 0x7f) | 0x80);

sys/dev/pci/esa.c

1203

esa_write_codec(void *aux, uint8_t reg, uint16_t data)

sys/dev/pci/esa.c

1217

bus_space_write_1(iot, ioh, ESA_CODEC_COMMAND, reg & 0x7f);

sys/dev/pci/esm.c

386

wp_rdreg(struct esm_softc *ess, uint16_t reg)

sys/dev/pci/esm.c

389

bus_space_write_2(ess->st, ess->sh, PORT_DSP_INDEX, reg);

sys/dev/pci/esm.c

394

wp_wrreg(struct esm_softc *ess, uint16_t reg, uint16_t data)

sys/dev/pci/esm.c

397

bus_space_write_2(ess->st, ess->sh, PORT_DSP_INDEX, reg);

sys/dev/pci/esm.c

402

apu_setindex(struct esm_softc *ess, uint16_t reg)

sys/dev/pci/esm.c

406

wp_wrreg(ess, WPREG_CRAM_PTR, reg);

sys/dev/pci/esm.c

409

if (bus_space_read_2(ess->st, ess->sh, PORT_DSP_DATA) == reg)

sys/dev/pci/esm.c

411

bus_space_write_2(ess->st, ess->sh, PORT_DSP_DATA, reg);

sys/dev/pci/esm.c

418

wp_rdapu(struct esm_softc *ess, int ch, uint16_t reg)

sys/dev/pci/esm.c

422

apu_setindex(ess, ((unsigned)ch << 4) + reg);

sys/dev/pci/esm.c

428

wp_wrapu(struct esm_softc *ess, int ch, uint16_t reg, uint16_t data)

sys/dev/pci/esm.c

434

ess, ch, reg, data));

sys/dev/pci/esm.c

436

apu_setindex(ess, ((unsigned)ch << 4) + reg);

sys/dev/pci/esm.c

493

wc_wrreg(struct esm_softc *ess, uint16_t reg, uint16_t data)

sys/dev/pci/esm.c

496

bus_space_write_2(ess->st, ess->sh, PORT_WAVCACHE_INDEX, reg);

sys/dev/pci/esm.c

834

uint16_t reg;

sys/dev/pci/esm.c

904

for (reg = 0; reg < 15; reg++)

sys/dev/pci/esm.c

905

wp_wrapu(ess, apuch + i, reg, 0);

sys/dev/pci/esm.c

934

for (reg = 0; reg < 15; reg++)

sys/dev/pci/esm.c

935

wp_wrapu(ess, apuch + 2 + i, reg, 0);

sys/dev/pci/eso.c

530

eso_write_ctlreg(struct eso_softc *sc, uint8_t reg, uint8_t val)

sys/dev/pci/eso.c

535

eso_write_cmd(sc, reg);

sys/dev/pci/eso.c

560

eso_read_ctlreg(struct eso_softc *sc, uint8_t reg)

sys/dev/pci/eso.c

564

eso_write_cmd(sc, reg);

sys/dev/pci/eso.c

569

eso_write_mixreg(struct eso_softc *sc, uint8_t reg, uint8_t val)

sys/dev/pci/eso.c

576

bus_space_write_1(sc->sc_sb_iot, sc->sc_sb_ioh, ESO_SB_MIXERADDR, reg);

sys/dev/pci/eso.c

581

eso_read_mixreg(struct eso_softc *sc, uint8_t reg)

sys/dev/pci/eso.c

587

bus_space_write_1(sc->sc_sb_iot, sc->sc_sb_ioh, ESO_SB_MIXERADDR, reg);

sys/dev/pci/fms.c

343

fms_read_codec(void *addr, uint8_t reg, uint16_t *val)

sys/dev/pci/fms.c

360

reg | FM_CODEC_CMD_READ);

sys/dev/pci/fms.c

377

fms_write_codec(void *addr, uint8_t reg, uint16_t val)

sys/dev/pci/fms.c

394

bus_space_write_2(sc->sc_iot, sc->sc_ioh, FM_CODEC_CMD, reg);

sys/dev/pci/gcscaudio.c

409

gcscaudio_write_codec(void *arg, uint8_t reg, uint16_t val)

sys/dev/pci/gcscaudio.c

418

ACC_CODEC_REG2ADDR(reg) |

sys/dev/pci/gcscaudio.c

426

reg, val);

sys/dev/pci/gcscaudio.c

433

gcscaudio_read_codec(void *arg, uint8_t reg, uint16_t *val)

sys/dev/pci/gcscaudio.c

442

ACC_CODEC_REG2ADDR(reg));

sys/dev/pci/gcscaudio.c

451

(ACC_CODEC_ADDR2REG(v) == reg))

sys/dev/pci/gcscaudio.c

464

reg, v & ACC_CODEC_STATUS_STS_DATA_MASK);

sys/dev/pci/gcscaudioreg.h

54

#define ACC_CODEC_REG2ADDR(reg) (((reg) & 0x7f) << 24)

sys/dev/pci/gffb.c

1464

uint32_t reg;

sys/dev/pci/gffb.c

1466

reg = *data8;

sys/dev/pci/gffb.c

1467

reg |= reg >> 1;

sys/dev/pci/gffb.c

1468

gffb_dmanext(sc, reg << 24);

sys/dev/pci/gffb.c

1475

uint32_t reg;

sys/dev/pci/gffb.c

1477

reg = *data16;

sys/dev/pci/gffb.c

1478

reg |= reg >> 1;

sys/dev/pci/gffb.c

1479

gffb_dmanext(sc, reg << 16);

sys/dev/pci/gffb.c

1489

uint32_t reg;

sys/dev/pci/gffb.c

1491

reg = *data8;

sys/dev/pci/gffb.c

1492

gffb_dmanext(sc, reg << 24);

sys/dev/pci/gffb.c

1499

uint32_t reg;

sys/dev/pci/gffb.c

1501

reg = *data16;

sys/dev/pci/gffb.c

1502

gffb_dmanext(sc, reg << 16);

sys/dev/pci/gffb.c

165

gffb_write_crtc(struct gffb_softc *sc, int head, uint8_t reg, uint8_t val)

sys/dev/pci/gffb.c

168

GFFB_WRITE_1(GFFB_PCIO0 + 0x3d4, reg);

sys/dev/pci/gffb.c

171

GFFB_WRITE_1(GFFB_PCIO1 + 0x3d4, reg);

sys/dev/pci/gffb.c

177

gffb_read_crtc(struct gffb_softc *sc, int head, uint8_t reg)

sys/dev/pci/gffb.c

180

GFFB_WRITE_1(GFFB_PCIO0 + 0x3d4, reg);

sys/dev/pci/gffb.c

183

GFFB_WRITE_1(GFFB_PCIO1 + 0x3d4, reg);

sys/dev/pci/gffb.c

220

pcireg_t reg;

sys/dev/pci/gffb.c

236

reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PCI_ID_REG);

sys/dev/pci/gffb.c

237

switch (PCI_PRODUCT(reg)) {

sys/dev/pci/hdaudio_pci.c

129

int err, reg;

sys/dev/pci/hdaudio_pci.c

148

reg = PCI_BAR0;

sys/dev/pci/hdaudio_pci.c

149

maptype = pci_mapreg_type(sc->sc_pc, sc->sc_tag, reg);

sys/dev/pci/hdaudio_pci.c

150

err = pci_mapreg_map(pa, reg, maptype, 0,

sys/dev/pci/hifn7751.c

2996

hifn_write_4(struct hifn_softc *sc, int reggrp, bus_size_t reg, uint32_t val)

sys/dev/pci/hifn7751.c

3005

sc->sc_waw_lastreg == reg - 4) {

sys/dev/pci/hifn7751.c

3009

sc->sc_waw_lastreg = reg;

sys/dev/pci/hifn7751.c

3012

bus_space_write_4(sc->sc_st0, sc->sc_sh0, reg, val);

sys/dev/pci/hifn7751.c

3014

bus_space_write_4(sc->sc_st1, sc->sc_sh1, reg, val);

sys/dev/pci/hifn7751.c

3019

hifn_read_4(struct hifn_softc *sc, int reggrp, bus_size_t reg)

sys/dev/pci/hifn7751.c

3026

return (bus_space_read_4(sc->sc_st0, sc->sc_sh0, reg));

sys/dev/pci/hifn7751.c

3027

return (bus_space_read_4(sc->sc_st1, sc->sc_sh1, reg));

sys/dev/pci/hifn7751.c

761

uint32_t reg;

sys/dev/pci/hifn7751.c

797

for (reg = 0; reg < 1000; reg++) {

sys/dev/pci/hifn7751.c

803

if (reg == 1000)

sys/dev/pci/hifn7751var.h

182

#define WRITE_REG_0(sc,reg,val) hifn_write_4((sc), 0, (reg), (val))

sys/dev/pci/hifn7751var.h

183

#define WRITE_REG_1(sc,reg,val) hifn_write_4((sc), 1, (reg), (val))

sys/dev/pci/hifn7751var.h

184

#define READ_REG_0(sc,reg) hifn_read_4((sc), 0, (reg))

sys/dev/pci/hifn7751var.h

185

#define READ_REG_1(sc,reg) hifn_read_4((sc), 1, (reg))

sys/dev/pci/if_age.c

1168

uint32_t reg;

sys/dev/pci/if_age.c

1172

reg = CSR_READ_4(sc, AGE_MAC_CFG);

sys/dev/pci/if_age.c

1173

reg &= ~MAC_CFG_FULL_DUPLEX;

sys/dev/pci/if_age.c

1174

reg &= ~(MAC_CFG_TX_FC | MAC_CFG_RX_FC);

sys/dev/pci/if_age.c

1175

reg &= ~MAC_CFG_SPEED_MASK;

sys/dev/pci/if_age.c

1181

reg |= MAC_CFG_SPEED_10_100;

sys/dev/pci/if_age.c

1184

reg |= MAC_CFG_SPEED_1000;

sys/dev/pci/if_age.c

1188

reg |= MAC_CFG_FULL_DUPLEX;

sys/dev/pci/if_age.c

1190

reg |= MAC_CFG_TX_FC;

sys/dev/pci/if_age.c

1192

reg |= MAC_CFG_RX_FC;

sys/dev/pci/if_age.c

1195

CSR_WRITE_4(sc, AGE_MAC_CFG, reg);

sys/dev/pci/if_age.c

1608

uint32_t reg;

sys/dev/pci/if_age.c

1615

if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0)

sys/dev/pci/if_age.c

1622

reg);

sys/dev/pci/if_age.c

1636

uint32_t reg, fsize;

sys/dev/pci/if_age.c

1729

reg = CSR_READ_4(sc, AGE_MASTER_CFG);

sys/dev/pci/if_age.c

1730

reg &= ~MASTER_MTIMER_ENB;

sys/dev/pci/if_age.c

1732

reg &= ~MASTER_ITIMER_ENB;

sys/dev/pci/if_age.c

1734

reg |= MASTER_ITIMER_ENB;

sys/dev/pci/if_age.c

1735

CSR_WRITE_4(sc, AGE_MASTER_CFG, reg);

sys/dev/pci/if_age.c

1791

reg = CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN);

sys/dev/pci/if_age.c

1792

rxf_lo = reg / 16;

sys/dev/pci/if_age.c

1795

rxf_hi = (reg * 7) / 8;

sys/dev/pci/if_age.c

1798

reg = CSR_READ_4(sc, AGE_SRAM_RRD_LEN);

sys/dev/pci/if_age.c

1799

rrd_lo = reg / 8;

sys/dev/pci/if_age.c

1800

rrd_hi = (reg * 7) / 8;

sys/dev/pci/if_age.c

1883

reg = CSR_READ_4(sc, AGE_MAC_CFG);

sys/dev/pci/if_age.c

1884

reg |= MAC_CFG_RXCSUM_ENB;

sys/dev/pci/if_age.c

1891

CSR_WRITE_4(sc, AGE_MAC_CFG, reg | MAC_CFG_TX_ENB | MAC_CFG_RX_ENB);

sys/dev/pci/if_age.c

1913

uint32_t reg;

sys/dev/pci/if_age.c

1951

if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0)

sys/dev/pci/if_age.c

1957

device_xname(sc->sc_dev), reg);

sys/dev/pci/if_age.c

2089

uint32_t reg;

sys/dev/pci/if_age.c

2092

reg = CSR_READ_4(sc, AGE_MAC_CFG);

sys/dev/pci/if_age.c

2093

if ((reg & MAC_CFG_TX_ENB) != 0) {

sys/dev/pci/if_age.c

2094

reg &= ~MAC_CFG_TX_ENB;

sys/dev/pci/if_age.c

2095

CSR_WRITE_4(sc, AGE_MAC_CFG, reg);

sys/dev/pci/if_age.c

2098

reg = CSR_READ_4(sc, AGE_DMA_CFG);

sys/dev/pci/if_age.c

2099

if ((reg & DMA_CFG_RD_ENB) != 0) {

sys/dev/pci/if_age.c

2100

reg &= ~DMA_CFG_RD_ENB;

sys/dev/pci/if_age.c

2101

CSR_WRITE_4(sc, AGE_DMA_CFG, reg);

sys/dev/pci/if_age.c

2116

uint32_t reg;

sys/dev/pci/if_age.c

2119

reg = CSR_READ_4(sc, AGE_MAC_CFG);

sys/dev/pci/if_age.c

2120

if ((reg & MAC_CFG_RX_ENB) != 0) {

sys/dev/pci/if_age.c

2121

reg &= ~MAC_CFG_RX_ENB;

sys/dev/pci/if_age.c

2122

CSR_WRITE_4(sc, AGE_MAC_CFG, reg);

sys/dev/pci/if_age.c

2125

reg = CSR_READ_4(sc, AGE_DMA_CFG);

sys/dev/pci/if_age.c

2126

if ((reg & DMA_CFG_WR_ENB) != 0) {

sys/dev/pci/if_age.c

2127

reg &= ~DMA_CFG_WR_ENB;

sys/dev/pci/if_age.c

2128

CSR_WRITE_4(sc, AGE_DMA_CFG, reg);

sys/dev/pci/if_age.c

2276

uint32_t reg;

sys/dev/pci/if_age.c

2278

reg = CSR_READ_4(sc, AGE_MAC_CFG);

sys/dev/pci/if_age.c

2279

reg &= ~MAC_CFG_VLAN_TAG_STRIP;

sys/dev/pci/if_age.c

2281

reg |= MAC_CFG_VLAN_TAG_STRIP;

sys/dev/pci/if_age.c

2282

CSR_WRITE_4(sc, AGE_MAC_CFG, reg);

sys/dev/pci/if_age.c

349

age_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val)

sys/dev/pci/if_age.c

359

MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));

sys/dev/pci/if_age.c

369

device_xname(sc->sc_dev), phy, reg);

sys/dev/pci/if_age.c

381

age_miibus_writereg(device_t dev, int phy, int reg, uint16_t val)

sys/dev/pci/if_age.c

392

MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));

sys/dev/pci/if_age.c

403

device_xname(sc->sc_dev), phy, reg);

sys/dev/pci/if_age.c

441

uint32_t reg;

sys/dev/pci/if_age.c

444

reg = CSR_READ_4(sc, AGE_MAC_CFG);

sys/dev/pci/if_age.c

448

reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB;

sys/dev/pci/if_age.c

449

CSR_WRITE_4(sc, AGE_MAC_CFG, reg);

sys/dev/pci/if_age.c

564

uint32_t ea[2], reg;

sys/dev/pci/if_age.c

567

reg = CSR_READ_4(sc, AGE_SPI_CTRL);

sys/dev/pci/if_age.c

568

if ((reg & SPI_VPD_ENB) != 0) {

sys/dev/pci/if_age.c

570

reg &= ~SPI_VPD_ENB;

sys/dev/pci/if_age.c

571

CSR_WRITE_4(sc, AGE_SPI_CTRL, reg);

sys/dev/pci/if_age.c

584

reg = CSR_READ_4(sc, AGE_TWSI_CTRL);

sys/dev/pci/if_age.c

585

if ((reg & TWSI_CTRL_SW_LD_START) == 0)

sys/dev/pci/if_age.c

611

uint16_t reg, pn;

sys/dev/pci/if_age.c

640

ATPHY_CDTC, &reg);

sys/dev/pci/if_age.c

641

if ((reg & PHY_CDTC_ENB) == 0)

sys/dev/pci/if_age.c

646

ATPHY_CDTS, &reg);

sys/dev/pci/if_age.c

647

if ((reg & PHY_CDTS_STAT_MASK) != PHY_CDTS_STAT_OPEN) {

sys/dev/pci/if_age.c

662

ATPHY_DBG_DATA, &reg);

sys/dev/pci/if_age.c

664

ATPHY_DBG_DATA, reg | 0x03);

sys/dev/pci/if_agereg.h

854

#define CSR_WRITE_4(sc, reg, val) \

sys/dev/pci/if_agereg.h

855

bus_space_write_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val))

sys/dev/pci/if_agereg.h

856

#define CSR_WRITE_2(sc, reg, val) \

sys/dev/pci/if_agereg.h

857

bus_space_write_2((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val))

sys/dev/pci/if_agereg.h

858

#define CSR_READ_2(sc, reg) \

sys/dev/pci/if_agereg.h

859

bus_space_read_2((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg))

sys/dev/pci/if_agereg.h

860

#define CSR_READ_4(sc, reg) \

sys/dev/pci/if_agereg.h

861

bus_space_read_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg))

sys/dev/pci/if_alc.c

186

alc_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val)

sys/dev/pci/if_alc.c

192

v = alc_mii_readreg_816x(sc, phy, reg, val);

sys/dev/pci/if_alc.c

194

v = alc_mii_readreg_813x(sc, phy, reg, val);

sys/dev/pci/if_alc.c

199

alc_mii_readreg_813x(struct alc_softc *sc, int phy, int reg, uint16_t *val)

sys/dev/pci/if_alc.c

213

if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0 && reg == MII_EXTSR) {

sys/dev/pci/if_alc.c

2140

uint32_t reg;

sys/dev/pci/if_alc.c

2143

reg = CSR_READ_4(sc, ALC_MAC_CFG);

sys/dev/pci/if_alc.c

2144

reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC |

sys/dev/pci/if_alc.c

2149

reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW;

sys/dev/pci/if_alc.c

2154

reg |= MAC_CFG_SPEED_10_100;

sys/dev/pci/if_alc.c

2157

reg |= MAC_CFG_SPEED_1000;

sys/dev/pci/if_alc.c

2161

reg |= MAC_CFG_FULL_DUPLEX;

sys/dev/pci/if_alc.c

2163

reg |= MAC_CFG_TX_FC;

sys/dev/pci/if_alc.c

2165

reg |= MAC_CFG_RX_FC;

sys/dev/pci/if_alc.c

2167

CSR_WRITE_4(sc, ALC_MAC_CFG, reg);

sys/dev/pci/if_alc.c

2174

uint32_t *reg;

sys/dev/pci/if_alc.c

2188

for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered;

sys/dev/pci/if_alc.c

2189

reg++) {

sys/dev/pci/if_alc.c

219

MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));

sys/dev/pci/if_alc.c

2194

for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes;

sys/dev/pci/if_alc.c

2195

reg++) {

sys/dev/pci/if_alc.c

2208

uint32_t *reg;

sys/dev/pci/if_alc.c

2222

for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered;

sys/dev/pci/if_alc.c

2223

reg++) {

sys/dev/pci/if_alc.c

2224

*reg = CSR_READ_4(sc, ALC_RX_MIB_BASE + i);

sys/dev/pci/if_alc.c

2228

for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes;

sys/dev/pci/if_alc.c

2229

reg++) {

sys/dev/pci/if_alc.c

2230

*reg = CSR_READ_4(sc, ALC_TX_MIB_BASE + i);

sys/dev/pci/if_alc.c

229

device_xname(sc->sc_dev), phy, reg);

sys/dev/pci/if_alc.c

238

alc_mii_readreg_816x(struct alc_softc *sc, int phy, int reg, uint16_t *val)

sys/dev/pci/if_alc.c

251

MDIO_SUP_PREAMBLE | clk | MDIO_REG_ADDR(reg));

sys/dev/pci/if_alc.c

261

device_xname(sc->sc_dev), phy, reg);

sys/dev/pci/if_alc.c

2671

uint32_t reg;

sys/dev/pci/if_alc.c

2673

reg = CSR_READ_4(sc, ALC_MISC3);

sys/dev/pci/if_alc.c

2674

reg &= ~MISC3_25M_BY_SW;

sys/dev/pci/if_alc.c

2675

reg |= MISC3_25M_NOTO_INTNL;

sys/dev/pci/if_alc.c

2676

CSR_WRITE_4(sc, ALC_MISC3, reg);

sys/dev/pci/if_alc.c

2678

reg = CSR_READ_4(sc, ALC_MISC);

sys/dev/pci/if_alc.c

2684

reg &= ~MISC_PSW_OCP_MASK;

sys/dev/pci/if_alc.c

2685

reg |= (MISC_PSW_OCP_DEFAULT << MISC_PSW_OCP_SHIFT);

sys/dev/pci/if_alc.c

2686

reg &= ~MISC_INTNLOSC_OPEN;

sys/dev/pci/if_alc.c

2687

CSR_WRITE_4(sc, ALC_MISC, reg);

sys/dev/pci/if_alc.c

2688

CSR_WRITE_4(sc, ALC_MISC, reg | MISC_INTNLOSC_OPEN);

sys/dev/pci/if_alc.c

2689

reg = CSR_READ_4(sc, ALC_MISC2);

sys/dev/pci/if_alc.c

2690

reg &= ~MISC2_CALB_START;

sys/dev/pci/if_alc.c

2691

CSR_WRITE_4(sc, ALC_MISC2, reg);

sys/dev/pci/if_alc.c

2692

CSR_WRITE_4(sc, ALC_MISC2, reg | MISC2_CALB_START);

sys/dev/pci/if_alc.c

2695

reg &= ~MISC_INTNLOSC_OPEN;

sys/dev/pci/if_alc.c

2698

reg &= ~MISC_ISO_ENB;

sys/dev/pci/if_alc.c

2699

CSR_WRITE_4(sc, ALC_MISC, reg | MISC_INTNLOSC_OPEN);

sys/dev/pci/if_alc.c

270

alc_miibus_writereg(device_t dev, int phy, int reg, uint16_t val)

sys/dev/pci/if_alc.c

2700

CSR_WRITE_4(sc, ALC_MISC, reg);

sys/dev/pci/if_alc.c

2709

uint32_t pmcfg, reg;

sys/dev/pci/if_alc.c

2728

reg = CSR_READ_4(sc, ALC_MASTER_CFG);

sys/dev/pci/if_alc.c

2729

reg |= MASTER_OOB_DIS_OFF | MASTER_RESET;

sys/dev/pci/if_alc.c

2730

CSR_WRITE_4(sc, ALC_MASTER_CFG, reg);

sys/dev/pci/if_alc.c

2750

reg = CSR_READ_4(sc, ALC_IDLE_STATUS);

sys/dev/pci/if_alc.c

2751

if ((reg & (IDLE_STATUS_RXMAC | IDLE_STATUS_TXMAC |

sys/dev/pci/if_alc.c

2758

device_xname(sc->sc_dev), reg);

sys/dev/pci/if_alc.c

276

rv = alc_mii_writereg_816x(sc, phy, reg, val);

sys/dev/pci/if_alc.c

2763

reg = CSR_READ_4(sc, ALC_MASTER_CFG);

sys/dev/pci/if_alc.c

2764

reg |= MASTER_CLK_SEL_DIS;

sys/dev/pci/if_alc.c

2765

CSR_WRITE_4(sc, ALC_MASTER_CFG, reg);

sys/dev/pci/if_alc.c

2773

reg = CSR_READ_4(sc, ALC_MISC3);

sys/dev/pci/if_alc.c

2774

reg &= ~MISC3_25M_BY_SW;

sys/dev/pci/if_alc.c

2775

reg |= MISC3_25M_NOTO_INTNL;

sys/dev/pci/if_alc.c

2776

CSR_WRITE_4(sc, ALC_MISC3, reg);

sys/dev/pci/if_alc.c

2777

reg = CSR_READ_4(sc, ALC_MISC);

sys/dev/pci/if_alc.c

2778

reg &= ~MISC_INTNLOSC_OPEN;

sys/dev/pci/if_alc.c

278

rv = alc_mii_writereg_813x(sc, phy, reg, val);

sys/dev/pci/if_alc.c

2780

reg &= ~MISC_ISO_ENB;

sys/dev/pci/if_alc.c

2781

CSR_WRITE_4(sc, ALC_MISC, reg);

sys/dev/pci/if_alc.c

2806

uint32_t reg, rxf_hi, rxf_lo;

sys/dev/pci/if_alc.c

284

alc_mii_writereg_813x(struct alc_softc *sc, int phy, int reg, uint16_t val)

sys/dev/pci/if_alc.c

291

MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));

sys/dev/pci/if_alc.c

2925

reg = ALC_USECS(sc->alc_int_rx_mod) << IM_TIMER_RX_SHIFT;

sys/dev/pci/if_alc.c

2927

reg |= ALC_USECS(sc->alc_int_tx_mod) << IM_TIMER_TX_SHIFT;

sys/dev/pci/if_alc.c

2928

CSR_WRITE_4(sc, ALC_IM_TIMER, reg);

sys/dev/pci/if_alc.c

2933

reg = CSR_READ_4(sc, ALC_MASTER_CFG);

sys/dev/pci/if_alc.c

2934

reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB);

sys/dev/pci/if_alc.c

2935

reg |= MASTER_SA_TIMER_ENB;

sys/dev/pci/if_alc.c

2937

reg |= MASTER_IM_RX_TIMER_ENB;

sys/dev/pci/if_alc.c

2940

reg |= MASTER_IM_TX_TIMER_ENB;

sys/dev/pci/if_alc.c

2941

CSR_WRITE_4(sc, ALC_MASTER_CFG, reg);

sys/dev/pci/if_alc.c

301

device_xname(sc->sc_dev), phy, reg);

sys/dev/pci/if_alc.c

3016

reg = (sc->alc_ident->max_framelen >> TSO_OFFLOAD_THRESH_UNIT_SHIFT) &

sys/dev/pci/if_alc.c

3019

reg |= TSO_OFFLOAD_ERRLGPKT_DROP_ENB;

sys/dev/pci/if_alc.c

3020

CSR_WRITE_4(sc, ALC_TSO_OFFLOAD_THRESH, reg);

sys/dev/pci/if_alc.c

3022

reg = (alc_dma_burst[sc->alc_dma_rd_burst] <<

sys/dev/pci/if_alc.c

3026

reg >>= 1;

sys/dev/pci/if_alc.c

3027

reg |= (TXQ_CFG_TD_BURST_DEFAULT << TXQ_CFG_TD_BURST_SHIFT) &

sys/dev/pci/if_alc.c

3029

reg |= TXQ_CFG_IP_OPTION_ENB | TXQ_CFG_8023_ENB;

sys/dev/pci/if_alc.c

3030

CSR_WRITE_4(sc, ALC_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE);

sys/dev/pci/if_alc.c

3032

reg = (TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q1_BURST_SHIFT |

sys/dev/pci/if_alc.c

3036

CSR_WRITE_4(sc, ALC_HQTD_CFG, reg);

sys/dev/pci/if_alc.c

3037

reg = WRR_PRI_RESTRICT_NONE;

sys/dev/pci/if_alc.c

3038

reg |= (WRR_PRI_DEFAULT << WRR_PRI0_SHIFT |

sys/dev/pci/if_alc.c

3042

CSR_WRITE_4(sc, ALC_WRR, reg);

sys/dev/pci/if_alc.c

3058

reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN);

sys/dev/pci/if_alc.c

3059

reg &= SRAM_RX_FIFO_LEN_MASK;

sys/dev/pci/if_alc.c

3060

reg *= 8;

sys/dev/pci/if_alc.c

3061

if (reg > 8 * 1024)

sys/dev/pci/if_alc.c

3062

reg -= RX_FIFO_PAUSE_816X_RSVD;

sys/dev/pci/if_alc.c

3064

reg -= RX_BUF_SIZE_MAX;

sys/dev/pci/if_alc.c

3065

reg /= 8;

sys/dev/pci/if_alc.c

3067

((reg << RX_FIFO_PAUSE_THRESH_LO_SHIFT) &

sys/dev/pci/if_alc.c

3074

reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN);

sys/dev/pci/if_alc.c

3075

rxf_hi = (reg * 8) / 10;

sys/dev/pci/if_alc.c

3076

rxf_lo = (reg * 3) / 10;

sys/dev/pci/if_alc.c

309

alc_mii_writereg_816x(struct alc_softc *sc, int phy, int reg, uint16_t val)

sys/dev/pci/if_alc.c

3091

reg = (RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) &

sys/dev/pci/if_alc.c

3093

reg |= RXQ_CFG_RSS_MODE_DIS;

sys/dev/pci/if_alc.c

3095

reg |= (RXQ_CFG_816X_IDT_TBL_SIZE_DEFAULT <<

sys/dev/pci/if_alc.c

3099

reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M;

sys/dev/pci/if_alc.c

3103

reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M;

sys/dev/pci/if_alc.c

3105

CSR_WRITE_4(sc, ALC_RXQ_CFG, reg);

sys/dev/pci/if_alc.c

3108

reg = DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI;

sys/dev/pci/if_alc.c

3109

reg |= sc->alc_rcb;

sys/dev/pci/if_alc.c

3111

reg |= DMA_CFG_CMB_ENB;

sys/dev/pci/if_alc.c

3113

reg |= DMA_CFG_SMB_ENB;

sys/dev/pci/if_alc.c

3115

reg |= DMA_CFG_SMB_DIS;

sys/dev/pci/if_alc.c

3116

reg |= (sc->alc_dma_rd_burst & DMA_CFG_RD_BURST_MASK) <<

sys/dev/pci/if_alc.c

3118

reg |= (sc->alc_dma_wr_burst & DMA_CFG_WR_BURST_MASK) <<

sys/dev/pci/if_alc.c

3120

reg |= (DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) &

sys/dev/pci/if_alc.c

3122

reg |= (DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) &

sys/dev/pci/if_alc.c

3128

reg |= DMA_CFG_RD_CHNL_SEL_2;

sys/dev/pci/if_alc.c

3133

reg |= DMA_CFG_RD_CHNL_SEL_4;

sys/dev/pci/if_alc.c

3137

CSR_WRITE_4(sc, ALC_DMA_CFG, reg);

sys/dev/pci/if_alc.c

3152

reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX |

sys/dev/pci/if_alc.c

3159

reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW;

sys/dev/pci/if_alc.c

3161

reg |= MAC_CFG_SPEED_10_100;

sys/dev/pci/if_alc.c

3163

reg |= MAC_CFG_SPEED_1000;

sys/dev/pci/if_alc.c

3164

CSR_WRITE_4(sc, ALC_MAC_CFG, reg);

sys/dev/pci/if_alc.c

319

((val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT) | MDIO_REG_ADDR(reg) |

sys/dev/pci/if_alc.c

3194

uint32_t reg;

sys/dev/pci/if_alc.c

3216

reg = CSR_READ_4(sc, ALC_DMA_CFG);

sys/dev/pci/if_alc.c

3217

reg &= ~(DMA_CFG_CMB_ENB | DMA_CFG_SMB_ENB);

sys/dev/pci/if_alc.c

3218

reg |= DMA_CFG_SMB_DIS;

sys/dev/pci/if_alc.c

3219

CSR_WRITE_4(sc, ALC_DMA_CFG, reg);

sys/dev/pci/if_alc.c

3262

uint32_t reg;

sys/dev/pci/if_alc.c

3267

reg = CSR_READ_4(sc, ALC_MAC_CFG);

sys/dev/pci/if_alc.c

3268

if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) {

sys/dev/pci/if_alc.c

3269

reg &= ~(MAC_CFG_TX_ENB | MAC_CFG_RX_ENB);

sys/dev/pci/if_alc.c

3270

CSR_WRITE_4(sc, ALC_MAC_CFG, reg);

sys/dev/pci/if_alc.c

3273

reg = CSR_READ_4(sc, ALC_IDLE_STATUS);

sys/dev/pci/if_alc.c

3274

if ((reg & (IDLE_STATUS_RXMAC | IDLE_STATUS_TXMAC)) == 0)

sys/dev/pci/if_alc.c

3280

device_xname(sc->sc_dev), reg);

sys/dev/pci/if_alc.c

330

device_xname(sc->sc_dev), phy, reg);

sys/dev/pci/if_alc.c

3312

uint32_t reg;

sys/dev/pci/if_alc.c

3316

reg = CSR_READ_4(sc, ALC_RXQ_CFG);

sys/dev/pci/if_alc.c

3318

if ((reg & RXQ_CFG_ENB) != 0) {

sys/dev/pci/if_alc.c

3319

reg &= ~RXQ_CFG_ENB;

sys/dev/pci/if_alc.c

3320

CSR_WRITE_4(sc, ALC_RXQ_CFG, reg);

sys/dev/pci/if_alc.c

3323

if ((reg & RXQ_CFG_QUEUE0_ENB) != 0) {

sys/dev/pci/if_alc.c

3324

reg &= ~RXQ_CFG_QUEUE0_ENB;

sys/dev/pci/if_alc.c

3325

CSR_WRITE_4(sc, ALC_RXQ_CFG, reg);

sys/dev/pci/if_alc.c

3329

reg = CSR_READ_4(sc, ALC_TXQ_CFG);

sys/dev/pci/if_alc.c

3330

if ((reg & TXQ_CFG_ENB) != 0) {

sys/dev/pci/if_alc.c

3331

reg &= ~TXQ_CFG_ENB;

sys/dev/pci/if_alc.c

3332

CSR_WRITE_4(sc, ALC_TXQ_CFG, reg);

sys/dev/pci/if_alc.c

3336

reg = CSR_READ_4(sc, ALC_IDLE_STATUS);

sys/dev/pci/if_alc.c

3337

if ((reg & (IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0)

sys/dev/pci/if_alc.c

3343

device_xname(sc->sc_dev), reg);

sys/dev/pci/if_alc.c

342

uint32_t reg;

sys/dev/pci/if_alc.c

3441

uint32_t reg;

sys/dev/pci/if_alc.c

3443

reg = CSR_READ_4(sc, ALC_MAC_CFG);

sys/dev/pci/if_alc.c

3445

reg |= MAC_CFG_VLAN_TAG_STRIP;

sys/dev/pci/if_alc.c

3447

reg &= ~MAC_CFG_VLAN_TAG_STRIP;

sys/dev/pci/if_alc.c

3448

CSR_WRITE_4(sc, ALC_MAC_CFG, reg);

sys/dev/pci/if_alc.c

371

reg = CSR_READ_4(sc, ALC_MAC_CFG);

sys/dev/pci/if_alc.c

372

reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB;

sys/dev/pci/if_alc.c

373

CSR_WRITE_4(sc, ALC_MAC_CFG, reg);

sys/dev/pci/if_alc.c

380

alc_miidbg_readreg(struct alc_softc *sc, int reg, uint16_t *val)

sys/dev/pci/if_alc.c

385

reg);

sys/dev/pci/if_alc.c

394

alc_miidbg_writereg(struct alc_softc *sc, int reg, uint16_t val)

sys/dev/pci/if_alc.c

399

reg);

sys/dev/pci/if_alc.c

410

alc_miiext_readreg(struct alc_softc *sc, int devaddr, int reg, uint16_t *val)

sys/dev/pci/if_alc.c

415

CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) |

sys/dev/pci/if_alc.c

432

device_xname(sc->sc_dev), reg);

sys/dev/pci/if_alc.c

441

alc_miiext_writereg(struct alc_softc *sc, int devaddr, int reg, uint16_t val)

sys/dev/pci/if_alc.c

446

CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) |

sys/dev/pci/if_alc.c

464

device_xname(sc->sc_dev), reg);

sys/dev/pci/if_alc.c

715

uint32_t reg;

sys/dev/pci/if_alc.c

721

reg = CSR_READ_4(sc, ALC_SLD);

sys/dev/pci/if_alc.c

722

if ((reg & (SLD_PROGRESS | SLD_START)) == 0)

sys/dev/pci/if_alc.c

727

CSR_WRITE_4(sc, ALC_SLD, reg | SLD_START);

sys/dev/pci/if_alc.c

730

reg = CSR_READ_4(sc, ALC_SLD);

sys/dev/pci/if_alc.c

731

if ((reg & SLD_START) == 0)

sys/dev/pci/if_alc.c

743

reg = CSR_READ_4(sc, ALC_EEPROM_LD);

sys/dev/pci/if_alc.c

744

if ((reg & (EEPROM_LD_EEPROM_EXIST |

sys/dev/pci/if_alc.c

747

reg = CSR_READ_4(sc, ALC_EEPROM_LD);

sys/dev/pci/if_alc.c

748

if ((reg & (EEPROM_LD_PROGRESS |

sys/dev/pci/if_alc.c

754

CSR_WRITE_4(sc, ALC_EEPROM_LD, reg |

sys/dev/pci/if_alc.c

758

reg = CSR_READ_4(sc, ALC_EEPROM_LD);

sys/dev/pci/if_alc.c

759

if ((reg & EEPROM_LD_START) == 0)

sys/dev/pci/if_alcreg.h

1491

#define CSR_WRITE_4(_sc, reg, val) \

sys/dev/pci/if_alcreg.h

1492

bus_space_write_4((_sc)->sc_mem_bt, (_sc)->sc_mem_bh, (reg), (val))

sys/dev/pci/if_alcreg.h

1493

#define CSR_WRITE_2(_sc, reg, val) \

sys/dev/pci/if_alcreg.h

1494

bus_space_write_2((_sc)->sc_mem_bt, (_sc)->sc_mem_bh, (reg), (val))

sys/dev/pci/if_alcreg.h

1495

#define CSR_WRITE_1(_sc, reg, val) \

sys/dev/pci/if_alcreg.h

1496

bus_space_write_1((_sc)->sc_mem_bt, (_sc)->sc_mem_bh, (reg), (val))

sys/dev/pci/if_alcreg.h

1497

#define CSR_READ_2(_sc, reg) \

sys/dev/pci/if_alcreg.h

1498

bus_space_read_2((_sc)->sc_mem_bt, (_sc)->sc_mem_bh, (reg))

sys/dev/pci/if_alcreg.h

1499

#define CSR_READ_4(_sc, reg) \

sys/dev/pci/if_alcreg.h

1500

bus_space_read_4((_sc)->sc_mem_bt, (_sc)->sc_mem_bh, (reg))

sys/dev/pci/if_ale.c

1131

uint32_t reg;

sys/dev/pci/if_ale.c

1134

reg = CSR_READ_4(sc, ALE_MAC_CFG);

sys/dev/pci/if_ale.c

1135

reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC |

sys/dev/pci/if_ale.c

1142

reg |= MAC_CFG_SPEED_10_100;

sys/dev/pci/if_ale.c

1145

reg |= MAC_CFG_SPEED_1000;

sys/dev/pci/if_ale.c

1149

reg |= MAC_CFG_FULL_DUPLEX;

sys/dev/pci/if_ale.c

1151

reg |= MAC_CFG_TX_FC;

sys/dev/pci/if_ale.c

1153

reg |= MAC_CFG_RX_FC;

sys/dev/pci/if_ale.c

1155

CSR_WRITE_4(sc, ALE_MAC_CFG, reg);

sys/dev/pci/if_ale.c

1162

uint32_t *reg;

sys/dev/pci/if_ale.c

1165

for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) {

sys/dev/pci/if_ale.c

1170

for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) {

sys/dev/pci/if_ale.c

1182

uint32_t *reg;

sys/dev/pci/if_ale.c

1189

for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) {

sys/dev/pci/if_ale.c

1190

*reg = CSR_READ_4(sc, ALE_RX_MIB_BASE + i);

sys/dev/pci/if_ale.c

1194

for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) {

sys/dev/pci/if_ale.c

1195

*reg = CSR_READ_4(sc, ALE_TX_MIB_BASE + i);

sys/dev/pci/if_ale.c

130

ale_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val)

sys/dev/pci/if_ale.c

140

switch (reg) {

sys/dev/pci/if_ale.c

152

MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));

sys/dev/pci/if_ale.c

1576

uint32_t reg;

sys/dev/pci/if_ale.c

1592

if ((reg = CSR_READ_4(sc, ALE_IDLE_STATUS)) == 0)

sys/dev/pci/if_ale.c

1599

reg);

sys/dev/pci/if_ale.c

1609

uint32_t reg, rxf_hi, rxf_lo;

sys/dev/pci/if_ale.c

162

device_xname(sc->sc_dev), phy, reg);

sys/dev/pci/if_ale.c

1691

reg = ALE_USECS(sc->ale_int_rx_mod) << IM_TIMER_RX_SHIFT;

sys/dev/pci/if_ale.c

1692

reg |= ALE_USECS(sc->ale_int_tx_mod) << IM_TIMER_TX_SHIFT;

sys/dev/pci/if_ale.c

1693

CSR_WRITE_4(sc, ALE_IM_TIMER, reg);

sys/dev/pci/if_ale.c

1694

reg = CSR_READ_4(sc, ALE_MASTER_CFG);

sys/dev/pci/if_ale.c

1695

reg &= ~(MASTER_CHIP_REV_MASK | MASTER_CHIP_ID_MASK);

sys/dev/pci/if_ale.c

1696

reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB);

sys/dev/pci/if_ale.c

1698

reg |= MASTER_IM_RX_TIMER_ENB;

sys/dev/pci/if_ale.c

1700

reg |= MASTER_IM_TX_TIMER_ENB;

sys/dev/pci/if_ale.c

1701

CSR_WRITE_4(sc, ALE_MASTER_CFG, reg);

sys/dev/pci/if_ale.c

171

ale_miibus_writereg(device_t dev, int phy, int reg, uint16_t val)

sys/dev/pci/if_ale.c

1733

reg = sc->ale_max_frame_size;

sys/dev/pci/if_ale.c

1735

reg = (sc->ale_max_frame_size * 2) / 3;

sys/dev/pci/if_ale.c

1737

reg = sc->ale_max_frame_size / 2;

sys/dev/pci/if_ale.c

1739

roundup(reg, TX_JUMBO_THRESH_UNIT) >>

sys/dev/pci/if_ale.c

1744

reg = (128 << (sc->ale_dma_rd_burst >> DMA_CFG_RD_BURST_SHIFT))

sys/dev/pci/if_ale.c

1746

reg |= (TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) &

sys/dev/pci/if_ale.c

1748

CSR_WRITE_4(sc, ALE_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE | TXQ_CFG_ENB);

sys/dev/pci/if_ale.c

1752

reg = roundup(sc->ale_max_frame_size, RX_JUMBO_THRESH_UNIT);

sys/dev/pci/if_ale.c

1754

(((reg >> RX_JUMBO_THRESH_UNIT_SHIFT) <<

sys/dev/pci/if_ale.c

1758

reg = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN);

sys/dev/pci/if_ale.c

1759

rxf_hi = (reg * 7) / 10;

sys/dev/pci/if_ale.c

1760

rxf_lo = (reg * 3)/ 10;

sys/dev/pci/if_ale.c

1777

reg = 0;

sys/dev/pci/if_ale.c

1779

reg |= DMA_CFG_TXCMB_ENB;

sys/dev/pci/if_ale.c

1782

sc->ale_dma_rd_burst | reg |

sys/dev/pci/if_ale.c

181

switch (reg) {

sys/dev/pci/if_ale.c

1811

reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX |

sys/dev/pci/if_ale.c

1815

reg |= MAC_CFG_SPEED_10_100;

sys/dev/pci/if_ale.c

1817

reg |= MAC_CFG_SPEED_1000;

sys/dev/pci/if_ale.c

1818

CSR_WRITE_4(sc, ALE_MAC_CFG, reg);

sys/dev/pci/if_ale.c

1848

uint32_t reg;

sys/dev/pci/if_ale.c

1870

reg = CSR_READ_4(sc, ALE_TXQ_CFG);

sys/dev/pci/if_ale.c

1871

reg &= ~TXQ_CFG_ENB;

sys/dev/pci/if_ale.c

1872

CSR_WRITE_4(sc, ALE_TXQ_CFG, reg);

sys/dev/pci/if_ale.c

1873

reg = CSR_READ_4(sc, ALE_RXQ_CFG);

sys/dev/pci/if_ale.c

1874

reg &= ~RXQ_CFG_ENB;

sys/dev/pci/if_ale.c

1875

CSR_WRITE_4(sc, ALE_RXQ_CFG, reg);

sys/dev/pci/if_ale.c

1876

reg = CSR_READ_4(sc, ALE_DMA_CFG);

sys/dev/pci/if_ale.c

1877

reg &= ~(DMA_CFG_TXCMB_ENB | DMA_CFG_RXCMB_ENB);

sys/dev/pci/if_ale.c

1878

CSR_WRITE_4(sc, ALE_DMA_CFG, reg);

sys/dev/pci/if_ale.c

1903

uint32_t reg;

sys/dev/pci/if_ale.c

1906

reg = CSR_READ_4(sc, ALE_MAC_CFG);

sys/dev/pci/if_ale.c

1907

if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) {

sys/dev/pci/if_ale.c

1908

reg &= ~(MAC_CFG_TX_ENB | MAC_CFG_RX_ENB);

sys/dev/pci/if_ale.c

1909

CSR_WRITE_4(sc, ALE_MAC_CFG, reg);

sys/dev/pci/if_ale.c

1913

reg = CSR_READ_4(sc, ALE_IDLE_STATUS);

sys/dev/pci/if_ale.c

1914

if (reg == 0)

sys/dev/pci/if_ale.c

1920

device_xname(sc->sc_dev), reg);

sys/dev/pci/if_ale.c

193

MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));

sys/dev/pci/if_ale.c

1971

uint32_t reg;

sys/dev/pci/if_ale.c

1973

reg = CSR_READ_4(sc, ALE_MAC_CFG);

sys/dev/pci/if_ale.c

1974

reg &= ~MAC_CFG_VLAN_TAG_STRIP;

sys/dev/pci/if_ale.c

1976

reg |= MAC_CFG_VLAN_TAG_STRIP;

sys/dev/pci/if_ale.c

1977

CSR_WRITE_4(sc, ALE_MAC_CFG, reg);

sys/dev/pci/if_ale.c

203

device_xname(sc->sc_dev), phy, reg);

sys/dev/pci/if_ale.c

215

uint32_t reg;

sys/dev/pci/if_ale.c

246

reg = CSR_READ_4(sc, ALE_MAC_CFG);

sys/dev/pci/if_ale.c

247

reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB;

sys/dev/pci/if_ale.c

248

CSR_WRITE_4(sc, ALE_MAC_CFG, reg);

sys/dev/pci/if_ale.c

293

uint32_t ea[2], reg;

sys/dev/pci/if_ale.c

296

reg = CSR_READ_4(sc, ALE_SPI_CTRL);

sys/dev/pci/if_ale.c

297

if ((reg & SPI_VPD_ENB) != 0) {

sys/dev/pci/if_ale.c

298

reg &= ~SPI_VPD_ENB;

sys/dev/pci/if_ale.c

299

CSR_WRITE_4(sc, ALE_SPI_CTRL, reg);

sys/dev/pci/if_ale.c

312

reg = CSR_READ_4(sc, ALE_TWSI_CTRL);

sys/dev/pci/if_ale.c

313

if ((reg & TWSI_CTRL_SW_LD_START) == 0)

sys/dev/pci/if_alereg.h

951

#define CSR_WRITE_4(_sc, reg, val) \

sys/dev/pci/if_alereg.h

952

bus_space_write_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val))

sys/dev/pci/if_alereg.h

953

#define CSR_WRITE_2(_sc, reg, val) \

sys/dev/pci/if_alereg.h

954

bus_space_write_2((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val))

sys/dev/pci/if_alereg.h

955

#define CSR_WRITE_1(_sc, reg, val) \

sys/dev/pci/if_alereg.h

956

bus_space_write_1((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val))

sys/dev/pci/if_alereg.h

957

#define CSR_READ_2(_sc, reg) \

sys/dev/pci/if_alereg.h

958

bus_space_read_2((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg))

sys/dev/pci/if_alereg.h

959

#define CSR_READ_4(_sc, reg) \

sys/dev/pci/if_alereg.h

960

bus_space_read_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg))

sys/dev/pci/if_aq.c

1002

AQ_WRITE_REG((sc), (reg), _v); \

sys/dev/pci/if_aq.c

3320

uint32_t tid0, tid1, reg, *data, size;

sys/dev/pci/if_aq.c

3331

for (reg = reg0, data = data0, size = size0;

sys/dev/pci/if_aq.c

3332

size >= 4; reg += 4, data++, size -= 4) {

sys/dev/pci/if_aq.c

3333

*data = AQ_READ_REG(sc, reg);

sys/dev/pci/if_aq.c

973

#define AQ_WRITE_REG(sc, reg, val) \

sys/dev/pci/if_aq.c

974

bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))

sys/dev/pci/if_aq.c

976

#define AQ_READ_REG(sc, reg) \

sys/dev/pci/if_aq.c

977

bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg))

sys/dev/pci/if_aq.c

979

#define AQ_READ_REGS(sc, reg, p, cnt) \

sys/dev/pci/if_aq.c

980

bus_space_read_region_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (p), (cnt))

sys/dev/pci/if_aq.c

982

#define AQ_READ64_REG(sc, reg) \

sys/dev/pci/if_aq.c

983

((uint64_t)AQ_READ_REG(sc, reg) | \

sys/dev/pci/if_aq.c

984

(((uint64_t)AQ_READ_REG(sc, (reg) + 4)) << 32))

sys/dev/pci/if_aq.c

986

#define AQ_WRITE64_REG(sc, reg, val) \

sys/dev/pci/if_aq.c

988

AQ_WRITE_REG(sc, reg, (uint32_t)val); \

sys/dev/pci/if_aq.c

989

AQ_WRITE_REG(sc, reg + 4, (uint32_t)(val >> 32)); \

sys/dev/pci/if_aq.c

992

#define AQ_READ_REG_BIT(sc, reg, mask) \

sys/dev/pci/if_aq.c

993

__SHIFTOUT(AQ_READ_REG(sc, reg), mask)

sys/dev/pci/if_aq.c

995

#define AQ_WRITE_REG_BIT(sc, reg, mask, val) \

sys/dev/pci/if_aq.c

998

_v = AQ_READ_REG((sc), (reg)); \

sys/dev/pci/if_athn_pci.c

134

pcireg_t memtype, reg;

sys/dev/pci/if_athn_pci.c

163

reg = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x40);

sys/dev/pci/if_athn_pci.c

164

if (reg & 0xff00)

sys/dev/pci/if_athn_pci.c

165

pci_conf_write(pa->pa_pc, pa->pa_tag, 0x40, reg & ~0xff00);

sys/dev/pci/if_athn_pci.c

168

reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG);

sys/dev/pci/if_athn_pci.c

169

reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT);

sys/dev/pci/if_athn_pci.c

170

reg |= 168 << PCI_LATTIMER_SHIFT;

sys/dev/pci/if_athn_pci.c

171

pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, reg);

sys/dev/pci/if_athn_pci.c

174

reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG);

sys/dev/pci/if_athn_pci.c

175

subsysid = PCI_PRODUCT(reg);

sys/dev/pci/if_athn_pci.c

292

pcireg_t reg;

sys/dev/pci/if_athn_pci.c

297

reg = pci_conf_read(psc->psc_pc, psc->psc_tag, 0x40);

sys/dev/pci/if_athn_pci.c

298

if (reg & 0xff00)

sys/dev/pci/if_athn_pci.c

299

pci_conf_write(psc->psc_pc, psc->psc_tag, 0x40, reg & ~0xff00);

sys/dev/pci/if_athn_pci.c

340

pcireg_t reg;

sys/dev/pci/if_athn_pci.c

343

reg = pci_conf_read(psc->psc_pc, psc->psc_tag,

sys/dev/pci/if_athn_pci.c

345

reg &= ~(PCIE_LCSR_ASPM_L0S | PCIE_LCSR_ASPM_L1);

sys/dev/pci/if_athn_pci.c

347

psc->psc_cap_off + PCIE_LCSR, reg);

sys/dev/pci/if_bce.c

1379

bce_mii_read(device_t self, int phy, int reg, uint16_t *val)

sys/dev/pci/if_bce.c

1391

(MII_COMMAND_ACK << 16) | BCE_MIPHY(phy) | BCE_MIREG(reg)); /* MAGIC */

sys/dev/pci/if_bce.c

1404

"0x%08x\n", phy, reg, data);

sys/dev/pci/if_bce.c

1413

bce_mii_write(device_t self, int phy, int reg, uint16_t val)

sys/dev/pci/if_bce.c

1427

BCE_MIPHY(phy) | BCE_MIREG(reg));

sys/dev/pci/if_bce.c

1440

phy, reg, val);

sys/dev/pci/if_bce.c

1452

uint32_t reg;

sys/dev/pci/if_bce.c

1456

reg = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_CTL);

sys/dev/pci/if_bce.c

1457

if (sc->bce_mii.mii_media_active & IFM_FDX && !(reg & EXC_FD))

sys/dev/pci/if_bce.c

1459

reg | EXC_FD);

sys/dev/pci/if_bce.c

1460

else if (!(sc->bce_mii.mii_media_active & IFM_FDX) && reg & EXC_FD)

sys/dev/pci/if_bce.c

1462

reg & ~EXC_FD);

sys/dev/pci/if_bge.c

1084

bge_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val)

sys/dev/pci/if_bge.c

1106

BGE_MIPHY(phy) | BGE_MIREG(reg));

sys/dev/pci/if_bge.c

1140

bge_miibus_writereg(device_t dev, int phy, int reg, uint16_t val)

sys/dev/pci/if_bge.c

1150

(reg == MII_GTCR || reg == BRGPHY_MII_AUXCTL))

sys/dev/pci/if_bge.c

1165

BGE_MIPHY(phy) | BGE_MIREG(reg) | val);

sys/dev/pci/if_bge.c

2092

uint32_t dma_rw_ctl, misc_ctl, mode_ctl, reg;

sys/dev/pci/if_bge.c

2120

reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK;

sys/dev/pci/if_bge.c

2121

CSR_WRITE_4(sc, BGE_MODE_CTL, reg | BGE_MODECTL_PCIE_TLPADDR1);

sys/dev/pci/if_bge.c

2124

reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG +

sys/dev/pci/if_bge.c

2127

reg | BGE_TLP_PHYCTL1_EN_L1PLLPD);

sys/dev/pci/if_bge.c

2139

reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK;

sys/dev/pci/if_bge.c

2141

reg | BGE_MODECTL_PCIE_TLPADDR1);

sys/dev/pci/if_bge.c

2144

reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG +

sys/dev/pci/if_bge.c

2147

reg | BGE_TLP_PHYCTL5_DIS_L2CLKREQ);

sys/dev/pci/if_bge.c

2158

reg = CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL);

sys/dev/pci/if_bge.c

2160

reg | BGE_CPMU_PADRNG_CTL_RDIV2);

sys/dev/pci/if_bge.c

2166

reg = mode_ctl & ~BGE_MODECTL_PCIE_TLPADDRMASK;

sys/dev/pci/if_bge.c

2168

reg | BGE_MODECTL_PCIE_TLPADDR0);

sys/dev/pci/if_bge.c

2171

reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG +

sys/dev/pci/if_bge.c

2173

reg &= ~BGE_TLP_FTSMAX_MSK;

sys/dev/pci/if_bge.c

2175

reg | BGE_TLP_FTSMAX_VAL);

sys/dev/pci/if_bge.c

2181

reg = CSR_READ_4(sc, BGE_CPMU_LSPD_10MB_CLK);

sys/dev/pci/if_bge.c

2182

reg &= ~BGE_CPMU_LSPD_10MB_MACCLK_MASK;

sys/dev/pci/if_bge.c

2183

reg |= BGE_CPMU_LSPD_10MB_MACCLK_6_25;

sys/dev/pci/if_bge.c

2184

CSR_WRITE_4(sc, BGE_CPMU_LSPD_10MB_CLK, reg);

sys/dev/pci/if_bge.c

3239

pcireg_t memtype, subid, reg;

sys/dev/pci/if_bge.c

3320

reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag,

sys/dev/pci/if_bge.c

3322

sc->bge_mps = 128 << (reg & PCIE_DCAP_MAX_PAYLOAD);

sys/dev/pci/if_bge.c

3470

reg = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE);

sys/dev/pci/if_bge.c

3471

reg |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR |

sys/dev/pci/if_bge.c

3474

pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE, reg);

sys/dev/pci/if_bge.c

4200

pcireg_t devctl, reg;

sys/dev/pci/if_bge.c

4326

reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag,

sys/dev/pci/if_bge.c

4330

reg | (1 << 15));

sys/dev/pci/if_bge.c

4350

reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, BGE_PCI_CMD);

sys/dev/pci/if_bge.c

4374

reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, sc->bge_pcixcap

sys/dev/pci/if_bge.c

4378

reg &= ~PCIX_CMD_BYTECNT_MASK;

sys/dev/pci/if_bge.c

4379

reg |= PCIX_CMD_BCNT_2048;

sys/dev/pci/if_bge.c

4385

reg &= ~(PCIX_CMD_SPLTRANS_MASK

sys/dev/pci/if_bge.c

4387

reg |= PCIX_CMD_BCNT_2048;

sys/dev/pci/if_bge.c

4390

+ PCIX_CMD, reg & ~PCIX_CMD_RELAXED_ORDER);

sys/dev/pci/if_bge.c

5595

uint32_t mode, reg;

sys/dev/pci/if_bge.c

5614

reg = CSR_READ_4(sc, BGE_CPMU_CTRL);

sys/dev/pci/if_bge.c

5615

reg &= ~(BGE_CPMU_CTRL_LINK_AWARE_MODE |

sys/dev/pci/if_bge.c

5617

CSR_WRITE_4(sc, BGE_CPMU_CTRL, reg);

sys/dev/pci/if_bge.c

5619

reg = CSR_READ_4(sc, BGE_CPMU_LSPD_10MB_CLK);

sys/dev/pci/if_bge.c

5620

reg &= ~BGE_CPMU_LSPD_10MB_CLK;

sys/dev/pci/if_bge.c

5621

reg |= BGE_CPMU_LSPD_10MB_MACCLK_6_25;

sys/dev/pci/if_bge.c

5622

CSR_WRITE_4(sc, BGE_CPMU_LSPD_10MB_CLK, reg);

sys/dev/pci/if_bge.c

5624

reg = CSR_READ_4(sc, BGE_CPMU_LNK_AWARE_PWRMD);

sys/dev/pci/if_bge.c

5625

reg &= ~BGE_CPMU_LNK_AWARE_MACCLK_MASK;

sys/dev/pci/if_bge.c

5626

reg |= BGE_CPMU_LNK_AWARE_MACCLK_6_25;

sys/dev/pci/if_bge.c

5627

CSR_WRITE_4(sc, BGE_CPMU_LNK_AWARE_PWRMD, reg);

sys/dev/pci/if_bge.c

5629

reg = CSR_READ_4(sc, BGE_CPMU_HST_ACC);

sys/dev/pci/if_bge.c

5630

reg &= ~BGE_CPMU_HST_ACC_MACCLK_MASK;

sys/dev/pci/if_bge.c

5631

reg |= BGE_CPMU_HST_ACC_MACCLK_6_25;

sys/dev/pci/if_bge.c

5632

CSR_WRITE_4(sc, BGE_CPMU_HST_ACC, reg);

sys/dev/pci/if_bge.c

5638

reg = CSR_READ_4(sc, BGE_PCIE_PWRMNG_THRESH);

sys/dev/pci/if_bge.c

5639

reg = (reg & ~BGE_PCIE_PWRMNG_L1THRESH_MASK)

sys/dev/pci/if_bge.c

5642

CSR_WRITE_4(sc, BGE_PCIE_PWRMNG_THRESH, reg);

sys/dev/pci/if_bge.c

5644

reg = CSR_READ_4(sc, BGE_PCIE_EIDLE_DELAY);

sys/dev/pci/if_bge.c

5645

reg = (reg & ~BGE_PCIE_EIDLE_DELAY_MASK)

sys/dev/pci/if_bge.c

5647

CSR_WRITE_4(sc, BGE_PCIE_EIDLE_DELAY, reg);

sys/dev/pci/if_bge.c

5655

reg = CSR_READ_4(sc, BGE_PCIE_LINKCTL);

sys/dev/pci/if_bge.c

5656

reg = (reg & ~BGE_PCIE_LINKCTL_L1_PLL_PDEN)

sys/dev/pci/if_bge.c

5658

CSR_WRITE_4(sc, BGE_PCIE_LINKCTL, reg);

sys/dev/pci/if_bge.c

5765

reg = 1;

sys/dev/pci/if_bge.c

5767

reg = 2;

sys/dev/pci/if_bge.c

5768

CSR_WRITE_4_FLUSH(sc, BGE_MAX_RX_FRAME_LOWAT, reg);

sys/dev/pci/if_bge.c

5856

uint32_t reg;

sys/dev/pci/if_bge.c

5858

reg = CSR_READ_4(sc, BGE_CPMU_CTRL);

sys/dev/pci/if_bge.c

5859

if ((reg & BGE_CPMU_CTRL_GPHY_10MB_RXONLY) != 0) {

sys/dev/pci/if_bge.c

5860

reg &= ~BGE_CPMU_CTRL_GPHY_10MB_RXONLY;

sys/dev/pci/if_bge.c

5861

CSR_WRITE_4(sc, BGE_CPMU_CTRL, reg);

sys/dev/pci/if_bge.c

5870

uint32_t reg;

sys/dev/pci/if_bge.c

5872

reg = CSR_READ_4(sc, BGE_CPMU_LSPD_1000MB_CLK);

sys/dev/pci/if_bge.c

5873

if ((reg & BGE_CPMU_LSPD_1000MB_MACCLK_MASK)

sys/dev/pci/if_bge.c

5875

reg &= ~BGE_CPMU_LSPD_1000MB_MACCLK_MASK;

sys/dev/pci/if_bge.c

5877

CSR_WRITE_4(sc, BGE_CPMU_LSPD_1000MB_CLK, reg);

sys/dev/pci/if_bge.c

6117

bge_stop_block(struct bge_softc *sc, bus_addr_t reg, uint32_t bit)

sys/dev/pci/if_bge.c

6121

BGE_CLRBIT_FLUSH(sc, reg, bit);

sys/dev/pci/if_bge.c

6125

if ((CSR_READ_4(sc, reg) & bit) == 0)

sys/dev/pci/if_bge.c

6133

if (reg != BGE_SRS_MODE)

sys/dev/pci/if_bge.c

6136

(u_long)reg, bit);

sys/dev/pci/if_bge.c

6357

uint32_t reg, scale;

sys/dev/pci/if_bge.c

6359

reg = CSR_READ_4(sc, BGE_CPMU_CLCK_STAT) &

sys/dev/pci/if_bge.c

6361

if (reg == BGE_CPMU_CLCK_STAT_MAC_CLCK_62_5)

sys/dev/pci/if_bge.c

6363

else if (reg == BGE_CPMU_CLCK_STAT_MAC_CLCK_6_25)

sys/dev/pci/if_bge.c

6368

reg = CSR_READ_4(sc, BGE_MISC_CFG) &

sys/dev/pci/if_bge.c

6370

reg |= scale << 1;

sys/dev/pci/if_bge.c

6371

CSR_WRITE_4(sc, BGE_MISC_CFG, reg);

sys/dev/pci/if_bgevar.h

100

#define CSR_WRITE_4(sc, reg, val) \

sys/dev/pci/if_bgevar.h

101

bus_space_write_4(sc->bge_btag, sc->bge_bhandle, reg, val)

sys/dev/pci/if_bgevar.h

103

#define CSR_READ_4(sc, reg) \

sys/dev/pci/if_bgevar.h

104

bus_space_read_4(sc->bge_btag, sc->bge_bhandle, reg)

sys/dev/pci/if_bgevar.h

106

#define CSR_WRITE_4_FLUSH(sc, reg, val) \

sys/dev/pci/if_bgevar.h

108

CSR_WRITE_4(sc, reg, val); \

sys/dev/pci/if_bgevar.h

109

CSR_READ_4(sc, reg); \

sys/dev/pci/if_bgevar.h

112

#define BGE_SETBIT(sc, reg, x) \

sys/dev/pci/if_bgevar.h

113

CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | (x)))

sys/dev/pci/if_bgevar.h

114

#define BGE_SETBIT_FLUSH(sc, reg, x) \

sys/dev/pci/if_bgevar.h

116

BGE_SETBIT(sc, reg, x); \

sys/dev/pci/if_bgevar.h

117

CSR_READ_4(sc, reg); \

sys/dev/pci/if_bgevar.h

119

#define BGE_CLRBIT(sc, reg, x) \

sys/dev/pci/if_bgevar.h

120

CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~(x)))

sys/dev/pci/if_bgevar.h

121

#define BGE_CLRBIT_FLUSH(sc, reg, x) \

sys/dev/pci/if_bgevar.h

123

BGE_CLRBIT(sc, reg, x); \

sys/dev/pci/if_bgevar.h

124

CSR_READ_4(sc, reg); \

sys/dev/pci/if_bgevar.h

128

#define APE_WRITE_4(sc, reg, val) \

sys/dev/pci/if_bgevar.h

129

bus_space_write_4(sc->bge_apetag, sc->bge_apehandle, reg, val)

sys/dev/pci/if_bgevar.h

131

#define APE_READ_4(sc, reg) \

sys/dev/pci/if_bgevar.h

132

bus_space_read_4(sc->bge_apetag, sc->bge_apehandle, reg)

sys/dev/pci/if_bgevar.h

134

#define APE_WRITE_4_FLUSH(sc, reg, val) \

sys/dev/pci/if_bgevar.h

136

APE_WRITE_4(sc, reg, val); \

sys/dev/pci/if_bgevar.h

137

APE_READ_4(sc, reg); \

sys/dev/pci/if_bgevar.h

140

#define APE_SETBIT(sc, reg, x) \

sys/dev/pci/if_bgevar.h

141

APE_WRITE_4(sc, reg, (APE_READ_4(sc, reg) | (x)))

sys/dev/pci/if_bgevar.h

142

#define APE_CLRBIT(sc, reg, x) \

sys/dev/pci/if_bgevar.h

143

APE_WRITE_4(sc, reg, (APE_READ_4(sc, reg) & ~(x)))

sys/dev/pci/if_bgevar.h

145

#define PCI_SETBIT(pc, tag, reg, x) \

sys/dev/pci/if_bgevar.h

146

pci_conf_write(pc, tag, reg, (pci_conf_read(pc, tag, reg) | (x)))

sys/dev/pci/if_bgevar.h

147

#define PCI_CLRBIT(pc, tag, reg, x) \

sys/dev/pci/if_bgevar.h

148

pci_conf_write(pc, tag, reg, (pci_conf_read(pc, tag, reg) & ~(x)))

sys/dev/pci/if_bgevar.h

249

int reg;

sys/dev/pci/if_bnx.c

1100

bnx_miibus_read_reg(device_t dev, int phy, int reg, uint16_t *val)

sys/dev/pci/if_bnx.c

1112

if (reg >= MII_BMCR && reg <= MII_ANLPRNP)

sys/dev/pci/if_bnx.c

1113

reg += 0x10;

sys/dev/pci/if_bnx.c

1126

data = BNX_MIPHY(phy) | BNX_MIREG(reg) |

sys/dev/pci/if_bnx.c

1147

"reg = 0x%04X\n", __FILE__, __LINE__, phy, reg);

sys/dev/pci/if_bnx.c

1155

phy, (uint16_t) reg & 0xffff, *val);

sys/dev/pci/if_bnx.c

1180

bnx_miibus_write_reg(device_t dev, int phy, int reg, uint16_t val)

sys/dev/pci/if_bnx.c

1188

phy, (uint16_t) reg & 0xffff, val);

sys/dev/pci/if_bnx.c

1196

if (reg >= MII_BMCR && reg <= MII_ANLPRNP)

sys/dev/pci/if_bnx.c

1197

reg += 0x10;

sys/dev/pci/if_bnx.c

1210

val1 = BNX_MIPHY(phy) | BNX_MIREG(reg) | val |

sys/dev/pci/if_bnx.c

3756

uint32_t reg, val;

sys/dev/pci/if_bnx.c

3812

reg = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_DEV_INFO_SIGNATURE);

sys/dev/pci/if_bnx.c

3816

__FILE__, __LINE__); reg = 0);

sys/dev/pci/if_bnx.c

3818

if ((reg & BNX_DEV_INFO_SIGNATURE_MAGIC_MASK) !=

sys/dev/pci/if_bnx.c

3822

(reg & BNX_DEV_INFO_SIGNATURE_MAGIC_MASK),

sys/dev/pci/if_bnx.c

529

pcireg_t reg;

sys/dev/pci/if_bnx.c

532

if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIX, &reg,

sys/dev/pci/if_bnx.c

538

if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIEXPRESS, &reg,

sys/dev/pci/if_bnx.c

541

reg + PCIE_LCSR);

sys/dev/pci/if_bnx.c

551

if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_MSI, &reg,

sys/dev/pci/if_bnx.c

556

if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_MSIX, &reg,

sys/dev/pci/if_bnxvar.h

85

#define REG_WR(sc, reg, val) bus_space_write_4(sc->bnx_btag, sc->bnx_bhandle, reg, val)

sys/dev/pci/if_bnxvar.h

86

#define REG_WR16(sc, reg, val) bus_space_write_2(sc->bnx_btag, sc->bnx_bhandle, reg, val)

sys/dev/pci/if_bnxvar.h

87

#define REG_RD(sc, reg) bus_space_read_4(sc->bnx_btag, sc->bnx_bhandle, reg)

sys/dev/pci/if_bnxvar.h

91

#define BNX_SETBIT(sc, reg, x) REG_WR(sc, reg, (REG_RD(sc, reg) | (x)))

sys/dev/pci/if_bnxvar.h

92

#define BNX_CLRBIT(sc, reg, x) REG_WR(sc, reg, (REG_RD(sc, reg) & ~(x)))

sys/dev/pci/if_bnxvar.h

93

#define PCI_SETBIT(pc, tag, reg, x) pci_conf_write(pc, tag, reg, (pci_conf_read(pc, tag, reg) | (x)))

sys/dev/pci/if_bnxvar.h

94

#define PCI_CLRBIT(pc, tag, reg, x) pci_conf_write(pc, tag, reg, (pci_conf_read(pc, tag, reg) & ~(x)))

sys/dev/pci/if_bwfm_pci.c

1556

bwfm_pci_buscore_read(struct bwfm_softc *bwfm, uint32_t reg)

sys/dev/pci/if_bwfm_pci.c

1561

page = reg & ~(BWFM_PCI_BAR0_REG_SIZE - 1);

sys/dev/pci/if_bwfm_pci.c

1562

offset = reg & (BWFM_PCI_BAR0_REG_SIZE - 1);

sys/dev/pci/if_bwfm_pci.c

1568

bwfm_pci_buscore_write(struct bwfm_softc *bwfm, uint32_t reg, uint32_t val)

sys/dev/pci/if_bwfm_pci.c

1573

page = reg & ~(BWFM_PCI_BAR0_REG_SIZE - 1);

sys/dev/pci/if_bwfm_pci.c

1574

offset = reg & (BWFM_PCI_BAR0_REG_SIZE - 1);

sys/dev/pci/if_bwfm_pci.c

1590

uint32_t reg;

sys/dev/pci/if_bwfm_pci.c

1594

reg = pci_conf_read(sc->sc_pc, sc->sc_tag,

sys/dev/pci/if_bwfm_pci.c

1597

reg & ~BWFM_PCI_CFGREG_LINK_STATUS_CTRL_ASPM_ENAB);

sys/dev/pci/if_bwfm_pci.c

1606

BWFM_PCI_CFGREG_LINK_STATUS_CTRL, reg);

sys/dev/pci/if_bwfm_pci.c

1627

reg = bus_space_read_4(sc->sc_reg_iot, sc->sc_reg_ioh,

sys/dev/pci/if_bwfm_pci.c

1630

DEVNAME(sc), cfg_offset[i], reg));

sys/dev/pci/if_bwfm_pci.c

1632

BWFM_PCI_PCIE2REG_CONFIGDATA, reg);

sys/dev/pci/if_bwfm_pci.c

1636

reg = bus_space_read_4(sc->sc_reg_iot, sc->sc_reg_ioh,

sys/dev/pci/if_bwfm_pci.c

1638

if (reg != 0xffffffff)

sys/dev/pci/if_bwfm_pci.c

1640

BWFM_PCI_PCIE2REG_MAILBOXINT, reg);

sys/dev/pci/if_bwfm_pci.c

479

uint32_t idx_offset, reg;

sys/dev/pci/if_bwfm_pci.c

491

reg = bus_space_read_4(sc->sc_reg_iot, sc->sc_reg_ioh,

sys/dev/pci/if_bwfm_pci.c

494

BWFM_PCI_PCIE2REG_CONFIGDATA, reg);

sys/dev/pci/if_bwi_pci.c

132

pcireg_t memtype, reg;

sys/dev/pci/if_bwi_pci.c

184

reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG);

sys/dev/pci/if_bwi_pci.c

188

sc->sc_pci_subvid = PCI_VENDOR(reg);

sys/dev/pci/if_bwi_pci.c

189

sc->sc_pci_subdid = PCI_PRODUCT(reg);

sys/dev/pci/if_bwi_pci.c

230

bwi_pci_conf_write(void *sc, uint32_t reg, uint32_t val)

sys/dev/pci/if_bwi_pci.c

234

pci_conf_write(psc->psc_pc, psc->psc_pcitag, reg, val);

sys/dev/pci/if_bwi_pci.c

238

bwi_pci_conf_read(void *sc, uint32_t reg)

sys/dev/pci/if_bwi_pci.c

242

return (pci_conf_read(psc->psc_pc, psc->psc_pcitag, reg));

sys/dev/pci/if_cas.c

1651

cas_mii_readreg(device_t self, int phy, int reg, uint16_t *val)

sys/dev/pci/if_cas.c

1661

printf("cas_mii_readreg: phy %d reg %d\n", phy, reg);

sys/dev/pci/if_cas.c

1665

v = (reg << CAS_MIF_REG_SHIFT) | (phy << CAS_MIF_PHY_SHIFT) |

sys/dev/pci/if_cas.c

1683

cas_mii_writereg(device_t self, int phy, int reg, uint16_t val)

sys/dev/pci/if_cas.c

1694

phy, reg, val);

sys/dev/pci/if_cas.c

1700

(reg << CAS_MIF_REG_SHIFT) |

sys/dev/pci/if_cas.c

1766

cas_pcs_readreg(device_t self, int phy, int reg, uint16_t *val)

sys/dev/pci/if_cas.c

1774

printf("cas_pcs_readreg: phy %d reg %d\n", phy, reg);

sys/dev/pci/if_cas.c

1780

switch (reg) {

sys/dev/pci/if_cas.c

1782

reg = CAS_MII_CONTROL;

sys/dev/pci/if_cas.c

1785

reg = CAS_MII_STATUS;

sys/dev/pci/if_cas.c

1788

reg = CAS_MII_ANAR;

sys/dev/pci/if_cas.c

1791

reg = CAS_MII_ANLPAR;

sys/dev/pci/if_cas.c

1800

*val = bus_space_read_4(t, pcs, reg) & 0xffff;

sys/dev/pci/if_cas.c

1805

cas_pcs_writereg(device_t self, int phy, int reg, uint16_t val)

sys/dev/pci/if_cas.c

1815

phy, reg, val);

sys/dev/pci/if_cas.c

1821

if (reg == MII_ANAR)

sys/dev/pci/if_cas.c

1824

switch (reg) {

sys/dev/pci/if_cas.c

1827

reg = CAS_MII_CONTROL;

sys/dev/pci/if_cas.c

1830

reg = CAS_MII_STATUS;

sys/dev/pci/if_cas.c

1833

reg = CAS_MII_ANAR;

sys/dev/pci/if_cas.c

1836

reg = CAS_MII_ANLPAR;

sys/dev/pci/if_cas.c

1842

bus_space_write_4(t, pcs, reg, val);

sys/dev/pci/if_cas.c

1847

if (reg == CAS_MII_ANAR || reset)

sys/dev/pci/if_cas.c

482

uint32_t reg;

sys/dev/pci/if_cas.c

637

reg = bus_space_read_4(sc->sc_memt, sc->sc_memh,

sys/dev/pci/if_cas.c

640

reg |= CAS_SATURN_PCFG_FSI;

sys/dev/pci/if_cas.c

642

CAS_SATURN_PCFG, reg);

sys/dev/pci/if_cas.c

879

uint32_t reg;

sys/dev/pci/if_cas.c

882

reg = bus_space_read_4(sc->sc_memt, h, r);

sys/dev/pci/if_cas.c

883

if ((reg & clr) == 0 && (reg & set) == set)

sys/dev/pci/if_dge.c

1884

uint32_t reg;

sys/dev/pci/if_dge.c

1990

reg = CSR_READ(sc, DGE_RXCSUM);

sys/dev/pci/if_dge.c

1992

reg |= RXCSUM_IPOFL;

sys/dev/pci/if_dge.c

1994

reg &= ~RXCSUM_IPOFL;

sys/dev/pci/if_dge.c

1996

reg |= RXCSUM_IPOFL | RXCSUM_TUOFL;

sys/dev/pci/if_dge.c

1998

reg &= ~RXCSUM_TUOFL;

sys/dev/pci/if_dge.c

2000

reg &= ~RXCSUM_IPOFL;

sys/dev/pci/if_dge.c

2002

CSR_WRITE(sc, DGE_RXCSUM, reg);

sys/dev/pci/if_dge.c

2233

uint32_t hash, reg, bit;

sys/dev/pci/if_dge.c

2275

reg = (hash >> 5) & 0x7f;

sys/dev/pci/if_dge.c

2278

hash = CSR_READ(sc, DGE_MTA + (reg << 2));

sys/dev/pci/if_dge.c

2281

CSR_WRITE(sc, DGE_MTA + (reg << 2), hash);

sys/dev/pci/if_dge.c

2322

uint32_t reg;

sys/dev/pci/if_dge.c

2326

reg = CSR_READ(sc, DGE_EECD) & ~(EECD_SK | EECD_DI | EECD_CS);

sys/dev/pci/if_dge.c

2329

CSR_WRITE(sc, DGE_EECD, reg);

sys/dev/pci/if_dge.c

2331

CSR_WRITE(sc, DGE_EECD, reg | EECD_CS);

sys/dev/pci/if_dge.c

2349

CSR_WRITE(sc, DGE_EECD, reg);

sys/dev/pci/if_dge.c

2360

int reg;

sys/dev/pci/if_dge.c

2362

reg = CSR_READ(sc, DGE_EECD) & ~(EECD_DI | EECD_SK);

sys/dev/pci/if_dge.c

2364

reg |= EECD_DI;

sys/dev/pci/if_dge.c

2366

CSR_WRITE(sc, DGE_EECD, reg);

sys/dev/pci/if_dge.c

2368

CSR_WRITE(sc, DGE_EECD, reg | EECD_SK);

sys/dev/pci/if_dge.c

2370

CSR_WRITE(sc, DGE_EECD, reg);

sys/dev/pci/if_dge.c

2380

int reg, rv;

sys/dev/pci/if_dge.c

2382

reg = CSR_READ(sc, DGE_EECD) & ~(EECD_DI | EECD_DO | EECD_SK);

sys/dev/pci/if_dge.c

2384

CSR_WRITE(sc, DGE_EECD, reg | EECD_SK); /* Raise clock */

sys/dev/pci/if_dge.c

2387

CSR_WRITE(sc, DGE_EECD, reg); /* Lower clock */

sys/dev/pci/if_dge.c

2425

dge_xgmii_writereg(struct dge_softc *sc, int phy, int reg, int val)

sys/dev/pci/if_dge.c

2430

if (((mdic = phwait(sc, phy, reg, 1, MDIO_ADDR)) & MDIO_CMD)) {

sys/dev/pci/if_dge.c

2432

device_xname(sc->sc_dev), phy, reg);

sys/dev/pci/if_dge.c

2435

if (((mdic = phwait(sc, phy, reg, 1, MDIO_WRITE)) & MDIO_CMD)) {

sys/dev/pci/if_dge.c

2437

device_xname(sc->sc_dev), phy, reg);

sys/dev/pci/if_dge.c

365

#define CSR_READ(sc, reg) \

sys/dev/pci/if_dge.c

366

bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))

sys/dev/pci/if_dge.c

367

#define CSR_WRITE(sc, reg, val) \

sys/dev/pci/if_dge.c

368

bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))

sys/dev/pci/if_dge.c

700

uint32_t reg;

sys/dev/pci/if_dge.c

756

reg = CSR_READ(sc, DGE_STATUS);

sys/dev/pci/if_dge.c

757

if (reg & STATUS_BUS64)

sys/dev/pci/if_dge.c

768

switch (reg & STATUS_PCIX_MSK) {

sys/dev/pci/if_dge.c

781

reg & STATUS_PCIX_MSK);

sys/dev/pci/if_dge.c

785

sc->sc_bus_speed = (reg & STATUS_BUS64) ? 66 : 33;

sys/dev/pci/if_dgereg.h

194

#define RA_ADDR(reg, idx) ((reg) + (idx) * 8)

sys/dev/pci/if_ena.c

317

pcireg_t memtype, reg;

sys/dev/pci/if_ena.c

327

reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);

sys/dev/pci/if_ena.c

328

if (((reg & PCI_COMMAND_MASTER_ENABLE) == 0) ||

sys/dev/pci/if_ena.c

329

((reg & PCI_COMMAND_MEM_ENABLE) == 0)) {

sys/dev/pci/if_ena.c

334

reg |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_MEM_ENABLE;

sys/dev/pci/if_ena.c

336

reg);

sys/dev/pci/if_ena.c

3687

pcireg_t reg;

sys/dev/pci/if_ena.c

3703

reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);

sys/dev/pci/if_ena.c

3704

if ((reg & PCI_COMMAND_MASTER_ENABLE) == 0) {

sys/dev/pci/if_ena.c

3705

reg |= PCI_COMMAND_MASTER_ENABLE;

sys/dev/pci/if_ena.c

3706

pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, reg);

sys/dev/pci/if_epic_pci.c

128

pcireg_t reg;

sys/dev/pci/if_epic_pci.c

131

reg = pci_conf_read(pc, pa->pa_tag, PCI_SUBSYS_ID_REG);

sys/dev/pci/if_epic_pci.c

134

if (esp->subsysid == reg)

sys/dev/pci/if_et.c

361

et_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val)

sys/dev/pci/if_et.c

371

__SHIFTIN(reg, ET_MII_ADDR_REG);

sys/dev/pci/if_et.c

387

phy, reg);

sys/dev/pci/if_et.c

405

et_miibus_writereg(device_t dev, int phy, int reg, uint16_t val)

sys/dev/pci/if_et.c

417

__SHIFTIN(reg, ET_MII_ADDR_REG);

sys/dev/pci/if_et.c

433

phy, reg);

sys/dev/pci/if_et.c

434

et_miibus_readreg(dev, phy, reg, &tmp);

sys/dev/pci/if_etreg.h

355

#define CSR_WRITE_4(sc, reg, val) \

sys/dev/pci/if_etreg.h

356

bus_space_write_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val))

sys/dev/pci/if_etreg.h

357

#define CSR_READ_4(sc, reg) \

sys/dev/pci/if_etreg.h

358

bus_space_read_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg))

sys/dev/pci/if_ex_pci.c

364

pcireg_t reg;

sys/dev/pci/if_ex_pci.c

366

reg = pci_conf_read(psc->psc_pc, psc->psc_tag, PCI_COMMAND_STATUS_REG);

sys/dev/pci/if_ex_pci.c

370

(reg & 0xffff0000) |

sys/dev/pci/if_fxp_pci.c

244

pcireg_t reg;

sys/dev/pci/if_fxp_pci.c

261

if (((reg = pci_conf_read(psc->psc_pc, psc->psc_tag,

sys/dev/pci/if_fxp_pci.c

265

reg = pci_conf_read(psc->psc_pc, psc->psc_tag, PCI_COMMAND_STATUS_REG);

sys/dev/pci/if_fxp_pci.c

269

(reg & 0xffff0000) |

sys/dev/pci/if_iavf.c

1101

uint32_t reg;

sys/dev/pci/if_iavf.c

1129

reg = iavf_rd(sc, I40E_VFINT_DYN_CTL01);

sys/dev/pci/if_iavf.c

1130

reg |= (IAVF_NOITR << I40E_VFINT_DYN_CTL0_ITR_INDX_SHIFT);

sys/dev/pci/if_iavf.c

1131

iavf_wr(sc, I40E_VFINT_DYN_CTL01, reg);

sys/dev/pci/if_iavf.c

1156

uint32_t reg;

sys/dev/pci/if_iavf.c

1177

reg = iavf_rd(sc, I40E_VFINT_DYN_CTL01);

sys/dev/pci/if_iavf.c

1178

reg |= I40E_VFINT_DYN_CTL0_INTENA_MSK_MASK |

sys/dev/pci/if_iavf.c

1180

iavf_wr(sc, I40E_VFINT_DYN_CTL01, reg);

sys/dev/pci/if_iavf.c

1505

uint32_t reg;

sys/dev/pci/if_iavf.c

1508

reg = iavf_rd(sc, I40E_VFGEN_RSTAT) &

sys/dev/pci/if_iavf.c

1510

if (reg == IAVF_VFR_VFACTIVE ||

sys/dev/pci/if_iavf.c

1511

reg == IAVF_VFR_COMPLETED)

sys/dev/pci/if_iavf.c

2080

uint32_t reg;

sys/dev/pci/if_iavf.c

2115

reg = iavf_rd(sc, sc->sc_aq_regs->atq_bal);

sys/dev/pci/if_iavf.c

2116

if (reg != ixl_dmamem_lo(&sc->sc_atq))

sys/dev/pci/if_iavf.c

2119

reg = iavf_rd(sc, sc->sc_aq_regs->arq_bal);

sys/dev/pci/if_iavf.c

2120

if (reg != ixl_dmamem_lo(&sc->sc_arq))

sys/dev/pci/if_ipwreg.h

313

#define CSR_READ_1(sc, reg) \

sys/dev/pci/if_ipwreg.h

314

bus_space_read_1((sc)->sc_st, (sc)->sc_sh, (reg))

sys/dev/pci/if_ipwreg.h

316

#define CSR_READ_2(sc, reg) \

sys/dev/pci/if_ipwreg.h

317

bus_space_read_2((sc)->sc_st, (sc)->sc_sh, (reg))

sys/dev/pci/if_ipwreg.h

319

#define CSR_READ_4(sc, reg) \

sys/dev/pci/if_ipwreg.h

320

bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))

sys/dev/pci/if_ipwreg.h

322

#define CSR_WRITE_1(sc, reg, val) \

sys/dev/pci/if_ipwreg.h

323

bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))

sys/dev/pci/if_ipwreg.h

325

#define CSR_WRITE_2(sc, reg, val) \

sys/dev/pci/if_ipwreg.h

326

bus_space_write_2((sc)->sc_st, (sc)->sc_sh, (reg), (val))

sys/dev/pci/if_ipwreg.h

328

#define CSR_WRITE_4(sc, reg, val) \

sys/dev/pci/if_ipwreg.h

329

bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))

sys/dev/pci/if_ipwreg.h

331

#define CSR_WRITE_MULTI_1(sc, reg, buf, len) \

sys/dev/pci/if_ipwreg.h

332

bus_space_write_multi_1((sc)->sc_st, (sc)->sc_sh, (reg), \

sys/dev/pci/if_iwireg.h

533

#define CSR_READ_1(sc, reg) \

sys/dev/pci/if_iwireg.h

534

bus_space_read_1((sc)->sc_st, (sc)->sc_sh, (reg))

sys/dev/pci/if_iwireg.h

536

#define CSR_READ_2(sc, reg) \

sys/dev/pci/if_iwireg.h

537

bus_space_read_2((sc)->sc_st, (sc)->sc_sh, (reg))

sys/dev/pci/if_iwireg.h

539

#define CSR_READ_4(sc, reg) \

sys/dev/pci/if_iwireg.h

540

bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))

sys/dev/pci/if_iwireg.h

546

#define CSR_WRITE_1(sc, reg, val) \

sys/dev/pci/if_iwireg.h

547

bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))

sys/dev/pci/if_iwireg.h

549

#define CSR_WRITE_2(sc, reg, val) \

sys/dev/pci/if_iwireg.h

550

bus_space_write_2((sc)->sc_st, (sc)->sc_sh, (reg), (val))

sys/dev/pci/if_iwireg.h

552

#define CSR_WRITE_4(sc, reg, val) \

sys/dev/pci/if_iwireg.h

553

bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))

sys/dev/pci/if_iwm.c

1151

iwm_poll_bit(struct iwm_softc *sc, int reg, uint32_t bits, uint32_t mask,

sys/dev/pci/if_iwm.c

1155

if ((IWM_READ(sc, reg) & mask) == (bits & mask)) {

sys/dev/pci/if_iwm.c

1221

iwm_set_bits_mask_prph(struct iwm_softc *sc, uint32_t reg, uint32_t bits,

sys/dev/pci/if_iwm.c

1227

val = iwm_read_prph(sc, reg) & mask;

sys/dev/pci/if_iwm.c

1229

iwm_write_prph(sc, reg, val);

sys/dev/pci/if_iwm.c

1237

iwm_set_bits_prph(struct iwm_softc *sc, uint32_t reg, uint32_t bits)

sys/dev/pci/if_iwm.c

1239

return iwm_set_bits_mask_prph(sc, reg, bits, ~0);

sys/dev/pci/if_iwm.c

1243

iwm_clear_bits_prph(struct iwm_softc *sc, uint32_t reg, uint32_t bits)

sys/dev/pci/if_iwm.c

1245

return iwm_set_bits_mask_prph(sc, reg, 0, ~bits);

sys/dev/pci/if_iwm.c

1693

pcireg_t reg;

sys/dev/pci/if_iwm.c

1695

reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag,

sys/dev/pci/if_iwm.c

1697

if (reg & PCIE_LCSR_ASPM_L1) {

sys/dev/pci/if_iwm.c

1708

reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag,

sys/dev/pci/if_iwm.c

1710

sc->sc_ltr_enabled = (reg & PCIE_DCSR2_LTR_MEC) ? 1 : 0;

sys/dev/pci/if_iwm.c

8929

pcireg_t reg, memtype;

sys/dev/pci/if_iwm.c

8967

reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40);

sys/dev/pci/if_iwm.c

8968

pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, reg & ~0xff00);

sys/dev/pci/if_iwm.c

8971

reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, PCI_COMMAND_STATUS_REG);

sys/dev/pci/if_iwm.c

8972

reg |= PCI_COMMAND_MASTER_ENABLE;

sys/dev/pci/if_iwm.c

8973

pci_conf_write(sc->sc_pct, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, reg);

sys/dev/pci/if_iwm.c

8989

reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, PCI_COMMAND_STATUS_REG);

sys/dev/pci/if_iwm.c

8991

CLR(reg, PCI_COMMAND_INTERRUPT_DISABLE);

sys/dev/pci/if_iwm.c

8993

SET(reg, PCI_COMMAND_INTERRUPT_DISABLE);

sys/dev/pci/if_iwm.c

8994

pci_conf_write(sc->sc_pct, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, reg);

sys/dev/pci/if_iwm.c

9431

pcireg_t reg;

sys/dev/pci/if_iwm.c

9434

reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40);

sys/dev/pci/if_iwm.c

9435

pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, reg & ~0xff00);

sys/dev/pci/if_iwmreg.h

7199

#define IWM_READ(sc, reg) \

sys/dev/pci/if_iwmreg.h

7200

bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))

sys/dev/pci/if_iwmreg.h

7202

#define IWM_WRITE(sc, reg, val) \

sys/dev/pci/if_iwmreg.h

7203

bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))

sys/dev/pci/if_iwmreg.h

7205

#define IWM_WRITE_1(sc, reg, val) \

sys/dev/pci/if_iwmreg.h

7206

bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))

sys/dev/pci/if_iwmreg.h

7208

#define IWM_SETBITS(sc, reg, mask) \

sys/dev/pci/if_iwmreg.h

7209

IWM_WRITE(sc, reg, IWM_READ(sc, reg) | (mask))

sys/dev/pci/if_iwmreg.h

7211

#define IWM_CLRBITS(sc, reg, mask) \

sys/dev/pci/if_iwmreg.h

7212

IWM_WRITE(sc, reg, IWM_READ(sc, reg) & ~(mask))

sys/dev/pci/if_iwn.c

428

pcireg_t memtype, reg;

sys/dev/pci/if_iwn.c

4361

pcireg_t reg;

sys/dev/pci/if_iwn.c

4378

reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag,

sys/dev/pci/if_iwn.c

4380

if (!(reg & PCIE_LCSR_ASPM_L0S)) /* L0s Entry disabled. */

sys/dev/pci/if_iwn.c

456

reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40);

sys/dev/pci/if_iwn.c

457

if (reg & 0xff00)

sys/dev/pci/if_iwn.c

458

pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, reg & ~0xff00);

sys/dev/pci/if_iwn.c

462

reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, PCI_COMMAND_STATUS_REG);

sys/dev/pci/if_iwn.c

463

reg |= PCI_COMMAND_MASTER_ENABLE;

sys/dev/pci/if_iwn.c

464

pci_conf_write(sc->sc_pct, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, reg);

sys/dev/pci/if_iwn.c

486

reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, PCI_COMMAND_STATUS_REG);

sys/dev/pci/if_iwn.c

488

CLR(reg, PCI_COMMAND_INTERRUPT_DISABLE);

sys/dev/pci/if_iwn.c

490

SET(reg, PCI_COMMAND_INTERRUPT_DISABLE);

sys/dev/pci/if_iwn.c

491

pci_conf_write(sc->sc_pct, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, reg);

sys/dev/pci/if_iwn.c

6101

pcireg_t reg;

sys/dev/pci/if_iwn.c

6116

reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag,

sys/dev/pci/if_iwn.c

6119

if (reg & PCIE_LCSR_ASPM_L1) /* L1 Entry enabled. */

sys/dev/pci/if_iwn.c

969

pcireg_t reg;

sys/dev/pci/if_iwn.c

976

reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40);

sys/dev/pci/if_iwn.c

977

if (reg & 0xff00)

sys/dev/pci/if_iwn.c

978

pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, reg & ~0xff00);

sys/dev/pci/if_iwnreg.h

1998

#define IWN_READ(sc, reg) \

sys/dev/pci/if_iwnreg.h

1999

bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))

sys/dev/pci/if_iwnreg.h

2001

#define IWN_WRITE(sc, reg, val) \

sys/dev/pci/if_iwnreg.h

2002

bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))

sys/dev/pci/if_iwnreg.h

2004

#define IWN_WRITE_1(sc, reg, val) \

sys/dev/pci/if_iwnreg.h

2005

bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))

sys/dev/pci/if_iwnreg.h

2007

#define IWN_SETBITS(sc, reg, mask) \

sys/dev/pci/if_iwnreg.h

2008

IWN_WRITE(sc, reg, IWN_READ(sc, reg) | (mask))

sys/dev/pci/if_iwnreg.h

2010

#define IWN_CLRBITS(sc, reg, mask) \

sys/dev/pci/if_iwnreg.h

2011

IWN_WRITE(sc, reg, IWN_READ(sc, reg) & ~(mask))

sys/dev/pci/if_ixl.c

1969

uint32_t reg;

sys/dev/pci/if_ixl.c

2006

reg = ixl_rd(sc, I40E_QRX_ENA(i));

sys/dev/pci/if_ixl.c

2007

SET(reg, I40E_QRX_ENA_QENA_REQ_MASK);

sys/dev/pci/if_ixl.c

2008

ixl_wr(sc, I40E_QRX_ENA(i), reg);

sys/dev/pci/if_ixl.c

2014

reg = ixl_rd(sc, I40E_QTX_ENA(i));

sys/dev/pci/if_ixl.c

2015

SET(reg, I40E_QTX_ENA_QENA_REQ_MASK);

sys/dev/pci/if_ixl.c

2016

ixl_wr(sc, I40E_QTX_ENA(i), reg);

sys/dev/pci/if_ixl.c

2182

uint32_t reg;

sys/dev/pci/if_ixl.c

2209

reg = ixl_rd(sc, I40E_QTX_ENA(i));

sys/dev/pci/if_ixl.c

2210

CLR(reg, I40E_QTX_ENA_QENA_REQ_MASK);

sys/dev/pci/if_ixl.c

2211

ixl_wr(sc, I40E_QTX_ENA(i), reg);

sys/dev/pci/if_ixl.c

2215

reg = ixl_rd(sc, I40E_QRX_ENA(i));

sys/dev/pci/if_ixl.c

2216

CLR(reg, I40E_QRX_ENA_QENA_REQ_MASK);

sys/dev/pci/if_ixl.c

2217

ixl_wr(sc, I40E_QRX_ENA(i), reg);

sys/dev/pci/if_ixl.c

2427

bus_size_t reg;

sys/dev/pci/if_ixl.c

2431

reg = I40E_GLLAN_TXPRE_QDIS(qid / 128);

sys/dev/pci/if_ixl.c

2434

r = ixl_rd(sc, reg);

sys/dev/pci/if_ixl.c

2439

ixl_wr(sc, reg, r);

sys/dev/pci/if_ixl.c

2504

uint32_t reg;

sys/dev/pci/if_ixl.c

2508

reg = ixl_rd(sc, ena);

sys/dev/pci/if_ixl.c

2509

if (ISSET(reg, I40E_QTX_ENA_QENA_STAT_MASK))

sys/dev/pci/if_ixl.c

2522

uint32_t reg;

sys/dev/pci/if_ixl.c

2528

reg = ixl_rd(sc, ena);

sys/dev/pci/if_ixl.c

2529

if (ISSET(reg, I40E_QTX_ENA_QENA_STAT_MASK) == 0)

sys/dev/pci/if_ixl.c

3026

uint32_t reg;

sys/dev/pci/if_ixl.c

3030

reg = ixl_rd(sc, ena);

sys/dev/pci/if_ixl.c

3031

if (ISSET(reg, I40E_QRX_ENA_QENA_STAT_MASK))

sys/dev/pci/if_ixl.c

3044

uint32_t reg;

sys/dev/pci/if_ixl.c

3050

reg = ixl_rd(sc, ena);

sys/dev/pci/if_ixl.c

3051

if (ISSET(reg, I40E_QRX_ENA_QENA_STAT_MASK) == 0)

sys/dev/pci/if_ixl.c

3516

ixl_print_hmc_error(struct ixl_softc *sc, uint32_t reg)

sys/dev/pci/if_ixl.c

3521

hmc_idx = reg & I40E_PFHMC_ERRORINFO_PMF_INDEX_MASK;

sys/dev/pci/if_ixl.c

3523

hmc_isvf = reg & I40E_PFHMC_ERRORINFO_PMF_ISVF_MASK;

sys/dev/pci/if_ixl.c

3525

hmc_errtype = reg & I40E_PFHMC_ERRORINFO_HMC_ERROR_TYPE_MASK;

sys/dev/pci/if_ixl.c

3527

hmc_objtype = reg & I40E_PFHMC_ERRORINFO_HMC_OBJECT_TYPE_MASK;

sys/dev/pci/if_ixl.c

3540

uint32_t icr, mask, reg;

sys/dev/pci/if_ixl.c

3564

reg = ixl_rd(sc, I40E_GLGEN_RSTAT);

sys/dev/pci/if_ixl.c

3565

reg = reg & I40E_GLGEN_RSTAT_RESET_TYPE_MASK;

sys/dev/pci/if_ixl.c

3566

reg = reg >> I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT;

sys/dev/pci/if_ixl.c

3569

reg == I40E_RESET_CORER ? "CORER" :

sys/dev/pci/if_ixl.c

3570

reg == I40E_RESET_GLOBR ? "GLOBR" :

sys/dev/pci/if_ixl.c

3571

reg == I40E_RESET_EMPR ? "EMPR" :

sys/dev/pci/if_ixl.c

3588

reg = ixl_rd(sc, I40E_PFHMC_ERRORINFO);

sys/dev/pci/if_ixl.c

3589

if (ISSET(reg, I40E_PFHMC_ERRORINFO_ERROR_DETECTED_MASK))

sys/dev/pci/if_ixl.c

3590

ixl_print_hmc_error(sc, reg);

sys/dev/pci/if_ixl.c

4653

uint32_t reg;

sys/dev/pci/if_ixl.c

4655

reg = ixl_rd_rx_csr(sc, I40E_PFQF_CTL_0);

sys/dev/pci/if_ixl.c

4657

CLR(reg, I40E_PFQF_CTL_0_HASHLUTSIZE_MASK);

sys/dev/pci/if_ixl.c

4658

SET(reg, I40E_HASH_LUT_SIZE_128 << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT);

sys/dev/pci/if_ixl.c

4660

SET(reg, I40E_PFQF_CTL_0_FD_ENA_MASK);

sys/dev/pci/if_ixl.c

4661

SET(reg, I40E_PFQF_CTL_0_ETYPE_ENA_MASK);

sys/dev/pci/if_ixl.c

4662

SET(reg, I40E_PFQF_CTL_0_MACVLAN_ENA_MASK);

sys/dev/pci/if_ixl.c

4664

ixl_wr_rx_csr(sc, I40E_PFQF_CTL_0, reg);

sys/dev/pci/if_ixl.c

5106

uint32_t reg;

sys/dev/pci/if_ixl.c

5118

reg = ixl_rd(sc, regs[i].objsiz);

sys/dev/pci/if_ixl.c

5119

e->hmc_size = IXL_BIT_ULL(0x3F & reg);

sys/dev/pci/if_ixl.c

5476

uint32_t reg = 0, reg0 = 0;

sys/dev/pci/if_ixl.c

5491

reg = ixl_rd(sc, I40E_GLGEN_RSTAT);

sys/dev/pci/if_ixl.c

5492

if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))

sys/dev/pci/if_ixl.c

5496

if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {

sys/dev/pci/if_ixl.c

5503

reg = ixl_rd(sc, I40E_GLNVM_ULD);

sys/dev/pci/if_ixl.c

5504

reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |

sys/dev/pci/if_ixl.c

5506

if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |

sys/dev/pci/if_ixl.c

5512

if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |

sys/dev/pci/if_ixl.c

5515

"(I40E_GLNVM_ULD = 0x%x)\n", reg);

sys/dev/pci/if_ixl.c

5524

reg = ixl_rd(sc, I40E_PFGEN_CTRL);

sys/dev/pci/if_ixl.c

5525

ixl_wr(sc, I40E_PFGEN_CTRL, reg | I40E_PFGEN_CTRL_PFSWR_MASK);

sys/dev/pci/if_ixl.c

5527

reg = ixl_rd(sc, I40E_PFGEN_CTRL);

sys/dev/pci/if_ixl.c

5528

if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))

sys/dev/pci/if_ixl.c

5539

if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {

sys/dev/pci/if_ixl.c

5541

"(I40E_PFGEN_CTRL= 0x%x)\n", reg);

sys/dev/pci/if_ixl.c

6807

ixl_rx_ctl_read(struct ixl_softc *sc, uint32_t reg, uint32_t *rv)

sys/dev/pci/if_ixl.c

6813

iaq.iaq_param[1] = htole32(reg);

sys/dev/pci/if_ixl.c

6835

ixl_rd_rx_csr(struct ixl_softc *sc, uint32_t reg)

sys/dev/pci/if_ixl.c

6847

rv = ixl_rx_ctl_read(sc, reg, &val);

sys/dev/pci/if_ixl.c

6856

val = ixl_rd(sc, reg);

sys/dev/pci/if_ixl.c

6862

ixl_rx_ctl_write(struct ixl_softc *sc, uint32_t reg, uint32_t value)

sys/dev/pci/if_ixl.c

6868

iaq.iaq_param[1] = htole32(reg);

sys/dev/pci/if_ixl.c

6890

ixl_wr_rx_csr(struct ixl_softc *sc, uint32_t reg, uint32_t value)

sys/dev/pci/if_ixl.c

6901

rv = ixl_rx_ctl_write(sc, reg, value);

sys/dev/pci/if_ixl.c

6910

ixl_wr(sc, reg, value);

sys/dev/pci/if_ixl.c

6987

uint32_t reg;

sys/dev/pci/if_ixl.c

6991

reg = ixl_rd(sc, I40E_GLNVM_SRCTL);

sys/dev/pci/if_ixl.c

6992

if (ISSET(reg, I40E_GLNVM_SRCTL_DONE_MASK))

sys/dev/pci/if_ixl.c

7007

uint32_t reg;

sys/dev/pci/if_ixl.c

7012

reg = ((uint32_t)offset << I40E_GLNVM_SRCTL_ADDR_SHIFT) |

sys/dev/pci/if_ixl.c

7014

ixl_wr(sc, I40E_GLNVM_SRCTL, reg);

sys/dev/pci/if_ixl.c

7022

reg = ixl_rd(sc, I40E_GLNVM_SRDATA);

sys/dev/pci/if_ixl.c

7023

*data = (uint16_t)__SHIFTOUT(reg, I40E_GLNVM_SRDATA_RDDATA_MASK);

sys/dev/pci/if_ixlvar.h

666

uint32_t reg;

sys/dev/pci/if_jme.c

1005

SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg));

sys/dev/pci/if_jme.c

1014

aprint_error_dev(sc->jme_dev, "phy write timeout : %d\n", reg);

sys/dev/pci/if_jme.c

1922

uint32_t reg;

sys/dev/pci/if_jme.c

1927

reg = bus_space_read_4(sc->jme_bt_phy, sc->jme_bh_phy,

sys/dev/pci/if_jme.c

1929

if ((reg & SMBCSR_HW_BUSY_MASK) == SMBCSR_HW_IDLE)

sys/dev/pci/if_jme.c

1939

reg = ((uint32_t)addr << SMBINTF_ADDR_SHIFT) & SMBINTF_ADDR_MASK;

sys/dev/pci/if_jme.c

1941

JME_SMBINTF, reg | SMBINTF_RD | SMBINTF_CMD_TRIGGER);

sys/dev/pci/if_jme.c

1944

reg = bus_space_read_4(sc->jme_bt_phy, sc->jme_bh_phy,

sys/dev/pci/if_jme.c

1946

if ((reg & SMBINTF_CMD_TRIGGER) == 0)

sys/dev/pci/if_jme.c

1955

reg = bus_space_read_4(sc->jme_bt_phy, sc->jme_bh_phy, JME_SMBINTF);

sys/dev/pci/if_jme.c

1956

*val = (reg & SMBINTF_RD_DATA_MASK) >> SMBINTF_RD_DATA_SHIFT;

sys/dev/pci/if_jme.c

1965

uint8_t fup, reg, val;

sys/dev/pci/if_jme.c

1982

if (jme_eeprom_read_byte(sc, offset + 1, &reg) != 0)

sys/dev/pci/if_jme.c

1984

if (reg >= JME_PAR0 &&

sys/dev/pci/if_jme.c

1985

reg < JME_PAR0 + ETHER_ADDR_LEN) {

sys/dev/pci/if_jme.c

1989

eaddr[reg - JME_PAR0] = val;

sys/dev/pci/if_jme.c

2059

uint32_t reg;

sys/dev/pci/if_jme.c

2078

reg = (sc->jme_intrxto << PCCRX_COAL_TO_SHIFT) & PCCRX_COAL_TO_MASK;

sys/dev/pci/if_jme.c

2079

reg |= (sc->jme_intrxct << PCCRX_COAL_PKT_SHIFT) & PCCRX_COAL_PKT_MASK;

sys/dev/pci/if_jme.c

2080

bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCRX0, reg);

sys/dev/pci/if_jme.c

2090

uint32_t reg;

sys/dev/pci/if_jme.c

2109

reg = (sc->jme_intrxto << PCCRX_COAL_TO_SHIFT) & PCCRX_COAL_TO_MASK;

sys/dev/pci/if_jme.c

2110

reg |= (sc->jme_intrxct << PCCRX_COAL_PKT_SHIFT) & PCCRX_COAL_PKT_MASK;

sys/dev/pci/if_jme.c

2111

bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCRX0, reg);

sys/dev/pci/if_jme.c

2121

uint32_t reg;

sys/dev/pci/if_jme.c

2140

reg = (sc->jme_inttxto << PCCTX_COAL_TO_SHIFT) & PCCTX_COAL_TO_MASK;

sys/dev/pci/if_jme.c

2141

reg |= (sc->jme_inttxct << PCCTX_COAL_PKT_SHIFT) & PCCTX_COAL_PKT_MASK;

sys/dev/pci/if_jme.c

2142

reg |= PCCTX_COAL_TXQ0;

sys/dev/pci/if_jme.c

2143

bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCTX, reg);

sys/dev/pci/if_jme.c

2153

uint32_t reg;

sys/dev/pci/if_jme.c

2172

reg = (sc->jme_inttxto << PCCTX_COAL_TO_SHIFT) & PCCTX_COAL_TO_MASK;

sys/dev/pci/if_jme.c

2173

reg |= (sc->jme_inttxct << PCCTX_COAL_PKT_SHIFT) & PCCTX_COAL_PKT_MASK;

sys/dev/pci/if_jme.c

2174

reg |= PCCTX_COAL_TXQ0;

sys/dev/pci/if_jme.c

2175

bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCTX, reg);

sys/dev/pci/if_jme.c

554

uint32_t reg;

sys/dev/pci/if_jme.c

557

reg = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXCSR);

sys/dev/pci/if_jme.c

558

if ((reg & RXCSR_RX_ENB) == 0)

sys/dev/pci/if_jme.c

560

reg &= ~RXCSR_RX_ENB;

sys/dev/pci/if_jme.c

561

bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXCSR, reg);

sys/dev/pci/if_jme.c

576

uint32_t reg;

sys/dev/pci/if_jme.c

579

reg = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXCSR);

sys/dev/pci/if_jme.c

580

if ((reg & TXCSR_TX_ENB) == 0)

sys/dev/pci/if_jme.c

582

reg &= ~TXCSR_TX_ENB;

sys/dev/pci/if_jme.c

583

bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_TXCSR, reg);

sys/dev/pci/if_jme.c

726

uint32_t reg;

sys/dev/pci/if_jme.c

847

reg = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PMCS);

sys/dev/pci/if_jme.c

848

reg &= ~PMCS_WOL_ENB_MASK;

sys/dev/pci/if_jme.c

849

bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_PMCS, reg);

sys/dev/pci/if_jme.c

851

reg = bus_space_read_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC);

sys/dev/pci/if_jme.c

857

reg |= RXMAC_PAD_10BYTES;

sys/dev/pci/if_jme.c

861

reg |= RXMAC_CSUM_ENB;

sys/dev/pci/if_jme.c

862

reg |= RXMAC_VLAN_ENB; /* enable hardware vlan */

sys/dev/pci/if_jme.c

863

bus_space_write_4(sc->jme_bt_mac, sc->jme_bh_mac, JME_RXMAC, reg);

sys/dev/pci/if_jme.c

866

reg = bus_space_read_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_GPREG0);

sys/dev/pci/if_jme.c

867

reg &= ~GPREG0_PCC_UNIT_MASK;

sys/dev/pci/if_jme.c

869

reg |= GPREG0_PCC_UNIT_US;

sys/dev/pci/if_jme.c

877

reg |= GPREG0_SH_POST_DW7_DIS | GPREG0_SH_POST_DW6_DIS |

sys/dev/pci/if_jme.c

882

reg &= ~GPREG0_POST_DW0_ENB;

sys/dev/pci/if_jme.c

884

reg &= ~GPREG0_PME_ENB;

sys/dev/pci/if_jme.c

886

reg &= ~GPREG0_PHY_ADDR_MASK;

sys/dev/pci/if_jme.c

887

reg |= sc->jme_phyaddr;

sys/dev/pci/if_jme.c

888

bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_GPREG0, reg);

sys/dev/pci/if_jme.c

891

reg = (sc->jme_inttxto << PCCTX_COAL_TO_SHIFT) & PCCTX_COAL_TO_MASK;

sys/dev/pci/if_jme.c

892

reg |= (sc->jme_inttxct << PCCTX_COAL_PKT_SHIFT) & PCCTX_COAL_PKT_MASK;

sys/dev/pci/if_jme.c

893

reg |= PCCTX_COAL_TXQ0;

sys/dev/pci/if_jme.c

894

bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCTX, reg);

sys/dev/pci/if_jme.c

897

reg = (sc->jme_intrxto << PCCRX_COAL_TO_SHIFT) & PCCRX_COAL_TO_MASK;

sys/dev/pci/if_jme.c

898

reg |= (sc->jme_intrxct << PCCRX_COAL_PKT_SHIFT) & PCCRX_COAL_PKT_MASK;

sys/dev/pci/if_jme.c

899

bus_space_write_4(sc->jme_bt_misc, sc->jme_bh_misc, JME_PCCRX0, reg);

sys/dev/pci/if_jme.c

954

jme_mii_read(device_t self, int phy, int reg, uint16_t *val)

sys/dev/pci/if_jme.c

970

SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg));

sys/dev/pci/if_jme.c

979

aprint_error_dev(sc->jme_dev, "phy read timeout : %d\n", reg);

sys/dev/pci/if_jme.c

988

jme_mii_write(device_t self, int phy, int reg, uint16_t val)

sys/dev/pci/if_kse.c

1419

kse_mii_readreg(device_t self, int phy, int reg, uint16_t *val)

sys/dev/pci/if_kse.c

1423

if (phy != 1 || reg >= __arraycount(phy1csr) || reg < 0)

sys/dev/pci/if_kse.c

1425

*val = CSR_READ_2(sc, phy1csr[reg]);

sys/dev/pci/if_kse.c

1430

kse_mii_writereg(device_t self, int phy, int reg, uint16_t val)

sys/dev/pci/if_kse.c

1434

if (phy != 1 || reg >= __arraycount(phy1csr) || reg < 0)

sys/dev/pci/if_kse.c

1436

CSR_WRITE_2(sc, phy1csr[reg], val);

sys/dev/pci/if_kse.c

1502

int nport, p, i, reg, val;

sys/dev/pci/if_kse.c

1508

reg = EVCNTBR + p * 0x20 + i;

sys/dev/pci/if_kse.c

1509

CSR_WRITE_2(sc, IACR, reg);

sys/dev/pci/if_kse.c

1536

int nport, p, i, reg, val;

sys/dev/pci/if_kse.c

1542

reg = EVCNTBR + p * 0x20 + i;

sys/dev/pci/if_kse.c

1543

CSR_WRITE_2(sc, IACR, reg);

sys/dev/pci/if_lii.c

148

#define AT_READ_4(sc, reg) \

sys/dev/pci/if_lii.c

149

bus_space_read_4((sc)->sc_mmiot, (sc)->sc_mmioh, (reg))

sys/dev/pci/if_lii.c

150

#define AT_READ_2(sc, reg) \

sys/dev/pci/if_lii.c

151

bus_space_read_2((sc)->sc_mmiot, (sc)->sc_mmioh, (reg))

sys/dev/pci/if_lii.c

152

#define AT_READ_1(sc, reg) \

sys/dev/pci/if_lii.c

153

bus_space_read_1((sc)->sc_mmiot, (sc)->sc_mmioh, (reg))

sys/dev/pci/if_lii.c

154

#define AT_WRITE_4(sc, reg, val) \

sys/dev/pci/if_lii.c

155

bus_space_write_4((sc)->sc_mmiot, (sc)->sc_mmioh, (reg), (val))

sys/dev/pci/if_lii.c

156

#define AT_WRITE_2(sc, reg, val) \

sys/dev/pci/if_lii.c

157

bus_space_write_2((sc)->sc_mmiot, (sc)->sc_mmioh, (reg), (val))

sys/dev/pci/if_lii.c

158

#define AT_WRITE_1(sc, reg, val) \

sys/dev/pci/if_lii.c

159

bus_space_write_1((sc)->sc_mmiot, (sc)->sc_mmioh, (reg), (val))

sys/dev/pci/if_lii.c

162

AT_READ_4(struct lii_softc *sc, bus_size_t reg)

sys/dev/pci/if_lii.c

164

uint32_t r = bus_space_read_4(sc->sc_mmiot, sc->sc_mmioh, reg);

sys/dev/pci/if_lii.c

165

printf("AT_READ_4(%x) = %x\n", (unsigned int)reg, r);

sys/dev/pci/if_lii.c

170

AT_READ_2(struct lii_softc *sc, bus_size_t reg)

sys/dev/pci/if_lii.c

172

uint16_t r = bus_space_read_2(sc->sc_mmiot, sc->sc_mmioh, reg);

sys/dev/pci/if_lii.c

173

printf("AT_READ_2(%x) = %x\n", (unsigned int)reg, r);

sys/dev/pci/if_lii.c

178

AT_READ_1(struct lii_softc *sc, bus_size_t reg)

sys/dev/pci/if_lii.c

180

uint8_t r = bus_space_read_1(sc->sc_mmiot, sc->sc_mmioh, reg);

sys/dev/pci/if_lii.c

181

printf("AT_READ_1(%x) = %x\n", (unsigned int)reg, r);

sys/dev/pci/if_lii.c

186

AT_WRITE_4(struct lii_softc *sc, bus_size_t reg, uint32_t val)

sys/dev/pci/if_lii.c

188

printf("AT_WRITE_4(%x, %x)\n", (unsigned int)reg, val);

sys/dev/pci/if_lii.c

189

bus_space_write_4(sc->sc_mmiot, sc->sc_mmioh, reg, val);

sys/dev/pci/if_lii.c

193

AT_WRITE_2(struct lii_softc *sc, bus_size_t reg, uint16_t val)

sys/dev/pci/if_lii.c

195

printf("AT_WRITE_2(%x, %x)\n", (unsigned int)reg, val);

sys/dev/pci/if_lii.c

196

bus_space_write_2(sc->sc_mmiot, sc->sc_mmioh, reg, val);

sys/dev/pci/if_lii.c

200

AT_WRITE_1(struct lii_softc *sc, bus_size_t reg, uint8_t val)

sys/dev/pci/if_lii.c

202

printf("AT_WRITE_1(%x, %x)\n", (unsigned int)reg, val);

sys/dev/pci/if_lii.c

203

bus_space_write_1(sc->sc_mmiot, sc->sc_mmioh, reg, val);

sys/dev/pci/if_lii.c

414

lii_eeprom_read(struct lii_softc *sc, uint32_t reg, uint32_t *val)

sys/dev/pci/if_lii.c

416

int r = pci_vpd_read(sc->sc_pc, sc->sc_tag, reg, 1, (pcireg_t *)val);

sys/dev/pci/if_lii.c

418

DPRINTF(("lii_eeprom_read(%x) = %x\n", reg, *val));

sys/dev/pci/if_lii.c

496

lii_spi_read(struct lii_softc *sc, uint32_t reg, uint32_t *val)

sys/dev/pci/if_lii.c

502

AT_WRITE_4(sc, ATL2_SF_ADDR, reg);

sys/dev/pci/if_lii.c

583

lii_mii_readreg(device_t dev, int phy, int reg, uint16_t *val)

sys/dev/pci/if_lii.c

589

data = (reg & MDIOC_REG_MASK) << MDIOC_REG_SHIFT;

sys/dev/pci/if_lii.c

607

reg);

sys/dev/pci/if_lii.c

616

lii_mii_writereg(device_t dev, int phy, int reg, uint16_t val)

sys/dev/pci/if_lii.c

622

data = (reg & MDIOC_REG_MASK) << MDIOC_REG_SHIFT;

sys/dev/pci/if_lii.c

641

reg);

sys/dev/pci/if_mcx.c

3626

mcx_access_hca_reg(struct mcx_softc *sc, uint16_t reg, int op, void *data,

sys/dev/pci/if_mcx.c

3643

in->cmd_register_id = htobe16(reg);

sys/dev/pci/if_mcx.c

3662

(op == MCX_REG_OP_WRITE ? "write" : "read"), reg);

sys/dev/pci/if_mcx.c

3669

reg);

sys/dev/pci/if_mcx.c

3677

reg, out->cmd_status, be32toh(out->cmd_syndrome));

sys/dev/pci/if_msk.c

1036

for (reg = SK_TO0;reg <= SK_TO11; reg++)

sys/dev/pci/if_msk.c

1037

sk_win_write_1(sc, reg, 36);

sys/dev/pci/if_msk.c

1039

for (reg = SK_TO0;reg <= SK_TO11; reg++)

sys/dev/pci/if_msk.c

1040

sk_win_write_1(sc, reg + (SK_WIN_LEN / 2), 36);

sys/dev/pci/if_msk.c

2178

uint32_t idx, reg, sk_ctl;

sys/dev/pci/if_msk.c

2184

reg = SK_STAT_BMU_TXA1_RIDX;

sys/dev/pci/if_msk.c

2186

reg = SK_STAT_BMU_TXA2_RIDX;

sys/dev/pci/if_msk.c

2193

while (idx != sk_win_read_2(sc, reg)) {

sys/dev/pci/if_msk.c

2396

uint16_t reg;

sys/dev/pci/if_msk.c

2417

reg = SK_YU_READ_2(sc_if, YUKON_PAR);

sys/dev/pci/if_msk.c

2418

DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg));

sys/dev/pci/if_msk.c

2421

reg |= YU_PAR_MIB_CLR;

sys/dev/pci/if_msk.c

2422

DPRINTFN(6, ("msk_init_yukon: YUKON_PAR=%#x\n", reg));

sys/dev/pci/if_msk.c

2424

SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);

sys/dev/pci/if_msk.c

2428

reg &= ~YU_PAR_MIB_CLR;

sys/dev/pci/if_msk.c

2429

SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);

sys/dev/pci/if_msk.c

2448

reg = YU_SMR_DATA_BLIND(0x1c) |

sys/dev/pci/if_msk.c

245

sk_win_read_4(struct sk_softc *sc, uint32_t reg)

sys/dev/pci/if_msk.c

2454

reg |= YU_SMR_MFL_JUMBO;

sys/dev/pci/if_msk.c

2456

SK_YU_WRITE_2(sc_if, YUKON_SMR, reg);

sys/dev/pci/if_msk.c

247

return CSR_READ_4(sc, reg);

sys/dev/pci/if_msk.c

2473

reg = sk_win_read_2(sc_if->sk_softc,

sys/dev/pci/if_msk.c

2475

SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg);

sys/dev/pci/if_msk.c

251

sk_win_read_2(struct sk_softc *sc, uint32_t reg)

sys/dev/pci/if_msk.c

253

return CSR_READ_2(sc, reg);

sys/dev/pci/if_msk.c

257

sk_win_read_1(struct sk_softc *sc, uint32_t reg)

sys/dev/pci/if_msk.c

259

return CSR_READ_1(sc, reg);

sys/dev/pci/if_msk.c

263

sk_win_write_4(struct sk_softc *sc, uint32_t reg, uint32_t x)

sys/dev/pci/if_msk.c

265

CSR_WRITE_4(sc, reg, x);

sys/dev/pci/if_msk.c

269

sk_win_write_2(struct sk_softc *sc, uint32_t reg, uint16_t x)

sys/dev/pci/if_msk.c

271

CSR_WRITE_2(sc, reg, x);

sys/dev/pci/if_msk.c

275

sk_win_write_1(struct sk_softc *sc, uint32_t reg, uint8_t x)

sys/dev/pci/if_msk.c

277

CSR_WRITE_1(sc, reg, x);

sys/dev/pci/if_msk.c

281

msk_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val)

sys/dev/pci/if_msk.c

288

YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ);

sys/dev/pci/if_msk.c

307

phy, reg, *val));

sys/dev/pci/if_msk.c

313

msk_miibus_writereg(device_t dev, int phy, int reg, uint16_t val)

sys/dev/pci/if_msk.c

319

phy, reg, val));

sys/dev/pci/if_msk.c

323

YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE);

sys/dev/pci/if_msk.c

391

uint16_t reg;

sys/dev/pci/if_msk.c

401

reg = SK_YU_READ_2(sc_if, YUKON_RCR);

sys/dev/pci/if_msk.c

402

reg |= YU_RCR_UFLEN;

sys/dev/pci/if_msk.c

406

reg &= ~(YU_RCR_UFLEN | YU_RCR_MUFLEN);

sys/dev/pci/if_msk.c

432

reg |= YU_RCR_MUFLEN;

sys/dev/pci/if_msk.c

439

SK_YU_WRITE_2(sc_if, YUKON_RCR, reg);

sys/dev/pci/if_msk.c

928

int reg;

sys/dev/pci/if_nfe.c

537

nfe_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val)

sys/dev/pci/if_nfe.c

550

NFE_WRITE(sc, NFE_PHY_CTL, (phy << NFE_PHYADD_SHIFT) | reg);

sys/dev/pci/if_nfe.c

559

device_xname(sc->sc_dev), phy, reg));

sys/dev/pci/if_nfe.c

565

device_xname(sc->sc_dev), phy, reg));

sys/dev/pci/if_nfe.c

573

device_xname(sc->sc_dev), phy, reg, data));

sys/dev/pci/if_nfe.c

580

nfe_miibus_writereg(device_t dev, int phy, int reg, uint16_t val)

sys/dev/pci/if_nfe.c

594

ctl = NFE_PHY_WRITE | (phy << NFE_PHYADD_SHIFT) | reg;

sys/dev/pci/if_nfe.c

606

phy, reg);

sys/dev/pci/if_nfe.c

612

device_xname(sc->sc_dev), phy, reg));

sys/dev/pci/if_nfereg.h

199

#define NFE_READ(sc, reg) \

sys/dev/pci/if_nfereg.h

200

bus_space_read_4((sc)->sc_memt, (sc)->sc_memh, (reg))

sys/dev/pci/if_nfereg.h

202

#define NFE_WRITE(sc, reg, val) \

sys/dev/pci/if_nfereg.h

203

bus_space_write_4((sc)->sc_memt, (sc)->sc_memh, (reg), (val))

sys/dev/pci/if_ntwoc_pci.c

150

ntwoc_pci_sca_write_1(struct sca_softc *sc, u_int reg, u_int8_t val)

sys/dev/pci/if_ntwoc_pci.c

152

bus_space_write_1(sc->sc_iot, sc->sc_ioh, SCA_REG(reg), val);

sys/dev/pci/if_ntwoc_pci.c

156

ntwoc_pci_sca_write_2(struct sca_softc *sc, u_int reg, u_int16_t val)

sys/dev/pci/if_ntwoc_pci.c

158

bus_space_write_2(sc->sc_iot, sc->sc_ioh, SCA_REG(reg), val);

sys/dev/pci/if_ntwoc_pci.c

162

ntwoc_pci_sca_read_1(struct sca_softc *sc, u_int reg)

sys/dev/pci/if_ntwoc_pci.c

165

bus_space_read_1(sc->sc_iot, sc->sc_ioh, SCA_REG(reg));

sys/dev/pci/if_ntwoc_pci.c

169

ntwoc_pci_sca_read_2(struct sca_softc *sc, u_int reg)

sys/dev/pci/if_ntwoc_pci.c

172

bus_space_read_2(sc->sc_iot, sc->sc_ioh, SCA_REG(reg));

sys/dev/pci/if_pcn.c

1609

uint32_t reg;

sys/dev/pci/if_pcn.c

1753

reg = pcn_bcr_read(sc, LE_BCR18);

sys/dev/pci/if_pcn.c

1759

reg |= LE_B18_BREADE | LE_B18_BWRITE;

sys/dev/pci/if_pcn.c

1763

reg |= LE_B18_BREADE | LE_B18_BWRITE | LE_B18_NOUFLO;

sys/dev/pci/if_pcn.c

1766

pcn_bcr_write(sc, LE_BCR18, reg);

sys/dev/pci/if_pcn.c

2060

uint32_t reg;

sys/dev/pci/if_pcn.c

2066

reg = pcn_bcr_read(sc, LE_BCR2);

sys/dev/pci/if_pcn.c

2067

reg |= LE_B2_ASEL;

sys/dev/pci/if_pcn.c

2068

pcn_bcr_write(sc, LE_BCR2, reg);

sys/dev/pci/if_pcn.c

2073

reg = pcn_bcr_read(sc, LE_BCR2);

sys/dev/pci/if_pcn.c

2074

reg &= ~LE_B2_ASEL;

sys/dev/pci/if_pcn.c

2075

pcn_bcr_write(sc, LE_BCR2, reg);

sys/dev/pci/if_pcn.c

2077

reg = pcn_csr_read(sc, LE_CSR15);

sys/dev/pci/if_pcn.c

2078

reg = (reg & ~LE_C15_PORTSEL(PORTSEL_MASK)) |

sys/dev/pci/if_pcn.c

2080

pcn_csr_write(sc, LE_CSR15, reg);

sys/dev/pci/if_pcn.c

2084

reg = LE_B9_FDEN;

sys/dev/pci/if_pcn.c

2086

reg |= LE_B9_AUIFD;

sys/dev/pci/if_pcn.c

2087

pcn_bcr_write(sc, LE_BCR9, reg);

sys/dev/pci/if_pcn.c

2143

pcn_mii_readreg(device_t self, int phy, int reg, uint16_t *val)

sys/dev/pci/if_pcn.c

2147

pcn_bcr_write(sc, LE_BCR33, reg | (phy << PHYAD_SHIFT));

sys/dev/pci/if_pcn.c

2161

pcn_mii_writereg(device_t self, int phy, int reg, uint16_t val)

sys/dev/pci/if_pcn.c

2165

pcn_bcr_write(sc, LE_BCR33, reg | (phy << PHYAD_SHIFT));

sys/dev/pci/if_pcn.c

463

pcn_csr_read(struct pcn_softc *sc, int reg)

sys/dev/pci/if_pcn.c

466

bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg);

sys/dev/pci/if_pcn.c

471

pcn_csr_write(struct pcn_softc *sc, int reg, uint32_t val)

sys/dev/pci/if_pcn.c

474

bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg);

sys/dev/pci/if_pcn.c

479

pcn_bcr_read(struct pcn_softc *sc, int reg)

sys/dev/pci/if_pcn.c

482

bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg);

sys/dev/pci/if_pcn.c

487

pcn_bcr_write(struct pcn_softc *sc, int reg, uint32_t val)

sys/dev/pci/if_pcn.c

490

bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg);

sys/dev/pci/if_pcn.c

575

uint32_t chipid, reg;

sys/dev/pci/if_pcn.c

796

reg = pcn_bcr_read(sc, LE_BCR25) & 0x00ff;

sys/dev/pci/if_pcn.c

797

if (reg != 0)

sys/dev/pci/if_ral_pci.c

169

pcireg_t memtype, reg;

sys/dev/pci/if_ral_pci.c

199

reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);

sys/dev/pci/if_ral_pci.c

200

reg |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_MEM_ENABLE;

sys/dev/pci/if_ral_pci.c

201

pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, reg);

sys/dev/pci/if_rge.c

163

uint16_t reg;

sys/dev/pci/if_rge.c

1891

uint16_t reg;

sys/dev/pci/if_rge.c

1900

rtl8125_mac_bps[i].reg,

sys/dev/pci/if_rge.c

1904

rtl8125_mac_bps[i].reg, 0);

sys/dev/pci/if_rge.c

1906

if (rtl8125_mac_bps[i].reg < 0xf9f8)

sys/dev/pci/if_rge.c

1908

rtl8125_mac_bps[i].reg, 0);

sys/dev/pci/if_rge.c

1930

rge_write_mac_ocp(sc, rtl8125b_mac_bps[i].reg,

sys/dev/pci/if_rge.c

1956

for (reg = 0xf812; reg <= 0xf9f6; reg += 2)

sys/dev/pci/if_rge.c

1957

rge_write_mac_ocp(sc, reg, 0);

sys/dev/pci/if_rge.c

1978

rtl8125d_2_mac_bps[i].reg,

sys/dev/pci/if_rge.c

1982

rtl8125d_2_mac_bps[i].reg, 0);

sys/dev/pci/if_rge.c

1985

for (reg = 0xf884; reg <= 0xf9f6; reg += 2)

sys/dev/pci/if_rge.c

1986

rge_write_mac_ocp(sc, reg, 0);

sys/dev/pci/if_rge.c

202

pcireg_t reg;

sys/dev/pci/if_rge.c

2149

rge_write_ephy(sc, mac_r25_ephy[i].reg, mac_r25_ephy[i].val);

sys/dev/pci/if_rge.c

2173

rge_write_ephy(sc, mac_r25b_ephy[i].reg, mac_r25b_ephy[i].val);

sys/dev/pci/if_rge.c

2182

rge_r27_write_ephy(sc, mac_r27_ephy[i].reg,

sys/dev/pci/if_rge.c

334

reg = pci_conf_read(pa->pa_pc, pa->pa_tag,

sys/dev/pci/if_rge.c

336

reg &= ~(PCIE_LCSR_ASPM_L0S | PCIE_LCSR_ASPM_L1 |

sys/dev/pci/if_rge.c

3374

mac_r25_mcu[i].reg, mac_r25_mcu[i].val);

sys/dev/pci/if_rge.c

3386

mac_r25b_mcu[i].reg, mac_r25b_mcu[i].val);

sys/dev/pci/if_rge.c

339

reg);

sys/dev/pci/if_rge.c

3390

mac_r25d_1_mcu[i].reg,

sys/dev/pci/if_rge.c

3397

mac_r25d_1_mcu[i].reg,

sys/dev/pci/if_rge.c

3404

mac_r25d_1_mcu[i].reg,

sys/dev/pci/if_rge.c

3409

mac_r25d_2_mcu[i].reg,

sys/dev/pci/if_rge.c

3416

mac_r25d_2_mcu[i].reg,

sys/dev/pci/if_rge.c

3421

mac_r26_1_mcu[i].reg, mac_r26_1_mcu[i].val);

sys/dev/pci/if_rge.c

3427

mac_r26_1_mcu[i].reg, mac_r26_1_mcu[i].val);

sys/dev/pci/if_rge.c

3431

mac_r26_2_mcu[i].reg, mac_r26_2_mcu[i].val);

sys/dev/pci/if_rge.c

3435

mac_r27_mcu[i].reg, mac_r27_mcu[i].val);

sys/dev/pci/if_rge.c

3441

mac_r27_mcu[i].reg, mac_r27_mcu[i].val);

sys/dev/pci/if_rge.c

3475

uint16_t reg;

sys/dev/pci/if_rge.c

3486

for (reg = 0xfc28; reg < 0xfc48; reg += 2)

sys/dev/pci/if_rge.c

3487

rge_write_mac_ocp(sc, reg, 0);

sys/dev/pci/if_rge.c

3726

rge_write_csi(struct rge_softc *sc, uint32_t reg, uint32_t val)

sys/dev/pci/if_rge.c

3731

RGE_WRITE_4(sc, RGE_CSIAR, (reg & RGE_CSIAR_ADDR_MASK) |

sys/dev/pci/if_rge.c

3744

rge_read_csi(struct rge_softc *sc, uint32_t reg)

sys/dev/pci/if_rge.c

3748

RGE_WRITE_4(sc, RGE_CSIAR, (reg & RGE_CSIAR_ADDR_MASK) |

sys/dev/pci/if_rge.c

3763

rge_write_mac_ocp(struct rge_softc *sc, uint16_t reg, uint16_t val)

sys/dev/pci/if_rge.c

3767

tmp = (reg >> 1) << RGE_MACOCP_ADDR_SHIFT;

sys/dev/pci/if_rge.c

3774

rge_read_mac_ocp(struct rge_softc *sc, uint16_t reg)

sys/dev/pci/if_rge.c

3778

val = (reg >> 1) << RGE_MACOCP_ADDR_SHIFT;

sys/dev/pci/if_rge.c

3785

rge_write_ephy(struct rge_softc *sc, uint16_t reg, uint16_t val)

sys/dev/pci/if_rge.c

3790

tmp = (reg & RGE_EPHYAR_ADDR_MASK) << RGE_EPHYAR_ADDR_SHIFT;

sys/dev/pci/if_rge.c

3804

rge_read_ephy(struct rge_softc *sc, uint16_t reg)

sys/dev/pci/if_rge.c

3809

val = (reg & RGE_EPHYAR_ADDR_MASK) << RGE_EPHYAR_ADDR_SHIFT;

sys/dev/pci/if_rge.c

3841

rge_read_sds(struct rge_softc *sc, uint16_t reg)

sys/dev/pci/if_rge.c

3845

RGE_WRITE_2(sc, RGE_SDS_ADDR, reg);

sys/dev/pci/if_rge.c

3855

rge_write_sds(struct rge_softc *sc, uint16_t reg, uint16_t val)

sys/dev/pci/if_rge.c

3858

RGE_WRITE_2(sc, RGE_SDS_ADDR, reg);

sys/dev/pci/if_rge.c

3882

rge_check_ephy_ext_add(struct rge_softc *sc, uint16_t reg)

sys/dev/pci/if_rge.c

3886

val = (reg >> 12);

sys/dev/pci/if_rge.c

3889

return reg & 0x0fff;

sys/dev/pci/if_rge.c

3893

rge_r27_write_ephy(struct rge_softc *sc, uint16_t reg, uint16_t val)

sys/dev/pci/if_rge.c

3895

rge_write_ephy(sc, rge_check_ephy_ext_add(sc, reg), val);

sys/dev/pci/if_rge.c

3899

rge_write_phy(struct rge_softc *sc, uint16_t addr, uint16_t reg, uint16_t val)

sys/dev/pci/if_rge.c

3903

phyaddr = addr ? addr : RGE_PHYBASE + (reg / 8);

sys/dev/pci/if_rge.c

3906

off = addr ? reg : 0x10 + (reg % 8);

sys/dev/pci/if_rge.c

3914

rge_read_phy(struct rge_softc *sc, uint16_t addr, uint16_t reg)

sys/dev/pci/if_rge.c

3918

phyaddr = addr ? addr : RGE_PHYBASE + (reg / 8);

sys/dev/pci/if_rge.c

3921

off = addr ? reg : 0x10 + (reg % 8);

sys/dev/pci/if_rge.c

3929

rge_write_phy_ocp(struct rge_softc *sc, uint16_t reg, uint16_t val)

sys/dev/pci/if_rge.c

3934

tmp = (reg >> 1) << RGE_PHYOCP_ADDR_SHIFT;

sys/dev/pci/if_rge.c

3946

rge_read_phy_ocp(struct rge_softc *sc, uint16_t reg)

sys/dev/pci/if_rge.c

3951

val = (reg >> 1) << RGE_PHYOCP_ADDR_SHIFT;

sys/dev/pci/if_rgereg.h

441

#define RGE_WRITE_4(sc, reg, val) \

sys/dev/pci/if_rgereg.h

442

bus_space_write_4(sc->rge_btag, sc->rge_bhandle, reg, val)

sys/dev/pci/if_rgereg.h

443

#define RGE_WRITE_2(sc, reg, val) \

sys/dev/pci/if_rgereg.h

444

bus_space_write_2(sc->rge_btag, sc->rge_bhandle, reg, val)

sys/dev/pci/if_rgereg.h

445

#define RGE_WRITE_1(sc, reg, val) \

sys/dev/pci/if_rgereg.h

446

bus_space_write_1(sc->rge_btag, sc->rge_bhandle, reg, val)

sys/dev/pci/if_rgereg.h

448

#define RGE_READ_4(sc, reg) \

sys/dev/pci/if_rgereg.h

449

bus_space_read_4(sc->rge_btag, sc->rge_bhandle, reg)

sys/dev/pci/if_rgereg.h

450

#define RGE_READ_2(sc, reg) \

sys/dev/pci/if_rgereg.h

451

bus_space_read_2(sc->rge_btag, sc->rge_bhandle, reg)

sys/dev/pci/if_rgereg.h

452

#define RGE_READ_1(sc, reg) \

sys/dev/pci/if_rgereg.h

453

bus_space_read_1(sc->rge_btag, sc->rge_bhandle, reg)

sys/dev/pci/if_rgereg.h

455

#define RGE_SETBIT_4(sc, reg, val) \

sys/dev/pci/if_rgereg.h

456

RGE_WRITE_4(sc, reg, RGE_READ_4(sc, reg) | (val))

sys/dev/pci/if_rgereg.h

457

#define RGE_SETBIT_2(sc, reg, val) \

sys/dev/pci/if_rgereg.h

458

RGE_WRITE_2(sc, reg, RGE_READ_2(sc, reg) | (val))

sys/dev/pci/if_rgereg.h

459

#define RGE_SETBIT_1(sc, reg, val) \

sys/dev/pci/if_rgereg.h

460

RGE_WRITE_1(sc, reg, RGE_READ_1(sc, reg) | (val))

sys/dev/pci/if_rgereg.h

462

#define RGE_CLRBIT_4(sc, reg, val) \

sys/dev/pci/if_rgereg.h

463

RGE_WRITE_4(sc, reg, RGE_READ_4(sc, reg) & ~(val))

sys/dev/pci/if_rgereg.h

464

#define RGE_CLRBIT_2(sc, reg, val) \

sys/dev/pci/if_rgereg.h

465

RGE_WRITE_2(sc, reg, RGE_READ_2(sc, reg) & ~(val))

sys/dev/pci/if_rgereg.h

466

#define RGE_CLRBIT_1(sc, reg, val) \

sys/dev/pci/if_rgereg.h

467

RGE_WRITE_1(sc, reg, RGE_READ_1(sc, reg) & ~(val))

sys/dev/pci/if_rgereg.h

469

#define RGE_EPHY_SETBIT(sc, reg, val) \

sys/dev/pci/if_rgereg.h

470

rge_write_ephy(sc, reg, rge_read_ephy(sc, reg) | (val))

sys/dev/pci/if_rgereg.h

472

#define RGE_EPHY_CLRBIT(sc, reg, val) \

sys/dev/pci/if_rgereg.h

473

rge_write_ephy(sc, reg, rge_read_ephy(sc, reg) & ~(val))

sys/dev/pci/if_rgereg.h

475

#define RGE_PHY_SETBIT(sc, reg, val) \

sys/dev/pci/if_rgereg.h

476

rge_write_phy_ocp(sc, reg, rge_read_phy_ocp(sc, reg) | (val))

sys/dev/pci/if_rgereg.h

478

#define RGE_PHY_CLRBIT(sc, reg, val) \

sys/dev/pci/if_rgereg.h

479

rge_write_phy_ocp(sc, reg, rge_read_phy_ocp(sc, reg) & ~(val))

sys/dev/pci/if_rgereg.h

481

#define RGE_MAC_SETBIT(sc, reg, val) \

sys/dev/pci/if_rgereg.h

482

rge_write_mac_ocp(sc, reg, rge_read_mac_ocp(sc, reg) | (val))

sys/dev/pci/if_rgereg.h

484

#define RGE_MAC_CLRBIT(sc, reg, val) \

sys/dev/pci/if_rgereg.h

485

rge_write_mac_ocp(sc, reg, rge_read_mac_ocp(sc, reg) & ~(val))

sys/dev/pci/if_rgereg.h

488

uint16_t reg;

sys/dev/pci/if_rgereg.h

944

uint16_t reg;

sys/dev/pci/if_rgereg.h

972

uint16_t reg;

sys/dev/pci/if_rtwn.c

1165

uint32_t reg;

sys/dev/pci/if_rtwn.c

1167

reg = rtwn_read_4(sc, R92C_CR);

sys/dev/pci/if_rtwn.c

1168

reg = RW(reg, R92C_CR_NETTYPE, type);

sys/dev/pci/if_rtwn.c

1169

rtwn_write_4(sc, R92C_CR, reg);

sys/dev/pci/if_rtwn.c

1202

uint8_t reg;

sys/dev/pci/if_rtwn.c

1207

reg = rtwn_read_1(sc, R92C_LEDCFG2) & 0xf0;

sys/dev/pci/if_rtwn.c

1209

reg |= R92C_LEDCFG2_DIS;

sys/dev/pci/if_rtwn.c

1211

reg |= R92C_LEDCFG2_EN;

sys/dev/pci/if_rtwn.c

1212

rtwn_write_1(sc, R92C_LEDCFG2, reg);

sys/dev/pci/if_rtwn.c

1294

uint32_t reg;

sys/dev/pci/if_rtwn.c

1378

reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0));

sys/dev/pci/if_rtwn.c

1379

reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20);

sys/dev/pci/if_rtwn.c

1380

rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg);

sys/dev/pci/if_rtwn.c

1382

reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1));

sys/dev/pci/if_rtwn.c

1383

reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20);

sys/dev/pci/if_rtwn.c

1384

rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg);

sys/dev/pci/if_rtwn.c

1415

reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0));

sys/dev/pci/if_rtwn.c

1417

reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32);

sys/dev/pci/if_rtwn.c

1419

reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20);

sys/dev/pci/if_rtwn.c

1421

rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg);

sys/dev/pci/if_rtwn.c

1423

reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1));

sys/dev/pci/if_rtwn.c

1425

reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32);

sys/dev/pci/if_rtwn.c

1427

reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20);

sys/dev/pci/if_rtwn.c

1429

rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg);

sys/dev/pci/if_rtwn.c

1516

reg = rtwn_read_4(sc, R92C_TCR);

sys/dev/pci/if_rtwn.c

1517

reg &= ~0x01;

sys/dev/pci/if_rtwn.c

1518

rtwn_write_4(sc, R92C_TCR, reg);

sys/dev/pci/if_rtwn.c

1519

reg |= 0x01;

sys/dev/pci/if_rtwn.c

1520

rtwn_write_4(sc, R92C_TCR, reg);

sys/dev/pci/if_rtwn.c

2232

uint32_t reg;

sys/dev/pci/if_rtwn.c

2255

reg = rtwn_read_4(sc, R92C_APS_FSMCO);

sys/dev/pci/if_rtwn.c

2256

reg |= (R92C_APS_FSMCO_SOP_ABG |

sys/dev/pci/if_rtwn.c

2259

rtwn_write_4(sc, R92C_APS_FSMCO, reg);

sys/dev/pci/if_rtwn.c

2273

reg = rtwn_read_4(sc, R92C_AFE_XTAL_CTRL);

sys/dev/pci/if_rtwn.c

2274

reg &= ~0x00024800; /* XXX magic from linux */

sys/dev/pci/if_rtwn.c

2275

rtwn_write_4(sc, R92C_AFE_XTAL_CTRL, reg);

sys/dev/pci/if_rtwn.c

2319

reg = rtwn_read_4(sc, R92C_AFE_XTAL_CTRL + 2);

sys/dev/pci/if_rtwn.c

2320

reg &= 0xfd; /* XXX magic from linux */

sys/dev/pci/if_rtwn.c

2321

rtwn_write_4(sc, R92C_AFE_XTAL_CTRL + 2, reg);

sys/dev/pci/if_rtwn.c

2327

reg = rtwn_read_1(sc, R92C_GPIO_IO_SEL);

sys/dev/pci/if_rtwn.c

2328

if (!(reg & R92C_GPIO_IO_SEL_RFKILL)) {

sys/dev/pci/if_rtwn.c

2335

reg = rtwn_read_1(sc, R92C_APSD_CTRL);

sys/dev/pci/if_rtwn.c

2351

reg = rtwn_read_2(sc, R92C_CR);

sys/dev/pci/if_rtwn.c

2352

reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN |

sys/dev/pci/if_rtwn.c

2356

rtwn_write_2(sc, R92C_CR, reg);

sys/dev/pci/if_rtwn.c

2394

uint16_t reg;

sys/dev/pci/if_rtwn.c

2404

reg = rtwn_read_2(sc, R92C_SYS_FUNC_EN);

sys/dev/pci/if_rtwn.c

2405

if (!(reg & R92C_SYS_FUNC_EN_CPUEN))

sys/dev/pci/if_rtwn.c

2410

rtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN);

sys/dev/pci/if_rtwn.c

2418

tsleep(&reg, 0, "rtwnrst", hz);

sys/dev/pci/if_rtwn.c

2427

uint32_t reg;

sys/dev/pci/if_rtwn.c

2432

reg = rtwn_read_4(sc, R92C_MCUFWDL);

sys/dev/pci/if_rtwn.c

2433

reg = RW(reg, R92C_MCUFWDL_PAGE, page);

sys/dev/pci/if_rtwn.c

2434

rtwn_write_4(sc, R92C_MCUFWDL, reg);

sys/dev/pci/if_rtwn.c

2463

uint32_t reg;

sys/dev/pci/if_rtwn.c

2563

reg = rtwn_read_4(sc, R92C_MCUFWDL);

sys/dev/pci/if_rtwn.c

2564

reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY;

sys/dev/pci/if_rtwn.c

2565

rtwn_write_4(sc, R92C_MCUFWDL, reg);

sys/dev/pci/if_rtwn.c

2589

uint32_t reg;

sys/dev/pci/if_rtwn.c

2617

reg = rtwn_read_2(sc, R92C_TRXDMA_CTRL);

sys/dev/pci/if_rtwn.c

2618

reg &= ~R92C_TRXDMA_CTRL_QMAP_M;

sys/dev/pci/if_rtwn.c

2619

reg |= 0xF771;

sys/dev/pci/if_rtwn.c

2620

rtwn_write_2(sc, R92C_TRXDMA_CTRL, reg);

sys/dev/pci/if_rtwn.c

2662

rtwn_write_1(sc, rtl8192ce_mac[i].reg, rtl8192ce_mac[i].val);

sys/dev/pci/if_rtwn.c

2669

uint32_t reg;

sys/dev/pci/if_rtwn.c

2707

reg = rtwn_bb_read(sc, R92C_FPGA0_TXINFO);

sys/dev/pci/if_rtwn.c

2708

reg = (reg & ~0x00000003) | 0x2;

sys/dev/pci/if_rtwn.c

2709

rtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg);

sys/dev/pci/if_rtwn.c

2711

reg = rtwn_bb_read(sc, R92C_FPGA1_TXINFO);

sys/dev/pci/if_rtwn.c

2712

reg = (reg & ~0x00300033) | 0x00200022;

sys/dev/pci/if_rtwn.c

2713

rtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg);

sys/dev/pci/if_rtwn.c

2715

reg = rtwn_bb_read(sc, R92C_CCK0_AFESETTING);

sys/dev/pci/if_rtwn.c

2716

reg = (reg & ~0xff000000) | 0x45 << 24;

sys/dev/pci/if_rtwn.c

2717

rtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg);

sys/dev/pci/if_rtwn.c

2719

reg = rtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA);

sys/dev/pci/if_rtwn.c

2720

reg = (reg & ~0x000000ff) | 0x23;

sys/dev/pci/if_rtwn.c

2721

rtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg);

sys/dev/pci/if_rtwn.c

2723

reg = rtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1);

sys/dev/pci/if_rtwn.c

2724

reg = (reg & ~0x00000030) | 1 << 4;

sys/dev/pci/if_rtwn.c

2725

rtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg);

sys/dev/pci/if_rtwn.c

2727

reg = rtwn_bb_read(sc, 0xe74);

sys/dev/pci/if_rtwn.c

2728

reg = (reg & ~0x0c000000) | 2 << 26;

sys/dev/pci/if_rtwn.c

2729

rtwn_bb_write(sc, 0xe74, reg);

sys/dev/pci/if_rtwn.c

2730

reg = rtwn_bb_read(sc, 0xe78);

sys/dev/pci/if_rtwn.c

2731

reg = (reg & ~0x0c000000) | 2 << 26;

sys/dev/pci/if_rtwn.c

2732

rtwn_bb_write(sc, 0xe78, reg);

sys/dev/pci/if_rtwn.c

2733

reg = rtwn_bb_read(sc, 0xe7c);

sys/dev/pci/if_rtwn.c

2734

reg = (reg & ~0x0c000000) | 2 << 26;

sys/dev/pci/if_rtwn.c

2735

rtwn_bb_write(sc, 0xe7c, reg);

sys/dev/pci/if_rtwn.c

2736

reg = rtwn_bb_read(sc, 0xe80);

sys/dev/pci/if_rtwn.c

2737

reg = (reg & ~0x0c000000) | 2 << 26;

sys/dev/pci/if_rtwn.c

2738

rtwn_bb_write(sc, 0xe80, reg);

sys/dev/pci/if_rtwn.c

2739

reg = rtwn_bb_read(sc, 0xe88);

sys/dev/pci/if_rtwn.c

2740

reg = (reg & ~0x0c000000) | 2 << 26;

sys/dev/pci/if_rtwn.c

2741

rtwn_bb_write(sc, 0xe88, reg);

sys/dev/pci/if_rtwn.c

2760

uint32_t reg, type;

sys/dev/pci/if_rtwn.c

2780

reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx));

sys/dev/pci/if_rtwn.c

2781

type = (reg >> off) & 0x10;

sys/dev/pci/if_rtwn.c

2784

reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i));

sys/dev/pci/if_rtwn.c

2785

reg |= 0x100000;

sys/dev/pci/if_rtwn.c

2786

rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg);

sys/dev/pci/if_rtwn.c

2789

reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i));

sys/dev/pci/if_rtwn.c

2790

reg |= 0x10;

sys/dev/pci/if_rtwn.c

2791

rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg);

sys/dev/pci/if_rtwn.c

2794

reg = rtwn_bb_read(sc, R92C_HSSI_PARAM2(i));

sys/dev/pci/if_rtwn.c

2795

reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH;

sys/dev/pci/if_rtwn.c

2796

rtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg);

sys/dev/pci/if_rtwn.c

2798

reg = rtwn_bb_read(sc, R92C_HSSI_PARAM2(i));

sys/dev/pci/if_rtwn.c

2799

reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH;

sys/dev/pci/if_rtwn.c

2800

rtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg);

sys/dev/pci/if_rtwn.c

2820

reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx));

sys/dev/pci/if_rtwn.c

2821

reg &= ~(0x10 << off) | (type << off);

sys/dev/pci/if_rtwn.c

2822

rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg);

sys/dev/pci/if_rtwn.c

2848

uint8_t reg;

sys/dev/pci/if_rtwn.c

2862

reg = rtwn_read_1(sc, 0x16);

sys/dev/pci/if_rtwn.c

2863

reg = (reg & ~0xf0) | 0x90;

sys/dev/pci/if_rtwn.c

2864

rtwn_write_1(sc, 0x16, reg);

sys/dev/pci/if_rtwn.c

2916

uint32_t reg;

sys/dev/pci/if_rtwn.c

2922

reg = rtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32);

sys/dev/pci/if_rtwn.c

2923

reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]);

sys/dev/pci/if_rtwn.c

2924

rtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg);

sys/dev/pci/if_rtwn.c

2925

reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11);

sys/dev/pci/if_rtwn.c

2926

reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]);

sys/dev/pci/if_rtwn.c

2927

reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]);

sys/dev/pci/if_rtwn.c

2928

reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]);

sys/dev/pci/if_rtwn.c

2929

rtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg);

sys/dev/pci/if_rtwn.c

2931

reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32);

sys/dev/pci/if_rtwn.c

2932

reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]);

sys/dev/pci/if_rtwn.c

2933

reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]);

sys/dev/pci/if_rtwn.c

2934

reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]);

sys/dev/pci/if_rtwn.c

2935

rtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg);

sys/dev/pci/if_rtwn.c

2936

reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11);

sys/dev/pci/if_rtwn.c

2937

reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]);

sys/dev/pci/if_rtwn.c

2938

rtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg);

sys/dev/pci/if_rtwn.c

3113

uint32_t reg;

sys/dev/pci/if_rtwn.c

3121

reg = rtwn_read_1(sc, R92C_RRSR + 2);

sys/dev/pci/if_rtwn.c

3122

reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5;

sys/dev/pci/if_rtwn.c

3123

rtwn_write_1(sc, R92C_RRSR + 2, reg);

sys/dev/pci/if_rtwn.c

3131

reg = rtwn_bb_read(sc, R92C_CCK0_SYSTEM);

sys/dev/pci/if_rtwn.c

3132

reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4;

sys/dev/pci/if_rtwn.c

3133

rtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg);

sys/dev/pci/if_rtwn.c

3135

reg = rtwn_bb_read(sc, R92C_OFDM1_LSTF);

sys/dev/pci/if_rtwn.c

3136

reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10;

sys/dev/pci/if_rtwn.c

3137

rtwn_bb_write(sc, R92C_OFDM1_LSTF, reg);

sys/dev/pci/if_rtwn.c

3143

reg = rtwn_bb_read(sc, 0x818);

sys/dev/pci/if_rtwn.c

3144

reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26;

sys/dev/pci/if_rtwn.c

3145

rtwn_bb_write(sc, 0x818, reg);

sys/dev/pci/if_rtwn.c

3268

uint32_t reg;

sys/dev/pci/if_rtwn.c

3307

reg = rtwn_read_4(sc, R92C_RRSR);

sys/dev/pci/if_rtwn.c

3308

reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_ALL);

sys/dev/pci/if_rtwn.c

3309

rtwn_write_4(sc, R92C_RRSR, reg);

sys/dev/pci/if_rtwn.c

3356

reg = rtwn_bb_read(sc, R92C_FPGA0_RFMOD);

sys/dev/pci/if_rtwn.c

3357

reg |= R92C_RFMOD_CCK_EN;

sys/dev/pci/if_rtwn.c

3358

rtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg);

sys/dev/pci/if_rtwn.c

3359

reg = rtwn_bb_read(sc, R92C_FPGA0_RFMOD);

sys/dev/pci/if_rtwn.c

3360

reg |= R92C_RFMOD_OFDM_EN;

sys/dev/pci/if_rtwn.c

3361

rtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg);

sys/dev/pci/if_rtwn.c

3432

uint16_t reg;

sys/dev/pci/if_rtwn.c

3457

reg = rtwn_read_1(sc, R92C_SYS_FUNC_EN);

sys/dev/pci/if_rtwn.c

3458

reg |= R92C_SYS_FUNC_EN_BB_GLB_RST;

sys/dev/pci/if_rtwn.c

3459

rtwn_write_1(sc, R92C_SYS_FUNC_EN, reg);

sys/dev/pci/if_rtwn.c

3460

reg &= ~R92C_SYS_FUNC_EN_BB_GLB_RST;

sys/dev/pci/if_rtwn.c

3461

rtwn_write_1(sc, R92C_SYS_FUNC_EN, reg);

sys/dev/pci/if_rtwn.c

3463

reg = rtwn_read_2(sc, R92C_CR);

sys/dev/pci/if_rtwn.c

3464

reg &= ~(R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN |

sys/dev/pci/if_rtwn.c

3468

rtwn_write_2(sc, R92C_CR, reg);

sys/dev/pci/if_rtwn.c

839

uint32_t reg[R92C_MAX_CHAINS], val;

sys/dev/pci/if_rtwn.c

841

reg[0] = rtwn_bb_read(sc, R92C_HSSI_PARAM2(0));

sys/dev/pci/if_rtwn.c

843

reg[chain] = rtwn_bb_read(sc, R92C_HSSI_PARAM2(chain));

sys/dev/pci/if_rtwn.c

846

reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE);

sys/dev/pci/if_rtwn.c

850

RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) |

sys/dev/pci/if_rtwn.c

855

reg[0] | R92C_HSSI_PARAM2_READ_EDGE);

sys/dev/pci/if_rtwn.c

887

uint32_t reg;

sys/dev/pci/if_rtwn.c

890

reg = rtwn_read_4(sc, R92C_EFUSE_CTRL);

sys/dev/pci/if_rtwn.c

891

reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr);

sys/dev/pci/if_rtwn.c

892

reg &= ~R92C_EFUSE_CTRL_VALID;

sys/dev/pci/if_rtwn.c

893

rtwn_write_4(sc, R92C_EFUSE_CTRL, reg);

sys/dev/pci/if_rtwn.c

896

reg = rtwn_read_4(sc, R92C_EFUSE_CTRL);

sys/dev/pci/if_rtwn.c

897

if (reg & R92C_EFUSE_CTRL_VALID)

sys/dev/pci/if_rtwn.c

898

return MS(reg, R92C_EFUSE_CTRL_DATA);

sys/dev/pci/if_rtwn.c

910

uint32_t reg;

sys/dev/pci/if_rtwn.c

919

reg = rtwn_efuse_read_1(sc, addr);

sys/dev/pci/if_rtwn.c

920

if (reg == 0xff)

sys/dev/pci/if_rtwn.c

923

off = reg >> 4;

sys/dev/pci/if_rtwn.c

924

msk = reg & 0xf;

sys/dev/pci/if_rtwn.c

948

uint32_t reg;

sys/dev/pci/if_rtwn.c

950

reg = rtwn_read_2(sc, R92C_SYS_ISO_CTRL);

sys/dev/pci/if_rtwn.c

951

if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) {

sys/dev/pci/if_rtwn.c

953

reg | R92C_SYS_ISO_CTRL_PWC_EV12V);

sys/dev/pci/if_rtwn.c

955

reg = rtwn_read_2(sc, R92C_SYS_FUNC_EN);

sys/dev/pci/if_rtwn.c

956

if (!(reg & R92C_SYS_FUNC_EN_ELDR)) {

sys/dev/pci/if_rtwn.c

958

reg | R92C_SYS_FUNC_EN_ELDR);

sys/dev/pci/if_rtwn.c

960

reg = rtwn_read_2(sc, R92C_SYS_CLKR);

sys/dev/pci/if_rtwn.c

961

if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) !=

sys/dev/pci/if_rtwn.c

964

reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M);

sys/dev/pci/if_rtwn.c

972

uint32_t reg;

sys/dev/pci/if_rtwn.c

976

reg = rtwn_read_4(sc, R92C_SYS_CFG);

sys/dev/pci/if_rtwn.c

977

DPRINTF(("%s: version=0x%08x\n", device_xname(sc->sc_dev), reg));

sys/dev/pci/if_rtwn.c

978

if (reg & R92C_SYS_CFG_TRP_VAUX_EN)

sys/dev/pci/if_rtwn.c

982

if (reg & R92C_SYS_CFG_TYPE_92C) {

sys/dev/pci/if_rtwn.c

990

if (reg & R92C_SYS_CFG_VENDOR_UMC) {

sys/dev/pci/if_rtwn.c

992

if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0)

sys/dev/pci/if_rtwn.c

994

} else if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) != 0) {

sys/dev/pci/if_rtwn.c

995

if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 1)

sys/dev/pci/if_sf_pci.c

176

pcireg_t reg;

sys/dev/pci/if_sf_pci.c

199

reg = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SF_PCI_MEMBA);

sys/dev/pci/if_sf_pci.c

200

switch (reg) {

sys/dev/pci/if_sf_pci.c

204

reg, 0, &memt, &memh, NULL, NULL) == 0);

sys/dev/pci/if_sf_pci.c

211

(reg == (PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT)) ?

sys/dev/pci/if_sip.c

2556

uint32_t reg;

sys/dev/pci/if_sip.c

2564

reg = 0;

sys/dev/pci/if_sip.c

2567

reg |= VRCR_IPEN;

sys/dev/pci/if_sip.c

2569

reg |= VRCR_VTDEN | VRCR_VTREN;

sys/dev/pci/if_sip.c

2570

bus_space_write_4(st, sh, SIP_VRCR, reg);

sys/dev/pci/if_sip.c

2577

reg = 0;

sys/dev/pci/if_sip.c

2580

reg |= VTCR_PPCHK;

sys/dev/pci/if_sip.c

2582

reg |= VTCR_VPPTI;

sys/dev/pci/if_sip.c

2583

bus_space_write_4(st, sh, SIP_VTCR, reg);

sys/dev/pci/if_sip.c

2955

uint16_t reg;

sys/dev/pci/if_sip.c

2960

reg = EROMAR_EECS;

sys/dev/pci/if_sip.c

2961

bus_space_write_4(st, sh, SIP_EROMAR, reg);

sys/dev/pci/if_sip.c

2966

reg |= EROMAR_EEDI;

sys/dev/pci/if_sip.c

2968

reg &= ~EROMAR_EEDI;

sys/dev/pci/if_sip.c

2969

bus_space_write_4(st, sh, SIP_EROMAR, reg);

sys/dev/pci/if_sip.c

2971

reg | EROMAR_EESK);

sys/dev/pci/if_sip.c

2973

bus_space_write_4(st, sh, SIP_EROMAR, reg);

sys/dev/pci/if_sip.c

2980

reg |= EROMAR_EEDI;

sys/dev/pci/if_sip.c

2982

reg &= ~EROMAR_EEDI;

sys/dev/pci/if_sip.c

2983

bus_space_write_4(st, sh, SIP_EROMAR, reg);

sys/dev/pci/if_sip.c

2985

reg | EROMAR_EESK);

sys/dev/pci/if_sip.c

2987

bus_space_write_4(st, sh, SIP_EROMAR, reg);

sys/dev/pci/if_sip.c

2992

reg = EROMAR_EECS;

sys/dev/pci/if_sip.c

2996

reg | EROMAR_EESK);

sys/dev/pci/if_sip.c

3000

bus_space_write_4(st, sh, SIP_EROMAR, reg);

sys/dev/pci/if_sip.c

3342

sipcom_dp83820_mii_readreg(device_t self, int phy, int reg, uint16_t *val)

sys/dev/pci/if_sip.c

3352

switch (reg) {

sys/dev/pci/if_sip.c

3397

return mii_bitbang_readreg(self, &sipcom_mii_bitbang_ops, phy, reg,

sys/dev/pci/if_sip.c

3407

sipcom_dp83820_mii_writereg(device_t self, int phy, int reg, uint16_t val)

sys/dev/pci/if_sip.c

3417

switch (reg) {

sys/dev/pci/if_sip.c

3429

return mii_bitbang_writereg(self, &sipcom_mii_bitbang_ops, phy, reg,

sys/dev/pci/if_sip.c

3530

sipcom_sis900_mii_readreg(device_t self, int phy, int reg, uint16_t *val)

sys/dev/pci/if_sip.c

3541

phy, reg, val);

sys/dev/pci/if_sip.c

3553

(phy << ENPHY_PHYADDR_SHIFT) | (reg << ENPHY_REGADDR_SHIFT) |

sys/dev/pci/if_sip.c

3569

sipcom_sis900_mii_writereg(device_t self, int phy, int reg, uint16_t val)

sys/dev/pci/if_sip.c

3576

phy, reg, val);

sys/dev/pci/if_sip.c

3590

(reg << ENPHY_REGADDR_SHIFT) | ENPHY_ACCESS);

sys/dev/pci/if_sip.c

3661

sipcom_dp83815_mii_readreg(device_t self, int phy, int reg, uint16_t *val)

sys/dev/pci/if_sip.c

3684

data = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg));

sys/dev/pci/if_sip.c

3685

} while (reg == MII_BMSR && data == 0);

sys/dev/pci/if_sip.c

3697

sipcom_dp83815_mii_writereg(device_t self, int phy, int reg, uint16_t val)

sys/dev/pci/if_sip.c

3708

bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg), val);

sys/dev/pci/if_sip.c

3756

uint32_t reg;

sys/dev/pci/if_sip.c

3760

reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4);

sys/dev/pci/if_sip.c

3761

reg &= 0x0fff;

sys/dev/pci/if_sip.c

3762

bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, reg | 0x1000);

sys/dev/pci/if_sip.c

3764

reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00fc);

sys/dev/pci/if_sip.c

3765

reg &= 0x00ff;

sys/dev/pci/if_sip.c

3766

if ((reg & 0x0080) == 0 || (reg >= 0x00d8)) {

sys/dev/pci/if_sip.c

3769

reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4);

sys/dev/pci/if_sip.c

3771

reg | 0x20);

sys/dev/pci/if_sip.c

842

uint32_t reg;

sys/dev/pci/if_sip.c

864

reg = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG);

sys/dev/pci/if_sip.c

865

if (reg & CFG_PCI64_DET) {

sys/dev/pci/if_sip.c

868

if (reg & CFG_DATA64_EN) {

sys/dev/pci/if_sip.c

897

if (reg & CFG_T64ADDR)

sys/dev/pci/if_sip.c

910

if (reg & (CFG_TBI_EN | CFG_EXT_125)) {

sys/dev/pci/if_sip.c

913

if (reg & CFG_EXT_125) {

sys/dev/pci/if_sip.c

918

if (reg & CFG_TBI_EN) {

sys/dev/pci/if_sip.c

926

(reg & CFG_MRM_DIS) != 0)

sys/dev/pci/if_sip.c

929

(reg & CFG_MWI_DIS) != 0)

sys/dev/pci/if_sk.c

2458

while (bhack[i].reg) {

sys/dev/pci/if_sk.c

2460

SK_PHYADDR_BCOM, bhack[i].reg,

sys/dev/pci/if_sk.c

259

sk_win_read_4(struct sk_softc *sc, uint32_t reg)

sys/dev/pci/if_sk.c

262

CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));

sys/dev/pci/if_sk.c

263

return CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg));

sys/dev/pci/if_sk.c

2635

uint16_t reg;

sys/dev/pci/if_sk.c

2646

reg = SK_YU_READ_2(sc_if, YUKON_PAR);

sys/dev/pci/if_sk.c

2647

DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg));

sys/dev/pci/if_sk.c

265

return CSR_READ_4(sc, reg);

sys/dev/pci/if_sk.c

2650

reg |= YU_PAR_MIB_CLR;

sys/dev/pci/if_sk.c

2651

DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg));

sys/dev/pci/if_sk.c

2653

SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);

sys/dev/pci/if_sk.c

2657

reg &= ~YU_PAR_MIB_CLR;

sys/dev/pci/if_sk.c

2658

SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);

sys/dev/pci/if_sk.c

2686

reg = sk_win_read_2(sc_if->sk_softc,

sys/dev/pci/if_sk.c

2688

SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg);

sys/dev/pci/if_sk.c

270

sk_win_read_2(struct sk_softc *sc, uint32_t reg)

sys/dev/pci/if_sk.c

273

CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));

sys/dev/pci/if_sk.c

274

return CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg));

sys/dev/pci/if_sk.c

276

return CSR_READ_2(sc, reg);

sys/dev/pci/if_sk.c

281

sk_win_read_1(struct sk_softc *sc, uint32_t reg)

sys/dev/pci/if_sk.c

284

CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));

sys/dev/pci/if_sk.c

285

return CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg));

sys/dev/pci/if_sk.c

287

return CSR_READ_1(sc, reg);

sys/dev/pci/if_sk.c

2870

uint16_t reg = SK_YU_READ_2(sc_if, YUKON_GPCR);

sys/dev/pci/if_sk.c

2871

reg |= YU_GPCR_TXEN | YU_GPCR_RXEN;

sys/dev/pci/if_sk.c

2874

reg &= ~(YU_GPCR_SPEED | YU_GPCR_DPLX_EN);

sys/dev/pci/if_sk.c

2876

SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg);

sys/dev/pci/if_sk.c

292

sk_win_write_4(struct sk_softc *sc, uint32_t reg, uint32_t x)

sys/dev/pci/if_sk.c

295

CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));

sys/dev/pci/if_sk.c

296

CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), x);

sys/dev/pci/if_sk.c

298

CSR_WRITE_4(sc, reg, x);

sys/dev/pci/if_sk.c

303

sk_win_write_2(struct sk_softc *sc, uint32_t reg, uint16_t x)

sys/dev/pci/if_sk.c

306

CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));

sys/dev/pci/if_sk.c

307

CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), x);

sys/dev/pci/if_sk.c

309

CSR_WRITE_2(sc, reg, x);

sys/dev/pci/if_sk.c

314

sk_win_write_1(struct sk_softc *sc, uint32_t reg, uint8_t x)

sys/dev/pci/if_sk.c

317

CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));

sys/dev/pci/if_sk.c

318

CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), x);

sys/dev/pci/if_sk.c

320

CSR_WRITE_1(sc, reg, x);

sys/dev/pci/if_sk.c

410

sk_xmac_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val)

sys/dev/pci/if_sk.c

420

SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));

sys/dev/pci/if_sk.c

442

sk_xmac_miibus_writereg(device_t dev, int phy, int reg, uint16_t val)

sys/dev/pci/if_sk.c

449

SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));

sys/dev/pci/if_sk.c

496

sk_marv_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val)

sys/dev/pci/if_sk.c

506

phy, reg));

sys/dev/pci/if_sk.c

511

YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ);

sys/dev/pci/if_sk.c

531

phy, reg, *val));

sys/dev/pci/if_sk.c

537

sk_marv_miibus_writereg(device_t dev, int phy, int reg, uint16_t val)

sys/dev/pci/if_sk.c

543

phy, reg, val));

sys/dev/pci/if_sk.c

547

YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE);

sys/dev/pci/if_skreg.h

114

#define SK_WIN(reg) (((reg) & SK_WIN_MASK) / SK_WIN_LEN)

sys/dev/pci/if_skreg.h

117

#define SK_REG(reg) ((reg) & SK_REG_MASK)

sys/dev/pci/if_skreg.h

1425

#define SK_Y2_PCI_REG(reg) ((reg) + SK_Y2_PCI_BASE)

sys/dev/pci/if_skreg.h

144

#define SK_IF_READ_4(sc_if, skip, reg) \

sys/dev/pci/if_skreg.h

1442

#define SK_XMAC_REG(sc, reg) (((reg) * 2) + SK_XMAC1_BASE + \

sys/dev/pci/if_skreg.h

1446

#define SK_XM_READ_4(sc, reg) \

sys/dev/pci/if_skreg.h

1448

SK_XMAC_REG(sc, reg)) & 0xFFFF) | \

sys/dev/pci/if_skreg.h

145

sk_win_read_4(sc_if->sk_softc, reg + \

sys/dev/pci/if_skreg.h

1450

SK_XMAC_REG(sc, reg + 2)) & 0xFFFF) << 16))

sys/dev/pci/if_skreg.h

1452

#define SK_XM_WRITE_4(sc, reg, val) \

sys/dev/pci/if_skreg.h

1453

sk_win_write_2(sc->sk_softc, SK_XMAC_REG(sc, reg), \

sys/dev/pci/if_skreg.h

1455

sk_win_write_2(sc->sk_softc, SK_XMAC_REG(sc, reg + 2), \

sys/dev/pci/if_skreg.h

1458

#define SK_XM_READ_4(sc, reg) \

sys/dev/pci/if_skreg.h

1459

sk_win_read_4(sc->sk_softc, SK_XMAC_REG(sc, reg))

sys/dev/pci/if_skreg.h

1461

#define SK_XM_WRITE_4(sc, reg, val) \

sys/dev/pci/if_skreg.h

1462

sk_win_write_4(sc->sk_softc, SK_XMAC_REG(sc, reg), (val))

sys/dev/pci/if_skreg.h

1465

#define SK_XM_READ_2(sc, reg) \

sys/dev/pci/if_skreg.h

1466

sk_win_read_2(sc->sk_softc, SK_XMAC_REG(sc, reg))

sys/dev/pci/if_skreg.h

1468

#define SK_XM_WRITE_2(sc, reg, val) \

sys/dev/pci/if_skreg.h

1469

sk_win_write_2(sc->sk_softc, SK_XMAC_REG(sc, reg), val)

sys/dev/pci/if_skreg.h

147

#define SK_IF_READ_2(sc_if, skip, reg) \

sys/dev/pci/if_skreg.h

1471

#define SK_XM_SETBIT_4(sc, reg, x) \

sys/dev/pci/if_skreg.h

1472

SK_XM_WRITE_4(sc, reg, (SK_XM_READ_4(sc, reg)) | (x))

sys/dev/pci/if_skreg.h

1474

#define SK_XM_CLRBIT_4(sc, reg, x) \

sys/dev/pci/if_skreg.h

1475

SK_XM_WRITE_4(sc, reg, (SK_XM_READ_4(sc, reg)) & ~(x))

sys/dev/pci/if_skreg.h

1477

#define SK_XM_SETBIT_2(sc, reg, x) \

sys/dev/pci/if_skreg.h

1478

SK_XM_WRITE_2(sc, reg, (SK_XM_READ_2(sc, reg)) | (x))

sys/dev/pci/if_skreg.h

148

sk_win_read_2(sc_if->sk_softc, reg + \

sys/dev/pci/if_skreg.h

1480

#define SK_XM_CLRBIT_2(sc, reg, x) \

sys/dev/pci/if_skreg.h

1481

SK_XM_WRITE_2(sc, reg, (SK_XM_READ_2(sc, reg)) & ~(x))

sys/dev/pci/if_skreg.h

1484

#define SK_YU_REG(sc, reg) \

sys/dev/pci/if_skreg.h

1485

((reg) + SK_MARV1_BASE + \

sys/dev/pci/if_skreg.h

1488

#define SK_YU_READ_4(sc, reg) \

sys/dev/pci/if_skreg.h

1489

sk_win_read_4((sc)->sk_softc, SK_YU_REG((sc), (reg)))

sys/dev/pci/if_skreg.h

1491

#define SK_YU_READ_2(sc, reg) \

sys/dev/pci/if_skreg.h

1492

sk_win_read_2((sc)->sk_softc, SK_YU_REG((sc), (reg)))

sys/dev/pci/if_skreg.h

1494

#define SK_YU_WRITE_4(sc, reg, val) \

sys/dev/pci/if_skreg.h

1495

sk_win_write_4((sc)->sk_softc, SK_YU_REG((sc), (reg)), (val))

sys/dev/pci/if_skreg.h

1497

#define SK_YU_WRITE_2(sc, reg, val) \

sys/dev/pci/if_skreg.h

1498

sk_win_write_2((sc)->sk_softc, SK_YU_REG((sc), (reg)), (val))

sys/dev/pci/if_skreg.h

150

#define SK_IF_READ_1(sc_if, skip, reg) \

sys/dev/pci/if_skreg.h

1500

#define SK_YU_SETBIT_4(sc, reg, x) \

sys/dev/pci/if_skreg.h

1501

SK_YU_WRITE_4(sc, reg, (SK_YU_READ_4(sc, reg)) | (x))

sys/dev/pci/if_skreg.h

1503

#define SK_YU_CLRBIT_4(sc, reg, x) \

sys/dev/pci/if_skreg.h

1504

SK_YU_WRITE_4(sc, reg, (SK_YU_READ_4(sc, reg)) & ~(x))

sys/dev/pci/if_skreg.h

1506

#define SK_YU_SETBIT_2(sc, reg, x) \

sys/dev/pci/if_skreg.h

1507

SK_YU_WRITE_2(sc, reg, (SK_YU_READ_2(sc, reg)) | (x))

sys/dev/pci/if_skreg.h

1509

#define SK_YU_CLRBIT_2(sc, reg, x) \

sys/dev/pci/if_skreg.h

151

sk_win_read_1(sc_if->sk_softc, reg + \

sys/dev/pci/if_skreg.h

1510

SK_YU_WRITE_2(sc, reg, (SK_YU_READ_2(sc, reg)) & ~(x))

sys/dev/pci/if_skreg.h

154

#define SK_IF_WRITE_4(sc_if, skip, reg, val) \

sys/dev/pci/if_skreg.h

156

reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val)

sys/dev/pci/if_skreg.h

157

#define SK_IF_WRITE_2(sc_if, skip, reg, val) \

sys/dev/pci/if_skreg.h

159

reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val)

sys/dev/pci/if_skreg.h

160

#define SK_IF_WRITE_1(sc_if, skip, reg, val) \

sys/dev/pci/if_skreg.h

1604

#define CSR_WRITE_4(sc, reg, val) \

sys/dev/pci/if_skreg.h

1605

bus_space_write_4((sc)->sk_btag, (sc)->sk_bhandle, (reg), (val))

sys/dev/pci/if_skreg.h

1606

#define CSR_WRITE_2(sc, reg, val) \

sys/dev/pci/if_skreg.h

1607

bus_space_write_2((sc)->sk_btag, (sc)->sk_bhandle, (reg), (val))

sys/dev/pci/if_skreg.h

1608

#define CSR_WRITE_1(sc, reg, val) \

sys/dev/pci/if_skreg.h

1609

bus_space_write_1((sc)->sk_btag, (sc)->sk_bhandle, (reg), (val))

sys/dev/pci/if_skreg.h

1611

#define CSR_READ_4(sc, reg) \

sys/dev/pci/if_skreg.h

1612

bus_space_read_4((sc)->sk_btag, (sc)->sk_bhandle, (reg))

sys/dev/pci/if_skreg.h

1613

#define CSR_READ_2(sc, reg) \

sys/dev/pci/if_skreg.h

1614

bus_space_read_2((sc)->sk_btag, (sc)->sk_bhandle, (reg))

sys/dev/pci/if_skreg.h

1615

#define CSR_READ_1(sc, reg) \

sys/dev/pci/if_skreg.h

1616

bus_space_read_1((sc)->sk_btag, (sc)->sk_bhandle, (reg))

sys/dev/pci/if_skreg.h

162

reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val)

sys/dev/pci/if_skreg.h

684

#define SK_PCI_REG(reg) ((reg) + SK_PCI_BASE)

sys/dev/pci/if_skvar.h

174

int reg;

sys/dev/pci/if_ste.c

1667

ste_mii_readreg(device_t self, int phy, int reg, uint16_t *val)

sys/dev/pci/if_ste.c

1674

return mii_bitbang_readreg(self, &ste_mii_bitbang_ops, phy, reg, val);

sys/dev/pci/if_ste.c

1683

ste_mii_writereg(device_t self, int phy, int reg, uint16_t val)

sys/dev/pci/if_ste.c

1690

return mii_bitbang_writereg(self, &ste_mii_bitbang_ops, phy, reg, val);

sys/dev/pci/if_stge.c

1963

stge_mii_readreg(device_t self, int phy, int reg, uint16_t *val)

sys/dev/pci/if_stge.c

1966

return mii_bitbang_readreg(self, &stge_mii_bitbang_ops, phy, reg, val);

sys/dev/pci/if_stge.c

1975

stge_mii_writereg(device_t self, int phy, int reg, uint16_t val)

sys/dev/pci/if_stge.c

1978

return mii_bitbang_writereg(self, &stge_mii_bitbang_ops, phy, reg,

sys/dev/pci/if_stge.c

223

#define CSR_WRITE_4(_sc, reg, val) \

sys/dev/pci/if_stge.c

224

bus_space_write_4((_sc)->sc_st, (_sc)->sc_sh, (reg), (val))

sys/dev/pci/if_stge.c

225

#define CSR_WRITE_2(_sc, reg, val) \

sys/dev/pci/if_stge.c

226

bus_space_write_2((_sc)->sc_st, (_sc)->sc_sh, (reg), (val))

sys/dev/pci/if_stge.c

227

#define CSR_WRITE_1(_sc, reg, val) \

sys/dev/pci/if_stge.c

228

bus_space_write_1((_sc)->sc_st, (_sc)->sc_sh, (reg), (val))

sys/dev/pci/if_stge.c

230

#define CSR_READ_4(_sc, reg) \

sys/dev/pci/if_stge.c

231

bus_space_read_4((_sc)->sc_st, (_sc)->sc_sh, (reg))

sys/dev/pci/if_stge.c

232

#define CSR_READ_2(_sc, reg) \

sys/dev/pci/if_stge.c

233

bus_space_read_2((_sc)->sc_st, (_sc)->sc_sh, (reg))

sys/dev/pci/if_stge.c

234

#define CSR_READ_1(_sc, reg) \

sys/dev/pci/if_stge.c

235

bus_space_read_1((_sc)->sc_st, (_sc)->sc_sh, (reg))

sys/dev/pci/if_tireg.h

963

#define CSR_WRITE_4(sc, reg, val) \

sys/dev/pci/if_tireg.h

964

bus_space_write_stream_4((sc)->ti_btag, (sc)->ti_bhandle, reg, val)

sys/dev/pci/if_tireg.h

966

#define CSR_READ_4(sc, reg) \

sys/dev/pci/if_tireg.h

967

bus_space_read_stream_4((sc)->ti_btag, (sc)->ti_bhandle, reg)

sys/dev/pci/if_tireg.h

969

#define CSR_WRITE_4(sc, reg, val) \

sys/dev/pci/if_tireg.h

970

bus_space_write_4((sc)->ti_btag, (sc)->ti_bhandle, reg, val)

sys/dev/pci/if_tireg.h

972

#define CSR_READ_4(sc, reg) \

sys/dev/pci/if_tireg.h

973

bus_space_read_4((sc)->ti_btag, (sc)->ti_bhandle, reg)

sys/dev/pci/if_tireg.h

976

#define TI_SETBIT(sc, reg, x) \

sys/dev/pci/if_tireg.h

977

CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | (x)))

sys/dev/pci/if_tireg.h

978

#define TI_CLRBIT(sc, reg, x) \

sys/dev/pci/if_tireg.h

979

CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~(x)))

sys/dev/pci/if_tl.c

1484

uint32_t reg;

sys/dev/pci/if_tl.c

1499

reg = tl_intreg_read(sc, TL_INT_STATS_TX);

sys/dev/pci/if_tl.c

1500

if_statadd_ref(ifp, nsr, if_opackets, reg & 0x00ffffff);

sys/dev/pci/if_tl.c

1501

oerr_underr = reg >> 24;

sys/dev/pci/if_tl.c

1503

reg = tl_intreg_read(sc, TL_INT_STATS_RX);

sys/dev/pci/if_tl.c

1504

ierr_overr = reg >> 24;

sys/dev/pci/if_tl.c

1506

reg = tl_intreg_read(sc, TL_INT_STATS_FERR);

sys/dev/pci/if_tl.c

1507

ierr_crc = (reg & TL_FERR_CRC) >> 16;

sys/dev/pci/if_tl.c

1508

ierr_code = (reg & TL_FERR_CODE) >> 24;

sys/dev/pci/if_tl.c

1509

oerr_deferred = (reg & TL_FERR_DEF);

sys/dev/pci/if_tl.c

1511

reg = tl_intreg_read(sc, TL_INT_STATS_COLL);

sys/dev/pci/if_tl.c

1512

oerr_multicoll = (reg & TL_COL_MULTI);

sys/dev/pci/if_tl.c

1513

oerr_coll = (reg & TL_COL_SINGLE) >> 16;

sys/dev/pci/if_tl.c

1515

reg = tl_intreg_read(sc, TL_INT_LERR);

sys/dev/pci/if_tl.c

1516

oerr_exesscoll = (reg & TL_LERR_ECOLL);

sys/dev/pci/if_tl.c

1517

oerr_latecoll = (reg & TL_LERR_LCOLL) >> 8;

sys/dev/pci/if_tl.c

1518

oerr_carrloss = (reg & TL_LERR_CL) >> 16;

sys/dev/pci/if_tl.c

766

tl_intreg_read(tl_softc_t *sc, uint32_t reg)

sys/dev/pci/if_tl.c

769

TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, reg & TL_HOST_DIOADR_MASK);

sys/dev/pci/if_tl.c

774

tl_intreg_read_byte(tl_softc_t *sc, uint32_t reg)

sys/dev/pci/if_tl.c

778

(reg & (~0x07)) & TL_HOST_DIOADR_MASK);

sys/dev/pci/if_tl.c

779

return TL_HR_READ_BYTE(sc, TL_HOST_DIO_DATA + (reg & 0x07));

sys/dev/pci/if_tl.c

783

tl_intreg_write(tl_softc_t *sc, uint32_t reg, uint32_t val)

sys/dev/pci/if_tl.c

786

TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, reg & TL_HOST_DIOADR_MASK);

sys/dev/pci/if_tl.c

791

tl_intreg_write_byte(tl_softc_t *sc, uint32_t reg, uint8_t val)

sys/dev/pci/if_tl.c

795

(reg & (~0x03)) & TL_HOST_DIOADR_MASK);

sys/dev/pci/if_tl.c

796

TL_HR_WRITE_BYTE(sc, TL_HOST_DIO_DATA + (reg & 0x03), val);

sys/dev/pci/if_tl.c

830

tl_mii_read(device_t self, int phy, int reg, uint16_t *val)

sys/dev/pci/if_tl.c

844

tl_mii_sendbits(sc, reg, 5);

sys/dev/pci/if_tl.c

870

tl_mii_write(device_t self, int phy, int reg, uint16_t val)

sys/dev/pci/if_tl.c

882

tl_mii_sendbits(sc, reg, 5);

sys/dev/pci/if_tl.c

896

uint32_t reg;

sys/dev/pci/if_tl.c

906

reg = tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetCmd);

sys/dev/pci/if_tl.c

908

reg |= TL_NETCOMMAND_DUPLEX;

sys/dev/pci/if_tl.c

910

reg &= ~TL_NETCOMMAND_DUPLEX;

sys/dev/pci/if_tl.c

911

tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, reg);

sys/dev/pci/if_tl.c

957

uint8_t reg;

sys/dev/pci/if_tl.c

959

reg = tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio);

sys/dev/pci/if_tl.c

960

reg = (reg & ~(TL_NETSIO_EDATA | TL_NETSIO_ECLOCK)) | bits;

sys/dev/pci/if_tl.c

961

tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, reg);

sys/dev/pci/if_tl.c

968

uint8_t reg;

sys/dev/pci/if_tl.c

970

reg = tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio);

sys/dev/pci/if_tl.c

971

reg = (reg & ~TL_NETSIO_ETXEN) | bits;

sys/dev/pci/if_tl.c

972

tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, reg);

sys/dev/pci/if_tlp_pci.c

1397

uint32_t reg;

sys/dev/pci/if_tlp_pci.c

1442

reg = TULIP_READ(sc, CSR_GPP);

sys/dev/pci/if_tlp_pci.c

1443

if ((~reg & (GPP_SMC9332DST_OK10 |

sys/dev/pci/if_tlp_pci.c

1448

} else if ((reg & GPP_SMC9332DST_OK10) == 0) {

sys/dev/pci/if_tlp_pci.c

364

pcireg_t reg;

sys/dev/pci/if_tlp_pci.c

436

reg = pci_conf_read(pc, pa->pa_tag, 0x80);

sys/dev/pci/if_tlp_pci.c

437

switch (reg) {

sys/dev/pci/if_tlp_pci.c

515

reg = pci_conf_read(pc, pa->pa_tag, TULIP_PCI_CFDA);

sys/dev/pci/if_tlp_pci.c

516

if (reg & (CFDA_SLEEP | CFDA_SNOOZE))

sys/dev/pci/if_tlp_pci.c

518

reg & ~(CFDA_SLEEP | CFDA_SNOOZE));

sys/dev/pci/if_tlvar.h

91

#define TL_HR_READ(sc, reg) \

sys/dev/pci/if_tlvar.h

92

bus_space_read_4(sc->tl_bustag, sc->tl_bushandle, (reg))

sys/dev/pci/if_tlvar.h

93

#define TL_HR_READ_BYTE(sc, reg) \

sys/dev/pci/if_tlvar.h

94

bus_space_read_1(sc->tl_bustag, sc->tl_bushandle, (reg))

sys/dev/pci/if_tlvar.h

95

#define TL_HR_WRITE(sc, reg, data) \

sys/dev/pci/if_tlvar.h

96

bus_space_write_4(sc->tl_bustag, sc->tl_bushandle, (reg), (data))

sys/dev/pci/if_tlvar.h

97

#define TL_HR_WRITE_BYTE(sc, reg, data) \

sys/dev/pci/if_tlvar.h

98

bus_space_write_1(sc->tl_bustag, sc->tl_bushandle, (reg), (data))

sys/dev/pci/if_txpreg.h

627

#define WRITE_REG(sc,reg,val) \

sys/dev/pci/if_txpreg.h

628

bus_space_write_4((sc)->sc_bt, (sc)->sc_bh, reg, val)

sys/dev/pci/if_txpreg.h

629

#define READ_REG(sc,reg) \

sys/dev/pci/if_txpreg.h

630

bus_space_read_4((sc)->sc_bt, (sc)->sc_bh, reg)

sys/dev/pci/if_vge.c

260

#define CSR_WRITE_4(sc, reg, val) \

sys/dev/pci/if_vge.c

261

bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/dev/pci/if_vge.c

262

#define CSR_WRITE_2(sc, reg, val) \

sys/dev/pci/if_vge.c

263

bus_space_write_2((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/dev/pci/if_vge.c

264

#define CSR_WRITE_1(sc, reg, val) \

sys/dev/pci/if_vge.c

265

bus_space_write_1((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))

sys/dev/pci/if_vge.c

267

#define CSR_READ_4(sc, reg) \

sys/dev/pci/if_vge.c

268

bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/dev/pci/if_vge.c

269

#define CSR_READ_2(sc, reg) \

sys/dev/pci/if_vge.c

270

bus_space_read_2((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/dev/pci/if_vge.c

271

#define CSR_READ_1(sc, reg) \

sys/dev/pci/if_vge.c

272

bus_space_read_1((sc)->sc_bst, (sc)->sc_bsh, (reg))

sys/dev/pci/if_vge.c

274

#define CSR_SETBIT_1(sc, reg, x) \

sys/dev/pci/if_vge.c

275

CSR_WRITE_1((sc), (reg), CSR_READ_1((sc), (reg)) | (x))

sys/dev/pci/if_vge.c

276

#define CSR_SETBIT_2(sc, reg, x) \

sys/dev/pci/if_vge.c

277

CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) | (x))

sys/dev/pci/if_vge.c

278

#define CSR_SETBIT_4(sc, reg, x) \

sys/dev/pci/if_vge.c

279

CSR_WRITE_4((sc), (reg), CSR_READ_4((sc), (reg)) | (x))

sys/dev/pci/if_vge.c

281

#define CSR_CLRBIT_1(sc, reg, x) \

sys/dev/pci/if_vge.c

282

CSR_WRITE_1((sc), (reg), CSR_READ_1((sc), (reg)) & ~(x))

sys/dev/pci/if_vge.c

283

#define CSR_CLRBIT_2(sc, reg, x) \

sys/dev/pci/if_vge.c

284

CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) & ~(x))

sys/dev/pci/if_vge.c

285

#define CSR_CLRBIT_4(sc, reg, x) \

sys/dev/pci/if_vge.c

286

CSR_WRITE_4((sc), (reg), CSR_READ_4((sc), (reg)) & ~(x))

sys/dev/pci/if_vge.c

466

vge_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val)

sys/dev/pci/if_vge.c

480

CSR_WRITE_1(sc, VGE_MIIADDR, reg);

sys/dev/pci/if_vge.c

505

vge_miibus_writereg(device_t dev, int phy, int reg, uint16_t val)

sys/dev/pci/if_vge.c

518

CSR_WRITE_1(sc, VGE_MIIADDR, reg);

sys/dev/pci/if_vr.c

1467

uint32_t reg;

sys/dev/pci/if_vr.c

1502

reg = PCI_CONF_READ(PCI_COMMAND_STATUS_REG);

sys/dev/pci/if_vr.c

1503

reg |= PCI_COMMAND_MASTER_ENABLE;

sys/dev/pci/if_vr.c

1504

PCI_CONF_WRITE(PCI_COMMAND_STATUS_REG, reg);

sys/dev/pci/if_vr.c

286

#define CSR_WRITE_4(sc, reg, val) \

sys/dev/pci/if_vr.c

287

bus_space_write_4(sc->vr_bst, sc->vr_bsh, reg, val)

sys/dev/pci/if_vr.c

288

#define CSR_WRITE_2(sc, reg, val) \

sys/dev/pci/if_vr.c

289

bus_space_write_2(sc->vr_bst, sc->vr_bsh, reg, val)

sys/dev/pci/if_vr.c

290

#define CSR_WRITE_1(sc, reg, val) \

sys/dev/pci/if_vr.c

291

bus_space_write_1(sc->vr_bst, sc->vr_bsh, reg, val)

sys/dev/pci/if_vr.c

293

#define CSR_READ_4(sc, reg) \

sys/dev/pci/if_vr.c

294

bus_space_read_4(sc->vr_bst, sc->vr_bsh, reg)

sys/dev/pci/if_vr.c

295

#define CSR_READ_2(sc, reg) \

sys/dev/pci/if_vr.c

296

bus_space_read_2(sc->vr_bst, sc->vr_bsh, reg)

sys/dev/pci/if_vr.c

297

#define CSR_READ_1(sc, reg) \

sys/dev/pci/if_vr.c

298

bus_space_read_1(sc->vr_bst, sc->vr_bsh, reg)

sys/dev/pci/if_vr.c

328

#define VR_SETBIT(sc, reg, x) \

sys/dev/pci/if_vr.c

329

CSR_WRITE_1(sc, reg, \

sys/dev/pci/if_vr.c

330

CSR_READ_1(sc, reg) | (x))

sys/dev/pci/if_vr.c

332

#define VR_CLRBIT(sc, reg, x) \

sys/dev/pci/if_vr.c

333

CSR_WRITE_1(sc, reg, \

sys/dev/pci/if_vr.c

334

CSR_READ_1(sc, reg) & ~(x))

sys/dev/pci/if_vr.c

336

#define VR_SETBIT16(sc, reg, x) \

sys/dev/pci/if_vr.c

337

CSR_WRITE_2(sc, reg, \

sys/dev/pci/if_vr.c

338

CSR_READ_2(sc, reg) | (x))

sys/dev/pci/if_vr.c

340

#define VR_CLRBIT16(sc, reg, x) \

sys/dev/pci/if_vr.c

341

CSR_WRITE_2(sc, reg, \

sys/dev/pci/if_vr.c

342

CSR_READ_2(sc, reg) & ~(x))

sys/dev/pci/if_vr.c

344

#define VR_SETBIT32(sc, reg, x) \

sys/dev/pci/if_vr.c

345

CSR_WRITE_4(sc, reg, \

sys/dev/pci/if_vr.c

346

CSR_READ_4(sc, reg) | (x))

sys/dev/pci/if_vr.c

348

#define VR_CLRBIT32(sc, reg, x) \

sys/dev/pci/if_vr.c

349

CSR_WRITE_4(sc, reg, \

sys/dev/pci/if_vr.c

350

CSR_READ_4(sc, reg) & ~(x))

sys/dev/pci/if_vr.c

390

vr_mii_readreg(device_t self, int phy, int reg, uint16_t *val)

sys/dev/pci/if_vr.c

395

return (mii_bitbang_readreg(self, &vr_mii_bitbang_ops, phy, reg, val));

sys/dev/pci/if_vr.c

402

vr_mii_writereg(device_t self, int phy, int reg, uint16_t val)

sys/dev/pci/if_vr.c

407

return mii_bitbang_writereg(self, &vr_mii_bitbang_ops, phy, reg, val);

sys/dev/pci/if_vte.c

168

pcireg_t reg, csr;

sys/dev/pci/if_vte.c

183

reg = pci_conf_read(pa->pa_pc, pa->pa_tag, VTE_PCI_BMEM);

sys/dev/pci/if_vte.c

184

if (PCI_MAPREG_TYPE(reg) == PCI_MAPREG_TYPE_MEM) {

sys/dev/pci/if_vte.c

190

reg = pci_conf_read(pa->pa_pc, pa->pa_tag, VTE_PCI_BIO);

sys/dev/pci/if_vte.c

191

if (PCI_MAPREG_TYPE(reg) == PCI_MAPREG_TYPE_IO) {

sys/dev/pci/if_vte.c

338

vte_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val)

sys/dev/pci/if_vte.c

344

(phy << MMDIO_PHY_ADDR_SHIFT) | (reg << MMDIO_REG_ADDR_SHIFT));

sys/dev/pci/if_vte.c

352

aprint_error_dev(sc->vte_dev, "phy read timeout : %d\n", reg);

sys/dev/pci/if_vte.c

361

vte_miibus_writereg(device_t dev, int phy, int reg, uint16_t val)

sys/dev/pci/if_vte.c

368

(phy << MMDIO_PHY_ADDR_SHIFT) | (reg << MMDIO_REG_ADDR_SHIFT));

sys/dev/pci/if_vte.c

376

aprint_error_dev(sc->vte_dev, "phy write timeout : %d\n", reg);

sys/dev/pci/if_vtevar.h

154

#define CSR_WRITE_2(_sc, reg, val) \

sys/dev/pci/if_vtevar.h

156

(reg), (val))

sys/dev/pci/if_vtevar.h

157

#define CSR_READ_2(_sc, reg) \

sys/dev/pci/if_vtevar.h

158

bus_space_read_2((_sc)->vte_bustag, (_sc)->vte_bushandle, (reg))

sys/dev/pci/if_wm.c

10410

uint32_t status, reg;

sys/dev/pci/if_wm.c

10658

reg = CSR_READ(sc, WMREG_FEXTNVM4);

sys/dev/pci/if_wm.c

10659

reg &= ~FEXTNVM4_BEACON_DURATION;

sys/dev/pci/if_wm.c

10660

reg |= FEXTNVM4_BEACON_DURATION_8US;

sys/dev/pci/if_wm.c

10661

CSR_WRITE(sc, WMREG_FEXTNVM4, reg);

sys/dev/pci/if_wm.c

10685

reg = CSR_READ(sc, WMREG_FEXTNVM6);

sys/dev/pci/if_wm.c

10687

reg |= FEXTNVM6_K1_OFF_ENABLE;

sys/dev/pci/if_wm.c

10689

reg &= ~FEXTNVM6_K1_OFF_ENABLE;

sys/dev/pci/if_wm.c

10690

CSR_WRITE(sc, WMREG_FEXTNVM6, reg);

sys/dev/pci/if_wm.c

10780

uint32_t pcs_adv, pcs_lpab, reg;

sys/dev/pci/if_wm.c

10787

reg = CSR_READ(sc, WMREG_PCS_LSTS);

sys/dev/pci/if_wm.c

10788

if ((reg & PCS_LSTS_LINKOK) != 0) {

sys/dev/pci/if_wm.c

10804

if ((reg & PCS_LSTS_FDX) != 0)

sys/dev/pci/if_wm.c

10810

reg = CSR_READ(sc, WMREG_PCS_LSTS);

sys/dev/pci/if_wm.c

10811

if ((reg & PCS_LSTS_AN_COMP) == 0) {

sys/dev/pci/if_wm.c

11175

uint32_t reg;

sys/dev/pci/if_wm.c

11178

reg = CSR_READ(sc, WMREG_ICR);

sys/dev/pci/if_wm.c

11182

device_xname(sc->sc_dev), reg));

sys/dev/pci/if_wm.c

11187

if ((reg & ICR_LSC) != 0) {

sys/dev/pci/if_wm.c

11191

if ((reg & ICR_GPI(0)) != 0)

sys/dev/pci/if_wm.c

11202

if (sc->sc_type == WM_T_82574 && ((reg & ICR_RXO) != 0)) {

sys/dev/pci/if_wm.c

11276

uint32_t reg;

sys/dev/pci/if_wm.c

11305

reg = CSR_READ(sc, WMREG_CTRL_EXT);

sys/dev/pci/if_wm.c

11306

reg &= ~((CTRL_EXT_SWDPIO_MASK << CTRL_EXT_SWDPIO_SHIFT) |

sys/dev/pci/if_wm.c

11308

reg |= CTRL_EXT_SWDPIO(4);

sys/dev/pci/if_wm.c

11310

CSR_WRITE(sc, WMREG_CTRL_EXT, reg);

sys/dev/pci/if_wm.c

11314

CSR_WRITE(sc, WMREG_CTRL_EXT, reg | CTRL_EXT_SWDPIN(4));

sys/dev/pci/if_wm.c

11318

sc->sc_ctrl_ext = reg | CTRL_EXT_SWDPIN(4);

sys/dev/pci/if_wm.c

11723

uint32_t reg;

sys/dev/pci/if_wm.c

11734

reg = CSR_READ(sc, WMREG_MDIC);

sys/dev/pci/if_wm.c

11735

phyid = (reg & MDIC_PHY_MASK) >> MDIC_PHY_SHIFT;

sys/dev/pci/if_wm.c

11742

reg = CSR_READ(sc, WMREG_MDICNFG);

sys/dev/pci/if_wm.c

11743

phyid = (reg & MDICNFG_PHY_MASK) >> MDICNFG_PHY_SHIFT;

sys/dev/pci/if_wm.c

11912

uint32_t reg;

sys/dev/pci/if_wm.c

11927

reg = CSR_READ(sc, WMREG_PHPM);

sys/dev/pci/if_wm.c

11928

reg &= ~PHPM_GO_LINK_D;

sys/dev/pci/if_wm.c

11929

CSR_WRITE(sc, WMREG_PHPM, reg);

sys/dev/pci/if_wm.c

12114

wm_gmii_i82543_readreg(device_t dev, int phy, int reg, uint16_t *val)

sys/dev/pci/if_wm.c

12119

wm_i82543_mii_sendbits(sc, reg | (phy << 5) |

sys/dev/pci/if_wm.c

12125

device_xname(dev), phy, reg, *val));

sys/dev/pci/if_wm.c

12136

wm_gmii_i82543_writereg(device_t dev, int phy, int reg, uint16_t val)

sys/dev/pci/if_wm.c

12142

(reg << 18) | (phy << 23) | (MII_COMMAND_WRITE << 28) |

sys/dev/pci/if_wm.c

12154

wm_gmii_mdic_readreg(device_t dev, int phy, int reg, uint16_t *val)

sys/dev/pci/if_wm.c

12161

&& (reg > MII_ADDRMASK)) {

sys/dev/pci/if_wm.c

12163

__func__, sc->sc_phytype, reg);

sys/dev/pci/if_wm.c

12164

reg &= MII_ADDRMASK;

sys/dev/pci/if_wm.c

12168

MDIC_REGADD(reg));

sys/dev/pci/if_wm.c

12180

device_xname(dev), phy, reg));

sys/dev/pci/if_wm.c

12186

device_xname(sc->sc_dev), phy, reg));

sys/dev/pci/if_wm.c

12207

wm_gmii_mdic_writereg(device_t dev, int phy, int reg, uint16_t val)

sys/dev/pci/if_wm.c

12214

&& (reg > MII_ADDRMASK)) {

sys/dev/pci/if_wm.c

12216

__func__, sc->sc_phytype, reg);

sys/dev/pci/if_wm.c

12217

reg &= MII_ADDRMASK;

sys/dev/pci/if_wm.c

12221

MDIC_REGADD(reg) | MDIC_DATA(val));

sys/dev/pci/if_wm.c

12233

device_xname(dev), phy, reg));

sys/dev/pci/if_wm.c

12238

device_xname(dev), phy, reg));

sys/dev/pci/if_wm.c

12258

wm_gmii_i82544_readreg(device_t dev, int phy, int reg, uint16_t *val)

sys/dev/pci/if_wm.c

12269

rv = wm_gmii_i82544_readreg_locked(dev, phy, reg, val);

sys/dev/pci/if_wm.c

12277

wm_gmii_i82544_readreg_locked(device_t dev, int phy, int reg, uint16_t *val)

sys/dev/pci/if_wm.c

12286

if (reg > BME1000_MAX_MULTI_PAGE_REG) {

sys/dev/pci/if_wm.c

12288

IGPHY_PAGE_SELECT, reg);

sys/dev/pci/if_wm.c

12295

if ((reg >> MII_ADDRBITS) != 0)

sys/dev/pci/if_wm.c

12298

__func__, sc->sc_phytype, reg);

sys/dev/pci/if_wm.c

12303

return wm_gmii_mdic_readreg(dev, phy, reg & MII_ADDRMASK, val);

sys/dev/pci/if_wm.c

12312

wm_gmii_i82544_writereg(device_t dev, int phy, int reg, uint16_t val)

sys/dev/pci/if_wm.c

12323

rv = wm_gmii_i82544_writereg_locked(dev, phy, reg & MII_ADDRMASK, val);

sys/dev/pci/if_wm.c

12330

wm_gmii_i82544_writereg_locked(device_t dev, int phy, int reg, uint16_t val)

sys/dev/pci/if_wm.c

12339

if (reg > BME1000_MAX_MULTI_PAGE_REG) {

sys/dev/pci/if_wm.c

12341

IGPHY_PAGE_SELECT, reg);

sys/dev/pci/if_wm.c

12348

if ((reg >> MII_ADDRBITS) != 0)

sys/dev/pci/if_wm.c

12351

__func__, sc->sc_phytype, reg);

sys/dev/pci/if_wm.c

12356

return wm_gmii_mdic_writereg(dev, phy, reg & MII_ADDRMASK, val);

sys/dev/pci/if_wm.c

12367

wm_gmii_i80003_readreg(device_t dev, int phy, int reg, uint16_t *val)

sys/dev/pci/if_wm.c

12383

if ((reg & MII_ADDRMASK) < GG82563_MIN_ALT_REG)

sys/dev/pci/if_wm.c

12392

temp = reg >> GG82563_PAGE_SHIFT;

sys/dev/pci/if_wm.c

12409

rv = wm_gmii_mdic_readreg(dev, phy, reg & MII_ADDRMASK, val);

sys/dev/pci/if_wm.c

12412

rv = wm_gmii_mdic_readreg(dev, phy, reg & MII_ADDRMASK, val);

sys/dev/pci/if_wm.c

12427

wm_gmii_i80003_writereg(device_t dev, int phy, int reg, uint16_t val)

sys/dev/pci/if_wm.c

12442

if ((reg & MII_ADDRMASK) < GG82563_MIN_ALT_REG)

sys/dev/pci/if_wm.c

12451

temp = (uint16_t)reg >> GG82563_PAGE_SHIFT;

sys/dev/pci/if_wm.c

12468

rv = wm_gmii_mdic_writereg(dev, phy, reg & MII_ADDRMASK, val);

sys/dev/pci/if_wm.c

12471

rv = wm_gmii_mdic_writereg(dev, phy, reg & MII_ADDRMASK, val);

sys/dev/pci/if_wm.c

12486

wm_gmii_bm_readreg(device_t dev, int phy, int reg, uint16_t *val)

sys/dev/pci/if_wm.c

12489

uint16_t page = reg >> BME1000_PAGE_SHIFT;

sys/dev/pci/if_wm.c

12499

phy = ((page >= 768) || ((page == 0) && (reg == 25))

sys/dev/pci/if_wm.c

12500

|| (reg == 31)) ? 1 : phy;

sys/dev/pci/if_wm.c

12503

rv = wm_access_phy_wakeup_reg_bm(dev, reg, val, true, false);

sys/dev/pci/if_wm.c

12507

if (reg > BME1000_MAX_MULTI_PAGE_REG) {

sys/dev/pci/if_wm.c

12519

rv = wm_gmii_mdic_readreg(dev, phy, reg & MII_ADDRMASK, val);

sys/dev/pci/if_wm.c

12534

wm_gmii_bm_writereg(device_t dev, int phy, int reg, uint16_t val)

sys/dev/pci/if_wm.c

12537

uint16_t page = reg >> BME1000_PAGE_SHIFT;

sys/dev/pci/if_wm.c

12547

phy = ((page >= 768) || ((page == 0) && (reg == 25))

sys/dev/pci/if_wm.c

12548

|| (reg == 31)) ? 1 : phy;

sys/dev/pci/if_wm.c

12551

rv = wm_access_phy_wakeup_reg_bm(dev, reg, &val, false, false);

sys/dev/pci/if_wm.c

12555

if (reg > BME1000_MAX_MULTI_PAGE_REG) {

sys/dev/pci/if_wm.c

12567

rv = wm_gmii_mdic_writereg(dev, phy, reg & MII_ADDRMASK, val);

sys/dev/pci/if_wm.c

12752

wm_gmii_hv_readreg(device_t dev, int phy, int reg, uint16_t *val)

sys/dev/pci/if_wm.c

12766

rv = wm_gmii_hv_readreg_locked(dev, phy, reg, val);

sys/dev/pci/if_wm.c

12772

wm_gmii_hv_readreg_locked(device_t dev, int phy, int reg, uint16_t *val)

sys/dev/pci/if_wm.c

12774

uint16_t page = BM_PHY_REG_PAGE(reg);

sys/dev/pci/if_wm.c

12775

uint16_t regnum = BM_PHY_REG_NUM(reg);

sys/dev/pci/if_wm.c

12782

return wm_access_phy_wakeup_reg_bm(dev, reg, val, true, false);

sys/dev/pci/if_wm.c

12818

wm_gmii_hv_writereg(device_t dev, int phy, int reg, uint16_t val)

sys/dev/pci/if_wm.c

12832

rv = wm_gmii_hv_writereg_locked(dev, phy, reg, val);

sys/dev/pci/if_wm.c

12839

wm_gmii_hv_writereg_locked(device_t dev, int phy, int reg, uint16_t val)

sys/dev/pci/if_wm.c

12842

uint16_t page = BM_PHY_REG_PAGE(reg);

sys/dev/pci/if_wm.c

12843

uint16_t regnum = BM_PHY_REG_NUM(reg);

sys/dev/pci/if_wm.c

12850

return wm_access_phy_wakeup_reg_bm(dev, reg, &val, false,

sys/dev/pci/if_wm.c

12905

wm_gmii_82580_readreg(device_t dev, int phy, int reg, uint16_t *val)

sys/dev/pci/if_wm.c

12917

if (reg > MII_ADDRMASK) {

sys/dev/pci/if_wm.c

12919

__func__, sc->sc_phytype, reg);

sys/dev/pci/if_wm.c

12920

reg &= MII_ADDRMASK;

sys/dev/pci/if_wm.c

12923

rv = wm_gmii_mdic_readreg(dev, phy, reg, val);

sys/dev/pci/if_wm.c

12937

wm_gmii_82580_writereg(device_t dev, int phy, int reg, uint16_t val)

sys/dev/pci/if_wm.c

12949

if (reg > MII_ADDRMASK) {

sys/dev/pci/if_wm.c

12951

__func__, sc->sc_phytype, reg);

sys/dev/pci/if_wm.c

12952

reg &= MII_ADDRMASK;

sys/dev/pci/if_wm.c

12955

rv = wm_gmii_mdic_writereg(dev, phy, reg, val);

sys/dev/pci/if_wm.c

12969

wm_gmii_gs40g_readreg(device_t dev, int phy, int reg, uint16_t *val)

sys/dev/pci/if_wm.c

12983

page = reg >> GS40G_PAGE_SHIFT;

sys/dev/pci/if_wm.c

12989

offset = reg & GS40G_OFFSET_MASK;

sys/dev/pci/if_wm.c

13005

wm_gmii_gs40g_writereg(device_t dev, int phy, int reg, uint16_t val)

sys/dev/pci/if_wm.c

13019

page = reg >> GS40G_PAGE_SHIFT;

sys/dev/pci/if_wm.c

13025

offset = reg & GS40G_OFFSET_MASK;

sys/dev/pci/if_wm.c

13104

wm_kmrn_readreg(struct wm_softc *sc, int reg, uint16_t *val)

sys/dev/pci/if_wm.c

13118

rv = wm_kmrn_readreg_locked(sc, reg, val);

sys/dev/pci/if_wm.c

13129

wm_kmrn_readreg_locked(struct wm_softc *sc, int reg, uint16_t *val)

sys/dev/pci/if_wm.c

13133

((reg << KUMCTRLSTA_OFFSET_SHIFT) & KUMCTRLSTA_OFFSET) |

sys/dev/pci/if_wm.c

13149

wm_kmrn_writereg(struct wm_softc *sc, int reg, uint16_t val)

sys/dev/pci/if_wm.c

13163

rv = wm_kmrn_writereg_locked(sc, reg, val);

sys/dev/pci/if_wm.c

13174

wm_kmrn_writereg_locked(struct wm_softc *sc, int reg, uint16_t val)

sys/dev/pci/if_wm.c

13178

((reg << KUMCTRLSTA_OFFSET_SHIFT) & KUMCTRLSTA_OFFSET) | val);

sys/dev/pci/if_wm.c

13188

wm_access_emi_reg_locked(device_t dev, int reg, uint16_t *val, bool rd)

sys/dev/pci/if_wm.c

13193

rv = sc->phy.writereg_locked(dev, 2, I82579_EMI_ADDR, reg);

sys/dev/pci/if_wm.c

13205

wm_read_emi_reg_locked(device_t dev, int reg, uint16_t *val)

sys/dev/pci/if_wm.c

13208

return wm_access_emi_reg_locked(dev, reg, val, true);

sys/dev/pci/if_wm.c

13212

wm_write_emi_reg_locked(device_t dev, int reg, uint16_t val)

sys/dev/pci/if_wm.c

13215

return wm_access_emi_reg_locked(dev, reg, &val, false);

sys/dev/pci/if_wm.c

13229

uint32_t reg;

sys/dev/pci/if_wm.c

13235

reg = CSR_READ(sc, WMREG_MDIC);

sys/dev/pci/if_wm.c

13236

ismdio = ((reg & MDIC_DEST) != 0);

sys/dev/pci/if_wm.c

13243

reg = CSR_READ(sc, WMREG_MDICNFG);

sys/dev/pci/if_wm.c

13244

ismdio = ((reg & MDICNFG_DEST) != 0);

sys/dev/pci/if_wm.c

13293

wm_sgmii_readreg(device_t dev, int phy, int reg, uint16_t *val)

sys/dev/pci/if_wm.c

13304

rv = wm_sgmii_readreg_locked(dev, phy, reg, val);

sys/dev/pci/if_wm.c

13311

wm_sgmii_readreg_locked(device_t dev, int phy, int reg, uint16_t *val)

sys/dev/pci/if_wm.c

13317

i2ccmd = (reg << I2CCMD_REG_ADDR_SHIFT)

sys/dev/pci/if_wm.c

13351

wm_sgmii_writereg(device_t dev, int phy, int reg, uint16_t val)

sys/dev/pci/if_wm.c

13362

rv = wm_sgmii_writereg_locked(dev, phy, reg, val);

sys/dev/pci/if_wm.c

13370

wm_sgmii_writereg_locked(device_t dev, int phy, int reg, uint16_t val)

sys/dev/pci/if_wm.c

13380

i2ccmd = (reg << I2CCMD_REG_ADDR_SHIFT)

sys/dev/pci/if_wm.c

13833

uint32_t reg;

sys/dev/pci/if_wm.c

13840

reg = CSR_READ(sc, WMREG_PCS_CFG);

sys/dev/pci/if_wm.c

13841

reg |= PCS_CFG_PCS_EN;

sys/dev/pci/if_wm.c

13842

CSR_WRITE(sc, WMREG_PCS_CFG, reg);

sys/dev/pci/if_wm.c

13845

reg = CSR_READ(sc, WMREG_CTRL_EXT);

sys/dev/pci/if_wm.c

13846

reg &= ~CTRL_EXT_SWDPIN(3);

sys/dev/pci/if_wm.c

13847

CSR_WRITE(sc, WMREG_CTRL_EXT, reg);

sys/dev/pci/if_wm.c

13859

uint32_t ctrl_ext, pcs_lctl, reg;

sys/dev/pci/if_wm.c

13881

reg = CSR_READ(sc, WMREG_CONNSW);

sys/dev/pci/if_wm.c

13882

reg |= CONNSW_ENRGSRC;

sys/dev/pci/if_wm.c

13883

CSR_WRITE(sc, WMREG_CONNSW, reg);

sys/dev/pci/if_wm.c

13922

reg = CSR_READ(sc, WMREG_PCS_ANADV);

sys/dev/pci/if_wm.c

13923

reg &= ~(TXCW_ASYM_PAUSE | TXCW_SYM_PAUSE);

sys/dev/pci/if_wm.c

13924

reg |= TXCW_ASYM_PAUSE | TXCW_SYM_PAUSE;

sys/dev/pci/if_wm.c

13925

CSR_WRITE(sc, WMREG_PCS_ANADV, reg);

sys/dev/pci/if_wm.c

13940

uint32_t pcs_adv, pcs_lpab, reg;

sys/dev/pci/if_wm.c

13946

reg = CSR_READ(sc, WMREG_PCS_LSTS);

sys/dev/pci/if_wm.c

13947

if ((reg & PCS_LSTS_LINKOK) == 0) {

sys/dev/pci/if_wm.c

13965

switch (__SHIFTOUT(reg, PCS_LSTS_SPEED)) {

sys/dev/pci/if_wm.c

13982

if ((reg & PCS_LSTS_FDX) != 0)

sys/dev/pci/if_wm.c

13989

reg = CSR_READ(sc, WMREG_PCS_LSTS);

sys/dev/pci/if_wm.c

13990

if ((reg & PCS_LSTS_AN_COMP) == 0) {

sys/dev/pci/if_wm.c

14034

uint32_t reg;

sys/dev/pci/if_wm.c

14042

reg = CSR_READ(sc, WMREG_PCS_LSTS);

sys/dev/pci/if_wm.c

14043

if ((reg & PCS_LSTS_LINKOK) != 0) {

sys/dev/pci/if_wm.c

14048

if ((reg & PCS_LSTS_FDX) != 0)

sys/dev/pci/if_wm.c

14178

uint32_t reg;

sys/dev/pci/if_wm.c

14181

reg = CSR_READ(sc, WMREG_EECD);

sys/dev/pci/if_wm.c

14185

reg |= EECD_DI;

sys/dev/pci/if_wm.c

14187

reg &= ~EECD_DI;

sys/dev/pci/if_wm.c

14188

CSR_WRITE(sc, WMREG_EECD, reg);

sys/dev/pci/if_wm.c

14191

CSR_WRITE(sc, WMREG_EECD, reg | EECD_SK);

sys/dev/pci/if_wm.c

14194

CSR_WRITE(sc, WMREG_EECD, reg);

sys/dev/pci/if_wm.c

14208

uint32_t reg, val;

sys/dev/pci/if_wm.c

14211

reg = CSR_READ(sc, WMREG_EECD) & ~EECD_DI;

sys/dev/pci/if_wm.c

14215

CSR_WRITE(sc, WMREG_EECD, reg | EECD_SK);

sys/dev/pci/if_wm.c

14220

CSR_WRITE(sc, WMREG_EECD, reg);

sys/dev/pci/if_wm.c

14237

uint32_t reg, val;

sys/dev/pci/if_wm.c

14249

reg = CSR_READ(sc, WMREG_EECD) & ~(EECD_SK | EECD_DI);

sys/dev/pci/if_wm.c

14250

CSR_WRITE(sc, WMREG_EECD, reg);

sys/dev/pci/if_wm.c

14260

reg |= EECD_SK;

sys/dev/pci/if_wm.c

14261

CSR_WRITE(sc, WMREG_EECD, reg);

sys/dev/pci/if_wm.c

14262

reg &= ~EECD_SK;

sys/dev/pci/if_wm.c

14263

CSR_WRITE(sc, WMREG_EECD, reg);

sys/dev/pci/if_wm.c

14270

reg |= EECD_CS;

sys/dev/pci/if_wm.c

14271

CSR_WRITE(sc, WMREG_EECD, reg);

sys/dev/pci/if_wm.c

14286

reg = CSR_READ(sc, WMREG_EECD) & ~EECD_CS;

sys/dev/pci/if_wm.c

14287

CSR_WRITE(sc, WMREG_EECD, reg);

sys/dev/pci/if_wm.c

14306

uint32_t reg;

sys/dev/pci/if_wm.c

14309

reg = CSR_READ(sc, WMREG_EECD);

sys/dev/pci/if_wm.c

14310

sc->sc_nvm_addrbits = (reg & EECD_EE_ABITS) ? 16 : 8;

sys/dev/pci/if_wm.c

14313

size = __SHIFTOUT(reg, EECD_EE_SIZE_EX_MASK);

sys/dev/pci/if_wm.c

14325

reg = data;

sys/dev/pci/if_wm.c

14326

size = __SHIFTOUT(reg, EECD_EE_SIZE_EX_MASK);

sys/dev/pci/if_wm.c

14400

uint32_t reg, val;

sys/dev/pci/if_wm.c

14413

reg = CSR_READ(sc, WMREG_EECD) & ~(EECD_SK | EECD_CS);

sys/dev/pci/if_wm.c

14414

CSR_WRITE(sc, WMREG_EECD, reg);

sys/dev/pci/if_wm.c

14422

CSR_WRITE(sc, WMREG_EECD, reg | EECD_CS);

sys/dev/pci/if_wm.c

14425

CSR_WRITE(sc, WMREG_EECD, reg);

sys/dev/pci/if_wm.c

14442

reg = (CSR_READ(sc, WMREG_EECD) & ~EECD_SK) | EECD_CS;

sys/dev/pci/if_wm.c

14443

CSR_WRITE(sc, WMREG_EECD, reg);

sys/dev/pci/if_wm.c

14458

uint32_t i, reg = 0;

sys/dev/pci/if_wm.c

14462

reg = CSR_READ(sc, rw);

sys/dev/pci/if_wm.c

14464

if (reg & EERD_DONE) {

sys/dev/pci/if_wm.c

15436

uint32_t reg;

sys/dev/pci/if_wm.c

15442

reg = CSR_READ(sc, WMREG_EECD);

sys/dev/pci/if_wm.c

15445

reg |= EECD_EE_REQ;

sys/dev/pci/if_wm.c

15446

CSR_WRITE(sc, WMREG_EECD, reg);

sys/dev/pci/if_wm.c

15450

reg = CSR_READ(sc, WMREG_EECD);

sys/dev/pci/if_wm.c

15451

if (reg & EECD_EE_GNT)

sys/dev/pci/if_wm.c

15455

if ((reg & EECD_EE_GNT) == 0) {

sys/dev/pci/if_wm.c

15458

reg &= ~EECD_EE_REQ;

sys/dev/pci/if_wm.c

15459

CSR_WRITE(sc, WMREG_EECD, reg);

sys/dev/pci/if_wm.c

15495

uint32_t reg;

sys/dev/pci/if_wm.c

15501

reg = CSR_READ(sc, WMREG_EECD);

sys/dev/pci/if_wm.c

15504

reg |= EECD_CS;

sys/dev/pci/if_wm.c

15505

wm_nvm_eec_clock_lower(sc, &reg);

sys/dev/pci/if_wm.c

15508

reg &= ~(EECD_CS | EECD_DI);

sys/dev/pci/if_wm.c

15509

CSR_WRITE(sc, WMREG_EECD, reg);

sys/dev/pci/if_wm.c

15510

wm_nvm_eec_clock_raise(sc, &reg);

sys/dev/pci/if_wm.c

15511

wm_nvm_eec_clock_lower(sc, &reg);

sys/dev/pci/if_wm.c

15514

reg = CSR_READ(sc, WMREG_EECD);

sys/dev/pci/if_wm.c

15515

reg &= ~EECD_EE_REQ;

sys/dev/pci/if_wm.c

15516

CSR_WRITE(sc, WMREG_EECD, reg);

sys/dev/pci/if_wm.c

15895

uint32_t reg;

sys/dev/pci/if_wm.c

15900

reg = CSR_READ(sc, WMREG_EXTCNFCTR);

sys/dev/pci/if_wm.c

15903

reg | EXTCNFCTR_MDIO_SW_OWNERSHIP);

sys/dev/pci/if_wm.c

15904

reg = CSR_READ(sc, WMREG_EXTCNFCTR);

sys/dev/pci/if_wm.c

15905

if ((reg & EXTCNFCTR_MDIO_SW_OWNERSHIP) != 0)

sys/dev/pci/if_wm.c

15924

uint32_t reg;

sys/dev/pci/if_wm.c

15929

reg = CSR_READ(sc, WMREG_EXTCNFCTR);

sys/dev/pci/if_wm.c

15930

reg &= ~EXTCNFCTR_MDIO_SW_OWNERSHIP;

sys/dev/pci/if_wm.c

15931

CSR_WRITE(sc, WMREG_EXTCNFCTR, reg);

sys/dev/pci/if_wm.c

16060

uint32_t reg;

sys/dev/pci/if_wm.c

16077

reg = CSR_READ(sc, WMREG_FWSM);

sys/dev/pci/if_wm.c

16078

if ((reg & FWSM_RSPCIPHY) == 0) {

sys/dev/pci/if_wm.c

16093

reg = CSR_READ(sc, WMREG_MANC);

sys/dev/pci/if_wm.c

16094

if ((reg & MANC_BLK_PHY_RST_ON_IDE) != 0)

sys/dev/pci/if_wm.c

16110

uint32_t reg;

sys/dev/pci/if_wm.c

16116

reg = CSR_READ(sc, WMREG_SWSM);

sys/dev/pci/if_wm.c

16117

CSR_WRITE(sc, WMREG_SWSM, reg | SWSM_DRV_LOAD);

sys/dev/pci/if_wm.c

16119

reg = CSR_READ(sc, WMREG_CTRL_EXT);

sys/dev/pci/if_wm.c

16120

CSR_WRITE(sc, WMREG_CTRL_EXT, reg | CTRL_EXT_DRV_LOAD);

sys/dev/pci/if_wm.c

16127

uint32_t reg;

sys/dev/pci/if_wm.c

16133

reg = CSR_READ(sc, WMREG_SWSM);

sys/dev/pci/if_wm.c

16134

CSR_WRITE(sc, WMREG_SWSM, reg & ~SWSM_DRV_LOAD);

sys/dev/pci/if_wm.c

16136

reg = CSR_READ(sc, WMREG_CTRL_EXT);

sys/dev/pci/if_wm.c

16137

CSR_WRITE(sc, WMREG_CTRL_EXT, reg & ~CTRL_EXT_DRV_LOAD);

sys/dev/pci/if_wm.c

16144

uint32_t reg;

sys/dev/pci/if_wm.c

16152

reg = CSR_READ(sc, WMREG_EXTCNFCTR);

sys/dev/pci/if_wm.c

16155

reg |= EXTCNFCTR_GATE_PHY_CFG;

sys/dev/pci/if_wm.c

16157

reg &= ~EXTCNFCTR_GATE_PHY_CFG;

sys/dev/pci/if_wm.c

16159

CSR_WRITE(sc, WMREG_EXTCNFCTR, reg);

sys/dev/pci/if_wm.c

16165

uint32_t fwsm, reg;

sys/dev/pci/if_wm.c

16201

reg = CSR_READ(sc, WMREG_CTRL_EXT);

sys/dev/pci/if_wm.c

16202

reg |= CTRL_EXT_FORCE_SMBUS;

sys/dev/pci/if_wm.c

16203

CSR_WRITE(sc, WMREG_CTRL_EXT, reg);

sys/dev/pci/if_wm.c

16238

reg = CSR_READ(sc, WMREG_CTRL_EXT);

sys/dev/pci/if_wm.c

16239

reg &= ~CTRL_EXT_FORCE_SMBUS;

sys/dev/pci/if_wm.c

16240

CSR_WRITE(sc, WMREG_CTRL_EXT, reg);

sys/dev/pci/if_wm.c

16391

uint32_t reg;

sys/dev/pci/if_wm.c

16407

reg = CSR_READ(sc, WMREG_H2ME);

sys/dev/pci/if_wm.c

16408

reg &= ~H2ME_ULP;

sys/dev/pci/if_wm.c

16409

reg |= H2ME_ENFORCE_SETTINGS;

sys/dev/pci/if_wm.c

16410

CSR_WRITE(sc, WMREG_H2ME, reg);

sys/dev/pci/if_wm.c

16421

reg = CSR_READ(sc, WMREG_H2ME);

sys/dev/pci/if_wm.c

16422

reg &= ~H2ME_ENFORCE_SETTINGS;

sys/dev/pci/if_wm.c

16423

CSR_WRITE(sc, WMREG_H2ME, reg);

sys/dev/pci/if_wm.c

16460

reg = CSR_READ(sc, WMREG_CTRL_EXT);

sys/dev/pci/if_wm.c

16461

reg &= ~CTRL_EXT_FORCE_SMBUS;

sys/dev/pci/if_wm.c

16462

CSR_WRITE(sc, WMREG_CTRL_EXT, reg);

sys/dev/pci/if_wm.c

16486

reg = CSR_READ(sc, WMREG_FEXTNVM7);

sys/dev/pci/if_wm.c

16487

reg &= ~FEXTNVM7_DIS_SMB_PERST;

sys/dev/pci/if_wm.c

16488

CSR_WRITE(sc, WMREG_FEXTNVM7, reg);

sys/dev/pci/if_wm.c

16587

uint32_t reg;

sys/dev/pci/if_wm.c

16593

reg = CSR_READ(sc, WMREG_PHY_CTRL);

sys/dev/pci/if_wm.c

16594

reg |= PHY_CTRL_GBE_DIS | PHY_CTRL_NOND0A_GBE_DIS;

sys/dev/pci/if_wm.c

16595

CSR_WRITE(sc, WMREG_PHY_CTRL, reg);

sys/dev/pci/if_wm.c

16806

uint32_t reg, pmreg;

sys/dev/pci/if_wm.c

16827

reg = CSR_READ(sc, WMREG_CTRL_EXT);

sys/dev/pci/if_wm.c

16828

reg |= CTRL_EXT_SWDPIN(3);

sys/dev/pci/if_wm.c

16829

CSR_WRITE(sc, WMREG_CTRL_EXT, reg);

sys/dev/pci/if_wm.c

16840

reg = CSR_READ(sc, WMREG_WUFC) | WUFC_MAG;

sys/dev/pci/if_wm.c

16841

reg |= WUFC_MC;

sys/dev/pci/if_wm.c

16879

pcireg_t reg, mask = 0;

sys/dev/pci/if_wm.c

16922

reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag,

sys/dev/pci/if_wm.c

16924

reg &= ~mask;

sys/dev/pci/if_wm.c

16926

sc->sc_pcixe_capoff + PCIE_LCSR, reg);

sys/dev/pci/if_wm.c

16940

uint32_t reg;

sys/dev/pci/if_wm.c

16963

reg = CSR_READ(sc, WMREG_PHPM);

sys/dev/pci/if_wm.c

16964

reg &= ~PHPM_D0A_LPLU;

sys/dev/pci/if_wm.c

16965

CSR_WRITE(sc, WMREG_PHPM, reg);

sys/dev/pci/if_wm.c

16972

reg = CSR_READ(sc, WMREG_PHY_CTRL);

sys/dev/pci/if_wm.c

16973

reg &= ~(PHY_CTRL_GBE_DIS | PHY_CTRL_D0A_LPLU);

sys/dev/pci/if_wm.c

16974

CSR_WRITE(sc, WMREG_PHY_CTRL, reg);

sys/dev/pci/if_wm.c

17145

int i, reg, rv;

sys/dev/pci/if_wm.c

17177

reg = CSR_READ(sc, WMREG_PHY_CTRL);

sys/dev/pci/if_wm.c

17178

reg |= PHY_CTRL_GBE_DIS | PHY_CTRL_NOND0A_GBE_DIS;

sys/dev/pci/if_wm.c

17179

CSR_WRITE(sc, WMREG_PHY_CTRL, reg);

sys/dev/pci/if_wm.c

17706

uint32_t reg;

sys/dev/pci/if_wm.c

17734

reg = CSR_READ(sc, WMREG_FEXTNVM4);

sys/dev/pci/if_wm.c

17735

reg &= ~FEXTNVM4_BEACON_DURATION;

sys/dev/pci/if_wm.c

17736

reg |= FEXTNVM4_BEACON_DURATION_16US;

sys/dev/pci/if_wm.c

17737

CSR_WRITE(sc, WMREG_FEXTNVM4, reg);

sys/dev/pci/if_wm.c

17810

uint16_t reg;

sys/dev/pci/if_wm.c

17812

rv = wm_gmii_hv_readreg_locked(sc->sc_dev, 1, HV_KMRN_MODE_CTRL, &reg);

sys/dev/pci/if_wm.c

17817

reg | HV_KMRN_MDIO_SLOW);

sys/dev/pci/if_wm.c

17905

uint32_t reg;

sys/dev/pci/if_wm.c

17922

reg = CSR_READ(sc, WMREG_MDICNFG);

sys/dev/pci/if_wm.c

17924

reg |= MDICNFG_DEST;

sys/dev/pci/if_wm.c

17926

reg |= MDICNFG_COM_MDIO;

sys/dev/pci/if_wm.c

17927

CSR_WRITE(sc, WMREG_MDICNFG, reg);

sys/dev/pci/if_wm.c

17935

uint32_t reg;

sys/dev/pci/if_wm.c

17988

reg = CSR_READ(sc, WMREG_CTRL_EXT);

sys/dev/pci/if_wm.c

17989

reg &= ~CTRL_EXT_FORCE_SMBUS;

sys/dev/pci/if_wm.c

17990

CSR_WRITE(sc, WMREG_CTRL_EXT, reg);

sys/dev/pci/if_wm.c

17999

uint32_t reg;

sys/dev/pci/if_wm.c

18003

reg = CSR_READ(sc, WMREG_FEXTNVM3);

sys/dev/pci/if_wm.c

18004

reg &= ~FEXTNVM3_PHY_CFG_COUNTER_MASK;

sys/dev/pci/if_wm.c

18005

reg |= FEXTNVM3_PHY_CFG_COUNTER_50MS;

sys/dev/pci/if_wm.c

18006

CSR_WRITE(sc, WMREG_FEXTNVM3, reg);

sys/dev/pci/if_wm.c

18009

reg = CSR_READ(sc, WMREG_CTRL);

sys/dev/pci/if_wm.c

18010

reg |= CTRL_LANPHYPC_OVERRIDE;

sys/dev/pci/if_wm.c

18011

reg &= ~CTRL_LANPHYPC_VALUE;

sys/dev/pci/if_wm.c

18012

CSR_WRITE(sc, WMREG_CTRL, reg);

sys/dev/pci/if_wm.c

18015

reg &= ~CTRL_LANPHYPC_OVERRIDE;

sys/dev/pci/if_wm.c

18016

CSR_WRITE(sc, WMREG_CTRL, reg);

sys/dev/pci/if_wm.c

18036

uint32_t reg = __SHIFTIN(link, LTRV_NONSNOOP_REQ)

sys/dev/pci/if_wm.c

18131

reg |= lat_enc | __SHIFTIN(lat_enc, LTRV_NONSNOOP);

sys/dev/pci/if_wm.c

18132

CSR_WRITE(sc, WMREG_LTRV, reg);

sys/dev/pci/if_wm.c

18135

reg = CSR_READ(sc, WMREG_SVT) & ~SVT_OFF_HWM;

sys/dev/pci/if_wm.c

18136

reg |= obff_hwm;

sys/dev/pci/if_wm.c

18137

CSR_WRITE(sc, WMREG_SVT, reg);

sys/dev/pci/if_wm.c

18140

reg = CSR_READ(sc, WMREG_SVCR);

sys/dev/pci/if_wm.c

18141

reg |= SVCR_OFF_EN | SVCR_OFF_MASKINT;

sys/dev/pci/if_wm.c

18142

CSR_WRITE(sc, WMREG_SVCR, reg);

sys/dev/pci/if_wm.c

18157

uint32_t reg;

sys/dev/pci/if_wm.c

18174

reg = mdicnfg & ~MDICNFG_DEST;

sys/dev/pci/if_wm.c

18175

CSR_WRITE(sc, WMREG_MDICNFG, reg);

sys/dev/pci/if_wm.c

18198

reg = CSR_READ(sc, WMREG_CTRL);

sys/dev/pci/if_wm.c

18199

CSR_WRITE(sc, WMREG_CTRL, reg | CTRL_PHY_RESET);

sys/dev/pci/if_wm.c

18201

reg = CSR_READ(sc, WMREG_CTRL_EXT);

sys/dev/pci/if_wm.c

18202

reg |= CTRL_EXT_PHYPDEN | CTRL_EXT_SDLPE;

sys/dev/pci/if_wm.c

18203

CSR_WRITE(sc, WMREG_CTRL_EXT, reg);

sys/dev/pci/if_wm.c

18206

reg = (INVM_AUTOLOAD << 4) | (tmp_nvmword << 16);

sys/dev/pci/if_wm.c

18207

CSR_WRITE(sc, WMREG_EEARBC_I210, reg);

sys/dev/pci/if_wm.c

18219

reg = (INVM_AUTOLOAD << 4) | (nvmword << 16);

sys/dev/pci/if_wm.c

18220

CSR_WRITE(sc, WMREG_EEARBC_I210, reg);

sys/dev/pci/if_wm.c

18236

uint32_t reg;

sys/dev/pci/if_wm.c

18243

reg = CSR_READ(sc, WMREG_FEXTNVM7);

sys/dev/pci/if_wm.c

18244

reg |= FEXTNVM7_SIDE_CLK_UNGATE;

sys/dev/pci/if_wm.c

18245

CSR_WRITE(sc, WMREG_FEXTNVM7, reg);

sys/dev/pci/if_wm.c

18247

reg = CSR_READ(sc, WMREG_FEXTNVM9);

sys/dev/pci/if_wm.c

18248

reg |= FEXTNVM9_IOSFSB_CLKGATE_DIS | FEXTNVM9_IOSFSB_CLKREQ_DIS;

sys/dev/pci/if_wm.c

18249

CSR_WRITE(sc, WMREG_FEXTNVM9, reg);

sys/dev/pci/if_wm.c

18260

uint32_t reg;

sys/dev/pci/if_wm.c

18262

reg = CSR_READ(sc, WMREG_TDH(wmq->wmq_id));

sys/dev/pci/if_wm.c

18263

node.sysctl_data = ®

sys/dev/pci/if_wm.c

18274

uint32_t reg;

sys/dev/pci/if_wm.c

18276

reg = CSR_READ(sc, WMREG_TDT(wmq->wmq_id));

sys/dev/pci/if_wm.c

18277

node.sysctl_data = ®

sys/dev/pci/if_wm.c

1845

wm_io_read(struct wm_softc *sc, int reg)

sys/dev/pci/if_wm.c

1848

bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0, reg);

sys/dev/pci/if_wm.c

1854

wm_io_write(struct wm_softc *sc, int reg, uint32_t val)

sys/dev/pci/if_wm.c

1857

bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0, reg);

sys/dev/pci/if_wm.c

1862

wm_82575_write_8bit_ctlr_reg(struct wm_softc *sc, uint32_t reg, uint32_t off,

sys/dev/pci/if_wm.c

1870

CSR_WRITE(sc, reg, regval);

sys/dev/pci/if_wm.c

1874

if (CSR_READ(sc, reg) & SCTL_CTL_READY)

sys/dev/pci/if_wm.c

1880

device_xname(sc->sc_dev), reg);

sys/dev/pci/if_wm.c

2032

uint32_t reg;

sys/dev/pci/if_wm.c

2349

reg = CSR_READ(sc, WMREG_STATUS);

sys/dev/pci/if_wm.c

2350

if (reg & STATUS_BUS64)

sys/dev/pci/if_wm.c

2352

if ((reg & STATUS_PCIX_MODE) != 0) {

sys/dev/pci/if_wm.c

2398

switch (reg & STATUS_PCIXSPD_MASK) {

sys/dev/pci/if_wm.c

2411

reg & STATUS_PCIXSPD_MASK);

sys/dev/pci/if_wm.c

2416

sc->sc_bus_speed = (reg & STATUS_PCI66) ? 66 : 33;

sys/dev/pci/if_wm.c

2450

reg = CSR_READ(sc, WMREG_EECD);

sys/dev/pci/if_wm.c

2451

if (reg & EECD_EE_SIZE) {

sys/dev/pci/if_wm.c

2466

reg = CSR_READ(sc, WMREG_EECD);

sys/dev/pci/if_wm.c

2474

if (reg & EECD_EE_TYPE) {

sys/dev/pci/if_wm.c

2482

if ((reg & EECD_EE_ABITS) != 0) {

sys/dev/pci/if_wm.c

2568

reg = ICH8_FLASH_READ32(sc, ICH_FLASH_GFPREG);

sys/dev/pci/if_wm.c

2569

sc->sc_ich8_flash_base = (reg & ICH_GFPREG_BASE_MASK) *

sys/dev/pci/if_wm.c

2572

((reg >> 16) & ICH_GFPREG_BASE_MASK) + 1;

sys/dev/pci/if_wm.c

2573

sc->sc_ich8_flash_bank_size -= (reg & ICH_GFPREG_BASE_MASK);

sys/dev/pci/if_wm.c

2631

reg = CSR_READ(sc, WMREG_SWSM2);

sys/dev/pci/if_wm.c

2632

if ((reg & SWSM2_LOCK) == 0) {

sys/dev/pci/if_wm.c

2633

CSR_WRITE(sc, WMREG_SWSM2, reg | SWSM2_LOCK);

sys/dev/pci/if_wm.c

2648

reg = CSR_READ(sc, WMREG_SWSM);

sys/dev/pci/if_wm.c

2649

if ((reg & SWSM_SMBI) != 0)

sys/dev/pci/if_wm.c

2652

CSR_WRITE(sc, WMREG_SWSM, reg & ~SWSM_SMBI);

sys/dev/pci/if_wm.c

3020

reg = CSR_READ(sc, WMREG_CTRL_EXT);

sys/dev/pci/if_wm.c

3021

link_mode = reg & CTRL_EXT_LINK_MODE_MASK;

sys/dev/pci/if_wm.c

3064

reg &= ~CTRL_EXT_LINK_MODE_MASK;

sys/dev/pci/if_wm.c

3066

reg |= CTRL_EXT_LINK_MODE_SGMII;

sys/dev/pci/if_wm.c

3068

reg |= CTRL_EXT_LINK_MODE_PCIE_SERDES;

sys/dev/pci/if_wm.c

3069

CSR_WRITE(sc, WMREG_CTRL_EXT, reg);

sys/dev/pci/if_wm.c

3078

reg &= ~CTRL_EXT_I2C_ENA;

sys/dev/pci/if_wm.c

3080

reg |= CTRL_EXT_I2C_ENA;

sys/dev/pci/if_wm.c

3082

reg &= ~CTRL_EXT_I2C_ENA;

sys/dev/pci/if_wm.c

3083

CSR_WRITE(sc, WMREG_CTRL_EXT, reg);

sys/dev/pci/if_wm.c

3764

pcireg_t reg;

sys/dev/pci/if_wm.c

3767

reg = CSR_READ(sc, WMREG_WUS);

sys/dev/pci/if_wm.c

3768

if (reg != 0) {

sys/dev/pci/if_wm.c

3769

snprintb(buf, sizeof(buf), WUS_FLAGS, reg);

sys/dev/pci/if_wm.c

4459

uint32_t hash, reg, bit;

sys/dev/pci/if_wm.c

4546

reg = (hash >> 5);

sys/dev/pci/if_wm.c

4554

reg &= 0x1f;

sys/dev/pci/if_wm.c

4556

reg &= 0x7f;

sys/dev/pci/if_wm.c

4559

hash = CSR_READ(sc, mta_reg + (reg << 2));

sys/dev/pci/if_wm.c

4562

if (sc->sc_type == WM_T_82544 && (reg & 1) != 0) {

sys/dev/pci/if_wm.c

4568

bit = CSR_READ(sc, mta_reg + ((reg - 1) << 2));

sys/dev/pci/if_wm.c

4569

CSR_WRITE(sc, mta_reg + (reg << 2), hash);

sys/dev/pci/if_wm.c

4571

CSR_WRITE(sc, mta_reg + ((reg - 1) << 2), bit);

sys/dev/pci/if_wm.c

4574

CSR_WRITE(sc, mta_reg + (reg << 2), hash);

sys/dev/pci/if_wm.c

4692

uint32_t reg = 0;

sys/dev/pci/if_wm.c

4708

reg = CSR_READ(sc, WMREG_STATUS);

sys/dev/pci/if_wm.c

4709

if ((reg & STATUS_LAN_INIT_DONE) != 0)

sys/dev/pci/if_wm.c

4724

reg &= ~STATUS_LAN_INIT_DONE;

sys/dev/pci/if_wm.c

4725

CSR_WRITE(sc, WMREG_STATUS, reg);

sys/dev/pci/if_wm.c

4732

uint32_t reg;

sys/dev/pci/if_wm.c

4801

reg = CSR_READ(sc, WMREG_STATUS);

sys/dev/pci/if_wm.c

4802

if ((reg & STATUS_PHYRA) != 0)

sys/dev/pci/if_wm.c

4803

CSR_WRITE(sc, WMREG_STATUS, reg & ~STATUS_PHYRA);

sys/dev/pci/if_wm.c

4816

uint16_t reg;

sys/dev/pci/if_wm.c

4842

wm_gmii_hv_readreg(dev, 2, BM_PORT_GEN_CFG, &reg);

sys/dev/pci/if_wm.c

4843

reg &= ~BM_WUC_HOST_WU_BIT;

sys/dev/pci/if_wm.c

4844

wm_gmii_hv_writereg(dev, 2, BM_PORT_GEN_CFG, reg);

sys/dev/pci/if_wm.c

4917

uint32_t extcnfctr, sw_cfg_mask, cnf_size, word_addr, i, reg;

sys/dev/pci/if_wm.c

4951

reg = CSR_READ(sc, WMREG_FEXTNVM);

sys/dev/pci/if_wm.c

4952

if ((reg & sw_cfg_mask) == 0)

sys/dev/pci/if_wm.c

4969

reg = CSR_READ(sc, WMREG_EXTCNFSIZE);

sys/dev/pci/if_wm.c

4970

cnf_size = __SHIFTOUT(reg, EXTCNFSIZE_LENGTH);

sys/dev/pci/if_wm.c

4988

reg = CSR_READ(sc, WMREG_LEDCTL);

sys/dev/pci/if_wm.c

4990

(uint16_t)reg);

sys/dev/pci/if_wm.c

5092

uint32_t tarc0, tarc1, reg;

sys/dev/pci/if_wm.c

5102

reg = CSR_READ(sc, WMREG_TXDCTL(0));

sys/dev/pci/if_wm.c

5103

reg |= TXDCTL_COUNT_DESC;

sys/dev/pci/if_wm.c

5104

CSR_WRITE(sc, WMREG_TXDCTL(0), reg);

sys/dev/pci/if_wm.c

5107

reg = CSR_READ(sc, WMREG_TXDCTL(1));

sys/dev/pci/if_wm.c

5108

reg |= TXDCTL_COUNT_DESC;

sys/dev/pci/if_wm.c

5109

CSR_WRITE(sc, WMREG_TXDCTL(1), reg);

sys/dev/pci/if_wm.c

5149

reg = CSR_READ(sc, WMREG_CTRL_EXT);

sys/dev/pci/if_wm.c

5150

reg &= ~CTRL_EXT_DMA_DYN_CLK;

sys/dev/pci/if_wm.c

5151

CSR_WRITE(sc, WMREG_CTRL_EXT, reg);

sys/dev/pci/if_wm.c

5161

reg = CSR_READ(sc, WMREG_CTRL_EXT);

sys/dev/pci/if_wm.c

5162

reg &= ~__BIT(23); /* Clear bit 23 */

sys/dev/pci/if_wm.c

5163

reg |= __BIT(22); /* Set bit 22 */

sys/dev/pci/if_wm.c

5164

CSR_WRITE(sc, WMREG_CTRL_EXT, reg);

sys/dev/pci/if_wm.c

5178

reg = CSR_READ(sc, WMREG_GCR);

sys/dev/pci/if_wm.c

5179

reg |= GCR_L1_ACT_WITHOUT_L0S_RX;

sys/dev/pci/if_wm.c

5180

CSR_WRITE(sc, WMREG_GCR, reg);

sys/dev/pci/if_wm.c

5188

reg = CSR_READ(sc, WMREG_GCR);

sys/dev/pci/if_wm.c

5189

reg |= __BIT(22);

sys/dev/pci/if_wm.c

5190

CSR_WRITE(sc, WMREG_GCR, reg);

sys/dev/pci/if_wm.c

5200

reg = CSR_READ(sc, WMREG_GCR2);

sys/dev/pci/if_wm.c

5201

reg |= __BIT(0);

sys/dev/pci/if_wm.c

5202

CSR_WRITE(sc, WMREG_GCR2, reg);

sys/dev/pci/if_wm.c

5246

reg = CSR_READ(sc, WMREG_CTRL_EXT);

sys/dev/pci/if_wm.c

5247

reg |= __BIT(22); /* Set bit 22 */

sys/dev/pci/if_wm.c

5253

reg |= CTRL_EXT_PHYPDEN;

sys/dev/pci/if_wm.c

5254

CSR_WRITE(sc, WMREG_CTRL_EXT, reg);

sys/dev/pci/if_wm.c

5268

reg = CSR_READ(sc, WMREG_STATUS);

sys/dev/pci/if_wm.c

5269

reg &= ~__BIT(31);

sys/dev/pci/if_wm.c

5270

CSR_WRITE(sc, WMREG_STATUS, reg);

sys/dev/pci/if_wm.c

5276

reg = CSR_READ(sc, WMREG_IOSFPC);

sys/dev/pci/if_wm.c

5277

reg |= RCTL_RDMTS_HEX; /* XXX RTCL bit? */

sys/dev/pci/if_wm.c

5278

CSR_WRITE(sc, WMREG_IOSFPC, reg);

sys/dev/pci/if_wm.c

5285

reg = CSR_READ(sc, WMREG_RFCTL);

sys/dev/pci/if_wm.c

5286

reg |= WMREG_RFCTL_NFSWDIS | WMREG_RFCTL_NFSRDIS;

sys/dev/pci/if_wm.c

5287

CSR_WRITE(sc, WMREG_RFCTL, reg);

sys/dev/pci/if_wm.c

5304

reg = CSR_READ(sc, WMREG_RFCTL);

sys/dev/pci/if_wm.c

5305

reg |= WMREG_RFCTL_NEWIPV6EXDIS |WMREG_RFCTL_IPV6EXDIS;

sys/dev/pci/if_wm.c

5306

CSR_WRITE(sc, WMREG_RFCTL, reg);

sys/dev/pci/if_wm.c

5310

reg = CSR_READ(sc, WMREG_RFCTL);

sys/dev/pci/if_wm.c

5311

reg |= WMREG_RFCTL_EXSTEN;

sys/dev/pci/if_wm.c

5312

CSR_WRITE(sc, WMREG_RFCTL, reg);

sys/dev/pci/if_wm.c

5328

reg = CSR_READ(sc, WMREG_RFCTL);

sys/dev/pci/if_wm.c

5329

reg |= WMREG_RFCTL_IPV6EXDIS;

sys/dev/pci/if_wm.c

5330

CSR_WRITE(sc, WMREG_RFCTL, reg);

sys/dev/pci/if_wm.c

5354

uint32_t reg;

sys/dev/pci/if_wm.c

5369

reg = CSR_READ(sc, WMREG_CTRL);

sys/dev/pci/if_wm.c

5370

CSR_WRITE(sc, WMREG_CTRL, reg | CTRL_PHY_RESET);

sys/dev/pci/if_wm.c

5375

CSR_WRITE(sc, WMREG_CTRL, reg);

sys/dev/pci/if_wm.c

5403

uint32_t reg;

sys/dev/pci/if_wm.c

5412

reg = CSR_READ(sc, WMREG_FEXTNVM11);

sys/dev/pci/if_wm.c

5413

reg |= FEXTNVM11_DIS_MULRFIX;

sys/dev/pci/if_wm.c

5414

CSR_WRITE(sc, WMREG_FEXTNVM11, reg);

sys/dev/pci/if_wm.c

5417

reg = CSR_READ(sc, WMREG_TDLEN(0));

sys/dev/pci/if_wm.c

5418

if (((preg & DESCRING_STATUS_FLUSH_REQ) == 0) || (reg == 0))

sys/dev/pci/if_wm.c

5432

reg = CSR_READ(sc, WMREG_TCTL);

sys/dev/pci/if_wm.c

5433

CSR_WRITE(sc, WMREG_TCTL, reg | TCTL_EN);

sys/dev/pci/if_wm.c

5468

reg = CSR_READ(sc, WMREG_RXDCTL(0));

sys/dev/pci/if_wm.c

5470

reg &= 0xffffc000;

sys/dev/pci/if_wm.c

5476

reg |= (0x1f | (1 << 8) | RXDCTL_GRAN);

sys/dev/pci/if_wm.c

5477

CSR_WRITE(sc, WMREG_RXDCTL(0), reg);

sys/dev/pci/if_wm.c

5496

uint32_t reg;

sys/dev/pci/if_wm.c

5677

reg = CSR_READ(sc, WMREG_CTRL) | CTRL_RST;

sys/dev/pci/if_wm.c

5680

CSR_WRITE(sc, WMREG_CTRL, reg);

sys/dev/pci/if_wm.c

5692

reg = CSR_READ(sc, WMREG_CTRL) | CTRL_RST;

sys/dev/pci/if_wm.c

5703

reg |= CTRL_PHY_RESET;

sys/dev/pci/if_wm.c

5709

CSR_WRITE(sc, WMREG_CTRL, reg);

sys/dev/pci/if_wm.c

5762

reg = CSR_READ(sc, WMREG_FEXTNVM3);

sys/dev/pci/if_wm.c

5763

reg &= ~FEXTNVM3_PHY_CFG_COUNTER_MASK;

sys/dev/pci/if_wm.c

5764

reg |= FEXTNVM3_PHY_CFG_COUNTER_50MS;

sys/dev/pci/if_wm.c

5765

CSR_WRITE(sc, WMREG_FEXTNVM3, reg);

sys/dev/pci/if_wm.c

5778

reg = CSR_READ(sc, WMREG_CTRL_EXT) | CTRL_EXT_EE_RST;

sys/dev/pci/if_wm.c

5779

CSR_WRITE(sc, WMREG_CTRL_EXT, reg);

sys/dev/pci/if_wm.c

5805

reg = CSR_READ(sc, WMREG_CTRL_EXT) | CTRL_EXT_EE_RST;

sys/dev/pci/if_wm.c

5806

CSR_WRITE(sc, WMREG_CTRL_EXT, reg);

sys/dev/pci/if_wm.c

5875

reg = CSR_READ(sc, WMREG_ICR);

sys/dev/pci/if_wm.c

5889

reg = CSR_READ(sc, WMREG_KABGTXD);

sys/dev/pci/if_wm.c

5890

reg |= KABGTXD_BGSQLBIAS;

sys/dev/pci/if_wm.c

5891

CSR_WRITE(sc, WMREG_KABGTXD, reg);

sys/dev/pci/if_wm.c

7033

uint32_t reg, sfp_mask = 0;

sys/dev/pci/if_wm.c

7093

reg = CSR_READ(sc, WMREG_GCR);

sys/dev/pci/if_wm.c

7099

reg |= GCR_NO_SNOOP_ALL;

sys/dev/pci/if_wm.c

7101

reg &= ~GCR_NO_SNOOP_ALL;

sys/dev/pci/if_wm.c

7102

CSR_WRITE(sc, WMREG_GCR, reg);

sys/dev/pci/if_wm.c

7107

reg = CSR_READ(sc, WMREG_FFLT_DBG);

sys/dev/pci/if_wm.c

7108

reg |= (1 << 12);

sys/dev/pci/if_wm.c

7109

CSR_WRITE(sc, WMREG_FFLT_DBG, reg);

sys/dev/pci/if_wm.c

7116

reg = CSR_READ(sc, WMREG_CTRL_EXT);

sys/dev/pci/if_wm.c

7117

reg |= CTRL_EXT_RO_DIS;

sys/dev/pci/if_wm.c

7118

CSR_WRITE(sc, WMREG_CTRL_EXT, reg);

sys/dev/pci/if_wm.c

7241

reg = CSR_READ(sc, WMREG_CTRL_EXT);

sys/dev/pci/if_wm.c

7242

reg &= ~CTRL_EXT_LINK_MODE_MASK;

sys/dev/pci/if_wm.c

7243

CSR_WRITE(sc, WMREG_CTRL_EXT, reg);

sys/dev/pci/if_wm.c

7259

reg = CSR_READ(sc, WMREG_RXCSUM);

sys/dev/pci/if_wm.c

7260

reg &= ~(RXCSUM_IPOFL | RXCSUM_IPV6OFL | RXCSUM_TUOFL);

sys/dev/pci/if_wm.c

7262

reg |= RXCSUM_IPOFL;

sys/dev/pci/if_wm.c

7264

reg |= RXCSUM_IPOFL | RXCSUM_TUOFL;

sys/dev/pci/if_wm.c

7266

reg |= RXCSUM_IPV6OFL | RXCSUM_TUOFL;

sys/dev/pci/if_wm.c

7267

CSR_WRITE(sc, WMREG_RXCSUM, reg);

sys/dev/pci/if_wm.c

7277

reg = CSR_READ(sc, WMREG_CTRL_EXT);

sys/dev/pci/if_wm.c

7278

reg |= CTRL_EXT_PBA | CTRL_EXT_EIAME | CTRL_EXT_NSICR;

sys/dev/pci/if_wm.c

7279

CSR_WRITE(sc, WMREG_CTRL_EXT, reg);

sys/dev/pci/if_wm.c

7293

reg = CSR_READ(sc, WMREG_CTRL_EXT);

sys/dev/pci/if_wm.c

7294

reg |= CTRL_EXT_PBA | CTRL_EXT_EIAME;

sys/dev/pci/if_wm.c

7295

CSR_WRITE(sc, WMREG_CTRL_EXT, reg);

sys/dev/pci/if_wm.c

7303

reg = CSR_READ(sc, WMREG_RFCTL);

sys/dev/pci/if_wm.c

7304

reg |= WMREG_RFCTL_ACKDIS;

sys/dev/pci/if_wm.c

7305

CSR_WRITE(sc, WMREG_RFCTL, reg);

sys/dev/pci/if_wm.c

7392

reg = CSR_READ(sc, WMREG_RXCSUM);

sys/dev/pci/if_wm.c

7393

reg |= RXCSUM_PCSD;

sys/dev/pci/if_wm.c

7394

CSR_WRITE(sc, WMREG_RXCSUM, reg);

sys/dev/pci/if_wm.c

7492

reg = CSR_READ(sc, WMREG_TCTL_EXT);

sys/dev/pci/if_wm.c

7493

reg &= ~TCTL_EXT_GCEX_MASK;

sys/dev/pci/if_wm.c

7494

reg |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX;

sys/dev/pci/if_wm.c

7495

CSR_WRITE(sc, WMREG_TCTL_EXT, reg);

sys/dev/pci/if_wm.c

7557

reg = CSR_READ(sc, WMREG_PBA_ECC);

sys/dev/pci/if_wm.c

7558

reg |= PBA_ECC_CORR_EN;

sys/dev/pci/if_wm.c

7559

CSR_WRITE(sc, WMREG_PBA_ECC, reg);

sys/dev/pci/if_wm.c

7565

reg = CSR_READ(sc, WMREG_PBECCSTS);

sys/dev/pci/if_wm.c

7566

reg |= PBECCSTS_UNCORR_ECC_ENABLE;

sys/dev/pci/if_wm.c

7567

CSR_WRITE(sc, WMREG_PBECCSTS, reg);

sys/dev/pci/if_wm.c

791

#define CSR_READ(sc, reg) \

sys/dev/pci/if_wm.c

792

bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))

sys/dev/pci/if_wm.c

793

#define CSR_WRITE(sc, reg, val) \

sys/dev/pci/if_wm.c

794

bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))

sys/dev/pci/if_wm.c

798

#define ICH8_FLASH_READ32(sc, reg) \

sys/dev/pci/if_wm.c

800

(reg) + sc->sc_flashreg_offset)

sys/dev/pci/if_wm.c

801

#define ICH8_FLASH_WRITE32(sc, reg, data) \

sys/dev/pci/if_wm.c

803

(reg) + sc->sc_flashreg_offset, (data))

sys/dev/pci/if_wm.c

805

#define ICH8_FLASH_READ16(sc, reg) \

sys/dev/pci/if_wm.c

807

(reg) + sc->sc_flashreg_offset)

sys/dev/pci/if_wm.c

808

#define ICH8_FLASH_WRITE16(sc, reg, data) \

sys/dev/pci/if_wm.c

810

(reg) + sc->sc_flashreg_offset, (data))

sys/dev/pci/if_wmreg.h

1613

#define WM_INVM_DATA_REG(reg) (0x12120 + 4*(reg))

sys/dev/pci/if_wpireg.h

721

#define WPI_READ(sc, reg) \

sys/dev/pci/if_wpireg.h

722

bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))

sys/dev/pci/if_wpireg.h

724

#define WPI_WRITE(sc, reg, val) \

sys/dev/pci/if_wpireg.h

725

bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))

sys/dev/pci/if_xge.c

595

uint64_t reg;

sys/dev/pci/if_xge.c

600

reg = PIF_RCSR(ADAPTER_STATUS);

sys/dev/pci/if_xge.c

601

if ((reg & (RMAC_REMOTE_FAULT | RMAC_LOCAL_FAULT)) == 0)

sys/dev/pci/igc/if_igc.c

1086

igc_read_mac_counter(struct igc_hw *hw, bus_size_t reg, bool is64)

sys/dev/pci/igc/if_igc.c

1090

val = IGC_READ_REG(hw, reg);

sys/dev/pci/igc/if_igc.c

1092

val += ((uint64_t)IGC_READ_REG(hw, reg + 4)) << 32;

sys/dev/pci/igc/if_igc.c

1128

bus_size_t regaddr = igc_mac_counters[cnt].reg;

sys/dev/pci/igc/if_igc.c

1187

(void)igc_read_mac_counter(hw, igc_mac_counters[cnt].reg,

sys/dev/pci/igc/if_igc.c

870

uint32_t reg, status;

sys/dev/pci/igc/if_igc.c

873

reg = ~IGC_DMACR_DMAC_EN; /* XXXRO */

sys/dev/pci/igc/if_igc.c

874

IGC_WRITE_REG(hw, IGC_DMACR, reg);

sys/dev/pci/igc/if_igc.c

887

reg = IGC_READ_REG(hw, IGC_FCRTC);

sys/dev/pci/igc/if_igc.c

888

reg &= ~IGC_FCRTC_RTH_COAL_MASK;

sys/dev/pci/igc/if_igc.c

889

reg |= (hwm << IGC_FCRTC_RTH_COAL_SHIFT) & IGC_FCRTC_RTH_COAL_MASK;

sys/dev/pci/igc/if_igc.c

890

IGC_WRITE_REG(hw, IGC_FCRTC, reg);

sys/dev/pci/igc/if_igc.c

895

reg = IGC_READ_REG(hw, IGC_DMACR);

sys/dev/pci/igc/if_igc.c

896

reg &= ~IGC_DMACR_DMACTHR_MASK;

sys/dev/pci/igc/if_igc.c

897

reg |= (dmac << IGC_DMACR_DMACTHR_SHIFT) & IGC_DMACR_DMACTHR_MASK;

sys/dev/pci/igc/if_igc.c

900

reg |= IGC_DMACR_DMAC_EN | IGC_DMACR_DMAC_LX_MASK;

sys/dev/pci/igc/if_igc.c

911

reg |= (sc->dmac * 5) >> 6;

sys/dev/pci/igc/if_igc.c

913

reg |= sc->dmac >> 5;

sys/dev/pci/igc/if_igc.c

915

IGC_WRITE_REG(hw, IGC_DMACR, reg);

sys/dev/pci/igc/if_igc.c

920

reg = IGC_READ_REG(hw, IGC_DMCTLX);

sys/dev/pci/igc/if_igc.c

921

reg |= IGC_DMCTLX_DCFLUSH_DIS;

sys/dev/pci/igc/if_igc.c

930

reg |= 0xA;

sys/dev/pci/igc/if_igc.c

932

reg |= 0x4;

sys/dev/pci/igc/if_igc.c

934

IGC_WRITE_REG(hw, IGC_DMCTLX, reg);

sys/dev/pci/igc/if_igc.c

941

reg = IGC_READ_REG(hw, IGC_PCIEMISC);

sys/dev/pci/igc/if_igc.c

942

reg &= ~IGC_PCIEMISC_LX_DECISION;

sys/dev/pci/igc/if_igc.c

943

IGC_WRITE_REG(hw, IGC_PCIEMISC, reg);

sys/dev/pci/igc/if_igc.h

395

#define IGC_READ_REG(a, reg) \

sys/dev/pci/igc/if_igc.h

397

((struct igc_osdep *)(a)->back)->os_memh, reg)

sys/dev/pci/igc/if_igc.h

398

#define IGC_WRITE_REG(a, reg, value) \

sys/dev/pci/igc/if_igc.h

400

((struct igc_osdep *)(a)->back)->os_memh, reg, value)

sys/dev/pci/igc/if_igc.h

401

#define IGC_READ_REG_ARRAY(a, reg, off) \

sys/dev/pci/igc/if_igc.h

403

((struct igc_osdep *)(a)->back)->os_memh, (reg + ((off) << 2)))

sys/dev/pci/igc/if_igc.h

404

#define IGC_WRITE_REG_ARRAY(a, reg, off, value) \

sys/dev/pci/igc/if_igc.h

407

(reg + ((off) << 2)),value)

sys/dev/pci/igc/igc_defines.h

1160

#define GG82563_REG(page, reg) \

sys/dev/pci/igc/igc_defines.h

1161

(((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))

sys/dev/pci/igc/igc_evcnt.h

165

bus_size_t reg;

sys/dev/pci/igc/igc_i225.c

871

uint32_t i, reg;

sys/dev/pci/igc/igc_i225.c

877

reg = IGC_READ_REG(hw, IGC_EECD);

sys/dev/pci/igc/igc_i225.c

878

if (reg & IGC_EECD_FLUDONE_I225) {

sys/dev/pci/igc/igc_nvm.c

111

uint32_t i, reg = 0;

sys/dev/pci/igc/igc_nvm.c

117

reg = IGC_READ_REG(hw, IGC_EERD);

sys/dev/pci/igc/igc_nvm.c

119

reg = IGC_READ_REG(hw, IGC_EEWR);

sys/dev/pci/igc/igc_nvm.c

121

if (reg & IGC_NVM_RW_REG_DONE)

sys/dev/pci/igma.c

300

u_int32_t reg;

sys/dev/pci/igma.c

302

reg = co->read_reg(cd, cd->vga_cntrl);

sys/dev/pci/igma.c

303

if (reg & VGA_PIPE_B_SELECT)

sys/dev/pci/igma.c

518

uint32_t reg;

sys/dev/pci/igma.c

520

reg = co->read_reg(cd, ii->ii_reg);

sys/dev/pci/igma.c

521

reg &= GPIO_DATA_PULLUP_DISABLE | GPIO_CLOCK_PULLUP_DISABLE;

sys/dev/pci/igma.c

525

reg |= GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK;

sys/dev/pci/igma.c

528

reg |= GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK

sys/dev/pci/igma.c

533

reg |= GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK;

sys/dev/pci/igma.c

536

reg |= GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK

sys/dev/pci/igma.c

539

co->write_reg(cd, ii->ii_reg, reg);

sys/dev/pci/igma.c

541

reg = co->read_reg(cd, ii->ii_reg);

sys/dev/pci/igma.c

562

uint32_t reg;

sys/dev/pci/igma.c

565

reg = co->read_reg(cd, ii->ii_reg);

sys/dev/pci/igma.c

567

sda = reg & GPIO_DATA_VAL_IN;

sys/dev/pci/igma.c

568

scl = reg & GPIO_CLOCK_VAL_IN;

sys/dev/pci/igma.c

570

reg = (sda ? 1 : 0) | (scl ? 2 : 0);

sys/dev/pci/igma.c

571

return reg;

sys/dev/pci/iop_pci.c

100

if (PCI_VENDOR(reg) == PCI_VENDOR_PROMISE)

sys/dev/pci/iop_pci.c

115

pcireg_t reg;

sys/dev/pci/iop_pci.c

130

reg = pci_conf_read(pc, pa->pa_tag, i);

sys/dev/pci/iop_pci.c

131

if (PCI_MAPREG_TYPE(reg) == PCI_MAPREG_TYPE_MEM) {

sys/dev/pci/iop_pci.c

132

sc->sc_memaddr = PCI_MAPREG_MEM_ADDR(reg);

sys/dev/pci/iop_pci.c

159

reg = pci_conf_read(pc, pa->pa_tag, PCI_SUBSYS_ID_REG);

sys/dev/pci/iop_pci.c

160

printf("subid %x, %x\n", PCI_VENDOR(reg), PCI_PRODUCT(reg));

sys/dev/pci/iop_pci.c

181

reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);

sys/dev/pci/iop_pci.c

183

reg | PCI_COMMAND_MASTER_ENABLE);

sys/dev/pci/iop_pci.c

71

pcireg_t reg;

sys/dev/pci/iop_pci.c

99

reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG);

sys/dev/pci/ips.c

1814

u_int32_t reg;

sys/dev/pci/ips.c

1818

reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, IPS_REG_CCC);

sys/dev/pci/ips.c

1819

if ((reg & IPS_REG_CCC_SEM) == 0)

sys/dev/pci/ips.c

1841

u_int8_t reg;

sys/dev/pci/ips.c

1843

reg = bus_space_read_1(sc->sc_iot, sc->sc_ioh, IPS_REG_HIS);

sys/dev/pci/ips.c

1844

bus_space_write_1(sc->sc_iot, sc->sc_ioh, IPS_REG_HIS, reg);

sys/dev/pci/ips.c

1845

if (reg != 0xff && (reg & IPS_REG_HIS_SCE))

sys/dev/pci/ips.c

1884

u_int32_t reg;

sys/dev/pci/ips.c

1886

reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, IPS_REG_OIM);

sys/dev/pci/ips.c

1887

reg &= ~IPS_REG_OIM_DS;

sys/dev/pci/ips.c

1888

bus_space_write_4(sc->sc_iot, sc->sc_ioh, IPS_REG_OIM, reg);

sys/dev/pci/ips.c

1901

u_int32_t reg;

sys/dev/pci/ips.c

1903

reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, IPS_REG_OQP);

sys/dev/pci/ips.c

1905

reg));

sys/dev/pci/ips.c

1907

return (reg);

sys/dev/pci/ismt.c

664

pcireg_t reg;

sys/dev/pci/ismt.c

672

reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG);

sys/dev/pci/ismt.c

673

reg |= PCI_COMMAND_MASTER_ENABLE;

sys/dev/pci/ismt.c

674

pci_conf_write(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, reg);

sys/dev/pci/ixgbe/ixgbe.c

3333

uint32_t reg, usec, rate;

sys/dev/pci/ixgbe/ixgbe.c

3343

reg = IXGBE_READ_REG(&sc->hw, IXGBE_EITR(que->msix));

sys/dev/pci/ixgbe/ixgbe.c

3344

usec = ((reg & 0x0FF8) >> 3);

sys/dev/pci/ixgbe/ixgbe.c

3353

reg &= ~0xfff; /* default, no limitation */

sys/dev/pci/ixgbe/ixgbe.c

3357

reg |= ((4000000 / rate) & 0xff8);

sys/dev/pci/ixgbe/ixgbe.c

3367

&& (reg < IXGBE_MIN_RSC_EITR_10G1G))

sys/dev/pci/ixgbe/ixgbe.c

3373

ixgbe_eitr_write(sc, que->msix, reg);

sys/dev/pci/ixgbe/ixgbe.c

589

u32 reg;

sys/dev/pci/ixgbe/ixgbe.c

5923

u32 reg;

sys/dev/pci/ixgbe/ixgbe.c

5951

reg = IXGBE_READ_REG(hw, IXGBE_RETA(i));

sys/dev/pci/ixgbe/ixgbe.c

5952

sbuf_printf(buf, "RETA(%2d): 0x%08x\n", i, reg);

sys/dev/pci/ixgbe/ixgbe.c

5954

reg = IXGBE_READ_REG(hw, IXGBE_ERETA(i - 32));

sys/dev/pci/ixgbe/ixgbe.c

5955

sbuf_printf(buf, "ERETA(%2d): 0x%08x\n", i - 32, reg);

sys/dev/pci/ixgbe/ixgbe.c

5983

u16 reg;

sys/dev/pci/ixgbe/ixgbe.c

5997

IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &reg)) {

sys/dev/pci/ixgbe/ixgbe.c

6006

val = reg >> 8;

sys/dev/pci/ixgbe/ixgbe.c

6028

u16 reg;

sys/dev/pci/ixgbe/ixgbe.c

6041

IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &reg)) {

sys/dev/pci/ixgbe/ixgbe.c

6050

val = !!(reg & 0x4000);

sys/dev/pci/ixgbe/ixgbe.c

609

reg = IXGBE_READ_REG(hw, IXGBE_RQSMR(regnum));

sys/dev/pci/ixgbe/ixgbe.c

610

reg &= ~(0x000000ffUL << (regshift * 8));

sys/dev/pci/ixgbe/ixgbe.c

611

reg |= i << (regshift * 8);

sys/dev/pci/ixgbe/ixgbe.c

612

IXGBE_WRITE_REG(hw, IXGBE_RQSMR(regnum), reg);

sys/dev/pci/ixgbe/ixgbe.c

6662

ixgbe_check_fan_failure(struct ixgbe_softc *sc, u32 reg, bool in_interrupt)

sys/dev/pci/ixgbe/ixgbe.c

6669

if ((reg & mask) == 0)

sys/dev/pci/ixgbe/ixgbe.c

680

u32 tqsmreg, reg;

sys/dev/pci/ixgbe/ixgbe.c

699

reg = IXGBE_READ_REG(hw, tqsmreg);

sys/dev/pci/ixgbe/ixgbe.c

700

reg &= ~(0x000000ffUL << (regshift * 8));

sys/dev/pci/ixgbe/ixgbe.c

701

reg |= i << (regshift * 8);

sys/dev/pci/ixgbe/ixgbe.c

702

IXGBE_WRITE_REG(hw, tqsmreg, reg);

sys/dev/pci/ixgbe/ixgbe_82598.c

1084

s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val)

sys/dev/pci/ixgbe/ixgbe_82598.c

1091

IXGBE_ATLASCTL_WRITE_CMD | (reg << 8));

sys/dev/pci/ixgbe/ixgbe_82598.c

1108

s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val)

sys/dev/pci/ixgbe/ixgbe_82598.c

1114

atlas_ctl = (reg << 8) | val;

sys/dev/pci/ixgbe/ixgbe_82598.c

419

u32 reg;

sys/dev/pci/ixgbe/ixgbe_82598.c

544

reg = (u32)hw->fc.pause_time * 0x00010001;

sys/dev/pci/ixgbe/ixgbe_82598.c

546

IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);

sys/dev/pci/ixgbe/ixgbe_82598.h

48

s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val);

sys/dev/pci/ixgbe/ixgbe_82598.h

49

s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val);

sys/dev/pci/ixgbe/ixgbe_82599.c

1712

#define IXGBE_WRITE_REG_BE32(a, reg, value) \

sys/dev/pci/ixgbe/ixgbe_82599.c

1713

IXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(IXGBE_NTOHL(value)))

sys/dev/pci/ixgbe/ixgbe_82599.c

2096

s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)

sys/dev/pci/ixgbe/ixgbe_82599.c

2103

(reg << 8));

sys/dev/pci/ixgbe/ixgbe_82599.c

2120

s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)

sys/dev/pci/ixgbe/ixgbe_82599.c

2126

core_ctl = (reg << 8) | val;

sys/dev/pci/ixgbe/ixgbe_82599.h

59

s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val);

sys/dev/pci/ixgbe/ixgbe_82599.h

60

s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val);

sys/dev/pci/ixgbe/ixgbe_api.c

1438

s32 ixgbe_read_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 *val)

sys/dev/pci/ixgbe/ixgbe_api.c

1440

return ixgbe_call_func(hw, hw->mac.ops.read_analog_reg8, (hw, reg,

sys/dev/pci/ixgbe/ixgbe_api.c

1452

s32 ixgbe_write_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 val)

sys/dev/pci/ixgbe/ixgbe_api.c

1454

return ixgbe_call_func(hw, hw->mac.ops.write_analog_reg8, (hw, reg,

sys/dev/pci/ixgbe/ixgbe_api.c

1513

s32 ixgbe_read_link(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val)

sys/dev/pci/ixgbe/ixgbe_api.c

1516

reg, val), IXGBE_NOT_IMPLEMENTED);

sys/dev/pci/ixgbe/ixgbe_api.c

1528

s32 ixgbe_read_link_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val)

sys/dev/pci/ixgbe/ixgbe_api.c

1531

(hw, addr, reg, val), IXGBE_NOT_IMPLEMENTED);

sys/dev/pci/ixgbe/ixgbe_api.c

1578

s32 ixgbe_write_link(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val)

sys/dev/pci/ixgbe/ixgbe_api.c

1581

(hw, addr, reg, val), IXGBE_NOT_IMPLEMENTED);

sys/dev/pci/ixgbe/ixgbe_api.c

1593

s32 ixgbe_write_link_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val)

sys/dev/pci/ixgbe/ixgbe_api.c

1596

(hw, addr, reg, val), IXGBE_NOT_IMPLEMENTED);

sys/dev/pci/ixgbe/ixgbe_api.h

144

s32 ixgbe_read_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 *val);

sys/dev/pci/ixgbe/ixgbe_api.h

145

s32 ixgbe_write_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 val);

sys/dev/pci/ixgbe/ixgbe_api.h

184

s32 ixgbe_read_link(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val);

sys/dev/pci/ixgbe/ixgbe_api.h

185

s32 ixgbe_read_link_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val);

sys/dev/pci/ixgbe/ixgbe_api.h

191

s32 ixgbe_write_link(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val);

sys/dev/pci/ixgbe/ixgbe_api.h

192

s32 ixgbe_write_link_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val);

sys/dev/pci/ixgbe/ixgbe_common.c

1086

u32 reg;

sys/dev/pci/ixgbe/ixgbe_common.c

1091

reg = IXGBE_READ_REG(hw, IXGBE_STATUS);

sys/dev/pci/ixgbe/ixgbe_common.c

1092

bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;

sys/dev/pci/ixgbe/ixgbe_common.c

1096

reg = IXGBE_READ_REG(hw, IXGBE_FACTPS_BY_MAC(hw));

sys/dev/pci/ixgbe/ixgbe_common.c

1097

if (reg & IXGBE_FACTPS_LFS)

sys/dev/pci/ixgbe/ixgbe_common.c

1812

u32 reg;

sys/dev/pci/ixgbe/ixgbe_common.c

1819

reg = IXGBE_READ_REG(hw, IXGBE_EERD);

sys/dev/pci/ixgbe/ixgbe_common.c

1821

reg = IXGBE_READ_REG(hw, IXGBE_EEWR);

sys/dev/pci/ixgbe/ixgbe_common.c

1823

if (reg & IXGBE_EEPROM_RW_REG_DONE) {

sys/dev/pci/ixgbe/ixgbe_common.c

240

u32 reg = 0, reg_bp = 0;

sys/dev/pci/ixgbe/ixgbe_common.c

277

reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);

sys/dev/pci/ixgbe/ixgbe_common.c

2840

u32 reg;

sys/dev/pci/ixgbe/ixgbe_common.c

2952

reg = (u32)hw->fc.pause_time * 0x00010001;

sys/dev/pci/ixgbe/ixgbe_common.c

2954

IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);

sys/dev/pci/ixgbe/ixgbe_common.c

301

reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);

sys/dev/pci/ixgbe/ixgbe_common.c

313

reg |= IXGBE_PCS1GANA_ASM_PAUSE;

sys/dev/pci/ixgbe/ixgbe_common.c

314

reg &= ~IXGBE_PCS1GANA_SYM_PAUSE;

sys/dev/pci/ixgbe/ixgbe_common.c

335

reg |= IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE;

sys/dev/pci/ixgbe/ixgbe_common.c

355

IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);

sys/dev/pci/ixgbe/ixgbe_common.c

356

reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);

sys/dev/pci/ixgbe/ixgbe_common.c

360

reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;

sys/dev/pci/ixgbe/ixgbe_common.c

362

IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);

sys/dev/pci/ixgbe/ixgbe_common.c

363

DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg);

sys/dev/pci/ixgbe/ixgbe_common.c

382

DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg);

sys/dev/pci/ixgbe/ixgbe_common.c

4175

u32 offset, reg;

sys/dev/pci/ixgbe/ixgbe_common.c

4184

reg = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);

sys/dev/pci/ixgbe/ixgbe_common.c

4185

switch (reg & IXGBE_GCR_EXT_VT_MODE_MASK) {

sys/dev/pci/ixgbe/ixgbe_common.c

4205

reg = IXGBE_READ_REG(hw, IXGBE_PVFTXDCTL(offset));

sys/dev/pci/ixgbe/ixgbe_common.c

4206

reg |= IXGBE_TXDCTL_ENABLE;

sys/dev/pci/ixgbe/ixgbe_common.c

4207

IXGBE_WRITE_REG(hw, IXGBE_PVFTXDCTL(offset), reg);

sys/dev/pci/ixgbe/ixgbe_common.c

4211

reg = IXGBE_READ_REG(hw, IXGBE_PVFTXDCTL(offset));

sys/dev/pci/ixgbe/ixgbe_common.c

4212

reg &= ~IXGBE_TXDCTL_ENABLE;

sys/dev/pci/ixgbe/ixgbe_common.c

4213

IXGBE_WRITE_REG(hw, IXGBE_PVFTXDCTL(offset), reg);

sys/dev/pci/ixgbe/ixgbe_common.c

5297

u32 reg, i;

sys/dev/pci/ixgbe/ixgbe_common.c

5299

reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);

sys/dev/pci/ixgbe/ixgbe_common.c

5302

(reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT));

sys/dev/pci/ixgbe/ixgbe_common.h

42

#define IXGBE_WRITE_REG64(hw, reg, value) \

sys/dev/pci/ixgbe/ixgbe_common.h

44

IXGBE_WRITE_REG(hw, reg, (u32) value); \

sys/dev/pci/ixgbe/ixgbe_common.h

45

IXGBE_WRITE_REG(hw, reg + 4, (u32) (value >> 32)); \

sys/dev/pci/ixgbe/ixgbe_dcb_82598.c

119

u32 reg = 0;

sys/dev/pci/ixgbe/ixgbe_dcb_82598.c

124

reg = IXGBE_READ_REG(hw, IXGBE_RUPPBMR) | IXGBE_RUPPBMR_MQA;

sys/dev/pci/ixgbe/ixgbe_dcb_82598.c

125

IXGBE_WRITE_REG(hw, IXGBE_RUPPBMR, reg);

sys/dev/pci/ixgbe/ixgbe_dcb_82598.c

127

reg = IXGBE_READ_REG(hw, IXGBE_RMCS);

sys/dev/pci/ixgbe/ixgbe_dcb_82598.c

129

reg &= ~IXGBE_RMCS_ARBDIS;

sys/dev/pci/ixgbe/ixgbe_dcb_82598.c

131

reg |= IXGBE_RMCS_RRM;

sys/dev/pci/ixgbe/ixgbe_dcb_82598.c

133

reg |= IXGBE_RMCS_DFP;

sys/dev/pci/ixgbe/ixgbe_dcb_82598.c

135

IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg);

sys/dev/pci/ixgbe/ixgbe_dcb_82598.c

142

reg = credit_refill | (credit_max << IXGBE_RT2CR_MCL_SHIFT);

sys/dev/pci/ixgbe/ixgbe_dcb_82598.c

145

reg |= IXGBE_RT2CR_LSP;

sys/dev/pci/ixgbe/ixgbe_dcb_82598.c

147

IXGBE_WRITE_REG(hw, IXGBE_RT2CR(i), reg);

sys/dev/pci/ixgbe/ixgbe_dcb_82598.c

150

reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);

sys/dev/pci/ixgbe/ixgbe_dcb_82598.c

151

reg |= IXGBE_RDRXCTL_RDMTS_1_2;

sys/dev/pci/ixgbe/ixgbe_dcb_82598.c

152

reg |= IXGBE_RDRXCTL_MPBEN;

sys/dev/pci/ixgbe/ixgbe_dcb_82598.c

153

reg |= IXGBE_RDRXCTL_MCEN;

sys/dev/pci/ixgbe/ixgbe_dcb_82598.c

154

IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);

sys/dev/pci/ixgbe/ixgbe_dcb_82598.c

156

reg = IXGBE_READ_REG(hw, IXGBE_RXCTRL);

sys/dev/pci/ixgbe/ixgbe_dcb_82598.c

158

reg &= ~IXGBE_RXCTRL_DMBYPS;

sys/dev/pci/ixgbe/ixgbe_dcb_82598.c

159

IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg);

sys/dev/pci/ixgbe/ixgbe_dcb_82598.c

178

u32 reg, max_credits;

sys/dev/pci/ixgbe/ixgbe_dcb_82598.c

181

reg = IXGBE_READ_REG(hw, IXGBE_DPMCS);

sys/dev/pci/ixgbe/ixgbe_dcb_82598.c

184

reg &= ~IXGBE_DPMCS_ARBDIS;

sys/dev/pci/ixgbe/ixgbe_dcb_82598.c

185

reg |= IXGBE_DPMCS_TSOEF;

sys/dev/pci/ixgbe/ixgbe_dcb_82598.c

188

reg |= (0x4 << IXGBE_DPMCS_MTSOS_SHIFT);

sys/dev/pci/ixgbe/ixgbe_dcb_82598.c

190

IXGBE_WRITE_REG(hw, IXGBE_DPMCS, reg);

sys/dev/pci/ixgbe/ixgbe_dcb_82598.c

195

reg = max_credits << IXGBE_TDTQ2TCCR_MCL_SHIFT;

sys/dev/pci/ixgbe/ixgbe_dcb_82598.c

196

reg |= (u32)(refill[i]);

sys/dev/pci/ixgbe/ixgbe_dcb_82598.c

197

reg |= (u32)(bwg_id[i]) << IXGBE_TDTQ2TCCR_BWG_SHIFT;

sys/dev/pci/ixgbe/ixgbe_dcb_82598.c

200

reg |= IXGBE_TDTQ2TCCR_GSP;

sys/dev/pci/ixgbe/ixgbe_dcb_82598.c

203

reg |= IXGBE_TDTQ2TCCR_LSP;

sys/dev/pci/ixgbe/ixgbe_dcb_82598.c

205

IXGBE_WRITE_REG(hw, IXGBE_TDTQ2TCCR(i), reg);

sys/dev/pci/ixgbe/ixgbe_dcb_82598.c

225

u32 reg;

sys/dev/pci/ixgbe/ixgbe_dcb_82598.c

228

reg = IXGBE_READ_REG(hw, IXGBE_PDPMCS);

sys/dev/pci/ixgbe/ixgbe_dcb_82598.c

230

reg &= ~IXGBE_PDPMCS_ARBDIS;

sys/dev/pci/ixgbe/ixgbe_dcb_82598.c

232

reg |= (IXGBE_PDPMCS_TPPAC | IXGBE_PDPMCS_TRM);

sys/dev/pci/ixgbe/ixgbe_dcb_82598.c

234

IXGBE_WRITE_REG(hw, IXGBE_PDPMCS, reg);

sys/dev/pci/ixgbe/ixgbe_dcb_82598.c

238

reg = refill[i];

sys/dev/pci/ixgbe/ixgbe_dcb_82598.c

239

reg |= (u32)(max[i]) << IXGBE_TDPT2TCCR_MCL_SHIFT;

sys/dev/pci/ixgbe/ixgbe_dcb_82598.c

240

reg |= (u32)(bwg_id[i]) << IXGBE_TDPT2TCCR_BWG_SHIFT;

sys/dev/pci/ixgbe/ixgbe_dcb_82598.c

243

reg |= IXGBE_TDPT2TCCR_GSP;

sys/dev/pci/ixgbe/ixgbe_dcb_82598.c

246

reg |= IXGBE_TDPT2TCCR_LSP;

sys/dev/pci/ixgbe/ixgbe_dcb_82598.c

248

IXGBE_WRITE_REG(hw, IXGBE_TDPT2TCCR(i), reg);

sys/dev/pci/ixgbe/ixgbe_dcb_82598.c

252

reg = IXGBE_READ_REG(hw, IXGBE_DTXCTL);

sys/dev/pci/ixgbe/ixgbe_dcb_82598.c

253

reg |= IXGBE_DTXCTL_ENDBUBD;

sys/dev/pci/ixgbe/ixgbe_dcb_82598.c

254

IXGBE_WRITE_REG(hw, IXGBE_DTXCTL, reg);

sys/dev/pci/ixgbe/ixgbe_dcb_82598.c

268

u32 fcrtl, reg;

sys/dev/pci/ixgbe/ixgbe_dcb_82598.c

272

reg = IXGBE_READ_REG(hw, IXGBE_RMCS);

sys/dev/pci/ixgbe/ixgbe_dcb_82598.c

273

reg &= ~IXGBE_RMCS_TFCE_802_3X;

sys/dev/pci/ixgbe/ixgbe_dcb_82598.c

274

reg |= IXGBE_RMCS_TFCE_PRIORITY;

sys/dev/pci/ixgbe/ixgbe_dcb_82598.c

275

IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg);

sys/dev/pci/ixgbe/ixgbe_dcb_82598.c

278

reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);

sys/dev/pci/ixgbe/ixgbe_dcb_82598.c

279

reg &= ~(IXGBE_FCTRL_RPFCE | IXGBE_FCTRL_RFCE);

sys/dev/pci/ixgbe/ixgbe_dcb_82598.c

282

reg |= IXGBE_FCTRL_RPFCE;

sys/dev/pci/ixgbe/ixgbe_dcb_82598.c

284

IXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg);

sys/dev/pci/ixgbe/ixgbe_dcb_82598.c

295

reg = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;

sys/dev/pci/ixgbe/ixgbe_dcb_82598.c

297

IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), reg);

sys/dev/pci/ixgbe/ixgbe_dcb_82598.c

301

reg = hw->fc.pause_time | (hw->fc.pause_time << 16);

sys/dev/pci/ixgbe/ixgbe_dcb_82598.c

303

IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);

sys/dev/pci/ixgbe/ixgbe_dcb_82598.c

320

u32 reg = 0;

sys/dev/pci/ixgbe/ixgbe_dcb_82598.c

326

reg = IXGBE_READ_REG(hw, IXGBE_RQSMR(i));

sys/dev/pci/ixgbe/ixgbe_dcb_82598.c

327

reg |= ((0x1010101) * j);

sys/dev/pci/ixgbe/ixgbe_dcb_82598.c

328

IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg);

sys/dev/pci/ixgbe/ixgbe_dcb_82598.c

329

reg = IXGBE_READ_REG(hw, IXGBE_RQSMR(i + 1));

sys/dev/pci/ixgbe/ixgbe_dcb_82598.c

330

reg |= ((0x1010101) * j);

sys/dev/pci/ixgbe/ixgbe_dcb_82598.c

331

IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i + 1), reg);

sys/dev/pci/ixgbe/ixgbe_dcb_82598.c

335

reg = IXGBE_READ_REG(hw, IXGBE_TQSMR(i));

sys/dev/pci/ixgbe/ixgbe_dcb_82598.c

336

reg |= ((0x1010101) * i);

sys/dev/pci/ixgbe/ixgbe_dcb_82598.c

337

IXGBE_WRITE_REG(hw, IXGBE_TQSMR(i), reg);

sys/dev/pci/ixgbe/ixgbe_dcb_82599.c

129

u32 reg = 0;

sys/dev/pci/ixgbe/ixgbe_dcb_82599.c

138

reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC | IXGBE_RTRPCS_ARBDIS;

sys/dev/pci/ixgbe/ixgbe_dcb_82599.c

139

IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);

sys/dev/pci/ixgbe/ixgbe_dcb_82599.c

147

reg = 0;

sys/dev/pci/ixgbe/ixgbe_dcb_82599.c

149

reg |= (map[i] << (i * IXGBE_RTRUP2TC_UP_SHIFT));

sys/dev/pci/ixgbe/ixgbe_dcb_82599.c

151

IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);

sys/dev/pci/ixgbe/ixgbe_dcb_82599.c

157

reg = credit_refill | (credit_max << IXGBE_RTRPT4C_MCL_SHIFT);

sys/dev/pci/ixgbe/ixgbe_dcb_82599.c

159

reg |= (u32)(bwg_id[i]) << IXGBE_RTRPT4C_BWG_SHIFT;

sys/dev/pci/ixgbe/ixgbe_dcb_82599.c

162

reg |= IXGBE_RTRPT4C_LSP;

sys/dev/pci/ixgbe/ixgbe_dcb_82599.c

164

IXGBE_WRITE_REG(hw, IXGBE_RTRPT4C(i), reg);

sys/dev/pci/ixgbe/ixgbe_dcb_82599.c

171

reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC;

sys/dev/pci/ixgbe/ixgbe_dcb_82599.c

172

IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);

sys/dev/pci/ixgbe/ixgbe_dcb_82599.c

190

u32 reg, max_credits;

sys/dev/pci/ixgbe/ixgbe_dcb_82599.c

202

reg = max_credits << IXGBE_RTTDT2C_MCL_SHIFT;

sys/dev/pci/ixgbe/ixgbe_dcb_82599.c

203

reg |= (u32)(refill[i]);

sys/dev/pci/ixgbe/ixgbe_dcb_82599.c

204

reg |= (u32)(bwg_id[i]) << IXGBE_RTTDT2C_BWG_SHIFT;

sys/dev/pci/ixgbe/ixgbe_dcb_82599.c

207

reg |= IXGBE_RTTDT2C_GSP;

sys/dev/pci/ixgbe/ixgbe_dcb_82599.c

210

reg |= IXGBE_RTTDT2C_LSP;

sys/dev/pci/ixgbe/ixgbe_dcb_82599.c

212

IXGBE_WRITE_REG(hw, IXGBE_RTTDT2C(i), reg);

sys/dev/pci/ixgbe/ixgbe_dcb_82599.c

219

reg = IXGBE_RTTDCS_TDPAC | IXGBE_RTTDCS_TDRM;

sys/dev/pci/ixgbe/ixgbe_dcb_82599.c

220

IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);

sys/dev/pci/ixgbe/ixgbe_dcb_82599.c

240

u32 reg;

sys/dev/pci/ixgbe/ixgbe_dcb_82599.c

247

reg = IXGBE_RTTPCS_TPPAC | IXGBE_RTTPCS_TPRM |

sys/dev/pci/ixgbe/ixgbe_dcb_82599.c

250

IXGBE_WRITE_REG(hw, IXGBE_RTTPCS, reg);

sys/dev/pci/ixgbe/ixgbe_dcb_82599.c

258

reg = 0;

sys/dev/pci/ixgbe/ixgbe_dcb_82599.c

260

reg |= (map[i] << (i * IXGBE_RTTUP2TC_UP_SHIFT));

sys/dev/pci/ixgbe/ixgbe_dcb_82599.c

262

IXGBE_WRITE_REG(hw, IXGBE_RTTUP2TC, reg);

sys/dev/pci/ixgbe/ixgbe_dcb_82599.c

266

reg = refill[i];

sys/dev/pci/ixgbe/ixgbe_dcb_82599.c

267

reg |= (u32)(max[i]) << IXGBE_RTTPT2C_MCL_SHIFT;

sys/dev/pci/ixgbe/ixgbe_dcb_82599.c

268

reg |= (u32)(bwg_id[i]) << IXGBE_RTTPT2C_BWG_SHIFT;

sys/dev/pci/ixgbe/ixgbe_dcb_82599.c

271

reg |= IXGBE_RTTPT2C_GSP;

sys/dev/pci/ixgbe/ixgbe_dcb_82599.c

274

reg |= IXGBE_RTTPT2C_LSP;

sys/dev/pci/ixgbe/ixgbe_dcb_82599.c

276

IXGBE_WRITE_REG(hw, IXGBE_RTTPT2C(i), reg);

sys/dev/pci/ixgbe/ixgbe_dcb_82599.c

283

reg = IXGBE_RTTPCS_TPPAC | IXGBE_RTTPCS_TPRM |

sys/dev/pci/ixgbe/ixgbe_dcb_82599.c

285

IXGBE_WRITE_REG(hw, IXGBE_RTTPCS, reg);

sys/dev/pci/ixgbe/ixgbe_dcb_82599.c

300

u32 i, j, fcrtl, reg;

sys/dev/pci/ixgbe/ixgbe_dcb_82599.c

307

reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);

sys/dev/pci/ixgbe/ixgbe_dcb_82599.c

308

reg |= IXGBE_MFLCN_DPF;

sys/dev/pci/ixgbe/ixgbe_dcb_82599.c

315

reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE);

sys/dev/pci/ixgbe/ixgbe_dcb_82599.c

318

reg |= pfc_en << IXGBE_MFLCN_RPFCE_SHIFT;

sys/dev/pci/ixgbe/ixgbe_dcb_82599.c

321

reg |= IXGBE_MFLCN_RPFCE;

sys/dev/pci/ixgbe/ixgbe_dcb_82599.c

323

IXGBE_WRITE_REG(hw, IXGBE_MFLCN, reg);

sys/dev/pci/ixgbe/ixgbe_dcb_82599.c

343

reg = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;

sys/dev/pci/ixgbe/ixgbe_dcb_82599.c

354

reg = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576;

sys/dev/pci/ixgbe/ixgbe_dcb_82599.c

358

IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), reg);

sys/dev/pci/ixgbe/ixgbe_dcb_82599.c

367

reg = hw->fc.pause_time | (hw->fc.pause_time << 16);

sys/dev/pci/ixgbe/ixgbe_dcb_82599.c

369

IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);

sys/dev/pci/ixgbe/ixgbe_dcb_82599.c

388

u32 reg = 0;

sys/dev/pci/ixgbe/ixgbe_dcb_82599.c

410

reg = 0x01010101 * (i / 4);

sys/dev/pci/ixgbe/ixgbe_dcb_82599.c

411

IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg);

sys/dev/pci/ixgbe/ixgbe_dcb_82599.c

424

reg = 0x00000000;

sys/dev/pci/ixgbe/ixgbe_dcb_82599.c

426

reg = 0x01010101;

sys/dev/pci/ixgbe/ixgbe_dcb_82599.c

428

reg = 0x02020202;

sys/dev/pci/ixgbe/ixgbe_dcb_82599.c

430

reg = 0x03030303;

sys/dev/pci/ixgbe/ixgbe_dcb_82599.c

432

reg = 0x04040404;

sys/dev/pci/ixgbe/ixgbe_dcb_82599.c

434

reg = 0x05050505;

sys/dev/pci/ixgbe/ixgbe_dcb_82599.c

436

reg = 0x06060606;

sys/dev/pci/ixgbe/ixgbe_dcb_82599.c

438

reg = 0x07070707;

sys/dev/pci/ixgbe/ixgbe_dcb_82599.c

439

IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), reg);

sys/dev/pci/ixgbe/ixgbe_dcb_82599.c

455

reg = 0x01010101 * (i / 8);

sys/dev/pci/ixgbe/ixgbe_dcb_82599.c

456

IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg);

sys/dev/pci/ixgbe/ixgbe_dcb_82599.c

469

reg = 0x00000000;

sys/dev/pci/ixgbe/ixgbe_dcb_82599.c

471

reg = 0x01010101;

sys/dev/pci/ixgbe/ixgbe_dcb_82599.c

473

reg = 0x02020202;

sys/dev/pci/ixgbe/ixgbe_dcb_82599.c

475

reg = 0x03030303;

sys/dev/pci/ixgbe/ixgbe_dcb_82599.c

476

IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), reg);

sys/dev/pci/ixgbe/ixgbe_dcb_82599.c

514

u32 reg;

sys/dev/pci/ixgbe/ixgbe_dcb_82599.c

518

reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);

sys/dev/pci/ixgbe/ixgbe_dcb_82599.c

519

reg |= IXGBE_RTTDCS_ARBDIS;

sys/dev/pci/ixgbe/ixgbe_dcb_82599.c

520

IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);

sys/dev/pci/ixgbe/ixgbe_dcb_82599.c

522

reg = IXGBE_READ_REG(hw, IXGBE_MRQC);

sys/dev/pci/ixgbe/ixgbe_dcb_82599.c

525

switch (reg & IXGBE_MRQC_MRQE_MASK) {

sys/dev/pci/ixgbe/ixgbe_dcb_82599.c

529

reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |

sys/dev/pci/ixgbe/ixgbe_dcb_82599.c

535

reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |

sys/dev/pci/ixgbe/ixgbe_dcb_82599.c

544

reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |

sys/dev/pci/ixgbe/ixgbe_dcb_82599.c

551

reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |

sys/dev/pci/ixgbe/ixgbe_dcb_82599.c

554

reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |

sys/dev/pci/ixgbe/ixgbe_dcb_82599.c

557

IXGBE_WRITE_REG(hw, IXGBE_MRQC, reg);

sys/dev/pci/ixgbe/ixgbe_dcb_82599.c

561

reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;

sys/dev/pci/ixgbe/ixgbe_dcb_82599.c

564

reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;

sys/dev/pci/ixgbe/ixgbe_dcb_82599.c

566

reg |= IXGBE_MTQC_VT_ENA;

sys/dev/pci/ixgbe/ixgbe_dcb_82599.c

568

IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);

sys/dev/pci/ixgbe/ixgbe_dcb_82599.c

576

reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);

sys/dev/pci/ixgbe/ixgbe_dcb_82599.c

577

reg &= ~IXGBE_RTTDCS_ARBDIS;

sys/dev/pci/ixgbe/ixgbe_dcb_82599.c

578

IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);

sys/dev/pci/ixgbe/ixgbe_dcb_82599.c

581

reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);

sys/dev/pci/ixgbe/ixgbe_dcb_82599.c

582

reg |= IXGBE_SECTX_DCB;

sys/dev/pci/ixgbe/ixgbe_dcb_82599.c

583

IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);

sys/dev/pci/ixgbe/ixgbe_osdep.c

100

ixgbe_write_reg(struct ixgbe_hw *hw, u32 reg, u32 val)

sys/dev/pci/ixgbe/ixgbe_osdep.c

104

reg, val);

sys/dev/pci/ixgbe/ixgbe_osdep.c

108

ixgbe_read_reg_array(struct ixgbe_hw *hw, u32 reg, u32 offset)

sys/dev/pci/ixgbe/ixgbe_osdep.c

112

reg + (offset << 2));

sys/dev/pci/ixgbe/ixgbe_osdep.c

116

ixgbe_write_reg_array(struct ixgbe_hw *hw, u32 reg, u32 offset, u32 val)

sys/dev/pci/ixgbe/ixgbe_osdep.c

120

reg + (offset << 2), val);

sys/dev/pci/ixgbe/ixgbe_osdep.c

50

ixgbe_read_pci_cfg(struct ixgbe_hw *hw, u32 reg)

sys/dev/pci/ixgbe/ixgbe_osdep.c

55

switch (reg % 4) {

sys/dev/pci/ixgbe/ixgbe_osdep.c

57

return pci_conf_read(pc, tag, reg) & __BITS(15, 0);

sys/dev/pci/ixgbe/ixgbe_osdep.c

59

return __SHIFTOUT(pci_conf_read(pc, tag, reg - 2),

sys/dev/pci/ixgbe/ixgbe_osdep.c

62

panic("%s: invalid register (%" PRIx32, __func__, reg);

sys/dev/pci/ixgbe/ixgbe_osdep.c

68

ixgbe_write_pci_cfg(struct ixgbe_hw *hw, u32 reg, u16 value)

sys/dev/pci/ixgbe/ixgbe_osdep.c

74

switch (reg % 4) {

sys/dev/pci/ixgbe/ixgbe_osdep.c

76

old = pci_conf_read(pc, tag, reg) & __BITS(31, 16);

sys/dev/pci/ixgbe/ixgbe_osdep.c

77

pci_conf_write(pc, tag, reg, value | old);

sys/dev/pci/ixgbe/ixgbe_osdep.c

80

old = pci_conf_read(pc, tag, reg - 2) & __BITS(15, 0);

sys/dev/pci/ixgbe/ixgbe_osdep.c

81

pci_conf_write(pc, tag, reg - 2,

sys/dev/pci/ixgbe/ixgbe_osdep.c

85

panic("%s: invalid register (%" PRIx32, __func__, reg);

sys/dev/pci/ixgbe/ixgbe_osdep.c

93

ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg)

sys/dev/pci/ixgbe/ixgbe_osdep.c

96

((struct ixgbe_softc *)hw->back)->osdep.mem_bus_space_handle, reg);

sys/dev/pci/ixgbe/ixgbe_osdep.h

200

#define IXGBE_READ_REG(a, reg) ixgbe_read_reg(a, reg)

sys/dev/pci/ixgbe/ixgbe_osdep.h

203

#define IXGBE_WRITE_REG(a, reg, val) ixgbe_write_reg(a, reg, val)

sys/dev/pci/ixgbe/ixgbe_osdep.h

206

#define IXGBE_READ_REG_ARRAY(a, reg, offset) \

sys/dev/pci/ixgbe/ixgbe_osdep.h

207

ixgbe_read_reg_array(a, reg, offset)

sys/dev/pci/ixgbe/ixgbe_osdep.h

210

#define IXGBE_WRITE_REG_ARRAY(a, reg, offset, val) \

sys/dev/pci/ixgbe/ixgbe_osdep.h

211

ixgbe_write_reg_array(a, reg, offset, val)

sys/dev/pci/ixgbe/ixgbe_phy.c

117

s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,

sys/dev/pci/ixgbe/ixgbe_phy.c

129

reg_high = ((reg >> 7) & 0xFE) | 1; /* Indicate read combined */

sys/dev/pci/ixgbe/ixgbe_phy.c

130

csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);

sys/dev/pci/ixgbe/ixgbe_phy.c

143

if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))

sys/dev/pci/ixgbe/ixgbe_phy.c

194

s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,

sys/dev/pci/ixgbe/ixgbe_phy.c

203

reg_high = (reg >> 7) & 0xFE; /* Indicate write combined */

sys/dev/pci/ixgbe/ixgbe_phy.c

204

csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);

sys/dev/pci/ixgbe/ixgbe_phy.c

219

if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))

sys/dev/pci/ixgbe/ixgbe_phy.c

2748

u16 reg;

sys/dev/pci/ixgbe/ixgbe_phy.c

2755

&reg);

sys/dev/pci/ixgbe/ixgbe_phy.c

2760

reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;

sys/dev/pci/ixgbe/ixgbe_phy.c

2764

reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;

sys/dev/pci/ixgbe/ixgbe_phy.c

2769

reg);

sys/dev/pci/ixgbe/ixgbe_phy.h

219

s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *, u8 addr, u16 reg,

sys/dev/pci/ixgbe/ixgbe_phy.h

221

s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *, u8 addr, u16 reg,

sys/dev/pci/ixgbe/ixgbe_type.h

4160

s32 (*read_link)(struct ixgbe_hw *, u8 addr, u16 reg, u16 *val);

sys/dev/pci/ixgbe/ixgbe_type.h

4161

s32 (*read_link_unlocked)(struct ixgbe_hw *, u8 addr, u16 reg,

sys/dev/pci/ixgbe/ixgbe_type.h

4163

s32 (*write_link)(struct ixgbe_hw *, u8 addr, u16 reg, u16 val);

sys/dev/pci/ixgbe/ixgbe_type.h

4164

s32 (*write_link_unlocked)(struct ixgbe_hw *, u8 addr, u16 reg,

sys/dev/pci/ixgbe/ixgbe_x540.c

748

u32 reg;

sys/dev/pci/ixgbe/ixgbe_x540.c

754

reg = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));

sys/dev/pci/ixgbe/ixgbe_x540.c

755

if (reg & IXGBE_EEC_FLUDONE) {

sys/dev/pci/ixgbe/ixgbe_x550.c

1061

u32 reg, high_pri_tc;

sys/dev/pci/ixgbe/ixgbe_x550.c

1066

reg = IXGBE_READ_REG(hw, IXGBE_DMACR);

sys/dev/pci/ixgbe/ixgbe_x550.c

1067

reg &= ~IXGBE_DMACR_DMAC_EN;

sys/dev/pci/ixgbe/ixgbe_x550.c

1068

IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);

sys/dev/pci/ixgbe/ixgbe_x550.c

1077

reg = IXGBE_READ_REG(hw, IXGBE_DMACR);

sys/dev/pci/ixgbe/ixgbe_x550.c

1080

reg &= ~IXGBE_DMACR_DMACWT_MASK;

sys/dev/pci/ixgbe/ixgbe_x550.c

1081

reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;

sys/dev/pci/ixgbe/ixgbe_x550.c

1083

reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;

sys/dev/pci/ixgbe/ixgbe_x550.c

1087

reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &

sys/dev/pci/ixgbe/ixgbe_x550.c

1090

reg |= IXGBE_DMACR_EN_MNG_IND;

sys/dev/pci/ixgbe/ixgbe_x550.c

1093

reg |= IXGBE_DMACR_DMAC_EN;

sys/dev/pci/ixgbe/ixgbe_x550.c

1094

IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);

sys/dev/pci/ixgbe/ixgbe_x550.c

1109

u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;

sys/dev/pci/ixgbe/ixgbe_x550.c

1132

reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));

sys/dev/pci/ixgbe/ixgbe_x550.c

1133

reg &= ~IXGBE_DMCTH_DMACRXT_MASK;

sys/dev/pci/ixgbe/ixgbe_x550.c

1148

reg |= (rx_pb_size > maxframe_size_kb) ?

sys/dev/pci/ixgbe/ixgbe_x550.c

1151

IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);

sys/dev/pci/ixgbe/ixgbe_x550.c

1164

u32 reg;

sys/dev/pci/ixgbe/ixgbe_x550.c

1169

reg = IXGBE_READ_REG(hw, IXGBE_DMACR);

sys/dev/pci/ixgbe/ixgbe_x550.c

1170

reg &= ~IXGBE_DMACR_DMAC_EN;

sys/dev/pci/ixgbe/ixgbe_x550.c

1171

IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);

sys/dev/pci/ixgbe/ixgbe_x550.c

1176

reg = IXGBE_READ_REG(hw, IXGBE_DMACR);

sys/dev/pci/ixgbe/ixgbe_x550.c

1177

reg |= IXGBE_DMACR_DMAC_EN;

sys/dev/pci/ixgbe/ixgbe_x550.c

1178

IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);

sys/dev/pci/ixgbe/ixgbe_x550.c

123

static s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)

sys/dev/pci/ixgbe/ixgbe_x550.c

125

return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value);

sys/dev/pci/ixgbe/ixgbe_x550.c

136

static s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)

sys/dev/pci/ixgbe/ixgbe_x550.c

138

return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value);

sys/dev/pci/ixgbe/ixgbe_x550.c

149

static s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)

sys/dev/pci/ixgbe/ixgbe_x550.c

153

status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);

sys/dev/pci/ixgbe/ixgbe_x550.c

1535

u32 reg;

sys/dev/pci/ixgbe/ixgbe_x550.c

1540

reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);

sys/dev/pci/ixgbe/ixgbe_x550.c

1541

reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);

sys/dev/pci/ixgbe/ixgbe_x550.c

1542

IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);

sys/dev/pci/ixgbe/ixgbe_x550.c

1545

reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);

sys/dev/pci/ixgbe/ixgbe_x550.c

1546

reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);

sys/dev/pci/ixgbe/ixgbe_x550.c

1547

IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);

sys/dev/pci/ixgbe/ixgbe_x550.c

1558

u32 reg;

sys/dev/pci/ixgbe/ixgbe_x550.c

1563

reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);

sys/dev/pci/ixgbe/ixgbe_x550.c

1564

reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);

sys/dev/pci/ixgbe/ixgbe_x550.c

1565

IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);

sys/dev/pci/ixgbe/ixgbe_x550.c

1568

reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);

sys/dev/pci/ixgbe/ixgbe_x550.c

1569

reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);

sys/dev/pci/ixgbe/ixgbe_x550.c

1570

IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);

sys/dev/pci/ixgbe/ixgbe_x550.c

1582

u32 idx, reg, num_qs, start_q, bitmask;

sys/dev/pci/ixgbe/ixgbe_x550.c

1587

reg = IXGBE_READ_REG(hw, IXGBE_MRQC);

sys/dev/pci/ixgbe/ixgbe_x550.c

1588

switch (reg & IXGBE_MRQC_MRQE_MASK) {

sys/dev/pci/ixgbe/ixgbe_x550.c

1607

reg = 0;

sys/dev/pci/ixgbe/ixgbe_x550.c

1608

reg |= (bitmask << (start_q % 32));

sys/dev/pci/ixgbe/ixgbe_x550.c

1609

IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);

sys/dev/pci/ixgbe/ixgbe_x550.c

1610

IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);

sys/dev/pci/ixgbe/ixgbe_x550.c

1623

u32 i, j, reg, q, shift, vf, idx;

sys/dev/pci/ixgbe/ixgbe_x550.c

1628

reg = IXGBE_READ_REG(hw, IXGBE_MRQC);

sys/dev/pci/ixgbe/ixgbe_x550.c

1629

switch (reg & IXGBE_MRQC_MRQE_MASK) {

sys/dev/pci/ixgbe/ixgbe_x550.c

168

static s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)

sys/dev/pci/ixgbe/ixgbe_x550.c

172

status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);

sys/dev/pci/ixgbe/ixgbe_x550.c

191

u8 reg;

sys/dev/pci/ixgbe/ixgbe_x550.c

194

status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);

sys/dev/pci/ixgbe/ixgbe_x550.c

197

reg |= IXGBE_PE_BIT1;

sys/dev/pci/ixgbe/ixgbe_x550.c

198

status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);

sys/dev/pci/ixgbe/ixgbe_x550.c

202

status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, &reg);

sys/dev/pci/ixgbe/ixgbe_x550.c

205

reg &= ~IXGBE_PE_BIT1;

sys/dev/pci/ixgbe/ixgbe_x550.c

206

status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);

sys/dev/pci/ixgbe/ixgbe_x550.c

210

status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);

sys/dev/pci/ixgbe/ixgbe_x550.c

213

reg &= ~IXGBE_PE_BIT1;

sys/dev/pci/ixgbe/ixgbe_x550.c

214

status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);

sys/dev/pci/ixgbe/ixgbe_x550.c

2140

u16 reg;

sys/dev/pci/ixgbe/ixgbe_x550.c

2147

&reg);

sys/dev/pci/ixgbe/ixgbe_x550.c

2150

!(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))

sys/dev/pci/ixgbe/ixgbe_x550.c

2156

&reg);

sys/dev/pci/ixgbe/ixgbe_x550.c

2159

!(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |

sys/dev/pci/ixgbe/ixgbe_x550.c

2166

&reg);

sys/dev/pci/ixgbe/ixgbe_x550.c

2172

if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {

sys/dev/pci/ixgbe/ixgbe_x550.c

2176

} else if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) {

sys/dev/pci/ixgbe/ixgbe_x550.c

2180

&reg);

sys/dev/pci/ixgbe/ixgbe_x550.c

2186

if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) {

sys/dev/pci/ixgbe/ixgbe_x550.c

2195

IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);

sys/dev/pci/ixgbe/ixgbe_x550.c

2198

!(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))

sys/dev/pci/ixgbe/ixgbe_x550.c

220

status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);

sys/dev/pci/ixgbe/ixgbe_x550.c

2203

IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);

sys/dev/pci/ixgbe/ixgbe_x550.c

2209

if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)

sys/dev/pci/ixgbe/ixgbe_x550.c

2227

u16 reg;

sys/dev/pci/ixgbe/ixgbe_x550.c

223

reg |= IXGBE_PE_BIT1;

sys/dev/pci/ixgbe/ixgbe_x550.c

224

status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);

sys/dev/pci/ixgbe/ixgbe_x550.c

2246

IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);

sys/dev/pci/ixgbe/ixgbe_x550.c

2251

reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;

sys/dev/pci/ixgbe/ixgbe_x550.c

2255

IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);

sys/dev/pci/ixgbe/ixgbe_x550.c

2264

&reg);

sys/dev/pci/ixgbe/ixgbe_x550.c

2269

reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN |

sys/dev/pci/ixgbe/ixgbe_x550.c

2274

reg);

sys/dev/pci/ixgbe/ixgbe_x550.c

2282

&reg);

sys/dev/pci/ixgbe/ixgbe_x550.c

2287

reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |

sys/dev/pci/ixgbe/ixgbe_x550.c

2292

reg);

sys/dev/pci/ixgbe/ixgbe_x550.c

2300

&reg);

sys/dev/pci/ixgbe/ixgbe_x550.c

2305

reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;

sys/dev/pci/ixgbe/ixgbe_x550.c

2309

reg);

sys/dev/pci/ixgbe/ixgbe_x550.c

2745

u16 reg;

sys/dev/pci/ixgbe/ixgbe_x550.c

2750

&reg);

sys/dev/pci/ixgbe/ixgbe_x550.c

2758

if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {

sys/dev/pci/ixgbe/ixgbe_x550.c

2762

&reg);

sys/dev/pci/ixgbe/ixgbe_x550.c

2767

reg &= ~IXGBE_MDIO_POWER_UP_STALL;

sys/dev/pci/ixgbe/ixgbe_x550.c

2772

reg);

sys/dev/pci/ixgbe/ixgbe_x550.c

3395

u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +

sys/dev/pci/ixgbe/ixgbe_x550.c

3397

u32 value = IXGBE_READ_REG(hw, reg);

sys/dev/pci/ixgbe/ixgbe_x550.c

653

u16 reg, u16 *val)

sys/dev/pci/ixgbe/ixgbe_x550.c

655

return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, TRUE);

sys/dev/pci/ixgbe/ixgbe_x550.c

669

u16 reg, u16 *val)

sys/dev/pci/ixgbe/ixgbe_x550.c

671

return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, FALSE);

sys/dev/pci/ixgbe/ixgbe_x550.c

684

u8 addr, u16 reg, u16 val)

sys/dev/pci/ixgbe/ixgbe_x550.c

686

return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, TRUE);

sys/dev/pci/ixgbe/ixgbe_x550.c

700

u8 addr, u16 reg, u16 val)

sys/dev/pci/ixgbe/ixgbe_x550.c

702

return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, FALSE);

sys/dev/pci/ixgbe/ixv.c

1902

u32 reg, rxdctl;

sys/dev/pci/ixgbe/ixv.c

1929

reg = IXGBE_READ_REG(hw, IXGBE_VFSRRCTL(j));

sys/dev/pci/ixgbe/ixv.c

1930

reg &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;

sys/dev/pci/ixgbe/ixv.c

1931

reg &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;

sys/dev/pci/ixgbe/ixv.c

1932

reg |= bufsz;

sys/dev/pci/ixgbe/ixv.c

1933

reg |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;

sys/dev/pci/ixgbe/ixv.c

1934

IXGBE_WRITE_REG(hw, IXGBE_VFSRRCTL(j), reg);

sys/dev/pci/ixgbe/ixv.c

2437

#define UPDATE_STAT_32(reg, last, count) \

sys/dev/pci/ixgbe/ixv.c

2439

u32 current = IXGBE_READ_REG(hw, (reg)); \

sys/dev/pci/ixgbe/ixv.c

2486

uint32_t reg, usec, rate;

sys/dev/pci/ixgbe/ixv.c

2491

reg = IXGBE_READ_REG(&que->sc->hw, IXGBE_VTEITR(que->msix));

sys/dev/pci/ixgbe/ixv.c

2492

usec = ((reg & 0x0FF8) >> 3);

sys/dev/pci/ixgbe/ixv.c

2501

reg &= ~0xfff; /* default, no limitation */

sys/dev/pci/ixgbe/ixv.c

2505

reg |= ((4000000 / rate) & 0xff8);

sys/dev/pci/ixgbe/ixv.c

2515

&& (reg < IXGBE_MIN_RSC_EITR_10G1G))

sys/dev/pci/ixgbe/ixv.c

2521

ixv_eitr_write(sc, que->msix, reg);

sys/dev/pci/joy_pci.c

100

reg += sizeof(pcireg_t))

sys/dev/pci/joy_pci.c

101

if (bar_is_io(pa->pa_pc, pa->pa_tag, reg))

sys/dev/pci/joy_pci.c

103

if (reg >= PCI_MAPREG_END) {

sys/dev/pci/joy_pci.c

109

if (pci_mapreg_map(pa, reg, PCI_MAPREG_TYPE_IO, 0,

sys/dev/pci/joy_pci.c

53

static int bar_is_io(pci_chipset_tag_t pc, pcitag_t tag, int reg);

sys/dev/pci/joy_pci.c

75

bar_is_io(pci_chipset_tag_t pc, pcitag_t tag, int reg)

sys/dev/pci/joy_pci.c

79

address = pci_conf_read(pc, tag, reg);

sys/dev/pci/joy_pci.c

80

pci_conf_write(pc, tag, reg, 0xffffffff);

sys/dev/pci/joy_pci.c

81

mask = pci_conf_read(pc, tag, reg);

sys/dev/pci/joy_pci.c

82

pci_conf_write(pc, tag, reg, address);

sys/dev/pci/joy_pci.c

95

int reg;

sys/dev/pci/joy_pci.c

99

for (reg = PCI_MAPREG_START; reg < PCI_MAPREG_END;

sys/dev/pci/lynxfb.c

106

#define DPR_READ(fb, reg) \

sys/dev/pci/lynxfb.c

107

bus_space_read_4((fb)->memt, (fb)->dprh, (reg))

sys/dev/pci/lynxfb.c

108

#define DPR_WRITE(fb, reg, val) \

sys/dev/pci/lynxfb.c

109

bus_space_write_4((fb)->memt, (fb)->dprh, (reg), (val))

sys/dev/pci/lynxfb.c

625

uint32_t reg;

sys/dev/pci/lynxfb.c

629

reg = lynxfb_vgats_read(fb, 0x16);

sys/dev/pci/lynxfb.c

630

if ((reg & 0x18) == 0x10)

sys/dev/pci/machfb.c

1379

uint8_t reg, vclk_ctl;

sys/dev/pci/machfb.c

1421

reg = regrb_pll(sc, VCLK_POST_DIV);

sys/dev/pci/machfb.c

1422

reg &= ~(3 << clockshift);

sys/dev/pci/machfb.c

1423

reg |= (sc->log2_vclk_post_div << clockshift);

sys/dev/pci/machfb.c

1424

regwb_pll(sc, VCLK_POST_DIV, reg);

sys/dev/pci/machfb.c

1893

int reg = 0;

sys/dev/pci/machfb.c

1899

regw(sc, HOST_DATA0 + reg, latch);

sys/dev/pci/machfb.c

1902

reg = (reg + 4) & 0x3c;

sys/dev/pci/machfb.c

1907

regw(sc, HOST_DATA0 + reg, latch);

sys/dev/pci/machfb.c

2101

uint32_t reg;

sys/dev/pci/machfb.c

2108

reg = regr(sc, CRTC_GEN_CNTL);

sys/dev/pci/machfb.c

2109

regw(sc, CRTC_GEN_CNTL, reg & ~(MACH64_BLANK));

sys/dev/pci/machfb.c

2113

reg = regr(sc, CRTC_GEN_CNTL);

sys/dev/pci/machfb.c

2114

regw(sc, CRTC_GEN_CNTL, reg | (MACH64_BLANK));

sys/dev/pci/machfb.c

353

uint32_t reg;

sys/dev/pci/machfb.c

355

reg = regr(sc, CLOCK_CNTL);

sys/dev/pci/machfb.c

356

reg |= PLL_WR_EN;

sys/dev/pci/machfb.c

357

regw(sc, CLOCK_CNTL, reg);

sys/dev/pci/machfb.c

358

reg &= ~(PLL_ADDR | PLL_DATA);

sys/dev/pci/machfb.c

359

reg |= (index & 0x3f) << PLL_ADDR_SHIFT;

sys/dev/pci/machfb.c

360

reg |= data << PLL_DATA_SHIFT;

sys/dev/pci/machfb.c

361

reg |= CLOCK_STROBE;

sys/dev/pci/machfb.c

362

regw(sc, CLOCK_CNTL, reg);

sys/dev/pci/machfb.c

363

reg &= ~PLL_WR_EN;

sys/dev/pci/machfb.c

364

regw(sc, CLOCK_CNTL, reg);

sys/dev/pci/machfb.c

426

uint32_t reg;

sys/dev/pci/machfb.c

457

reg = PCI_MAPREG_START + (bar * 4);

sys/dev/pci/machfb.c

459

sc->sc_pcitag, reg);

sys/dev/pci/machfb.c

460

(void)pci_mapreg_info(sc->sc_pc, sc->sc_pcitag, reg,

sys/dev/pci/machfb.c

572

reg = regr(sc, CLOCK_CNTL);

sys/dev/pci/machfb.c

573

sc->sc_clock = reg & 3;

sys/dev/pci/machfb.c

803

reg = regr(sc, BUS_CNTL);

sys/dev/pci/machfb.c

804

aprint_debug_dev(sc->sc_dev, "BUS_CNTL: %08x\n", reg);

sys/dev/pci/machfb.c

805

reg |= BUS_APER_REG_DIS;

sys/dev/pci/machfb.c

806

regw(sc, BUS_CNTL, reg);

sys/dev/pci/mgafb.c

445

mgafb_dac_write(struct mgafb_softc *sc, uint8_t reg, uint8_t val)

sys/dev/pci/mgafb.c

447

MGA_WRITE1(sc, MGA_DAC_BASE + reg, val);

sys/dev/pci/mgafb.c

451

mgafb_dac_read(struct mgafb_softc *sc, uint8_t reg)

sys/dev/pci/mgafb.c

453

return MGA_READ1(sc, MGA_DAC_BASE + reg);

sys/dev/pci/mgafb.c

68

MGA_WRITE4(struct mgafb_softc *sc, bus_size_t reg, uint32_t v)

sys/dev/pci/mgafb.c

70

bus_space_write_4(sc->sc_regt, sc->sc_regh, reg, v);

sys/dev/pci/mgafb.c

71

bus_space_barrier(sc->sc_regt, sc->sc_regh, reg, 4,

sys/dev/pci/mgafb.c

76

MGA_WRITE1(struct mgafb_softc *sc, bus_size_t reg, uint8_t v)

sys/dev/pci/mgafb.c

78

bus_space_write_1(sc->sc_regt, sc->sc_regh, reg, v);

sys/dev/pci/mgafb.c

79

bus_space_barrier(sc->sc_regt, sc->sc_regh, reg, 1,

sys/dev/pci/mgafb.c

84

MGA_READ4(struct mgafb_softc *sc, bus_size_t reg)

sys/dev/pci/mgafb.c

86

bus_space_barrier(sc->sc_regt, sc->sc_regh, reg, 4,

sys/dev/pci/mgafb.c

88

return bus_space_read_4(sc->sc_regt, sc->sc_regh, reg);

sys/dev/pci/mgafb.c

92

MGA_READ1(struct mgafb_softc *sc, bus_size_t reg)

sys/dev/pci/mgafb.c

94

bus_space_barrier(sc->sc_regt, sc->sc_regh, reg, 1,

sys/dev/pci/mgafb.c

96

return bus_space_read_1(sc->sc_regt, sc->sc_regh, reg);

sys/dev/pci/mlx_pci.c

164

pcireg_t reg;

sys/dev/pci/mlx_pci.c

177

reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG);

sys/dev/pci/mlx_pci.c

179

if (PCI_VENDOR(reg) == mpi->mpi_subvendor &&

sys/dev/pci/mlx_pci.c

180

PCI_PRODUCT(reg) == mpi->mpi_subproduct)

sys/dev/pci/mlx_pci.c

209

pcireg_t reg;

sys/dev/pci/mlx_pci.c

233

reg = pci_conf_read(pa->pa_pc, pa->pa_tag, i);

sys/dev/pci/mlx_pci.c

235

if (PCI_MAPREG_TYPE(reg) == PCI_MAPREG_TYPE_IO) {

sys/dev/pci/mlx_pci.c

236

if (ior == -1 && PCI_MAPREG_IO_SIZE(reg) != 0)

sys/dev/pci/mlx_pci.c

239

if (memr == -1 && PCI_MAPREG_MEM_SIZE(reg) != 0)

sys/dev/pci/mlx_pci.c

265

reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);

sys/dev/pci/mlx_pci.c

267

reg | PCI_COMMAND_MASTER_ENABLE);

sys/dev/pci/mly.c

238

pcireg_t reg;

sys/dev/pci/mly.c

254

reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG);

sys/dev/pci/mly.c

256

if (PCI_VENDOR(reg) == mpi->subvendor &&

sys/dev/pci/mly.c

257

PCI_PRODUCT(reg) == mpi->subproduct)

sys/dev/pci/mly.c

288

pcireg_t reg;

sys/dev/pci/mly.c

314

reg = pci_conf_read(pa->pa_pc, pa->pa_tag, i);

sys/dev/pci/mly.c

316

if (PCI_MAPREG_TYPE(reg) == PCI_MAPREG_TYPE_IO) {

sys/dev/pci/mly.c

317

if (ior == -1 && PCI_MAPREG_IO_SIZE(reg) != 0)

sys/dev/pci/mly.c

320

if (memr == -1 && PCI_MAPREG_MEM_SIZE(reg) != 0)

sys/dev/pci/mly.c

348

reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);

sys/dev/pci/mly.c

350

reg | PCI_COMMAND_MASTER_ENABLE);

sys/dev/pci/mpt_pci.c

133

pcireg_t reg, memtype;

sys/dev/pci/mpt_pci.c

173

reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);

sys/dev/pci/mpt_pci.c

174

reg |= PCI_COMMAND_MASTER_ENABLE;

sys/dev/pci/mpt_pci.c

178

pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, reg);

sys/dev/pci/mpt_pci.c

187

reg = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x68);

sys/dev/pci/mpt_pci.c

188

reg &= 0x8fffff;

sys/dev/pci/mpt_pci.c

189

pci_conf_write(pa->pa_pc, pa->pa_tag, 0x68, reg);

sys/dev/pci/mpt_pci.c

195

reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM);

sys/dev/pci/mpt_pci.c

196

reg &= ~1;

sys/dev/pci/mpt_pci.c

197

pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, reg);

sys/dev/pci/mvsata_pci.c

156

uint32_t reg, mask;

sys/dev/pci/mvsata_pci.c

212

reg = bus_space_read_4(psc->psc_iot, psc->psc_ioh, MVSATA_PCI_RESETCFG);

sys/dev/pci/mvsata_pci.c

213

read_pre_amps = (reg & 0x00000001) ? 1 : 0;

sys/dev/pci/nfsmb.c

139

pcireg_t reg;

sys/dev/pci/nfsmb.c

167

reg = pci_conf_read(pa->pa_pc, pa->pa_tag, baseregs[0]);

sys/dev/pci/nfsmb.c

169

nfsmbca.nfsmb_addr = NFORCE_SMBBASE(reg);

sys/dev/pci/nfsmb.c

173

reg = pci_conf_read(pa->pa_pc, pa->pa_tag, baseregs[1]);

sys/dev/pci/nfsmb.c

175

nfsmbca.nfsmb_addr = NFORCE_SMBBASE(reg);

sys/dev/pci/njs_pci.c

126

pcireg_t reg;

sys/dev/pci/njs_pci.c

142

reg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);

sys/dev/pci/njs_pci.c

143

reg |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE |

sys/dev/pci/njs_pci.c

145

pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, reg);

sys/dev/pci/nvme_pci.c

153

pcireg_t memtype, reg;

sys/dev/pci/nvme_pci.c

177

reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);

sys/dev/pci/nvme_pci.c

178

if (((reg & PCI_COMMAND_MASTER_ENABLE) == 0) ||

sys/dev/pci/nvme_pci.c

179

((reg & PCI_COMMAND_MEM_ENABLE) == 0)) {

sys/dev/pci/nvme_pci.c

184

reg |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_MEM_ENABLE;

sys/dev/pci/nvme_pci.c

186

reg);

sys/dev/pci/pccbb.c

106

#define Pcic_read(sc, reg) pccbb_pcmcia_read((sc), (reg))

sys/dev/pci/pccbb.c

107

#define Pcic_write(sc, reg, val) pccbb_pcmcia_write((sc), (reg), (val))

sys/dev/pci/pccbb.c

1160

pccbb_pcmcia_read(struct pccbb_softc *sc, int reg)

sys/dev/pci/pccbb.c

1163

PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ);

sys/dev/pci/pccbb.c

1166

PCCBB_PCMCIA_OFFSET + reg);

sys/dev/pci/pccbb.c

1170

pccbb_pcmcia_write(struct pccbb_softc *sc, int reg, uint8_t val)

sys/dev/pci/pccbb.c

1173

PCCBB_PCMCIA_OFFSET + reg, val);

sys/dev/pci/pccbb.c

1176

PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE);

sys/dev/pci/pccbb.c

1758

pcireg_t reg;

sys/dev/pci/pccbb.c

1794

reg = pci_conf_read(sc->sc_pc, sc->sc_tag,

sys/dev/pci/pccbb.c

1796

reg |= CB_BCR_INTR_IREQ_ENABLE;

sys/dev/pci/pccbb.c

1798

reg);

sys/dev/pci/pccbb.c

1802

reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL);

sys/dev/pci/pccbb.c

1804

reg &= ~PCI113X_CBCTRL_PCI_INTR;

sys/dev/pci/pccbb.c

1805

pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg);

sys/dev/pci/pccbb.c

1872

pcireg_t reg;

sys/dev/pci/pccbb.c

1880

reg = pci_conf_read(sc->sc_pc, tag, offset);

sys/dev/pci/pccbb.c

1885

return reg;

sys/dev/pci/pccbb.c

1895

pccbb_conf_write(cardbus_chipset_tag_t cc, pcitag_t tag, int reg, pcireg_t val)

sys/dev/pci/pccbb.c

1899

pci_conf_write(sc->sc_pc, tag, reg, val);

sys/dev/pci/pccbb.c

2193

int reg;

sys/dev/pci/pccbb.c

2198

reg = Pcic_read(sc, PCIC_ADDRWIN_ENABLE);

sys/dev/pci/pccbb.c

2201

reg &= ~PCIC_ADDRWIN_ENABLE_IO0;

sys/dev/pci/pccbb.c

2204

reg &= ~PCIC_ADDRWIN_ENABLE_IO1;

sys/dev/pci/pccbb.c

2207

Pcic_write(sc, PCIC_ADDRWIN_ENABLE, reg);

sys/dev/pci/pccbb.c

2271

int reg;

sys/dev/pci/pccbb.c

2334

reg = Pcic_read(sc, PCIC_IF_STATUS);

sys/dev/pci/pccbb.c

2335

if ((reg & PCIC_IF_STATUS_POWERACTIVE) == 0)

sys/dev/pci/pccbb.c

2337

reg);

sys/dev/pci/pccbb.c

2559

int reg;

sys/dev/pci/pccbb.c

2611

reg = Pcic_read(sc, PCIC_ADDRWIN_ENABLE);

sys/dev/pci/pccbb.c

2612

reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16);

sys/dev/pci/pccbb.c

2613

Pcic_write(sc, PCIC_ADDRWIN_ENABLE, reg);

sys/dev/pci/pccbb.c

2728

int reg;

sys/dev/pci/pccbb.c

2733

reg = Pcic_read(sc, PCIC_ADDRWIN_ENABLE);

sys/dev/pci/pccbb.c

2734

reg &= ~(1 << window);

sys/dev/pci/pccbb.c

2735

Pcic_write(sc, PCIC_ADDRWIN_ENABLE, reg);

sys/dev/pci/pccbb.c

3116

pcireg_t reg;

sys/dev/pci/pccbb.c

3122

reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK);

sys/dev/pci/pccbb.c

3124

reg &= ~(CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER);

sys/dev/pci/pccbb.c

3125

bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg);

sys/dev/pci/pccbb.c

3151

pcireg_t reg;

sys/dev/pci/pccbb.c

3160

reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK);

sys/dev/pci/pccbb.c

3162

reg |= CB_SOCKET_MASK_CSTS | CB_SOCKET_MASK_CD | CB_SOCKET_MASK_POWER;

sys/dev/pci/pccbb.c

3163

bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg);

sys/dev/pci/pccbb.c

3165

reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT);

sys/dev/pci/pccbb.c

3166

bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg);

sys/dev/pci/pccbb.c

380

pcireg_t reg, sock_base;

sys/dev/pci/pccbb.c

489

reg = pci_conf_read(pc, pa->pa_tag, PCI_BRIDGE_CONTROL_REG);

sys/dev/pci/pccbb.c

490

reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA);

sys/dev/pci/pccbb.c

491

pci_conf_write(pc, pa->pa_tag, PCI_BRIDGE_CONTROL_REG, reg);

sys/dev/pci/pci.c

1032

if (val != pcs->reg[off])

sys/dev/pci/pci.c

1033

pci_conf_write(pc, tag, (off * 4), pcs->reg[off]);

sys/dev/pci/pci.c

1074

pcireg_t reg;

sys/dev/pci/pci.c

1078

reg = pci_conf_read(pc, tag, off + PCI_MSI_CTL);

sys/dev/pci/pci.c

1080

reg & ~PCI_MSI_CTL_MSI_ENABLE);

sys/dev/pci/pci.c

1363

pcireg_t reg;

sys/dev/pci/pci.c

1378

PCI_CAP_PWRMGMT, &off, &reg)) {

sys/dev/pci/pci.c

1381

priv->p_pm_cap = reg;

sys/dev/pci/pci.c

529

pcireg_t reg;

sys/dev/pci/pci.c

532

reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);

sys/dev/pci/pci.c

533

if (!(reg & PCI_STATUS_CAPLIST_SUPPORT))

sys/dev/pci/pci.c

537

reg = pci_conf_read(pc, tag, PCI_BHLC_REG);

sys/dev/pci/pci.c

538

switch (PCI_HDRTYPE_TYPE(reg)) {

sys/dev/pci/pci.c

561

reg = pci_conf_read(pc, tag, ofs);

sys/dev/pci/pci.c

562

if (PCI_CAPLIST_CAP(reg) == capid) {

sys/dev/pci/pci.c

566

*value = reg;

sys/dev/pci/pci.c

569

ofs = PCI_CAPLIST_NEXT(reg);

sys/dev/pci/pci.c

579

pcireg_t reg;

sys/dev/pci/pci.c

590

reg = pci_conf_read(pc, tag, ofs);

sys/dev/pci/pci.c

591

if (PCI_HT_CAP(reg) == capid) {

sys/dev/pci/pci.c

595

*value = reg;

sys/dev/pci/pci.c

598

ofs = PCI_CAPLIST_NEXT(reg);

sys/dev/pci/pci.c

611

pcireg_t reg;

sys/dev/pci/pci.c

618

reg = pci_conf_read(pc, tag, offset + PCI_MSI_CTL);

sys/dev/pci/pci.c

619

mmc = PCI_MSI_CTL_MMC(reg);

sys/dev/pci/pci.c

636

pcireg_t reg;

sys/dev/pci/pci.c

642

reg = pci_conf_read(pc, tag, offset + PCI_MSIX_CTL);

sys/dev/pci/pci.c

644

return PCI_MSIX_CTL_TBLSIZE(reg);

sys/dev/pci/pci.c

651

pcireg_t reg;

sys/dev/pci/pci.c

659

reg = pci_conf_read(pc, tag, ofs);

sys/dev/pci/pci.c

660

if (reg == 0xffffffff || reg == 0)

sys/dev/pci/pci.c

668

if (PCI_EXTCAPLIST_CAP(reg) == capid) {

sys/dev/pci/pci.c

672

*value = reg;

sys/dev/pci/pci.c

675

ofs = PCI_EXTCAPLIST_NEXT(reg);

sys/dev/pci/pci.c

678

reg = pci_conf_read(pc, tag, ofs);

sys/dev/pci/pci.c

765

pcireg_t pciecap, capreg, reg;

sys/dev/pci/pci.c

777

reg = pci_conf_read(ppbpc, ppbtag, pciecap

sys/dev/pci/pci.c

779

if ((reg & PCIE_DCSR2_ARI_FWD) != 0)

sys/dev/pci/pci.c

869

uint32_t reg;

sys/dev/pci/pci.c

875

if (pci_get_capability(pc, tag, PCI_CAP_VPD, &ofs, &reg) == 0)

sys/dev/pci/pci.c

879

reg &= 0x0000ffff;

sys/dev/pci/pci.c

880

reg &= ~PCI_VPD_OPFLAG;

sys/dev/pci/pci.c

881

reg |= PCI_VPD_ADDRESS(offset);

sys/dev/pci/pci.c

882

pci_conf_write(pc, tag, ofs, reg);

sys/dev/pci/pci.c

893

reg = pci_conf_read(pc, tag, ofs);

sys/dev/pci/pci.c

894

} while ((reg & PCI_VPD_OPFLAG) == 0);

sys/dev/pci/pci.c

905

pcireg_t reg;

sys/dev/pci/pci.c

911

if (pci_get_capability(pc, tag, PCI_CAP_VPD, &ofs, &reg) == 0)

sys/dev/pci/pci.c

917

reg &= 0x0000ffff;

sys/dev/pci/pci.c

918

reg |= PCI_VPD_OPFLAG;

sys/dev/pci/pci.c

919

reg |= PCI_VPD_ADDRESS(offset);

sys/dev/pci/pci.c

920

pci_conf_write(pc, tag, ofs, reg);

sys/dev/pci/pci.c

931

reg = pci_conf_read(pc, tag, ofs);

sys/dev/pci/pci.c

932

} while (reg & PCI_VPD_OPFLAG);

sys/dev/pci/pci.c

955

pcs->reg[off] = pci_conf_read(pc, tag, (off * 4));

sys/dev/pci/pci_map.c

113

pci_mem_find(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t type,

sys/dev/pci/pci_map.c

122

isrom = (reg == PCI_MAPREG_ROM);

sys/dev/pci/pci_map.c

124

if ((!isrom) && (reg < PCI_MAPREG_START ||

sys/dev/pci/pci_map.c

130

reg >= PCI_MAPREG_END ||

sys/dev/pci/pci_map.c

132

(reg & 3)))

sys/dev/pci/pci_map.c

135

if (is64bit && (reg + 4) >= PCI_MAPREG_END)

sys/dev/pci/pci_map.c

150

address = pci_conf_read(pc, tag, reg);

sys/dev/pci/pci_map.c

159

pci_conf_write(pc, tag, reg, 0xffffffff);

sys/dev/pci/pci_map.c

160

mask = pci_conf_read(pc, tag, reg);

sys/dev/pci/pci_map.c

161

pci_conf_write(pc, tag, reg, address);

sys/dev/pci/pci_map.c

163

address1 = pci_conf_read(pc, tag, reg + 4);

sys/dev/pci/pci_map.c

165

pci_conf_write(pc, tag, reg + 4, 0xffffffff);

sys/dev/pci/pci_map.c

166

mask1 = pci_conf_read(pc, tag, reg + 4);

sys/dev/pci/pci_map.c

167

pci_conf_write(pc, tag, reg + 4, address1);

sys/dev/pci/pci_map.c

298

int reg, struct pci_ea_entry *entryp)

sys/dev/pci/pci_map.c

307

if (reg >= PCI_BAR0 && reg <= PCI_BAR5)

sys/dev/pci/pci_map.c

308

wanted_bei = PCI_EA_BEI_BAR0 + ((reg - PCI_BAR0) / 4);

sys/dev/pci/pci_map.c

309

else if (reg == PCI_MAPREG_ROM)

sys/dev/pci/pci_map.c

393

int reg, pcireg_t type, bus_addr_t *basep, bus_size_t *sizep, int *flagsp,

sys/dev/pci/pci_map.c

398

int rv = pci_ea_lookup(pc, tag, ea_cap_ptr, reg, &entry);

sys/dev/pci/pci_map.c

49

pci_io_find(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t type,

sys/dev/pci/pci_map.c

493

#define _PCI_MAPREG_TYPEBITS(reg) \

sys/dev/pci/pci_map.c

494

(PCI_MAPREG_TYPE(reg) == PCI_MAPREG_TYPE_IO ? \

sys/dev/pci/pci_map.c

495

reg & PCI_MAPREG_TYPE_MASK : \

sys/dev/pci/pci_map.c

496

reg & (PCI_MAPREG_TYPE_MASK|PCI_MAPREG_MEM_TYPE_MASK))

sys/dev/pci/pci_map.c

499

pci_mapreg_type(pci_chipset_tag_t pc, pcitag_t tag, int reg)

sys/dev/pci/pci_map.c

502

return _PCI_MAPREG_TYPEBITS(pci_conf_read(pc, tag, reg));

sys/dev/pci/pci_map.c

506

pci_mapreg_probe(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t *typep)

sys/dev/pci/pci_map.c

512

address = pci_conf_read(pc, tag, reg);

sys/dev/pci/pci_map.c

526

pci_conf_write(pc, tag, reg, 0xffffffff);

sys/dev/pci/pci_map.c

527

mask = pci_conf_read(pc, tag, reg);

sys/dev/pci/pci_map.c

528

pci_conf_write(pc, tag, reg, address);

sys/dev/pci/pci_map.c

541

pci_mapreg_info(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t type,

sys/dev/pci/pci_map.c

547

return pci_ea_find(pc, tag, ea_cap_ptr, reg, type,

sys/dev/pci/pci_map.c

55

if (reg < PCI_MAPREG_START ||

sys/dev/pci/pci_map.c

551

return pci_io_find(pc, tag, reg, type, basep, sizep,

sys/dev/pci/pci_map.c

554

return pci_mem_find(pc, tag, reg, type, basep, sizep,

sys/dev/pci/pci_map.c

559

pci_mapreg_map(const struct pci_attach_args *pa, int reg, pcireg_t type,

sys/dev/pci/pci_map.c

563

return pci_mapreg_submap(pa, reg, type, busflags, 0, 0, tagp,

sys/dev/pci/pci_map.c

568

pci_mapreg_submap(const struct pci_attach_args *pa, int reg, pcireg_t type,

sys/dev/pci/pci_map.c

595

if (pci_ea_find(pa->pa_pc, pa->pa_tag, ea_cap_ptr, reg, type,

sys/dev/pci/pci_map.c

598

if (reg != PCI_MAPREG_ROM && !entry.enabled) {

sys/dev/pci/pci_map.c

606

if (pci_io_find(pa->pa_pc, pa->pa_tag, reg, type,

sys/dev/pci/pci_map.c

61

reg >= PCI_MAPREG_END ||

sys/dev/pci/pci_map.c

610

if (pci_mem_find(pa->pa_pc, pa->pa_tag, reg, type,

sys/dev/pci/pci_map.c

616

if (reg == PCI_MAPREG_ROM) {

sys/dev/pci/pci_map.c

629

pci_conf_read(pa->pa_pc, pa->pa_tag, reg);

sys/dev/pci/pci_map.c

63

(reg & 3))

sys/dev/pci/pci_map.c

632

pci_conf_write(pa->pa_pc, pa->pa_tag, reg,

sys/dev/pci/pci_map.c

77

address = pci_conf_read(pc, tag, reg);

sys/dev/pci/pci_map.c

86

pci_conf_write(pc, tag, reg, 0xffffffff);

sys/dev/pci/pci_map.c

87

mask = pci_conf_read(pc, tag, reg);

sys/dev/pci/pci_map.c

88

pci_conf_write(pc, tag, reg, address);

sys/dev/pci/pci_subr.c

1005

rval = regs[o2i(reg)];

sys/dev/pci/pci_subr.c

1008

rval64h = regs[o2i(reg + 4)];

sys/dev/pci/pci_subr.c

1027

pci_conf_write(pc, tag, reg, 0xffffffff);

sys/dev/pci/pci_subr.c

1028

mask = pci_conf_read(pc, tag, reg);

sys/dev/pci/pci_subr.c

1029

pci_conf_write(pc, tag, reg, rval);

sys/dev/pci/pci_subr.c

1032

pci_conf_write(pc, tag, reg + 4, 0xffffffff);

sys/dev/pci/pci_subr.c

1033

mask64h = pci_conf_read(pc, tag, reg + 4);

sys/dev/pci/pci_subr.c

1034

pci_conf_write(pc, tag, reg + 4, rval64h);

sys/dev/pci/pci_subr.c

1041

printf(" Base address register at 0x%02x", reg);

sys/dev/pci/pci_subr.c

1162

pci_conf_print_agp_datarate(pcireg_t reg, bool isagp3)

sys/dev/pci/pci_subr.c

1166

if (reg & AGP_MODE_V3_RATE_4x)

sys/dev/pci/pci_subr.c

1168

if (reg & AGP_MODE_V3_RATE_8x)

sys/dev/pci/pci_subr.c

1172

if (reg & AGP_MODE_V2_RATE_1x)

sys/dev/pci/pci_subr.c

1174

if (reg & AGP_MODE_V2_RATE_2x)

sys/dev/pci/pci_subr.c

1176

if (reg & AGP_MODE_V2_RATE_4x)

sys/dev/pci/pci_subr.c

1408

pcireg_t reg;

sys/dev/pci/pci_subr.c

1417

reg = regs[o2i(capoff)];

sys/dev/pci/pci_subr.c

1420

(reg & 0xffff0000) >> 16);

sys/dev/pci/pci_subr.c

1421

onoff("64bit device", reg, PCIX_STATUS_64BIT);

sys/dev/pci/pci_subr.c

1422

onoff("133MHz capable", reg, PCIX_STATUS_133);

sys/dev/pci/pci_subr.c

1423

onoff("Split completion discarded", reg, PCIX_STATUS_SPLDISC);

sys/dev/pci/pci_subr.c

1424

onoff("Unexpected split completion", reg, PCIX_STATUS_SPLUNEX);

sys/dev/pci/pci_subr.c

1425

onoff("Split completion overrun", reg, PCIX_BRIDGE_ST_SPLOVRN);

sys/dev/pci/pci_subr.c

1426

onoff("Split request delayed", reg, PCIX_BRIDGE_ST_SPLRQDL);

sys/dev/pci/pci_subr.c

1428

PCIREG_SHIFTOUT(reg, PCIX_BRIDGE_2NDST_CLKF));

sys/dev/pci/pci_subr.c

1430

(reg & PCIX_BRIDGE_2NDST_VER_MASK)

sys/dev/pci/pci_subr.c

1432

onoff("266MHz capable", reg, PCIX_BRIDGE_ST_266);

sys/dev/pci/pci_subr.c

1433

onoff("533MHz capable", reg, PCIX_BRIDGE_ST_533);

sys/dev/pci/pci_subr.c

1436

(reg & 0xffff0000) >> 16);

sys/dev/pci/pci_subr.c

1437

onoff("Data Parity Error Recovery", reg,

sys/dev/pci/pci_subr.c

1439

onoff("Enable Relaxed Ordering", reg, PCIX_CMD_RELAXED_ORDER);

sys/dev/pci/pci_subr.c

1441

PCIX_CMD_BYTECNT(reg));

sys/dev/pci/pci_subr.c

1443

pcix_split_trans((reg & PCIX_CMD_SPLTRANS_MASK)

sys/dev/pci/pci_subr.c

1446

reg = regs[o2i(capoff+PCIX_STATUS)]; /* Or PCIX_BRIDGE_PRI_STATUS */

sys/dev/pci/pci_subr.c

1448

isbridge ? "Bridge " : "", reg);

sys/dev/pci/pci_subr.c

1449

printf(" Function: %d\n", PCIX_STATUS_FN(reg));

sys/dev/pci/pci_subr.c

1450

printf(" Device: %d\n", PCIX_STATUS_DEV(reg));

sys/dev/pci/pci_subr.c

1451

printf(" Bus: %d\n", PCIX_STATUS_BUS(reg));

sys/dev/pci/pci_subr.c

1452

onoff("64bit device", reg, PCIX_STATUS_64BIT);

sys/dev/pci/pci_subr.c

1453

onoff("133MHz capable", reg, PCIX_STATUS_133);

sys/dev/pci/pci_subr.c

1454

onoff("Split completion discarded", reg, PCIX_STATUS_SPLDISC);

sys/dev/pci/pci_subr.c

1455

onoff("Unexpected split completion", reg, PCIX_STATUS_SPLUNEX);

sys/dev/pci/pci_subr.c

1457

onoff("Split completion overrun", reg, PCIX_BRIDGE_ST_SPLOVRN);

sys/dev/pci/pci_subr.c

1458

onoff("Split request delayed", reg, PCIX_BRIDGE_ST_SPLRQDL);

sys/dev/pci/pci_subr.c

1460

onoff2("Device Complexity", reg, PCIX_STATUS_DEVCPLX,

sys/dev/pci/pci_subr.c

1463

512 << ((reg & PCIX_STATUS_MAXB_MASK)

sys/dev/pci/pci_subr.c

1466

pcix_split_trans((reg & PCIX_STATUS_MAXST_MASK)

sys/dev/pci/pci_subr.c

1469

8 << ((reg & 0x1c000000) >> PCIX_STATUS_MAXRS_SHIFT));

sys/dev/pci/pci_subr.c

1470

onoff("Received split completion error", reg,

sys/dev/pci/pci_subr.c

1473

onoff("266MHz capable", reg, PCIX_STATUS_266);

sys/dev/pci/pci_subr.c

1474

onoff("533MHz capable", reg, PCIX_STATUS_533);

sys/dev/pci/pci_subr.c

1481

reg = regs[o2i(capoff + PCIX_BRIDGE_UP_STCR + (4 * i))];

sys/dev/pci/pci_subr.c

1483

(i == 0) ? "Upstream" : "Downstream", reg);

sys/dev/pci/pci_subr.c

1484

printf(" Capacity: %d\n", reg & PCIX_BRIDGE_STCAP);

sys/dev/pci/pci_subr.c

1486

(reg & PCIX_BRIDGE_STCLIM) >> PCIX_BRIDGE_STCLIM_SHIFT);

sys/dev/pci/pci_subr.c

1614

pcireg_t reg;

sys/dev/pci/pci_subr.c

1616

reg = regs[o2i(capoff + PCI_CAP_SUBSYS_ID)];

sys/dev/pci/pci_subr.c

1619

printf(" Subsystem ID: 0x%08x\n", reg);

sys/dev/pci/pci_subr.c

1626

pcireg_t reg, reg2, val;

sys/dev/pci/pci_subr.c

1630

reg = regs[o2i(capoff + PCI_SECURE_CAP)];

sys/dev/pci/pci_subr.c

1631

printf(" Capability Register: 0x%04x\n", reg >> 16);

sys/dev/pci/pci_subr.c

1632

val = PCIREG_SHIFTOUT(reg, PCI_SECURE_CAP_TYPE);

sys/dev/pci/pci_subr.c

1642

val = PCIREG_SHIFTOUT(reg, PCI_SECURE_CAP_REV);

sys/dev/pci/pci_subr.c

1650

onoff("IOTLB support", reg, PCI_SECURE_CAP_IOTLBSUP);

sys/dev/pci/pci_subr.c

1651

onoff("HyperTransport tunnel translation support", reg,

sys/dev/pci/pci_subr.c

1653

onoff("Not present table entries cached", reg, PCI_SECURE_CAP_NPCACHE);

sys/dev/pci/pci_subr.c

1654

onoff("IOMMU Extended Feature Register support", reg,

sys/dev/pci/pci_subr.c

1656

onoff("IOMMU Miscellaneous Information Register 1", reg,

sys/dev/pci/pci_subr.c

1658

havemisc1 = reg & PCI_SECURE_CAP_EXT;

sys/dev/pci/pci_subr.c

1660

reg = regs[o2i(capoff + PCI_SECURE_IOMMU_BAL)];

sys/dev/pci/pci_subr.c

1661

printf(" Base Address Low Register: 0x%08x\n", reg);

sys/dev/pci/pci_subr.c

1662

onoff("Enable", reg, PCI_SECURE_IOMMU_BAL_EN);

sys/dev/pci/pci_subr.c

1667

| (reg & (PCI_SECURE_IOMMU_BAL_H | PCI_SECURE_IOMMU_BAL_L)));

sys/dev/pci/pci_subr.c

1669

reg = regs[o2i(capoff + PCI_SECURE_IOMMU_RANGE)];

sys/dev/pci/pci_subr.c

1670

printf(" IOMMU Range Register: 0x%08x\n", reg);

sys/dev/pci/pci_subr.c

1672

PCIREG_SHIFTOUT(reg, PCI_SECURE_IOMMU_RANGE_UNITID));

sys/dev/pci/pci_subr.c

1673

onoff("Range valid", reg, PCI_SECURE_IOMMU_RANGE_RNGVALID);

sys/dev/pci/pci_subr.c

1675

PCIREG_SHIFTOUT(reg, PCI_SECURE_IOMMU_RANGE_BUSNUM));

sys/dev/pci/pci_subr.c

1677

PCIREG_SHIFTOUT(reg, PCI_SECURE_IOMMU_RANGE_FIRSTDEV));

sys/dev/pci/pci_subr.c

1679

PCIREG_SHIFTOUT(reg, PCI_SECURE_IOMMU_RANGE_LASTDEV));

sys/dev/pci/pci_subr.c

1681

reg = regs[o2i(capoff + PCI_SECURE_IOMMU_MISC0)];

sys/dev/pci/pci_subr.c

1682

printf(" Miscellaneous Information Register 0: 0x%08x\n", reg);

sys/dev/pci/pci_subr.c

1684

PCIREG_SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC0_MSINUM));

sys/dev/pci/pci_subr.c

1685

val = PCIREG_SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC0_GVASIZE);

sys/dev/pci/pci_subr.c

1691

val = PCIREG_SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC0_PASIZE);

sys/dev/pci/pci_subr.c

1693

val = PCIREG_SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC0_VASIZE);

sys/dev/pci/pci_subr.c

1695

onoff("ATS response address range reserved", reg,

sys/dev/pci/pci_subr.c

1698

PCIREG_SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC0_MISNPPR));

sys/dev/pci/pci_subr.c

1703

reg = regs[o2i(capoff + PCI_SECURE_IOMMU_MISC1)];

sys/dev/pci/pci_subr.c

1704

printf(" Miscellaneous Information Register 1: 0x%08x\n", reg);

sys/dev/pci/pci_subr.c

1706

PCIREG_SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC1_MSINUM));

sys/dev/pci/pci_subr.c

1890

pcireg_t reg; /* for each register */

sys/dev/pci/pci_subr.c

1900

reg = regs[o2i(capoff)];

sys/dev/pci/pci_subr.c

1901

printf(" Capability register: 0x%04x\n", reg >> 16);

sys/dev/pci/pci_subr.c

1902

pciever = (unsigned int)(PCIE_XCAP_VER(reg));

sys/dev/pci/pci_subr.c

1905

pcie_devtype = PCIE_XCAP_TYPE(reg);

sys/dev/pci/pci_subr.c

1946

onoff("Slot implemented", reg, PCIE_XCAP_SI);

sys/dev/pci/pci_subr.c

1948

PCIREG_SHIFTOUT(reg, PCIE_XCAP_IRQ));

sys/dev/pci/pci_subr.c

1951

reg = regs[o2i(capoff + PCIE_DCAP)];

sys/dev/pci/pci_subr.c

1952

printf(" Device Capabilities Register: 0x%08x\n", reg);

sys/dev/pci/pci_subr.c

1954

128 << (unsigned int)(reg & PCIE_DCAP_MAX_PAYLOAD));

sys/dev/pci/pci_subr.c

1956

switch (PCIREG_SHIFTOUT(reg, PCIE_DCAP_PHANTOM_FUNCS)) {

sys/dev/pci/pci_subr.c

1971

(reg & PCIE_DCAP_EXT_TAG_FIELD) == 0 ? 5 : 8);

sys/dev/pci/pci_subr.c

1973

pci_print_pcie_L0s_latency(PCIREG_SHIFTOUT(reg, PCIE_DCAP_L0S_LATENCY));

sys/dev/pci/pci_subr.c

1975

pci_print_pcie_L1_latency(PCIREG_SHIFTOUT(reg, PCIE_DCAP_L1_LATENCY));

sys/dev/pci/pci_subr.c

1976

onoff("Attention Button Present", reg, PCIE_DCAP_ATTN_BUTTON);

sys/dev/pci/pci_subr.c

1977

onoff("Attention Indicator Present", reg, PCIE_DCAP_ATTN_IND);

sys/dev/pci/pci_subr.c

1978

onoff("Power Indicator Present", reg, PCIE_DCAP_PWR_IND);

sys/dev/pci/pci_subr.c

1979

onoff("Role-Based Error Report", reg, PCIE_DCAP_ROLE_ERR_RPT);

sys/dev/pci/pci_subr.c

1983

PCIREG_SHIFTOUT(reg, PCIE_DCAP_SLOT_PWR_LIM_VAL),

sys/dev/pci/pci_subr.c

1984

PCIREG_SHIFTOUT(reg, PCIE_DCAP_SLOT_PWR_LIM_SCALE));

sys/dev/pci/pci_subr.c

1986

onoff("Function-Level Reset Capability", reg, PCIE_DCAP_FLR);

sys/dev/pci/pci_subr.c

1989

reg = regs[o2i(capoff + PCIE_DCSR)];

sys/dev/pci/pci_subr.c

1990

printf(" Device Control Register: 0x%04x\n", reg & 0xffff);

sys/dev/pci/pci_subr.c

1991

onoff("Correctable Error Reporting Enable", reg,

sys/dev/pci/pci_subr.c

1993

onoff("Non Fatal Error Reporting Enable", reg, PCIE_DCSR_ENA_NFER);

sys/dev/pci/pci_subr.c

1994

onoff("Fatal Error Reporting Enable", reg, PCIE_DCSR_ENA_FER);

sys/dev/pci/pci_subr.c

1995

onoff("Unsupported Request Reporting Enable", reg, PCIE_DCSR_ENA_URR);

sys/dev/pci/pci_subr.c

1996

onoff("Enable Relaxed Ordering", reg, PCIE_DCSR_ENA_RELAX_ORD);

sys/dev/pci/pci_subr.c

1998

128 << PCIREG_SHIFTOUT(reg, PCIE_DCSR_MAX_PAYLOAD));

sys/dev/pci/pci_subr.c

1999

onoff("Extended Tag Field Enable", reg, PCIE_DCSR_EXT_TAG_FIELD);

sys/dev/pci/pci_subr.c

2000

onoff("Phantom Functions Enable", reg, PCIE_DCSR_PHANTOM_FUNCS);

sys/dev/pci/pci_subr.c

2001

onoff("Aux Power PM Enable", reg, PCIE_DCSR_AUX_POWER_PM);

sys/dev/pci/pci_subr.c

2002

onoff("Enable No Snoop", reg, PCIE_DCSR_ENA_NO_SNOOP);

sys/dev/pci/pci_subr.c

2004

128 << PCIREG_SHIFTOUT(reg, PCIE_DCSR_MAX_READ_REQ));

sys/dev/pci/pci_subr.c

2006

onoff("Bridge Config Retry Enable", reg,

sys/dev/pci/pci_subr.c

2010

reg = regs[o2i(capoff + PCIE_DCSR)];

sys/dev/pci/pci_subr.c

2011

printf(" Device Status Register: 0x%04x\n", reg >> 16);

sys/dev/pci/pci_subr.c

2012

onoff("Correctable Error Detected", reg, PCIE_DCSR_CED);

sys/dev/pci/pci_subr.c

2013

onoff("Non Fatal Error Detected", reg, PCIE_DCSR_NFED);

sys/dev/pci/pci_subr.c

2014

onoff("Fatal Error Detected", reg, PCIE_DCSR_FED);

sys/dev/pci/pci_subr.c

2015

onoff("Unsupported Request Detected", reg, PCIE_DCSR_URD);

sys/dev/pci/pci_subr.c

2016

onoff("Aux Power Detected", reg, PCIE_DCSR_AUX_PWR);

sys/dev/pci/pci_subr.c

2017

onoff("Transaction Pending", reg, PCIE_DCSR_TRANSACTION_PND);

sys/dev/pci/pci_subr.c

2018

onoff("Emergency Power Reduction Detected", reg, PCIE_DCSR_EMGPWRREDD);

sys/dev/pci/pci_subr.c

2022

reg = regs[o2i(capoff + PCIE_LCAP)];

sys/dev/pci/pci_subr.c

2023

printf(" Link Capabilities Register: 0x%08x\n", reg);

sys/dev/pci/pci_subr.c

2025

pci_print_pcie_linkspeed(PCIE_LCAP, reg & PCIE_LCAP_MAX_SPEED);

sys/dev/pci/pci_subr.c

2027

PCIREG_SHIFTOUT(reg, PCIE_LCAP_MAX_WIDTH));

sys/dev/pci/pci_subr.c

2029

switch (PCIREG_SHIFTOUT(reg, PCIE_LCAP_ASPM)) {

sys/dev/pci/pci_subr.c

2044

pci_print_pcie_L0s_latency(PCIREG_SHIFTOUT(reg,PCIE_LCAP_L0S_EXIT));

sys/dev/pci/pci_subr.c

2046

pci_print_pcie_L1_latency(PCIREG_SHIFTOUT(reg, PCIE_LCAP_L1_EXIT));

sys/dev/pci/pci_subr.c

2048

PCIREG_SHIFTOUT(reg, PCIE_LCAP_PORT));

sys/dev/pci/pci_subr.c

2049

onoff("Clock Power Management", reg, PCIE_LCAP_CLOCK_PM);

sys/dev/pci/pci_subr.c

2050

onoff("Surprise Down Error Report", reg,

sys/dev/pci/pci_subr.c

2052

onoff("Data Link Layer Link Active", reg, PCIE_LCAP_DL_ACTIVE);

sys/dev/pci/pci_subr.c

2053

onoff("Link BW Notification Capable", reg,

sys/dev/pci/pci_subr.c

2055

onoff("ASPM Optionally Compliance", reg,

sys/dev/pci/pci_subr.c

2059

reg = regs[o2i(capoff + PCIE_LCSR)];

sys/dev/pci/pci_subr.c

2060

printf(" Link Control Register: 0x%04x\n", reg & 0xffff);

sys/dev/pci/pci_subr.c

2062

switch (reg & (PCIE_LCSR_ASPM_L1 | PCIE_LCSR_ASPM_L0S)) {

sys/dev/pci/pci_subr.c

2076

onoff2("Read Completion Boundary Control", reg, PCIE_LCSR_RCB,

sys/dev/pci/pci_subr.c

2078

onoff("Link Disable", reg, PCIE_LCSR_LINK_DIS);

sys/dev/pci/pci_subr.c

2079

onoff("Retrain Link", reg, PCIE_LCSR_RETRAIN);

sys/dev/pci/pci_subr.c

2080

onoff("Common Clock Configuration", reg, PCIE_LCSR_COMCLKCFG);

sys/dev/pci/pci_subr.c

2081

onoff("Extended Synch", reg, PCIE_LCSR_EXTNDSYNC);

sys/dev/pci/pci_subr.c

2082

onoff("Enable Clock Power Management", reg, PCIE_LCSR_ENCLKPM);

sys/dev/pci/pci_subr.c

2083

onoff("Hardware Autonomous Width Disable", reg,PCIE_LCSR_HAWD);

sys/dev/pci/pci_subr.c

2084

onoff("Link Bandwidth Management Interrupt Enable", reg,

sys/dev/pci/pci_subr.c

2086

onoff("Link Autonomous Bandwidth Interrupt Enable", reg,

sys/dev/pci/pci_subr.c

2089

switch (PCIREG_SHIFTOUT(reg, PCIE_LCSR_DRSSGNL)) {

sys/dev/pci/pci_subr.c

2105

reg = regs[o2i(capoff + PCIE_LCSR)];

sys/dev/pci/pci_subr.c

2106

printf(" Link Status Register: 0x%04x\n", reg >> 16);

sys/dev/pci/pci_subr.c

2109

PCIREG_SHIFTOUT(reg, PCIE_LCSR_LINKSPEED));

sys/dev/pci/pci_subr.c

2111

PCIREG_SHIFTOUT(reg, PCIE_LCSR_NLW));

sys/dev/pci/pci_subr.c

2112

onoff("Training Error", reg, PCIE_LCSR_LINKTRAIN_ERR);

sys/dev/pci/pci_subr.c

2113

onoff("Link Training", reg, PCIE_LCSR_LINKTRAIN);

sys/dev/pci/pci_subr.c

2114

onoff("Slot Clock Configuration", reg, PCIE_LCSR_SLOTCLKCFG);

sys/dev/pci/pci_subr.c

2115

onoff("Data Link Layer Link Active", reg, PCIE_LCSR_DLACTIVE);

sys/dev/pci/pci_subr.c

2116

onoff("Link Bandwidth Management Status", reg,

sys/dev/pci/pci_subr.c

2118

onoff("Link Autonomous Bandwidth Status", reg,

sys/dev/pci/pci_subr.c

2126

slcap = reg = regs[o2i(capoff + PCIE_SLCAP)];

sys/dev/pci/pci_subr.c

2127

printf(" Slot Capability Register: 0x%08x\n", reg);

sys/dev/pci/pci_subr.c

2128

onoff("Attention Button Present", reg, PCIE_SLCAP_ABP);

sys/dev/pci/pci_subr.c

2129

onoff("Power Controller Present", reg, PCIE_SLCAP_PCP);

sys/dev/pci/pci_subr.c

2130

onoff("MRL Sensor Present", reg, PCIE_SLCAP_MSP);

sys/dev/pci/pci_subr.c

2131

onoff("Attention Indicator Present", reg, PCIE_SLCAP_AIP);

sys/dev/pci/pci_subr.c

2132

onoff("Power Indicator Present", reg, PCIE_SLCAP_PIP);

sys/dev/pci/pci_subr.c

2133

onoff("Hot-Plug Surprise", reg, PCIE_SLCAP_HPS);

sys/dev/pci/pci_subr.c

2134

onoff("Hot-Plug Capable", reg, PCIE_SLCAP_HPC);

sys/dev/pci/pci_subr.c

2136

pci_conf_print_pcie_power(PCIREG_SHIFTOUT(reg, PCIE_SLCAP_SPLV),

sys/dev/pci/pci_subr.c

2137

PCIREG_SHIFTOUT(reg, PCIE_SLCAP_SPLS));

sys/dev/pci/pci_subr.c

2138

onoff("Electromechanical Interlock Present", reg,

sys/dev/pci/pci_subr.c

2140

onoff("No Command Completed Support", reg, PCIE_SLCAP_NCCS);

sys/dev/pci/pci_subr.c

2142

(unsigned int)(reg & PCIE_SLCAP_PSN) >> 19);

sys/dev/pci/pci_subr.c

2145

reg = regs[o2i(capoff + PCIE_SLCSR)];

sys/dev/pci/pci_subr.c

2146

printf(" Slot Control Register: 0x%04x\n", reg & 0xffff);

sys/dev/pci/pci_subr.c

2147

onoff("Attention Button Pressed Enabled", reg, PCIE_SLCSR_ABE);

sys/dev/pci/pci_subr.c

2148

onoff("Power Fault Detected Enabled", reg, PCIE_SLCSR_PFE);

sys/dev/pci/pci_subr.c

2149

onoff("MRL Sensor Changed Enabled", reg, PCIE_SLCSR_MSE);

sys/dev/pci/pci_subr.c

2150

onoff("Presence Detect Changed Enabled", reg, PCIE_SLCSR_PDE);

sys/dev/pci/pci_subr.c

2151

onoff("Command Completed Interrupt Enabled", reg,

sys/dev/pci/pci_subr.c

2153

onoff("Hot-Plug Interrupt Enabled", reg, PCIE_SLCSR_HPE);

sys/dev/pci/pci_subr.c

2161

switch ((reg & PCIE_SLCSR_AIC) >> 6) {

sys/dev/pci/pci_subr.c

2178

switch ((reg & PCIE_SLCSR_PIC) >> 8) {

sys/dev/pci/pci_subr.c

2194

reg & PCIE_SLCSR_PCC ? "off" : "on");

sys/dev/pci/pci_subr.c

2196

reg, PCIE_SLCSR_EIC);

sys/dev/pci/pci_subr.c

2197

onoff("Data Link Layer State Changed Enable", reg,

sys/dev/pci/pci_subr.c

2199

onoff("Auto Slot Power Limit Disable", reg,

sys/dev/pci/pci_subr.c

2203

printf(" Slot Status Register: 0x%04x\n", reg >> 16);

sys/dev/pci/pci_subr.c

2204

onoff("Attention Button Pressed", reg, PCIE_SLCSR_ABP);

sys/dev/pci/pci_subr.c

2205

onoff("Power Fault Detected", reg, PCIE_SLCSR_PFD);

sys/dev/pci/pci_subr.c

2206

onoff("MRL Sensor Changed", reg, PCIE_SLCSR_MSC);

sys/dev/pci/pci_subr.c

2207

onoff("Presence Detect Changed", reg, PCIE_SLCSR_PDC);

sys/dev/pci/pci_subr.c

2208

onoff("Command Completed", reg, PCIE_SLCSR_CC);

sys/dev/pci/pci_subr.c

2209

onoff("MRL Open", reg, PCIE_SLCSR_MS);

sys/dev/pci/pci_subr.c

2210

onoff("Card Present in slot", reg, PCIE_SLCSR_PDS);

sys/dev/pci/pci_subr.c

2211

onoff("Electromechanical Interlock engaged", reg,

sys/dev/pci/pci_subr.c

2213

onoff("Data Link Layer State Changed", reg, PCIE_SLCSR_LACS);

sys/dev/pci/pci_subr.c

2218

reg = regs[o2i(capoff + PCIE_RCR)];

sys/dev/pci/pci_subr.c

2219

printf(" Root Control Register: 0x%04x\n", reg & 0xffff);

sys/dev/pci/pci_subr.c

2220

onoff("SERR on Correctable Error Enable", reg,

sys/dev/pci/pci_subr.c

2222

onoff("SERR on Non-Fatal Error Enable", reg,

sys/dev/pci/pci_subr.c

2224

onoff("SERR on Fatal Error Enable", reg, PCIE_RCR_SERR_FER);

sys/dev/pci/pci_subr.c

2225

onoff("PME Interrupt Enable", reg, PCIE_RCR_PME_IE);

sys/dev/pci/pci_subr.c

2226

onoff("CRS Software Visibility Enable", reg, PCIE_RCR_CRS_SVE);

sys/dev/pci/pci_subr.c

2230

reg >> 16);

sys/dev/pci/pci_subr.c

2231

onoff("CRS Software Visibility", reg, PCIE_RCR_CRS_SV);

sys/dev/pci/pci_subr.c

2234

reg = regs[o2i(capoff + PCIE_RSR)];

sys/dev/pci/pci_subr.c

2235

printf(" Root Status Register: 0x%08x\n", reg);

sys/dev/pci/pci_subr.c

2237

(unsigned int)(reg & PCIE_RSR_PME_REQESTER));

sys/dev/pci/pci_subr.c

2238

onoff("PME was asserted", reg, PCIE_RSR_PME_STAT);

sys/dev/pci/pci_subr.c

2239

onoff("another PME is pending", reg, PCIE_RSR_PME_PEND);

sys/dev/pci/pci_subr.c

2247

reg = regs[o2i(capoff + PCIE_DCAP2)];

sys/dev/pci/pci_subr.c

2248

printf(" Device Capabilities 2: 0x%08x\n", reg);

sys/dev/pci/pci_subr.c

2250

val = reg & PCIE_DCAP2_COMPT_RANGE;

sys/dev/pci/pci_subr.c

2262

onoff("Completion Timeout Disable Supported", reg,

sys/dev/pci/pci_subr.c

2264

onoff("ARI Forwarding Supported", reg, PCIE_DCAP2_ARI_FWD);

sys/dev/pci/pci_subr.c

2265

onoff("AtomicOp Routing Supported", reg, PCIE_DCAP2_ATOM_ROUT);

sys/dev/pci/pci_subr.c

2266

onoff("32bit AtomicOp Completer Supported", reg, PCIE_DCAP2_32ATOM);

sys/dev/pci/pci_subr.c

2267

onoff("64bit AtomicOp Completer Supported", reg, PCIE_DCAP2_64ATOM);

sys/dev/pci/pci_subr.c

2268

onoff("128-bit CAS Completer Supported", reg, PCIE_DCAP2_128CAS);

sys/dev/pci/pci_subr.c

2269

onoff("No RO-enabled PR-PR passing", reg, PCIE_DCAP2_NO_ROPR_PASS);

sys/dev/pci/pci_subr.c

2270

onoff("LTR Mechanism Supported", reg, PCIE_DCAP2_LTR_MEC);

sys/dev/pci/pci_subr.c

2272

switch (PCIREG_SHIFTOUT(reg, PCIE_DCAP2_TPH_COMP)) {

sys/dev/pci/pci_subr.c

2287

switch (PCIREG_SHIFTOUT(reg, PCIE_DCAP2_LNSYSCLS)) {

sys/dev/pci/pci_subr.c

2301

onoff("10-bit Tag Completer Supported", reg, PCIE_DCAP2_TBT_COMP);

sys/dev/pci/pci_subr.c

2302

onoff("10-bit Tag Requester Supported", reg, PCIE_DCAP2_TBT_REQ);

sys/dev/pci/pci_subr.c

2304

switch (PCIREG_SHIFTOUT(reg, PCIE_DCAP2_OBFF)) {

sys/dev/pci/pci_subr.c

2318

onoff("Extended Fmt Field Supported", reg, PCIE_DCAP2_EXTFMT_FLD);

sys/dev/pci/pci_subr.c

2319

onoff("End-End TLP Prefix Supported", reg, PCIE_DCAP2_EETLP_PREF);

sys/dev/pci/pci_subr.c

2320

val = PCIREG_SHIFTOUT(reg, PCIE_DCAP2_MAX_EETLP);

sys/dev/pci/pci_subr.c

2323

switch (PCIREG_SHIFTOUT(reg, PCIE_DCAP2_EMGPWRRED)) {

sys/dev/pci/pci_subr.c

2337

onoff("Emergency Power Reduction Initialization Required", reg,

sys/dev/pci/pci_subr.c

2339

onoff("FRS Supported", reg, PCIE_DCAP2_FRS);

sys/dev/pci/pci_subr.c

2342

reg = regs[o2i(capoff + PCIE_DCSR2)];

sys/dev/pci/pci_subr.c

2343

printf(" Device Control 2: 0x%04x\n", reg & 0xffff);

sys/dev/pci/pci_subr.c

2345

pci_print_pcie_compl_timeout(reg & PCIE_DCSR2_COMPT_VAL);

sys/dev/pci/pci_subr.c

2346

onoff("Completion Timeout Disabled", reg, PCIE_DCSR2_COMPT_DIS);

sys/dev/pci/pci_subr.c

2347

onoff("ARI Forwarding Enabled", reg, PCIE_DCSR2_ARI_FWD);

sys/dev/pci/pci_subr.c

2348

onoff("AtomicOp Requester Enabled", reg, PCIE_DCSR2_ATOM_REQ);

sys/dev/pci/pci_subr.c

2349

onoff("AtomicOp Egress Blocking", reg, PCIE_DCSR2_ATOM_EBLK);

sys/dev/pci/pci_subr.c

2350

onoff("IDO Request Enabled", reg, PCIE_DCSR2_IDO_REQ);

sys/dev/pci/pci_subr.c

2351

onoff("IDO Completion Enabled", reg, PCIE_DCSR2_IDO_COMP);

sys/dev/pci/pci_subr.c

2352

onoff("LTR Mechanism Enabled", reg, PCIE_DCSR2_LTR_MEC);

sys/dev/pci/pci_subr.c

2353

onoff("Emergency Power Reduction Request", reg,

sys/dev/pci/pci_subr.c

2355

onoff("10-bit Tag Requester Enabled", reg, PCIE_DCSR2_TBT_REQ);

sys/dev/pci/pci_subr.c

2357

switch (PCIREG_SHIFTOUT(reg, PCIE_DCSR2_OBFF_EN)) {

sys/dev/pci/pci_subr.c

2371

onoff("End-End TLP Prefix Blocking on", reg, PCIE_DCSR2_EETLP);

sys/dev/pci/pci_subr.c

2377

reg = regs[o2i(capoff + PCIE_LCAP2)];

sys/dev/pci/pci_subr.c

2379

if ((reg & PCIE_LCAP2_SUP_LNKSV) != 0) {

sys/dev/pci/pci_subr.c

2380

printf(" Link Capabilities 2: 0x%08x\n", reg);

sys/dev/pci/pci_subr.c

2383

PCIREG_SHIFTOUT(reg, PCIE_LCAP2_SUP_LNKSV));

sys/dev/pci/pci_subr.c

2385

onoff("Crosslink Supported", reg, PCIE_LCAP2_CROSSLNK);

sys/dev/pci/pci_subr.c

2389

PCIREG_SHIFTOUT(reg, PCIE_LCAP2_LOWSKPOS_GENSUPPSV));

sys/dev/pci/pci_subr.c

2394

PCIREG_SHIFTOUT(reg, PCIE_LCAP2_LOWSKPOS_RECSUPPSV));

sys/dev/pci/pci_subr.c

2396

onoff("Retimer Presence Detect Supported", reg,

sys/dev/pci/pci_subr.c

2398

onoff("DRS Supported", reg, PCIE_LCAP2_DRS);

sys/dev/pci/pci_subr.c

2399

drs_supported = (reg & PCIE_LCAP2_DRS) ? true : false;

sys/dev/pci/pci_subr.c

2403

reg = regs[o2i(capoff + PCIE_LCSR2)];

sys/dev/pci/pci_subr.c

2405

printf(" Link Control 2: 0x%04x\n", reg & 0xffff);

sys/dev/pci/pci_subr.c

2408

PCIREG_SHIFTOUT(reg, PCIE_LCSR2_TGT_LSPEED));

sys/dev/pci/pci_subr.c

2409

onoff("Enter Compliance Enabled", reg, PCIE_LCSR2_ENT_COMPL);

sys/dev/pci/pci_subr.c

2410

onoff("HW Autonomous Speed Disabled", reg,

sys/dev/pci/pci_subr.c

2414

PCIREG_SHIFTOUT(reg, PCIE_LCSR2_SEL_DEEMP));

sys/dev/pci/pci_subr.c

2417

PCIREG_SHIFTOUT(reg, PCIE_LCSR2_TX_MARGIN));

sys/dev/pci/pci_subr.c

2418

onoff("Enter Modified Compliance", reg, PCIE_LCSR2_EN_MCOMP);

sys/dev/pci/pci_subr.c

2419

onoff("Compliance SOS", reg, PCIE_LCSR2_COMP_SOS);

sys/dev/pci/pci_subr.c

2422

PCIREG_SHIFTOUT(reg, PCIE_LCSR2_COMP_DEEMP));

sys/dev/pci/pci_subr.c

2426

printf(" Link Status 2: 0x%04x\n", (reg >> 16) & 0xffff);

sys/dev/pci/pci_subr.c

2429

PCIREG_SHIFTOUT(reg, PCIE_LCSR2_DEEMP_LVL));

sys/dev/pci/pci_subr.c

2431

onoff("Equalization Complete", reg, PCIE_LCSR2_EQ_COMPL);

sys/dev/pci/pci_subr.c

2432

onoff("Equalization Phase 1 Successful", reg,

sys/dev/pci/pci_subr.c

2434

onoff("Equalization Phase 2 Successful", reg,

sys/dev/pci/pci_subr.c

2436

onoff("Equalization Phase 3 Successful", reg,

sys/dev/pci/pci_subr.c

2438

onoff("Link Equalization Request", reg, PCIE_LCSR2_LNKEQ_REQ);

sys/dev/pci/pci_subr.c

2439

onoff("Retimer Presence Detected", reg, PCIE_LCSR2_RETIMERPD);

sys/dev/pci/pci_subr.c

2442

switch (PCIREG_SHIFTOUT(reg, PCIE_LCSR2_DSCOMPN)) {

sys/dev/pci/pci_subr.c

2464

onoff("DRS Message Received", reg, PCIE_LCSR2_DRSRCV);

sys/dev/pci/pci_subr.c

2476

pcireg_t reg;

sys/dev/pci/pci_subr.c

2480

reg = regs[o2i(capoff + PCI_MSIX_CTL)];

sys/dev/pci/pci_subr.c

2482

(reg >> 16) & 0xff);

sys/dev/pci/pci_subr.c

2483

printf(" Table Size: %d\n", PCI_MSIX_CTL_TBLSIZE(reg));

sys/dev/pci/pci_subr.c

2484

onoff("Function Mask", reg, PCI_MSIX_CTL_FUNCMASK);

sys/dev/pci/pci_subr.c

2485

onoff("MSI-X Enable", reg, PCI_MSIX_CTL_ENABLE);

sys/dev/pci/pci_subr.c

2486

reg = regs[o2i(capoff + PCI_MSIX_TBLOFFSET)];

sys/dev/pci/pci_subr.c

2487

printf(" Table offset register: 0x%08x\n", reg);

sys/dev/pci/pci_subr.c

2489

(pcireg_t)(reg & PCI_MSIX_TBLOFFSET_MASK));

sys/dev/pci/pci_subr.c

2490

printf(" BIR: 0x%x\n", (pcireg_t)(reg & PCI_MSIX_TBLBIR_MASK));

sys/dev/pci/pci_subr.c

2491

reg = regs[o2i(capoff + PCI_MSIX_PBAOFFSET)];

sys/dev/pci/pci_subr.c

2492

printf(" Pending bit array register: 0x%08x\n", reg);

sys/dev/pci/pci_subr.c

2494

(pcireg_t)(reg & PCI_MSIX_PBAOFFSET_MASK));

sys/dev/pci/pci_subr.c

2495

printf(" BIR: 0x%x\n", (pcireg_t)(reg & PCI_MSIX_PBABIR_MASK));

sys/dev/pci/pci_subr.c

2501

pcireg_t reg;

sys/dev/pci/pci_subr.c

2505

reg = regs[o2i(capoff + PCI_SATA_REV)];

sys/dev/pci/pci_subr.c

2506

printf(" Revision register: 0x%04x\n", (reg >> 16) & 0xff);

sys/dev/pci/pci_subr.c

2508

PCIREG_SHIFTOUT(reg, PCI_SATA_REV_MAJOR),

sys/dev/pci/pci_subr.c

2509

PCIREG_SHIFTOUT(reg, PCI_SATA_REV_MINOR));

sys/dev/pci/pci_subr.c

2511

reg = regs[o2i(capoff + PCI_SATA_BAR)];

sys/dev/pci/pci_subr.c

2513

printf(" BAR Register: 0x%08x\n", reg);

sys/dev/pci/pci_subr.c

2515

if ((reg & PCI_SATA_BAR_SPEC) == PCI_SATA_BAR_INCONF)

sys/dev/pci/pci_subr.c

2518

printf("BAR %d\n", (int)PCI_SATA_BAR_NUM(reg));

sys/dev/pci/pci_subr.c

2520

PCIREG_SHIFTOUT(reg, PCI_SATA_BAR_OFFSET) * 4);

sys/dev/pci/pci_subr.c

2527

pcireg_t reg;

sys/dev/pci/pci_subr.c

2531

reg = regs[o2i(capoff + PCI_AFCAPR)];

sys/dev/pci/pci_subr.c

2532

printf(" AF Capabilities register: 0x%02x\n", (reg >> 24) & 0xff);

sys/dev/pci/pci_subr.c

2534

PCIREG_SHIFTOUT(reg, PCI_AF_LENGTH));

sys/dev/pci/pci_subr.c

2535

onoff("Transaction Pending", reg, PCI_AF_TP_CAP);

sys/dev/pci/pci_subr.c

2536

onoff("Function Level Reset", reg, PCI_AF_FLR_CAP);

sys/dev/pci/pci_subr.c

2537

reg = regs[o2i(capoff + PCI_AFCSR)];

sys/dev/pci/pci_subr.c

2538

printf(" AF Control register: 0x%02x\n", reg & 0xff);

sys/dev/pci/pci_subr.c

2543

printf(" AF Status register: 0x%02x\n", (reg >> 8) & 0xff);

sys/dev/pci/pci_subr.c

2544

onoff("Transaction Pending", reg, PCI_AFSR_TP);

sys/dev/pci/pci_subr.c

2594

pcireg_t reg, reg2;

sys/dev/pci/pci_subr.c

2599

reg = regs[o2i(capoff + PCI_EA_CAP1)];

sys/dev/pci/pci_subr.c

2600

printf(" EA Num Entries register: 0x%04x\n", reg >> 16);

sys/dev/pci/pci_subr.c

2601

entries = PCIREG_SHIFTOUT(reg, PCI_EA_CAP1_NUMENTRIES);

sys/dev/pci/pci_subr.c

2606

reg = regs[o2i(capoff + PCI_EA_CAP2)];

sys/dev/pci/pci_subr.c

2607

printf(" EA Capability Second register: 0x%08x\n", reg);

sys/dev/pci/pci_subr.c

2609

(uint8_t)PCIREG_SHIFTOUT(reg, PCI_EA_CAP2_SECONDARY));

sys/dev/pci/pci_subr.c

2611

(uint8_t)PCIREG_SHIFTOUT(reg, PCI_EA_CAP2_SUBORDINATE));

sys/dev/pci/pci_subr.c

2623

reg = regs[o2i(entoff)];

sys/dev/pci/pci_subr.c

2624

printf(" The first register: 0x%08x\n", reg);

sys/dev/pci/pci_subr.c

2625

entry_size = PCIREG_SHIFTOUT(reg, PCI_EA_ES);

sys/dev/pci/pci_subr.c

2628

bei = PCIREG_SHIFTOUT(reg, PCI_EA_BEI);

sys/dev/pci/pci_subr.c

2662

pci_conf_print_ea_cap_prop(PCIREG_SHIFTOUT(reg, PCI_EA_PP));

sys/dev/pci/pci_subr.c

2664

pci_conf_print_ea_cap_prop(PCIREG_SHIFTOUT(reg, PCI_EA_SP));

sys/dev/pci/pci_subr.c

2665

onoff("Writable", reg, PCI_EA_W);

sys/dev/pci/pci_subr.c

2666

onoff("Enable for this entry", reg, PCI_EA_E);

sys/dev/pci/pci_subr.c

2674

reg = regs[o2i(entoff + 4)];

sys/dev/pci/pci_subr.c

2675

base = reg & PCI_EA_LOWMASK;

sys/dev/pci/pci_subr.c

2676

baseis64 = reg & PCI_EA_BASEMAXOFFSET_64BIT;

sys/dev/pci/pci_subr.c

2677

printf(" Base Address Register Low: 0x%08x\n", reg);

sys/dev/pci/pci_subr.c

2687

reg = regs[o2i(entoff + 8)];

sys/dev/pci/pci_subr.c

2688

offset = reg & PCI_EA_LOWMASK;

sys/dev/pci/pci_subr.c

2689

offsetis64 = reg & PCI_EA_BASEMAXOFFSET_64BIT;

sys/dev/pci/pci_subr.c

2690

printf(" Max Offset Register Low: 0x%08x\n", reg);

sys/dev/pci/pci_subr.c

2834

pci_conf_print_aer_cap_uc(pcireg_t reg)

sys/dev/pci/pci_subr.c

2837

onoff("Undefined", reg, PCI_AER_UC_UNDEFINED);

sys/dev/pci/pci_subr.c

2838

onoff("Data Link Protocol Error", reg, PCI_AER_UC_DL_PROTOCOL_ERROR);

sys/dev/pci/pci_subr.c

2839

onoff("Surprise Down Error", reg, PCI_AER_UC_SURPRISE_DOWN_ERROR);

sys/dev/pci/pci_subr.c

2840

onoff("Poisoned TLP Received", reg, PCI_AER_UC_POISONED_TLP);

sys/dev/pci/pci_subr.c

2841

onoff("Flow Control Protocol Error", reg, PCI_AER_UC_FC_PROTOCOL_ERROR);

sys/dev/pci/pci_subr.c

2842

onoff("Completion Timeout", reg, PCI_AER_UC_COMPLETION_TIMEOUT);

sys/dev/pci/pci_subr.c

2843

onoff("Completer Abort", reg, PCI_AER_UC_COMPLETER_ABORT);

sys/dev/pci/pci_subr.c

2844

onoff("Unexpected Completion", reg, PCI_AER_UC_UNEXPECTED_COMPLETION);

sys/dev/pci/pci_subr.c

2845

onoff("Receiver Overflow", reg, PCI_AER_UC_RECEIVER_OVERFLOW);

sys/dev/pci/pci_subr.c

2846

onoff("Malformed TLP", reg, PCI_AER_UC_MALFORMED_TLP);

sys/dev/pci/pci_subr.c

2847

onoff("ECRC Error", reg, PCI_AER_UC_ECRC_ERROR);

sys/dev/pci/pci_subr.c

2848

onoff("Unsupported Request Error", reg,

sys/dev/pci/pci_subr.c

2850

onoff("ACS Violation", reg, PCI_AER_UC_ACS_VIOLATION);

sys/dev/pci/pci_subr.c

2851

onoff("Uncorrectable Internal Error", reg, PCI_AER_UC_INTERNAL_ERROR);

sys/dev/pci/pci_subr.c

2852

onoff("MC Blocked TLP", reg, PCI_AER_UC_MC_BLOCKED_TLP);

sys/dev/pci/pci_subr.c

2853

onoff("AtomicOp Egress BLK", reg, PCI_AER_UC_ATOMIC_OP_EGRESS_BLOCKED);

sys/dev/pci/pci_subr.c

2854

onoff("TLP Prefix Blocked Error", reg,

sys/dev/pci/pci_subr.c

2856

onoff("Poisoned TLP Egress Blocked", reg,

sys/dev/pci/pci_subr.c

2861

pci_conf_print_aer_cap_cor(pcireg_t reg)

sys/dev/pci/pci_subr.c

2864

onoff("Receiver Error", reg, PCI_AER_COR_RECEIVER_ERROR);

sys/dev/pci/pci_subr.c

2865

onoff("Bad TLP", reg, PCI_AER_COR_BAD_TLP);

sys/dev/pci/pci_subr.c

2866

onoff("Bad DLLP", reg, PCI_AER_COR_BAD_DLLP);

sys/dev/pci/pci_subr.c

2867

onoff("REPLAY_NUM Rollover", reg, PCI_AER_COR_REPLAY_NUM_ROLLOVER);

sys/dev/pci/pci_subr.c

2868

onoff("Replay Timer Timeout", reg, PCI_AER_COR_REPLAY_TIMER_TIMEOUT);

sys/dev/pci/pci_subr.c

2869

onoff("Advisory Non-Fatal Error", reg, PCI_AER_COR_ADVISORY_NF_ERROR);

sys/dev/pci/pci_subr.c

2870

onoff("Corrected Internal Error", reg, PCI_AER_COR_INTERNAL_ERROR);

sys/dev/pci/pci_subr.c

2871

onoff("Header Log Overflow", reg, PCI_AER_COR_HEADER_LOG_OVERFLOW);

sys/dev/pci/pci_subr.c

2875

pci_conf_print_aer_cap_control(pcireg_t reg, bool *tlp_prefix_log)

sys/dev/pci/pci_subr.c

2879

PCIREG_SHIFTOUT(reg, PCI_AER_FIRST_ERROR_PTR));

sys/dev/pci/pci_subr.c

2880

onoff("ECRC Generation Capable", reg, PCI_AER_ECRC_GEN_CAPABLE);

sys/dev/pci/pci_subr.c

2881

onoff("ECRC Generation Enable", reg, PCI_AER_ECRC_GEN_ENABLE);

sys/dev/pci/pci_subr.c

2882

onoff("ECRC Check Capable", reg, PCI_AER_ECRC_CHECK_CAPABLE);

sys/dev/pci/pci_subr.c

2883

onoff("ECRC Check Enable", reg, PCI_AER_ECRC_CHECK_ENABLE);

sys/dev/pci/pci_subr.c

2884

onoff("Multiple Header Recording Capable", reg,

sys/dev/pci/pci_subr.c

2886

onoff("Multiple Header Recording Enable", reg,PCI_AER_MULT_HDR_ENABLE);

sys/dev/pci/pci_subr.c

2887

onoff("Completion Timeout Prefix/Header Log Capable", reg,

sys/dev/pci/pci_subr.c

2893

onoff("TLP Prefix Log Present", reg, PCI_AER_TLP_PREFIX_LOG_PRESENT);

sys/dev/pci/pci_subr.c

2894

*tlp_prefix_log = (reg & PCI_AER_TLP_PREFIX_LOG_PRESENT) ? true : false;

sys/dev/pci/pci_subr.c

2898

pci_conf_print_aer_cap_rooterr_cmd(pcireg_t reg)

sys/dev/pci/pci_subr.c

2901

onoff("Correctable Error Reporting Enable", reg,

sys/dev/pci/pci_subr.c

2903

onoff("Non-Fatal Error Reporting Enable", reg,

sys/dev/pci/pci_subr.c

2905

onoff("Fatal Error Reporting Enable", reg, PCI_AER_ROOTERR_F_ENABLE);

sys/dev/pci/pci_subr.c

2909

pci_conf_print_aer_cap_rooterr_status(pcireg_t reg)

sys/dev/pci/pci_subr.c

2912

onoff("ERR_COR Received", reg, PCI_AER_ROOTERR_COR_ERR);

sys/dev/pci/pci_subr.c

2913

onoff("Multiple ERR_COR Received", reg, PCI_AER_ROOTERR_MULTI_COR_ERR);

sys/dev/pci/pci_subr.c

2914

onoff("ERR_FATAL/NONFATAL_ERR Received", reg, PCI_AER_ROOTERR_UC_ERR);

sys/dev/pci/pci_subr.c

2915

onoff("Multiple ERR_FATAL/NONFATAL_ERR Received", reg,

sys/dev/pci/pci_subr.c

2917

onoff("First Uncorrectable Fatal", reg,PCI_AER_ROOTERR_FIRST_UC_FATAL);

sys/dev/pci/pci_subr.c

2918

onoff("Non-Fatal Error Messages Received", reg,PCI_AER_ROOTERR_NF_ERR);

sys/dev/pci/pci_subr.c

2919

onoff("Fatal Error Messages Received", reg, PCI_AER_ROOTERR_F_ERR);

sys/dev/pci/pci_subr.c

2921

PCIREG_SHIFTOUT(reg, PCI_AER_ROOTERR_INT_MESSAGE));

sys/dev/pci/pci_subr.c

2925

pci_conf_print_aer_cap_errsrc_id(pcireg_t reg)

sys/dev/pci/pci_subr.c

2929

PCIREG_SHIFTOUT(reg, PCI_AER_ERRSRC_ID_ERR_COR));

sys/dev/pci/pci_subr.c

2931

PCIREG_SHIFTOUT(reg, PCI_AER_ERRSRC_ID_ERR_UC));

sys/dev/pci/pci_subr.c

2937

pcireg_t reg;

sys/dev/pci/pci_subr.c

2943

reg = regs[o2i(pcie_capoff)];

sys/dev/pci/pci_subr.c

2944

pcie_devtype = PCIE_XCAP_TYPE(reg);

sys/dev/pci/pci_subr.c

2946

if (PCIREG_SHIFTOUT(reg, PCIE_XCAP_VER_MASK) >= 2) {

sys/dev/pci/pci_subr.c

2947

reg = regs[o2i(pcie_capoff + PCIE_DCAP2)];

sys/dev/pci/pci_subr.c

2949

if (reg & PCIE_DCAP2_EETLP_PREF) {

sys/dev/pci/pci_subr.c

2957

reg = regs[o2i(extcapoff + PCI_AER_UC_STATUS)];

sys/dev/pci/pci_subr.c

2958

printf(" Uncorrectable Error Status register: 0x%08x\n", reg);

sys/dev/pci/pci_subr.c

2959

pci_conf_print_aer_cap_uc(reg);

sys/dev/pci/pci_subr.c

2960

reg = regs[o2i(extcapoff + PCI_AER_UC_MASK)];

sys/dev/pci/pci_subr.c

2961

printf(" Uncorrectable Error Mask register: 0x%08x\n", reg);

sys/dev/pci/pci_subr.c

2962

pci_conf_print_aer_cap_uc(reg);

sys/dev/pci/pci_subr.c

2963

reg = regs[o2i(extcapoff + PCI_AER_UC_SEVERITY)];

sys/dev/pci/pci_subr.c

2964

printf(" Uncorrectable Error Severity register: 0x%08x\n", reg);

sys/dev/pci/pci_subr.c

2965

pci_conf_print_aer_cap_uc(reg);

sys/dev/pci/pci_subr.c

2967

reg = regs[o2i(extcapoff + PCI_AER_COR_STATUS)];

sys/dev/pci/pci_subr.c

2968

printf(" Correctable Error Status register: 0x%08x\n", reg);

sys/dev/pci/pci_subr.c

2969

pci_conf_print_aer_cap_cor(reg);

sys/dev/pci/pci_subr.c

2970

reg = regs[o2i(extcapoff + PCI_AER_COR_MASK)];

sys/dev/pci/pci_subr.c

2971

printf(" Correctable Error Mask register: 0x%08x\n", reg);

sys/dev/pci/pci_subr.c

2972

pci_conf_print_aer_cap_cor(reg);

sys/dev/pci/pci_subr.c

2974

reg = regs[o2i(extcapoff + PCI_AER_CAP_CONTROL)];

sys/dev/pci/pci_subr.c

2976

reg);

sys/dev/pci/pci_subr.c

2977

pci_conf_print_aer_cap_control(reg, &tlp_prefix_log);

sys/dev/pci/pci_subr.c

2978

reg = regs[o2i(extcapoff + PCI_AER_HEADER_LOG)];

sys/dev/pci/pci_subr.c

2986

reg = regs[o2i(extcapoff + PCI_AER_ROOTERR_CMD)];

sys/dev/pci/pci_subr.c

2987

printf(" Root Error Command register: 0x%08x\n", reg);

sys/dev/pci/pci_subr.c

2988

pci_conf_print_aer_cap_rooterr_cmd(reg);

sys/dev/pci/pci_subr.c

2989

reg = regs[o2i(extcapoff + PCI_AER_ROOTERR_STATUS)];

sys/dev/pci/pci_subr.c

2990

printf(" Root Error Status register: 0x%08x\n", reg);

sys/dev/pci/pci_subr.c

2991

pci_conf_print_aer_cap_rooterr_status(reg);

sys/dev/pci/pci_subr.c

2993

reg = regs[o2i(extcapoff + PCI_AER_ERRSRC_ID)];

sys/dev/pci/pci_subr.c

2995

reg);

sys/dev/pci/pci_subr.c

2996

pci_conf_print_aer_cap_errsrc_id(reg);

sys/dev/pci/pci_subr.c

3001

reg = regs[o2i(extcapoff + PCI_AER_TLP_PREFIX_LOG)];

sys/dev/pci/pci_subr.c

3002

printf(" TLP Prefix Log register: 0x%08x\n", reg);

sys/dev/pci/pci_subr.c

3017

pcireg_t reg;

sys/dev/pci/pci_subr.c

3023

reg = regs[o2i(off + (sizeof(uint32_t) * (i / num_per_reg)))];

sys/dev/pci/pci_subr.c

3027

(uint32_t)(reg & __BITS(arbsize - 1, 0)));

sys/dev/pci/pci_subr.c

3028

reg >>= arbsize;

sys/dev/pci/pci_subr.c

3039

pcireg_t reg, n;

sys/dev/pci/pci_subr.c

3045

reg = regs[o2i(extcapoff + PCI_VC_CAP1)];

sys/dev/pci/pci_subr.c

3046

printf(" Port VC Capability register 1: 0x%08x\n", reg);

sys/dev/pci/pci_subr.c

3047

count = PCIREG_SHIFTOUT(reg, PCI_VC_CAP1_EXT_COUNT);

sys/dev/pci/pci_subr.c

3049

n = PCIREG_SHIFTOUT(reg, PCI_VC_CAP1_LOWPRI_EXT_COUNT);

sys/dev/pci/pci_subr.c

3051

n = PCIREG_SHIFTOUT(reg, PCI_VC_CAP1_REFCLK);

sys/dev/pci/pci_subr.c

3054

parbsize = 1 << PCIREG_SHIFTOUT(reg, PCI_VC_CAP1_PORT_ARB_TABLE_SIZE);

sys/dev/pci/pci_subr.c

3057

reg = regs[o2i(extcapoff + PCI_VC_CAP2)];

sys/dev/pci/pci_subr.c

3058

printf(" Port VC Capability register 2: 0x%08x\n", reg);

sys/dev/pci/pci_subr.c

3060

reg, PCI_VC_CAP2_ARB_CAP_HW_FIXED_SCHEME);

sys/dev/pci/pci_subr.c

3062

reg, PCI_VC_CAP2_ARB_CAP_WRR_32);

sys/dev/pci/pci_subr.c

3064

reg, PCI_VC_CAP2_ARB_CAP_WRR_64);

sys/dev/pci/pci_subr.c

3066

reg, PCI_VC_CAP2_ARB_CAP_WRR_128);

sys/dev/pci/pci_subr.c

3067

arbtab = PCIREG_SHIFTOUT(reg, PCI_VC_CAP2_ARB_TABLE_OFFSET);

sys/dev/pci/pci_subr.c

3070

reg = regs[o2i(extcapoff + PCI_VC_CONTROL)] & 0xffff;

sys/dev/pci/pci_subr.c

3071

printf(" Port VC Control register: 0x%04x\n", reg);

sys/dev/pci/pci_subr.c

3072

arbsel = PCIREG_SHIFTOUT(reg, PCI_VC_CONTROL_VC_ARB_SELECT);

sys/dev/pci/pci_subr.c

3075

reg = regs[o2i(extcapoff + PCI_VC_STATUS)] >> 16;

sys/dev/pci/pci_subr.c

3076

printf(" Port VC Status register: 0x%04x\n", reg);

sys/dev/pci/pci_subr.c

3078

reg, PCI_VC_STATUS_LOAD_VC_ARB_TABLE);

sys/dev/pci/pci_subr.c

3085

reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_CAP(i))];

sys/dev/pci/pci_subr.c

3087

printf(" VC Resource Capability Register: 0x%08x\n", reg);

sys/dev/pci/pci_subr.c

3089

reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_HW_FIXED_SCHEME);

sys/dev/pci/pci_subr.c

3091

reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_32);

sys/dev/pci/pci_subr.c

3093

reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_64);

sys/dev/pci/pci_subr.c

3095

reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_128);

sys/dev/pci/pci_subr.c

3097

reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_TWRR_128);

sys/dev/pci/pci_subr.c

3099

reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_256);

sys/dev/pci/pci_subr.c

3101

reg, PCI_VC_RESOURCE_CAP_ADV_PKT_SWITCH);

sys/dev/pci/pci_subr.c

3103

reg, PCI_VC_RESOURCE_CAP_REJCT_SNOOP_TRANS);

sys/dev/pci/pci_subr.c

3104

n = PCIREG_SHIFTOUT(reg, PCI_VC_RESOURCE_CAP_MAX_TIME_SLOTS) + 1;

sys/dev/pci/pci_subr.c

3106

arbtab = PCIREG_SHIFTOUT(reg,

sys/dev/pci/pci_subr.c

3111

reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_CTL(i))];

sys/dev/pci/pci_subr.c

3112

printf(" VC Resource Control Register: 0x%08x\n", reg);

sys/dev/pci/pci_subr.c

3114

PCIREG_SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_TCVC_MAP));

sys/dev/pci/pci_subr.c

3120

arbsel = PCIREG_SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_PORT_ARB_SELECT);

sys/dev/pci/pci_subr.c

3122

n = PCIREG_SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_VC_ID);

sys/dev/pci/pci_subr.c

3124

onoff(" VC Enable", reg, PCI_VC_RESOURCE_CTL_VC_ENABLE);

sys/dev/pci/pci_subr.c

3126

reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_STA(i))] >> 16;

sys/dev/pci/pci_subr.c

3127

printf(" VC Resource Status Register: 0x%08x\n", reg);

sys/dev/pci/pci_subr.c

3129

reg, PCI_VC_RESOURCE_STA_PORT_ARB_TABLE);

sys/dev/pci/pci_subr.c

3131

reg, PCI_VC_RESOURCE_STA_VC_NEG_PENDING);

sys/dev/pci/pci_subr.c

3185

pci_conf_print_pwrbdgt_type(uint8_t reg)

sys/dev/pci/pci_subr.c

3188

switch (reg) {

sys/dev/pci/pci_subr.c

3209

pci_conf_print_pwrbdgt_pwrrail(uint8_t reg)

sys/dev/pci/pci_subr.c

3212

switch (reg) {

sys/dev/pci/pci_subr.c

3229

pcireg_t reg;

sys/dev/pci/pci_subr.c

3233

reg = regs[o2i(extcapoff + PCI_PWRBDGT_DSEL)];

sys/dev/pci/pci_subr.c

3234

printf(" Data Select register: 0x%08x\n", reg);

sys/dev/pci/pci_subr.c

3236

reg = regs[o2i(extcapoff + PCI_PWRBDGT_DATA)];

sys/dev/pci/pci_subr.c

3237

printf(" Data register: 0x%08x\n", reg);

sys/dev/pci/pci_subr.c

3240

PCIREG_SHIFTOUT(reg, PCI_PWRBDGT_DATA_BASEPWR),

sys/dev/pci/pci_subr.c

3241

PCIREG_SHIFTOUT(reg, PCI_PWRBDGT_DATA_SCALE));

sys/dev/pci/pci_subr.c

3243

(uint8_t)PCIREG_SHIFTOUT(reg, PCI_PWRBDGT_PM_SUBSTAT));

sys/dev/pci/pci_subr.c

3245

PCIREG_SHIFTOUT(reg, PCI_PWRBDGT_PM_STAT));

sys/dev/pci/pci_subr.c

3248

(uint8_t)(PCIREG_SHIFTOUT(reg, PCI_PWRBDGT_TYPE))));

sys/dev/pci/pci_subr.c

3251

(uint8_t)(PCIREG_SHIFTOUT(reg, PCI_PWRBDGT_PWRRAIL))));

sys/dev/pci/pci_subr.c

3253

reg = regs[o2i(extcapoff + PCI_PWRBDGT_CAP)];

sys/dev/pci/pci_subr.c

3254

printf(" Power Budget Capability register: 0x%08x\n", reg);

sys/dev/pci/pci_subr.c

3256

reg, PCI_PWRBDGT_CAP_SYSALLOC);

sys/dev/pci/pci_subr.c

3278

pcireg_t reg;

sys/dev/pci/pci_subr.c

3284

reg = regs[o2i(extcapoff + PCI_RCLINK_DCL_ESDESC)];

sys/dev/pci/pci_subr.c

3285

printf(" Element Self Description Register: 0x%08x\n", reg);

sys/dev/pci/pci_subr.c

3287

pci_conf_print_rclink_dcl_cap_elmtype((unsigned char)reg));

sys/dev/pci/pci_subr.c

3288

nent = PCIREG_SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_NUMLINKENT);

sys/dev/pci/pci_subr.c

3291

(uint8_t)PCIREG_SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_COMPID));

sys/dev/pci/pci_subr.c

3293

(uint8_t)PCIREG_SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_PORTNUM));

sys/dev/pci/pci_subr.c

3295

reg = regs[o2i(extcapoff + PCI_RCLINK_DCL_LINKDESC(i))];

sys/dev/pci/pci_subr.c

3297

printf(" Link Description Register: 0x%08x\n", reg);

sys/dev/pci/pci_subr.c

3298

onoff(" Link Valid", reg, PCI_RCLINK_DCL_LINKDESC_LVALID);

sys/dev/pci/pci_subr.c

3299

linktype = reg & PCI_RCLINK_DCL_LINKDESC_LTYPE;

sys/dev/pci/pci_subr.c

3300

onoff2(" Link Type", reg, PCI_RCLINK_DCL_LINKDESC_LTYPE,

sys/dev/pci/pci_subr.c

3302

onoff(" Associated RCRB Header", reg,

sys/dev/pci/pci_subr.c

3305

(uint8_t)PCIREG_SHIFTOUT(reg,

sys/dev/pci/pci_subr.c

3308

(uint8_t)PCIREG_SHIFTOUT(reg,

sys/dev/pci/pci_subr.c

3313

reg = regs[o2i(extcapoff

sys/dev/pci/pci_subr.c

3316

reg);

sys/dev/pci/pci_subr.c

3317

reg = regs[o2i(extcapoff

sys/dev/pci/pci_subr.c

3320

reg);

sys/dev/pci/pci_subr.c

3357

pcireg_t reg;

sys/dev/pci/pci_subr.c

3361

reg = regs[o2i(extcapoff + PCI_RCEC_ASSOC_ASSOCBITMAP)];

sys/dev/pci/pci_subr.c

3363

" 0x%08x\n", reg);

sys/dev/pci/pci_subr.c

3366

reg = regs[o2i(extcapoff + PCI_RCEC_ASSOC_ASSOCBUSNUM)];

sys/dev/pci/pci_subr.c

3368

reg);

sys/dev/pci/pci_subr.c

3370

PCIREG_SHIFTOUT(reg,

sys/dev/pci/pci_subr.c

3373

PCIREG_SHIFTOUT(reg,

sys/dev/pci/pci_subr.c

3387

pcireg_t reg, cap, ctl;

sys/dev/pci/pci_subr.c

3392

reg = regs[o2i(extcapoff + PCI_ACS_CAP)];

sys/dev/pci/pci_subr.c

3393

cap = reg & 0xffff;

sys/dev/pci/pci_subr.c

3394

ctl = reg >> 16;

sys/dev/pci/pci_subr.c

3430

pcireg_t reg, cap, ctl;

sys/dev/pci/pci_subr.c

3434

reg = regs[o2i(extcapoff + PCI_ARI_CAP)];

sys/dev/pci/pci_subr.c

3435

cap = reg & 0xffff;

sys/dev/pci/pci_subr.c

3436

ctl = reg >> 16;

sys/dev/pci/pci_subr.c

3438

onoff("MVFC Function Groups Capability", reg, PCI_ARI_CAP_M);

sys/dev/pci/pci_subr.c

3439

onoff("ACS Function Groups Capability", reg, PCI_ARI_CAP_A);

sys/dev/pci/pci_subr.c

3441

PCIREG_SHIFTOUT(reg, PCI_ARI_CAP_NXTFN));

sys/dev/pci/pci_subr.c

3443

onoff("MVFC Function Groups Enable", reg, PCI_ARI_CTL_M);

sys/dev/pci/pci_subr.c

3444

onoff("ACS Function Groups Enable", reg, PCI_ARI_CTL_A);

sys/dev/pci/pci_subr.c

3446

PCIREG_SHIFTOUT(reg, PCI_ARI_CTL_FUNCGRP));

sys/dev/pci/pci_subr.c

3452

pcireg_t reg, cap, ctl;

sys/dev/pci/pci_subr.c

3457

reg = regs[o2i(extcapoff + PCI_ARI_CAP)];

sys/dev/pci/pci_subr.c

3458

cap = reg & 0xffff;

sys/dev/pci/pci_subr.c

3459

ctl = reg >> 16;

sys/dev/pci/pci_subr.c

3461

num = PCIREG_SHIFTOUT(reg, PCI_ATS_CAP_INVQDEPTH);

sys/dev/pci/pci_subr.c

3465

onoff("Page Aligned Request", reg, PCI_ATS_CAP_PALIGNREQ);

sys/dev/pci/pci_subr.c

3466

onoff("Global Invalidate", reg, PCI_ATS_CAP_GLOBALINVL);

sys/dev/pci/pci_subr.c

3467

onoff("Relaxed Ordering", reg, PCI_ATS_CAP_RELAXORD);

sys/dev/pci/pci_subr.c

3471

PCIREG_SHIFTOUT(reg, PCI_ATS_CTL_STU));

sys/dev/pci/pci_subr.c

3472

onoff("Enable", reg, PCI_ATS_CTL_EN);

sys/dev/pci/pci_subr.c

3493

pcireg_t reg;

sys/dev/pci/pci_subr.c

3500

reg = regs[o2i(extcapoff + PCI_SRIOV_CAP)];

sys/dev/pci/pci_subr.c

3501

printf(" Capabilities register: 0x%08x\n", reg);

sys/dev/pci/pci_subr.c

3502

onoff("VF Migration Capable", reg, PCI_SRIOV_CAP_VF_MIGRATION);

sys/dev/pci/pci_subr.c

3503

onoff("ARI Capable Hierarchy Preserved", reg,

sys/dev/pci/pci_subr.c

3505

if (reg & PCI_SRIOV_CAP_VF_MIGRATION) {

sys/dev/pci/pci_subr.c

3507

PCIREG_SHIFTOUT(reg, PCI_SRIOV_CAP_VF_MIGRATION_INTMSG_N));

sys/dev/pci/pci_subr.c

3510

reg = regs[o2i(extcapoff + PCI_SRIOV_CTL)] & 0xffff;

sys/dev/pci/pci_subr.c

3511

printf(" Control register: 0x%04x\n", reg);

sys/dev/pci/pci_subr.c

3512

onoff("VF Enable", reg, PCI_SRIOV_CTL_VF_ENABLE);

sys/dev/pci/pci_subr.c

3513

onoff("VF Migration Enable", reg, PCI_SRIOV_CTL_VF_MIGRATION_SUPPORT);

sys/dev/pci/pci_subr.c

3514

onoff("VF Migration Interrupt Enable", reg,

sys/dev/pci/pci_subr.c

3516

onoff("VF Memory Space Enable", reg, PCI_SRIOV_CTL_VF_MSE);

sys/dev/pci/pci_subr.c

3517

onoff("ARI Capable Hierarchy", reg, PCI_SRIOV_CTL_ARI_CAP_HIER);

sys/dev/pci/pci_subr.c

3519

reg = regs[o2i(extcapoff + PCI_SRIOV_STA)] >> 16;

sys/dev/pci/pci_subr.c

3520

printf(" Status register: 0x%04x\n", reg);

sys/dev/pci/pci_subr.c

3521

onoff("VF Migration Status", reg, PCI_SRIOV_STA_VF_MIGRATION);

sys/dev/pci/pci_subr.c

3523

reg = regs[o2i(extcapoff + PCI_SRIOV_INITIAL_VFS)] & 0xffff;

sys/dev/pci/pci_subr.c

3524

printf(" InitialVFs register: 0x%04x\n", reg);

sys/dev/pci/pci_subr.c

3525

total_vfs = reg = regs[o2i(extcapoff + PCI_SRIOV_TOTAL_VFS)] >> 16;

sys/dev/pci/pci_subr.c

3526

printf(" TotalVFs register: 0x%04x\n", reg);

sys/dev/pci/pci_subr.c

3527

reg = regs[o2i(extcapoff + PCI_SRIOV_NUM_VFS)] & 0xffff;

sys/dev/pci/pci_subr.c

3528

printf(" NumVFs register: 0x%04x\n", reg);

sys/dev/pci/pci_subr.c

3530

reg = regs[o2i(extcapoff + PCI_SRIOV_FUNC_DEP_LINK)] >> 16;

sys/dev/pci/pci_subr.c

3531

printf(" Function Dependency Link register: 0x%04x\n", reg);

sys/dev/pci/pci_subr.c

3533

reg = regs[o2i(extcapoff + PCI_SRIOV_VF_OFF)] & 0xffff;

sys/dev/pci/pci_subr.c

3534

printf(" First VF Offset register: 0x%04x\n", reg);

sys/dev/pci/pci_subr.c

3535

reg = regs[o2i(extcapoff + PCI_SRIOV_VF_STRIDE)] >> 16;

sys/dev/pci/pci_subr.c

3536

printf(" VF Stride register: 0x%04x\n", reg);

sys/dev/pci/pci_subr.c

3537

reg = regs[o2i(extcapoff + PCI_SRIOV_VF_DID)] >> 16;

sys/dev/pci/pci_subr.c

3538

printf(" Device ID: 0x%04x\n", reg);

sys/dev/pci/pci_subr.c

3540

reg = regs[o2i(extcapoff + PCI_SRIOV_PAGE_CAP)];

sys/dev/pci/pci_subr.c

3541

printf(" Supported Page Sizes register: 0x%08x\n", reg);

sys/dev/pci/pci_subr.c

3544

if (reg & __BIT(i)) {

sys/dev/pci/pci_subr.c

3557

reg = regs[o2i(extcapoff + PCI_SRIOV_PAGE_SIZE)];

sys/dev/pci/pci_subr.c

3558

printf(" System Page Sizes register: 0x%08x\n", reg);

sys/dev/pci/pci_subr.c

3560

if (reg != 0) {

sys/dev/pci/pci_subr.c

3561

int bitpos = ffs(reg) -1;

sys/dev/pci/pci_subr.c

3577

reg = regs[o2i(extcapoff + PCI_SRIOV_BAR(i))];

sys/dev/pci/pci_subr.c

3578

printf(" VF BAR%d register: 0x%08x\n", i, reg);

sys/dev/pci/pci_subr.c

3582

reg = regs[o2i(extcapoff + PCI_SRIOV_VF_MIG_STA_AR)];

sys/dev/pci/pci_subr.c

3584

reg);

sys/dev/pci/pci_subr.c

3586

PCIREG_SHIFTOUT(reg, PCI_SRIOV_VF_MIG_STA_OFFSET));

sys/dev/pci/pci_subr.c

3587

i = PCIREG_SHIFTOUT(reg, PCI_SRIOV_VF_MIG_STA_BIR);

sys/dev/pci/pci_subr.c

3603

pcireg_t reg, cap, ctl;

sys/dev/pci/pci_subr.c

3610

reg = regs[o2i(extcapoff + PCI_MCAST_CTL)];

sys/dev/pci/pci_subr.c

3611

cap = reg & 0xffff;

sys/dev/pci/pci_subr.c

3612

ctl = reg >> 16;

sys/dev/pci/pci_subr.c

3615

(pcireg_t)(reg & PCI_MCAST_CAP_MAXGRP) + 1);

sys/dev/pci/pci_subr.c

3618

n = PCIREG_SHIFTOUT(reg, PCI_MCAST_CAP_WINSIZEREQ);

sys/dev/pci/pci_subr.c

3622

onoff("ECRC Regeneration Supported", reg, PCI_MCAST_CAP_ECRCREGEN);

sys/dev/pci/pci_subr.c

3626

PCIREG_SHIFTOUT(reg, PCI_MCAST_CTL_NUMGRP) + 1);

sys/dev/pci/pci_subr.c

3627

onoff("Enable", reg, PCI_MCAST_CTL_ENA);

sys/dev/pci/pci_subr.c

3671

pcireg_t reg, ctl, sta;

sys/dev/pci/pci_subr.c

3675

reg = regs[o2i(extcapoff + PCI_PAGE_REQ_CTL)];

sys/dev/pci/pci_subr.c

3676

ctl = reg & 0xffff;

sys/dev/pci/pci_subr.c

3677

sta = reg >> 16;

sys/dev/pci/pci_subr.c

3679

onoff("Enable", reg, PCI_PAGE_REQ_CTL_E);

sys/dev/pci/pci_subr.c

3680

onoff("Reset", reg, PCI_PAGE_REQ_CTL_R);

sys/dev/pci/pci_subr.c

3683

onoff("Response Failure", reg, PCI_PAGE_REQ_STA_RF);

sys/dev/pci/pci_subr.c

3684

onoff("Unexpected Page Request Group Index", reg,

sys/dev/pci/pci_subr.c

3686

onoff("Stopped", reg, PCI_PAGE_REQ_STA_S);

sys/dev/pci/pci_subr.c

3687

onoff("PRG Response PASID Required", reg, PCI_PAGE_REQ_STA_PASIDR);

sys/dev/pci/pci_subr.c

3689

reg = regs[o2i(extcapoff + PCI_PAGE_REQ_OUTSTCAPA)];

sys/dev/pci/pci_subr.c

3690

printf(" Outstanding Page Request Capacity: %u\n", reg);

sys/dev/pci/pci_subr.c

3691

reg = regs[o2i(extcapoff + PCI_PAGE_REQ_OUTSTALLOC)];

sys/dev/pci/pci_subr.c

3692

printf(" Outstanding Page Request Allocation: %u\n", reg);

sys/dev/pci/pci_subr.c

3759

pcireg_t reg;

sys/dev/pci/pci_subr.c

3764

reg = regs[o2i(extcapoff + PCI_DPA_CAP)];

sys/dev/pci/pci_subr.c

3765

printf(" Capability register: 0x%08x\n", reg);

sys/dev/pci/pci_subr.c

3766

substmax = PCIREG_SHIFTOUT(reg, PCI_DPA_CAP_SUBSTMAX);

sys/dev/pci/pci_subr.c

3769

switch (PCIREG_SHIFTOUT(reg, PCI_DPA_CAP_TLUINT)) {

sys/dev/pci/pci_subr.c

3784

switch (PCIREG_SHIFTOUT(reg, PCI_DPA_CAP_PAS)) {

sys/dev/pci/pci_subr.c

3799

PCIREG_SHIFTOUT(reg, PCI_DPA_CAP_XLCY0));

sys/dev/pci/pci_subr.c

3801

PCIREG_SHIFTOUT(reg, PCI_DPA_CAP_XLCY1));

sys/dev/pci/pci_subr.c

3803

reg = regs[o2i(extcapoff + PCI_DPA_LATIND)];

sys/dev/pci/pci_subr.c

3804

printf(" Latency Indicator register: 0x%08x\n", reg);

sys/dev/pci/pci_subr.c

3806

reg = regs[o2i(extcapoff + PCI_DPA_CS)];

sys/dev/pci/pci_subr.c

3807

printf(" Status register: 0x%04x\n", reg & 0xffff);

sys/dev/pci/pci_subr.c

3809

PCIREG_SHIFTOUT(reg, PCI_DPA_CS_SUBSTSTAT));

sys/dev/pci/pci_subr.c

3810

onoff("Substate Control Enabled", reg, PCI_DPA_CS_SUBSTCTLEN);

sys/dev/pci/pci_subr.c

3811

printf(" Control register: 0x%04x\n", reg >> 16);

sys/dev/pci/pci_subr.c

3813

PCIREG_SHIFTOUT(reg, PCI_DPA_CS_SUBSTCTL));

sys/dev/pci/pci_subr.c

3839

pcireg_t reg;

sys/dev/pci/pci_subr.c

3845

reg = regs[o2i(extcapoff + PCI_TPH_REQ_CAP)];

sys/dev/pci/pci_subr.c

3846

printf(" TPH Requester Capability register: 0x%08x\n", reg);

sys/dev/pci/pci_subr.c

3847

onoff("No ST Mode Supported", reg, PCI_TPH_REQ_CAP_NOST);

sys/dev/pci/pci_subr.c

3848

onoff("Interrupt Vector Mode Supported", reg, PCI_TPH_REQ_CAP_INTVEC);

sys/dev/pci/pci_subr.c

3849

onoff("Device Specific Mode Supported", reg, PCI_TPH_REQ_CAP_DEVSPEC);

sys/dev/pci/pci_subr.c

3850

onoff("Extend TPH Requester Supported", reg, PCI_TPH_REQ_CAP_XTPHREQ);

sys/dev/pci/pci_subr.c

3851

sttbloc = PCIREG_SHIFTOUT(reg, PCI_TPH_REQ_CAP_STTBLLOC);

sys/dev/pci/pci_subr.c

3855

size = PCIREG_SHIFTOUT(reg, PCI_TPH_REQ_CAP_STTBLSIZ) + 1;

sys/dev/pci/pci_subr.c

3859

reg = regs[o2i(extcapoff + PCI_TPH_REQ_CTL)];

sys/dev/pci/pci_subr.c

3860

printf(" TPH Requester Control register: 0x%08x\n", reg);

sys/dev/pci/pci_subr.c

3862

switch (PCIREG_SHIFTOUT(reg, PCI_TPH_REQ_CTL_STSEL)) {

sys/dev/pci/pci_subr.c

3877

switch (PCIREG_SHIFTOUT(reg, PCI_TPH_REQ_CTL_TPHREQEN)) {

sys/dev/pci/pci_subr.c

3896

reg = regs[o2i(extcapoff + PCI_TPH_REQ_STTBL + i / 2)];

sys/dev/pci/pci_subr.c

3898

uint32_t entry = reg;

sys/dev/pci/pci_subr.c

3912

pcireg_t reg;

sys/dev/pci/pci_subr.c

3915

reg = regs[o2i(extcapoff + PCI_LTR_MAXSNOOPLAT)];

sys/dev/pci/pci_subr.c

3916

printf(" Max Snoop Latency Register: 0x%04x\n", reg & 0xffff);

sys/dev/pci/pci_subr.c

3918

(uintmax_t)(PCIREG_SHIFTOUT(reg, PCI_LTR_MAXSNOOPLAT_VAL)

sys/dev/pci/pci_subr.c

3919

* PCI_LTR_SCALETONS(PCIREG_SHIFTOUT(reg, PCI_LTR_MAXSNOOPLAT_SCALE))));

sys/dev/pci/pci_subr.c

3920

printf(" Max No-Snoop Latency Register: 0x%04x\n", reg >> 16);

sys/dev/pci/pci_subr.c

3922

(uintmax_t)(PCIREG_SHIFTOUT(reg, PCI_LTR_MAXNOSNOOPLAT_VAL)

sys/dev/pci/pci_subr.c

3923

* PCI_LTR_SCALETONS(PCIREG_SHIFTOUT(reg, PCI_LTR_MAXNOSNOOPLAT_SCALE))));

sys/dev/pci/pci_subr.c

3930

pcireg_t reg;

sys/dev/pci/pci_subr.c

3935

reg = regs[o2i(extcapoff + PCI_SECPCIE_LCTL3)];

sys/dev/pci/pci_subr.c

3936

printf(" Link Control 3 register: 0x%08x\n", reg);

sys/dev/pci/pci_subr.c

3937

onoff("Perform Equalization", reg, PCI_SECPCIE_LCTL3_PERFEQ);

sys/dev/pci/pci_subr.c

3939

reg, PCI_SECPCIE_LCTL3_LINKEQREQ_IE);

sys/dev/pci/pci_subr.c

3942

PCIREG_SHIFTOUT(reg, PCI_SECPCIE_LCTL3_ELSKPOSGENV));

sys/dev/pci/pci_subr.c

3945

reg = regs[o2i(extcapoff + PCI_SECPCIE_LANEERR_STA)];

sys/dev/pci/pci_subr.c

3946

printf(" Lane Error Status register: 0x%08x\n", reg);

sys/dev/pci/pci_subr.c

3950

reg = regs[o2i(pcie_capoff + PCIE_LCAP)];

sys/dev/pci/pci_subr.c

3951

maxlinkwidth = PCIREG_SHIFTOUT(reg, PCIE_LCAP_MAX_WIDTH);

sys/dev/pci/pci_subr.c

3957

reg = regs[o2i(extcapoff + PCI_SECPCIE_EQCTL(i))];

sys/dev/pci/pci_subr.c

3959

reg >>= 16;

sys/dev/pci/pci_subr.c

3961

reg &= 0xffff;

sys/dev/pci/pci_subr.c

3963

i, reg);

sys/dev/pci/pci_subr.c

3965

PCIREG_SHIFTOUT(reg,

sys/dev/pci/pci_subr.c

3968

PCIREG_SHIFTOUT(reg, PCI_SECPCIE_EQCTL_DP_RCV_HINT));

sys/dev/pci/pci_subr.c

3970

PCIREG_SHIFTOUT(reg,

sys/dev/pci/pci_subr.c

3973

PCIREG_SHIFTOUT(reg, PCI_SECPCIE_EQCTL_UP_RCV_HINT));

sys/dev/pci/pci_subr.c

3982

pcireg_t reg, cap, ctl;

sys/dev/pci/pci_subr.c

3987

reg = regs[o2i(extcapoff + PCI_PASID_CAP)];

sys/dev/pci/pci_subr.c

3988

cap = reg & 0xffff;

sys/dev/pci/pci_subr.c

3989

ctl = reg >> 16;

sys/dev/pci/pci_subr.c

3991

onoff("Execute Permission Supported", reg, PCI_PASID_CAP_XPERM);

sys/dev/pci/pci_subr.c

3992

onoff("Privileged Mode Supported", reg, PCI_PASID_CAP_PRIVMODE);

sys/dev/pci/pci_subr.c

3993

num = (1 << PCIREG_SHIFTOUT(reg, PCI_PASID_CAP_MAXPASIDW)) - 1;

sys/dev/pci/pci_subr.c

3997

onoff("PASID Enable", reg, PCI_PASID_CTL_PASID_EN);

sys/dev/pci/pci_subr.c

3998

onoff("Execute Permission Enable", reg, PCI_PASID_CTL_XPERM_EN);

sys/dev/pci/pci_subr.c

3999

onoff("Privileged Mode Enable", reg, PCI_PASID_CTL_PRIVMODE_EN);

sys/dev/pci/pci_subr.c

4005

pcireg_t reg, cap, ctl;

sys/dev/pci/pci_subr.c

4010

reg = regs[o2i(extcapoff + PCI_LNR_CAP)];

sys/dev/pci/pci_subr.c

4011

cap = reg & 0xffff;

sys/dev/pci/pci_subr.c

4012

ctl = reg >> 16;

sys/dev/pci/pci_subr.c

4014

onoff("LNR-64 Supported", reg, PCI_LNR_CAP_64);

sys/dev/pci/pci_subr.c

4015

onoff("LNR-128 Supported", reg, PCI_LNR_CAP_128);

sys/dev/pci/pci_subr.c

4016

num = 1 << PCIREG_SHIFTOUT(reg, PCI_LNR_CAP_REGISTMAX);

sys/dev/pci/pci_subr.c

4020

onoff("LNR Enable", reg, PCI_LNR_CTL_EN);

sys/dev/pci/pci_subr.c

4021

onoff("LNR CLS", reg, PCI_LNR_CTL_CLS);

sys/dev/pci/pci_subr.c

4022

num = 1 << PCIREG_SHIFTOUT(reg, PCI_LNR_CTL_REGISTLIM);

sys/dev/pci/pci_subr.c

4043

pcireg_t reg, cap, ctl, stat, errsrc;

sys/dev/pci/pci_subr.c

4049

reg = regs[o2i(extcapoff + PCI_DPC_CCR)];

sys/dev/pci/pci_subr.c

4050

cap = reg & 0xffff;

sys/dev/pci/pci_subr.c

4051

ctl = reg >> 16;

sys/dev/pci/pci_subr.c

4052

rpext = (reg & PCI_DPCCAP_RPEXT) ? true : false;

sys/dev/pci/pci_subr.c

4056

onoff("RP Extensions for DPC", reg, PCI_DPCCAP_RPEXT);

sys/dev/pci/pci_subr.c

4057

onoff("Poisoned TLP Egress Blocking Supported", reg,

sys/dev/pci/pci_subr.c

4059

onoff("DPC Software Triggering Supported", reg, PCI_DPCCAP_SWTRIG);

sys/dev/pci/pci_subr.c

4061

PCIREG_SHIFTOUT(reg, PCI_DPCCAP_RPPIOLOGSZ));

sys/dev/pci/pci_subr.c

4062

onoff("DL_Active ERR_COR Signaling Supported", reg,

sys/dev/pci/pci_subr.c

4065

switch (PCIREG_SHIFTOUT(reg, PCI_DPCCTL_TIRGEN)) {

sys/dev/pci/pci_subr.c

4081

(reg & PCI_DPCCTL_COMPCTL)

sys/dev/pci/pci_subr.c

4083

onoff("DPC Interrupt Enable", reg, PCI_DPCCTL_IE);

sys/dev/pci/pci_subr.c

4084

onoff("DPC ERR_COR Enable", reg, PCI_DPCCTL_ERRCOREN);

sys/dev/pci/pci_subr.c

4085

onoff("Poisoned TLP Egress Blocking Enable", reg,

sys/dev/pci/pci_subr.c

4087

onoff("DPC Software Trigger", reg, PCI_DPCCTL_SWTRIG);

sys/dev/pci/pci_subr.c

4088

onoff("DL_Active ERR_COR Enable", reg, PCI_DPCCTL_DLACTECOR);

sys/dev/pci/pci_subr.c

4090

reg = regs[o2i(extcapoff + PCI_DPC_STATESID)];

sys/dev/pci/pci_subr.c

4091

stat = reg & 0xffff;

sys/dev/pci/pci_subr.c

4092

errsrc = reg >> 16;

sys/dev/pci/pci_subr.c

4094

onoff("DPC Trigger Status", reg, PCI_DPCSTAT_TSTAT);

sys/dev/pci/pci_subr.c

4095

switch (PCIREG_SHIFTOUT(reg, PCI_DPCSTAT_TREASON)) {

sys/dev/pci/pci_subr.c

4110

onoff("DPC Interrupt Status", reg, PCI_DPCSTAT_ISTAT);

sys/dev/pci/pci_subr.c

4112

onoff("DPC RP Busy", reg, PCI_DPCSTAT_RPBUSY);

sys/dev/pci/pci_subr.c

4113

switch (PCIREG_SHIFTOUT(reg, PCI_DPCSTAT_TREASON)) {

sys/dev/pci/pci_subr.c

4127

PCIREG_SHIFTOUT(reg, PCI_DPCSTAT_RPPIOFEP));

sys/dev/pci/pci_subr.c

4137

reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_STAT)];

sys/dev/pci/pci_subr.c

4138

printf(" RP PIO Status Register: 0x%08x\n", reg);

sys/dev/pci/pci_subr.c

4139

pci_conf_print_dpc_pio(reg);

sys/dev/pci/pci_subr.c

4141

reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_MASK)];

sys/dev/pci/pci_subr.c

4142

printf(" RP PIO Mask Register: 0x%08x\n", reg);

sys/dev/pci/pci_subr.c

4143

pci_conf_print_dpc_pio(reg);

sys/dev/pci/pci_subr.c

4145

reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_SEVE)];

sys/dev/pci/pci_subr.c

4146

printf(" RP PIO Severity Register: 0x%08x\n", reg);

sys/dev/pci/pci_subr.c

4147

pci_conf_print_dpc_pio(reg);

sys/dev/pci/pci_subr.c

4149

reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_SYSERR)];

sys/dev/pci/pci_subr.c

4150

printf(" RP PIO SysError Register: 0x%08x\n", reg);

sys/dev/pci/pci_subr.c

4151

pci_conf_print_dpc_pio(reg);

sys/dev/pci/pci_subr.c

4153

reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_EXCPT)];

sys/dev/pci/pci_subr.c

4154

printf(" RP PIO Exception Register: 0x%08x\n", reg);

sys/dev/pci/pci_subr.c

4155

pci_conf_print_dpc_pio(reg);

sys/dev/pci/pci_subr.c

4186

pcireg_t reg;

sys/dev/pci/pci_subr.c

4192

reg = regs[o2i(extcapoff + PCI_L1PM_CAP)];

sys/dev/pci/pci_subr.c

4193

printf(" L1 PM Substates Capability register: 0x%08x\n", reg);

sys/dev/pci/pci_subr.c

4194

onoff("PCI-PM L1.2 Supported", reg, PCI_L1PM_CAP_PCIPM12);

sys/dev/pci/pci_subr.c

4195

onoff("PCI-PM L1.1 Supported", reg, PCI_L1PM_CAP_PCIPM11);

sys/dev/pci/pci_subr.c

4196

onoff("ASPM L1.2 Supported", reg, PCI_L1PM_CAP_ASPM12);

sys/dev/pci/pci_subr.c

4197

onoff("ASPM L1.1 Supported", reg, PCI_L1PM_CAP_ASPM11);

sys/dev/pci/pci_subr.c

4198

onoff("L1 PM Substates Supported", reg, PCI_L1PM_CAP_L1PM);

sys/dev/pci/pci_subr.c

4204

onoff("Link Activation Supported", reg,

sys/dev/pci/pci_subr.c

4208

PCIREG_SHIFTOUT(reg, PCI_L1PM_CAP_PCMRT));

sys/dev/pci/pci_subr.c

4210

PCIREG_SHIFTOUT(reg, PCI_L1PM_CAP_PTPOSCALE));

sys/dev/pci/pci_subr.c

4211

val = PCIREG_SHIFTOUT(reg, PCI_L1PM_CAP_PTPOVAL);

sys/dev/pci/pci_subr.c

4218

reg = regs[o2i(extcapoff + PCI_L1PM_CTL1)];

sys/dev/pci/pci_subr.c

4219

printf(" L1 PM Substates Control register 1: 0x%08x\n", reg);

sys/dev/pci/pci_subr.c

4220

onoff("PCI-PM L1.2 Enable", reg, PCI_L1PM_CTL1_PCIPM12_EN);

sys/dev/pci/pci_subr.c

4221

onoff("PCI-PM L1.1 Enable", reg, PCI_L1PM_CTL1_PCIPM11_EN);

sys/dev/pci/pci_subr.c

4222

onoff("ASPM L1.2 Enable", reg, PCI_L1PM_CTL1_ASPM12_EN);

sys/dev/pci/pci_subr.c

4223

onoff("ASPM L1.1 Enable", reg, PCI_L1PM_CTL1_ASPM11_EN);

sys/dev/pci/pci_subr.c

4224

onoff("Link Activation Interrupt Enable", reg, PCI_L1PM_CTL1_LAIE);

sys/dev/pci/pci_subr.c

4225

onoff("Link Activation Control", reg, PCI_L1PM_CTL1_LA);

sys/dev/pci/pci_subr.c

4227

PCIREG_SHIFTOUT(reg, PCI_L1PM_CTL1_CMRT));

sys/dev/pci/pci_subr.c

4228

scale = PCI_LTR_SCALETONS(PCIREG_SHIFTOUT(reg, PCI_L1PM_CTL1_LTRTHSCALE));

sys/dev/pci/pci_subr.c

4229

val = PCIREG_SHIFTOUT(reg, PCI_L1PM_CTL1_LTRTHVAL);

sys/dev/pci/pci_subr.c

4232

reg = regs[o2i(extcapoff + PCI_L1PM_CTL2)];

sys/dev/pci/pci_subr.c

4233

printf(" L1 PM Substates Control register 2: 0x%08x\n", reg);

sys/dev/pci/pci_subr.c

4235

PCIREG_SHIFTOUT(reg, PCI_L1PM_CTL2_TPOSCALE));

sys/dev/pci/pci_subr.c

4236

val = PCIREG_SHIFTOUT(reg, PCI_L1PM_CTL2_TPOVAL);

sys/dev/pci/pci_subr.c

4244

reg = regs[o2i(extcapoff + PCI_L1PM_CTL2)];

sys/dev/pci/pci_subr.c

4245

printf(" L1 PM Substates Status register: 0x%08x\n", reg);

sys/dev/pci/pci_subr.c

4246

onoff("Link Activation Status", reg, PCI_L1PM_STAT_LA);

sys/dev/pci/pci_subr.c

4253

pcireg_t reg;

sys/dev/pci/pci_subr.c

4258

reg = regs[o2i(extcapoff + PCI_PTM_CAP)];

sys/dev/pci/pci_subr.c

4259

printf(" PTM Capability register: 0x%08x\n", reg);

sys/dev/pci/pci_subr.c

4260

onoff("PTM Requester Capable", reg, PCI_PTM_CAP_REQ);

sys/dev/pci/pci_subr.c

4261

onoff("PTM Responder Capable", reg, PCI_PTM_CAP_RESP);

sys/dev/pci/pci_subr.c

4262

onoff("PTM Root Capable", reg, PCI_PTM_CAP_ROOT);

sys/dev/pci/pci_subr.c

4264

val = PCIREG_SHIFTOUT(reg, PCI_PTM_CAP_LCLCLKGRNL);

sys/dev/pci/pci_subr.c

4277

reg = regs[o2i(extcapoff + PCI_PTM_CTL)];

sys/dev/pci/pci_subr.c

4278

printf(" PTM Control register: 0x%08x\n", reg);

sys/dev/pci/pci_subr.c

4279

onoff("PTM Enable", reg, PCI_PTM_CTL_EN);

sys/dev/pci/pci_subr.c

4280

onoff("Root Select", reg, PCI_PTM_CTL_ROOTSEL);

sys/dev/pci/pci_subr.c

4282

val = PCIREG_SHIFTOUT(reg, PCI_PTM_CTL_EFCTGRNL);

sys/dev/pci/pci_subr.c

4305

pcireg_t reg;

sys/dev/pci/pci_subr.c

4308

reg = regs[o2i(extcapoff + PCI_DLF_CAP)];

sys/dev/pci/pci_subr.c

4309

printf(" Capability register: 0x%08x\n", reg);

sys/dev/pci/pci_subr.c

4310

onoff("Scaled Flow Control", reg, PCI_DLF_LFEAT_SCLFCTL);

sys/dev/pci/pci_subr.c

4311

onoff("DLF Exchange enable", reg, PCI_DLF_CAP_XCHG);

sys/dev/pci/pci_subr.c

4313

reg = regs[o2i(extcapoff + PCI_DLF_STAT)];

sys/dev/pci/pci_subr.c

4314

printf(" Status register: 0x%08x\n", reg);

sys/dev/pci/pci_subr.c

4315

onoff("Scaled Flow Control", reg, PCI_DLF_LFEAT_SCLFCTL);

sys/dev/pci/pci_subr.c

4316

onoff("Remote DLF supported Valid", reg, PCI_DLF_STAT_RMTVALID);

sys/dev/pci/pci_subr.c

4322

pcireg_t reg, lwidth;

sys/dev/pci/pci_subr.c

4327

reg = regs[o2i(extcapoff + PCI_PL16G_CAP)];

sys/dev/pci/pci_subr.c

4328

printf(" Capability register: 0x%08x\n", reg);

sys/dev/pci/pci_subr.c

4330

reg = regs[o2i(extcapoff + PCI_PL16G_CTL)];

sys/dev/pci/pci_subr.c

4331

printf(" Control register: 0x%08x\n", reg);

sys/dev/pci/pci_subr.c

4333

reg = regs[o2i(extcapoff + PCI_PL16G_STAT)];

sys/dev/pci/pci_subr.c

4334

printf(" Status register: 0x%08x\n", reg);

sys/dev/pci/pci_subr.c

4335

onoff("Equalization 16.0 GT/s Complete", reg, PCI_PL16G_STAT_EQ_COMPL);

sys/dev/pci/pci_subr.c

4336

onoff("Equalization 16.0 GT/s Phase 1 Successful", reg,

sys/dev/pci/pci_subr.c

4338

onoff("Equalization 16.0 GT/s Phase 2 Successful", reg,

sys/dev/pci/pci_subr.c

4340

onoff("Equalization 16.0 GT/s Phase 3 Successful", reg,

sys/dev/pci/pci_subr.c

4343

reg = regs[o2i(extcapoff + PCI_PL16G_LDPMS)];

sys/dev/pci/pci_subr.c

4345

reg);

sys/dev/pci/pci_subr.c

4347

reg = regs[o2i(extcapoff + PCI_PL16G_FRDPMS)];

sys/dev/pci/pci_subr.c

4349

" 0x%08x\n", reg);

sys/dev/pci/pci_subr.c

4351

reg = regs[o2i(extcapoff + PCI_PL16G_SRDPMS)];

sys/dev/pci/pci_subr.c

4353

" 0x%08x\n", reg);

sys/dev/pci/pci_subr.c

4358

reg = regs[o2i(pcie_capoff + PCIE_LCAP)];

sys/dev/pci/pci_subr.c

4359

lwidth = PCIREG_SHIFTOUT(reg, PCIE_LCAP_MAX_WIDTH);

sys/dev/pci/pci_subr.c

4362

reg = regs[o2i(extcapoff + PCI_PL16G_LEC + i)];

sys/dev/pci/pci_subr.c

4367

down = reg & 0x0000000f;

sys/dev/pci/pci_subr.c

4368

up = (reg >> 4) & 0x0000000f;

sys/dev/pci/pci_subr.c

4375

reg >>= 8;

sys/dev/pci/pci_subr.c

4413

pci_conf_print_lmr_lcsr(pcireg_t reg, bool up, bool dp)

sys/dev/pci/pci_subr.c

4418

rnum = PCIREG_SHIFTOUT(reg, PCI_LMR_LCTL_RNUM);

sys/dev/pci/pci_subr.c

4427

PCIREG_SHIFTOUT(reg, PCI_LMR_LCTL_MTYPE));

sys/dev/pci/pci_subr.c

4429

(PCIREG_SHIFTOUT(reg, PCI_LMR_LCTL_UMODEL) == 0)

sys/dev/pci/pci_subr.c

4432

PCIREG_SHIFTOUT(reg, PCI_LMR_LCTL_MPAYLOAD));

sys/dev/pci/pci_subr.c

4438

pcireg_t reg, lwidth;

sys/dev/pci/pci_subr.c

4445

reg = regs[o2i(extcapoff + PCI_LMR_PCAPSTAT)];

sys/dev/pci/pci_subr.c

4446

printf(" Port Capability register: 0x%04x\n", reg & 0xffff);

sys/dev/pci/pci_subr.c

4447

onoff("Margining uses Driver Software", reg, PCI_LMR_PCAP_MUDS);

sys/dev/pci/pci_subr.c

4448

printf(" Port Status register: 0x%04x\n", (reg >> 16) & 0xffff);

sys/dev/pci/pci_subr.c

4449

onoff("Margining Ready", reg, PCI_LMR_PSTAT_MR);

sys/dev/pci/pci_subr.c

4450

onoff("Margining Software Ready", reg, PCI_LMR_PSTAT_MSR);

sys/dev/pci/pci_subr.c

4456

reg = regs[o2i(pcie_capoff)];

sys/dev/pci/pci_subr.c

4457

pcie_devtype = PCIE_XCAP_TYPE(reg);

sys/dev/pci/pci_subr.c

4474

reg = regs[o2i(pcie_capoff + PCIE_LCAP)];

sys/dev/pci/pci_subr.c

4475

lwidth = PCIREG_SHIFTOUT(reg, PCIE_LCAP_MAX_WIDTH);

sys/dev/pci/pci_subr.c

4480

reg = regs[o2i(extcapoff + PCI_LMR_LANECSR + (i * 4))];

sys/dev/pci/pci_subr.c

4482

lctl = reg & 0xffff;

sys/dev/pci/pci_subr.c

4486

lstat = (reg >> 16) & 0xffff;

sys/dev/pci/pci_subr.c

925

pcireg_t reg;

sys/dev/pci/pci_subr.c

928

reg = regs[o2i(pcie_capoff + PCIE_XCAP)];

sys/dev/pci/pci_subr.c

929

if (PCIE_XCAP_TYPE(reg) == PCIE_XCAP_TYPE_RC_EVNTC)

sys/dev/pci/pci_subr.c

980

const pcireg_t *regs, int reg, const char *name)

sys/dev/pci/pci_usrreq.c

102

pci_conf_write(sc->sc_pc, tag, bdfr->cfgreg.reg,

sys/dev/pci/pci_usrreq.c

241

r->val = pci_conf_read(pc, tag, r->reg);

sys/dev/pci/pci_usrreq.c

247

pci_conf_write(pc, tag, r->reg, r->val);

sys/dev/pci/pci_usrreq.c

91

bdfr->function > 7 || ISSET(bdfr->cfgreg.reg, 3))

sys/dev/pci/pci_usrreq.c

98

bdfr->cfgreg.reg);

sys/dev/pci/pciconf.c

1004

if (pm->reg == PCI_MAPREG_ROM) {

sys/dev/pci/pciconf.c

1007

base = pci_conf_read(pd->pc, pd->tag, pm->reg);

sys/dev/pci/pciconf.c

1027

if (pd->ppb && pm->reg == 0) {

sys/dev/pci/pciconf.c

1048

if (pm->reg != PCI_MAPREG_ROM) {

sys/dev/pci/pciconf.c

1054

pm->address, pm->reg);

sys/dev/pci/pciconf.c

1056

base = pci_conf_read(pd->pc, pd->tag, pm->reg);

sys/dev/pci/pciconf.c

1059

pci_conf_write(pd->pc, pd->tag, pm->reg, base);

sys/dev/pci/pciconf.c

1064

pci_conf_write(pd->pc, pd->tag, pm->reg + 4,

sys/dev/pci/pciconf.c

1077

if (!pci_bar_is_reserved(pb, pd, pm->reg)) {

sys/dev/pci/pciconf.c

1083

if (pm->reg == PCI_MAPREG_ROM && pm->address != -1) {

sys/dev/pci/pciconf.c

1092

pm->address, pm->reg);

sys/dev/pci/pciconf.c

1098

pci_conf_write(pd->pc, pd->tag, pm->reg, base);

sys/dev/pci/pciconf.c

145

int reg; /* 0 for busses */

sys/dev/pci/pciconf.c

468

pi->reg = 0;

sys/dev/pci/pciconf.c

487

pm->reg = 0;

sys/dev/pci/pciconf.c

505

pm->reg = 0;

sys/dev/pci/pciconf.c

724

pi->reg = br;

sys/dev/pci/pciconf.c

787

pm->reg = br;

sys/dev/pci/pciconf.c

824

pm->reg = PCI_MAPREG_ROM;

sys/dev/pci/pciconf.c

923

rsvd = pci_bar_is_reserved(pb, pd, pi->reg);

sys/dev/pci/pciconf.c

940

if (pd->ppb && pi->reg == 0) {

sys/dev/pci/pciconf.c

961

" (reg %x)\n", pi->size, pi->address, pi->reg);

sys/dev/pci/pciconf.c

963

pci_conf_write(pd->pc, pd->tag, pi->reg,

sys/dev/pci/pciconf.c

989

rsvd = pci_bar_is_reserved(pb, pd, pm->reg);

sys/dev/pci/pciide_common.c

431

int reg, chan;

sys/dev/pci/pciide_common.c

518

for (reg = 0; reg < IDEDMA_NREGS; reg++) {

sys/dev/pci/pciide_common.c

520

if (size > (IDEDMA_SCH_OFFSET - reg))

sys/dev/pci/pciide_common.c

521

size = IDEDMA_SCH_OFFSET - reg;

sys/dev/pci/pciide_common.c

523

IDEDMA_SCH_OFFSET * chan + reg, size,

sys/dev/pci/pciide_common.c

524

&pc->dma_iohs[reg]) != 0) {

sys/dev/pci/pciide_common.c

527

"size %lu", reg, (u_long)size);

sys/dev/pci/pciide_opti_reg.h

109

opti_read_config(struct ata_channel *chp, int reg)

sys/dev/pci/pciide_opti_reg.h

123

rv = bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[reg], 0);

sys/dev/pci/pciide_opti_reg.h

134

opti_write_config(struct ata_channel *chp, int reg, u_int8_t val)

sys/dev/pci/pciide_opti_reg.h

147

bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[reg], 0, val);

sys/dev/pci/pciidevar.h

191

pciide_pci_read(pci_chipset_tag_t pc, pcitag_t pa, int reg)

sys/dev/pci/pciidevar.h

194

return (pci_conf_read(pc, pa, (reg & ~0x03)) >>

sys/dev/pci/pciidevar.h

195

((reg & 0x03) * 8) & 0xff);

sys/dev/pci/pciidevar.h

199

pciide_pci_write(pci_chipset_tag_t pc, pcitag_t pa, int reg, uint8_t val)

sys/dev/pci/pciidevar.h

203

pcival = pci_conf_read(pc, pa, (reg & ~0x03));

sys/dev/pci/pciidevar.h

204

pcival &= ~(0xff << ((reg & 0x03) * 8));

sys/dev/pci/pciidevar.h

205

pcival |= (val << ((reg & 0x03) * 8));

sys/dev/pci/pciidevar.h

206

pci_conf_write(pc, pa, (reg & ~0x03), pcival);

sys/dev/pci/pciio.h

53

u_int reg; /* offset into PCI configuration space */

sys/dev/pci/pcireg.h

1359

#define PCI_BRIDGE_BUS_NUM_PRIMARY(reg) \

sys/dev/pci/pcireg.h

1360

((uint32_t)__SHIFTOUT((reg), PCI_BRIDGE_BUS_PRIMARY))

sys/dev/pci/pcireg.h

1361

#define PCI_BRIDGE_BUS_NUM_SECONDARY(reg) \

sys/dev/pci/pcireg.h

1362

((uint32_t)__SHIFTOUT((reg), PCI_BRIDGE_BUS_SECONDARY))

sys/dev/pci/pcireg.h

1363

#define PCI_BRIDGE_BUS_NUM_SUBORDINATE(reg) \

sys/dev/pci/pcireg.h

1364

((uint32_t)__SHIFTOUT((reg), PCI_BRIDGE_BUS_SUBORDINATE))

sys/dev/pci/pcireg.h

1365

#define PCI_BRIDGE_BUS_SEC_LATTIMER_VAL(reg) \

sys/dev/pci/pcireg.h

1366

((uint32_t)__SHIFTOUT((reg), PCI_BRIDGE_BUS_SEC_LATTIMER))

sys/dev/pci/pcireg.h

1379

#define PCI_BRIDGE_STATIO_IOBASE_ADDR(reg) \

sys/dev/pci/pcireg.h

1380

((__SHIFTOUT((reg), PCI_BRIDGE_STATIO_IOBASE) \

sys/dev/pci/pcireg.h

1382

#define PCI_BRIDGE_STATIO_IOLIMIT_ADDR(reg) \

sys/dev/pci/pcireg.h

1383

(((__SHIFTOUT((reg), PCI_BRIDGE_STATIO_IOLIMIT) \

sys/dev/pci/pcireg.h

1385

#define PCI_BRIDGE_IO_32BITS(reg) \

sys/dev/pci/pcireg.h

1386

(((reg) & PCI_BRIDGE_STATIO_IOADDR_TYPE) == PCI_BRIDGE_STATIO_IOADDR_32)

sys/dev/pci/pcireg.h

1392

#define PCI_BRIDGE_MEMORY_BASE_ADDR(reg) \

sys/dev/pci/pcireg.h

1393

((__SHIFTOUT((reg), PCI_BRIDGE_MEMORY_BASE) \

sys/dev/pci/pcireg.h

1395

#define PCI_BRIDGE_MEMORY_LIMIT_ADDR(reg) \

sys/dev/pci/pcireg.h

1396

(((__SHIFTOUT((reg), PCI_BRIDGE_MEMORY_LIMIT) \

sys/dev/pci/pcireg.h

1403

#define PCI_BRIDGE_PREFETCHMEM_BASE_ADDR(reg) \

sys/dev/pci/pcireg.h

1404

((__SHIFTOUT((reg), PCI_BRIDGE_PREFETCHMEM_BASE) \

sys/dev/pci/pcireg.h

1406

#define PCI_BRIDGE_PREFETCHMEM_LIMIT_ADDR(reg) \

sys/dev/pci/pcireg.h

1407

(((__SHIFTOUT((reg), PCI_BRIDGE_PREFETCHMEM_LIMIT) \

sys/dev/pci/pcireg.h

1409

#define PCI_BRIDGE_PREFETCHMEM_64BITS(reg) ((reg) & 0xf)

sys/dev/pci/pcireg.h

718

#define PCI_MSI_CTL_MME(reg) __SHIFTOUT(reg, PCI_MSI_CTL_MME_MASK)

sys/dev/pci/pcireg.h

720

#define PCI_MSI_CTL_MMC(reg) __SHIFTOUT(reg, PCI_MSI_CTL_MMC_MASK)

sys/dev/pci/pcireg.h

760

#define PCIX_CMD_BYTECNT(reg) \

sys/dev/pci/pcireg.h

761

(512 << (((reg) & PCIX_CMD_BYTECNT_MASK) >> PCIX_CMD_BYTECNT_SHIFT))

sys/dev/pci/pcivar.h

234

pcireg_t reg[16];

sys/dev/pci/pcscp.c

329

pcscp_read_reg(struct ncr53c9x_softc *sc, int reg)

sys/dev/pci/pcscp.c

333

return PCSCP_READ_REG(esc, reg);

sys/dev/pci/pcscp.c

337

pcscp_write_reg(struct ncr53c9x_softc *sc, int reg, uint8_t v)

sys/dev/pci/pcscp.c

341

PCSCP_WRITE_REG(esc, reg, v);

sys/dev/pci/pcscp.c

88

#define READ_DMAREG(sc, reg) \

sys/dev/pci/pcscp.c

89

bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))

sys/dev/pci/pcscp.c

90

#define WRITE_DMAREG(sc, reg, var) \

sys/dev/pci/pcscp.c

91

bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (var))

sys/dev/pci/pcscp.c

93

#define PCSCP_READ_REG(sc, reg) \

sys/dev/pci/pcscp.c

94

bus_space_read_1((sc)->sc_st, (sc)->sc_sh, (reg) << 2)

sys/dev/pci/pcscp.c

95

#define PCSCP_WRITE_REG(sc, reg, val) \

sys/dev/pci/pcscp.c

96

bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg) << 2, (val))

sys/dev/pci/piixpm.c

532

uint8_t sctl, old_sda, index, mask, reg;

sys/dev/pci/piixpm.c

567

reg = piixpm_sb800_pmread(sc, index);

sys/dev/pci/piixpm.c

569

old_sda = __SHIFTOUT(reg, mask);

sys/dev/pci/piixpm.c

571

reg &= ~mask;

sys/dev/pci/piixpm.c

572

reg |= __SHIFTIN(smbus->sda, mask);

sys/dev/pci/piixpm.c

578

sc->sc_sb800_mmio ? index : SB800_INDIRECTIO_DATA, reg);

sys/dev/pci/piixpm.c

592

uint8_t sctl, index, mask, reg;

sys/dev/pci/piixpm.c

608

reg = piixpm_sb800_pmread(sc, index);

sys/dev/pci/piixpm.c

609

reg &= ~mask;

sys/dev/pci/piixpm.c

610

reg |= __SHIFTIN(smbus->sda_save, mask);

sys/dev/pci/piixpm.c

616

sc->sc_sb800_mmio ? index : SB800_INDIRECTIO_DATA, reg);

sys/dev/pci/pm2fb.c

1103

uint32_t reg;

sys/dev/pci/pm2fb.c

1105

reg = *data8;

sys/dev/pci/pm2fb.c

1108

PM2_RE_BITMASK, reg);

sys/dev/pci/pm2fb.c

1115

uint32_t reg;

sys/dev/pci/pm2fb.c

1117

reg = *data16;

sys/dev/pci/pm2fb.c

1120

PM2_RE_BITMASK, reg);

sys/dev/pci/pm2fb.c

1524

uint8_t reg, bm = 0, bn = 0, bp = 0;

sys/dev/pci/pm2fb.c

1550

reg = bus_space_read_1(sc->sc_memt, sc->sc_regh,

sys/dev/pci/pm2fb.c

1552

} while (reg == PCLK_LOCKED);

sys/dev/pci/pm2fb.c

264

uint32_t reg;

sys/dev/pci/pm2fb.c

267

reg = bus_space_read_4(sc->sc_memt, sc->sc_regh,

sys/dev/pci/pm2fb.c

269

} while (reg <= slots);

sys/dev/pci/pm2fb.c

748

pm2fb_read_dac(struct pm2fb_softc *sc, int reg)

sys/dev/pci/pm2fb.c

752

PM2_DAC_PAL_WRITE_IDX, reg);

sys/dev/pci/pm2fb.c

757

PM2V_DAC_INDEX_LOW, reg & 0xff);

sys/dev/pci/pm2fb.c

759

PM2V_DAC_INDEX_HIGH, (reg >> 8) & 0xff);

sys/dev/pci/pm2fb.c

766

pm2fb_write_dac(struct pm2fb_softc *sc, int reg, uint8_t data)

sys/dev/pci/pm2fb.c

772

PM2_DAC_PAL_WRITE_IDX, reg);

sys/dev/pci/pm2fb.c

778

PM2V_DAC_INDEX_LOW, reg & 0xff);

sys/dev/pci/pm2fb.c

780

PM2V_DAC_INDEX_HIGH, (reg >> 8) & 0xff);

sys/dev/pci/pm3fb.c

179

uint32_t reg;

sys/dev/pci/pm3fb.c

182

reg = bus_space_read_4(sc->sc_memt, sc->sc_regh,

sys/dev/pci/pm3fb.c

184

} while (reg <= slots);

sys/dev/pci/pm3fb.c

622

pm3fb_write_dac(struct pm3fb_softc *sc, int reg, uint8_t data)

sys/dev/pci/pm3fb.c

626

bus_space_write_1(sc->sc_memt, sc->sc_regh, PM3_DAC_INDEX_LOW, reg & 0xff);

sys/dev/pci/pm3fb.c

627

bus_space_write_1(sc->sc_memt, sc->sc_regh, PM3_DAC_INDEX_HIGH, (reg >> 8) & 0xff);

sys/dev/pci/pm3fb.c

928

uint32_t reg;

sys/dev/pci/pm3fb.c

930

reg = *data8;

sys/dev/pci/pm3fb.c

933

PM3_BITMASKPATTERN, reg);

sys/dev/pci/pm3fb.c

940

uint32_t reg;

sys/dev/pci/pm3fb.c

942

reg = *data16;

sys/dev/pci/pm3fb.c

945

PM3_BITMASKPATTERN, reg);

sys/dev/pci/ppb.c

120

pcireg_t reg;

sys/dev/pci/ppb.c

124

&off, &reg))

sys/dev/pci/ppb.c

127

capversion = PCIE_XCAP_VER(reg);

sys/dev/pci/ppb.c

128

devtype = PCIE_XCAP_TYPE(reg);

sys/dev/pci/ppb.c

173

reg = pci_conf_read(sc->sc_pc, sc->sc_tag, off + PCIE_LCAP);

sys/dev/pci/ppb.c

174

u_int mlw = __SHIFTOUT(reg, PCIE_LCAP_MAX_WIDTH);

sys/dev/pci/ppb.c

175

u_int mls = __SHIFTOUT(reg, PCIE_LCAP_MAX_SPEED);

sys/dev/pci/ppb.c

185

reg = pci_conf_read(sc->sc_pc, sc->sc_tag, off + PCIE_LCSR);

sys/dev/pci/ppb.c

186

if (reg & PCIE_LCSR_DLACTIVE) { /* DLLA */

sys/dev/pci/ppb.c

187

u_int lw = __SHIFTOUT(reg, PCIE_LCSR_NLW);

sys/dev/pci/ppb.c

188

u_int ls = __SHIFTOUT(reg, PCIE_LCSR_LINKSPEED);

sys/dev/pci/ppb.c

220

pcireg_t busdata, reg;

sys/dev/pci/ppb.c

252

&sc->sc_pciecapoff, &reg) && (reg & PCIE_XCAP_SI)) {

sys/dev/pci/ppb.c

257

reg = pci_conf_read(sc->sc_pc, sc->sc_tag,

sys/dev/pci/ppb.c

259

if (reg & PCIE_SLCSR_ENABLE_MASK) {

sys/dev/pci/ppb.c

260

reg &= ~PCIE_SLCSR_ENABLE_MASK;

sys/dev/pci/ppb.c

262

sc->sc_pciecapoff + PCIE_SLCSR, reg);

sys/dev/pci/ppb.c

363

reg = pci_conf_read(pc, pa->pa_tag, PCI_BRIDGE_STATIO_REG);

sys/dev/pci/ppb.c

364

base = PCI_BRIDGE_STATIO_IOBASE_ADDR(reg);

sys/dev/pci/ppb.c

365

limit = PCI_BRIDGE_STATIO_IOLIMIT_ADDR(reg);

sys/dev/pci/ppb.c

366

if (PCI_BRIDGE_IO_32BITS(reg)) {

sys/dev/pci/ppb.c

367

reg = pci_conf_read(pc, pa->pa_tag,

sys/dev/pci/ppb.c

369

base |= __SHIFTOUT(reg, PCI_BRIDGE_IOHIGH_BASE) << 16;

sys/dev/pci/ppb.c

370

limit |= __SHIFTOUT(reg, PCI_BRIDGE_IOHIGH_LIMIT) <<16;

sys/dev/pci/ppb.c

378

reg = pci_conf_read(pc, pa->pa_tag, PCI_BRIDGE_MEMORY_REG);

sys/dev/pci/ppb.c

379

base = PCI_BRIDGE_MEMORY_BASE_ADDR(reg);

sys/dev/pci/ppb.c

380

limit = PCI_BRIDGE_MEMORY_LIMIT_ADDR(reg);

sys/dev/pci/ppb.c

387

reg = pci_conf_read(pc, pa->pa_tag,

sys/dev/pci/ppb.c

389

base = PCI_BRIDGE_PREFETCHMEM_BASE_ADDR(reg);

sys/dev/pci/ppb.c

390

limit = PCI_BRIDGE_PREFETCHMEM_LIMIT_ADDR(reg);

sys/dev/pci/ppb.c

392

if (PCI_BRIDGE_PREFETCHMEM_64BITS(reg)) {

sys/dev/pci/ppb.c

393

reg = pci_conf_read(pc, pa->pa_tag,

sys/dev/pci/ppb.c

412

reg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);

sys/dev/pci/ppb.c

413

if ((reg & PCI_COMMAND_MASTER_ENABLE) == 0)

sys/dev/pci/ppb.c

415

reg | PCI_COMMAND_MASTER_ENABLE);

sys/dev/pci/ppb.c

529

pcireg_t reg;

sys/dev/pci/ppb.c

531

reg = pci_conf_read(sc->sc_pc, sc->sc_tag,

sys/dev/pci/ppb.c

538

if ((reg & PCIE_SLCSR_STATCHG_MASK) == 0)

sys/dev/pci/ppb.c

543

sc->sc_pciecapoff + PCIE_SLCSR, reg);

sys/dev/pci/ppb.c

548

if (reg & PCIE_SLCSR_ABP) {

sys/dev/pci/ppb.c

555

if (reg & PCIE_SLCSR_PFD) {

sys/dev/pci/ppb.c

562

if (reg & PCIE_SLCSR_MSC) {

sys/dev/pci/ppb.c

569

if (reg & PCIE_SLCSR_PDC) {

sys/dev/pci/ppb.c

573

if (reg & PCIE_SLCSR_PDS) {

sys/dev/pci/ppb.c

581

if (reg & PCIE_SLCSR_CC) {

sys/dev/pci/ppb.c

588

if (reg & PCIE_SLCSR_LACS) {

sys/dev/pci/puccn.c

112

reg = pci_conf_read(pa.pa_pc, pa.pa_tag, PCI_ID_REG);

sys/dev/pci/puccn.c

113

if (PCI_VENDOR(reg) == PCI_VENDOR_INVALID

sys/dev/pci/puccn.c

114

|| PCI_VENDOR(reg) == 0)

sys/dev/pci/puccn.c

125

reg = pci_conf_read(pa.pa_pc, pa.pa_tag,

sys/dev/pci/puccn.c

127

if (PCI_CLASS(reg) == PCI_CLASS_COMMUNICATIONS

sys/dev/pci/puccn.c

128

&& PCI_SUBCLASS(reg)

sys/dev/pci/puccn.c

96

pcireg_t reg, bhlcr, subsys = 0; /* XXX */

sys/dev/pci/qat/qat_ae.c

1041

uint32_t times, reset, clock, reg, mask;

sys/dev/pci/qat/qat_ae.c

1054

reg = qat_cap_global_read_4(sc, CAP_GLOBAL_CTL_RESET);

sys/dev/pci/qat/qat_ae.c

1057

& reg);

sys/dev/pci/qat/qat_ae.c

1190

u_int mask, reg;

sys/dev/pci/qat/qat_ae.c

1197

for (reg = 0; reg < MAX_GPR_REG; reg++) {

sys/dev/pci/qat/qat_ae.c

1199

reg, 0);

sys/dev/pci/qat/qat_ae.c

1201

reg, 0);

sys/dev/pci/qat/qat_ae.c

1798

qat_aefw_csum_calc(u_int reg, int ch)

sys/dev/pci/qat/qat_ae.c

1802

u_int inbyte = (u_int)((reg >> 0x18) ^ ch);

sys/dev/pci/qat/qat_ae.c

1804

reg ^= inbyte << (CRC_WIDTH - 0x8);

sys/dev/pci/qat/qat_ae.c

1806

if (reg & topbit)

sys/dev/pci/qat/qat_ae.c

1807

reg = (reg << 1) ^ CRC_POLY;

sys/dev/pci/qat/qat_ae.c

1809

reg <<= 1;

sys/dev/pci/qat/qat_ae.c

1812

return (reg & CRC_WIDTHMASK(CRC_WIDTH));

sys/dev/pci/qat/qat_ae.c

299

qat_aereg_get_10bit_addr(enum aereg_type regtype, u_short reg)

sys/dev/pci/qat/qat_ae.c

306

addr = (reg & 0x7f) | 0x80;

sys/dev/pci/qat/qat_ae.c

310

addr = reg & 0x1f;

sys/dev/pci/qat/qat_ae.c

315

addr = 0x180 | (reg & 0x1f);

sys/dev/pci/qat/qat_ae.c

318

addr = 0x140 | ((reg & 0x3) << 1);

sys/dev/pci/qat/qat_ae.c

323

addr = 0x1c0 | (reg & 0x1f);

sys/dev/pci/qat/qat_ae.c

326

addr = 0x100 | ((reg & 0x3) << 1);

sys/dev/pci/qat/qat_ae.c

329

addr = 0x241 | ((reg & 0x3) << 1);

sys/dev/pci/qat/qat_ae.c

332

addr = 0x280 | (reg & 0x1f);

sys/dev/pci/qat/qat_ae.c

341

addr = 0x300 | (reg & 0xff);

sys/dev/pci/qat/qatvar.h

975

uint32_t reg;

sys/dev/pci/qat/qatvar.h

977

reg = qat_misc_read_4(sc, offset);

sys/dev/pci/qat/qatvar.h

978

reg |= value;

sys/dev/pci/qat/qatvar.h

979

qat_misc_write_4(sc, offset, reg);

sys/dev/pci/qat/qatvar.h

986

uint32_t reg;

sys/dev/pci/qat/qatvar.h

988

reg = qat_misc_read_4(sc, offset);

sys/dev/pci/qat/qatvar.h

989

reg &= mask;

sys/dev/pci/qat/qatvar.h

990

qat_misc_write_4(sc, offset, reg);

sys/dev/pci/r128fb.c

1126

uint32_t reg;

sys/dev/pci/r128fb.c

1143

reg = bus_space_read_4(sc->sc_memt, sc->sc_regh, R128_LVDS_GEN_CNTL);

sys/dev/pci/r128fb.c

1144

reg &= ~R128_LEVEL_MASK;

sys/dev/pci/r128fb.c

1145

reg |= (level << R128_LEVEL_SHIFT);

sys/dev/pci/r128fb.c

1146

bus_space_write_4(sc->sc_memt, sc->sc_regh, R128_LVDS_GEN_CNTL, reg);

sys/dev/pci/r128fb.c

1147

DPRINTF("backlight level: %d reg %08x\n", level, reg);

sys/dev/pci/r128fb.c

1153

uint32_t reg;

sys/dev/pci/r128fb.c

1159

reg = bus_space_read_4(sc->sc_memt, sc->sc_regh, R128_LVDS_GEN_CNTL);

sys/dev/pci/r128fb.c

1160

reg &= ~R128_LEVEL_MASK;

sys/dev/pci/r128fb.c

1162

reg |= level << R128_LEVEL_SHIFT;

sys/dev/pci/r128fb.c

1163

bus_space_write_4(sc->sc_memt, sc->sc_regh, R128_LVDS_GEN_CNTL, reg);

sys/dev/pci/r128fb.c

1164

DPRINTF("backlight state: %d reg %08x\n", on, reg);

sys/dev/pci/r128fb.c

148

uint32_t reg;

sys/dev/pci/r128fb.c

151

reg = (bus_space_read_4(sc->sc_memt, sc->sc_regh,

sys/dev/pci/r128fb.c

153

} while (reg <= slots);

sys/dev/pci/r128fb.c

159

uint32_t reg;

sys/dev/pci/r128fb.c

161

reg = bus_space_read_4(sc->sc_memt, sc->sc_regh, R128_PC_NGUI_CTLSTAT);

sys/dev/pci/r128fb.c

162

reg |= R128_PC_FLUSH_ALL;

sys/dev/pci/r128fb.c

163

bus_space_write_4(sc->sc_memt, sc->sc_regh, R128_PC_NGUI_CTLSTAT, reg);

sys/dev/pci/r128fb.c

165

reg = bus_space_read_4(sc->sc_memt, sc->sc_regh,

sys/dev/pci/r128fb.c

167

} while (reg & R128_PC_BUSY);

sys/dev/pci/r128fb.c

201

uint32_t reg, flags;

sys/dev/pci/r128fb.c

337

reg = bus_space_read_4(sc->sc_memt, sc->sc_regh, R128_LVDS_GEN_CNTL);

sys/dev/pci/r128fb.c

338

DPRINTF("R128_LVDS_GEN_CNTL: %08x\n", reg);

sys/dev/pci/r128fb.c

339

if (reg & R128_LVDS_ON) {

sys/dev/pci/r128fb.c

343

((reg & R128_LEVEL_MASK) >> R128_LEVEL_SHIFT);

sys/dev/pci/r128fb.c

648

uint32_t reg;

sys/dev/pci/r128fb.c

651

reg = (r << 16) | (g << 8) | b;

sys/dev/pci/r128fb.c

653

bus_space_write_4(sc->sc_memt, sc->sc_regh, R128_PALETTE_DATA, reg);

sys/dev/pci/r128fb.c

660

uint32_t datatype, d, reg;

sys/dev/pci/r128fb.c

727

reg = bus_space_read_4(sc->sc_memt, sc->sc_regh, R128_CRTC_GEN_CNTL);

sys/dev/pci/r128fb.c

728

DPRINTF("depth: %d\n", reg & R128_CRTC_PIX_WIDTH);

sys/dev/pci/r128fb.c

729

reg &= ~R128_CRTC_PIX_WIDTH;

sys/dev/pci/r128fb.c

730

reg |= d;

sys/dev/pci/r128fb.c

731

bus_space_write_4(sc->sc_memt, sc->sc_regh, R128_CRTC_GEN_CNTL, reg);

sys/dev/pci/r128fb.c

908

uint32_t reg;

sys/dev/pci/r128fb.c

910

reg = *data8;

sys/dev/pci/r128fb.c

912

sc->sc_regh, R128_HOST_DATA0, reg);

sys/dev/pci/r128fb.c

919

uint32_t reg;

sys/dev/pci/r128fb.c

921

reg = *data16;

sys/dev/pci/r128fb.c

923

sc->sc_regh, R128_HOST_DATA0, reg);

sys/dev/pci/radeonfb.c

1497

radeonfb_get32(struct radeonfb_softc *sc, uint32_t reg)

sys/dev/pci/radeonfb.c

1500

return bus_space_read_4(sc->sc_regt, sc->sc_regh, reg);

sys/dev/pci/radeonfb.c

1504

radeonfb_put32(struct radeonfb_softc *sc, uint32_t reg, uint32_t val)

sys/dev/pci/radeonfb.c

1507

bus_space_write_4(sc->sc_regt, sc->sc_regh, reg, val);

sys/dev/pci/radeonfb.c

1511

radeonfb_put32s(struct radeonfb_softc *sc, uint32_t reg, uint32_t val)

sys/dev/pci/radeonfb.c

1514

bus_space_write_stream_4(sc->sc_regt, sc->sc_regh, reg, val);

sys/dev/pci/radeonfb.c

1518

radeonfb_mask32(struct radeonfb_softc *sc, uint32_t reg,

sys/dev/pci/radeonfb.c

1525

val = radeonfb_get32(sc, reg);

sys/dev/pci/radeonfb.c

1527

radeonfb_put32(sc, reg, val);

sys/dev/pci/radeonfb.c

1618

radeonfb_scratch_test(struct radeonfb_softc *sc, int reg, uint32_t v)

sys/dev/pci/radeonfb.c

1622

saved = GET32(sc, reg);

sys/dev/pci/radeonfb.c

1623

PUT32(sc, reg, v);

sys/dev/pci/radeonfb.c

1624

if (GET32(sc, reg) != v) {

sys/dev/pci/radeonfb.c

1627

PUT32(sc, reg, saved);

sys/dev/pci/radeonfb.c

2640

uint32_t reg, mask;

sys/dev/pci/radeonfb.c

2646

reg = GET32(sc, AVIVO_D1CRTC_CONTROL);

sys/dev/pci/radeonfb.c

2647

return ((reg & AVIVO_CRTC_EN) == 0);

sys/dev/pci/radeonfb.c

2651

reg = RADEON_CRTC2_GEN_CNTL;

sys/dev/pci/radeonfb.c

2654

reg = RADEON_CRTC_EXT_CNTL;

sys/dev/pci/radeonfb.c

2657

return ((GET32(dp->rd_softc, reg) & mask) ? 1 : 0);

sys/dev/pci/radeonfb.c

2664

uint32_t reg, mask;

sys/dev/pci/radeonfb.c

2692

reg = RADEON_CRTC2_GEN_CNTL;

sys/dev/pci/radeonfb.c

2697

reg = RADEON_CRTC_EXT_CNTL;

sys/dev/pci/radeonfb.c

2704

SET32(sc, reg, mask);

sys/dev/pci/radeonfb.c

2710

CLR32(sc, reg, mask);

sys/dev/pci/radeonfb.c

3147

uint32_t reg;

sys/dev/pci/radeonfb.c

3209

reg = *data8;

sys/dev/pci/radeonfb.c

3210

reg |= reg >> 1;

sys/dev/pci/radeonfb.c

3212

reg = reg << 24;

sys/dev/pci/radeonfb.c

3215

sc->sc_regh, RADEON_HOST_DATA0, reg);

sys/dev/pci/radeonfb.c

3223

reg = *data16;

sys/dev/pci/radeonfb.c

3224

reg |= reg >> 1;

sys/dev/pci/radeonfb.c

3226

reg = reg << 16;

sys/dev/pci/radeonfb.c

3229

sc->sc_regh, RADEON_HOST_DATA0, reg);

sys/dev/pci/radeonfb.c

3237

reg = *data32;

sys/dev/pci/radeonfb.c

3238

reg |= reg >> 1;

sys/dev/pci/radeonfb.c

3240

sc->sc_regh, RADEON_HOST_DATA0, reg);

sys/dev/pci/radeonfb.c

3251

reg = *data8;

sys/dev/pci/radeonfb.c

3253

reg = reg << 24;

sys/dev/pci/radeonfb.c

3256

sc->sc_regh, RADEON_HOST_DATA0, reg);

sys/dev/pci/radeonfb.c

3264

reg = *data16;

sys/dev/pci/radeonfb.c

3266

reg = reg << 16;

sys/dev/pci/radeonfb.c

3269

sc->sc_regh, RADEON_HOST_DATA0, reg);

sys/dev/pci/radeonfb.c

3277

reg = *data32;

sys/dev/pci/radeonfb.c

3279

sc->sc_regh, RADEON_HOST_DATA0, reg);

sys/dev/pci/rtsx_pci.c

100

pcireg_t reg;

sys/dev/pci/rtsx_pci.c

168

reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);

sys/dev/pci/rtsx_pci.c

169

reg |= PCI_COMMAND_MASTER_ENABLE;

sys/dev/pci/rtsx_pci.c

170

pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg);

sys/dev/pci/satalink.c

330

ba5_read_4_ind(struct pciide_softc *sc, bus_addr_t reg)

sys/dev/pci/satalink.c

336

pci_conf_write(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_ADDR, reg);

sys/dev/pci/satalink.c

344

ba5_read_4(struct pciide_softc *sc, bus_addr_t reg)

sys/dev/pci/satalink.c

348

return (bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, reg));

sys/dev/pci/satalink.c

350

return (ba5_read_4_ind(sc, reg));

sys/dev/pci/satalink.c

353

#define BA5_READ_4(sc, chan, reg) \

sys/dev/pci/satalink.c

354

ba5_read_4((sc), satalink_ba5_regmap[(chan)].reg)

sys/dev/pci/satalink.c

357

ba5_write_4_ind(struct pciide_softc *sc, bus_addr_t reg, uint32_t val)

sys/dev/pci/satalink.c

362

pci_conf_write(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_ADDR, reg);

sys/dev/pci/satalink.c

368

ba5_write_4(struct pciide_softc *sc, bus_addr_t reg, uint32_t val)

sys/dev/pci/satalink.c

372

bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, reg, val);

sys/dev/pci/satalink.c

374

ba5_write_4_ind(sc, reg, val);

sys/dev/pci/satalink.c

377

#define BA5_WRITE_4(sc, chan, reg, val) \

sys/dev/pci/satalink.c

378

ba5_write_4((sc), satalink_ba5_regmap[(chan)].reg, (val))

sys/dev/pci/satalink.c

395

pcireg_t cls, reg;

sys/dev/pci/satalink.c

413

reg = ba5_read_4(sc, addr[i]);

sys/dev/pci/satalink.c

414

if ((reg & 0x7) < cls)

sys/dev/pci/satalink.c

415

ba5_write_4(sc, addr[i], (reg & 0x07) | cls);

sys/dev/pci/satalink.c

545

int chan, reg;

sys/dev/pci/satalink.c

569

for (reg = 0; reg < IDEDMA_NREGS; reg++) {

sys/dev/pci/satalink.c

571

if (size > (IDEDMA_SCH_OFFSET - reg))

sys/dev/pci/satalink.c

572

size = IDEDMA_SCH_OFFSET - reg;

sys/dev/pci/satalink.c

575

satalink_ba5_regmap[chan].ba5_IDEDMA_CMD + reg,

sys/dev/pci/satalink.c

576

size, &pc->dma_iohs[reg]) != 0) {

sys/dev/pci/satalink.c

581

chan].ba5_IDEDMA_CMD + reg,

sys/dev/pci/sdhc_pci.c

345

int reg;

sys/dev/pci/sdhc_pci.c

416

for (reg = SDHC_PCI_BAR_START + SDHC_PCI_FIRST_BAR(slotinfo) *

sys/dev/pci/sdhc_pci.c

418

reg < SDHC_PCI_BAR_END && nslots > 0;

sys/dev/pci/sdhc_pci.c

419

reg += width, nslots--) {

sys/dev/pci/sdhc_pci.c

422

type = pci_mapreg_type(pa->pa_pc, pa->pa_tag, reg);

sys/dev/pci/sdhc_pci.c

431

if (pci_mapreg_map(pa, reg, type, 0,

sys/dev/pci/sdhc_pci.c

440

"couldn't initialize host (0x%x)\n", reg);

sys/dev/pci/sdhc_pci.c

486

sdhc_pci_conf_write(struct pci_attach_args *pa, int reg, uint8_t val)

sys/dev/pci/sdhc_pci.c

490

r = pci_conf_read(pa->pa_pc, pa->pa_tag, reg & ~0x3);

sys/dev/pci/sdhc_pci.c

491

r &= ~(0xff << ((reg & 0x3) * 8));

sys/dev/pci/sdhc_pci.c

492

r |= (val << ((reg & 0x3) * 8));

sys/dev/pci/sdhc_pci.c

493

pci_conf_write(pa->pa_pc, pa->pa_tag, reg & ~0x3, r);

sys/dev/pci/sdhc_pci.c

505

pcireg_t id, reg;

sys/dev/pci/sdhc_pci.c

525

reg = pci_conf_read(pc, tag, SDHC_PCI_GENERAL_CTL);

sys/dev/pci/sdhc_pci.c

526

reg |= MMC_SD_DIS;

sys/dev/pci/sdhc_pci.c

527

pci_conf_write(pc, tag, SDHC_PCI_GENERAL_CTL, reg);

sys/dev/pci/sdhc_pci.c

559

uint8_t reg;

sys/dev/pci/sdhc_pci.c

563

reg = sdhc_host_read_1(hp, SDHC_POWER_CTL);

sys/dev/pci/sdhc_pci.c

564

reg |= 0x10;

sys/dev/pci/sdhc_pci.c

565

sdhc_host_write_1(hp, SDHC_POWER_CTL, reg);

sys/dev/pci/sdhc_pci.c

569

reg &= ~0x10;

sys/dev/pci/sdhc_pci.c

570

sdhc_host_write_1(hp, SDHC_POWER_CTL, reg);

sys/dev/pci/siside.c

184

pcireg_t id, masqid, reg;

sys/dev/pci/siside.c

191

reg = pci_conf_read(pa->pa_pc, pa->pa_tag, SIS96x_DETECT);

sys/dev/pci/siside.c

193

reg | SIS96x_DETECT_MASQ);

sys/dev/pci/siside.c

198

reg);

sys/dev/pci/sv.c

1004

uint8_t reg;

sys/dev/pci/sv.c

1021

reg = sv_read_indirect(sc, ports[idx].l_port);

sys/dev/pci/sv.c

1023

reg |= SV_MUTE_BIT;

sys/dev/pci/sv.c

1025

reg &= ~SV_MUTE_BIT;

sys/dev/pci/sv.c

1026

sv_write_indirect(sc, ports[idx].l_port, reg);

sys/dev/pci/sv.c

1029

reg = sv_read_indirect(sc, ports[idx].r_port);

sys/dev/pci/sv.c

1031

reg |= SV_MUTE_BIT;

sys/dev/pci/sv.c

1033

reg &= ~SV_MUTE_BIT;

sys/dev/pci/sv.c

1034

sv_write_indirect(sc, ports[idx].r_port, reg);

sys/dev/pci/sv.c

1061

reg = sv_read_indirect(sc, ports[idx].l_port);

sys/dev/pci/sv.c

1062

reg &= ~(ports[idx].mask);

sys/dev/pci/sv.c

1065

reg |= lval;

sys/dev/pci/sv.c

1066

sv_write_indirect(sc, ports[idx].l_port, reg);

sys/dev/pci/sv.c

1069

reg = sv_read_indirect(sc, ports[idx].r_port);

sys/dev/pci/sv.c

1070

reg &= ~(ports[idx].mask);

sys/dev/pci/sv.c

1074

reg |= rval;

sys/dev/pci/sv.c

1076

sv_write_indirect(sc, ports[idx].r_port, reg);

sys/dev/pci/sv.c

1101

reg = sv_read_indirect(sc, SV_LEFT_ADC_INPUT_CONTROL);

sys/dev/pci/sv.c

1102

reg &= ~SV_REC_SOURCE_MASK;

sys/dev/pci/sv.c

1103

reg |= (((cp->un.ord) << SV_REC_SOURCE_SHIFT) & SV_REC_SOURCE_MASK);

sys/dev/pci/sv.c

1104

sv_write_indirect(sc, SV_LEFT_ADC_INPUT_CONTROL, reg);

sys/dev/pci/sv.c

1106

reg = sv_read_indirect(sc, SV_RIGHT_ADC_INPUT_CONTROL);

sys/dev/pci/sv.c

1107

reg &= ~SV_REC_SOURCE_MASK;

sys/dev/pci/sv.c

1108

reg |= (((cp->un.ord) << SV_REC_SOURCE_SHIFT) & SV_REC_SOURCE_MASK);

sys/dev/pci/sv.c

1109

sv_write_indirect(sc, SV_RIGHT_ADC_INPUT_CONTROL, reg);

sys/dev/pci/sv.c

1127

reg = sv_read_indirect(sc, SV_LEFT_ADC_INPUT_CONTROL);

sys/dev/pci/sv.c

1128

reg &= ~SV_REC_GAIN_MASK;

sys/dev/pci/sv.c

1129

reg |= val;

sys/dev/pci/sv.c

1130

sv_write_indirect(sc, SV_LEFT_ADC_INPUT_CONTROL, reg);

sys/dev/pci/sv.c

1132

reg = sv_read_indirect(sc, SV_RIGHT_ADC_INPUT_CONTROL);

sys/dev/pci/sv.c

1133

reg &= ~SV_REC_GAIN_MASK;

sys/dev/pci/sv.c

1134

reg |= val;

sys/dev/pci/sv.c

1135

sv_write_indirect(sc, SV_RIGHT_ADC_INPUT_CONTROL, reg);

sys/dev/pci/sv.c

1145

reg = sv_read_indirect(sc, SV_LEFT_ADC_INPUT_CONTROL);

sys/dev/pci/sv.c

1147

reg |= SV_MIC_BOOST_BIT;

sys/dev/pci/sv.c

1149

reg &= ~SV_MIC_BOOST_BIT;

sys/dev/pci/sv.c

1152

sv_write_indirect(sc, SV_LEFT_ADC_INPUT_CONTROL, reg);

sys/dev/pci/sv.c

1161

reg = sv_read_indirect(sc, SV_SRS_SPACE_CONTROL);

sys/dev/pci/sv.c

1163

reg &= ~SV_SRS_SPACE_ONOFF;

sys/dev/pci/sv.c

1165

reg |= SV_SRS_SPACE_ONOFF;

sys/dev/pci/sv.c

1168

sv_write_indirect(sc, SV_SRS_SPACE_CONTROL, reg);

sys/dev/pci/sv.c

1181

uint8_t reg;

sys/dev/pci/sv.c

1201

reg = sv_read_indirect(sc, ports[idx].l_port);

sys/dev/pci/sv.c

1202

cp->un.ord = ((reg & SV_MUTE_BIT) ? 1 : 0);

sys/dev/pci/sv.c

1214

reg = sv_read_indirect(sc, ports[idx].l_port);

sys/dev/pci/sv.c

1215

reg &= ports[idx].mask;

sys/dev/pci/sv.c

1218

((reg * AUDIO_MAX_GAIN) / ports[idx].mask);

sys/dev/pci/sv.c

1224

reg = sv_read_indirect(sc,

sys/dev/pci/sv.c

1226

reg &= ports[idx].mask;

sys/dev/pci/sv.c

1229

((reg * AUDIO_MAX_GAIN)

sys/dev/pci/sv.c

1250

reg = sv_read_indirect(sc, SV_LEFT_ADC_INPUT_CONTROL);

sys/dev/pci/sv.c

1251

cp->un.ord = ((reg & SV_REC_SOURCE_MASK) >> SV_REC_SOURCE_SHIFT);

sys/dev/pci/sv.c

1265

reg = sv_read_indirect(sc, SV_LEFT_ADC_INPUT_CONTROL) & SV_REC_GAIN_MASK;

sys/dev/pci/sv.c

1267

(((unsigned int)reg) * AUDIO_MAX_GAIN) / SV_REC_GAIN_MASK;

sys/dev/pci/sv.c

1276

reg = sv_read_indirect(sc, SV_LEFT_ADC_INPUT_CONTROL);

sys/dev/pci/sv.c

1277

cp->un.ord = ((reg & SV_MIC_BOOST_BIT) ? 1 : 0);

sys/dev/pci/sv.c

1285

reg = sv_read_indirect(sc, SV_SRS_SPACE_CONTROL);

sys/dev/pci/sv.c

1286

cp->un.ord = ((reg & SV_SRS_SPACE_ONOFF) ? 0 : 1);

sys/dev/pci/sv.c

201

sv_write(struct sv_softc *sc, uint8_t reg, uint8_t val)

sys/dev/pci/sv.c

204

DPRINTFN(8,("sv_write(0x%x, 0x%x)\n", reg, val));

sys/dev/pci/sv.c

205

bus_space_write_1(sc->sc_iot, sc->sc_ioh, reg, val);

sys/dev/pci/sv.c

209

sv_read(struct sv_softc *sc, uint8_t reg)

sys/dev/pci/sv.c

213

val = bus_space_read_1(sc->sc_iot, sc->sc_ioh, reg);

sys/dev/pci/sv.c

214

DPRINTFN(8,("sv_read(0x%x) = 0x%x\n", reg, val));

sys/dev/pci/sv.c

219

sv_read_indirect(struct sv_softc *sc, uint8_t reg)

sys/dev/pci/sv.c

223

sv_write(sc, SV_CODEC_IADDR, reg & SV_IADDR_MASK);

sys/dev/pci/sv.c

229

sv_write_indirect(struct sv_softc *sc, uint8_t reg, uint8_t val)

sys/dev/pci/sv.c

233

iaddr = reg & SV_IADDR_MASK;

sys/dev/pci/sv.c

234

if (reg == SV_DMA_DATA_FORMAT)

sys/dev/pci/sv.c

331

uint8_t reg;

sys/dev/pci/sv.c

390

reg = sv_read(sc, SV_CODEC_CONTROL);

sys/dev/pci/sv.c

391

reg |= SV_CTL_RESET;

sys/dev/pci/sv.c

392

sv_write(sc, SV_CODEC_CONTROL, reg);

sys/dev/pci/sv.c

395

reg = sv_read(sc, SV_CODEC_CONTROL);

sys/dev/pci/sv.c

396

reg &= ~SV_CTL_RESET;

sys/dev/pci/sv.c

397

reg |= SV_CTL_INTA | SV_CTL_ENHANCED;

sys/dev/pci/sv.c

400

sv_write(sc, SV_CODEC_CONTROL, reg);

sys/dev/pci/sv.c

404

sv_write(sc, SV_CODEC_CONTROL, reg);

sys/dev/pci/sv.c

439

reg = sv_read(sc, SV_CODEC_INTMASK);

sys/dev/pci/sv.c

440

reg &= ~(SV_INTMASK_DMAA | SV_INTMASK_DMAC);

sys/dev/pci/sv.c

441

reg |= SV_INTMASK_UD | SV_INTMASK_SINT | SV_INTMASK_MIDI;

sys/dev/pci/sv.c

442

sv_write(sc, SV_CODEC_INTMASK, reg);

sys/dev/pci/svwsata.c

196

int chan, reg;

sys/dev/pci/svwsata.c

220

for (reg = 0; reg < IDEDMA_NREGS; reg++) {

sys/dev/pci/svwsata.c

222

if (size > (IDEDMA_SCH_OFFSET - reg))

sys/dev/pci/svwsata.c

223

size = IDEDMA_SCH_OFFSET - reg;

sys/dev/pci/svwsata.c

226

(chan << 8) + SVWSATA_DMA + reg,

sys/dev/pci/svwsata.c

227

size, &pc->dma_iohs[reg]) != 0) {

sys/dev/pci/svwsata.c

231

(u_long) (chan << 8) + SVWSATA_DMA + reg,

sys/dev/pci/tdvfb.c

785

tdvfb_cvg_read(struct tdvfb_softc *sc, uint32_t reg)

sys/dev/pci/tdvfb.c

788

rv = bus_space_read_4(sc->sc_cvgt, sc->sc_cvgh, reg);

sys/dev/pci/tdvfb.c

790

aprint_normal("cvg_read val %x from reg %x\n", rv, reg);

sys/dev/pci/tdvfb.c

796

tdvfb_cvg_write(struct tdvfb_softc *sc, uint32_t reg, uint32_t val)

sys/dev/pci/tdvfb.c

799

aprint_normal("cvg_write val %x to reg %x\n", val, reg);

sys/dev/pci/tdvfb.c

80

static uint32_t tdvfb_cvg_read(struct tdvfb_softc *sc, uint32_t reg);

sys/dev/pci/tdvfb.c

801

bus_space_write_4(sc->sc_cvgt, sc->sc_cvgh, reg, val);

sys/dev/pci/tdvfb.c

805

tdvfb_cvg_set(struct tdvfb_softc *sc, uint32_t reg, uint32_t bits)

sys/dev/pci/tdvfb.c

808

v = tdvfb_cvg_read(sc, reg) | bits;

sys/dev/pci/tdvfb.c

809

tdvfb_cvg_write(sc, reg, v);

sys/dev/pci/tdvfb.c

81

static void tdvfb_cvg_write(struct tdvfb_softc *sc, uint32_t reg,

sys/dev/pci/tdvfb.c

813

tdvfb_cvg_unset(struct tdvfb_softc *sc, uint32_t reg, uint32_t bits)

sys/dev/pci/tdvfb.c

816

v = tdvfb_cvg_read(sc, reg) & ~bits;

sys/dev/pci/tdvfb.c

817

tdvfb_cvg_write(sc, reg, v);

sys/dev/pci/tdvfb.c

821

tdvfb_cvg_dac_read(struct tdvfb_softc *sc, uint32_t reg)

sys/dev/pci/tdvfb.c

825

tdvfb_cvg_dac_write(sc, reg, TDV_DAC_DATA_READ);

sys/dev/pci/tdvfb.c

829

aprint_normal("cvg_dac_read val %x from reg %x\n", rv, reg);

sys/dev/pci/tdvfb.c

83

static void tdvfb_cvg_set(struct tdvfb_softc *sc, uint32_t reg,

sys/dev/pci/tdvfb.c

835

tdvfb_cvg_dac_write(struct tdvfb_softc *sc, uint32_t reg, uint32_t val)

sys/dev/pci/tdvfb.c

839

wreg = ((reg & TDV_GENDAC_ADDRMASK) << 8) | val;

sys/dev/pci/tdvfb.c

842

aprint_normal("cvg_dac_write val %x to reg %x (%x)\n", val, reg,

sys/dev/pci/tdvfb.c

85

static void tdvfb_cvg_unset(struct tdvfb_softc *sc, uint32_t reg,

sys/dev/pci/tdvfb.c

87

static uint8_t tdvfb_cvg_dac_read(struct tdvfb_softc *sc, uint32_t reg);

sys/dev/pci/tdvfb.c

88

static void tdvfb_cvg_dac_write(struct tdvfb_softc *sc, uint32_t reg,

sys/dev/pci/tga.c

641

uint32_t reg;

sys/dev/pci/tga.c

643

reg = TGARREG(dc, TGA_REG_SISR);

sys/dev/pci/tga.c

644

if (( reg & 0x00010001) != 0x00010001) {

sys/dev/pci/tga.c

646

if ((reg & 0x1f) != 0) {

sys/dev/pci/tga.c

648

TGAWREG(dc, TGA_REG_SISR, (reg & 0x1f));

sys/dev/pci/tgavar.h

135

#define TGARREG(dc,reg) (bus_space_read_4((dc)->dc_memt, (dc)->dc_regs, \

sys/dev/pci/tgavar.h

136

(reg) << 2))

sys/dev/pci/tgavar.h

139

#define TGAWREG(dc,reg,val) bus_space_write_4((dc)->dc_memt, (dc)->dc_regs, \

sys/dev/pci/tgavar.h

140

(reg) << 2, (val))

sys/dev/pci/tgavar.h

143

#define TGAWALREG(dc,reg,alias,val) bus_space_write_4( \

sys/dev/pci/tgavar.h

145

((alias) * TGA_CREGS_ALIAS) + ((reg) << 2), \

sys/dev/pci/tgavar.h

149

#define TGAREGWB(dc,reg, nregs) bus_space_barrier( \

sys/dev/pci/tgavar.h

151

((reg) << 2), 4 * (nregs), BUS_SPACE_BARRIER_WRITE)

sys/dev/pci/tgavar.h

154

#define TGAREGRB(dc,reg, nregs) bus_space_barrier( \

sys/dev/pci/tgavar.h

156

((reg) << 2), 4 * (nregs), BUS_SPACE_BARRIER_READ)

sys/dev/pci/tgavar.h

159

#define TGAREGRWB(dc,reg, nregs) bus_space_barrier( \

sys/dev/pci/tgavar.h

161

((reg) << 2), 4 * (nregs), \

sys/dev/pci/ubsec.c

141

#define WRITE_REG(sc,reg,val) \

sys/dev/pci/ubsec.c

142

bus_space_write_4((sc)->sc_st, (sc)->sc_sh, reg, val)

sys/dev/pci/unichromeaccel.h

42

#define MMIO_OUT8(reg, val) \

sys/dev/pci/unichromeaccel.h

43

bus_space_write_1(sc->sc_memt, sc->sc_memh, reg, val)

sys/dev/pci/unichromeaccel.h

44

#define MMIO_OUT16(reg, val) \

sys/dev/pci/unichromeaccel.h

45

bus_space_write_2(sc->sc_memt, sc->sc_memh, reg, val)

sys/dev/pci/unichromeaccel.h

46

#define MMIO_OUT32(reg, val) \

sys/dev/pci/unichromeaccel.h

47

bus_space_write_4(sc->sc_memt, sc->sc_memh, reg, val)

sys/dev/pci/unichromeaccel.h

48

#define MMIO_IN8(reg) \

sys/dev/pci/unichromeaccel.h

49

bus_space_read_1(sc->sc_memt, sc->sc_memh, reg)

sys/dev/pci/unichromeaccel.h

50

#define MMIO_IN16(reg) \

sys/dev/pci/unichromeaccel.h

51

bus_space_read_2(sc->sc_memt, sc->sc_memh, reg)

sys/dev/pci/unichromeaccel.h

52

#define MMIO_IN32(reg) \

sys/dev/pci/unichromeaccel.h

53

bus_space_read_4(sc->sc_memt, sc->sc_memh, reg)

sys/dev/pci/unichromefb.c

1015

struct io_register *reg;

sys/dev/pci/unichromefb.c

1019

reg = NULL;

sys/dev/pci/unichromefb.c

1040

reg = display_fifo_depth_reg.iga1_fifo_depth_select_reg.reg;

sys/dev/pci/unichromefb.c

1041

uni_load_reg(sc, val, regnum, reg, VIASR);

sys/dev/pci/unichromefb.c

1046

reg = fifo_threshold_select_reg.iga1_fifo_threshold_select_reg.reg;

sys/dev/pci/unichromefb.c

1047

uni_load_reg(sc, val, regnum, reg, VIASR);

sys/dev/pci/unichromefb.c

1052

reg = fifo_high_threshold_select_reg.iga1_fifo_high_threshold_select_reg.reg;

sys/dev/pci/unichromefb.c

1053

uni_load_reg(sc, val, regnum, reg, VIASR);

sys/dev/pci/unichromefb.c

1058

reg = display_queue_expire_num_reg.iga1_display_queue_expire_num_reg.reg;

sys/dev/pci/unichromefb.c

1059

uni_load_reg(sc, val, regnum, reg, VIASR);

sys/dev/pci/unichromefb.c

810

struct io_register *reg;

sys/dev/pci/unichromefb.c

814

reg = NULL;

sys/dev/pci/unichromefb.c

826

reg = iga1_crtc_reg.hor_total.reg;

sys/dev/pci/unichromefb.c

832

reg = iga1_crtc_reg.hor_addr.reg;

sys/dev/pci/unichromefb.c

838

reg = iga1_crtc_reg.hor_blank_start.reg;

sys/dev/pci/unichromefb.c

845

reg = iga1_crtc_reg.hor_blank_end.reg;

sys/dev/pci/unichromefb.c

851

reg = iga1_crtc_reg.hor_sync_start.reg;

sys/dev/pci/unichromefb.c

858

reg = iga1_crtc_reg.hor_sync_end.reg;

sys/dev/pci/unichromefb.c

864

reg = iga1_crtc_reg.ver_total.reg;

sys/dev/pci/unichromefb.c

870

reg = iga1_crtc_reg.ver_addr.reg;

sys/dev/pci/unichromefb.c

876

reg = iga1_crtc_reg.ver_blank_start.reg;

sys/dev/pci/unichromefb.c

883

reg = iga1_crtc_reg.ver_blank_end.reg;

sys/dev/pci/unichromefb.c

889

reg = iga1_crtc_reg.ver_sync_start.reg;

sys/dev/pci/unichromefb.c

896

reg = iga1_crtc_reg.ver_sync_end.reg;

sys/dev/pci/unichromefb.c

911

uni_load_reg(sc, val, regnum, reg, VIACR);

sys/dev/pci/unichromefb.c

919

struct io_register *reg, int type)

sys/dev/pci/unichromefb.c

931

startidx = reg[i].start_bit;

sys/dev/pci/unichromefb.c

932

endidx = reg[i].end_bit;

sys/dev/pci/unichromefb.c

933

cridx = reg[i].io_addr;

sys/dev/pci/unichromefb.c

978

offset_reg.iga1_offset_reg.reg,

sys/dev/pci/unichromefb.c

999

fetch_count_reg.iga1_fetch_count_reg.reg,

sys/dev/pci/unichromehw.h

256

struct io_register reg[IGA1_HOR_TOTAL_REG_NUM];

sys/dev/pci/unichromehw.h

262

struct io_register reg[IGA1_HOR_ADDR_REG_NUM];

sys/dev/pci/unichromehw.h

268

struct io_register reg[IGA1_HOR_BLANK_START_REG_NUM];

sys/dev/pci/unichromehw.h

274

struct io_register reg[IGA1_HOR_BLANK_END_REG_NUM];

sys/dev/pci/unichromehw.h

280

struct io_register reg[IGA1_HOR_SYNC_START_REG_NUM];

sys/dev/pci/unichromehw.h

286

struct io_register reg[IGA1_HOR_SYNC_END_REG_NUM];

sys/dev/pci/unichromehw.h

292

struct io_register reg[IGA1_VER_TOTAL_REG_NUM];

sys/dev/pci/unichromehw.h

298

struct io_register reg[IGA1_VER_ADDR_REG_NUM];

sys/dev/pci/unichromehw.h

304

struct io_register reg[IGA1_VER_BLANK_START_REG_NUM];

sys/dev/pci/unichromehw.h

310

struct io_register reg[IGA1_VER_BLANK_END_REG_NUM];

sys/dev/pci/unichromehw.h

316

struct io_register reg[IGA1_VER_SYNC_START_REG_NUM];

sys/dev/pci/unichromehw.h

322

struct io_register reg[IGA1_VER_SYNC_END_REG_NUM];

sys/dev/pci/unichromehw.h

333

struct io_register reg[IGA2_SHADOW_HOR_TOTAL_REG_NUM];

sys/dev/pci/unichromehw.h

339

struct io_register reg[IGA2_SHADOW_HOR_BLANK_END_REG_NUM];

sys/dev/pci/unichromehw.h

346

struct io_register reg[IGA2_SHADOW_VER_TOTAL_REG_NUM];

sys/dev/pci/unichromehw.h

352

struct io_register reg[IGA2_SHADOW_VER_ADDR_REG_NUM];

sys/dev/pci/unichromehw.h

358

struct io_register reg[IGA2_SHADOW_VER_BLANK_START_REG_NUM];

sys/dev/pci/unichromehw.h

364

struct io_register reg[IGA2_SHADOW_VER_BLANK_END_REG_NUM];

sys/dev/pci/unichromehw.h

370

struct io_register reg[IGA2_SHADOW_VER_SYNC_START_REG_NUM];

sys/dev/pci/unichromehw.h

376

struct io_register reg[IGA2_SHADOW_VER_SYNC_END_REG_NUM];

sys/dev/pci/unichromehw.h

386

struct io_register reg[IGA2_HOR_TOTAL_REG_NUM];

sys/dev/pci/unichromehw.h

392

struct io_register reg[IGA2_HOR_ADDR_REG_NUM];

sys/dev/pci/unichromehw.h

398

struct io_register reg[IGA2_HOR_BLANK_START_REG_NUM];

sys/dev/pci/unichromehw.h

404

struct io_register reg[IGA2_HOR_BLANK_END_REG_NUM];

sys/dev/pci/unichromehw.h

410

struct io_register reg[IGA2_HOR_SYNC_START_REG_NUM];

sys/dev/pci/unichromehw.h

416

struct io_register reg[IGA2_HOR_SYNC_END_REG_NUM];

sys/dev/pci/unichromehw.h

422

struct io_register reg[IGA2_VER_TOTAL_REG_NUM];

sys/dev/pci/unichromehw.h

428

struct io_register reg[IGA2_VER_ADDR_REG_NUM];

sys/dev/pci/unichromehw.h

434

struct io_register reg[IGA2_VER_BLANK_START_REG_NUM];

sys/dev/pci/unichromehw.h

440

struct io_register reg[IGA2_VER_BLANK_END_REG_NUM];

sys/dev/pci/unichromehw.h

446

struct io_register reg[IGA2_VER_SYNC_START_REG_NUM];

sys/dev/pci/unichromehw.h

452

struct io_register reg[IGA2_VER_SYNC_END_REG_NUM];

sys/dev/pci/unichromehw.h

458

struct io_register reg[IGA1_OFFSET_REG_NUM];

sys/dev/pci/unichromehw.h

464

struct io_register reg[IGA2_OFFSET_REG_NUM];

sys/dev/pci/unichromehw.h

475

struct io_register reg[IGA1_FETCH_COUNT_REG_NUM];

sys/dev/pci/unichromehw.h

481

struct io_register reg[IGA2_FETCH_COUNT_REG_NUM];

sys/dev/pci/unichromehw.h

492

struct io_register reg[IGA1_STARTING_ADDR_REG_NUM];

sys/dev/pci/unichromehw.h

497

struct io_register reg[IGA2_STARTING_ADDR_REG_NUM];

sys/dev/pci/unichromehw.h

508

struct io_register reg[LCD_POWER_SEQ_TD0_REG_NUM];

sys/dev/pci/unichromehw.h

513

struct io_register reg[LCD_POWER_SEQ_TD1_REG_NUM];

sys/dev/pci/unichromehw.h

518

struct io_register reg[LCD_POWER_SEQ_TD2_REG_NUM];

sys/dev/pci/unichromehw.h

523

struct io_register reg[LCD_POWER_SEQ_TD3_REG_NUM];

sys/dev/pci/unichromehw.h

536

struct io_register reg[LCD_HOR_SCALING_FACTOR_REG_NUM];

sys/dev/pci/unichromehw.h

541

struct io_register reg[LCD_VER_SCALING_FACTOR_REG_NUM];

sys/dev/pci/unichromehw.h

574

struct io_register reg[IGA1_FIFO_DEPTH_SELECT_REG_NUM];

sys/dev/pci/unichromehw.h

579

struct io_register reg[IGA1_FIFO_THRESHOLD_REG_NUM];

sys/dev/pci/unichromehw.h

584

struct io_register reg[IGA1_FIFO_HIGH_THRESHOLD_REG_NUM];

sys/dev/pci/unichromehw.h

589

struct io_register reg[IGA1_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM];

sys/dev/pci/unichromehw.h

594

struct io_register reg[IGA2_FIFO_DEPTH_SELECT_REG_NUM];

sys/dev/pci/unichromehw.h

599

struct io_register reg[IGA2_FIFO_THRESHOLD_REG_NUM];

sys/dev/pci/unichromehw.h

604

struct io_register reg[IGA2_FIFO_HIGH_THRESHOLD_REG_NUM];

sys/dev/pci/unichromehw.h

609

struct io_register reg[IGA2_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM];

sys/dev/pci/universe_pci.c

132

reg = read_csr_4(d, misc_ctl);

sys/dev/pci/universe_pci.c

134

if (reg & 0x00020000) /* SYSCON */

sys/dev/pci/universe_pci.c

136

reg = read_csr_4(d, mast_ctl);

sys/dev/pci/universe_pci.c

137

aprint_normal("requesting at VME bus level %d\n", (reg >> 22) & 3);

sys/dev/pci/universe_pci.c

55

#define read_csr_4(d, reg) \

sys/dev/pci/universe_pci.c

56

bus_space_read_4(d->csrt, d->csrh, offsetof(struct universereg, reg))

sys/dev/pci/universe_pci.c

57

#define write_csr_4(d, reg, val) \

sys/dev/pci/universe_pci.c

58

bus_space_write_4(d->csrt, d->csrh, offsetof(struct universereg, reg), val)

sys/dev/pci/universe_pci.c

67

#define read_pcislv(d, idx, reg) \

sys/dev/pci/universe_pci.c

69

pcislvoffsets[idx] + offsetof(struct universe_pcislvimg, reg))

sys/dev/pci/universe_pci.c

70

#define write_pcislv(d, idx, reg, val) \

sys/dev/pci/universe_pci.c

72

pcislvoffsets[idx] + offsetof(struct universe_pcislvimg, reg), val)

sys/dev/pci/universe_pci.c

82

#define read_vmeslv(d, idx, reg) \

sys/dev/pci/universe_pci.c

84

vmeslvoffsets[idx] + offsetof(struct universe_vmeslvimg, reg))

sys/dev/pci/universe_pci.c

85

#define write_vmeslv(d, idx, reg, val) \

sys/dev/pci/universe_pci.c

87

vmeslvoffsets[idx] + offsetof(struct universe_vmeslvimg, reg), val)

sys/dev/pci/universe_pci.c

95

u_int32_t reg;

sys/dev/pci/veritefb.c

395

vfb_read1(struct veritefb_softc *sc, bus_size_t reg)

sys/dev/pci/veritefb.c

397

if (reg >= VFB_IOONLY_BASE)

sys/dev/pci/veritefb.c

398

return bus_space_read_1(sc->sc_iot, sc->sc_ioh, reg);

sys/dev/pci/veritefb.c

400

sc->sc_regoff + reg);

sys/dev/pci/veritefb.c

404

vfb_write1(struct veritefb_softc *sc, bus_size_t reg, uint8_t val)

sys/dev/pci/veritefb.c

406

if (reg >= VFB_IOONLY_BASE) {

sys/dev/pci/veritefb.c

407

bus_space_write_1(sc->sc_iot, sc->sc_ioh, reg, val);

sys/dev/pci/veritefb.c

410

bus_space_write_1(sc->sc_regt, sc->sc_regh, sc->sc_regoff + reg,

sys/dev/pci/veritefb.c

415

vfb_read4(struct veritefb_softc *sc, bus_size_t reg)

sys/dev/pci/veritefb.c

417

if (reg >= VFB_IOONLY_BASE)

sys/dev/pci/veritefb.c

418

return bus_space_read_4(sc->sc_iot, sc->sc_ioh, reg);

sys/dev/pci/veritefb.c

420

sc->sc_regoff + reg);

sys/dev/pci/veritefb.c

424

vfb_write4(struct veritefb_softc *sc, bus_size_t reg, uint32_t val)

sys/dev/pci/veritefb.c

426

if (reg >= VFB_IOONLY_BASE) {

sys/dev/pci/veritefb.c

427

bus_space_write_4(sc->sc_iot, sc->sc_ioh, reg, val);

sys/dev/pci/veritefb.c

430

bus_space_write_4(sc->sc_regt, sc->sc_regh, sc->sc_regoff + reg,

sys/dev/pci/veritefb.c

465

vfb_pacepoll4(struct veritefb_softc *sc, bus_size_t reg, uint32_t data,

sys/dev/pci/veritefb.c

471

if ((vfb_read4(sc, reg) & mask) == (data & mask))

sys/dev/pci/veritefb.c

476

vfb_pacepoll1(struct veritefb_softc *sc, bus_size_t reg, uint8_t data,

sys/dev/pci/veritefb.c

482

if ((vfb_read1(sc, reg) & mask) == (data & mask))

sys/dev/pci/vga_pci.c

188

int bar, reg;

sys/dev/pci/vga_pci.c

202

reg = PCI_MAPREG_START + (bar * 4);

sys/dev/pci/vga_pci.c

203

if (!pci_mapreg_probe(psc->sc_pc, psc->sc_pcitag, reg,

sys/dev/pci/vga_pci.c

218

"WARNING: ignoring 64-bit BAR @ 0x%02x\n", reg);

sys/dev/pci/vga_pci.c

223

if (pci_mapreg_info(psc->sc_pc, psc->sc_pcitag, reg,

sys/dev/pci/vga_pci.c

229

"WARNING: strange BAR @ 0x%02x\n", reg);

sys/dev/pci/viaide.c

1137

int chan, reg;

sys/dev/pci/viaide.c

1165

for (reg = 0; reg < IDEDMA_NREGS; reg++) {

sys/dev/pci/viaide.c

1167

if (size > (IDEDMA_SCH_OFFSET - reg))

sys/dev/pci/viaide.c

1168

size = IDEDMA_SCH_OFFSET - reg;

sys/dev/pci/viaide.c

1170

IDEDMA_SCH_OFFSET * chan + reg, size,

sys/dev/pci/viaide.c

1171

&pc->dma_iohs[reg]) != 0) {

sys/dev/pci/viaide.c

1175

reg, (u_long)size);

sys/dev/pci/vio9p.c

595

uint8_t reg;

sys/dev/pci/vio9p.c

609

reg = virtio_read_device_config_1(sc->sc_virtio,

sys/dev/pci/vio9p.c

611

sc->sc_tag[i] = reg;

sys/dev/pci/virtio_pci.c

479

int reg;

sys/dev/pci/virtio_pci.c

484

reg = PCI_BAR(i);

sys/dev/pci/virtio_pci.c

485

type = pci_mapreg_type(pc, tag, reg);

sys/dev/pci/virtio_pci.c

486

if (pci_mapreg_map(pa, reg, type, 0,

sys/dev/pci/virtio_pci.c

577

pcireg_t reg[8];

sys/dev/pci/virtio_pci.c

585

&v->reg[0]))

sys/dev/pci/virtio_pci.c

590

v->reg[i] =

sys/dev/pci/virtio_pci.c

607

v->reg[i] =

sys/dev/pci/voodoofb.c

257

voodoo3_write32(struct voodoofb_softc *sc, uint32_t reg, uint32_t val)

sys/dev/pci/voodoofb.c

259

bus_space_write_4(sc->sc_regt, sc->sc_regh, reg, val);

sys/dev/pci/voodoofb.c

263

voodoo3_write32s(struct voodoofb_softc *sc, uint32_t reg, uint32_t val)

sys/dev/pci/voodoofb.c

265

bus_space_write_stream_4(sc->sc_regt, sc->sc_regh, reg, val);

sys/dev/pci/voodoofb.c

268

voodoo3_read32(struct voodoofb_softc *sc, uint32_t reg)

sys/dev/pci/voodoofb.c

270

return bus_space_read_4(sc->sc_regt, sc->sc_regh, reg);

sys/dev/pci/voodoofb.c

274

voodoo3_write_crtc(struct voodoofb_softc *sc, uint8_t reg, uint8_t val)

sys/dev/pci/voodoofb.c

276

bus_space_write_1(sc->sc_ioregt, sc->sc_ioregh, CRTC_INDEX - 0x300, reg);

sys/dev/pci/voodoofb.c

281

voodoo3_write_seq(struct voodoofb_softc *sc, uint8_t reg, uint8_t val)

sys/dev/pci/voodoofb.c

283

bus_space_write_1(sc->sc_ioregt, sc->sc_ioregh, SEQ_INDEX - 0x300, reg);

sys/dev/pci/voodoofb.c

288

voodoo3_write_gra(struct voodoofb_softc *sc, uint8_t reg, uint8_t val)

sys/dev/pci/voodoofb.c

290

bus_space_write_1(sc->sc_ioregt, sc->sc_ioregh, GRA_INDEX - 0x300, reg);

sys/dev/pci/voodoofb.c

295

voodoo3_write_attr(struct voodoofb_softc *sc, uint8_t reg, uint8_t val)

sys/dev/pci/voodoofb.c

301

bus_space_write_1(sc->sc_ioregt, sc->sc_ioregh, ATT_IW - 0x300, reg);

sys/dev/pci/voodoofb.c

307

vga_outb(struct voodoofb_softc *sc, uint32_t reg, uint8_t val)

sys/dev/pci/voodoofb.c

309

bus_space_write_1(sc->sc_ioregt, sc->sc_ioregh, reg - 0x300, val);

sys/dev/pci/voyager.c

152

uint32_t reg;

sys/dev/pci/voyager.c

250

reg = bus_space_read_4(sc->sc_memt, sc->sc_regh, SM502_GPIO0_CONTROL);

sys/dev/pci/voyager.c

251

if ((reg & GPIO_I2C_BITS) == 0) {

sys/dev/pci/voyager.c

287

uint32_t reg;

sys/dev/pci/voyager.c

289

reg = bus_space_read_4(sc->sc_memt, sc->sc_regh, SM502_GPIO_DATA0);

sys/dev/pci/voyager.c

290

reg &= ~GPIO_I2C_BITS;

sys/dev/pci/voyager.c

291

reg |= bits;

sys/dev/pci/voyager.c

292

bus_space_write_4(sc->sc_memt, sc->sc_regh, SM502_GPIO_DATA0, reg);

sys/dev/pci/voyager.c

299

uint32_t reg;

sys/dev/pci/voyager.c

301

reg = bus_space_read_4(sc->sc_memt, sc->sc_regh, SM502_GPIO_DIR0);

sys/dev/pci/voyager.c

302

reg &= ~(1 << 13);

sys/dev/pci/voyager.c

303

reg |= bits;

sys/dev/pci/voyager.c

304

bus_space_write_4(sc->sc_memt, sc->sc_regh, SM502_GPIO_DIR0, reg);

sys/dev/pci/voyager.c

311

uint32_t reg;

sys/dev/pci/voyager.c

313

reg = bus_space_read_4(sc->sc_memt, sc->sc_regh, SM502_GPIO_DATA0);

sys/dev/pci/voyager.c

314

return reg;

sys/dev/pci/voyager.c

364

uint32_t reg;

sys/dev/pci/voyager.c

368

reg = bus_space_read_4(sc->sc_memt, sc->sc_regh, regnum);

sys/dev/pci/voyager.c

369

reg &= mask;

sys/dev/pci/voyager.c

370

reg |= bits;

sys/dev/pci/voyager.c

371

bus_space_write_4(sc->sc_memt, sc->sc_regh, regnum, reg);

sys/dev/pci/voyager.c

410

uint32_t reg;

sys/dev/pci/voyager.c

424

reg = bus_space_read_4(sc->sc_memt, sc->sc_regh, SM502_INTR_MASK);

sys/dev/pci/voyager.c

425

reg |= 1 << bit;

sys/dev/pci/voyager.c

426

bus_space_write_4(sc->sc_memt, sc->sc_regh, SM502_INTR_MASK, reg);

sys/dev/pci/voyager.c

441

uint32_t reg;

sys/dev/pci/voyager.c

443

reg = bus_space_read_4(sc->sc_memt, sc->sc_regh, pwmreg);

sys/dev/pci/voyager.c

445

pwmreg, reg,

sys/dev/pci/voyager.c

446

96000000 / (1 << ((reg & SM502_PWM_CLOCK_DIV_MASK) >> SM502_PWM_CLOCK_DIV_SHIFT)),

sys/dev/pci/voyager.c

447

(reg & SM502_PWM_CLOCK_HIGH_MASK) >> SM502_PWM_CLOCK_HIGH_SHIFT,

sys/dev/pci/voyager.c

448

(reg & SM502_PWM_CLOCK_LOW_MASK) >> SM502_PWM_CLOCK_LOW_SHIFT);

sys/dev/pci/voyager.c

456

uint32_t reg = 0, hi, lo;

sys/dev/pci/voyager.c

482

reg = ((hi - 1) & 0xfff) << SM502_PWM_CLOCK_HIGH_SHIFT;

sys/dev/pci/voyager.c

483

reg |= ((lo - 1) & 0xfff) << SM502_PWM_CLOCK_LOW_SHIFT;

sys/dev/pci/voyager.c

484

reg |= (bit & 0xf) << SM502_PWM_CLOCK_DIV_SHIFT;

sys/dev/pci/voyager.c

485

DPRINTF("reg: %08x\n", reg);

sys/dev/pci/voyager.c

486

return reg;

sys/dev/pci/voyager/pwmclock.c

126

uint32_t reg, last, curr, diff, acc;

sys/dev/pci/voyager/pwmclock.c

137

reg = voyager_set_pwm(100, 100); /* 100Hz, 10% duty cycle */

sys/dev/pci/voyager/pwmclock.c

138

reg |= SM502_PWM_ENABLE | SM502_PWM_ENABLE_INTR |

sys/dev/pci/voyager/pwmclock.c

140

sc->sc_reg = reg;

sys/dev/pci/voyager/pwmclock.c

274

uint32_t reg, now, diff;

sys/dev/pci/voyager/pwmclock.c

277

reg = bus_space_read_4(sc->sc_memt, sc->sc_regh, SM502_PWM1);

sys/dev/pci/voyager/pwmclock.c

278

if ((reg & SM502_PWM_INTR_PENDING) == 0)

sys/dev/pci/voyager/vac.c

115

#define VAC_READ(sc, reg) \

sys/dev/pci/voyager/vac.c

116

bus_space_read_4((sc)->sc_memt, (sc)->sc_regh, (reg))

sys/dev/pci/voyager/vac.c

117

#define VAC_WRITE(sc, reg, val) \

sys/dev/pci/voyager/vac.c

118

bus_space_write_4((sc)->sc_memt, (sc)->sc_regh, (reg), (val))

sys/dev/pci/voyager/vac.c

170

vac_ac97_read(void *priv, uint8_t reg, uint16_t *val)

sys/dev/pci/voyager/vac.c

176

addr = ((uint32_t)reg << SM502_AC97_ADDR_SHIFT) & SM502_AC97_ADDR_MASK;

sys/dev/pci/voyager/vac.c

198

vac_ac97_write(void *priv, uint8_t reg, uint16_t val)

sys/dev/pci/voyager/vac.c

203

addr = ((uint32_t)reg << SM502_AC97_ADDR_SHIFT) & SM502_AC97_ADDR_MASK;

sys/dev/pci/voyager/vac.c

220

uint32_t reg;

sys/dev/pci/voyager/vac.c

240

reg = VAC_READ(sc, SM502_AC97_CONTROL);

sys/dev/pci/voyager/vac.c

241

if ((reg & SM502_AC97_BCLK_RUNNING) != 0 &&

sys/dev/pci/voyager/vac.c

242

(reg & SM502_AC97_STATUS_MASK) == SM502_AC97_STATUS_ON) {

sys/dev/pci/voyager/vac.c

244

"AC-link up (control 0x%08x)\n", reg);

sys/dev/pci/voyager/vac.c

251

"AC-link did not come ready (control 0x%08x)\n", reg);

sys/dev/pci/voyager/voyagerfb.c

1150

uint32_t reg;

sys/dev/pci/voyager/voyagerfb.c

1152

reg = (r << 16) | (g << 8) | b;

sys/dev/pci/voyager/voyagerfb.c

1155

SM502_PALETTE_PANEL + (idx << 2), reg);

sys/dev/pci/voyager/voyagerfb.c

1162

int reg;

sys/dev/pci/voyager/voyagerfb.c

1181

reg = bus_space_read_4(sc->sc_memt, sc->sc_regh, SM502_PANEL_DISP_CTRL);

sys/dev/pci/voyager/voyagerfb.c

1182

reg &= ~SM502_PDC_DEPTH_MASK;

sys/dev/pci/voyager/voyagerfb.c

1189

reg |= SM502_PDC_8BIT;

sys/dev/pci/voyager/voyagerfb.c

1195

reg |= SM502_PDC_16BIT;

sys/dev/pci/voyager/voyagerfb.c

1202

reg |= SM502_PDC_32BIT;

sys/dev/pci/voyager/voyagerfb.c

1213

reg);

sys/dev/pci/voyager/voyagerfb.c

235

uint32_t reg;

sys/dev/pci/voyager/voyagerfb.c

238

reg = bus_space_read_4(sc->sc_memt, sc->sc_regh, SM502_CURRENT_GATE);

sys/dev/pci/voyager/voyagerfb.c

239

if ((reg & SM502_GATE_GPIO_ENABLE) == 0) {

sys/dev/pci/voyager/voyagerfb.c

240

reg |= SM502_GATE_GPIO_ENABLE;

sys/dev/pci/voyager/voyagerfb.c

242

reg);

sys/dev/pci/voyager/voyagerfb.c

246

reg = bus_space_read_4(sc->sc_memt, sc->sc_regh, SM502_GPIO1_CONTROL);

sys/dev/pci/voyager/voyagerfb.c

247

reg |= SM502_GPIO1_I2C_BITS;

sys/dev/pci/voyager/voyagerfb.c

248

bus_space_write_4(sc->sc_memt, sc->sc_regh, SM502_GPIO1_CONTROL, reg);

sys/dev/pci/voyager/voyagerfb.c

479

uint32_t m, n, k, pll, reg;

sys/dev/pci/voyager/voyagerfb.c

492

reg = bus_space_read_4(sc->sc_memt, sc->sc_regh, clk);

sys/dev/pci/voyager/voyagerfb.c

493

reg = (reg & ~SM502_PMC_P2_SRC_MASK) |

sys/dev/pci/voyager/voyagerfb.c

495

bus_space_write_4(sc->sc_memt, sc->sc_regh, clk, reg);

sys/dev/pci/voyager/voyagerfb.c

499

reg = bus_space_read_4(sc->sc_memt, sc->sc_regh, clk);

sys/dev/pci/voyager/voyagerfb.c

500

reg &= ~(SM502_PMC_P2_DIV_MASK | SM502_PMC_P2_DIS2X);

sys/dev/pci/voyager/voyagerfb.c

501

bus_space_write_4(sc->sc_memt, sc->sc_regh, clk, reg);

sys/dev/pci/voyager/voyagerfb.c

607

uint32_t reg;

sys/dev/pci/voyager/voyagerfb.c

638

reg = bus_space_read_4(sc->sc_memt, sc->sc_regh, SM502_DRAM_CONTROL);

sys/dev/pci/voyager/voyagerfb.c

639

switch(reg & 0x0000e000) {

sys/dev/pci/voyager/voyagerfb.c

668

reg = bus_space_read_4(sc->sc_memt, sc->sc_regh,

sys/dev/pci/voyager/voyagerfb.c

671

(reg & SM502_PDC_PANEL_ENABLE) == 0 ||

sys/dev/pci/wcfb.c

164

uint32_t reg;

sys/dev/pci/wcfb.c

220

reg = bus_space_read_4(sc->sc_regt, sc->sc_regh, WC_RESOLUTION);

sys/dev/pci/wcfb.c

221

sc->sc_height = (reg >> 16) + 1;

sys/dev/pci/wcfb.c

225

sc->sc_width = (reg & 0xffff) + 1;

sys/dev/pci/wcfb.c

746

wcfb_rop_common(struct wcfb_softc *sc, bus_addr_t reg, int sx, int sy,

sys/dev/pci/wcfb.c

767

bus_space_write_4(sc->sc_regt, sc->sc_regh, reg, 0x61000001);

sys/dev/pci/wcfb.c

768

bus_space_write_4(sc->sc_regt, sc->sc_regh, reg, 0);

sys/dev/pci/wcfb.c

769

bus_space_write_4(sc->sc_regt, sc->sc_regh, reg, 0x6301c080);

sys/dev/pci/wcfb.c

770

bus_space_write_4(sc->sc_regt, sc->sc_regh, reg, 0x80000000);

sys/dev/pci/wcfb.c

771

bus_space_write_4(sc->sc_regt, sc->sc_regh, reg, rop);

sys/dev/pci/wcfb.c

772

bus_space_write_4(sc->sc_regt, sc->sc_regh, reg, planemask);

sys/dev/pci/wcfb.c

773

bus_space_write_4(sc->sc_regt, sc->sc_regh, reg, 0);

sys/dev/pci/wcfb.c

774

bus_space_write_4(sc->sc_regt, sc->sc_regh, reg, 0x64000303);

sys/dev/pci/wcfb.c

780

bus_space_write_4(sc->sc_regt, sc->sc_regh, reg, WCFB_COORDS(0, 0));

sys/dev/pci/wcfb.c

781

bus_space_write_4(sc->sc_regt, sc->sc_regh, reg, 0);

sys/dev/pci/wcfb.c

782

bus_space_write_4(sc->sc_regt, sc->sc_regh, reg, 0x00030000);

sys/dev/pci/wcfb.c

783

bus_space_write_4(sc->sc_regt, sc->sc_regh, reg, 0x2200010d);

sys/dev/pci/wcfb.c

785

bus_space_write_4(sc->sc_regt, sc->sc_regh, reg, 0x33f01000 | dir);

sys/dev/pci/wcfb.c

786

bus_space_write_4(sc->sc_regt, sc->sc_regh, reg, WCFB_COORDS(dx, dy));

sys/dev/pci/wcfb.c

787

bus_space_write_4(sc->sc_regt, sc->sc_regh, reg, WCFB_COORDS(w, h));

sys/dev/pci/wcfb.c

788

bus_space_write_4(sc->sc_regt, sc->sc_regh, reg, WCFB_COORDS(sx, sy));

sys/dev/pci/wcfb.c

796

bus_addr_t reg = WC_JFB_ENGINE;

sys/dev/pci/wcfb.c

815

bus_space_write_4(sc->sc_regt, sc->sc_regh, reg, 0x00400016);

sys/dev/pci/wcfb.c

816

bus_space_write_4(sc->sc_regt, sc->sc_regh, reg, 0x5b000002);

sys/dev/pci/wcfb.c

817

bus_space_write_4(sc->sc_regt, sc->sc_regh, reg, 0x5a000000);

sys/dev/pci/wcfb.c

818

bus_space_write_4(sc->sc_regt, sc->sc_regh, reg, spr);

sys/dev/pci/wcfb.c

819

bus_space_write_4(sc->sc_regt, sc->sc_regh, reg, splr);

sys/dev/pci/wcfb.c

821

wcfb_rop_common(sc, reg, sx, sy, dx, dy, w, h, rop, planemask);

sys/dev/pci/wcfb.c

823

bus_space_write_4(sc->sc_regt, sc->sc_regh, reg, 0x5a000001);

sys/dev/pci/wcfb.c

824

bus_space_write_4(sc->sc_regt, sc->sc_regh, reg, 0x5b000001);

sys/dev/pci/weasel_pci.c

320

u_int8_t reg;

sys/dev/pci/weasel_pci.c

329

reg = bus_space_read_1(sc->sc_st, sc->sc_sh, WEASEL_CHALLENGE);

sys/dev/pci/weasel_pci.c

330

bus_space_write_1(sc->sc_st, sc->sc_sh, WEASEL_RESPONSE, ~reg);

sys/dev/pci/xmm7360.c

237

#define pci_mapreg_map(pa, reg, type, busfl, tp, hp, bp, szp, maxsize) \

sys/dev/pci/xmm7360.c

238

pci_mapreg_map(pa, reg, type, busfl, tp, hp, bp, szp)

sys/dev/pci/yds.c

1018

pcireg_t reg;

sys/dev/pci/yds.c

1023

reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, YDS_PCI_DSCTRL);

sys/dev/pci/yds.c

1024

if (reg & 0x03) {

sys/dev/pci/yds.c

1026

YDS_PCI_DSCTRL, reg & ~0x03);

sys/dev/pci/yds.c

1028

YDS_PCI_DSCTRL, reg | 0x03);

sys/dev/pci/yds.c

1030

YDS_PCI_DSCTRL, reg & ~0x03);

sys/dev/pci/yds.c

560

pcireg_t reg;

sys/dev/pci/yds.c

568

reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, YDS_PCI_LEGACY);

sys/dev/pci/yds.c

569

reg &= ~0x8133c03f; /* these bits are out of interest */

sys/dev/pci/yds.c

570

reg |= ((YDS_PCI_EX_LEGACY_IMOD) |

sys/dev/pci/yds.c

573

reg |= YDS_PCI_EX_LEGACY_SMOD_DISABLE;

sys/dev/pci/yds.c

575

pci_conf_write(sc->sc_pc, sc->sc_pcitag, YDS_PCI_LEGACY, reg);

sys/dev/pci/yds.c

584

YDS_PCI_LEGACY, reg | (i << (0+16)));

sys/dev/pci/yds.c

602

reg |= (i << (0+16));

sys/dev/pci/yds.c

608

reg &= ~YDS_PCI_LEGACY_FMEN;

sys/dev/pci/yds.c

610

YDS_PCI_LEGACY, reg);

sys/dev/pci/yds.c

622

YDS_PCI_LEGACY, reg | (i << (4+16)));

sys/dev/pci/yds.c

639

reg |= (i << (4+16));

sys/dev/pci/yds.c

645

reg &= ~(YDS_PCI_LEGACY_MEN | YDS_PCI_LEGACY_MIEN);

sys/dev/pci/yds.c

646

pci_conf_write(sc->sc_pc, sc->sc_pcitag, YDS_PCI_LEGACY, reg);

sys/dev/pci/yds.c

656

uint32_t reg;

sys/dev/pci/yds.c

673

reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, YDS_PCI_DSCTRL);

sys/dev/pci/yds.c

675

reg | YDS_DSCTRL_WRST);

sys/dev/pci/yds.c

707

pcireg_t reg;

sys/dev/pci/yds.c

712

reg = pci_conf_read(pc, tag, YDS_PCI_LEGACY);

sys/dev/pci/yds.c

713

pci_conf_write(pc, tag, YDS_PCI_LEGACY, reg & YDS_PCI_LEGACY_LAD);

sys/dev/pci/yds.c

716

reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);

sys/dev/pci/yds.c

717

reg |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE |

sys/dev/pci/yds.c

719

pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg);

sys/dev/pci/yds.c

720

reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);

sys/dev/pci/yds.c

744

pcireg_t reg;

sys/dev/pci/yds.c

806

reg = pci_conf_read(pc, pa->pa_tag, YDS_PCI_LEGACY);

sys/dev/pci/yds.c

808

reg & YDS_PCI_LEGACY_LAD);

sys/dev/pci/yds.c

811

reg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);

sys/dev/pci/yds.c

812

reg |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE |

sys/dev/pci/yds.c

814

pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, reg);

sys/dev/pci/yds.c

815

reg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);

sys/dev/pci/yds.c

833

reg = pci_conf_read(pc, pa->pa_tag, YDS_PCI_DSCTRL);

sys/dev/pci/yds.c

834

pci_conf_write(pc, pa->pa_tag, YDS_PCI_DSCTRL, reg & ~YDS_DSCTRL_CRST);

sys/dev/pci/yds.c

885

pci_conf_write(pc, pa->pa_tag, YDS_PCI_DSCTRL, reg | YDS_DSCTRL_CRST);

sys/dev/pci/yds.c

887

pci_conf_write(pc, pa->pa_tag, YDS_PCI_DSCTRL, reg & ~YDS_DSCTRL_CRST);

sys/dev/pci/yds.c

969

yds_read_codec(void *sc_, uint8_t reg, uint16_t *data)

sys/dev/pci/yds.c

974

YWRITE2(sc->sc, AC97_CMD_ADDR, AC97_CMD_READ | AC97_ID(sc->id) | reg);

sys/dev/pci/yds.c

994

yds_write_codec(void *sc_, uint8_t reg, uint16_t data)

sys/dev/pci/yds.c

999

YWRITE2(sc->sc, AC97_CMD_ADDR, AC97_CMD_WRITE | AC97_ID(sc->id) | reg);

sys/dev/pckbport/alps.c

387

pms_alps_set_address(pckbport_tag_t tag, pckbport_slot_t slot, uint16_t reg)

sys/dev/pckbport/alps.c

398

nibble = (reg >> 12) & __BITS(3, 0);

sys/dev/pckbport/alps.c

402

nibble = (reg >> 8) & __BITS(3, 0);

sys/dev/pckbport/alps.c

406

nibble = (reg >> 4) & __BITS(3, 0);

sys/dev/pckbport/alps.c

410

nibble = (reg >> 0) & __BITS(3, 0);

sys/dev/pckbport/alps.c

425

pms_alps_cm_read_1(pckbport_tag_t tag, pckbport_slot_t slot, uint16_t reg,

sys/dev/pckbport/alps.c

432

if ((res = pms_alps_set_address(tag, slot, reg)) != 0)

sys/dev/pckbport/alps.c

441

if (reg != ((resp[0] << 8) | resp[1])) {

sys/dev/pckbport/alps.c

458

pms_alps_cm_write_1(pckbport_tag_t tag, pckbport_slot_t slot, uint16_t reg,

sys/dev/pckbport/alps.c

464

if ((res = pms_alps_set_address(tag, slot, reg)) != 0)

sys/dev/pckbport/elantech.c

133

pms_elantech_read_1(pckbport_tag_t tag, pckbport_slot_t slot, uint8_t reg,

sys/dev/pckbport/elantech.c

146

cmd = reg;

sys/dev/pckbport/elantech.c

158

pms_elantech_write_1(pckbport_tag_t tag, pckbport_slot_t slot, uint8_t reg,

sys/dev/pckbport/elantech.c

170

cmd = reg;

sys/dev/pcmcia/com_pcmcia.c

264

int reg;

sys/dev/pcmcia/com_pcmcia.c

267

reg = pcmcia_ccr_read(pf, PCMCIA_CCR_OPTION);

sys/dev/pcmcia/com_pcmcia.c

268

if (reg & 0x08) {

sys/dev/pcmcia/com_pcmcia.c

269

reg &= ~0x08;

sys/dev/pcmcia/com_pcmcia.c

270

pcmcia_ccr_write(pf, PCMCIA_CCR_OPTION, reg);

sys/dev/pcmcia/esp_pcmcia.c

286

esp_pcmcia_read_reg(struct ncr53c9x_softc *sc, int reg)

sys/dev/pcmcia/esp_pcmcia.c

290

return bus_space_read_1(esc->sc_iot, esc->sc_ioh, reg);

sys/dev/pcmcia/esp_pcmcia.c

294

esp_pcmcia_write_reg(struct ncr53c9x_softc *sc, int reg, uint8_t val)

sys/dev/pcmcia/esp_pcmcia.c

299

if (reg == NCR_CMD && v == (NCRCMD_TRANS|NCRCMD_DMA))

sys/dev/pcmcia/esp_pcmcia.c

301

bus_space_write_1(esc->sc_iot, esc->sc_ioh, reg, v);

sys/dev/pcmcia/if_ep_pcmcia.c

188

int reg;

sys/dev/pcmcia/if_ep_pcmcia.c

192

reg = pcmcia_ccr_read(pf, PCMCIA_CCR_OPTION);

sys/dev/pcmcia/if_ep_pcmcia.c

193

if (reg & 0x08) {

sys/dev/pcmcia/if_ep_pcmcia.c

194

reg &= ~0x08;

sys/dev/pcmcia/if_ep_pcmcia.c

195

pcmcia_ccr_write(pf, PCMCIA_CCR_OPTION, reg);

sys/dev/pcmcia/if_malo_pcmciavar.h

21

#define MALO_READ_1(sc, reg) \

sys/dev/pcmcia/if_malo_pcmciavar.h

22

bus_space_read_1((sc)->sc_iot, (sc)->sc_ioh, (reg))

sys/dev/pcmcia/if_malo_pcmciavar.h

23

#define MALO_READ_2(sc, reg) \

sys/dev/pcmcia/if_malo_pcmciavar.h

24

bus_space_read_2((sc)->sc_iot, (sc)->sc_ioh, (reg))

sys/dev/pcmcia/if_malo_pcmciavar.h

26

#define MALO_READ_MULTI_2(sc, reg, off, size) \

sys/dev/pcmcia/if_malo_pcmciavar.h

27

bus_space_read_multi_stream_2((sc)->sc_iot, (sc)->sc_ioh, (reg), (off), (size))

sys/dev/pcmcia/if_malo_pcmciavar.h

30

#define MALO_READ_MULTI_2(sc, reg, off, size) \

sys/dev/pcmcia/if_malo_pcmciavar.h

31

bus_space_read_multi_2((sc)->sc_iot, (sc)->sc_ioh, (reg), (off), (size))

sys/dev/pcmcia/if_malo_pcmciavar.h

36

#define MALO_WRITE_1(sc, reg, val) \

sys/dev/pcmcia/if_malo_pcmciavar.h

37

bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))

sys/dev/pcmcia/if_malo_pcmciavar.h

38

#define MALO_WRITE_2(sc, reg, val) \

sys/dev/pcmcia/if_malo_pcmciavar.h

39

bus_space_write_2((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))

sys/dev/pcmcia/if_malo_pcmciavar.h

41

#define MALO_WRITE_MULTI_2(sc, reg, off, size) \

sys/dev/pcmcia/if_malo_pcmciavar.h

42

bus_space_write_multi_stream_2((sc)->sc_iot, (sc)->sc_ioh, (reg), (off), (size))

sys/dev/pcmcia/if_malo_pcmciavar.h

45

#define MALO_WRITE_MULTI_2(sc, reg, off, size) \

sys/dev/pcmcia/if_malo_pcmciavar.h

46

bus_space_write_multi_2((sc)->sc_iot, (sc)->sc_ioh, (reg), (off), (size))

sys/dev/pcmcia/if_xi.c

552

xi_mdi_read(device_t self, int phy, int reg, uint16_t *val)

sys/dev/pcmcia/if_xi.c

564

xi_mdi_pulse_bits(sc, reg, 5); /* PHY register */

sys/dev/pcmcia/if_xi.c

575

("xi_mdi_read: phy %d reg %d -> %04hx\n", phy, reg, data));

sys/dev/pcmcia/if_xi.c

583

xi_mdi_write(device_t self, int phy, int reg, uint16_t val)

sys/dev/pcmcia/if_xi.c

593

xi_mdi_pulse_bits(sc, reg, 5); /* PHY register */

sys/dev/pcmcia/if_xi.c

599

("xi_mdi_write: phy %d reg %d val %04hx\n", phy, reg, val));

sys/dev/pcmcia/mhzc.c

477

int memwin, reg;

sys/dev/pcmcia/mhzc.c

506

reg = pcmcia_ccr_read(sc->sc_pf, PCMCIA_CCR_OPTION);

sys/dev/pcmcia/mhzc.c

507

pcmcia_ccr_write(sc->sc_pf, PCMCIA_CCR_OPTION, reg);

sys/dev/pcmcia/mhzc.c

509

reg = bus_space_read_1(memh.memt, memh.memh, 0x380);

sys/dev/pcmcia/mhzc.c

511

reg = bus_space_read_1(memh.memt, memh.memh, 0x380);

sys/dev/pcmcia/mhzc.c

515

reg = pcmcia_ccr_read(sc->sc_pf, PCMCIA_CCR_OPTION);

sys/dev/pcmcia/mhzc.c

517

pcmcia_ccr_write(sc->sc_pf, PCMCIA_CCR_OPTION, reg);

sys/dev/pcmcia/pcmcia.c

476

int reg;

sys/dev/pcmcia/pcmcia.c

550

reg = 0;

sys/dev/pcmcia/pcmcia.c

552

reg |= PCMCIA_CCR_STATUS_AUDIO;

sys/dev/pcmcia/pcmcia.c

553

pcmcia_ccr_write(pf, PCMCIA_CCR_STATUS, reg);

sys/dev/pcmcia/pcmcia.c

557

reg = (pf->cfe->number & PCMCIA_CCR_OPTION_CFINDEX);

sys/dev/pcmcia/pcmcia.c

558

reg |= PCMCIA_CCR_OPTION_LEVIREQ;

sys/dev/pcmcia/pcmcia.c

560

reg |= (PCMCIA_CCR_OPTION_FUNC_ENABLE |

sys/dev/pcmcia/pcmcia.c

563

reg |= PCMCIA_CCR_OPTION_IREQ_ENABLE;

sys/dev/pcmcia/pcmcia.c

566

pcmcia_ccr_write(pf, PCMCIA_CCR_OPTION, reg);

sys/dev/pcmcia/pcmcia.c

616

int reg;

sys/dev/pcmcia/pcmcia.c

630

reg = pcmcia_ccr_read(pf, PCMCIA_CCR_OPTION);

sys/dev/pcmcia/pcmcia.c

631

reg &= ~(PCMCIA_CCR_OPTION_FUNC_ENABLE|

sys/dev/pcmcia/pcmcia.c

634

pcmcia_ccr_write(pf, PCMCIA_CCR_OPTION, reg);

sys/dev/pcmcia/pcmcia_cis.c

1007

reg = pcmcia_tuple_read_1(tuple, 0);

sys/dev/pcmcia/pcmcia_cis.c

1008

rasz = 1 + ((reg & PCMCIA_TPCC_RASZ_MASK) >>

sys/dev/pcmcia/pcmcia_cis.c

1010

rmsz = 1 + ((reg & PCMCIA_TPCC_RMSZ_MASK) >>

sys/dev/pcmcia/pcmcia_cis.c

1012

rfsz = ((reg & PCMCIA_TPCC_RFSZ_MASK) >>

sys/dev/pcmcia/pcmcia_cis.c

1049

u_int reg, reg2;

sys/dev/pcmcia/pcmcia_cis.c

1056

reg = pcmcia_tuple_read_1(tuple, idx);

sys/dev/pcmcia/pcmcia_cis.c

1058

intface = reg & PCMCIA_TPCE_INDX_INTFACE;

sys/dev/pcmcia/pcmcia_cis.c

1059

def = reg & PCMCIA_TPCE_INDX_DEFAULT;

sys/dev/pcmcia/pcmcia_cis.c

1060

num = reg & PCMCIA_TPCE_INDX_NUM_MASK;

sys/dev/pcmcia/pcmcia_cis.c

1132

reg = pcmcia_tuple_read_1(tuple, idx);

sys/dev/pcmcia/pcmcia_cis.c

1138

if (reg & PCMCIA_TPCE_IF_MWAIT)

sys/dev/pcmcia/pcmcia_cis.c

1140

if (reg & PCMCIA_TPCE_IF_RDYBSY)

sys/dev/pcmcia/pcmcia_cis.c

1142

if (reg & PCMCIA_TPCE_IF_WP)

sys/dev/pcmcia/pcmcia_cis.c

1144

if (reg & PCMCIA_TPCE_IF_BVD)

sys/dev/pcmcia/pcmcia_cis.c

1146

cfe->iftype = reg & PCMCIA_TPCE_IF_IFTYPE;

sys/dev/pcmcia/pcmcia_cis.c

1148

reg = pcmcia_tuple_read_1(tuple, idx);

sys/dev/pcmcia/pcmcia_cis.c

1151

power = reg & PCMCIA_TPCE_FS_POWER_MASK;

sys/dev/pcmcia/pcmcia_cis.c

1152

timing = reg & PCMCIA_TPCE_FS_TIMING;

sys/dev/pcmcia/pcmcia_cis.c

1153

iospace = reg & PCMCIA_TPCE_FS_IOSPACE;

sys/dev/pcmcia/pcmcia_cis.c

1154

irq = reg & PCMCIA_TPCE_FS_IRQ;

sys/dev/pcmcia/pcmcia_cis.c

1155

memspace = reg & PCMCIA_TPCE_FS_MEMSPACE_MASK;

sys/dev/pcmcia/pcmcia_cis.c

1156

misc = reg & PCMCIA_TPCE_FS_MISC;

sys/dev/pcmcia/pcmcia_cis.c

1162

reg = pcmcia_tuple_read_1(tuple, idx);

sys/dev/pcmcia/pcmcia_cis.c

1167

if ((reg >> j) & 0x01) {

sys/dev/pcmcia/pcmcia_cis.c

1185

reg = pcmcia_tuple_read_1(tuple, idx);

sys/dev/pcmcia/pcmcia_cis.c

1188

if ((reg & PCMCIA_TPCE_TD_RESERVED_MASK) !=

sys/dev/pcmcia/pcmcia_cis.c

1191

if ((reg & PCMCIA_TPCE_TD_RDYBSY_MASK) !=

sys/dev/pcmcia/pcmcia_cis.c

1194

if ((reg & PCMCIA_TPCE_TD_WAIT_MASK) !=

sys/dev/pcmcia/pcmcia_cis.c

1204

reg = pcmcia_tuple_read_1(tuple, idx);

sys/dev/pcmcia/pcmcia_cis.c

1209

if (reg & PCMCIA_TPCE_IO_BUSWIDTH_8BIT)

sys/dev/pcmcia/pcmcia_cis.c

1211

if (reg & PCMCIA_TPCE_IO_BUSWIDTH_16BIT)

sys/dev/pcmcia/pcmcia_cis.c

1214

reg & PCMCIA_TPCE_IO_IOADDRLINES_MASK;

sys/dev/pcmcia/pcmcia_cis.c

1216

if (reg & PCMCIA_TPCE_IO_HASRANGE) {

sys/dev/pcmcia/pcmcia_cis.c

1217

reg = pcmcia_tuple_read_1(tuple, idx);

sys/dev/pcmcia/pcmcia_cis.c

1220

cfe->num_iospace = 1 + (reg &

sys/dev/pcmcia/pcmcia_cis.c

1233

switch (reg & PCMCIA_TPCE_IO_RANGE_ADDRSIZE_MASK) {

sys/dev/pcmcia/pcmcia_cis.c

1254

switch (reg &

sys/dev/pcmcia/pcmcia_cis.c

1291

reg = pcmcia_tuple_read_1(tuple, idx);

sys/dev/pcmcia/pcmcia_cis.c

1297

if (reg & PCMCIA_TPCE_IR_SHARE)

sys/dev/pcmcia/pcmcia_cis.c

1299

if (reg & PCMCIA_TPCE_IR_PULSE)

sys/dev/pcmcia/pcmcia_cis.c

1301

if (reg & PCMCIA_TPCE_IR_LEVEL)

sys/dev/pcmcia/pcmcia_cis.c

1304

if (reg & PCMCIA_TPCE_IR_HASMASK) {

sys/dev/pcmcia/pcmcia_cis.c

1315

(1 << (reg & PCMCIA_TPCE_IR_IRQ));

sys/dev/pcmcia/pcmcia_cis.c

1357

reg = pcmcia_tuple_read_1(tuple, idx);

sys/dev/pcmcia/pcmcia_cis.c

1360

cfe->num_memspace = (reg & PCMCIA_TPCE_MS_COUNT)

sys/dev/pcmcia/pcmcia_cis.c

1372

((reg & PCMCIA_TPCE_MS_LENGTH_SIZE_MASK) >>

sys/dev/pcmcia/pcmcia_cis.c

1375

((reg &

sys/dev/pcmcia/pcmcia_cis.c

1379

(reg & PCMCIA_TPCE_MS_HOSTADDR) ?

sys/dev/pcmcia/pcmcia_cis.c

1429

reg = pcmcia_tuple_read_1(tuple, idx);

sys/dev/pcmcia/pcmcia_cis.c

1435

if (reg & PCMCIA_TPCE_MI_PWRDOWN)

sys/dev/pcmcia/pcmcia_cis.c

1437

if (reg & PCMCIA_TPCE_MI_READONLY)

sys/dev/pcmcia/pcmcia_cis.c

1439

if (reg & PCMCIA_TPCE_MI_AUDIO)

sys/dev/pcmcia/pcmcia_cis.c

1441

cfe->maxtwins = reg & PCMCIA_TPCE_MI_MAXTWINS;

sys/dev/pcmcia/pcmcia_cis.c

1443

while (reg & PCMCIA_TPCE_MI_EXT) {

sys/dev/pcmcia/pcmcia_cis.c

1444

reg = pcmcia_tuple_read_1(tuple, idx);

sys/dev/pcmcia/pcmcia_cis.c

801

u_int reg, dtype, dspeed;

sys/dev/pcmcia/pcmcia_cis.c

803

reg = pcmcia_tuple_read_1(tuple, 0);

sys/dev/pcmcia/pcmcia_cis.c

804

dtype = reg & PCMCIA_DTYPE_MASK;

sys/dev/pcmcia/pcmcia_cis.c

805

dspeed = reg & PCMCIA_DSPEED_MASK;

sys/dev/pcmcia/pcmcia_cis.c

993

u_int reg, rasz, rmsz, rfsz;

sys/dev/podulebus/esp_podule.c

310

castle_read_reg(struct ncr53c9x_softc *sc, int reg)

sys/dev/podulebus/esp_podule.c

315

val = CASTLE_ESP_READ(esc, reg);

sys/dev/podulebus/esp_podule.c

320

castle_write_reg(struct ncr53c9x_softc *sc, int reg, uint8_t val)

sys/dev/podulebus/esp_podule.c

324

if (reg == NCR_CMD && val == (NCRCMD_TRANS | NCRCMD_DMA))

sys/dev/podulebus/esp_podule.c

326

CASTLE_ESP_WRITE(esc, reg, val);

sys/dev/podulebus/sec.c

131

dmac_write(struct sec_softc *sc, int reg, uint8_t val)

sys/dev/podulebus/sec.c

135

SEC_DMAC + DMAC(reg), val);

sys/dev/podulebus/sec.c

139

dmac_read(struct sec_softc *sc, int reg)

sys/dev/podulebus/sec.c

143

SEC_DMAC + DMAC(reg));

sys/dev/ppbus/ppbus_msq.h

138

#define MS_RSET(reg,assert,clear) { MS_OP_RSET, {{ reg }, { assert }, { clear }}}

sys/dev/ppbus/ppbus_msq.h

139

#define MS_RASSERT(reg,byte) { MS_OP_RASSERT, { { reg }, { byte }}}

sys/dev/ppbus/ppbus_msq.h

140

#define MS_RCLR(reg,clear) { MS_OP_RSET, {{ reg }, { MS_ASSERT_NONE }, { clear }}}

sys/dev/ppbus/ppbus_msq.h

142

#define MS_RFETCH(reg,mask,ptr) { MS_OP_RFETCH, {{ reg }, { mask }, { ptr }}}

sys/dev/ppbus/ppbus_msq.h

145

#define MS_TRIG(reg,len,array) { MS_OP_TRIG, {{ reg }, { len }, { array }}}

sys/dev/ppbus/ppbus_msq.h

148

#define MS_RASSERT_P(n,reg) { MS_OP_RASSERT_P, {{ n }, { reg }}}

sys/dev/ppbus/ppbus_msq.h

149

#define MS_RFETCH_P(n,reg,mask) { MS_OP_RFETCH_P, {{ n }, { reg }, { mask }}}

sys/dev/qbus/dhu.c

139

#define DHU_READ_WORD(reg) \

sys/dev/qbus/dhu.c

140

bus_space_read_2(sc->sc_iot, sc->sc_ioh, reg)

sys/dev/qbus/dhu.c

141

#define DHU_WRITE_WORD(reg, val) \

sys/dev/qbus/dhu.c

142

bus_space_write_2(sc->sc_iot, sc->sc_ioh, reg, val)

sys/dev/qbus/dhu.c

143

#define DHU_READ_BYTE(reg) \

sys/dev/qbus/dhu.c

144

bus_space_read_1(sc->sc_iot, sc->sc_ioh, reg)

sys/dev/qbus/dhu.c

145

#define DHU_WRITE_BYTE(reg, val) \

sys/dev/qbus/dhu.c

146

bus_space_write_1(sc->sc_iot, sc->sc_ioh, reg, val)

sys/dev/qbus/dl.c

175

#define DL_READ_WORD(reg) \

sys/dev/qbus/dl.c

176

bus_space_read_2(sc->sc_iot, sc->sc_ioh, reg)

sys/dev/qbus/dl.c

177

#define DL_WRITE_WORD(reg, val) \

sys/dev/qbus/dl.c

178

bus_space_write_2(sc->sc_iot, sc->sc_ioh, reg, val)

sys/dev/qbus/dl.c

179

#define DL_WRITE_BYTE(reg, val) \

sys/dev/qbus/dl.c

180

bus_space_write_1(sc->sc_iot, sc->sc_ioh, reg, val)

sys/dev/qbus/qd.c

539

#define QD_RCSR(reg) \

sys/dev/qbus/qd.c

540

bus_space_read_2(sc->sc_iot, sc->sc_ioh, reg)

sys/dev/qbus/qd.c

541

#define QD_WCSR(reg, val) \

sys/dev/qbus/qd.c

542

bus_space_write_2(sc->sc_iot, sc->sc_ioh, reg, val)

sys/dev/qbus/qd.c

607

qdflags[unit].config = *(u_short *)reg;

sys/dev/qbus/qd.c

628

*(u_short *)reg = (u_short) ((int)phys_adr >> 16);

sys/dev/qbus/qd.c

677

qdaddr = (void *)reg;

sys/dev/qbus/rl.c

120

#define RL_WREG(reg, val) \

sys/dev/qbus/rl.c

121

bus_space_write_2(sc->sc_iot, sc->sc_ioh, (reg), (val))

sys/dev/qbus/rl.c

122

#define RL_RREG(reg) \

sys/dev/qbus/rl.c

123

bus_space_read_2(sc->sc_iot, sc->sc_ioh, (reg))

sys/dev/sbus/agten.c

190

agten_write_dac(struct agten_softc *sc, int reg, uint8_t val)

sys/dev/sbus/agten.c

193

0x200 + (reg << 2), (uint32_t)val << 16);

sys/dev/sbus/agten.c

206

agten_write_dac_10(struct agten_softc *sc, int reg, uint16_t val)

sys/dev/sbus/agten.c

208

agten_write_dac(sc, reg, (val >> 2) & 0xff);

sys/dev/sbus/agten.c

209

agten_write_dac(sc, reg, (val & 0x3) << 6);

sys/dev/sbus/agten.c

231

uint32_t reg;

sys/dev/sbus/agten.c

257

reg = prom_getpropint(node, "i128_fb_physaddr", -1);

sys/dev/sbus/agten.c

260

sa->sa_reg[0].oa_space, sa->sa_reg[0].oa_base + reg,

sys/dev/sbus/agten.c

270

reg = prom_getpropint(node, "i128_reg_physaddr", -1);

sys/dev/sbus/agten.c

272

sa->sa_reg[0].oa_space, sa->sa_reg[0].oa_base + reg,

sys/dev/sbus/agten.c

279

reg = prom_getpropint(node, "p9100_reg_physaddr", -1);

sys/dev/sbus/agten.c

281

sa->sa_reg[0].oa_space, sa->sa_reg[0].oa_base + reg,

sys/dev/sbus/agten.c

288

reg = prom_getpropint(node, "glint_fb0_physaddr", -1);

sys/dev/sbus/agten.c

290

sa->sa_reg[0].oa_space, sa->sa_reg[0].oa_base + reg);

sys/dev/sbus/agten.c

292

reg = prom_getpropint(node, "glint_reg_physaddr", -1);

sys/dev/sbus/agten.c

294

sa->sa_reg[0].oa_space, sa->sa_reg[0].oa_base + reg);

sys/dev/sbus/agten.c

725

uint8_t reg =

sys/dev/sbus/agten.c

732

agten_write_dac(sc, IBM561_CMD, flag ? reg | CR2_ENABLE_RGB_OUTPUT :

sys/dev/sbus/agten.c

733

reg);

sys/dev/sbus/be.c

1281

be_mii_readreg(device_t self, int phy, int reg, uint16_t *val)

sys/dev/sbus/be.c

1294

be_mii_sendbits(sc, phy, reg, 5);

sys/dev/sbus/be.c

1311

be_mii_writereg(device_t self, int phy, int reg, uint16_t val)

sys/dev/sbus/be.c

1323

be_mii_sendbits(sc, phy, reg, 5);

sys/dev/sbus/bpp.c

431

#define _bpp_set(reg,mask) do { \

sys/dev/sbus/bpp.c

432

chw->reg &= ~(mask); \

sys/dev/sbus/bpp.c

433

chw->reg |= (hw->reg & (mask)); \

sys/dev/sbus/dbri.c

537

uint32_t reg;

sys/dev/sbus/dbri.c

562

reg = bus_space_read_4(iot, ioh, DBRI_REG0);

sys/dev/sbus/dbri.c

565

reg |= (DBRI_BURST_4 | DBRI_BURST_8);

sys/dev/sbus/dbri.c

566

bus_space_write_4(iot, ioh, DBRI_REG0, reg);

sys/dev/sbus/esp_sbus.c

575

esp_read_reg(struct ncr53c9x_softc *sc, int reg)

sys/dev/sbus/esp_sbus.c

580

v = bus_space_read_1(esc->sc_bustag, esc->sc_reg, reg * 4);

sys/dev/sbus/esp_sbus.c

582

if (esp_sbus_debug && (reg < 0x10) && esp__read_regnames[reg].r_flag)

sys/dev/sbus/esp_sbus.c

583

printf("RD:%x <%s> %x\n", reg * 4,

sys/dev/sbus/esp_sbus.c

584

((unsigned int)reg < 0x10) ?

sys/dev/sbus/esp_sbus.c

585

esp__read_regnames[reg].r_name : "<***>", v);

sys/dev/sbus/esp_sbus.c

591

esp_write_reg(struct ncr53c9x_softc *sc, int reg, uint8_t v)

sys/dev/sbus/esp_sbus.c

596

if (esp_sbus_debug && (reg < 0x10) && esp__write_regnames[reg].r_flag)

sys/dev/sbus/esp_sbus.c

597

printf("WR:%x <%s> %x\n", reg * 4,

sys/dev/sbus/esp_sbus.c

598

((unsigned int)reg < 0x10) ?

sys/dev/sbus/esp_sbus.c

599

esp__write_regnames[reg].r_name : "<***>", v);

sys/dev/sbus/esp_sbus.c

601

bus_space_write_1(esc->sc_bustag, esc->sc_reg, reg * 4, v);

sys/dev/sbus/esp_sbus.c

605

esp_rdreg1(struct ncr53c9x_softc *sc, int reg)

sys/dev/sbus/esp_sbus.c

609

return bus_space_read_1(esc->sc_bustag, esc->sc_reg, reg);

sys/dev/sbus/esp_sbus.c

613

esp_wrreg1(struct ncr53c9x_softc *sc, int reg, uint8_t v)

sys/dev/sbus/esp_sbus.c

617

bus_space_write_1(esc->sc_bustag, esc->sc_reg, reg, v);

sys/dev/sbus/magma.c

276

cd1400_read_reg(struct cd1400 *cd, int reg)

sys/dev/sbus/magma.c

278

return(cd->cd_reg[reg]);

sys/dev/sbus/magma.c

285

cd1400_write_reg(struct cd1400 *cd, int reg, u_char value)

sys/dev/sbus/magma.c

287

cd->cd_reg[reg] = value;

sys/dev/sbus/mgx.c

1278

uint32_t reg;

sys/dev/sbus/mgx.c

1281

reg = (sc->sc_cursor_y << 16) | (sc->sc_cursor_x & 0xffff);

sys/dev/sbus/mgx.c

1282

mgx_write_4(sc, ATR_CURSOR_POSITION, reg);

sys/dev/sbus/mgx.c

1290

uint8_t reg;

sys/dev/sbus/mgx.c

1296

reg = mgx_read_1(sc, ATR_DPMS);

sys/dev/sbus/mgx.c

1299

reg &= ~DPMS_SYNC_DISABLE_ALL;

sys/dev/sbus/mgx.c

1301

reg |= DPMS_SYNC_DISABLE_ALL;

sys/dev/sbus/mgx.c

1303

mgx_write_1(sc, ATR_DPMS, reg);

sys/dev/sbus/mgx.c

176

mgx_write_vga(struct mgx_softc *sc, uint32_t reg, uint8_t val)

sys/dev/sbus/mgx.c

178

bus_space_write_1(sc->sc_tag, sc->sc_vgah, reg ^ 3, val);

sys/dev/sbus/mgx.c

182

mgx_read_vga(struct mgx_softc *sc, uint32_t reg)

sys/dev/sbus/mgx.c

184

return bus_space_read_1(sc->sc_tag, sc->sc_vgah, reg ^ 3);

sys/dev/sbus/mgx.c

188

mgx_write_1(struct mgx_softc *sc, uint32_t reg, uint8_t val)

sys/dev/sbus/mgx.c

190

bus_space_write_1(sc->sc_tag, sc->sc_blith, reg ^ 3, val);

sys/dev/sbus/mgx.c

194

mgx_read_1(struct mgx_softc *sc, uint32_t reg)

sys/dev/sbus/mgx.c

196

return bus_space_read_1(sc->sc_tag, sc->sc_blith, reg ^ 3);

sys/dev/sbus/mgx.c

201

mgx_read_4(struct mgx_softc *sc, uint32_t reg)

sys/dev/sbus/mgx.c

203

return bus_space_read_4(sc->sc_tag, sc->sc_blith, reg);

sys/dev/sbus/mgx.c

208

mgx_write_2(struct mgx_softc *sc, uint32_t reg, uint16_t val)

sys/dev/sbus/mgx.c

210

bus_space_write_2(sc->sc_tag, sc->sc_blith, reg ^ 2, val);

sys/dev/sbus/mgx.c

214

mgx_write_4(struct mgx_softc *sc, uint32_t reg, uint32_t val)

sys/dev/sbus/mgx.c

216

bus_space_write_4(sc->sc_tag, sc->sc_blith, reg, val);

sys/dev/sbus/mgx.c

550

uint8_t reg;

sys/dev/sbus/mgx.c

568

reg = mgx_read_1(sc, ATR_PIXEL);

sys/dev/sbus/mgx.c

569

reg &= ~PIXEL_DEPTH_MASK;

sys/dev/sbus/mgx.c

574

reg |= PIXEL_8;

sys/dev/sbus/mgx.c

578

reg |= PIXEL_15;

sys/dev/sbus/mgx.c

582

reg |= PIXEL_16;

sys/dev/sbus/mgx.c

586

reg |= PIXEL_32;

sys/dev/sbus/mgx.c

626

mgx_write_1(sc, ATR_PIXEL, reg);

sys/dev/sbus/p9100.c

748

p9100_set_color_reg(struct p9100_softc *sc, int reg, int32_t col)

sys/dev/sbus/p9100.c

764

p9100_ctl_write_4(sc, reg, out);

sys/dev/sbus/tcx.c

1422

uint32_t reg;

sys/dev/sbus/tcx.c

1424

reg = (((sc->sc_cursor_x - sc->sc_hotspot_x) & 0xfff) << 16) |

sys/dev/sbus/tcx.c

1426

bus_space_write_4(sc->sc_bustag, sc->sc_thc, THC_CURSOR_POS, reg);

sys/dev/sbus/tcx.c

533

uint32_t reg;

sys/dev/sbus/tcx.c

535

reg = bus_space_read_4(sc->sc_bustag, sc->sc_thc, THC_MISC);

sys/dev/sbus/tcx.c

536

reg |= THC_MISC_CURSRES;

sys/dev/sbus/tcx.c

537

bus_space_write_4(sc->sc_bustag, sc->sc_thc, THC_MISC, reg);

sys/dev/sbus/tcx.c

581

uint32_t reg;

sys/dev/sbus/tcx.c

583

reg = bus_space_read_4(sc->sc_bustag, sc->sc_thc, THC_MISC);

sys/dev/sbus/tcx.c

584

reg &= ~THC_MISC_VSYNC_DISABLE;

sys/dev/sbus/tcx.c

585

reg &= ~THC_MISC_HSYNC_DISABLE;

sys/dev/sbus/tcx.c

586

reg |= THC_MISC_VIDEN;

sys/dev/sbus/tcx.c

587

bus_space_write_4(sc->sc_bustag, sc->sc_thc, THC_MISC, reg);

sys/dev/sbus/tcx.c

594

uint32_t reg;

sys/dev/sbus/tcx.c

597

reg = bus_space_read_4(sc->sc_bustag, sc->sc_thc, THC_MISC);

sys/dev/sbus/tcx.c

598

reg &= ~THC_MISC_VSYNC_DISABLE;

sys/dev/sbus/tcx.c

599

reg &= ~THC_MISC_HSYNC_DISABLE;

sys/dev/sbus/tcx.c

600

reg |= THC_MISC_VIDEN;

sys/dev/sbus/tcx.c

601

bus_space_write_4(sc->sc_bustag, sc->sc_thc, THC_MISC, reg);

sys/dev/sbus/tcx.c

604

reg = bus_space_read_4(sc->sc_bustag, sc->sc_thc, THC_MISC);

sys/dev/sbus/tcx.c

605

reg |= THC_MISC_VSYNC_DISABLE;

sys/dev/sbus/tcx.c

606

reg |= THC_MISC_HSYNC_DISABLE;

sys/dev/sbus/tcx.c

607

reg &= ~THC_MISC_VIDEN;

sys/dev/sbus/tcx.c

608

bus_space_write_4(sc->sc_bustag, sc->sc_thc, THC_MISC, reg);

sys/dev/sdmmc/if_bwfm_sdio.c

373

uint32_t reg;

sys/dev/sdmmc/if_bwfm_sdio.c

435

reg = bwfm_sdio_read_1(sc, BWFM_SDIO_FUNC1_SLEEPCSR);

sys/dev/sdmmc/if_bwfm_sdio.c

436

if ((reg & BWFM_SDIO_FUNC1_SLEEPCSR_KSO) == 0) {

sys/dev/sdmmc/if_bwfm_sdio.c

437

reg |= BWFM_SDIO_FUNC1_SLEEPCSR_KSO;

sys/dev/sdmmc/if_bwfm_sdio.c

438

bwfm_sdio_write_1(sc, BWFM_SDIO_FUNC1_SLEEPCSR, reg);

sys/dev/sdmmc/if_bwfm_sdio.c

475

uint32_t reg, clk;

sys/dev/sdmmc/if_bwfm_sdio.c

544

reg = bwfm_sdio_read_1(sc, BWFM_SDIO_FUNC1_WAKEUPCTRL);

sys/dev/sdmmc/if_bwfm_sdio.c

545

reg |= BWFM_SDIO_FUNC1_WAKEUPCTRL_HTWAIT;

sys/dev/sdmmc/if_bwfm_sdio.c

546

bwfm_sdio_write_1(sc, BWFM_SDIO_FUNC1_WAKEUPCTRL, reg);

sys/dev/sdmmc/if_bwfm_sdio.c

792

uint32_t reg, char *data, size_t size)

sys/dev/sdmmc/if_bwfm_sdio.c

800

err = sdmmc_io_read_region_1(sf, reg, data, size);

sys/dev/sdmmc/if_bwfm_sdio.c

802

err = sdmmc_io_read_multi_1(sf, reg, data, size);

sys/dev/sdmmc/if_bwfm_sdio.c

812

uint32_t reg, char *data, size_t size)

sys/dev/sdmmc/if_bwfm_sdio.c

819

err = sdmmc_io_write_region_1(sf, reg, data, size);

sys/dev/sdmmc/if_bwfm_sdio.c

828

bwfm_sdio_ram_read_write(struct bwfm_sdio_softc *sc, uint32_t reg,

sys/dev/sdmmc/if_bwfm_sdio.c

837

sbaddr = reg + off;

sys/dev/sdmmc/if_bwfm_sdio.c

892

bwfm_sdio_dev_read(struct bwfm_sdio_softc *sc, uint32_t reg)

sys/dev/sdmmc/if_bwfm_sdio.c

898

val = bwfm_sdio_read_4(sc, core->co_base + reg);

sys/dev/sdmmc/if_bwfm_sdio.c

905

bwfm_sdio_dev_write(struct bwfm_sdio_softc *sc, uint32_t reg, uint32_t val)

sys/dev/sdmmc/if_bwfm_sdio.c

910

bwfm_sdio_write_4(sc, core->co_base + reg, val);

sys/dev/sdmmc/if_bwfm_sdio.c

914

bwfm_sdio_buscore_read(struct bwfm_softc *bwfm, uint32_t reg)

sys/dev/sdmmc/if_bwfm_sdio.c

920

val = bwfm_sdio_read_4(sc, reg);

sys/dev/sdmmc/if_bwfm_sdio.c

928

bwfm_sdio_buscore_write(struct bwfm_softc *bwfm, uint32_t reg, uint32_t val)

sys/dev/sdmmc/if_bwfm_sdio.c

933

bwfm_sdio_write_4(sc, reg, val);

sys/dev/sdmmc/if_bwi_sdio.c

217

uint32_t reg;

sys/dev/sdmmc/if_bwi_sdio.c

220

reg = sdmmc_cisptr(ssc->sc_sf);

sys/dev/sdmmc/if_bwi_sdio.c

222

tplcode = sdmmc_io_read_1(sf0, reg++);

sys/dev/sdmmc/if_bwi_sdio.c

226

tpllen = sdmmc_io_read_1(sf0, reg++);

sys/dev/sdmmc/if_bwi_sdio.c

231

reg += tpllen;

sys/dev/sdmmc/if_bwi_sdio.c

235

switch (sdmmc_io_read_1(sf0, reg)) {

sys/dev/sdmmc/if_bwi_sdio.c

237

sprom->srom_rev = sdmmc_io_read_1(sf0, reg + 1);

sys/dev/sdmmc/if_bwi_sdio.c

241

sdmmc_io_read_1(sf0, reg + 1) |

sys/dev/sdmmc/if_bwi_sdio.c

242

((uint16_t)sdmmc_io_read_1(sf0, reg + 2) << 8);

sys/dev/sdmmc/if_bwi_sdio.c

246

sdmmc_io_read_1(sf0, reg + 1);

sys/dev/sdmmc/if_bwi_sdio.c

250

sdmmc_io_read_1(sf0, reg + 1) |

sys/dev/sdmmc/if_bwi_sdio.c

251

((uint16_t)sdmmc_io_read_1(sf0, reg + 2) << 8);

sys/dev/sdmmc/if_bwi_sdio.c

253

sdmmc_io_read_1(sf0, reg + 3) |

sys/dev/sdmmc/if_bwi_sdio.c

254

((uint16_t)sdmmc_io_read_1(sf0, reg + 4) << 8);

sys/dev/sdmmc/if_bwi_sdio.c

256

sdmmc_io_read_1(sf0, reg + 5) |

sys/dev/sdmmc/if_bwi_sdio.c

257

((uint16_t)sdmmc_io_read_1(sf0, reg + 6) << 8);

sys/dev/sdmmc/if_bwi_sdio.c

259

sdmmc_io_read_1(sf0, reg + 7);

sys/dev/sdmmc/if_bwi_sdio.c

261

sdmmc_io_read_1(sf0, reg + 8);

sys/dev/sdmmc/if_bwi_sdio.c

265

sdmmc_io_read_1(sf0, reg + 1);

sys/dev/sdmmc/if_bwi_sdio.c

268

sprom->ant_gain = sdmmc_io_read_1(sf0, reg + 1);

sys/dev/sdmmc/if_bwi_sdio.c

272

sdmmc_io_read_1(sf0, reg + 1) |

sys/dev/sdmmc/if_bwi_sdio.c

273

((uint16_t)sdmmc_io_read_1(sf0, reg + 2) << 8);

sys/dev/sdmmc/if_bwi_sdio.c

276

sprom->gpio[0] = sdmmc_io_read_1(sf0, reg + 1);

sys/dev/sdmmc/if_bwi_sdio.c

277

sprom->gpio[1] = sdmmc_io_read_1(sf0, reg + 2);

sys/dev/sdmmc/if_bwi_sdio.c

278

sprom->gpio[2] = sdmmc_io_read_1(sf0, reg + 3);

sys/dev/sdmmc/if_bwi_sdio.c

279

sprom->gpio[3] = sdmmc_io_read_1(sf0, reg + 4);

sys/dev/sdmmc/if_bwi_sdio.c

283

reg += tpllen;

sys/dev/sdmmc/if_bwi_sdio.c

298

bwi_sdio_conf_write(void *priv, uint32_t reg, uint32_t val)

sys/dev/sdmmc/if_bwi_sdio.c

302

KASSERT(reg == BWI_PCIR_SEL_REGWIN);

sys/dev/sdmmc/if_bwi_sdio.c

305

if (reg == BWI_PCIR_SEL_REGWIN && ssc->sc_sel_regwin != val) {

sys/dev/sdmmc/if_bwi_sdio.c

318

bwi_sdio_conf_read(void *priv, uint32_t reg)

sys/dev/sdmmc/if_bwi_sdio.c

322

KASSERT(reg == BWI_PCIR_SEL_REGWIN);

sys/dev/sdmmc/if_bwi_sdio.c

324

if (reg == BWI_PCIR_SEL_REGWIN) {

sys/dev/sdmmc/if_bwi_sdio.c

332

bwi_sdio_reg_write_multi_4(void *priv, uint32_t reg, const uint32_t *datap,

sys/dev/sdmmc/if_bwi_sdio.c

339

BWI_SDIO_REG_OFFSET(ssc, reg) | BWI_SDIO_REG_32BIT_ACCESS,

sys/dev/sdmmc/if_bwi_sdio.c

345

bwi_sdio_reg_read_multi_4(void *priv, uint32_t reg, uint32_t *datap,

sys/dev/sdmmc/if_bwi_sdio.c

352

BWI_SDIO_REG_OFFSET(ssc, reg) | BWI_SDIO_REG_32BIT_ACCESS,

sys/dev/sdmmc/if_bwi_sdio.c

358

bwi_sdio_reg_write_2(void *priv, uint32_t reg, uint16_t val)

sys/dev/sdmmc/if_bwi_sdio.c

365

sdmmc_io_write_2(ssc->sc_sf, BWI_SDIO_REG_OFFSET(ssc, reg), val);

sys/dev/sdmmc/if_bwi_sdio.c

370

bwi_sdio_reg_read_sprom(struct bwi_sdio_softc *ssc, uint32_t reg)

sys/dev/sdmmc/if_bwi_sdio.c

375

switch (reg) {

sys/dev/sdmmc/if_bwi_sdio.c

377

return *(uint16_t *)&cis->lan_nid[reg - BWI_SPROM_11BG_EADDR];

sys/dev/sdmmc/if_bwi_sdio.c

379

return *(uint16_t *)&cis->lan_nid[reg - BWI_SPROM_11A_EADDR];

sys/dev/sdmmc/if_bwi_sdio.c

383

return sprom->pa_params[(reg - BWI_SPROM_PA_PARAM_11BG) / 2];

sys/dev/sdmmc/if_bwi_sdio.c

385

return sprom->pa_params[(reg - BWI_SPROM_PA_PARAM_11A) / 2];

sys/dev/sdmmc/if_bwi_sdio.c

404

bwi_sdio_reg_read_2(void *priv, uint32_t reg)

sys/dev/sdmmc/if_bwi_sdio.c

410

if (reg >= BWI_SPROM_START &&

sys/dev/sdmmc/if_bwi_sdio.c

411

reg <= BWI_SPROM_START + BWI_SPROM_ANT_GAIN) {

sys/dev/sdmmc/if_bwi_sdio.c

412

return bwi_sdio_reg_read_sprom(ssc, reg - BWI_SPROM_START);

sys/dev/sdmmc/if_bwi_sdio.c

416

val = sdmmc_io_read_2(ssc->sc_sf, BWI_SDIO_REG_OFFSET(ssc, reg));

sys/dev/sdmmc/if_bwi_sdio.c

425

bwi_sdio_reg_write_4(void *priv, uint32_t reg, uint32_t val)

sys/dev/sdmmc/if_bwi_sdio.c

433

BWI_SDIO_REG_OFFSET(ssc, reg) | BWI_SDIO_REG_32BIT_ACCESS, val);

sys/dev/sdmmc/if_bwi_sdio.c

440

bwi_sdio_reg_read_4(void *priv, uint32_t reg)

sys/dev/sdmmc/if_bwi_sdio.c

447

BWI_SDIO_REG_OFFSET(ssc, reg) | BWI_SDIO_REG_32BIT_ACCESS);

sys/dev/sdmmc/if_bwi_sdio.c

75

#define BWI_SDIO_REG_OFFSET(ssc, reg) \

sys/dev/sdmmc/if_bwi_sdio.c

76

((reg) | ((ssc)->sc_sel_regwin & 0x7000))

sys/dev/sdmmc/sbt.c

39

#define CSR_READ_1(sc, reg) sdmmc_io_read_1((sc)->sc_sf, (reg))

sys/dev/sdmmc/sbt.c

40

#define CSR_WRITE_1(sc, reg, val) sdmmc_io_write_1((sc)->sc_sf, (reg), (val))

sys/dev/sdmmc/sdhc.c

109

hread1(struct sdhc_host *hp, bus_size_t reg)

sys/dev/sdmmc/sdhc.c

1102

int16_t reg;

sys/dev/sdmmc/sdhc.c

113

return bus_space_read_1(hp->iot, hp->ioh, reg);

sys/dev/sdmmc/sdhc.c

114

return bus_space_read_4(hp->iot, hp->ioh, reg & -4) >> (8 * (reg & 3));

sys/dev/sdmmc/sdhc.c

118

hread2(struct sdhc_host *hp, bus_size_t reg)

sys/dev/sdmmc/sdhc.c

1216

reg = HREAD2(hp, SDHC_CLOCK_CTL);

sys/dev/sdmmc/sdhc.c

1217

reg &= (SDHC_INTCLK_STABLE | SDHC_INTCLK_ENABLE);

sys/dev/sdmmc/sdhc.c

1218

HWRITE2(hp, SDHC_CLOCK_CTL, reg | div);

sys/dev/sdmmc/sdhc.c

122

return bus_space_read_2(hp->iot, hp->ioh, reg);

sys/dev/sdmmc/sdhc.c

123

return bus_space_read_4(hp->iot, hp->ioh, reg & -4) >> (8 * (reg & 2));

sys/dev/sdmmc/sdhc.c

126

#define HREAD1(hp, reg) hread1(hp, reg)

sys/dev/sdmmc/sdhc.c

127

#define HREAD2(hp, reg) hread2(hp, reg)

sys/dev/sdmmc/sdhc.c

128

#define HREAD4(hp, reg) \

sys/dev/sdmmc/sdhc.c

129

(bus_space_read_4((hp)->iot, (hp)->ioh, (reg)))

sys/dev/sdmmc/sdhc.c

1305

int reg;

sys/dev/sdmmc/sdhc.c

1330

reg = HREAD1(hp, SDHC_HOST_CTL);

sys/dev/sdmmc/sdhc.c

1332

reg &= ~(SDHC_4BIT_MODE|SDHC_ESDHC_8BIT_MODE);

sys/dev/sdmmc/sdhc.c

1334

reg |= SDHC_4BIT_MODE;

sys/dev/sdmmc/sdhc.c

1336

reg |= SDHC_ESDHC_8BIT_MODE;

sys/dev/sdmmc/sdhc.c

1338

reg &= ~SDHC_4BIT_MODE;

sys/dev/sdmmc/sdhc.c

1340

reg &= ~SDHC_8BIT_MODE;

sys/dev/sdmmc/sdhc.c

1343

reg |= SDHC_4BIT_MODE;

sys/dev/sdmmc/sdhc.c

1345

reg |= SDHC_8BIT_MODE;

sys/dev/sdmmc/sdhc.c

1348

HWRITE1(hp, SDHC_HOST_CTL, reg);

sys/dev/sdmmc/sdhc.c

169

#define HWRITE1(hp, reg, val) hwrite1(hp, reg, val)

sys/dev/sdmmc/sdhc.c

170

#define HWRITE2(hp, reg, val) hwrite2(hp, reg, val)

sys/dev/sdmmc/sdhc.c

171

#define HWRITE4(hp, reg, val) hwrite4(hp, reg, val)

sys/dev/sdmmc/sdhc.c

173

#define HCLR1(hp, reg, bits) \

sys/dev/sdmmc/sdhc.c

174

do if ((bits) != 0) HWRITE1((hp), (reg), HREAD1((hp), (reg)) & ~(bits)); while (0)

sys/dev/sdmmc/sdhc.c

175

#define HCLR2(hp, reg, bits) \

sys/dev/sdmmc/sdhc.c

176

do if ((bits) != 0) HWRITE2((hp), (reg), HREAD2((hp), (reg)) & ~(bits)); while (0)

sys/dev/sdmmc/sdhc.c

177

#define HCLR4(hp, reg, bits) \

sys/dev/sdmmc/sdhc.c

178

do if ((bits) != 0) HWRITE4((hp), (reg), HREAD4((hp), (reg)) & ~(bits)); while (0)

sys/dev/sdmmc/sdhc.c

179

#define HSET1(hp, reg, bits) \

sys/dev/sdmmc/sdhc.c

180

do if ((bits) != 0) HWRITE1((hp), (reg), HREAD1((hp), (reg)) | (bits)); while (0)

sys/dev/sdmmc/sdhc.c

181

#define HSET2(hp, reg, bits) \

sys/dev/sdmmc/sdhc.c

182

do if ((bits) != 0) HWRITE2((hp), (reg), HREAD2((hp), (reg)) | (bits)); while (0)

sys/dev/sdmmc/sdhc.c

183

#define HSET4(hp, reg, bits) \

sys/dev/sdmmc/sdhc.c

184

do if ((bits) != 0) HWRITE4((hp), (reg), HREAD4((hp), (reg)) | (bits)); while (0)

sys/dev/sdmmc/sdhc.c

2505

sdhc_host_read_1(struct sdhc_host *hp, int reg)

sys/dev/sdmmc/sdhc.c

2507

return HREAD1(hp, reg);

sys/dev/sdmmc/sdhc.c

2511

sdhc_host_read_2(struct sdhc_host *hp, int reg)

sys/dev/sdmmc/sdhc.c

2513

return HREAD2(hp, reg);

sys/dev/sdmmc/sdhc.c

2517

sdhc_host_read_4(struct sdhc_host *hp, int reg)

sys/dev/sdmmc/sdhc.c

2519

return HREAD4(hp, reg);

sys/dev/sdmmc/sdhc.c

2523

sdhc_host_write_1(struct sdhc_host *hp, int reg, uint8_t val)

sys/dev/sdmmc/sdhc.c

2525

HWRITE1(hp, reg, val);

sys/dev/sdmmc/sdhc.c

2529

sdhc_host_write_2(struct sdhc_host *hp, int reg, uint16_t val)

sys/dev/sdmmc/sdhc.c

2531

HWRITE2(hp, reg, val);

sys/dev/sdmmc/sdhc.c

2535

sdhc_host_write_4(struct sdhc_host *hp, int reg, uint32_t val)

sys/dev/sdmmc/sdhc.c

2537

HWRITE4(hp, reg, val);

sys/dev/sdmmc/sdhc.c

932

uint32_t reg;

sys/dev/sdmmc/sdhc.c

983

reg = HREAD1(hp, SDHC_POWER_CTL) & pcmask;

sys/dev/sdmmc/sdhc.c

984

HWRITE1(hp, SDHC_POWER_CTL, reg);

sys/dev/sdmmc/sdhc.c

986

reg |= (vdd << SDHC_VOLTAGE_SHIFT);

sys/dev/sdmmc/sdhc.c

987

HWRITE1(hp, SDHC_POWER_CTL, reg);

sys/dev/sdmmc/sdhc.c

989

reg |= SDHC_BUS_POWER;

sys/dev/sdmmc/sdhc.c

990

HWRITE1(hp, SDHC_POWER_CTL, reg);

sys/dev/sdmmc/sdmmc_cis.c

106

int tpllen, uint32_t reg)

sys/dev/sdmmc/sdmmc_cis.c

118

if (sdmmc_io_read_1(sf0, reg++) != 6) {

sys/dev/sdmmc/sdmmc_cis.c

124

cis->lan_nid[i] = sdmmc_io_read_1(sf0, reg++);

sys/dev/sdmmc/sdmmc_cis.c

135

int tpllen, uint32_t reg)

sys/dev/sdmmc/sdmmc_cis.c

158

max_blk_size = sdmmc_io_read_1(sf0, reg + 11);

sys/dev/sdmmc/sdmmc_cis.c

159

max_blk_size |= sdmmc_io_read_1(sf0, reg + 12) << 8;

sys/dev/sdmmc/sdmmc_cis.c

166

uint32_t reg)

sys/dev/sdmmc/sdmmc_cis.c

177

cis->cis1_major = sdmmc_io_read_1(sf0, reg++);

sys/dev/sdmmc/sdmmc_cis.c

178

cis->cis1_minor = sdmmc_io_read_1(sf0, reg++);

sys/dev/sdmmc/sdmmc_cis.c

181

ch = sdmmc_io_read_1(sf0, reg + i);

sys/dev/sdmmc/sdmmc_cis.c

200

uint32_t reg;

sys/dev/sdmmc/sdmmc_cis.c

205

reg = sdmmc_cisptr(sf);

sys/dev/sdmmc/sdmmc_cis.c

206

if (reg < SD_IO_CIS_START ||

sys/dev/sdmmc/sdmmc_cis.c

207

reg >= (SD_IO_CIS_START + SD_IO_CIS_SIZE - 16)) {

sys/dev/sdmmc/sdmmc_cis.c

208

aprint_error_dev(dev, "bad CIS ptr %#x\n", reg);

sys/dev/sdmmc/sdmmc_cis.c

213

tplcode = sdmmc_io_read_1(sf0, reg++);

sys/dev/sdmmc/sdmmc_cis.c

220

tpllen = sdmmc_io_read_1(sf0, reg++);

sys/dev/sdmmc/sdmmc_cis.c

225

reg, tplcode, tpllen);

sys/dev/sdmmc/sdmmc_cis.c

241

sdmmc_io_read_1(sf0, reg + i)));

sys/dev/sdmmc/sdmmc_cis.c

252

switch (sdmmc_io_read_1(sf0, reg++)) {

sys/dev/sdmmc/sdmmc_cis.c

254

decode_funce_common(sf, cis, tpllen, reg);

sys/dev/sdmmc/sdmmc_cis.c

257

decode_funce_lan_nid(sf, cis, tpllen, reg);

sys/dev/sdmmc/sdmmc_cis.c

260

decode_funce_function(sf, cis, tpllen, reg);

sys/dev/sdmmc/sdmmc_cis.c

262

reg += (tpllen - 1);

sys/dev/sdmmc/sdmmc_cis.c

269

reg += tpllen;

sys/dev/sdmmc/sdmmc_cis.c

272

cis->function = sdmmc_io_read_1(sf0, reg);

sys/dev/sdmmc/sdmmc_cis.c

274

reg += tpllen;

sys/dev/sdmmc/sdmmc_cis.c

281

reg += tpllen;

sys/dev/sdmmc/sdmmc_cis.c

284

cis->manufacturer = sdmmc_io_read_1(sf0, reg++);

sys/dev/sdmmc/sdmmc_cis.c

285

cis->manufacturer |= sdmmc_io_read_1(sf0, reg++) << 8;

sys/dev/sdmmc/sdmmc_cis.c

286

cis->product = sdmmc_io_read_1(sf0, reg++);

sys/dev/sdmmc/sdmmc_cis.c

287

cis->product |= sdmmc_io_read_1(sf0, reg++) << 8;

sys/dev/sdmmc/sdmmc_cis.c

292

decode_vers_1(sf, cis, tpllen, reg);

sys/dev/sdmmc/sdmmc_cis.c

293

reg += tpllen;

sys/dev/sdmmc/sdmmc_cis.c

298

reg += tpllen;

sys/dev/sdmmc/sdmmc_cis.c

310

reg += tpllen;

sys/dev/sdmmc/sdmmc_cis.c

74

int tpllen, uint32_t reg)

sys/dev/sdmmc/sdmmc_cis.c

93

fn0_blk_size = sdmmc_io_read_1(sf0, reg++);

sys/dev/sdmmc/sdmmc_cis.c

94

fn0_blk_size |= sdmmc_io_read_1(sf0, reg++) << 8;

sys/dev/sdmmc/sdmmc_cis.c

95

max_tran_speed = sdmmc_io_read_1(sf0, reg++);

sys/dev/sdmmc/sdmmc_io.c

193

uint8_t reg;

sys/dev/sdmmc/sdmmc_io.c

200

reg = sdmmc_io_read_1(sf, SD_IO_CCCR_CAPABILITY);

sys/dev/sdmmc/sdmmc_io.c

201

if (!(reg & CCCR_CAPS_LSC) || (reg & CCCR_CAPS_4BLS)) {

sys/dev/sdmmc/sdmmc_io.c

226

reg = sdmmc_io_read_1(sf, SD_IO_CCCR_HIGH_SPEED);

sys/dev/sdmmc/sdmmc_io.c

227

if (reg & CCCR_HIGH_SPEED_SHS) {

sys/dev/sdmmc/sdmmc_io.c

228

reg |= CCCR_HIGH_SPEED_EHS;

sys/dev/sdmmc/sdmmc_io.c

229

sdmmc_io_write_1(sf, SD_IO_CCCR_HIGH_SPEED, reg);

sys/dev/sdmmc/sdmmc_io.c

253

reg = sdmmc_io_read_1(sf0, SD_IO_FBR(sf->number) + 0x000);

sys/dev/sdmmc/sdmmc_io.c

254

sf->interface = FBR_STD_FUNC_IF_CODE(reg);

sys/dev/sdmmc/sdmmc_io.c

287

uint8_t reg;

sys/dev/sdmmc/sdmmc_io.c

293

reg = sdmmc_io_read_1(sf0, SD_IO_CCCR_FN_IOREADY);

sys/dev/sdmmc/sdmmc_io.c

295

return (reg & (1 << sf->number)) != 0;

sys/dev/sdmmc/sdmmc_io.c

303

uint8_t reg;

sys/dev/sdmmc/sdmmc_io.c

310

reg = sdmmc_io_read_1(sf0, SD_IO_CCCR_FN_ENABLE);

sys/dev/sdmmc/sdmmc_io.c

311

SET(reg, (1U << sf->number));

sys/dev/sdmmc/sdmmc_io.c

312

sdmmc_io_write_1(sf0, SD_IO_CCCR_FN_ENABLE, reg);

sys/dev/sdmmc/sdmmc_io.c

330

uint8_t reg;

sys/dev/sdmmc/sdmmc_io.c

336

reg = sdmmc_io_read_1(sf0, SD_IO_CCCR_FN_ENABLE);

sys/dev/sdmmc/sdmmc_io.c

337

CLR(reg, (1U << sf->number));

sys/dev/sdmmc/sdmmc_io.c

338

sdmmc_io_write_1(sf0, SD_IO_CCCR_FN_ENABLE, reg);

sys/dev/sdmmc/sdmmc_io.c

344

int reg, u_char *datap, int arg, bool toutok)

sys/dev/sdmmc/sdmmc_io.c

358

arg |= (reg & SD_ARG_CMD52_REG_MASK) <<

sys/dev/sdmmc/sdmmc_io.c

377

error, reg, datap,

sys/dev/sdmmc/sdmmc_io.c

393

int reg, u_char *datap, int len, int arg)

sys/dev/sdmmc/sdmmc_io.c

413

arg |= (reg & SD_ARG_CMD53_REG_MASK) <<

sys/dev/sdmmc/sdmmc_io.c

472

error, reg, datap, datalen,

sys/dev/sdmmc/sdmmc_io.c

480

sdmmc_io_read_1(struct sdmmc_function *sf, int reg)

sys/dev/sdmmc/sdmmc_io.c

486

(void)sdmmc_io_rw_direct(sf->sc, sf, reg, (u_char *)&data,

sys/dev/sdmmc/sdmmc_io.c

492

sdmmc_io_write_1(struct sdmmc_function *sf, int reg, uint8_t data)

sys/dev/sdmmc/sdmmc_io.c

497

(void)sdmmc_io_rw_direct(sf->sc, sf, reg, (u_char *)&data,

sys/dev/sdmmc/sdmmc_io.c

502

sdmmc_io_read_2(struct sdmmc_function *sf, int reg)

sys/dev/sdmmc/sdmmc_io.c

508

(void)sdmmc_io_rw_extended(sf->sc, sf, reg, (u_char *)&data, 2,

sys/dev/sdmmc/sdmmc_io.c

514

sdmmc_io_write_2(struct sdmmc_function *sf, int reg, uint16_t data)

sys/dev/sdmmc/sdmmc_io.c

519

(void)sdmmc_io_rw_extended(sf->sc, sf, reg, (u_char *)&data, 2,

sys/dev/sdmmc/sdmmc_io.c

524

sdmmc_io_read_4(struct sdmmc_function *sf, int reg)

sys/dev/sdmmc/sdmmc_io.c

530

(void)sdmmc_io_rw_extended(sf->sc, sf, reg, (u_char *)&data, 4,

sys/dev/sdmmc/sdmmc_io.c

536

sdmmc_io_write_4(struct sdmmc_function *sf, int reg, uint32_t data)

sys/dev/sdmmc/sdmmc_io.c

541

(void)sdmmc_io_rw_extended(sf->sc, sf, reg, (u_char *)&data, 4,

sys/dev/sdmmc/sdmmc_io.c

547

sdmmc_io_read_multi_1(struct sdmmc_function *sf, int reg, u_char *data,

sys/dev/sdmmc/sdmmc_io.c

557

error = sdmmc_io_rw_extended(sf->sc, sf, reg, data,

sys/dev/sdmmc/sdmmc_io.c

566

error = sdmmc_io_rw_extended(sf->sc, sf, reg, data, datalen,

sys/dev/sdmmc/sdmmc_io.c

573

sdmmc_io_write_multi_1(struct sdmmc_function *sf, int reg, u_char *data,

sys/dev/sdmmc/sdmmc_io.c

583

error = sdmmc_io_rw_extended(sf->sc, sf, reg, data,

sys/dev/sdmmc/sdmmc_io.c

592

error = sdmmc_io_rw_extended(sf->sc, sf, reg, data, datalen,

sys/dev/sdmmc/sdmmc_io.c

600

sdmmc_io_read_region_1(struct sdmmc_function *sf, int reg, u_char *data,

sys/dev/sdmmc/sdmmc_io.c

610

error = sdmmc_io_rw_extended(sf->sc, sf, reg, data,

sys/dev/sdmmc/sdmmc_io.c

615

reg += blocks * sf->blklen;

sys/dev/sdmmc/sdmmc_io.c

621

error = sdmmc_io_rw_extended(sf->sc, sf, reg, data, datalen,

sys/dev/sdmmc/sdmmc_io.c

628

sdmmc_io_write_region_1(struct sdmmc_function *sf, int reg, u_char *data,

sys/dev/sdmmc/sdmmc_io.c

638

error = sdmmc_io_rw_extended(sf->sc, sf, reg, data,

sys/dev/sdmmc/sdmmc_io.c

643

reg += blocks * sf->blklen;

sys/dev/sdmmc/sdmmc_io.c

649

error = sdmmc_io_rw_extended(sf->sc, sf, reg, data, datalen,

sys/dev/sdmmc/sdmmc_io.c

658

int reg, u_char *datap)

sys/dev/sdmmc/sdmmc_io.c

663

return sdmmc_io_rw_direct(sc, sf, reg, datap,

sys/dev/sdmmc/sdmmc_io.c

744

uint8_t reg;

sys/dev/sdmmc/sdmmc_io.c

747

reg = sdmmc_io_read_1(sf0, SD_IO_CCCR_FN_INTEN);

sys/dev/sdmmc/sdmmc_io.c

748

reg |= 1 << sf->number;

sys/dev/sdmmc/sdmmc_io.c

749

sdmmc_io_write_1(sf0, SD_IO_CCCR_FN_INTEN, reg);

sys/dev/sdmmc/sdmmc_io.c

758

uint8_t reg;

sys/dev/sdmmc/sdmmc_io.c

761

reg = sdmmc_io_read_1(sf0, SD_IO_CCCR_FN_INTEN);

sys/dev/sdmmc/sdmmc_io.c

762

reg &= ~(1 << sf->number);

sys/dev/sdmmc/sdmmc_io.c

763

sdmmc_io_write_1(sf0, SD_IO_CCCR_FN_INTEN, reg);

sys/dev/sdmmc/sdmmc_mem.c

1526

uint32_t reg;

sys/dev/sdmmc/sdmmc_mem.c

1531

reg = SD_EXTENSION_INFO_REG(ginfo, index, 0);

sys/dev/sdmmc/sdmmc_mem.c

1534

SDMMCDEVNAME(sc), sfc, reg));

sys/dev/sdmmc/sdmmc_mem.c

1540

SD_EXTENSION_INFO_REG_FNO(reg);

sys/dev/sdmmc/sdmmc_mem.c

1542

SD_EXTENSION_INFO_REG_START_ADDR(reg);

sys/dev/spi/bmx280thpspi.c

69

bmx280thpspi_read_reg_direct(spi_handle_t sh, uint8_t reg, uint8_t *buf,

sys/dev/spi/bmx280thpspi.c

73

uint8_t rreg = reg | 0x80;

sys/dev/spi/bmx280thpspi.c

86

bmx280thpspi_read_reg(struct bmx280_sc *sc, uint8_t reg, uint8_t *buf,

sys/dev/spi/bmx280thpspi.c

91

return bmx280thpspi_read_reg_direct(ssc->sc_sh, reg, buf, rlen);

sys/dev/spi/mcp23xxxgpio_spi.c

139

uint8_t reg, uint8_t *valp)

sys/dev/spi/mcp23xxxgpio_spi.c

147

buf[1] = reg;

sys/dev/spi/mcp23xxxgpio_spi.c

154

uint8_t reg, uint8_t val)

sys/dev/spi/mcp23xxxgpio_spi.c

162

buf[1] = reg;

sys/dev/spi/mcp48x1.c

214

uint16_t reg, regbe;

sys/dev/spi/mcp48x1.c

216

reg = 0;

sys/dev/spi/mcp48x1.c

219

reg |= MCP48X1DAC_GAIN;

sys/dev/spi/mcp48x1.c

222

reg |= MCP48X1DAC_SHDN;

sys/dev/spi/mcp48x1.c

224

reg |= sc->sc_dac_data << sc->sc_dm->shift;

sys/dev/spi/mcp48x1.c

226

regbe = htobe16(reg);

sys/dev/spi/oj6sh.c

270

oj6sh_read(spi_handle_t spi, uint8_t reg)

sys/dev/spi/oj6sh.c

274

spi_send_recv(spi, 1, &reg, 1, &ret);

sys/dev/spi/oj6sh.c

275

DPRINTF(4,("%s: 0x%02x = 0x%02x\n", __func__, reg, ret));

sys/dev/spi/oj6sh.c

280

oj6sh_write(spi_handle_t spi, uint8_t reg, uint8_t val)

sys/dev/spi/oj6sh.c

282

uint8_t tmp[2] = {reg | 0x80, val};

sys/dev/spi/oj6sh.c

285

DPRINTF(4,("%s: 0x%02x = 0x%02x\n", __func__, reg, val));

sys/dev/spi/sc16is7xxspi.c

108

reg, channel, buf, blen);

sys/dev/spi/sc16is7xxspi.c

114

sc16is7xxspi_write_register(struct sc16is7xx_sc *sc, uint8_t reg, int channel,

sys/dev/spi/sc16is7xxspi.c

123

reg, channel, buf, blen);

sys/dev/spi/sc16is7xxspi.c

142

sc16is7xx_spi_com_read_1(struct com_regs *regs, u_int reg)

sys/dev/spi/sc16is7xxspi.c

153

reg, regs->cr_channel, &buf, 1);

sys/dev/spi/sc16is7xxspi.c

173

sc16is7xx_spi_com_write_1(struct com_regs *regs, u_int reg, uint8_t val)

sys/dev/spi/sc16is7xxspi.c

183

reg, regs->cr_channel, &val, 1);

sys/dev/spi/sc16is7xxspi.c

198

sc16is7xx_spi_com_write_multi_1(struct com_regs *regs, u_int reg, const uint8_t *datap,

sys/dev/spi/sc16is7xxspi.c

209

reg, regs->cr_channel, __UNCONST(datap), count);

sys/dev/spi/sc16is7xxspi.c

64

uint8_t reg, int channel, uint8_t *buf, size_t blen)

sys/dev/spi/sc16is7xxspi.c

69

xreg = ((reg << 3) | (channel << 1)) | 0x80;

sys/dev/spi/sc16is7xxspi.c

77

uint8_t reg, int channel, uint8_t *buf, size_t blen)

sys/dev/spi/sc16is7xxspi.c

83

xreg = (reg << 3) | (channel << 1);

sys/dev/spi/sc16is7xxspi.c

99

sc16is7xxspi_read_register(struct sc16is7xx_sc *sc, uint8_t reg, int channel,

sys/dev/spi/scmdspi.c

115

scmdspi_read_reg(struct scmd_sc *sc, uint8_t reg, uint8_t *buf)

sys/dev/spi/scmdspi.c

117

return scmdspi_read_reg_direct(sc->sc_sh, reg, buf);

sys/dev/spi/scmdspi.c

128

scmdspi_write_reg_direct(spi_handle_t sh, uint8_t reg, uint8_t buf)

sys/dev/spi/scmdspi.c

130

uint8_t rreg = reg & 0x7F;

sys/dev/spi/scmdspi.c

147

scmdspi_write_reg(struct scmd_sc *sc, uint8_t reg, uint8_t buf)

sys/dev/spi/scmdspi.c

149

return scmdspi_write_reg_direct(sc->sc_sh, reg, buf);

sys/dev/spi/scmdspi.c

86

scmdspi_read_reg_direct(spi_handle_t sh, uint8_t reg, uint8_t *buf)

sys/dev/spi/scmdspi.c

90

uint8_t rreg = reg | 0x80;

sys/dev/spi/tmp121.c

146

uint16_t reg;

sys/dev/spi/tmp121.c

150

if (spi_recv(sc->sc_sh, 2, (uint8_t *)&reg) != 0) {

sys/dev/spi/tmp121.c

155

sreg = (int16_t)be16toh(reg);

sys/dev/sysmon/sysmon_envsys_events.c

510

const struct ev_reg_t *reg;

sys/dev/sysmon/sysmon_envsys_events.c

534

for (reg = reg_events; reg->name != NULL; reg++) {

sys/dev/sysmon/sysmon_envsys_events.c

535

if (sed_t->sed_edata->flags & reg->crittype) {

sys/dev/sysmon/sysmon_envsys_events.c

541

reg->powertype,

sys/dev/sysmon/sysmon_envsys_events.c

547

sed_t->sed_edata->desc, reg->name);

sys/dev/sysmon/sysmon_envsys_events.c

550

(void)strlcat(str, reg->name, sizeof(str));

sys/dev/tc/asc_tc.c

301

asc_read_reg(struct ncr53c9x_softc *sc, int reg)

sys/dev/tc/asc_tc.c

306

reg * sizeof(uint32_t)) & 0xff;

sys/dev/tc/asc_tc.c

310

asc_write_reg(struct ncr53c9x_softc *sc, int reg, uint8_t val)

sys/dev/tc/asc_tc.c

315

reg * sizeof(uint32_t), val);

sys/dev/tc/asc_tcds.c

458

asc_read_reg(struct ncr53c9x_softc *sc, int reg)

sys/dev/tc/asc_tcds.c

464

reg * sizeof(uint32_t));

sys/dev/tc/asc_tcds.c

470

asc_write_reg(struct ncr53c9x_softc *sc, int reg, u_char val)

sys/dev/tc/asc_tcds.c

475

reg * sizeof(uint32_t), val);

sys/dev/tc/bba.c

616

bba_codec_dwrite(struct am7930_softc *amsc, int reg, uint8_t val)

sys/dev/tc/bba.c

621

DPRINTF(("bba_codec_dwrite(): sc=%p, reg=%d, val=%d\n", sc, reg, val));

sys/dev/tc/bba.c

625

reg << 2, val << 8);

sys/dev/tc/bba.c

628

reg << 6, val);

sys/dev/tc/bba.c

634

bba_codec_dread(struct am7930_softc *amsc, int reg)

sys/dev/tc/bba.c

639

DPRINTF(("bba_codec_dread(): sc=%p, reg=%d\n", sc, reg));

sys/dev/tc/bba.c

643

reg << 2) >> 8) & 0xff);

sys/dev/tc/bba.c

646

reg << 6) & 0xff);

sys/dev/tc/zs_ioasic.c

544

zs_read_reg(struct zs_chanstate *cs, u_int reg)

sys/dev/tc/zs_ioasic.c

549

zc->zc_csr = reg << 8;

sys/dev/tc/zs_ioasic.c

559

zs_write_reg(struct zs_chanstate *cs, u_int reg, u_int val)

sys/dev/tc/zs_ioasic.c

563

zc->zc_csr = reg << 8;

sys/dev/usb/auvitek.c

333

auvitek_read_1(struct auvitek_softc *sc, uint16_t reg)

sys/dev/usb/auvitek.c

343

USETW(req.wIndex, reg);

sys/dev/usb/auvitek.c

359

auvitek_write_1(struct auvitek_softc *sc, uint16_t reg, uint8_t data)

sys/dev/usb/auvitek.c

368

USETW(req.wIndex, reg);

sys/dev/usb/emdtv.c

389

uint16_t gpio_value, reg;

sys/dev/usb/emdtv.c

429

reg = gpio_value & 0x10 ? 0x04 : 0x08;

sys/dev/usb/emdtv.c

430

gpio = emdtv_read_1(sc, UR_GET_STATUS, reg);

sys/dev/usb/emdtv.c

439

emdtv_write_1(sc, UR_GET_STATUS, reg, gpio);

sys/dev/usb/emdtv.c

444

emdtv_write_1(sc, UR_GET_STATUS, reg, gpio);

sys/dev/usb/emdtv.c

449

emdtv_write_1(sc, UR_GET_STATUS, reg, gpio);

sys/dev/usb/emdtv_board.h

51

#define EMDTV_GPIO_BIT_VAL(reg, val, reset) \

sys/dev/usb/emdtv_board.h

52

((reg) | 0x80 | (reset ? (1 << 6) : 0) | (val << 5))

sys/dev/usb/if_athn_usb.c

1439

uint32_t reg, intr_mask;

sys/dev/usb/if_athn_usb.c

1505

reg = AR_READ(sc, AR_RX_FILTER);

sys/dev/usb/if_athn_usb.c

1506

reg = (reg & ~AR_RX_FILTER_BEACON) |

sys/dev/usb/if_athn_usb.c

1508

AR_WRITE(sc, AR_RX_FILTER, reg);

sys/dev/usb/if_aue.c

273

#define AUE_SETBIT(sc, reg, x) \

sys/dev/usb/if_aue.c

274

aue_csr_write_1(sc, reg, aue_csr_read_1(sc, reg) | (x))

sys/dev/usb/if_aue.c

276

#define AUE_CLRBIT(sc, reg, x) \

sys/dev/usb/if_aue.c

277

aue_csr_write_1(sc, reg, aue_csr_read_1(sc, reg) & ~(x))

sys/dev/usb/if_aue.c

280

aue_csr_read_1(struct aue_softc *sc, int reg)

sys/dev/usb/if_aue.c

293

USETW(req.wIndex, reg);

sys/dev/usb/if_aue.c

301

device_unit(un->un_dev), reg, err, 0);

sys/dev/usb/if_aue.c

309

aue_csr_read_2(struct aue_softc *sc, int reg)

sys/dev/usb/if_aue.c

322

USETW(req.wIndex, reg);

sys/dev/usb/if_aue.c

330

device_unit(un->un_dev), reg, err, 0);

sys/dev/usb/if_aue.c

338

aue_csr_write_1(struct aue_softc *sc, int reg, int aval)

sys/dev/usb/if_aue.c

352

USETW(req.wIndex, reg);

sys/dev/usb/if_aue.c

360

device_unit(un->un_dev), reg, err, 0);

sys/dev/usb/if_aue.c

368

aue_csr_write_2(struct aue_softc *sc, int reg, int aval)

sys/dev/usb/if_aue.c

382

USETW(req.wIndex, reg);

sys/dev/usb/if_aue.c

390

device_unit(un->un_dev), reg, err, 0);

sys/dev/usb/if_aue.c

447

aue_uno_mii_read_reg(struct usbnet *un, int phy, int reg, uint16_t *val)

sys/dev/usb/if_aue.c

475

aue_csr_write_1(sc, AUE_PHY_CTL, reg | AUE_PHYCTL_READ);

sys/dev/usb/if_aue.c

488

device_unit(un->un_dev), phy, reg, 0);

sys/dev/usb/if_aue.c

496

device_unit(un->un_dev), phy, reg, *val);

sys/dev/usb/if_aue.c

502

aue_uno_mii_write_reg(struct usbnet *un, int phy, int reg, uint16_t val)

sys/dev/usb/if_aue.c

509

device_unit(un->un_dev), phy, reg, val);

sys/dev/usb/if_aue.c

521

aue_csr_write_1(sc, AUE_PHY_CTL, reg | AUE_PHYCTL_WRITE);

sys/dev/usb/if_aue.c

532

device_unit(un->un_dev), phy, reg, val);

sys/dev/usb/if_axe.c

318

axe_uno_mii_read_reg(struct usbnet *un, int phy, int reg, uint16_t *val)

sys/dev/usb/if_axe.c

325

DPRINTFN(30, "phy %#jx reg %#jx\n", phy, reg, 0, 0);

sys/dev/usb/if_axe.c

334

err = axe_cmd(sc, AXE_CMD_MII_READ_REG, reg, phy, &data);

sys/dev/usb/if_axe.c

344

if (AXE_IS_772(un) && reg == MII_BMSR) {

sys/dev/usb/if_axe.c

354

DPRINTFN(30, "phy %#jx reg %#jx val %#jx", phy, reg, *val, 0);

sys/dev/usb/if_axe.c

360

axe_uno_mii_write_reg(struct usbnet *un, int phy, int reg, uint16_t val)

sys/dev/usb/if_axe.c

372

err = axe_cmd(sc, AXE_CMD_MII_WRITE_REG, reg, phy, &aval);

sys/dev/usb/if_axen.c

137

axen_uno_mii_read_reg(struct usbnet *un, int phy, int reg, uint16_t *val)

sys/dev/usb/if_axen.c

146

usbd_status err = axen_cmd(un, AXEN_CMD_MII_READ_REG, reg, phy, &data);

sys/dev/usb/if_axen.c

153

if (reg == MII_BMSR)

sys/dev/usb/if_axen.c

160

axen_uno_mii_write_reg(struct usbnet *un, int phy, int reg, uint16_t val)

sys/dev/usb/if_axen.c

167

usbd_status err = axen_cmd(un, AXEN_CMD_MII_WRITE_REG, reg, phy, &uval);

sys/dev/usb/if_cue.c

160

cue_csr_read_1(struct usbnet *un, int reg)

sys/dev/usb/if_cue.c

172

USETW(req.wIndex, reg);

sys/dev/usb/if_cue.c

179

device_xname(un->un_dev), reg, usbd_errstr(err)));

sys/dev/usb/if_cue.c

184

device_xname(un->un_dev), reg, val));

sys/dev/usb/if_cue.c

191

cue_csr_read_2(struct usbnet *un, int reg)

sys/dev/usb/if_cue.c

203

USETW(req.wIndex, reg);

sys/dev/usb/if_cue.c

209

device_xname(un->un_dev), reg, UGETW(val)));

sys/dev/usb/if_cue.c

213

device_xname(un->un_dev), reg, usbd_errstr(err)));

sys/dev/usb/if_cue.c

221

cue_csr_write_1(struct usbnet *un, int reg, int val)

sys/dev/usb/if_cue.c

230

device_xname(un->un_dev), reg, val));

sys/dev/usb/if_cue.c

235

USETW(req.wIndex, reg);

sys/dev/usb/if_cue.c

242

device_xname(un->un_dev), reg, usbd_errstr(err)));

sys/dev/usb/if_cue.c

247

device_xname(un->un_dev), reg, cue_csr_read_1(un, reg)));

sys/dev/usb/if_cue.c

254

cue_csr_write_2(struct usbnet *un, int reg, int aval)

sys/dev/usb/if_cue.c

265

device_xname(un->un_dev), reg, aval));

sys/dev/usb/if_cue.c

271

USETW(req.wIndex, reg);

sys/dev/usb/if_cue.c

278

device_xname(un->un_dev), reg, usbd_errstr(err)));

sys/dev/usb/if_mos.c

177

mos_reg_read_1(struct usbnet *un, int reg)

sys/dev/usb/if_mos.c

189

USETW(req.wIndex, reg);

sys/dev/usb/if_mos.c

195

aprint_error_dev(un->un_dev, "read reg %x\n", reg);

sys/dev/usb/if_mos.c

203

mos_reg_read_2(struct usbnet *un, int reg)

sys/dev/usb/if_mos.c

217

USETW(req.wIndex, reg);

sys/dev/usb/if_mos.c

223

aprint_error_dev(un->un_dev, "read reg2 %x\n", reg);

sys/dev/usb/if_mos.c

231

mos_reg_write_1(struct usbnet *un, int reg, int aval)

sys/dev/usb/if_mos.c

245

USETW(req.wIndex, reg);

sys/dev/usb/if_mos.c

252

reg, aval);

sys/dev/usb/if_mos.c

258

mos_reg_write_2(struct usbnet *un, int reg, int aval)

sys/dev/usb/if_mos.c

272

USETW(req.wIndex, reg);

sys/dev/usb/if_mos.c

279

reg, aval);

sys/dev/usb/if_mos.c

356

mos_uno_mii_read_reg(struct usbnet *un, int phy, int reg, uint16_t *val)

sys/dev/usb/if_mos.c

363

mos_reg_write_1(un, MOS_PHY_STS, (reg & MOS_PHYSTS_PHYREG) |

sys/dev/usb/if_mos.c

384

device_xname(un->un_dev), __func__, phy, reg, res));

sys/dev/usb/if_mos.c

390

mos_uno_mii_write_reg(struct usbnet *un, int phy, int reg, uint16_t val)

sys/dev/usb/if_mos.c

395

device_xname(un->un_dev), __func__, phy, reg, val));

sys/dev/usb/if_mos.c

400

mos_reg_write_1(un, MOS_PHY_STS, (reg & MOS_PHYSTS_PHYREG) |

sys/dev/usb/if_mue.c

1005

uint32_t reg, rxfilt, h, hireg, loreg;

sys/dev/usb/if_mue.c

1015

reg = (un->un_flags & LAN7500) ? MUE_7500_RFE_CTL : MUE_7800_RFE_CTL;

sys/dev/usb/if_mue.c

1016

rxfilt = mue_csr_read(un, reg);

sys/dev/usb/if_mue.c

1082

mue_csr_write(un, reg, rxfilt);

sys/dev/usb/if_mue.c

1089

uint32_t reg, val;

sys/dev/usb/if_mue.c

1093

reg = (un->un_flags & LAN7500) ? MUE_7500_RFE_CTL : MUE_7800_RFE_CTL;

sys/dev/usb/if_mue.c

1094

val = mue_csr_read(un, reg);

sys/dev/usb/if_mue.c

1116

mue_csr_write(un, reg, val);

sys/dev/usb/if_mue.c

123

#define MUE_SETBIT(un, reg, x) \

sys/dev/usb/if_mue.c

124

mue_csr_write(un, reg, mue_csr_read(un, reg) | (x))

sys/dev/usb/if_mue.c

126

#define MUE_CLRBIT(un, reg, x) \

sys/dev/usb/if_mue.c

127

mue_csr_write(un, reg, mue_csr_read(un, reg) & ~(x))

sys/dev/usb/if_mue.c

129

#define MUE_WAIT_SET(un, reg, set, fail) \

sys/dev/usb/if_mue.c

130

mue_wait_for_bits(un, reg, set, ~0, fail)

sys/dev/usb/if_mue.c

132

#define MUE_WAIT_CLR(un, reg, clear, fail) \

sys/dev/usb/if_mue.c

133

mue_wait_for_bits(un, reg, 0, clear, fail)

sys/dev/usb/if_mue.c

145

mue_csr_read(struct usbnet *un, uint32_t reg)

sys/dev/usb/if_mue.c

158

USETW(req.wIndex, reg);

sys/dev/usb/if_mue.c

163

MUE_PRINTF(un, "reg = %#x: %s\n", reg, usbd_errstr(err));

sys/dev/usb/if_mue.c

171

mue_csr_write(struct usbnet *un, uint32_t reg, uint32_t aval)

sys/dev/usb/if_mue.c

184

USETW(req.wIndex, reg);

sys/dev/usb/if_mue.c

189

MUE_PRINTF(un, "reg = %#x: %s\n", reg, usbd_errstr(err));

sys/dev/usb/if_mue.c

197

mue_wait_for_bits(struct usbnet *un, uint32_t reg,

sys/dev/usb/if_mue.c

206

val = mue_csr_read(un, reg);

sys/dev/usb/if_mue.c

218

mue_uno_mii_read_reg(struct usbnet *un, int phy, int reg, uint16_t *val)

sys/dev/usb/if_mue.c

234

MUE_MII_ACCESS_BUSY | MUE_MII_ACCESS_REGADDR(reg) |

sys/dev/usb/if_mue.c

250

mue_uno_mii_write_reg(struct usbnet *un, int phy, int reg, uint16_t val)

sys/dev/usb/if_mue.c

263

MUE_MII_ACCESS_BUSY | MUE_MII_ACCESS_REGADDR(reg) |

sys/dev/usb/if_otus.c

1459

otus_write(struct otus_softc *sc, uint32_t reg, uint32_t val)

sys/dev/usb/if_otus.c

1462

DPRINTFN(DBG_FN | DBG_REG, sc, "reg=%#x, val=%#x\n", reg, val);

sys/dev/usb/if_otus.c

1467

sc->sc_write_buf[sc->sc_write_idx].reg = htole32(reg);

sys/dev/usb/if_otus.c

1542

uint32_t regs[8], reg;

sys/dev/usb/if_otus.c

1552

reg = AR_EEPROM_OFFSET;

sys/dev/usb/if_otus.c

1554

for (j = 0; j < 8; j++, reg += 4)

sys/dev/usb/if_otus.c

1555

regs[j] = htole32(reg);

sys/dev/usb/if_otus.c

2568

otus_phy_get_def(struct otus_softc *sc, uint32_t reg)

sys/dev/usb/if_otus.c

2575

if (AR_PHY(ar5416_phy_regs[i]) == reg)

sys/dev/usb/if_otusreg.h

202

#define AR_PHY(reg) (AR_PHY_BASE + (reg) * 4)

sys/dev/usb/if_otusvar.h

213

uint32_t reg;

sys/dev/usb/if_rum.c

1413

rum_read(struct rum_softc *sc, uint16_t reg)

sys/dev/usb/if_rum.c

1417

rum_read_multi(sc, reg, &val, sizeof(val));

sys/dev/usb/if_rum.c

1423

rum_read_multi(struct rum_softc *sc, uint16_t reg, void *buf, int len)

sys/dev/usb/if_rum.c

1431

USETW(req.wIndex, reg);

sys/dev/usb/if_rum.c

1443

rum_write(struct rum_softc *sc, uint16_t reg, uint32_t val)

sys/dev/usb/if_rum.c

1447

rum_write_multi(sc, reg, &tmp, sizeof(tmp));

sys/dev/usb/if_rum.c

1451

rum_write_multi(struct rum_softc *sc, uint16_t reg, void *buf, size_t len)

sys/dev/usb/if_rum.c

1463

USETW(req.wIndex, reg + offset);

sys/dev/usb/if_rum.c

1475

rum_bbp_write(struct rum_softc *sc, uint8_t reg, uint8_t val)

sys/dev/usb/if_rum.c

1489

tmp = RT2573_BBP_BUSY | (reg & 0x7f) << 8 | val;

sys/dev/usb/if_rum.c

1494

rum_bbp_read(struct rum_softc *sc, uint8_t reg)

sys/dev/usb/if_rum.c

1508

val = RT2573_BBP_BUSY | RT2573_BBP_READ | reg << 8;

sys/dev/usb/if_rum.c

1523

rum_rf_write(struct rum_softc *sc, uint8_t reg, uint32_t val)

sys/dev/usb/if_rum.c

1538

(reg & 3);

sys/dev/usb/if_rum.c

1542

sc->rf_regs[reg] = val;

sys/dev/usb/if_rum.c

1544

DPRINTFN(15, ("RF R[%u] <- 0x%05x\n", reg & 3, val & 0xfffff));

sys/dev/usb/if_rum.c

1908

if (sc->bbp_prom[i].reg == 0 || sc->bbp_prom[i].reg == 0xff)

sys/dev/usb/if_rum.c

1910

DPRINTF(("BBP R%d=%02x\n", sc->bbp_prom[i].reg,

sys/dev/usb/if_rum.c

1937

rum_bbp_write(sc, rum_def_bbp[i].reg, rum_def_bbp[i].val);

sys/dev/usb/if_rum.c

1941

if (sc->bbp_prom[i].reg == 0 || sc->bbp_prom[i].reg == 0xff)

sys/dev/usb/if_rum.c

1943

rum_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val);

sys/dev/usb/if_rum.c

1967

rum_write(sc, rum_def_mac[i].reg, rum_def_mac[i].val);

sys/dev/usb/if_rum.c

211

uint32_t reg;

sys/dev/usb/if_rum.c

2150

uint16_t reg = RT2573_MCU_CODE_BASE;

sys/dev/usb/if_rum.c

2154

for (; size >= 4; reg += 4, ucode += 4, size -= 4)

sys/dev/usb/if_rum.c

2155

rum_write(sc, reg, UGETDW(ucode));

sys/dev/usb/if_rum.c

218

uint8_t reg;

sys/dev/usb/if_rumvar.h

127

uint8_t reg;

sys/dev/usb/if_run.c

1020

run_read(struct run_softc *sc, uint16_t reg, uint32_t *val)

sys/dev/usb/if_run.c

1025

error = run_read_region_1(sc, reg, (uint8_t *)&tmp, sizeof(tmp));

sys/dev/usb/if_run.c

1034

run_read_region_1(struct run_softc *sc, uint16_t reg, uint8_t *buf, int len)

sys/dev/usb/if_run.c

1041

USETW(req.wIndex, reg);

sys/dev/usb/if_run.c

1047

run_write_2(struct run_softc *sc, uint16_t reg, uint16_t val)

sys/dev/usb/if_run.c

1054

USETW(req.wIndex, reg);

sys/dev/usb/if_run.c

1060

run_write(struct run_softc *sc, uint16_t reg, uint32_t val)

sys/dev/usb/if_run.c

1063

return run_write_region_1(sc, reg, (uint8_t *)&tmp, sizeof(tmp));

sys/dev/usb/if_run.c

1067

run_write_region_1(struct run_softc *sc, uint16_t reg, const uint8_t *buf,

sys/dev/usb/if_run.c

1084

USETW(req.wIndex, reg);

sys/dev/usb/if_run.c

1090

reg += delta;

sys/dev/usb/if_run.c

1102

error = run_write_2(sc, reg + i, buf[i] | buf[i + 1] << 8);

sys/dev/usb/if_run.c

1108

run_set_region_4(struct run_softc *sc, uint16_t reg, uint32_t val, int count)

sys/dev/usb/if_run.c

1120

error = run_write_region_1(sc, reg, (uint8_t *)tmp,

sys/dev/usb/if_run.c

1124

reg += delta * sizeof(uint32_t);

sys/dev/usb/if_run.c

1128

for (; count > 0 && error == 0; count--, reg += 4)

sys/dev/usb/if_run.c

1129

error = run_write(sc, reg, val);

sys/dev/usb/if_run.c

1138

uint16_t reg;

sys/dev/usb/if_run.c

1171

reg = RT3070_EFUSE_DATA3 - (addr & 0xc);

sys/dev/usb/if_run.c

1172

if ((error = run_read(sc, reg, &tmp)) != 0)

sys/dev/usb/if_run.c

1217

run_rt2870_rf_write(struct run_softc *sc, uint8_t reg, uint32_t val)

sys/dev/usb/if_run.c

1233

(val & 0x3fffff) << 2 | (reg & 3);

sys/dev/usb/if_run.c

1238

run_rt3070_rf_read(struct run_softc *sc, uint8_t reg, uint8_t *val)

sys/dev/usb/if_run.c

1252

tmp = RT3070_RF_KICK | reg << 8;

sys/dev/usb/if_run.c

1270

run_rt3070_rf_write(struct run_softc *sc, uint8_t reg, uint8_t val)

sys/dev/usb/if_run.c

1284

tmp = RT3070_RF_WRITE | RT3070_RF_KICK | reg << 8 | val;

sys/dev/usb/if_run.c

1289

run_bbp_read(struct run_softc *sc, uint8_t reg, uint8_t *val)

sys/dev/usb/if_run.c

1303

tmp = RT2860_BBP_CSR_READ | RT2860_BBP_CSR_KICK | reg << 8;

sys/dev/usb/if_run.c

1321

run_bbp_write(struct run_softc *sc, uint8_t reg, uint8_t val)

sys/dev/usb/if_run.c

1335

tmp = RT2860_BBP_CSR_KICK | reg << 8 | val;

sys/dev/usb/if_run.c

1562

sc->bbp[i].reg = val >> 8;

sys/dev/usb/if_run.c

1563

DPRINTF(("BBP%d=0x%02x\n", sc->bbp[i].reg,

sys/dev/usb/if_run.c

1573

sc->rf[i].reg = val >> 8;

sys/dev/usb/if_run.c

1574

DPRINTF(("RF%d=0x%02x\n", sc->rf[i].reg,

sys/dev/usb/if_run.c

1679

uint32_t reg;

sys/dev/usb/if_run.c

1682

reg = val;

sys/dev/usb/if_run.c

1684

reg |= (uint32_t)val << 16;

sys/dev/usb/if_run.c

1686

sc->txpow20mhz[ridx] = reg;

sys/dev/usb/if_run.c

1687

sc->txpow40mhz_2ghz[ridx] = b4inc(reg, delta_2ghz);

sys/dev/usb/if_run.c

1688

sc->txpow40mhz_5ghz[ridx] = b4inc(reg, delta_5ghz);

sys/dev/usb/if_run.c

3513

uint8_t reg, rf, txpow_bound;

sys/dev/usb/if_run.c

3566

run_rt3070_rf_write(sc, rt5592_2ghz_def_rf[i].reg,

sys/dev/usb/if_run.c

3580

reg = 2;

sys/dev/usb/if_run.c

3585

run_rt3070_rf_write(sc, rt5592_5ghz_def_rf[i].reg,

sys/dev/usb/if_run.c

3591

run_rt3070_rf_write(sc, rt5592_chan_5ghz[i].reg,

sys/dev/usb/if_run.c

3600

reg = 3;

sys/dev/usb/if_run.c

3607

rf |= (reg << 6);

sys/dev/usb/if_run.c

3616

rf |= (reg << 6);

sys/dev/usb/if_run.c

4036

run_bbp_write(sc, rt5592_def_bbp[i].reg,

sys/dev/usb/if_run.c

4045

run_bbp_write(sc, rt5390_def_bbp[i].reg,

sys/dev/usb/if_run.c

4098

run_bbp_write(sc, rt2860_def_bbp[i].reg,

sys/dev/usb/if_run.c

4143

run_rt3070_rf_write(sc, rt3572_def_rf[i].reg,

sys/dev/usb/if_run.c

4148

run_rt3070_rf_write(sc, rt3070_def_rf[i].reg,

sys/dev/usb/if_run.c

4276

run_rt3070_rf_write(sc, rt3593_def_rf[i].reg,

sys/dev/usb/if_run.c

4333

run_rt3070_rf_write(sc, rt5592_def_rf[i].reg,

sys/dev/usb/if_run.c

4340

run_rt3070_rf_write(sc, rt5392_def_rf[i].reg,

sys/dev/usb/if_run.c

4353

run_rt3070_rf_write(sc, rt5390_def_rf[i].reg,

sys/dev/usb/if_run.c

448

uint32_t reg;

sys/dev/usb/if_run.c

4513

if (sc->rf[i].reg == 0 || sc->rf[i].reg == 0xff)

sys/dev/usb/if_run.c

4515

run_rt3070_rf_write(sc, sc->rf[i].reg, sc->rf[i].val);

sys/dev/usb/if_run.c

455

uint8_t reg;

sys/dev/usb/if_run.c

4785

run_write(sc, rt2870_def_mac[i].reg, rt2870_def_mac[i].val);

sys/dev/usb/if_run.c

4872

if (sc->bbp[i].reg == 0 || sc->bbp[i].reg == 0xff)

sys/dev/usb/if_run.c

4874

run_bbp_write(sc, sc->bbp[i].reg, sc->bbp[i].val);

sys/dev/usb/if_run.c

503

uint8_t reg;

sys/dev/usb/if_run.c

526

uint8_t reg;

sys/dev/usb/if_runvar.h

180

uint8_t reg;

sys/dev/usb/if_smsc.c

258

smsc_wait_for_bits(struct usbnet *un, uint32_t reg, uint32_t bits)

sys/dev/usb/if_smsc.c

266

if ((err = smsc_readreg(un, reg, &val)) != 0)

sys/dev/usb/if_smsc.c

277

smsc_uno_miibus_readreg(struct usbnet *un, int phy, int reg, uint16_t *val)

sys/dev/usb/if_smsc.c

294

addr = (phy << 11) | (reg << 6) | SMSC_MII_READ;

sys/dev/usb/if_smsc.c

314

smsc_uno_miibus_writereg(struct usbnet *un, int phy, int reg, uint16_t val)

sys/dev/usb/if_smsc.c

328

addr = (phy << 11) | (reg << 6) | SMSC_MII_WRITE;

sys/dev/usb/if_udav.c

100

#define UDAV_SETBIT(un, reg, x) \

sys/dev/usb/if_udav.c

101

udav_csr_write1(un, reg, udav_csr_read1(un, reg) | (x))

sys/dev/usb/if_udav.c

103

#define UDAV_CLRBIT(un, reg, x) \

sys/dev/usb/if_udav.c

104

udav_csr_write1(un, reg, udav_csr_read1(un, reg) & ~(x))

sys/dev/usb/if_udav.c

704

udav_uno_mii_read_reg(struct usbnet *un, int phy, int reg, uint16_t *val)

sys/dev/usb/if_udav.c

709

device_xname(un->un_dev), __func__, phy, reg));

sys/dev/usb/if_udav.c

730

UDAV_EPAR_PHY_ADR0 | (reg & UDAV_EPAR_EROA_MASK));

sys/dev/usb/if_udav.c

746

device_xname(un->un_dev), __func__, phy, reg, *val));

sys/dev/usb/if_udav.c

752

udav_uno_mii_write_reg(struct usbnet *un, int phy, int reg, uint16_t val)

sys/dev/usb/if_udav.c

757

device_xname(un->un_dev), __func__, phy, reg, val));

sys/dev/usb/if_udav.c

776

UDAV_EPAR_PHY_ADR0 | (reg & UDAV_EPAR_EROA_MASK));

sys/dev/usb/if_ural.c

1550

ural_read(struct ural_softc *sc, uint16_t reg)

sys/dev/usb/if_ural.c

1559

USETW(req.wIndex, reg);

sys/dev/usb/if_ural.c

1573

ural_read_multi(struct ural_softc *sc, uint16_t reg, void *buf, int len)

sys/dev/usb/if_ural.c

1581

USETW(req.wIndex, reg);

sys/dev/usb/if_ural.c

1592

ural_write(struct ural_softc *sc, uint16_t reg, uint16_t val)

sys/dev/usb/if_ural.c

1600

USETW(req.wIndex, reg);

sys/dev/usb/if_ural.c

1611

ural_write_multi(struct ural_softc *sc, uint16_t reg, void *buf, int len)

sys/dev/usb/if_ural.c

1619

USETW(req.wIndex, reg);

sys/dev/usb/if_ural.c

1630

ural_bbp_write(struct ural_softc *sc, uint8_t reg, uint8_t val)

sys/dev/usb/if_ural.c

1644

tmp = reg << 8 | val;

sys/dev/usb/if_ural.c

1649

ural_bbp_read(struct ural_softc *sc, uint8_t reg)

sys/dev/usb/if_ural.c

1654

val = RAL_BBP_WRITE | reg << 8;

sys/dev/usb/if_ural.c

1670

ural_rf_write(struct ural_softc *sc, uint8_t reg, uint32_t val)

sys/dev/usb/if_ural.c

1684

tmp = RAL_RF_BUSY | RAL_RF_20BIT | (val & 0xfffff) << 2 | (reg & 0x3);

sys/dev/usb/if_ural.c

1689

sc->rf_regs[reg] = val;

sys/dev/usb/if_ural.c

1691

DPRINTFN(15, ("RF R[%u] <- 0x%05x\n", reg & 0x3, val & 0xfffff));

sys/dev/usb/if_ural.c

180

uint16_t reg;

sys/dev/usb/if_ural.c

2014

ural_bbp_write(sc, ural_def_bbp[i].reg, ural_def_bbp[i].val);

sys/dev/usb/if_ural.c

2019

if (sc->bbp_prom[i].reg == 0xff)

sys/dev/usb/if_ural.c

2021

ural_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val);

sys/dev/usb/if_ural.c

206

uint8_t reg;

sys/dev/usb/if_ural.c

2094

ural_write(sc, ural_def_mac[i].reg, ural_def_mac[i].val);

sys/dev/usb/if_uralvar.h

125

uint8_t reg;

sys/dev/usb/if_ure.c

1075

uint32_t reg = 0;

sys/dev/usb/if_ure.c

1106

reg |= URE_TXPKT_IPV4_CS;

sys/dev/usb/if_ure.c

1108

reg |= URE_TXPKT_TCP_CS;

sys/dev/usb/if_ure.c

1110

reg |= URE_TXPKT_UDP_CS;

sys/dev/usb/if_ure.c

1111

reg |= l4off << URE_L4_OFFSET_SHIFT;

sys/dev/usb/if_ure.c

1120

reg |= URE_TXPKT_IPV6_CS;

sys/dev/usb/if_ure.c

1122

reg |= URE_TXPKT_TCP_CS;

sys/dev/usb/if_ure.c

1124

reg |= URE_TXPKT_UDP_CS;

sys/dev/usb/if_ure.c

1125

reg |= l4off << URE_L4_OFFSET_SHIFT;

sys/dev/usb/if_ure.c

1129

reg |= URE_TXPKT_IPV4_CS;

sys/dev/usb/if_ure.c

1131

return reg;

sys/dev/usb/if_ure.c

166

ure_read_1(struct usbnet *un, uint16_t reg, uint16_t index)

sys/dev/usb/if_ure.c

172

shift = (reg & 3) << 3;

sys/dev/usb/if_ure.c

173

reg &= ~3;

sys/dev/usb/if_ure.c

175

ure_read_mem(un, reg, index, &temp, 4);

sys/dev/usb/if_ure.c

183

ure_read_2(struct usbnet *un, uint16_t reg, uint16_t index)

sys/dev/usb/if_ure.c

189

shift = (reg & 2) << 3;

sys/dev/usb/if_ure.c

190

reg &= ~3;

sys/dev/usb/if_ure.c

192

ure_read_mem(un, reg, index, &temp, 4);

sys/dev/usb/if_ure.c

200

ure_read_4(struct usbnet *un, uint16_t reg, uint16_t index)

sys/dev/usb/if_ure.c

204

ure_read_mem(un, reg, index, &temp, 4);

sys/dev/usb/if_ure.c

209

ure_write_1(struct usbnet *un, uint16_t reg, uint16_t index, uint32_t val)

sys/dev/usb/if_ure.c

216

shift = reg & 3;

sys/dev/usb/if_ure.c

219

if (reg & 3) {

sys/dev/usb/if_ure.c

222

reg &= ~3;

sys/dev/usb/if_ure.c

226

return ure_write_mem(un, reg, index | byen, &temp, 4);

sys/dev/usb/if_ure.c

230

ure_write_2(struct usbnet *un, uint16_t reg, uint16_t index, uint32_t val)

sys/dev/usb/if_ure.c

237

shift = reg & 2;

sys/dev/usb/if_ure.c

240

if (reg & 2) {

sys/dev/usb/if_ure.c

243

reg &= ~3;

sys/dev/usb/if_ure.c

247

return ure_write_mem(un, reg, index | byen, &temp, 4);

sys/dev/usb/if_ure.c

251

ure_write_4(struct usbnet *un, uint16_t reg, uint16_t index, uint32_t val)

sys/dev/usb/if_ure.c

256

return ure_write_mem(un, reg, index | URE_BYTE_EN_DWORD, &temp, 4);

sys/dev/usb/if_ure.c

262

uint16_t reg;

sys/dev/usb/if_ure.c

265

reg = (addr & 0x0fff) | 0xb000;

sys/dev/usb/if_ure.c

267

return ure_read_2(un, reg, URE_MCU_TYPE_PLA);

sys/dev/usb/if_ure.c

273

uint16_t reg;

sys/dev/usb/if_ure.c

276

reg = (addr & 0x0fff) | 0xb000;

sys/dev/usb/if_ure.c

278

ure_write_2(un, reg, URE_MCU_TYPE_PLA, data);

sys/dev/usb/if_ure.c

282

ure_uno_mii_read_reg(struct usbnet *un, int phy, int reg, uint16_t *val)

sys/dev/usb/if_ure.c

291

if (reg == RTK_GMEDIASTAT) {

sys/dev/usb/if_ure.c

296

*val = ure_ocp_reg_read(un, URE_OCP_BASE_MII + reg * 2);

sys/dev/usb/if_ure.c

302

ure_uno_mii_write_reg(struct usbnet *un, int phy, int reg, uint16_t val)

sys/dev/usb/if_ure.c

308

ure_ocp_reg_write(un, URE_OCP_BASE_MII + reg * 2, val);

sys/dev/usb/if_url.c

114

#define URL_SETBIT(un, reg, x) \

sys/dev/usb/if_url.c

115

url_csr_write_1(un, reg, url_csr_read_1(un, reg) | (x))

sys/dev/usb/if_url.c

117

#define URL_SETBIT2(un, reg, x) \

sys/dev/usb/if_url.c

118

url_csr_write_2(un, reg, url_csr_read_2(un, reg) | (x))

sys/dev/usb/if_url.c

120

#define URL_CLRBIT(un, reg, x) \

sys/dev/usb/if_url.c

121

url_csr_write_1(un, reg, url_csr_read_1(un, reg) & ~(x))

sys/dev/usb/if_url.c

123

#define URL_CLRBIT2(un, reg, x) \

sys/dev/usb/if_url.c

124

url_csr_write_2(un, reg, url_csr_read_2(un, reg) & ~(x))

sys/dev/usb/if_url.c

301

url_csr_read_1(struct usbnet *un, int reg)

sys/dev/usb/if_url.c

308

return url_mem(un, URL_CMD_READMEM, reg, &val, 1) ? 0 : val;

sys/dev/usb/if_url.c

313

url_csr_read_2(struct usbnet *un, int reg)

sys/dev/usb/if_url.c

321

return url_mem(un, URL_CMD_READMEM, reg, &val, 2) ? 0 : UGETW(val);

sys/dev/usb/if_url.c

326

url_csr_write_1(struct usbnet *un, int reg, int aval)

sys/dev/usb/if_url.c

333

return url_mem(un, URL_CMD_WRITEMEM, reg, &val, 1) ? -1 : 0;

sys/dev/usb/if_url.c

338

url_csr_write_2(struct usbnet *un, int reg, int aval)

sys/dev/usb/if_url.c

347

return url_mem(un, URL_CMD_WRITEMEM, reg, &val, 2) ? -1 : 0;

sys/dev/usb/if_url.c

352

url_csr_write_4(struct usbnet *un, int reg, int aval)

sys/dev/usb/if_url.c

361

return url_mem(un, URL_CMD_WRITEMEM, reg, &val, 4) ? -1 : 0;

sys/dev/usb/if_url.c

548

url_uno_mii_read_reg(struct usbnet *un, int phy, int reg, uint16_t *val)

sys/dev/usb/if_url.c

554

device_xname(un->un_dev), __func__, phy, reg));

sys/dev/usb/if_url.c

564

switch (reg) {

sys/dev/usb/if_url.c

566

reg = URL_BMCR;

sys/dev/usb/if_url.c

569

reg = URL_BMSR;

sys/dev/usb/if_url.c

577

reg = URL_ANAR;

sys/dev/usb/if_url.c

580

reg = URL_ANLP;

sys/dev/usb/if_url.c

583

reg = URL_MSR;

sys/dev/usb/if_url.c

587

device_xname(un->un_dev), __func__, reg);

sys/dev/usb/if_url.c

591

if (reg == URL_MSR)

sys/dev/usb/if_url.c

592

data = url_csr_read_1(un, reg);

sys/dev/usb/if_url.c

594

data = url_csr_read_2(un, reg);

sys/dev/usb/if_url.c

599

device_xname(un->un_dev), __func__, phy, reg, *val));

sys/dev/usb/if_url.c

605

url_uno_mii_write_reg(struct usbnet *un, int phy, int reg, uint16_t val)

sys/dev/usb/if_url.c

609

device_xname(un->un_dev), __func__, phy, reg, val));

sys/dev/usb/if_url.c

618

switch (reg) {

sys/dev/usb/if_url.c

620

reg = URL_BMCR;

sys/dev/usb/if_url.c

623

reg = URL_BMSR;

sys/dev/usb/if_url.c

629

reg = URL_ANAR;

sys/dev/usb/if_url.c

632

reg = URL_ANLP;

sys/dev/usb/if_url.c

635

reg = URL_MSR;

sys/dev/usb/if_url.c

639

device_xname(un->un_dev), __func__, reg);

sys/dev/usb/if_url.c

643

if (reg == URL_MSR)

sys/dev/usb/if_url.c

644

url_csr_write_1(un, reg, val);

sys/dev/usb/if_url.c

646

url_csr_write_2(un, reg, val);

sys/dev/usb/if_url.c

667

url_ext_mii_read_reg(struct usbnet *un, int phy, int reg)

sys/dev/usb/if_url.c

672

device_xname(un->un_dev), __func__, phy, reg));

sys/dev/usb/if_url.c

681

(reg | URL_PHYCNT_PHYOWN) & ~URL_PHYCNT_RWCR);

sys/dev/usb/if_url.c

693

device_xname(un->un_dev), __func__, phy, reg, val));

sys/dev/usb/if_url.c

699

url_ext_mii_write_reg(struct usbnet *un, int phy, int reg, int data)

sys/dev/usb/if_url.c

703

device_xname(un->un_dev), __func__, phy, reg, data));

sys/dev/usb/if_url.c

707

url_csr_write_1(un, URL_PHYCNT, reg | URL_PHYCNT_RWCR); /* Write */

sys/dev/usb/if_urtw.c

190

uint32_t reg;

sys/dev/usb/if_urtw.c

195

uint8_t reg;

sys/dev/usb/if_urtw.c

2075

if (rate == urtw_ratetable[i].reg)

sys/dev/usb/if_urtw.c

2089

return urtw_ratetable[i].reg;

sys/dev/usb/if_urtw.c

2887

urtw_8225_write(sc, urtw_8225_rf_part1[i].reg,

sys/dev/usb/if_urtw.c

2911

urtw_8187_write_phy_ofdm(sc, urtw_8225_rf_part2[i].reg,

sys/dev/usb/if_urtw.c

2921

urtw_8187_write_phy_cck(sc, urtw_8225_rf_part3[i].reg,

sys/dev/usb/if_urtw.c

3283

urtw_8225_write(sc, urtw_8225v2_rf_part1[i].reg,

sys/dev/usb/if_urtw.c

3331

urtw_8187_write_phy_ofdm(sc, urtw_8225v2_rf_part2[i].reg,

sys/dev/usb/if_urtw.c

3340

urtw_8187_write_phy_cck(sc, urtw_8225v2_rf_part3[i].reg,

sys/dev/usb/if_urtw.c

3736

urtw_write8_idx_m(sc, urtw_8187b_regtbl[i].reg,

sys/dev/usb/if_urtw.c

3856

urtw_8225_write(sc, urtw_8225v2_b_rf[i].reg,

sys/dev/usb/if_urtwn.c

1244

uint32_t reg[R92C_MAX_CHAINS], val;

sys/dev/usb/if_urtwn.c

1246

reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0));

sys/dev/usb/if_urtwn.c

1248

reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain));

sys/dev/usb/if_urtwn.c

1252

reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE);

sys/dev/usb/if_urtwn.c

1256

RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) |

sys/dev/usb/if_urtwn.c

1261

reg[0] | R92C_HSSI_PARAM2_READ_EDGE);

sys/dev/usb/if_urtwn.c

1298

uint32_t reg;

sys/dev/usb/if_urtwn.c

1303

reg = urtwn_read_4(sc, R92C_EFUSE_CTRL);

sys/dev/usb/if_urtwn.c

1304

reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr);

sys/dev/usb/if_urtwn.c

1305

reg &= ~R92C_EFUSE_CTRL_VALID;

sys/dev/usb/if_urtwn.c

1306

urtwn_write_4(sc, R92C_EFUSE_CTRL, reg);

sys/dev/usb/if_urtwn.c

1310

reg = urtwn_read_4(sc, R92C_EFUSE_CTRL);

sys/dev/usb/if_urtwn.c

1311

if (reg & R92C_EFUSE_CTRL_VALID) {

sys/dev/usb/if_urtwn.c

1313

return MS(reg, R92C_EFUSE_CTRL_DATA);

sys/dev/usb/if_urtwn.c

1326

uint32_t reg;

sys/dev/usb/if_urtwn.c

1339

reg = urtwn_efuse_read_1(sc, addr);

sys/dev/usb/if_urtwn.c

1340

if (reg == 0xff)

sys/dev/usb/if_urtwn.c

1343

off = reg >> 4;

sys/dev/usb/if_urtwn.c

1344

msk = reg & 0xf;

sys/dev/usb/if_urtwn.c

1365

uint32_t reg;

sys/dev/usb/if_urtwn.c

1367

reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL);

sys/dev/usb/if_urtwn.c

1368

if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) {

sys/dev/usb/if_urtwn.c

1370

reg | R92C_SYS_ISO_CTRL_PWC_EV12V);

sys/dev/usb/if_urtwn.c

1372

reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN);

sys/dev/usb/if_urtwn.c

1373

if (!(reg & R92C_SYS_FUNC_EN_ELDR)) {

sys/dev/usb/if_urtwn.c

1375

reg | R92C_SYS_FUNC_EN_ELDR);

sys/dev/usb/if_urtwn.c

1377

reg = urtwn_read_2(sc, R92C_SYS_CLKR);

sys/dev/usb/if_urtwn.c

1378

if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) !=

sys/dev/usb/if_urtwn.c

1381

reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M);

sys/dev/usb/if_urtwn.c

1388

uint32_t reg;

sys/dev/usb/if_urtwn.c

1396

reg = urtwn_read_4(sc, R92C_SYS_CFG);

sys/dev/usb/if_urtwn.c

1397

if (reg & R92C_SYS_CFG_TRP_VAUX_EN) {

sys/dev/usb/if_urtwn.c

1401

if (reg & R92C_SYS_CFG_TYPE_92C) {

sys/dev/usb/if_urtwn.c

1410

if (reg & R92C_SYS_CFG_VENDOR_UMC) {

sys/dev/usb/if_urtwn.c

1412

if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) {

sys/dev/usb/if_urtwn.c

1541

uint32_t reg;

sys/dev/usb/if_urtwn.c

1556

reg = urtwn_efuse_read_1(sc, addr);

sys/dev/usb/if_urtwn.c

1557

if (reg == 0xff)

sys/dev/usb/if_urtwn.c

1560

if ((reg & 0x1f) == 0x0f) {

sys/dev/usb/if_urtwn.c

1561

tmp = (reg & 0xe0) >> 5;

sys/dev/usb/if_urtwn.c

1562

reg = urtwn_efuse_read_1(sc, addr);

sys/dev/usb/if_urtwn.c

1563

if ((reg & 0x0f) != 0x0f)

sys/dev/usb/if_urtwn.c

1564

off = ((reg & 0xf0) >> 1) | tmp;

sys/dev/usb/if_urtwn.c

1567

off = reg >> 4;

sys/dev/usb/if_urtwn.c

1568

msk = reg & 0xf;

sys/dev/usb/if_urtwn.c

1762

uint8_t reg;

sys/dev/usb/if_urtwn.c

1769

reg = urtwn_read_1(sc, R92C_CR + 2) & 0x0c;

sys/dev/usb/if_urtwn.c

1770

urtwn_write_1(sc, R92C_CR + 2, reg | type);

sys/dev/usb/if_urtwn.c

1806

uint8_t reg;

sys/dev/usb/if_urtwn.c

1816

reg = urtwn_read_1(sc, R92C_LEDCFG1) & R92E_LEDSON;

sys/dev/usb/if_urtwn.c

1817

urtwn_write_1(sc, R92C_LEDCFG1, reg |

sys/dev/usb/if_urtwn.c

1820

reg = urtwn_read_1(sc, R92C_LEDCFG1) &

sys/dev/usb/if_urtwn.c

1822

urtwn_write_1(sc, R92C_LEDCFG1, reg);

sys/dev/usb/if_urtwn.c

1825

reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0xf0;

sys/dev/usb/if_urtwn.c

1826

urtwn_write_1(sc, R92C_LEDCFG2, reg | 0x60);

sys/dev/usb/if_urtwn.c

1828

reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0x90;

sys/dev/usb/if_urtwn.c

1830

reg | R92C_LEDCFG0_DIS);

sys/dev/usb/if_urtwn.c

1831

reg = urtwn_read_1(sc, R92C_MAC_PINMUX_CFG);

sys/dev/usb/if_urtwn.c

1833

reg & 0xfe);

sys/dev/usb/if_urtwn.c

1836

reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70;

sys/dev/usb/if_urtwn.c

1838

reg |= R92C_LEDCFG0_DIS;

sys/dev/usb/if_urtwn.c

1840

urtwn_write_1(sc, R92C_LEDCFG0, reg);

sys/dev/usb/if_urtwn.c

1963

uint32_t reg;

sys/dev/usb/if_urtwn.c

2053

reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0));

sys/dev/usb/if_urtwn.c

2054

reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20);

sys/dev/usb/if_urtwn.c

2055

urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg);

sys/dev/usb/if_urtwn.c

2058

reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1));

sys/dev/usb/if_urtwn.c

2059

reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20);

sys/dev/usb/if_urtwn.c

2060

urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg);

sys/dev/usb/if_urtwn.c

2097

reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0));

sys/dev/usb/if_urtwn.c

2098

reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32);

sys/dev/usb/if_urtwn.c

2099

urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg);

sys/dev/usb/if_urtwn.c

2102

reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1));

sys/dev/usb/if_urtwn.c

2103

reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32);

sys/dev/usb/if_urtwn.c

2104

urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg);

sys/dev/usb/if_urtwn.c

2198

reg = urtwn_read_4(sc, R92C_TCR);

sys/dev/usb/if_urtwn.c

2199

reg &= ~0x01;

sys/dev/usb/if_urtwn.c

2200

urtwn_write_4(sc, R92C_TCR, reg);

sys/dev/usb/if_urtwn.c

2201

reg |= 0x01;

sys/dev/usb/if_urtwn.c

2202

urtwn_write_4(sc, R92C_TCR, reg);

sys/dev/usb/if_urtwn.c

3131

uint32_t reg;

sys/dev/usb/if_urtwn.c

3157

reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL);

sys/dev/usb/if_urtwn.c

3158

if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) {

sys/dev/usb/if_urtwn.c

3160

reg | R92C_LDOV12D_CTRL_LDV12_EN);

sys/dev/usb/if_urtwn.c

3210

reg = urtwn_read_2(sc, R92C_CR);

sys/dev/usb/if_urtwn.c

3211

reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN |

sys/dev/usb/if_urtwn.c

3215

urtwn_write_2(sc, R92C_CR, reg);

sys/dev/usb/if_urtwn.c

3227

uint32_t reg;

sys/dev/usb/if_urtwn.c

3295

reg = urtwn_read_2(sc, R92C_CR);

sys/dev/usb/if_urtwn.c

3296

reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN |

sys/dev/usb/if_urtwn.c

3299

urtwn_write_2(sc, R92C_CR, reg);

sys/dev/usb/if_urtwn.c

3307

uint32_t reg;

sys/dev/usb/if_urtwn.c

3355

reg = urtwn_read_2(sc, R92C_CR);

sys/dev/usb/if_urtwn.c

3356

reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN |

sys/dev/usb/if_urtwn.c

3359

urtwn_write_2(sc, R92C_CR, reg);

sys/dev/usb/if_urtwn.c

3422

uint16_t reg;

sys/dev/usb/if_urtwn.c

3437

reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN);

sys/dev/usb/if_urtwn.c

3438

if (!(reg & R92C_SYS_FUNC_EN_CPUEN))

sys/dev/usb/if_urtwn.c

3450

uint16_t reg;

sys/dev/usb/if_urtwn.c

3457

reg = urtwn_read_2(sc, R92C_RSV_CTRL) & ~R92E_RSV_MIO_EN;

sys/dev/usb/if_urtwn.c

3458

urtwn_write_2(sc,R92C_RSV_CTRL, reg);

sys/dev/usb/if_urtwn.c

3462

reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN);

sys/dev/usb/if_urtwn.c

3463

urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN);

sys/dev/usb/if_urtwn.c

3466

urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg | R92C_SYS_FUNC_EN_CPUEN);

sys/dev/usb/if_urtwn.c

3470

reg = urtwn_read_2(sc, R92C_RSV_CTRL) | R92E_RSV_MIO_EN;

sys/dev/usb/if_urtwn.c

3471

urtwn_write_2(sc,R92C_RSV_CTRL, reg);

sys/dev/usb/if_urtwn.c

3485

uint32_t reg;

sys/dev/usb/if_urtwn.c

3492

reg = urtwn_read_4(sc, R92C_MCUFWDL);

sys/dev/usb/if_urtwn.c

3493

reg = RW(reg, R92C_MCUFWDL_PAGE, page);

sys/dev/usb/if_urtwn.c

3494

urtwn_write_4(sc, R92C_MCUFWDL, reg);

sys/dev/usb/if_urtwn.c

3522

uint32_t reg;

sys/dev/usb/if_urtwn.c

3637

reg = urtwn_read_4(sc, R92C_MCUFWDL);

sys/dev/usb/if_urtwn.c

3638

reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY;

sys/dev/usb/if_urtwn.c

3639

urtwn_write_4(sc, R92C_MCUFWDL, reg);

sys/dev/usb/if_urtwn.c

3670

uint32_t reg;

sys/dev/usb/if_urtwn.c

3684

reg = urtwn_read_2(sc, R92C_USB_EP + 1);

sys/dev/usb/if_urtwn.c

3685

DPRINTFN(DBG_INIT, "USB endpoints mapping %#jx", reg, 0, 0, 0);

sys/dev/usb/if_urtwn.c

3686

if (MS(reg, R92C_USB_EP_HQ) != 0)

sys/dev/usb/if_urtwn.c

3688

if (MS(reg, R92C_USB_EP_NQ) != 0)

sys/dev/usb/if_urtwn.c

3690

if (MS(reg, R92C_USB_EP_LQ) != 0)

sys/dev/usb/if_urtwn.c

3719

reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL);

sys/dev/usb/if_urtwn.c

3720

reg &= ~R92C_TRXDMA_CTRL_QMAP_M;

sys/dev/usb/if_urtwn.c

3723

reg |= R92C_TRXDMA_CTRL_QMAP_HQ;

sys/dev/usb/if_urtwn.c

3725

reg |= R92C_TRXDMA_CTRL_QMAP_NQ;

sys/dev/usb/if_urtwn.c

3727

reg |= R92C_TRXDMA_CTRL_QMAP_LQ;

sys/dev/usb/if_urtwn.c

3735

reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ;

sys/dev/usb/if_urtwn.c

3737

reg |= R92C_TRXDMA_CTRL_QMAP_HQ_LQ;

sys/dev/usb/if_urtwn.c

3740

reg |= R92C_TRXDMA_CTRL_QMAP_3EP;

sys/dev/usb/if_urtwn.c

3742

urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg);

sys/dev/usb/if_urtwn.c

3757

uint32_t reg;

sys/dev/usb/if_urtwn.c

3788

reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL);

sys/dev/usb/if_urtwn.c

3789

reg &= ~R92C_TRXDMA_CTRL_QMAP_M;

sys/dev/usb/if_urtwn.c

3791

reg |= R92C_TRXDMA_CTRL_QMAP_LQ;

sys/dev/usb/if_urtwn.c

3793

reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ;

sys/dev/usb/if_urtwn.c

3795

reg |= R92C_TRXDMA_CTRL_QMAP_3EP;

sys/dev/usb/if_urtwn.c

3796

urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg);

sys/dev/usb/if_urtwn.c

3820

urtwn_write_1(sc, rtl8188eu_mac[i].reg,

sys/dev/usb/if_urtwn.c

3824

urtwn_write_1(sc, rtl8192eu_mac[i].reg,

sys/dev/usb/if_urtwn.c

3828

urtwn_write_1(sc, rtl8192cu_mac[i].reg,

sys/dev/usb/if_urtwn.c

3837

uint32_t reg;

sys/dev/usb/if_urtwn.c

3919

reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO);

sys/dev/usb/if_urtwn.c

3920

reg = (reg & ~0x00000003) | 0x2;

sys/dev/usb/if_urtwn.c

3921

urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg);

sys/dev/usb/if_urtwn.c

3923

reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO);

sys/dev/usb/if_urtwn.c

3924

reg = (reg & ~0x00300033) | 0x00200022;

sys/dev/usb/if_urtwn.c

3925

urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg);

sys/dev/usb/if_urtwn.c

3927

reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING);

sys/dev/usb/if_urtwn.c

3928

reg = (reg & ~0xff000000) | (0x45 << 24);

sys/dev/usb/if_urtwn.c

3929

urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg);

sys/dev/usb/if_urtwn.c

3931

reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA);

sys/dev/usb/if_urtwn.c

3932

reg = (reg & ~0x000000ff) | 0x23;

sys/dev/usb/if_urtwn.c

3933

urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg);

sys/dev/usb/if_urtwn.c

3935

reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1);

sys/dev/usb/if_urtwn.c

3936

reg = (reg & ~0x00000030) | (1 << 4);

sys/dev/usb/if_urtwn.c

3937

urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg);

sys/dev/usb/if_urtwn.c

3939

reg = urtwn_bb_read(sc, 0xe74);

sys/dev/usb/if_urtwn.c

3940

reg = (reg & ~0x0c000000) | (2 << 26);

sys/dev/usb/if_urtwn.c

3941

urtwn_bb_write(sc, 0xe74, reg);

sys/dev/usb/if_urtwn.c

3942

reg = urtwn_bb_read(sc, 0xe78);

sys/dev/usb/if_urtwn.c

3943

reg = (reg & ~0x0c000000) | (2 << 26);

sys/dev/usb/if_urtwn.c

3944

urtwn_bb_write(sc, 0xe78, reg);

sys/dev/usb/if_urtwn.c

3945

reg = urtwn_bb_read(sc, 0xe7c);

sys/dev/usb/if_urtwn.c

3946

reg = (reg & ~0x0c000000) | (2 << 26);

sys/dev/usb/if_urtwn.c

3947

urtwn_bb_write(sc, 0xe7c, reg);

sys/dev/usb/if_urtwn.c

3948

reg = urtwn_bb_read(sc, 0xe80);

sys/dev/usb/if_urtwn.c

3949

reg = (reg & ~0x0c000000) | (2 << 26);

sys/dev/usb/if_urtwn.c

3950

urtwn_bb_write(sc, 0xe80, reg);

sys/dev/usb/if_urtwn.c

3951

reg = urtwn_bb_read(sc, 0xe88);

sys/dev/usb/if_urtwn.c

3952

reg = (reg & ~0x0c000000) | (2 << 26);

sys/dev/usb/if_urtwn.c

3953

urtwn_bb_write(sc, 0xe88, reg);

sys/dev/usb/if_urtwn.c

3975

reg = urtwn_bb_read(sc, R92C_AFE_CTRL3);

sys/dev/usb/if_urtwn.c

3977

RW(reg, R92C_AFE_XTAL_CTRL_ADDR,

sys/dev/usb/if_urtwn.c

3985

reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL);

sys/dev/usb/if_urtwn.c

3987

RW(reg, R92C_AFE_XTAL_CTRL_ADDR,

sys/dev/usb/if_urtwn.c

4001

uint32_t reg, mask, saved;

sys/dev/usb/if_urtwn.c

4030

reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i));

sys/dev/usb/if_urtwn.c

4031

reg |= 0x100000;

sys/dev/usb/if_urtwn.c

4032

urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg);

sys/dev/usb/if_urtwn.c

4036

reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i));

sys/dev/usb/if_urtwn.c

4037

reg |= 0x10;

sys/dev/usb/if_urtwn.c

4038

urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg);

sys/dev/usb/if_urtwn.c

4042

reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i));

sys/dev/usb/if_urtwn.c

4043

reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH;

sys/dev/usb/if_urtwn.c

4044

urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg);

sys/dev/usb/if_urtwn.c

4046

reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i));

sys/dev/usb/if_urtwn.c

4047

reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH;

sys/dev/usb/if_urtwn.c

4048

urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg);

sys/dev/usb/if_urtwn.c

4067

reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)) & ~mask;

sys/dev/usb/if_urtwn.c

4068

urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg | saved);

sys/dev/usb/if_urtwn.c

4136

uint8_t reg;

sys/dev/usb/if_urtwn.c

4153

reg = urtwn_read_1(sc, 0x16);

sys/dev/usb/if_urtwn.c

4154

reg = (reg & ~0xf0) | 0x90;

sys/dev/usb/if_urtwn.c

4155

urtwn_write_1(sc, 0x16, reg);

sys/dev/usb/if_urtwn.c

4211

uint32_t reg;

sys/dev/usb/if_urtwn.c

4218

reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32);

sys/dev/usb/if_urtwn.c

4219

reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]);

sys/dev/usb/if_urtwn.c

4220

urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg);

sys/dev/usb/if_urtwn.c

4222

reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11);

sys/dev/usb/if_urtwn.c

4223

reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]);

sys/dev/usb/if_urtwn.c

4224

reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]);

sys/dev/usb/if_urtwn.c

4225

reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]);

sys/dev/usb/if_urtwn.c

4226

urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg);

sys/dev/usb/if_urtwn.c

4228

reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32);

sys/dev/usb/if_urtwn.c

4229

reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]);

sys/dev/usb/if_urtwn.c

4230

reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]);

sys/dev/usb/if_urtwn.c

4231

reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]);

sys/dev/usb/if_urtwn.c

4232

urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg);

sys/dev/usb/if_urtwn.c

4234

reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11);

sys/dev/usb/if_urtwn.c

4235

reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]);

sys/dev/usb/if_urtwn.c

4236

urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg);

sys/dev/usb/if_urtwn.c

4502

uint32_t reg;

sys/dev/usb/if_urtwn.c

4507

reg = urtwn_read_1(sc, R92C_RRSR + 2);

sys/dev/usb/if_urtwn.c

4508

reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5;

sys/dev/usb/if_urtwn.c

4509

urtwn_write_1(sc, R92C_RRSR + 2, (uint8_t)reg);

sys/dev/usb/if_urtwn.c

4517

reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM);

sys/dev/usb/if_urtwn.c

4518

reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4;

sys/dev/usb/if_urtwn.c

4519

urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg);

sys/dev/usb/if_urtwn.c

4521

reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF);

sys/dev/usb/if_urtwn.c

4522

reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10;

sys/dev/usb/if_urtwn.c

4523

urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg);

sys/dev/usb/if_urtwn.c

4529

reg = urtwn_bb_read(sc, 0x818);

sys/dev/usb/if_urtwn.c

4530

reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26;

sys/dev/usb/if_urtwn.c

4531

urtwn_bb_write(sc, 0x818, reg);

sys/dev/usb/if_urtwn.c

4808

uint32_t reg;

sys/dev/usb/if_urtwn.c

4880

reg = urtwn_read_4(sc, R92C_CR);

sys/dev/usb/if_urtwn.c

4884

reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA);

sys/dev/usb/if_urtwn.c

4888

reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_ADHOC);

sys/dev/usb/if_urtwn.c

4891

urtwn_write_4(sc, R92C_CR, reg);

sys/dev/usb/if_urtwn.c

4894

reg = urtwn_read_4(sc, R92C_RRSR);

sys/dev/usb/if_urtwn.c

4895

reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M);

sys/dev/usb/if_urtwn.c

4896

urtwn_write_4(sc, R92C_RRSR, reg);

sys/dev/usb/if_urtwn.c

4926

reg = urtwn_read_4(sc, R92C_TDECTRL);

sys/dev/usb/if_urtwn.c

4927

reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6);

sys/dev/usb/if_urtwn.c

4928

urtwn_write_4(sc, R92C_TDECTRL, reg);

sys/dev/usb/if_urtwn.c

4986

reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD);

sys/dev/usb/if_urtwn.c

4987

reg |= R92C_RFMOD_CCK_EN;

sys/dev/usb/if_urtwn.c

4988

urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg);

sys/dev/usb/if_urtwn.c

4989

reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD);

sys/dev/usb/if_urtwn.c

4990

reg |= R92C_RFMOD_OFDM_EN;

sys/dev/usb/if_urtwn.c

4991

urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg);

sys/dev/usb/if_urtwn.c

5132

uint32_t reg;

sys/dev/usb/if_urtwn.c

5202

reg = urtwn_read_4(sc, R92C_GPIO_PIN_CTRL) & ~0x0000ff00;

sys/dev/usb/if_urtwn.c

5203

reg |= ((reg << 8) & 0x0000ff00) | 0x00ff0000;

sys/dev/usb/if_urtwn.c

5204

urtwn_write_4(sc, R92C_GPIO_PIN_CTRL, reg);

sys/dev/usb/if_urtwn.c

5209

reg = urtwn_read_2(sc, R92C_GPIO_MUXCFG + 2) & ~0x00f0;

sys/dev/usb/if_urtwn.c

5210

reg |= (((reg & 0x000f) << 4) | 0x0780);

sys/dev/usb/if_urtwn.c

5211

urtwn_write_2(sc, R92C_GPIO_MUXCFG + 2, reg);

sys/dev/usb/if_zyd.c

1008

error = zyd_write16(sc, phyini[i].reg, phyini[i].val);

sys/dev/usb/if_zyd.c

1015

error = zyd_write16(sc, phy2230s[i].reg,

sys/dev/usb/if_zyd.c

1041

error = zyd_write16(sc, phyini[i].reg, phyini[i].val);

sys/dev/usb/if_zyd.c

1103

error = zyd_write16(sc, phyini_1[i].reg, phyini_1[i].val);

sys/dev/usb/if_zyd.c

1114

error = zyd_write16(sc, phyini_2[i].reg, phyini_2[i].val);

sys/dev/usb/if_zyd.c

1125

error = zyd_write16(sc, phyini_3[i].reg, phyini_3[i].val);

sys/dev/usb/if_zyd.c

1197

error = zyd_write16(sc, phyini[i].reg, phyini[i].val);

sys/dev/usb/if_zyd.c

1265

error = zyd_write16(sc, phyini[i].reg, phyini[i].val);

sys/dev/usb/if_zyd.c

1313

error = zyd_write16(sc, phyini[i].reg, phyini[i].val);

sys/dev/usb/if_zyd.c

1359

error = zyd_write16(sc, phyini[i].reg, phyini[i].val);

sys/dev/usb/if_zyd.c

1396

error = zyd_write16(sc, phyini[i].reg, phyini[i].val);

sys/dev/usb/if_zyd.c

1442

error = zyd_write16(sc, phyini[i].reg, phyini[i].val);

sys/dev/usb/if_zyd.c

1564

for (; phyp->reg != 0; phyp++) {

sys/dev/usb/if_zyd.c

1565

if ((error = zyd_write16(sc, phyp->reg, phyp->val)) != 0)

sys/dev/usb/if_zyd.c

1883

(((struct zyd_pair *)cmd->data) + i)->reg)

sys/dev/usb/if_zyd.c

843

zyd_read16(struct zyd_softc *sc, uint16_t reg, uint16_t *val)

sys/dev/usb/if_zyd.c

848

reg = htole16(reg);

sys/dev/usb/if_zyd.c

849

error = zyd_cmd(sc, ZYD_CMD_IORD, &reg, sizeof(reg), &tmp, sizeof(tmp),

sys/dev/usb/if_zyd.c

859

zyd_read32(struct zyd_softc *sc, uint16_t reg, uint32_t *val)

sys/dev/usb/if_zyd.c

865

regs[0] = htole16(ZYD_REG32_HI(reg));

sys/dev/usb/if_zyd.c

866

regs[1] = htole16(ZYD_REG32_LO(reg));

sys/dev/usb/if_zyd.c

877

zyd_write16(struct zyd_softc *sc, uint16_t reg, uint16_t val)

sys/dev/usb/if_zyd.c

881

pair.reg = htole16(reg);

sys/dev/usb/if_zyd.c

888

zyd_write32(struct zyd_softc *sc, uint16_t reg, uint32_t val)

sys/dev/usb/if_zyd.c

892

pair[0].reg = htole16(ZYD_REG32_HI(reg));

sys/dev/usb/if_zyd.c

894

pair[1].reg = htole16(ZYD_REG32_LO(reg));

sys/dev/usb/if_zyd.c

955

error = zyd_write16(sc, phyini[i].reg, phyini[i].val);

sys/dev/usb/if_zydreg.h

1060

uint16_t reg;

sys/dev/usb/if_zydreg.h

1062

#define ZYD_REG32_LO(reg) (reg)

sys/dev/usb/if_zydreg.h

1063

#define ZYD_REG32_HI(reg) \

sys/dev/usb/if_zydreg.h

1064

((reg) + ((((reg) & 0xf000) == 0x9000) ? 2 : 1))

sys/dev/usb/if_zydreg.h

1102

uint16_t reg;

sys/dev/usb/if_zydreg.h

1107

uint16_t reg;

sys/dev/usb/pseye.c

546

pseye_getreg(struct pseye_softc *sc, uint16_t reg)

sys/dev/usb/pseye.c

555

USETW(req.wIndex, reg);

sys/dev/usb/pseye.c

561

reg, usbd_errstr(err));

sys/dev/usb/pseye.c

569

pseye_setreg(struct pseye_softc *sc, uint16_t reg, uint8_t val)

sys/dev/usb/pseye.c

577

USETW(req.wIndex, reg);

sys/dev/usb/pseye.c

583

reg, usbd_errstr(err));

sys/dev/usb/pseye.c

587

pseye_setregv(struct pseye_softc *sc, uint16_t reg, uint8_t val)

sys/dev/usb/pseye.c

589

pseye_setreg(sc, reg, val);

sys/dev/usb/pseye.c

590

if (pseye_getreg(sc, reg) != val)

sys/dev/usb/pseye.c

592

reg);

sys/dev/usb/pseye.c

596

pseye_sccb_setreg(struct pseye_softc *sc, uint8_t reg, uint8_t val)

sys/dev/usb/pseye.c

598

pseye_setreg(sc, PSEYE_SCCB_SUBADDR, reg);

sys/dev/usb/pseye.c

604

reg);

sys/dev/usb/pseye.c

611

uint8_t reg;

sys/dev/usb/pseye.c

614

reg = pseye_getreg(sc, PSEYE_SCCB_STATUS);

sys/dev/usb/pseye.c

615

if (reg == 0x00)

sys/dev/usb/pseye.c

617

else if (reg == 0x04)

sys/dev/usb/slurm.c

209

slurm_getreg(struct slurm_softc *sc, int reg, uint16_t *val)

sys/dev/usb/slurm.c

214

++reg;

sys/dev/usb/slurm.c

216

s[0] = reg;

sys/dev/usb/slurm.c

220

reg, &s, sizeof(s));

sys/dev/usb/slurm.c

228

slurm_setreg(struct slurm_softc *sc, int reg, uint16_t val)

sys/dev/usb/slurm.c

233

++reg;

sys/dev/usb/slurm.c

235

s[0] = reg;

sys/dev/usb/slurm.c

240

reg, &s, sizeof(s));

sys/dev/usb/u3g.c

558

u3g_set(void *arg, int portno, int reg, int onoff)

sys/dev/usb/u3g.c

569

switch (reg) {

sys/dev/usb/uark.c

218

uark_set(void *vsc, int portno, int reg, int onoff)

sys/dev/usb/uark.c

225

switch (reg) {

sys/dev/usb/ubsa_common.c

192

ubsa_set(void *addr, int portno, int reg, int onoff)

sys/dev/usb/ubsa_common.c

199

switch (reg) {

sys/dev/usb/uchcom.c

855

uchcom_set(void *arg, int portno, int reg, int onoff)

sys/dev/usb/uchcom.c

862

switch (reg) {

sys/dev/usb/udl.c

242

udl_reg_write_1(struct udl_softc *sc, uint8_t reg, uint8_t val)

sys/dev/usb/udl.c

246

(UDL_BULK_CMD_REG_WRITE_1 << 16) | (reg << 8) | val);

sys/dev/usb/udl.c

250

udl_reg_write_2(struct udl_softc *sc, uint8_t reg, uint16_t val)

sys/dev/usb/udl.c

253

udl_reg_write_1(sc, reg++, val >> 8);

sys/dev/usb/udl.c

254

udl_reg_write_1(sc, reg, val);

sys/dev/usb/udl.c

258

udl_reg_write_3(struct udl_softc *sc, uint8_t reg, uint32_t val)

sys/dev/usb/udl.c

261

udl_reg_write_1(sc, reg++, val >> 16);

sys/dev/usb/udl.c

262

udl_reg_write_1(sc, reg++, val >> 8);

sys/dev/usb/udl.c

263

udl_reg_write_1(sc, reg, val);

sys/dev/usb/uftdi.c

581

uftdi_set(void *vsc, int portno, int reg, int onoff)

sys/dev/usb/uftdi.c

588

reg, onoff));

sys/dev/usb/uftdi.c

593

switch (reg) {

sys/dev/usb/uipaq.c

343

uipaq_set(void *addr, int portno, int reg, int onoff)

sys/dev/usb/uipaq.c

350

switch (reg) {

sys/dev/usb/uipaq.c

362

"unhandled set request: reg=%x onoff=%x\n", reg, onoff);

sys/dev/usb/ukyopon.c

162

ukyopon_set(void *addr, int portno, int reg, int onoff)

sys/dev/usb/ukyopon.c

166

umodem_set(&sc->sc_umodem, portno, reg, onoff);

sys/dev/usb/umcs.c

355

umcs7840_get_reg(struct umcs7840_softc *sc, uint8_t reg, uint8_t *data)

sys/dev/usb/umcs.c

363

USETW(req.wIndex, reg);

sys/dev/usb/umcs.c

369

"Reading register %d failed: %s\n", reg, usbd_errstr(err));

sys/dev/usb/umcs.c

374

umcs7840_set_reg(struct umcs7840_softc *sc, uint8_t reg, uint8_t data)

sys/dev/usb/umcs.c

382

USETW(req.wIndex, reg);

sys/dev/usb/umcs.c

387

aprint_normal_dev(sc->sc_dev, "Writing register %d failed: %s\n", reg, usbd_errstr(err));

sys/dev/usb/umcs.c

394

uint8_t reg, uint8_t *data)

sys/dev/usb/umcs.c

406

USETW(req.wIndex, reg);

sys/dev/usb/umcs.c

411

aprint_normal_dev(sc->sc_dev, "Reading UART %d register %d failed: %s\n", portno, reg, usbd_errstr(err));

sys/dev/usb/umcs.c

416

umcs7840_set_UART_reg(struct umcs7840_softc *sc, uint8_t portno, uint8_t reg, uint8_t data)

sys/dev/usb/umcs.c

428

USETW(req.wIndex, reg);

sys/dev/usb/umcs.c

435

portno, reg, usbd_errstr(err));

sys/dev/usb/umcs.c

588

umcs7840_set(void *self, int portno, int reg, int onoff)

sys/dev/usb/umcs.c

595

switch (reg) {

sys/dev/usb/umct.c

378

umct_set(void *addr, int portno, int reg, int onoff)

sys/dev/usb/umct.c

385

switch (reg) {

sys/dev/usb/umodem_common.c

602

umodem_set(void *addr, int portno, int reg, int onoff)

sys/dev/usb/umodem_common.c

609

switch (reg) {

sys/dev/usb/uplcom.c

651

uplcom_set(void *addr, int portno, int reg, int onoff)

sys/dev/usb/uplcom.c

658

switch (reg) {

sys/dev/usb/usbnet.c

205

uno_read_reg(struct usbnet *un, int phy, int reg, uint16_t *val)

sys/dev/usb/usbnet.c

208

return (*un->un_ops->uno_read_reg)(un, phy, reg, val);

sys/dev/usb/usbnet.c

212

uno_write_reg(struct usbnet *un, int phy, int reg, uint16_t val)

sys/dev/usb/usbnet.c

215

return (*un->un_ops->uno_write_reg)(un, phy, reg, val);

sys/dev/usb/usbnet.c

921

usbnet_mii_readreg(device_t dev, int phy, int reg, uint16_t *val)

sys/dev/usb/usbnet.c

934

err = uno_read_reg(un, phy, reg, val);

sys/dev/usb/usbnet.c

945

usbnet_mii_writereg(device_t dev, int phy, int reg, uint16_t val)

sys/dev/usb/usbnet.c

958

err = uno_write_reg(un, phy, reg, val);

sys/dev/usb/usbnet.h

133

typedef int (*usbnet_mii_read_reg_cb)(struct usbnet *, int reg,

sys/dev/usb/usbnet.h

136

typedef int (*usbnet_mii_write_reg_cb)(struct usbnet *, int reg,

sys/dev/usb/uslsa.c

330

uslsa_set(void *vsc, int portno, int reg, int onoff)

sys/dev/usb/uslsa.c

337

reg, onoff));

sys/dev/usb/uslsa.c

342

switch (reg) {

sys/dev/usb/ustir.c

178

ustir_read_reg(struct ustir_softc *sc, unsigned int reg, uint8_t *data)

sys/dev/usb/ustir.c

185

USETW(req.wIndex, reg);

sys/dev/usb/ustir.c

192

ustir_write_reg(struct ustir_softc *sc, unsigned int reg, uint8_t data)

sys/dev/usb/ustir.c

199

USETW(req.wIndex, reg);

sys/dev/usb/uvscom.c

596

uvscom_set(void *addr, int portno, int reg, int onoff)

sys/dev/usb/uvscom.c

603

switch (reg) {

sys/dev/usb/uxrcom.c

174

uxrcom_set(void *addr, int portno, int reg, int onoff)

sys/dev/usb/uxrcom.c

186

switch (reg) {

sys/dev/virtio/virtio_mmio.c

132

virtio_mmio_reg_read(struct virtio_mmio_softc *sc, bus_addr_t reg)

sys/dev/virtio/virtio_mmio.c

136

val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, reg);

sys/dev/virtio/virtio_mmio.c

144

virtio_mmio_reg_write(struct virtio_mmio_softc *sc, bus_addr_t reg,

sys/dev/virtio/virtio_mmio.c

150

bus_space_write_4(sc->sc_iot, sc->sc_ioh, reg, val);

sys/dev/virtio/virtio_mmio.c

154

virtio_mmio_v2_set_addr(struct virtio_mmio_softc *sc, bus_addr_t reg,

sys/dev/virtio/virtio_mmio.c

157

virtio_mmio_reg_write(sc, reg, BUS_ADDR_LO32(addr));

sys/dev/virtio/virtio_mmio.c

158

virtio_mmio_reg_write(sc, reg + 4, BUS_ADDR_HI32(addr));

sys/dev/vme/if_ie_vme.c

245

#define read_iev(sc, reg) \

sys/dev/vme/if_ie_vme.c

246

bus_space_read_2(sc->ievt, sc->ievh, offsetof(struct ievme, reg))

sys/dev/vme/if_ie_vme.c

247

#define write_iev(sc, reg, val) \

sys/dev/vme/if_ie_vme.c

248

bus_space_write_2(sc->ievt, sc->ievh, offsetof(struct ievme, reg), val)

sys/kern/subr_vmem.c

1802

} *reg = NULL;

sys/kern/subr_vmem.c

1859

struct reg *r;

sys/kern/subr_vmem.c

1912

reg = realloc(reg, sizeof(*reg) * nreg);

sys/kern/subr_vmem.c

1913

r = &reg[nreg - 1];

sys/kern/subr_vmem.c

1921

r = &reg[rand() % nreg];

sys/kern/subr_vmem.c

1931

*r = reg[nreg - 1];

sys/kern/sys_process_lwpstatus.c

205

s = sizeof(struct reg);

sys/lib/libunwind/DwarfInstructions.hpp

183

uint32_t reg;

sys/lib/libunwind/DwarfInstructions.hpp

285

reg = addressSpace.get8(p);

sys/lib/libunwind/DwarfInstructions.hpp

287

value = sp[-reg];

sys/lib/libunwind/DwarfInstructions.hpp

499

reg = opcode - DW_OP_reg0;

sys/lib/libunwind/DwarfInstructions.hpp

500

*(++sp) = registers.getRegister(reg);

sys/lib/libunwind/DwarfInstructions.hpp

504

reg = addressSpace.getULEB128(p, expressionEnd);

sys/lib/libunwind/DwarfInstructions.hpp

505

*(++sp) = registers.getRegister(reg);

sys/lib/libunwind/DwarfInstructions.hpp

540

reg = opcode - DW_OP_breg0;

sys/lib/libunwind/DwarfInstructions.hpp

542

*(++sp) = registers.getRegister(reg) + svalue;

sys/lib/libunwind/DwarfInstructions.hpp

546

reg = addressSpace.getULEB128(p, expressionEnd);

sys/lib/libunwind/DwarfInstructions.hpp

548

*(++sp) = registers.getRegister(reg) + svalue;

sys/lib/libunwind/DwarfParser.hpp

317

uint64_t reg;

sys/lib/libunwind/DwarfParser.hpp

345

reg = R::dwarf2regno(addressSpace.getULEB128(p, instructionsEnd));

sys/lib/libunwind/DwarfParser.hpp

348

if (reg > kMaxRegisterNumber)

sys/lib/libunwind/DwarfParser.hpp

350

results->savedRegisters[reg].location = kRegisterInCFA;

sys/lib/libunwind/DwarfParser.hpp

351

results->savedRegisters[reg].value = offset;

sys/lib/libunwind/DwarfParser.hpp

354

reg = R::dwarf2regno(addressSpace.getULEB128(p, instructionsEnd));

sys/lib/libunwind/DwarfParser.hpp

355

if (reg > kMaxRegisterNumber)

sys/lib/libunwind/DwarfParser.hpp

357

results->savedRegisters[reg] = initialState.savedRegisters[reg];

sys/lib/libunwind/DwarfParser.hpp

360

reg = R::dwarf2regno(addressSpace.getULEB128(p, instructionsEnd));

sys/lib/libunwind/DwarfParser.hpp

361

if (reg > kMaxRegisterNumber)

sys/lib/libunwind/DwarfParser.hpp

363

results->savedRegisters[reg].location = kRegisterUnused;

sys/lib/libunwind/DwarfParser.hpp

366

reg = R::dwarf2regno(addressSpace.getULEB128(p, instructionsEnd));

sys/lib/libunwind/DwarfParser.hpp

367

if (reg > kMaxRegisterNumber)

sys/lib/libunwind/DwarfParser.hpp

372

results->savedRegisters[reg].location = kRegisterUnused;

sys/lib/libunwind/DwarfParser.hpp

375

reg = R::dwarf2regno(addressSpace.getULEB128(p, instructionsEnd));

sys/lib/libunwind/DwarfParser.hpp

377

if (reg > kMaxRegisterNumber)

sys/lib/libunwind/DwarfParser.hpp

381

results->savedRegisters[reg].location = kRegisterInRegister;

sys/lib/libunwind/DwarfParser.hpp

382

results->savedRegisters[reg].value = reg2;

sys/lib/libunwind/DwarfParser.hpp

405

reg = R::dwarf2regno(addressSpace.getULEB128(p, instructionsEnd));

sys/lib/libunwind/DwarfParser.hpp

407

if (reg > kMaxRegisterNumber)

sys/lib/libunwind/DwarfParser.hpp

409

results->cfaRegister = reg;

sys/lib/libunwind/DwarfParser.hpp

413

reg = R::dwarf2regno(addressSpace.getULEB128(p, instructionsEnd));

sys/lib/libunwind/DwarfParser.hpp

414

if (reg > kMaxRegisterNumber)

sys/lib/libunwind/DwarfParser.hpp

416

results->cfaRegister = reg;

sys/lib/libunwind/DwarfParser.hpp

429

reg = R::dwarf2regno(addressSpace.getULEB128(p, instructionsEnd));

sys/lib/libunwind/DwarfParser.hpp

430

if (reg > kMaxRegisterNumber)

sys/lib/libunwind/DwarfParser.hpp

432

results->savedRegisters[reg].location = kRegisterAtExpression;

sys/lib/libunwind/DwarfParser.hpp

433

results->savedRegisters[reg].value = p;

sys/lib/libunwind/DwarfParser.hpp

438

reg = R::dwarf2regno(addressSpace.getULEB128(p, instructionsEnd));

sys/lib/libunwind/DwarfParser.hpp

439

if (reg > kMaxRegisterNumber)

sys/lib/libunwind/DwarfParser.hpp

443

results->savedRegisters[reg].location = kRegisterInCFA;

sys/lib/libunwind/DwarfParser.hpp

444

results->savedRegisters[reg].value = offset;

sys/lib/libunwind/DwarfParser.hpp

447

reg = R::dwarf2regno(addressSpace.getULEB128(p, instructionsEnd));

sys/lib/libunwind/DwarfParser.hpp

450

if (reg > kMaxRegisterNumber)

sys/lib/libunwind/DwarfParser.hpp

452

results->cfaRegister = reg;

sys/lib/libunwind/DwarfParser.hpp

461

reg = R::dwarf2regno(addressSpace.getULEB128(p, instructionsEnd));

sys/lib/libunwind/DwarfParser.hpp

464

if (reg > kMaxRegisterNumber)

sys/lib/libunwind/DwarfParser.hpp

466

results->savedRegisters[reg].location = kRegisterOffsetFromCFA;

sys/lib/libunwind/DwarfParser.hpp

467

results->savedRegisters[reg].value = offset;

sys/lib/libunwind/DwarfParser.hpp

470

reg = R::dwarf2regno(addressSpace.getULEB128(p, instructionsEnd));

sys/lib/libunwind/DwarfParser.hpp

471

if (reg > kMaxRegisterNumber)

sys/lib/libunwind/DwarfParser.hpp

475

results->savedRegisters[reg].location = kRegisterOffsetFromCFA;

sys/lib/libunwind/DwarfParser.hpp

476

results->savedRegisters[reg].value = offset;

sys/lib/libunwind/DwarfParser.hpp

479

reg = R::dwarf2regno(addressSpace.getULEB128(p, instructionsEnd));

sys/lib/libunwind/DwarfParser.hpp

480

if (reg > kMaxRegisterNumber)

sys/lib/libunwind/DwarfParser.hpp

482

results->savedRegisters[reg].location = kRegisterIsExpression;

sys/lib/libunwind/DwarfParser.hpp

483

results->savedRegisters[reg].value = p;

sys/lib/libunwind/DwarfParser.hpp

489

for (reg = 8; reg < 16; ++reg) {

sys/lib/libunwind/DwarfParser.hpp

490

results->savedRegisters[reg].location = kRegisterInRegister;

sys/lib/libunwind/DwarfParser.hpp

491

results->savedRegisters[reg].value = reg + 16;

sys/lib/libunwind/DwarfParser.hpp

493

for (reg = 16; reg < 32; ++reg) {

sys/lib/libunwind/DwarfParser.hpp

494

results->savedRegisters[reg].location = kRegisterInCFA;

sys/lib/libunwind/DwarfParser.hpp

495

results->savedRegisters[reg].value = (reg - 16) * sizeof(typename R::reg_t);

sys/lib/libunwind/DwarfParser.hpp

506

reg = R::dwarf2regno(addressSpace.getULEB128(p, instructionsEnd));

sys/lib/libunwind/DwarfParser.hpp

507

if (reg > kMaxRegisterNumber)

sys/lib/libunwind/DwarfParser.hpp

511

results->savedRegisters[reg].location = kRegisterInCFA;

sys/lib/libunwind/DwarfParser.hpp

512

results->savedRegisters[reg].value = -offset;

sys/lib/libunwind/DwarfParser.hpp

518

reg = R::dwarf2regno(operand);

sys/lib/libunwind/DwarfParser.hpp

519

if (reg > kMaxRegisterNumber)

sys/lib/libunwind/DwarfParser.hpp

523

results->savedRegisters[reg].location = kRegisterInCFA;

sys/lib/libunwind/DwarfParser.hpp

524

results->savedRegisters[reg].value = offset;

sys/lib/libunwind/DwarfParser.hpp

530

reg = R::dwarf2regno(operand);

sys/lib/libunwind/DwarfParser.hpp

531

if (reg > kMaxRegisterNumber)

sys/lib/libunwind/DwarfParser.hpp

533

results->savedRegisters[reg] = initialState.savedRegisters[reg];

sys/lib/libunwind/Registers.hpp

1001

uint64_t getIP() const { return reg[REGNO_HPPA_PC]; }

sys/lib/libunwind/Registers.hpp

1003

void setIP(uint64_t value) { reg[REGNO_HPPA_PC] = value; }

sys/lib/libunwind/Registers.hpp

1005

uint64_t getSP() const { return reg[REGNO_HPPA_R30]; }

sys/lib/libunwind/Registers.hpp

1007

void setSP(uint64_t value) { reg[REGNO_HPPA_R30] = value; }

sys/lib/libunwind/Registers.hpp

1022

uint32_t reg[REGNO_HPPA_R31 + 1];

sys/lib/libunwind/Registers.hpp

1080

return reg[num];

sys/lib/libunwind/Registers.hpp

1088

reg[num] = value;

sys/lib/libunwind/Registers.hpp

1091

uint64_t getIP() const { return reg[REGNO_MIPS_PC]; }

sys/lib/libunwind/Registers.hpp

1093

void setIP(uint64_t value) { reg[REGNO_MIPS_PC] = value; }

sys/lib/libunwind/Registers.hpp

1095

uint64_t getSP() const { return reg[REGNO_MIPS_R29]; }

sys/lib/libunwind/Registers.hpp

1097

void setSP(uint64_t value) { reg[REGNO_MIPS_R29] = value; }

sys/lib/libunwind/Registers.hpp

1112

uint32_t reg[REGNO_MIPS_R31 + 1];

sys/lib/libunwind/Registers.hpp

1170

return reg[num];

sys/lib/libunwind/Registers.hpp

1178

reg[num] = value;

sys/lib/libunwind/Registers.hpp

118

return reg[num];

sys/lib/libunwind/Registers.hpp

1181

uint64_t getIP() const { return reg[REGNO_MIPS64_PC]; }

sys/lib/libunwind/Registers.hpp

1183

void setIP(uint64_t value) { reg[REGNO_MIPS64_PC] = value; }

sys/lib/libunwind/Registers.hpp

1185

uint64_t getSP() const { return reg[REGNO_MIPS64_R29]; }

sys/lib/libunwind/Registers.hpp

1187

void setSP(uint64_t value) { reg[REGNO_MIPS64_R29] = value; }

sys/lib/libunwind/Registers.hpp

1202

uint64_t reg[REGNO_MIPS64_R31 + 1];

sys/lib/libunwind/Registers.hpp

123

reg[num] = value;

sys/lib/libunwind/Registers.hpp

1246

return reg[num];

sys/lib/libunwind/Registers.hpp

1251

reg[num] = value;

sys/lib/libunwind/Registers.hpp

1254

uint64_t getIP() const { return reg[REGNO_OR1K_LR]; }

sys/lib/libunwind/Registers.hpp

1256

void setIP(uint64_t value) { reg[REGNO_OR1K_LR] = value; }

sys/lib/libunwind/Registers.hpp

1258

uint64_t getSP() const { return reg[REGNO_OR1K_SP]; }

sys/lib/libunwind/Registers.hpp

126

uint64_t getIP() const { return reg[REGNO_X86_64_RIP]; }

sys/lib/libunwind/Registers.hpp

1260

void setSP(uint64_t value) { reg[REGNO_OR1K_SP] = value; }

sys/lib/libunwind/Registers.hpp

1272

uint32_t reg[REGNO_OR1K_FPCSR + 1];

sys/lib/libunwind/Registers.hpp

128

void setIP(uint64_t value) { reg[REGNO_X86_64_RIP] = value; }

sys/lib/libunwind/Registers.hpp

130

uint64_t getSP() const { return reg[REGNO_X86_64_RSP]; }

sys/lib/libunwind/Registers.hpp

132

void setSP(uint64_t value) { reg[REGNO_X86_64_RSP] = value; }

sys/lib/libunwind/Registers.hpp

142

uint64_t reg[REGNO_X86_64_RIP + 1];

sys/lib/libunwind/Registers.hpp

224

return reg[num];

sys/lib/libunwind/Registers.hpp

241

reg[num] = value;

sys/lib/libunwind/Registers.hpp

245

uint64_t getIP() const { return reg[REGNO_PPC32_SRR0]; }

sys/lib/libunwind/Registers.hpp

247

void setIP(uint64_t value) { reg[REGNO_PPC32_SRR0] = value; }

sys/lib/libunwind/Registers.hpp

249

uint64_t getSP() const { return reg[REGNO_PPC32_R1]; }

sys/lib/libunwind/Registers.hpp

251

void setSP(uint64_t value) { reg[REGNO_PPC32_R1] = value; }

sys/lib/libunwind/Registers.hpp

272

uint32_t reg[REGNO_PPC32_SRR0 + 1];

sys/lib/libunwind/Registers.hpp

329

return reg[num];

sys/lib/libunwind/Registers.hpp

337

reg[num] = value;

sys/lib/libunwind/Registers.hpp

340

uint64_t getIP() const { return reg[REGNO_AARCH64_X30]; }

sys/lib/libunwind/Registers.hpp

342

void setIP(uint64_t value) { reg[REGNO_AARCH64_X30] = value; }

sys/lib/libunwind/Registers.hpp

344

uint64_t getSP() const { return reg[REGNO_AARCH64_SP]; }

sys/lib/libunwind/Registers.hpp

346

void setSP(uint64_t value) { reg[REGNO_AARCH64_SP] = value; }

sys/lib/libunwind/Registers.hpp

360

uint64_t reg[REGNO_AARCH64_SP + 1];

sys/lib/libunwind/Registers.hpp

418

return reg[num];

sys/lib/libunwind/Registers.hpp

423

reg[num] = value;

sys/lib/libunwind/Registers.hpp

426

uint64_t getIP() const { return reg[REGNO_ARM32_R15]; }

sys/lib/libunwind/Registers.hpp

428

void setIP(uint64_t value) { reg[REGNO_ARM32_R15] = value; }

sys/lib/libunwind/Registers.hpp

430

uint64_t getSP() const { return reg[REGNO_ARM32_SP]; }

sys/lib/libunwind/Registers.hpp

432

void setSP(uint64_t value) { reg[REGNO_ARM32_SP] = value; }

sys/lib/libunwind/Registers.hpp

492

uint32_t reg[REGNO_ARM32_SPSR + 1];

sys/lib/libunwind/Registers.hpp

52

return reg[num];

sys/lib/libunwind/Registers.hpp

538

return reg[num];

sys/lib/libunwind/Registers.hpp

543

reg[num] = value;

sys/lib/libunwind/Registers.hpp

546

uint64_t getIP() const { return reg[REGNO_VAX_R15]; }

sys/lib/libunwind/Registers.hpp

548

void setIP(uint64_t value) { reg[REGNO_VAX_R15] = value; }

sys/lib/libunwind/Registers.hpp

550

uint64_t getSP() const { return reg[REGNO_VAX_R14]; }

sys/lib/libunwind/Registers.hpp

552

void setSP(uint64_t value) { reg[REGNO_VAX_R14] = value; }

sys/lib/libunwind/Registers.hpp

564

uint32_t reg[REGNO_VAX_PSW + 1];

sys/lib/libunwind/Registers.hpp

57

reg[num] = value;

sys/lib/libunwind/Registers.hpp

60

uint32_t getIP() const { return reg[REGNO_X86_EIP]; }

sys/lib/libunwind/Registers.hpp

617

return reg[num];

sys/lib/libunwind/Registers.hpp

62

void setIP(uint32_t value) { reg[REGNO_X86_EIP] = value; }

sys/lib/libunwind/Registers.hpp

622

reg[num] = value;

sys/lib/libunwind/Registers.hpp

625

uint64_t getIP() const { return reg[REGNO_M68K_PC]; }

sys/lib/libunwind/Registers.hpp

627

void setIP(uint64_t value) { reg[REGNO_M68K_PC] = value; }

sys/lib/libunwind/Registers.hpp

629

uint64_t getSP() const { return reg[REGNO_M68K_A7]; }

sys/lib/libunwind/Registers.hpp

631

void setSP(uint64_t value) { reg[REGNO_M68K_A7] = value; }

sys/lib/libunwind/Registers.hpp

64

uint32_t getSP() const { return reg[REGNO_X86_ESP]; }

sys/lib/libunwind/Registers.hpp

648

uint32_t reg[REGNO_M68K_PC + 1];

sys/lib/libunwind/Registers.hpp

66

void setSP(uint32_t value) { reg[REGNO_X86_ESP] = value; }

sys/lib/libunwind/Registers.hpp

712

return reg[num];

sys/lib/libunwind/Registers.hpp

717

reg[num] = value;

sys/lib/libunwind/Registers.hpp

720

uint64_t getIP() const { return reg[REGNO_SH3_PC]; }

sys/lib/libunwind/Registers.hpp

722

void setIP(uint64_t value) { reg[REGNO_SH3_PC] = value; }

sys/lib/libunwind/Registers.hpp

724

uint64_t getSP() const { return reg[REGNO_SH3_R15]; }

sys/lib/libunwind/Registers.hpp

726

void setSP(uint64_t value) { reg[REGNO_SH3_R15] = value; }

sys/lib/libunwind/Registers.hpp

735

uint32_t reg[REGNO_SH3_SR + 1];

sys/lib/libunwind/Registers.hpp

76

uint32_t reg[REGNO_X86_EIP + 1];

sys/lib/libunwind/Registers.hpp

776

return reg[num];

sys/lib/libunwind/Registers.hpp

781

reg[num] = value;

sys/lib/libunwind/Registers.hpp

784

uint64_t getIP() const { return reg[REGNO_SPARC64_PC]; }

sys/lib/libunwind/Registers.hpp

786

void setIP(uint64_t value) { reg[REGNO_SPARC64_PC] = value; }

sys/lib/libunwind/Registers.hpp

788

uint64_t getSP() const { return reg[REGNO_SPARC64_R14]; }

sys/lib/libunwind/Registers.hpp

790

void setSP(uint64_t value) { reg[REGNO_SPARC64_R14] = value; }

sys/lib/libunwind/Registers.hpp

799

uint64_t reg[REGNO_SPARC64_PC + 1];

sys/lib/libunwind/Registers.hpp

840

return reg[num];

sys/lib/libunwind/Registers.hpp

845

reg[num] = value;

sys/lib/libunwind/Registers.hpp

848

uint64_t getIP() const { return reg[REGNO_SPARC_PC]; }

sys/lib/libunwind/Registers.hpp

850

void setIP(uint64_t value) { reg[REGNO_SPARC_PC] = value; }

sys/lib/libunwind/Registers.hpp

852

uint64_t getSP() const { return reg[REGNO_SPARC_R14]; }

sys/lib/libunwind/Registers.hpp

854

void setSP(uint64_t value) { reg[REGNO_SPARC_R14] = value; }

sys/lib/libunwind/Registers.hpp

863

uint32_t reg[REGNO_SPARC_PC + 1];

sys/lib/libunwind/Registers.hpp

905

return reg[num];

sys/lib/libunwind/Registers.hpp

913

reg[num] = value;

sys/lib/libunwind/Registers.hpp

916

uint64_t getIP() const { return reg[REGNO_ALPHA_PC]; }

sys/lib/libunwind/Registers.hpp

918

void setIP(uint64_t value) { reg[REGNO_ALPHA_PC] = value; }

sys/lib/libunwind/Registers.hpp

920

uint64_t getSP() const { return reg[REGNO_ALPHA_R30]; }

sys/lib/libunwind/Registers.hpp

922

void setSP(uint64_t value) { reg[REGNO_ALPHA_R30] = value; }

sys/lib/libunwind/Registers.hpp

937

uint64_t reg[REGNO_ALPHA_PC + 1];

sys/lib/libunwind/Registers.hpp

990

return reg[num];

sys/lib/libunwind/Registers.hpp

998

reg[num] = value;

sys/miscfs/procfs/procfs_vnops.c

909

vap->va_bytes = vap->va_size = sizeof(struct reg);

sys/net/bpfjit.c

144

uint32_t reg; /* saved A or X register */

sys/net/bpfjit.c

541

offsetof(struct bpfjit_stack, reg),

sys/net/bpfjit.c

640

offsetof(struct bpfjit_stack, reg));

sys/net/bpfjit.c

679

offsetof(struct bpfjit_stack, reg),

sys/net/bpfjit.c

784

offsetof(struct bpfjit_stack, reg));

sys/netipsec/key.c

7262

struct secreg *reg, *newreg = 0;

sys/netipsec/key.c

7277

LIST_FOREACH(reg, &key_misc.reglist[mhp->msg->sadb_msg_satype], chain) {

sys/netipsec/key.c

7278

if (reg->so == so) {

sys/netipsec/key.c

7397

struct secreg *reg;

sys/netipsec/key.c

7410

LIST_FOREACH(reg, &key_misc.reglist[i], chain) {

sys/netipsec/key.c

7411

if (reg->so == so) {

sys/netipsec/key.c

7412

LIST_REMOVE(reg, chain);

sys/netipsec/key.c

7417

if (reg != NULL)

sys/netipsec/key.c

7418

kmem_free(reg, sizeof(*reg));

sys/rump/dev/lib/libpci/rumpdev_pci.c

82

pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg)

sys/rump/dev/lib/libpci/rumpdev_pci.c

88

rumpcomp_pci_confread(bus, device, fun, reg, &rv);

sys/rump/dev/lib/libpci/rumpdev_pci.c

93

pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data)

sys/rump/dev/lib/libpci/rumpdev_pci.c

98

rumpcomp_pci_confwrite(bus, device, fun, reg, data);

sys/rump/librump/rumpvfs/rumpfs.c

180

} reg;

sys/rump/librump/rumpvfs/rumpfs.c

196

#define rn_readfd rn_u.reg.readfd

sys/rump/librump/rumpvfs/rumpfs.c

197

#define rn_writefd rn_u.reg.writefd

sys/rump/librump/rumpvfs/rumpfs.c

198

#define rn_offset rn_u.reg.offset

sys/sys/compat_stub.h

365

struct reg;

sys/sys/compat_stub.h

368

(struct lwp *, const struct reg *));

sys/sys/proc.h

592

sizeof(process_reg32) : sizeof(struct reg))

sys/sys/ptrace.h

212

struct reg;

sys/sys/ptrace.h

214

#define process_reg32 struct reg

sys/sys/ptrace.h

217

#define process_reg64 struct reg

sys/sys/ptrace.h

309

int process_read_regs(struct lwp *, struct reg *);

sys/sys/ptrace.h

338

int process_write_regs(struct lwp *, const struct reg *);

sys/sys/videoio.h

3275

u_int64_t reg;

tests/fs/puffs/h_dtfs/dtfs.h

62

} reg;

tests/fs/puffs/h_dtfs/dtfs.h

71

#define df_blocks u.reg.blocks

tests/fs/puffs/h_dtfs/dtfs.h

72

#define df_numblocks u.reg.numblocks

tests/fs/puffs/h_dtfs/dtfs.h

73

#define df_datalen u.reg.datalen

tests/kernel/arch/sh3/asm.h

44

#define MOVL_VAR(label, reg) \

tests/kernel/arch/sh3/asm.h

46

mov.l @(r0, r12), reg

tests/kernel/arch/sh3/asm.h

52

#define MOVL_VAR(label, reg) \

tests/kernel/arch/sh3/asm.h

53

mov.l label, reg; \

tests/lib/libc/sys/t_ptrace_amd64_wait.h

48

struct reg r;

tests/lib/libc/sys/t_ptrace_core_wait.h

220

struct reg r;

tests/lib/libc/sys/t_ptrace_i386_wait.h

45

struct reg r;

tests/lib/libc/sys/t_ptrace_register_wait.h

40

struct reg gpr;

tests/lib/libc/sys/t_ptrace_x86_wait.h

124

dbreg_preserve(int reg, enum dbreg_preserve_mode mode)

tests/lib/libc/sys/t_ptrace_x86_wait.h

1624

dbregs_dont_inherit_lwp(int reg)

tests/lib/libc/sys/t_ptrace_x86_wait.h

1682

r1.dr[reg] = (long)(intptr_t)check_happy;

tests/lib/libc/sys/t_ptrace_x86_wait.h

1684

reg, reg, r1.dr[0]);

tests/lib/libc/sys/t_ptrace_x86_wait.h

174

r1.dr[reg] = (long)(intptr_t)&watchme;

tests/lib/libc/sys/t_ptrace_x86_wait.h

176

reg, r1.dr[reg]);

tests/lib/libc/sys/t_ptrace_x86_wait.h

1792

dbregs_dont_inherit_execve(int reg)

tests/lib/libc/sys/t_ptrace_x86_wait.h

1839

r1.dr[reg] = (long)(intptr_t)check_happy;

tests/lib/libc/sys/t_ptrace_x86_wait.h

1841

reg, reg, r1.dr[reg]);

tests/lib/libc/sys/t_ptrace_x86_wait.h

2933

struct reg gpr;

tests/lib/libc/sys/t_ptrace_x86_wait.h

377

dbregs_trap_variable(int reg, int cond, int len, bool write)

tests/lib/libc/sys/t_ptrace_x86_wait.h

399

switch (reg) {

tests/lib/libc/sys/t_ptrace_x86_wait.h

456

r1.dr[reg] = (long)(intptr_t)&watchme;

tests/lib/libc/sys/t_ptrace_x86_wait.h

458

reg, reg, r1.dr[reg]);

usr.bin/dc/bcode.c

1523

v = stack_tos(&bmachine.reg[idx]);

usr.bin/dc/bcode.c

240

bmachine.reg = calloc(bmachine.reg_array_size,

usr.bin/dc/bcode.c

241

sizeof(bmachine.reg[0]));

usr.bin/dc/bcode.c

242

if (bmachine.reg == NULL)

usr.bin/dc/bcode.c

253

stack_init(&bmachine.reg[i]);

usr.bin/dc/bcode.c

49

struct stack *reg;

usr.bin/dc/bcode.c

808

v = stack_tos(&bmachine.reg[idx]);

usr.bin/dc/bcode.c

830

stack_set_tos(&bmachine.reg[idx], val);

usr.bin/dc/bcode.c

843

stack = &bmachine.reg[idx];

usr.bin/dc/bcode.c

867

stack_push(&bmachine.reg[idx], value);

usr.bin/dc/bcode.c

874

int reg;

usr.bin/dc/bcode.c

880

reg = readreg();

usr.bin/dc/bcode.c

881

if (reg >= 0) {

usr.bin/dc/bcode.c

891

stack = &bmachine.reg[reg];

usr.bin/dc/bcode.c

908

int reg;

usr.bin/dc/bcode.c

914

reg = readreg();

usr.bin/dc/bcode.c

915

if (reg >= 0) {

usr.bin/dc/bcode.c

932

stack = &bmachine.reg[reg];

usr.bin/find/function.c

1671

regex_t reg;

usr.bin/find/function.c

1687

rv = regcomp(&reg, lineregexp, REG_NOSUB|regcomp_flags|

usr.bin/find/function.c

1691

regerror(rv, &reg, errbuf, sizeof errbuf);

usr.bin/find/function.c

1696

new->regexp_data = reg;

usr.bin/pkill/pkill.c

128

regex_t reg;

usr.bin/pkill/pkill.c

308

if ((rv = regcomp(&reg, *argv, cflags)) != 0) {

usr.bin/pkill/pkill.c

309

(void)regerror(rv, &reg, buf, sizeof(buf));

usr.bin/pkill/pkill.c

335

rv = regexec(&reg, buf, 1, &regmatch, 0);

usr.bin/pkill/pkill.c

345

(void)regerror(rv, &reg, buf, sizeof(buf));

usr.bin/pkill/pkill.c

352

regfree(&reg);

usr.bin/scmdctl/common.c

191

uint8_t reg;

usr.bin/scmdctl/common.c

206

reg = SCMD_REG_MA_DRIVE + reg_index;

usr.bin/scmdctl/common.c

209

fprintf(stderr,"common_set_motor: reg_index: %d ; reg: %02X ; reg_v: %d\n",reg_index,reg,reg_v);

usr.bin/scmdctl/common.c

210

err = (*(fb->func_phy_write))(fd, debug, 0, reg, reg_v);

usr.bin/scmdctl/common.c

221

uint8_t reg, reg_index = 0, reg_offset = 0;

usr.bin/scmdctl/common.c

228

reg = SCMD_REG_MOTOR_A_INVERT;

usr.bin/scmdctl/common.c

230

reg = SCMD_REG_MOTOR_B_INVERT;

usr.bin/scmdctl/common.c

232

err = (*(fb->func_phy_read))(fd, debug, 0, reg, reg, &b);

usr.bin/scmdctl/common.c

235

err = (*(fb->func_phy_write))(fd, debug, 0, reg, b);

usr.bin/scmdctl/common.c

244

reg = SCMD_REG_INV_2_9 + reg_offset;

usr.bin/scmdctl/common.c

246

fprintf(stderr,"common_invert_motor: remote invert: motor_index: %d ; reg_offset: %d ; reg_index: %02X ; reg: %02X\n",motor_index,reg_offset,reg_index,reg);

usr.bin/scmdctl/common.c

247

err = (*(fb->func_phy_read))(fd, debug, 0, reg, reg, &b);

usr.bin/scmdctl/common.c

250

err = (*(fb->func_phy_write))(fd, debug, 0, reg, b);

usr.bin/scmdctl/common.c

263

uint8_t reg, reg_index = 0, reg_offset = 0;

usr.bin/scmdctl/common.c

279

reg = SCMD_REG_BRIDGE_SLV_L + reg_offset;

usr.bin/scmdctl/common.c

281

fprintf(stderr,"common_bridge_motor: remote bridge: module_index: %d ; reg_offset: %d ; reg_index: %02X ; reg: %02X\n",module_index,reg_offset,reg_index,reg);

usr.bin/scmdctl/common.c

282

err = (*(fb->func_phy_read))(fd, debug, 0, reg, reg, &b);

usr.bin/scmdctl/common.c

285

err = (*(fb->func_phy_write))(fd, debug, 0, reg, b);

usr.bin/scmdctl/common.c

428

uint8_t reg;

usr.bin/scmdctl/common.c

433

reg = SCMD_REG_LOCAL_USER_LOCK;

usr.bin/scmdctl/common.c

436

reg = SCMD_REG_LOCAL_MASTER_LOCK;

usr.bin/scmdctl/common.c

439

reg = SCMD_REG_USER_LOCK;

usr.bin/scmdctl/common.c

442

reg = SCMD_REG_MASTER_LOCK;

usr.bin/scmdctl/common.c

450

err = (*(fb->func_phy_read))(fd, debug, 0, reg, reg, &b);

usr.bin/scmdctl/common.c

461

uint8_t reg;

usr.bin/scmdctl/common.c

467

reg = SCMD_REG_LOCAL_USER_LOCK;

usr.bin/scmdctl/common.c

470

reg = SCMD_REG_LOCAL_MASTER_LOCK;

usr.bin/scmdctl/common.c

473

reg = SCMD_REG_USER_LOCK;

usr.bin/scmdctl/common.c

476

reg = SCMD_REG_MASTER_LOCK;

usr.bin/scmdctl/common.c

498

err = (*(fb->func_phy_write))(fd, debug, 0, reg, state);

usr.bin/scmdctl/i2cspi.c

106

i2cspi_read_register(int fd, bool debug, int a_module, uint8_t reg, uint8_t reg_end, uint8_t *r)

usr.bin/scmdctl/i2cspi.c

108

if (reg > SCMD_LAST_REG ||

usr.bin/scmdctl/i2cspi.c

112

if (reg_end < reg)

usr.bin/scmdctl/i2cspi.c

116

fprintf(stderr,"i2cspi_read_register: reg: %d ; reg_rend: %d ; rlen: %d\n",reg, reg_end, reg_end - reg + 1);

usr.bin/scmdctl/i2cspi.c

118

return i2cspi_phy_read_register(fd, debug, reg + (SCMD_REG_SIZE * a_module), reg_end - reg + 1, r);

usr.bin/scmdctl/i2cspi.c

122

i2cspi_write_register(int fd, bool debug, int a_module, uint8_t reg, uint8_t reg_v)

usr.bin/scmdctl/i2cspi.c

126

if (reg > SCMD_LAST_REG)

usr.bin/scmdctl/i2cspi.c

129

err = i2cspi_phy_write_register(fd, debug, reg + (SCMD_REG_SIZE * a_module), reg_v);

usr.bin/scmdctl/i2cspi.c

53

i2cspi_phy_read_register(int fd, bool debug, uint8_t reg, int rlen, uint8_t *buf)

usr.bin/scmdctl/i2cspi.c

60

err = lseek(fd, reg, SEEK_SET);

usr.bin/scmdctl/i2cspi.c

72

fprintf(stderr,"i2cspi_phy_read_register: reg: 0x%02X: rlen: %d: return err: %d\n",reg, rlen, err);

usr.bin/scmdctl/i2cspi.c

78

i2cspi_phy_write_register(int fd, bool debug, uint8_t reg, uint8_t buf)

usr.bin/scmdctl/i2cspi.c

82

err = lseek(fd, reg, SEEK_SET);

usr.bin/scmdctl/i2cspi.c

94

fprintf(stderr,"i2cspi_phy_write_register: reg: 0x%02X: return err: %d\n",reg, err);

usr.bin/scmdctl/scmdctl.c

164

uint8_t reg = 0, reg_e = 0, ur, ebus_s, lock_state;

usr.bin/scmdctl/scmdctl.c

368

reg = (uint8_t)strtoi(argv[3], NULL, 0, 0, 0x7e, &error);

usr.bin/scmdctl/scmdctl.c

377

reg = c;

usr.bin/scmdctl/scmdctl.c

379

reg_e = reg;

usr.bin/scmdctl/scmdctl.c

393

if (reg_e < reg) {

usr.bin/scmdctl/scmdctl.c

394

fprintf(stderr,"Register end can not be less than register start: %d %d\n\n", reg, reg_e);

usr.bin/scmdctl/scmdctl.c

399

error = uart_read_register(fd,debug,module,reg,reg_e,&register_shadow[reg]);

usr.bin/scmdctl/scmdctl.c

401

error = i2cspi_read_register(fd,debug,module,reg,reg_e,&register_shadow[reg]);

usr.bin/scmdctl/scmdctl.c

415

reg = (uint8_t)strtoi(argv[3], NULL, 0, 0, 0x7e, &error);

usr.bin/scmdctl/scmdctl.c

424

reg = c;

usr.bin/scmdctl/scmdctl.c

430

error = uart_write_register(fd,debug,module,reg,reg_value);

usr.bin/scmdctl/scmdctl.c

432

error = i2cspi_write_register(fd,debug,module,reg,reg_value);

usr.bin/scmdctl/scmdctl.c

590

for(int g = reg; g <= reg_e; g++)

usr.bin/scmdctl/uart.c

150

uart_phy_read_register(int fd, bool debug, uint8_t reg, uint8_t *buf)

usr.bin/scmdctl/uart.c

159

if (SCMD_IS_HOLE(reg)) {

usr.bin/scmdctl/uart.c

166

sprintf(cmdbuf, "R%02X\r\n", reg);

usr.bin/scmdctl/uart.c

175

reg = reg | 0x80;

usr.bin/scmdctl/uart.c

176

spi_t.sit_send = ®

usr.bin/scmdctl/uart.c

184

err,reg,reg & 0x7f);

usr.bin/scmdctl/uart.c

245

uart_phy_write_register(int fd, bool debug, uint8_t reg, uint8_t buf)

usr.bin/scmdctl/uart.c

253

if (SCMD_IS_HOLE(reg)) {

usr.bin/scmdctl/uart.c

259

sprintf(cmdbuf, "W%02X%02X\r\n", reg, buf);

usr.bin/scmdctl/uart.c

267

reg = reg & 0x7f;

usr.bin/scmdctl/uart.c

268

spi_t.sit_send = ®

usr.bin/scmdctl/uart.c

276

err,reg,reg & 0x7f);

usr.bin/scmdctl/uart.c

309

uart_local_read_register(int fd, bool debug, uint8_t reg, uint8_t reg_end, uint8_t *r)

usr.bin/scmdctl/uart.c

314

for(int q = reg, g = 0; q <= reg_end; q++, g++) {

usr.bin/scmdctl/uart.c

345

uart_remote_read_register(int fd, bool debug, int a_module, uint8_t reg, uint8_t reg_end, uint8_t *r)

usr.bin/scmdctl/uart.c

351

for(int q = reg, g = 0; q <= reg_end; q++, g++) {

usr.bin/scmdctl/uart.c

399

uart_read_register(int fd, bool debug, int a_module, uint8_t reg, uint8_t reg_end, uint8_t *r)

usr.bin/scmdctl/uart.c

403

if (reg > SCMD_LAST_REG ||

usr.bin/scmdctl/uart.c

407

if (reg_end < reg)

usr.bin/scmdctl/uart.c

413

err = uart_local_read_register(fd, debug, reg, reg_end, r);

usr.bin/scmdctl/uart.c

415

err = uart_remote_read_register(fd, debug, a_module, reg, reg_end, r);

usr.bin/scmdctl/uart.c

423

uart_remote_write_register(int fd, bool debug, int a_module, uint8_t reg, uint8_t reg_v)

usr.bin/scmdctl/uart.c

429

err = uart_set_view_port(fd, debug, a_module, reg);

usr.bin/scmdctl/uart.c

457

uart_write_register(int fd, bool debug, int a_module, uint8_t reg, uint8_t reg_v)

usr.bin/scmdctl/uart.c

461

if (reg > SCMD_LAST_REG)

usr.bin/scmdctl/uart.c

467

err = uart_phy_write_register(fd, debug, reg, reg_v);

usr.bin/scmdctl/uart.c

469

err = uart_remote_write_register(fd, debug, a_module, reg, reg_v);

usr.bin/script/script.c

385

consume(FILE *fp, off_t len, char *buf, int reg)

usr.bin/script/script.c

389

if (reg) {

usr.bin/script/script.c

448

int reg;

usr.bin/script/script.c

453

reg = S_ISREG(pst.st_mode);

usr.bin/script/script.c

455

for (nread = 0; !reg || nread < pst.st_size; nread += save_len) {

usr.bin/script/script.c

457

if (reg)

usr.bin/script/script.c

465

if (reg && stamp.scr_len >

usr.bin/script/script.c

480

(void)consume(fp, stamp.scr_len, buf, reg);

usr.bin/script/script.c

489

(void)consume(fp, stamp.scr_len, buf, reg);

usr.bin/script/script.c

493

(void)consume(fp, stamp.scr_len, buf, reg);

usr.bin/vgrind/RETEST/retest.c

54

char reg[132];

usr.bin/vgrind/RETEST/retest.c

63

scanf ("%131s", reg);

usr.bin/vgrind/RETEST/retest.c

64

ireg = convexp(reg);

usr.sbin/cpuctl/arch/i386.c

1914

const uint64_t reg = rdmsr(MSR_NB_CFG);

usr.sbin/cpuctl/arch/i386.c

1915

if ((reg & NB_CFG_INITAPICCPUIDLO) == 0) {

usr.sbin/emcfanctl/emcfanctl.h

74

const uint8_t reg;

usr.sbin/emcfanctl/emcfanctlconst.h

1000

.reg = 0x4F

usr.sbin/emcfanctl/emcfanctlconst.h

1004

.reg = 0x50

usr.sbin/emcfanctl/emcfanctlconst.h

1008

.reg = 0x51

usr.sbin/emcfanctl/emcfanctlconst.h

1012

.reg = 0x52

usr.sbin/emcfanctl/emcfanctlconst.h

1016

.reg = 0x53

usr.sbin/emcfanctl/emcfanctlconst.h

1020

.reg = 0x54

usr.sbin/emcfanctl/emcfanctlconst.h

1024

.reg = 0x55

usr.sbin/emcfanctl/emcfanctlconst.h

1028

.reg = 0x56

usr.sbin/emcfanctl/emcfanctlconst.h

1032

.reg = 0x57

usr.sbin/emcfanctl/emcfanctlconst.h

1036

.reg = 0x58

usr.sbin/emcfanctl/emcfanctlconst.h

1040

.reg = 0x59

usr.sbin/emcfanctl/emcfanctlconst.h

1044

.reg = 0x5A

usr.sbin/emcfanctl/emcfanctlconst.h

1048

.reg = 0x5B

usr.sbin/emcfanctl/emcfanctlconst.h

1052

.reg = 0x5C

usr.sbin/emcfanctl/emcfanctlconst.h

1056

.reg = 0x5D

usr.sbin/emcfanctl/emcfanctlconst.h

1060

.reg = 0x5E

usr.sbin/emcfanctl/emcfanctlconst.h

1064

.reg = 0x5F

usr.sbin/emcfanctl/emcfanctlconst.h

1068

.reg = 0x60

usr.sbin/emcfanctl/emcfanctlconst.h

1072

.reg = 0x61

usr.sbin/emcfanctl/emcfanctlconst.h

1076

.reg = 0x62

usr.sbin/emcfanctl/emcfanctlconst.h

1080

.reg = 0x63

usr.sbin/emcfanctl/emcfanctlconst.h

1084

.reg = 0x64

usr.sbin/emcfanctl/emcfanctlconst.h

1088

.reg = 0x65

usr.sbin/emcfanctl/emcfanctlconst.h

1092

.reg = 0x66

usr.sbin/emcfanctl/emcfanctlconst.h

1096

.reg = 0x67

usr.sbin/emcfanctl/emcfanctlconst.h

1100

.reg = 0x68

usr.sbin/emcfanctl/emcfanctlconst.h

1104

.reg = 0x69

usr.sbin/emcfanctl/emcfanctlconst.h

1108

.reg = 0x6A

usr.sbin/emcfanctl/emcfanctlconst.h

1112

.reg = 0x6B

usr.sbin/emcfanctl/emcfanctlconst.h

1116

.reg = 0x6C

usr.sbin/emcfanctl/emcfanctlconst.h

1120

.reg = 0x6D

usr.sbin/emcfanctl/emcfanctlconst.h

1124

.reg = 0x6E

usr.sbin/emcfanctl/emcfanctlconst.h

1128

.reg = 0x6F

usr.sbin/emcfanctl/emcfanctlconst.h

1132

.reg = 0x70

usr.sbin/emcfanctl/emcfanctlconst.h

1136

.reg = 0x71

usr.sbin/emcfanctl/emcfanctlconst.h

1140

.reg = 0x72

usr.sbin/emcfanctl/emcfanctlconst.h

1144

.reg = 0x73

usr.sbin/emcfanctl/emcfanctlconst.h

1148

.reg = 0x74

usr.sbin/emcfanctl/emcfanctlconst.h

1152

.reg = 0x75

usr.sbin/emcfanctl/emcfanctlconst.h

1156

.reg = 0x76

usr.sbin/emcfanctl/emcfanctlconst.h

1160

.reg = 0x77

usr.sbin/emcfanctl/emcfanctlconst.h

1164

.reg = 0x78

usr.sbin/emcfanctl/emcfanctlconst.h

1168

.reg = 0x79

usr.sbin/emcfanctl/emcfanctlconst.h

1172

.reg = 0xE1

usr.sbin/emcfanctl/emcfanctlconst.h

1176

.reg = 0xE2

usr.sbin/emcfanctl/emcfanctlconst.h

1180

.reg = 0xE3

usr.sbin/emcfanctl/emcfanctlconst.h

1184

.reg = 0xE4

usr.sbin/emcfanctl/emcfanctlconst.h

1188

.reg = 0xE5

usr.sbin/emcfanctl/emcfanctlconst.h

1192

.reg = 0xE6

usr.sbin/emcfanctl/emcfanctlconst.h

1196

.reg = 0xEF

usr.sbin/emcfanctl/emcfanctlconst.h

1200

.reg = 0xFC

usr.sbin/emcfanctl/emcfanctlconst.h

1204

.reg = 0xFD

usr.sbin/emcfanctl/emcfanctlconst.h

1208

.reg = 0xFE

usr.sbin/emcfanctl/emcfanctlconst.h

1212

.reg = 0xFF

usr.sbin/emcfanctl/emcfanctlconst.h

1219

.reg = 0x00

usr.sbin/emcfanctl/emcfanctlconst.h

1223

.reg = 0x01

usr.sbin/emcfanctl/emcfanctlconst.h

1227

.reg = 0x02

usr.sbin/emcfanctl/emcfanctlconst.h

1231

.reg = 0x03

usr.sbin/emcfanctl/emcfanctlconst.h

1235

.reg = 0x04

usr.sbin/emcfanctl/emcfanctlconst.h

1239

.reg = 0x05

usr.sbin/emcfanctl/emcfanctlconst.h

1243

.reg = 0x06

usr.sbin/emcfanctl/emcfanctlconst.h

1247

.reg = 0x07

usr.sbin/emcfanctl/emcfanctlconst.h

1251

.reg = 0x08

usr.sbin/emcfanctl/emcfanctlconst.h

1255

.reg = 0x09

usr.sbin/emcfanctl/emcfanctlconst.h

1259

.reg = 0x0A

usr.sbin/emcfanctl/emcfanctlconst.h

1263

.reg = 0x0C

usr.sbin/emcfanctl/emcfanctlconst.h

1267

.reg = 0x0D

usr.sbin/emcfanctl/emcfanctlconst.h

1271

.reg = 0x0E

usr.sbin/emcfanctl/emcfanctlconst.h

1275

.reg = 0x0F

usr.sbin/emcfanctl/emcfanctlconst.h

1279

.reg = 0x10

usr.sbin/emcfanctl/emcfanctlconst.h

1283

.reg = 0x14

usr.sbin/emcfanctl/emcfanctlconst.h

1287

.reg = 0x15

usr.sbin/emcfanctl/emcfanctlconst.h

1291

.reg = 0x16

usr.sbin/emcfanctl/emcfanctlconst.h

1295

.reg = 0x17

usr.sbin/emcfanctl/emcfanctlconst.h

1299

.reg = 0x19

usr.sbin/emcfanctl/emcfanctlconst.h

1303

.reg = 0x1A

usr.sbin/emcfanctl/emcfanctlconst.h

1307

.reg = 0x1B

usr.sbin/emcfanctl/emcfanctlconst.h

1311

.reg = 0x1C

usr.sbin/emcfanctl/emcfanctlconst.h

1315

.reg = 0x1D

usr.sbin/emcfanctl/emcfanctlconst.h

1319

.reg = 0x1F

usr.sbin/emcfanctl/emcfanctlconst.h

1323

.reg = 0x20

usr.sbin/emcfanctl/emcfanctlconst.h

1327

.reg = 0x21

usr.sbin/emcfanctl/emcfanctlconst.h

1331

.reg = 0x22

usr.sbin/emcfanctl/emcfanctlconst.h

1335

.reg = 0x23

usr.sbin/emcfanctl/emcfanctlconst.h

1339

.reg = 0x24

usr.sbin/emcfanctl/emcfanctlconst.h

1343

.reg = 0x25

usr.sbin/emcfanctl/emcfanctlconst.h

1347

.reg = 0x26

usr.sbin/emcfanctl/emcfanctlconst.h

1351

.reg = 0x27

usr.sbin/emcfanctl/emcfanctlconst.h

1355

.reg = 0x28

usr.sbin/emcfanctl/emcfanctlconst.h

1359

.reg = 0x29

usr.sbin/emcfanctl/emcfanctlconst.h

1363

.reg = 0x2A

usr.sbin/emcfanctl/emcfanctlconst.h

1367

.reg = 0x2B

usr.sbin/emcfanctl/emcfanctlconst.h

1371

.reg = 0x30

usr.sbin/emcfanctl/emcfanctlconst.h

1375

.reg = 0x31

usr.sbin/emcfanctl/emcfanctlconst.h

1379

.reg = 0x32

usr.sbin/emcfanctl/emcfanctlconst.h

1383

.reg = 0x33

usr.sbin/emcfanctl/emcfanctlconst.h

1387

.reg = 0x34

usr.sbin/emcfanctl/emcfanctlconst.h

1391

.reg = 0x35

usr.sbin/emcfanctl/emcfanctlconst.h

1395

.reg = 0x38

usr.sbin/emcfanctl/emcfanctlconst.h

1399

.reg = 0x39

usr.sbin/emcfanctl/emcfanctlconst.h

1403

.reg = 0x3A

usr.sbin/emcfanctl/emcfanctlconst.h

1407

.reg = 0x3B

usr.sbin/emcfanctl/emcfanctlconst.h

1411

.reg = 0x3C

usr.sbin/emcfanctl/emcfanctlconst.h

1415

.reg = 0x3D

usr.sbin/emcfanctl/emcfanctlconst.h

1419

.reg = 0x40

usr.sbin/emcfanctl/emcfanctlconst.h

1423

.reg = 0x41

usr.sbin/emcfanctl/emcfanctlconst.h

1427

.reg = 0x42

usr.sbin/emcfanctl/emcfanctlconst.h

1431

.reg = 0x43

usr.sbin/emcfanctl/emcfanctlconst.h

1435

.reg = 0x45

usr.sbin/emcfanctl/emcfanctlconst.h

1439

.reg = 0x46

usr.sbin/emcfanctl/emcfanctlconst.h

1443

.reg = 0x47

usr.sbin/emcfanctl/emcfanctlconst.h

1447

.reg = 0x48

usr.sbin/emcfanctl/emcfanctlconst.h

1451

.reg = 0x49

usr.sbin/emcfanctl/emcfanctlconst.h

1455

.reg = 0x4A

usr.sbin/emcfanctl/emcfanctlconst.h

1459

.reg = 0x4B

usr.sbin/emcfanctl/emcfanctlconst.h

1463

.reg = 0x4C

usr.sbin/emcfanctl/emcfanctlconst.h

1467

.reg = 0x4D

usr.sbin/emcfanctl/emcfanctlconst.h

1471

.reg = 0x4E

usr.sbin/emcfanctl/emcfanctlconst.h

1475

.reg = 0x4F

usr.sbin/emcfanctl/emcfanctlconst.h

1479

.reg = 0x50

usr.sbin/emcfanctl/emcfanctlconst.h

1483

.reg = 0x51

usr.sbin/emcfanctl/emcfanctlconst.h

1487

.reg = 0x52

usr.sbin/emcfanctl/emcfanctlconst.h

1491

.reg = 0x53

usr.sbin/emcfanctl/emcfanctlconst.h

1495

.reg = 0x54

usr.sbin/emcfanctl/emcfanctlconst.h

1499

.reg = 0x55

usr.sbin/emcfanctl/emcfanctlconst.h

1503

.reg = 0x56

usr.sbin/emcfanctl/emcfanctlconst.h

1507

.reg = 0x57

usr.sbin/emcfanctl/emcfanctlconst.h

1511

.reg = 0x58

usr.sbin/emcfanctl/emcfanctlconst.h

1515

.reg = 0x59

usr.sbin/emcfanctl/emcfanctlconst.h

1519

.reg = 0x5A

usr.sbin/emcfanctl/emcfanctlconst.h

1523

.reg = 0x5B

usr.sbin/emcfanctl/emcfanctlconst.h

1527

.reg = 0x5C

usr.sbin/emcfanctl/emcfanctlconst.h

1531

.reg = 0x5D

usr.sbin/emcfanctl/emcfanctlconst.h

1535

.reg = 0x5E

usr.sbin/emcfanctl/emcfanctlconst.h

1539

.reg = 0x5F

usr.sbin/emcfanctl/emcfanctlconst.h

1543

.reg = 0x60

usr.sbin/emcfanctl/emcfanctlconst.h

1547

.reg = 0x61

usr.sbin/emcfanctl/emcfanctlconst.h

1551

.reg = 0x62

usr.sbin/emcfanctl/emcfanctlconst.h

1555

.reg = 0x63

usr.sbin/emcfanctl/emcfanctlconst.h

1559

.reg = 0x64

usr.sbin/emcfanctl/emcfanctlconst.h

1563

.reg = 0x65

usr.sbin/emcfanctl/emcfanctlconst.h

1567

.reg = 0x66

usr.sbin/emcfanctl/emcfanctlconst.h

1571

.reg = 0x67

usr.sbin/emcfanctl/emcfanctlconst.h

1575

.reg = 0x68

usr.sbin/emcfanctl/emcfanctlconst.h

1579

.reg = 0x69

usr.sbin/emcfanctl/emcfanctlconst.h

1583

.reg = 0x6A

usr.sbin/emcfanctl/emcfanctlconst.h

1587

.reg = 0x6B

usr.sbin/emcfanctl/emcfanctlconst.h

1591

.reg = 0x6C

usr.sbin/emcfanctl/emcfanctlconst.h

1595

.reg = 0x6D

usr.sbin/emcfanctl/emcfanctlconst.h

1599

.reg = 0x6E

usr.sbin/emcfanctl/emcfanctlconst.h

1603

.reg = 0x6F

usr.sbin/emcfanctl/emcfanctlconst.h

1607

.reg = 0x70

usr.sbin/emcfanctl/emcfanctlconst.h

1611

.reg = 0x71

usr.sbin/emcfanctl/emcfanctlconst.h

1615

.reg = 0x72

usr.sbin/emcfanctl/emcfanctlconst.h

1619

.reg = 0x73

usr.sbin/emcfanctl/emcfanctlconst.h

1623

.reg = 0x74

usr.sbin/emcfanctl/emcfanctlconst.h

1627

.reg = 0x75

usr.sbin/emcfanctl/emcfanctlconst.h

1631

.reg = 0x76

usr.sbin/emcfanctl/emcfanctlconst.h

1635

.reg = 0x77

usr.sbin/emcfanctl/emcfanctlconst.h

1639

.reg = 0x78

usr.sbin/emcfanctl/emcfanctlconst.h

1643

.reg = 0x79

usr.sbin/emcfanctl/emcfanctlconst.h

1647

.reg = 0x80

usr.sbin/emcfanctl/emcfanctlconst.h

1651

.reg = 0x81

usr.sbin/emcfanctl/emcfanctlconst.h

1655

.reg = 0x82

usr.sbin/emcfanctl/emcfanctlconst.h

1659

.reg = 0x83

usr.sbin/emcfanctl/emcfanctlconst.h

1663

.reg = 0x85

usr.sbin/emcfanctl/emcfanctlconst.h

1667

.reg = 0x86

usr.sbin/emcfanctl/emcfanctlconst.h

1671

.reg = 0x87

usr.sbin/emcfanctl/emcfanctlconst.h

1675

.reg = 0x88

usr.sbin/emcfanctl/emcfanctlconst.h

1679

.reg = 0x89

usr.sbin/emcfanctl/emcfanctlconst.h

1683

.reg = 0x8A

usr.sbin/emcfanctl/emcfanctlconst.h

1687

.reg = 0x8B

usr.sbin/emcfanctl/emcfanctlconst.h

1691

.reg = 0x8C

usr.sbin/emcfanctl/emcfanctlconst.h

1695

.reg = 0x8D

usr.sbin/emcfanctl/emcfanctlconst.h

1699

.reg = 0x8E

usr.sbin/emcfanctl/emcfanctlconst.h

1703

.reg = 0x8F

usr.sbin/emcfanctl/emcfanctlconst.h

1707

.reg = 0x90

usr.sbin/emcfanctl/emcfanctlconst.h

1711

.reg = 0x91

usr.sbin/emcfanctl/emcfanctlconst.h

1715

.reg = 0x92

usr.sbin/emcfanctl/emcfanctlconst.h

1719

.reg = 0x93

usr.sbin/emcfanctl/emcfanctlconst.h

1723

.reg = 0x94

usr.sbin/emcfanctl/emcfanctlconst.h

1727

.reg = 0x95

usr.sbin/emcfanctl/emcfanctlconst.h

1731

.reg = 0x96

usr.sbin/emcfanctl/emcfanctlconst.h

1735

.reg = 0x97

usr.sbin/emcfanctl/emcfanctlconst.h

1739

.reg = 0x98

usr.sbin/emcfanctl/emcfanctlconst.h

1743

.reg = 0x99

usr.sbin/emcfanctl/emcfanctlconst.h

1747

.reg = 0x9A

usr.sbin/emcfanctl/emcfanctlconst.h

1751

.reg = 0x9B

usr.sbin/emcfanctl/emcfanctlconst.h

1755

.reg = 0x9C

usr.sbin/emcfanctl/emcfanctlconst.h

1759

.reg = 0x9D

usr.sbin/emcfanctl/emcfanctlconst.h

1763

.reg = 0x9E

usr.sbin/emcfanctl/emcfanctlconst.h

1767

.reg = 0x9F

usr.sbin/emcfanctl/emcfanctlconst.h

1771

.reg = 0xA0

usr.sbin/emcfanctl/emcfanctlconst.h

1775

.reg = 0xA1

usr.sbin/emcfanctl/emcfanctlconst.h

1779

.reg = 0xA2

usr.sbin/emcfanctl/emcfanctlconst.h

1783

.reg = 0xA3

usr.sbin/emcfanctl/emcfanctlconst.h

1787

.reg = 0xA4

usr.sbin/emcfanctl/emcfanctlconst.h

1791

.reg = 0xA5

usr.sbin/emcfanctl/emcfanctlconst.h

1795

.reg = 0xA6

usr.sbin/emcfanctl/emcfanctlconst.h

1799

.reg = 0xA7

usr.sbin/emcfanctl/emcfanctlconst.h

1803

.reg = 0xA8

usr.sbin/emcfanctl/emcfanctlconst.h

1807

.reg = 0xA9

usr.sbin/emcfanctl/emcfanctlconst.h

1811

.reg = 0xAA

usr.sbin/emcfanctl/emcfanctlconst.h

1815

.reg = 0xAB

usr.sbin/emcfanctl/emcfanctlconst.h

1819

.reg = 0xAC

usr.sbin/emcfanctl/emcfanctlconst.h

1823

.reg = 0xAD

usr.sbin/emcfanctl/emcfanctlconst.h

1827

.reg = 0xAE

usr.sbin/emcfanctl/emcfanctlconst.h

1831

.reg = 0xAF

usr.sbin/emcfanctl/emcfanctlconst.h

1835

.reg = 0xB0

usr.sbin/emcfanctl/emcfanctlconst.h

1839

.reg = 0xB1

usr.sbin/emcfanctl/emcfanctlconst.h

1843

.reg = 0xB2

usr.sbin/emcfanctl/emcfanctlconst.h

1847

.reg = 0xB3

usr.sbin/emcfanctl/emcfanctlconst.h

1851

.reg = 0xB4

usr.sbin/emcfanctl/emcfanctlconst.h

1855

.reg = 0xB5

usr.sbin/emcfanctl/emcfanctlconst.h

1859

.reg = 0xB6

usr.sbin/emcfanctl/emcfanctlconst.h

1863

.reg = 0xB7

usr.sbin/emcfanctl/emcfanctlconst.h

1867

.reg = 0xB8

usr.sbin/emcfanctl/emcfanctlconst.h

1871

.reg = 0xB9

usr.sbin/emcfanctl/emcfanctlconst.h

1875

.reg = 0xE0

usr.sbin/emcfanctl/emcfanctlconst.h

1879

.reg = 0xE1

usr.sbin/emcfanctl/emcfanctlconst.h

1883

.reg = 0xE2

usr.sbin/emcfanctl/emcfanctlconst.h

1887

.reg = 0xE3

usr.sbin/emcfanctl/emcfanctlconst.h

1891

.reg = 0xE4

usr.sbin/emcfanctl/emcfanctlconst.h

1895

.reg = 0xE5

usr.sbin/emcfanctl/emcfanctlconst.h

1899

.reg = 0xE6

usr.sbin/emcfanctl/emcfanctlconst.h

190

.reg = 0x00

usr.sbin/emcfanctl/emcfanctlconst.h

1903

.reg = 0xEF

usr.sbin/emcfanctl/emcfanctlconst.h

1907

.reg = 0xFC

usr.sbin/emcfanctl/emcfanctlconst.h

1911

.reg = 0xFD

usr.sbin/emcfanctl/emcfanctlconst.h

1915

.reg = 0xFE

usr.sbin/emcfanctl/emcfanctlconst.h

1919

.reg = 0xFF

usr.sbin/emcfanctl/emcfanctlconst.h

1926

.reg = 0x00

usr.sbin/emcfanctl/emcfanctlconst.h

1930

.reg = 0x01

usr.sbin/emcfanctl/emcfanctlconst.h

1934

.reg = 0x02

usr.sbin/emcfanctl/emcfanctlconst.h

1938

.reg = 0x03

usr.sbin/emcfanctl/emcfanctlconst.h

194

.reg = 0x01

usr.sbin/emcfanctl/emcfanctlconst.h

1942

.reg = 0x04

usr.sbin/emcfanctl/emcfanctlconst.h

1946

.reg = 0x05

usr.sbin/emcfanctl/emcfanctlconst.h

1950

.reg = 0x06

usr.sbin/emcfanctl/emcfanctlconst.h

1954

.reg = 0x07

usr.sbin/emcfanctl/emcfanctlconst.h

1958

.reg = 0x08

usr.sbin/emcfanctl/emcfanctlconst.h

1962

.reg = 0x09

usr.sbin/emcfanctl/emcfanctlconst.h

1966

.reg = 0x0A

usr.sbin/emcfanctl/emcfanctlconst.h

1970

.reg = 0x0C

usr.sbin/emcfanctl/emcfanctlconst.h

1974

.reg = 0x0D

usr.sbin/emcfanctl/emcfanctlconst.h

1978

.reg = 0x0E

usr.sbin/emcfanctl/emcfanctlconst.h

198

.reg = 0x02

usr.sbin/emcfanctl/emcfanctlconst.h

1982

.reg = 0x0F

usr.sbin/emcfanctl/emcfanctlconst.h

1986

.reg = 0x10

usr.sbin/emcfanctl/emcfanctlconst.h

1990

.reg = 0x14

usr.sbin/emcfanctl/emcfanctlconst.h

1994

.reg = 0x15

usr.sbin/emcfanctl/emcfanctlconst.h

1998

.reg = 0x16

usr.sbin/emcfanctl/emcfanctlconst.h

2002

.reg = 0x17

usr.sbin/emcfanctl/emcfanctlconst.h

2006

.reg = 0x19

usr.sbin/emcfanctl/emcfanctlconst.h

2010

.reg = 0x1A

usr.sbin/emcfanctl/emcfanctlconst.h

2014

.reg = 0x1B

usr.sbin/emcfanctl/emcfanctlconst.h

2018

.reg = 0x1C

usr.sbin/emcfanctl/emcfanctlconst.h

202

.reg = 0x03

usr.sbin/emcfanctl/emcfanctlconst.h

2022

.reg = 0x1D

usr.sbin/emcfanctl/emcfanctlconst.h

2026

.reg = 0x1F

usr.sbin/emcfanctl/emcfanctlconst.h

2030

.reg = 0x20

usr.sbin/emcfanctl/emcfanctlconst.h

2034

.reg = 0x21

usr.sbin/emcfanctl/emcfanctlconst.h

2038

.reg = 0x22

usr.sbin/emcfanctl/emcfanctlconst.h

2042

.reg = 0x23

usr.sbin/emcfanctl/emcfanctlconst.h

2046

.reg = 0x24

usr.sbin/emcfanctl/emcfanctlconst.h

2050

.reg = 0x25

usr.sbin/emcfanctl/emcfanctlconst.h

2054

.reg = 0x26

usr.sbin/emcfanctl/emcfanctlconst.h

2058

.reg = 0x27

usr.sbin/emcfanctl/emcfanctlconst.h

206

.reg = 0x04

usr.sbin/emcfanctl/emcfanctlconst.h

2062

.reg = 0x28

usr.sbin/emcfanctl/emcfanctlconst.h

2066

.reg = 0x29

usr.sbin/emcfanctl/emcfanctlconst.h

2070

.reg = 0x2A

usr.sbin/emcfanctl/emcfanctlconst.h

2074

.reg = 0x2B

usr.sbin/emcfanctl/emcfanctlconst.h

2078

.reg = 0x2C

usr.sbin/emcfanctl/emcfanctlconst.h

2082

.reg = 0x2D

usr.sbin/emcfanctl/emcfanctlconst.h

2086

.reg = 0x2E

usr.sbin/emcfanctl/emcfanctlconst.h

2090

.reg = 0x2F

usr.sbin/emcfanctl/emcfanctlconst.h

2094

.reg = 0x30

usr.sbin/emcfanctl/emcfanctlconst.h

2098

.reg = 0x31

usr.sbin/emcfanctl/emcfanctlconst.h

210

.reg = 0x05

usr.sbin/emcfanctl/emcfanctlconst.h

2102

.reg = 0x32

usr.sbin/emcfanctl/emcfanctlconst.h

2106

.reg = 0x33

usr.sbin/emcfanctl/emcfanctlconst.h

2110

.reg = 0x34

usr.sbin/emcfanctl/emcfanctlconst.h

2114

.reg = 0x35

usr.sbin/emcfanctl/emcfanctlconst.h

2118

.reg = 0x38

usr.sbin/emcfanctl/emcfanctlconst.h

2122

.reg = 0x39

usr.sbin/emcfanctl/emcfanctlconst.h

2126

.reg = 0x3A

usr.sbin/emcfanctl/emcfanctlconst.h

2130

.reg = 0x3B

usr.sbin/emcfanctl/emcfanctlconst.h

2134

.reg = 0x3C

usr.sbin/emcfanctl/emcfanctlconst.h

2138

.reg = 0x3D

usr.sbin/emcfanctl/emcfanctlconst.h

214

.reg = 0x07

usr.sbin/emcfanctl/emcfanctlconst.h

2142

.reg = 0x40

usr.sbin/emcfanctl/emcfanctlconst.h

2146

.reg = 0x41

usr.sbin/emcfanctl/emcfanctlconst.h

2150

.reg = 0x42

usr.sbin/emcfanctl/emcfanctlconst.h

2154

.reg = 0x43

usr.sbin/emcfanctl/emcfanctlconst.h

2158

.reg = 0x45

usr.sbin/emcfanctl/emcfanctlconst.h

2162

.reg = 0x46

usr.sbin/emcfanctl/emcfanctlconst.h

2166

.reg = 0x47

usr.sbin/emcfanctl/emcfanctlconst.h

2170

.reg = 0x48

usr.sbin/emcfanctl/emcfanctlconst.h

2174

.reg = 0x49

usr.sbin/emcfanctl/emcfanctlconst.h

2178

.reg = 0x4A

usr.sbin/emcfanctl/emcfanctlconst.h

218

.reg = 0x08

usr.sbin/emcfanctl/emcfanctlconst.h

2182

.reg = 0x4B

usr.sbin/emcfanctl/emcfanctlconst.h

2186

.reg = 0x4C

usr.sbin/emcfanctl/emcfanctlconst.h

2190

.reg = 0x4D

usr.sbin/emcfanctl/emcfanctlconst.h

2194

.reg = 0x4E

usr.sbin/emcfanctl/emcfanctlconst.h

2198

.reg = 0x4F

usr.sbin/emcfanctl/emcfanctlconst.h

2202

.reg = 0x50

usr.sbin/emcfanctl/emcfanctlconst.h

2206

.reg = 0x51

usr.sbin/emcfanctl/emcfanctlconst.h

2210

.reg = 0x52

usr.sbin/emcfanctl/emcfanctlconst.h

2214

.reg = 0x53

usr.sbin/emcfanctl/emcfanctlconst.h

2218

.reg = 0x54

usr.sbin/emcfanctl/emcfanctlconst.h

222

.reg = 0x09

usr.sbin/emcfanctl/emcfanctlconst.h

2222

.reg = 0x55

usr.sbin/emcfanctl/emcfanctlconst.h

2226

.reg = 0x56

usr.sbin/emcfanctl/emcfanctlconst.h

2230

.reg = 0x57

usr.sbin/emcfanctl/emcfanctlconst.h

2234

.reg = 0x58

usr.sbin/emcfanctl/emcfanctlconst.h

2238

.reg = 0x59

usr.sbin/emcfanctl/emcfanctlconst.h

2242

.reg = 0x5A

usr.sbin/emcfanctl/emcfanctlconst.h

2246

.reg = 0x5B

usr.sbin/emcfanctl/emcfanctlconst.h

2250

.reg = 0x5C

usr.sbin/emcfanctl/emcfanctlconst.h

2254

.reg = 0x5D

usr.sbin/emcfanctl/emcfanctlconst.h

2258

.reg = 0x5E

usr.sbin/emcfanctl/emcfanctlconst.h

226

.reg = 0x0A

usr.sbin/emcfanctl/emcfanctlconst.h

2262

.reg = 0x5F

usr.sbin/emcfanctl/emcfanctlconst.h

2266

.reg = 0x60

usr.sbin/emcfanctl/emcfanctlconst.h

2270

.reg = 0x61

usr.sbin/emcfanctl/emcfanctlconst.h

2274

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usr.sbin/emcfanctl/emcfanctlconst.h

2278

.reg = 0x63

usr.sbin/emcfanctl/emcfanctlconst.h

2282

.reg = 0x64

usr.sbin/emcfanctl/emcfanctlconst.h

2286

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usr.sbin/emcfanctl/emcfanctlconst.h

2290

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usr.sbin/emcfanctl/emcfanctlconst.h

2294

.reg = 0x67

usr.sbin/emcfanctl/emcfanctlconst.h

2298

.reg = 0x68

usr.sbin/emcfanctl/emcfanctlconst.h

230

.reg = 0x0B

usr.sbin/emcfanctl/emcfanctlconst.h

2302

.reg = 0x69

usr.sbin/emcfanctl/emcfanctlconst.h

2306

.reg = 0x6A

usr.sbin/emcfanctl/emcfanctlconst.h

2310

.reg = 0x6B

usr.sbin/emcfanctl/emcfanctlconst.h

2314

.reg = 0x6C

usr.sbin/emcfanctl/emcfanctlconst.h

2318

.reg = 0x6D

usr.sbin/emcfanctl/emcfanctlconst.h

2322

.reg = 0x6E

usr.sbin/emcfanctl/emcfanctlconst.h

2326

.reg = 0x6F

usr.sbin/emcfanctl/emcfanctlconst.h

2330

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usr.sbin/emcfanctl/emcfanctlconst.h

2334

.reg = 0x71

usr.sbin/emcfanctl/emcfanctlconst.h

2338

.reg = 0x72

usr.sbin/emcfanctl/emcfanctlconst.h

234

.reg = 0x0D

usr.sbin/emcfanctl/emcfanctlconst.h

2342

.reg = 0x73

usr.sbin/emcfanctl/emcfanctlconst.h

2346

.reg = 0x74

usr.sbin/emcfanctl/emcfanctlconst.h

2350

.reg = 0x75

usr.sbin/emcfanctl/emcfanctlconst.h

2354

.reg = 0x76

usr.sbin/emcfanctl/emcfanctlconst.h

2358

.reg = 0x77

usr.sbin/emcfanctl/emcfanctlconst.h

2362

.reg = 0x78

usr.sbin/emcfanctl/emcfanctlconst.h

2366

.reg = 0x79

usr.sbin/emcfanctl/emcfanctlconst.h

2370

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usr.sbin/emcfanctl/emcfanctlconst.h

2374

.reg = 0x81

usr.sbin/emcfanctl/emcfanctlconst.h

2378

.reg = 0x82

usr.sbin/emcfanctl/emcfanctlconst.h

238

.reg = 0x0E

usr.sbin/emcfanctl/emcfanctlconst.h

2382

.reg = 0x83

usr.sbin/emcfanctl/emcfanctlconst.h

2386

.reg = 0x85

usr.sbin/emcfanctl/emcfanctlconst.h

2390

.reg = 0x86

usr.sbin/emcfanctl/emcfanctlconst.h

2394

.reg = 0x87

usr.sbin/emcfanctl/emcfanctlconst.h

2398

.reg = 0x88

usr.sbin/emcfanctl/emcfanctlconst.h

2402

.reg = 0x89

usr.sbin/emcfanctl/emcfanctlconst.h

2406

.reg = 0x8A

usr.sbin/emcfanctl/emcfanctlconst.h

2410

.reg = 0x8B

usr.sbin/emcfanctl/emcfanctlconst.h

2414

.reg = 0x8C

usr.sbin/emcfanctl/emcfanctlconst.h

2418

.reg = 0x8D

usr.sbin/emcfanctl/emcfanctlconst.h

242

.reg = 0x0C

usr.sbin/emcfanctl/emcfanctlconst.h

2422

.reg = 0x8E

usr.sbin/emcfanctl/emcfanctlconst.h

2426

.reg = 0x8F

usr.sbin/emcfanctl/emcfanctlconst.h

2430

.reg = 0x90

usr.sbin/emcfanctl/emcfanctlconst.h

2434

.reg = 0x91

usr.sbin/emcfanctl/emcfanctlconst.h

2438

.reg = 0x92

usr.sbin/emcfanctl/emcfanctlconst.h

2442

.reg = 0x93

usr.sbin/emcfanctl/emcfanctlconst.h

2446

.reg = 0x94

usr.sbin/emcfanctl/emcfanctlconst.h

2450

.reg = 0x95

usr.sbin/emcfanctl/emcfanctlconst.h

2454

.reg = 0x96

usr.sbin/emcfanctl/emcfanctlconst.h

2458

.reg = 0x97

usr.sbin/emcfanctl/emcfanctlconst.h

246

.reg = 0x0F

usr.sbin/emcfanctl/emcfanctlconst.h

2462

.reg = 0x98

usr.sbin/emcfanctl/emcfanctlconst.h

2466

.reg = 0x99

usr.sbin/emcfanctl/emcfanctlconst.h

2470

.reg = 0x9A

usr.sbin/emcfanctl/emcfanctlconst.h

2474

.reg = 0x9B

usr.sbin/emcfanctl/emcfanctlconst.h

2478

.reg = 0x9C

usr.sbin/emcfanctl/emcfanctlconst.h

2482

.reg = 0x9D

usr.sbin/emcfanctl/emcfanctlconst.h

2486

.reg = 0x9E

usr.sbin/emcfanctl/emcfanctlconst.h

2490

.reg = 0x9F

usr.sbin/emcfanctl/emcfanctlconst.h

2494

.reg = 0xA0

usr.sbin/emcfanctl/emcfanctlconst.h

2498

.reg = 0xA1

usr.sbin/emcfanctl/emcfanctlconst.h

250

.reg = 0x10

usr.sbin/emcfanctl/emcfanctlconst.h

2502

.reg = 0xA2

usr.sbin/emcfanctl/emcfanctlconst.h

2506

.reg = 0xA3

usr.sbin/emcfanctl/emcfanctlconst.h

2510

.reg = 0xA4

usr.sbin/emcfanctl/emcfanctlconst.h

2514

.reg = 0xA5

usr.sbin/emcfanctl/emcfanctlconst.h

2518

.reg = 0xA6

usr.sbin/emcfanctl/emcfanctlconst.h

2522

.reg = 0xA7

usr.sbin/emcfanctl/emcfanctlconst.h

2526

.reg = 0xA8

usr.sbin/emcfanctl/emcfanctlconst.h

2530

.reg = 0xA9

usr.sbin/emcfanctl/emcfanctlconst.h

2534

.reg = 0xAA

usr.sbin/emcfanctl/emcfanctlconst.h

2538

.reg = 0xAB

usr.sbin/emcfanctl/emcfanctlconst.h

254

.reg = 0x11

usr.sbin/emcfanctl/emcfanctlconst.h

2542

.reg = 0xAC

usr.sbin/emcfanctl/emcfanctlconst.h

2546

.reg = 0xAD

usr.sbin/emcfanctl/emcfanctlconst.h

2550

.reg = 0xAE

usr.sbin/emcfanctl/emcfanctlconst.h

2554

.reg = 0xAF

usr.sbin/emcfanctl/emcfanctlconst.h

2558

.reg = 0xB0

usr.sbin/emcfanctl/emcfanctlconst.h

2562

.reg = 0xB1

usr.sbin/emcfanctl/emcfanctlconst.h

2566

.reg = 0xB2

usr.sbin/emcfanctl/emcfanctlconst.h

2570

.reg = 0xB3

usr.sbin/emcfanctl/emcfanctlconst.h

2574

.reg = 0xB4

usr.sbin/emcfanctl/emcfanctlconst.h

2578

.reg = 0xB5

usr.sbin/emcfanctl/emcfanctlconst.h

258

.reg = 0x12

usr.sbin/emcfanctl/emcfanctlconst.h

2582

.reg = 0xB6

usr.sbin/emcfanctl/emcfanctlconst.h

2586

.reg = 0xB7

usr.sbin/emcfanctl/emcfanctlconst.h

2590

.reg = 0xB8

usr.sbin/emcfanctl/emcfanctlconst.h

2594

.reg = 0xB9

usr.sbin/emcfanctl/emcfanctlconst.h

2598

.reg = 0xE0

usr.sbin/emcfanctl/emcfanctlconst.h

2602

.reg = 0xE1

usr.sbin/emcfanctl/emcfanctlconst.h

2606

.reg = 0xE2

usr.sbin/emcfanctl/emcfanctlconst.h

2610

.reg = 0xE3

usr.sbin/emcfanctl/emcfanctlconst.h

2614

.reg = 0xE4

usr.sbin/emcfanctl/emcfanctlconst.h

2618

.reg = 0xE5

usr.sbin/emcfanctl/emcfanctlconst.h

262

.reg = 0x13

usr.sbin/emcfanctl/emcfanctlconst.h

2622

.reg = 0xE6

usr.sbin/emcfanctl/emcfanctlconst.h

2626

.reg = 0xEF

usr.sbin/emcfanctl/emcfanctlconst.h

2630

.reg = 0xFC

usr.sbin/emcfanctl/emcfanctlconst.h

2634

.reg = 0xFD

usr.sbin/emcfanctl/emcfanctlconst.h

2638

.reg = 0xFE

usr.sbin/emcfanctl/emcfanctlconst.h

2642

.reg = 0xFF

usr.sbin/emcfanctl/emcfanctlconst.h

2649

.reg = 0x20

usr.sbin/emcfanctl/emcfanctlconst.h

2653

.reg = 0x24

usr.sbin/emcfanctl/emcfanctlconst.h

2657

.reg = 0x25

usr.sbin/emcfanctl/emcfanctlconst.h

266

.reg = 0x14

usr.sbin/emcfanctl/emcfanctlconst.h

2661

.reg = 0x26

usr.sbin/emcfanctl/emcfanctlconst.h

2665

.reg = 0x27

usr.sbin/emcfanctl/emcfanctlconst.h

2669

.reg = 0x29

usr.sbin/emcfanctl/emcfanctlconst.h

2673

.reg = 0x2A

usr.sbin/emcfanctl/emcfanctlconst.h

2677

.reg = 0x2B

usr.sbin/emcfanctl/emcfanctlconst.h

2681

.reg = 0x2C

usr.sbin/emcfanctl/emcfanctlconst.h

2685

.reg = 0x2D

usr.sbin/emcfanctl/emcfanctlconst.h

2689

.reg = 0x30

usr.sbin/emcfanctl/emcfanctlconst.h

2693

.reg = 0x31

usr.sbin/emcfanctl/emcfanctlconst.h

2697

.reg = 0x32

usr.sbin/emcfanctl/emcfanctlconst.h

270

.reg = 0x16

usr.sbin/emcfanctl/emcfanctlconst.h

2701

.reg = 0x33

usr.sbin/emcfanctl/emcfanctlconst.h

2705

.reg = 0x35

usr.sbin/emcfanctl/emcfanctlconst.h

2709

.reg = 0x36

usr.sbin/emcfanctl/emcfanctlconst.h

2713

.reg = 0x37

usr.sbin/emcfanctl/emcfanctlconst.h

2717

.reg = 0x38

usr.sbin/emcfanctl/emcfanctlconst.h

2721

.reg = 0x39

usr.sbin/emcfanctl/emcfanctlconst.h

2725

.reg = 0x3A

usr.sbin/emcfanctl/emcfanctlconst.h

2729

.reg = 0x3B

usr.sbin/emcfanctl/emcfanctlconst.h

2733

.reg = 0x3C

usr.sbin/emcfanctl/emcfanctlconst.h

2737

.reg = 0x3D

usr.sbin/emcfanctl/emcfanctlconst.h

274

.reg = 0x17

usr.sbin/emcfanctl/emcfanctlconst.h

2741

.reg = 0x3E

usr.sbin/emcfanctl/emcfanctlconst.h

2745

.reg = 0x3F

usr.sbin/emcfanctl/emcfanctlconst.h

2749

.reg = 0x40

usr.sbin/emcfanctl/emcfanctlconst.h

2753

.reg = 0x41

usr.sbin/emcfanctl/emcfanctlconst.h

2757

.reg = 0x42

usr.sbin/emcfanctl/emcfanctlconst.h

2761

.reg = 0x43

usr.sbin/emcfanctl/emcfanctlconst.h

2765

.reg = 0x45

usr.sbin/emcfanctl/emcfanctlconst.h

2769

.reg = 0x46

usr.sbin/emcfanctl/emcfanctlconst.h

2773

.reg = 0x47

usr.sbin/emcfanctl/emcfanctlconst.h

2777

.reg = 0x48

usr.sbin/emcfanctl/emcfanctlconst.h

278

.reg = 0x18

usr.sbin/emcfanctl/emcfanctlconst.h

2781

.reg = 0x49

usr.sbin/emcfanctl/emcfanctlconst.h

2785

.reg = 0x4A

usr.sbin/emcfanctl/emcfanctlconst.h

2789

.reg = 0x4B

usr.sbin/emcfanctl/emcfanctlconst.h

2793

.reg = 0x4C

usr.sbin/emcfanctl/emcfanctlconst.h

2797

.reg = 0x4D

usr.sbin/emcfanctl/emcfanctlconst.h

2801

.reg = 0x4E

usr.sbin/emcfanctl/emcfanctlconst.h

2805

.reg = 0x4F

usr.sbin/emcfanctl/emcfanctlconst.h

2809

.reg = 0x50

usr.sbin/emcfanctl/emcfanctlconst.h

2813

.reg = 0x51

usr.sbin/emcfanctl/emcfanctlconst.h

2817

.reg = 0x52

usr.sbin/emcfanctl/emcfanctlconst.h

282

.reg = 0x19

usr.sbin/emcfanctl/emcfanctlconst.h

2821

.reg = 0x53

usr.sbin/emcfanctl/emcfanctlconst.h

2825

.reg = 0x55

usr.sbin/emcfanctl/emcfanctlconst.h

2829

.reg = 0x56

usr.sbin/emcfanctl/emcfanctlconst.h

2833

.reg = 0x57

usr.sbin/emcfanctl/emcfanctlconst.h

2837

.reg = 0x58

usr.sbin/emcfanctl/emcfanctlconst.h

2841

.reg = 0x59

usr.sbin/emcfanctl/emcfanctlconst.h

2845

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usr.sbin/emcfanctl/emcfanctlconst.h

2849

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usr.sbin/emcfanctl/emcfanctlconst.h

2853

.reg = 0x5C

usr.sbin/emcfanctl/emcfanctlconst.h

2857

.reg = 0x5D

usr.sbin/emcfanctl/emcfanctlconst.h

286

.reg = 0x21

usr.sbin/emcfanctl/emcfanctlconst.h

2861

.reg = 0x5E

usr.sbin/emcfanctl/emcfanctlconst.h

2865

.reg = 0x5F

usr.sbin/emcfanctl/emcfanctlconst.h

2869

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usr.sbin/emcfanctl/emcfanctlconst.h

2873

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usr.sbin/emcfanctl/emcfanctlconst.h

2877

.reg = 0x62

usr.sbin/emcfanctl/emcfanctlconst.h

2881

.reg = 0x63

usr.sbin/emcfanctl/emcfanctlconst.h

2885

.reg = 0x65

usr.sbin/emcfanctl/emcfanctlconst.h

2889

.reg = 0x66

usr.sbin/emcfanctl/emcfanctlconst.h

2893

.reg = 0x67

usr.sbin/emcfanctl/emcfanctlconst.h

2897

.reg = 0x68

usr.sbin/emcfanctl/emcfanctlconst.h

290

.reg = 0x46

usr.sbin/emcfanctl/emcfanctlconst.h

2901

.reg = 0x69

usr.sbin/emcfanctl/emcfanctlconst.h

2905

.reg = 0x6A

usr.sbin/emcfanctl/emcfanctlconst.h

2909

.reg = 0x6B

usr.sbin/emcfanctl/emcfanctlconst.h

2913

.reg = 0x6C

usr.sbin/emcfanctl/emcfanctlconst.h

2917

.reg = 0x6D

usr.sbin/emcfanctl/emcfanctlconst.h

2921

.reg = 0x6E

usr.sbin/emcfanctl/emcfanctlconst.h

2925

.reg = 0x6F

usr.sbin/emcfanctl/emcfanctlconst.h

2929

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usr.sbin/emcfanctl/emcfanctlconst.h

2933

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usr.sbin/emcfanctl/emcfanctlconst.h

2937

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usr.sbin/emcfanctl/emcfanctlconst.h

294

.reg = 0x47

usr.sbin/emcfanctl/emcfanctlconst.h

2941

.reg = 0x73

usr.sbin/emcfanctl/emcfanctlconst.h

2945

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usr.sbin/emcfanctl/emcfanctlconst.h

2949

.reg = 0x76

usr.sbin/emcfanctl/emcfanctlconst.h

2953

.reg = 0x77

usr.sbin/emcfanctl/emcfanctlconst.h

2957

.reg = 0x78

usr.sbin/emcfanctl/emcfanctlconst.h

2961

.reg = 0x79

usr.sbin/emcfanctl/emcfanctlconst.h

2965

.reg = 0x7A

usr.sbin/emcfanctl/emcfanctlconst.h

2969

.reg = 0x7B

usr.sbin/emcfanctl/emcfanctlconst.h

2973

.reg = 0x7C

usr.sbin/emcfanctl/emcfanctlconst.h

2977

.reg = 0x7D

usr.sbin/emcfanctl/emcfanctlconst.h

298

.reg = 0x48

usr.sbin/emcfanctl/emcfanctlconst.h

2981

.reg = 0x7E

usr.sbin/emcfanctl/emcfanctlconst.h

2985

.reg = 0x7F

usr.sbin/emcfanctl/emcfanctlconst.h

2989

.reg = 0xEF

usr.sbin/emcfanctl/emcfanctlconst.h

2993

.reg = 0xFC

usr.sbin/emcfanctl/emcfanctlconst.h

2997

.reg = 0xFD

usr.sbin/emcfanctl/emcfanctlconst.h

3001

.reg = 0xFE

usr.sbin/emcfanctl/emcfanctlconst.h

3005

.reg = 0xFF

usr.sbin/emcfanctl/emcfanctlconst.h

302

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usr.sbin/emcfanctl/emcfanctlconst.h

306

.reg = 0x4A

usr.sbin/emcfanctl/emcfanctlconst.h

310

.reg = 0x4B

usr.sbin/emcfanctl/emcfanctlconst.h

314

.reg = 0x4C

usr.sbin/emcfanctl/emcfanctlconst.h

318

.reg = 0x4D

usr.sbin/emcfanctl/emcfanctlconst.h

322

.reg = 0x4E

usr.sbin/emcfanctl/emcfanctlconst.h

326

.reg = 0x4F

usr.sbin/emcfanctl/emcfanctlconst.h

330

.reg = 0x50

usr.sbin/emcfanctl/emcfanctlconst.h

334

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usr.sbin/emcfanctl/emcfanctlconst.h

338

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usr.sbin/emcfanctl/emcfanctlconst.h

342

.reg = 0x53

usr.sbin/emcfanctl/emcfanctlconst.h

346

.reg = 0x54

usr.sbin/emcfanctl/emcfanctlconst.h

350

.reg = 0x55

usr.sbin/emcfanctl/emcfanctlconst.h

354

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usr.sbin/emcfanctl/emcfanctlconst.h

358

.reg = 0x57

usr.sbin/emcfanctl/emcfanctlconst.h

362

.reg = 0x58

usr.sbin/emcfanctl/emcfanctlconst.h

366

.reg = 0x59

usr.sbin/emcfanctl/emcfanctlconst.h

370

.reg = 0x5A

usr.sbin/emcfanctl/emcfanctlconst.h

374

.reg = 0x5B

usr.sbin/emcfanctl/emcfanctlconst.h

378

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usr.sbin/emcfanctl/emcfanctlconst.h

382

.reg = 0x5D

usr.sbin/emcfanctl/emcfanctlconst.h

386

.reg = 0x5E

usr.sbin/emcfanctl/emcfanctlconst.h

390

.reg = 0x5F

usr.sbin/emcfanctl/emcfanctlconst.h

394

.reg = 0xBF

usr.sbin/emcfanctl/emcfanctlconst.h

398

.reg = 0xFD

usr.sbin/emcfanctl/emcfanctlconst.h

402

.reg = 0xFE

usr.sbin/emcfanctl/emcfanctlconst.h

406

.reg = 0xFF

usr.sbin/emcfanctl/emcfanctlconst.h

413

.reg = 0x00

usr.sbin/emcfanctl/emcfanctlconst.h

417

.reg = 0x01

usr.sbin/emcfanctl/emcfanctlconst.h

421

.reg = 0x02

usr.sbin/emcfanctl/emcfanctlconst.h

425

.reg = 0x03

usr.sbin/emcfanctl/emcfanctlconst.h

429

.reg = 0x0A

usr.sbin/emcfanctl/emcfanctlconst.h

433

.reg = 0x0C

usr.sbin/emcfanctl/emcfanctlconst.h

437

.reg = 0x0D

usr.sbin/emcfanctl/emcfanctlconst.h

441

.reg = 0x10

usr.sbin/emcfanctl/emcfanctlconst.h

445

.reg = 0x11

usr.sbin/emcfanctl/emcfanctlconst.h

449

.reg = 0x14

usr.sbin/emcfanctl/emcfanctlconst.h

453

.reg = 0x17

usr.sbin/emcfanctl/emcfanctlconst.h

457

.reg = 0x19

usr.sbin/emcfanctl/emcfanctlconst.h

461

.reg = 0x1D

usr.sbin/emcfanctl/emcfanctlconst.h

465

.reg = 0x1F

usr.sbin/emcfanctl/emcfanctlconst.h

469

.reg = 0x20

usr.sbin/emcfanctl/emcfanctlconst.h

473

.reg = 0x21

usr.sbin/emcfanctl/emcfanctlconst.h

477

.reg = 0x23

usr.sbin/emcfanctl/emcfanctlconst.h

481

.reg = 0x24

usr.sbin/emcfanctl/emcfanctlconst.h

485

.reg = 0x25

usr.sbin/emcfanctl/emcfanctlconst.h

489

.reg = 0x26

usr.sbin/emcfanctl/emcfanctlconst.h

493

.reg = 0x27

usr.sbin/emcfanctl/emcfanctlconst.h

497

.reg = 0x28

usr.sbin/emcfanctl/emcfanctlconst.h

501

.reg = 0x29

usr.sbin/emcfanctl/emcfanctlconst.h

505

.reg = 0x2A

usr.sbin/emcfanctl/emcfanctlconst.h

509

.reg = 0x2B

usr.sbin/emcfanctl/emcfanctlconst.h

513

.reg = 0x30

usr.sbin/emcfanctl/emcfanctlconst.h

517

.reg = 0x34

usr.sbin/emcfanctl/emcfanctlconst.h

521

.reg = 0x38

usr.sbin/emcfanctl/emcfanctlconst.h

525

.reg = 0x3C

usr.sbin/emcfanctl/emcfanctlconst.h

529

.reg = 0x40

usr.sbin/emcfanctl/emcfanctlconst.h

533

.reg = 0x41

usr.sbin/emcfanctl/emcfanctlconst.h

537

.reg = 0x42

usr.sbin/emcfanctl/emcfanctlconst.h

541

.reg = 0x43

usr.sbin/emcfanctl/emcfanctlconst.h

545

.reg = 0x45

usr.sbin/emcfanctl/emcfanctlconst.h

549

.reg = 0x46

usr.sbin/emcfanctl/emcfanctlconst.h

553

.reg = 0x47

usr.sbin/emcfanctl/emcfanctlconst.h

557

.reg = 0x48

usr.sbin/emcfanctl/emcfanctlconst.h

561

.reg = 0x49

usr.sbin/emcfanctl/emcfanctlconst.h

565

.reg = 0x4A

usr.sbin/emcfanctl/emcfanctlconst.h

569

.reg = 0x4B

usr.sbin/emcfanctl/emcfanctlconst.h

573

.reg = 0x4C

usr.sbin/emcfanctl/emcfanctlconst.h

577

.reg = 0x4D

usr.sbin/emcfanctl/emcfanctlconst.h

581

.reg = 0x4E

usr.sbin/emcfanctl/emcfanctlconst.h

585

.reg = 0x4F

usr.sbin/emcfanctl/emcfanctlconst.h

589

.reg = 0x50

usr.sbin/emcfanctl/emcfanctlconst.h

593

.reg = 0x51

usr.sbin/emcfanctl/emcfanctlconst.h

597

.reg = 0x52

usr.sbin/emcfanctl/emcfanctlconst.h

601

.reg = 0x53

usr.sbin/emcfanctl/emcfanctlconst.h

605

.reg = 0x54

usr.sbin/emcfanctl/emcfanctlconst.h

609

.reg = 0x55

usr.sbin/emcfanctl/emcfanctlconst.h

613

.reg = 0x56

usr.sbin/emcfanctl/emcfanctlconst.h

617

.reg = 0x57

usr.sbin/emcfanctl/emcfanctlconst.h

621

.reg = 0x58

usr.sbin/emcfanctl/emcfanctlconst.h

625

.reg = 0x59

usr.sbin/emcfanctl/emcfanctlconst.h

629

.reg = 0x5A

usr.sbin/emcfanctl/emcfanctlconst.h

633

.reg = 0x5B

usr.sbin/emcfanctl/emcfanctlconst.h

637

.reg = 0x5C

usr.sbin/emcfanctl/emcfanctlconst.h

641

.reg = 0x5D

usr.sbin/emcfanctl/emcfanctlconst.h

645

.reg = 0x5E

usr.sbin/emcfanctl/emcfanctlconst.h

649

.reg = 0x5F

usr.sbin/emcfanctl/emcfanctlconst.h

653

.reg = 0x60

usr.sbin/emcfanctl/emcfanctlconst.h

657

.reg = 0x61

usr.sbin/emcfanctl/emcfanctlconst.h

661

.reg = 0x62

usr.sbin/emcfanctl/emcfanctlconst.h

665

.reg = 0x63

usr.sbin/emcfanctl/emcfanctlconst.h

669

.reg = 0x64

usr.sbin/emcfanctl/emcfanctlconst.h

673

.reg = 0x65

usr.sbin/emcfanctl/emcfanctlconst.h

677

.reg = 0x66

usr.sbin/emcfanctl/emcfanctlconst.h

681

.reg = 0x67

usr.sbin/emcfanctl/emcfanctlconst.h

685

.reg = 0x68

usr.sbin/emcfanctl/emcfanctlconst.h

689

.reg = 0x69

usr.sbin/emcfanctl/emcfanctlconst.h

693

.reg = 0x6A

usr.sbin/emcfanctl/emcfanctlconst.h

697

.reg = 0x6B

usr.sbin/emcfanctl/emcfanctlconst.h

701

.reg = 0x6C

usr.sbin/emcfanctl/emcfanctlconst.h

705

.reg = 0x6D

usr.sbin/emcfanctl/emcfanctlconst.h

709

.reg = 0x6E

usr.sbin/emcfanctl/emcfanctlconst.h

713

.reg = 0x6F

usr.sbin/emcfanctl/emcfanctlconst.h

717

.reg = 0x70

usr.sbin/emcfanctl/emcfanctlconst.h

721

.reg = 0x71

usr.sbin/emcfanctl/emcfanctlconst.h

725

.reg = 0x72

usr.sbin/emcfanctl/emcfanctlconst.h

729

.reg = 0x73

usr.sbin/emcfanctl/emcfanctlconst.h

733

.reg = 0x74

usr.sbin/emcfanctl/emcfanctlconst.h

737

.reg = 0x75

usr.sbin/emcfanctl/emcfanctlconst.h

741

.reg = 0x76

usr.sbin/emcfanctl/emcfanctlconst.h

745

.reg = 0x77

usr.sbin/emcfanctl/emcfanctlconst.h

749

.reg = 0x78

usr.sbin/emcfanctl/emcfanctlconst.h

753

.reg = 0x79

usr.sbin/emcfanctl/emcfanctlconst.h

757

.reg = 0xEF

usr.sbin/emcfanctl/emcfanctlconst.h

761

.reg = 0xFC

usr.sbin/emcfanctl/emcfanctlconst.h

765

.reg = 0xFD

usr.sbin/emcfanctl/emcfanctlconst.h

769

.reg = 0xFE

usr.sbin/emcfanctl/emcfanctlconst.h

773

.reg = 0xFF

usr.sbin/emcfanctl/emcfanctlconst.h

780

.reg = 0x00

usr.sbin/emcfanctl/emcfanctlconst.h

784

.reg = 0x01

usr.sbin/emcfanctl/emcfanctlconst.h

788

.reg = 0x02

usr.sbin/emcfanctl/emcfanctlconst.h

792

.reg = 0x03

usr.sbin/emcfanctl/emcfanctlconst.h

796

.reg = 0x04

usr.sbin/emcfanctl/emcfanctlconst.h

800

.reg = 0x05

usr.sbin/emcfanctl/emcfanctlconst.h

804

.reg = 0x06

usr.sbin/emcfanctl/emcfanctlconst.h

808

.reg = 0x07

usr.sbin/emcfanctl/emcfanctlconst.h

812

.reg = 0x0A

usr.sbin/emcfanctl/emcfanctlconst.h

816

.reg = 0x0C

usr.sbin/emcfanctl/emcfanctlconst.h

820

.reg = 0x0D

usr.sbin/emcfanctl/emcfanctlconst.h

824

.reg = 0x10

usr.sbin/emcfanctl/emcfanctlconst.h

828

.reg = 0x11

usr.sbin/emcfanctl/emcfanctlconst.h

832

.reg = 0x12

usr.sbin/emcfanctl/emcfanctlconst.h

836

.reg = 0x14

usr.sbin/emcfanctl/emcfanctlconst.h

840

.reg = 0x15

usr.sbin/emcfanctl/emcfanctlconst.h

844

.reg = 0x17

usr.sbin/emcfanctl/emcfanctlconst.h

848

.reg = 0x19

usr.sbin/emcfanctl/emcfanctlconst.h

852

.reg = 0x1A

usr.sbin/emcfanctl/emcfanctlconst.h

856

.reg = 0x1B

usr.sbin/emcfanctl/emcfanctlconst.h

860

.reg = 0x1D

usr.sbin/emcfanctl/emcfanctlconst.h

864

.reg = 0x1F

usr.sbin/emcfanctl/emcfanctlconst.h

868

.reg = 0x20

usr.sbin/emcfanctl/emcfanctlconst.h

872

.reg = 0x21

usr.sbin/emcfanctl/emcfanctlconst.h

876

.reg = 0x23

usr.sbin/emcfanctl/emcfanctlconst.h

880

.reg = 0x24

usr.sbin/emcfanctl/emcfanctlconst.h

884

.reg = 0x25

usr.sbin/emcfanctl/emcfanctlconst.h

888

.reg = 0x26

usr.sbin/emcfanctl/emcfanctlconst.h

892

.reg = 0x27

usr.sbin/emcfanctl/emcfanctlconst.h

896

.reg = 0x28

usr.sbin/emcfanctl/emcfanctlconst.h

900

.reg = 0x29

usr.sbin/emcfanctl/emcfanctlconst.h

904

.reg = 0x2A

usr.sbin/emcfanctl/emcfanctlconst.h

908

.reg = 0x2B

usr.sbin/emcfanctl/emcfanctlconst.h

912

.reg = 0x30

usr.sbin/emcfanctl/emcfanctlconst.h

916

.reg = 0x31

usr.sbin/emcfanctl/emcfanctlconst.h

920

.reg = 0x32

usr.sbin/emcfanctl/emcfanctlconst.h

924

.reg = 0x34

usr.sbin/emcfanctl/emcfanctlconst.h

928

.reg = 0x38

usr.sbin/emcfanctl/emcfanctlconst.h

932

.reg = 0x39

usr.sbin/emcfanctl/emcfanctlconst.h

936

.reg = 0x3A

usr.sbin/emcfanctl/emcfanctlconst.h

940

.reg = 0x3C

usr.sbin/emcfanctl/emcfanctlconst.h

944

.reg = 0x40

usr.sbin/emcfanctl/emcfanctlconst.h

948

.reg = 0x41

usr.sbin/emcfanctl/emcfanctlconst.h

952

.reg = 0x42

usr.sbin/emcfanctl/emcfanctlconst.h

956

.reg = 0x43

usr.sbin/emcfanctl/emcfanctlconst.h

960

.reg = 0x45

usr.sbin/emcfanctl/emcfanctlconst.h

964

.reg = 0x46

usr.sbin/emcfanctl/emcfanctlconst.h

968

.reg = 0x47

usr.sbin/emcfanctl/emcfanctlconst.h

972

.reg = 0x48

usr.sbin/emcfanctl/emcfanctlconst.h

976

.reg = 0x49

usr.sbin/emcfanctl/emcfanctlconst.h

980

.reg = 0x4A

usr.sbin/emcfanctl/emcfanctlconst.h

984

.reg = 0x4B

usr.sbin/emcfanctl/emcfanctlconst.h

988

.reg = 0x4C

usr.sbin/emcfanctl/emcfanctlconst.h

992

.reg = 0x4D

usr.sbin/emcfanctl/emcfanctlconst.h

996

.reg = 0x4E

usr.sbin/emcfanctl/emcfanctloutputs.c

106

if (emcfan_reg_is_real(iindex, the_registers[i].reg)) {

usr.sbin/emcfanctl/emcfanctloutputs.c

111

mj_append_field(&obj, "register", "integer", (int64_t)the_registers[i].reg);

usr.sbin/emcfanctl/emcfanctloutputs.c

115

printf("%s\t%d\t0x%02X\n",the_registers[i].name,the_registers[i].reg,the_registers[i].reg);

usr.sbin/emcfanctl/emcfanctloutputs.c

325

output_emcfan_simple_int(int fd, uint8_t product_id, int product_family, uint8_t reg, const char *what, const char *whatj, bool jsonify, bool debug)

usr.sbin/emcfanctl/emcfanctloutputs.c

332

err = emcfan_read_register(fd, reg, &res, debug);

usr.sbin/emcfanctl/emcfanctloutputs.c

340

mj_append_field(&obj, "register", "integer", (int64_t)reg);

usr.sbin/emcfanctl/emcfanctloutputs.c

355

output_emcfan_drive(int fd, uint8_t product_id, int product_family, uint8_t reg, bool jsonify, bool debug)

usr.sbin/emcfanctl/emcfanctloutputs.c

357

return(output_emcfan_simple_int(fd, product_id, product_family, reg, "Drive", "drive_level", jsonify, debug));

usr.sbin/emcfanctl/emcfanctloutputs.c

361

output_emcfan_divider(int fd, uint8_t product_id, int product_family, uint8_t reg, bool jsonify, bool debug)

usr.sbin/emcfanctl/emcfanctloutputs.c

363

return(output_emcfan_simple_int(fd, product_id, product_family, reg, "Divider", "frequency_divider", jsonify, debug));

usr.sbin/emcfanctl/emcfanctloutputs.c

367

output_emcfan_pwm_basefreq(int fd, uint8_t product_id, int product_family, uint8_t reg, int the_fan, bool jsonify, bool debug)

usr.sbin/emcfanctl/emcfanctloutputs.c

375

err = emcfan_read_register(fd, reg, &res, debug);

usr.sbin/emcfanctl/emcfanctloutputs.c

382

fprintf(stderr,"%s: reg=%d 0x%02X, res=0x%02x, tindex=%d, the_fan=%d\n",__func__,reg,reg,res,tindex,the_fan);

usr.sbin/emcfanctl/emcfanctloutputs.c

389

mj_append_field(&obj, "register", "integer", (int64_t)reg);

usr.sbin/emcfanctl/emcfanctloutputs.c

404

output_emcfan_polarity(int fd, uint8_t product_id, int product_family, uint8_t reg, int the_fan, bool jsonify, bool debug)

usr.sbin/emcfanctl/emcfanctloutputs.c

413

err = emcfan_read_register(fd, reg, &res, debug);

usr.sbin/emcfanctl/emcfanctloutputs.c

432

mj_append_field(&obj, "register", "integer", (int64_t)reg);

usr.sbin/emcfanctl/emcfanctloutputs.c

447

output_emcfan_pwm_output_type(int fd, uint8_t product_id, int product_family, uint8_t reg, int the_fan, bool jsonify, bool debug)

usr.sbin/emcfanctl/emcfanctloutputs.c

456

err = emcfan_read_register(fd, reg, &res, debug);

usr.sbin/emcfanctl/emcfanctloutputs.c

470

mj_append_field(&obj, "register", "integer", (int64_t)reg);

usr.sbin/emcfanctl/emcfanctloutputs.c

581

output_emcfan_apd(int fd, uint8_t product_id, int product_family, uint8_t reg, bool jsonify, bool debug)

usr.sbin/emcfanctl/emcfanctloutputs.c

589

err = emcfan_read_register(fd, reg, &res, debug);

usr.sbin/emcfanctl/emcfanctloutputs.c

600

mj_append_field(&obj, "register", "integer", (int64_t)reg);

usr.sbin/emcfanctl/emcfanctloutputs.c

615

output_emcfan_smbusto(int fd, uint8_t product_id, int product_family, uint8_t reg, int instance, bool jsonify, bool debug)

usr.sbin/emcfanctl/emcfanctloutputs.c

624

err = emcfan_read_register(fd, reg, &res, debug);

usr.sbin/emcfanctl/emcfanctloutputs.c

631

fprintf(stderr,"%s: reg=%d 0x%02X, res=0x%02x, tindex=%d, instance=%d\n",__func__,reg,reg,res,tindex,instance);

usr.sbin/emcfanctl/emcfanctloutputs.c

640

mj_append_field(&obj, "register", "integer", (int64_t)reg);

usr.sbin/emcfanctl/emcfanctlutil.c

113

err = emcfan_write_register(fd, reg, current, debug);

usr.sbin/emcfanctl/emcfanctlutil.c

157

emcfan_reg_is_real(int iindex, uint8_t reg)

usr.sbin/emcfanctl/emcfanctlutil.c

162

segment = reg / 64;

usr.sbin/emcfanctl/emcfanctlutil.c

163

index = reg % 64;

usr.sbin/emcfanctl/emcfanctlutil.c

175

r = the_registers[i].reg;

usr.sbin/emcfanctl/emcfanctlutil.c

227

if (the_reg == the_registers[i].reg) {

usr.sbin/emcfanctl/emcfanctlutil.c

237

emcfan_regname_by_reg(uint8_t product_id, int product_family, uint8_t reg)

usr.sbin/emcfanctl/emcfanctlutil.c

246

r = emcfan_hunt_by_reg(emcfanctl_2101_registers,__arraycount(emcfanctl_2101_registers),reg);

usr.sbin/emcfanctl/emcfanctlutil.c

249

r = emcfan_hunt_by_reg(emcfanctl_2103_1_registers,__arraycount(emcfanctl_2103_1_registers),reg);

usr.sbin/emcfanctl/emcfanctlutil.c

252

r = emcfan_hunt_by_reg(emcfanctl_2103_24_registers,__arraycount(emcfanctl_2103_24_registers),reg);

usr.sbin/emcfanctl/emcfanctlutil.c

255

r = emcfan_hunt_by_reg(emcfanctl_2104_registers,__arraycount(emcfanctl_2104_registers),reg);

usr.sbin/emcfanctl/emcfanctlutil.c

258

r = emcfan_hunt_by_reg(emcfanctl_2106_registers,__arraycount(emcfanctl_2106_registers),reg);

usr.sbin/emcfanctl/emcfanctlutil.c

267

r = emcfan_hunt_by_reg(emcfanctl_230x_registers,__arraycount(emcfanctl_230x_registers),reg);

usr.sbin/emcfanctl/emcfanctlutil.c

43

emcfan_read_register(int fd, uint8_t reg, uint8_t *res, bool debug)

usr.sbin/emcfanctl/emcfanctlutil.c

47

err = lseek(fd, reg, SEEK_SET);

usr.sbin/emcfanctl/emcfanctlutil.c

59

fprintf(stderr,"emcfan_read_register: reg=0x%02X, res=0x%02x, return err: %d\n",reg, *res, err);

usr.sbin/emcfanctl/emcfanctlutil.c

65

emcfan_write_register(int fd, uint8_t reg, uint8_t value, bool debug)

usr.sbin/emcfanctl/emcfanctlutil.c

69

err = lseek(fd, reg, SEEK_SET);

usr.sbin/emcfanctl/emcfanctlutil.c

81

fprintf(stderr,"emcfan_write_register: reg=0x%02X, value=0x%02X, return err: %d\n",reg, value, err);

usr.sbin/emcfanctl/emcfanctlutil.c

87

emcfan_rmw_register(int fd, uint8_t reg, uint8_t value,

usr.sbin/emcfanctl/emcfanctlutil.c

96

err = emcfan_read_register(fd, reg, &oldcurrent, debug);

usr.sbin/fwctl/fwcontrol.c

323

uint32_t max, reg, old;

usr.sbin/fwctl/fwcontrol.c

335

reg = read_write_quad(fd, devinfo->eui, BUGET_REG, 1, 0);

usr.sbin/fwctl/fwcontrol.c

339

devinfo->dst, addr, reg);

usr.sbin/fwctl/fwcontrol.c

340

if (reg > 0) {

usr.sbin/fwctl/fwcontrol.c

341

old = (reg & 0x3f);

usr.sbin/fwctl/fwcontrol.c

342

max = (reg & 0x3f00) >> 8;

usr.sbin/fwctl/fwcontrol.c

423

struct csrreg *reg;

usr.sbin/fwctl/fwcontrol.c

436

reg = (struct csrreg *)hdr;

usr.sbin/fwctl/fwcontrol.c

437

printf("vendor ID: 0x%06x\n", reg->val);

usr.sbin/fwctl/fwcontrol.c

460

reg = crom_get(&cc);

usr.sbin/fwctl/fwcontrol.c

464

reg->key,

usr.sbin/fwctl/fwcontrol.c

465

key_types[(reg->key & CSRTYPE_MASK)>>6],

usr.sbin/fwctl/fwcontrol.c

466

reg->key & CSRKEY_MASK, reg->val,

usr.sbin/fwctl/fwcontrol.c

550

struct fw_reg_req_t reg;

usr.sbin/fwctl/fwcontrol.c

554

reg.addr = offset + i;

usr.sbin/fwctl/fwcontrol.c

555

if (ioctl(fd, FWOHCI_RDPHYREG, &reg) < 0)

usr.sbin/fwctl/fwcontrol.c

557

buf[i] = (uint8_t) reg.data;

usr.sbin/fwctl/fwcontrol.c

558

printf("0x%02x ", reg.data);

usr.sbin/fwctl/fwcontrol.c

566

struct fw_reg_req_t reg;

usr.sbin/fwctl/fwcontrol.c

568

reg.addr = 0x7;

usr.sbin/fwctl/fwcontrol.c

569

reg.data = ((page & 7) << 5) | (port & 0xf);

usr.sbin/fwctl/fwcontrol.c

570

if (ioctl(fd, FWOHCI_WRPHYREG, &reg) < 0)

usr.sbin/gspa/gspa/gsp_act.c

120

reg_ind(int reg, int mode)

usr.sbin/gspa/gspa/gsp_act.c

128

o->reg_no = reg;

usr.sbin/gspa/gspa/gsp_act.c

134

reg_indxy(int reg, char *xy)

usr.sbin/gspa/gspa/gsp_act.c

139

return reg_ind(reg, M_INDXY);

usr.sbin/gspa/gspa/gsp_act.c

143

reg_index(int reg, expr disp)

usr.sbin/gspa/gspa/gsp_act.c

147

o = reg_ind(reg, M_INDEX);

usr.sbin/gspa/gspa/gsp_act.c

67

reg_op(int reg)

usr.sbin/gspa/gspa/gsp_act.c

74

o->reg_no = reg;

usr.sbin/gspa/gspa/gsp_ass.h

152

operand reg_op(int reg);

usr.sbin/npf/npftest/libnpftest/npf_bpf_test.c

85

npf_bpfcop_run(unsigned reg)

usr.sbin/npf/npftest/libnpftest/npf_bpf_test.c

89

BPF_STMT(BPF_LD+BPF_W+BPF_MEM, reg),

usr.sbin/npf/npftest/libnpftest/npf_test_subr.c

114

npf_test_addif(const char *ifname, bool reg, bool verbose)

usr.sbin/npf/npftest/libnpftest/npf_test_subr.c

128

if (reg) {

usr.sbin/ofctl/ofctl.c

579

int reg[sizeof(reg_buf)/sizeof(int)];

usr.sbin/ofctl/ofctl.c

635

memcpy(reg, reg_buf, 8);

usr.sbin/ofctl/ofctl.c

636

off += snprintf(buf + off, buflen - off, "%x,%x", reg[0],

usr.sbin/ofctl/ofctl.c

637

reg[1]);

usr.sbin/ofctl/ofctl.c

644

reg[len] = of_decode_int(&reg_buf[len * 4]);

usr.sbin/ofctl/ofctl.c

648

"%x", (reg[0] >> 11) & 31);

usr.sbin/ofctl/ofctl.c

649

if (reg[0] & 0x700)

usr.sbin/ofctl/ofctl.c

651

",%x", (reg[0] >> 8) & 7);

usr.sbin/ofctl/ofctl.c

654

"%x", (reg[0] >> 4) & 63);

usr.sbin/ofctl/ofctl.c

657

",%x", reg[len]);

usr.sbin/ofctl/ofctl.c

662

off += snprintf(buf + off, buflen - off, "%x", reg[0]);

usr.sbin/ofctl/ofctl.c

665

",%x", reg[len]);

usr.sbin/pcictl/pcictl.c

254

u_int reg;

usr.sbin/pcictl/pcictl.c

282

reg = parse_reg(argv[0]);

usr.sbin/pcictl/pcictl.c

283

if (pcibus_conf_read(pcifd, bus, dev, func, reg, &value) == -1)

usr.sbin/pcictl/pcictl.c

285

"(bus %d dev %d func %d reg %u)", bus, dev, func, reg);

usr.sbin/pcictl/pcictl.c

294

u_int reg;

usr.sbin/pcictl/pcictl.c

322

reg = parse_reg(argv[0]);

usr.sbin/pcictl/pcictl.c

325

if (pcibus_conf_write(pcifd, bus, dev, func, reg, value) == -1)

usr.sbin/pcictl/pcictl.c

328

bus, dev, func, reg, value);

usr.sbin/rpcbind/pmap_svc.c

170

struct pmap reg;

usr.sbin/rpcbind/pmap_svc.c

176

if (!svc_getargs(xprt, (xdrproc_t) xdr_pmap, (char *)&reg)) {

usr.sbin/rpcbind/pmap_svc.c

185

reg.pm_prog, reg.pm_vers);

usr.sbin/rpcbind/pmap_svc.c

188

if (!check_access(xprt, op, &reg, PMAPVERS)) {

usr.sbin/rpcbind/pmap_svc.c

210

rpcbreg.r_prog = reg.pm_prog;

usr.sbin/rpcbind/pmap_svc.c

211

rpcbreg.r_vers = reg.pm_vers;

usr.sbin/rpcbind/pmap_svc.c

217

(int)((reg.pm_port >> 8) & 0xff),

usr.sbin/rpcbind/pmap_svc.c

218

(int)(reg.pm_port & 0xff));

usr.sbin/rpcbind/pmap_svc.c

220

if (reg.pm_prot == IPPROTO_UDP) {

usr.sbin/rpcbind/pmap_svc.c

222

} else if (reg.pm_prot == IPPROTO_TCP) {

usr.sbin/rpcbind/pmap_svc.c

264

struct pmap reg;

usr.sbin/rpcbind/pmap_svc.c

272

if (!svc_getargs(xprt, (xdrproc_t) xdr_pmap, (char *)&reg)) {

usr.sbin/rpcbind/pmap_svc.c

277

if (!check_access(xprt, PMAPPROC_GETPORT, &reg, PMAPVERS)) {

usr.sbin/rpcbind/pmap_svc.c

287

reg.pm_prog, reg.pm_vers,

usr.sbin/rpcbind/pmap_svc.c

288

reg.pm_prot == IPPROTO_UDP ? "udp" : "tcp", uaddr);

usr.sbin/rpcbind/pmap_svc.c

292

fnd = find_service_pmap(reg.pm_prog, reg.pm_vers, reg.pm_prot);

usr.sbin/rpcbind/pmap_svc.c

298

if (reg.pm_prot == IPPROTO_UDP) {

usr.sbin/rpcbind/pmap_svc.c

317

delete_prog(reg.pm_prog);

usr.sbin/rpcbind/pmap_svc.c

334

rpcbs_getaddr(RPCBVERS_2_STAT, reg.pm_prog, reg.pm_vers,

usr.sbin/rpcbind/pmap_svc.c

335

reg.pm_prot == IPPROTO_UDP ? udptrans : tcptrans,

usr.sbin/rpcbind/rpcb_svc_com.c

160

RPCB reg, *a;

usr.sbin/rpcbind/rpcb_svc_com.c

163

reg = *regp;

usr.sbin/rpcbind/rpcb_svc_com.c

169

fnd = find_service(reg.r_prog, reg.r_vers, reg.r_netid);

usr.sbin/rpcbind/rpcb_svc_com.c

170

if (fnd && (fnd->rpcb_map.r_vers == reg.r_vers)) {

usr.sbin/rpcbind/rpcb_svc_com.c

171

if (!strcmp(fnd->rpcb_map.r_addr, reg.r_addr))

usr.sbin/rpcbind/rpcb_svc_com.c

187

a->r_prog = reg.r_prog;

usr.sbin/rpcbind/rpcb_svc_com.c

188

a->r_vers = reg.r_vers;

usr.sbin/rpcbind/rpcb_svc_com.c

189

a->r_netid = strdup(reg.r_netid);

usr.sbin/rpcbind/rpcb_svc_com.c

190

a->r_addr = strdup(reg.r_addr);

usr.sbin/rpcbind/rpcb_svc_com.c

299

RPCB reg;

usr.sbin/rpcbind/rpcb_svc_com.c

307

reg.r_prog = rbl->rpcb_map.r_prog;

usr.sbin/rpcbind/rpcb_svc_com.c

308

reg.r_vers = rbl->rpcb_map.r_vers;

usr.sbin/rpcbind/rpcb_svc_com.c

309

reg.r_netid = strdup(rbl->rpcb_map.r_netid);

usr.sbin/rpcbind/rpcb_svc_com.c

310

if (reg.r_netid == NULL)

usr.sbin/rpcbind/rpcb_svc_com.c

313

(void)map_unset(&reg, rpcbind_superuser);

usr.sbin/rpcbind/rpcb_svc_com.c

314

free(reg.r_netid);