#ifdef DDB
#define integrate
#define hide
#else
#define integrate static inline
#define hide static
#endif
#define MC_REGSPACING 16
#define MC_REGSIZE MACE_NREGS * MC_REGSPACING
#define MACE_REG(x) ((x)*MC_REGSPACING)
#define NIC_GET(sc, reg) (bus_space_read_1((sc)->sc_regt, \
(sc)->sc_regh, MACE_REG(reg)))
#define NIC_PUT(sc, reg, val) (bus_space_write_1((sc)->sc_regt, \
(sc)->sc_regh, MACE_REG(reg), (val)))
#ifndef MC_RXDMABUFS
#define MC_RXDMABUFS 4
#endif
#if (MC_RXDMABUFS < 2)
#error Must have at least two buffers for DMA!
#endif
#define MC_NPAGES ((MC_RXDMABUFS * 0x800 + PAGE_SIZE - 1) / PAGE_SIZE)
struct mc_rxframe {
u_int8_t rx_rcvcnt;
u_int8_t rx_rcvsts;
u_int8_t rx_rntpc;
u_int8_t rx_rcvcc;
u_char *rx_frame;
};
struct mc_softc {
device_t sc_dev;
struct ethercom sc_ethercom;
#define sc_if sc_ethercom.ec_if
struct mc_rxframe sc_rxframe;
u_int8_t sc_biucc;
u_int8_t sc_fifocc;
u_int8_t sc_plscc;
u_int8_t sc_enaddr[6];
u_int8_t sc_pad[2];
int sc_havecarrier;
void (*sc_bus_init)(struct mc_softc *);
void (*sc_putpacket)(struct mc_softc *, u_int);
bus_space_tag_t sc_regt;
bus_space_handle_t sc_regh;
bus_dma_tag_t sc_dmat;
bus_dmamap_t sc_dmam_tx, sc_dmam_rx;
bus_dma_segment_t sc_dmasegs_tx, sc_dmasegs_rx;
uint8_t *sc_txbuf, *sc_rxbuf;
bus_addr_t sc_txbuf_phys, sc_rxbuf_phys;
int sc_tail;
int sc_rxset;
int sc_txset, sc_txseti;
bool sc_txbusy;
krndsource_t rnd_source;
};
int mcsetup(struct mc_softc *, u_int8_t *);
void mcintr(void *arg);
void mc_rint(struct mc_softc *);
u_char mc_get_enaddr(bus_space_tag_t, bus_space_handle_t, bus_size_t,
u_char *);