#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: if_ni.c,v 1.50 2022/09/18 16:51:28 thorpej Exp $");
#include "opt_inet.h"
#include <sys/param.h>
#include <sys/mbuf.h>
#include <sys/socket.h>
#include <sys/device.h>
#include <sys/systm.h>
#include <sys/sockio.h>
#include <sys/sched.h>
#include <net/if.h>
#include <net/if_ether.h>
#include <net/if_dl.h>
#include <net/bpf.h>
#include <netinet/in.h>
#include <netinet/if_inarp.h>
#include <sys/bus.h>
#ifdef __vax__
#include <machine/mtpr.h>
#include <machine/pte.h>
#endif
#include <dev/bi/bireg.h>
#include <dev/bi/bivar.h>
#include "ioconf.h"
#include "locators.h"
#define NMSGBUF 8
#define NTXBUF 16
#define NTXFRAGS 8
#define NRXBUF 24
#define NBDESCS (NTXBUF * NTXFRAGS + NRXBUF)
#define NQUEUES 3
#define PKTHDR 18
#define RXADD 18
#define TXADD (10+NTXFRAGS*8)
#define MSGADD 134
#include <dev/bi/if_nireg.h>
#define NRETRIES 100
#define INSQTI(e, h) ({ \
int ret = 0, __i; \
for (__i = 0; __i < NRETRIES; __i++) { \
if ((ret = insqti(e, h)) != ILCK_FAILED) \
break; \
} \
if (__i == NRETRIES) \
panic("ni: insqti failed at %d", __LINE__); \
ret; \
})
#define REMQHI(h) ({ \
int __i; void *ret = NULL; \
for (__i = 0; __i < NRETRIES; __i++) { \
if ((ret = remqhi(h)) != (void *)ILCK_FAILED) \
break; \
} \
if (__i == NRETRIES) \
panic("ni: remqhi failed at %d", __LINE__); \
ret; \
})
#define nipqb (&sc->sc_gvppqb->nc_pqb)
#define gvp sc->sc_gvppqb
#define fqb sc->sc_fqb
#define bbd sc->sc_bbd
struct ni_softc {
device_t sc_dev;
struct evcnt sc_intrcnt;
struct ethercom sc_ec;
#define sc_if sc_ec.ec_if
bus_space_tag_t sc_iot;
bus_addr_t sc_ioh;
bus_dma_tag_t sc_dmat;
struct ni_gvppqb *sc_gvppqb;
struct ni_gvppqb *sc_pgvppqb;
struct ni_fqb *sc_fqb;
struct ni_bbd *sc_bbd;
uint8_t sc_enaddr[ETHER_ADDR_LEN];
};
static int nimatch(device_t, cfdata_t, void *);
static void niattach(device_t, device_t, void *);
static void niinit(struct ni_softc *);
static void nistart(struct ifnet *);
static void niintr(void *);
static int niioctl(struct ifnet *, u_long, void *);
static int ni_add_rxbuf(struct ni_softc *, struct ni_dg *, int);
static void ni_setup(struct ni_softc *);
static void nitimeout(struct ifnet *);
static void ni_shutdown(void *);
static void ni_getpgs(struct ni_softc *, int, void **, paddr_t *);
static int failtest(struct ni_softc *, int, int, int, const char *);
volatile int endwait, retry;
CFATTACH_DECL_NEW(ni, sizeof(struct ni_softc),
nimatch, niattach, NULL, NULL);
#define NI_WREG(csr, val) \
bus_space_write_4(sc->sc_iot, sc->sc_ioh, csr, val)
#define NI_RREG(csr) \
bus_space_read_4(sc->sc_iot, sc->sc_ioh, csr)
#define WAITREG(csr,val) while (NI_RREG(csr) & val);
static int
nimatch(device_t parent, cfdata_t cf, void *aux)
{
struct bi_attach_args *ba = aux;
u_short type;
type = bus_space_read_2(ba->ba_iot, ba->ba_ioh, BIREG_DTYPE);
if (type != BIDT_DEBNA && type != BIDT_DEBNT && type != BIDT_DEBNK)
return 0;
if (cf->cf_loc[BICF_NODE] != BICF_NODE_DEFAULT &&
cf->cf_loc[BICF_NODE] != ba->ba_nodenr)
return 0;
return 1;
}
static void
ni_getpgs(struct ni_softc *sc, int size, void **v, paddr_t *p)
{
bus_dma_segment_t seg;
int nsegs, error;
if ((error = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, &seg, 1,
&nsegs, BUS_DMA_NOWAIT)) != 0)
panic(" unable to allocate memory: error %d", error);
if ((error = bus_dmamem_map(sc->sc_dmat, &seg, nsegs, size, v,
BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0)
panic(" unable to map memory: error %d", error);
if (p)
*p = seg.ds_addr;
memset(*v, 0, size);
}
static int
failtest(struct ni_softc *sc, int reg, int mask, int test, const char *str)
{
int i = 100;
do {
DELAY(100000);
} while (((NI_RREG(reg) & mask) != test) && --i);
if (i == 0) {
printf("%s: %s\n", device_xname(sc->sc_dev), str);
return 1;
}
return 0;
}
static void
niattach(device_t parent, device_t self, void *aux)
{
struct bi_attach_args *ba = aux;
struct ni_softc *sc = device_private(self);
struct ifnet *ifp = (struct ifnet *)&sc->sc_if;
struct ni_msg *msg;
struct ni_ptdb *ptdb;
void *va;
int i, j, s;
u_short type;
sc->sc_dev = self;
type = bus_space_read_2(ba->ba_iot, ba->ba_ioh, BIREG_DTYPE);
aprint_normal(": DEBN%c\n", type == BIDT_DEBNA ? 'A'
: type == BIDT_DEBNT ? 'T' : 'K');
sc->sc_iot = ba->ba_iot;
sc->sc_ioh = ba->ba_ioh;
sc->sc_dmat = ba->ba_dmat;
bi_intr_establish(ba->ba_icookie, ba->ba_ivec,
niintr, sc, &sc->sc_intrcnt);
evcnt_attach_dynamic(&sc->sc_intrcnt, EVCNT_TYPE_INTR, NULL,
device_xname(self), "intr");
ni_getpgs(sc, sizeof(struct ni_gvppqb), (void **)&sc->sc_gvppqb,
(paddr_t *)&sc->sc_pgvppqb);
ni_getpgs(sc, sizeof(struct ni_fqb), (void **)&sc->sc_fqb, 0);
ni_getpgs(sc, NBDESCS * sizeof(struct ni_bbd),
(void **)&sc->sc_bbd, 0);
nipqb->np_veclvl = (ba->ba_ivec << 2) + 2;
nipqb->np_node = ba->ba_intcpu;
nipqb->np_vpqb = (uint32_t)gvp;
#ifdef __vax__
nipqb->np_spt = nipqb->np_gpt = mfpr(PR_SBR);
nipqb->np_sptlen = nipqb->np_gptlen = mfpr(PR_SLR);
#else
#error Must fix support for non-vax.
#endif
nipqb->np_bvplvl = 1;
nipqb->np_vfqb = (uint32_t)fqb;
nipqb->np_vbdt = (uint32_t)bbd;
nipqb->np_nbdr = NBDESCS;
nipqb->np_freeq = NQUEUES;
fqb->nf_mlen = PKTHDR+MSGADD;
fqb->nf_dlen = PKTHDR+TXADD;
fqb->nf_rlen = PKTHDR+RXADD;
strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ);
ifp->if_softc = sc;
ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
ifp->if_start = nistart;
ifp->if_ioctl = niioctl;
ifp->if_watchdog = nitimeout;
IFQ_SET_READY(&ifp->if_snd);
NI_WREG(BIREG_VAXBICSR, NI_RREG(BIREG_VAXBICSR) | BICSR_NRST);
DELAY(500000);
i = 20;
while ((NI_RREG(BIREG_VAXBICSR) & BICSR_BROKE) && --i)
DELAY(500000);
if (i == 0) {
aprint_error_dev(self, "BROKE bit set after reset\n");
return;
}
if (failtest(sc, NI_PSR, PSR_STATE, PSR_UNDEF, "not undefined state"))
return;
NI_WREG(NI_PSR, NI_RREG(NI_PSR) & ~PSR_OWN);
NI_WREG(NI_PCR, NI_RREG(NI_PCR) & ~PCR_OWN);
NI_WREG(NI_PCR, (uint32_t)sc->sc_pgvppqb | PCR_INIT | PCR_OWN);
while (NI_RREG(NI_PCR) & PCR_OWN)
DELAY(100000);
if (failtest(sc, NI_PSR, PSR_INITED, PSR_INITED, "failed initialize"))
return;
NI_WREG(NI_PSR, NI_RREG(NI_PSR) & ~PSR_OWN);
WAITREG(NI_PCR, PCR_OWN);
NI_WREG(NI_PCR, PCR_OWN | PCR_ENABLE);
WAITREG(NI_PCR, PCR_OWN);
WAITREG(NI_PSR, PSR_OWN);
if (failtest(sc, NI_PSR, PSR_STATE, PSR_ENABLED, "failed enable"))
return;
NI_WREG(NI_PSR, NI_RREG(NI_PSR) & ~PSR_OWN);
#if NBPG < 4096
#error pagesize too small
#endif
s = splvm();
ni_getpgs(sc, NMSGBUF * 512, &va, 0);
for (i = 0; i < NMSGBUF; i++) {
msg = (void *)((char *)va + i * 512);
INSQTI(msg, &fqb->nf_mforw);
}
WAITREG(NI_PCR, PCR_OWN);
NI_WREG(NI_PCR, PCR_FREEQNE | PCR_MFREEQ | PCR_OWN);
WAITREG(NI_PCR, PCR_OWN);
ni_getpgs(sc, NTXBUF * 512, &va, 0);
for (i = 0; i < NTXBUF; i++) {
struct ni_dg *data;
data = (void *)((char *)va + i * 512);
data->nd_status = 0;
data->nd_len = TXADD;
data->nd_ptdbidx = 1;
data->nd_opcode = BVP_DGRAM;
for (j = 0; j < NTXFRAGS; j++) {
data->bufs[j]._offset = 0;
data->bufs[j]._key = 1;
bbd[i * NTXFRAGS + j].nb_key = 1;
bbd[i * NTXFRAGS + j].nb_status = 0;
data->bufs[j]._index = i * NTXFRAGS + j;
}
INSQTI(data, &fqb->nf_dforw);
}
WAITREG(NI_PCR, PCR_OWN);
NI_WREG(NI_PCR, PCR_FREEQNE | PCR_DFREEQ | PCR_OWN);
WAITREG(NI_PCR, PCR_OWN);
ni_getpgs(sc, NRXBUF * 512, &va, 0);
for (i = 0; i < NRXBUF; i++) {
struct ni_dg *data;
int idx;
data = (void *)((char *)va + i * 512);
data->nd_len = RXADD;
data->nd_opcode = BVP_DGRAMRX;
data->nd_ptdbidx = 2;
data->bufs[0]._key = 1;
idx = NTXBUF * NTXFRAGS + i;
if (ni_add_rxbuf(sc, data, idx))
panic("niattach: ni_add_rxbuf: out of mbufs");
INSQTI(data, &fqb->nf_rforw);
}
WAITREG(NI_PCR, PCR_OWN);
NI_WREG(NI_PCR, PCR_FREEQNE | PCR_RFREEQ | PCR_OWN);
WAITREG(NI_PCR, PCR_OWN);
splx(s);
msg = REMQHI(&fqb->nf_mforw);
msg->nm_opcode = BVP_MSG;
msg->nm_status = 0;
msg->nm_len = sizeof(struct ni_param) + 6;
msg->nm_opcode2 = NI_WPARAM;
((struct ni_param *)&msg->nm_text[0])->np_flags = NP_PAD;
endwait = retry = 0;
INSQTI(msg, &gvp->nc_forw0);
retry: WAITREG(NI_PCR, PCR_OWN);
NI_WREG(NI_PCR, PCR_CMDQNE | PCR_CMDQ0 | PCR_OWN);
WAITREG(NI_PCR, PCR_OWN);
i = 1000;
while (endwait == 0 && --i)
DELAY(10000);
if (endwait == 0) {
if (++retry < 3)
goto retry;
aprint_error_dev(self, "no response to set params\n");
return;
}
msg = REMQHI(&fqb->nf_mforw);
msg->nm_opcode = BVP_MSG;
msg->nm_status = 0;
msg->nm_len = sizeof(struct ni_param) + 6;
msg->nm_opcode2 = NI_RCCNTR;
INSQTI(msg, &gvp->nc_forw0);
WAITREG(NI_PCR, PCR_OWN);
NI_WREG(NI_PCR, PCR_CMDQNE | PCR_CMDQ0 | PCR_OWN);
WAITREG(NI_PCR, PCR_OWN);
msg = REMQHI(&fqb->nf_mforw);
msg->nm_opcode = BVP_MSG;
msg->nm_status = 0;
msg->nm_len = 18;
msg->nm_opcode2 = NI_STPTDB;
ptdb = (struct ni_ptdb *)&msg->nm_text[0];
memset(ptdb, 0, sizeof(struct ni_ptdb));
ptdb->np_index = 1;
ptdb->np_fque = 1;
INSQTI(msg, &gvp->nc_forw0);
WAITREG(NI_PCR, PCR_OWN);
NI_WREG(NI_PCR, PCR_CMDQNE | PCR_CMDQ0 | PCR_OWN);
WAITREG(NI_PCR, PCR_OWN);
WAITREG(NI_PSR, PSR_OWN);
aprint_normal_dev(self, "hardware address %s\n",
ether_sprintf(sc->sc_enaddr));
if_attach(ifp);
ether_ifattach(ifp, sc->sc_enaddr);
if (shutdownhook_establish(ni_shutdown, sc) == 0)
aprint_error_dev(self,
"WARNING: unable to establish shutdown hook\n");
}
void
niinit(struct ni_softc *sc)
{
struct ifnet *ifp = &sc->sc_if;
ifp->if_flags |= IFF_RUNNING;
ni_setup(sc);
}
void
nistart(struct ifnet *ifp)
{
struct ni_softc *sc = ifp->if_softc;
struct ni_dg *data;
struct ni_bbd *bdp;
struct mbuf *m, *m0;
int i, cnt, res, mlen;
#ifdef DEBUG
if (ifp->if_flags & IFF_DEBUG)
printf("%s: nistart\n", device_xname(sc->sc_dev));
#endif
while (fqb->nf_dforw) {
IFQ_POLL(&ifp->if_snd, m);
if (m == 0)
break;
data = REMQHI(&fqb->nf_dforw);
if ((int)data == Q_EMPTY) {
break;
}
IFQ_DEQUEUE(&ifp->if_snd, m);
for (m0 = m, cnt = 0; m0; m0 = m0->m_next)
if (m0->m_len)
cnt++;
if (cnt > NTXFRAGS)
panic("nistart");
bpf_mtap(ifp, m, BPF_D_OUT);
bdp = &bbd[(data->bufs[0]._index & 0x7fff)];
for (m0 = m, i = 0, mlen = 0; m0; m0 = m0->m_next) {
if (m0->m_len == 0)
continue;
bdp->nb_status = (mtod(m0, uint32_t) & NIBD_OFFSET) |
NIBD_VALID;
bdp->nb_pte = (uint32_t)kvtopte(mtod(m0, void *));
bdp->nb_len = m0->m_len;
data->bufs[i]._offset = 0;
data->bufs[i]._len = bdp->nb_len;
data->bufs[i]._index |= NIDG_CHAIN;
mlen += bdp->nb_len;
bdp++;
i++;
}
data->nd_opcode = BVP_DGRAM;
data->nd_pad3 = 1;
data->nd_ptdbidx = 1;
data->nd_len = 10 + i * 8;
data->bufs[i - 1]._index &= ~NIDG_CHAIN;
data->nd_cmdref = (uint32_t)m;
#ifdef DEBUG
if (ifp->if_flags & IFF_DEBUG)
printf("%s: sending %d bytes (%d segments)\n",
device_xname(sc->sc_dev), mlen, i);
#endif
res = INSQTI(data, &gvp->nc_forw0);
if (res == Q_EMPTY) {
WAITREG(NI_PCR, PCR_OWN);
NI_WREG(NI_PCR, PCR_CMDQNE | PCR_CMDQ0 | PCR_OWN);
}
}
}
void
niintr(void *arg)
{
struct ni_softc *sc = arg;
struct ni_dg *data;
struct ni_msg *msg;
struct ifnet *ifp = &sc->sc_if;
struct ni_bbd *bd;
struct mbuf *m;
int idx, res;
if ((NI_RREG(NI_PSR) & PSR_STATE) != PSR_ENABLED)
return;
if ((NI_RREG(NI_PSR) & PSR_ERR))
printf("%s: PSR %x\n", device_xname(sc->sc_dev),
NI_RREG(NI_PSR));
KERNEL_LOCK(1, NULL);
while ((NI_RREG(NI_PSR) & PSR_RSQ) && (data = REMQHI(&gvp->nc_forwr))) {
switch (data->nd_opcode) {
case BVP_DGRAMRX:
idx = data->bufs[0]._index;
bd = &bbd[idx];
m = (void *)data->nd_cmdref;
m->m_pkthdr.len = m->m_len =
data->bufs[0]._len - ETHER_CRC_LEN;
m_set_rcvif(m, ifp);
if (ni_add_rxbuf(sc, data, idx)) {
bd->nb_len = (m->m_ext.ext_size - 2);
bd->nb_pte =
(long)kvtopte(m->m_ext.ext_buf);
bd->nb_status = 2 | NIBD_VALID;
bd->nb_key = 1;
}
data->nd_len = RXADD;
data->nd_status = 0;
res = INSQTI(data, &fqb->nf_rforw);
if (res == Q_EMPTY) {
WAITREG(NI_PCR, PCR_OWN);
NI_WREG(NI_PCR,
PCR_FREEQNE | PCR_RFREEQ | PCR_OWN);
}
if (m == (void *)data->nd_cmdref)
break;
if_percpuq_enqueue(ifp->if_percpuq, m);
break;
case BVP_DGRAM:
m = (struct mbuf *)data->nd_cmdref;
m_freem(m);
res = INSQTI(data, &fqb->nf_dforw);
if (res == Q_EMPTY) {
WAITREG(NI_PCR, PCR_OWN);
NI_WREG(NI_PCR,
PCR_FREEQNE | PCR_DFREEQ | PCR_OWN);
}
break;
case BVP_MSGRX:
msg = (struct ni_msg *)data;
switch (msg->nm_opcode2) {
case NI_WPARAM:
memcpy(sc->sc_enaddr, ((struct ni_param *)&msg->nm_text[0])->np_dpa, ETHER_ADDR_LEN);
endwait = 1;
break;
case NI_RCCNTR:
case NI_CLPTDB:
case NI_STPTDB:
break;
default:
printf("Unkn resp %d\n",
msg->nm_opcode2);
break;
}
res = INSQTI(data, &fqb->nf_mforw);
if (res == Q_EMPTY) {
WAITREG(NI_PCR, PCR_OWN);
NI_WREG(NI_PCR,
PCR_FREEQNE | PCR_MFREEQ | PCR_OWN);
}
break;
default:
printf("Unknown opcode %d\n", data->nd_opcode);
res = INSQTI(data, &fqb->nf_mforw);
if (res == Q_EMPTY) {
WAITREG(NI_PCR, PCR_OWN);
NI_WREG(NI_PCR,
PCR_FREEQNE | PCR_MFREEQ | PCR_OWN);
}
}
}
nistart(ifp);
NI_WREG(NI_PSR, NI_RREG(NI_PSR) & ~(PSR_OWN | PSR_RSQ));
KERNEL_UNLOCK_ONE(NULL);
}
int
niioctl(struct ifnet *ifp, u_long cmd, void *data)
{
struct ni_softc *sc = ifp->if_softc;
struct ifaddr *ifa = (struct ifaddr *)data;
int s = splnet(), error = 0;
switch (cmd) {
case SIOCINITIFADDR:
ifp->if_flags |= IFF_UP;
switch (ifa->ifa_addr->sa_family) {
#ifdef INET
case AF_INET:
niinit(sc);
arp_ifinit(ifp, ifa);
break;
#endif
}
break;
case SIOCSIFFLAGS:
if ((error = ifioctl_common(ifp, cmd, data)) != 0)
break;
switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) {
case IFF_RUNNING:
ifp->if_flags &= ~IFF_RUNNING;
ni_setup(sc);
break;
case IFF_UP:
niinit(sc);
break;
case IFF_UP | IFF_RUNNING:
ni_setup(sc);
break;
default:
break;
}
break;
case SIOCADDMULTI:
case SIOCDELMULTI:
if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) {
if (ifp->if_flags & IFF_RUNNING)
ni_setup(sc);
error = 0;
}
break;
default:
error = ether_ioctl(ifp, cmd, data);
break;
}
splx(s);
return error;
}
int
ni_add_rxbuf(struct ni_softc *sc, struct ni_dg *data, int idx)
{
struct ni_bbd *bd = &bbd[idx];
struct mbuf *m;
MGETHDR(m, M_DONTWAIT, MT_DATA);
if (m == NULL)
return ENOBUFS;
MCLGET(m, M_DONTWAIT);
if ((m->m_flags & M_EXT) == 0) {
m_freem(m);
return ENOBUFS;
}
m->m_data += 2;
bd->nb_len = (m->m_ext.ext_size - 2);
bd->nb_pte = (long)kvtopte(m->m_ext.ext_buf);
bd->nb_status = 2 | NIBD_VALID;
bd->nb_key = 1;
data->bufs[0]._offset = 0;
data->bufs[0]._len = bd->nb_len;
data->bufs[0]._index = idx;
data->nd_cmdref = (long)m;
return 0;
}
void
ni_setup(struct ni_softc *sc)
{
struct ethercom *ec = &sc->sc_ec;
struct ifnet *ifp = &sc->sc_if;
struct ni_msg *msg;
struct ni_ptdb *ptdb;
struct ether_multi *enm;
struct ether_multistep step;
int i, res;
msg = REMQHI(&fqb->nf_mforw);
if ((int)msg == Q_EMPTY)
return;
ptdb = (struct ni_ptdb *)&msg->nm_text[0];
memset(ptdb, 0, sizeof(struct ni_ptdb));
msg->nm_opcode = BVP_MSG;
msg->nm_len = 18;
ptdb->np_index = 2;
ptdb->np_fque = 2;
if (ifp->if_flags & IFF_RUNNING) {
msg->nm_opcode2 = NI_STPTDB;
ptdb->np_type = ETHERTYPE_IP;
ptdb->np_flags = PTDB_UNKN | PTDB_BDC;
if (ifp->if_flags & IFF_PROMISC)
ptdb->np_flags |= PTDB_PROMISC;
memset(ptdb->np_mcast[0], 0xff, ETHER_ADDR_LEN);
ptdb->np_adrlen = 1;
msg->nm_len += 8;
ifp->if_flags &= ~IFF_ALLMULTI;
if ((ifp->if_flags & IFF_PROMISC) == 0) {
ETHER_LOCK(ec);
ETHER_FIRST_MULTI(step, ec, enm);
i = 1;
while (enm != NULL) {
if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6)) {
ifp->if_flags |= IFF_ALLMULTI;
ptdb->np_flags |= PTDB_AMC;
break;
}
msg->nm_len += 8;
ptdb->np_adrlen++;
memcpy(ptdb->np_mcast[i++], enm->enm_addrlo,
ETHER_ADDR_LEN);
ETHER_NEXT_MULTI(step, enm);
}
ETHER_UNLOCK(ec);
}
} else
msg->nm_opcode2 = NI_CLPTDB;
res = INSQTI(msg, &gvp->nc_forw0);
if (res == Q_EMPTY) {
WAITREG(NI_PCR, PCR_OWN);
NI_WREG(NI_PCR, PCR_CMDQNE | PCR_CMDQ0 | PCR_OWN);
}
}
void
nitimeout(struct ifnet *ifp)
{
#if 0
struct ni_softc *sc = ifp->if_softc;
if (sc->sc_inq == 0)
return;
printf("%s: xmit logic died, resetting...\n", device_xname(sc->sc_dev));
niinit(sc);
#endif
}
void
ni_shutdown(void *arg)
{
struct ni_softc *sc = arg;
WAITREG(NI_PCR, PCR_OWN);
NI_WREG(NI_PCR, PCR_OWN | PCR_SHUTDOWN);
WAITREG(NI_PCR, PCR_OWN);
WAITREG(NI_PSR, PSR_OWN);
}