arch/alpha/include/asm/atomic.h
106
:"=&r" (temp), "=m" (v->counter) \
arch/alpha/include/asm/atomic.h
107
:"Ir" (i), "m" (v->counter)); \
arch/alpha/include/asm/atomic.h
112
arch_atomic64_##op##_return_relaxed(s64 i, atomic64_t * v) \
arch/alpha/include/asm/atomic.h
124
:"=&r" (temp), "=m" (v->counter), "=&r" (result) \
arch/alpha/include/asm/atomic.h
125
:"Ir" (i), "m" (v->counter) : "memory"); \
arch/alpha/include/asm/atomic.h
132
arch_atomic64_fetch_##op##_relaxed(s64 i, atomic64_t * v) \
arch/alpha/include/asm/atomic.h
143
:"=&r" (temp), "=m" (v->counter), "=&r" (result) \
arch/alpha/include/asm/atomic.h
144
:"Ir" (i), "m" (v->counter) : "memory"); \
arch/alpha/include/asm/atomic.h
203
static __inline__ int arch_atomic_fetch_add_unless(atomic_t *v, int a, int u)
arch/alpha/include/asm/atomic.h
219
: [mem] "m"(*v), [a] "rI"(a), [u] "rI"((long)u)
arch/alpha/include/asm/atomic.h
226
static __inline__ s64 arch_atomic64_fetch_add_unless(atomic64_t *v, s64 a, s64 u)
arch/alpha/include/asm/atomic.h
242
: [mem] "m"(*v), [a] "rI"(a), [u] "rI"(u)
arch/alpha/include/asm/atomic.h
249
static inline s64 arch_atomic64_dec_if_positive(atomic64_t *v)
arch/alpha/include/asm/atomic.h
264
: [mem] "m"(*v)
arch/alpha/include/asm/atomic.h
29
#define arch_atomic_read(v) READ_ONCE((v)->counter)
arch/alpha/include/asm/atomic.h
30
#define arch_atomic64_read(v) READ_ONCE((v)->counter)
arch/alpha/include/asm/atomic.h
32
#define arch_atomic_set(v,i) WRITE_ONCE((v)->counter, (i))
arch/alpha/include/asm/atomic.h
33
#define arch_atomic64_set(v,i) WRITE_ONCE((v)->counter, (i))
arch/alpha/include/asm/atomic.h
42
static __inline__ void arch_atomic_##op(int i, atomic_t * v) \
arch/alpha/include/asm/atomic.h
53
:"=&r" (temp), "=m" (v->counter) \
arch/alpha/include/asm/atomic.h
54
:"Ir" (i), "m" (v->counter)); \
arch/alpha/include/asm/atomic.h
58
static inline int arch_atomic_##op##_return_relaxed(int i, atomic_t *v) \
arch/alpha/include/asm/atomic.h
70
:"=&r" (temp), "=m" (v->counter), "=&r" (result) \
arch/alpha/include/asm/atomic.h
71
:"Ir" (i), "m" (v->counter) : "memory"); \
arch/alpha/include/asm/atomic.h
77
static inline int arch_atomic_fetch_##op##_relaxed(int i, atomic_t *v) \
arch/alpha/include/asm/atomic.h
88
:"=&r" (temp), "=m" (v->counter), "=&r" (result) \
arch/alpha/include/asm/atomic.h
89
:"Ir" (i), "m" (v->counter) : "memory"); \
arch/alpha/include/asm/atomic.h
95
static __inline__ void arch_atomic64_##op(s64 i, atomic64_t * v) \
arch/alpha/include/asm/io.h
544
#define iowrite16be(v,p) iowrite16(swab16(v), (p))
arch/alpha/include/asm/io.h
545
#define iowrite32be(v,p) iowrite32(swab32(v), (p))
arch/alpha/include/asm/io.h
546
#define iowrite64be(v,p) iowrite64(swab64(v), (p))
arch/alpha/include/asm/string.h
71
static inline void *memset16(uint16_t *p, uint16_t v, size_t n)
arch/alpha/include/asm/string.h
73
if (__builtin_constant_p(v))
arch/alpha/include/asm/string.h
74
return __constant_c_memset(p, 0x0001000100010001UL * v, n * 2);
arch/alpha/include/asm/string.h
75
return __memset16(p, v, n * 2);
arch/alpha/include/asm/vga.h
50
#define vga_writeb(v,a) writeb(v, (u8 __iomem *)(a))
arch/alpha/kernel/osf_sys.c
888
unsigned v, w, status;
arch/alpha/kernel/osf_sys.c
890
if (get_user(v, p) || get_user(w, p + 1))
arch/alpha/kernel/osf_sys.c
892
switch (v) {
arch/alpha/kernel/setup.c
1327
c_next(struct seq_file *f, void *v, loff_t *pos)
arch/alpha/kernel/setup.c
1334
c_stop(struct seq_file *f, void *v)
arch/alpha/kernel/srm_env.c
63
static int srm_env_proc_show(struct seq_file *m, void *v)
arch/alpha/kernel/sys_cabriolet.c
138
pc164_srm_device_interrupt(unsigned long v)
arch/alpha/kernel/sys_cabriolet.c
141
srm_device_interrupt(v);
arch/alpha/kernel/sys_cabriolet.c
146
pc164_device_interrupt(unsigned long v)
arch/alpha/kernel/sys_cabriolet.c
149
cabriolet_device_interrupt(v);
arch/alpha/kernel/sys_cabriolet.c
64
cabriolet_device_interrupt(unsigned long v)
arch/alpha/kernel/sys_cabriolet.c
80
isa_device_interrupt(v);
arch/alpha/kernel/sys_cabriolet.c
88
common_init_irq(void (*srm_dev_int)(unsigned long v))
arch/alpha/kernel/termios.c
10
if (copy_from_user(&v, termio, sizeof(struct termio)))
arch/alpha/kernel/termios.c
13
termios->c_iflag = (0xffff0000 & termios->c_iflag) | v.c_iflag;
arch/alpha/kernel/termios.c
14
termios->c_oflag = (0xffff0000 & termios->c_oflag) | v.c_oflag;
arch/alpha/kernel/termios.c
15
termios->c_cflag = (0xffff0000 & termios->c_cflag) | v.c_cflag;
arch/alpha/kernel/termios.c
16
termios->c_lflag = (0xffff0000 & termios->c_lflag) | v.c_lflag;
arch/alpha/kernel/termios.c
17
termios->c_line = (0xffff0000 & termios->c_lflag) | v.c_line;
arch/alpha/kernel/termios.c
19
canon = v.c_lflag & ICANON;
arch/alpha/kernel/termios.c
20
termios->c_cc[VINTR] = v.c_cc[_VINTR];
arch/alpha/kernel/termios.c
21
termios->c_cc[VQUIT] = v.c_cc[_VQUIT];
arch/alpha/kernel/termios.c
22
termios->c_cc[VERASE] = v.c_cc[_VERASE];
arch/alpha/kernel/termios.c
23
termios->c_cc[VKILL] = v.c_cc[_VKILL];
arch/alpha/kernel/termios.c
24
termios->c_cc[VEOL2] = v.c_cc[_VEOL2];
arch/alpha/kernel/termios.c
25
termios->c_cc[VSWTC] = v.c_cc[_VSWTC];
arch/alpha/kernel/termios.c
26
termios->c_cc[canon ? VEOF : VMIN] = v.c_cc[_VEOF];
arch/alpha/kernel/termios.c
27
termios->c_cc[canon ? VEOL : VTIME] = v.c_cc[_VEOL];
arch/alpha/kernel/termios.c
35
struct termio v;
arch/alpha/kernel/termios.c
38
memset(&v, 0, sizeof(struct termio));
arch/alpha/kernel/termios.c
39
v.c_iflag = termios->c_iflag;
arch/alpha/kernel/termios.c
40
v.c_oflag = termios->c_oflag;
arch/alpha/kernel/termios.c
41
v.c_cflag = termios->c_cflag;
arch/alpha/kernel/termios.c
42
v.c_lflag = termios->c_lflag;
arch/alpha/kernel/termios.c
43
v.c_line = termios->c_line;
arch/alpha/kernel/termios.c
45
canon = v.c_lflag & ICANON;
arch/alpha/kernel/termios.c
46
v.c_cc[_VINTR] = termios->c_cc[VINTR];
arch/alpha/kernel/termios.c
47
v.c_cc[_VQUIT] = termios->c_cc[VQUIT];
arch/alpha/kernel/termios.c
48
v.c_cc[_VERASE] = termios->c_cc[VERASE];
arch/alpha/kernel/termios.c
49
v.c_cc[_VKILL] = termios->c_cc[VKILL];
arch/alpha/kernel/termios.c
50
v.c_cc[_VEOF] = termios->c_cc[canon ? VEOF : VMIN];
arch/alpha/kernel/termios.c
51
v.c_cc[_VEOL] = termios->c_cc[canon ? VEOL : VTIME];
arch/alpha/kernel/termios.c
52
v.c_cc[_VEOL2] = termios->c_cc[VEOL2];
arch/alpha/kernel/termios.c
53
v.c_cc[_VSWTC] = termios->c_cc[VSWTC];
arch/alpha/kernel/termios.c
55
return copy_to_user(termio, &v, sizeof(struct termio));
arch/alpha/kernel/termios.c
7
struct termio v;
arch/alpha/math-emu/sfp-util.h
14
#define umul_ppmm(wh, wl, u, v) \
arch/alpha/math-emu/sfp-util.h
19
"r" ((UDItype)(v)))
arch/arc/include/asm/atomic-llsc.h
19
: [ctr] "r" (&v->counter), /* Not "m": llock only supports reg direct addr mode */ \
arch/arc/include/asm/atomic-llsc.h
25
static inline int arch_atomic_##op##_return_relaxed(int i, atomic_t *v) \
arch/arc/include/asm/atomic-llsc.h
35
: [ctr] "r" (&v->counter), \
arch/arc/include/asm/atomic-llsc.h
46
static inline int arch_atomic_fetch_##op##_relaxed(int i, atomic_t *v) \
arch/arc/include/asm/atomic-llsc.h
57
: [ctr] "r" (&v->counter), \
arch/arc/include/asm/atomic-llsc.h
6
#define arch_atomic_set(v, i) WRITE_ONCE(((v)->counter), (i))
arch/arc/include/asm/atomic-llsc.h
9
static inline void arch_atomic_##op(int i, atomic_t *v) \
arch/arc/include/asm/atomic-spinlock.h
11
static inline void arch_atomic_set(atomic_t *v, int i)
arch/arc/include/asm/atomic-spinlock.h
25
WRITE_ONCE(v->counter, i);
arch/arc/include/asm/atomic-spinlock.h
29
#define arch_atomic_set_release(v, i) arch_atomic_set((v), (i))
arch/arc/include/asm/atomic-spinlock.h
32
static inline void arch_atomic_##op(int i, atomic_t *v) \
arch/arc/include/asm/atomic-spinlock.h
37
v->counter c_op i; \
arch/arc/include/asm/atomic-spinlock.h
42
static inline int arch_atomic_##op##_return(int i, atomic_t *v) \
arch/arc/include/asm/atomic-spinlock.h
51
temp = v->counter; \
arch/arc/include/asm/atomic-spinlock.h
53
v->counter = temp; \
arch/arc/include/asm/atomic-spinlock.h
60
static inline int arch_atomic_fetch_##op(int i, atomic_t *v) \
arch/arc/include/asm/atomic-spinlock.h
69
orig = v->counter; \
arch/arc/include/asm/atomic-spinlock.h
70
v->counter c_op i; \
arch/arc/include/asm/atomic.h
17
#define arch_atomic_read(v) READ_ONCE((v)->counter)
arch/arc/include/asm/atomic64-arcv2.h
101
: "r"(&v->counter), "ir"(a) \
arch/arc/include/asm/atomic64-arcv2.h
17
static inline s64 arch_atomic64_read(const atomic64_t *v)
arch/arc/include/asm/atomic64-arcv2.h
180
static inline s64 arch_atomic64_dec_if_positive(atomic64_t *v)
arch/arc/include/asm/atomic64-arcv2.h
195
: "r"(&v->counter)
arch/arc/include/asm/atomic64-arcv2.h
204
static inline s64 arch_atomic64_fetch_add_unless(atomic64_t *v, s64 a, s64 u)
arch/arc/include/asm/atomic64-arcv2.h
221
: "r"(&v->counter), "r"(a), "r"(u)
arch/arc/include/asm/atomic64-arcv2.h
24
: "r"(&v->counter));
arch/arc/include/asm/atomic64-arcv2.h
29
static inline void arch_atomic64_set(atomic64_t *v, s64 a)
arch/arc/include/asm/atomic64-arcv2.h
45
: "r"(a), "r"(&v->counter)
arch/arc/include/asm/atomic64-arcv2.h
50
static inline void arch_atomic64_##op(s64 a, atomic64_t *v) \
arch/arc/include/asm/atomic64-arcv2.h
62
: "r"(&v->counter), "ir"(a) \
arch/arc/include/asm/atomic64-arcv2.h
67
static inline s64 arch_atomic64_##op##_return_relaxed(s64 a, atomic64_t *v) \
arch/arc/include/asm/atomic64-arcv2.h
79
: "r"(&v->counter), "ir"(a) \
arch/arc/include/asm/atomic64-arcv2.h
89
static inline s64 arch_atomic64_fetch_##op##_relaxed(s64 a, atomic64_t *v) \
arch/arc/include/asm/io.h
203
#define writeb(v,c) ({ __iowmb(); writeb_relaxed(v,c); })
arch/arc/include/asm/io.h
204
#define writew(v,c) ({ __iowmb(); writew_relaxed(v,c); })
arch/arc/include/asm/io.h
205
#define writel(v,c) ({ __iowmb(); writel_relaxed(v,c); })
arch/arc/include/asm/io.h
225
#define writeb_relaxed(v,c) __raw_writeb(v,c)
arch/arc/include/asm/io.h
226
#define writew_relaxed(v,c) __raw_writew((__force u16) cpu_to_le16(v),c)
arch/arc/include/asm/io.h
227
#define writel_relaxed(v,c) __raw_writel((__force u32) cpu_to_le32(v),c)
arch/arc/include/asm/io.h
42
#define iowrite16be(v,p) ({ __iowmb(); __raw_writew((__force u16)cpu_to_be16(v), p); })
arch/arc/include/asm/io.h
43
#define iowrite32be(v,p) ({ __iowmb(); __raw_writel((__force u32)cpu_to_be32(v), p); })
arch/arc/include/asm/perf_event.h
41
unsigned int m:8, c:8, r:5, i:1, s:2, v:8;
arch/arc/include/asm/perf_event.h
43
unsigned int v:8, s:2, i:1, r:5, c:8, m:8;
arch/arc/include/asm/perf_event.h
49
unsigned int c:16, r:8, v:8;
arch/arc/include/asm/perf_event.h
51
unsigned int v:8, r:8, c:16;
arch/arc/include/asm/setup.h
30
#define IS_AVAIL1(v, s) ((v) ? s : "")
arch/arc/include/asm/setup.h
31
#define IS_DISABLED_RUN(v) ((v) ? "" : "(disabled) ")
arch/arc/include/asm/setup.h
32
#define IS_USED_RUN(v) ((v) ? "" : "(not used) ")
arch/arc/include/asm/setup.h
34
#define IS_AVAIL2(v, s, cfg) IS_AVAIL1(v, s), IS_AVAIL1(v, IS_USED_CFG(cfg))
arch/arc/include/asm/setup.h
35
#define IS_AVAIL3(v, v2, s) IS_AVAIL1(v, s), IS_AVAIL1(v, IS_DISABLED_RUN(v2))
arch/arc/kernel/perf_event.c
738
if (!pct_bcr.v) {
arch/arc/kernel/perf_event.c
747
if (WARN(!cc_bcr.v, "Counters exist but No countable conditions?"))
arch/arc/kernel/setup.c
570
static int show_cpuinfo(struct seq_file *m, void *v)
arch/arc/kernel/setup.c
573
int cpu_id = ptr_to_cpu(v);
arch/arc/kernel/setup.c
625
static void *c_next(struct seq_file *m, void *v, loff_t *pos)
arch/arc/kernel/setup.c
631
static void c_stop(struct seq_file *m, void *v)
arch/arc/kernel/smp.c
122
#define __boot_write(f, v) f = v
arch/arc/kernel/smp.c
127
#define __boot_write(f, v) arc_write_uncached_32(&f, v)
arch/arc/kernel/unaligned.c
122
: "=r" (err), "=&r" (v), "=&r" (a) \
arch/arc/kernel/unaligned.c
123
: "0" (err), "1" (v), "2" (a)); \
arch/arc/kernel/unaligned.c
45
unsigned int err = 0, v, a = addr; \
arch/arc/kernel/unaligned.c
46
__get8_unaligned_check(v, a, err); \
arch/arc/kernel/unaligned.c
47
val = v << ((BE) ? 8 : 0); \
arch/arc/kernel/unaligned.c
48
__get8_unaligned_check(v, a, err); \
arch/arc/kernel/unaligned.c
49
val |= v << ((BE) ? 0 : 8); \
arch/arc/kernel/unaligned.c
56
unsigned int err = 0, v, a = addr; \
arch/arc/kernel/unaligned.c
57
__get8_unaligned_check(v, a, err); \
arch/arc/kernel/unaligned.c
58
val = v << ((BE) ? 24 : 0); \
arch/arc/kernel/unaligned.c
59
__get8_unaligned_check(v, a, err); \
arch/arc/kernel/unaligned.c
60
val |= v << ((BE) ? 16 : 8); \
arch/arc/kernel/unaligned.c
61
__get8_unaligned_check(v, a, err); \
arch/arc/kernel/unaligned.c
62
val |= v << ((BE) ? 8 : 16); \
arch/arc/kernel/unaligned.c
63
__get8_unaligned_check(v, a, err); \
arch/arc/kernel/unaligned.c
64
val |= v << ((BE) ? 0 : 24); \
arch/arc/kernel/unaligned.c
71
unsigned int err = 0, v = val, a = addr;\
arch/arc/kernel/unaligned.c
89
: "=r" (err), "=&r" (v), "=&r" (a) \
arch/arc/kernel/unaligned.c
90
: "0" (err), "1" (v), "2" (a)); \
arch/arc/kernel/unaligned.c
98
unsigned int err = 0, v = val, a = addr;\
arch/arc/mm/cache.c
509
#define __ic_line_inv_vaddr(p, v, s) __ic_line_inv_vaddr_local(p, v, s)
arch/arm/boot/compressed/misc-ep93xx.h
34
unsigned int v;
arch/arm/boot/compressed/misc-ep93xx.h
37
v = __raw_readl(PHYS_ETH_SELF_CTL);
arch/arm/boot/compressed/misc-ep93xx.h
38
__raw_writel(v | ETH_SELF_CTL_RESET, PHYS_ETH_SELF_CTL);
arch/arm/include/asm/arch_gicv3.h
165
#define gic_write_irouter(v, c) __gic_writeq_nonatomic(v, c)
arch/arm/include/asm/arch_gicv3.h
176
#define gits_write_baser(v, c) __gic_writeq_nonatomic(v, c)
arch/arm/include/asm/arch_gicv3.h
183
#define gicr_write_propbaser(v, c) __gic_writeq_nonatomic(v, c)
arch/arm/include/asm/arch_gicv3.h
185
#define gicr_write_pendbaser(v, c) __gic_writeq_nonatomic(v, c)
arch/arm/include/asm/arch_gicv3.h
191
#define gic_write_lpir(v, c) writel_relaxed(lower_32_bits(v), c)
arch/arm/include/asm/arch_gicv3.h
202
#define gits_write_cbaser(v, c) __gic_writeq_nonatomic(v, c)
arch/arm/include/asm/arch_gicv3.h
207
#define gits_write_cwriter(v, c) __gic_writeq_nonatomic(v, c)
arch/arm/include/asm/arch_gicv3.h
213
#define gicr_write_vpropbaser(v, c) __gic_writeq_nonatomic(v, c)
arch/arm/include/asm/arch_gicv3.h
63
#define write_gicreg(v, r) write_##r(v)
arch/arm/include/asm/atomic.h
128
static inline int arch_atomic_fetch_add_unless(atomic_t *v, int a, int u)
arch/arm/include/asm/atomic.h
134
prefetchw(&v->counter);
arch/arm/include/asm/atomic.h
145
: "=&r" (oldval), "=&r" (newval), "=&r" (tmp), "+Qo" (v->counter)
arch/arm/include/asm/atomic.h
146
: "r" (&v->counter), "r" (u), "r" (a)
arch/arm/include/asm/atomic.h
163
static inline void arch_atomic_##op(int i, atomic_t *v) \
arch/arm/include/asm/atomic.h
168
v->counter c_op i; \
arch/arm/include/asm/atomic.h
173
static inline int arch_atomic_##op##_return(int i, atomic_t *v) \
arch/arm/include/asm/atomic.h
179
v->counter c_op i; \
arch/arm/include/asm/atomic.h
180
val = v->counter; \
arch/arm/include/asm/atomic.h
187
static inline int arch_atomic_fetch_##op(int i, atomic_t *v) \
arch/arm/include/asm/atomic.h
193
val = v->counter; \
arch/arm/include/asm/atomic.h
194
v->counter c_op i; \
arch/arm/include/asm/atomic.h
210
static inline int arch_atomic_cmpxchg(atomic_t *v, int old, int new)
arch/arm/include/asm/atomic.h
216
ret = v->counter;
arch/arm/include/asm/atomic.h
218
v->counter = new;
arch/arm/include/asm/atomic.h
25
#define arch_atomic_read(v) READ_ONCE((v)->counter)
arch/arm/include/asm/atomic.h
26
#define arch_atomic_set(v,i) WRITE_ONCE(((v)->counter), (i))
arch/arm/include/asm/atomic.h
260
static inline s64 arch_atomic64_read(const atomic64_t *v)
arch/arm/include/asm/atomic.h
267
: "r" (&v->counter), "Qo" (v->counter)
arch/arm/include/asm/atomic.h
273
static inline void arch_atomic64_set(atomic64_t *v, s64 i)
arch/arm/include/asm/atomic.h
277
: "=Qo" (v->counter)
arch/arm/include/asm/atomic.h
278
: "r" (&v->counter), "r" (i)
arch/arm/include/asm/atomic.h
282
static inline s64 arch_atomic64_read(const atomic64_t *v)
arch/arm/include/asm/atomic.h
289
: "r" (&v->counter), "Qo" (v->counter)
arch/arm/include/asm/atomic.h
295
static inline void arch_atomic64_set(atomic64_t *v, s64 i)
arch/arm/include/asm/atomic.h
299
prefetchw(&v->counter);
arch/arm/include/asm/atomic.h
305
: "=&r" (tmp), "=Qo" (v->counter)
arch/arm/include/asm/atomic.h
306
: "r" (&v->counter), "r" (i)
arch/arm/include/asm/atomic.h
312
static inline void arch_atomic64_##op(s64 i, atomic64_t *v) \
arch/arm/include/asm/atomic.h
317
prefetchw(&v->counter); \
arch/arm/include/asm/atomic.h
325
: "=&r" (result), "=&r" (tmp), "+Qo" (v->counter) \
arch/arm/include/asm/atomic.h
326
: "r" (&v->counter), "r" (i) \
arch/arm/include/asm/atomic.h
332
arch_atomic64_##op##_return_relaxed(s64 i, atomic64_t *v) \
arch/arm/include/asm/atomic.h
337
prefetchw(&v->counter); \
arch/arm/include/asm/atomic.h
346
: "=&r" (result), "=&r" (tmp), "+Qo" (v->counter) \
arch/arm/include/asm/atomic.h
347
: "r" (&v->counter), "r" (i) \
arch/arm/include/asm/atomic.h
355
arch_atomic64_fetch_##op##_relaxed(s64 i, atomic64_t *v) \
arch/arm/include/asm/atomic.h
360
prefetchw(&v->counter); \
arch/arm/include/asm/atomic.h
369
: "=&r" (result), "=&r" (val), "=&r" (tmp), "+Qo" (v->counter) \
arch/arm/include/asm/atomic.h
37
static inline void arch_atomic_##op(int i, atomic_t *v) \
arch/arm/include/asm/atomic.h
370
: "r" (&v->counter), "r" (i) \
arch/arm/include/asm/atomic.h
42
prefetchw(&v->counter); \
arch/arm/include/asm/atomic.h
454
static inline s64 arch_atomic64_dec_if_positive(atomic64_t *v)
arch/arm/include/asm/atomic.h
460
prefetchw(&v->counter);
arch/arm/include/asm/atomic.h
472
: "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
arch/arm/include/asm/atomic.h
473
: "r" (&v->counter)
arch/arm/include/asm/atomic.h
482
static inline s64 arch_atomic64_fetch_add_unless(atomic64_t *v, s64 a, s64 u)
arch/arm/include/asm/atomic.h
488
prefetchw(&v->counter);
arch/arm/include/asm/atomic.h
49
: "=&r" (result), "=&r" (tmp), "+Qo" (v->counter) \
arch/arm/include/asm/atomic.h
50
: "r" (&v->counter), "Ir" (i) \
arch/arm/include/asm/atomic.h
501
: "=&r" (oldval), "=&r" (newval), "=&r" (tmp), "+Qo" (v->counter)
arch/arm/include/asm/atomic.h
502
: "r" (&v->counter), "r" (u), "r" (a)
arch/arm/include/asm/atomic.h
55
static inline int arch_atomic_##op##_return_relaxed(int i, atomic_t *v) \
arch/arm/include/asm/atomic.h
60
prefetchw(&v->counter); \
arch/arm/include/asm/atomic.h
68
: "=&r" (result), "=&r" (tmp), "+Qo" (v->counter) \
arch/arm/include/asm/atomic.h
69
: "r" (&v->counter), "Ir" (i) \
arch/arm/include/asm/atomic.h
76
static inline int arch_atomic_fetch_##op##_relaxed(int i, atomic_t *v) \
arch/arm/include/asm/atomic.h
81
prefetchw(&v->counter); \
arch/arm/include/asm/atomic.h
89
: "=&r" (result), "=&r" (val), "=&r" (tmp), "+Qo" (v->counter) \
arch/arm/include/asm/atomic.h
90
: "r" (&v->counter), "Ir" (i) \
arch/arm/include/asm/io.h
235
#define outb(v,p) ({ __iowmb(); __raw_writeb(v,__io(p)); })
arch/arm/include/asm/io.h
236
#define outw(v,p) ({ __iowmb(); __raw_writew((__force __u16) \
arch/arm/include/asm/io.h
237
cpu_to_le16(v),__io(p)); })
arch/arm/include/asm/io.h
238
#define outl(v,p) ({ __iowmb(); __raw_writel((__force __u32) \
arch/arm/include/asm/io.h
239
cpu_to_le32(v),__io(p)); })
arch/arm/include/asm/io.h
280
#define writeb_relaxed(v,c) __raw_writeb(v,c)
arch/arm/include/asm/io.h
281
#define writew_relaxed(v,c) __raw_writew((__force u16) cpu_to_le16(v),c)
arch/arm/include/asm/io.h
282
#define writel_relaxed(v,c) __raw_writel((__force u32) cpu_to_le32(v),c)
arch/arm/include/asm/io.h
288
#define writeb(v,c) ({ __iowmb(); writeb_relaxed(v,c); })
arch/arm/include/asm/io.h
289
#define writew(v,c) ({ __iowmb(); writew_relaxed(v,c); })
arch/arm/include/asm/io.h
290
#define writel(v,c) ({ __iowmb(); writel_relaxed(v,c); })
arch/arm/include/asm/io.h
326
#define memset_io(c,v,l) _memset_io(c,(v),(l))
arch/arm/include/asm/io.h
393
#define iowrite16be(v,p) ({ __iowmb(); __raw_writew((__force __u16)cpu_to_be16(v), p); })
arch/arm/include/asm/io.h
394
#define iowrite32be(v,p) ({ __iowmb(); __raw_writel((__force __u32)cpu_to_be32(v), p); })
arch/arm/include/asm/io.h
60
#define __raw_writew(v,a) ((void)(__chk_io_ptr(a), *(volatile unsigned short __force *)(a) = (v)))
arch/arm/include/asm/string.h
35
extern void *__memset32(uint32_t *, uint32_t v, __kernel_size_t);
arch/arm/include/asm/string.h
36
static inline void *memset32(uint32_t *p, uint32_t v, __kernel_size_t n)
arch/arm/include/asm/string.h
38
return __memset32(p, v, n * 4);
arch/arm/include/asm/string.h
43
static inline void *memset64(uint64_t *p, uint64_t v, __kernel_size_t n)
arch/arm/include/asm/string.h
50
} word = { .val = v };
arch/arm/include/asm/vdso/cp15.h
26
#define __write_sysreg(v, r, w, c, t) asm volatile(w " " c : : "r" ((t)(v)))
arch/arm/include/asm/vdso/cp15.h
27
#define write_sysreg(v, ...) __write_sysreg(v, __VA_ARGS__)
arch/arm/kernel/dma.c
264
static int proc_dma_show(struct seq_file *m, void *v)
arch/arm/kernel/hw_breakpoint.c
1152
void *v)
arch/arm/kernel/setup.c
1259
static int c_show(struct seq_file *m, void *v)
arch/arm/kernel/setup.c
1330
static void *c_next(struct seq_file *m, void *v, loff_t *pos)
arch/arm/kernel/setup.c
1336
static void c_stop(struct seq_file *m, void *v)
arch/arm/kernel/swp_emulate.c
83
static int proc_status_show(struct seq_file *m, void *v)
arch/arm/kernel/thumbee.c
20
unsigned long v;
arch/arm/kernel/thumbee.c
21
asm("mrc p14, 6, %0, c1, c0, 0\n" : "=r" (v));
arch/arm/kernel/thumbee.c
22
return v;
arch/arm/kernel/thumbee.c
25
static inline void teehbr_write(unsigned long v)
arch/arm/kernel/thumbee.c
27
asm("mcr p14, 6, %0, c1, c0, 0\n" : : "r" (v));
arch/arm/mach-exynos/platsmp.c
35
unsigned int v;
arch/arm/mach-exynos/platsmp.c
44
: "=&r" (v)
arch/arm/mach-footbridge/dc21285.c
119
v = *CSR_PCICMD;
arch/arm/mach-footbridge/dc21285.c
120
if (v & PCICMD_ABORT) {
arch/arm/mach-footbridge/dc21285.c
121
*CSR_PCICMD = v & (0xffff|PCICMD_ABORT);
arch/arm/mach-footbridge/dc21285.c
64
u32 v = 0xffffffff;
arch/arm/mach-footbridge/dc21285.c
70
: "=r" (v) : "r" (addr), "r" (where) : "cc");
arch/arm/mach-footbridge/dc21285.c
74
: "=r" (v) : "r" (addr), "r" (where) : "cc");
arch/arm/mach-footbridge/dc21285.c
78
: "=r" (v) : "r" (addr), "r" (where) : "cc");
arch/arm/mach-footbridge/dc21285.c
82
*value = v;
arch/arm/mach-footbridge/dc21285.c
84
v = *CSR_PCICMD;
arch/arm/mach-footbridge/dc21285.c
85
if (v & PCICMD_ABORT) {
arch/arm/mach-footbridge/dc21285.c
86
*CSR_PCICMD = v & (0xffff|PCICMD_ABORT);
arch/arm/mach-footbridge/dc21285.c
98
u32 v;
arch/arm/mach-footbridge/netwinder-hw.c
405
#define WRITE_RWA(r,v) do { outb((r), 0x279); udelay(10); outb((v), 0xa79); } while (0)
arch/arm/mach-hisi/hotplug.c
252
unsigned int v;
arch/arm/mach-hisi/hotplug.c
266
: "=&r" (v)
arch/arm/mach-lpc32xx/lpc32xx.h
13
#define _SBF(f, v) ((v) << (f))
arch/arm/mach-omap1/io.c
101
__raw_writew(v, OMAP1_IO_ADDRESS(pa));
arch/arm/mach-omap1/io.c
105
void omap_writel(u32 v, u32 pa)
arch/arm/mach-omap1/io.c
107
__raw_writel(v, OMAP1_IO_ADDRESS(pa));
arch/arm/mach-omap1/io.c
93
void omap_writeb(u8 v, u32 pa)
arch/arm/mach-omap1/io.c
95
__raw_writeb(v, OMAP1_IO_ADDRESS(pa));
arch/arm/mach-omap1/io.c
99
void omap_writew(u16 v, u32 pa)
arch/arm/mach-omap1/pm.c
391
static int omap_pm_debug_show(struct seq_file *m, void *v)
arch/arm/mach-omap2/clkt2xxx_dpllcore.c
55
u32 v;
arch/arm/mach-omap2/clkt2xxx_dpllcore.c
61
v = omap2xxx_cm_get_core_clk_src();
arch/arm/mach-omap2/clkt2xxx_dpllcore.c
63
if (v == CORE_CLK_SRC_32K)
arch/arm/mach-omap2/clkt2xxx_dpllcore.c
66
core_clk *= v;
arch/arm/mach-omap2/clockdomain.c
453
static int cpu_notifier(struct notifier_block *nb, unsigned long cmd, void *v)
arch/arm/mach-omap2/cm2xxx.c
257
u32 v;
arch/arm/mach-omap2/cm2xxx.c
259
v = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
arch/arm/mach-omap2/cm2xxx.c
260
v &= OMAP24XX_CORE_CLK_SRC_MASK;
arch/arm/mach-omap2/cm2xxx.c
262
return v;
arch/arm/mach-omap2/cm2xxx.c
45
u32 v;
arch/arm/mach-omap2/cm2xxx.c
47
v = omap2_cm_read_mod_reg(module, OMAP2_CM_CLKSTCTRL);
arch/arm/mach-omap2/cm2xxx.c
48
v &= ~mask;
arch/arm/mach-omap2/cm2xxx.c
49
v |= c << __ffs(mask);
arch/arm/mach-omap2/cm2xxx.c
50
omap2_cm_write_mod_reg(v, module, OMAP2_CM_CLKSTCTRL);
arch/arm/mach-omap2/cm2xxx.c
55
u32 v;
arch/arm/mach-omap2/cm2xxx.c
57
v = omap2_cm_read_mod_reg(module, OMAP2_CM_CLKSTCTRL);
arch/arm/mach-omap2/cm2xxx.c
58
v &= mask;
arch/arm/mach-omap2/cm2xxx.c
59
v >>= __ffs(mask);
arch/arm/mach-omap2/cm2xxx.c
61
return (v == OMAP24XX_CLKSTCTRL_ENABLE_AUTO) ? 1 : 0;
arch/arm/mach-omap2/cm2xxx.c
80
u32 v;
arch/arm/mach-omap2/cm2xxx.c
82
v = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
arch/arm/mach-omap2/cm2xxx.c
83
v &= ~OMAP24XX_AUTO_DPLL_MASK;
arch/arm/mach-omap2/cm2xxx.c
84
v |= m << OMAP24XX_AUTO_DPLL_SHIFT;
arch/arm/mach-omap2/cm2xxx.c
85
omap2_cm_write_mod_reg(v, PLL_MOD, CM_AUTOIDLE);
arch/arm/mach-omap2/cm2xxx_3xxx.h
64
u32 v;
arch/arm/mach-omap2/cm2xxx_3xxx.h
66
v = omap2_cm_read_mod_reg(module, idx);
arch/arm/mach-omap2/cm2xxx_3xxx.h
67
v &= ~mask;
arch/arm/mach-omap2/cm2xxx_3xxx.h
68
v |= bits;
arch/arm/mach-omap2/cm2xxx_3xxx.h
69
omap2_cm_write_mod_reg(v, module, idx);
arch/arm/mach-omap2/cm2xxx_3xxx.h
71
return v;
arch/arm/mach-omap2/cm2xxx_3xxx.h
77
u32 v;
arch/arm/mach-omap2/cm2xxx_3xxx.h
79
v = omap2_cm_read_mod_reg(domain, idx);
arch/arm/mach-omap2/cm2xxx_3xxx.h
80
v &= mask;
arch/arm/mach-omap2/cm2xxx_3xxx.h
81
v >>= __ffs(mask);
arch/arm/mach-omap2/cm2xxx_3xxx.h
83
return v;
arch/arm/mach-omap2/cm33xx.c
107
u32 v;
arch/arm/mach-omap2/cm33xx.c
109
v = _clkctrl_idlest(inst, clkctrl_offs);
arch/arm/mach-omap2/cm33xx.c
111
return (v == CLKCTRL_IDLEST_FUNCTIONAL ||
arch/arm/mach-omap2/cm33xx.c
112
v == CLKCTRL_IDLEST_INTERFACE_IDLE) ? true : false;
arch/arm/mach-omap2/cm33xx.c
126
u32 v;
arch/arm/mach-omap2/cm33xx.c
128
v = am33xx_cm_read_reg(inst, cdoffs);
arch/arm/mach-omap2/cm33xx.c
129
v &= ~AM33XX_CLKTRCTRL_MASK;
arch/arm/mach-omap2/cm33xx.c
130
v |= c << AM33XX_CLKTRCTRL_SHIFT;
arch/arm/mach-omap2/cm33xx.c
131
am33xx_cm_write_reg(v, inst, cdoffs);
arch/arm/mach-omap2/cm33xx.c
146
u32 v;
arch/arm/mach-omap2/cm33xx.c
148
v = am33xx_cm_read_reg(inst, cdoffs);
arch/arm/mach-omap2/cm33xx.c
149
v &= AM33XX_CLKTRCTRL_MASK;
arch/arm/mach-omap2/cm33xx.c
150
v >>= AM33XX_CLKTRCTRL_SHIFT;
arch/arm/mach-omap2/cm33xx.c
152
return (v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ? true : false;
arch/arm/mach-omap2/cm33xx.c
271
u32 v;
arch/arm/mach-omap2/cm33xx.c
273
v = am33xx_cm_read_reg(inst, clkctrl_offs);
arch/arm/mach-omap2/cm33xx.c
274
v &= ~AM33XX_MODULEMODE_MASK;
arch/arm/mach-omap2/cm33xx.c
275
v |= mode << AM33XX_MODULEMODE_SHIFT;
arch/arm/mach-omap2/cm33xx.c
276
am33xx_cm_write_reg(v, inst, clkctrl_offs);
arch/arm/mach-omap2/cm33xx.c
289
u32 v;
arch/arm/mach-omap2/cm33xx.c
291
v = am33xx_cm_read_reg(inst, clkctrl_offs);
arch/arm/mach-omap2/cm33xx.c
292
v &= ~AM33XX_MODULEMODE_MASK;
arch/arm/mach-omap2/cm33xx.c
293
am33xx_cm_write_reg(v, inst, clkctrl_offs);
arch/arm/mach-omap2/cm33xx.c
60
u32 v;
arch/arm/mach-omap2/cm33xx.c
62
v = am33xx_cm_read_reg(inst, idx);
arch/arm/mach-omap2/cm33xx.c
63
v &= ~mask;
arch/arm/mach-omap2/cm33xx.c
64
v |= bits;
arch/arm/mach-omap2/cm33xx.c
65
am33xx_cm_write_reg(v, inst, idx);
arch/arm/mach-omap2/cm33xx.c
67
return v;
arch/arm/mach-omap2/cm33xx.c
72
u32 v;
arch/arm/mach-omap2/cm33xx.c
74
v = am33xx_cm_read_reg(inst, idx);
arch/arm/mach-omap2/cm33xx.c
75
v &= mask;
arch/arm/mach-omap2/cm33xx.c
76
v >>= __ffs(mask);
arch/arm/mach-omap2/cm33xx.c
78
return v;
arch/arm/mach-omap2/cm33xx.c
91
u32 v = am33xx_cm_read_reg(inst, clkctrl_offs);
arch/arm/mach-omap2/cm33xx.c
92
v &= AM33XX_IDLEST_MASK;
arch/arm/mach-omap2/cm33xx.c
93
v >>= AM33XX_IDLEST_SHIFT;
arch/arm/mach-omap2/cm33xx.c
94
return v;
arch/arm/mach-omap2/cm3xxx.c
34
u32 v;
arch/arm/mach-omap2/cm3xxx.c
36
v = omap2_cm_read_mod_reg(module, OMAP2_CM_CLKSTCTRL);
arch/arm/mach-omap2/cm3xxx.c
37
v &= ~mask;
arch/arm/mach-omap2/cm3xxx.c
38
v |= c << __ffs(mask);
arch/arm/mach-omap2/cm3xxx.c
39
omap2_cm_write_mod_reg(v, module, OMAP2_CM_CLKSTCTRL);
arch/arm/mach-omap2/cm3xxx.c
44
u32 v;
arch/arm/mach-omap2/cm3xxx.c
46
v = omap2_cm_read_mod_reg(module, OMAP2_CM_CLKSTCTRL);
arch/arm/mach-omap2/cm3xxx.c
47
v &= mask;
arch/arm/mach-omap2/cm3xxx.c
48
v >>= __ffs(mask);
arch/arm/mach-omap2/cm3xxx.c
50
return (v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ? 1 : 0;
arch/arm/mach-omap2/cminst44xx.c
104
u32 v;
arch/arm/mach-omap2/cminst44xx.c
106
v = _clkctrl_idlest(part, inst, clkctrl_offs);
arch/arm/mach-omap2/cminst44xx.c
108
return (v == CLKCTRL_IDLEST_FUNCTIONAL ||
arch/arm/mach-omap2/cminst44xx.c
109
v == CLKCTRL_IDLEST_INTERFACE_IDLE) ? true : false;
arch/arm/mach-omap2/cminst44xx.c
134
u32 v;
arch/arm/mach-omap2/cminst44xx.c
136
v = omap4_cminst_read_inst_reg(part, inst, idx);
arch/arm/mach-omap2/cminst44xx.c
137
v &= ~mask;
arch/arm/mach-omap2/cminst44xx.c
138
v |= bits;
arch/arm/mach-omap2/cminst44xx.c
139
omap4_cminst_write_inst_reg(v, part, inst, idx);
arch/arm/mach-omap2/cminst44xx.c
141
return v;
arch/arm/mach-omap2/cminst44xx.c
157
u32 v;
arch/arm/mach-omap2/cminst44xx.c
159
v = omap4_cminst_read_inst_reg(part, inst, idx);
arch/arm/mach-omap2/cminst44xx.c
160
v &= mask;
arch/arm/mach-omap2/cminst44xx.c
161
v >>= __ffs(mask);
arch/arm/mach-omap2/cminst44xx.c
163
return v;
arch/arm/mach-omap2/cminst44xx.c
182
u32 v;
arch/arm/mach-omap2/cminst44xx.c
184
v = omap4_cminst_read_inst_reg(part, inst, cdoffs + OMAP4_CM_CLKSTCTRL);
arch/arm/mach-omap2/cminst44xx.c
185
v &= ~OMAP4430_CLKTRCTRL_MASK;
arch/arm/mach-omap2/cminst44xx.c
186
v |= c << OMAP4430_CLKTRCTRL_SHIFT;
arch/arm/mach-omap2/cminst44xx.c
187
omap4_cminst_write_inst_reg(v, part, inst, cdoffs + OMAP4_CM_CLKSTCTRL);
arch/arm/mach-omap2/cminst44xx.c
201
u32 v;
arch/arm/mach-omap2/cminst44xx.c
203
v = omap4_cminst_read_inst_reg(part, inst, cdoffs + OMAP4_CM_CLKSTCTRL);
arch/arm/mach-omap2/cminst44xx.c
204
v &= OMAP4430_CLKTRCTRL_MASK;
arch/arm/mach-omap2/cminst44xx.c
205
v >>= OMAP4430_CLKTRCTRL_SHIFT;
arch/arm/mach-omap2/cminst44xx.c
207
return (v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ? true : false;
arch/arm/mach-omap2/cminst44xx.c
321
u32 v;
arch/arm/mach-omap2/cminst44xx.c
323
v = omap4_cminst_read_inst_reg(part, inst, clkctrl_offs);
arch/arm/mach-omap2/cminst44xx.c
324
v &= ~OMAP4430_MODULEMODE_MASK;
arch/arm/mach-omap2/cminst44xx.c
325
v |= mode << OMAP4430_MODULEMODE_SHIFT;
arch/arm/mach-omap2/cminst44xx.c
326
omap4_cminst_write_inst_reg(v, part, inst, clkctrl_offs);
arch/arm/mach-omap2/cminst44xx.c
339
u32 v;
arch/arm/mach-omap2/cminst44xx.c
341
v = omap4_cminst_read_inst_reg(part, inst, clkctrl_offs);
arch/arm/mach-omap2/cminst44xx.c
342
v &= ~OMAP4430_MODULEMODE_MASK;
arch/arm/mach-omap2/cminst44xx.c
343
omap4_cminst_write_inst_reg(v, part, inst, clkctrl_offs);
arch/arm/mach-omap2/cminst44xx.c
87
u32 v = omap4_cminst_read_inst_reg(part, inst, clkctrl_offs);
arch/arm/mach-omap2/cminst44xx.c
88
v &= OMAP4430_IDLEST_MASK;
arch/arm/mach-omap2/cminst44xx.c
89
v >>= OMAP4430_IDLEST_SHIFT;
arch/arm/mach-omap2/cminst44xx.c
90
return v;
arch/arm/mach-omap2/control.c
644
static int cpu_notifier(struct notifier_block *nb, unsigned long cmd, void *v)
arch/arm/mach-omap2/display.c
274
u32 v, irq_mask = 0;
arch/arm/mach-omap2/display.c
294
v = omap_hwmod_read(oh, DISPC_CONTROL);
arch/arm/mach-omap2/display.c
295
lcd_en = v & LCD_EN_MASK;
arch/arm/mach-omap2/display.c
296
digit_en = v & DIGIT_EN_MASK;
arch/arm/mach-omap2/display.c
300
v = omap_hwmod_read(oh, DISPC_CONTROL2);
arch/arm/mach-omap2/display.c
301
lcd2_en = v & LCD_EN_MASK;
arch/arm/mach-omap2/display.c
306
v = omap_hwmod_read(oh, DISPC_CONTROL3);
arch/arm/mach-omap2/display.c
307
lcd3_en = v & LCD_EN_MASK;
arch/arm/mach-omap2/display.c
341
v = omap_hwmod_read(oh, DISPC_CONTROL);
arch/arm/mach-omap2/display.c
342
v &= ~(LCD_EN_MASK | DIGIT_EN_MASK);
arch/arm/mach-omap2/display.c
343
omap_hwmod_write(v, oh, DISPC_CONTROL);
arch/arm/mach-omap2/display.c
347
v = omap_hwmod_read(oh, DISPC_CONTROL2);
arch/arm/mach-omap2/display.c
348
v &= ~LCD_EN_MASK;
arch/arm/mach-omap2/display.c
349
omap_hwmod_write(v, oh, DISPC_CONTROL2);
arch/arm/mach-omap2/display.c
354
v = omap_hwmod_read(oh, DISPC_CONTROL3);
arch/arm/mach-omap2/display.c
355
v &= ~LCD_EN_MASK;
arch/arm/mach-omap2/display.c
356
omap_hwmod_write(v, oh, DISPC_CONTROL3);
arch/arm/mach-omap2/hdq1w.c
39
u32 v;
arch/arm/mach-omap2/hdq1w.c
46
v = omap_hwmod_read(oh, HDQ_CTRL_STATUS_OFFSET);
arch/arm/mach-omap2/hdq1w.c
47
v |= 1 << HDQ_CTRL_STATUS_CLOCKENABLE_SHIFT;
arch/arm/mach-omap2/hdq1w.c
48
omap_hwmod_write(v, oh, HDQ_CTRL_STATUS_OFFSET);
arch/arm/mach-omap2/i2c.c
38
u32 v;
arch/arm/mach-omap2/i2c.c
48
v = omap_hwmod_read(oh, i2c_con);
arch/arm/mach-omap2/i2c.c
49
v &= ~I2C_EN;
arch/arm/mach-omap2/i2c.c
50
omap_hwmod_write(v, oh, i2c_con);
arch/arm/mach-omap2/i2c.c
56
v = omap_hwmod_read(oh, i2c_con);
arch/arm/mach-omap2/i2c.c
57
v |= I2C_EN;
arch/arm/mach-omap2/i2c.c
58
omap_hwmod_write(v, oh, i2c_con);
arch/arm/mach-omap2/io.c
381
int v = -EINVAL;
arch/arm/mach-omap2/io.c
393
v = clk_set_rate(dpll3_m2_ck, rate);
arch/arm/mach-omap2/io.c
394
if (v)
arch/arm/mach-omap2/io.c
395
pr_err("dpll3_m2_clk rate change failed: %d\n", v);
arch/arm/mach-omap2/io.c
399
return v;
arch/arm/mach-omap2/msdi.c
47
u16 v = 0;
arch/arm/mach-omap2/msdi.c
54
v |= MSDI_CON_POW_MASK;
arch/arm/mach-omap2/msdi.c
55
v |= MSDI_TARGET_RESET_CLKD << MSDI_CON_CLKD_SHIFT;
arch/arm/mach-omap2/msdi.c
56
omap_hwmod_write(v, oh, MSDI_CON_OFFSET);
arch/arm/mach-omap2/msdi.c
71
v &= ~MSDI_CON_CLKD_MASK;
arch/arm/mach-omap2/msdi.c
72
omap_hwmod_write(v, oh, MSDI_CON_OFFSET);
arch/arm/mach-omap2/omap-secure.c
228
static int cpu_notifier(struct notifier_block *nb, unsigned long cmd, void *v)
arch/arm/mach-omap2/omap-wakeupgen.c
433
static int irq_notifier(struct notifier_block *self, unsigned long cmd, void *v)
arch/arm/mach-omap2/omap_hwmod.c
1174
u32 v;
arch/arm/mach-omap2/omap_hwmod.c
1193
v = oh->_sysc_cache;
arch/arm/mach-omap2/omap_hwmod.c
1203
_enable_wakeup(oh, &v);
arch/arm/mach-omap2/omap_hwmod.c
1219
_set_slave_idlemode(oh, idlemode, &v);
arch/arm/mach-omap2/omap_hwmod.c
1229
_enable_wakeup(oh, &v);
arch/arm/mach-omap2/omap_hwmod.c
1235
_set_master_standbymode(oh, idlemode, &v);
arch/arm/mach-omap2/omap_hwmod.c
1245
_set_clockactivity(oh, CLOCKACT_TEST_ICLK, &v);
arch/arm/mach-omap2/omap_hwmod.c
1247
_write_sysconfig(v, oh);
arch/arm/mach-omap2/omap_hwmod.c
1256
_set_module_autoidle(oh, idlemode, &v);
arch/arm/mach-omap2/omap_hwmod.c
1257
_write_sysconfig(v, oh);
arch/arm/mach-omap2/omap_hwmod.c
1273
u32 v;
arch/arm/mach-omap2/omap_hwmod.c
1278
v = oh->_sysc_cache;
arch/arm/mach-omap2/omap_hwmod.c
1286
_enable_wakeup(oh, &v);
arch/arm/mach-omap2/omap_hwmod.c
1292
_set_slave_idlemode(oh, idlemode, &v);
arch/arm/mach-omap2/omap_hwmod.c
1301
_enable_wakeup(oh, &v);
arch/arm/mach-omap2/omap_hwmod.c
1307
_set_master_standbymode(oh, idlemode, &v);
arch/arm/mach-omap2/omap_hwmod.c
1311
if (oh->_sysc_cache != v)
arch/arm/mach-omap2/omap_hwmod.c
1312
_write_sysconfig(v, oh);
arch/arm/mach-omap2/omap_hwmod.c
1324
u32 v;
arch/arm/mach-omap2/omap_hwmod.c
1330
v = oh->_sysc_cache;
arch/arm/mach-omap2/omap_hwmod.c
1334
_set_slave_idlemode(oh, HWMOD_IDLEMODE_FORCE, &v);
arch/arm/mach-omap2/omap_hwmod.c
1337
_set_master_standbymode(oh, HWMOD_IDLEMODE_FORCE, &v);
arch/arm/mach-omap2/omap_hwmod.c
1340
_set_module_autoidle(oh, 1, &v);
arch/arm/mach-omap2/omap_hwmod.c
1342
_write_sysconfig(v, oh);
arch/arm/mach-omap2/omap_hwmod.c
1650
int v;
arch/arm/mach-omap2/omap_hwmod.c
1668
v = _omap4_wait_target_disable(oh);
arch/arm/mach-omap2/omap_hwmod.c
1669
if (v)
arch/arm/mach-omap2/omap_hwmod.c
1694
u32 v;
arch/arm/mach-omap2/omap_hwmod.c
1715
v = oh->_sysc_cache;
arch/arm/mach-omap2/omap_hwmod.c
1716
ret = _set_softreset(oh, &v);
arch/arm/mach-omap2/omap_hwmod.c
1720
_write_sysconfig(v, oh);
arch/arm/mach-omap2/omap_hwmod.c
1735
ret = _clear_softreset(oh, &v);
arch/arm/mach-omap2/omap_hwmod.c
1739
_write_sysconfig(v, oh);
arch/arm/mach-omap2/omap_hwmod.c
2897
void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs)
arch/arm/mach-omap2/omap_hwmod.c
2900
writew_relaxed(v, oh->_mpu_rt_va + reg_offs);
arch/arm/mach-omap2/omap_hwmod.c
2902
writel_relaxed(v, oh->_mpu_rt_va + reg_offs);
arch/arm/mach-omap2/omap_hwmod.c
2916
u32 v;
arch/arm/mach-omap2/omap_hwmod.c
2922
v = oh->_sysc_cache;
arch/arm/mach-omap2/omap_hwmod.c
2923
ret = _set_softreset(oh, &v);
arch/arm/mach-omap2/omap_hwmod.c
2926
_write_sysconfig(v, oh);
arch/arm/mach-omap2/omap_hwmod.c
2928
ret = _clear_softreset(oh, &v);
arch/arm/mach-omap2/omap_hwmod.c
2931
_write_sysconfig(v, oh);
arch/arm/mach-omap2/omap_hwmod.c
295
static void _write_sysconfig(u32 v, struct omap_hwmod *oh)
arch/arm/mach-omap2/omap_hwmod.c
305
oh->_sysc_cache = v;
arch/arm/mach-omap2/omap_hwmod.c
316
omap_hwmod_write(v, oh, oh->class->sysc->sysc_offs);
arch/arm/mach-omap2/omap_hwmod.c
333
u32 *v)
arch/arm/mach-omap2/omap_hwmod.c
350
*v &= ~mstandby_mask;
arch/arm/mach-omap2/omap_hwmod.c
351
*v |= __ffs(standbymode) << mstandby_shift;
arch/arm/mach-omap2/omap_hwmod.c
366
static int _set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode, u32 *v)
arch/arm/mach-omap2/omap_hwmod.c
383
*v &= ~sidle_mask;
arch/arm/mach-omap2/omap_hwmod.c
384
*v |= __ffs(idlemode) << sidle_shift;
arch/arm/mach-omap2/omap_hwmod.c
400
static int _set_clockactivity(struct omap_hwmod *oh, u8 clockact, u32 *v)
arch/arm/mach-omap2/omap_hwmod.c
417
*v &= ~clkact_mask;
arch/arm/mach-omap2/omap_hwmod.c
418
*v |= clockact << clkact_shift;
arch/arm/mach-omap2/omap_hwmod.c
431
static int _set_softreset(struct omap_hwmod *oh, u32 *v)
arch/arm/mach-omap2/omap_hwmod.c
446
*v |= softrst_mask;
arch/arm/mach-omap2/omap_hwmod.c
459
static int _clear_softreset(struct omap_hwmod *oh, u32 *v)
arch/arm/mach-omap2/omap_hwmod.c
476
*v &= ~softrst_mask;
arch/arm/mach-omap2/omap_hwmod.c
527
u32 v;
arch/arm/mach-omap2/omap_hwmod.c
547
v = oh->_sysc_cache;
arch/arm/mach-omap2/omap_hwmod.c
550
v |= dmadisable_mask;
arch/arm/mach-omap2/omap_hwmod.c
551
_write_sysconfig(v, oh);
arch/arm/mach-omap2/omap_hwmod.c
570
u32 *v)
arch/arm/mach-omap2/omap_hwmod.c
587
*v &= ~autoidle_mask;
arch/arm/mach-omap2/omap_hwmod.c
588
*v |= autoidle << autoidle_shift;
arch/arm/mach-omap2/omap_hwmod.c
600
static int _enable_wakeup(struct omap_hwmod *oh, u32 *v)
arch/arm/mach-omap2/omap_hwmod.c
614
*v |= 0x1 << oh->class->sysc->sysc_fields->enwkup_shift;
arch/arm/mach-omap2/omap_hwmod.c
617
_set_slave_idlemode(oh, HWMOD_IDLEMODE_SMART_WKUP, v);
arch/arm/mach-omap2/omap_hwmod.c
619
_set_master_standbymode(oh, HWMOD_IDLEMODE_SMART_WKUP, v);
arch/arm/mach-omap2/omap_hwmod.h
636
void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs);
arch/arm/mach-omap2/pdata-quirks.c
146
u32 v;
arch/arm/mach-omap2/pdata-quirks.c
148
v = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
arch/arm/mach-omap2/pdata-quirks.c
149
v |= (AM35XX_CPGMAC_C0_RX_PULSE_CLR | AM35XX_CPGMAC_C0_TX_PULSE_CLR |
arch/arm/mach-omap2/pdata-quirks.c
151
omap_ctrl_writel(v, AM35XX_CONTROL_LVL_INTR_CLEAR);
arch/arm/mach-omap2/pdata-quirks.c
157
u32 v;
arch/arm/mach-omap2/pdata-quirks.c
159
v = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
arch/arm/mach-omap2/pdata-quirks.c
160
v |= (AM35XX_CPGMAC_C0_RX_PULSE_CLR | AM35XX_CPGMAC_C0_TX_PULSE_CLR);
arch/arm/mach-omap2/pdata-quirks.c
161
omap_ctrl_writel(v, AM35XX_CONTROL_LVL_INTR_CLEAR);
arch/arm/mach-omap2/pdata-quirks.c
172
u32 v;
arch/arm/mach-omap2/pdata-quirks.c
174
v = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
arch/arm/mach-omap2/pdata-quirks.c
175
v &= ~AM35XX_CPGMACSS_SW_RST;
arch/arm/mach-omap2/pdata-quirks.c
176
omap_ctrl_writel(v, AM35XX_CONTROL_IP_SW_RESET);
arch/arm/mach-omap2/powerdomain.c
337
static int cpu_notifier(struct notifier_block *nb, unsigned long cmd, void *v)
arch/arm/mach-omap2/prm2xxx.c
58
u32 v;
arch/arm/mach-omap2/prm2xxx.c
60
v = omap2_prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTST);
arch/arm/mach-omap2/prm2xxx.c
64
if (v & (1 << p->reg_shift))
arch/arm/mach-omap2/prm2xxx_3xxx.c
159
u32 v;
arch/arm/mach-omap2/prm2xxx_3xxx.c
161
v = pwrst << __ffs(OMAP_LOGICRETSTATE_MASK);
arch/arm/mach-omap2/prm2xxx_3xxx.c
162
omap2_prm_rmw_mod_reg_bits(OMAP_LOGICRETSTATE_MASK, v, pwrdm->prcm_offs,
arch/arm/mach-omap2/prm2xxx_3xxx.h
67
u32 v;
arch/arm/mach-omap2/prm2xxx_3xxx.h
69
v = omap2_prm_read_mod_reg(module, idx);
arch/arm/mach-omap2/prm2xxx_3xxx.h
70
v &= ~mask;
arch/arm/mach-omap2/prm2xxx_3xxx.h
71
v |= bits;
arch/arm/mach-omap2/prm2xxx_3xxx.h
72
omap2_prm_write_mod_reg(v, module, idx);
arch/arm/mach-omap2/prm2xxx_3xxx.h
74
return v;
arch/arm/mach-omap2/prm2xxx_3xxx.h
80
u32 v;
arch/arm/mach-omap2/prm2xxx_3xxx.h
82
v = omap2_prm_read_mod_reg(domain, idx);
arch/arm/mach-omap2/prm2xxx_3xxx.h
83
v &= mask;
arch/arm/mach-omap2/prm2xxx_3xxx.h
84
v >>= __ffs(mask);
arch/arm/mach-omap2/prm2xxx_3xxx.h
86
return v;
arch/arm/mach-omap2/prm33xx.c
148
u32 v;
arch/arm/mach-omap2/prm33xx.c
150
v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
arch/arm/mach-omap2/prm33xx.c
151
v &= OMAP_POWERSTATE_MASK;
arch/arm/mach-omap2/prm33xx.c
152
v >>= OMAP_POWERSTATE_SHIFT;
arch/arm/mach-omap2/prm33xx.c
154
return v;
arch/arm/mach-omap2/prm33xx.c
159
u32 v;
arch/arm/mach-omap2/prm33xx.c
161
v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);
arch/arm/mach-omap2/prm33xx.c
162
v &= OMAP_POWERSTATEST_MASK;
arch/arm/mach-omap2/prm33xx.c
163
v >>= OMAP_POWERSTATEST_SHIFT;
arch/arm/mach-omap2/prm33xx.c
165
return v;
arch/arm/mach-omap2/prm33xx.c
200
u32 v;
arch/arm/mach-omap2/prm33xx.c
202
v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);
arch/arm/mach-omap2/prm33xx.c
203
v &= AM33XX_LOGICSTATEST_MASK;
arch/arm/mach-omap2/prm33xx.c
204
v >>= AM33XX_LOGICSTATEST_SHIFT;
arch/arm/mach-omap2/prm33xx.c
206
return v;
arch/arm/mach-omap2/prm33xx.c
211
u32 v, m;
arch/arm/mach-omap2/prm33xx.c
217
v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
arch/arm/mach-omap2/prm33xx.c
218
v &= m;
arch/arm/mach-omap2/prm33xx.c
219
v >>= __ffs(m);
arch/arm/mach-omap2/prm33xx.c
221
return v;
arch/arm/mach-omap2/prm33xx.c
256
u32 m, v;
arch/arm/mach-omap2/prm33xx.c
262
v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);
arch/arm/mach-omap2/prm33xx.c
263
v &= m;
arch/arm/mach-omap2/prm33xx.c
264
v >>= __ffs(m);
arch/arm/mach-omap2/prm33xx.c
266
return v;
arch/arm/mach-omap2/prm33xx.c
271
u32 m, v;
arch/arm/mach-omap2/prm33xx.c
277
v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
arch/arm/mach-omap2/prm33xx.c
278
v &= m;
arch/arm/mach-omap2/prm33xx.c
279
v >>= __ffs(m);
arch/arm/mach-omap2/prm33xx.c
281
return v;
arch/arm/mach-omap2/prm33xx.c
34
u32 v;
arch/arm/mach-omap2/prm33xx.c
36
v = am33xx_prm_read_reg(inst, idx);
arch/arm/mach-omap2/prm33xx.c
37
v &= ~mask;
arch/arm/mach-omap2/prm33xx.c
38
v |= bits;
arch/arm/mach-omap2/prm33xx.c
39
am33xx_prm_write_reg(v, inst, idx);
arch/arm/mach-omap2/prm33xx.c
41
return v;
arch/arm/mach-omap2/prm33xx.c
59
u32 v;
arch/arm/mach-omap2/prm33xx.c
61
v = am33xx_prm_read_reg(inst, rstctrl_offs);
arch/arm/mach-omap2/prm33xx.c
62
v &= 1 << shift;
arch/arm/mach-omap2/prm33xx.c
63
v >>= shift;
arch/arm/mach-omap2/prm33xx.c
65
return v;
arch/arm/mach-omap2/prm3xxx.c
451
u32 v;
arch/arm/mach-omap2/prm3xxx.c
453
v = omap2_prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTST);
arch/arm/mach-omap2/prm3xxx.c
457
if (v & (1 << p->reg_shift))
arch/arm/mach-omap2/prm44xx.c
110
u32 v;
arch/arm/mach-omap2/prm44xx.c
112
v = omap4_prm_read_inst_reg(inst, reg);
arch/arm/mach-omap2/prm44xx.c
113
v &= ~mask;
arch/arm/mach-omap2/prm44xx.c
114
v |= bits;
arch/arm/mach-omap2/prm44xx.c
115
omap4_prm_write_inst_reg(v, inst, reg);
arch/arm/mach-omap2/prm44xx.c
117
return v;
arch/arm/mach-omap2/prm44xx.c
374
u32 v;
arch/arm/mach-omap2/prm44xx.c
381
v = omap4_prm_read_inst_reg(inst,
arch/arm/mach-omap2/prm44xx.c
386
if (v & (1 << p->reg_shift))
arch/arm/mach-omap2/prm44xx.c
438
u32 v;
arch/arm/mach-omap2/prm44xx.c
440
v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
arch/arm/mach-omap2/prm44xx.c
442
v &= OMAP_POWERSTATE_MASK;
arch/arm/mach-omap2/prm44xx.c
443
v >>= OMAP_POWERSTATE_SHIFT;
arch/arm/mach-omap2/prm44xx.c
445
return v;
arch/arm/mach-omap2/prm44xx.c
450
u32 v;
arch/arm/mach-omap2/prm44xx.c
452
v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
arch/arm/mach-omap2/prm44xx.c
454
v &= OMAP_POWERSTATEST_MASK;
arch/arm/mach-omap2/prm44xx.c
455
v >>= OMAP_POWERSTATEST_SHIFT;
arch/arm/mach-omap2/prm44xx.c
457
return v;
arch/arm/mach-omap2/prm44xx.c
462
u32 v;
arch/arm/mach-omap2/prm44xx.c
464
v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
arch/arm/mach-omap2/prm44xx.c
466
v &= OMAP4430_LASTPOWERSTATEENTERED_MASK;
arch/arm/mach-omap2/prm44xx.c
467
v >>= OMAP4430_LASTPOWERSTATEENTERED_SHIFT;
arch/arm/mach-omap2/prm44xx.c
469
return v;
arch/arm/mach-omap2/prm44xx.c
492
u32 v;
arch/arm/mach-omap2/prm44xx.c
494
v = pwrst << __ffs(OMAP4430_LOGICRETSTATE_MASK);
arch/arm/mach-omap2/prm44xx.c
495
omap4_prminst_rmw_inst_reg_bits(OMAP4430_LOGICRETSTATE_MASK, v,
arch/arm/mach-omap2/prm44xx.c
532
u32 v;
arch/arm/mach-omap2/prm44xx.c
534
v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
arch/arm/mach-omap2/prm44xx.c
536
v &= OMAP4430_LOGICSTATEST_MASK;
arch/arm/mach-omap2/prm44xx.c
537
v >>= OMAP4430_LOGICSTATEST_SHIFT;
arch/arm/mach-omap2/prm44xx.c
539
return v;
arch/arm/mach-omap2/prm44xx.c
544
u32 v;
arch/arm/mach-omap2/prm44xx.c
546
v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
arch/arm/mach-omap2/prm44xx.c
548
v &= OMAP4430_LOGICRETSTATE_MASK;
arch/arm/mach-omap2/prm44xx.c
549
v >>= OMAP4430_LOGICRETSTATE_SHIFT;
arch/arm/mach-omap2/prm44xx.c
551
return v;
arch/arm/mach-omap2/prm44xx.c
584
u32 m, v;
arch/arm/mach-omap2/prm44xx.c
588
v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
arch/arm/mach-omap2/prm44xx.c
590
v &= m;
arch/arm/mach-omap2/prm44xx.c
591
v >>= __ffs(m);
arch/arm/mach-omap2/prm44xx.c
593
return v;
arch/arm/mach-omap2/prm44xx.c
598
u32 m, v;
arch/arm/mach-omap2/prm44xx.c
602
v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
arch/arm/mach-omap2/prm44xx.c
604
v &= m;
arch/arm/mach-omap2/prm44xx.c
605
v >>= __ffs(m);
arch/arm/mach-omap2/prm44xx.c
607
return v;
arch/arm/mach-omap2/prm44xx.c
770
static int cpu_notifier(struct notifier_block *nb, unsigned long cmd, void *v)
arch/arm/mach-omap2/prminst44xx.c
102
u32 v;
arch/arm/mach-omap2/prminst44xx.c
104
v = omap4_prminst_read_inst_reg(part, inst, rstctrl_offs);
arch/arm/mach-omap2/prminst44xx.c
105
v &= 1 << shift;
arch/arm/mach-omap2/prminst44xx.c
106
v >>= shift;
arch/arm/mach-omap2/prminst44xx.c
108
return v;
arch/arm/mach-omap2/prminst44xx.c
180
u32 v;
arch/arm/mach-omap2/prminst44xx.c
186
v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION, inst,
arch/arm/mach-omap2/prminst44xx.c
188
v |= OMAP4430_RST_GLOBAL_WARM_SW_MASK;
arch/arm/mach-omap2/prminst44xx.c
189
omap4_prminst_write_inst_reg(v, OMAP4430_PRM_PARTITION,
arch/arm/mach-omap2/prminst44xx.c
193
v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
arch/arm/mach-omap2/prminst44xx.c
79
u32 v;
arch/arm/mach-omap2/prminst44xx.c
81
v = omap4_prminst_read_inst_reg(part, inst, idx);
arch/arm/mach-omap2/prminst44xx.c
82
v &= ~mask;
arch/arm/mach-omap2/prminst44xx.c
83
v |= bits;
arch/arm/mach-omap2/prminst44xx.c
84
omap4_prminst_write_inst_reg(v, part, inst, idx);
arch/arm/mach-omap2/prminst44xx.c
86
return v;
arch/arm/mach-omap2/sr_device.c
47
u32 v;
arch/arm/mach-omap2/sr_device.c
57
v = omap_ctrl_readb(offset) |
arch/arm/mach-omap2/sr_device.c
61
v = omap_ctrl_readl(volt_data[i].sr_efuse_offs);
arch/arm/mach-omap2/sr_device.c
72
if (v == 0)
arch/arm/mach-omap2/sr_device.c
75
nvalue_table[j].nvalue = v;
arch/arm/mach-omap2/voltage.c
333
struct voltagedomain **v;
arch/arm/mach-omap2/voltage.c
336
for (v = voltdms; *v; v++)
arch/arm/mach-omap2/voltage.c
337
_voltdm_register(*v);
arch/arm/mach-rpc/ecard.c
650
static int ecard_devices_proc_show(struct seq_file *m, void *v)
arch/arm/mach-rpc/ecard.c
92
static inline unsigned short ecard_getu16(unsigned char *v)
arch/arm/mach-rpc/ecard.c
94
return v[0] | v[1] << 8;
arch/arm/mach-rpc/ecard.c
97
static inline signed long ecard_gets24(unsigned char *v)
arch/arm/mach-rpc/ecard.c
99
return v[0] | v[1] << 8 | v[2] << 16 | ((v[2] & 0x80) ? 0xff000000 : 0);
arch/arm/mach-rpc/include/mach/acornfb.h
48
u_int rr, v, p;
arch/arm/mach-rpc/include/mach/acornfb.h
53
v = (rr + pixclk / 2) / pixclk;
arch/arm/mach-rpc/include/mach/acornfb.h
55
if (v > 32 || v < 2)
arch/arm/mach-rpc/include/mach/acornfb.h
58
p = (rr + v / 2) / v;
arch/arm/mach-rpc/include/mach/acornfb.h
67
best_v = v - 1;
arch/arm/mach-rpc/include/mach/uncompress.h
56
#define palette_write(v) *(unsigned long *)(IO_START+0x00400000) = 0x00000000|((v) & 0x00ffffff)
arch/arm/mach-sa1100/assabet.c
81
unsigned long m = mask, v = val;
arch/arm/mach-sa1100/assabet.c
83
assabet_bcr_gc->set_multiple(assabet_bcr_gc, &m, &v);
arch/arm/mach-sa1100/include/mach/neponset.h
28
#define neponset_ncr_set(v) neponset_ncr_frob(0, v)
arch/arm/mach-sa1100/include/mach/neponset.h
29
#define neponset_ncr_clear(v) neponset_ncr_frob(v, 0)
arch/arm/mach-sa1100/neponset.c
126
unsigned long m = mask, v = val;
arch/arm/mach-sa1100/neponset.c
129
n->gpio[0]->set_multiple(n->gpio[0], &m, &v);
arch/arm/mach-shmobile/platsmp-apmu.c
110
: "=&r" (v)
arch/arm/mach-shmobile/platsmp-apmu.c
159
unsigned int v;
arch/arm/mach-shmobile/platsmp-apmu.c
167
: "=&r" (v)
arch/arm/mach-shmobile/platsmp-apmu.c
91
unsigned int v;
arch/arm/mach-shmobile/platsmp-apmu.c
97
: "=&r" (v)
arch/arm/mach-spear/hotplug.c
20
unsigned int v;
arch/arm/mach-spear/hotplug.c
34
: "=&r" (v)
arch/arm/mach-spear/hotplug.c
41
unsigned int v;
arch/arm/mach-spear/hotplug.c
49
: "=&r" (v)
arch/arm/mach-tegra/irq.c
47
unsigned long cmd, void *v)
arch/arm/mach-versatile/hotplug.c
22
unsigned int v;
arch/arm/mach-versatile/hotplug.c
36
: "=&r" (v)
arch/arm/mach-versatile/hotplug.c
43
unsigned int v;
arch/arm/mach-versatile/hotplug.c
52
: "=&r" (v)
arch/arm/mm/alignment.c
131
static int alignment_proc_show(struct seq_file *m, void *v)
arch/arm/mm/alignment.c
217
unsigned int err = 0, v, a = addr; \
arch/arm/mm/alignment.c
218
__get8_unaligned_check(ins,v,a,err); \
arch/arm/mm/alignment.c
219
val = v << ((BE) ? 8 : 0); \
arch/arm/mm/alignment.c
220
__get8_unaligned_check(ins,v,a,err); \
arch/arm/mm/alignment.c
221
val |= v << ((BE) ? 0 : 8); \
arch/arm/mm/alignment.c
234
unsigned int err = 0, v, a = addr; \
arch/arm/mm/alignment.c
235
__get8_unaligned_check(ins,v,a,err); \
arch/arm/mm/alignment.c
236
val = v << ((BE) ? 24 : 0); \
arch/arm/mm/alignment.c
237
__get8_unaligned_check(ins,v,a,err); \
arch/arm/mm/alignment.c
238
val |= v << ((BE) ? 16 : 8); \
arch/arm/mm/alignment.c
239
__get8_unaligned_check(ins,v,a,err); \
arch/arm/mm/alignment.c
240
val |= v << ((BE) ? 8 : 16); \
arch/arm/mm/alignment.c
241
__get8_unaligned_check(ins,v,a,err); \
arch/arm/mm/alignment.c
242
val |= v << ((BE) ? 0 : 24); \
arch/arm/mm/alignment.c
255
unsigned int err = 0, v = val, a = addr; \
arch/arm/mm/alignment.c
273
: "=r" (err), "=&r" (v), "=&r" (a) \
arch/arm/mm/alignment.c
274
: "0" (err), "1" (v), "2" (a)); \
arch/arm/mm/alignment.c
287
unsigned int err = 0, v = val, a = addr; \
arch/arm/mm/alignment.c
315
: "=r" (err), "=&r" (v), "=&r" (a) \
arch/arm/mm/alignment.c
316
: "0" (err), "1" (v), "2" (a)); \
arch/arm/mm/fault-armv.c
243
unsigned long v = 1;
arch/arm/mm/fault-armv.c
257
v = check_writebuffer(p1, p2);
arch/arm/mm/fault-armv.c
270
if (v) {
arch/arm/mm/mmu.c
668
pteval_t v = pgprot_val(protection_map[i]);
arch/arm/mm/mmu.c
669
protection_map[i] = __pgprot(v | user_pgprot);
arch/arm/mm/pmsa-v7.c
103
static inline void rgnr_write(u32 v)
arch/arm/mm/pmsa-v7.c
105
writel_relaxed(v, BASEADDR_V7M_SCB + PMSAv7_RNR);
arch/arm/mm/pmsa-v7.c
111
static inline void dracr_write(u32 v)
arch/arm/mm/pmsa-v7.c
115
writel_relaxed((v << 16) | rsr, BASEADDR_V7M_SCB + PMSAv7_RASR);
arch/arm/mm/pmsa-v7.c
119
static inline void drsr_write(u32 v)
arch/arm/mm/pmsa-v7.c
123
writel_relaxed(v | racr, BASEADDR_V7M_SCB + PMSAv7_RASR);
arch/arm/mm/pmsa-v7.c
127
static inline void drbar_write(u32 v)
arch/arm/mm/pmsa-v7.c
129
writel_relaxed(v, BASEADDR_V7M_SCB + PMSAv7_RBAR);
arch/arm/mm/pmsa-v7.c
139
static inline void iracr_write(u32 v) {}
arch/arm/mm/pmsa-v7.c
140
static inline void irsr_write(u32 v) {}
arch/arm/mm/pmsa-v7.c
141
static inline void irbar_write(u32 v) {}
arch/arm/mm/pmsa-v7.c
47
static inline void rgnr_write(u32 v)
arch/arm/mm/pmsa-v7.c
49
write_sysreg(v, RNGNR);
arch/arm/mm/pmsa-v7.c
55
static inline void dracr_write(u32 v)
arch/arm/mm/pmsa-v7.c
57
write_sysreg(v, DRACR);
arch/arm/mm/pmsa-v7.c
61
static inline void drsr_write(u32 v)
arch/arm/mm/pmsa-v7.c
63
write_sysreg(v, DRSR);
arch/arm/mm/pmsa-v7.c
67
static inline void drbar_write(u32 v)
arch/arm/mm/pmsa-v7.c
69
write_sysreg(v, DRBAR);
arch/arm/mm/pmsa-v7.c
79
static inline void iracr_write(u32 v)
arch/arm/mm/pmsa-v7.c
81
write_sysreg(v, IRACR);
arch/arm/mm/pmsa-v7.c
85
static inline void irsr_write(u32 v)
arch/arm/mm/pmsa-v7.c
87
write_sysreg(v, IRSR);
arch/arm/mm/pmsa-v7.c
91
static inline void irbar_write(u32 v)
arch/arm/mm/pmsa-v7.c
93
write_sysreg(v, IRBAR);
arch/arm/mm/pmsa-v8.c
35
static inline void prsel_write(u32 v)
arch/arm/mm/pmsa-v8.c
37
write_sysreg(v, PRSEL);
arch/arm/mm/pmsa-v8.c
40
static inline void prbar_write(u32 v)
arch/arm/mm/pmsa-v8.c
42
write_sysreg(v, PRBAR);
arch/arm/mm/pmsa-v8.c
45
static inline void prlar_write(u32 v)
arch/arm/mm/pmsa-v8.c
47
write_sysreg(v, PRLAR);
arch/arm/mm/pmsa-v8.c
61
static inline void prsel_write(u32 v)
arch/arm/mm/pmsa-v8.c
63
writel_relaxed(v, BASEADDR_V7M_SCB + PMSAv8_RNR);
arch/arm/mm/pmsa-v8.c
66
static inline void prbar_write(u32 v)
arch/arm/mm/pmsa-v8.c
68
writel_relaxed(v, BASEADDR_V7M_SCB + PMSAv8_RBAR);
arch/arm/mm/pmsa-v8.c
71
static inline void prlar_write(u32 v)
arch/arm/mm/pmsa-v8.c
73
writel_relaxed(v, BASEADDR_V7M_SCB + PMSAv8_RLAR);
arch/arm/mm/ptdump_debugfs.c
7
static int ptdump_show(struct seq_file *m, void *v)
arch/arm/net/bpf_jit_32.c
296
#define imm12val(v, s) (rol32(v, (s)) | (s) << 7)
arch/arm/net/bpf_jit_32.c
299
u32 v = (x); \
arch/arm/net/bpf_jit_32.c
300
if (!(v & ~0x000000ff)) \
arch/arm/net/bpf_jit_32.c
301
r = imm12val(v, 0); \
arch/arm/net/bpf_jit_32.c
302
else if (!(v & ~0xc000003f)) \
arch/arm/net/bpf_jit_32.c
303
r = imm12val(v, 2); \
arch/arm/net/bpf_jit_32.c
304
else if (!(v & ~0xf000000f)) \
arch/arm/net/bpf_jit_32.c
305
r = imm12val(v, 4); \
arch/arm/net/bpf_jit_32.c
306
else if (!(v & ~0xfc000003)) \
arch/arm/net/bpf_jit_32.c
307
r = imm12val(v, 6); \
arch/arm/net/bpf_jit_32.c
308
else if (!(v & ~0xff000000)) \
arch/arm/net/bpf_jit_32.c
309
r = imm12val(v, 8); \
arch/arm/net/bpf_jit_32.c
310
else if (!(v & ~0x3fc00000)) \
arch/arm/net/bpf_jit_32.c
311
r = imm12val(v, 10); \
arch/arm/net/bpf_jit_32.c
312
else if (!(v & ~0x0ff00000)) \
arch/arm/net/bpf_jit_32.c
313
r = imm12val(v, 12); \
arch/arm/net/bpf_jit_32.c
314
else if (!(v & ~0x03fc0000)) \
arch/arm/net/bpf_jit_32.c
315
r = imm12val(v, 14); \
arch/arm/net/bpf_jit_32.c
316
else if (!(v & ~0x00ff0000)) \
arch/arm/net/bpf_jit_32.c
317
r = imm12val(v, 16); \
arch/arm/net/bpf_jit_32.c
318
else if (!(v & ~0x003fc000)) \
arch/arm/net/bpf_jit_32.c
319
r = imm12val(v, 18); \
arch/arm/net/bpf_jit_32.c
320
else if (!(v & ~0x000ff000)) \
arch/arm/net/bpf_jit_32.c
321
r = imm12val(v, 20); \
arch/arm/net/bpf_jit_32.c
322
else if (!(v & ~0x0003fc00)) \
arch/arm/net/bpf_jit_32.c
323
r = imm12val(v, 22); \
arch/arm/net/bpf_jit_32.c
324
else if (!(v & ~0x0000ff00)) \
arch/arm/net/bpf_jit_32.c
325
r = imm12val(v, 24); \
arch/arm/net/bpf_jit_32.c
326
else if (!(v & ~0x00003fc0)) \
arch/arm/net/bpf_jit_32.c
327
r = imm12val(v, 26); \
arch/arm/net/bpf_jit_32.c
328
else if (!(v & ~0x00000ff0)) \
arch/arm/net/bpf_jit_32.c
329
r = imm12val(v, 28); \
arch/arm/net/bpf_jit_32.c
330
else if (!(v & ~0x000003fc)) \
arch/arm/net/bpf_jit_32.c
331
r = imm12val(v, 30); \
arch/arm/nwfpe/fpmodule.c
48
static int nwfpe_notify(struct notifier_block *self, unsigned long cmd, void *v)
arch/arm/nwfpe/fpmodule.c
50
struct thread_info *thread = v;
arch/arm/plat-orion/gpio.c
390
u32 v;
arch/arm/plat-orion/gpio.c
392
v = readl(GPIO_IN_POL(ochip)) ^ readl(GPIO_DATA_IN(ochip));
arch/arm/plat-orion/gpio.c
398
if (v & (1 << pin))
arch/arm/vfp/vfp.h
177
#define vfp_single_packed_sign(v) ((v) & 0x80000000)
arch/arm/vfp/vfp.h
178
#define vfp_single_packed_negate(v) ((v) ^ 0x80000000)
arch/arm/vfp/vfp.h
179
#define vfp_single_packed_abs(v) ((v) & ~0x80000000)
arch/arm/vfp/vfp.h
180
#define vfp_single_packed_exponent(v) (((v) >> VFP_SINGLE_MANTISSA_BITS) & ((1 << VFP_SINGLE_EXPONENT_BITS) - 1))
arch/arm/vfp/vfp.h
181
#define vfp_single_packed_mantissa(v) ((v) & ((1 << VFP_SINGLE_MANTISSA_BITS) - 1))
arch/arm/vfp/vfp.h
286
#define vfp_double_packed_sign(v) ((v) & (1ULL << 63))
arch/arm/vfp/vfp.h
287
#define vfp_double_packed_negate(v) ((v) ^ (1ULL << 63))
arch/arm/vfp/vfp.h
288
#define vfp_double_packed_abs(v) ((v) & ~(1ULL << 63))
arch/arm/vfp/vfp.h
289
#define vfp_double_packed_exponent(v) (((v) >> VFP_DOUBLE_MANTISSA_BITS) & ((1 << VFP_DOUBLE_EXPONENT_BITS) - 1))
arch/arm/vfp/vfp.h
290
#define vfp_double_packed_mantissa(v) ((v) & ((1ULL << VFP_DOUBLE_MANTISSA_BITS) - 1))
arch/arm/vfp/vfp.h
33
u32 v;
arch/arm/vfp/vfp.h
39
: "=r" (v) : "r" (val) : "cc");
arch/arm/vfp/vfp.h
41
return v;
arch/arm/vfp/vfpmodule.c
187
static int vfp_notifier(struct notifier_block *self, unsigned long cmd, void *v)
arch/arm/vfp/vfpmodule.c
189
struct thread_info *thread = v;
arch/arm/vfp/vfpmodule.c
516
void *v)
arch/arm/vfp/vfpsingle.c
310
u64 v = (u64)a << 31;
arch/arm/vfp/vfpsingle.c
311
do_div(v, z);
arch/arm/vfp/vfpsingle.c
312
return v + (z >> 1);
arch/arm/vfp/vfpsingle.c
899
s32 v;
arch/arm/vfp/vfpsingle.c
901
v = vfp_get_float(sn);
arch/arm/vfp/vfpsingle.c
902
pr_debug("VFP: s%u = %08x\n", sn, v);
arch/arm/vfp/vfpsingle.c
903
vfp_single_unpack(&vsn, v);
arch/arm/vfp/vfpsingle.c
915
v = vfp_get_float(sd);
arch/arm/vfp/vfpsingle.c
916
pr_debug("VFP: s%u = %08x\n", sd, v);
arch/arm/vfp/vfpsingle.c
917
vfp_single_unpack(&vsn, v);
arch/arm64/include/asm/arch_gicv3.h
144
#define gic_write_irouter(v, c) writeq_relaxed(v, c)
arch/arm64/include/asm/arch_gicv3.h
146
#define gic_write_lpir(v, c) writeq_relaxed(v, c)
arch/arm64/include/asm/arch_gicv3.h
152
#define gits_write_baser(v, c) writeq_relaxed(v, c)
arch/arm64/include/asm/arch_gicv3.h
155
#define gits_write_cbaser(v, c) writeq_relaxed(v, c)
arch/arm64/include/asm/arch_gicv3.h
157
#define gits_write_cwriter(v, c) writeq_relaxed(v, c)
arch/arm64/include/asm/arch_gicv3.h
160
#define gicr_write_propbaser(v, c) writeq_relaxed(v, c)
arch/arm64/include/asm/arch_gicv3.h
162
#define gicr_write_pendbaser(v, c) writeq_relaxed(v, c)
arch/arm64/include/asm/arch_gicv3.h
165
#define gicr_write_vpropbaser(v, c) writeq_relaxed(v, c)
arch/arm64/include/asm/arch_gicv3.h
168
#define gicr_write_vpendbaser(v, c) writeq_relaxed(v, c)
arch/arm64/include/asm/arch_gicv3.h
20
#define write_gicreg(v, r) write_sysreg_s(v, SYS_ ## r)
arch/arm64/include/asm/archrandom.h
101
*v++ = res.a1;
arch/arm64/include/asm/archrandom.h
104
*v++ = res.a2;
arch/arm64/include/asm/archrandom.h
107
*v++ = res.a3;
arch/arm64/include/asm/archrandom.h
119
if (__cpu_has_rng() && __arm64_rndrrs(v))
arch/arm64/include/asm/archrandom.h
26
static inline bool __arm64_rndr(unsigned long *v)
arch/arm64/include/asm/archrandom.h
37
: "=r" (*v), "=r" (ok)
arch/arm64/include/asm/archrandom.h
44
static inline bool __arm64_rndrrs(unsigned long *v)
arch/arm64/include/asm/archrandom.h
55
: "=r" (*v), "=r" (ok)
arch/arm64/include/asm/archrandom.h
69
static inline size_t __must_check arch_get_random_longs(unsigned long *v, size_t max_longs)
arch/arm64/include/asm/archrandom.h
77
if (max_longs && __cpu_has_rng() && __arm64_rndr(v))
arch/arm64/include/asm/archrandom.h
82
static inline size_t __must_check arch_get_random_seed_longs(unsigned long *v, size_t max_longs)
arch/arm64/include/asm/atomic.h
102
#define arch_atomic_read(v) __READ_ONCE((v)->counter)
arch/arm64/include/asm/atomic.h
103
#define arch_atomic_set(v, i) __WRITE_ONCE(((v)->counter), (i))
arch/arm64/include/asm/atomic.h
20
static __always_inline void arch_##op(int i, atomic_t *v) \
arch/arm64/include/asm/atomic.h
22
__lse_ll_sc_body(op, i, v); \
arch/arm64/include/asm/atomic.h
35
static __always_inline int arch_##op##name(int i, atomic_t *v) \
arch/arm64/include/asm/atomic.h
37
return __lse_ll_sc_body(op##name, i, v); \
arch/arm64/include/asm/atomic.h
59
static __always_inline void arch_##op(long i, atomic64_t *v) \
arch/arm64/include/asm/atomic.h
61
__lse_ll_sc_body(op, i, v); \
arch/arm64/include/asm/atomic.h
74
static __always_inline long arch_##op##name(long i, atomic64_t *v) \
arch/arm64/include/asm/atomic.h
76
return __lse_ll_sc_body(op##name, i, v); \
arch/arm64/include/asm/atomic.h
97
static __always_inline long arch_atomic64_dec_if_positive(atomic64_t *v)
arch/arm64/include/asm/atomic.h
99
return __lse_ll_sc_body(atomic64_dec_if_positive, v);
arch/arm64/include/asm/atomic_ll_sc.h
123
__ll_sc_atomic64_##op(s64 i, atomic64_t *v) \
arch/arm64/include/asm/atomic_ll_sc.h
134
: "=&r" (result), "=&r" (tmp), "+Q" (v->counter) \
arch/arm64/include/asm/atomic_ll_sc.h
140
__ll_sc_atomic64_##op##_return##name(s64 i, atomic64_t *v) \
arch/arm64/include/asm/atomic_ll_sc.h
152
: "=&r" (result), "=&r" (tmp), "+Q" (v->counter) \
arch/arm64/include/asm/atomic_ll_sc.h
161
__ll_sc_atomic64_fetch_##op##name(s64 i, atomic64_t *v) \
arch/arm64/include/asm/atomic_ll_sc.h
173
: "=&r" (result), "=&r" (val), "=&r" (tmp), "+Q" (v->counter) \
arch/arm64/include/asm/atomic_ll_sc.h
218
__ll_sc_atomic64_dec_if_positive(atomic64_t *v)
arch/arm64/include/asm/atomic_ll_sc.h
232
: "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
arch/arm64/include/asm/atomic_ll_sc.h
266
[v] "+Q" (*(u##sz *)ptr) \
arch/arm64/include/asm/atomic_ll_sc.h
27
__ll_sc_atomic_##op(int i, atomic_t *v) \
arch/arm64/include/asm/atomic_ll_sc.h
322
: [v] "+Q" (*(u128 *)ptr), \
arch/arm64/include/asm/atomic_ll_sc.h
38
: "=&r" (result), "=&r" (tmp), "+Q" (v->counter) \
arch/arm64/include/asm/atomic_ll_sc.h
44
__ll_sc_atomic_##op##_return##name(int i, atomic_t *v) \
arch/arm64/include/asm/atomic_ll_sc.h
56
: "=&r" (result), "=&r" (tmp), "+Q" (v->counter) \
arch/arm64/include/asm/atomic_ll_sc.h
65
__ll_sc_atomic_fetch_##op##name(int i, atomic_t *v) \
arch/arm64/include/asm/atomic_ll_sc.h
77
: "=&r" (result), "=&r" (val), "=&r" (tmp), "+Q" (v->counter) \
arch/arm64/include/asm/atomic_lse.h
101
static __always_inline void __lse_atomic_and(int i, atomic_t *v)
arch/arm64/include/asm/atomic_lse.h
103
return __lse_atomic_andnot(~i, v);
arch/arm64/include/asm/atomic_lse.h
108
__lse_atomic_fetch_and##name(int i, atomic_t *v) \
arch/arm64/include/asm/atomic_lse.h
110
return __lse_atomic_fetch_andnot##name(~i, v); \
arch/arm64/include/asm/atomic_lse.h
122
__lse_atomic64_##op(s64 i, atomic64_t *v) \
arch/arm64/include/asm/atomic_lse.h
127
: [v] "+Q" (v->counter) \
arch/arm64/include/asm/atomic_lse.h
136
static __always_inline void __lse_atomic64_sub(s64 i, atomic64_t *v)
arch/arm64/include/asm/atomic_lse.h
138
__lse_atomic64_add(-i, v);
arch/arm64/include/asm/atomic_lse.h
145
__lse_atomic64_fetch_##op##name(s64 i, atomic64_t *v) \
arch/arm64/include/asm/atomic_lse.h
15
__lse_atomic_##op(int i, atomic_t *v) \
arch/arm64/include/asm/atomic_lse.h
152
: [v] "+Q" (v->counter), \
arch/arm64/include/asm/atomic_lse.h
176
__lse_atomic64_fetch_sub##name(s64 i, atomic64_t *v) \
arch/arm64/include/asm/atomic_lse.h
178
return __lse_atomic64_fetch_add##name(-i, v); \
arch/arm64/include/asm/atomic_lse.h
190
__lse_atomic64_add_return##name(s64 i, atomic64_t *v) \
arch/arm64/include/asm/atomic_lse.h
192
return __lse_atomic64_fetch_add##name(i, v) + i; \
arch/arm64/include/asm/atomic_lse.h
196
__lse_atomic64_sub_return##name(s64 i, atomic64_t *v) \
arch/arm64/include/asm/atomic_lse.h
198
return __lse_atomic64_fetch_sub##name(i, v) - i; \
arch/arm64/include/asm/atomic_lse.h
20
: [v] "+Q" (v->counter) \
arch/arm64/include/asm/atomic_lse.h
208
static __always_inline void __lse_atomic64_and(s64 i, atomic64_t *v)
arch/arm64/include/asm/atomic_lse.h
210
return __lse_atomic64_andnot(~i, v);
arch/arm64/include/asm/atomic_lse.h
215
__lse_atomic64_fetch_and##name(s64 i, atomic64_t *v) \
arch/arm64/include/asm/atomic_lse.h
217
return __lse_atomic64_fetch_andnot##name(~i, v); \
arch/arm64/include/asm/atomic_lse.h
227
static __always_inline s64 __lse_atomic64_dec_if_positive(atomic64_t *v)
arch/arm64/include/asm/atomic_lse.h
241
: [ret] "+&r" (v), [v] "+Q" (v->counter), [tmp] "=&r" (tmp)
arch/arm64/include/asm/atomic_lse.h
245
return (long)v;
arch/arm64/include/asm/atomic_lse.h
257
: [v] "+Q" (*(u##sz *)ptr), \
arch/arm64/include/asm/atomic_lse.h
29
static __always_inline void __lse_atomic_sub(int i, atomic_t *v)
arch/arm64/include/asm/atomic_lse.h
300
[v] "+Q" (*(u128 *)ptr) \
arch/arm64/include/asm/atomic_lse.h
31
__lse_atomic_add(-i, v);
arch/arm64/include/asm/atomic_lse.h
38
__lse_atomic_fetch_##op##name(int i, atomic_t *v) \
arch/arm64/include/asm/atomic_lse.h
45
: [v] "+Q" (v->counter), \
arch/arm64/include/asm/atomic_lse.h
69
__lse_atomic_fetch_sub##name(int i, atomic_t *v) \
arch/arm64/include/asm/atomic_lse.h
71
return __lse_atomic_fetch_add##name(-i, v); \
arch/arm64/include/asm/atomic_lse.h
83
__lse_atomic_add_return##name(int i, atomic_t *v) \
arch/arm64/include/asm/atomic_lse.h
85
return __lse_atomic_fetch_add##name(i, v) + i; \
arch/arm64/include/asm/atomic_lse.h
89
__lse_atomic_sub_return##name(int i, atomic_t *v) \
arch/arm64/include/asm/atomic_lse.h
91
return __lse_atomic_fetch_sub(i, v) - i; \
arch/arm64/include/asm/barrier.h
130
#define __smp_store_release(p, v) \
arch/arm64/include/asm/barrier.h
134
{ .__val = (__force __unqual_scalar_typeof(*p)) (v) }; \
arch/arm64/include/asm/cmpxchg.h
227
: [tmp] "=&r" (tmp), [v] "+Q" (*(u##sz *)ptr) \
arch/arm64/include/asm/cputype.h
290
#define MIDR_REV_RANGE(m, v, r_min, r_max) MIDR_RANGE(m, v, r_min, v, r_max)
arch/arm64/include/asm/cputype.h
291
#define MIDR_REV(m, v, r) MIDR_RANGE(m, v, r, v, r)
arch/arm64/include/asm/fpsimdmacros.h
293
mov v\nz\().16b, v\nz\().16b
arch/arm64/include/asm/fpsimdmacros.h
96
.macro _sme_check_wv v
arch/arm64/include/asm/io.h
112
: "=r" (tmp) : "r" ((unsigned long)(v)) \
arch/arm64/include/asm/io.h
117
#define __io_br(v)
arch/arm64/include/asm/io.h
118
#define __io_aw(v)
arch/arm64/include/asm/io.h
121
#define __iormb(v) __io_ar(v)
arch/arm64/include/asm/io.h
302
#define iowrite16be(v,p) ({ __iowmb(); __raw_writew((__force __u16)cpu_to_be16(v), p); })
arch/arm64/include/asm/io.h
303
#define iowrite32be(v,p) ({ __iowmb(); __raw_writel((__force __u32)cpu_to_be32(v), p); })
arch/arm64/include/asm/io.h
304
#define iowrite64be(v,p) ({ __iowmb(); __raw_writeq((__force __u64)cpu_to_be64(v), p); })
arch/arm64/include/asm/io.h
99
#define __io_ar(v) \
arch/arm64/include/asm/kvm_emulate.h
607
#define kvm_pend_exception(v, e) \
arch/arm64/include/asm/kvm_emulate.h
609
WARN_ON(vcpu_get_flag((v), INCREMENT_PC)); \
arch/arm64/include/asm/kvm_emulate.h
610
vcpu_set_flag((v), PENDING_EXCEPTION); \
arch/arm64/include/asm/kvm_emulate.h
611
vcpu_set_flag((v), e); \
arch/arm64/include/asm/kvm_host.h
1000
#define __vcpu_test_and_clear_flag(v, flagset, f, m) \
arch/arm64/include/asm/kvm_host.h
1002
typeof(v->arch.flagset) set; \
arch/arm64/include/asm/kvm_host.h
1004
set = __vcpu_get_flag(v, flagset, f, m); \
arch/arm64/include/asm/kvm_host.h
1005
__vcpu_clear_flag(v, flagset, f, m); \
arch/arm64/include/asm/kvm_host.h
1010
#define vcpu_get_flag(v, ...) __vcpu_get_flag((v), __VA_ARGS__)
arch/arm64/include/asm/kvm_host.h
1011
#define vcpu_set_flag(v, ...) __vcpu_set_flag((v), __VA_ARGS__)
arch/arm64/include/asm/kvm_host.h
1012
#define vcpu_clear_flag(v, ...) __vcpu_clear_flag((v), __VA_ARGS__)
arch/arm64/include/asm/kvm_host.h
1013
#define vcpu_test_and_clear_flag(v, ...) \
arch/arm64/include/asm/kvm_host.h
1014
__vcpu_test_and_clear_flag((v), __VA_ARGS__)
arch/arm64/include/asm/kvm_host.h
1136
#define vcpu_gp_regs(v) (&(v)->arch.ctxt.regs)
arch/arm64/include/asm/kvm_host.h
1169
#define __vcpu_assign_sys_reg(v, r, val) \
arch/arm64/include/asm/kvm_host.h
1171
const struct kvm_cpu_context *ctxt = &(v)->arch.ctxt; \
arch/arm64/include/asm/kvm_host.h
1173
if (vcpu_has_nv((v)) && (r) >= __SANITISED_REG_START__) \
arch/arm64/include/asm/kvm_host.h
1174
__v = kvm_vcpu_apply_reg_masks((v), (r), __v); \
arch/arm64/include/asm/kvm_host.h
1179
#define __vcpu_rmw_sys_reg(v, r, op, val) \
arch/arm64/include/asm/kvm_host.h
1181
const struct kvm_cpu_context *ctxt = &(v)->arch.ctxt; \
arch/arm64/include/asm/kvm_host.h
1184
if (vcpu_has_nv((v)) && (r) >= __SANITISED_REG_START__) \
arch/arm64/include/asm/kvm_host.h
1185
__v = kvm_vcpu_apply_reg_masks((v), (r), __v); \
arch/arm64/include/asm/kvm_host.h
1190
#define __vcpu_sys_reg(v,r) \
arch/arm64/include/asm/kvm_host.h
1192
const struct kvm_cpu_context *ctxt = &(v)->arch.ctxt; \
arch/arm64/include/asm/kvm_host.h
1194
if (vcpu_has_nv((v)) && (r) >= __SANITISED_REG_START__) \
arch/arm64/include/asm/kvm_host.h
1195
__v = kvm_vcpu_apply_reg_masks((v), (r), __v); \
arch/arm64/include/asm/kvm_host.h
1507
#define vcpu_has_feature(v, f) __vcpu_has_feature(&(v)->kvm->arch, (f))
arch/arm64/include/asm/kvm_host.h
1509
#define kvm_vcpu_initialized(v) vcpu_get_flag(vcpu, VCPU_INITIALIZED)
arch/arm64/include/asm/kvm_host.h
944
#define __build_check_flag(v, flagset, f, m) \
arch/arm64/include/asm/kvm_host.h
946
typeof(v->arch.flagset) *_fset; \
arch/arm64/include/asm/kvm_host.h
954
#define __vcpu_get_flag(v, flagset, f, m) \
arch/arm64/include/asm/kvm_host.h
956
__build_check_flag(v, flagset, f, m); \
arch/arm64/include/asm/kvm_host.h
958
READ_ONCE(v->arch.flagset) & (m); \
arch/arm64/include/asm/kvm_host.h
974
#define __vcpu_set_flag(v, flagset, f, m) \
arch/arm64/include/asm/kvm_host.h
976
typeof(v->arch.flagset) *fset; \
arch/arm64/include/asm/kvm_host.h
978
__build_check_flag(v, flagset, f, m); \
arch/arm64/include/asm/kvm_host.h
980
fset = &v->arch.flagset; \
arch/arm64/include/asm/kvm_host.h
988
#define __vcpu_clear_flag(v, flagset, f, m) \
arch/arm64/include/asm/kvm_host.h
990
typeof(v->arch.flagset) *fset; \
arch/arm64/include/asm/kvm_host.h
992
__build_check_flag(v, flagset, f, m); \
arch/arm64/include/asm/kvm_host.h
994
fset = &v->arch.flagset; \
arch/arm64/include/asm/kvm_hyp.h
28
#define write_sysreg_el0(v,r) write_sysreg_s(v, r##_EL02)
arch/arm64/include/asm/kvm_hyp.h
30
#define write_sysreg_el1(v,r) write_sysreg_s(v, r##_EL12)
arch/arm64/include/asm/kvm_hyp.h
32
#define write_sysreg_el2(v,r) write_sysreg_s(v, r##_EL1)
arch/arm64/include/asm/kvm_hyp.h
52
#define write_sysreg_elx(v,r,nvh,vh) \
arch/arm64/include/asm/kvm_hyp.h
54
u64 __val = (u64)(v); \
arch/arm64/include/asm/kvm_hyp.h
62
#define write_sysreg_el0(v,r) write_sysreg_elx(v, r, _EL0, _EL02)
arch/arm64/include/asm/kvm_hyp.h
64
#define write_sysreg_el1(v,r) write_sysreg_elx(v, r, _EL1, _EL12)
arch/arm64/include/asm/kvm_hyp.h
66
#define write_sysreg_el2(v,r) write_sysreg_elx(v, r, _EL2, _EL1)
arch/arm64/include/asm/kvm_mmu.h
121
static __always_inline unsigned long __kern_hyp_va(unsigned long v)
arch/arm64/include/asm/kvm_mmu.h
136
: "+r" (v));
arch/arm64/include/asm/kvm_mmu.h
138
return v;
arch/arm64/include/asm/kvm_mmu.h
141
#define kern_hyp_va(v) ((typeof(v))(__kern_hyp_va((unsigned long)(v))))
arch/arm64/include/asm/pointer_auth.h
44
#define __ptrauth_key_install_nosync(k, v) \
arch/arm64/include/asm/pointer_auth.h
46
struct ptrauth_key __pki_v = (v); \
arch/arm64/include/asm/rqspinlock.h
89
#define res_smp_cond_load_acquire(v, c) smp_cond_load_acquire_timewait(v, c, 0, 1)
arch/arm64/include/asm/sysreg.h
1102
#define gic_insn(v, insn) write_sysreg_s(v, GICV5_OP_GIC_##insn)
arch/arm64/include/asm/sysreg.h
1148
#define __mrs_s(v, r) \
arch/arm64/include/asm/sysreg.h
1150
" mrs_s " v ", " __stringify(r) "\n" \
arch/arm64/include/asm/sysreg.h
1153
#define __msr_s(r, v) \
arch/arm64/include/asm/sysreg.h
1155
" msr_s " __stringify(r) ", " v "\n" \
arch/arm64/include/asm/sysreg.h
1172
#define write_sysreg(v, r) do { \
arch/arm64/include/asm/sysreg.h
1173
u64 __val = (u64)(v); \
arch/arm64/include/asm/sysreg.h
1199
#define write_sysreg_s(v, r) do { \
arch/arm64/include/asm/sysreg.h
1200
u64 __val = (u64)(v); \
arch/arm64/kernel/cpufeature.c
1949
const char *v = arm64_get_bp_hardening_vector(EL1_VECTOR_KPTI);
arch/arm64/kernel/cpufeature.c
1951
__this_cpu_write(this_cpu_vector, v);
arch/arm64/kernel/cpuinfo.c
214
static int c_show(struct seq_file *m, void *v)
arch/arm64/kernel/cpuinfo.c
219
struct cpuinfo_arm64 *cpuinfo = v;
arch/arm64/kernel/cpuinfo.c
285
static void *c_next(struct seq_file *m, void *v, loff_t *pos)
arch/arm64/kernel/cpuinfo.c
291
static void c_stop(struct seq_file *m, void *v)
arch/arm64/kernel/fpsimd.c
1981
unsigned long cmd, void *v)
arch/arm64/kernel/pi/idreg-override.c
254
static int __init parse_hexdigit(const char *p, u64 *v)
arch/arm64/kernel/pi/idreg-override.c
264
*v = tolower(*p) - (isdigit(*p) ? '0' : 'a' - 10);
arch/arm64/kernel/pi/idreg-override.c
269
const struct ftr_set_desc *reg, int f, u64 *v)
arch/arm64/kernel/pi/idreg-override.c
281
return parse_hexdigit(cmdline + len, v);
arch/arm64/kernel/pi/idreg-override.c
306
u64 v;
arch/arm64/kernel/pi/idreg-override.c
308
if (find_field(cmdline, opt, len, reg, f, &v))
arch/arm64/kernel/pi/idreg-override.c
317
if (filter && !filter(v)) {
arch/arm64/kernel/pi/idreg-override.c
324
override->val |= (v << shift) & mask;
arch/arm64/kernel/proton-pack.c
1002
const char *v = arm64_get_bp_hardening_vector(slot);
arch/arm64/kernel/proton-pack.c
1004
__this_cpu_write(this_cpu_vector, v);
arch/arm64/kernel/proton-pack.c
1013
write_sysreg(v, vbar_el1);
arch/arm64/kernel/setup.c
410
unsigned long v, void *p)
arch/arm64/kvm/arm.c
2261
void *v)
arch/arm64/kvm/arm.c
804
int kvm_arch_vcpu_runnable(struct kvm_vcpu *v)
arch/arm64/kvm/arm.c
806
bool irq_lines = *vcpu_hcr(v) & (HCR_VI | HCR_VF | HCR_VSE);
arch/arm64/kvm/arm.c
808
return ((irq_lines || kvm_vgic_vcpu_pending_irq(v))
arch/arm64/kvm/arm.c
809
&& !kvm_arm_vcpu_stopped(v) && !v->arch.pause);
arch/arm64/kvm/at.c
1035
#define perm_idx(v, r, i) ((vcpu_read_sys_reg((v), (r)) >> ((i) * 4)) & 0xf)
arch/arm64/kvm/at.c
1051
#define set_priv_wxn(wr, v) \
arch/arm64/kvm/at.c
1053
(wr)->pwxn = (v); \
arch/arm64/kvm/at.c
1056
#define set_unpriv_wxn(wr, v) \
arch/arm64/kvm/at.c
1058
(wr)->uwxn = (v); \
arch/arm64/kvm/hyp/include/hyp/debug-sr.h
19
#define write_debug(v,r,n) write_sysreg(v, r##n##_el1)
arch/arm64/kvm/hyp/nvhe/list_debug.c
10
static inline __must_check bool nvhe_check_data_corruption(bool v)
arch/arm64/kvm/hyp/nvhe/list_debug.c
12
return v;
arch/arm64/kvm/hyp/nvhe/switch.c
159
#define __pmu_switch_to_guest(v) ({ false; })
arch/arm64/kvm/hyp/nvhe/switch.c
160
#define __pmu_switch_to_host(v) do {} while (0)
arch/arm64/kvm/hyp/vgic-v3-sr.c
19
#define vtr_to_max_lr_idx(v) ((v) & 0xf)
arch/arm64/kvm/hyp/vgic-v3-sr.c
20
#define vtr_to_nr_pre_bits(v) ((((u32)(v) >> 26) & 7) + 1)
arch/arm64/kvm/hyp/vgic-v3-sr.c
21
#define vtr_to_nr_apr_regs(v) (1 << (vtr_to_nr_pre_bits(v) - 5))
arch/arm64/kvm/nested.c
1681
enum vcpu_sysreg sr, u64 v)
arch/arm64/kvm/nested.c
1686
v &= ~resx.res0;
arch/arm64/kvm/nested.c
1687
v |= resx.res1;
arch/arm64/kvm/nested.c
1689
return v;
arch/arm64/kvm/nested.c
997
#define tlbi_va_s1_to_va(v) (u64)sign_extend64((v) << 12, 48)
arch/arm64/kvm/sys_regs.c
2560
#define SYS_REG_USER_FILTER(name, acc, rst, v, gu, su, filter) { \
arch/arm64/kvm/sys_regs.c
2568
.val = v, \
arch/arm64/kvm/sys_regs.c
2571
#define EL2_REG_FILTERED(name, acc, rst, v, filter) \
arch/arm64/kvm/sys_regs.c
2572
SYS_REG_USER_FILTER(name, acc, rst, v, NULL, NULL, filter)
arch/arm64/kvm/sys_regs.c
2574
#define EL2_REG(name, acc, rst, v) \
arch/arm64/kvm/sys_regs.c
2575
EL2_REG_FILTERED(name, acc, rst, v, el2_visibility)
arch/arm64/kvm/sys_regs.c
2577
#define EL2_REG_VNCR(name, rst, v) EL2_REG(name, bad_vncr_trap, rst, v)
arch/arm64/kvm/sys_regs.c
2582
#define EL2_REG_REDIR(name, rst, v) EL2_REG(name, bad_redir_trap, rst, v)
arch/arm64/kvm/sys_regs.c
5026
static void *idregs_debug_next(struct seq_file *s, void *v, loff_t *pos)
arch/arm64/kvm/sys_regs.c
5035
static void idregs_debug_stop(struct seq_file *s, void *v)
arch/arm64/kvm/sys_regs.c
5039
static int idregs_debug_show(struct seq_file *s, void *v)
arch/arm64/kvm/sys_regs.c
5041
const struct sys_reg_desc *desc = v;
arch/arm64/kvm/sys_regs.c
5089
static void *sr_resx_next(struct seq_file *s, void *v, loff_t *pos)
arch/arm64/kvm/sys_regs.c
5098
static void sr_resx_stop(struct seq_file *s, void *v)
arch/arm64/kvm/sys_regs.c
5102
static int sr_resx_show(struct seq_file *s, void *v)
arch/arm64/kvm/sys_regs.c
5104
const struct sys_reg_desc *desc = v;
arch/arm64/kvm/vgic/vgic-debug.c
121
static void *vgic_debug_next(struct seq_file *s, void *v, loff_t *pos)
arch/arm64/kvm/vgic/vgic-debug.c
124
struct vgic_state_iter *iter = v;
arch/arm64/kvm/vgic/vgic-debug.c
135
static void vgic_debug_stop(struct seq_file *s, void *v)
arch/arm64/kvm/vgic/vgic-debug.c
137
struct vgic_state_iter *iter = v;
arch/arm64/kvm/vgic/vgic-debug.c
139
if (IS_ERR_OR_NULL(v))
arch/arm64/kvm/vgic/vgic-debug.c
234
static int vgic_debug_show(struct seq_file *s, void *v)
arch/arm64/kvm/vgic/vgic-debug.c
237
struct vgic_state_iter *iter = v;
arch/arm64/kvm/vgic/vgic-debug.c
409
static void *vgic_its_debug_next(struct seq_file *s, void *v, loff_t *pos)
arch/arm64/kvm/vgic/vgic-debug.c
412
struct vgic_its_iter *iter = v;
arch/arm64/kvm/vgic/vgic-debug.c
431
static void vgic_its_debug_stop(struct seq_file *s, void *v)
arch/arm64/kvm/vgic/vgic-debug.c
434
struct vgic_its_iter *iter = v;
arch/arm64/kvm/vgic/vgic-debug.c
451
static int vgic_its_debug_show(struct seq_file *s, void *v)
arch/arm64/kvm/vgic/vgic-debug.c
453
struct vgic_its_iter *iter = v;
arch/arm64/mm/ptdump_debugfs.c
7
static int ptdump_show(struct seq_file *m, void *v)
arch/csky/include/asm/atomic.h
104
arch_atomic_fetch_add_unless(atomic_t *v, int a, int u)
arch/csky/include/asm/atomic.h
120
: "r" (a), "r" (&v->counter), "r" (u)
arch/csky/include/asm/atomic.h
128
arch_atomic_inc_unless_negative(atomic_t *v)
arch/csky/include/asm/atomic.h
144
: "r" (&v->counter)
arch/csky/include/asm/atomic.h
153
arch_atomic_dec_unless_positive(atomic_t *v)
arch/csky/include/asm/atomic.h
16
static __always_inline int arch_atomic_read(const atomic_t *v)
arch/csky/include/asm/atomic.h
169
: "r" (&v->counter)
arch/csky/include/asm/atomic.h
177
arch_atomic_dec_if_positive(atomic_t *v)
arch/csky/include/asm/atomic.h
18
return READ_ONCE(v->counter);
arch/csky/include/asm/atomic.h
191
: "r" (&v->counter)
arch/csky/include/asm/atomic.h
20
static __always_inline void arch_atomic_set(atomic_t *v, int i)
arch/csky/include/asm/atomic.h
22
WRITE_ONCE(v->counter, i);
arch/csky/include/asm/atomic.h
27
void arch_atomic_##op(int i, atomic_t *v) \
arch/csky/include/asm/atomic.h
36
: "r" (i), "r" (&v->counter) \
arch/csky/include/asm/atomic.h
50
int arch_atomic_fetch_##op##_relaxed(int i, atomic_t *v) \
arch/csky/include/asm/atomic.h
60
: "r" (i), "r"(&v->counter) \
arch/csky/include/asm/atomic.h
67
int arch_atomic_##op##_return_relaxed(int i, atomic_t *v) \
arch/csky/include/asm/atomic.h
69
return arch_atomic_fetch_##op##_relaxed(i, v) c_op i; \
arch/csky/include/asm/futex.h
109
: [r] "+r" (ret), [v] "=&r" (val), [u] "+m" (*uaddr),
arch/csky/include/asm/io.h
25
#define writeb(v,c) ({ wmb(); writeb_relaxed((v),(c)); })
arch/csky/include/asm/io.h
26
#define writew(v,c) ({ wmb(); writew_relaxed((v),(c)); })
arch/csky/include/asm/io.h
27
#define writel(v,c) ({ wmb(); writel_relaxed((v),(c)); })
arch/csky/include/asm/io.h
29
#define writeb(v,c) ({ wmb(); writeb_relaxed((v),(c)); mb(); })
arch/csky/include/asm/io.h
30
#define writew(v,c) ({ wmb(); writew_relaxed((v),(c)); mb(); })
arch/csky/include/asm/io.h
31
#define writel(v,c) ({ wmb(); writel_relaxed((v),(c)); mb(); })
arch/csky/kernel/cpu-probe.c
46
static int c_show(struct seq_file *m, void *v)
arch/csky/kernel/cpu-probe.c
66
static void *c_next(struct seq_file *m, void *v, loff_t *pos)
arch/csky/kernel/cpu-probe.c
72
static void c_stop(struct seq_file *m, void *v) {}
arch/hexagon/include/asm/atomic.h
109
static inline int arch_atomic_fetch_add_unless(atomic_t *v, int a, int u)
arch/hexagon/include/asm/atomic.h
127
: "r" (v), "r" (a), "r" (u)
arch/hexagon/include/asm/atomic.h
17
static inline void arch_atomic_set(atomic_t *v, int new)
arch/hexagon/include/asm/atomic.h
24
: "r" (&v->counter), "r" (new)
arch/hexagon/include/asm/atomic.h
29
#define arch_atomic_set_release(v, i) arch_atomic_set((v), (i))
arch/hexagon/include/asm/atomic.h
31
#define arch_atomic_read(v) READ_ONCE((v)->counter)
arch/hexagon/include/asm/atomic.h
34
static inline void arch_atomic_##op(int i, atomic_t *v) \
arch/hexagon/include/asm/atomic.h
44
: "r" (&v->counter), "r" (i) \
arch/hexagon/include/asm/atomic.h
50
static inline int arch_atomic_##op##_return(int i, atomic_t *v) \
arch/hexagon/include/asm/atomic.h
60
: "r" (&v->counter), "r" (i) \
arch/hexagon/include/asm/atomic.h
67
static inline int arch_atomic_fetch_##op(int i, atomic_t *v) \
arch/hexagon/include/asm/atomic.h
77
: "r" (&v->counter), "r" (i) \
arch/hexagon/include/asm/cmpxchg.h
45
#define arch_xchg(ptr, v) ((__typeof__(*(ptr)))__arch_xchg((unsigned long)(v), (ptr), \
arch/hexagon/kernel/setup.c
100
static void *c_next(struct seq_file *m, void *v, loff_t *pos)
arch/hexagon/kernel/setup.c
106
static void c_stop(struct seq_file *m, void *v)
arch/hexagon/kernel/setup.c
114
static int show_cpuinfo(struct seq_file *m, void *v)
arch/hexagon/kernel/setup.c
116
int cpu = (unsigned long) v - 1;
arch/loongarch/include/asm/atomic-amo.h
112
static inline void arch_atomic64_##op(long i, atomic64_t *v) \
arch/loongarch/include/asm/atomic-amo.h
116
: "+ZB" (v->counter) \
arch/loongarch/include/asm/atomic-amo.h
122
static inline long arch_atomic64_##op##_return##suffix(long i, atomic64_t *v) \
arch/loongarch/include/asm/atomic-amo.h
127
: "+ZB" (v->counter), "=&r" (result) \
arch/loongarch/include/asm/atomic-amo.h
135
static inline long arch_atomic64_fetch_##op##suffix(long i, atomic64_t *v) \
arch/loongarch/include/asm/atomic-amo.h
141
: "+ZB" (v->counter), "=&r" (result) \
arch/loongarch/include/asm/atomic-amo.h
16
static inline void arch_atomic_##op(int i, atomic_t *v) \
arch/loongarch/include/asm/atomic-amo.h
20
: "+ZB" (v->counter) \
arch/loongarch/include/asm/atomic-amo.h
26
static inline int arch_atomic_##op##_return##suffix(int i, atomic_t *v) \
arch/loongarch/include/asm/atomic-amo.h
32
: "+ZB" (v->counter), "=&r" (result) \
arch/loongarch/include/asm/atomic-amo.h
40
static inline int arch_atomic_fetch_##op##suffix(int i, atomic_t *v) \
arch/loongarch/include/asm/atomic-amo.h
46
: "+ZB" (v->counter), "=&r" (result) \
arch/loongarch/include/asm/atomic-llsc.h
16
static inline void arch_atomic_##op(int i, atomic_t *v) \
arch/loongarch/include/asm/atomic-llsc.h
25
:"=&r" (temp) , "+ZC"(v->counter) \
arch/loongarch/include/asm/atomic-llsc.h
31
static inline int arch_atomic_##op##_return_relaxed(int i, atomic_t *v) \
arch/loongarch/include/asm/atomic-llsc.h
41
: "=&r" (result), "=&r" (temp), "+ZC"(v->counter) \
arch/loongarch/include/asm/atomic-llsc.h
48
static inline int arch_atomic_fetch_##op##_relaxed(int i, atomic_t *v) \
arch/loongarch/include/asm/atomic-llsc.h
58
: "=&r" (result), "=&r" (temp), "+ZC" (v->counter) \
arch/loongarch/include/asm/atomic.h
104
#define arch_atomic_dec_if_positive(v) arch_atomic_sub_if_positive(1, v)
arch/loongarch/include/asm/atomic.h
110
#define arch_atomic64_read(v) READ_ONCE((v)->counter)
arch/loongarch/include/asm/atomic.h
111
#define arch_atomic64_set(v, i) WRITE_ONCE((v)->counter, (i))
arch/loongarch/include/asm/atomic.h
113
static inline long arch_atomic64_fetch_add_unless(atomic64_t *v, long a, long u)
arch/loongarch/include/asm/atomic.h
128
[c] "=ZB" (v->counter)
arch/loongarch/include/asm/atomic.h
136
static inline long arch_atomic64_sub_if_positive(long i, atomic64_t *v)
arch/loongarch/include/asm/atomic.h
151
: "=&r" (result), "=&r" (temp), "+ZC" (v->counter)
arch/loongarch/include/asm/atomic.h
163
: "=&r" (result), "=&r" (temp), "+ZC" (v->counter)
arch/loongarch/include/asm/atomic.h
170
#define arch_atomic64_dec_if_positive(v) arch_atomic64_sub_if_positive(1, v)
arch/loongarch/include/asm/atomic.h
44
#define arch_atomic_read(v) READ_ONCE((v)->counter)
arch/loongarch/include/asm/atomic.h
45
#define arch_atomic_set(v, i) WRITE_ONCE((v)->counter, (i))
arch/loongarch/include/asm/atomic.h
47
static inline int arch_atomic_fetch_add_unless(atomic_t *v, int a, int u)
arch/loongarch/include/asm/atomic.h
62
[c]"=ZB" (v->counter)
arch/loongarch/include/asm/atomic.h
70
static inline int arch_atomic_sub_if_positive(int i, atomic_t *v)
arch/loongarch/include/asm/atomic.h
85
: "=&r" (result), "=&r" (temp), "+ZC" (v->counter)
arch/loongarch/include/asm/atomic.h
97
: "=&r" (result), "=&r" (temp), "+ZC" (v->counter)
arch/loongarch/include/asm/barrier.h
103
WRITE_ONCE(*p, v); \
arch/loongarch/include/asm/barrier.h
106
#define __smp_store_mb(p, v) \
arch/loongarch/include/asm/barrier.h
109
{ .__val = (__force typeof(p)) (v) }; \
arch/loongarch/include/asm/barrier.h
99
#define __smp_store_release(p, v) \
arch/loongarch/include/asm/kvm_csr.h
25
#define gcsr_write(v, csr) \
arch/loongarch/include/asm/kvm_csr.h
27
register unsigned long __v = v; \
arch/loongarch/include/asm/kvm_csr.h
36
#define gcsr_xchg(v, m, csr) \
arch/loongarch/include/asm/kvm_csr.h
38
register unsigned long __v = v; \
arch/loongarch/include/asm/loongson.h
49
: [hw] "r" (addr), [v] "r" (val)
arch/loongarch/include/asm/loongson.h
59
: [hw] "r" (addr), [v] "r" (val64)
arch/loongarch/kernel/module.c
100
return rela_stack_push(v, rela_stack, rela_stack_top);
arch/loongarch/kernel/module.c
103
static int apply_r_larch_sop_push_dup(struct module *mod, u32 *location, Elf_Addr v,
arch/loongarch/kernel/module.c
123
Elf_Shdr *sechdrs, u32 *location, Elf_Addr v,
arch/loongarch/kernel/module.c
126
ptrdiff_t offset = (void *)v - (void *)location;
arch/loongarch/kernel/module.c
129
v = module_emit_plt_entry(mod, sechdrs, v);
arch/loongarch/kernel/module.c
132
v = module_emit_plt_entry(mod, sechdrs, v);
arch/loongarch/kernel/module.c
134
return apply_r_larch_sop_push_pcrel(mod, location, v, rela_stack, rela_stack_top, type);
arch/loongarch/kernel/module.c
137
static int apply_r_larch_sop(struct module *mod, u32 *location, Elf_Addr v,
arch/loongarch/kernel/module.c
183
static int apply_r_larch_sop_imm_field(struct module *mod, u32 *location, Elf_Addr v,
arch/loongarch/kernel/module.c
274
static int apply_r_larch_add_sub(struct module *mod, u32 *location, Elf_Addr v,
arch/loongarch/kernel/module.c
279
*(s32 *)location += v;
arch/loongarch/kernel/module.c
282
*(s32 *)location -= v;
arch/loongarch/kernel/module.c
286
*(s64 *)location += v;
arch/loongarch/kernel/module.c
289
*(s64 *)location -= v;
arch/loongarch/kernel/module.c
299
Elf_Shdr *sechdrs, u32 *location, Elf_Addr v,
arch/loongarch/kernel/module.c
302
ptrdiff_t offset = (void *)v - (void *)location;
arch/loongarch/kernel/module.c
306
v = module_emit_plt_entry(mod, sechdrs, v);
arch/loongarch/kernel/module.c
309
v = module_emit_plt_entry(mod, sechdrs, v);
arch/loongarch/kernel/module.c
311
offset = (void *)v - (void *)location;
arch/loongarch/kernel/module.c
332
static int apply_r_larch_pcadd(struct module *mod, u32 *location, Elf_Addr v,
arch/loongarch/kernel/module.c
337
s32 offset_hi20 = (void *)((v + 0x800)) - (void *)((Elf_Addr)location);
arch/loongarch/kernel/module.c
341
insn->reg2i12_format.immediate = v & 0xfff;
arch/loongarch/kernel/module.c
344
v = offset_hi20 >> 12;
arch/loongarch/kernel/module.c
345
insn->reg1i20_format.immediate = v & 0xfffff;
arch/loongarch/kernel/module.c
35
typedef int (*reloc_rela_handler)(struct module *mod, u32 *location, Elf_Addr v,
arch/loongarch/kernel/module.c
355
static int apply_r_larch_pcala(struct module *mod, u32 *location, Elf_Addr v,
arch/loongarch/kernel/module.c
360
s32 offset_hi20 = (void *)((v + 0x800) & ~0xfff) -
arch/loongarch/kernel/module.c
364
ptrdiff_t offset_rem = (void *)v - (void *)anchor;
arch/loongarch/kernel/module.c
369
insn->reg2i12_format.immediate = v & 0xfff;
arch/loongarch/kernel/module.c
372
v = offset_hi20 >> 12;
arch/loongarch/kernel/module.c
373
insn->reg1i20_format.immediate = v & 0xfffff;
arch/loongarch/kernel/module.c
377
v = offset_rem >> 32;
arch/loongarch/kernel/module.c
378
insn->reg1i20_format.immediate = v & 0xfffff;
arch/loongarch/kernel/module.c
381
v = offset_rem >> 52;
arch/loongarch/kernel/module.c
382
insn->reg2i12_format.immediate = v & 0xfff;
arch/loongarch/kernel/module.c
394
Elf_Shdr *sechdrs, u32 *location, Elf_Addr v,
arch/loongarch/kernel/module.c
400
v = module_emit_got_entry(mod, sechdrs, v);
arch/loongarch/kernel/module.c
401
if (!v)
arch/loongarch/kernel/module.c
427
return got_handler(mod, location, v, rela_stack, rela_stack_top, type);
arch/loongarch/kernel/module.c
430
static int apply_r_larch_32_pcrel(struct module *mod, u32 *location, Elf_Addr v,
arch/loongarch/kernel/module.c
433
ptrdiff_t offset = (void *)v - (void *)location;
arch/loongarch/kernel/module.c
442
static int apply_r_larch_64_pcrel(struct module *mod, u32 *location, Elf_Addr v,
arch/loongarch/kernel/module.c
445
ptrdiff_t offset = (void *)v - (void *)location;
arch/loongarch/kernel/module.c
484
Elf_Addr v;
arch/loongarch/kernel/module.c
523
v = sym->st_value + rel[i].r_addend;
arch/loongarch/kernel/module.c
548
v = lo12 = offset - hi20;
arch/loongarch/kernel/module.c
568
v, rela_stack, &rela_stack_top, type);
arch/loongarch/kernel/module.c
573
v, rela_stack, &rela_stack_top, type);
arch/loongarch/kernel/module.c
577
v, rela_stack, &rela_stack_top, type);
arch/loongarch/kernel/module.c
580
err = handler(mod, location, v, rela_stack, &rela_stack_top, type);
arch/loongarch/kernel/module.c
60
static int apply_r_larch_none(struct module *mod, u32 *location, Elf_Addr v,
arch/loongarch/kernel/module.c
66
static int apply_r_larch_error(struct module *me, u32 *location, Elf_Addr v,
arch/loongarch/kernel/module.c
73
static int apply_r_larch_32(struct module *mod, u32 *location, Elf_Addr v,
arch/loongarch/kernel/module.c
76
*location = v;
arch/loongarch/kernel/module.c
83
static int apply_r_larch_64(struct module *mod, u32 *location, Elf_Addr v,
arch/loongarch/kernel/module.c
86
*(Elf_Addr *)location = v;
arch/loongarch/kernel/module.c
91
static int apply_r_larch_sop_push_pcrel(struct module *mod, u32 *location, Elf_Addr v,
arch/loongarch/kernel/module.c
94
return rela_stack_push(v - (unsigned long)location, rela_stack, rela_stack_top);
arch/loongarch/kernel/module.c
97
static int apply_r_larch_sop_push_absolute(struct module *mod, u32 *location, Elf_Addr v,
arch/loongarch/kernel/proc.c
115
static void *c_next(struct seq_file *m, void *v, loff_t *pos)
arch/loongarch/kernel/proc.c
121
static void c_stop(struct seq_file *m, void *v)
arch/loongarch/kernel/proc.c
16
static int show_cpuinfo(struct seq_file *m, void *v)
arch/loongarch/kernel/proc.c
18
unsigned long n = (unsigned long) v - 1;
arch/loongarch/kernel/relocate.c
284
unsigned long v, void *p)
arch/loongarch/kernel/relocate.c
70
long v = p->symvalue;
arch/loongarch/kernel/relocate.c
77
lu12iw = (v >> 12) & 0xfffff;
arch/loongarch/kernel/relocate.c
78
ori = v & 0xfff;
arch/loongarch/kernel/relocate.c
80
lu32id = (v >> 32) & 0xfffff;
arch/loongarch/kernel/relocate.c
81
lu52id = v >> 52;
arch/loongarch/kvm/vcpu.c
1002
return kvm_set_one_reg(vcpu, reg, v);
arch/loongarch/kvm/vcpu.c
682
static int _kvm_get_cpucfg_mask(int id, u64 *v)
arch/loongarch/kvm/vcpu.c
691
*v = GENMASK(31, 0);
arch/loongarch/kvm/vcpu.c
694
*v = GENMASK(26, 0);
arch/loongarch/kvm/vcpu.c
698
*v = CPUCFG2_FP | CPUCFG2_FPSP | CPUCFG2_FPDP |
arch/loongarch/kvm/vcpu.c
706
*v |= CPUCFG2_LSX;
arch/loongarch/kvm/vcpu.c
708
*v |= CPUCFG2_LASX;
arch/loongarch/kvm/vcpu.c
710
*v |= CPUCFG2_X86BT;
arch/loongarch/kvm/vcpu.c
712
*v |= CPUCFG2_ARMBT;
arch/loongarch/kvm/vcpu.c
714
*v |= CPUCFG2_MIPSBT;
arch/loongarch/kvm/vcpu.c
716
*v |= CPUCFG2_PTW;
arch/loongarch/kvm/vcpu.c
719
*v |= config & (CPUCFG2_FRECIPE | CPUCFG2_DIV32 | CPUCFG2_LAM_BH);
arch/loongarch/kvm/vcpu.c
720
*v |= config & (CPUCFG2_LAMCAS | CPUCFG2_LLACQ_SCREL | CPUCFG2_SCQ);
arch/loongarch/kvm/vcpu.c
723
*v = GENMASK(23, 0);
arch/loongarch/kvm/vcpu.c
727
*v &= config & ~(CPUCFG3_SFB);
arch/loongarch/kvm/vcpu.c
728
*v &= config & ~(CPUCFG3_ALDORDER_CAP | CPUCFG3_ASTORDER_CAP | CPUCFG3_SLDORDER_CAP);
arch/loongarch/kvm/vcpu.c
732
*v = GENMASK(31, 0);
arch/loongarch/kvm/vcpu.c
736
*v = GENMASK(14, 0);
arch/loongarch/kvm/vcpu.c
738
*v = 0;
arch/loongarch/kvm/vcpu.c
741
*v = GENMASK(16, 0);
arch/loongarch/kvm/vcpu.c
744
*v = GENMASK(30, 0);
arch/loongarch/kvm/vcpu.c
751
*v = 0;
arch/loongarch/kvm/vcpu.c
817
const struct kvm_one_reg *reg, u64 *v)
arch/loongarch/kvm/vcpu.c
825
ret = _kvm_getcsr(vcpu, id, v);
arch/loongarch/kvm/vcpu.c
830
*v = vcpu->arch.cpucfg[id];
arch/loongarch/kvm/vcpu.c
840
*v = vcpu->arch.lbt.scr0;
arch/loongarch/kvm/vcpu.c
843
*v = vcpu->arch.lbt.scr1;
arch/loongarch/kvm/vcpu.c
846
*v = vcpu->arch.lbt.scr2;
arch/loongarch/kvm/vcpu.c
849
*v = vcpu->arch.lbt.scr3;
arch/loongarch/kvm/vcpu.c
852
*v = vcpu->arch.lbt.eflags;
arch/loongarch/kvm/vcpu.c
855
*v = vcpu->arch.fpu.ftop;
arch/loongarch/kvm/vcpu.c
865
*v = get_cycles() + vcpu->kvm->arch.time_offset;
arch/loongarch/kvm/vcpu.c
868
*v = INSN_HVCL | KVM_HCALL_SWDBG;
arch/loongarch/kvm/vcpu.c
886
u64 v, size = reg->id & KVM_REG_SIZE_MASK;
arch/loongarch/kvm/vcpu.c
890
ret = kvm_get_one_reg(vcpu, reg, &v);
arch/loongarch/kvm/vcpu.c
893
ret = put_user(v, (u64 __user *)(long)reg->addr);
arch/loongarch/kvm/vcpu.c
904
const struct kvm_one_reg *reg, u64 v)
arch/loongarch/kvm/vcpu.c
912
ret = _kvm_setcsr(vcpu, id, v);
arch/loongarch/kvm/vcpu.c
916
ret = kvm_check_cpucfg(id, v);
arch/loongarch/kvm/vcpu.c
919
vcpu->arch.cpucfg[id] = (u32)v;
arch/loongarch/kvm/vcpu.c
930
vcpu->arch.lbt.scr0 = v;
arch/loongarch/kvm/vcpu.c
933
vcpu->arch.lbt.scr1 = v;
arch/loongarch/kvm/vcpu.c
936
vcpu->arch.lbt.scr2 = v;
arch/loongarch/kvm/vcpu.c
939
vcpu->arch.lbt.scr3 = v;
arch/loongarch/kvm/vcpu.c
942
vcpu->arch.lbt.eflags = v;
arch/loongarch/kvm/vcpu.c
945
vcpu->arch.fpu.ftop = v;
arch/loongarch/kvm/vcpu.c
960
vcpu->kvm->arch.time_offset = (signed long)(v - get_cycles());
arch/loongarch/kvm/vcpu.c
990
u64 v, size = reg->id & KVM_REG_SIZE_MASK;
arch/loongarch/kvm/vcpu.c
994
ret = get_user(v, (u64 __user *)(long)reg->addr);
arch/m68k/amiga/pcmcia.c
70
unsigned char v;
arch/m68k/amiga/pcmcia.c
74
v = GAYLE_CFG_0V;
arch/m68k/amiga/pcmcia.c
77
v = GAYLE_CFG_5V;
arch/m68k/amiga/pcmcia.c
80
v = GAYLE_CFG_12V;
arch/m68k/amiga/pcmcia.c
83
v = GAYLE_CFG_0V;
arch/m68k/amiga/pcmcia.c
86
cfg_byte = (cfg_byte & 0xfc) | v;
arch/m68k/atari/time.c
100
#define COPY(v) val->v=(mste_rtc.v & 0xf)
arch/m68k/atari/time.c
114
#define COPY(v) mste_rtc.v=val->v
arch/m68k/bvme6000/config.c
235
u32 v = 800000, ov;
arch/m68k/bvme6000/config.c
243
ov = v;
arch/m68k/bvme6000/config.c
248
v = (msb << 8) | rtc->t1lsb; /* Read timer1 */
arch/m68k/bvme6000/config.c
251
abs(ov-v) > 80 ||
arch/m68k/bvme6000/config.c
252
v > RTC_TIMER_COUNT - (RTC_TIMER_COUNT / 100));
arch/m68k/bvme6000/config.c
254
v = RTC_TIMER_COUNT - v;
arch/m68k/bvme6000/config.c
256
v += RTC_TIMER_CYCLES / 2;
arch/m68k/bvme6000/config.c
261
v += clk_offset + clk_total;
arch/m68k/bvme6000/config.c
265
return v;
arch/m68k/coldfire/intc-2.c
128
u8 v;
arch/m68k/coldfire/intc-2.c
133
v = __raw_readb(MCFEPORT_EPDDR);
arch/m68k/coldfire/intc-2.c
134
__raw_writeb(v & ~(0x1 << irq), MCFEPORT_EPDDR);
arch/m68k/coldfire/intc-2.c
137
v = __raw_readb(MCFEPORT_EPIER);
arch/m68k/coldfire/intc-2.c
138
__raw_writeb(v | (0x1 << irq), MCFEPORT_EPIER);
arch/m68k/coldfire/intc-5272.c
100
v = 0xd << intc_irqmap[irq].index;
arch/m68k/coldfire/intc-5272.c
101
writel(v, intc_irqmap[irq].icr);
arch/m68k/coldfire/intc-5272.c
113
u32 v;
arch/m68k/coldfire/intc-5272.c
114
v = readl(intc_irqmap[irq].icr);
arch/m68k/coldfire/intc-5272.c
115
v &= (0x7 << intc_irqmap[irq].index);
arch/m68k/coldfire/intc-5272.c
116
v |= (0x8 << intc_irqmap[irq].index);
arch/m68k/coldfire/intc-5272.c
117
writel(v, intc_irqmap[irq].icr);
arch/m68k/coldfire/intc-5272.c
129
u32 v;
arch/m68k/coldfire/intc-5272.c
130
v = readl(MCFSIM_PITR);
arch/m68k/coldfire/intc-5272.c
132
v &= ~(0x1 << (32 - irq));
arch/m68k/coldfire/intc-5272.c
134
v |= (0x1 << (32 - irq));
arch/m68k/coldfire/intc-5272.c
135
writel(v, MCFSIM_PITR);
arch/m68k/coldfire/intc-5272.c
86
u32 v;
arch/m68k/coldfire/intc-5272.c
88
v = 0x8 << intc_irqmap[irq].index;
arch/m68k/coldfire/intc-5272.c
89
writel(v, intc_irqmap[irq].icr);
arch/m68k/coldfire/intc-5272.c
98
u32 v;
arch/m68k/coldfire/intc-simr.c
104
u8 v;
arch/m68k/coldfire/intc-simr.c
108
v = __raw_readb(MCFEPORT_EPDDR);
arch/m68k/coldfire/intc-simr.c
109
__raw_writeb(v & ~(0x1 << ebit), MCFEPORT_EPDDR);
arch/m68k/coldfire/intc-simr.c
113
v = __raw_readb(MCFEPORT_EPIER);
arch/m68k/coldfire/intc-simr.c
114
__raw_writeb(v | (0x1 << ebit), MCFEPORT_EPIER);
arch/m68k/coldfire/m520x.c
176
u8 v;
arch/m68k/coldfire/m520x.c
179
v = readb(MCF_GPIO_PAR_FEC);
arch/m68k/coldfire/m520x.c
180
writeb(v | 0xf0, MCF_GPIO_PAR_FEC);
arch/m68k/coldfire/m520x.c
182
v = readb(MCF_GPIO_PAR_FECI2C);
arch/m68k/coldfire/m520x.c
183
writeb(v | 0x0f, MCF_GPIO_PAR_FECI2C);
arch/m68k/coldfire/m5272.c
55
u32 v;
arch/m68k/coldfire/m5272.c
58
v = readl(MCFSIM_PBCNT);
arch/m68k/coldfire/m5272.c
59
v = (v & ~0x000000ff) | 0x00000055;
arch/m68k/coldfire/m5272.c
60
writel(v, MCFSIM_PBCNT);
arch/m68k/coldfire/m5272.c
62
v = readl(MCFSIM_PDCNT);
arch/m68k/coldfire/m5272.c
63
v = (v & ~0x000003fc) | 0x000002a8;
arch/m68k/coldfire/m5272.c
64
writel(v, MCFSIM_PDCNT);
arch/m68k/coldfire/m527x.c
112
u8 v;
arch/m68k/coldfire/m527x.c
116
v = readb(MCFGPIO_PAR_FECI2C);
arch/m68k/coldfire/m527x.c
117
writeb(v | 0xf0, MCFGPIO_PAR_FECI2C);
arch/m68k/coldfire/m527x.c
123
v = readb(MCFGPIO_PAR_FEC0HL);
arch/m68k/coldfire/m527x.c
124
writeb(v | 0xc0, MCFGPIO_PAR_FEC0HL);
arch/m68k/coldfire/m527x.c
129
v = readb(MCFGPIO_PAR_FEC1HL);
arch/m68k/coldfire/m527x.c
130
writeb(v | 0xc0, MCFGPIO_PAR_FEC1HL);
arch/m68k/coldfire/m53xx.c
198
u8 v;
arch/m68k/coldfire/m53xx.c
201
v = readb(MCFGPIO_PAR_FECI2C);
arch/m68k/coldfire/m53xx.c
202
v |= MCF_GPIO_PAR_FECI2C_PAR_MDC_EMDC |
arch/m68k/coldfire/m53xx.c
204
writeb(v, MCFGPIO_PAR_FECI2C);
arch/m68k/coldfire/m53xx.c
206
v = readb(MCFGPIO_PAR_FEC);
arch/m68k/coldfire/m53xx.c
207
v = MCF_GPIO_PAR_FEC_PAR_FEC_7W_FEC | MCF_GPIO_PAR_FEC_PAR_FEC_MII_FEC;
arch/m68k/coldfire/m53xx.c
208
writeb(v, MCFGPIO_PAR_FEC);
arch/m68k/include/asm/amigayle.h
64
#define gayle_outb(v,a) writeb( v, GAYLE_IO+(a)+(((a)&1)*GAYLE_ODD) )
arch/m68k/include/asm/amigayle.h
67
#define gayle_outw(v,a) writew( v, GAYLE_IO+(a) )
arch/m68k/include/asm/atariints.h
38
#define IRQ_VECTOR_TO_SOURCE(v) ((v) - ((v) < 0x20 ? 0x18 : (0x40-8)))
arch/m68k/include/asm/atomic.h
132
static inline void arch_atomic_inc(atomic_t *v)
arch/m68k/include/asm/atomic.h
134
__asm__ __volatile__("addql #1,%0" : "+m" (*v));
arch/m68k/include/asm/atomic.h
138
static inline void arch_atomic_dec(atomic_t *v)
arch/m68k/include/asm/atomic.h
140
__asm__ __volatile__("subql #1,%0" : "+m" (*v));
arch/m68k/include/asm/atomic.h
144
static inline int arch_atomic_dec_and_test(atomic_t *v)
arch/m68k/include/asm/atomic.h
147
__asm__ __volatile__("subql #1,%1; seq %0" : "=d" (c), "+m" (*v));
arch/m68k/include/asm/atomic.h
152
static inline int arch_atomic_dec_and_test_lt(atomic_t *v)
arch/m68k/include/asm/atomic.h
157
: "=d" (c), "=m" (*v)
arch/m68k/include/asm/atomic.h
158
: "m" (*v));
arch/m68k/include/asm/atomic.h
162
static inline int arch_atomic_inc_and_test(atomic_t *v)
arch/m68k/include/asm/atomic.h
165
__asm__ __volatile__("addql #1,%1; seq %0" : "=d" (c), "+m" (*v));
arch/m68k/include/asm/atomic.h
172
static inline int arch_atomic_cmpxchg(atomic_t *v, int old, int new)
arch/m68k/include/asm/atomic.h
178
prev = arch_atomic_read(v);
arch/m68k/include/asm/atomic.h
180
arch_atomic_set(v, new);
arch/m68k/include/asm/atomic.h
186
static inline int arch_atomic_xchg(atomic_t *v, int new)
arch/m68k/include/asm/atomic.h
19
#define arch_atomic_read(v) READ_ONCE((v)->counter)
arch/m68k/include/asm/atomic.h
192
prev = arch_atomic_read(v);
arch/m68k/include/asm/atomic.h
193
arch_atomic_set(v, new);
arch/m68k/include/asm/atomic.h
20
#define arch_atomic_set(v, i) WRITE_ONCE(((v)->counter), (i))
arch/m68k/include/asm/atomic.h
201
static inline int arch_atomic_sub_and_test(int i, atomic_t *v)
arch/m68k/include/asm/atomic.h
205
: "=d" (c), "+m" (*v)
arch/m68k/include/asm/atomic.h
211
static inline int arch_atomic_add_negative(int i, atomic_t *v)
arch/m68k/include/asm/atomic.h
215
: "=d" (c), "+m" (*v)
arch/m68k/include/asm/atomic.h
33
static inline void arch_atomic_##op(int i, atomic_t *v) \
arch/m68k/include/asm/atomic.h
35
__asm__ __volatile__(#asm_op "l %1,%0" : "+m" (*v) : ASM_DI (i));\
arch/m68k/include/asm/atomic.h
41
static inline int arch_atomic_##op##_return(int i, atomic_t *v) \
arch/m68k/include/asm/atomic.h
50
: "+m" (*v), "=&d" (t), "=&d" (tmp) \
arch/m68k/include/asm/atomic.h
51
: "di" (i), "2" (arch_atomic_read(v))); \
arch/m68k/include/asm/atomic.h
56
static inline int arch_atomic_fetch_##op(int i, atomic_t *v) \
arch/m68k/include/asm/atomic.h
65
: "+m" (*v), "=&d" (t), "=&d" (tmp) \
arch/m68k/include/asm/atomic.h
66
: "di" (i), "2" (arch_atomic_read(v))); \
arch/m68k/include/asm/atomic.h
73
static inline int arch_atomic_##op##_return(int i, atomic_t * v) \
arch/m68k/include/asm/atomic.h
79
t = (v->counter c_op i); \
arch/m68k/include/asm/atomic.h
86
static inline int arch_atomic_fetch_##op(int i, atomic_t * v) \
arch/m68k/include/asm/atomic.h
92
t = v->counter; \
arch/m68k/include/asm/atomic.h
93
v->counter c_op i; \
arch/m68k/include/asm/io_mm.h
264
#define isa_inb_p(p) ({u8 v=isa_inb(p);isa_delay();v;})
arch/m68k/include/asm/io_mm.h
265
#define isa_outb_p(v,p) ({isa_outb((v),(p));isa_delay();})
arch/m68k/include/asm/io_mm.h
266
#define isa_inw_p(p) ({u16 v=isa_inw(p);isa_delay();v;})
arch/m68k/include/asm/io_mm.h
267
#define isa_outw_p(v,p) ({isa_outw((v),(p));isa_delay();})
arch/m68k/include/asm/io_mm.h
268
#define isa_inl_p(p) ({u32 v=isa_inl(p);isa_delay();v;})
arch/m68k/include/asm/io_mm.h
269
#define isa_outl_p(v,p) ({isa_outl((v),(p));isa_delay();})
arch/m68k/include/asm/io_mm.h
294
#define isa_rom_outb_p(v, p) ({ isa_rom_outb((v), (p)); isa_delay(); })
arch/m68k/include/asm/io_mm.h
295
#define isa_rom_outw_p(v, p) ({ isa_rom_outw((v), (p)); isa_delay(); })
arch/m68k/include/asm/libgcc.h
12
#define umul_ppmm(w1, w0, u, v) \
arch/m68k/include/asm/libgcc.h
14
unsigned long __u = (u), __v = (v); \
arch/m68k/include/asm/mcfmmu.h
102
static inline void mmu_write(u32 a, u32 v)
arch/m68k/include/asm/mcfmmu.h
104
*((volatile u32 *) a) = v;
arch/m68k/include/uapi/asm/bootinfo.h
167
#define BI_VERSION_MAJOR(v) (((v) >> 16) & 0xffff)
arch/m68k/include/uapi/asm/bootinfo.h
168
#define BI_VERSION_MINOR(v) ((v) & 0xffff)
arch/m68k/kernel/setup_mm.c
376
static int show_cpuinfo(struct seq_file *m, void *v)
arch/m68k/kernel/setup_mm.c
462
static void *c_next(struct seq_file *m, void *v, loff_t *pos)
arch/m68k/kernel/setup_mm.c
467
static void c_stop(struct seq_file *m, void *v)
arch/m68k/kernel/setup_mm.c
478
static int hardware_proc_show(struct seq_file *m, void *v)
arch/m68k/kernel/setup_no.c
172
static int show_cpuinfo(struct seq_file *m, void *v)
arch/m68k/kernel/setup_no.c
203
static void *c_next(struct seq_file *m, void *v, loff_t *pos)
arch/m68k/kernel/setup_no.c
209
static void c_stop(struct seq_file *m, void *v)
arch/microblaze/include/asm/io.h
38
#define out_be32(a, v) __raw_writel((v), (void __iomem __force *)(a))
arch/microblaze/include/asm/io.h
39
#define out_be16(a, v) __raw_writew((v), (a))
arch/microblaze/include/asm/io.h
44
#define writel_be(v, a) out_be32((__force unsigned *)a, v)
arch/microblaze/include/asm/io.h
48
#define out_le32(a, v) __raw_writel(__cpu_to_le32(v), (a))
arch/microblaze/include/asm/io.h
49
#define out_le16(a, v) __raw_writew(__cpu_to_le16(v), (a))
arch/microblaze/include/asm/io.h
55
#define out_8(a, v) __raw_writeb((v), (a))
arch/microblaze/include/asm/mmu.h
19
unsigned long v:1; /* Entry is valid */
arch/microblaze/kernel/cpu/mb.c
143
static void *c_next(struct seq_file *m, void *v, loff_t *pos)
arch/microblaze/kernel/cpu/mb.c
149
static void c_stop(struct seq_file *m, void *v)
arch/microblaze/kernel/cpu/mb.c
28
static int show_cpuinfo(struct seq_file *m, void *v)
arch/microblaze/lib/libgcc.h
30
extern long long __muldi3(long long u, long long v);
arch/microblaze/lib/muldi3.c
14
#define umul_ppmm(w1, w0, u, v) \
arch/microblaze/lib/muldi3.c
21
__vl = __ll_lowpart(v); \
arch/microblaze/lib/muldi3.c
22
__vh = __ll_highpart(v); \
arch/microblaze/lib/muldi3.c
40
#define __umulsidi3(u, v) ({ \
arch/microblaze/lib/muldi3.c
42
umul_ppmm(__w.s.high, __w.s.low, u, v); \
arch/microblaze/lib/muldi3.c
47
long long __muldi3(long long u, long long v)
arch/microblaze/lib/muldi3.c
50
const DWunion vv = {.ll = v};
arch/microblaze/mm/pgtable.c
100
v = (unsigned long) area->addr;
arch/microblaze/mm/pgtable.c
102
v = (ioremap_bot -= size);
arch/microblaze/mm/pgtable.c
112
err = map_page(v + i, p + i, flags);
arch/microblaze/mm/pgtable.c
115
vfree((void *)v);
arch/microblaze/mm/pgtable.c
119
return (void __iomem *) (v + ((unsigned long)addr & ~PAGE_MASK));
arch/microblaze/mm/pgtable.c
168
unsigned long v, p, s, f;
arch/microblaze/mm/pgtable.c
170
v = CONFIG_KERNEL_START;
arch/microblaze/mm/pgtable.c
175
if (!is_kernel_text(v))
arch/microblaze/mm/pgtable.c
181
map_page(v, p, f);
arch/microblaze/mm/pgtable.c
182
v += PAGE_SIZE;
arch/microblaze/mm/pgtable.c
52
unsigned long v, i;
arch/mips/alchemy/common/clock.c
1018
v = alchemy_rdsys(a->reg);
arch/mips/alchemy/common/clock.c
1019
a->parent = ((v >> a->shift) >> 2) & 7;
arch/mips/alchemy/common/clock.c
279
unsigned long v = (alchemy_rdsys(AU1000_SYS_POWERCTRL) & 3) + 2;
arch/mips/alchemy/common/clock.c
283
pn, 0, 1, v);
arch/mips/alchemy/common/clock.c
308
unsigned long v;
arch/mips/alchemy/common/clock.c
315
v = __raw_readl(addr + AU1550_MEM_SDCONFIGB);
arch/mips/alchemy/common/clock.c
316
div = (v & (1 << 15)) ? 1 : 2;
arch/mips/alchemy/common/clock.c
319
v = __raw_readl(addr + AU1550_MEM_SDCONFIGB);
arch/mips/alchemy/common/clock.c
320
div = (v & (1 << 31)) ? 1 : 2;
arch/mips/alchemy/common/clock.c
349
unsigned long v = alchemy_rdsmem(AU1000_MEM_STCFG0);
arch/mips/alchemy/common/clock.c
354
v = 4 + ((v >> 11) & 1);
arch/mips/alchemy/common/clock.c
357
v = ((v >> 13) & 7) + 1;
arch/mips/alchemy/common/clock.c
360
pn, 0, 1, v);
arch/mips/alchemy/common/clock.c
498
unsigned long v, flags;
arch/mips/alchemy/common/clock.c
501
v = alchemy_rdsys(c->reg);
arch/mips/alchemy/common/clock.c
502
v |= (1 << 1) << c->shift;
arch/mips/alchemy/common/clock.c
503
alchemy_wrsys(v, c->reg);
arch/mips/alchemy/common/clock.c
512
unsigned long v = alchemy_rdsys(c->reg) >> (c->shift + 1);
arch/mips/alchemy/common/clock.c
514
return v & 1;
arch/mips/alchemy/common/clock.c
520
unsigned long v, flags;
arch/mips/alchemy/common/clock.c
523
v = alchemy_rdsys(c->reg);
arch/mips/alchemy/common/clock.c
524
v &= ~((1 << 1) << c->shift);
arch/mips/alchemy/common/clock.c
525
alchemy_wrsys(v, c->reg);
arch/mips/alchemy/common/clock.c
532
unsigned long v, flags;
arch/mips/alchemy/common/clock.c
535
v = alchemy_rdsys(c->reg);
arch/mips/alchemy/common/clock.c
537
v |= (1 << c->shift);
arch/mips/alchemy/common/clock.c
539
v &= ~(1 << c->shift);
arch/mips/alchemy/common/clock.c
540
alchemy_wrsys(v, c->reg);
arch/mips/alchemy/common/clock.c
557
unsigned long div, v, flags, ret;
arch/mips/alchemy/common/clock.c
564
v = alchemy_rdsys(c->reg);
arch/mips/alchemy/common/clock.c
565
v &= ~(0xff << sh);
arch/mips/alchemy/common/clock.c
566
v |= div << sh;
arch/mips/alchemy/common/clock.c
567
alchemy_wrsys(v, c->reg);
arch/mips/alchemy/common/clock.c
577
unsigned long v = alchemy_rdsys(c->reg) >> (c->shift + 2);
arch/mips/alchemy/common/clock.c
579
v = ((v & 0xff) + 1) * 2;
arch/mips/alchemy/common/clock.c
580
return parent_rate / v;
arch/mips/alchemy/common/clock.c
603
unsigned long v = alchemy_rdsys(c->reg);
arch/mips/alchemy/common/clock.c
605
v &= ~(3 << c->shift);
arch/mips/alchemy/common/clock.c
606
v |= (c->parent & 3) << c->shift;
arch/mips/alchemy/common/clock.c
607
alchemy_wrsys(v, c->reg);
arch/mips/alchemy/common/clock.c
634
unsigned long v, flags;
arch/mips/alchemy/common/clock.c
637
v = alchemy_rdsys(c->reg);
arch/mips/alchemy/common/clock.c
638
v &= ~(3 << c->shift); /* set input mux to "disabled" state */
arch/mips/alchemy/common/clock.c
639
alchemy_wrsys(v, c->reg);
arch/mips/alchemy/common/clock.c
661
unsigned long flags, v;
arch/mips/alchemy/common/clock.c
664
v = c->parent - 1;
arch/mips/alchemy/common/clock.c
666
return v;
arch/mips/alchemy/common/clock.c
679
unsigned long div, v, flags, ret;
arch/mips/alchemy/common/clock.c
684
v = alchemy_rdsys(c->reg) & (1 << 30); /* test "scale" bit */
arch/mips/alchemy/common/clock.c
685
ret = alchemy_calc_div(rate, parent_rate, v ? 1 : 2,
arch/mips/alchemy/common/clock.c
686
v ? 256 : 512, &div);
arch/mips/alchemy/common/clock.c
689
v = alchemy_rdsys(c->reg);
arch/mips/alchemy/common/clock.c
690
v &= ~(0xff << sh);
arch/mips/alchemy/common/clock.c
691
v |= (div & 0xff) << sh;
arch/mips/alchemy/common/clock.c
692
alchemy_wrsys(v, c->reg);
arch/mips/alchemy/common/clock.c
703
unsigned long v, t;
arch/mips/alchemy/common/clock.c
705
v = alchemy_rdsys(c->reg);
arch/mips/alchemy/common/clock.c
706
t = parent_rate / (((v >> sh) & 0xff) + 1);
arch/mips/alchemy/common/clock.c
707
if ((v & (1 << 30)) == 0) /* test scale bit */
arch/mips/alchemy/common/clock.c
759
unsigned long v;
arch/mips/alchemy/common/clock.c
800
v = alchemy_rdsys(a->reg);
arch/mips/alchemy/common/clock.c
801
a->parent = (v >> a->shift) & 3;
arch/mips/alchemy/common/clock.c
826
unsigned long v = alchemy_rdsys(c->reg);
arch/mips/alchemy/common/clock.c
828
return (((v >> c->shift) >> 2) & 7) != 0;
arch/mips/alchemy/common/clock.c
833
unsigned long v = alchemy_rdsys(c->reg);
arch/mips/alchemy/common/clock.c
835
v &= ~((7 << 2) << c->shift);
arch/mips/alchemy/common/clock.c
836
v |= ((c->parent & 7) << 2) << c->shift;
arch/mips/alchemy/common/clock.c
837
alchemy_wrsys(v, c->reg);
arch/mips/alchemy/common/clock.c
857
unsigned long v, flags;
arch/mips/alchemy/common/clock.c
860
v = alchemy_rdsys(c->reg);
arch/mips/alchemy/common/clock.c
861
v &= ~((3 << 2) << c->shift); /* mux to "disabled" state */
arch/mips/alchemy/common/clock.c
862
alchemy_wrsys(v, c->reg);
arch/mips/alchemy/common/clock.c
892
unsigned long v = (alchemy_rdsys(c->reg) >> c->shift) & 3;
arch/mips/alchemy/common/clock.c
894
return parent_rate / c->dt[v];
arch/mips/alchemy/common/clock.c
901
unsigned long d, v, flags;
arch/mips/alchemy/common/clock.c
921
v = alchemy_rdsys(c->reg);
arch/mips/alchemy/common/clock.c
922
v &= ~(3 << c->shift);
arch/mips/alchemy/common/clock.c
923
v |= (i & 3) << c->shift;
arch/mips/alchemy/common/clock.c
924
alchemy_wrsys(v, c->reg);
arch/mips/alchemy/common/clock.c
965
unsigned long v;
arch/mips/alchemy/common/gpiolib.c
126
static int alchemy_gpic_set(struct gpio_chip *chip, unsigned int off, int v)
arch/mips/alchemy/common/gpiolib.c
128
au1300_gpio_set_value(off + AU1300_GPIO_BASE, v);
arch/mips/alchemy/common/gpiolib.c
139
int v)
arch/mips/alchemy/common/gpiolib.c
141
return au1300_gpio_direction_output(off + AU1300_GPIO_BASE, v);
arch/mips/alchemy/devboards/bcsr.c
103
unsigned short v = 1 << (d->irq - bcsr_csc_base);
arch/mips/alchemy/devboards/bcsr.c
104
__raw_writew(v, bcsr_virt + BCSR_REG_MASKCLR);
arch/mips/alchemy/devboards/bcsr.c
110
unsigned short v = 1 << (d->irq - bcsr_csc_base);
arch/mips/alchemy/devboards/bcsr.c
111
__raw_writew(v, bcsr_virt + BCSR_REG_MASKCLR);
arch/mips/alchemy/devboards/bcsr.c
112
__raw_writew(v, bcsr_virt + BCSR_REG_INTSTAT); /* ack */
arch/mips/alchemy/devboards/bcsr.c
118
unsigned short v = 1 << (d->irq - bcsr_csc_base);
arch/mips/alchemy/devboards/bcsr.c
119
__raw_writew(v, bcsr_virt + BCSR_REG_MASKSET);
arch/mips/alchemy/devboards/db1550.c
36
unsigned long v;
arch/mips/alchemy/devboards/db1550.c
41
v = alchemy_rdsys(AU1000_SYS_PINFUNC);
arch/mips/alchemy/devboards/db1550.c
42
alchemy_wrsys(v | 1 | SYS_PF_PSC1_S1, AU1000_SYS_PINFUNC);
arch/mips/bcm63xx/gpio.c
42
u32 *v;
arch/mips/bcm63xx/gpio.c
50
v = &gpio_out_low;
arch/mips/bcm63xx/gpio.c
54
v = &gpio_out_high;
arch/mips/bcm63xx/gpio.c
59
*v |= mask;
arch/mips/bcm63xx/gpio.c
61
*v &= ~mask;
arch/mips/bcm63xx/gpio.c
62
bcm_gpio_writel(*v, reg);
arch/mips/boot/tools/relocs.c
558
static int write_reloc_as_bin(uint32_t v, FILE *f)
arch/mips/boot/tools/relocs.c
562
v = cpu_to_elf32(v);
arch/mips/boot/tools/relocs.c
564
memcpy(buf, &v, sizeof(uint32_t));
arch/mips/boot/tools/relocs.c
568
static int write_reloc_as_text(uint32_t v, FILE *f)
arch/mips/boot/tools/relocs.c
572
res = fprintf(f, "\t.long 0x%08"PRIx32"\n", v);
arch/mips/cavium-octeon/executive/cvmx-boot-vector.c
143
uint64_t v = _cvmx_bootvector_data[i];
arch/mips/cavium-octeon/executive/cvmx-boot-vector.c
146
v &= 0xffffffff00000000ull; /* KScratch not available */
arch/mips/cavium-octeon/executive/cvmx-boot-vector.c
148
cvmx_write_csr(CVMX_MIO_BOOT_LOC_DAT, v);
arch/mips/cavium-octeon/oct_ilm.c
31
static int oct_ilm_show(struct seq_file *m, void *v)
arch/mips/cavium-octeon/octeon-irq.c
1608
u32 v;
arch/mips/cavium-octeon/octeon-irq.c
1610
r = of_property_read_u32_index(gpio_node, "interrupts", 0, &v);
arch/mips/cavium-octeon/octeon-irq.c
1615
base_hwirq = v;
arch/mips/include/asm/atomic.h
107
arch_##pfx##_fetch_##op##_relaxed(type i, pfx##_t * v) \
arch/mips/include/asm/atomic.h
115
result = v->counter; \
arch/mips/include/asm/atomic.h
116
v->counter c_op i; \
arch/mips/include/asm/atomic.h
132
"+" GCC_OFF_SMALL_ASM() (v->counter) \
arch/mips/include/asm/atomic.h
197
static __inline__ type arch_##pfx##_sub_if_positive(type i, pfx##_t * v) \
arch/mips/include/asm/atomic.h
207
result = v->counter; \
arch/mips/include/asm/atomic.h
210
v->counter = result; \
arch/mips/include/asm/atomic.h
232
"+" GCC_OFF_SMALL_ASM() (v->counter) \
arch/mips/include/asm/atomic.h
249
#define arch_atomic_dec_if_positive(v) arch_atomic_sub_if_positive(1, v)
arch/mips/include/asm/atomic.h
253
#define arch_atomic64_dec_if_positive(v) arch_atomic64_sub_if_positive(1, v)
arch/mips/include/asm/atomic.h
27
static __always_inline type arch_##pfx##_read(const pfx##_t *v) \
arch/mips/include/asm/atomic.h
29
return READ_ONCE(v->counter); \
arch/mips/include/asm/atomic.h
32
static __always_inline void arch_##pfx##_set(pfx##_t *v, type i) \
arch/mips/include/asm/atomic.h
34
WRITE_ONCE(v->counter, i); \
arch/mips/include/asm/atomic.h
45
static __inline__ void arch_##pfx##_##op(type i, pfx##_t * v) \
arch/mips/include/asm/atomic.h
53
v->counter c_op i; \
arch/mips/include/asm/atomic.h
67
: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (v->counter) \
arch/mips/include/asm/atomic.h
73
arch_##pfx##_##op##_return_relaxed(type i, pfx##_t * v) \
arch/mips/include/asm/atomic.h
81
result = v->counter; \
arch/mips/include/asm/atomic.h
83
v->counter = result; \
arch/mips/include/asm/atomic.h
99
"+" GCC_OFF_SMALL_ASM() (v->counter) \
arch/mips/include/asm/cop2.h
49
extern int cu2_notifier_call_chain(unsigned long val, void *v);
arch/mips/include/asm/cpu-info.h
133
extern int proc_cpuinfo_notifier_call_chain(unsigned long val, void *v);
arch/mips/include/asm/dec/ioasic.h
20
static inline void ioasic_write(unsigned int reg, u32 v)
arch/mips/include/asm/dec/ioasic.h
22
ioasic_base[reg / 4] = v;
arch/mips/include/asm/io.h
489
#define csr_out32(v, a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST) = (v))
arch/mips/include/asm/kvm_host.h
752
const struct kvm_one_reg *reg, s64 *v);
arch/mips/include/asm/kvm_host.h
754
const struct kvm_one_reg *reg, s64 v);
arch/mips/include/asm/mach-au1x00/au1000.h
611
static inline void alchemy_wrsys(unsigned long v, int regofs)
arch/mips/include/asm/mach-au1x00/au1000.h
615
__raw_writel(v, b + regofs);
arch/mips/include/asm/mach-au1x00/au1000.h
627
static inline void alchemy_wrsmem(unsigned long v, int regofs)
arch/mips/include/asm/mach-au1x00/au1000.h
631
__raw_writel(v, b + regofs);
arch/mips/include/asm/mach-au1x00/gpio-au1000.h
218
static inline void alchemy_gpio1_set_value(int gpio, int v)
arch/mips/include/asm/mach-au1x00/gpio-au1000.h
221
unsigned long r = v ? AU1000_SYS_OUTPUTSET : AU1000_SYS_OUTPUTCLR;
arch/mips/include/asm/mach-au1x00/gpio-au1000.h
238
static inline int alchemy_gpio1_direction_output(int gpio, int v)
arch/mips/include/asm/mach-au1x00/gpio-au1000.h
243
alchemy_gpio1_set_value(gpio, v);
arch/mips/include/asm/mach-au1x00/gpio-au1000.h
298
static inline void alchemy_gpio2_set_value(int gpio, int v)
arch/mips/include/asm/mach-au1x00/gpio-au1000.h
302
mask = ((v) ? 0x00010001 : 0x00010000) << (gpio - ALCHEMY_GPIO2_BASE);
arch/mips/include/asm/mach-au1x00/gpio-au1000.h
323
static inline int alchemy_gpio2_direction_output(int gpio, int v)
arch/mips/include/asm/mach-au1x00/gpio-au1000.h
326
alchemy_gpio2_set_value(gpio, v);
arch/mips/include/asm/mach-au1x00/gpio-au1000.h
474
static inline int alchemy_gpio_direction_output(int gpio, int v)
arch/mips/include/asm/mach-au1x00/gpio-au1000.h
477
alchemy_gpio2_direction_output(gpio, v) :
arch/mips/include/asm/mach-au1x00/gpio-au1000.h
478
alchemy_gpio1_direction_output(gpio, v);
arch/mips/include/asm/mach-au1x00/gpio-au1000.h
488
static inline void alchemy_gpio_set_value(int gpio, int v)
arch/mips/include/asm/mach-au1x00/gpio-au1000.h
491
alchemy_gpio2_set_value(gpio, v);
arch/mips/include/asm/mach-au1x00/gpio-au1000.h
493
alchemy_gpio1_set_value(gpio, v);
arch/mips/include/asm/mach-au1x00/gpio-au1300.h
105
unsigned long v;
arch/mips/include/asm/mach-au1x00/gpio-au1300.h
114
v = __raw_readl(roff + AU1300_GPIC_RSTVAL);
arch/mips/include/asm/mach-au1x00/gpio-au1300.h
115
return (v >> gpio) & 1;
arch/mips/include/asm/mach-au1x00/gpio-au1300.h
55
static inline int au1300_gpio_set_value(unsigned int gpio, int v)
arch/mips/include/asm/mach-au1x00/gpio-au1300.h
64
__raw_writel(bit, roff + (v ? AU1300_GPIC_PINVAL
arch/mips/include/asm/mach-au1x00/gpio-au1300.h
71
static inline int au1300_gpio_direction_output(unsigned int gpio, int v)
arch/mips/include/asm/mach-au1x00/gpio-au1300.h
74
return au1300_gpio_set_value(gpio, v);
arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
100
#define bcm_ddr_writel(v, o) bcm_rset_writel(RSET_DDR, (v), (o))
arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
102
#define bcm_misc_writel(v, o) bcm_rset_writel(RSET_MISC, (v), (o))
arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
58
#define bcm_writeb(v, a) (*(volatile unsigned char *) BCM_REGS_VA((a)) = (v))
arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
59
#define bcm_writew(v, a) (*(volatile unsigned short *) BCM_REGS_VA((a)) = (v))
arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
60
#define bcm_writel(v, a) (*(volatile unsigned int *) BCM_REGS_VA((a)) = (v))
arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
61
#define bcm_writeq(v, a) (*(volatile u64 *) BCM_REGS_VA((a)) = (v))
arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
69
#define bcm_rset_writeb(s, v, o) bcm_writeb((v), \
arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
71
#define bcm_rset_writew(s, v, o) bcm_writew((v), \
arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
73
#define bcm_rset_writel(s, v, o) bcm_writel((v), \
arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
80
#define bcm_perf_writel(v, o) bcm_rset_writel(RSET_PERF, (v), (o))
arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
82
#define bcm_timer_writel(v, o) bcm_rset_writel(RSET_TIMER, (v), (o))
arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
84
#define bcm_wdt_writel(v, o) bcm_rset_writel(RSET_WDT, (v), (o))
arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
86
#define bcm_gpio_writel(v, o) bcm_rset_writel(RSET_GPIO, (v), (o))
arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
88
#define bcm_uart0_writel(v, o) bcm_rset_writel(RSET_UART0, (v), (o))
arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
90
#define bcm_mpi_writel(v, o) bcm_rset_writel(RSET_MPI, (v), (o))
arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
92
#define bcm_pcmcia_writel(v, o) bcm_rset_writel(RSET_PCMCIA, (v), (o))
arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
94
#define bcm_pcie_writel(v, o) bcm_rset_writel(RSET_PCIE, (v), (o))
arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
96
#define bcm_sdram_writel(v, o) bcm_rset_writel(RSET_SDRAM, (v), (o))
arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
98
#define bcm_memc_writel(v, o) bcm_rset_writel(RSET_MEMC, (v), (o))
arch/mips/include/asm/mipsmtregs.h
376
#define mttgpr(rs, v) \
arch/mips/include/asm/mipsmtregs.h
385
: : "r" (v)); \
arch/mips/include/asm/mipsmtregs.h
396
#define mttc0(rs, sel, v) \
arch/mips/include/asm/mipsmtregs.h
406
: "r" (v)); \
arch/mips/include/asm/mipsmtregs.h
410
#define mttr(rd, u, sel, v) \
arch/mips/include/asm/mipsmtregs.h
414
: : "r" (v)); \
arch/mips/include/asm/octeon/cvmx-mio-defs.h
3507
uint64_t v:1;
arch/mips/include/asm/octeon/cvmx-mio-defs.h
3531
uint64_t v:1;
arch/mips/include/asm/octeon/cvmx-mio-defs.h
3555
uint64_t v:2;
arch/mips/include/asm/octeon/cvmx-mio-defs.h
3561
uint64_t v:2;
arch/mips/include/asm/octeon/cvmx.h
90
#define CAST64(v) ((long long)(long)(v))
arch/mips/include/asm/octeon/cvmx.h
91
#define CASTPTR(type, v) ((type *)(long)(v))
arch/mips/include/asm/sibyte/sb1250_defs.h
222
#define _SB_MAKEMASK(v, n) (_SB_MAKE64((_SB_MAKE64(1)<<(v))-1) << _SB_MAKE64(n))
arch/mips/include/asm/sibyte/sb1250_defs.h
223
#define _SB_MAKEMASK_32(v, n) (_SB_MAKE32((_SB_MAKE32(1)<<(v))-1) << _SB_MAKE32(n))
arch/mips/include/asm/sibyte/sb1250_defs.h
229
#define _SB_MAKEVALUE(v, n) (_SB_MAKE64(v) << _SB_MAKE64(n))
arch/mips/include/asm/sibyte/sb1250_defs.h
230
#define _SB_MAKEVALUE_32(v, n) (_SB_MAKE32(v) << _SB_MAKE32(n))
arch/mips/include/asm/sibyte/sb1250_defs.h
232
#define _SB_GETVALUE(v, n, m) ((_SB_MAKE64(v) & _SB_MAKE64(m)) >> _SB_MAKE64(n))
arch/mips/include/asm/sibyte/sb1250_defs.h
233
#define _SB_GETVALUE_32(v, n, m) ((_SB_MAKE32(v) & _SB_MAKE32(m)) >> _SB_MAKE32(n))
arch/mips/include/asm/vga.h
45
static inline void scr_memsetw(u16 *s, u16 v, unsigned int count)
arch/mips/include/asm/vga.h
47
memset16(s, cpu_to_le16(v), count / 2);
arch/mips/include/asm/vpe.h
112
void release_vpe(struct vpe *v);
arch/mips/include/asm/vpe.h
117
int vpe_run(struct vpe *v);
arch/mips/kernel/module.c
106
*location = (*location & 0xffff0000) | (v & 0xffff);
arch/mips/kernel/module.c
122
if (v != l->value)
arch/mips/kernel/module.c
133
val += v;
arch/mips/kernel/module.c
155
val = v + vallo;
arch/mips/kernel/module.c
171
Elf_Addr v, unsigned int bits)
arch/mips/kernel/module.c
177
if (v % 4) {
arch/mips/kernel/module.c
187
offset += ((long)v - (long)location) >> 2;
arch/mips/kernel/module.c
202
Elf_Addr v)
arch/mips/kernel/module.c
204
return apply_r_mips_pc(me, location, base, v, 16);
arch/mips/kernel/module.c
208
Elf_Addr v)
arch/mips/kernel/module.c
210
return apply_r_mips_pc(me, location, base, v, 21);
arch/mips/kernel/module.c
214
Elf_Addr v)
arch/mips/kernel/module.c
216
return apply_r_mips_pc(me, location, base, v, 26);
arch/mips/kernel/module.c
219
static int apply_r_mips_64(u32 *location, Elf_Addr v, bool rela)
arch/mips/kernel/module.c
224
*(Elf_Addr *)location = v;
arch/mips/kernel/module.c
229
static int apply_r_mips_higher(u32 *location, Elf_Addr v, bool rela)
arch/mips/kernel/module.c
235
((((long long)v + 0x80008000LL) >> 32) & 0xffff);
arch/mips/kernel/module.c
240
static int apply_r_mips_highest(u32 *location, Elf_Addr v, bool rela)
arch/mips/kernel/module.c
246
((((long long)v + 0x800080008000LL) >> 48) & 0xffff);
arch/mips/kernel/module.c
269
Elf_Addr v, bool rela)
arch/mips/kernel/module.c
275
apply_r_mips_32(location, base, v);
arch/mips/kernel/module.c
278
return apply_r_mips_26(me, location, base, v);
arch/mips/kernel/module.c
280
return apply_r_mips_hi16(me, location, v, rela);
arch/mips/kernel/module.c
282
return apply_r_mips_lo16(me, location, base, v, rela);
arch/mips/kernel/module.c
284
return apply_r_mips_pc16(me, location, base, v);
arch/mips/kernel/module.c
286
return apply_r_mips_pc21(me, location, base, v);
arch/mips/kernel/module.c
288
return apply_r_mips_pc26(me, location, base, v);
arch/mips/kernel/module.c
290
return apply_r_mips_64(location, v, rela);
arch/mips/kernel/module.c
292
return apply_r_mips_higher(location, v, rela);
arch/mips/kernel/module.c
294
return apply_r_mips_highest(location, v, rela);
arch/mips/kernel/module.c
314
Elf_Addr v;
arch/mips/kernel/module.c
33
static void apply_r_mips_32(u32 *location, u32 base, Elf_Addr v)
arch/mips/kernel/module.c
344
v = sym->st_value + r.rela->r_addend;
arch/mips/kernel/module.c
348
v = sym->st_value;
arch/mips/kernel/module.c
35
*location = base + v;
arch/mips/kernel/module.c
353
err = reloc_handler(type, me, location, base, v, rela);
arch/mips/kernel/module.c
39
Elf_Addr v)
arch/mips/kernel/module.c
41
if (v % 4) {
arch/mips/kernel/module.c
47
if ((v & 0xf0000000) != (((unsigned long)location + 4) & 0xf0000000)) {
arch/mips/kernel/module.c
54
((base + (v >> 2)) & 0x03ffffff);
arch/mips/kernel/module.c
59
static int apply_r_mips_hi16(struct module *me, u32 *location, Elf_Addr v,
arch/mips/kernel/module.c
66
((((long long) v + 0x8000LL) >> 16) & 0xffff);
arch/mips/kernel/module.c
80
n->value = v;
arch/mips/kernel/module.c
99
u32 base, Elf_Addr v, bool rela)
arch/mips/kernel/perf_regs.c
42
long v;
arch/mips/kernel/perf_regs.c
46
v = regs->cp0_epc;
arch/mips/kernel/perf_regs.c
49
v = regs->regs[idx - PERF_REG_MIPS_R1 + 1];
arch/mips/kernel/perf_regs.c
52
v = regs->regs[idx - PERF_REG_MIPS_R28 + 28];
arch/mips/kernel/perf_regs.c
60
return (s64)v; /* Sign extend if 32-bit. */
arch/mips/kernel/pm.c
68
void *v)
arch/mips/kernel/proc.c
31
int proc_cpuinfo_notifier_call_chain(unsigned long val, void *v)
arch/mips/kernel/proc.c
316
static void *c_next(struct seq_file *m, void *v, loff_t *pos)
arch/mips/kernel/proc.c
322
static void c_stop(struct seq_file *m, void *v)
arch/mips/kernel/proc.c
33
return raw_notifier_call_chain(&proc_cpuinfo_chain, val, v);
arch/mips/kernel/proc.c
36
static int show_cpuinfo(struct seq_file *m, void *v)
arch/mips/kernel/proc.c
39
unsigned long n = (unsigned long) v - 1;
arch/mips/kernel/r4k-bugs64.c
188
long v, tmp;
arch/mips/kernel/r4k-bugs64.c
215
: "=r" (v), "=&r" (tmp)
arch/mips/kernel/r4k-bugs64.c
233
: "=r" (v), "=&r" (tmp)
arch/mips/kernel/r4k-bugs64.c
252
long v, w, tmp;
arch/mips/kernel/r4k-bugs64.c
286
: "=&r" (v), "=&r" (w), "=&r" (tmp)
arch/mips/kernel/r4k-bugs64.c
289
daddiu_bug = v != w;
arch/mips/kernel/r4k-bugs64.c
304
: "=&r" (v), "=&r" (w), "=&r" (tmp)
arch/mips/kernel/r4k-bugs64.c
307
if (v == w) {
arch/mips/kernel/relocate.c
463
unsigned long v, void *p)
arch/mips/kernel/segment.c
49
static int segments_show(struct seq_file *m, void *v)
arch/mips/kernel/smp-cps.c
214
int cl, c, v;
arch/mips/kernel/smp-cps.c
241
for (v = 0; v < min_t(int, core_vpes, NR_CPUS - nvpes); v++) {
arch/mips/kernel/smp-cps.c
242
cpu_set_cluster(&cpu_data[nvpes + v], cl);
arch/mips/kernel/smp-cps.c
243
cpu_set_core(&cpu_data[nvpes + v], c);
arch/mips/kernel/smp-cps.c
244
cpu_set_vpe_id(&cpu_data[nvpes + v], v);
arch/mips/kernel/smp-cps.c
255
for (v = 0; v < min_t(unsigned, nvpes, NR_CPUS); v++) {
arch/mips/kernel/smp-cps.c
256
set_cpu_possible(v, true);
arch/mips/kernel/smp-cps.c
257
set_cpu_present(v, true);
arch/mips/kernel/smp-cps.c
258
__cpu_number_map[v] = v;
arch/mips/kernel/smp-cps.c
259
__cpu_logical_map[v] = v;
arch/mips/kernel/smp-cps.c
368
int v;
arch/mips/kernel/smp-cps.c
372
for (v = 0; v < core_vpes; v++)
arch/mips/kernel/spram.c
169
unsigned int v;
arch/mips/kernel/spram.c
176
v = vp[0];
arch/mips/kernel/spram.c
177
if (v != TDAT)
arch/mips/kernel/spram.c
179
vp, TDAT, v);
arch/mips/kernel/spram.c
180
v = vp[1];
arch/mips/kernel/spram.c
181
if (v != ~TDAT)
arch/mips/kernel/spram.c
183
vp+1, ~TDAT, v);
arch/mips/kernel/traps.c
1257
int cu2_notifier_call_chain(unsigned long val, void *v)
arch/mips/kernel/traps.c
1259
return raw_notifier_call_chain(&cu2_chain, val, v);
arch/mips/kernel/traps.c
2507
void *v)
arch/mips/kernel/vpe-mt.c
140
list_for_each_entry(notifier, &v->notify, list)
arch/mips/kernel/vpe-mt.c
180
struct vpe *v;
arch/mips/kernel/vpe-mt.c
184
v = get_vpe(i);
arch/mips/kernel/vpe-mt.c
185
if (v != NULL) {
arch/mips/kernel/vpe-mt.c
186
v->state = VPE_STATE_INUSE;
arch/mips/kernel/vpe-mt.c
187
return v;
arch/mips/kernel/vpe-mt.c
197
struct vpe *v = vpe;
arch/mips/kernel/vpe-mt.c
199
v->__start = start;
arch/mips/kernel/vpe-mt.c
200
return vpe_run(v);
arch/mips/kernel/vpe-mt.c
207
struct vpe *v = vpe;
arch/mips/kernel/vpe-mt.c
213
t = list_entry(v->tc.next, struct tc, tc);
arch/mips/kernel/vpe-mt.c
228
struct vpe *v = vpe;
arch/mips/kernel/vpe-mt.c
232
t = list_entry(v->tc.next, struct tc, tc);
arch/mips/kernel/vpe-mt.c
251
v->state = VPE_STATE_UNUSED;
arch/mips/kernel/vpe-mt.c
26
int vpe_run(struct vpe *v)
arch/mips/kernel/vpe-mt.c
329
struct vpe *v = NULL;
arch/mips/kernel/vpe-mt.c
410
v = alloc_vpe(tc);
arch/mips/kernel/vpe-mt.c
411
if (v == NULL) {
arch/mips/kernel/vpe-mt.c
416
v->ntcs = hw_tcs - aprp_cpu_index();
arch/mips/kernel/vpe-mt.c
419
list_add(&t->tc, &v->tc);
arch/mips/kernel/vpe-mt.c
446
t->pvpe = v; /* set the parent vpe */
arch/mips/kernel/vpe-mt.c
46
if (list_empty(&v->tc)) {
arch/mips/kernel/vpe-mt.c
508
struct vpe *v, *n;
arch/mips/kernel/vpe-mt.c
515
list_for_each_entry_safe(v, n, &vpecontrol.vpe_list, list) {
arch/mips/kernel/vpe-mt.c
516
if (v->state != VPE_STATE_UNUSED)
arch/mips/kernel/vpe-mt.c
517
release_vpe(v);
arch/mips/kernel/vpe-mt.c
52
v->minor);
arch/mips/kernel/vpe-mt.c
57
t = list_first_entry(&v->tc, struct tc, tc);
arch/mips/kernel/vpe-mt.c
81
write_tc_c0_tcrestart((unsigned long)v->__start);
arch/mips/kernel/vpe-mt.c
99
mttgpr($6, v->ntcs);
arch/mips/kernel/vpe.c
101
INIT_LIST_HEAD(&v->tc);
arch/mips/kernel/vpe.c
103
list_add_tail(&v->list, &vpecontrol.vpe_list);
arch/mips/kernel/vpe.c
106
INIT_LIST_HEAD(&v->notify);
arch/mips/kernel/vpe.c
107
v->minor = VPE_MODULE_MINOR;
arch/mips/kernel/vpe.c
110
return v;
arch/mips/kernel/vpe.c
134
void release_vpe(struct vpe *v)
arch/mips/kernel/vpe.c
136
list_del(&v->list);
arch/mips/kernel/vpe.c
137
if (v->load_addr)
arch/mips/kernel/vpe.c
138
release_progmem(v->load_addr);
arch/mips/kernel/vpe.c
139
kfree(v);
arch/mips/kernel/vpe.c
229
Elf32_Addr v)
arch/mips/kernel/vpe.c
235
Elf32_Addr v)
arch/mips/kernel/vpe.c
240
rel = (int)v - gp_addr;
arch/mips/kernel/vpe.c
244
rel = (int)(short)((int)v + gp_offs +
arch/mips/kernel/vpe.c
260
Elf32_Addr v)
arch/mips/kernel/vpe.c
263
rel = (((unsigned int)v - (unsigned int)location));
arch/mips/kernel/vpe.c
279
Elf32_Addr v)
arch/mips/kernel/vpe.c
281
*location += v;
arch/mips/kernel/vpe.c
287
Elf32_Addr v)
arch/mips/kernel/vpe.c
289
if (v % 4) {
arch/mips/kernel/vpe.c
307
((*location + (v >> 2)) & 0x03ffffff);
arch/mips/kernel/vpe.c
312
Elf32_Addr v)
arch/mips/kernel/vpe.c
326
n->value = v;
arch/mips/kernel/vpe.c
334
Elf32_Addr v)
arch/mips/kernel/vpe.c
352
if (v != l->value) {
arch/mips/kernel/vpe.c
365
val += v;
arch/mips/kernel/vpe.c
387
val = v + vallo;
arch/mips/kernel/vpe.c
405
Elf32_Addr v) = {
arch/mips/kernel/vpe.c
435
Elf32_Addr v;
arch/mips/kernel/vpe.c
454
v = sym->st_value;
arch/mips/kernel/vpe.c
456
res = reloc_handlers[ELF32_R_TYPE(r_info)](me, location, v);
arch/mips/kernel/vpe.c
550
static int find_vpe_symbols(struct vpe *v, Elf_Shdr *sechdrs,
arch/mips/kernel/vpe.c
559
v->__start = sym[i].st_value;
arch/mips/kernel/vpe.c
56
struct vpe *res, *v;
arch/mips/kernel/vpe.c
562
v->shared_ptr = (void *)sym[i].st_value;
arch/mips/kernel/vpe.c
565
if ((v->__start == 0) || (v->shared_ptr == NULL))
arch/mips/kernel/vpe.c
576
static int vpe_elfload(struct vpe *v)
arch/mips/kernel/vpe.c
588
hdr = (Elf_Ehdr *) v->pbuffer;
arch/mips/kernel/vpe.c
589
len = v->plen;
arch/mips/kernel/vpe.c
63
list_for_each_entry(v, &vpecontrol.vpe_list, list) {
arch/mips/kernel/vpe.c
64
if (v->minor == VPE_MODULE_MINOR) {
arch/mips/kernel/vpe.c
644
v->load_addr = alloc_progmem(mod.mem[MOD_TEXT].size);
arch/mips/kernel/vpe.c
645
if (!v->load_addr)
arch/mips/kernel/vpe.c
648
pr_info("VPE loader: loading to %p\n", v->load_addr);
arch/mips/kernel/vpe.c
65
res = v;
arch/mips/kernel/vpe.c
657
dest = v->load_addr + sechdrs[i].sh_entsize;
arch/mips/kernel/vpe.c
731
flush_icache_range((unsigned long)v->load_addr,
arch/mips/kernel/vpe.c
732
(unsigned long)v->load_addr + v->len);
arch/mips/kernel/vpe.c
734
if ((find_vpe_symbols(v, sechdrs, symindex, strtab, &mod)) < 0) {
arch/mips/kernel/vpe.c
735
if (v->__start == 0) {
arch/mips/kernel/vpe.c
740
if (v->shared_ptr == NULL)
arch/mips/kernel/vpe.c
754
struct vpe *v;
arch/mips/kernel/vpe.c
763
v = get_vpe(aprp_cpu_index());
arch/mips/kernel/vpe.c
764
if (v == NULL) {
arch/mips/kernel/vpe.c
770
state = xchg(&v->state, VPE_STATE_INUSE);
arch/mips/kernel/vpe.c
774
list_for_each_entry(notifier, &v->notify, list)
arch/mips/kernel/vpe.c
777
release_progmem(v->load_addr);
arch/mips/kernel/vpe.c
782
v->pbuffer = vmalloc(P_SIZE);
arch/mips/kernel/vpe.c
783
if (!v->pbuffer) {
arch/mips/kernel/vpe.c
787
v->plen = P_SIZE;
arch/mips/kernel/vpe.c
788
v->load_addr = NULL;
arch/mips/kernel/vpe.c
789
v->len = 0;
arch/mips/kernel/vpe.c
790
v->shared_ptr = NULL;
arch/mips/kernel/vpe.c
791
v->__start = 0;
arch/mips/kernel/vpe.c
799
struct vpe *v;
arch/mips/kernel/vpe.c
803
v = get_vpe(aprp_cpu_index());
arch/mips/kernel/vpe.c
804
if (v == NULL)
arch/mips/kernel/vpe.c
807
hdr = (Elf_Ehdr *) v->pbuffer;
arch/mips/kernel/vpe.c
809
if (vpe_elfload(v) >= 0) {
arch/mips/kernel/vpe.c
810
vpe_run(v);
arch/mips/kernel/vpe.c
826
v->shared_ptr = NULL;
arch/mips/kernel/vpe.c
828
vfree(v->pbuffer);
arch/mips/kernel/vpe.c
829
v->plen = 0;
arch/mips/kernel/vpe.c
842
struct vpe *v;
arch/mips/kernel/vpe.c
847
v = get_vpe(aprp_cpu_index());
arch/mips/kernel/vpe.c
849
if (v == NULL)
arch/mips/kernel/vpe.c
852
if ((count + v->len) > v->plen) {
arch/mips/kernel/vpe.c
857
count -= copy_from_user(v->pbuffer + v->len, buffer, count);
arch/mips/kernel/vpe.c
861
v->len += count;
arch/mips/kernel/vpe.c
875
struct vpe *v = get_vpe(index);
arch/mips/kernel/vpe.c
877
if (v == NULL)
arch/mips/kernel/vpe.c
880
return v->shared_ptr;
arch/mips/kernel/vpe.c
886
struct vpe *v = get_vpe(index);
arch/mips/kernel/vpe.c
888
if (v == NULL)
arch/mips/kernel/vpe.c
891
list_add(¬ify->list, &v->notify);
arch/mips/kernel/vpe.c
95
struct vpe *v;
arch/mips/kernel/vpe.c
97
v = kzalloc_obj(struct vpe);
arch/mips/kernel/vpe.c
98
if (v == NULL)
arch/mips/kvm/mips.c
652
s64 v;
arch/mips/kvm/mips.c
659
v = (long)vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0];
arch/mips/kvm/mips.c
663
v = (long)vcpu->arch.hi;
arch/mips/kvm/mips.c
666
v = (long)vcpu->arch.lo;
arch/mips/kvm/mips.c
670
v = (long)vcpu->arch.pc;
arch/mips/kvm/mips.c
680
v = get_fpr32(&fpu->fpr[idx], 0);
arch/mips/kvm/mips.c
682
v = get_fpr32(&fpu->fpr[idx & ~1], idx & 1);
arch/mips/kvm/mips.c
691
v = get_fpr64(&fpu->fpr[idx], 0);
arch/mips/kvm/mips.c
696
v = boot_cpu_data.fpu_id;
arch/mips/kvm/mips.c
701
v = fpu->fcr31;
arch/mips/kvm/mips.c
725
v = boot_cpu_data.msa_id;
arch/mips/kvm/mips.c
730
v = fpu->msacsr;
arch/mips/kvm/mips.c
735
ret = kvm_mips_callbacks->get_one_reg(vcpu, reg, &v);
arch/mips/kvm/mips.c
743
return put_user(v, uaddr64);
arch/mips/kvm/mips.c
746
u32 v32 = (u32)v;
arch/mips/kvm/mips.c
763
s64 v;
arch/mips/kvm/mips.c
770
if (get_user(v, uaddr64) != 0)
arch/mips/kvm/mips.c
778
v = (s64)v32;
arch/mips/kvm/mips.c
793
vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0] = v;
arch/mips/kvm/mips.c
797
vcpu->arch.hi = v;
arch/mips/kvm/mips.c
800
vcpu->arch.lo = v;
arch/mips/kvm/mips.c
804
vcpu->arch.pc = v;
arch/mips/kvm/mips.c
814
set_fpr32(&fpu->fpr[idx], 0, v);
arch/mips/kvm/mips.c
816
set_fpr32(&fpu->fpr[idx & ~1], idx & 1, v);
arch/mips/kvm/mips.c
825
set_fpr64(&fpu->fpr[idx], 0, v);
arch/mips/kvm/mips.c
835
fpu->fcr31 = v;
arch/mips/kvm/mips.c
861
fpu->msacsr = v;
arch/mips/kvm/mips.c
866
return kvm_mips_callbacks->set_one_reg(vcpu, reg, v);
arch/mips/kvm/vz.c
1878
static inline s64 entrylo_kvm_to_user(unsigned long v)
arch/mips/kvm/vz.c
1880
s64 mask, ret = v;
arch/mips/kvm/vz.c
1889
ret |= ((s64)v & mask) << 32;
arch/mips/kvm/vz.c
1894
static inline unsigned long entrylo_user_to_kvm(s64 v)
arch/mips/kvm/vz.c
1896
unsigned long mask, ret = v;
arch/mips/kvm/vz.c
1905
ret |= (v >> 32) & mask;
arch/mips/kvm/vz.c
1912
s64 *v)
arch/mips/kvm/vz.c
1919
*v = (long)read_gc0_index();
arch/mips/kvm/vz.c
1922
*v = entrylo_kvm_to_user(read_gc0_entrylo0());
arch/mips/kvm/vz.c
1925
*v = entrylo_kvm_to_user(read_gc0_entrylo1());
arch/mips/kvm/vz.c
1928
*v = (long)read_gc0_context();
arch/mips/kvm/vz.c
1933
*v = read_gc0_contextconfig();
arch/mips/kvm/vz.c
1938
*v = read_gc0_userlocal();
arch/mips/kvm/vz.c
1944
*v = read_gc0_xcontextconfig();
arch/mips/kvm/vz.c
1948
*v = (long)read_gc0_pagemask();
arch/mips/kvm/vz.c
1951
*v = (long)read_gc0_pagegrain();
arch/mips/kvm/vz.c
1956
*v = read_gc0_segctl0();
arch/mips/kvm/vz.c
1961
*v = read_gc0_segctl1();
arch/mips/kvm/vz.c
1966
*v = read_gc0_segctl2();
arch/mips/kvm/vz.c
1971
*v = read_gc0_pwbase();
arch/mips/kvm/vz.c
1976
*v = read_gc0_pwfield();
arch/mips/kvm/vz.c
1981
*v = read_gc0_pwsize();
arch/mips/kvm/vz.c
1984
*v = (long)read_gc0_wired();
arch/mips/kvm/vz.c
1989
*v = read_gc0_pwctl();
arch/mips/kvm/vz.c
1992
*v = (long)read_gc0_hwrena();
arch/mips/kvm/vz.c
1995
*v = (long)read_gc0_badvaddr();
arch/mips/kvm/vz.c
2000
*v = read_gc0_badinstr();
arch/mips/kvm/vz.c
2005
*v = read_gc0_badinstrp();
arch/mips/kvm/vz.c
2008
*v = kvm_mips_read_count(vcpu);
arch/mips/kvm/vz.c
2011
*v = (long)read_gc0_entryhi();
arch/mips/kvm/vz.c
2014
*v = (long)read_gc0_compare();
arch/mips/kvm/vz.c
2017
*v = (long)read_gc0_status();
arch/mips/kvm/vz.c
2020
*v = read_gc0_intctl();
arch/mips/kvm/vz.c
2023
*v = (long)read_gc0_cause();
arch/mips/kvm/vz.c
2026
*v = (long)read_gc0_epc();
arch/mips/kvm/vz.c
2032
*v = read_gc0_prid();
arch/mips/kvm/vz.c
2035
*v = (long)kvm_read_c0_guest_prid(cop0);
arch/mips/kvm/vz.c
2040
*v = kvm_vz_read_gc0_ebase();
arch/mips/kvm/vz.c
2043
*v = read_gc0_config();
arch/mips/kvm/vz.c
2048
*v = read_gc0_config1();
arch/mips/kvm/vz.c
2053
*v = read_gc0_config2();
arch/mips/kvm/vz.c
2058
*v = read_gc0_config3();
arch/mips/kvm/vz.c
2063
*v = read_gc0_config4();
arch/mips/kvm/vz.c
2068
*v = read_gc0_config5();
arch/mips/kvm/vz.c
2071
*v = kvm_read_sw_gc0_config6(cop0);
arch/mips/kvm/vz.c
2079
*v = vcpu->arch.maar[idx];
arch/mips/kvm/vz.c
2084
*v = kvm_read_sw_gc0_maari(&vcpu->arch.cop0);
arch/mips/kvm/vz.c
2088
*v = read_gc0_xcontext();
arch/mips/kvm/vz.c
2092
*v = (long)read_gc0_errorepc();
arch/mips/kvm/vz.c
2100
*v = (long)read_gc0_kscratch1();
arch/mips/kvm/vz.c
2103
*v = (long)read_gc0_kscratch2();
arch/mips/kvm/vz.c
2106
*v = (long)read_gc0_kscratch3();
arch/mips/kvm/vz.c
2109
*v = (long)read_gc0_kscratch4();
arch/mips/kvm/vz.c
2112
*v = (long)read_gc0_kscratch5();
arch/mips/kvm/vz.c
2115
*v = (long)read_gc0_kscratch6();
arch/mips/kvm/vz.c
2120
*v = vcpu->arch.count_ctl;
arch/mips/kvm/vz.c
2123
*v = ktime_to_ns(vcpu->arch.count_resume);
arch/mips/kvm/vz.c
2126
*v = vcpu->arch.count_hz;
arch/mips/kvm/vz.c
2136
s64 v)
arch/mips/kvm/vz.c
2145
write_gc0_index(v);
arch/mips/kvm/vz.c
2148
write_gc0_entrylo0(entrylo_user_to_kvm(v));
arch/mips/kvm/vz.c
2151
write_gc0_entrylo1(entrylo_user_to_kvm(v));
arch/mips/kvm/vz.c
2154
write_gc0_context(v);
arch/mips/kvm/vz.c
2159
write_gc0_contextconfig(v);
arch/mips/kvm/vz.c
2164
write_gc0_userlocal(v);
arch/mips/kvm/vz.c
2170
write_gc0_xcontextconfig(v);
arch/mips/kvm/vz.c
2174
write_gc0_pagemask(v);
arch/mips/kvm/vz.c
2177
write_gc0_pagegrain(v);
arch/mips/kvm/vz.c
2182
write_gc0_segctl0(v);
arch/mips/kvm/vz.c
2187
write_gc0_segctl1(v);
arch/mips/kvm/vz.c
2192
write_gc0_segctl2(v);
arch/mips/kvm/vz.c
2197
write_gc0_pwbase(v);
arch/mips/kvm/vz.c
2202
write_gc0_pwfield(v);
arch/mips/kvm/vz.c
2207
write_gc0_pwsize(v);
arch/mips/kvm/vz.c
2210
change_gc0_wired(MIPSR6_WIRED_WIRED, v);
arch/mips/kvm/vz.c
2215
write_gc0_pwctl(v);
arch/mips/kvm/vz.c
2218
write_gc0_hwrena(v);
arch/mips/kvm/vz.c
2221
write_gc0_badvaddr(v);
arch/mips/kvm/vz.c
2226
write_gc0_badinstr(v);
arch/mips/kvm/vz.c
2231
write_gc0_badinstrp(v);
arch/mips/kvm/vz.c
2234
kvm_mips_write_count(vcpu, v);
arch/mips/kvm/vz.c
2237
write_gc0_entryhi(v);
arch/mips/kvm/vz.c
2240
kvm_mips_write_compare(vcpu, v, false);
arch/mips/kvm/vz.c
2243
write_gc0_status(v);
arch/mips/kvm/vz.c
2246
write_gc0_intctl(v);
arch/mips/kvm/vz.c
2254
if ((read_gc0_cause() ^ v) & CAUSEF_DC) {
arch/mips/kvm/vz.c
2255
if (v & CAUSEF_DC) {
arch/mips/kvm/vz.c
2258
change_gc0_cause((u32)~CAUSEF_DC, v);
arch/mips/kvm/vz.c
2261
change_gc0_cause((u32)~CAUSEF_DC, v);
arch/mips/kvm/vz.c
2265
write_gc0_cause(v);
arch/mips/kvm/vz.c
2269
write_gc0_epc(v);
arch/mips/kvm/vz.c
2277
kvm_write_c0_guest_prid(cop0, v);
arch/mips/kvm/vz.c
2282
kvm_vz_write_gc0_ebase(v);
arch/mips/kvm/vz.c
2286
change = (cur ^ v) & kvm_vz_config_user_wrmask(vcpu);
arch/mips/kvm/vz.c
2288
v = cur ^ change;
arch/mips/kvm/vz.c
2289
write_gc0_config(v);
arch/mips/kvm/vz.c
2296
change = (cur ^ v) & kvm_vz_config1_user_wrmask(vcpu);
arch/mips/kvm/vz.c
2298
v = cur ^ change;
arch/mips/kvm/vz.c
2299
write_gc0_config1(v);
arch/mips/kvm/vz.c
2306
change = (cur ^ v) & kvm_vz_config2_user_wrmask(vcpu);
arch/mips/kvm/vz.c
2308
v = cur ^ change;
arch/mips/kvm/vz.c
2309
write_gc0_config2(v);
arch/mips/kvm/vz.c
2316
change = (cur ^ v) & kvm_vz_config3_user_wrmask(vcpu);
arch/mips/kvm/vz.c
2318
v = cur ^ change;
arch/mips/kvm/vz.c
2319
write_gc0_config3(v);
arch/mips/kvm/vz.c
2326
change = (cur ^ v) & kvm_vz_config4_user_wrmask(vcpu);
arch/mips/kvm/vz.c
2328
v = cur ^ change;
arch/mips/kvm/vz.c
2329
write_gc0_config4(v);
arch/mips/kvm/vz.c
2336
change = (cur ^ v) & kvm_vz_config5_user_wrmask(vcpu);
arch/mips/kvm/vz.c
2338
v = cur ^ change;
arch/mips/kvm/vz.c
2339
write_gc0_config5(v);
arch/mips/kvm/vz.c
2344
change = (cur ^ v) & kvm_vz_config6_user_wrmask(vcpu);
arch/mips/kvm/vz.c
2346
v = cur ^ change;
arch/mips/kvm/vz.c
2347
kvm_write_sw_gc0_config6(cop0, (int)v);
arch/mips/kvm/vz.c
2356
vcpu->arch.maar[idx] = mips_process_maar(dmtc_op, v);
arch/mips/kvm/vz.c
2361
kvm_write_maari(vcpu, v);
arch/mips/kvm/vz.c
2365
write_gc0_xcontext(v);
arch/mips/kvm/vz.c
2369
write_gc0_errorepc(v);
arch/mips/kvm/vz.c
2377
write_gc0_kscratch1(v);
arch/mips/kvm/vz.c
2380
write_gc0_kscratch2(v);
arch/mips/kvm/vz.c
2383
write_gc0_kscratch3(v);
arch/mips/kvm/vz.c
2386
write_gc0_kscratch4(v);
arch/mips/kvm/vz.c
2389
write_gc0_kscratch5(v);
arch/mips/kvm/vz.c
2392
write_gc0_kscratch6(v);
arch/mips/kvm/vz.c
2397
ret = kvm_mips_set_count_ctl(vcpu, v);
arch/mips/kvm/vz.c
2400
ret = kvm_mips_set_count_resume(vcpu, v);
arch/mips/kvm/vz.c
2403
ret = kvm_mips_set_count_hz(vcpu, v);
arch/mips/kvm/vz.c
57
static inline void kvm_vz_write_gc0_ebase(long v)
arch/mips/kvm/vz.c
66
write_gc0_ebase_64(v | MIPS_EBASE_WG);
arch/mips/kvm/vz.c
67
write_gc0_ebase_64(v);
arch/mips/kvm/vz.c
69
write_gc0_ebase(v | MIPS_EBASE_WG);
arch/mips/kvm/vz.c
70
write_gc0_ebase(v);
arch/mips/math-emu/dsemul.c
233
s32 v;
arch/mips/math-emu/dsemul.c
236
v = regs->cp0_epc & ~3;
arch/mips/math-emu/dsemul.c
237
v += insn.mm_a_format.simmediate << 2;
arch/mips/math-emu/dsemul.c
238
regs->regs[rs] = (long)v;
arch/mips/math-emu/ieee754dp.h
37
#define XDPSRS(v,rs) \
arch/mips/math-emu/ieee754dp.h
38
((rs > (DP_FBITS+3))?1:((v) >> (rs)) | ((v) << (64-(rs)) != 0))
arch/mips/math-emu/ieee754dp.h
43
#define XDPSRS1(v) \
arch/mips/math-emu/ieee754dp.h
44
(((v) >> 1) | ((v) & 1))
arch/mips/math-emu/ieee754int.h
120
#define FLUSHDP(v, vc, vs, ve, vm) \
arch/mips/math-emu/ieee754int.h
127
v = ieee754dp_zero(vs); \
arch/mips/math-emu/ieee754int.h
131
#define FLUSHSP(v, vc, vs, ve, vm) \
arch/mips/math-emu/ieee754int.h
138
v = ieee754sp_zero(vs); \
arch/mips/math-emu/ieee754int.h
54
#define EXPLODESP(v, vc, vs, ve, vm) \
arch/mips/math-emu/ieee754int.h
56
vs = SPSIGN(v); \
arch/mips/math-emu/ieee754int.h
57
ve = SPBEXP(v); \
arch/mips/math-emu/ieee754int.h
58
vm = SPMANT(v); \
arch/mips/math-emu/ieee754int.h
92
#define EXPLODEDP(v, vc, vs, ve, vm) \
arch/mips/math-emu/ieee754int.h
94
vm = DPMANT(v); \
arch/mips/math-emu/ieee754int.h
95
vs = DPSIGN(v); \
arch/mips/math-emu/ieee754int.h
96
ve = DPBEXP(v); \
arch/mips/math-emu/ieee754sp.h
37
#define XSPSRS64(v, rs) \
arch/mips/math-emu/ieee754sp.h
38
(((rs) >= 64) ? ((v) != 0) : ((v) >> (rs)) | ((v) << (64-(rs)) != 0))
arch/mips/math-emu/ieee754sp.h
41
#define XSPSRS(v, rs) \
arch/mips/math-emu/ieee754sp.h
42
((rs > (SP_FBITS+3))?1:((v) >> (rs)) | ((v) << (32-(rs)) != 0))
arch/mips/mm/c-r4k.c
1811
void *v)
arch/mips/mm/tlb-r4k.c
526
static inline void write_c0_entryhi_native(unsigned long long v)
arch/mips/mm/tlb-r4k.c
529
write_c0_entryhi_64(v);
arch/mips/mm/tlb-r4k.c
531
write_c0_entryhi(v);
arch/mips/mm/tlb-r4k.c
842
void *v)
arch/mips/net/bpf_jit_comp32.c
791
static s64 jit_xchg64(s64 a, atomic64_t *v)
arch/mips/net/bpf_jit_comp32.c
793
return atomic64_xchg(v, a);
arch/mips/pic32/pic32mzda/config.c
27
u32 v;
arch/mips/pic32/pic32mzda/config.c
29
v = readl(pic32_conf_base + offset);
arch/mips/pic32/pic32mzda/config.c
30
v >>= rshift;
arch/mips/pic32/pic32mzda/config.c
31
v &= mask;
arch/mips/pic32/pic32mzda/config.c
33
return v;
arch/mips/pic32/pic32mzda/config.c
38
u32 v;
arch/mips/pic32/pic32mzda/config.c
42
v = readl(pic32_conf_base + offset);
arch/mips/pic32/pic32mzda/config.c
43
v &= ~mask;
arch/mips/pic32/pic32mzda/config.c
44
v |= (set & mask);
arch/mips/pic32/pic32mzda/config.c
45
writel(v, pic32_conf_base + offset);
arch/mips/sibyte/common/bus_watcher.c
100
static int bw_proc_show(struct seq_file *m, void *v)
arch/mips/txx9/rbtx4927/irq.c
132
unsigned char v;
arch/mips/txx9/rbtx4927/irq.c
134
v = readb(rbtx4927_imask_addr);
arch/mips/txx9/rbtx4927/irq.c
135
v |= (1 << (d->irq - RBTX4927_IRQ_IOC));
arch/mips/txx9/rbtx4927/irq.c
136
writeb(v, rbtx4927_imask_addr);
arch/mips/txx9/rbtx4927/irq.c
141
unsigned char v;
arch/mips/txx9/rbtx4927/irq.c
143
v = readb(rbtx4927_imask_addr);
arch/mips/txx9/rbtx4927/irq.c
144
v &= ~(1 << (d->irq - RBTX4927_IRQ_IOC));
arch/mips/txx9/rbtx4927/irq.c
145
writeb(v, rbtx4927_imask_addr);
arch/nios2/include/asm/registers.h
33
#define WRCTL(r, v) __builtin_wrctl(r, v)
arch/nios2/kernel/cpuinfo.c
116
static int show_cpuinfo(struct seq_file *m, void *v)
arch/nios2/kernel/cpuinfo.c
175
static void *cpuinfo_next(struct seq_file *m, void *v, loff_t *pos)
arch/nios2/kernel/cpuinfo.c
181
static void cpuinfo_stop(struct seq_file *m, void *v)
arch/nios2/kernel/module.c
44
uint32_t v = sym->st_value + rela[i].r_addend;
arch/nios2/kernel/module.c
54
*loc += v;
arch/nios2/kernel/module.c
57
v -= (uint32_t)loc + 4;
arch/nios2/kernel/module.c
58
if ((int32_t)v > 0x7fff ||
arch/nios2/kernel/module.c
59
(int32_t)v < -(int32_t)0x8000) {
arch/nios2/kernel/module.c
65
*loc = ((((word >> 22) << 16) | (v & 0xffff)) << 6) |
arch/nios2/kernel/module.c
69
if (v & 3) {
arch/nios2/kernel/module.c
74
if ((v >> 28) != ((uint32_t)loc >> 28)) {
arch/nios2/kernel/module.c
79
*loc = (*loc & 0x3f) | ((v >> 2) << 6);
arch/nios2/kernel/module.c
84
((v >> 16) & 0xffff)) << 6) | (word & 0x3f);
arch/nios2/kernel/module.c
88
*loc = ((((word >> 22) << 16) | (v & 0xffff)) << 6) |
arch/nios2/kernel/module.c
96
word2 = ((v >> 16) + ((v >> 15) & 1)) & 0xffff;
arch/openrisc/include/asm/atomic.h
107
static inline int arch_atomic_fetch_add_unless(atomic_t *v, int a, int u)
arch/openrisc/include/asm/atomic.h
121
: "r"(&v->counter), "r"(a), "r"(u)
arch/openrisc/include/asm/atomic.h
128
#define arch_atomic_read(v) READ_ONCE((v)->counter)
arch/openrisc/include/asm/atomic.h
129
#define arch_atomic_set(v,i) WRITE_ONCE((v)->counter, (i))
arch/openrisc/include/asm/atomic.h
16
static inline void arch_atomic_##op(int i, atomic_t *v) \
arch/openrisc/include/asm/atomic.h
27
: "r"(&v->counter), "r"(i) \
arch/openrisc/include/asm/atomic.h
33
static inline int arch_atomic_##op##_return(int i, atomic_t *v) \
arch/openrisc/include/asm/atomic.h
44
: "r"(&v->counter), "r"(i) \
arch/openrisc/include/asm/atomic.h
52
static inline int arch_atomic_fetch_##op(int i, atomic_t *v) \
arch/openrisc/include/asm/atomic.h
63
: "r"(&v->counter), "r"(i) \
arch/openrisc/kernel/setup.c
263
static int show_cpuinfo(struct seq_file *m, void *v)
arch/openrisc/kernel/setup.c
269
struct cpuinfo_or1k *cpuinfo = v;
arch/openrisc/kernel/setup.c
325
static void *c_next(struct seq_file *m, void *v, loff_t *pos)
arch/openrisc/kernel/setup.c
331
static void c_stop(struct seq_file *m, void *v)
arch/openrisc/mm/init.c
103
v += PAGE_SIZE, p += PAGE_SIZE, j++, pte++) {
arch/openrisc/mm/init.c
104
if (v >= (u32) _e_kernel_ro ||
arch/openrisc/mm/init.c
105
v < (u32) _s_kernel_ro)
arch/openrisc/mm/init.c
61
unsigned long v, p, e;
arch/openrisc/mm/init.c
73
v = PAGE_OFFSET;
arch/openrisc/mm/init.c
79
v = (u32) __va(p);
arch/openrisc/mm/init.c
80
pge = pgd_offset_k(v);
arch/openrisc/mm/init.c
84
p4e = p4d_offset(pge, v);
arch/openrisc/mm/init.c
85
pue = pud_offset(p4e, v);
arch/openrisc/mm/init.c
86
pme = pmd_offset(pue, v);
arch/parisc/include/asm/atomic.h
100
static __inline__ int arch_atomic_fetch_##op(int i, atomic_t *v) \
arch/parisc/include/asm/atomic.h
105
_atomic_spin_lock_irqsave(v, flags); \
arch/parisc/include/asm/atomic.h
106
ret = v->counter; \
arch/parisc/include/asm/atomic.h
107
v->counter c_op i; \
arch/parisc/include/asm/atomic.h
108
_atomic_spin_unlock_irqrestore(v, flags); \
arch/parisc/include/asm/atomic.h
149
static __inline__ void arch_atomic64_##op(s64 i, atomic64_t *v) \
arch/parisc/include/asm/atomic.h
153
_atomic_spin_lock_irqsave(v, flags); \
arch/parisc/include/asm/atomic.h
154
v->counter c_op i; \
arch/parisc/include/asm/atomic.h
155
_atomic_spin_unlock_irqrestore(v, flags); \
arch/parisc/include/asm/atomic.h
159
static __inline__ s64 arch_atomic64_##op##_return(s64 i, atomic64_t *v) \
arch/parisc/include/asm/atomic.h
164
_atomic_spin_lock_irqsave(v, flags); \
arch/parisc/include/asm/atomic.h
165
ret = (v->counter c_op i); \
arch/parisc/include/asm/atomic.h
166
_atomic_spin_unlock_irqrestore(v, flags); \
arch/parisc/include/asm/atomic.h
172
static __inline__ s64 arch_atomic64_fetch_##op(s64 i, atomic64_t *v) \
arch/parisc/include/asm/atomic.h
177
_atomic_spin_lock_irqsave(v, flags); \
arch/parisc/include/asm/atomic.h
178
ret = v->counter; \
arch/parisc/include/asm/atomic.h
179
v->counter c_op i; \
arch/parisc/include/asm/atomic.h
180
_atomic_spin_unlock_irqrestore(v, flags); \
arch/parisc/include/asm/atomic.h
217
arch_atomic64_set(atomic64_t *v, s64 i)
arch/parisc/include/asm/atomic.h
220
_atomic_spin_lock_irqsave(v, flags);
arch/parisc/include/asm/atomic.h
222
v->counter = i;
arch/parisc/include/asm/atomic.h
224
_atomic_spin_unlock_irqrestore(v, flags);
arch/parisc/include/asm/atomic.h
227
#define arch_atomic64_set_release(v, i) arch_atomic64_set((v), (i))
arch/parisc/include/asm/atomic.h
230
arch_atomic64_read(const atomic64_t *v)
arch/parisc/include/asm/atomic.h
232
return READ_ONCE((v)->counter);
arch/parisc/include/asm/atomic.h
59
static __inline__ void arch_atomic_set(atomic_t *v, int i)
arch/parisc/include/asm/atomic.h
62
_atomic_spin_lock_irqsave(v, flags);
arch/parisc/include/asm/atomic.h
64
v->counter = i;
arch/parisc/include/asm/atomic.h
66
_atomic_spin_unlock_irqrestore(v, flags);
arch/parisc/include/asm/atomic.h
69
#define arch_atomic_set_release(v, i) arch_atomic_set((v), (i))
arch/parisc/include/asm/atomic.h
71
static __inline__ int arch_atomic_read(const atomic_t *v)
arch/parisc/include/asm/atomic.h
73
return READ_ONCE((v)->counter);
arch/parisc/include/asm/atomic.h
77
static __inline__ void arch_atomic_##op(int i, atomic_t *v) \
arch/parisc/include/asm/atomic.h
81
_atomic_spin_lock_irqsave(v, flags); \
arch/parisc/include/asm/atomic.h
82
v->counter c_op i; \
arch/parisc/include/asm/atomic.h
83
_atomic_spin_unlock_irqrestore(v, flags); \
arch/parisc/include/asm/atomic.h
87
static __inline__ int arch_atomic_##op##_return(int i, atomic_t *v) \
arch/parisc/include/asm/atomic.h
92
_atomic_spin_lock_irqsave(v, flags); \
arch/parisc/include/asm/atomic.h
93
ret = (v->counter c_op i); \
arch/parisc/include/asm/atomic.h
94
_atomic_spin_unlock_irqrestore(v, flags); \
arch/parisc/include/asm/barrier.h
33
#define __smp_store_release(p, v) \
arch/parisc/include/asm/barrier.h
37
{ .__val = (__force typeof(*p)) (v) }; \
arch/parisc/include/asm/pdc_chassis.h
52
#define PDC_CHASSIS_DISP_DATA(v) ((unsigned long)(v) << 17)
arch/parisc/include/asm/processor.h
317
extern int show_cpuinfo (struct seq_file *m, void *v);
arch/parisc/include/asm/psw.h
81
unsigned int v:1;
arch/parisc/kernel/irq.c
174
int show_interrupts(struct seq_file *p, void *v)
arch/parisc/kernel/irq.c
176
int i = *(loff_t *) v, j;
arch/parisc/kernel/module.c
101
#define lsel(v,a) (((v)+(a))>>11)
arch/parisc/kernel/module.c
103
#define rsel(v,a) (((v)+(a))&0x7ff)
arch/parisc/kernel/module.c
105
#define lrsel(v,a) (((v)+rnd(a))>>11)
arch/parisc/kernel/module.c
107
#define rrsel(v,a) ((((v)+rnd(a))&0x7ff)+((a)-rnd(a)))
arch/parisc/kernel/module.c
99
#define fsel(v,a) ((v)+(a))
arch/parisc/kernel/pci-dma.c
338
static int __maybe_unused proc_pcxl_dma_show(struct seq_file *m, void *v)
arch/parisc/kernel/pdc_chassis.c
249
static int pdc_chassis_warn_show(struct seq_file *m, void *v)
arch/parisc/kernel/processor.c
379
show_cpuinfo (struct seq_file *m, void *v)
arch/parisc/kernel/setup.c
157
c_next (struct seq_file *m, void *v, loff_t *pos)
arch/parisc/kernel/setup.c
164
c_stop (struct seq_file *m, void *v)
arch/powerpc/boot/4xx.c
379
static inline u32 __fix_zero(u32 v, u32 def)
arch/powerpc/boot/4xx.c
381
return v ? v : def;
arch/powerpc/boot/addnote.c
68
#define PUT_16BE(off, v)(buf[off] = ((v) >> 8) & 0xff, \
arch/powerpc/boot/addnote.c
69
buf[(off) + 1] = (v) & 0xff)
arch/powerpc/boot/addnote.c
70
#define PUT_32BE(off, v)(PUT_16BE((off), (v) >> 16L), PUT_16BE((off) + 2, (v)))
arch/powerpc/boot/addnote.c
71
#define PUT_64BE(off, v)((PUT_32BE((off), (unsigned long long)(v) >> 32L), \
arch/powerpc/boot/addnote.c
72
PUT_32BE((off) + 4, (unsigned long long)(v))))
arch/powerpc/boot/addnote.c
78
#define PUT_16LE(off, v) (buf[off] = (v) & 0xff, \
arch/powerpc/boot/addnote.c
79
buf[(off) + 1] = ((v) >> 8) & 0xff)
arch/powerpc/boot/addnote.c
80
#define PUT_32LE(off, v) (PUT_16LE((off), (v)), PUT_16LE((off) + 2, (v) >> 16L))
arch/powerpc/boot/addnote.c
81
#define PUT_64LE(off, v) (PUT_32LE((off), (unsigned long long)(v)), \
arch/powerpc/boot/addnote.c
82
PUT_32LE((off) + 4, (unsigned long long)(v) >> 32L))
arch/powerpc/boot/addnote.c
87
#define PUT_16(off, v) (e_data == ELFDATA2MSB ? PUT_16BE(off, v) : \
arch/powerpc/boot/addnote.c
88
PUT_16LE(off, v))
arch/powerpc/boot/addnote.c
89
#define PUT_32(off, v) (e_data == ELFDATA2MSB ? PUT_32BE(off, v) : \
arch/powerpc/boot/addnote.c
90
PUT_32LE(off, v))
arch/powerpc/boot/addnote.c
91
#define PUT_64(off, v) (e_data == ELFDATA2MSB ? PUT_64BE(off, v) : \
arch/powerpc/boot/addnote.c
92
PUT_64LE(off, v))
arch/powerpc/boot/decompress.c
50
static long flush(void *v, unsigned long buffer_size)
arch/powerpc/boot/decompress.c
55
char *in = v;
arch/powerpc/boot/hack-coff.c
20
#define put_16be(x, v) (((unsigned char *)(x))[0] = (v) >> 8, \
arch/powerpc/boot/hack-coff.c
21
((unsigned char *)(x))[1] = (v) & 0xff)
arch/powerpc/boot/main.c
199
int v;
arch/powerpc/boot/main.c
203
n = getprop(chosen, "linux,cmdline-timeout", &v, sizeof(v));
arch/powerpc/boot/main.c
204
if (n == sizeof(v))
arch/powerpc/boot/main.c
205
getline_timeout = v;
arch/powerpc/boot/reg.h
21
#define mtspr(rn, v) asm volatile("mtspr " __stringify(rn) ",%0" : : "r" (v))
arch/powerpc/boot/ugecon.c
108
u32 v;
arch/powerpc/boot/ugecon.c
114
if (getprop(devp, "virtual-reg", &v, sizeof(v)) != sizeof(v))
arch/powerpc/boot/ugecon.c
117
return (void *)v;
arch/powerpc/include/asm/archrandom.h
10
size_t __must_check arch_get_random_seed_longs(unsigned long *v, size_t max_longs);
arch/powerpc/include/asm/archrandom.h
13
int pnv_get_random_long(unsigned long *v);
arch/powerpc/include/asm/archrandom.h
5
static inline size_t __must_check arch_get_random_longs(unsigned long *v, size_t max_longs)
arch/powerpc/include/asm/atomic.h
139
static __inline__ int arch_atomic_fetch_add_unless(atomic_t *v, int a, int u)
arch/powerpc/include/asm/atomic.h
155
: "r" (&v->counter), "rI" (a), "r" (u)
arch/powerpc/include/asm/atomic.h
167
static __inline__ int arch_atomic_dec_if_positive(atomic_t *v)
arch/powerpc/include/asm/atomic.h
182
: "r" (&v->counter)
arch/powerpc/include/asm/atomic.h
193
static __inline__ s64 arch_atomic64_read(const atomic64_t *v)
arch/powerpc/include/asm/atomic.h
199
__asm__ __volatile__("ld %0,0(%1)" : "=r"(t) : "b"(&v->counter));
arch/powerpc/include/asm/atomic.h
201
__asm__ __volatile__("ld%U1%X1 %0,%1" : "=r"(t) : DS_FORM_CONSTRAINT (v->counter));
arch/powerpc/include/asm/atomic.h
206
static __inline__ void arch_atomic64_set(atomic64_t *v, s64 i)
arch/powerpc/include/asm/atomic.h
210
__asm__ __volatile__("std %1,0(%2)" : "=m"(v->counter) : "r"(i), "b"(&v->counter));
arch/powerpc/include/asm/atomic.h
212
__asm__ __volatile__("std%U0%X0 %1,%0" : "=" DS_FORM_CONSTRAINT (v->counter) : "r"(i));
arch/powerpc/include/asm/atomic.h
216
static __inline__ void arch_atomic64_##op(s64 a, atomic64_t *v) \
arch/powerpc/include/asm/atomic.h
225
: "=&r" (t), "+m" (v->counter) \
arch/powerpc/include/asm/atomic.h
226
: "r" (a), "r" (&v->counter) \
arch/powerpc/include/asm/atomic.h
232
arch_atomic64_##op##_return_relaxed(s64 a, atomic64_t *v) \
arch/powerpc/include/asm/atomic.h
241
: "=&r" (t), "+m" (v->counter) \
arch/powerpc/include/asm/atomic.h
242
: "r" (a), "r" (&v->counter) \
arch/powerpc/include/asm/atomic.h
250
arch_atomic64_fetch_##op##_relaxed(s64 a, atomic64_t *v) \
arch/powerpc/include/asm/atomic.h
259
: "=&r" (res), "=&r" (t), "+m" (v->counter) \
arch/powerpc/include/asm/atomic.h
260
: "r" (a), "r" (&v->counter) \
arch/powerpc/include/asm/atomic.h
27
static __inline__ int arch_atomic_read(const atomic_t *v)
arch/powerpc/include/asm/atomic.h
298
static __inline__ void arch_atomic64_inc(atomic64_t *v)
arch/powerpc/include/asm/atomic.h
307
: "=&r" (t), "+m" (v->counter)
arch/powerpc/include/asm/atomic.h
308
: "r" (&v->counter)
arch/powerpc/include/asm/atomic.h
313
static __inline__ s64 arch_atomic64_inc_return_relaxed(atomic64_t *v)
arch/powerpc/include/asm/atomic.h
322
: "=&r" (t), "+m" (v->counter)
arch/powerpc/include/asm/atomic.h
323
: "r" (&v->counter)
arch/powerpc/include/asm/atomic.h
329
static __inline__ void arch_atomic64_dec(atomic64_t *v)
arch/powerpc/include/asm/atomic.h
33
__asm__ __volatile__("lwz %0,0(%1)" : "=r"(t) : "b"(&v->counter));
arch/powerpc/include/asm/atomic.h
338
: "=&r" (t), "+m" (v->counter)
arch/powerpc/include/asm/atomic.h
339
: "r" (&v->counter)
arch/powerpc/include/asm/atomic.h
344
static __inline__ s64 arch_atomic64_dec_return_relaxed(atomic64_t *v)
arch/powerpc/include/asm/atomic.h
35
__asm__ __volatile__("lwz%U1%X1 %0,%1" : "=r"(t) : "m<>"(v->counter));
arch/powerpc/include/asm/atomic.h
353
: "=&r" (t), "+m" (v->counter)
arch/powerpc/include/asm/atomic.h
354
: "r" (&v->counter)
arch/powerpc/include/asm/atomic.h
367
static __inline__ s64 arch_atomic64_dec_if_positive(atomic64_t *v)
arch/powerpc/include/asm/atomic.h
381
: "r" (&v->counter)
arch/powerpc/include/asm/atomic.h
397
static __inline__ s64 arch_atomic64_fetch_add_unless(atomic64_t *v, s64 a, s64 u)
arch/powerpc/include/asm/atomic.h
40
static __inline__ void arch_atomic_set(atomic_t *v, int i)
arch/powerpc/include/asm/atomic.h
413
: "r" (&v->counter), "r" (a), "r" (u)
arch/powerpc/include/asm/atomic.h
427
static __inline__ int arch_atomic64_inc_not_zero(atomic64_t *v)
arch/powerpc/include/asm/atomic.h
44
__asm__ __volatile__("stw %1,0(%2)" : "=m"(v->counter) : "r"(i), "b"(&v->counter));
arch/powerpc/include/asm/atomic.h
443
: "r" (&v->counter)
arch/powerpc/include/asm/atomic.h
448
#define arch_atomic64_inc_not_zero(v) arch_atomic64_inc_not_zero((v))
arch/powerpc/include/asm/atomic.h
46
__asm__ __volatile__("stw%U0%X0 %1,%0" : "=m<>"(v->counter) : "r"(i));
arch/powerpc/include/asm/atomic.h
50
static __inline__ void arch_atomic_##op(int a, atomic_t *v) \
arch/powerpc/include/asm/atomic.h
59
: "=&r" (t), "+m" (v->counter) \
arch/powerpc/include/asm/atomic.h
60
: "r"#sign (a), "r" (&v->counter) \
arch/powerpc/include/asm/atomic.h
65
static inline int arch_atomic_##op##_return_relaxed(int a, atomic_t *v) \
arch/powerpc/include/asm/atomic.h
74
: "=&r" (t), "+m" (v->counter) \
arch/powerpc/include/asm/atomic.h
75
: "r"#sign (a), "r" (&v->counter) \
arch/powerpc/include/asm/atomic.h
82
static inline int arch_atomic_fetch_##op##_relaxed(int a, atomic_t *v) \
arch/powerpc/include/asm/atomic.h
91
: "=&r" (res), "=&r" (t), "+m" (v->counter) \
arch/powerpc/include/asm/atomic.h
92
: "r"#sign (a), "r" (&v->counter) \
arch/powerpc/include/asm/barrier.h
72
#define __smp_store_release(p, v) \
arch/powerpc/include/asm/barrier.h
76
WRITE_ONCE(*p, v); \
arch/powerpc/include/asm/book3s/32/mmu-hash.h
160
unsigned long v:1; /* Entry is valid */
arch/powerpc/include/asm/book3s/64/mmu-hash.h
176
__be64 v;
arch/powerpc/include/asm/book3s/64/mmu-hash.h
328
unsigned long v;
arch/powerpc/include/asm/book3s/64/mmu-hash.h
337
v = (vpn >> (23 - VPN_SHIFT)) & ~(mmu_psize_defs[psize].avpnm);
arch/powerpc/include/asm/book3s/64/mmu-hash.h
338
v <<= HPTE_V_AVPN_SHIFT;
arch/powerpc/include/asm/book3s/64/mmu-hash.h
339
v |= ((unsigned long) ssize) << HPTE_V_SSIZE_SHIFT;
arch/powerpc/include/asm/book3s/64/mmu-hash.h
340
return v;
arch/powerpc/include/asm/book3s/64/mmu-hash.h
348
static inline unsigned long hpte_old_to_new_v(unsigned long v)
arch/powerpc/include/asm/book3s/64/mmu-hash.h
351
return v & HPTE_V_COMMON_BITS;
arch/powerpc/include/asm/book3s/64/mmu-hash.h
354
static inline unsigned long hpte_old_to_new_r(unsigned long v, unsigned long r)
arch/powerpc/include/asm/book3s/64/mmu-hash.h
358
(((v) >> HPTE_V_SSIZE_SHIFT) << HPTE_R_3_0_SSIZE_SHIFT);
arch/powerpc/include/asm/book3s/64/mmu-hash.h
361
static inline unsigned long hpte_new_to_old_v(unsigned long v, unsigned long r)
arch/powerpc/include/asm/book3s/64/mmu-hash.h
364
return (v & HPTE_V_COMMON_BITS) |
arch/powerpc/include/asm/book3s/64/mmu-hash.h
379
hpte_v = be64_to_cpu(hptep->v);
arch/powerpc/include/asm/book3s/64/mmu-hash.h
392
unsigned long v;
arch/powerpc/include/asm/book3s/64/mmu-hash.h
393
v = hpte_encode_avpn(vpn, base_psize, ssize);
arch/powerpc/include/asm/book3s/64/mmu-hash.h
395
v |= HPTE_V_LARGE;
arch/powerpc/include/asm/book3s/64/mmu-hash.h
396
return v;
arch/powerpc/include/asm/btext.h
26
void __init btext_drawhex(unsigned long v);
arch/powerpc/include/asm/dcr-native.h
64
#define mtdcr(rn, v) \
arch/powerpc/include/asm/dcr-native.h
68
: : "n" (rn), "r" (v)); \
arch/powerpc/include/asm/dcr-native.h
70
mtdcrx(rn, v); \
arch/powerpc/include/asm/dcr-native.h
72
__mtdcr(rn, v); \
arch/powerpc/include/asm/guest-state-buffer.h
668
__vector128 v;
arch/powerpc/include/asm/guest-state-buffer.h
672
u.v = *val;
arch/powerpc/include/asm/guest-state-buffer.h
784
vector128 *v)
arch/powerpc/include/asm/guest-state-buffer.h
787
__vector128 v;
arch/powerpc/include/asm/guest-state-buffer.h
793
*v = u.v;
arch/powerpc/include/asm/guest-state-buffer.h
800
*v = u.v;
arch/powerpc/include/asm/io.h
698
#define writeb_relaxed(v, addr) writeb(v, addr)
arch/powerpc/include/asm/io.h
699
#define writew_relaxed(v, addr) writew(v, addr)
arch/powerpc/include/asm/io.h
700
#define writel_relaxed(v, addr) writel(v, addr)
arch/powerpc/include/asm/io.h
701
#define writeq_relaxed(v, addr) writeq(v, addr)
arch/powerpc/include/asm/io.h
965
static inline void __raw_writeq_be(unsigned long v, volatile void __iomem *addr)
arch/powerpc/include/asm/io.h
967
__raw_writeq((__force unsigned long)cpu_to_be64(v), addr);
arch/powerpc/include/asm/kvm_book3s.h
523
static inline void kvmppc_get_vsx_vr(struct kvm_vcpu *vcpu, int i, vector128 *v)
arch/powerpc/include/asm/kvm_book3s.h
526
*v = vcpu->arch.vr.vr[i];
arch/powerpc/include/asm/kvm_book3s_64.h
262
static inline unsigned long kvmppc_actual_pgsz(unsigned long v, unsigned long r)
arch/powerpc/include/asm/kvm_book3s_64.h
264
int shift = kvmppc_hpte_actual_page_shift(v, r);
arch/powerpc/include/asm/kvm_book3s_64.h
298
static inline unsigned long compute_tlbie_rb(unsigned long v, unsigned long r,
arch/powerpc/include/asm/kvm_book3s_64.h
304
b_pgshift = a_pgshift = kvmppc_hpte_page_shifts(v, r);
arch/powerpc/include/asm/kvm_book3s_64.h
320
rb = (v & ~0x7fUL) << 16; /* AVA field */
arch/powerpc/include/asm/kvm_book3s_64.h
327
if (v & HPTE_V_SECONDARY)
arch/powerpc/include/asm/kvm_book3s_64.h
335
if (!(v & HPTE_V_1TB_SEG))
arch/powerpc/include/asm/kvm_book3s_64.h
336
va_low ^= v >> (SID_SHIFT - 16);
arch/powerpc/include/asm/kvm_book3s_64.h
338
va_low ^= v >> (SID_SHIFT_1T - 16);
arch/powerpc/include/asm/kvm_book3s_64.h
373
rb |= (v >> HPTE_V_SSIZE_SHIFT) << 8; /* B field */
arch/powerpc/include/asm/local.h
110
t = l->v;
arch/powerpc/include/asm/local.h
111
l->v = n;
arch/powerpc/include/asm/local.h
132
if (l->v != u) {
arch/powerpc/include/asm/local.h
133
l->v += a;
arch/powerpc/include/asm/local.h
148
#define __local_inc(l) ((l)->v++)
arch/powerpc/include/asm/local.h
149
#define __local_dec(l) ((l)->v++)
arch/powerpc/include/asm/local.h
15
long v;
arch/powerpc/include/asm/local.h
150
#define __local_add(i,l) ((l)->v+=(i))
arch/powerpc/include/asm/local.h
151
#define __local_sub(i,l) ((l)->v-=(i))
arch/powerpc/include/asm/local.h
22
return READ_ONCE(l->v);
arch/powerpc/include/asm/local.h
27
WRITE_ONCE(l->v, i);
arch/powerpc/include/asm/local.h
36
l->v c_op i; \
arch/powerpc/include/asm/local.h
47
t = (l->v c_op a); \
arch/powerpc/include/asm/local.h
85
t = l->v;
arch/powerpc/include/asm/local.h
87
l->v = n;
arch/powerpc/include/asm/machdep.h
207
int (*get_random_seed)(unsigned long *v);
arch/powerpc/include/asm/mmu_context.h
195
int v;
arch/powerpc/include/asm/mmu_context.h
198
v = atomic_dec_if_positive(&mm->context.vas_windows);
arch/powerpc/include/asm/mmu_context.h
201
WARN_ON(v < 0);
arch/powerpc/include/asm/pmac_feature.h
371
#define MACIO_OUT32(r,v) (out_le32(MACIO_FCR32(macio,r), (v)))
arch/powerpc/include/asm/pmac_feature.h
372
#define MACIO_BIS(r,v) (MACIO_OUT32((r), MACIO_IN32(r) | (v)))
arch/powerpc/include/asm/pmac_feature.h
373
#define MACIO_BIC(r,v) (MACIO_OUT32((r), MACIO_IN32(r) & ~(v)))
arch/powerpc/include/asm/pmac_feature.h
375
#define MACIO_OUT8(r,v) (out_8(MACIO_FCR8(macio,r), (v)))
arch/powerpc/include/asm/pmac_feature.h
391
#define UN_OUT(r,v) (out_be32(UN_REG(r), (v)))
arch/powerpc/include/asm/pmac_feature.h
392
#define UN_BIS(r,v) (UN_OUT((r), UN_IN(r) | (v)))
arch/powerpc/include/asm/pmac_feature.h
393
#define UN_BIC(r,v) (UN_OUT((r), UN_IN(r) & ~(v)))
arch/powerpc/include/asm/pmac_pfunc.h
26
u32 v;
arch/powerpc/include/asm/ppc-opcode.h
363
#define PPC_LO(v) ((v) & 0xffff)
arch/powerpc/include/asm/ppc-opcode.h
364
#define PPC_HI(v) (((v) >> 16) & 0xffff)
arch/powerpc/include/asm/ppc-opcode.h
365
#define PPC_HA(v) PPC_HI((v) + 0x8000)
arch/powerpc/include/asm/ppc-opcode.h
366
#define PPC_HIGHER(v) (((v) >> 32) & 0xffff)
arch/powerpc/include/asm/ppc-opcode.h
367
#define PPC_HIGHEST(v) (((v) >> 48) & 0xffff)
arch/powerpc/include/asm/ppc-opcode.h
371
#define PPC_LI(v) ((v) & PPC_LI_MASK)
arch/powerpc/include/asm/ps3.h
26
void ps3_get_firmware_version(union ps3_firmware_version *v);
arch/powerpc/include/asm/reg.h
1378
#define __mtmsrd(v, l) asm volatile("mtmsrd %0," __stringify(l) \
arch/powerpc/include/asm/reg.h
1379
: : "r" (v) : "memory")
arch/powerpc/include/asm/reg.h
1380
#define mtmsr(v) __mtmsrd((v), 0)
arch/powerpc/include/asm/reg.h
1383
#define mtmsr(v) asm volatile("mtmsr %0" : \
arch/powerpc/include/asm/reg.h
1384
: "r" ((unsigned long)(v)) \
arch/powerpc/include/asm/reg.h
1386
#define __mtmsrd(v, l) BUILD_BUG()
arch/powerpc/include/asm/reg.h
1399
#define mtspr(rn, v) asm volatile("mtspr " __stringify(rn) ",%0" : \
arch/powerpc/include/asm/reg.h
1400
: "r" ((unsigned long)(v)) \
arch/powerpc/include/asm/reg_booke.h
582
#define mttmr(rn, v) asm volatile(MTTMR(rn, %0) : \
arch/powerpc/include/asm/reg_booke.h
583
: "r" ((unsigned long)(v)) \
arch/powerpc/include/asm/sstep.h
135
__vector128 v;
arch/powerpc/include/asm/string.h
64
extern void *__memset16(uint16_t *, uint16_t v, __kernel_size_t);
arch/powerpc/include/asm/string.h
65
extern void *__memset32(uint32_t *, uint32_t v, __kernel_size_t);
arch/powerpc/include/asm/string.h
66
extern void *__memset64(uint64_t *, uint64_t v, __kernel_size_t);
arch/powerpc/include/asm/string.h
68
static inline void *memset16(uint16_t *p, uint16_t v, __kernel_size_t n)
arch/powerpc/include/asm/string.h
70
return __memset16(p, v, n * 2);
arch/powerpc/include/asm/string.h
73
static inline void *memset32(uint32_t *p, uint32_t v, __kernel_size_t n)
arch/powerpc/include/asm/string.h
75
return __memset32(p, v, n * 4);
arch/powerpc/include/asm/string.h
78
static inline void *memset64(uint64_t *p, uint64_t v, __kernel_size_t n)
arch/powerpc/include/asm/string.h
80
return __memset64(p, v, n * 8);
arch/powerpc/include/asm/vas.h
45
#define GET_FIELD(m, v) (((v) & (m)) >> MASK_LSH(m))
arch/powerpc/include/asm/vas.h
47
#define SET_FIELD(m, v, val) \
arch/powerpc/include/asm/vas.h
48
(((v) & ~(m)) | ((((typeof(v))(val)) << MASK_LSH(m)) & (m)))
arch/powerpc/include/asm/vdso/timebase.h
43
#define mttbl(v) asm volatile("mttbl %0":: "r"(v))
arch/powerpc/include/asm/vdso/timebase.h
44
#define mttbu(v) asm volatile("mttbu %0":: "r"(v))
arch/powerpc/include/asm/vga.h
38
static inline void scr_memsetw(u16 *s, u16 v, unsigned int n)
arch/powerpc/include/asm/vga.h
40
memset16(s, cpu_to_le16(v), n / 2);
arch/powerpc/kernel/align.c
114
u8 v[8];
arch/powerpc/kernel/align.c
173
unsafe_get_user(temp.v[0], p++, Efault_read);
arch/powerpc/kernel/align.c
174
unsafe_get_user(temp.v[1], p++, Efault_read);
arch/powerpc/kernel/align.c
175
unsafe_get_user(temp.v[2], p++, Efault_read);
arch/powerpc/kernel/align.c
176
unsafe_get_user(temp.v[3], p++, Efault_read);
arch/powerpc/kernel/align.c
179
unsafe_get_user(temp.v[4], p++, Efault_read);
arch/powerpc/kernel/align.c
180
unsafe_get_user(temp.v[5], p++, Efault_read);
arch/powerpc/kernel/align.c
183
unsafe_get_user(temp.v[6], p++, Efault_read);
arch/powerpc/kernel/align.c
184
unsafe_get_user(temp.v[7], p++, Efault_read);
arch/powerpc/kernel/align.c
260
unsafe_put_user(data.v[0], p++, Efault_write);
arch/powerpc/kernel/align.c
261
unsafe_put_user(data.v[1], p++, Efault_write);
arch/powerpc/kernel/align.c
262
unsafe_put_user(data.v[2], p++, Efault_write);
arch/powerpc/kernel/align.c
263
unsafe_put_user(data.v[3], p++, Efault_write);
arch/powerpc/kernel/align.c
266
unsafe_put_user(data.v[4], p++, Efault_write);
arch/powerpc/kernel/align.c
267
unsafe_put_user(data.v[5], p++, Efault_write);
arch/powerpc/kernel/align.c
270
unsafe_put_user(data.v[6], p++, Efault_write);
arch/powerpc/kernel/align.c
271
unsafe_put_user(data.v[7], p++, Efault_write);
arch/powerpc/kernel/btext.c
554
void __init btext_drawhex(unsigned long v)
arch/powerpc/kernel/btext.c
559
btext_drawchar(hex_asc_hi(v >> 56));
arch/powerpc/kernel/btext.c
560
btext_drawchar(hex_asc_lo(v >> 56));
arch/powerpc/kernel/btext.c
561
btext_drawchar(hex_asc_hi(v >> 48));
arch/powerpc/kernel/btext.c
562
btext_drawchar(hex_asc_lo(v >> 48));
arch/powerpc/kernel/btext.c
563
btext_drawchar(hex_asc_hi(v >> 40));
arch/powerpc/kernel/btext.c
564
btext_drawchar(hex_asc_lo(v >> 40));
arch/powerpc/kernel/btext.c
565
btext_drawchar(hex_asc_hi(v >> 32));
arch/powerpc/kernel/btext.c
566
btext_drawchar(hex_asc_lo(v >> 32));
arch/powerpc/kernel/btext.c
568
btext_drawchar(hex_asc_hi(v >> 24));
arch/powerpc/kernel/btext.c
569
btext_drawchar(hex_asc_lo(v >> 24));
arch/powerpc/kernel/btext.c
570
btext_drawchar(hex_asc_hi(v >> 16));
arch/powerpc/kernel/btext.c
571
btext_drawchar(hex_asc_lo(v >> 16));
arch/powerpc/kernel/btext.c
572
btext_drawchar(hex_asc_hi(v >> 8));
arch/powerpc/kernel/btext.c
573
btext_drawchar(hex_asc_lo(v >> 8));
arch/powerpc/kernel/btext.c
574
btext_drawchar(hex_asc_hi(v));
arch/powerpc/kernel/btext.c
575
btext_drawchar(hex_asc_lo(v));
arch/powerpc/kernel/eeh.c
1546
static int proc_eeh_show(struct seq_file *m, void *v)
arch/powerpc/kernel/eeh_cache.c
263
static int eeh_addr_cache_show(struct seq_file *s, void *v)
arch/powerpc/kernel/io.c
126
#define IO_CHECK_ALIGN(v,a) ((((unsigned long)(v)) & ((a) - 1)) == 0)
arch/powerpc/kernel/prom_init.c
503
unsigned long v;
arch/powerpc/kernel/prom_init.c
538
v = va_arg(args, unsigned int);
arch/powerpc/kernel/prom_init.c
541
v = va_arg(args, unsigned long);
arch/powerpc/kernel/prom_init.c
545
v = va_arg(args, unsigned long long);
arch/powerpc/kernel/prom_init.c
548
prom_print_hex(v);
arch/powerpc/kernel/prom_init.c
554
v = va_arg(args, unsigned int);
arch/powerpc/kernel/prom_init.c
557
v = va_arg(args, unsigned long);
arch/powerpc/kernel/prom_init.c
561
v = va_arg(args, unsigned long long);
arch/powerpc/kernel/prom_init.c
564
prom_print_dec(v);
arch/powerpc/kernel/rtas-proc.c
138
static int ppc_rtas_sensors_show(struct seq_file *m, void *v);
arch/powerpc/kernel/rtas-proc.c
139
static int ppc_rtas_clock_show(struct seq_file *m, void *v);
arch/powerpc/kernel/rtas-proc.c
142
static int ppc_rtas_progress_show(struct seq_file *m, void *v);
arch/powerpc/kernel/rtas-proc.c
145
static int ppc_rtas_poweron_show(struct seq_file *m, void *v);
arch/powerpc/kernel/rtas-proc.c
151
static int ppc_rtas_tone_freq_show(struct seq_file *m, void *v);
arch/powerpc/kernel/rtas-proc.c
154
static int ppc_rtas_tone_volume_show(struct seq_file *m, void *v);
arch/powerpc/kernel/rtas-proc.c
155
static int ppc_rtas_rmo_buf_show(struct seq_file *m, void *v);
arch/powerpc/kernel/rtas-proc.c
299
static int ppc_rtas_poweron_show(struct seq_file *m, void *v)
arch/powerpc/kernel/rtas-proc.c
333
static int ppc_rtas_progress_show(struct seq_file *m, void *v)
arch/powerpc/kernel/rtas-proc.c
362
static int ppc_rtas_clock_show(struct seq_file *m, void *v)
arch/powerpc/kernel/rtas-proc.c
384
static int ppc_rtas_sensors_show(struct seq_file *m, void *v)
arch/powerpc/kernel/rtas-proc.c
719
static int ppc_rtas_tone_freq_show(struct seq_file *m, void *v)
arch/powerpc/kernel/rtas-proc.c
747
static int ppc_rtas_tone_volume_show(struct seq_file *m, void *v)
arch/powerpc/kernel/rtas-proc.c
765
static int ppc_rtas_rmo_buf_show(struct seq_file *m, void *v)
arch/powerpc/kernel/setup-common.c
167
size_t __must_check arch_get_random_seed_longs(unsigned long *v, size_t max_longs)
arch/powerpc/kernel/setup-common.c
169
if (max_longs && ppc_md.get_random_seed && ppc_md.get_random_seed(v))
arch/powerpc/kernel/setup-common.c
221
static int show_cpuinfo(struct seq_file *m, void *v)
arch/powerpc/kernel/setup-common.c
223
unsigned long cpu_id = (unsigned long)v - 1;
arch/powerpc/kernel/setup-common.c
343
static void *c_next(struct seq_file *m, void *v, loff_t *pos)
arch/powerpc/kernel/setup-common.c
349
static void c_stop(struct seq_file *m, void *v)
arch/powerpc/kernel/setup-common.c
756
static int dump_kernel_offset(struct notifier_block *self, unsigned long v,
arch/powerpc/kvm/book3s_32_mmu.c
341
struct kvm_vcpu *v;
arch/powerpc/kvm/book3s_32_mmu.c
344
kvm_for_each_vcpu(i, v, vcpu->kvm)
arch/powerpc/kvm/book3s_32_mmu.c
345
kvmppc_mmu_pte_flush(v, ea, 0x0FFFF000);
arch/powerpc/kvm/book3s_64_mmu.c
534
struct kvm_vcpu *v;
arch/powerpc/kvm/book3s_64_mmu.c
558
kvm_for_each_vcpu(i, v, vcpu->kvm)
arch/powerpc/kvm/book3s_64_mmu.c
559
kvmppc_mmu_pte_vflush(v, va >> 12, mask);
arch/powerpc/kvm/book3s_64_mmu_hv.c
1010
unsigned long v, r;
arch/powerpc/kvm/book3s_64_mmu_hv.c
1063
v = be64_to_cpu(hptep[0]);
arch/powerpc/kvm/book3s_64_mmu_hv.c
1071
n = kvmppc_actual_pgsz(v, r);
arch/powerpc/kvm/book3s_64_mmu_hv.c
1077
v &= ~HPTE_V_ABSENT;
arch/powerpc/kvm/book3s_64_mmu_hv.c
1078
v |= HPTE_V_VALID;
arch/powerpc/kvm/book3s_64_mmu_hv.c
1079
__unlock_hpte(hptep, v);
arch/powerpc/kvm/book3s_64_mmu_hv.c
1627
unsigned long v, r, hr;
arch/powerpc/kvm/book3s_64_mmu_hv.c
1647
v = r = 0;
arch/powerpc/kvm/book3s_64_mmu_hv.c
1653
v = be64_to_cpu(hptp[0]);
arch/powerpc/kvm/book3s_64_mmu_hv.c
1656
v = hpte_new_to_old_v(v, hr);
arch/powerpc/kvm/book3s_64_mmu_hv.c
1661
valid = !!(v & HPTE_V_VALID);
arch/powerpc/kvm/book3s_64_mmu_hv.c
1672
if (v & HPTE_V_ABSENT) {
arch/powerpc/kvm/book3s_64_mmu_hv.c
1673
v &= ~HPTE_V_ABSENT;
arch/powerpc/kvm/book3s_64_mmu_hv.c
1674
v |= HPTE_V_VALID;
arch/powerpc/kvm/book3s_64_mmu_hv.c
1677
if ((flags & KVM_GET_HTAB_BOLTED_ONLY) && !(v & HPTE_V_BOLTED))
arch/powerpc/kvm/book3s_64_mmu_hv.c
1691
hpte[0] = cpu_to_be64(v);
arch/powerpc/kvm/book3s_64_mmu_hv.c
1802
unsigned long v, r;
arch/powerpc/kvm/book3s_64_mmu_hv.c
1859
v = be64_to_cpu(hpte_v);
arch/powerpc/kvm/book3s_64_mmu_hv.c
1862
if (!(v & HPTE_V_VALID))
arch/powerpc/kvm/book3s_64_mmu_hv.c
1864
pshift = kvmppc_hpte_base_page_shift(v, r);
arch/powerpc/kvm/book3s_64_mmu_hv.c
1873
ret = kvmppc_virtmode_do_h_enter(kvm, H_EXACT, i, v, r,
arch/powerpc/kvm/book3s_64_mmu_hv.c
1876
pr_err("%s ret %ld i=%ld v=%lx r=%lx\n", __func__, ret, i, v, r);
arch/powerpc/kvm/book3s_64_mmu_hv.c
1879
if (!mmu_ready && is_vrma_hpte(v)) {
arch/powerpc/kvm/book3s_64_mmu_hv.c
2015
unsigned long v, hr, gr;
arch/powerpc/kvm/book3s_64_mmu_hv.c
2056
v = be64_to_cpu(hptp[0]) & ~HPTE_V_HVLOCK;
arch/powerpc/kvm/book3s_64_mmu_hv.c
2059
unlock_hpte(hptp, v);
arch/powerpc/kvm/book3s_64_mmu_hv.c
2062
if (!(v & (HPTE_V_VALID | HPTE_V_ABSENT)))
arch/powerpc/kvm/book3s_64_mmu_hv.c
2067
i, v, hr, gr);
arch/powerpc/kvm/book3s_64_mmu_hv.c
332
static unsigned long kvmppc_mmu_get_real_addr(unsigned long v, unsigned long r,
arch/powerpc/kvm/book3s_64_mmu_hv.c
337
ra_mask = kvmppc_actual_pgsz(v, r) - 1;
arch/powerpc/kvm/book3s_64_mmu_hv.c
348
unsigned long v, orig_v, gr;
arch/powerpc/kvm/book3s_64_mmu_hv.c
376
v = orig_v = be64_to_cpu(hptep[0]) & ~HPTE_V_HVLOCK;
arch/powerpc/kvm/book3s_64_mmu_hv.c
378
v = hpte_new_to_old_v(v, be64_to_cpu(hptep[1]));
arch/powerpc/kvm/book3s_64_mmu_hv.c
385
gpte->vpage = ((v & HPTE_V_AVPN) << 4) | ((eaddr >> 12) & 0xfff);
arch/powerpc/kvm/book3s_64_mmu_hv.c
407
gpte->raddr = kvmppc_mmu_get_real_addr(v, gr, eaddr);
arch/powerpc/kvm/book3s_hv.c
1505
struct kvm_vcpu *v;
arch/powerpc/kvm/book3s_hv.c
1512
v = kvmppc_find_vcpu(vcpu->kvm, cpu);
arch/powerpc/kvm/book3s_hv.c
1513
if (!v)
arch/powerpc/kvm/book3s_hv.c
1520
pcpu = READ_ONCE(v->cpu);
arch/powerpc/kvm/book3s_hv.c
1523
if (kvmppc_doorbell_pending(v))
arch/powerpc/kvm/book3s_hv.c
4743
struct kvm_vcpu *v;
arch/powerpc/kvm/book3s_hv.c
4806
for_each_runnable_thread(i, v, vc) {
arch/powerpc/kvm/book3s_hv.c
4807
kvmppc_core_prepare_to_enter(v);
arch/powerpc/kvm/book3s_hv.c
4808
if (signal_pending(v->arch.run_task)) {
arch/powerpc/kvm/book3s_hv.c
4809
kvmppc_remove_runnable(vc, v, mftb());
arch/powerpc/kvm/book3s_hv.c
4810
v->stat.signal_exits++;
arch/powerpc/kvm/book3s_hv.c
4811
v->run->exit_reason = KVM_EXIT_INTR;
arch/powerpc/kvm/book3s_hv.c
4812
v->arch.ret = -EINTR;
arch/powerpc/kvm/book3s_hv.c
4813
wake_up(&v->arch.cpu_run);
arch/powerpc/kvm/book3s_hv.c
4819
for_each_runnable_thread(i, v, vc) {
arch/powerpc/kvm/book3s_hv.c
4820
if (!kvmppc_vcpu_woken(v))
arch/powerpc/kvm/book3s_hv.c
4821
n_ceded += v->arch.ceded;
arch/powerpc/kvm/book3s_hv.c
4823
v->arch.ceded = 0;
arch/powerpc/kvm/book3s_hv.c
4859
v = next_runnable_thread(vc, &i);
arch/powerpc/kvm/book3s_hv.c
4860
wake_up(&v->arch.cpu_run);
arch/powerpc/kvm/book3s_hv.c
530
static int set_vpa(struct kvm_vcpu *vcpu, struct kvmppc_vpa *v,
arch/powerpc/kvm/book3s_hv.c
537
if (v->next_gpa != addr || v->len != len) {
arch/powerpc/kvm/book3s_hv.c
538
v->next_gpa = addr;
arch/powerpc/kvm/book3s_hv.c
539
v->len = addr ? len : 0;
arch/powerpc/kvm/book3s_hv.c
540
v->update_pending = 1;
arch/powerpc/kvm/book3s_hv_nestedv2.c
144
vector128 v;
arch/powerpc/kvm/book3s_hv_nestedv2.c
346
memcpy(&v, &vcpu->arch.fp.fpr[i],
arch/powerpc/kvm/book3s_hv_nestedv2.c
348
rc = kvmppc_gse_put_vector128(gsb, iden, &v);
arch/powerpc/kvm/book3s_hv_nestedv2.c
407
vector128 v;
arch/powerpc/kvm/book3s_hv_nestedv2.c
589
kvmppc_gse_get_vector128(gse, &v);
arch/powerpc/kvm/book3s_hv_nestedv2.c
591
memcpy(&vcpu->arch.fp.fpr[i], &v,
arch/powerpc/kvm/book3s_hv_rm_mmu.c
1107
unsigned long v, r, orig_v;
arch/powerpc/kvm/book3s_hv_rm_mmu.c
1141
v = be64_to_cpu(hpte[i]) & ~HPTE_V_HVLOCK;
arch/powerpc/kvm/book3s_hv_rm_mmu.c
1143
v = hpte_new_to_old_v(v, be64_to_cpu(hpte[i+1]));
arch/powerpc/kvm/book3s_hv_rm_mmu.c
1146
if (!(v & valid) || (v & mask) != val)
arch/powerpc/kvm/book3s_hv_rm_mmu.c
1152
v = orig_v = be64_to_cpu(hpte[i]) & ~HPTE_V_HVLOCK;
arch/powerpc/kvm/book3s_hv_rm_mmu.c
1155
v = hpte_new_to_old_v(v, r);
arch/powerpc/kvm/book3s_hv_rm_mmu.c
1162
if ((v & valid) && (v & mask) == val &&
arch/powerpc/kvm/book3s_hv_rm_mmu.c
1163
kvmppc_hpte_base_page_shift(v, r) == pshift)
arch/powerpc/kvm/book3s_hv_rm_mmu.c
1195
unsigned long v, r, gr, orig_v;
arch/powerpc/kvm/book3s_hv_rm_mmu.c
1212
v = cache_entry->hpte_v;
arch/powerpc/kvm/book3s_hv_rm_mmu.c
1223
v = orig_v = be64_to_cpu(hpte[0]) & ~HPTE_V_HVLOCK;
arch/powerpc/kvm/book3s_hv_rm_mmu.c
1226
v = hpte_new_to_old_v(v, r);
arch/powerpc/kvm/book3s_hv_rm_mmu.c
1236
if ((status & DSISR_NOHPTE) && (v & HPTE_V_VALID))
arch/powerpc/kvm/book3s_hv_rm_mmu.c
1269
vcpu->arch.pgfault_hpte[0] = v;
arch/powerpc/kvm/book3s_hv_rm_mmu.c
1288
cache_entry->hpte_v = v;
arch/powerpc/kvm/book3s_hv_rm_mmu.c
416
static inline int is_mmio_hpte(unsigned long v, unsigned long r)
arch/powerpc/kvm/book3s_hv_rm_mmu.c
418
return ((v & HPTE_V_ABSENT) &&
arch/powerpc/kvm/book3s_hv_rm_mmu.c
490
unsigned long v, r, rb;
arch/powerpc/kvm/book3s_hv_rm_mmu.c
515
v = pte & ~HPTE_V_HVLOCK;
arch/powerpc/kvm/book3s_hv_rm_mmu.c
516
if (v & HPTE_V_VALID) {
arch/powerpc/kvm/book3s_hv_rm_mmu.c
518
rb = compute_tlbie_rb(v, pte_r, pte_index);
arch/powerpc/kvm/book3s_hv_rm_mmu.c
529
remove_revmap_chain(kvm, pte_index, rev, v,
arch/powerpc/kvm/book3s_hv_rm_mmu.c
536
if (is_mmio_hpte(v, pte_r))
arch/powerpc/kvm/book3s_hv_rm_mmu.c
539
if (v & HPTE_V_ABSENT)
arch/powerpc/kvm/book3s_hv_rm_mmu.c
540
v = (v & ~HPTE_V_ABSENT) | HPTE_V_VALID;
arch/powerpc/kvm/book3s_hv_rm_mmu.c
541
hpret[0] = v;
arch/powerpc/kvm/book3s_hv_rm_mmu.c
680
unsigned long v, r, rb, mask, bits;
arch/powerpc/kvm/book3s_hv_rm_mmu.c
691
v = pte_v = be64_to_cpu(hpte[0]);
arch/powerpc/kvm/book3s_hv_rm_mmu.c
693
v = hpte_new_to_old_v(v, be64_to_cpu(hpte[1]));
arch/powerpc/kvm/book3s_hv_rm_mmu.c
694
if ((v & (HPTE_V_ABSENT | HPTE_V_VALID)) == 0 ||
arch/powerpc/kvm/book3s_hv_rm_mmu.c
695
((flags & H_AVPN) && (v & ~0x7fUL) != avpn)) {
arch/powerpc/kvm/book3s_hv_rm_mmu.c
716
if (v & HPTE_V_VALID) {
arch/powerpc/kvm/book3s_hv_rm_mmu.c
727
rb = compute_tlbie_rb(v, r, pte_index);
arch/powerpc/kvm/book3s_hv_rm_mmu.c
738
if (is_mmio_hpte(v, pte_r))
arch/powerpc/kvm/book3s_hv_rm_mmu.c
750
unsigned long v, r;
arch/powerpc/kvm/book3s_hv_rm_mmu.c
765
v = be64_to_cpu(hpte[0]) & ~HPTE_V_HVLOCK;
arch/powerpc/kvm/book3s_hv_rm_mmu.c
768
v = hpte_new_to_old_v(v, r);
arch/powerpc/kvm/book3s_hv_rm_mmu.c
771
if (v & HPTE_V_ABSENT) {
arch/powerpc/kvm/book3s_hv_rm_mmu.c
772
v &= ~HPTE_V_ABSENT;
arch/powerpc/kvm/book3s_hv_rm_mmu.c
773
v |= HPTE_V_VALID;
arch/powerpc/kvm/book3s_hv_rm_mmu.c
775
if (v & HPTE_V_VALID) {
arch/powerpc/kvm/book3s_hv_rm_mmu.c
779
kvmppc_set_gpr(vcpu, 4 + i * 2, v);
arch/powerpc/kvm/book3s_hv_rm_mmu.c
791
unsigned long v, r, gr;
arch/powerpc/kvm/book3s_hv_rm_mmu.c
805
v = be64_to_cpu(hpte[0]);
arch/powerpc/kvm/book3s_hv_rm_mmu.c
807
if (!(v & (HPTE_V_VALID | HPTE_V_ABSENT)))
arch/powerpc/kvm/book3s_hv_rm_mmu.c
815
if (v & HPTE_V_VALID) {
arch/powerpc/kvm/book3s_hv_rm_mmu.c
819
rmap = revmap_for_hpte(kvm, v, gr, NULL, NULL);
arch/powerpc/kvm/book3s_hv_rm_mmu.c
830
unlock_hpte(hpte, v & ~HPTE_V_HVLOCK);
arch/powerpc/kvm/book3s_hv_rm_mmu.c
840
unsigned long v, r, gr;
arch/powerpc/kvm/book3s_hv_rm_mmu.c
853
v = be64_to_cpu(hpte[0]);
arch/powerpc/kvm/book3s_hv_rm_mmu.c
855
if (!(v & (HPTE_V_VALID | HPTE_V_ABSENT)))
arch/powerpc/kvm/book3s_hv_rm_mmu.c
863
if (v & HPTE_V_VALID) {
arch/powerpc/kvm/book3s_hv_rm_mmu.c
872
kvmppc_set_dirty_from_hpte(kvm, v, gr);
arch/powerpc/kvm/book3s_hv_rm_mmu.c
878
unlock_hpte(hpte, v & ~HPTE_V_HVLOCK);
arch/powerpc/kvm/book3s_pr_papr.c
110
if (copy_to_user((void __user *)pteg, &v, sizeof(v)))
arch/powerpc/kvm/book3s_pr_papr.c
157
unsigned long v = 0;
arch/powerpc/kvm/book3s_pr_papr.c
195
if (copy_to_user((void __user *)pteg, &v, sizeof(v))) {
arch/powerpc/kvm/book3s_pr_papr.c
219
unsigned long rb, pteg, r, v;
arch/powerpc/kvm/book3s_pr_papr.c
236
v = pte[0];
arch/powerpc/kvm/book3s_pr_papr.c
246
rb = compute_tlbie_rb(v, r, pte_index);
arch/powerpc/kvm/book3s_pr_papr.c
91
unsigned long v = 0, pteg, rb;
arch/powerpc/kvm/powerpc.c
50
int kvm_arch_vcpu_runnable(struct kvm_vcpu *v)
arch/powerpc/kvm/powerpc.c
52
return !!(v->arch.pending_exceptions) || kvm_request_pending(v);
arch/powerpc/kvm/test-guest-state-buffer.c
30
__vector128 v;
arch/powerpc/kvm/test-guest-state-buffer.c
60
rc = kvmppc_gse_put_vector128(gsb, KVMPPC_GSID_VSRS(0), &u.v);
arch/powerpc/kvm/test-guest-state-buffer.c
85
kvmppc_gse_get_vector128(curr, &u.v);
arch/powerpc/lib/sstep.c
1024
store_vsrn(reg + i, &buf[j].v);
arch/powerpc/lib/sstep.c
1037
store_vsrn(reg + i, &buf[j].v);
arch/powerpc/lib/sstep.c
1042
buf[j].v = current->thread.vr_state.vr[reg - 32 + i];
arch/powerpc/lib/sstep.c
1294
unsigned long v, int size)
arch/powerpc/lib/sstep.c
1296
unsigned long long res = v ^ (v >> 8);
arch/powerpc/lib/sstep.c
683
__vector128 v;
arch/powerpc/lib/sstep.c
701
put_vr(rn, &u.v);
arch/powerpc/lib/sstep.c
703
current->thread.vr_state.vr[rn] = u.v;
arch/powerpc/lib/sstep.c
713
__vector128 v;
arch/powerpc/lib/sstep.c
727
get_vr(rn, &u.v);
arch/powerpc/lib/sstep.c
729
u.v = current->thread.vr_state.vr[rn];
arch/powerpc/lib/sstep.c
827
unsigned long v = *(unsigned long *)(mem + 8);
arch/powerpc/lib/sstep.c
828
reg->d[IS_BE] = !rev ? v : byterev_8(v);
arch/powerpc/lib/sstep.c
978
load_vsrn(reg + i, &buf[j].v);
arch/powerpc/lib/sstep.c
991
load_vsrn(reg + i, &buf[j].v);
arch/powerpc/lib/sstep.c
996
current->thread.vr_state.vr[reg - 32 + i] = buf[j].v;
arch/powerpc/mm/book3s64/hash_native.c
240
unsigned long *word = (unsigned long *)&hptep->v;
arch/powerpc/mm/book3s64/hash_native.c
255
unsigned long *word = (unsigned long *)&hptep->v;
arch/powerpc/mm/book3s64/hash_native.c
279
if (! (be64_to_cpu(hptep->v) & HPTE_V_VALID)) {
arch/powerpc/mm/book3s64/hash_native.c
282
if (! (be64_to_cpu(hptep->v) & HPTE_V_VALID))
arch/powerpc/mm/book3s64/hash_native.c
316
hptep->v = cpu_to_be64(hpte_v);
arch/powerpc/mm/book3s64/hash_native.c
341
hpte_v = be64_to_cpu(hptep->v);
arch/powerpc/mm/book3s64/hash_native.c
346
hpte_v = be64_to_cpu(hptep->v);
arch/powerpc/mm/book3s64/hash_native.c
364
hptep->v = 0;
arch/powerpc/mm/book3s64/hash_native.c
537
VM_WARN_ON(!(be64_to_cpu(hptep->v) & HPTE_V_BOLTED));
arch/powerpc/mm/book3s64/hash_native.c
540
hptep->v = 0;
arch/powerpc/mm/book3s64/hash_native.c
574
hptep->v = 0;
arch/powerpc/mm/book3s64/hash_native.c
637
hptep->v = 0;
arch/powerpc/mm/book3s64/hash_native.c
664
unsigned long hpte_v = be64_to_cpu(hpte->v);
arch/powerpc/mm/book3s64/hash_native.c
755
hpte_v = be64_to_cpu(hptep->v);
arch/powerpc/mm/book3s64/hash_native.c
763
hptep->v = 0;
arch/powerpc/mm/book3s64/hash_native.c
816
hptep->v = 0;
arch/powerpc/mm/book3s64/slb.c
214
unsigned long e, v;
arch/powerpc/mm/book3s64/slb.c
224
asm volatile("slbmfev %0,%1" : "=r" (v) : "r" (i));
arch/powerpc/mm/book3s64/slb.c
226
slb_ptr->vsid = v;
arch/powerpc/mm/book3s64/slb.c
234
unsigned long e, v;
arch/powerpc/mm/book3s64/slb.c
244
v = slb_ptr->vsid;
arch/powerpc/mm/book3s64/slb.c
247
if (!e && !v)
arch/powerpc/mm/book3s64/slb.c
250
pr_err("%02d %016lx %016lx %s\n", i, e, v,
arch/powerpc/mm/book3s64/slb.c
256
llp = v & SLB_VSID_LLP;
arch/powerpc/mm/book3s64/slb.c
257
if (v & SLB_VSID_B_1T) {
arch/powerpc/mm/book3s64/slb.c
260
(v & ~SLB_VSID_B) >> SLB_VSID_SHIFT_1T, llp);
arch/powerpc/mm/book3s64/slb.c
264
(v & ~SLB_VSID_B) >> SLB_VSID_SHIFT, llp);
arch/powerpc/mm/ioremap_32.c
20
unsigned long v;
arch/powerpc/mm/ioremap_32.c
61
v = p_block_mapped(p);
arch/powerpc/mm/ioremap_32.c
62
if (v)
arch/powerpc/mm/ioremap_32.c
63
return (void __iomem *)v + offset;
arch/powerpc/mm/mem.c
244
unsigned long v = __fix_to_virt(FIX_KMAP_END);
arch/powerpc/mm/mem.c
247
for (; v < end; v += PAGE_SIZE)
arch/powerpc/mm/mem.c
248
map_kernel_page(v, 0, __pgprot(0)); /* XXX gross */
arch/powerpc/mm/nohash/8xx.c
120
unsigned long v = PAGE_OFFSET + offset;
arch/powerpc/mm/nohash/8xx.c
126
for (; p < ALIGN(p, SZ_512K) && p < top && !err; p += SZ_16K, v += SZ_16K)
arch/powerpc/mm/nohash/8xx.c
127
err = __early_map_kernel_hugepage(v, p, prot, MMU_PAGE_16K, new);
arch/powerpc/mm/nohash/8xx.c
128
for (; p < ALIGN(p, SZ_8M) && p < top && !err; p += SZ_512K, v += SZ_512K)
arch/powerpc/mm/nohash/8xx.c
129
err = __early_map_kernel_hugepage(v, p, prot, MMU_PAGE_512K, new);
arch/powerpc/mm/nohash/8xx.c
130
for (; p < ALIGN_DOWN(top, SZ_8M) && p < top && !err; p += SZ_8M, v += SZ_8M)
arch/powerpc/mm/nohash/8xx.c
131
err = __early_map_kernel_hugepage(v, p, prot, MMU_PAGE_8M, new);
arch/powerpc/mm/nohash/8xx.c
132
for (; p < ALIGN_DOWN(top, SZ_512K) && p < top && !err; p += SZ_512K, v += SZ_512K)
arch/powerpc/mm/nohash/8xx.c
133
err = __early_map_kernel_hugepage(v, p, prot, MMU_PAGE_512K, new);
arch/powerpc/mm/nohash/8xx.c
134
for (; p < ALIGN_DOWN(top, SZ_16K) && p < top && !err; p += SZ_16K, v += SZ_16K)
arch/powerpc/mm/nohash/8xx.c
135
err = __early_map_kernel_hugepage(v, p, prot, MMU_PAGE_16K, new);
arch/powerpc/mm/nohash/8xx.c
138
flush_tlb_kernel_range(PAGE_OFFSET + v, PAGE_OFFSET + top);
arch/powerpc/mm/pgtable_32.c
103
v = PAGE_OFFSET + s;
arch/powerpc/mm/pgtable_32.c
106
ktext = core_kernel_text(v);
arch/powerpc/mm/pgtable_32.c
107
map_kernel_page(v, p, ktext ? PAGE_KERNEL_X : PAGE_KERNEL);
arch/powerpc/mm/pgtable_32.c
108
v += PAGE_SIZE;
arch/powerpc/mm/pgtable_32.c
98
unsigned long v, s;
arch/powerpc/mm/ptdump/bats.c
60
static int bats_show(struct seq_file *m, void *v)
arch/powerpc/mm/ptdump/hashpagetable.c
183
static void dump_hpte_info(struct pg_state *st, unsigned long ea, u64 v, u64 r,
arch/powerpc/mm/ptdump/hashpagetable.c
193
seq_printf(st->seq, "AVPN:%llx\t", HPTE_V_AVPN_VAL(v));
arch/powerpc/mm/ptdump/hashpagetable.c
194
dump_flag_info(st, v_flag_array, v, ARRAY_SIZE(v_flag_array));
arch/powerpc/mm/ptdump/hashpagetable.c
206
static int native_find(unsigned long ea, int psize, bool primary, u64 *v, u64
arch/powerpc/mm/ptdump/hashpagetable.c
228
hpte_v = be64_to_cpu(hptep->v);
arch/powerpc/mm/ptdump/hashpagetable.c
232
*v = be64_to_cpu(hptep->v);
arch/powerpc/mm/ptdump/hashpagetable.c
235
*v = hpte_new_to_old_v(*v, *r);
arch/powerpc/mm/ptdump/hashpagetable.c
245
static int pseries_find(unsigned long ea, int psize, bool primary, u64 *v, u64 *r)
arch/powerpc/mm/ptdump/hashpagetable.c
248
unsigned long v;
arch/powerpc/mm/ptdump/hashpagetable.c
273
if (HPTE_V_COMPARE(ptes[j].v, want_v) &&
arch/powerpc/mm/ptdump/hashpagetable.c
274
(ptes[j].v & HPTE_V_VALID)) {
arch/powerpc/mm/ptdump/hashpagetable.c
276
*v = ptes[j].v;
arch/powerpc/mm/ptdump/hashpagetable.c
322
static int base_hpte_find(unsigned long ea, int psize, bool primary, u64 *v,
arch/powerpc/mm/ptdump/hashpagetable.c
326
return pseries_find(ea, psize, primary, v, r);
arch/powerpc/mm/ptdump/hashpagetable.c
328
return native_find(ea, psize, primary, v, r);
arch/powerpc/mm/ptdump/hashpagetable.c
334
u64 v = 0, r = 0;
arch/powerpc/mm/ptdump/hashpagetable.c
342
slot = base_hpte_find(ea, psize, true, &v, &r);
arch/powerpc/mm/ptdump/hashpagetable.c
346
slot = base_hpte_find(ea, psize, false, &v, &r);
arch/powerpc/mm/ptdump/hashpagetable.c
360
if ((v & HPTE_V_LARGE) == HPTE_V_LARGE) {
arch/powerpc/mm/ptdump/hashpagetable.c
376
dump_hpte_info(st, ea, v, r, rpn, base_psize, actual_psize, lp_bits);
arch/powerpc/mm/ptdump/hashpagetable.c
521
static int ptdump_show(struct seq_file *m, void *v)
arch/powerpc/mm/ptdump/ptdump.c
334
static int ptdump_show(struct seq_file *m, void *v)
arch/powerpc/mm/ptdump/segment_regs.c
29
static int sr_show(struct seq_file *m, void *v)
arch/powerpc/perf/hv-24x7.c
40
#define DOMAIN(n, v, x, c) \
arch/powerpc/perf/hv-24x7.c
54
#define DOMAIN(n, v, x, c) \
arch/powerpc/perf/hv-24x7.h
8
#define DOMAIN(n, v, x, c) HV_PERF_DOMAIN_##n = v,
arch/powerpc/perf/isa207-common.h
149
#define CNST_FAB_MATCH_VAL(v) (((v) & EVENT_THR_CTL_MASK) << 56)
arch/powerpc/perf/isa207-common.h
153
#define CNST_THRESH_VAL(v) (((v) & EVENT_THRESH_MASK) << 32)
arch/powerpc/perf/isa207-common.h
156
#define CNST_THRESH_CTL_SEL_VAL(v) (((v) & 0x7ffull) << 32)
arch/powerpc/perf/isa207-common.h
159
#define p10_CNST_THRESH_CMP_VAL(v) (((v) & 0x7ffull) << 43)
arch/powerpc/perf/isa207-common.h
162
#define CNST_EBB_VAL(v) (((v) & EVENT_EBB_MASK) << 24)
arch/powerpc/perf/isa207-common.h
165
#define CNST_IFM_VAL(v) (((v) & EVENT_IFM_MASK) << 25)
arch/powerpc/perf/isa207-common.h
168
#define CNST_L1_QUAL_VAL(v) (((v) & 3) << 22)
arch/powerpc/perf/isa207-common.h
171
#define CNST_SAMPLE_VAL(v) (((v) & EVENT_SAMPLE_MASK) << 16)
arch/powerpc/perf/isa207-common.h
174
#define CNST_CACHE_GROUP_VAL(v) (((v) & 0xffull) << 55)
arch/powerpc/perf/isa207-common.h
179
#define CNST_L2L3_GROUP_VAL(v) (((v) & 0x1full) << 55)
arch/powerpc/perf/isa207-common.h
182
#define CNST_RADIX_SCOPE_GROUP_VAL(v) (((v) & 0x1ull) << 21)
arch/powerpc/perf/isa207-common.h
234
#define MMCRA_THR_CTR_MANT(v) (((v) >> MMCRA_THR_CTR_MANT_SHIFT) &\
arch/powerpc/perf/isa207-common.h
239
#define MMCRA_THR_CTR_EXP(v) (((v) >> MMCRA_THR_CTR_EXP_SHIFT) &\
arch/powerpc/perf/isa207-common.h
243
#define P10_MMCRA_THR_CTR_MANT(v) (((v) >> MMCRA_THR_CTR_MANT_SHIFT) &\
arch/powerpc/perf/isa207-common.h
44
#define EVENT_COMBINE(v) (((v) >> EVENT_COMBINE_SHIFT) & EVENT_COMBINE_MASK)
arch/powerpc/perf/isa207-common.h
75
#define p9_EVENT_COMBINE(v) (((v) >> p9_EVENT_COMBINE_SHIFT) & p9_EVENT_COMBINE_MASK)
arch/powerpc/perf/isa207-common.h
78
#define p9_SDAR_MODE(v) (((v) >> p9_SDAR_MODE_SHIFT) & p9_SDAR_MODE_MASK)
arch/powerpc/perf/isa207-common.h
95
#define p10_SDAR_MODE(v) (((v) >> p10_SDAR_MODE_SHIFT) & \
arch/powerpc/platforms/52xx/mpc52xx_gpt.c
284
mpc52xx_gpt_gpio_set(struct gpio_chip *gc, unsigned int gpio, int v)
arch/powerpc/platforms/52xx/mpc52xx_gpt.c
290
dev_dbg(gpt->dev, "%s: gpio:%d v:%d\n", __func__, gpio, v);
arch/powerpc/platforms/52xx/mpc52xx_gpt.c
291
r = v ? MPC52xx_GPT_MODE_GPIO_OUT_HIGH : MPC52xx_GPT_MODE_GPIO_OUT_LOW;
arch/powerpc/platforms/cell/spufs/coredump.c
44
static int match_context(const void *v, struct file *file, unsigned fd)
arch/powerpc/platforms/cell/spufs/spu_restore.c
125
fpcr = regs_spill[offset].v;
arch/powerpc/platforms/cell/spufs/spu_save.c
77
regs_spill[offset].v = spu_mffpscr();
arch/powerpc/platforms/cell/spufs/spu_utils.h
24
vector unsigned int v;
arch/powerpc/platforms/microwatt/rng.c
18
static int microwatt_get_random_darn(unsigned long *v)
arch/powerpc/platforms/microwatt/rng.c
28
*v = val;
arch/powerpc/platforms/pasemi/setup.c
382
unsigned long e, v;
arch/powerpc/platforms/pasemi/setup.c
388
asm volatile("slbmfev %0,%1" : "=r" (v) : "r" (i));
arch/powerpc/platforms/pasemi/setup.c
389
pr_err("%02d %016lx %016lx\n", i, e, v);
arch/powerpc/platforms/powermac/bootx_init.c
49
unsigned long v;
arch/powerpc/platforms/powermac/bootx_init.c
79
v = va_arg(args, unsigned long);
arch/powerpc/platforms/powermac/bootx_init.c
80
btext_drawhex(v);
arch/powerpc/platforms/powermac/pfunc_base.c
231
val = args->u[0].v << shift;
arch/powerpc/platforms/powermac/pfunc_base.c
251
val = args->u[0].v << shift;
arch/powerpc/platforms/powermac/pfunc_base.c
51
if (args && args->count && !args->u[0].v)
arch/powerpc/platforms/powermac/smp.c
102
#define PSURGE_QUAD_OUT(r, v) (out_8(quad_base + ((r) << 4) + 4, (v)))
arch/powerpc/platforms/powermac/smp.c
104
#define PSURGE_QUAD_BIS(r, v) (PSURGE_QUAD_OUT((r), PSURGE_QUAD_IN(r) | (v)))
arch/powerpc/platforms/powermac/smp.c
105
#define PSURGE_QUAD_BIC(r, v) (PSURGE_QUAD_OUT((r), PSURGE_QUAD_IN(r) & ~(v)))
arch/powerpc/platforms/powermac/smp.c
636
args.u[0].v = !freeze;
arch/powerpc/platforms/powernv/opal-xscom.c
58
__be64 v;
arch/powerpc/platforms/powernv/opal-xscom.c
61
rc = opal_xscom_read(chip, reg, (__be64 *)__pa(&v));
arch/powerpc/platforms/powernv/opal-xscom.c
66
*value = be64_to_cpu(v);
arch/powerpc/platforms/powernv/rng.c
150
static int __init pnv_get_random_long_early(unsigned long *v)
arch/powerpc/platforms/powernv/rng.c
166
return ppc_md.get_random_seed(v);
arch/powerpc/platforms/powernv/rng.c
187
unsigned long v;
arch/powerpc/platforms/powernv/rng.c
191
pnv_get_random_long_early(&v);
arch/powerpc/platforms/powernv/rng.c
52
static int pnv_get_random_darn(unsigned long *v)
arch/powerpc/platforms/powernv/rng.c
62
*v = val;
arch/powerpc/platforms/powernv/rng.c
84
int pnv_get_random_long(unsigned long *v)
arch/powerpc/platforms/powernv/rng.c
90
*v = rng_whiten(rng, in_be64(rng->regs));
arch/powerpc/platforms/powernv/rng.c
94
*v = rng_whiten(rng, __raw_rm_readq(rng->regs_real));
arch/powerpc/platforms/ps3/setup.c
41
void ps3_get_firmware_version(union ps3_firmware_version *v)
arch/powerpc/platforms/ps3/setup.c
43
*v = ps3_firmware_version;
arch/powerpc/platforms/pseries/lpar.c
560
static int vcpudispatch_stats_display(struct seq_file *p, void *v)
arch/powerpc/platforms/pseries/lpar.c
625
static int vcpudispatch_stats_freq_display(struct seq_file *p, void *v)
arch/powerpc/platforms/pseries/lparcfg.c
531
static int pseries_lparcfg_data(struct seq_file *m, void *v)
arch/powerpc/platforms/pseries/lparcfg.c
767
static int lparcfg_data(struct seq_file *m, void *v)
arch/powerpc/platforms/pseries/lparcfg.c
796
return pseries_lparcfg_data(m, v);
arch/powerpc/platforms/pseries/rng.c
16
static int pseries_get_random_long(unsigned long *v)
arch/powerpc/platforms/pseries/rng.c
21
*v = retbuf[0];
arch/powerpc/sysdev/dart.h
48
#define DART_OUT(r,v) (out_be32(DART_REG(r), (v)))
arch/powerpc/sysdev/mpic.c
301
#define mpic_write(b,r,v) _mpic_write(mpic->reg_type,&(b),(r),(v))
arch/powerpc/sysdev/mpic.c
303
#define mpic_ipi_write(i,v) _mpic_ipi_write(mpic,(i),(v))
arch/powerpc/sysdev/mpic.c
305
#define mpic_tm_write(i,v) _mpic_tm_write(mpic,(i),(v))
arch/powerpc/sysdev/mpic.c
307
#define mpic_cpu_write(i,v) _mpic_cpu_write(mpic,(i),(v))
arch/powerpc/sysdev/mpic.c
309
#define mpic_irq_write(s,r,v) _mpic_irq_write(mpic,(s),(r),(v))
arch/powerpc/xmon/xmon.c
1418
unsigned char v;
arch/powerpc/xmon/xmon.c
1426
if (mread(adrs+i, &v, 1) == 0) {
arch/powerpc/xmon/xmon.c
1430
fcs = FCS(fcs, v);
arch/powerpc/xmon/xmon.c
205
#define GETWORD(v) (((v)[3] << 24) + ((v)[2] << 16) + ((v)[1] << 8) + (v)[0])
arch/powerpc/xmon/xmon.c
207
#define GETWORD(v) (((v)[0] << 24) + ((v)[1] << 16) + ((v)[2] << 8) + (v)[3])
arch/powerpc/xmon/xmon.c
3219
unsigned char v;
arch/powerpc/xmon/xmon.c
3230
ok = mread(a, &v, 1);
arch/powerpc/xmon/xmon.c
3483
unsigned long v;
arch/powerpc/xmon/xmon.c
3558
v = 0;
arch/powerpc/xmon/xmon.c
3560
v = (v << 4) + d;
arch/powerpc/xmon/xmon.c
3565
*vp = v;
arch/riscv/include/asm/archrandom.h
17
static inline bool __must_check csr_seed_long(unsigned long *v)
arch/riscv/include/asm/archrandom.h
21
u16 *entropy = (u16 *)v;
arch/riscv/include/asm/archrandom.h
52
static inline size_t __must_check arch_get_random_longs(unsigned long *v, size_t max_longs)
arch/riscv/include/asm/archrandom.h
57
static inline size_t __must_check arch_get_random_seed_longs(unsigned long *v, size_t max_longs)
arch/riscv/include/asm/archrandom.h
66
if (riscv_has_extension_likely(RISCV_ISA_EXT_ZKR) && csr_seed_long(v))
arch/riscv/include/asm/atomic.h
101
c_type arch_atomic##prefix##_fetch_##op(c_type i, atomic##prefix##_t *v) \
arch/riscv/include/asm/atomic.h
106
: "+A" (v->counter), "=r" (ret) \
arch/riscv/include/asm/atomic.h
115
atomic##prefix##_t *v) \
arch/riscv/include/asm/atomic.h
117
return arch_atomic##prefix##_fetch_##op##_relaxed(i, v) c_op I; \
arch/riscv/include/asm/atomic.h
120
c_type arch_atomic##prefix##_##op##_return(c_type i, atomic##prefix##_t *v) \
arch/riscv/include/asm/atomic.h
122
return arch_atomic##prefix##_fetch_##op(i, v) c_op I; \
arch/riscv/include/asm/atomic.h
214
static __always_inline int arch_atomic_fetch_add_unless(atomic_t *v, int a, int u)
arch/riscv/include/asm/atomic.h
218
_arch_atomic_fetch_add_unless(prev, rc, v->counter, a, u, "w");
arch/riscv/include/asm/atomic.h
225
static __always_inline s64 arch_atomic64_fetch_add_unless(atomic64_t *v, s64 a, s64 u)
arch/riscv/include/asm/atomic.h
230
_arch_atomic_fetch_add_unless(prev, rc, v->counter, a, u, "d");
arch/riscv/include/asm/atomic.h
252
static __always_inline bool arch_atomic_inc_unless_negative(atomic_t *v)
arch/riscv/include/asm/atomic.h
256
_arch_atomic_inc_unless_negative(prev, rc, v->counter, "w");
arch/riscv/include/asm/atomic.h
27
static __always_inline int arch_atomic_read(const atomic_t *v)
arch/riscv/include/asm/atomic.h
278
static __always_inline bool arch_atomic_dec_unless_positive(atomic_t *v)
arch/riscv/include/asm/atomic.h
282
_arch_atomic_dec_unless_positive(prev, rc, v->counter, "w");
arch/riscv/include/asm/atomic.h
29
return READ_ONCE(v->counter);
arch/riscv/include/asm/atomic.h
304
static __always_inline int arch_atomic_dec_if_positive(atomic_t *v)
arch/riscv/include/asm/atomic.h
308
_arch_atomic_dec_if_positive(prev, rc, v->counter, "w");
arch/riscv/include/asm/atomic.h
31
static __always_inline void arch_atomic_set(atomic_t *v, int i)
arch/riscv/include/asm/atomic.h
316
static __always_inline bool arch_atomic64_inc_unless_negative(atomic64_t *v)
arch/riscv/include/asm/atomic.h
321
_arch_atomic_inc_unless_negative(prev, rc, v->counter, "d");
arch/riscv/include/asm/atomic.h
328
static __always_inline bool arch_atomic64_dec_unless_positive(atomic64_t *v)
arch/riscv/include/asm/atomic.h
33
WRITE_ONCE(v->counter, i);
arch/riscv/include/asm/atomic.h
333
_arch_atomic_dec_unless_positive(prev, rc, v->counter, "d");
arch/riscv/include/asm/atomic.h
340
static __always_inline s64 arch_atomic64_dec_if_positive(atomic64_t *v)
arch/riscv/include/asm/atomic.h
345
_arch_atomic_dec_if_positive(prev, rc, v->counter, "d");
arch/riscv/include/asm/atomic.h
38
static __always_inline s64 arch_atomic64_read(const atomic64_t *v)
arch/riscv/include/asm/atomic.h
40
return READ_ONCE(v->counter);
arch/riscv/include/asm/atomic.h
42
static __always_inline void arch_atomic64_set(atomic64_t *v, s64 i)
arch/riscv/include/asm/atomic.h
44
WRITE_ONCE(v->counter, i);
arch/riscv/include/asm/atomic.h
55
void arch_atomic##prefix##_##op(c_type i, atomic##prefix##_t *v) \
arch/riscv/include/asm/atomic.h
59
: "+A" (v->counter) \
arch/riscv/include/asm/atomic.h
90
atomic##prefix##_t *v) \
arch/riscv/include/asm/atomic.h
95
: "+A" (v->counter), "=r" (ret) \
arch/riscv/include/asm/barrier.h
54
#define __smp_store_release(p, v) \
arch/riscv/include/asm/barrier.h
58
WRITE_ONCE(*p, v); \
arch/riscv/include/asm/futex.h
95
: [r] "+r" (ret), [v] "=&r" (val), [u] "+m" (*uaddr), [t] "=&r" (tmp)
arch/riscv/include/asm/insn-def.h
170
#define RV_OPCODE(v) __ASM_STR(v)
arch/riscv/include/asm/insn-def.h
171
#define RV_FUNC3(v) __ASM_STR(v)
arch/riscv/include/asm/insn-def.h
172
#define RV_FUNC7(v) __ASM_STR(v)
arch/riscv/include/asm/insn-def.h
173
#define RV_SIMM12(v) __ASM_STR(v)
arch/riscv/include/asm/insn-def.h
174
#define RV_RD(v) __ASM_STR(v)
arch/riscv/include/asm/insn-def.h
175
#define RV_RS1(v) __ASM_STR(v)
arch/riscv/include/asm/insn-def.h
176
#define RV_RS2(v) __ASM_STR(v)
arch/riscv/include/asm/insn-def.h
177
#define __RV_REG(v) __ASM_STR(x ## v)
arch/riscv/include/asm/insn-def.h
178
#define RV___RD(v) __RV_REG(v)
arch/riscv/include/asm/insn-def.h
179
#define RV___RS1(v) __RV_REG(v)
arch/riscv/include/asm/insn-def.h
180
#define RV___RS2(v) __RV_REG(v)
arch/riscv/include/asm/io.h
55
#define __io_par(v) RISCV_FENCE(i, ior)
arch/riscv/include/asm/kvm_aia.h
109
int kvm_riscv_aia_aplic_set_attr(struct kvm *kvm, unsigned long type, u32 v);
arch/riscv/include/asm/kvm_aia.h
110
int kvm_riscv_aia_aplic_get_attr(struct kvm *kvm, unsigned long type, u32 *v);
arch/riscv/include/asm/mmio.h
119
#define writeb_relaxed(v, c) ({ __io_rbw(); writeb_cpu((v), (c)); __io_raw(); })
arch/riscv/include/asm/mmio.h
120
#define writew_relaxed(v, c) ({ __io_rbw(); writew_cpu((v), (c)); __io_raw(); })
arch/riscv/include/asm/mmio.h
121
#define writel_relaxed(v, c) ({ __io_rbw(); writel_cpu((v), (c)); __io_raw(); })
arch/riscv/include/asm/mmio.h
125
#define writeq_relaxed(v, c) ({ __io_rbw(); writeq_cpu((v), (c)); __io_raw(); })
arch/riscv/include/asm/mmio.h
135
#define __io_ar(v) RISCV_FENCE(i, ir)
arch/riscv/include/asm/mmio.h
143
#define writeb(v, c) ({ __io_bw(); writeb_cpu((v), (c)); __io_aw(); })
arch/riscv/include/asm/mmio.h
144
#define writew(v, c) ({ __io_bw(); writew_cpu((v), (c)); __io_aw(); })
arch/riscv/include/asm/mmio.h
145
#define writel(v, c) ({ __io_bw(); writel_cpu((v), (c)); __io_aw(); })
arch/riscv/include/asm/mmio.h
149
#define writeq(v, c) ({ __io_bw(); writeq_cpu((v), (c)); __io_aw(); })
arch/riscv/include/asm/mmio.h
92
#define writeb_cpu(v, c) ((void)__raw_writeb((v), (c)))
arch/riscv/include/asm/mmio.h
93
#define writew_cpu(v, c) ((void)__raw_writew((__force u16)cpu_to_le16(v), (c)))
arch/riscv/include/asm/mmio.h
94
#define writel_cpu(v, c) ((void)__raw_writel((__force u32)cpu_to_le32(v), (c)))
arch/riscv/include/asm/mmio.h
98
#define writeq_cpu(v, c) ((void)__raw_writeq((__force u64)cpu_to_le64(v), (c)))
arch/riscv/kernel/cpu.c
319
static void *c_next(struct seq_file *m, void *v, loff_t *pos)
arch/riscv/kernel/cpu.c
325
static void c_stop(struct seq_file *m, void *v)
arch/riscv/kernel/cpu.c
329
static int c_show(struct seq_file *m, void *v)
arch/riscv/kernel/cpu.c
331
unsigned long cpu_id = (unsigned long)v - 1;
arch/riscv/kernel/cpufeature.c
500
__RISCV_ISA_EXT_SUPERSET_VALIDATE(v, RISCV_ISA_EXT_v, riscv_v_exts, riscv_ext_vector_float_validate),
arch/riscv/kernel/module.c
100
ptrdiff_t offset = (void *)v - location;
arch/riscv/kernel/module.c
110
Elf_Addr v)
arch/riscv/kernel/module.c
112
ptrdiff_t offset = (void *)v - location;
arch/riscv/kernel/module.c
122
Elf_Addr v)
arch/riscv/kernel/module.c
124
ptrdiff_t offset = (void *)v - location;
arch/riscv/kernel/module.c
136
Elf_Addr v)
arch/riscv/kernel/module.c
138
ptrdiff_t offset = (void *)v - location;
arch/riscv/kernel/module.c
153
Elf_Addr v)
arch/riscv/kernel/module.c
155
ptrdiff_t offset = (void *)v - location;
arch/riscv/kernel/module.c
160
me->name, (long long)v, location);
arch/riscv/kernel/module.c
168
Elf_Addr v)
arch/riscv/kernel/module.c
174
return riscv_insn_rmw(location, 0xfffff, (v & 0xfff) << 20);
arch/riscv/kernel/module.c
178
Elf_Addr v)
arch/riscv/kernel/module.c
184
u32 imm11_5 = (v & 0xfe0) << (31 - 11);
arch/riscv/kernel/module.c
185
u32 imm4_0 = (v & 0x1f) << (11 - 4);
arch/riscv/kernel/module.c
191
Elf_Addr v)
arch/riscv/kernel/module.c
196
me->name, (long long)v, location);
arch/riscv/kernel/module.c
200
return riscv_insn_rmw(location, 0xfff, ((s32)v + 0x800) & 0xfffff000);
arch/riscv/kernel/module.c
204
Elf_Addr v)
arch/riscv/kernel/module.c
207
s32 hi20 = ((s32)v + 0x800) & 0xfffff000;
arch/riscv/kernel/module.c
208
s32 lo12 = ((s32)v - hi20);
arch/riscv/kernel/module.c
214
Elf_Addr v)
arch/riscv/kernel/module.c
217
s32 hi20 = ((s32)v + 0x800) & 0xfffff000;
arch/riscv/kernel/module.c
218
s32 lo12 = ((s32)v - hi20);
arch/riscv/kernel/module.c
226
Elf_Addr v)
arch/riscv/kernel/module.c
228
ptrdiff_t offset = (void *)v - location;
arch/riscv/kernel/module.c
232
offset = (void *)module_emit_got_entry(me, v) - location;
arch/riscv/kernel/module.c
236
me->name, (long long)v, location);
arch/riscv/kernel/module.c
244
Elf_Addr v)
arch/riscv/kernel/module.c
246
ptrdiff_t offset = (void *)v - location;
arch/riscv/kernel/module.c
252
offset = (void *)module_emit_plt_entry(me, v) - location;
arch/riscv/kernel/module.c
256
me->name, (long long)v, location);
arch/riscv/kernel/module.c
268
Elf_Addr v)
arch/riscv/kernel/module.c
270
ptrdiff_t offset = (void *)v - location;
arch/riscv/kernel/module.c
276
me->name, (long long)v, location);
arch/riscv/kernel/module.c
287
Elf_Addr v)
arch/riscv/kernel/module.c
293
Elf_Addr v)
arch/riscv/kernel/module.c
301
static int apply_r_riscv_add8_rela(struct module *me, void *location, Elf_Addr v)
arch/riscv/kernel/module.c
303
*(u8 *)location += (u8)v;
arch/riscv/kernel/module.c
308
Elf_Addr v)
arch/riscv/kernel/module.c
310
*(u16 *)location += (u16)v;
arch/riscv/kernel/module.c
315
Elf_Addr v)
arch/riscv/kernel/module.c
317
*(u32 *)location += (u32)v;
arch/riscv/kernel/module.c
322
Elf_Addr v)
arch/riscv/kernel/module.c
324
*(u64 *)location += (u64)v;
arch/riscv/kernel/module.c
328
static int apply_r_riscv_sub8_rela(struct module *me, void *location, Elf_Addr v)
arch/riscv/kernel/module.c
330
*(u8 *)location -= (u8)v;
arch/riscv/kernel/module.c
335
Elf_Addr v)
arch/riscv/kernel/module.c
337
*(u16 *)location -= (u16)v;
arch/riscv/kernel/module.c
342
Elf_Addr v)
arch/riscv/kernel/module.c
344
*(u32 *)location -= (u32)v;
arch/riscv/kernel/module.c
349
Elf_Addr v)
arch/riscv/kernel/module.c
351
*(u64 *)location -= (u64)v;
arch/riscv/kernel/module.c
356
Elf_Addr v)
arch/riscv/kernel/module.c
363
static int tls_not_supported(struct module *me, void *location, Elf_Addr v)
arch/riscv/kernel/module.c
37
int (*reloc_handler)(struct module *me, void *location, Elf_Addr v);
arch/riscv/kernel/module.c
370
static int apply_r_riscv_sub6_rela(struct module *me, void *location, Elf_Addr v)
arch/riscv/kernel/module.c
373
u8 value = v;
arch/riscv/kernel/module.c
379
static int apply_r_riscv_set6_rela(struct module *me, void *location, Elf_Addr v)
arch/riscv/kernel/module.c
382
u8 value = v;
arch/riscv/kernel/module.c
388
static int apply_r_riscv_set8_rela(struct module *me, void *location, Elf_Addr v)
arch/riscv/kernel/module.c
390
*(u8 *)location = (u8)v;
arch/riscv/kernel/module.c
395
Elf_Addr v)
arch/riscv/kernel/module.c
397
*(u16 *)location = (u16)v;
arch/riscv/kernel/module.c
402
Elf_Addr v)
arch/riscv/kernel/module.c
404
*(u32 *)location = (u32)v;
arch/riscv/kernel/module.c
409
Elf_Addr v)
arch/riscv/kernel/module.c
411
*(u32 *)location = v - (uintptr_t)location;
arch/riscv/kernel/module.c
416
Elf_Addr v)
arch/riscv/kernel/module.c
418
ptrdiff_t offset = (void *)v - location;
arch/riscv/kernel/module.c
423
offset = (void *)module_emit_plt_entry(me, v) - location;
arch/riscv/kernel/module.c
426
me->name, (long long)v, location);
arch/riscv/kernel/module.c
435
static int apply_r_riscv_set_uleb128(struct module *me, void *location, Elf_Addr v)
arch/riscv/kernel/module.c
437
*(long *)location = v;
arch/riscv/kernel/module.c
441
static int apply_r_riscv_sub_uleb128(struct module *me, void *location, Elf_Addr v)
arch/riscv/kernel/module.c
443
*(long *)location -= v;
arch/riscv/kernel/module.c
656
unsigned int hashtable_bits, Elf_Addr v,
arch/riscv/kernel/module.c
673
entry->value = v;
arch/riscv/kernel/module.c
771
int (*handler)(struct module *me, void *location, Elf_Addr v);
arch/riscv/kernel/module.c
776
Elf_Addr v;
arch/riscv/kernel/module.c
80
static int apply_r_riscv_32_rela(struct module *me, void *location, Elf_Addr v)
arch/riscv/kernel/module.c
82
if (v != (u32)v) {
arch/riscv/kernel/module.c
821
v = sym->st_value + rel[i].r_addend;
arch/riscv/kernel/module.c
84
me->name, (long long)v);
arch/riscv/kernel/module.c
855
v = lo12;
arch/riscv/kernel/module.c
87
*(u32 *)location = v;
arch/riscv/kernel/module.c
880
hashtable_bits, v,
arch/riscv/kernel/module.c
884
res = handler(me, location, v);
arch/riscv/kernel/module.c
91
static int apply_r_riscv_64_rela(struct module *me, void *location, Elf_Addr v)
arch/riscv/kernel/module.c
93
*(u64 *)location = v;
arch/riscv/kernel/module.c
98
Elf_Addr v)
arch/riscv/kernel/setup.c
393
unsigned long v, void *p)
arch/riscv/kernel/sys_hwprobe.c
94
if (has_vector() && riscv_isa_extension_available(NULL, v))
arch/riscv/kvm/aia_aplic.c
531
int kvm_riscv_aia_aplic_set_attr(struct kvm *kvm, unsigned long type, u32 v)
arch/riscv/kvm/aia_aplic.c
538
rc = aplic_mmio_write_offset(kvm, type, v);
arch/riscv/kvm/aia_aplic.c
545
int kvm_riscv_aia_aplic_get_attr(struct kvm *kvm, unsigned long type, u32 *v)
arch/riscv/kvm/aia_aplic.c
552
rc = aplic_mmio_read_offset(kvm, type, v);
arch/riscv/kvm/aia_device.c
305
unsigned long v, type = (unsigned long)attr->attr;
arch/riscv/kvm/aia_device.c
354
if (copy_from_user(&v, uaddr, sizeof(v)))
arch/riscv/kvm/aia_device.c
358
r = kvm_riscv_aia_imsic_rw_attr(dev->kvm, type, true, &v);
arch/riscv/kvm/aia_device.c
373
unsigned long v, type = (unsigned long)attr->attr;
arch/riscv/kvm/aia_device.c
424
if (copy_from_user(&v, uaddr, sizeof(v)))
arch/riscv/kvm/aia_device.c
428
r = kvm_riscv_aia_imsic_rw_attr(dev->kvm, type, false, &v);
arch/riscv/kvm/aia_device.c
433
if (copy_to_user(uaddr, &v, sizeof(v)))
arch/riscv/kvm/tlb.c
199
struct kvm_vmid *v = &vcpu->kvm->arch.vmid;
arch/riscv/kvm/tlb.c
200
unsigned long vmid = READ_ONCE(v->vmid);
arch/riscv/kvm/tlb.c
210
struct kvm_vmid *v = &vcpu->kvm->arch.vmid;
arch/riscv/kvm/tlb.c
211
unsigned long vmid = READ_ONCE(v->vmid);
arch/riscv/kvm/vcpu.c
367
struct kvm_vcpu_arch *v = &vcpu->arch;
arch/riscv/kvm/vcpu.c
378
v->irqs_pending_mask))
arch/riscv/kvm/vcpu.c
379
set_bit(IRQ_VS_SOFT, v->irqs_pending);
arch/riscv/kvm/vcpu.c
382
v->irqs_pending_mask))
arch/riscv/kvm/vcpu.c
383
clear_bit(IRQ_VS_SOFT, v->irqs_pending);
arch/riscv/kvm/vcpu.c
390
!test_and_set_bit(IRQ_PMU_OVF, v->irqs_pending_mask))
arch/riscv/kvm/vcpu.c
391
clear_bit(IRQ_PMU_OVF, v->irqs_pending);
arch/riscv/kvm/vcpu_onereg.c
1119
if (!riscv_isa_extension_available(vcpu->arch.isa, v))
arch/riscv/kvm/vcpu_vector.c
152
if (!riscv_isa_extension_available(isa, v))
arch/riscv/kvm/vcpu_vector.c
178
if (!riscv_isa_extension_available(isa, v))
arch/riscv/kvm/vcpu_vector.c
28
if (riscv_isa_extension_available(isa, v)) {
arch/riscv/kvm/vcpu_vector.c
47
if (riscv_isa_extension_available(isa, v))
arch/riscv/kvm/vcpu_vector.c
57
if (riscv_isa_extension_available(isa, v))
arch/riscv/kvm/vcpu_vector.c
66
if (riscv_isa_extension_available(NULL, v))
arch/riscv/kvm/vcpu_vector.c
72
if (riscv_isa_extension_available(NULL, v))
arch/riscv/kvm/vmid.c
122
kvm_for_each_vcpu(i, v, vcpu->kvm)
arch/riscv/kvm/vmid.c
123
kvm_make_request(KVM_REQ_UPDATE_HGATP, v);
arch/riscv/kvm/vmid.c
74
struct kvm_vcpu *v;
arch/riscv/mm/ptdump.c
413
static int ptdump_show(struct seq_file *m, void *v)
arch/s390/boot/string.c
44
void *memset64(uint64_t *s, uint64_t v, size_t count)
arch/s390/boot/string.c
49
*xs++ = v;
arch/s390/include/asm/archrandom.h
22
static inline size_t __must_check arch_get_random_longs(unsigned long *v, size_t max_longs)
arch/s390/include/asm/archrandom.h
27
static inline size_t __must_check arch_get_random_seed_longs(unsigned long *v, size_t max_longs)
arch/s390/include/asm/archrandom.h
31
cpacf_trng(NULL, 0, (u8 *)v, max_longs * sizeof(*v));
arch/s390/include/asm/archrandom.h
32
atomic64_add(max_longs * sizeof(*v), &s390_arch_random_counter);
arch/s390/include/asm/atomic.h
105
static __always_inline int arch_atomic_xchg(atomic_t *v, int new)
arch/s390/include/asm/atomic.h
107
return arch_xchg(&v->counter, new);
arch/s390/include/asm/atomic.h
111
static __always_inline int arch_atomic_cmpxchg(atomic_t *v, int old, int new)
arch/s390/include/asm/atomic.h
113
return arch_cmpxchg(&v->counter, old, new);
arch/s390/include/asm/atomic.h
117
static __always_inline bool arch_atomic_try_cmpxchg(atomic_t *v, int *old, int new)
arch/s390/include/asm/atomic.h
119
return arch_try_cmpxchg(&v->counter, old, new);
arch/s390/include/asm/atomic.h
125
static __always_inline s64 arch_atomic64_read(const atomic64_t *v)
arch/s390/include/asm/atomic.h
127
return __atomic64_read((long *)&v->counter);
arch/s390/include/asm/atomic.h
131
static __always_inline void arch_atomic64_set(atomic64_t *v, s64 i)
arch/s390/include/asm/atomic.h
133
__atomic64_set((long *)&v->counter, i);
arch/s390/include/asm/atomic.h
137
static __always_inline s64 arch_atomic64_add_return(s64 i, atomic64_t *v)
arch/s390/include/asm/atomic.h
139
return __atomic64_add_barrier(i, (long *)&v->counter) + i;
arch/s390/include/asm/atomic.h
143
static __always_inline s64 arch_atomic64_fetch_add(s64 i, atomic64_t *v)
arch/s390/include/asm/atomic.h
145
return __atomic64_add_barrier(i, (long *)&v->counter);
arch/s390/include/asm/atomic.h
149
static __always_inline void arch_atomic64_add(s64 i, atomic64_t *v)
arch/s390/include/asm/atomic.h
151
__atomic64_add(i, (long *)&v->counter);
arch/s390/include/asm/atomic.h
155
static __always_inline void arch_atomic64_inc(atomic64_t *v)
arch/s390/include/asm/atomic.h
157
__atomic64_add_const(1, (long *)&v->counter);
arch/s390/include/asm/atomic.h
161
static __always_inline void arch_atomic64_dec(atomic64_t *v)
arch/s390/include/asm/atomic.h
163
__atomic64_add_const(-1, (long *)&v->counter);
arch/s390/include/asm/atomic.h
167
static __always_inline bool arch_atomic64_sub_and_test(s64 i, atomic64_t *v)
arch/s390/include/asm/atomic.h
169
return __atomic64_add_and_test_barrier(-i, (long *)&v->counter);
arch/s390/include/asm/atomic.h
173
static __always_inline bool arch_atomic64_dec_and_test(atomic64_t *v)
arch/s390/include/asm/atomic.h
175
return __atomic64_add_const_and_test_barrier(-1, (long *)&v->counter);
arch/s390/include/asm/atomic.h
179
static __always_inline bool arch_atomic64_inc_and_test(atomic64_t *v)
arch/s390/include/asm/atomic.h
18
static __always_inline int arch_atomic_read(const atomic_t *v)
arch/s390/include/asm/atomic.h
181
return __atomic64_add_const_and_test_barrier(1, (long *)&v->counter);
arch/s390/include/asm/atomic.h
185
static __always_inline s64 arch_atomic64_xchg(atomic64_t *v, s64 new)
arch/s390/include/asm/atomic.h
187
return arch_xchg(&v->counter, new);
arch/s390/include/asm/atomic.h
191
static __always_inline s64 arch_atomic64_cmpxchg(atomic64_t *v, s64 old, s64 new)
arch/s390/include/asm/atomic.h
193
return arch_cmpxchg(&v->counter, old, new);
arch/s390/include/asm/atomic.h
197
static __always_inline bool arch_atomic64_try_cmpxchg(atomic64_t *v, s64 *old, s64 new)
arch/s390/include/asm/atomic.h
199
return arch_try_cmpxchg(&v->counter, old, new);
arch/s390/include/asm/atomic.h
20
return __atomic_read(&v->counter);
arch/s390/include/asm/atomic.h
204
static __always_inline void arch_atomic64_##op(s64 i, atomic64_t *v) \
arch/s390/include/asm/atomic.h
206
__atomic64_##op(i, (long *)&v->counter); \
arch/s390/include/asm/atomic.h
208
static __always_inline long arch_atomic64_fetch_##op(s64 i, atomic64_t *v) \
arch/s390/include/asm/atomic.h
210
return __atomic64_##op##_barrier(i, (long *)&v->counter); \
arch/s390/include/asm/atomic.h
24
static __always_inline void arch_atomic_set(atomic_t *v, int i)
arch/s390/include/asm/atomic.h
26
__atomic_set(&v->counter, i);
arch/s390/include/asm/atomic.h
30
static __always_inline int arch_atomic_add_return(int i, atomic_t *v)
arch/s390/include/asm/atomic.h
32
return __atomic_add_barrier(i, &v->counter) + i;
arch/s390/include/asm/atomic.h
36
static __always_inline int arch_atomic_fetch_add(int i, atomic_t *v)
arch/s390/include/asm/atomic.h
38
return __atomic_add_barrier(i, &v->counter);
arch/s390/include/asm/atomic.h
42
static __always_inline void arch_atomic_add(int i, atomic_t *v)
arch/s390/include/asm/atomic.h
44
__atomic_add(i, &v->counter);
arch/s390/include/asm/atomic.h
48
static __always_inline void arch_atomic_inc(atomic_t *v)
arch/s390/include/asm/atomic.h
50
__atomic_add_const(1, &v->counter);
arch/s390/include/asm/atomic.h
54
static __always_inline void arch_atomic_dec(atomic_t *v)
arch/s390/include/asm/atomic.h
56
__atomic_add_const(-1, &v->counter);
arch/s390/include/asm/atomic.h
60
static __always_inline bool arch_atomic_sub_and_test(int i, atomic_t *v)
arch/s390/include/asm/atomic.h
62
return __atomic_add_and_test_barrier(-i, &v->counter);
arch/s390/include/asm/atomic.h
66
static __always_inline bool arch_atomic_dec_and_test(atomic_t *v)
arch/s390/include/asm/atomic.h
68
return __atomic_add_const_and_test_barrier(-1, &v->counter);
arch/s390/include/asm/atomic.h
72
static __always_inline bool arch_atomic_inc_and_test(atomic_t *v)
arch/s390/include/asm/atomic.h
74
return __atomic_add_const_and_test_barrier(1, &v->counter);
arch/s390/include/asm/atomic.h
83
static __always_inline void arch_atomic_##op(int i, atomic_t *v) \
arch/s390/include/asm/atomic.h
85
__atomic_##op(i, &v->counter); \
arch/s390/include/asm/atomic.h
87
static __always_inline int arch_atomic_fetch_##op(int i, atomic_t *v) \
arch/s390/include/asm/atomic.h
89
return __atomic_##op##_barrier(i, &v->counter); \
arch/s390/include/asm/barrier.h
40
#define __smp_store_release(p, v) \
arch/s390/include/asm/barrier.h
44
WRITE_ONCE(*p, v); \
arch/s390/include/asm/fpu-insn-asm.h
286
.macro VLVG v, gr, disp, m
arch/s390/include/asm/fpu-insn-asm.h
294
.macro VLVGB v, gr, index, base
arch/s390/include/asm/fpu-insn-asm.h
297
.macro VLVGH v, gr, index
arch/s390/include/asm/fpu-insn-asm.h
300
.macro VLVGF v, gr, index
arch/s390/include/asm/fpu-insn-asm.h
303
.macro VLVGG v, gr, index
arch/s390/include/asm/fpu-insn-asm.h
317
.macro VL v, disp, index="%r0", base
arch/s390/include/asm/fpu-insn-asm.h
547
.macro VLL v, gr, disp, base
arch/s390/include/asm/fpu-insn-asm.h
557
.macro VSTL v, gr, disp, base
arch/s390/include/asm/fpu-insn.h
208
static __always_inline void fpu_vleib(u8 v, s16 val, u8 index)
arch/s390/include/asm/fpu-insn.h
212
: [v] "I" (v), [val] "K" (val), [index] "I" (index)
arch/s390/include/asm/fpu-insn.h
216
static __always_inline void fpu_vleig(u8 v, s16 val, u8 index)
arch/s390/include/asm/fpu-insn.h
220
: [v] "I" (v), [val] "K" (val), [index] "I" (index)
arch/s390/include/asm/fpu-insn.h
224
static __always_inline u64 fpu_vlgvf(u8 v, u16 index)
arch/s390/include/asm/fpu-insn.h
230
: [v] "I" (v), [index] "L" (index)
arch/s390/include/asm/fpu-insn.h
319
static __always_inline void fpu_vlvgf(u8 v, u32 val, u16 index)
arch/s390/include/asm/fpu-insn.h
323
: [v] "I" (v), [val] "d" (val), [index] "L" (index)
arch/s390/include/asm/fpu-insn.h
473
static __always_inline void fpu_vzero(u8 v)
arch/s390/include/asm/fpu-insn.h
477
: [v] "I" (v)
arch/s390/include/asm/string.h
70
void *__memset16(uint16_t *s, uint16_t v, size_t count);
arch/s390/include/asm/string.h
71
void *__memset32(uint32_t *s, uint32_t v, size_t count);
arch/s390/include/asm/string.h
72
void *__memset64(uint64_t *s, uint64_t v, size_t count);
arch/s390/include/asm/string.h
75
static inline void *memset16(uint16_t *s, uint16_t v, size_t count)
arch/s390/include/asm/string.h
77
return __memset16(s, v, count * sizeof(v));
arch/s390/include/asm/string.h
82
static inline void *memset32(uint32_t *s, uint32_t v, size_t count)
arch/s390/include/asm/string.h
84
return __memset32(s, v, count * sizeof(v));
arch/s390/include/asm/string.h
90
void *memset64(uint64_t *s, uint64_t v, size_t count);
arch/s390/include/asm/string.h
92
static inline void *memset64(uint64_t *s, uint64_t v, size_t count)
arch/s390/include/asm/string.h
94
return __memset64(s, v, count * sizeof(v));
arch/s390/include/uapi/asm/runtime_instr.h
15
__u32 v : 1;
arch/s390/kernel/diag/diag.c
111
static void *show_diag_stat_next(struct seq_file *m, void *v, loff_t *pos)
arch/s390/kernel/diag/diag.c
117
static void show_diag_stat_stop(struct seq_file *m, void *v)
arch/s390/kernel/diag/diag.c
77
static int show_diag_stat(struct seq_file *m, void *v)
arch/s390/kernel/diag/diag.c
80
unsigned long n = (unsigned long) v - 1;
arch/s390/kernel/irq.c
248
int show_interrupts(struct seq_file *p, void *v)
arch/s390/kernel/irq.c
250
int index = *(loff_t *) v;
arch/s390/kernel/perf_cpum_sf.c
131
static inline struct hws_trailer_entry *trailer_entry_ptr(unsigned long v)
arch/s390/kernel/perf_cpum_sf.c
135
ret = (void *)v;
arch/s390/kernel/processor.c
127
static void show_cpu_summary(struct seq_file *m, void *v)
arch/s390/kernel/processor.c
341
static int show_cpuinfo(struct seq_file *m, void *v)
arch/s390/kernel/processor.c
343
unsigned long n = (unsigned long) v - 1;
arch/s390/kernel/processor.c
347
show_cpu_summary(m, v);
arch/s390/kernel/processor.c
370
static void *c_next(struct seq_file *m, void *v, loff_t *pos)
arch/s390/kernel/processor.c
376
static void c_stop(struct seq_file *m, void *v)
arch/s390/kernel/runtime_instr.c
61
cb->v = 1;
arch/s390/kernel/sysinfo.c
255
static int sysinfo_show(struct seq_file *m, void *v)
arch/s390/kernel/wti.c
122
static int wti_show(struct seq_file *seq, void *v)
arch/s390/kvm/kvm-s390.c
302
void *v)
arch/s390/kvm/kvm-s390.c
307
unsigned long long *delta = v;
arch/s390/kvm/kvm-s390.c
4790
riccb->v &&
arch/s390/mm/dump_pagetables.c
226
static int ptdump_show(struct seq_file *m, void *v)
arch/s390/pci/pci_debug.c
92
static int pci_perf_show(struct seq_file *m, void *v)
arch/s390/tools/relocs.c
331
static int print_reloc(uint32_t v)
arch/s390/tools/relocs.c
333
return fprintf(stdout, "\t.long 0x%08"PRIx32"\n", v) > 0 ? 0 : -1;
arch/sh/boards/mach-hp6xx/setup.c
127
u16 v;
arch/sh/boards/mach-hp6xx/setup.c
129
v = inw(HD64461_STBCR);
arch/sh/boards/mach-hp6xx/setup.c
130
v |= HD64461_STBCR_SURTST | HD64461_STBCR_SIRST |
arch/sh/boards/mach-hp6xx/setup.c
136
v |= HD64461_STBCR_SPC1ST;
arch/sh/boards/mach-hp6xx/setup.c
138
outw(v, HD64461_STBCR);
arch/sh/boards/mach-hp6xx/setup.c
139
v = inw(HD64461_GPADR);
arch/sh/boards/mach-hp6xx/setup.c
140
v |= HD64461_GPADR_SPEAKER | HD64461_GPADR_PCMCIA0;
arch/sh/boards/mach-hp6xx/setup.c
141
outw(v, HD64461_GPADR);
arch/sh/boards/mach-hp6xx/setup.c
160
v = __raw_readw(SCPCR);
arch/sh/boards/mach-hp6xx/setup.c
161
v &= ~SCPCR_TS_MASK;
arch/sh/boards/mach-hp6xx/setup.c
162
v |= SCPCR_TS_ENABLE;
arch/sh/boards/mach-hp6xx/setup.c
163
__raw_writew(v, SCPCR);
arch/sh/boards/mach-hp6xx/setup.c
56
u16 v;
arch/sh/boards/mach-hp6xx/setup.c
60
v = inw(HD64461_GPADR);
arch/sh/boards/mach-hp6xx/setup.c
61
v &= ~HD64461_GPADR_SPEAKER;
arch/sh/boards/mach-hp6xx/setup.c
62
outw(v, HD64461_GPADR);
arch/sh/boards/mach-hp6xx/setup.c
74
u16 v;
arch/sh/boards/mach-hp6xx/setup.c
78
v = inw(HD64461_GPADR);
arch/sh/boards/mach-hp6xx/setup.c
79
v |= HD64461_GPADR_SPEAKER;
arch/sh/boards/mach-hp6xx/setup.c
80
outw(v, HD64461_GPADR);
arch/sh/boards/mach-kfr2r09/lcd_wqvga.c
67
int i, unsigned long v)
arch/sh/boards/mach-kfr2r09/lcd_wqvga.c
70
so->write_data(sohandle, v); /* PTH4/LCDRS High [param, 17:0] */
arch/sh/boards/mach-kfr2r09/lcd_wqvga.c
72
so->write_index(sohandle, v); /* PTH4/LCDRS Low [cmd, 7:0] */
arch/sh/drivers/dma/dma-api.c
166
static int dma_proc_show(struct seq_file *m, void *v)
arch/sh/drivers/dma/dma-api.c
168
struct dma_info *info = v;
arch/sh/drivers/pci/fixups-se7751.c
32
#define PCIC_WRITE(x,v) writel((v), PCI_REG(x))
arch/sh/include/asm/atomic-grb.h
20
"+r" (v) \
arch/sh/include/asm/atomic-grb.h
26
static inline int arch_atomic_##op##_return(int i, atomic_t *v) \
arch/sh/include/asm/atomic-grb.h
40
"+r" (v) \
arch/sh/include/asm/atomic-grb.h
48
static inline int arch_atomic_fetch_##op(int i, atomic_t *v) \
arch/sh/include/asm/atomic-grb.h
6
static inline void arch_atomic_##op(int i, atomic_t *v) \
arch/sh/include/asm/atomic-grb.h
62
: "=&r" (tmp), "=&r" (res), "+r" (v) \
arch/sh/include/asm/atomic-irq.h
14
static inline void arch_atomic_##op(int i, atomic_t *v) \
arch/sh/include/asm/atomic-irq.h
19
v->counter c_op i; \
arch/sh/include/asm/atomic-irq.h
24
static inline int arch_atomic_##op##_return(int i, atomic_t *v) \
arch/sh/include/asm/atomic-irq.h
29
temp = v->counter; \
arch/sh/include/asm/atomic-irq.h
31
v->counter = temp; \
arch/sh/include/asm/atomic-irq.h
38
static inline int arch_atomic_fetch_##op(int i, atomic_t *v) \
arch/sh/include/asm/atomic-irq.h
43
temp = v->counter; \
arch/sh/include/asm/atomic-irq.h
44
v->counter c_op i; \
arch/sh/include/asm/atomic-llsc.h
20
static inline void arch_atomic_##op(int i, atomic_t *v) \
arch/sh/include/asm/atomic-llsc.h
30
: "r" (i), "r" (&v->counter) \
arch/sh/include/asm/atomic-llsc.h
35
static inline int arch_atomic_##op##_return(int i, atomic_t *v) \
arch/sh/include/asm/atomic-llsc.h
46
: "r" (i), "r" (&v->counter) \
arch/sh/include/asm/atomic-llsc.h
53
static inline int arch_atomic_fetch_##op(int i, atomic_t *v) \
arch/sh/include/asm/atomic-llsc.h
65
: "r" (i), "r" (&v->counter) \
arch/sh/include/asm/atomic.h
22
#define arch_atomic_read(v) READ_ONCE((v)->counter)
arch/sh/include/asm/atomic.h
23
#define arch_atomic_set(v,i) WRITE_ONCE((v)->counter, (i))
arch/sh/include/asm/io.h
28
#define __raw_writeb(v,a) (__chk_io_ptr(a), *(volatile u8 __force *)(a) = (v))
arch/sh/include/asm/io.h
29
#define __raw_writew(v,a) (__chk_io_ptr(a), *(volatile u16 __force *)(a) = (v))
arch/sh/include/asm/io.h
30
#define __raw_writel(v,a) (__chk_io_ptr(a), *(volatile u32 __force *)(a) = (v))
arch/sh/include/asm/io.h
31
#define __raw_writeq(v,a) (__chk_io_ptr(a), *(volatile u64 __force *)(a) = (v))
arch/sh/include/asm/io.h
43
#define writeb_relaxed(v,c) ((void)__raw_writeb((__force u8)ioswabb(v),c))
arch/sh/include/asm/io.h
44
#define writew_relaxed(v,c) ((void)__raw_writew((__force u16)ioswabw(v),c))
arch/sh/include/asm/io.h
45
#define writel_relaxed(v,c) ((void)__raw_writel((__force u32)ioswabl(v),c))
arch/sh/include/asm/io.h
46
#define writeq_relaxed(v,c) ((void)__raw_writeq((__force u64)ioswabq(v),c))
arch/sh/include/asm/io.h
53
#define writeb(v,a) ({ wmb(); writeb_relaxed((v),(a)); })
arch/sh/include/asm/io.h
54
#define writew(v,a) ({ wmb(); writew_relaxed((v),(a)); })
arch/sh/include/asm/io.h
55
#define writel(v,a) ({ wmb(); writel_relaxed((v),(a)); })
arch/sh/include/asm/io.h
56
#define writeq(v,a) ({ wmb(); writeq_relaxed((v),(a)); })
arch/sh/include/asm/io.h
76
static inline void write##bwlq##_uncached(type v, unsigned long addr) \
arch/sh/include/asm/io.h
79
__raw_write##bwlq(v, addr); \
arch/sh/include/cpu-sh3/cpu/dac.h
20
unsigned char v;
arch/sh/include/cpu-sh3/cpu/dac.h
21
v = __raw_readb(DACR);
arch/sh/include/cpu-sh3/cpu/dac.h
22
if(channel) v |= DACR_DAOE1;
arch/sh/include/cpu-sh3/cpu/dac.h
23
else v |= DACR_DAOE0;
arch/sh/include/cpu-sh3/cpu/dac.h
24
__raw_writeb(v,DACR);
arch/sh/include/cpu-sh3/cpu/dac.h
29
unsigned char v;
arch/sh/include/cpu-sh3/cpu/dac.h
30
v = __raw_readb(DACR);
arch/sh/include/cpu-sh3/cpu/dac.h
31
if(channel) v &= ~DACR_DAOE1;
arch/sh/include/cpu-sh3/cpu/dac.h
32
else v &= ~DACR_DAOE0;
arch/sh/include/cpu-sh3/cpu/dac.h
33
__raw_writeb(v,DACR);
arch/sh/include/uapi/asm/swab.h
42
} v, w;
arch/sh/include/uapi/asm/swab.h
43
v.u = val;
arch/sh/include/uapi/asm/swab.h
44
w.s.b = __arch_swab32(v.s.a);
arch/sh/include/uapi/asm/swab.h
45
w.s.a = __arch_swab32(v.s.b);
arch/sh/kernel/cpu/proc.c
137
static void *c_next(struct seq_file *m, void *v, loff_t *pos)
arch/sh/kernel/cpu/proc.c
142
static void c_stop(struct seq_file *m, void *v)
arch/sh/kernel/cpu/proc.c
79
static int show_cpuinfo(struct seq_file *m, void *v)
arch/sh/kernel/cpu/proc.c
81
struct sh_cpuinfo *c = v;
arch/sh/math-emu/sfp-util.h
22
#define umul_ppmm(w1, w0, u, v) \
arch/sh/math-emu/sfp-util.h
25
: "r" ((u32)(u)), "r" ((u32)(v)) \
arch/sh/mm/alignment.c
120
static int alignment_proc_show(struct seq_file *m, void *v)
arch/sh/mm/cache-sh2.c
20
unsigned long v;
arch/sh/mm/cache-sh2.c
26
for (v = begin; v < end; v+=L1_CACHE_BYTES) {
arch/sh/mm/cache-sh2.c
27
unsigned long addr = CACHE_OC_ADDRESS_ARRAY | (v & 0x00000ff0);
arch/sh/mm/cache-sh2.c
31
if ((data & CACHE_PHYSADDR_MASK) == (v & CACHE_PHYSADDR_MASK)) {
arch/sh/mm/cache-sh2.c
41
unsigned long v;
arch/sh/mm/cache-sh2.c
48
for (v = begin; v < end; v+=L1_CACHE_BYTES)
arch/sh/mm/cache-sh2.c
49
__raw_writel((v & CACHE_PHYSADDR_MASK),
arch/sh/mm/cache-sh2.c
50
CACHE_OC_ADDRESS_ARRAY | (v & 0x00000ff0) | 0x00000008);
arch/sh/mm/cache-sh2.c
72
unsigned long v;
arch/sh/mm/cache-sh2.c
79
for (v = begin; v < end; v+=L1_CACHE_BYTES)
arch/sh/mm/cache-sh2.c
80
__raw_writel((v & CACHE_PHYSADDR_MASK),
arch/sh/mm/cache-sh2.c
81
CACHE_OC_ADDRESS_ARRAY | (v & 0x00000ff0) | 0x00000008);
arch/sh/mm/cache-sh2a.c
104
for (v = begin; v < end; v+=L1_CACHE_BYTES) {
arch/sh/mm/cache-sh2a.c
109
sh2a_flush_oc_line(v, way);
arch/sh/mm/cache-sh2a.c
111
sh2a_invalidate_line(CACHE_OC_ADDRESS_ARRAY, v);
arch/sh/mm/cache-sh2a.c
123
unsigned long v;
arch/sh/mm/cache-sh2a.c
139
for (v = begin; v < end; v += L1_CACHE_BYTES)
arch/sh/mm/cache-sh2a.c
140
sh2a_invalidate_line(CACHE_OC_ADDRESS_ARRAY, v);
arch/sh/mm/cache-sh2a.c
154
unsigned long v;
arch/sh/mm/cache-sh2a.c
173
for (v = start; v < end; v += L1_CACHE_BYTES)
arch/sh/mm/cache-sh2a.c
174
sh2a_invalidate_line(CACHE_IC_ADDRESS_ARRAY, v);
arch/sh/mm/cache-sh2a.c
26
static void sh2a_flush_oc_line(unsigned long v, int way)
arch/sh/mm/cache-sh2a.c
28
unsigned long addr = (v & 0x000007f0) | (way << 11);
arch/sh/mm/cache-sh2a.c
32
if ((data & CACHE_PHYSADDR_MASK) == (v & CACHE_PHYSADDR_MASK)) {
arch/sh/mm/cache-sh2a.c
39
static void sh2a_invalidate_line(unsigned long cache_addr, unsigned long v)
arch/sh/mm/cache-sh2a.c
42
unsigned long addr = (v & 0x000007f0) | SH_CACHE_ASSOC;
arch/sh/mm/cache-sh2a.c
52
unsigned long v;
arch/sh/mm/cache-sh2a.c
70
for (v = begin; v < end; v += L1_CACHE_BYTES) {
arch/sh/mm/cache-sh2a.c
71
unsigned long data = __raw_readl(v);
arch/sh/mm/cache-sh2a.c
73
__raw_writel(data & ~SH_CACHE_UPDATED, v);
arch/sh/mm/cache-sh2a.c
78
for (v = begin; v < end; v += L1_CACHE_BYTES)
arch/sh/mm/cache-sh2a.c
79
sh2a_flush_oc_line(v, way);
arch/sh/mm/cache-sh2a.c
93
unsigned long v;
arch/sh/mm/cache-sh3.c
34
unsigned long v, j;
arch/sh/mm/cache-sh3.c
42
for (v = begin; v < end; v+=L1_CACHE_BYTES) {
arch/sh/mm/cache-sh3.c
47
p = __pa(v);
arch/sh/mm/cache-sh3.c
48
addr = addrstart | (v & current_cpu_data.dcache.entry_mask);
arch/sh/mm/cache-sh3.c
73
unsigned long v;
arch/sh/mm/cache-sh3.c
80
for (v = begin; v < end; v+=L1_CACHE_BYTES) {
arch/sh/mm/cache-sh3.c
83
data = (v & 0xfffffc00); /* _Virtual_ address, ~U, ~V */
arch/sh/mm/cache-sh3.c
85
(v & current_cpu_data.dcache.entry_mask) | SH_CACHE_ASSOC;
arch/sh/mm/cache-sh4.c
44
unsigned long flags, v;
arch/sh/mm/cache-sh4.c
67
for (v = start; v < end; v += L1_CACHE_BYTES) {
arch/sh/mm/cache-sh4.c
71
__ocbwb(v);
arch/sh/mm/cache-sh4.c
73
icacheaddr = CACHE_IC_ADDRESS_ARRAY | (v &
arch/sh/mm/cache-sh7705.c
48
int v = SH_CACHE_UPDATED | SH_CACHE_VALID;
arch/sh/mm/cache-sh7705.c
52
if ((data & v) == v)
arch/sh/mm/cache-sh7705.c
53
__raw_writel(data & ~v, addr);
arch/sh/mm/flush-sh4.c
101
__ocbi(v); v += L1_CACHE_BYTES;
arch/sh/mm/flush-sh4.c
16
reg_size_t aligned_start, v, cnt, end;
arch/sh/mm/flush-sh4.c
19
v = aligned_start & ~(L1_CACHE_BYTES-1);
arch/sh/mm/flush-sh4.c
22
cnt = (end - v) / L1_CACHE_BYTES;
arch/sh/mm/flush-sh4.c
25
__ocbwb(v); v += L1_CACHE_BYTES;
arch/sh/mm/flush-sh4.c
26
__ocbwb(v); v += L1_CACHE_BYTES;
arch/sh/mm/flush-sh4.c
27
__ocbwb(v); v += L1_CACHE_BYTES;
arch/sh/mm/flush-sh4.c
28
__ocbwb(v); v += L1_CACHE_BYTES;
arch/sh/mm/flush-sh4.c
29
__ocbwb(v); v += L1_CACHE_BYTES;
arch/sh/mm/flush-sh4.c
30
__ocbwb(v); v += L1_CACHE_BYTES;
arch/sh/mm/flush-sh4.c
31
__ocbwb(v); v += L1_CACHE_BYTES;
arch/sh/mm/flush-sh4.c
32
__ocbwb(v); v += L1_CACHE_BYTES;
arch/sh/mm/flush-sh4.c
37
__ocbwb(v); v += L1_CACHE_BYTES;
arch/sh/mm/flush-sh4.c
50
reg_size_t aligned_start, v, cnt, end;
arch/sh/mm/flush-sh4.c
53
v = aligned_start & ~(L1_CACHE_BYTES-1);
arch/sh/mm/flush-sh4.c
56
cnt = (end - v) / L1_CACHE_BYTES;
arch/sh/mm/flush-sh4.c
59
__ocbp(v); v += L1_CACHE_BYTES;
arch/sh/mm/flush-sh4.c
60
__ocbp(v); v += L1_CACHE_BYTES;
arch/sh/mm/flush-sh4.c
61
__ocbp(v); v += L1_CACHE_BYTES;
arch/sh/mm/flush-sh4.c
62
__ocbp(v); v += L1_CACHE_BYTES;
arch/sh/mm/flush-sh4.c
63
__ocbp(v); v += L1_CACHE_BYTES;
arch/sh/mm/flush-sh4.c
64
__ocbp(v); v += L1_CACHE_BYTES;
arch/sh/mm/flush-sh4.c
65
__ocbp(v); v += L1_CACHE_BYTES;
arch/sh/mm/flush-sh4.c
66
__ocbp(v); v += L1_CACHE_BYTES;
arch/sh/mm/flush-sh4.c
70
__ocbp(v); v += L1_CACHE_BYTES;
arch/sh/mm/flush-sh4.c
80
reg_size_t aligned_start, v, cnt, end;
arch/sh/mm/flush-sh4.c
83
v = aligned_start & ~(L1_CACHE_BYTES-1);
arch/sh/mm/flush-sh4.c
86
cnt = (end - v) / L1_CACHE_BYTES;
arch/sh/mm/flush-sh4.c
89
__ocbi(v); v += L1_CACHE_BYTES;
arch/sh/mm/flush-sh4.c
90
__ocbi(v); v += L1_CACHE_BYTES;
arch/sh/mm/flush-sh4.c
91
__ocbi(v); v += L1_CACHE_BYTES;
arch/sh/mm/flush-sh4.c
92
__ocbi(v); v += L1_CACHE_BYTES;
arch/sh/mm/flush-sh4.c
93
__ocbi(v); v += L1_CACHE_BYTES;
arch/sh/mm/flush-sh4.c
94
__ocbi(v); v += L1_CACHE_BYTES;
arch/sh/mm/flush-sh4.c
95
__ocbi(v); v += L1_CACHE_BYTES;
arch/sh/mm/flush-sh4.c
96
__ocbi(v); v += L1_CACHE_BYTES;
arch/sparc/include/asm/atomic_32.h
47
#define arch_atomic_set_release(v, i) arch_atomic_set((v), (i))
arch/sparc/include/asm/atomic_32.h
49
#define arch_atomic_read(v) READ_ONCE((v)->counter)
arch/sparc/include/asm/atomic_32.h
51
#define arch_atomic_add(i, v) ((void)arch_atomic_add_return( (int)(i), (v)))
arch/sparc/include/asm/atomic_32.h
52
#define arch_atomic_sub(i, v) ((void)arch_atomic_add_return(-(int)(i), (v)))
arch/sparc/include/asm/atomic_32.h
54
#define arch_atomic_and(i, v) ((void)arch_atomic_fetch_and((i), (v)))
arch/sparc/include/asm/atomic_32.h
55
#define arch_atomic_or(i, v) ((void)arch_atomic_fetch_or((i), (v)))
arch/sparc/include/asm/atomic_32.h
56
#define arch_atomic_xor(i, v) ((void)arch_atomic_fetch_xor((i), (v)))
arch/sparc/include/asm/atomic_32.h
58
#define arch_atomic_sub_return(i, v) (arch_atomic_add_return(-(int)(i), (v)))
arch/sparc/include/asm/atomic_32.h
59
#define arch_atomic_fetch_sub(i, v) (arch_atomic_fetch_add (-(int)(i), (v)))
arch/sparc/include/asm/atomic_64.h
17
#define arch_atomic_read(v) READ_ONCE((v)->counter)
arch/sparc/include/asm/atomic_64.h
18
#define arch_atomic64_read(v) READ_ONCE((v)->counter)
arch/sparc/include/asm/atomic_64.h
20
#define arch_atomic_set(v, i) WRITE_ONCE(((v)->counter), (i))
arch/sparc/include/asm/atomic_64.h
21
#define arch_atomic64_set(v, i) WRITE_ONCE(((v)->counter), (i))
arch/sparc/include/asm/atomic_64.h
70
s64 arch_atomic64_dec_if_positive(atomic64_t *v);
arch/sparc/include/asm/barrier_64.h
41
#define __smp_store_release(p, v) \
arch/sparc/include/asm/barrier_64.h
45
WRITE_ONCE(*p, v); \
arch/sparc/include/asm/leon.h
82
#define LEON3_BYPASS_STORE_PA(x, v) (leon_store_reg((unsigned long)(x), (unsigned long)(v)))
arch/sparc/include/asm/leon.h
84
#define LEON_BYPASS_STORE_PA(x, v) leon_store_reg((unsigned long)(x), (unsigned long)(v))
arch/sparc/include/asm/pcic.h
117
#define PCI_COUNTER_IRQ_SYS(v) (((v) >> 4) & 0xf)
arch/sparc/include/asm/pcic.h
118
#define PCI_COUNTER_IRQ_CPU(v) ((v) & 0xf)
arch/sparc/include/asm/pgtable_32.h
123
unsigned long v;
arch/sparc/include/asm/pgtable_32.h
128
v = pmd_val(pmd) & SRMMU_PTD_PMASK;
arch/sparc/include/asm/pgtable_32.h
129
return (unsigned long)__nocache_va(v << 4);
arch/sparc/include/asm/pgtable_32.h
134
unsigned long v = pmd_val(pmd) & SRMMU_PTD_PMASK;
arch/sparc/include/asm/pgtable_32.h
135
return (unsigned long)__nocache_va(v << 4);
arch/sparc/include/asm/pgtable_32.h
143
unsigned long v = pud_val(pud) & SRMMU_PTD_PMASK;
arch/sparc/include/asm/pgtable_32.h
144
return (pmd_t *)__nocache_va(v << 4);
arch/sparc/kernel/cpu.c
422
static void *c_next(struct seq_file *m, void *v, loff_t *pos)
arch/sparc/kernel/cpu.c
428
static void c_stop(struct seq_file *m, void *v)
arch/sparc/kernel/ioport.c
320
static int sparc_io_proc_show(struct seq_file *m, void *v)
arch/sparc/kernel/ldc.c
2390
const u64 *v;
arch/sparc/kernel/ldc.c
2403
v = mdesc_get_property(hp, mp, "domaining-enabled", NULL);
arch/sparc/kernel/ldc.c
2404
if (!v)
arch/sparc/kernel/ldc.c
2416
if (!*v) {
arch/sparc/kernel/ldc.c
564
struct ldc_version *v = &ver_arr[i];
arch/sparc/kernel/ldc.c
565
if (v->major <= major) {
arch/sparc/kernel/ldc.c
566
ret = v;
arch/sparc/kernel/led.c
54
static int led_proc_show(struct seq_file *m, void *v)
arch/sparc/kernel/leon_pci_grpci1.c
158
u32 v;
arch/sparc/kernel/leon_pci_grpci1.c
163
ret = grpci1_cfg_r32(priv, bus, devfn, where & ~0x3, &v);
arch/sparc/kernel/leon_pci_grpci1.c
164
*val = 0xffff & (v >> (8 * (where & 0x3)));
arch/sparc/kernel/leon_pci_grpci1.c
171
u32 v;
arch/sparc/kernel/leon_pci_grpci1.c
174
ret = grpci1_cfg_r32(priv, bus, devfn, where & ~0x3, &v);
arch/sparc/kernel/leon_pci_grpci1.c
175
*val = 0xff & (v >> (8 * (where & 3)));
arch/sparc/kernel/leon_pci_grpci1.c
211
u32 v;
arch/sparc/kernel/leon_pci_grpci1.c
215
ret = grpci1_cfg_r32(priv, bus, devfn, where&~3, &v);
arch/sparc/kernel/leon_pci_grpci1.c
218
v = (v & ~(0xffff << (8 * (where & 0x3)))) |
arch/sparc/kernel/leon_pci_grpci1.c
220
return grpci1_cfg_w32(priv, bus, devfn, where & ~0x3, v);
arch/sparc/kernel/leon_pci_grpci1.c
227
u32 v;
arch/sparc/kernel/leon_pci_grpci1.c
229
ret = grpci1_cfg_r32(priv, bus, devfn, where & ~0x3, &v);
arch/sparc/kernel/leon_pci_grpci1.c
232
v = (v & ~(0xff << (8 * (where & 0x3)))) |
arch/sparc/kernel/leon_pci_grpci1.c
234
return grpci1_cfg_w32(priv, bus, devfn, where & ~0x3, v);
arch/sparc/kernel/leon_pci_grpci1.c
50
#define REGSTORE(a, v) (__raw_writel(cpu_to_be32(v), &(a)))
arch/sparc/kernel/leon_pci_grpci2.c
285
u32 v;
arch/sparc/kernel/leon_pci_grpci2.c
290
ret = grpci2_cfg_r32(priv, bus, devfn, where & ~0x3, &v);
arch/sparc/kernel/leon_pci_grpci2.c
291
*val = 0xffff & (v >> (8 * (where & 0x3)));
arch/sparc/kernel/leon_pci_grpci2.c
298
u32 v;
arch/sparc/kernel/leon_pci_grpci2.c
301
ret = grpci2_cfg_r32(priv, bus, devfn, where & ~0x3, &v);
arch/sparc/kernel/leon_pci_grpci2.c
302
*val = 0xff & (v >> (8 * (where & 3)));
arch/sparc/kernel/leon_pci_grpci2.c
349
u32 v;
arch/sparc/kernel/leon_pci_grpci2.c
353
ret = grpci2_cfg_r32(priv, bus, devfn, where&~3, &v);
arch/sparc/kernel/leon_pci_grpci2.c
356
v = (v & ~(0xffff << (8 * (where & 0x3)))) |
arch/sparc/kernel/leon_pci_grpci2.c
358
return grpci2_cfg_w32(priv, bus, devfn, where & ~0x3, v);
arch/sparc/kernel/leon_pci_grpci2.c
365
u32 v;
arch/sparc/kernel/leon_pci_grpci2.c
367
ret = grpci2_cfg_r32(priv, bus, devfn, where & ~0x3, &v);
arch/sparc/kernel/leon_pci_grpci2.c
370
v = (v & ~(0xff << (8 * (where & 0x3)))) |
arch/sparc/kernel/leon_pci_grpci2.c
372
return grpci2_cfg_w32(priv, bus, devfn, where & ~0x3, v);
arch/sparc/kernel/leon_pci_grpci2.c
95
#define REGSTORE(a, v) (__raw_writel(cpu_to_be32(v), &(a)))
arch/sparc/kernel/mdesc.c
764
const u64 *v;
arch/sparc/kernel/mdesc.c
776
v = mdesc_get_property(hp, pn, "hostid", NULL);
arch/sparc/kernel/mdesc.c
777
if (v)
arch/sparc/kernel/mdesc.c
778
printk("PLATFORM: hostid [%08llx]\n", *v);
arch/sparc/kernel/mdesc.c
779
v = mdesc_get_property(hp, pn, "serial#", NULL);
arch/sparc/kernel/mdesc.c
780
if (v)
arch/sparc/kernel/mdesc.c
781
printk("PLATFORM: serial# [%08llx]\n", *v);
arch/sparc/kernel/mdesc.c
782
v = mdesc_get_property(hp, pn, "stick-frequency", NULL);
arch/sparc/kernel/mdesc.c
783
printk("PLATFORM: stick-frequency [%08llx]\n", *v);
arch/sparc/kernel/mdesc.c
784
v = mdesc_get_property(hp, pn, "mac-address", NULL);
arch/sparc/kernel/mdesc.c
785
if (v)
arch/sparc/kernel/mdesc.c
786
printk("PLATFORM: mac-address [%llx]\n", *v);
arch/sparc/kernel/mdesc.c
787
v = mdesc_get_property(hp, pn, "watchdog-resolution", NULL);
arch/sparc/kernel/mdesc.c
788
if (v)
arch/sparc/kernel/mdesc.c
789
printk("PLATFORM: watchdog-resolution [%llu ms]\n", *v);
arch/sparc/kernel/mdesc.c
790
v = mdesc_get_property(hp, pn, "watchdog-max-timeout", NULL);
arch/sparc/kernel/mdesc.c
791
if (v)
arch/sparc/kernel/mdesc.c
792
printk("PLATFORM: watchdog-max-timeout [%llu ms]\n", *v);
arch/sparc/kernel/mdesc.c
793
v = mdesc_get_property(hp, pn, "max-cpus", NULL);
arch/sparc/kernel/mdesc.c
794
if (v) {
arch/sparc/kernel/mdesc.c
795
max_cpus = *v;
arch/sparc/kernel/mdesc.c
803
if (v) {
arch/sparc/kernel/mdesc.c
804
max_cpu = *v;
arch/sparc/kernel/module.c
100
v -= (Elf_Addr) location;
arch/sparc/kernel/module.c
102
((v >> 2) & 0x7ffff);
arch/sparc/kernel/module.c
107
(((v & 0x3ff) +
arch/sparc/kernel/module.c
115
location[0] = v >> 24;
arch/sparc/kernel/module.c
116
location[1] = v >> 16;
arch/sparc/kernel/module.c
117
location[2] = v >> 8;
arch/sparc/kernel/module.c
118
location[3] = v >> 0;
arch/sparc/kernel/module.c
122
v -= (Elf_Addr) location;
arch/sparc/kernel/module.c
124
((v >> 2) & 0x3fffffff);
arch/sparc/kernel/module.c
128
v -= (Elf_Addr) location;
arch/sparc/kernel/module.c
130
((v >> 2) & 0x3fffff);
arch/sparc/kernel/module.c
134
*loc32 = (*loc32 & ~0x3ff) | (v & 0x3ff);
arch/sparc/kernel/module.c
139
((v >> 10) & 0x3fffff);
arch/sparc/kernel/module.c
64
Elf_Addr v;
arch/sparc/kernel/module.c
79
v = sym->st_value + rel[i].r_addend;
arch/sparc/kernel/module.c
83
v -= (Elf_Addr) location;
arch/sparc/kernel/module.c
84
*loc32 = v;
arch/sparc/kernel/module.c
89
location[0] = v >> 56;
arch/sparc/kernel/module.c
90
location[1] = v >> 48;
arch/sparc/kernel/module.c
91
location[2] = v >> 40;
arch/sparc/kernel/module.c
92
location[3] = v >> 32;
arch/sparc/kernel/module.c
93
location[4] = v >> 24;
arch/sparc/kernel/module.c
94
location[5] = v >> 16;
arch/sparc/kernel/module.c
95
location[6] = v >> 8;
arch/sparc/kernel/module.c
96
location[7] = v >> 0;
arch/sparc/kernel/pcic.c
217
unsigned int v;
arch/sparc/kernel/pcic.c
222
pcic_read_config_dword(bus->number, devfn, where&~3, &v);
arch/sparc/kernel/pcic.c
223
*val = 0xff & (v >> (8*(where & 3)));
arch/sparc/kernel/pcic.c
227
pcic_read_config_dword(bus->number, devfn, where&~3, &v);
arch/sparc/kernel/pcic.c
228
*val = 0xffff & (v >> (8*(where & 3)));
arch/sparc/kernel/pcic.c
256
unsigned int v;
arch/sparc/kernel/pcic.c
261
pcic_read_config_dword(bus->number, devfn, where&~3, &v);
arch/sparc/kernel/pcic.c
262
v = (v & ~(0xff << (8*(where&3)))) |
arch/sparc/kernel/pcic.c
264
return pcic_write_config_dword(bus->number, devfn, where&~3, v);
arch/sparc/kernel/pcic.c
267
pcic_read_config_dword(bus->number, devfn, where&~3, &v);
arch/sparc/kernel/pcic.c
268
v = (v & ~(0xffff << (8*(where&3)))) |
arch/sparc/kernel/pcic.c
270
return pcic_write_config_dword(bus->number, devfn, where&~3, v);
arch/sparc/kernel/pcic.c
679
unsigned long v;
arch/sparc/kernel/pcic.c
696
v = readb(pcic->pcic_regs+PCI_COUNTER_IRQ);
arch/sparc/kernel/pcic.c
697
timer_irq = PCI_COUNTER_IRQ_SYS(v);
arch/sparc/kernel/ptrace_32.c
266
u32 v[4];
arch/sparc/kernel/ptrace_32.c
273
v,
arch/sparc/kernel/ptrace_32.c
278
(v[0] & (PSR_ICC | PSR_SYSCALL));
arch/sparc/kernel/ptrace_32.c
279
regs->pc = v[1];
arch/sparc/kernel/ptrace_32.c
280
regs->npc = v[2];
arch/sparc/kernel/ptrace_32.c
281
regs->y = v[3];
arch/sparc/kernel/termios.c
18
struct termio v;
arch/sparc/kernel/termios.c
19
memset(&v, 0, sizeof(struct termio));
arch/sparc/kernel/termios.c
20
v.c_iflag = termios->c_iflag;
arch/sparc/kernel/termios.c
21
v.c_oflag = termios->c_oflag;
arch/sparc/kernel/termios.c
22
v.c_cflag = termios->c_cflag;
arch/sparc/kernel/termios.c
23
v.c_lflag = termios->c_lflag;
arch/sparc/kernel/termios.c
24
v.c_line = termios->c_line;
arch/sparc/kernel/termios.c
25
memcpy(v.c_cc, termios->c_cc, NCC);
arch/sparc/kernel/termios.c
26
if (!(v.c_lflag & ICANON)) {
arch/sparc/kernel/termios.c
27
v.c_cc[_VMIN] = termios->c_cc[VMIN];
arch/sparc/kernel/termios.c
28
v.c_cc[_VTIME] = termios->c_cc[VTIME];
arch/sparc/kernel/termios.c
30
return copy_to_user(termio, &v, sizeof(struct termio));
arch/sparc/kernel/viohs.c
246
struct vio_version *v = &vio->ver_table[i];
arch/sparc/kernel/viohs.c
247
if (v->major <= major) {
arch/sparc/kernel/viohs.c
248
ret = v;
arch/sparc/lib/atomic32.c
103
spin_lock_irqsave(ATOMIC_HASH(v), flags);
arch/sparc/lib/atomic32.c
104
ret = v->counter;
arch/sparc/lib/atomic32.c
106
v->counter += a;
arch/sparc/lib/atomic32.c
107
spin_unlock_irqrestore(ATOMIC_HASH(v), flags);
arch/sparc/lib/atomic32.c
113
void arch_atomic_set(atomic_t *v, int i)
arch/sparc/lib/atomic32.c
117
spin_lock_irqsave(ATOMIC_HASH(v), flags);
arch/sparc/lib/atomic32.c
118
v->counter = i;
arch/sparc/lib/atomic32.c
119
spin_unlock_irqrestore(ATOMIC_HASH(v), flags);
arch/sparc/lib/atomic32.c
32
int arch_atomic_fetch_##op(int i, atomic_t *v) \
arch/sparc/lib/atomic32.c
36
spin_lock_irqsave(ATOMIC_HASH(v), flags); \
arch/sparc/lib/atomic32.c
38
ret = v->counter; \
arch/sparc/lib/atomic32.c
39
v->counter c_op i; \
arch/sparc/lib/atomic32.c
41
spin_unlock_irqrestore(ATOMIC_HASH(v), flags); \
arch/sparc/lib/atomic32.c
47
int arch_atomic_##op##_return(int i, atomic_t *v) \
arch/sparc/lib/atomic32.c
51
spin_lock_irqsave(ATOMIC_HASH(v), flags); \
arch/sparc/lib/atomic32.c
53
ret = (v->counter c_op i); \
arch/sparc/lib/atomic32.c
55
spin_unlock_irqrestore(ATOMIC_HASH(v), flags); \
arch/sparc/lib/atomic32.c
70
int arch_atomic_xchg(atomic_t *v, int new)
arch/sparc/lib/atomic32.c
75
spin_lock_irqsave(ATOMIC_HASH(v), flags);
arch/sparc/lib/atomic32.c
76
ret = v->counter;
arch/sparc/lib/atomic32.c
77
v->counter = new;
arch/sparc/lib/atomic32.c
78
spin_unlock_irqrestore(ATOMIC_HASH(v), flags);
arch/sparc/lib/atomic32.c
83
int arch_atomic_cmpxchg(atomic_t *v, int old, int new)
arch/sparc/lib/atomic32.c
88
spin_lock_irqsave(ATOMIC_HASH(v), flags);
arch/sparc/lib/atomic32.c
89
ret = v->counter;
arch/sparc/lib/atomic32.c
91
v->counter = new;
arch/sparc/lib/atomic32.c
93
spin_unlock_irqrestore(ATOMIC_HASH(v), flags);
arch/sparc/lib/atomic32.c
98
int arch_atomic_fetch_add_unless(atomic_t *v, int a, int u)
arch/sparc/math-emu/sfp-util_32.h
28
#define umul_ppmm(w1, w0, u, v) \
arch/sparc/math-emu/sfp-util_32.h
72
"r" ((USItype)(v)) \
arch/sparc/math-emu/sfp-util_64.h
43
#define umul_ppmm(wh, wl, u, v) \
arch/sparc/math-emu/sfp-util_64.h
72
"r" ((UDItype)(v)) \
arch/sparc/mm/tsb.c
103
__flush_tsb_one_entry(tsb, v + (i << hash_shift), hash_shift,
arch/sparc/mm/tsb.c
54
unsigned long v;
arch/sparc/mm/tsb.c
59
for (v = start; v < end; v += PAGE_SIZE) {
arch/sparc/mm/tsb.c
60
unsigned long hash = tsb_hash(v, PAGE_SHIFT,
arch/sparc/mm/tsb.c
64
if (tag_compare(ent->tag, v))
arch/sparc/mm/tsb.c
69
static void __flush_tsb_one_entry(unsigned long tsb, unsigned long v,
arch/sparc/mm/tsb.c
75
v &= ~0x1UL;
arch/sparc/mm/tsb.c
76
hash = tsb_hash(v, hash_shift, nentries);
arch/sparc/mm/tsb.c
78
tag = (v >> 22UL);
arch/sparc/mm/tsb.c
93
static void __flush_huge_tsb_one_entry(unsigned long tsb, unsigned long v,
arch/sparc/vdso/vclock_gettime.c
148
u64 v;
arch/sparc/vdso/vclock_gettime.c
152
v = (cycles - vvar->clock.cycle_last) & vvar->clock.mask;
arch/sparc/vdso/vclock_gettime.c
153
return v * vvar->clock.mult;
arch/sparc/vdso/vclock_gettime.c
158
u64 v;
arch/sparc/vdso/vclock_gettime.c
162
v = (cycles - vvar->clock.cycle_last) & vvar->clock.mask;
arch/sparc/vdso/vclock_gettime.c
163
return v * vvar->clock.mult;
arch/um/drivers/vfio_kern.c
167
uint64_t v;
arch/um/drivers/vfio_kern.c
171
r = os_read_file(irqfd, &v, sizeof(v));
arch/um/drivers/vfio_kern.c
172
if (r == sizeof(v))
arch/um/drivers/vfio_kern.c
174
} while (r == sizeof(v) || r == -EINTR);
arch/um/include/asm/archrandom.h
10
static inline size_t __must_check arch_get_random_longs(unsigned long *v, size_t max_longs)
arch/um/include/asm/archrandom.h
14
ret = os_getrandom(v, max_longs * sizeof(*v), 0);
arch/um/include/asm/archrandom.h
17
return ret / sizeof(*v);
arch/um/include/asm/archrandom.h
20
static inline size_t __must_check arch_get_random_seed_longs(unsigned long *v, size_t max_longs)
arch/um/include/asm/page.h
91
#define virt_addr_valid(v) pfn_valid(phys_to_pfn(__pa(v)))
arch/um/kernel/exitcode.c
21
static int exitcode_proc_show(struct seq_file *m, void *v)
arch/um/kernel/um_arch.c
107
static void *c_next(struct seq_file *m, void *v, loff_t *pos)
arch/um/kernel/um_arch.c
113
static void c_stop(struct seq_file *m, void *v)
arch/um/kernel/um_arch.c
71
static int show_cpuinfo(struct seq_file *m, void *v)
arch/um/kernel/um_arch.c
76
i = (uintptr_t) v - 1;
arch/x86/boot/bitops.h
27
bool v;
arch/x86/boot/bitops.h
30
asm("btl %2,%1" : "=@ccc" (v) : "m" (*p), "Ir" (nr));
arch/x86/boot/bitops.h
31
return v;
arch/x86/boot/boot.h
100
static inline void wrfs8(u8 v, addr_t addr)
arch/x86/boot/boot.h
103
asm volatile("movb %1,%%fs:%0" : "+m" (*ptr) : "qi" (v));
arch/x86/boot/boot.h
105
static inline void wrfs16(u16 v, addr_t addr)
arch/x86/boot/boot.h
108
asm volatile("movw %1,%%fs:%0" : "+m" (*ptr) : "ri" (v));
arch/x86/boot/boot.h
110
static inline void wrfs32(u32 v, addr_t addr)
arch/x86/boot/boot.h
113
asm volatile("movl %1,%%fs:%0" : "+m" (*ptr) : "ri" (v));
arch/x86/boot/boot.h
119
u8 v;
arch/x86/boot/boot.h
120
asm volatile("movb %%gs:%1,%0" : "=q" (v) : "m" (*ptr));
arch/x86/boot/boot.h
121
return v;
arch/x86/boot/boot.h
126
u16 v;
arch/x86/boot/boot.h
127
asm volatile("movw %%gs:%1,%0" : "=r" (v) : "m" (*ptr));
arch/x86/boot/boot.h
128
return v;
arch/x86/boot/boot.h
133
u32 v;
arch/x86/boot/boot.h
134
asm volatile("movl %%gs:%1,%0" : "=r" (v) : "m" (*ptr));
arch/x86/boot/boot.h
135
return v;
arch/x86/boot/boot.h
138
static inline void wrgs8(u8 v, addr_t addr)
arch/x86/boot/boot.h
141
asm volatile("movb %1,%%gs:%0" : "+m" (*ptr) : "qi" (v));
arch/x86/boot/boot.h
143
static inline void wrgs16(u16 v, addr_t addr)
arch/x86/boot/boot.h
146
asm volatile("movw %1,%%gs:%0" : "+m" (*ptr) : "ri" (v));
arch/x86/boot/boot.h
148
static inline void wrgs32(u32 v, addr_t addr)
arch/x86/boot/boot.h
151
asm volatile("movl %1,%%gs:%0" : "+m" (*ptr) : "ri" (v));
arch/x86/boot/boot.h
81
u8 v;
arch/x86/boot/boot.h
82
asm volatile("movb %%fs:%1,%0" : "=q" (v) : "m" (*ptr));
arch/x86/boot/boot.h
83
return v;
arch/x86/boot/boot.h
88
u16 v;
arch/x86/boot/boot.h
89
asm volatile("movw %%fs:%1,%0" : "=r" (v) : "m" (*ptr));
arch/x86/boot/boot.h
90
return v;
arch/x86/boot/boot.h
95
u32 v;
arch/x86/boot/boot.h
96
asm volatile("movl %%fs:%1,%0" : "=r" (v) : "m" (*ptr));
arch/x86/boot/boot.h
97
return v;
arch/x86/boot/io.h
16
void (*f_outb)(u8 v, u16 port);
arch/x86/boot/io.h
17
void (*f_outw)(u16 v, u16 port);
arch/x86/boot/video.c
103
unsigned int v;
arch/x86/boot/video.c
127
v = 0;
arch/x86/boot/video.c
129
v <<= 4;
arch/x86/boot/video.c
131
v += (key > '9') ? key-'a'+10 : key-'0';
arch/x86/boot/video.c
134
return v;
arch/x86/boot/video.h
103
static inline void out_idx(u8 v, u16 port, u8 index)
arch/x86/boot/video.h
105
outw(index+(v << 8), port);
arch/x86/boot/video.h
109
static inline u8 tst_idx(u8 v, u16 port, u8 index)
arch/x86/boot/video.h
111
out_idx(port, index, v);
arch/x86/coco/sev/vc-handle.c
355
#define error(v)
arch/x86/coco/sev/vc-shared.c
426
unsigned long v = info & SVM_EVTINJ_VEC_MASK;
arch/x86/coco/sev/vc-shared.c
430
((v == X86_TRAP_GP) || (v == X86_TRAP_UD)) &&
arch/x86/coco/sev/vc-shared.c
432
ctxt->fi.vector = v;
arch/x86/events/amd/lbr.c
250
u64 mask = 0, v;
arch/x86/events/amd/lbr.c
296
v = lbr_select_map[i];
arch/x86/events/amd/lbr.c
297
if (v == LBR_NOT_SUPP)
arch/x86/events/amd/lbr.c
300
if (v != LBR_IGNORE)
arch/x86/events/amd/lbr.c
301
mask |= v;
arch/x86/events/intel/lbr.c
1108
u64 mask = 0, v;
arch/x86/events/intel/lbr.c
1115
v = x86_pmu.lbr_sel_map[i];
arch/x86/events/intel/lbr.c
1116
if (v == LBR_NOT_SUPP)
arch/x86/events/intel/lbr.c
1119
if (v != LBR_IGN)
arch/x86/events/intel/lbr.c
1120
mask |= v;
arch/x86/events/intel/p4.c
753
unsigned int v, emask;
arch/x86/events/intel/p4.c
756
v = p4_config_unpack_event(event->attr.config);
arch/x86/events/intel/p4.c
757
if (v >= ARRAY_SIZE(p4_event_bind_map))
arch/x86/events/intel/p4.c
761
if (!p4_event_match_cpu_model(v))
arch/x86/events/intel/p4.c
780
if (p4_ht_active() && p4_event_bind_map[v].shared) {
arch/x86/events/intel/p4.c
781
v = perf_allow_cpu();
arch/x86/events/intel/p4.c
782
if (v)
arch/x86/events/intel/p4.c
783
return v;
arch/x86/events/intel/p4.c
788
if (emask & ~p4_event_bind_map[v].escr_emask)
arch/x86/events/intel/p4.c
797
v = p4_config_unpack_metric(event->attr.config);
arch/x86/events/intel/p4.c
798
if (v >= ARRAY_SIZE(p4_pebs_bind_map))
arch/x86/events/intel/p4.c
860
u64 v;
arch/x86/events/intel/p4.c
863
rdmsrq(hwc->config_base, v);
arch/x86/events/intel/p4.c
864
if (v & P4_CCCR_OVF) {
arch/x86/events/intel/p4.c
865
wrmsrq(hwc->config_base, v & ~P4_CCCR_OVF);
arch/x86/events/intel/p4.c
876
rdmsrq(hwc->event_base, v);
arch/x86/events/intel/p4.c
877
if (!(v & ARCH_P4_UNFLAGGED_BIT))
arch/x86/events/perf_event.h
1125
#define EVENT_ATTR_STR(_name, v, str) \
arch/x86/events/perf_event.h
1126
static struct perf_pmu_events_attr event_attr_##v = { \
arch/x86/events/perf_event.h
1132
#define EVENT_ATTR_STR_HT(_name, v, noht, ht) \
arch/x86/events/perf_event.h
1133
static struct perf_pmu_events_ht_attr event_attr_##v = { \
arch/x86/events/perf_event.h
1140
#define EVENT_ATTR_STR_HYBRID(_name, v, str, _pmu) \
arch/x86/events/perf_event.h
1141
static struct perf_pmu_events_hybrid_attr event_attr_##v = { \
arch/x86/events/rapl.c
110
#define RAPL_EVENT_ATTR_STR(_name, v, str) \
arch/x86/events/rapl.c
111
static struct perf_pmu_events_attr event_attr_##v = { \
arch/x86/events/rapl.c
200
static inline u64 rapl_scale(u64 v, struct perf_event *event)
arch/x86/events/rapl.c
213
return v << (32 - hw_unit);
arch/x86/include/asm/apic.h
202
static inline void native_apic_msr_write(u32 reg, u32 v)
arch/x86/include/asm/apic.h
208
wrmsrq(APIC_BASE_MSR + (reg >> 4), v);
arch/x86/include/asm/apic.h
274
void (*write)(u32 reg, u32 v);
arch/x86/include/asm/apic.h
326
void (*write)(u32 reg, u32 v);
arch/x86/include/asm/apic.h
38
#define apic_printk(v, s, a...) \
arch/x86/include/asm/apic.h
40
if ((v) <= apic_verbosity) \
arch/x86/include/asm/apic.h
498
#define APIC_VECTOR_TO_BIT_NUMBER(v) ((unsigned int)(v) % 32)
arch/x86/include/asm/apic.h
499
#define APIC_VECTOR_TO_REG_OFFSET(v) ((unsigned int)(v) / 32 * 0x10)
arch/x86/include/asm/apic.h
93
static inline void native_apic_mem_write(u32 reg, u32 v)
arch/x86/include/asm/apic.h
98
ASM_OUTPUT("=r" (v), "=m" (*addr)),
arch/x86/include/asm/apic.h
99
ASM_INPUT("0" (v), "m" (*addr)));
arch/x86/include/asm/archrandom.h
20
static inline bool __must_check rdrand_long(unsigned long *v)
arch/x86/include/asm/archrandom.h
26
: "=@ccc" (ok), [out] "=r" (*v));
arch/x86/include/asm/archrandom.h
33
static inline bool __must_check rdseed_long(unsigned long *v)
arch/x86/include/asm/archrandom.h
37
: "=@ccc" (ok), [out] "=r" (*v));
arch/x86/include/asm/archrandom.h
46
static inline size_t __must_check arch_get_random_longs(unsigned long *v, size_t max_longs)
arch/x86/include/asm/archrandom.h
48
return max_longs && static_cpu_has(X86_FEATURE_RDRAND) && rdrand_long(v) ? 1 : 0;
arch/x86/include/asm/archrandom.h
51
static inline size_t __must_check arch_get_random_seed_longs(unsigned long *v, size_t max_longs)
arch/x86/include/asm/archrandom.h
53
return max_longs && static_cpu_has(X86_FEATURE_RDSEED) && rdseed_long(v) ? 1 : 0;
arch/x86/include/asm/atomic.h
101
return arch_cmpxchg(&v->counter, old, new);
arch/x86/include/asm/atomic.h
105
static __always_inline bool arch_atomic_try_cmpxchg(atomic_t *v, int *old, int new)
arch/x86/include/asm/atomic.h
107
return arch_try_cmpxchg(&v->counter, old, new);
arch/x86/include/asm/atomic.h
111
static __always_inline int arch_atomic_xchg(atomic_t *v, int new)
arch/x86/include/asm/atomic.h
113
return arch_xchg(&v->counter, new);
arch/x86/include/asm/atomic.h
117
static __always_inline void arch_atomic_and(int i, atomic_t *v)
arch/x86/include/asm/atomic.h
120
: "+m" (v->counter)
arch/x86/include/asm/atomic.h
125
static __always_inline int arch_atomic_fetch_and(int i, atomic_t *v)
arch/x86/include/asm/atomic.h
127
int val = arch_atomic_read(v);
arch/x86/include/asm/atomic.h
129
do { } while (!arch_atomic_try_cmpxchg(v, &val, val & i));
arch/x86/include/asm/atomic.h
135
static __always_inline void arch_atomic_or(int i, atomic_t *v)
arch/x86/include/asm/atomic.h
138
: "+m" (v->counter)
arch/x86/include/asm/atomic.h
143
static __always_inline int arch_atomic_fetch_or(int i, atomic_t *v)
arch/x86/include/asm/atomic.h
145
int val = arch_atomic_read(v);
arch/x86/include/asm/atomic.h
147
do { } while (!arch_atomic_try_cmpxchg(v, &val, val | i));
arch/x86/include/asm/atomic.h
153
static __always_inline void arch_atomic_xor(int i, atomic_t *v)
arch/x86/include/asm/atomic.h
156
: "+m" (v->counter)
arch/x86/include/asm/atomic.h
161
static __always_inline int arch_atomic_fetch_xor(int i, atomic_t *v)
arch/x86/include/asm/atomic.h
163
int val = arch_atomic_read(v);
arch/x86/include/asm/atomic.h
165
do { } while (!arch_atomic_try_cmpxchg(v, &val, val ^ i));
arch/x86/include/asm/atomic.h
17
static __always_inline int arch_atomic_read(const atomic_t *v)
arch/x86/include/asm/atomic.h
23
return __READ_ONCE((v)->counter);
arch/x86/include/asm/atomic.h
26
static __always_inline void arch_atomic_set(atomic_t *v, int i)
arch/x86/include/asm/atomic.h
28
__WRITE_ONCE(v->counter, i);
arch/x86/include/asm/atomic.h
31
static __always_inline void arch_atomic_add(int i, atomic_t *v)
arch/x86/include/asm/atomic.h
34
: "+m" (v->counter)
arch/x86/include/asm/atomic.h
38
static __always_inline void arch_atomic_sub(int i, atomic_t *v)
arch/x86/include/asm/atomic.h
41
: "+m" (v->counter)
arch/x86/include/asm/atomic.h
45
static __always_inline bool arch_atomic_sub_and_test(int i, atomic_t *v)
arch/x86/include/asm/atomic.h
47
return GEN_BINARY_RMWcc(LOCK_PREFIX "subl", v->counter, e, "er", i);
arch/x86/include/asm/atomic.h
51
static __always_inline void arch_atomic_inc(atomic_t *v)
arch/x86/include/asm/atomic.h
54
: "+m" (v->counter) :: "memory");
arch/x86/include/asm/atomic.h
58
static __always_inline void arch_atomic_dec(atomic_t *v)
arch/x86/include/asm/atomic.h
61
: "+m" (v->counter) :: "memory");
arch/x86/include/asm/atomic.h
65
static __always_inline bool arch_atomic_dec_and_test(atomic_t *v)
arch/x86/include/asm/atomic.h
67
return GEN_UNARY_RMWcc(LOCK_PREFIX "decl", v->counter, e);
arch/x86/include/asm/atomic.h
71
static __always_inline bool arch_atomic_inc_and_test(atomic_t *v)
arch/x86/include/asm/atomic.h
73
return GEN_UNARY_RMWcc(LOCK_PREFIX "incl", v->counter, e);
arch/x86/include/asm/atomic.h
77
static __always_inline bool arch_atomic_add_negative(int i, atomic_t *v)
arch/x86/include/asm/atomic.h
79
return GEN_BINARY_RMWcc(LOCK_PREFIX "addl", v->counter, s, "er", i);
arch/x86/include/asm/atomic.h
83
static __always_inline int arch_atomic_add_return(int i, atomic_t *v)
arch/x86/include/asm/atomic.h
85
return i + xadd(&v->counter, i);
arch/x86/include/asm/atomic.h
89
#define arch_atomic_sub_return(i, v) arch_atomic_add_return(-(i), v)
arch/x86/include/asm/atomic.h
91
static __always_inline int arch_atomic_fetch_add(int i, atomic_t *v)
arch/x86/include/asm/atomic.h
93
return xadd(&v->counter, i);
arch/x86/include/asm/atomic.h
97
#define arch_atomic_fetch_sub(i, v) arch_atomic_fetch_add(-(i), v)
arch/x86/include/asm/atomic.h
99
static __always_inline int arch_atomic_cmpxchg(atomic_t *v, int old, int new)
arch/x86/include/asm/atomic64_32.h
100
static __always_inline bool arch_atomic64_try_cmpxchg(atomic64_t *v, s64 *old, s64 new)
arch/x86/include/asm/atomic64_32.h
102
return arch_try_cmpxchg64(&v->counter, old, new);
arch/x86/include/asm/atomic64_32.h
106
static __always_inline s64 arch_atomic64_xchg(atomic64_t *v, s64 n)
arch/x86/include/asm/atomic64_32.h
113
ASM_INPUT("S" (v), "b" (low), "c" (high)),
arch/x86/include/asm/atomic64_32.h
119
static __always_inline void arch_atomic64_set(atomic64_t *v, s64 i)
arch/x86/include/asm/atomic64_32.h
125
ASM_INPUT("S" (v), "b" (low), "c" (high)),
arch/x86/include/asm/atomic64_32.h
129
static __always_inline s64 arch_atomic64_read(const atomic64_t *v)
arch/x86/include/asm/atomic64_32.h
132
alternative_atomic64(read, "=&A" (r), "c" (v), "memory");
arch/x86/include/asm/atomic64_32.h
136
static __always_inline s64 arch_atomic64_add_return(s64 i, atomic64_t *v)
arch/x86/include/asm/atomic64_32.h
139
ASM_OUTPUT("+A" (i), "+c" (v)),
arch/x86/include/asm/atomic64_32.h
146
static __always_inline s64 arch_atomic64_sub_return(s64 i, atomic64_t *v)
arch/x86/include/asm/atomic64_32.h
149
ASM_OUTPUT("+A" (i), "+c" (v)),
arch/x86/include/asm/atomic64_32.h
156
static __always_inline s64 arch_atomic64_inc_return(atomic64_t *v)
arch/x86/include/asm/atomic64_32.h
161
"S" (v),
arch/x86/include/asm/atomic64_32.h
167
static __always_inline s64 arch_atomic64_dec_return(atomic64_t *v)
arch/x86/include/asm/atomic64_32.h
172
"S" (v),
arch/x86/include/asm/atomic64_32.h
178
static __always_inline void arch_atomic64_add(s64 i, atomic64_t *v)
arch/x86/include/asm/atomic64_32.h
181
ASM_OUTPUT("+A" (i), "+c" (v)),
arch/x86/include/asm/atomic64_32.h
186
static __always_inline void arch_atomic64_sub(s64 i, atomic64_t *v)
arch/x86/include/asm/atomic64_32.h
189
ASM_OUTPUT("+A" (i), "+c" (v)),
arch/x86/include/asm/atomic64_32.h
194
static __always_inline void arch_atomic64_inc(atomic64_t *v)
arch/x86/include/asm/atomic64_32.h
198
"S" (v),
arch/x86/include/asm/atomic64_32.h
203
static __always_inline void arch_atomic64_dec(atomic64_t *v)
arch/x86/include/asm/atomic64_32.h
207
"S" (v),
arch/x86/include/asm/atomic64_32.h
212
static __always_inline int arch_atomic64_add_unless(atomic64_t *v, s64 a, s64 u)
arch/x86/include/asm/atomic64_32.h
218
"S" (v),
arch/x86/include/asm/atomic64_32.h
224
static __always_inline int arch_atomic64_inc_not_zero(atomic64_t *v)
arch/x86/include/asm/atomic64_32.h
229
"S" (v),
arch/x86/include/asm/atomic64_32.h
235
static __always_inline s64 arch_atomic64_dec_if_positive(atomic64_t *v)
arch/x86/include/asm/atomic64_32.h
240
"S" (v),
arch/x86/include/asm/atomic64_32.h
249
static __always_inline void arch_atomic64_and(s64 i, atomic64_t *v)
arch/x86/include/asm/atomic64_32.h
251
s64 val = arch_atomic64_read_nonatomic(v);
arch/x86/include/asm/atomic64_32.h
253
do { } while (!arch_atomic64_try_cmpxchg(v, &val, val & i));
arch/x86/include/asm/atomic64_32.h
256
static __always_inline s64 arch_atomic64_fetch_and(s64 i, atomic64_t *v)
arch/x86/include/asm/atomic64_32.h
258
s64 val = arch_atomic64_read_nonatomic(v);
arch/x86/include/asm/atomic64_32.h
260
do { } while (!arch_atomic64_try_cmpxchg(v, &val, val & i));
arch/x86/include/asm/atomic64_32.h
266
static __always_inline void arch_atomic64_or(s64 i, atomic64_t *v)
arch/x86/include/asm/atomic64_32.h
268
s64 val = arch_atomic64_read_nonatomic(v);
arch/x86/include/asm/atomic64_32.h
270
do { } while (!arch_atomic64_try_cmpxchg(v, &val, val | i));
arch/x86/include/asm/atomic64_32.h
273
static __always_inline s64 arch_atomic64_fetch_or(s64 i, atomic64_t *v)
arch/x86/include/asm/atomic64_32.h
275
s64 val = arch_atomic64_read_nonatomic(v);
arch/x86/include/asm/atomic64_32.h
277
do { } while (!arch_atomic64_try_cmpxchg(v, &val, val | i));
arch/x86/include/asm/atomic64_32.h
283
static __always_inline void arch_atomic64_xor(s64 i, atomic64_t *v)
arch/x86/include/asm/atomic64_32.h
285
s64 val = arch_atomic64_read_nonatomic(v);
arch/x86/include/asm/atomic64_32.h
287
do { } while (!arch_atomic64_try_cmpxchg(v, &val, val ^ i));
arch/x86/include/asm/atomic64_32.h
290
static __always_inline s64 arch_atomic64_fetch_xor(s64 i, atomic64_t *v)
arch/x86/include/asm/atomic64_32.h
292
s64 val = arch_atomic64_read_nonatomic(v);
arch/x86/include/asm/atomic64_32.h
294
do { } while (!arch_atomic64_try_cmpxchg(v, &val, val ^ i));
arch/x86/include/asm/atomic64_32.h
300
static __always_inline s64 arch_atomic64_fetch_add(s64 i, atomic64_t *v)
arch/x86/include/asm/atomic64_32.h
302
s64 val = arch_atomic64_read_nonatomic(v);
arch/x86/include/asm/atomic64_32.h
304
do { } while (!arch_atomic64_try_cmpxchg(v, &val, val + i));
arch/x86/include/asm/atomic64_32.h
310
#define arch_atomic64_fetch_sub(i, v) arch_atomic64_fetch_add(-(i), (v))
arch/x86/include/asm/atomic64_32.h
37
static __always_inline s64 arch_atomic64_read_nonatomic(const atomic64_t *v)
arch/x86/include/asm/atomic64_32.h
40
return __READ_ONCE(v->counter);
arch/x86/include/asm/atomic64_32.h
94
static __always_inline s64 arch_atomic64_cmpxchg(atomic64_t *v, s64 old, s64 new)
arch/x86/include/asm/atomic64_32.h
96
return arch_cmpxchg64(&v->counter, old, new);
arch/x86/include/asm/atomic64_64.h
101
return arch_try_cmpxchg(&v->counter, old, new);
arch/x86/include/asm/atomic64_64.h
105
static __always_inline s64 arch_atomic64_xchg(atomic64_t *v, s64 new)
arch/x86/include/asm/atomic64_64.h
107
return arch_xchg(&v->counter, new);
arch/x86/include/asm/atomic64_64.h
111
static __always_inline void arch_atomic64_and(s64 i, atomic64_t *v)
arch/x86/include/asm/atomic64_64.h
114
: "+m" (v->counter)
arch/x86/include/asm/atomic64_64.h
119
static __always_inline s64 arch_atomic64_fetch_and(s64 i, atomic64_t *v)
arch/x86/include/asm/atomic64_64.h
121
s64 val = arch_atomic64_read(v);
arch/x86/include/asm/atomic64_64.h
124
} while (!arch_atomic64_try_cmpxchg(v, &val, val & i));
arch/x86/include/asm/atomic64_64.h
129
static __always_inline void arch_atomic64_or(s64 i, atomic64_t *v)
arch/x86/include/asm/atomic64_64.h
13
static __always_inline s64 arch_atomic64_read(const atomic64_t *v)
arch/x86/include/asm/atomic64_64.h
132
: "+m" (v->counter)
arch/x86/include/asm/atomic64_64.h
137
static __always_inline s64 arch_atomic64_fetch_or(s64 i, atomic64_t *v)
arch/x86/include/asm/atomic64_64.h
139
s64 val = arch_atomic64_read(v);
arch/x86/include/asm/atomic64_64.h
142
} while (!arch_atomic64_try_cmpxchg(v, &val, val | i));
arch/x86/include/asm/atomic64_64.h
147
static __always_inline void arch_atomic64_xor(s64 i, atomic64_t *v)
arch/x86/include/asm/atomic64_64.h
15
return __READ_ONCE((v)->counter);
arch/x86/include/asm/atomic64_64.h
150
: "+m" (v->counter)
arch/x86/include/asm/atomic64_64.h
155
static __always_inline s64 arch_atomic64_fetch_xor(s64 i, atomic64_t *v)
arch/x86/include/asm/atomic64_64.h
157
s64 val = arch_atomic64_read(v);
arch/x86/include/asm/atomic64_64.h
160
} while (!arch_atomic64_try_cmpxchg(v, &val, val ^ i));
arch/x86/include/asm/atomic64_64.h
18
static __always_inline void arch_atomic64_set(atomic64_t *v, s64 i)
arch/x86/include/asm/atomic64_64.h
20
__WRITE_ONCE(v->counter, i);
arch/x86/include/asm/atomic64_64.h
23
static __always_inline void arch_atomic64_add(s64 i, atomic64_t *v)
arch/x86/include/asm/atomic64_64.h
26
: "=m" (v->counter)
arch/x86/include/asm/atomic64_64.h
27
: "er" (i), "m" (v->counter) : "memory");
arch/x86/include/asm/atomic64_64.h
30
static __always_inline void arch_atomic64_sub(s64 i, atomic64_t *v)
arch/x86/include/asm/atomic64_64.h
33
: "=m" (v->counter)
arch/x86/include/asm/atomic64_64.h
34
: "er" (i), "m" (v->counter) : "memory");
arch/x86/include/asm/atomic64_64.h
37
static __always_inline bool arch_atomic64_sub_and_test(s64 i, atomic64_t *v)
arch/x86/include/asm/atomic64_64.h
39
return GEN_BINARY_RMWcc(LOCK_PREFIX "subq", v->counter, e, "er", i);
arch/x86/include/asm/atomic64_64.h
43
static __always_inline void arch_atomic64_inc(atomic64_t *v)
arch/x86/include/asm/atomic64_64.h
46
: "=m" (v->counter)
arch/x86/include/asm/atomic64_64.h
47
: "m" (v->counter) : "memory");
arch/x86/include/asm/atomic64_64.h
51
static __always_inline void arch_atomic64_dec(atomic64_t *v)
arch/x86/include/asm/atomic64_64.h
54
: "=m" (v->counter)
arch/x86/include/asm/atomic64_64.h
55
: "m" (v->counter) : "memory");
arch/x86/include/asm/atomic64_64.h
59
static __always_inline bool arch_atomic64_dec_and_test(atomic64_t *v)
arch/x86/include/asm/atomic64_64.h
61
return GEN_UNARY_RMWcc(LOCK_PREFIX "decq", v->counter, e);
arch/x86/include/asm/atomic64_64.h
65
static __always_inline bool arch_atomic64_inc_and_test(atomic64_t *v)
arch/x86/include/asm/atomic64_64.h
67
return GEN_UNARY_RMWcc(LOCK_PREFIX "incq", v->counter, e);
arch/x86/include/asm/atomic64_64.h
71
static __always_inline bool arch_atomic64_add_negative(s64 i, atomic64_t *v)
arch/x86/include/asm/atomic64_64.h
73
return GEN_BINARY_RMWcc(LOCK_PREFIX "addq", v->counter, s, "er", i);
arch/x86/include/asm/atomic64_64.h
77
static __always_inline s64 arch_atomic64_add_return(s64 i, atomic64_t *v)
arch/x86/include/asm/atomic64_64.h
79
return i + xadd(&v->counter, i);
arch/x86/include/asm/atomic64_64.h
83
#define arch_atomic64_sub_return(i, v) arch_atomic64_add_return(-(i), v)
arch/x86/include/asm/atomic64_64.h
85
static __always_inline s64 arch_atomic64_fetch_add(s64 i, atomic64_t *v)
arch/x86/include/asm/atomic64_64.h
87
return xadd(&v->counter, i);
arch/x86/include/asm/atomic64_64.h
91
#define arch_atomic64_fetch_sub(i, v) arch_atomic64_fetch_add(-(i), v)
arch/x86/include/asm/atomic64_64.h
93
static __always_inline s64 arch_atomic64_cmpxchg(atomic64_t *v, s64 old, s64 new)
arch/x86/include/asm/atomic64_64.h
95
return arch_cmpxchg(&v->counter, old, new);
arch/x86/include/asm/atomic64_64.h
99
static __always_inline bool arch_atomic64_try_cmpxchg(atomic64_t *v, s64 *old, s64 new)
arch/x86/include/asm/barrier.h
59
#define __smp_store_release(p, v) \
arch/x86/include/asm/barrier.h
63
WRITE_ONCE(*p, v); \
arch/x86/include/asm/cmpxchg.h
78
#define arch_xchg(ptr, v) __xchg_op((ptr), (v), xchg, "")
arch/x86/include/asm/elf.h
190
unsigned v; \
arch/x86/include/asm/elf.h
214
asm("movl %%ds,%0" : "=r" (v)); (pr_reg)[23] = v; \
arch/x86/include/asm/elf.h
215
asm("movl %%es,%0" : "=r" (v)); (pr_reg)[24] = v; \
arch/x86/include/asm/elf.h
216
asm("movl %%fs,%0" : "=r" (v)); (pr_reg)[25] = v; \
arch/x86/include/asm/elf.h
217
asm("movl %%gs,%0" : "=r" (v)); (pr_reg)[26] = v; \
arch/x86/include/asm/insn.h
26
static inline void insn_field_set(struct insn_field *p, insn_value_t v,
arch/x86/include/asm/insn.h
29
p->value = v;
arch/x86/include/asm/insn.h
34
insn_byte_t v)
arch/x86/include/asm/insn.h
36
p->bytes[n] = v;
arch/x86/include/asm/insn.h
52
static inline void insn_field_set(struct insn_field *p, insn_value_t v,
arch/x86/include/asm/insn.h
55
p->value = v;
arch/x86/include/asm/insn.h
56
p->little = __cpu_to_le32(v);
arch/x86/include/asm/insn.h
61
insn_byte_t v)
arch/x86/include/asm/insn.h
63
p->bytes[n] = v;
arch/x86/include/asm/io.h
101
#define writeq_relaxed(v, a) __writeq(v, a)
arch/x86/include/asm/io.h
86
#define writeb_relaxed(v, a) __writeb(v, a)
arch/x86/include/asm/io.h
87
#define writew_relaxed(v, a) __writew(v, a)
arch/x86/include/asm/io.h
88
#define writel_relaxed(v, a) __writel(v, a)
arch/x86/include/asm/iosf_mbi.h
237
int iosf_mbi_call_pmic_bus_access_notifier_chain(unsigned long val, void *v)
arch/x86/include/asm/kvm_host.h
2181
#define EMULTYPE_SET_SOFT_INT_VECTOR(v) ((u32)((v) & 0xff) << 16)
arch/x86/include/asm/kvm_host.h
2394
int kvm_cpu_has_injectable_intr(struct kvm_vcpu *v);
arch/x86/include/asm/kvm_host.h
2396
int kvm_cpu_has_extint(struct kvm_vcpu *v);
arch/x86/include/asm/kvm_host.h
2398
int kvm_cpu_get_extint(struct kvm_vcpu *v);
arch/x86/include/asm/kvm_host.h
2399
int kvm_cpu_get_interrupt(struct kvm_vcpu *v);
arch/x86/include/asm/perf_event_p4.h
40
#define P4_ESCR_EVENT(v) ((v) << P4_ESCR_EVENT_SHIFT)
arch/x86/include/asm/perf_event_p4.h
41
#define P4_ESCR_EMASK(v) ((v) << P4_ESCR_EVENTMASK_SHIFT)
arch/x86/include/asm/perf_event_p4.h
42
#define P4_ESCR_TAG(v) ((v) << P4_ESCR_TAG_SHIFT)
arch/x86/include/asm/perf_event_p4.h
62
#define P4_CCCR_THRESHOLD(v) ((v) << P4_CCCR_THRESHOLD_SHIFT)
arch/x86/include/asm/perf_event_p4.h
63
#define P4_CCCR_ESEL(v) ((v) << P4_CCCR_ESCR_SELECT_SHIFT)
arch/x86/include/asm/perf_event_p4.h
800
#define p4_config_unpack_metric(v) (((u64)(v)) & P4_PEBS_CONFIG_METRIC_MASK)
arch/x86/include/asm/perf_event_p4.h
801
#define p4_config_unpack_pebs(v) (((u64)(v)) & P4_PEBS_CONFIG_MASK)
arch/x86/include/asm/perf_event_p4.h
803
#define p4_config_pebs_has(v, mask) (p4_config_unpack_pebs(v) & (mask))
arch/x86/include/asm/perf_event_p4.h
81
#define p4_config_pack_escr(v) (((u64)(v)) << 32)
arch/x86/include/asm/perf_event_p4.h
82
#define p4_config_pack_cccr(v) (((u64)(v)) & 0xffffffffULL)
arch/x86/include/asm/perf_event_p4.h
83
#define p4_config_unpack_escr(v) (((u64)(v)) >> 32)
arch/x86/include/asm/perf_event_p4.h
84
#define p4_config_unpack_cccr(v) (((u64)(v)) & 0xffffffffULL)
arch/x86/include/asm/perf_event_p4.h
86
#define p4_config_unpack_emask(v) \
arch/x86/include/asm/perf_event_p4.h
88
u32 t = p4_config_unpack_escr((v)); \
arch/x86/include/asm/perf_event_p4.h
94
#define p4_config_unpack_event(v) \
arch/x86/include/asm/perf_event_p4.h
96
u32 t = p4_config_unpack_escr((v)); \
arch/x86/include/asm/pgtable.h
126
pmdval_t v = native_pmd_val(pmd);
arch/x86/include/asm/pgtable.h
128
return native_make_pmd(v | set);
arch/x86/include/asm/pgtable.h
133
pmdval_t v = native_pmd_val(pmd);
arch/x86/include/asm/pgtable.h
135
return native_make_pmd(v & ~clear);
arch/x86/include/asm/pgtable.h
140
pudval_t v = native_pud_val(pud);
arch/x86/include/asm/pgtable.h
142
return native_make_pud(v | set);
arch/x86/include/asm/pgtable.h
147
pudval_t v = native_pud_val(pud);
arch/x86/include/asm/pgtable.h
149
return native_make_pud(v & ~clear);
arch/x86/include/asm/pgtable.h
350
pteval_t v = native_pte_val(pte);
arch/x86/include/asm/pgtable.h
352
return native_make_pte(v | set);
arch/x86/include/asm/pgtable.h
357
pteval_t v = native_pte_val(pte);
arch/x86/include/asm/pgtable.h
359
return native_make_pte(v & ~clear);
arch/x86/include/asm/pgtable.h
373
static inline pgprotval_t mksaveddirty_shift(pgprotval_t v)
arch/x86/include/asm/pgtable.h
375
pgprotval_t cond = (~v >> _PAGE_BIT_RW) & 1;
arch/x86/include/asm/pgtable.h
377
v |= ((v >> _PAGE_BIT_DIRTY) & cond) << _PAGE_BIT_SAVED_DIRTY;
arch/x86/include/asm/pgtable.h
378
v &= ~(cond << _PAGE_BIT_DIRTY);
arch/x86/include/asm/pgtable.h
380
return v;
arch/x86/include/asm/pgtable.h
383
static inline pgprotval_t clear_saveddirty_shift(pgprotval_t v)
arch/x86/include/asm/pgtable.h
385
pgprotval_t cond = (v >> _PAGE_BIT_RW) & 1;
arch/x86/include/asm/pgtable.h
387
v |= ((v >> _PAGE_BIT_SAVED_DIRTY) & cond) << _PAGE_BIT_DIRTY;
arch/x86/include/asm/pgtable.h
388
v &= ~(cond << _PAGE_BIT_SAVED_DIRTY);
arch/x86/include/asm/pgtable.h
390
return v;
arch/x86/include/asm/pgtable.h
395
pteval_t v = native_pte_val(pte);
arch/x86/include/asm/pgtable.h
397
v = mksaveddirty_shift(v);
arch/x86/include/asm/pgtable.h
398
return native_make_pte(v);
arch/x86/include/asm/pgtable.h
403
pteval_t v = native_pte_val(pte);
arch/x86/include/asm/pgtable.h
405
v = clear_saveddirty_shift(v);
arch/x86/include/asm/pgtable.h
406
return native_make_pte(v);
arch/x86/include/asm/pgtable.h
509
pmdval_t v = native_pmd_val(pmd);
arch/x86/include/asm/pgtable.h
511
v = mksaveddirty_shift(v);
arch/x86/include/asm/pgtable.h
512
return native_make_pmd(v);
arch/x86/include/asm/pgtable.h
518
pmdval_t v = native_pmd_val(pmd);
arch/x86/include/asm/pgtable.h
520
v = clear_saveddirty_shift(v);
arch/x86/include/asm/pgtable.h
521
return native_make_pmd(v);
arch/x86/include/asm/pgtable.h
598
pudval_t v = native_pud_val(pud);
arch/x86/include/asm/pgtable.h
600
v = mksaveddirty_shift(v);
arch/x86/include/asm/pgtable.h
601
return native_make_pud(v);
arch/x86/include/asm/pgtable.h
607
pudval_t v = native_pud_val(pud);
arch/x86/include/asm/pgtable.h
609
v = clear_saveddirty_shift(v);
arch/x86/include/asm/pgtable.h
610
return native_make_pud(v);
arch/x86/include/asm/pgtable_64.h
249
#define kc_vaddr_to_offset(v) ((v) & __VIRTUAL_MASK)
arch/x86/include/asm/sev-common.h
117
#define GHCB_MSR_VMPL_REQ_LEVEL(v) \
arch/x86/include/asm/sev-common.h
119
((((u64)(v) & GENMASK_ULL(7, 0)) << 32) | \
arch/x86/include/asm/sev-common.h
124
#define GHCB_MSR_VMPL_RESP_VAL(v) \
arch/x86/include/asm/sev-common.h
126
(((u64)(v) & GENMASK_ULL(63, 32)) >> 32)
arch/x86/include/asm/sev-common.h
133
#define GHCB_MSR_HV_FT_RESP_VAL(v) \
arch/x86/include/asm/sev-common.h
135
(((u64)(v) & GENMASK_ULL(63, 12)) >> 12)
arch/x86/include/asm/sev-common.h
15
#define GHCB_DATA(v) \
arch/x86/include/asm/sev-common.h
16
(((unsigned long)(v) & ~GHCB_MSR_INFO_MASK) >> GHCB_DATA_LOW)
arch/x86/include/asm/sev-common.h
213
#define GHCB_RESP_CODE(v) ((v) & GHCB_MSR_INFO_MASK)
arch/x86/include/asm/sev-common.h
31
#define GHCB_MSR_INFO(v) ((v) & 0xfffUL)
arch/x86/include/asm/sev-common.h
32
#define GHCB_MSR_PROTO_MAX(v) (((v) >> 48) & 0xffff)
arch/x86/include/asm/sev-common.h
33
#define GHCB_MSR_PROTO_MIN(v) (((v) >> 32) & 0xffff)
arch/x86/include/asm/sev-common.h
72
#define GHCB_MSR_REG_GPA_REQ_VAL(v) \
arch/x86/include/asm/sev-common.h
74
(((u64)((v) & GENMASK_ULL(51, 0)) << 12) | \
arch/x86/include/asm/sev-common.h
79
#define GHCB_MSR_REG_GPA_RESP_VAL(v) \
arch/x86/include/asm/sev-common.h
81
(((u64)(v) & GENMASK_ULL(63, 12)) >> 12)
arch/x86/include/asm/string.h
21
static __always_inline void *__inline_memset(void *s, int v, size_t n)
arch/x86/include/asm/string.h
27
: "a" ((uint8_t)v)
arch/x86/include/asm/string_32.h
198
static inline void *memset16(uint16_t *s, uint16_t v, size_t n)
arch/x86/include/asm/string_32.h
203
: "a" (v), "1" (s), "0" (n)
arch/x86/include/asm/string_32.h
209
static inline void *memset32(uint32_t *s, uint32_t v, size_t n)
arch/x86/include/asm/string_32.h
214
: "a" (v), "1" (s), "0" (n)
arch/x86/include/asm/string_64.h
32
static inline void *memset16(uint16_t *s, uint16_t v, size_t n)
arch/x86/include/asm/string_64.h
38
: "a" (v)
arch/x86/include/asm/string_64.h
45
static inline void *memset32(uint32_t *s, uint32_t v, size_t n)
arch/x86/include/asm/string_64.h
51
: "a" (v)
arch/x86/include/asm/string_64.h
58
static inline void *memset64(uint64_t *s, uint64_t v, size_t n)
arch/x86/include/asm/string_64.h
64
: "a" (v)
arch/x86/include/asm/uv/uv_hub.h
259
unsigned long v;
arch/x86/include/asm/uv/uv_hub.h
427
static inline unsigned long uv_gpa_nasid(void *v)
arch/x86/include/asm/uv/uv_hub.h
429
return uv_soc_phys_ram_to_nasid(__pa(v));
arch/x86/include/asm/uv/uv_hub.h
454
static inline unsigned long uv_gpa(void *v)
arch/x86/include/asm/uv/uv_hub.h
456
return uv_soc_phys_ram_to_gpa(__pa(v));
arch/x86/include/asm/uv/uv_mmrs.h
1327
unsigned long v;
arch/x86/include/asm/uv/uv_mmrs.h
1917
unsigned long v;
arch/x86/include/asm/uv/uv_mmrs.h
2144
unsigned long v;
arch/x86/include/asm/uv/uv_mmrs.h
2209
unsigned long v;
arch/x86/include/asm/uv/uv_mmrs.h
2277
unsigned long v;
arch/x86/include/asm/uv/uv_mmrs.h
2380
unsigned long v;
arch/x86/include/asm/uv/uv_mmrs.h
2483
unsigned long v;
arch/x86/include/asm/uv/uv_mmrs.h
2586
unsigned long v;
arch/x86/include/asm/uv/uv_mmrs.h
2670
unsigned long v;
arch/x86/include/asm/uv/uv_mmrs.h
2722
unsigned long v;
arch/x86/include/asm/uv/uv_mmrs.h
2821
unsigned long v;
arch/x86/include/asm/uv/uv_mmrs.h
2927
unsigned long v;
arch/x86/include/asm/uv/uv_mmrs.h
2959
unsigned long v;
arch/x86/include/asm/uv/uv_mmrs.h
2999
unsigned long v;
arch/x86/include/asm/uv/uv_mmrs.h
3045
unsigned long v;
arch/x86/include/asm/uv/uv_mmrs.h
3104
unsigned long v;
arch/x86/include/asm/uv/uv_mmrs.h
3158
unsigned long v;
arch/x86/include/asm/uv/uv_mmrs.h
3215
unsigned long v;
arch/x86/include/asm/uv/uv_mmrs.h
3266
unsigned long v;
arch/x86/include/asm/uv/uv_mmrs.h
3305
unsigned long v;
arch/x86/include/asm/uv/uv_mmrs.h
3348
unsigned long v;
arch/x86/include/asm/uv/uv_mmrs.h
3399
unsigned long v;
arch/x86/include/asm/uv/uv_mmrs.h
3457
unsigned long v;
arch/x86/include/asm/uv/uv_mmrs.h
3526
unsigned long v;
arch/x86/include/asm/uv/uv_mmrs.h
3584
unsigned long v;
arch/x86/include/asm/uv/uv_mmrs.h
3653
unsigned long v;
arch/x86/include/asm/uv/uv_mmrs.h
3711
unsigned long v;
arch/x86/include/asm/uv/uv_mmrs.h
3780
unsigned long v;
arch/x86/include/asm/uv/uv_mmrs.h
3865
unsigned long v;
arch/x86/include/asm/uv/uv_mmrs.h
3952
unsigned long v;
arch/x86/include/asm/uv/uv_mmrs.h
4028
unsigned long v;
arch/x86/include/asm/uv/uv_mmrs.h
4124
unsigned long v;
arch/x86/include/asm/uv/uv_mmrs.h
4211
unsigned long v;
arch/x86/include/asm/uv/uv_mmrs.h
4277
unsigned long v;
arch/x86/include/asm/uv/uv_mmrs.h
4348
unsigned long v;
arch/x86/include/asm/uv/uv_mmrs.h
4407
unsigned long v;
arch/x86/include/asm/uv/uv_mmrs.h
4465
unsigned long v;
arch/x86/include/asm/uv/uv_mmrs.h
4582
unsigned long v;
arch/x86/include/asm/uv/uv_mmrs.h
551
unsigned long v;
arch/x86/include/asm/xen/page.h
297
#define virt_to_machine(v) (phys_to_machine(XPADDR(__pa(v))))
arch/x86/include/asm/xen/page.h
298
static inline unsigned long virt_to_pfn(const void *v)
arch/x86/include/asm/xen/page.h
300
return PFN_DOWN(__pa(v));
arch/x86/include/asm/xen/page.h
302
#define virt_to_mfn(v) (pfn_to_mfn(virt_to_pfn(v)))
arch/x86/include/asm/xen/page.h
306
#define virt_to_gfn(v) (pfn_to_gfn(virt_to_pfn(v)))
arch/x86/include/asm/xen/page.h
334
#define pmd_val_ma(v) ((v).pmd)
arch/x86/include/asm/xen/page.h
336
#define pud_val_ma(v) ((v).p4d.pgd.pgd)
arch/x86/include/asm/xen/page.h
338
#define pud_val_ma(v) ((v).pud)
arch/x86/include/uapi/asm/swab.h
24
} v;
arch/x86/include/uapi/asm/swab.h
25
v.u = val;
arch/x86/include/uapi/asm/swab.h
27
: "=r" (v.s.a), "=r" (v.s.b)
arch/x86/include/uapi/asm/swab.h
28
: "0" (v.s.a), "1" (v.s.b));
arch/x86/include/uapi/asm/swab.h
29
return v.u;
arch/x86/kernel/alternative.c
438
s32 v = *(s##n_ *)(p_); \
arch/x86/kernel/alternative.c
439
v += (d_); \
arch/x86/kernel/alternative.c
440
BUG_ON((v >> 31) != (v >> (n_-1))); \
arch/x86/kernel/alternative.c
441
*(s##n_ *)(p_) = (s##n_)v; \
arch/x86/kernel/amd_node.c
161
static int smn_node_show(struct seq_file *m, void *v)
arch/x86/kernel/amd_node.c
179
static int smn_address_show(struct seq_file *m, void *v)
arch/x86/kernel/amd_node.c
185
static int smn_value_show(struct seq_file *m, void *v)
arch/x86/kernel/apic/apic.c
1082
u32 v;
arch/x86/kernel/apic/apic.c
1093
v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
arch/x86/kernel/apic/apic.c
1094
apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
arch/x86/kernel/apic/apic.c
1100
v = apic_read(APIC_LVTT);
arch/x86/kernel/apic/apic.c
1101
apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
arch/x86/kernel/apic/apic.c
1102
v = apic_read(APIC_LVT0);
arch/x86/kernel/apic/apic.c
1103
apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
arch/x86/kernel/apic/apic.c
1104
v = apic_read(APIC_LVT1);
arch/x86/kernel/apic/apic.c
1105
apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
arch/x86/kernel/apic/apic.c
1107
v = apic_read(APIC_LVTPC);
arch/x86/kernel/apic/apic.c
1108
apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
arch/x86/kernel/apic/apic.c
1114
v = apic_read(APIC_LVTTHMR);
arch/x86/kernel/apic/apic.c
1115
apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);
arch/x86/kernel/apic/apic.c
1120
v = apic_read(APIC_LVTCMCI);
arch/x86/kernel/apic/apic.c
1121
if (!(v & APIC_LVT_MASKED))
arch/x86/kernel/apic/apic.c
1122
apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED);
arch/x86/kernel/apic/apic.c
2108
u32 v;
arch/x86/kernel/apic/apic.c
2128
v = apic_read(APIC_ISR + ((vector & ~0x1f) >> 1));
arch/x86/kernel/apic/apic.c
2129
if (v & (1 << (vector & 0x1f))) {
arch/x86/kernel/apic/apic.c
2175
u32 v, i = 0;
arch/x86/kernel/apic/apic.c
2182
v = apic_read(APIC_ESR);
arch/x86/kernel/apic/apic.c
2186
apic_pr_debug("APIC error on CPU%d: %02x", smp_processor_id(), v);
arch/x86/kernel/apic/apic.c
2188
v &= 0xff;
arch/x86/kernel/apic/apic.c
2189
while (v) {
arch/x86/kernel/apic/apic.c
2190
if (v & 0x1)
arch/x86/kernel/apic/apic.c
2193
v >>= 1;
arch/x86/kernel/apic/apic.c
437
unsigned int v;
arch/x86/kernel/apic/apic.c
443
v = apic_read(APIC_LVTT);
arch/x86/kernel/apic/apic.c
444
v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
arch/x86/kernel/apic/apic.c
445
apic_write(APIC_LVTT, v);
arch/x86/kernel/apic/apic.c
454
if (v & APIC_LVT_TIMER_TSCDEADLINE)
arch/x86/kernel/apic/io_apic.c
1660
unsigned long v;
arch/x86/kernel/apic/io_apic.c
1700
v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
arch/x86/kernel/apic/io_apic.c
1715
if (!(v & (1 << (i & 0x1f)))) {
arch/x86/kernel/apic/io_apic.c
1908
unsigned long v = apic_read(APIC_LVT0);
arch/x86/kernel/apic/io_apic.c
1910
apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
arch/x86/kernel/apic/io_apic.c
1915
unsigned long v = apic_read(APIC_LVT0);
arch/x86/kernel/apic/io_apic.c
1917
apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
arch/x86/kernel/apic/vector.c
1200
unsigned int i, v, ver, maxlvt;
arch/x86/kernel/apic/vector.c
1205
v = apic_read(APIC_ID);
arch/x86/kernel/apic/vector.c
1206
pr_info("... APIC ID: %08x (%01x)\n", v, read_apic_id());
arch/x86/kernel/apic/vector.c
1207
v = apic_read(APIC_LVR);
arch/x86/kernel/apic/vector.c
1208
pr_info("... APIC VERSION: %08x\n", v);
arch/x86/kernel/apic/vector.c
1209
ver = GET_APIC_VERSION(v);
arch/x86/kernel/apic/vector.c
1212
v = apic_read(APIC_TASKPRI);
arch/x86/kernel/apic/vector.c
1213
pr_debug("... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
arch/x86/kernel/apic/vector.c
1218
v = apic_read(APIC_ARBPRI);
arch/x86/kernel/apic/vector.c
1220
v, v & APIC_ARBPRI_MASK);
arch/x86/kernel/apic/vector.c
1222
v = apic_read(APIC_PROCPRI);
arch/x86/kernel/apic/vector.c
1223
pr_debug("... APIC PROCPRI: %08x\n", v);
arch/x86/kernel/apic/vector.c
1231
v = apic_read(APIC_RRR);
arch/x86/kernel/apic/vector.c
1232
pr_debug("... APIC RRR: %08x\n", v);
arch/x86/kernel/apic/vector.c
1235
v = apic_read(APIC_LDR);
arch/x86/kernel/apic/vector.c
1236
pr_debug("... APIC LDR: %08x\n", v);
arch/x86/kernel/apic/vector.c
1238
v = apic_read(APIC_DFR);
arch/x86/kernel/apic/vector.c
1239
pr_debug("... APIC DFR: %08x\n", v);
arch/x86/kernel/apic/vector.c
1241
v = apic_read(APIC_SPIV);
arch/x86/kernel/apic/vector.c
1242
pr_debug("... APIC SPIV: %08x\n", v);
arch/x86/kernel/apic/vector.c
1257
v = apic_read(APIC_ESR);
arch/x86/kernel/apic/vector.c
1258
pr_debug("... APIC ESR: %08x\n", v);
arch/x86/kernel/apic/vector.c
1265
v = apic_read(APIC_LVTT);
arch/x86/kernel/apic/vector.c
1266
pr_debug("... APIC LVTT: %08x\n", v);
arch/x86/kernel/apic/vector.c
1270
v = apic_read(APIC_LVTPC);
arch/x86/kernel/apic/vector.c
1271
pr_debug("... APIC LVTPC: %08x\n", v);
arch/x86/kernel/apic/vector.c
1273
v = apic_read(APIC_LVT0);
arch/x86/kernel/apic/vector.c
1274
pr_debug("... APIC LVT0: %08x\n", v);
arch/x86/kernel/apic/vector.c
1275
v = apic_read(APIC_LVT1);
arch/x86/kernel/apic/vector.c
1276
pr_debug("... APIC LVT1: %08x\n", v);
arch/x86/kernel/apic/vector.c
1280
v = apic_read(APIC_LVTERR);
arch/x86/kernel/apic/vector.c
1281
pr_debug("... APIC LVTERR: %08x\n", v);
arch/x86/kernel/apic/vector.c
1284
v = apic_read(APIC_TMICT);
arch/x86/kernel/apic/vector.c
1285
pr_debug("... APIC TMICT: %08x\n", v);
arch/x86/kernel/apic/vector.c
1286
v = apic_read(APIC_TMCCT);
arch/x86/kernel/apic/vector.c
1287
pr_debug("... APIC TMCCT: %08x\n", v);
arch/x86/kernel/apic/vector.c
1288
v = apic_read(APIC_TDCR);
arch/x86/kernel/apic/vector.c
1289
pr_debug("... APIC TDCR: %08x\n", v);
arch/x86/kernel/apic/vector.c
1292
v = apic_read(APIC_EFEAT);
arch/x86/kernel/apic/vector.c
1293
maxlvt = (v >> 16) & 0xff;
arch/x86/kernel/apic/vector.c
1294
pr_debug("... APIC EFEAT: %08x\n", v);
arch/x86/kernel/apic/vector.c
1295
v = apic_read(APIC_ECTRL);
arch/x86/kernel/apic/vector.c
1296
pr_debug("... APIC ECTRL: %08x\n", v);
arch/x86/kernel/apic/vector.c
1298
v = apic_read(APIC_EILVTn(i));
arch/x86/kernel/apic/vector.c
1299
pr_debug("... APIC EILVT%d: %08x\n", i, v);
arch/x86/kernel/apic/vector.c
1323
unsigned int v;
arch/x86/kernel/apic/vector.c
1333
v = inb(0xa1) << 8 | inb(0x21);
arch/x86/kernel/apic/vector.c
1334
pr_debug("... PIC IMR: %04x\n", v);
arch/x86/kernel/apic/vector.c
1336
v = inb(0xa0) << 8 | inb(0x20);
arch/x86/kernel/apic/vector.c
1337
pr_debug("... PIC IRR: %04x\n", v);
arch/x86/kernel/apic/vector.c
1341
v = inb(0xa0) << 8 | inb(0x20);
arch/x86/kernel/apic/vector.c
1347
pr_debug("... PIC ISR: %04x\n", v);
arch/x86/kernel/apic/vector.c
1349
v = inb(PIC_ELCR2) << 8 | inb(PIC_ELCR1);
arch/x86/kernel/apic/vector.c
1350
pr_debug("... PIC ELCR: %04x\n", v);
arch/x86/kernel/apic/x2apic_uv_x.c
1037
mmioh0.v = uv_read_local_mmr(UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG0);
arch/x86/kernel/apic/x2apic_uv_x.c
1045
mmioh1.v = uv_read_local_mmr(UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG1);
arch/x86/kernel/apic/x2apic_uv_x.c
1059
mmioh0.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0);
arch/x86/kernel/apic/x2apic_uv_x.c
107
m_n_config.v = uv_early_read_mmr(UVH_RH10_GAM_ADDR_MAP_CONFIG);
arch/x86/kernel/apic/x2apic_uv_x.c
1072
mmioh1.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1);
arch/x86/kernel/apic/x2apic_uv_x.c
1091
mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG);
arch/x86/kernel/apic/x2apic_uv_x.c
113
m_n_config.v = uv_early_read_mmr(UVH_RH_GAM_ADDR_MAP_CONFIG);
arch/x86/kernel/apic/x2apic_uv_x.c
1179
m_gr_config.v = uv_read_local_mmr(UVH_GR0_GAM_GR_CONFIG);
arch/x86/kernel/apic/x2apic_uv_x.c
152
node_id.v = uv_early_read_mmr(UVH_NODE_ID);
arch/x86/kernel/apic/x2apic_uv_x.c
249
uvh_apicid.v = uv_early_read_mmr(UVH_APICID);
arch/x86/kernel/apic/x2apic_uv_x.c
812
alias.v = uv_read_local_mmr(m_overlay);
arch/x86/kernel/apic/x2apic_uv_x.c
815
redirect.v = uv_read_local_mmr(m_redirect);
arch/x86/kernel/apic/x2apic_uv_x.c
852
gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG);
arch/x86/kernel/apic/x2apic_uv_x.c
856
gru.v = uv_read_local_mmr(UVH_RH10_GAM_GRU_OVERLAY_CONFIG);
arch/x86/kernel/apic/x2apic_uv_x.c
869
base = (gru.v & mask) >> shift;
arch/x86/kernel/apic/x2apic_uv_x.c
884
mmr.v = uv_read_local_mmr(UVH_RH10_GAM_MMR_OVERLAY_CONFIG);
arch/x86/kernel/apic/x2apic_uv_x.c
891
mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG);
arch/x86/kernel/apm_32.c
1606
static int proc_apm_show(struct seq_file *m, void *v)
arch/x86/kernel/bootflag.c
24
static void __init sbf_write(u8 v)
arch/x86/kernel/bootflag.c
29
if (!parity8(v))
arch/x86/kernel/bootflag.c
30
v ^= SBF_PARITY;
arch/x86/kernel/bootflag.c
33
sbf_port, v);
arch/x86/kernel/bootflag.c
36
CMOS_WRITE(v, sbf_port);
arch/x86/kernel/bootflag.c
44
u8 v;
arch/x86/kernel/bootflag.c
50
v = CMOS_READ(sbf_port);
arch/x86/kernel/bootflag.c
53
return v;
arch/x86/kernel/bootflag.c
56
static bool __init sbf_value_valid(u8 v)
arch/x86/kernel/bootflag.c
58
if (v & SBF_RESERVED) /* Reserved bits */
arch/x86/kernel/bootflag.c
60
if (!parity8(v))
arch/x86/kernel/bootflag.c
68
u8 v;
arch/x86/kernel/bootflag.c
73
v = sbf_read();
arch/x86/kernel/bootflag.c
74
if (!sbf_value_valid(v)) {
arch/x86/kernel/bootflag.c
76
"CMOS RAM was invalid\n", v);
arch/x86/kernel/bootflag.c
79
v &= ~SBF_RESERVED;
arch/x86/kernel/bootflag.c
80
v &= ~SBF_BOOTING;
arch/x86/kernel/bootflag.c
81
v &= ~SBF_DIAG;
arch/x86/kernel/bootflag.c
83
v |= SBF_PNPOS;
arch/x86/kernel/bootflag.c
85
sbf_write(v);
arch/x86/kernel/cpu/common.c
826
unsigned int *v;
arch/x86/kernel/cpu/common.c
832
v = (unsigned int *)c->x86_model_id;
arch/x86/kernel/cpu/common.c
833
cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
arch/x86/kernel/cpu/common.c
834
cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
arch/x86/kernel/cpu/common.c
835
cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
arch/x86/kernel/cpu/common.c
916
char *v = c->x86_vendor_id;
arch/x86/kernel/cpu/common.c
923
if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
arch/x86/kernel/cpu/common.c
925
!strcmp(v, cpu_devs[i]->c_ident[1]))) {
arch/x86/kernel/cpu/common.c
934
"CPU: Your system may be unstable.\n", v);
arch/x86/kernel/cpu/mce/core.c
427
noinstr void mce_wrmsrq(u32 msr, u64 v)
arch/x86/kernel/cpu/mce/core.c
438
*(u64 *)((char *)this_cpu_ptr(&injectm) + offset) = v;
arch/x86/kernel/cpu/mce/core.c
445
low = (u32)v;
arch/x86/kernel/cpu/mce/core.c
446
high = (u32)(v >> 32);
arch/x86/kernel/cpu/mce/internal.h
328
noinstr void mce_wrmsrq(u32 msr, u64 v);
arch/x86/kernel/cpu/proc.c
167
static void *c_next(struct seq_file *m, void *v, loff_t *pos)
arch/x86/kernel/cpu/proc.c
173
static void c_stop(struct seq_file *m, void *v)
arch/x86/kernel/cpu/proc.c
63
static int show_cpuinfo(struct seq_file *m, void *v)
arch/x86/kernel/cpu/proc.c
65
struct cpuinfo_x86 *c = v;
arch/x86/kernel/setup.c
832
dump_kernel_offset(struct notifier_block *self, unsigned long v, void *p)
arch/x86/kernel/signal_32.c
208
#define get_user_seg(seg) ({ unsigned int v; savesegment(seg, v); v; })
arch/x86/kernel/tls.c
257
struct user_desc v;
arch/x86/kernel/tls.c
261
fill_user_desc(&v, GDT_ENTRY_TLS_MIN + pos, tls);
arch/x86/kernel/tls.c
262
membuf_write(&to, &v, sizeof(v));
arch/x86/kernel/traps.c
114
u8 v, reg, rm, rex = 0;
arch/x86/kernel/traps.c
122
v = *(u8 *)(addr++);
arch/x86/kernel/traps.c
123
if (v == INSN_ASOP)
arch/x86/kernel/traps.c
126
if (v == INSN_LOCK) {
arch/x86/kernel/traps.c
131
if ((v & 0xf0) == 0x40) {
arch/x86/kernel/traps.c
132
rex = v;
arch/x86/kernel/traps.c
139
switch (v) {
arch/x86/kernel/traps.c
157
v = *(u8 *)(addr++);
arch/x86/kernel/traps.c
158
if (v == SECOND_BYTE_OPCODE_UD2) {
arch/x86/kernel/traps.c
163
if (v != SECOND_BYTE_OPCODE_UD1)
arch/x86/kernel/traps.c
167
v = *(u8 *)(addr++); /* ModRM */
arch/x86/kernel/traps.c
169
if (X86_MODRM_MOD(v) != 3 && X86_MODRM_RM(v) == 4)
arch/x86/kernel/traps.c
172
reg = X86_MODRM_REG(v) + 8*!!X86_REX_R(rex);
arch/x86/kernel/traps.c
173
rm = X86_MODRM_RM(v) + 8*!!X86_REX_B(rex);
arch/x86/kernel/traps.c
176
switch (X86_MODRM_MOD(v)) {
arch/x86/kernel/traps.c
177
case 0: if (X86_MODRM_RM(v) == 5)
arch/x86/kernel/vm86_32.c
206
struct vm86_struct v;
arch/x86/kernel/vm86_32.c
242
if (copy_from_user(&v, user_vm86,
arch/x86/kernel/vm86_32.c
248
if (v.flags & VM86_SCREEN_BITMAP) {
arch/x86/kernel/vm86_32.c
256
vm86regs.pt.bx = v.regs.ebx;
arch/x86/kernel/vm86_32.c
257
vm86regs.pt.cx = v.regs.ecx;
arch/x86/kernel/vm86_32.c
258
vm86regs.pt.dx = v.regs.edx;
arch/x86/kernel/vm86_32.c
259
vm86regs.pt.si = v.regs.esi;
arch/x86/kernel/vm86_32.c
260
vm86regs.pt.di = v.regs.edi;
arch/x86/kernel/vm86_32.c
261
vm86regs.pt.bp = v.regs.ebp;
arch/x86/kernel/vm86_32.c
262
vm86regs.pt.ax = v.regs.eax;
arch/x86/kernel/vm86_32.c
263
vm86regs.pt.ip = v.regs.eip;
arch/x86/kernel/vm86_32.c
264
vm86regs.pt.cs = v.regs.cs;
arch/x86/kernel/vm86_32.c
265
vm86regs.pt.flags = v.regs.eflags;
arch/x86/kernel/vm86_32.c
266
vm86regs.pt.sp = v.regs.esp;
arch/x86/kernel/vm86_32.c
267
vm86regs.pt.ss = v.regs.ss;
arch/x86/kernel/vm86_32.c
268
vm86regs.es = v.regs.es;
arch/x86/kernel/vm86_32.c
269
vm86regs.ds = v.regs.ds;
arch/x86/kernel/vm86_32.c
270
vm86regs.fs = v.regs.fs;
arch/x86/kernel/vm86_32.c
271
vm86regs.gs = v.regs.gs;
arch/x86/kernel/vm86_32.c
273
vm86->flags = v.flags;
arch/x86/kernel/vm86_32.c
274
vm86->cpu_type = v.cpu_type;
arch/x86/kvm/debugfs.c
89
static int kvm_mmu_rmaps_stat_show(struct seq_file *m, void *v)
arch/x86/kvm/emulate.c
4770
u8 vex_3rd, map, pp, l, v;
arch/x86/kvm/emulate.c
4795
v = (vex_3rd >> 3) & 0xf;
arch/x86/kvm/emulate.c
4820
if (v)
arch/x86/kvm/hyperv.c
2025
struct kvm_vcpu *v;
arch/x86/kvm/hyperv.c
2141
kvm_for_each_vcpu(i, v, kvm) {
arch/x86/kvm/hyperv.c
2142
tlb_flush_fifo = kvm_hv_get_tlb_flush_fifo(v, false);
arch/x86/kvm/hyperv.c
2143
hv_tlb_flush_enqueue(v, tlb_flush_fifo,
arch/x86/kvm/hyperv.c
2152
v = kvm_get_vcpu(kvm, i);
arch/x86/kvm/hyperv.c
2153
if (!v)
arch/x86/kvm/hyperv.c
2155
tlb_flush_fifo = kvm_hv_get_tlb_flush_fifo(v, false);
arch/x86/kvm/hyperv.c
2156
hv_tlb_flush_enqueue(v, tlb_flush_fifo,
arch/x86/kvm/hyperv.c
2166
kvm_for_each_vcpu(i, v, kvm) {
arch/x86/kvm/hyperv.c
2167
hv_v = to_hv_vcpu(v);
arch/x86/kvm/hyperv.c
2188
tlb_flush_fifo = kvm_hv_get_tlb_flush_fifo(v, true);
arch/x86/kvm/hyperv.c
2189
hv_tlb_flush_enqueue(v, tlb_flush_fifo,
arch/x86/kvm/irq.c
101
if (!is_guest_mode(v) && kvm_vcpu_apicv_active(v))
arch/x86/kvm/irq.c
104
return kvm_apic_has_interrupt(v) != -1; /* LAPIC */
arch/x86/kvm/irq.c
112
int kvm_cpu_has_interrupt(struct kvm_vcpu *v)
arch/x86/kvm/irq.c
114
if (kvm_cpu_has_extint(v))
arch/x86/kvm/irq.c
117
if (lapic_in_kernel(v) && v->arch.apic->guest_apic_protected)
arch/x86/kvm/irq.c
118
return kvm_x86_call(protected_apic_has_interrupt)(v);
arch/x86/kvm/irq.c
120
return kvm_apic_has_interrupt(v) != -1; /* LAPIC */
arch/x86/kvm/irq.c
128
int kvm_cpu_get_extint(struct kvm_vcpu *v)
arch/x86/kvm/irq.c
130
if (!kvm_cpu_has_extint(v)) {
arch/x86/kvm/irq.c
131
WARN_ON(!lapic_in_kernel(v));
arch/x86/kvm/irq.c
135
if (!lapic_in_kernel(v))
arch/x86/kvm/irq.c
136
return v->arch.interrupt.nr;
arch/x86/kvm/irq.c
139
if (kvm_xen_has_interrupt(v))
arch/x86/kvm/irq.c
140
return v->kvm->arch.xen.upcall_vector;
arch/x86/kvm/irq.c
144
if (pic_in_kernel(v->kvm))
arch/x86/kvm/irq.c
145
return kvm_pic_read_irq(v->kvm); /* PIC */
arch/x86/kvm/irq.c
148
WARN_ON_ONCE(!irqchip_split(v->kvm));
arch/x86/kvm/irq.c
149
return get_userspace_extint(v);
arch/x86/kvm/irq.c
156
int kvm_cpu_get_interrupt(struct kvm_vcpu *v)
arch/x86/kvm/irq.c
158
int vector = kvm_cpu_get_extint(v);
arch/x86/kvm/irq.c
162
vector = kvm_apic_has_interrupt(v); /* APIC */
arch/x86/kvm/irq.c
164
kvm_apic_ack_interrupt(v, vector);
arch/x86/kvm/irq.c
42
static int pending_userspace_extint(struct kvm_vcpu *v)
arch/x86/kvm/irq.c
44
return v->arch.pending_external_vector != -1;
arch/x86/kvm/irq.c
59
int kvm_cpu_has_extint(struct kvm_vcpu *v)
arch/x86/kvm/irq.c
72
if (!lapic_in_kernel(v))
arch/x86/kvm/irq.c
73
return v->arch.interrupt.injected;
arch/x86/kvm/irq.c
75
if (kvm_xen_has_interrupt(v))
arch/x86/kvm/irq.c
78
if (!kvm_apic_accept_pic_intr(v))
arch/x86/kvm/irq.c
82
if (pic_in_kernel(v->kvm))
arch/x86/kvm/irq.c
83
return v->kvm->arch.vpic->output;
arch/x86/kvm/irq.c
86
WARN_ON_ONCE(!irqchip_split(v->kvm));
arch/x86/kvm/irq.c
87
return pending_userspace_extint(v);
arch/x86/kvm/irq.c
96
int kvm_cpu_has_injectable_intr(struct kvm_vcpu *v)
arch/x86/kvm/irq.c
98
if (kvm_cpu_has_extint(v))
arch/x86/kvm/lapic.c
607
u32 v = 0;
arch/x86/kvm/lapic.c
612
v = APIC_VERSION | ((apic->nr_lvt_entries - 1) << 16);
arch/x86/kvm/lapic.c
617
v |= APIC_LVR_DIRECTED_EOI;
arch/x86/kvm/lapic.c
618
kvm_lapic_set_reg(apic, APIC_LVR, v);
arch/x86/kvm/vmx/vmx.c
1227
unsigned long v;
arch/x86/kvm/vmx/vmx.c
1242
v = get_desc_base(&table[selector >> 3]);
arch/x86/kvm/vmx/vmx.c
1243
return v;
arch/x86/kvm/vmx/vmx.c
3037
struct loaded_vmcs *v, *n;
arch/x86/kvm/vmx/vmx.c
3039
list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
arch/x86/kvm/vmx/vmx.c
3041
__loaded_vmcs_clear(v);
arch/x86/kvm/vmx/vmx.c
815
struct loaded_vmcs *v;
arch/x86/kvm/vmx/vmx.c
828
list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
arch/x86/kvm/vmx/vmx.c
830
vmcs_clear(v->vmcs);
arch/x86/kvm/vmx/vmx.c
831
if (v->shadow_vmcs)
arch/x86/kvm/vmx/vmx.c
832
vmcs_clear(v->shadow_vmcs);
arch/x86/kvm/x86.c
2518
u64 v = (u64)khz * (1000000 + ppm);
arch/x86/kvm/x86.c
2519
do_div(v, 1000000);
arch/x86/kvm/x86.c
2520
return v;
arch/x86/kvm/x86.c
2932
long v;
arch/x86/kvm/x86.c
2940
v = (tsc_pg_val - clock->cycle_last) &
arch/x86/kvm/x86.c
2950
v = (*tsc_timestamp - clock->cycle_last) &
arch/x86/kvm/x86.c
2958
*tsc_timestamp = v = 0;
arch/x86/kvm/x86.c
2960
return v * clock->mult;
arch/x86/kvm/x86.c
3312
int kvm_guest_time_update(struct kvm_vcpu *v)
arch/x86/kvm/x86.c
3317
struct kvm_vcpu_arch *vcpu = &v->arch;
arch/x86/kvm/x86.c
3318
struct kvm_arch *ka = &v->kvm->arch;
arch/x86/kvm/x86.c
3344
kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
arch/x86/kvm/x86.c
3352
tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
arch/x86/kvm/x86.c
3365
u64 tsc = compute_guest_tsc(v, kernel_ns);
arch/x86/kvm/x86.c
3367
adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
arch/x86/kvm/x86.c
3378
v->arch.l1_tsc_scaling_ratio);
arch/x86/kvm/x86.c
3392
hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
arch/x86/kvm/x86.c
3410
kvm_setup_guest_pvclock(&hv_clock, v, &vcpu->pv_time, 0);
arch/x86/kvm/x86.c
3415
kvm_hv_setup_tsc_page(v->kvm, &hv_clock);
arch/x86/kvm/x86.c
3430
kvm_setup_guest_pvclock(&hv_clock, v, &vcpu->xen.vcpu_info_cache,
arch/x86/kvm/x86.c
3433
kvm_setup_guest_pvclock(&hv_clock, v, &vcpu->xen.vcpu_time_info_cache, 0);
arch/x86/kvm/x86.c
3523
static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
arch/x86/kvm/x86.c
3527
struct kvm *kvm = v->kvm;
arch/x86/kvm/x86.c
7771
const void *v)
arch/x86/kvm/x86.c
7779
!kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
arch/x86/kvm/x86.c
7780
&& kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
arch/x86/kvm/x86.c
7785
v += n;
arch/x86/kvm/x86.c
7791
static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
arch/x86/kvm/x86.c
7800
addr, n, v))
arch/x86/kvm/x86.c
7801
&& kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
arch/x86/kvm/x86.c
7803
trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
arch/x86/kvm/x86.c
7807
v += n;
arch/x86/kvm/x86.h
453
int kvm_guest_time_update(struct kvm_vcpu *v);
arch/x86/kvm/xen.c
321
static void kvm_xen_update_runstate_guest(struct kvm_vcpu *v, bool atomic)
arch/x86/kvm/xen.c
323
struct kvm_vcpu_xen *vx = &v->arch.xen;
arch/x86/kvm/xen.c
393
if (IS_ENABLED(CONFIG_64BIT) && v->kvm->arch.xen.long_mode) {
arch/x86/kvm/xen.c
457
if (v->kvm->arch.xen.runstate_update_flag)
arch/x86/kvm/xen.c
521
if (v->kvm->arch.xen.runstate_update_flag) {
arch/x86/kvm/xen.c
587
void kvm_xen_update_runstate(struct kvm_vcpu *v, int state)
arch/x86/kvm/xen.c
589
struct kvm_vcpu_xen *vx = &v->arch.xen;
arch/x86/kvm/xen.c
590
u64 now = get_kvmclock_ns(v->kvm);
arch/x86/kvm/xen.c
615
kvm_xen_update_runstate_guest(v, state == RUNSTATE_runnable);
arch/x86/kvm/xen.c
618
void kvm_xen_inject_vcpu_vector(struct kvm_vcpu *v)
arch/x86/kvm/xen.c
622
irq.dest_id = v->vcpu_id;
arch/x86/kvm/xen.c
623
irq.vector = v->arch.xen.upcall_vector;
arch/x86/kvm/xen.c
629
kvm_irq_delivery_to_apic(v->kvm, NULL, &irq);
arch/x86/kvm/xen.c
639
void kvm_xen_inject_pending_events(struct kvm_vcpu *v)
arch/x86/kvm/xen.c
641
unsigned long evtchn_pending_sel = READ_ONCE(v->arch.xen.evtchn_pending_sel);
arch/x86/kvm/xen.c
642
struct gfn_to_pfn_cache *gpc = &v->arch.xen.vcpu_info_cache;
arch/x86/kvm/xen.c
664
if (IS_ENABLED(CONFIG_64BIT) && v->kvm->arch.xen.long_mode) {
arch/x86/kvm/xen.c
672
"+m" (v->arch.xen.evtchn_pending_sel)
arch/x86/kvm/xen.c
684
"+m" (v->arch.xen.evtchn_pending_sel)
arch/x86/kvm/xen.c
693
if (v->arch.xen.upcall_vector)
arch/x86/kvm/xen.c
694
kvm_xen_inject_vcpu_vector(v);
arch/x86/kvm/xen.c
697
int __kvm_xen_has_interrupt(struct kvm_vcpu *v)
arch/x86/kvm/xen.c
699
struct gfn_to_pfn_cache *gpc = &v->arch.xen.vcpu_info_cache;
arch/x86/lib/insn.c
25
__typeof__(t) v; \
arch/x86/lib/insn.c
27
case 4: v = le32_to_cpu(r); break; \
arch/x86/lib/insn.c
28
case 2: v = le16_to_cpu(r); break; \
arch/x86/lib/insn.c
29
case 1: v = r; break; \
arch/x86/lib/insn.c
33
v; \
arch/x86/lib/kaslr.c
24
#define debug_putstr(v) early_printk("%s", v)
arch/x86/math-emu/fpu_emu.h
207
asmlinkage unsigned FPU_shrxs(void *v, unsigned x);
arch/x86/mm/debug_pagetables.c
16
static int ptdump_curknl_show(struct seq_file *m, void *v)
arch/x86/mm/debug_pagetables.c
26
static int ptdump_curusr_show(struct seq_file *m, void *v)
arch/x86/mm/debug_pagetables.c
37
static int ptdump_efi_show(struct seq_file *m, void *v)
arch/x86/mm/debug_pagetables.c
8
static int ptdump_show(struct seq_file *m, void *v)
arch/x86/mm/kmmio.c
136
pmdval_t v = pmd_val(*pmd);
arch/x86/mm/kmmio.c
138
*old = v;
arch/x86/mm/kmmio.c
149
pteval_t v = pte_val(*pte);
arch/x86/mm/kmmio.c
151
*old = v;
arch/x86/mm/pat/memtype.c
1003
static void memtype_seq_stop(struct seq_file *seq, void *v)
arch/x86/mm/pat/memtype.c
1005
kfree(v);
arch/x86/mm/pat/memtype.c
1008
static int memtype_seq_show(struct seq_file *seq, void *v)
arch/x86/mm/pat/memtype.c
1010
struct memtype *entry_print = (struct memtype *)v;
arch/x86/mm/pat/memtype.c
996
static void *memtype_seq_next(struct seq_file *seq, void *v, loff_t *pos)
arch/x86/mm/pat/memtype.c
998
kfree(v);
arch/x86/pci/early.c
13
u32 v;
arch/x86/pci/early.c
15
v = inl(0xcfc);
arch/x86/pci/early.c
16
return v;
arch/x86/pci/early.c
21
u8 v;
arch/x86/pci/early.c
23
v = inb(0xcfc + (offset&3));
arch/x86/pci/early.c
24
return v;
arch/x86/pci/early.c
29
u16 v;
arch/x86/pci/early.c
31
v = inw(0xcfc + (offset&2));
arch/x86/pci/early.c
32
return v;
arch/x86/pci/fixup.c
112
u8 v;
arch/x86/pci/fixup.c
131
pci_read_config_byte(d, where, &v);
arch/x86/pci/fixup.c
132
if (v & ~mask) {
arch/x86/pci/fixup.c
134
d->device, d->revision, where, v, mask, v & mask);
arch/x86/pci/fixup.c
135
v &= mask;
arch/x86/pci/fixup.c
136
pci_write_config_byte(d, where, v);
arch/x86/pci/xen.c
171
int *v;
arch/x86/pci/xen.c
176
v = kzalloc_objs(int, max(1, nvec));
arch/x86/pci/xen.c
177
if (!v)
arch/x86/pci/xen.c
181
ret = xen_pci_frontend_enable_msix(dev, v, nvec);
arch/x86/pci/xen.c
183
ret = xen_pci_frontend_enable_msi(dev, v);
arch/x86/pci/xen.c
188
irq = xen_bind_pirq_msi_to_irq(dev, msidesc, v[i],
arch/x86/pci/xen.c
200
kfree(v);
arch/x86/pci/xen.c
209
kfree(v);
arch/x86/tools/relocs.c
939
static int write32(uint32_t v, FILE *f)
arch/x86/tools/relocs.c
943
put_unaligned_le32(v, buf);
arch/x86/tools/relocs.c
948
static int write32_as_text(uint32_t v, FILE *f)
arch/x86/tools/relocs.c
950
return fprintf(f, "\t.long 0x%08"PRIx32"\n", v) > 0 ? 0 : -1;
arch/x86/virt/vmx/tdx/tdx.c
1368
void *v)
arch/x86/virt/vmx/tdx/tdx.c
1370
struct memory_notify *mn = v;
arch/x86/xen/enlighten_pv.c
454
static void set_aliased_prot(void *v, pgprot_t prot)
arch/x86/xen/enlighten_pv.c
463
ptep = lookup_address((unsigned long)v, &level);
arch/x86/xen/enlighten_pv.c
491
copy_from_kernel_nofault(&dummy, v, 1);
arch/x86/xen/enlighten_pv.c
493
if (HYPERVISOR_update_va_mapping((unsigned long)v, pte, 0))
arch/x86/xen/enlighten_pv.c
498
if (va != v && HYPERVISOR_update_va_mapping((unsigned long)va, pte, 0))
arch/x86/xen/mmu_pv.c
1369
static void set_current_cr3(void *v)
arch/x86/xen/mmu_pv.c
1371
this_cpu_write(xen_current_cr3, (unsigned long)v);
arch/x86/xen/mmu_pv.c
1726
static void __init convert_pfn_mfn(void *v)
arch/x86/xen/mmu_pv.c
1728
pte_t *pte = v;
arch/x86/xen/mmu_pv.c
725
static void xen_pte_unlock(void *v)
arch/x86/xen/mmu_pv.c
727
spinlock_t *ptl = v;
arch/x86/xen/p2m.c
889
static int p2m_dump_show(struct seq_file *m, void *v)
arch/x86/xen/smp_pv.c
381
static void stop_self(void *v)
arch/x86/xen/time.c
405
t.addr.v = NULL;
arch/x86/xen/time.c
423
t.addr.v = &xen_clock->pvti;
arch/x86/xen/time.c
456
t.addr.v = &ti->pvti;
arch/x86/xen/time.c
471
t.addr.v = NULL;
arch/xtensa/include/asm/atomic.h
110
: [i] "a" (i), [addr] "a" (v) \
arch/xtensa/include/asm/atomic.h
119
static inline void arch_atomic_##op(int i, atomic_t * v) \
arch/xtensa/include/asm/atomic.h
131
[mem] "+m" (*v) \
arch/xtensa/include/asm/atomic.h
138
static inline int arch_atomic_##op##_return(int i, atomic_t * v) \
arch/xtensa/include/asm/atomic.h
151
[mem] "+m" (*v) \
arch/xtensa/include/asm/atomic.h
160
static inline int arch_atomic_fetch_##op(int i, atomic_t * v) \
arch/xtensa/include/asm/atomic.h
172
[mem] "+m" (*v) \
arch/xtensa/include/asm/atomic.h
183
static inline void arch_atomic_##op(int i, atomic_t * v) \
arch/xtensa/include/asm/atomic.h
194
: [result] "=&a" (vval), [mem] "+m" (*v) \
arch/xtensa/include/asm/atomic.h
201
static inline int arch_atomic_##op##_return(int i, atomic_t * v) \
arch/xtensa/include/asm/atomic.h
212
: [result] "=&a" (vval), [mem] "+m" (*v) \
arch/xtensa/include/asm/atomic.h
221
static inline int arch_atomic_fetch_##op(int i, atomic_t * v) \
arch/xtensa/include/asm/atomic.h
233
[mem] "+m" (*v) \
arch/xtensa/include/asm/atomic.h
46
#define arch_atomic_read(v) READ_ONCE((v)->counter)
arch/xtensa/include/asm/atomic.h
55
#define arch_atomic_set(v,i) WRITE_ONCE((v)->counter, (i))
arch/xtensa/include/asm/atomic.h
59
static inline void arch_atomic_##op(int i, atomic_t *v) \
arch/xtensa/include/asm/atomic.h
71
: [i] "a" (i), [addr] "a" (v) \
arch/xtensa/include/asm/atomic.h
77
static inline int arch_atomic_##op##_return(int i, atomic_t *v) \
arch/xtensa/include/asm/atomic.h
90
: [i] "a" (i), [addr] "a" (v) \
arch/xtensa/include/asm/atomic.h
98
static inline int arch_atomic_fetch_##op(int i, atomic_t *v) \
arch/xtensa/include/asm/processor.h
238
unsigned int v; \
arch/xtensa/include/asm/processor.h
239
__asm__ __volatile__ ("rsr %0, "__stringify(sr) : "=a"(v)); \
arch/xtensa/include/asm/processor.h
240
v; \
arch/xtensa/kernel/hw_breakpoint.c
105
xtensa_set_sr(v, SREG_IBREAKA + 0);
arch/xtensa/kernel/hw_breakpoint.c
110
xtensa_set_sr(v, SREG_IBREAKA + 1);
arch/xtensa/kernel/hw_breakpoint.c
116
xtensa_set_sr(v, SREG_DBREAKA + 0);
arch/xtensa/kernel/hw_breakpoint.c
119
xtensa_set_sr(v, SREG_DBREAKC + 0);
arch/xtensa/kernel/hw_breakpoint.c
124
xtensa_set_sr(v, SREG_DBREAKA + 1);
arch/xtensa/kernel/hw_breakpoint.c
128
xtensa_set_sr(v, SREG_DBREAKC + 1);
arch/xtensa/kernel/hw_breakpoint.c
92
static void xtensa_wsr(unsigned long v, u8 sr)
arch/xtensa/kernel/perf_event.c
140
static inline void xtensa_pmu_write_counter(int idx, uint32_t v)
arch/xtensa/kernel/perf_event.c
142
set_er(v, XTENSA_PMU_PM(idx));
arch/xtensa/kernel/perf_event.c
375
uint32_t v = get_er(XTENSA_PMU_PMSTAT(i));
arch/xtensa/kernel/perf_event.c
380
if (!(v & XTENSA_PMU_PMSTAT_OVFL))
arch/xtensa/kernel/perf_event.c
383
set_er(v, XTENSA_PMU_PMSTAT(i));
arch/xtensa/kernel/s32c1i_selftest.c
25
static inline int probed_compare_swap(int *v, int cmp, int set)
arch/xtensa/kernel/s32c1i_selftest.c
35
: "a" (cmp), "a" (v), "a" (&rcw_probe_pc), "0" (set)
arch/xtensa/kernel/setup.c
703
c_next(struct seq_file *f, void *v, loff_t *pos)
arch/xtensa/kernel/setup.c
710
c_stop(struct seq_file *f, void *v)
arch/xtensa/kernel/traps.c
231
#define IS_POW2(v) (((v) & ((v) - 1)) == 0)
arch/xtensa/kernel/xtensa_ksyms.c
20
unsigned int __sync_fetch_and_and_4(volatile void *p, unsigned int v)
arch/xtensa/kernel/xtensa_ksyms.c
26
unsigned int __sync_fetch_and_or_4(volatile void *p, unsigned int v)
arch/xtensa/platforms/iss/console.c
90
static int rs_proc_show(struct seq_file *m, void *v)
block/bfq-cgroup.c
1050
u64 v;
block/bfq-cgroup.c
1058
if (sscanf(ctx.body, "%llu", &v) == 1) {
block/bfq-cgroup.c
1061
if (!v)
block/bfq-cgroup.c
1064
v = 0;
block/bfq-cgroup.c
1073
if (!v || (v >= BFQ_MIN_WEIGHT && v <= BFQ_MAX_WEIGHT)) {
block/bfq-cgroup.c
1074
bfq_group_set_weight(bfqg, bfqg->entity.weight, v);
block/bfq-cgroup.c
1088
u64 v;
block/bfq-cgroup.c
1093
v = simple_strtoull(buf, &endp, 0);
block/bfq-cgroup.c
1094
if (*endp == '\0' || sscanf(buf, "default %llu", &v) == 1) {
block/bfq-cgroup.c
1095
ret = bfq_io_set_weight_legacy(of_css(of), NULL, v);
block/bfq-cgroup.c
1102
static int bfqg_print_rwstat(struct seq_file *sf, void *v)
block/bfq-cgroup.c
1118
static int bfqg_print_rwstat_recursive(struct seq_file *sf, void *v)
block/bfq-cgroup.c
1127
static int bfqg_print_stat(struct seq_file *sf, void *v)
block/bfq-cgroup.c
1159
static int bfqg_print_stat_recursive(struct seq_file *sf, void *v)
block/bfq-cgroup.c
1176
static int bfqg_print_stat_sectors(struct seq_file *sf, void *v)
block/bfq-cgroup.c
1195
static int bfqg_print_stat_sectors_recursive(struct seq_file *sf, void *v)
block/bfq-cgroup.c
1208
u64 v = 0;
block/bfq-cgroup.c
1211
v = bfq_stat_read(&bfqg->stats.avg_queue_size_sum);
block/bfq-cgroup.c
1212
v = div64_u64(v, samples);
block/bfq-cgroup.c
1214
__blkg_prfill_u64(sf, pd, v);
block/bfq-cgroup.c
1219
static int bfqg_print_avg_queue_size(struct seq_file *sf, void *v)
block/bfq-cgroup.c
948
static int bfq_io_show_weight_legacy(struct seq_file *sf, void *v)
block/bfq-cgroup.c
972
static int bfq_io_show_weight(struct seq_file *sf, void *v)
block/blk-cgroup-rwstat.c
47
u64 v;
block/blk-cgroup-rwstat.c
57
v = rwstat->cnt[BLKG_RWSTAT_READ] +
block/blk-cgroup-rwstat.c
60
seq_printf(sf, "%s Total %llu\n", dname, v);
block/blk-cgroup-rwstat.c
61
return v;
block/blk-cgroup.c
1230
static int blkcg_print_stat(struct seq_file *sf, void *v)
block/blk-cgroup.c
736
u64 __blkg_prfill_u64(struct seq_file *sf, struct blkg_policy_data *pd, u64 v)
block/blk-cgroup.c
743
seq_printf(sf, "%s %llu\n", dname, (unsigned long long)v);
block/blk-cgroup.c
744
return v;
block/blk-cgroup.h
211
u64 __blkg_prfill_u64(struct seq_file *sf, struct blkg_policy_data *pd, u64 v);
block/blk-iocost.c
3082
static int ioc_weight_show(struct seq_file *sf, void *v)
block/blk-iocost.c
3101
u32 v;
block/blk-iocost.c
3107
if (!sscanf(buf, "default %u", &v) && !sscanf(buf, "%u", &v))
block/blk-iocost.c
3110
if (v < CGROUP_WEIGHT_MIN || v > CGROUP_WEIGHT_MAX)
block/blk-iocost.c
3114
iocc->dfl_weight = v * WEIGHT_ONE;
block/blk-iocost.c
3139
v = 0;
block/blk-iocost.c
3141
if (!sscanf(ctx.body, "%u", &v))
block/blk-iocost.c
3143
if (v < CGROUP_WEIGHT_MIN || v > CGROUP_WEIGHT_MAX)
block/blk-iocost.c
3148
iocg->cfg_weight = v * WEIGHT_ONE;
block/blk-iocost.c
3189
static int ioc_qos_show(struct seq_file *sf, void *v)
block/blk-iocost.c
3260
s64 v;
block/blk-iocost.c
3267
if (match_u64(&args[0], &v))
block/blk-iocost.c
3269
enable = v;
block/blk-iocost.c
3289
if (cgroup_parse_float(buf, 2, &v))
block/blk-iocost.c
3291
if (v < 0 || v > 10000)
block/blk-iocost.c
3293
qos[tok] = v * 100;
block/blk-iocost.c
3297
if (match_u64(&args[0], &v))
block/blk-iocost.c
3299
qos[tok] = v;
block/blk-iocost.c
3306
if (cgroup_parse_float(buf, 2, &v))
block/blk-iocost.c
3308
if (v < 0)
block/blk-iocost.c
3310
qos[tok] = clamp_t(s64, v * 100,
block/blk-iocost.c
3381
static int ioc_cost_model_show(struct seq_file *sf, void *v)
block/blk-iocost.c
3450
u64 v;
block/blk-iocost.c
3475
if (match_u64(&args[0], &v))
block/blk-iocost.c
3477
u[tok] = v;
block/blk-iocost.c
871
u64 v;
block/blk-iocost.c
885
v = DIV64_U64_ROUND_UP(VTIME_PER_SEC, seqiops);
block/blk-iocost.c
886
if (v > *page)
block/blk-iocost.c
887
*seqio = v - *page;
block/blk-iocost.c
891
v = DIV64_U64_ROUND_UP(VTIME_PER_SEC, randiops);
block/blk-iocost.c
892
if (v > *page)
block/blk-iocost.c
893
*randio = v - *page;
block/blk-iolatency.c
871
u64 v;
block/blk-iolatency.c
875
else if (sscanf(val, "%llu", &v) == 1)
block/blk-iolatency.c
876
lat_val = v * NSEC_PER_USEC;
block/blk-iolatency.c
910
static int iolatency_print_limit(struct seq_file *sf, void *v)
block/blk-ioprio.c
74
static int ioprio_show_prio_policy(struct seq_file *sf, void *v)
block/blk-mq-debugfs.c
293
int blk_mq_debugfs_rq_show(struct seq_file *m, void *v)
block/blk-mq-debugfs.c
295
return __blk_mq_debugfs_rq_show(m, list_entry_rq(v));
block/blk-mq-debugfs.c
308
static void *hctx_dispatch_next(struct seq_file *m, void *v, loff_t *pos)
block/blk-mq-debugfs.c
31
static void *queue_requeue_list_next(struct seq_file *m, void *v, loff_t *pos)
block/blk-mq-debugfs.c
312
return seq_list_next(v, &hctx->dispatch, pos);
block/blk-mq-debugfs.c
315
static void hctx_dispatch_stop(struct seq_file *m, void *v)
block/blk-mq-debugfs.c
35
return seq_list_next(v, &q->requeue_list, pos);
block/blk-mq-debugfs.c
38
static void queue_requeue_list_stop(struct seq_file *m, void *v)
block/blk-mq-debugfs.c
496
static void *ctx_##name##_rq_list_next(struct seq_file *m, void *v, \
block/blk-mq-debugfs.c
501
return seq_list_next(v, &ctx->rq_lists[type], pos); \
block/blk-mq-debugfs.c
504
static void ctx_##name##_rq_list_stop(struct seq_file *m, void *v) \
block/blk-mq-debugfs.c
523
static int blk_mq_debugfs_show(struct seq_file *m, void *v)
block/blk-mq-debugfs.h
21
int blk_mq_debugfs_rq_show(struct seq_file *m, void *v);
block/blk-rq-qos.c
11
unsigned int cur = atomic_read(v);
block/blk-rq-qos.c
16
} while (!atomic_try_cmpxchg(v, &cur, cur + 1));
block/blk-rq-qos.c
9
static bool atomic_inc_below(atomic_t *v, unsigned int below)
block/blk-sysfs.c
43
unsigned long v;
block/blk-sysfs.c
45
err = kstrtoul(page, 10, &v);
block/blk-sysfs.c
46
if (err || v > UINT_MAX)
block/blk-sysfs.c
49
*var = v;
block/blk-sysfs.c
651
s64 v;
block/blk-sysfs.c
653
err = kstrtos64(page, 10, &v);
block/blk-sysfs.c
657
*var = v;
block/blk-throttle.c
1229
u64 v = *(u64 *)((void *)tg + off);
block/blk-throttle.c
1231
if (v == U64_MAX)
block/blk-throttle.c
1233
return __blkg_prfill_u64(sf, pd, v);
block/blk-throttle.c
1240
unsigned int v = *(unsigned int *)((void *)tg + off);
block/blk-throttle.c
1242
if (v == UINT_MAX)
block/blk-throttle.c
1244
return __blkg_prfill_u64(sf, pd, v);
block/blk-throttle.c
1247
static int tg_print_conf_u64(struct seq_file *sf, void *v)
block/blk-throttle.c
1254
static int tg_print_conf_uint(struct seq_file *sf, void *v)
block/blk-throttle.c
1350
u64 v;
block/blk-throttle.c
1369
if (sscanf(ctx.body, "%llu", &v) != 1)
block/blk-throttle.c
1371
if (!v)
block/blk-throttle.c
1372
v = U64_MAX;
block/blk-throttle.c
1378
*(u64 *)((void *)tg + of_cft(of)->private) = v;
block/blk-throttle.c
1380
*(unsigned int *)((void *)tg + of_cft(of)->private) = v;
block/blk-throttle.c
1401
static int tg_print_rwstat(struct seq_file *sf, void *v)
block/blk-throttle.c
1419
static int tg_print_rwstat_recursive(struct seq_file *sf, void *v)
block/blk-throttle.c
1520
static int tg_print_limit(struct seq_file *sf, void *v)
block/blk-throttle.c
1533
u64 v[4];
block/blk-throttle.c
1555
v[0] = tg->bps[READ];
block/blk-throttle.c
1556
v[1] = tg->bps[WRITE];
block/blk-throttle.c
1557
v[2] = tg->iops[READ];
block/blk-throttle.c
1558
v[3] = tg->iops[WRITE];
block/blk-throttle.c
1584
v[0] = val;
block/blk-throttle.c
1586
v[1] = val;
block/blk-throttle.c
1588
v[2] = min_t(u64, val, UINT_MAX);
block/blk-throttle.c
1590
v[3] = min_t(u64, val, UINT_MAX);
block/blk-throttle.c
1595
tg->bps[READ] = v[0];
block/blk-throttle.c
1596
tg->bps[WRITE] = v[1];
block/blk-throttle.c
1597
tg->iops[READ] = v[2];
block/blk-throttle.c
1598
tg->iops[WRITE] = v[3];
block/genhd.c
1353
static int diskstats_show(struct seq_file *seqf, void *v)
block/genhd.c
1355
struct gendisk *gp = v;
block/genhd.c
932
static void *disk_seqf_next(struct seq_file *seqf, void *v, loff_t *pos)
block/genhd.c
944
static void disk_seqf_stop(struct seq_file *seqf, void *v)
block/genhd.c
966
static int show_partition(struct seq_file *seqf, void *v)
block/genhd.c
968
struct gendisk *sgp = v;
block/kyber-iosched.c
906
static void *kyber_##name##_rqs_next(struct seq_file *m, void *v, \
block/kyber-iosched.c
912
return seq_list_next(v, &khd->rqs[domain], pos); \
block/kyber-iosched.c
915
static void kyber_##name##_rqs_stop(struct seq_file *m, void *v) \
block/mq-deadline.c
811
static void *deadline_##name##_fifo_next(struct seq_file *m, void *v, \
block/mq-deadline.c
818
return seq_list_next(v, &per_prio->fifo_list[data_dir], pos); \
block/mq-deadline.c
821
static void deadline_##name##_fifo_stop(struct seq_file *m, void *v) \
block/mq-deadline.c
933
static void *deadline_dispatch_next(struct seq_file *m, void *v, loff_t *pos)
block/mq-deadline.c
938
return seq_list_next(v, &dd->dispatch, pos);
block/mq-deadline.c
941
static void deadline_dispatch_stop(struct seq_file *m, void *v)
block/partitions/check.h
27
struct folio *v;
block/partitions/check.h
33
folio_put(p.v);
block/partitions/core.c
727
p->v = folio;
block/partitions/core.c
730
p->v = NULL;
block/partitions/ldm.c
1191
struct vblk *v = list_entry (item, struct vblk, list);
block/partitions/ldm.c
1192
if ((v->vblk.part.disk_id == vb->vblk.part.disk_id) &&
block/partitions/ldm.c
1193
(v->vblk.part.start > vb->vblk.part.start)) {
block/partitions/ldm.c
1194
list_add_tail (&vb->list, &v->list);
block/partitions/ldm.c
1344
int size, perbuf, skip, finish, s, v, recs;
block/partitions/ldm.c
1364
for (v = 0; v < perbuf; v++, data+=size) { /* For each vblk */
block/partitions/ldm.c
543
struct vblk *v = list_entry (item, struct vblk, list);
block/partitions/ldm.c
544
if (uuid_equal(&v->vblk.disk.disk_id, &ldb->ph.disk_id))
block/partitions/ldm.c
545
return v;
block/partitions/msdos.c
255
struct solaris_x86_vtoc *v;
block/partitions/msdos.c
259
v = read_part_sector(state, offset + 1, §);
block/partitions/msdos.c
260
if (!v)
block/partitions/msdos.c
262
if (le32_to_cpu(v->v_sanity) != SOLARIS_X86_VTOC_SANE) {
block/partitions/msdos.c
272
if (le32_to_cpu(v->v_version) != 1) {
block/partitions/msdos.c
276
le32_to_cpu(v->v_version));
block/partitions/msdos.c
282
max_nparts = le16_to_cpu(v->v_nparts) > 8 ? SOLARIS_X86_NUMSLICE : 8;
block/partitions/msdos.c
284
struct solaris_x86_slice *s = &v->v_slice[i];
crypto/aegis128-neon-inner.c
110
m ^= aegis_aes_round(st.v[4]);
crypto/aegis128-neon-inner.c
111
st.v[4] ^= aegis_aes_round(st.v[3]);
crypto/aegis128-neon-inner.c
112
st.v[3] ^= aegis_aes_round(st.v[2]);
crypto/aegis128-neon-inner.c
113
st.v[2] ^= aegis_aes_round(st.v[1]);
crypto/aegis128-neon-inner.c
114
st.v[1] ^= aegis_aes_round(st.v[0]);
crypto/aegis128-neon-inner.c
115
st.v[0] ^= m;
crypto/aegis128-neon-inner.c
193
static uint8x16_t vqtbx1q_u8(uint8x16_t v, uint8x16_t a, uint8x16_t b)
crypto/aegis128-neon-inner.c
200
return vcombine_u8(vtbx2_u8(vget_low_u8(v), __a.pair, vget_low_u8(b)),
crypto/aegis128-neon-inner.c
201
vtbx2_u8(vget_high_u8(v), __a.pair, vget_high_u8(b)));
crypto/aegis128-neon-inner.c
204
static int8_t vminvq_s8(int8x16_t v)
crypto/aegis128-neon-inner.c
206
int8x8_t s = vpmin_s8(vget_low_s8(v), vget_high_s8(v));
crypto/aegis128-neon-inner.c
232
uint8x16_t s = st.v[1] ^ (st.v[2] & st.v[3]) ^ st.v[4];
crypto/aegis128-neon-inner.c
245
uint8x16_t s = st.v[1] ^ (st.v[2] & st.v[3]) ^ st.v[4];
crypto/aegis128-neon-inner.c
26
uint8x16_t v[5];
crypto/aegis128-neon-inner.c
281
msg = vld1q_u8(src) ^ st.v[1] ^ (st.v[2] & st.v[3]) ^ st.v[4];
crypto/aegis128-neon-inner.c
291
uint8x16_t s = st.v[1] ^ (st.v[2] & st.v[3]) ^ st.v[4];
crypto/aegis128-neon-inner.c
323
uint8x16_t v;
crypto/aegis128-neon-inner.c
328
v = st.v[3] ^ (uint8x16_t)vcombine_u64(vmov_n_u64(8ULL * assoclen),
crypto/aegis128-neon-inner.c
332
st = aegis128_update_neon(st, v);
crypto/aegis128-neon-inner.c
334
v = st.v[0] ^ st.v[1] ^ st.v[2] ^ st.v[3] ^ st.v[4];
crypto/aegis128-neon-inner.c
337
v = vqtbl1q_u8(~vceqq_u8(v, vld1q_u8(tag_xor)),
crypto/aegis128-neon-inner.c
340
return vminvq_s8((int8x16_t)v);
crypto/aegis128-neon-inner.c
343
vst1q_u8(tag_xor, v);
crypto/aegis128-neon-inner.c
44
vst1q_u8(state, st.v[0]);
crypto/aegis128-neon-inner.c
45
vst1q_u8(state + 16, st.v[1]);
crypto/aegis128-neon-inner.c
46
vst1q_u8(state + 32, st.v[2]);
crypto/aegis128-neon-inner.c
47
vst1q_u8(state + 48, st.v[3]);
crypto/aegis128-neon-inner.c
48
vst1q_u8(state + 64, st.v[4]);
crypto/aegis128-neon-inner.c
66
uint8x16_t v;
crypto/aegis128-neon-inner.c
73
v = vqtbl4q_u8(vld1q_u8_x4(crypto_aes_sbox), w);
crypto/aegis128-neon-inner.c
74
v = vqtbx4q_u8(v, vld1q_u8_x4(crypto_aes_sbox + 0x40), w - 0x40);
crypto/aegis128-neon-inner.c
75
v = vqtbx4q_u8(v, vld1q_u8_x4(crypto_aes_sbox + 0x80), w - 0x80);
crypto/aegis128-neon-inner.c
76
v = vqtbx4q_u8(v, vld1q_u8_x4(crypto_aes_sbox + 0xc0), w - 0xc0);
crypto/aegis128-neon-inner.c
78
asm("tbl %0.16b, {v16.16b-v19.16b}, %1.16b" : "=w"(v) : "w"(w));
crypto/aegis128-neon-inner.c
80
asm("tbx %0.16b, {v20.16b-v23.16b}, %1.16b" : "+w"(v) : "w"(w));
crypto/aegis128-neon-inner.c
82
asm("tbx %0.16b, {v24.16b-v27.16b}, %1.16b" : "+w"(v) : "w"(w));
crypto/aegis128-neon-inner.c
84
asm("tbx %0.16b, {v28.16b-v31.16b}, %1.16b" : "+w"(v) : "w"(w));
crypto/aegis128-neon-inner.c
88
w = (v << 1) ^ (uint8x16_t)(((int8x16_t)v >> 7) & 0x1b);
crypto/aegis128-neon-inner.c
89
w ^= (uint8x16_t)vrev32q_u16((uint16x8_t)v);
crypto/aegis128-neon-inner.c
90
w ^= vqtbl1q_u8(v ^ w, vld1q_u8(ror32by8));
crypto/anubis.c
559
u32 v = ctx->E[R - r][i];
crypto/anubis.c
561
T0[T4[(v >> 24) ] & 0xff] ^
crypto/anubis.c
562
T1[T4[(v >> 16) & 0xff] & 0xff] ^
crypto/anubis.c
563
T2[T4[(v >> 8) & 0xff] & 0xff] ^
crypto/anubis.c
564
T3[T4[(v ) & 0xff] & 0xff];
crypto/api.c
324
int crypto_probing_notify(unsigned long val, void *v)
crypto/api.c
328
ok = blocking_notifier_call_chain(&crypto_chain, val, v);
crypto/api.c
331
ok = blocking_notifier_call_chain(&crypto_chain, val, v);
crypto/asymmetric_keys/x509_cert_parser.c
576
const unsigned char *v = value;
crypto/asymmetric_keys/x509_cert_parser.c
584
if (v[0] != ASN1_OTS || v[1] != vlen - 2)
crypto/asymmetric_keys/x509_cert_parser.c
586
v += 2;
crypto/asymmetric_keys/x509_cert_parser.c
590
ctx->cert->raw_skid = v;
crypto/asymmetric_keys/x509_cert_parser.c
591
kid = asymmetric_key_generate_id(v, vlen, "", 0);
crypto/asymmetric_keys/x509_cert_parser.c
612
if (v[0] != ASN1_BTS)
crypto/asymmetric_keys/x509_cert_parser.c
616
if (v[2] >= 8)
crypto/asymmetric_keys/x509_cert_parser.c
618
if (v[3] & 0x80)
crypto/asymmetric_keys/x509_cert_parser.c
620
if (v[1] == 0x02 && v[2] <= 2 && (v[3] & 0x04))
crypto/asymmetric_keys/x509_cert_parser.c
622
else if (vlen > 4 && v[1] == 0x03 && (v[3] & 0x04))
crypto/asymmetric_keys/x509_cert_parser.c
629
ctx->raw_akid = v;
crypto/asymmetric_keys/x509_cert_parser.c
648
if (v[0] != (ASN1_CONS_BIT | ASN1_SEQ))
crypto/asymmetric_keys/x509_cert_parser.c
652
if (v[1] != vlen - 2)
crypto/asymmetric_keys/x509_cert_parser.c
655
if (v[1] == 0)
crypto/asymmetric_keys/x509_cert_parser.c
657
if (vlen >= 5 && v[2] == ASN1_BOOL && v[3] == 1 && v[4] == 0xFF)
crypto/ecc.c
1034
u64 u[ECC_MAX_DIGITS], v[ECC_MAX_DIGITS];
crypto/ecc.c
1047
vli_clear(v, ndigits);
crypto/ecc.c
1064
if (!EVEN(v))
crypto/ecc.c
1065
carry = vli_add(v, v, mod, ndigits);
crypto/ecc.c
1067
vli_rshift1(v, ndigits);
crypto/ecc.c
1069
v[ndigits - 1] |= 0x8000000000000000ull;
crypto/ecc.c
1074
if (vli_cmp(u, v, ndigits) < 0)
crypto/ecc.c
1077
vli_sub(u, u, v, ndigits);
crypto/ecc.c
1088
if (vli_cmp(v, u, ndigits) < 0)
crypto/ecc.c
1089
vli_add(v, v, mod, ndigits);
crypto/ecc.c
1091
vli_sub(v, v, u, ndigits);
crypto/ecc.c
1092
if (!EVEN(v))
crypto/ecc.c
1093
carry = vli_add(v, v, mod, ndigits);
crypto/ecc.c
1095
vli_rshift1(v, ndigits);
crypto/ecc.c
1097
v[ndigits - 1] |= 0x8000000000000000ull;
crypto/ecc.c
633
u64 *v[2] = { tmp, product };
crypto/ecc.c
655
u64 diff = v[i][j] - mod_m[j] - borrow;
crypto/ecc.c
657
if (diff != v[i][j])
crypto/ecc.c
658
borrow = (diff > v[i][j]);
crypto/ecc.c
659
v[1 - i][j] = diff;
crypto/ecc.c
666
vli_set(result, v[i], ndigits);
crypto/ecrdsa.c
122
vli_mod_inv(v, e, ctx->curve->n, ndigits);
crypto/ecrdsa.c
125
vli_mod_mult_slow(z1, s, v, ctx->curve->n, ndigits);
crypto/ecrdsa.c
127
vli_mod_mult_slow(z2, _r, v, ctx->curve->n, ndigits);
crypto/ecrdsa.c
80
u64 *v = e; /* e^{-1} \mod q */
crypto/internal.h
152
int crypto_probing_notify(unsigned long val, void *v);
crypto/internal.h
198
static inline void crypto_notify(unsigned long val, void *v)
crypto/internal.h
200
blocking_notifier_call_chain(&crypto_chain, val, v);
drivers/accel/habanalabs/common/habanalabs.h
2629
#define WREG32(reg, v) hdev->asic_funcs->wreg(hdev, (reg), (v))
drivers/accel/ivpu/ivpu_debugfs.c
106
static int reset_counter_show(struct seq_file *s, void *v)
drivers/accel/ivpu/ivpu_debugfs.c
114
static int reset_pending_show(struct seq_file *s, void *v)
drivers/accel/ivpu/ivpu_debugfs.c
122
static int firewall_irq_counter_show(struct seq_file *s, void *v)
drivers/accel/ivpu/ivpu_debugfs.c
184
static int fw_log_show(struct seq_file *s, void *v)
drivers/accel/ivpu/ivpu_debugfs.c
32
static int bo_list_show(struct seq_file *s, void *v)
drivers/accel/ivpu/ivpu_debugfs.c
413
static int priority_bands_show(struct seq_file *s, void *v)
drivers/accel/ivpu/ivpu_debugfs.c
42
static int fw_name_show(struct seq_file *s, void *v)
drivers/accel/ivpu/ivpu_debugfs.c
50
static int fw_version_show(struct seq_file *s, void *v)
drivers/accel/ivpu/ivpu_debugfs.c
58
static int fw_trace_capability_show(struct seq_file *s, void *v)
drivers/accel/ivpu/ivpu_debugfs.c
76
static int fw_trace_config_show(struct seq_file *s, void *v)
drivers/accel/ivpu/ivpu_debugfs.c
96
static int last_bootmode_show(struct seq_file *s, void *v)
drivers/acpi/apei/einj-core.c
250
struct vendor_error_type_extension *v)
drivers/acpi/apei/einj-core.c
255
vendor_size = v->length - sizeof(struct vendor_error_type_extension);
drivers/acpi/apei/einj-core.c
268
struct vendor_error_type_extension v;
drivers/acpi/apei/einj-core.c
277
memcpy_fromio(&v, p, sizeof(v));
drivers/acpi/apei/einj-core.c
278
get_oem_vendor_struct(paddr, offset, &v);
drivers/acpi/apei/einj-core.c
279
sbdf = v.pcie_sbdf;
drivers/acpi/apei/einj-core.c
283
v.vendor_id, v.device_id, v.rev_id);
drivers/acpi/apei/einj-core.c
284
acpi_os_unmap_iomem(p, sizeof(v));
drivers/acpi/apei/einj-core.c
823
static int available_error_type_show(struct seq_file *m, void *v)
drivers/acpi/apei/einj-cxl.c
28
int einj_cxl_available_error_type_show(struct seq_file *m, void *v)
drivers/acpi/sysfs.c
36
#define ACPI_DEBUG_INIT(v) { .name = #v, .value = v }
drivers/acpi/x86/apple.c
110
unsigned int v = k + 1;
drivers/acpi/x86/apple.c
122
newprops[v].type = val->type;
drivers/acpi/x86/apple.c
124
newprops[v].integer.value = val->integer.value;
drivers/acpi/x86/apple.c
126
newprops[v].string.length = val->string.length;
drivers/acpi/x86/apple.c
127
newprops[v].string.pointer = free_space;
drivers/acpi/x86/apple.c
132
newprops[v].buffer.length = val->buffer.length;
drivers/acpi/x86/apple.c
133
newprops[v].buffer.pointer = free_space;
drivers/ata/libata-pata-timings.c
57
#define ENOUGH(v, unit) (((v)-1)/(unit)+1)
drivers/ata/libata-pata-timings.c
58
#define EZ(v, unit) ((v)?ENOUGH(((v) * 1000), unit):0)
drivers/ata/pata_atp867x.c
363
u8 v;
drivers/ata/pata_atp867x.c
368
pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &v);
drivers/ata/pata_atp867x.c
369
if (v < 0x80) {
drivers/ata/pata_atp867x.c
370
v = 0x80;
drivers/ata/pata_atp867x.c
371
pci_write_config_byte(pdev, PCI_LATENCY_TIMER, v);
drivers/ata/pata_atp867x.c
372
dev_dbg(&pdev->dev, "ATP867X: set latency timer to %d\n", v);
drivers/ata/pata_atp867x.c
388
v = ioread8(ATP867X_IOBASE(ap) + 0x28);
drivers/ata/pata_atp867x.c
389
v &= 0xcf; /* Enable INTA#: bit4=0 means enable */
drivers/ata/pata_atp867x.c
390
v |= 0xc0; /* Enable PCI burst, MRM & not immediate interrupts */
drivers/ata/pata_atp867x.c
391
iowrite8(v, ATP867X_IOBASE(ap) + 0x28);
drivers/ata/pata_atp867x.c
396
v = ioread8(ATP867X_SYS_INFO(ap));
drivers/ata/pata_atp867x.c
397
v &= ATP867X_IO_SYS_MASK_RESERVED;
drivers/ata/pata_atp867x.c
399
v |= ATP867X_IO_SYS_INFO_SLOW_UDMA5;
drivers/ata/pata_atp867x.c
400
iowrite8(v, ATP867X_SYS_INFO(ap));
drivers/ata/pata_ep93xx.c
704
u32 v = qc->dma_dir == DMA_TO_DEVICE ? IDEUDMAOP_RWOP : 0;
drivers/ata/pata_ep93xx.c
730
writel(v, base + IDEUDMAOP);
drivers/ata/pata_ep93xx.c
732
writel(v | IDEUDMAOP_UEN, base + IDEUDMAOP);
drivers/ata/pata_it821x.c
194
u8 v;
drivers/ata/pata_it821x.c
224
pci_read_config_byte(pdev, 0x50, &v);
drivers/ata/pata_it821x.c
225
v &= ~(1 << (1 + ap->port_no));
drivers/ata/pata_it821x.c
226
v |= sel << (1 + ap->port_no);
drivers/ata/pata_it821x.c
227
pci_write_config_byte(pdev, 0x50, v);
drivers/ata/pata_mpc52xx.c
77
#define CALC_CLKCYC(c,v) ((((v)+(c)-1)/(c)))
drivers/ata/pata_parport/bpck.c
384
int i, j, k, p, v, f, om, od;
drivers/ata/pata_parport/bpck.c
406
v = 0;
drivers/ata/pata_parport/bpck.c
412
v = 2 * v + (f == 0x84);
drivers/ata/pata_parport/bpck.c
414
buf[2 * i + 1 - j] = v;
drivers/ata/pata_parport/bpck.c
93
#define WR(r,v) bpck_write_regr(pi,2,r,v)
drivers/ata/pata_parport/epat.c
208
#define WR(r, v) epat_write_regr(pi, 2, r, v)
drivers/ata/pata_parport/epat.c
213
#define WRi(r, v) epat_write_regr(pi, 0, r, v)
drivers/ata/pata_parport/epia.c
94
#define WR(r, v) epia_write_regr(pi, 0, r, v)
drivers/ata/pata_parport/on20.c
24
#define vl(v) \
drivers/ata/pata_parport/on20.c
26
w2(4); w0(v); w2(5); \
drivers/ata/sata_dwc_460ex.c
113
#define SATA_DWC_SCR0_SPD_GET(v) (((v) >> 4) & 0x0000000F)
drivers/ata/sata_dwc_460ex.c
114
#define SATA_DWC_DMACR_TX_CLEAR(v) (((v) & ~SATA_DWC_DMACR_TXCHEN) |\
drivers/ata/sata_dwc_460ex.c
116
#define SATA_DWC_DMACR_RX_CLEAR(v) (((v) & ~SATA_DWC_DMACR_RXCHEN) |\
drivers/ata/sata_dwc_460ex.c
41
#define sata_dwc_writel(a, v) writel_relaxed(v, a)
drivers/ata/sata_via.c
207
u32 v = 0;
drivers/ata/sata_via.c
215
v |= raw & 0x03;
drivers/ata/sata_via.c
219
v |= 0x02 << 4;
drivers/ata/sata_via.c
221
v |= 0x01 << 4;
drivers/ata/sata_via.c
224
v |= ipm_tbl[(raw >> 2) & 0x3];
drivers/ata/sata_via.c
230
pci_read_config_dword(pdev, 0xB0 + slot * 4, &v);
drivers/ata/sata_via.c
237
v |= ((raw & 0x02) << 1) | (raw & 0x01);
drivers/ata/sata_via.c
240
v |= ((raw >> 2) & 0x03) << 8;
drivers/ata/sata_via.c
247
*val = v;
drivers/ata/sata_via.c
255
u32 v = 0;
drivers/ata/sata_via.c
266
v |= ((val & 0x4) >> 1) | (val & 0x1);
drivers/ata/sata_via.c
269
v |= ((val >> 8) & 0x3) << 2;
drivers/ata/sata_via.c
271
pci_write_config_byte(pdev, 0xA4 + slot, v);
drivers/atm/eni.c
155
#define eni_out(v,r) writel((v),eni_dev->reg+(r)*4)
drivers/atm/iphase.h
1060
#define INPH_IA_VCC(v) ((struct ia_vcc *) (v)->dev_data)
drivers/atm/lanai.c
1001
v = eeprom_be4(lanai, EEPROM_MAGIC_REV);
drivers/atm/lanai.c
1002
if ((lanai->magicno ^ v) != 0xFFFFFFFF) {
drivers/atm/lanai.c
1005
lanai->magicno, v);
drivers/atm/lanai.c
946
u32 v;
drivers/atm/lanai.c
991
v = eeprom_be4(lanai, EEPROM_SERIAL_REV);
drivers/atm/lanai.c
992
if ((lanai->serialno ^ v) != 0xFFFFFFFF) {
drivers/atm/lanai.c
995
(unsigned int) lanai->serialno, (unsigned int) v);
drivers/atm/suni.c
51
#define ADD_LIMITED(s,v) \
drivers/atm/suni.c
52
atomic_add((v),&stats->s); \
drivers/auxdisplay/panel.c
1376
__u64 m, v;
drivers/auxdisplay/panel.c
1381
v = 0ULL;
drivers/auxdisplay/panel.c
1409
v |= 1ULL << bit;
drivers/auxdisplay/panel.c
1413
*value = v;
drivers/base/memory.c
207
int memory_notify(enum memory_block_state state, void *v)
drivers/base/memory.c
209
return blocking_notifier_call_chain(&memory_chain, state, v);
drivers/base/node.c
130
int node_notify(unsigned long val, void *v)
drivers/base/node.c
132
return blocking_notifier_call_chain(&node_chain, val, v);
drivers/base/power/wakeup.c
1112
void *v, loff_t *pos)
drivers/base/power/wakeup.c
1114
struct wakeup_source *ws = v;
drivers/base/power/wakeup.c
1130
static void wakeup_sources_stats_seq_stop(struct seq_file *m, void *v)
drivers/base/power/wakeup.c
1142
static int wakeup_sources_stats_seq_show(struct seq_file *m, void *v)
drivers/base/power/wakeup.c
1144
struct wakeup_source *ws = v;
drivers/base/regmap/regcache-maple.c
246
unsigned int r, v, sync_start;
drivers/base/regmap/regcache-maple.c
256
v = entry[r - mas.index];
drivers/base/regmap/regcache-maple.c
258
if (regcache_reg_needs_sync(map, r, v)) {
drivers/base/regmap/regmap-fsi.c
103
*val = be16_to_cpu(v);
drivers/base/regmap/regmap-fsi.c
109
__be16 v;
drivers/base/regmap/regmap-fsi.c
114
v = cpu_to_be16(val);
drivers/base/regmap/regmap-fsi.c
115
return fsi_slave_write(context, reg, &v, sizeof(v));
drivers/base/regmap/regmap-fsi.c
125
u8 v;
drivers/base/regmap/regmap-fsi.c
128
ret = fsi_slave_read(context, reg, &v, sizeof(v));
drivers/base/regmap/regmap-fsi.c
132
*val = v;
drivers/base/regmap/regmap-fsi.c
138
u8 v;
drivers/base/regmap/regmap-fsi.c
143
v = val;
drivers/base/regmap/regmap-fsi.c
144
return fsi_slave_write(context, reg, &v, sizeof(v));
drivers/base/regmap/regmap-fsi.c
17
u32 v;
drivers/base/regmap/regmap-fsi.c
20
ret = fsi_slave_read(context, reg, &v, sizeof(v));
drivers/base/regmap/regmap-fsi.c
24
*val = v;
drivers/base/regmap/regmap-fsi.c
30
u32 v = val;
drivers/base/regmap/regmap-fsi.c
32
return fsi_slave_write(context, reg, &v, sizeof(v));
drivers/base/regmap/regmap-fsi.c
42
__be32 v;
drivers/base/regmap/regmap-fsi.c
45
ret = fsi_slave_read(context, reg, &v, sizeof(v));
drivers/base/regmap/regmap-fsi.c
49
*val = be32_to_cpu(v);
drivers/base/regmap/regmap-fsi.c
55
__be32 v = cpu_to_be32(val);
drivers/base/regmap/regmap-fsi.c
57
return fsi_slave_write(context, reg, &v, sizeof(v));
drivers/base/regmap/regmap-fsi.c
67
u16 v;
drivers/base/regmap/regmap-fsi.c
70
ret = fsi_slave_read(context, reg, &v, sizeof(v));
drivers/base/regmap/regmap-fsi.c
74
*val = v;
drivers/base/regmap/regmap-fsi.c
80
u16 v;
drivers/base/regmap/regmap-fsi.c
85
v = val;
drivers/base/regmap/regmap-fsi.c
86
return fsi_slave_write(context, reg, &v, sizeof(v));
drivers/base/regmap/regmap-fsi.c
96
__be16 v;
drivers/base/regmap/regmap-fsi.c
99
ret = fsi_slave_read(context, reg, &v, sizeof(v));
drivers/base/regmap/regmap.c
286
u16 v = val << shift;
drivers/base/regmap/regmap.c
288
memcpy(buf, &v, sizeof(v));
drivers/base/regmap/regmap.c
2937
unsigned int v;
drivers/base/regmap/regmap.c
2995
&v);
drivers/base/regmap/regmap.c
2999
map->format.format_val(val + (i * val_bytes), v, 0);
drivers/base/regmap/regmap.c
309
u32 v = val << shift;
drivers/base/regmap/regmap.c
311
memcpy(buf, &v, sizeof(v));
drivers/base/regmap/regmap.c
337
u16 v = get_unaligned_be16(buf);
drivers/base/regmap/regmap.c
339
memcpy(buf, &v, sizeof(v));
drivers/base/regmap/regmap.c
344
u16 v = get_unaligned_le16(buf);
drivers/base/regmap/regmap.c
346
memcpy(buf, &v, sizeof(v));
drivers/base/regmap/regmap.c
351
u16 v;
drivers/base/regmap/regmap.c
353
memcpy(&v, buf, sizeof(v));
drivers/base/regmap/regmap.c
354
return v;
drivers/base/regmap/regmap.c
374
u32 v = get_unaligned_be32(buf);
drivers/base/regmap/regmap.c
376
memcpy(buf, &v, sizeof(v));
drivers/base/regmap/regmap.c
381
u32 v = get_unaligned_le32(buf);
drivers/base/regmap/regmap.c
383
memcpy(buf, &v, sizeof(v));
drivers/base/regmap/regmap.c
388
u32 v;
drivers/base/regmap/regmap.c
390
memcpy(&v, buf, sizeof(v));
drivers/base/regmap/regmap.c
391
return v;
drivers/bcma/driver_pci.c
105
u32 v;
drivers/bcma/driver_pci.c
109
v = BCMA_CORE_PCI_MDIOCTL_PREAM_EN;
drivers/bcma/driver_pci.c
110
v |= BCMA_CORE_PCI_MDIOCTL_DIVISOR_VAL;
drivers/bcma/driver_pci.c
111
pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, v);
drivers/bcma/driver_pci.c
116
v = (BCMA_CORE_PCI_MDIODATA_DEV_ADDR <<
drivers/bcma/driver_pci.c
118
v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF);
drivers/bcma/driver_pci.c
120
v = (device << BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD);
drivers/bcma/driver_pci.c
121
v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD);
drivers/bcma/driver_pci.c
124
v |= BCMA_CORE_PCI_MDIODATA_START;
drivers/bcma/driver_pci.c
125
v |= BCMA_CORE_PCI_MDIODATA_WRITE;
drivers/bcma/driver_pci.c
126
v |= BCMA_CORE_PCI_MDIODATA_TA;
drivers/bcma/driver_pci.c
127
v |= data;
drivers/bcma/driver_pci.c
128
pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v);
drivers/bcma/driver_pci.c
132
v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
drivers/bcma/driver_pci.c
133
if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE)
drivers/bcma/driver_pci.c
36
u32 v;
drivers/bcma/driver_pci.c
39
v = BCMA_CORE_PCI_MDIODATA_START;
drivers/bcma/driver_pci.c
40
v |= BCMA_CORE_PCI_MDIODATA_WRITE;
drivers/bcma/driver_pci.c
41
v |= (BCMA_CORE_PCI_MDIODATA_DEV_ADDR <<
drivers/bcma/driver_pci.c
43
v |= (BCMA_CORE_PCI_MDIODATA_BLK_ADDR <<
drivers/bcma/driver_pci.c
45
v |= BCMA_CORE_PCI_MDIODATA_TA;
drivers/bcma/driver_pci.c
46
v |= (phy << 4);
drivers/bcma/driver_pci.c
47
pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v);
drivers/bcma/driver_pci.c
51
v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
drivers/bcma/driver_pci.c
52
if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE)
drivers/bcma/driver_pci.c
62
u32 v;
drivers/bcma/driver_pci.c
66
v = BCMA_CORE_PCI_MDIOCTL_PREAM_EN;
drivers/bcma/driver_pci.c
67
v |= BCMA_CORE_PCI_MDIOCTL_DIVISOR_VAL;
drivers/bcma/driver_pci.c
68
pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, v);
drivers/bcma/driver_pci.c
73
v = (BCMA_CORE_PCI_MDIODATA_DEV_ADDR <<
drivers/bcma/driver_pci.c
75
v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF);
drivers/bcma/driver_pci.c
77
v = (device << BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD);
drivers/bcma/driver_pci.c
78
v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD);
drivers/bcma/driver_pci.c
81
v |= BCMA_CORE_PCI_MDIODATA_START;
drivers/bcma/driver_pci.c
82
v |= BCMA_CORE_PCI_MDIODATA_READ;
drivers/bcma/driver_pci.c
83
v |= BCMA_CORE_PCI_MDIODATA_TA;
drivers/bcma/driver_pci.c
85
pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v);
drivers/bcma/driver_pci.c
89
v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
drivers/bcma/driver_pci.c
90
if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE) {
drivers/bcma/sprom.c
206
u16 v;
drivers/bcma/sprom.c
209
v = in[SPOFF(offset)];
drivers/bcma/sprom.c
210
gain = (v & mask) >> shift;
drivers/bcma/sprom.c
223
u16 v, o;
drivers/bcma/sprom.c
233
v = sprom[SPOFF(SSB_SPROM8_IL0MAC) + i];
drivers/bcma/sprom.c
234
*(((__be16 *)bus->sprom.il0mac) + i) = cpu_to_be16(v);
drivers/block/drbd/drbd_int.h
1510
int drbd_seq_show(struct seq_file *seq, void *v);
drivers/block/drbd/drbd_proc.c
215
int drbd_seq_show(struct seq_file *seq, void *v)
drivers/block/drbd/drbd_proc.c
26
static void seq_printf_with_thousands_grouping(struct seq_file *seq, long v)
drivers/block/drbd/drbd_proc.c
29
if (unlikely(v >= 1000000)) {
drivers/block/drbd/drbd_proc.c
31
seq_printf(seq, "%ld,", v / 1000000);
drivers/block/drbd/drbd_proc.c
32
v %= 1000000;
drivers/block/drbd/drbd_proc.c
33
seq_printf(seq, "%03ld,%03ld", v/1000, v % 1000);
drivers/block/drbd/drbd_proc.c
34
} else if (likely(v >= 1000))
drivers/block/drbd/drbd_proc.c
35
seq_printf(seq, "%ld,%03ld", v/1000, v % 1000);
drivers/block/drbd/drbd_proc.c
37
seq_printf(seq, "%ld", v);
drivers/block/drbd/drbd_vli.h
138
#define LEVEL(t,b,v) \
drivers/block/drbd/drbd_vli.h
140
if ((in & ((1 << b) -1)) == v) { \
drivers/block/drbd/drbd_vli.h
164
#define LEVEL(t,b,v) do { \
drivers/block/drbd/drbd_vli.h
168
*out = ((in - adj) << b) | v; \
drivers/block/floppy.c
3660
struct floppy_struct v;
drivers/block/floppy.c
3670
memset(&v, 0, sizeof(struct floppy_struct));
drivers/block/floppy.c
3671
if (copy_from_user(&v, arg, offsetof(struct floppy_struct, name)))
drivers/block/floppy.c
3678
&v, drive, type, bdev);
drivers/block/floppy.c
3686
struct compat_floppy_struct v;
drivers/block/floppy.c
3690
memset(&v, 0, sizeof(v));
drivers/block/floppy.c
3698
memcpy(&v, p, offsetof(struct floppy_struct, name));
drivers/block/floppy.c
3700
if (copy_to_user(arg, &v, sizeof(struct compat_floppy_struct)))
drivers/block/floppy.c
3708
struct compat_floppy_drive_params v;
drivers/block/floppy.c
3712
if (copy_from_user(&v, arg, sizeof(struct compat_floppy_drive_params)))
drivers/block/floppy.c
3714
if (!valid_floppy_drive_params(v.autodetect, v.native_format))
drivers/block/floppy.c
3717
drive_params[drive].cmos = v.cmos;
drivers/block/floppy.c
3718
drive_params[drive].max_dtr = v.max_dtr;
drivers/block/floppy.c
3719
drive_params[drive].hlt = v.hlt;
drivers/block/floppy.c
3720
drive_params[drive].hut = v.hut;
drivers/block/floppy.c
3721
drive_params[drive].srt = v.srt;
drivers/block/floppy.c
3722
drive_params[drive].spinup = v.spinup;
drivers/block/floppy.c
3723
drive_params[drive].spindown = v.spindown;
drivers/block/floppy.c
3724
drive_params[drive].spindown_offset = v.spindown_offset;
drivers/block/floppy.c
3725
drive_params[drive].select_delay = v.select_delay;
drivers/block/floppy.c
3726
drive_params[drive].rps = v.rps;
drivers/block/floppy.c
3727
drive_params[drive].tracks = v.tracks;
drivers/block/floppy.c
3728
drive_params[drive].timeout = v.timeout;
drivers/block/floppy.c
3729
drive_params[drive].interleave_sect = v.interleave_sect;
drivers/block/floppy.c
3730
drive_params[drive].max_errors = v.max_errors;
drivers/block/floppy.c
3731
drive_params[drive].flags = v.flags;
drivers/block/floppy.c
3732
drive_params[drive].read_track = v.read_track;
drivers/block/floppy.c
3733
memcpy(drive_params[drive].autodetect, v.autodetect,
drivers/block/floppy.c
3734
sizeof(v.autodetect));
drivers/block/floppy.c
3735
drive_params[drive].checkfreq = v.checkfreq;
drivers/block/floppy.c
3736
drive_params[drive].native_format = v.native_format;
drivers/block/floppy.c
3744
struct compat_floppy_drive_params v;
drivers/block/floppy.c
3746
memset(&v, 0, sizeof(struct compat_floppy_drive_params));
drivers/block/floppy.c
3748
v.cmos = drive_params[drive].cmos;
drivers/block/floppy.c
3749
v.max_dtr = drive_params[drive].max_dtr;
drivers/block/floppy.c
3750
v.hlt = drive_params[drive].hlt;
drivers/block/floppy.c
3751
v.hut = drive_params[drive].hut;
drivers/block/floppy.c
3752
v.srt = drive_params[drive].srt;
drivers/block/floppy.c
3753
v.spinup = drive_params[drive].spinup;
drivers/block/floppy.c
3754
v.spindown = drive_params[drive].spindown;
drivers/block/floppy.c
3755
v.spindown_offset = drive_params[drive].spindown_offset;
drivers/block/floppy.c
3756
v.select_delay = drive_params[drive].select_delay;
drivers/block/floppy.c
3757
v.rps = drive_params[drive].rps;
drivers/block/floppy.c
3758
v.tracks = drive_params[drive].tracks;
drivers/block/floppy.c
3759
v.timeout = drive_params[drive].timeout;
drivers/block/floppy.c
3760
v.interleave_sect = drive_params[drive].interleave_sect;
drivers/block/floppy.c
3761
v.max_errors = drive_params[drive].max_errors;
drivers/block/floppy.c
3762
v.flags = drive_params[drive].flags;
drivers/block/floppy.c
3763
v.read_track = drive_params[drive].read_track;
drivers/block/floppy.c
3764
memcpy(v.autodetect, drive_params[drive].autodetect,
drivers/block/floppy.c
3765
sizeof(v.autodetect));
drivers/block/floppy.c
3766
v.checkfreq = drive_params[drive].checkfreq;
drivers/block/floppy.c
3767
v.native_format = drive_params[drive].native_format;
drivers/block/floppy.c
3770
if (copy_to_user(arg, &v, sizeof(struct compat_floppy_drive_params)))
drivers/block/floppy.c
3778
struct compat_floppy_drive_struct v;
drivers/block/floppy.c
3780
memset(&v, 0, sizeof(struct compat_floppy_drive_struct));
drivers/block/floppy.c
3790
v.spinup_date = drive_state[drive].spinup_date;
drivers/block/floppy.c
3791
v.select_date = drive_state[drive].select_date;
drivers/block/floppy.c
3792
v.first_read_date = drive_state[drive].first_read_date;
drivers/block/floppy.c
3793
v.probed_format = drive_state[drive].probed_format;
drivers/block/floppy.c
3794
v.track = drive_state[drive].track;
drivers/block/floppy.c
3795
v.maxblock = drive_state[drive].maxblock;
drivers/block/floppy.c
3796
v.maxtrack = drive_state[drive].maxtrack;
drivers/block/floppy.c
3797
v.generation = drive_state[drive].generation;
drivers/block/floppy.c
3798
v.keep_data = drive_state[drive].keep_data;
drivers/block/floppy.c
3799
v.fd_ref = drive_state[drive].fd_ref;
drivers/block/floppy.c
3800
v.fd_device = drive_state[drive].fd_device;
drivers/block/floppy.c
3801
v.last_checked = drive_state[drive].last_checked;
drivers/block/floppy.c
3802
v.dmabuf = (uintptr_t) drive_state[drive].dmabuf;
drivers/block/floppy.c
3803
v.bufblocks = drive_state[drive].bufblocks;
drivers/block/floppy.c
3806
if (copy_to_user(arg, &v, sizeof(struct compat_floppy_drive_struct)))
drivers/block/floppy.c
3818
struct floppy_fdc_state v;
drivers/block/floppy.c
3821
v = fdc_state[FDC(drive)];
drivers/block/floppy.c
3825
v32.spec1 = v.spec1;
drivers/block/floppy.c
3826
v32.spec2 = v.spec2;
drivers/block/floppy.c
3827
v32.dtr = v.dtr;
drivers/block/floppy.c
3828
v32.version = v.version;
drivers/block/floppy.c
3829
v32.dor = v.dor;
drivers/block/floppy.c
3830
v32.address = v.address;
drivers/block/floppy.c
3831
v32.rawcmd = v.rawcmd;
drivers/block/floppy.c
3832
v32.reset = v.reset;
drivers/block/floppy.c
3833
v32.need_configure = v.need_configure;
drivers/block/floppy.c
3834
v32.perp_mode = v.perp_mode;
drivers/block/floppy.c
3835
v32.has_fifo = v.has_fifo;
drivers/block/floppy.c
3836
v32.driver_version = v.driver_version;
drivers/block/floppy.c
3837
memcpy(v32.track, v.track, 4);
drivers/block/floppy.c
3847
struct floppy_write_errors v;
drivers/block/floppy.c
3851
v = write_errors[drive];
drivers/block/floppy.c
3853
v32.write_errors = v.write_errors;
drivers/block/floppy.c
3854
v32.first_error_sector = v.first_error_sector;
drivers/block/floppy.c
3855
v32.first_error_generation = v.first_error_generation;
drivers/block/floppy.c
3856
v32.last_error_sector = v.last_error_sector;
drivers/block/floppy.c
3857
v32.last_error_generation = v.last_error_generation;
drivers/block/floppy.c
3858
v32.badness = v.badness;
drivers/block/ps3vram.c
509
static int ps3vram_proc_show(struct seq_file *m, void *v)
drivers/block/rbd.c
60
static int atomic_inc_return_safe(atomic_t *v)
drivers/block/rbd.c
64
counter = (unsigned int)atomic_fetch_add_unless(v, 1, 0);
drivers/block/rbd.c
68
atomic_dec(v);
drivers/block/rbd.c
74
static int atomic_dec_return_safe(atomic_t *v)
drivers/block/rbd.c
78
counter = atomic_dec_return(v);
drivers/block/rbd.c
82
atomic_inc(v);
drivers/block/swim.c
63
#define swim_write(base, reg, v) out_8(&(base)->write_##reg, (v))
drivers/block/swim.c
87
#define iwm_write(base, reg, v) out_8(&(base)->reg, (v))
drivers/block/virtio_blk.c
1248
u32 v, max_size, sg_elems, opt_io_size;
drivers/block/virtio_blk.c
1280
struct virtio_blk_config, size_max, &v);
drivers/block/virtio_blk.c
1282
max_size = min(max_size, v);
drivers/block/virtio_blk.c
1323
max_discard_sectors, &v);
drivers/block/virtio_blk.c
1324
lim->max_hw_discard_sectors = v ? v : UINT_MAX;
drivers/block/virtio_blk.c
1332
max_write_zeroes_sectors, &v);
drivers/block/virtio_blk.c
1333
lim->max_write_zeroes_sectors = v ? v : UINT_MAX;
drivers/block/virtio_blk.c
1351
secure_erase_sector_alignment, &v);
drivers/block/virtio_blk.c
1356
if (!v) {
drivers/block/virtio_blk.c
1362
discard_granularity = min_not_zero(discard_granularity, v);
drivers/block/virtio_blk.c
1365
max_secure_erase_sectors, &v);
drivers/block/virtio_blk.c
1370
if (!v) {
drivers/block/virtio_blk.c
1376
lim->max_secure_erase_sectors = v;
drivers/block/virtio_blk.c
1379
max_secure_erase_seg, &v);
drivers/block/virtio_blk.c
1384
if (!v) {
drivers/block/virtio_blk.c
1390
max_discard_segs = min_not_zero(max_discard_segs, v);
drivers/block/virtio_blk.c
722
u32 v, wg;
drivers/block/virtio_blk.c
729
zoned.max_open_zones, &v);
drivers/block/virtio_blk.c
730
lim->max_open_zones = v;
drivers/block/virtio_blk.c
731
dev_dbg(&vdev->dev, "max open zones = %u\n", v);
drivers/block/virtio_blk.c
734
zoned.max_active_zones, &v);
drivers/block/virtio_blk.c
735
lim->max_active_zones = v;
drivers/block/virtio_blk.c
736
dev_dbg(&vdev->dev, "max active zones = %u\n", v);
drivers/block/virtio_blk.c
771
zoned.max_append_sectors, &v);
drivers/block/virtio_blk.c
772
if (!v) {
drivers/block/virtio_blk.c
776
if ((v << SECTOR_SHIFT) < wg) {
drivers/block/virtio_blk.c
779
wg, v);
drivers/block/virtio_blk.c
782
lim->max_hw_zone_append_sectors = v;
drivers/block/virtio_blk.c
783
dev_dbg(&vdev->dev, "max append sectors = %u\n", v);
drivers/bus/brcmstb_gisb.c
364
static int dump_gisb_error(struct notifier_block *self, unsigned long v,
drivers/bus/brcmstb_gisb.c
375
static int dump_gisb_error(struct notifier_block *self, unsigned long v,
drivers/bus/mvebu-mbus.c
119
struct seq_file *seq, void *v);
drivers/bus/mvebu-mbus.c
409
struct seq_file *seq, void *v)
drivers/bus/mvebu-mbus.c
439
struct seq_file *seq, void *v)
drivers/bus/mvebu-mbus.c
464
static int mvebu_sdram_debug_show(struct seq_file *seq, void *v)
drivers/bus/mvebu-mbus.c
467
return mbus->soc->show_cpu_target(mbus, seq, v);
drivers/bus/mvebu-mbus.c
471
static int mvebu_devs_debug_show(struct seq_file *seq, void *v)
drivers/bus/omap_l3_smx.h
319
#define __raw_writell(v, a) (__chk_io_ptr(a), \
drivers/bus/omap_l3_smx.h
320
*(volatile u64 __force *)(a) = (v))
drivers/bus/sunxi-rsb.c
107
#define RSB_DAR_RTA(v) (((v) & 0xff) << 16)
drivers/bus/sunxi-rsb.c
108
#define RSB_DAR_DA(v) ((v) & 0xffff)
drivers/bus/sunxi-rsb.c
71
#define RSB_CCR_SDA_OUT_DELAY(v) (((v) & 0x7) << 8)
drivers/bus/sunxi-rsb.c
73
#define RSB_CCR_CLK_DIV(v) ((v) & RSB_CCR_MAX_CLK_DIV)
drivers/bus/sunxi-rsb.c
77
#define RSB_INTS_TRANS_ERR_DATA_BIT(v) (((v) >> 8) & 0xf)
drivers/bus/ti-sysc.c
2446
void *v)
drivers/cache/starfive_starlink_cache.c
37
u64 v;
drivers/cache/starfive_starlink_cache.c
40
ret = readq_poll_timeout_atomic(ctl, v, !(v & STARLINK_CACHE_FLUSH_CTL_ENABLE_MASK),
drivers/char/apm-emulation.c
425
static int proc_apm_show(struct seq_file *m, void *v)
drivers/char/ds1620.c
334
static int ds1620_proc_therm_show(struct seq_file *m, void *v)
drivers/char/hpet.c
166
unsigned long v;
drivers/char/hpet.c
179
v = readl(&timer->hpet_config);
drivers/char/hpet.c
180
if (!(v & Tn_INT_TYPE_CNF_MASK)) {
drivers/char/hpet.c
181
v |= Tn_INT_TYPE_CNF_MASK;
drivers/char/hpet.c
182
writel(v, &timer->hpet_config);
drivers/char/hpet.c
186
v = (readq(&timer->hpet_config) & Tn_INT_ROUTE_CAP_MASK) >>
drivers/char/hpet.c
194
v &= ~0xf3df;
drivers/char/hpet.c
196
v &= ~0xffff;
drivers/char/hpet.c
198
for_each_set_bit(irq, &v, HPET_MAX_IRQ) {
drivers/char/hpet.c
214
v = readl(&timer->hpet_config);
drivers/char/hpet.c
215
v |= irq << Tn_INT_ROUTE_CNF_SHIFT;
drivers/char/hpet.c
216
writel(v, &timer->hpet_config);
drivers/char/hpet.c
322
unsigned long v;
drivers/char/hpet.c
333
v = devp->hd_irqdata;
drivers/char/hpet.c
336
if (v != 0)
drivers/char/hpet.c
414
unsigned long v;
drivers/char/hpet.c
416
v = readq(&timer->hpet_config);
drivers/char/hpet.c
417
v ^= Tn_TYPE_CNF_MASK;
drivers/char/hpet.c
418
writeq(v, &timer->hpet_config);
drivers/char/hpet.c
437
unsigned long g, v, t, m;
drivers/char/hpet.c
498
v = readq(&timer->hpet_config);
drivers/char/hpet.c
503
g = v | Tn_32MODE_CNF_MASK | Tn_INT_ENB_CNF_MASK;
drivers/char/hpet.c
507
v |= Tn_TYPE_CNF_MASK | Tn_VAL_SET_CNF_MASK;
drivers/char/hpet.c
508
writeq(v, &timer->hpet_config);
drivers/char/hpet.c
558
unsigned long v;
drivers/char/hpet.c
581
v = readq(&timer->hpet_config);
drivers/char/hpet.c
582
v &= ~Tn_INT_ENB_CNF_MASK;
drivers/char/hpet.c
583
writeq(v, &timer->hpet_config);
drivers/char/hpet.c
603
v = readq(&timer->hpet_config);
drivers/char/hpet.c
604
if ((v & Tn_PER_INT_CAP_MASK) == 0) {
drivers/char/hpet.c
611
v = readq(&timer->hpet_config);
drivers/char/hpet.c
612
if ((v & Tn_PER_INT_CAP_MASK) == 0) {
drivers/char/hpet.c
618
v = readq(&timer->hpet_config);
drivers/char/hpet.c
619
v ^= Tn_TYPE_CNF_MASK;
drivers/char/hpet.c
620
writeq(v, &timer->hpet_config);
drivers/char/ipmi/ipmi_si_hotmod.c
58
static int parse_str(const struct hotmod_vals *v, unsigned int *val, char *name,
drivers/char/ipmi/ipmi_si_hotmod.c
71
for (i = 0; v[i].name; i++) {
drivers/char/ipmi/ipmi_si_hotmod.c
72
if (strcmp(*curr, v[i].name) == 0) {
drivers/char/ipmi/ipmi_si_hotmod.c
73
*val = v[i].val;
drivers/char/misc.c
101
static int misc_seq_show(struct seq_file *seq, void *v)
drivers/char/misc.c
103
const struct miscdevice *p = list_entry(v, struct miscdevice, list);
drivers/char/misc.c
91
static void *misc_seq_next(struct seq_file *seq, void *v, loff_t *pos)
drivers/char/misc.c
93
return seq_list_next(v, &misc_list, pos);
drivers/char/misc.c
96
static void misc_seq_stop(struct seq_file *seq, void *v)
drivers/char/sonypi.c
556
u32 v;
drivers/char/sonypi.c
558
pci_read_config_dword(sonypi_device.dev, SONYPI_G10A, &v);
drivers/char/sonypi.c
559
v = (v & 0xFFFF0000) | ((u32) sonypi_device.ioport1);
drivers/char/sonypi.c
560
pci_write_config_dword(sonypi_device.dev, SONYPI_G10A, v);
drivers/char/sonypi.c
562
pci_read_config_dword(sonypi_device.dev, SONYPI_G10A, &v);
drivers/char/sonypi.c
563
v = (v & 0xFFF0FFFF) |
drivers/char/sonypi.c
565
pci_write_config_dword(sonypi_device.dev, SONYPI_G10A, v);
drivers/char/sonypi.c
567
v = inl(SONYPI_IRQ_PORT);
drivers/char/sonypi.c
568
v &= ~(((u32) 0x3) << SONYPI_IRQ_SHIFT);
drivers/char/sonypi.c
569
v |= (((u32) sonypi_device.bits) << SONYPI_IRQ_SHIFT);
drivers/char/sonypi.c
570
outl(v, SONYPI_IRQ_PORT);
drivers/char/sonypi.c
572
pci_read_config_dword(sonypi_device.dev, SONYPI_G10A, &v);
drivers/char/sonypi.c
573
v = (v & 0xFF1FFFFF) | 0x00C00000;
drivers/char/sonypi.c
574
pci_write_config_dword(sonypi_device.dev, SONYPI_G10A, v);
drivers/char/sonypi.c
608
u32 v;
drivers/char/sonypi.c
610
pci_read_config_dword(sonypi_device.dev, SONYPI_G10A, &v);
drivers/char/sonypi.c
611
v = v & 0xFF3FFFFF;
drivers/char/sonypi.c
612
pci_write_config_dword(sonypi_device.dev, SONYPI_G10A, v);
drivers/char/sonypi.c
614
v = inl(SONYPI_IRQ_PORT);
drivers/char/sonypi.c
615
v |= (0x3 << SONYPI_IRQ_SHIFT);
drivers/char/sonypi.c
616
outl(v, SONYPI_IRQ_PORT);
drivers/char/sonypi.c
659
static u8 sonypi_call3(u8 dev, u8 fn, u8 v)
drivers/char/sonypi.c
668
outb(v, sonypi_device.ioport1);
drivers/char/sonypi.c
691
static void sonypi_set(u8 fn, u8 v)
drivers/char/sonypi.c
693
wait_on_command(0, sonypi_call3(0x90, fn, v), ITERATIONS_SHORT);
drivers/char/sonypi.c
699
u8 v;
drivers/char/sonypi.c
701
v = sonypi_call2(0x8f, SONYPI_CAMERA_STATUS);
drivers/char/sonypi.c
702
return (v != 0xff && (v & SONYPI_CAMERA_STATUS_READY));
drivers/char/toshiba.c
292
static int proc_toshiba_show(struct seq_file *m, void *v)
drivers/char/tpm/eventlog/tpm1.c
108
static void *tpm1_bios_measurements_next(struct seq_file *m, void *v,
drivers/char/tpm/eventlog/tpm1.c
111
struct tcpa_event *event = v;
drivers/char/tpm/eventlog/tpm1.c
121
v += sizeof(struct tcpa_event) + converted_event_size;
drivers/char/tpm/eventlog/tpm1.c
124
if ((v + sizeof(struct tcpa_event)) > limit)
drivers/char/tpm/eventlog/tpm1.c
127
event = v;
drivers/char/tpm/eventlog/tpm1.c
133
((v + sizeof(struct tcpa_event) + converted_event_size) > limit))
drivers/char/tpm/eventlog/tpm1.c
136
return v;
drivers/char/tpm/eventlog/tpm1.c
139
static void tpm1_bios_measurements_stop(struct seq_file *m, void *v)
drivers/char/tpm/eventlog/tpm1.c
223
static int tpm1_binary_bios_measurements_show(struct seq_file *m, void *v)
drivers/char/tpm/eventlog/tpm1.c
225
struct tcpa_event *event = v;
drivers/char/tpm/eventlog/tpm1.c
242
temp_ptr = (char *) v;
drivers/char/tpm/eventlog/tpm1.c
252
static int tpm1_ascii_bios_measurements_show(struct seq_file *m, void *v)
drivers/char/tpm/eventlog/tpm1.c
255
struct tcpa_event *event = v;
drivers/char/tpm/eventlog/tpm1.c
257
(unsigned char *)(v + sizeof(struct tcpa_event));
drivers/char/tpm/eventlog/tpm2.c
104
event = v;
drivers/char/tpm/eventlog/tpm2.c
114
v = marker;
drivers/char/tpm/eventlog/tpm2.c
115
event = v;
drivers/char/tpm/eventlog/tpm2.c
118
if (((v + event_size) >= limit) || (event_size == 0))
drivers/char/tpm/eventlog/tpm2.c
121
return v;
drivers/char/tpm/eventlog/tpm2.c
124
static void tpm2_bios_measurements_stop(struct seq_file *m, void *v)
drivers/char/tpm/eventlog/tpm2.c
128
static int tpm2_binary_bios_measurements_show(struct seq_file *m, void *v)
drivers/char/tpm/eventlog/tpm2.c
133
struct tcg_pcr_event2_head *event = v;
drivers/char/tpm/eventlog/tpm2.c
137
if (v == SEQ_START_TOKEN) {
drivers/char/tpm/eventlog/tpm2.c
85
static void *tpm2_bios_measurements_next(struct seq_file *m, void *v,
drivers/char/tpm/eventlog/tpm2.c
99
if (v == SEQ_START_TOKEN) {
drivers/char/tpm/tpm2-sessions.c
436
u8 *v, u32 bytes, u8 *out)
drivers/char/tpm/tpm2-sessions.c
449
hmac_sha256_update(&hctx, v, SHA256_DIGEST_SIZE);
drivers/clk/clk-cdce706.c
532
unsigned m, n, v;
drivers/clk/clk-cdce706.c
540
ret = cdce706_reg_read(cdce, CDCE706_PLL_HI(i), &v);
drivers/clk/clk-cdce706.c
543
cdce->pll[i].div = m | ((v & CDCE706_PLL_HI_M_MASK) << 8);
drivers/clk/clk-cdce706.c
544
cdce->pll[i].mul = n | ((v & CDCE706_PLL_HI_N_MASK) <<
drivers/clk/clk-si5351.c
915
unsigned int v;
drivers/clk/clk-si5351.c
926
err = regmap_read_poll_timeout(drvdata->regmap, SI5351_PLL_RESET, v,
drivers/clk/clk-si5351.c
927
!(v & mask), 0, 20000);
drivers/clk/clk-twl.c
22
#define TWL6030_CFG_STATE_APP(v) (((v) & TWL6030_CFG_STATE_APP_MASK) >>\
drivers/clk/mediatek/clk-fhctl.c
43
const struct fhctl_offset *fhctl_get_offset_table(enum fhctl_variant v)
drivers/clk/mediatek/clk-fhctl.c
45
switch (v) {
drivers/clk/mediatek/clk-fhctl.h
29
const struct fhctl_offset *fhctl_get_offset_table(enum fhctl_variant v);
drivers/clk/microchip/clk-core.c
171
u32 v, div;
drivers/clk/microchip/clk-core.c
175
err = readl_poll_timeout(pb->ctrl_reg, v, v & PB_DIV_READY,
drivers/clk/microchip/clk-core.c
186
v = readl(pb->ctrl_reg);
drivers/clk/microchip/clk-core.c
187
v &= ~PB_DIV_MASK;
drivers/clk/microchip/clk-core.c
188
v |= (div - 1);
drivers/clk/microchip/clk-core.c
192
writel(v, pb->ctrl_reg);
drivers/clk/microchip/clk-core.c
197
err = readl_poll_timeout(pb->ctrl_reg, v, v & PB_DIV_READY,
drivers/clk/microchip/clk-core.c
281
u32 v, i;
drivers/clk/microchip/clk-core.c
283
v = (readl(refo->ctrl_reg) >> REFO_SEL_SHIFT) & REFO_SEL_MASK;
drivers/clk/microchip/clk-core.c
287
if (refo->parent_map[i] == v)
drivers/clk/microchip/clk-core.c
291
return v;
drivers/clk/microchip/clk-core.c
362
u32 v, rodiv, rotrim;
drivers/clk/microchip/clk-core.c
365
v = readl(refo->ctrl_reg);
drivers/clk/microchip/clk-core.c
366
rodiv = (v >> REFO_DIV_SHIFT) & REFO_DIV_MASK;
drivers/clk/microchip/clk-core.c
369
v = readl(refo->ctrl_reg + REFO_TRIM_REG);
drivers/clk/microchip/clk-core.c
370
rotrim = (v >> REFO_TRIM_SHIFT) & REFO_TRIM_MASK;
drivers/clk/microchip/clk-core.c
440
u32 v;
drivers/clk/microchip/clk-core.c
447
err = readl_poll_timeout(refo->ctrl_reg, v, !(v & REFO_ACTIVE),
drivers/clk/microchip/clk-core.c
459
v = readl(refo->ctrl_reg);
drivers/clk/microchip/clk-core.c
460
v &= ~(REFO_SEL_MASK << REFO_SEL_SHIFT);
drivers/clk/microchip/clk-core.c
461
v |= index << REFO_SEL_SHIFT;
drivers/clk/microchip/clk-core.c
463
writel(v, refo->ctrl_reg);
drivers/clk/microchip/clk-core.c
477
u32 trim, rodiv, v;
drivers/clk/microchip/clk-core.c
487
err = readl_poll_timeout(refo->ctrl_reg, v,
drivers/clk/microchip/clk-core.c
488
!(v & (REFO_ACTIVE | REFO_DIVSW_EN)),
drivers/clk/microchip/clk-core.c
496
v = readl(refo->ctrl_reg);
drivers/clk/microchip/clk-core.c
504
v &= ~(REFO_SEL_MASK << REFO_SEL_SHIFT);
drivers/clk/microchip/clk-core.c
505
v |= index << REFO_SEL_SHIFT;
drivers/clk/microchip/clk-core.c
508
v &= ~(REFO_DIV_MASK << REFO_DIV_SHIFT);
drivers/clk/microchip/clk-core.c
509
v |= rodiv << REFO_DIV_SHIFT;
drivers/clk/microchip/clk-core.c
510
writel(v, refo->ctrl_reg);
drivers/clk/microchip/clk-core.c
513
v = readl(refo->ctrl_reg + REFO_TRIM_REG);
drivers/clk/microchip/clk-core.c
514
v &= ~(REFO_TRIM_MASK << REFO_TRIM_SHIFT);
drivers/clk/microchip/clk-core.c
515
v |= trim << REFO_TRIM_SHIFT;
drivers/clk/microchip/clk-core.c
516
writel(v, refo->ctrl_reg + REFO_TRIM_REG);
drivers/clk/microchip/clk-core.c
522
err = readl_poll_timeout_atomic(refo->ctrl_reg, v, !(v & REFO_DIVSW_EN),
drivers/clk/microchip/clk-core.c
644
u32 mult, odiv, div, v;
drivers/clk/microchip/clk-core.c
647
v = readl(pll->ctrl_reg);
drivers/clk/microchip/clk-core.c
648
odiv = ((v >> PLL_ODIV_SHIFT) & PLL_ODIV_MASK);
drivers/clk/microchip/clk-core.c
649
mult = ((v >> PLL_MULT_SHIFT) & PLL_MULT_MASK) + 1;
drivers/clk/microchip/clk-core.c
679
u32 mult, odiv, v;
drivers/clk/microchip/clk-core.c
700
v = readl(pll->ctrl_reg);
drivers/clk/microchip/clk-core.c
701
v &= ~(PLL_MULT_MASK << PLL_MULT_SHIFT);
drivers/clk/microchip/clk-core.c
702
v &= ~(PLL_ODIV_MASK << PLL_ODIV_SHIFT);
drivers/clk/microchip/clk-core.c
703
v |= (mult << PLL_MULT_SHIFT) | (odiv << PLL_ODIV_SHIFT);
drivers/clk/microchip/clk-core.c
708
writel(v, pll->ctrl_reg);
drivers/clk/microchip/clk-core.c
716
err = readl_poll_timeout_atomic(pll->status_reg, v,
drivers/clk/microchip/clk-core.c
717
v & pll->lock_mask, 1, 100);
drivers/clk/microchip/clk-core.c
786
u32 v, div;
drivers/clk/microchip/clk-core.c
794
v = readl(sclk->slew_reg);
drivers/clk/microchip/clk-core.c
795
v &= ~(SLEW_SYSDIV << SLEW_SYSDIV_SHIFT);
drivers/clk/microchip/clk-core.c
796
v |= (div - 1) << SLEW_SYSDIV_SHIFT;
drivers/clk/microchip/clk-core.c
800
writel(v, sclk->slew_reg);
drivers/clk/microchip/clk-core.c
803
err = readl_poll_timeout_atomic(sclk->slew_reg, v,
drivers/clk/microchip/clk-core.c
804
!(v & SLEW_BUSY), 1, LOCK_TIMEOUT_US);
drivers/clk/microchip/clk-core.c
814
u32 i, v;
drivers/clk/microchip/clk-core.c
816
v = (readl(sclk->mux_reg) >> OSC_CUR_SHIFT) & OSC_CUR_MASK;
drivers/clk/microchip/clk-core.c
820
if (sclk->parent_map[i] == v)
drivers/clk/microchip/clk-core.c
824
return v;
drivers/clk/microchip/clk-core.c
831
u32 nosc, cosc, v;
drivers/clk/microchip/clk-core.c
840
v = readl(sclk->mux_reg);
drivers/clk/microchip/clk-core.c
841
v &= ~(OSC_NEW_MASK << OSC_NEW_SHIFT);
drivers/clk/microchip/clk-core.c
842
v |= nosc << OSC_NEW_SHIFT;
drivers/clk/microchip/clk-core.c
846
writel(v, sclk->mux_reg);
drivers/clk/microchip/clk-core.c
856
err = readl_poll_timeout_atomic(sclk->slew_reg, v,
drivers/clk/microchip/clk-core.c
857
!(v & OSC_SWEN), 1, LOCK_TIMEOUT_US);
drivers/clk/microchip/clk-core.c
881
u32 v;
drivers/clk/microchip/clk-core.c
889
v = readl(sclk->slew_reg);
drivers/clk/microchip/clk-core.c
890
v &= ~(SLEW_DIV << SLEW_DIV_SHIFT);
drivers/clk/microchip/clk-core.c
891
v |= sclk->slew_div << SLEW_DIV_SHIFT;
drivers/clk/microchip/clk-core.c
892
v |= SLEW_DOWNEN | SLEW_UPEN;
drivers/clk/microchip/clk-core.c
893
writel(v, sclk->slew_reg);
drivers/clk/microchip/clk-core.c
957
u32 v;
drivers/clk/microchip/clk-core.c
964
return readl_poll_timeout_atomic(sosc->status_reg, v,
drivers/clk/microchip/clk-core.c
965
v & sosc->status_mask, 1, 100);
drivers/clk/mvebu/dove-divider.c
39
u32 v;
drivers/clk/mvebu/dove-divider.c
41
v = readl_relaxed(base + DIV_CTRL1) | DIV_CTRL1_N_RESET_MASK;
drivers/clk/mvebu/dove-divider.c
42
writel_relaxed(v, base + DIV_CTRL1);
drivers/clk/mvebu/dove-divider.c
44
v = (readl_relaxed(base + DIV_CTRL0) & ~(mask | load)) | val;
drivers/clk/mvebu/dove-divider.c
45
writel_relaxed(v, base + DIV_CTRL0);
drivers/clk/mvebu/dove-divider.c
46
writel_relaxed(v | load, base + DIV_CTRL0);
drivers/clk/mvebu/dove-divider.c
48
writel_relaxed(v, base + DIV_CTRL0);
drivers/clk/qcom/clk-alpha-pll.c
709
const struct pll_vco *v = pll->vco_table;
drivers/clk/qcom/clk-alpha-pll.c
710
const struct pll_vco *end = v + pll->num_vco;
drivers/clk/qcom/clk-alpha-pll.c
712
for (; v < end; v++)
drivers/clk/qcom/clk-alpha-pll.c
713
if (rate >= v->min_freq && rate <= v->max_freq)
drivers/clk/qcom/clk-alpha-pll.c
714
return v;
drivers/clk/sifive/sifive-prci.c
279
u32 v;
drivers/clk/sifive/sifive-prci.c
282
v = __prci_readl(pd, PRCI_CLKMUXSTATUSREG_OFFSET);
drivers/clk/sifive/sifive-prci.c
283
v &= PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_MASK;
drivers/clk/sifive/sifive-prci.c
284
div = v ? 1 : 2;
drivers/clk/sifive/sifive-prci.c
37
static void __prci_writel(u32 v, u32 offs, struct __prci_data *pd)
drivers/clk/sifive/sifive-prci.c
39
writel_relaxed(v, pd->va + offs);
drivers/clk/sifive/sifive-prci.c
60
u32 v;
drivers/clk/sifive/sifive-prci.c
62
v = r & PRCI_COREPLLCFG0_DIVR_MASK;
drivers/clk/sifive/sifive-prci.c
63
v >>= PRCI_COREPLLCFG0_DIVR_SHIFT;
drivers/clk/sifive/sifive-prci.c
64
c->divr = v;
drivers/clk/sifive/sifive-prci.c
66
v = r & PRCI_COREPLLCFG0_DIVF_MASK;
drivers/clk/sifive/sifive-prci.c
67
v >>= PRCI_COREPLLCFG0_DIVF_SHIFT;
drivers/clk/sifive/sifive-prci.c
68
c->divf = v;
drivers/clk/sifive/sifive-prci.c
70
v = r & PRCI_COREPLLCFG0_DIVQ_MASK;
drivers/clk/sifive/sifive-prci.c
71
v >>= PRCI_COREPLLCFG0_DIVQ_SHIFT;
drivers/clk/sifive/sifive-prci.c
72
c->divq = v;
drivers/clk/sifive/sifive-prci.c
74
v = r & PRCI_COREPLLCFG0_RANGE_MASK;
drivers/clk/sifive/sifive-prci.c
75
v >>= PRCI_COREPLLCFG0_RANGE_SHIFT;
drivers/clk/sifive/sifive-prci.c
76
c->range = v;
drivers/clk/tegra/clk-dfll.c
1257
u32 v, s;
drivers/clk/tegra/clk-dfll.c
1263
v = dfll_readl(td, DFLL_MONITOR_DATA);
drivers/clk/tegra/clk-dfll.c
1264
v = (v & DFLL_MONITOR_DATA_VAL_MASK) >> DFLL_MONITOR_DATA_VAL_SHIFT;
drivers/clk/tegra/clk-dfll.c
1265
pre_scaler_rate = dfll_calc_monitored_rate(v, td->ref_rate);
drivers/clk/tegra/clk-dfll.c
1702
unsigned long rate, v, v_opp;
drivers/clk/tegra/clk-dfll.c
1706
v = td->soc->cvb->min_millivolts * 1000;
drivers/clk/tegra/clk-dfll.c
1707
lut = find_vdd_map_entry_exact(td, v);
drivers/clk/tegra/clk-dfll.c
1727
v += max(1UL, (v_max - v) / (MAX_DFLL_VOLTAGES - j));
drivers/clk/tegra/clk-dfll.c
1728
if (v >= v_opp)
drivers/clk/tegra/clk-dfll.c
1731
selector = find_vdd_map_entry_min(td, v);
drivers/clk/tegra/clk-dfll.c
1738
v = (j == MAX_DFLL_VOLTAGES - 1) ? v_max : v_opp;
drivers/clk/tegra/clk-dfll.c
1739
selector = find_vdd_map_entry_exact(td, v);
drivers/clk/tegra/clk-dfll.c
1745
if (v >= v_max)
drivers/clk/tegra/clk-tegra114.c
1283
u32 v;
drivers/clk/tegra/clk-tegra114.c
1285
v = readl_relaxed(clk_base + RST_DFLL_DVCO);
drivers/clk/tegra/clk-tegra114.c
1286
v |= (1 << DVFS_DFLL_RESET_SHIFT);
drivers/clk/tegra/clk-tegra114.c
1287
writel_relaxed(v, clk_base + RST_DFLL_DVCO);
drivers/clk/tegra/clk-tegra114.c
1299
u32 v;
drivers/clk/tegra/clk-tegra114.c
1301
v = readl_relaxed(clk_base + RST_DFLL_DVCO);
drivers/clk/tegra/clk-tegra114.c
1302
v &= ~(1 << DVFS_DFLL_RESET_SHIFT);
drivers/clk/tegra/clk-tegra114.c
1303
writel_relaxed(v, clk_base + RST_DFLL_DVCO);
drivers/clk/tegra/clk-tegra124.c
1390
u32 v;
drivers/clk/tegra/clk-tegra124.c
1392
v = readl_relaxed(clk_base + RST_DFLL_DVCO);
drivers/clk/tegra/clk-tegra124.c
1393
v |= (1 << DVFS_DFLL_RESET_SHIFT);
drivers/clk/tegra/clk-tegra124.c
1394
writel_relaxed(v, clk_base + RST_DFLL_DVCO);
drivers/clk/tegra/clk-tegra124.c
1406
u32 v;
drivers/clk/tegra/clk-tegra124.c
1408
v = readl_relaxed(clk_base + RST_DFLL_DVCO);
drivers/clk/tegra/clk-tegra124.c
1409
v &= ~(1 << DVFS_DFLL_RESET_SHIFT);
drivers/clk/tegra/clk-tegra124.c
1410
writel_relaxed(v, clk_base + RST_DFLL_DVCO);
drivers/clk/tegra/clk-tegra210.c
3640
u32 v;
drivers/clk/tegra/clk-tegra210.c
3642
v = readl_relaxed(clk_base + RST_DFLL_DVCO);
drivers/clk/tegra/clk-tegra210.c
3643
v |= (1 << DVFS_DFLL_RESET_SHIFT);
drivers/clk/tegra/clk-tegra210.c
3644
writel_relaxed(v, clk_base + RST_DFLL_DVCO);
drivers/clk/tegra/clk-tegra210.c
3656
u32 v;
drivers/clk/tegra/clk-tegra210.c
3658
v = readl_relaxed(clk_base + RST_DFLL_DVCO);
drivers/clk/tegra/clk-tegra210.c
3659
v &= ~(1 << DVFS_DFLL_RESET_SHIFT);
drivers/clk/tegra/clk-tegra210.c
3660
writel_relaxed(v, clk_base + RST_DFLL_DVCO);
drivers/clk/ti/adpll.c
350
u32 v;
drivers/clk/ti/adpll.c
353
v = readl_relaxed(d->regs + ADPLL_CLKCTRL_OFFSET);
drivers/clk/ti/adpll.c
354
v |= BIT(ADPLL_CLKCTRL_IDLE);
drivers/clk/ti/adpll.c
355
writel_relaxed(v, d->regs + ADPLL_CLKCTRL_OFFSET);
drivers/clk/ti/adpll.c
362
u32 v;
drivers/clk/ti/adpll.c
365
v = readl_relaxed(d->regs + ADPLL_CLKCTRL_OFFSET);
drivers/clk/ti/adpll.c
366
v &= ~BIT(ADPLL_CLKCTRL_IDLE);
drivers/clk/ti/adpll.c
367
writel_relaxed(v, d->regs + ADPLL_CLKCTRL_OFFSET);
drivers/clk/ti/adpll.c
373
u32 v;
drivers/clk/ti/adpll.c
375
v = readl_relaxed(d->regs + ADPLL_STATUS_OFFSET);
drivers/clk/ti/adpll.c
377
return v & BIT(ADPLL_STATUS_BYPASS);
drivers/clk/ti/adpll.c
387
u32 v = readl_relaxed(d->regs + ADPLL_STATUS_OFFSET);
drivers/clk/ti/adpll.c
389
return (v & ADPLL_STATUS_PREPARED_MASK) == ADPLL_STATUS_PREPARED_MASK;
drivers/clk/ti/adpll.c
442
u32 frac_m, divider, v;
drivers/clk/ti/adpll.c
461
v = readl_relaxed(d->regs + ADPLL_CLKCTRL_OFFSET);
drivers/clk/ti/adpll.c
462
if (v & BIT(ADPLL_CLKCTRL_REGM4XEN_ADPLL_S))
drivers/clk/ti/adpll.c
780
u32 v;
drivers/clk/ti/adpll.c
782
v = readl_relaxed(reg);
drivers/clk/ti/adpll.c
783
if (v == ADPLL_PLLSS_MMR_LOCK_ENABLED)
drivers/clk/ti/apll.c
104
u32 v;
drivers/clk/ti/apll.c
108
v = ti_clk_ll_ops->clk_readl(&ad->control_reg);
drivers/clk/ti/apll.c
109
v &= ad->enable_mask;
drivers/clk/ti/apll.c
111
v >>= __ffs(ad->enable_mask);
drivers/clk/ti/apll.c
113
return v == APLL_AUTO_IDLE ? 0 : 1;
drivers/clk/ti/apll.c
239
u32 v;
drivers/clk/ti/apll.c
241
v = ti_clk_ll_ops->clk_readl(&ad->control_reg);
drivers/clk/ti/apll.c
242
v &= ad->enable_mask;
drivers/clk/ti/apll.c
244
v >>= __ffs(ad->enable_mask);
drivers/clk/ti/apll.c
246
return v == OMAP2_EN_APLL_LOCKED ? 1 : 0;
drivers/clk/ti/apll.c
264
u32 v;
drivers/clk/ti/apll.c
267
v = ti_clk_ll_ops->clk_readl(&ad->control_reg);
drivers/clk/ti/apll.c
268
v &= ~ad->enable_mask;
drivers/clk/ti/apll.c
269
v |= OMAP2_EN_APLL_LOCKED << __ffs(ad->enable_mask);
drivers/clk/ti/apll.c
270
ti_clk_ll_ops->clk_writel(v, &ad->control_reg);
drivers/clk/ti/apll.c
273
v = ti_clk_ll_ops->clk_readl(&ad->idlest_reg);
drivers/clk/ti/apll.c
274
if (v & ad->idlest_mask)
drivers/clk/ti/apll.c
295
u32 v;
drivers/clk/ti/apll.c
297
v = ti_clk_ll_ops->clk_readl(&ad->control_reg);
drivers/clk/ti/apll.c
298
v &= ~ad->enable_mask;
drivers/clk/ti/apll.c
299
v |= OMAP2_EN_APLL_STOPPED << __ffs(ad->enable_mask);
drivers/clk/ti/apll.c
300
ti_clk_ll_ops->clk_writel(v, &ad->control_reg);
drivers/clk/ti/apll.c
313
u32 v;
drivers/clk/ti/apll.c
315
v = ti_clk_ll_ops->clk_readl(&ad->autoidle_reg);
drivers/clk/ti/apll.c
316
v &= ~ad->autoidle_mask;
drivers/clk/ti/apll.c
317
v |= val << __ffs(ad->autoidle_mask);
drivers/clk/ti/apll.c
318
ti_clk_ll_ops->clk_writel(v, &ad->control_reg);
drivers/clk/ti/apll.c
39
u32 v;
drivers/clk/ti/apll.c
50
v = ti_clk_ll_ops->clk_readl(&ad->idlest_reg);
drivers/clk/ti/apll.c
52
if ((v & ad->idlest_mask) == state)
drivers/clk/ti/apll.c
55
v = ti_clk_ll_ops->clk_readl(&ad->control_reg);
drivers/clk/ti/apll.c
56
v &= ~ad->enable_mask;
drivers/clk/ti/apll.c
57
v |= APLL_FORCE_LOCK << __ffs(ad->enable_mask);
drivers/clk/ti/apll.c
58
ti_clk_ll_ops->clk_writel(v, &ad->control_reg);
drivers/clk/ti/apll.c
63
v = ti_clk_ll_ops->clk_readl(&ad->idlest_reg);
drivers/clk/ti/apll.c
64
if ((v & ad->idlest_mask) == state)
drivers/clk/ti/apll.c
88
u32 v;
drivers/clk/ti/apll.c
94
v = ti_clk_ll_ops->clk_readl(&ad->control_reg);
drivers/clk/ti/apll.c
95
v &= ~ad->enable_mask;
drivers/clk/ti/apll.c
96
v |= APLL_AUTO_IDLE << __ffs(ad->enable_mask);
drivers/clk/ti/apll.c
97
ti_clk_ll_ops->clk_writel(v, &ad->control_reg);
drivers/clk/ti/clk.c
57
u32 v;
drivers/clk/ti/clk.c
59
v = readl_relaxed(ptr);
drivers/clk/ti/clk.c
60
v &= ~mask;
drivers/clk/ti/clk.c
61
v |= val;
drivers/clk/ti/clk.c
62
writel_relaxed(v, ptr);
drivers/clk/ti/clkt_dflt.c
197
u32 v;
drivers/clk/ti/clkt_dflt.c
220
v = ti_clk_ll_ops->clk_readl(&clk->enable_reg);
drivers/clk/ti/clkt_dflt.c
222
v &= ~(1 << clk->enable_bit);
drivers/clk/ti/clkt_dflt.c
224
v |= (1 << clk->enable_bit);
drivers/clk/ti/clkt_dflt.c
225
ti_clk_ll_ops->clk_writel(v, &clk->enable_reg);
drivers/clk/ti/clkt_dflt.c
226
v = ti_clk_ll_ops->clk_readl(&clk->enable_reg); /* OCP barrier */
drivers/clk/ti/clkt_dflt.c
246
u32 v;
drivers/clk/ti/clkt_dflt.c
250
v = ti_clk_ll_ops->clk_readl(&clk->enable_reg);
drivers/clk/ti/clkt_dflt.c
252
v |= (1 << clk->enable_bit);
drivers/clk/ti/clkt_dflt.c
254
v &= ~(1 << clk->enable_bit);
drivers/clk/ti/clkt_dflt.c
255
ti_clk_ll_ops->clk_writel(v, &clk->enable_reg);
drivers/clk/ti/clkt_dflt.c
274
u32 v;
drivers/clk/ti/clkt_dflt.c
276
v = ti_clk_ll_ops->clk_readl(&clk->enable_reg);
drivers/clk/ti/clkt_dflt.c
279
v ^= BIT(clk->enable_bit);
drivers/clk/ti/clkt_dflt.c
281
v &= BIT(clk->enable_bit);
drivers/clk/ti/clkt_dflt.c
283
return v ? 1 : 0;
drivers/clk/ti/clkt_dpll.c
181
static int _omap2_dpll_is_in_bypass(u32 v)
drivers/clk/ti/clkt_dpll.c
195
if (v == val)
drivers/clk/ti/clkt_dpll.c
206
u32 v;
drivers/clk/ti/clkt_dpll.c
213
v = ti_clk_ll_ops->clk_readl(&dd->control_reg);
drivers/clk/ti/clkt_dpll.c
214
v &= dd->enable_mask;
drivers/clk/ti/clkt_dpll.c
215
v >>= __ffs(dd->enable_mask);
drivers/clk/ti/clkt_dpll.c
218
if (_omap2_dpll_is_in_bypass(v))
drivers/clk/ti/clkt_dpll.c
241
u32 dpll_mult, dpll_div, v;
drivers/clk/ti/clkt_dpll.c
249
v = ti_clk_ll_ops->clk_readl(&dd->control_reg);
drivers/clk/ti/clkt_dpll.c
250
v &= dd->enable_mask;
drivers/clk/ti/clkt_dpll.c
251
v >>= __ffs(dd->enable_mask);
drivers/clk/ti/clkt_dpll.c
253
if (_omap2_dpll_is_in_bypass(v))
drivers/clk/ti/clkt_dpll.c
256
v = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg);
drivers/clk/ti/clkt_dpll.c
257
dpll_mult = v & dd->mult_mask;
drivers/clk/ti/clkt_dpll.c
259
dpll_div = v & dd->div1_mask;
drivers/clk/ti/clkt_iclk.c
30
u32 v;
drivers/clk/ti/clkt_iclk.c
36
v = ti_clk_ll_ops->clk_readl(&r);
drivers/clk/ti/clkt_iclk.c
37
v |= (1 << clk->enable_bit);
drivers/clk/ti/clkt_iclk.c
38
ti_clk_ll_ops->clk_writel(v, &r);
drivers/clk/ti/clkt_iclk.c
44
u32 v;
drivers/clk/ti/clkt_iclk.c
51
v = ti_clk_ll_ops->clk_readl(&r);
drivers/clk/ti/clkt_iclk.c
52
v &= ~(1 << clk->enable_bit);
drivers/clk/ti/clkt_iclk.c
53
ti_clk_ll_ops->clk_writel(v, &r);
drivers/clk/ti/dpll3xxx.c
305
u32 v, ctrl, mod_freq_divider, exponent, mantissa;
drivers/clk/ti/dpll3xxx.c
334
v = ti_clk_ll_ops->clk_readl(&dd->ssc_modfreq_reg);
drivers/clk/ti/dpll3xxx.c
335
v &= ~(dd->ssc_modfreq_mant_mask | dd->ssc_modfreq_exp_mask);
drivers/clk/ti/dpll3xxx.c
336
v |= mantissa << __ffs(dd->ssc_modfreq_mant_mask);
drivers/clk/ti/dpll3xxx.c
337
v |= exponent << __ffs(dd->ssc_modfreq_exp_mask);
drivers/clk/ti/dpll3xxx.c
338
ti_clk_ll_ops->clk_writel(v, &dd->ssc_modfreq_reg);
drivers/clk/ti/dpll3xxx.c
364
v = ti_clk_ll_ops->clk_readl(&dd->ssc_deltam_reg);
drivers/clk/ti/dpll3xxx.c
365
v &= ~(dd->ssc_deltam_int_mask | dd->ssc_deltam_frac_mask);
drivers/clk/ti/dpll3xxx.c
366
v |= deltam_step << __ffs(dd->ssc_deltam_int_mask |
drivers/clk/ti/dpll3xxx.c
368
ti_clk_ll_ops->clk_writel(v, &dd->ssc_deltam_reg);
drivers/clk/ti/dpll3xxx.c
388
u32 v;
drivers/clk/ti/dpll3xxx.c
399
v = ti_clk_ll_ops->clk_readl(&dd->control_reg);
drivers/clk/ti/dpll3xxx.c
400
v &= ~dd->freqsel_mask;
drivers/clk/ti/dpll3xxx.c
401
v |= freqsel << __ffs(dd->freqsel_mask);
drivers/clk/ti/dpll3xxx.c
402
ti_clk_ll_ops->clk_writel(v, &dd->control_reg);
drivers/clk/ti/dpll3xxx.c
406
v = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg);
drivers/clk/ti/dpll3xxx.c
411
v |= dd->dcc_mask; /* Enable DCC */
drivers/clk/ti/dpll3xxx.c
413
v &= ~dd->dcc_mask; /* Disable DCC */
drivers/clk/ti/dpll3xxx.c
416
v &= ~(dd->mult_mask | dd->div1_mask);
drivers/clk/ti/dpll3xxx.c
417
v |= dd->last_rounded_m << __ffs(dd->mult_mask);
drivers/clk/ti/dpll3xxx.c
418
v |= (dd->last_rounded_n - 1) << __ffs(dd->div1_mask);
drivers/clk/ti/dpll3xxx.c
423
v &= ~(dd->dco_mask);
drivers/clk/ti/dpll3xxx.c
424
v |= dco << __ffs(dd->dco_mask);
drivers/clk/ti/dpll3xxx.c
429
v &= ~(dd->sddiv_mask);
drivers/clk/ti/dpll3xxx.c
430
v |= sd_div << __ffs(dd->sddiv_mask);
drivers/clk/ti/dpll3xxx.c
452
ti_clk_ll_ops->clk_writel(v, &dd->mult_div1_reg);
drivers/clk/ti/dpll3xxx.c
456
v = ti_clk_ll_ops->clk_readl(&dd->control_reg);
drivers/clk/ti/dpll3xxx.c
460
v |= dd->m4xen_mask;
drivers/clk/ti/dpll3xxx.c
462
v &= ~dd->m4xen_mask;
drivers/clk/ti/dpll3xxx.c
467
v |= dd->lpmode_mask;
drivers/clk/ti/dpll3xxx.c
469
v &= ~dd->lpmode_mask;
drivers/clk/ti/dpll3xxx.c
472
ti_clk_ll_ops->clk_writel(v, &dd->control_reg);
drivers/clk/ti/dpll3xxx.c
50
u32 v;
drivers/clk/ti/dpll3xxx.c
54
v = ti_clk_ll_ops->clk_readl(&dd->control_reg);
drivers/clk/ti/dpll3xxx.c
55
v &= ~dd->enable_mask;
drivers/clk/ti/dpll3xxx.c
56
v |= clken_bits << __ffs(dd->enable_mask);
drivers/clk/ti/dpll3xxx.c
57
ti_clk_ll_ops->clk_writel(v, &dd->control_reg);
drivers/clk/ti/dpll3xxx.c
734
u32 v;
drivers/clk/ti/dpll3xxx.c
744
v = ti_clk_ll_ops->clk_readl(&dd->autoidle_reg);
drivers/clk/ti/dpll3xxx.c
745
v &= dd->autoidle_mask;
drivers/clk/ti/dpll3xxx.c
746
v >>= __ffs(dd->autoidle_mask);
drivers/clk/ti/dpll3xxx.c
748
return v;
drivers/clk/ti/dpll3xxx.c
763
u32 v;
drivers/clk/ti/dpll3xxx.c
778
v = ti_clk_ll_ops->clk_readl(&dd->autoidle_reg);
drivers/clk/ti/dpll3xxx.c
779
v &= ~dd->autoidle_mask;
drivers/clk/ti/dpll3xxx.c
780
v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask);
drivers/clk/ti/dpll3xxx.c
781
ti_clk_ll_ops->clk_writel(v, &dd->autoidle_reg);
drivers/clk/ti/dpll3xxx.c
793
u32 v;
drivers/clk/ti/dpll3xxx.c
803
v = ti_clk_ll_ops->clk_readl(&dd->autoidle_reg);
drivers/clk/ti/dpll3xxx.c
804
v &= ~dd->autoidle_mask;
drivers/clk/ti/dpll3xxx.c
805
v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask);
drivers/clk/ti/dpll3xxx.c
806
ti_clk_ll_ops->clk_writel(v, &dd->autoidle_reg);
drivers/clk/ti/dpll3xxx.c
848
u32 v;
drivers/clk/ti/dpll3xxx.c
863
v = ti_clk_ll_ops->clk_readl(&dd->control_reg) & dd->enable_mask;
drivers/clk/ti/dpll3xxx.c
864
v >>= __ffs(dd->enable_mask);
drivers/clk/ti/dpll3xxx.c
865
if ((v != OMAP3XXX_EN_DPLL_LOCKED) || (dd->flags & DPLL_J_TYPE))
drivers/clk/ti/dpll3xxx.c
883
u32 v;
drivers/clk/ti/dpll3xxx.c
887
v = ti_clk_ll_ops->clk_readl(&dd->control_reg);
drivers/clk/ti/dpll3xxx.c
888
clk->context = (v & dd->enable_mask) >> __ffs(dd->enable_mask);
drivers/clk/ti/dpll3xxx.c
891
v = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg);
drivers/clk/ti/dpll3xxx.c
892
dd->last_rounded_m = (v & dd->mult_mask) >>
drivers/clk/ti/dpll3xxx.c
894
dd->last_rounded_n = ((v & dd->div1_mask) >>
drivers/clk/ti/dpll3xxx.c
912
u32 v;
drivers/clk/ti/dpll3xxx.c
920
v = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg);
drivers/clk/ti/dpll3xxx.c
921
v &= ~(dd->mult_mask | dd->div1_mask);
drivers/clk/ti/dpll3xxx.c
922
v |= dd->last_rounded_m << __ffs(dd->mult_mask);
drivers/clk/ti/dpll3xxx.c
923
v |= (dd->last_rounded_n - 1) << __ffs(dd->div1_mask);
drivers/clk/ti/dpll3xxx.c
924
ti_clk_ll_ops->clk_writel(v, &dd->mult_div1_reg);
drivers/clk/ti/dpll3xxx.c
944
u32 v;
drivers/clk/ti/dpll3xxx.c
948
v = ti_clk_ll_ops->clk_readl(&dd->control_reg);
drivers/clk/ti/dpll3xxx.c
949
clk->context = (v & dd->enable_mask) >> __ffs(dd->enable_mask);
drivers/clk/ti/dpll3xxx.c
952
v = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg);
drivers/clk/ti/dpll3xxx.c
953
dd->last_rounded_m = (v & dd->mult_mask) >>
drivers/clk/ti/dpll3xxx.c
955
dd->last_rounded_n = ((v & dd->div1_mask) >>
drivers/clk/ti/dpll44xx.c
117
u32 v;
drivers/clk/ti/dpll44xx.c
129
v = ti_clk_ll_ops->clk_readl(&dd->control_reg);
drivers/clk/ti/dpll44xx.c
130
if (v & OMAP4430_DPLL_REGM4XEN_MASK)
drivers/clk/ti/dpll44xx.c
39
u32 v;
drivers/clk/ti/dpll44xx.c
49
v = ti_clk_ll_ops->clk_readl(&clk->clksel_reg);
drivers/clk/ti/dpll44xx.c
51
v &= ~mask;
drivers/clk/ti/dpll44xx.c
52
ti_clk_ll_ops->clk_writel(v, &clk->clksel_reg);
drivers/clk/ti/dpll44xx.c
57
u32 v;
drivers/clk/ti/dpll44xx.c
67
v = ti_clk_ll_ops->clk_readl(&clk->clksel_reg);
drivers/clk/ti/dpll44xx.c
69
v |= mask;
drivers/clk/ti/dpll44xx.c
70
ti_clk_ll_ops->clk_writel(v, &clk->clksel_reg);
drivers/clk/ti/fapll.c
102
u32 v = readl_relaxed(fd->base);
drivers/clk/ti/fapll.c
105
v |= FAPLL_MAIN_BP;
drivers/clk/ti/fapll.c
107
v &= ~FAPLL_MAIN_BP;
drivers/clk/ti/fapll.c
108
writel_relaxed(v, fd->base);
drivers/clk/ti/fapll.c
114
u32 v;
drivers/clk/ti/fapll.c
116
while ((v = readl_relaxed(fd->base))) {
drivers/clk/ti/fapll.c
117
if (v & FAPLL_MAIN_LOCK)
drivers/clk/ti/fapll.c
134
u32 v = readl_relaxed(fd->base);
drivers/clk/ti/fapll.c
136
v |= FAPLL_MAIN_PLLEN;
drivers/clk/ti/fapll.c
137
writel_relaxed(v, fd->base);
drivers/clk/ti/fapll.c
146
u32 v = readl_relaxed(fd->base);
drivers/clk/ti/fapll.c
148
v &= ~FAPLL_MAIN_PLLEN;
drivers/clk/ti/fapll.c
149
writel_relaxed(v, fd->base);
drivers/clk/ti/fapll.c
155
u32 v = readl_relaxed(fd->base);
drivers/clk/ti/fapll.c
157
return v & FAPLL_MAIN_PLLEN;
drivers/clk/ti/fapll.c
164
u32 fapll_n, fapll_p, v;
drivers/clk/ti/fapll.c
173
v = readl_relaxed(fd->base);
drivers/clk/ti/fapll.c
174
fapll_p = (v >> 8) & 0xff;
drivers/clk/ti/fapll.c
177
fapll_n = v >> 16;
drivers/clk/ti/fapll.c
244
u32 pre_div_p, mult_n, v;
drivers/clk/ti/fapll.c
256
v = readl_relaxed(fd->base);
drivers/clk/ti/fapll.c
257
v &= ~FAPLL_MAIN_CLEAR_MASK;
drivers/clk/ti/fapll.c
258
v |= pre_div_p << FAPLL_MAIN_DIV_P_SHIFT;
drivers/clk/ti/fapll.c
259
v |= mult_n << FAPLL_MAIN_MULT_N_SHIFT;
drivers/clk/ti/fapll.c
260
writel_relaxed(v, fd->base);
drivers/clk/ti/fapll.c
281
u32 v = readl_relaxed(synth->fd->base + FAPLL_PWD_OFFSET);
drivers/clk/ti/fapll.c
283
v &= ~(1 << synth->index);
drivers/clk/ti/fapll.c
284
writel_relaxed(v, synth->fd->base + FAPLL_PWD_OFFSET);
drivers/clk/ti/fapll.c
292
u32 v = readl_relaxed(synth->fd->base + FAPLL_PWD_OFFSET);
drivers/clk/ti/fapll.c
294
v |= 1 << synth->index;
drivers/clk/ti/fapll.c
295
writel_relaxed(v, synth->fd->base + FAPLL_PWD_OFFSET);
drivers/clk/ti/fapll.c
301
u32 v = readl_relaxed(synth->fd->base + FAPLL_PWD_OFFSET);
drivers/clk/ti/fapll.c
303
return !(v & (1 << synth->index));
drivers/clk/ti/fapll.c
336
u32 v, synth_int_div, synth_frac_div, synth_div_freq;
drivers/clk/ti/fapll.c
338
v = readl_relaxed(synth->freq);
drivers/clk/ti/fapll.c
339
synth_int_div = (v >> 24) & 0xf;
drivers/clk/ti/fapll.c
340
synth_frac_div = v & 0xffffff;
drivers/clk/ti/fapll.c
371
u32 post_div_m, synth_int_div = 0, synth_frac_div = 0, v;
drivers/clk/ti/fapll.c
395
v = readl_relaxed(synth->freq);
drivers/clk/ti/fapll.c
396
v &= ~0x1fffffff;
drivers/clk/ti/fapll.c
397
v |= (synth_int_div & SYNTH_MAX_INT_DIV) << 24;
drivers/clk/ti/fapll.c
398
v |= (synth_frac_div & 0xffffff);
drivers/clk/ti/fapll.c
399
v |= SYNTH_LDFREQ;
drivers/clk/ti/fapll.c
400
writel_relaxed(v, synth->freq);
drivers/clk/ti/fapll.c
448
u32 post_div_m = 0, v;
drivers/clk/ti/fapll.c
472
v = readl_relaxed(synth->div);
drivers/clk/ti/fapll.c
473
v &= ~SYNTH_MAX_DIV_M;
drivers/clk/ti/fapll.c
474
v |= post_div_m;
drivers/clk/ti/fapll.c
475
v |= SYNTH_LDMDIV1;
drivers/clk/ti/fapll.c
476
writel_relaxed(v, synth->div);
drivers/clk/ti/fapll.c
618
u32 v;
drivers/clk/ti/fapll.c
637
v = readl_relaxed(freq);
drivers/clk/ti/fapll.c
638
if (!v)
drivers/clk/ti/fapll.c
81
u32 v = readl_relaxed(fd->base);
drivers/clk/ti/fapll.c
84
return !(v & FAPLL_MAIN_BP);
drivers/clk/ti/fapll.c
86
return !!(v & FAPLL_MAIN_BP);
drivers/clk/ti/fapll.c
91
u32 v = readl_relaxed(fd->base);
drivers/clk/ti/fapll.c
94
v &= ~FAPLL_MAIN_BP;
drivers/clk/ti/fapll.c
96
v |= FAPLL_MAIN_BP;
drivers/clk/ti/fapll.c
97
writel_relaxed(v, fd->base);
drivers/clk/versatile/clk-icst.c
113
vco->v = divxy ? 17 : 14;
drivers/clk/versatile/clk-icst.c
128
vco->v = val & 0xFF;
drivers/clk/versatile/clk-icst.c
135
vco->v = (val >> 12) & 0xFF;
drivers/clk/versatile/clk-icst.c
141
vco->v = val & 0x1ff;
drivers/clk/versatile/clk-icst.c
162
val = vco.v & 0xFF;
drivers/clk/versatile/clk-icst.c
163
if (vco.v & 0x100)
drivers/clk/versatile/clk-icst.c
172
val = vco.v & 0xFF;
drivers/clk/versatile/clk-icst.c
173
if (vco.v & 0x100)
drivers/clk/versatile/clk-icst.c
182
val = (vco.v & 0xFF) | vco.s << 8;
drivers/clk/versatile/clk-icst.c
183
if (vco.v & 0x100)
drivers/clk/versatile/clk-icst.c
190
val = ((vco.v & 0xFF) << 12) | (vco.s << 20);
drivers/clk/versatile/clk-icst.c
191
if (vco.v & 0x100)
drivers/clk/versatile/clk-icst.c
199
val = vco.v | (vco.r << 9) | (vco.s << 16);
drivers/clk/versatile/clk-icst.c
81
vco->v = val & INTEGRATOR_AP_CM_BITS;
drivers/clk/versatile/clk-icst.c
96
vco->v = val & INTEGRATOR_AP_SYS_BITS;
drivers/clk/versatile/icst.c
29
u64 dividend = p->ref * 2 * (u64)(vco.v + 8);
drivers/clk/versatile/icst.c
49
struct icst_vco vco = { .s = 1, .v = p->vd_max, .r = p->rd_max };
drivers/clk/versatile/icst.c
91
vco.v = vd - 8;
drivers/clk/versatile/icst.h
25
unsigned short v;
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
27
#define WZRD_CLK_CFG_REG(v, n) (0x200 + 0x130 * (v) + 4 * (n))
drivers/clocksource/timer-ti-dm.c
326
unsigned long cmd, void *v)
drivers/comedi/drivers/comedi_8255.c
73
unsigned int v;
drivers/comedi/drivers/comedi_8255.c
88
v = spriv->io(dev, 0, I8255_DATA_A_REG, 0, context);
drivers/comedi/drivers/comedi_8255.c
89
v |= (spriv->io(dev, 0, I8255_DATA_B_REG, 0, context) << 8);
drivers/comedi/drivers/comedi_8255.c
90
v |= (spriv->io(dev, 0, I8255_DATA_C_REG, 0, context) << 16);
drivers/comedi/drivers/comedi_8255.c
92
data[1] = v;
drivers/comedi/drivers/plx9080.h
248
#define PLX_DMPBAM_TO_PAFL(v) ((((BIT(10) & (v)) >> 1) | \
drivers/comedi/drivers/plx9080.h
249
(GENMASK(8, 5) & (v))) >> 5)
drivers/comedi/drivers/s626.h
613
#define S626_UNMAKE(v, w, p) (((v) >> (p)) & ((1 << (w)) - 1))
drivers/comedi/drivers/s626.h
669
#define S626_GET_CRA_INDXSRC_B(v) \
drivers/comedi/drivers/s626.h
670
S626_UNMAKE((v), S626_CRAWID_INDXSRC_B, S626_CRABIT_INDXSRC_B)
drivers/comedi/drivers/s626.h
671
#define S626_GET_CRA_CNTSRC_B(v) \
drivers/comedi/drivers/s626.h
672
S626_UNMAKE((v), S626_CRAWID_CNTSRC_B, S626_CRABIT_CNTSRC_B)
drivers/comedi/drivers/s626.h
673
#define S626_GET_CRA_INDXPOL_A(v) \
drivers/comedi/drivers/s626.h
674
S626_UNMAKE((v), S626_CRAWID_INDXPOL_A, S626_CRABIT_INDXPOL_A)
drivers/comedi/drivers/s626.h
675
#define S626_GET_CRA_LOADSRC_A(v) \
drivers/comedi/drivers/s626.h
676
S626_UNMAKE((v), S626_CRAWID_LOADSRC_A, S626_CRABIT_LOADSRC_A)
drivers/comedi/drivers/s626.h
677
#define S626_GET_CRA_CLKMULT_A(v) \
drivers/comedi/drivers/s626.h
678
S626_UNMAKE((v), S626_CRAWID_CLKMULT_A, S626_CRABIT_CLKMULT_A)
drivers/comedi/drivers/s626.h
679
#define S626_GET_CRA_INTSRC_A(v) \
drivers/comedi/drivers/s626.h
680
S626_UNMAKE((v), S626_CRAWID_INTSRC_A, S626_CRABIT_INTSRC_A)
drivers/comedi/drivers/s626.h
681
#define S626_GET_CRA_CLKPOL_A(v) \
drivers/comedi/drivers/s626.h
682
S626_UNMAKE((v), S626_CRAWID_CLKPOL_A, S626_CRABIT_CLKPOL_A)
drivers/comedi/drivers/s626.h
683
#define S626_GET_CRA_INDXSRC_A(v) \
drivers/comedi/drivers/s626.h
684
S626_UNMAKE((v), S626_CRAWID_INDXSRC_A, S626_CRABIT_INDXSRC_A)
drivers/comedi/drivers/s626.h
685
#define S626_GET_CRA_CNTSRC_A(v) \
drivers/comedi/drivers/s626.h
686
S626_UNMAKE((v), S626_CRAWID_CNTSRC_A, S626_CRABIT_CNTSRC_A)
drivers/comedi/drivers/s626.h
771
#define S626_GET_CRB_CNTDIR_B(v) \
drivers/comedi/drivers/s626.h
772
S626_UNMAKE((v), S626_CRBWID_CNTDIR_B, S626_CRBBIT_CNTDIR_B)
drivers/comedi/drivers/s626.h
773
#define S626_GET_CRB_OVERDO_A(v) \
drivers/comedi/drivers/s626.h
774
S626_UNMAKE((v), S626_CRBWID_OVERDO_A, S626_CRBBIT_OVERDO_A)
drivers/comedi/drivers/s626.h
775
#define S626_GET_CRB_OVERDO_B(v) \
drivers/comedi/drivers/s626.h
776
S626_UNMAKE((v), S626_CRBWID_OVERDO_B, S626_CRBBIT_OVERDO_B)
drivers/comedi/drivers/s626.h
777
#define S626_GET_CRB_CLKENAB_A(v) \
drivers/comedi/drivers/s626.h
778
S626_UNMAKE((v), S626_CRBWID_CLKENAB_A, S626_CRBBIT_CLKENAB_A)
drivers/comedi/drivers/s626.h
779
#define S626_GET_CRB_INTSRC_B(v) \
drivers/comedi/drivers/s626.h
780
S626_UNMAKE((v), S626_CRBWID_INTSRC_B, S626_CRBBIT_INTSRC_B)
drivers/comedi/drivers/s626.h
781
#define S626_GET_CRB_LATCHSRC(v) \
drivers/comedi/drivers/s626.h
782
S626_UNMAKE((v), S626_CRBWID_LATCHSRC, S626_CRBBIT_LATCHSRC)
drivers/comedi/drivers/s626.h
783
#define S626_GET_CRB_LOADSRC_B(v) \
drivers/comedi/drivers/s626.h
784
S626_UNMAKE((v), S626_CRBWID_LOADSRC_B, S626_CRBBIT_LOADSRC_B)
drivers/comedi/drivers/s626.h
785
#define S626_GET_CRB_CLEAR_B(v) \
drivers/comedi/drivers/s626.h
786
S626_UNMAKE((v), S626_CRBWID_CLEAR_B, S626_CRBBIT_CLEAR_B)
drivers/comedi/drivers/s626.h
787
#define S626_GET_CRB_CLKMULT_B(v) \
drivers/comedi/drivers/s626.h
788
S626_UNMAKE((v), S626_CRBWID_CLKMULT_B, S626_CRBBIT_CLKMULT_B)
drivers/comedi/drivers/s626.h
789
#define S626_GET_CRB_CLKENAB_B(v) \
drivers/comedi/drivers/s626.h
790
S626_UNMAKE((v), S626_CRBWID_CLKENAB_B, S626_CRBBIT_CLKENAB_B)
drivers/comedi/drivers/s626.h
791
#define S626_GET_CRB_INDXPOL_B(v) \
drivers/comedi/drivers/s626.h
792
S626_UNMAKE((v), S626_CRBWID_INDXPOL_B, S626_CRBBIT_INDXPOL_B)
drivers/comedi/drivers/s626.h
793
#define S626_GET_CRB_CLKPOL_B(v) \
drivers/comedi/drivers/s626.h
794
S626_UNMAKE((v), S626_CRBWID_CLKPOL_B, S626_CRBBIT_CLKPOL_B)
drivers/comedi/drivers/s626.h
850
#define S626_GET_STD_INTSRC(v) \
drivers/comedi/drivers/s626.h
851
S626_UNMAKE((v), S626_STDWID_INTSRC, S626_STDBIT_INTSRC)
drivers/comedi/drivers/s626.h
852
#define S626_GET_STD_LATCHSRC(v) \
drivers/comedi/drivers/s626.h
853
S626_UNMAKE((v), S626_STDWID_LATCHSRC, S626_STDBIT_LATCHSRC)
drivers/comedi/drivers/s626.h
854
#define S626_GET_STD_LOADSRC(v) \
drivers/comedi/drivers/s626.h
855
S626_UNMAKE((v), S626_STDWID_LOADSRC, S626_STDBIT_LOADSRC)
drivers/comedi/drivers/s626.h
856
#define S626_GET_STD_INDXSRC(v) \
drivers/comedi/drivers/s626.h
857
S626_UNMAKE((v), S626_STDWID_INDXSRC, S626_STDBIT_INDXSRC)
drivers/comedi/drivers/s626.h
858
#define S626_GET_STD_INDXPOL(v) \
drivers/comedi/drivers/s626.h
859
S626_UNMAKE((v), S626_STDWID_INDXPOL, S626_STDBIT_INDXPOL)
drivers/comedi/drivers/s626.h
860
#define S626_GET_STD_ENCMODE(v) \
drivers/comedi/drivers/s626.h
861
S626_UNMAKE((v), S626_STDWID_ENCMODE, S626_STDBIT_ENCMODE)
drivers/comedi/drivers/s626.h
862
#define S626_GET_STD_CLKPOL(v) \
drivers/comedi/drivers/s626.h
863
S626_UNMAKE((v), S626_STDWID_CLKPOL, S626_STDBIT_CLKPOL)
drivers/comedi/drivers/s626.h
864
#define S626_GET_STD_CLKMULT(v) \
drivers/comedi/drivers/s626.h
865
S626_UNMAKE((v), S626_STDWID_CLKMULT, S626_STDBIT_CLKMULT)
drivers/comedi/drivers/s626.h
866
#define S626_GET_STD_CLKENAB(v) \
drivers/comedi/drivers/s626.h
867
S626_UNMAKE((v), S626_STDWID_CLKENAB, S626_STDBIT_CLKENAB)
drivers/comedi/proc.c
21
static int comedi_read(struct seq_file *m, void *v)
drivers/connector/connector.c
253
static int __maybe_unused cn_proc_show(struct seq_file *m, void *v)
drivers/cpufreq/e_powersaver.c
305
u32 v;
drivers/cpufreq/e_powersaver.c
308
v = (set_max_voltage - 700) / 16;
drivers/cpufreq/e_powersaver.c
310
if (v >= min_voltage && v <= max_voltage) {
drivers/cpufreq/e_powersaver.c
311
pr_info("Setting %dmV as maximum\n", v * 16 + 700);
drivers/cpufreq/e_powersaver.c
312
max_voltage = v;
drivers/cpufreq/s3c64xx-cpufreq.c
110
int count, v, i, found;
drivers/cpufreq/s3c64xx-cpufreq.c
127
v = regulator_list_voltage(vddarm, i);
drivers/cpufreq/s3c64xx-cpufreq.c
128
if (v >= dvfs->vddarm_min && v <= dvfs->vddarm_max)
drivers/crypto/allwinner/sun4i-ss/sun4i-ss-cipher.c
192
u32 v;
drivers/crypto/allwinner/sun4i-ss/sun4i-ss-cipher.c
259
v = *(u32 *)(areq->iv + i * 4);
drivers/crypto/allwinner/sun4i-ss/sun4i-ss-cipher.c
260
writesl(ss->base + SS_IV0 + i * 4, &v, 1);
drivers/crypto/allwinner/sun4i-ss/sun4i-ss-cipher.c
27
u32 v;
drivers/crypto/allwinner/sun4i-ss/sun4i-ss-cipher.c
67
v = *(u32 *)(areq->iv + i * 4);
drivers/crypto/allwinner/sun4i-ss/sun4i-ss-cipher.c
68
writesl(ss->base + SS_IV0 + i * 4, &v, 1);
drivers/crypto/allwinner/sun4i-ss/sun4i-ss-core.c
235
static int sun4i_ss_debugfs_show(struct seq_file *seq, void *v)
drivers/crypto/allwinner/sun4i-ss/sun4i-ss-core.c
343
u32 v;
drivers/crypto/allwinner/sun4i-ss/sun4i-ss-core.c
447
v = readl(ss->base + SS_CTL);
drivers/crypto/allwinner/sun4i-ss/sun4i-ss-core.c
448
v >>= 16;
drivers/crypto/allwinner/sun4i-ss/sun4i-ss-core.c
449
v &= 0x07;
drivers/crypto/allwinner/sun4i-ss/sun4i-ss-core.c
450
dev_info(&pdev->dev, "Die ID %d\n", v);
drivers/crypto/allwinner/sun4i-ss/sun4i-ss-hash.c
191
u32 spaces, rx_cnt = SS_RX_DEFAULT, bf[32] = {0}, v, ivmode = 0;
drivers/crypto/allwinner/sun4i-ss/sun4i-ss-hash.c
365
v = readl(ss->base + SS_CTL);
drivers/crypto/allwinner/sun4i-ss/sun4i-ss-hash.c
367
} while (i < SS_TIMEOUT && (v & SS_DATA_END));
drivers/crypto/allwinner/sun4i-ss/sun4i-ss-hash.c
371
i, SS_TIMEOUT, v, areq->nbytes);
drivers/crypto/allwinner/sun4i-ss/sun4i-ss-hash.c
466
v = readl(ss->base + SS_CTL);
drivers/crypto/allwinner/sun4i-ss/sun4i-ss-hash.c
468
} while (i < SS_TIMEOUT && (v & SS_DATA_END));
drivers/crypto/allwinner/sun4i-ss/sun4i-ss-hash.c
472
i, SS_TIMEOUT, v, areq->nbytes);
drivers/crypto/allwinner/sun4i-ss/sun4i-ss-hash.c
489
v = readl(ss->base + SS_MD0 + i * 4);
drivers/crypto/allwinner/sun4i-ss/sun4i-ss-hash.c
491
put_unaligned_le32(v, areq->result + i * 4);
drivers/crypto/allwinner/sun4i-ss/sun4i-ss-hash.c
493
put_unaligned_be32(v, areq->result + i * 4);
drivers/crypto/allwinner/sun4i-ss/sun4i-ss-hash.c
497
v = readl(ss->base + SS_MD0 + i * 4);
drivers/crypto/allwinner/sun4i-ss/sun4i-ss-hash.c
498
put_unaligned_le32(v, areq->result + i * 4);
drivers/crypto/allwinner/sun4i-ss/sun4i-ss-prng.c
22
u32 v;
drivers/crypto/allwinner/sun4i-ss/sun4i-ss-prng.c
58
v = readl(ss->base + SS_KEY0 + i * 4);
drivers/crypto/allwinner/sun4i-ss/sun4i-ss-prng.c
59
ss->seed[i] = v;
drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c
1047
v = readl(ce->base + CE_CTR);
drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c
1048
v >>= CE_DIE_ID_SHIFT;
drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c
1049
v &= CE_DIE_ID_MASK;
drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c
1050
dev_info(&pdev->dev, "CryptoEngine Die ID %x\n", v);
drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c
190
u32 v;
drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c
199
v = readl(ce->base + CE_ICR);
drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c
200
v |= 1 << flow;
drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c
201
writel(v, ce->base + CE_ICR);
drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c
213
v = 1 | ((le32_to_cpu(ce->chanlist[flow].tl->t_common_ctl) & 0x7F) << 8);
drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c
214
writel(v, ce->base + CE_TLR);
drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c
227
v = readl(ce->base + CE_ESR);
drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c
231
if (v) {
drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c
232
dev_err(ce->dev, "CE ERROR: %x for flow %x\n", v, flow);
drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c
236
if (v & CE_ERR_ALGO_NOTSUP)
drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c
238
if (v & CE_ERR_DATALEN)
drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c
240
if (v & CE_ERR_KEYSRAM)
drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c
247
v >>= (flow * 4);
drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c
248
v &= 0xF;
drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c
249
if (v) {
drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c
250
dev_err(ce->dev, "CE ERROR: %x for flow %x\n", v, flow);
drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c
254
if (v & CE_ERR_ALGO_NOTSUP)
drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c
256
if (v & CE_ERR_DATALEN)
drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c
258
if (v & CE_ERR_KEYSRAM)
drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c
262
v >>= (flow * 8);
drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c
263
v &= 0xFF;
drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c
264
if (v) {
drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c
265
dev_err(ce->dev, "CE ERROR: %x for flow %x\n", v, flow);
drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c
269
if (v & CE_ERR_ALGO_NOTSUP)
drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c
271
if (v & CE_ERR_DATALEN)
drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c
273
if (v & CE_ERR_KEYSRAM)
drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c
275
if (v & CE_ERR_ADDR_INVALID)
drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c
277
if (v & CE_ERR_KEYLADDER)
drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c
638
static int sun8i_ce_debugfs_show(struct seq_file *seq, void *v)
drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c
984
u32 v;
drivers/crypto/allwinner/sun8i-ss/sun8i-ss-core.c
123
i, flow, name, v,
drivers/crypto/allwinner/sun8i-ss/sun8i-ss-core.c
136
writel(v, ss->base + SS_CTL_REG);
drivers/crypto/allwinner/sun8i-ss/sun8i-ss-core.c
470
static int sun8i_ss_debugfs_show(struct seq_file *seq, void *v)
drivers/crypto/allwinner/sun8i-ss/sun8i-ss-core.c
72
u32 v = SS_START;
drivers/crypto/allwinner/sun8i-ss/sun8i-ss-core.c
81
v |= SS_FLOW1;
drivers/crypto/allwinner/sun8i-ss/sun8i-ss-core.c
817
u32 v;
drivers/crypto/allwinner/sun8i-ss/sun8i-ss-core.c
83
v |= SS_FLOW0;
drivers/crypto/allwinner/sun8i-ss/sun8i-ss-core.c
85
v |= rctx->op_mode;
drivers/crypto/allwinner/sun8i-ss/sun8i-ss-core.c
86
v |= rctx->method;
drivers/crypto/allwinner/sun8i-ss/sun8i-ss-core.c
873
v = readl(ss->base + SS_CTL_REG);
drivers/crypto/allwinner/sun8i-ss/sun8i-ss-core.c
874
v >>= SS_DIE_ID_SHIFT;
drivers/crypto/allwinner/sun8i-ss/sun8i-ss-core.c
875
v &= SS_DIE_ID_MASK;
drivers/crypto/allwinner/sun8i-ss/sun8i-ss-core.c
876
dev_info(&pdev->dev, "Security System Die ID %x\n", v);
drivers/crypto/allwinner/sun8i-ss/sun8i-ss-core.c
89
v |= SS_DECRYPTION;
drivers/crypto/allwinner/sun8i-ss/sun8i-ss-core.c
93
v |= SS_AES_128BITS << 7;
drivers/crypto/allwinner/sun8i-ss/sun8i-ss-core.c
96
v |= SS_AES_192BITS << 7;
drivers/crypto/allwinner/sun8i-ss/sun8i-ss-core.c
99
v |= SS_AES_256BITS << 7;
drivers/crypto/allwinner/sun8i-ss/sun8i-ss-hash.c
291
u32 v = SS_START;
drivers/crypto/allwinner/sun8i-ss/sun8i-ss-hash.c
300
v |= SS_FLOW1;
drivers/crypto/allwinner/sun8i-ss/sun8i-ss-hash.c
302
v |= SS_FLOW0;
drivers/crypto/allwinner/sun8i-ss/sun8i-ss-hash.c
304
v |= rctx->method;
drivers/crypto/allwinner/sun8i-ss/sun8i-ss-hash.c
312
v |= BIT(17);
drivers/crypto/allwinner/sun8i-ss/sun8i-ss-hash.c
319
i, flow, name, v,
drivers/crypto/allwinner/sun8i-ss/sun8i-ss-hash.c
332
writel(v, ss->base + SS_CTL_REG);
drivers/crypto/allwinner/sun8i-ss/sun8i-ss-prng.c
102
v = SS_ALG_PRNG | SS_PRNG_CONTINUE | SS_START;
drivers/crypto/allwinner/sun8i-ss/sun8i-ss-prng.c
104
v |= SS_FLOW1;
drivers/crypto/allwinner/sun8i-ss/sun8i-ss-prng.c
106
v |= SS_FLOW0;
drivers/crypto/allwinner/sun8i-ss/sun8i-ss-prng.c
139
writel(v, ss->base + SS_CTL_REG);
drivers/crypto/allwinner/sun8i-ss/sun8i-ss-prng.c
70
u32 v;
drivers/crypto/amlogic/amlogic-gxl-cipher.c
102
u32 v;
drivers/crypto/amlogic/amlogic-gxl-cipher.c
169
v = (MODE_KEY << 20) | DESC_OWN | 16;
drivers/crypto/amlogic/amlogic-gxl-cipher.c
170
desc->t_status = cpu_to_le32(v);
drivers/crypto/amlogic/amlogic-gxl-cipher.c
213
v = (op->keymode << 20) | DESC_OWN | todo | (algt->blockmode << 26);
drivers/crypto/amlogic/amlogic-gxl-cipher.c
215
v |= DESC_ENCRYPTION;
drivers/crypto/amlogic/amlogic-gxl-cipher.c
219
v |= DESC_LAST;
drivers/crypto/amlogic/amlogic-gxl-cipher.c
220
desc->t_status = cpu_to_le32(v);
drivers/crypto/amlogic/amlogic-gxl-core.c
108
static int meson_debugfs_show(struct seq_file *seq, void *v)
drivers/crypto/cavium/nitrox/nitrox_debugfs.c
20
static int device_show(struct seq_file *s, void *v)
drivers/crypto/cavium/nitrox/nitrox_debugfs.c
37
static int stats_show(struct seq_file *s, void *v)
drivers/crypto/cavium/nitrox/nitrox_debugfs.c
9
static int firmware_show(struct seq_file *s, void *v)
drivers/crypto/ccp/sp-pci.c
111
int v, ret;
drivers/crypto/ccp/sp-pci.c
113
for (v = 0; v < ARRAY_SIZE(sp_pci->msix_entry); v++)
drivers/crypto/ccp/sp-pci.c
114
sp_pci->msix_entry[v].entry = v;
drivers/crypto/ccp/sp-pci.c
116
ret = pci_enable_msix_range(pdev, sp_pci->msix_entry, 1, v);
drivers/crypto/gemini/sl3516-ce-core.c
125
u32 v;
drivers/crypto/gemini/sl3516-ce-core.c
178
v = readl(ce->base + IPSEC_STATUS_REG);
drivers/crypto/gemini/sl3516-ce-core.c
179
if (v & 0xFFF) {
drivers/crypto/gemini/sl3516-ce-core.c
180
dev_err(ce->dev, "IPSEC_STATUS_REG %x\n", v);
drivers/crypto/gemini/sl3516-ce-core.c
190
u32 v;
drivers/crypto/gemini/sl3516-ce-core.c
194
v = readl(ce->base + IPSEC_DMA_STATUS);
drivers/crypto/gemini/sl3516-ce-core.c
195
writel(v, ce->base + IPSEC_DMA_STATUS);
drivers/crypto/gemini/sl3516-ce-core.c
197
if (v & DMA_STATUS_TS_DERR)
drivers/crypto/gemini/sl3516-ce-core.c
199
if (v & DMA_STATUS_TS_PERR)
drivers/crypto/gemini/sl3516-ce-core.c
201
if (v & DMA_STATUS_RS_DERR)
drivers/crypto/gemini/sl3516-ce-core.c
203
if (v & DMA_STATUS_RS_PERR)
drivers/crypto/gemini/sl3516-ce-core.c
206
if (v & DMA_STATUS_TS_EOFI)
drivers/crypto/gemini/sl3516-ce-core.c
208
if (v & DMA_STATUS_RS_EOFI) {
drivers/crypto/gemini/sl3516-ce-core.c
248
static int sl3516_ce_debugfs_show(struct seq_file *seq, void *v)
drivers/crypto/gemini/sl3516-ce-core.c
399
u32 v;
drivers/crypto/gemini/sl3516-ce-core.c
468
v = readl(ce->base + IPSEC_ID);
drivers/crypto/gemini/sl3516-ce-core.c
470
v & GENMASK(31, 4),
drivers/crypto/gemini/sl3516-ce-core.c
471
v & GENMASK(3, 0));
drivers/crypto/gemini/sl3516-ce-core.c
472
v = readl(ce->base + IPSEC_DMA_DEVICE_ID);
drivers/crypto/gemini/sl3516-ce-core.c
474
v & GENMASK(15, 4),
drivers/crypto/gemini/sl3516-ce-core.c
475
v & GENMASK(3, 0));
drivers/crypto/gemini/sl3516-ce-core.c
79
u32 v;
drivers/crypto/gemini/sl3516-ce-core.c
81
v = TXDMA_CTRL_START | TXDMA_CTRL_CHAIN_MODE | TXDMA_CTRL_CONTINUE | \
drivers/crypto/gemini/sl3516-ce-core.c
84
writel(v, ce->base + IPSEC_TXDMA_CTRL);
drivers/crypto/gemini/sl3516-ce-core.c
89
u32 v;
drivers/crypto/gemini/sl3516-ce-core.c
91
v = RXDMA_CTRL_START | RXDMA_CTRL_CHAIN_MODE | RXDMA_CTRL_CONTINUE | \
drivers/crypto/gemini/sl3516-ce-core.c
96
writel(v, ce->base + IPSEC_RXDMA_CTRL);
drivers/crypto/hifn_795x.c
696
u32 v;
drivers/crypto/hifn_795x.c
700
v = a & 0x80080125;
drivers/crypto/hifn_795x.c
701
v ^= v >> 16;
drivers/crypto/hifn_795x.c
702
v ^= v >> 8;
drivers/crypto/hifn_795x.c
703
v ^= v >> 4;
drivers/crypto/hifn_795x.c
704
v ^= v >> 2;
drivers/crypto/hifn_795x.c
705
v ^= v >> 1;
drivers/crypto/hifn_795x.c
707
a = (v & 1) ^ (a << 1);
drivers/crypto/intel/iaa/iaa_crypto_stats.c
170
static int global_stats_show(struct seq_file *m, void *v)
drivers/crypto/intel/iaa/iaa_crypto_stats.c
193
static int wq_stats_show(struct seq_file *m, void *v)
drivers/crypto/intel/qat/qat_common/adf_cfg.c
21
static int qat_dev_cfg_show(struct seq_file *sfile, void *v)
drivers/crypto/intel/qat/qat_common/adf_cfg.c
25
list_entry(v, struct adf_cfg_section, list);
drivers/crypto/intel/qat/qat_common/adf_cfg.c
36
static void *qat_dev_cfg_next(struct seq_file *sfile, void *v, loff_t *pos)
drivers/crypto/intel/qat/qat_common/adf_cfg.c
40
return seq_list_next(v, &dev_cfg->sec_list, pos);
drivers/crypto/intel/qat/qat_common/adf_cfg.c
43
static void qat_dev_cfg_stop(struct seq_file *sfile, void *v)
drivers/crypto/intel/qat/qat_common/adf_cnv_dbgfs.c
105
static void *qat_cnv_errors_seq_next(struct seq_file *sfile, void *v,
drivers/crypto/intel/qat/qat_common/adf_cnv_dbgfs.c
118
static void qat_cnv_errors_seq_stop(struct seq_file *sfile, void *v)
drivers/crypto/intel/qat/qat_common/adf_cnv_dbgfs.c
122
static int qat_cnv_errors_seq_show(struct seq_file *sfile, void *v)
drivers/crypto/intel/qat/qat_common/adf_cnv_dbgfs.c
129
if (v == SEQ_START_TOKEN) {
drivers/crypto/intel/qat/qat_common/adf_cnv_dbgfs.c
135
ae_errors = v;
drivers/crypto/intel/qat/qat_common/adf_fw_counters.c
150
static void *qat_fw_counters_seq_next(struct seq_file *sfile, void *v, loff_t *pos)
drivers/crypto/intel/qat/qat_common/adf_fw_counters.c
162
static void qat_fw_counters_seq_stop(struct seq_file *sfile, void *v) {}
drivers/crypto/intel/qat/qat_common/adf_fw_counters.c
164
static int qat_fw_counters_seq_show(struct seq_file *sfile, void *v)
drivers/crypto/intel/qat/qat_common/adf_fw_counters.c
168
if (v == SEQ_START_TOKEN) {
drivers/crypto/intel/qat/qat_common/adf_fw_counters.c
174
struct adf_ae_counters *ae_counters = (struct adf_ae_counters *)v;
drivers/crypto/intel/qat/qat_common/adf_transport_debug.c
141
static void *adf_bank_next(struct seq_file *sfile, void *v, loff_t *pos)
drivers/crypto/intel/qat/qat_common/adf_transport_debug.c
152
static int adf_bank_show(struct seq_file *sfile, void *v)
drivers/crypto/intel/qat/qat_common/adf_transport_debug.c
157
if (v == SEQ_START_TOKEN) {
drivers/crypto/intel/qat/qat_common/adf_transport_debug.c
161
int ring_id = *((int *)v) - 1;
drivers/crypto/intel/qat/qat_common/adf_transport_debug.c
184
static void adf_bank_stop(struct seq_file *sfile, void *v)
drivers/crypto/intel/qat/qat_common/adf_transport_debug.c
34
static void *adf_ring_next(struct seq_file *sfile, void *v, loff_t *pos)
drivers/crypto/intel/qat/qat_common/adf_transport_debug.c
48
static int adf_ring_show(struct seq_file *sfile, void *v)
drivers/crypto/intel/qat/qat_common/adf_transport_debug.c
55
if (v == SEQ_START_TOKEN) {
drivers/crypto/intel/qat/qat_common/adf_transport_debug.c
79
v, ADF_MSG_SIZE_TO_BYTES(ring->msg_size), false);
drivers/crypto/intel/qat/qat_common/adf_transport_debug.c
83
static void adf_ring_stop(struct seq_file *sfile, void *v)
drivers/crypto/rockchip/rk3288_crypto.c
194
static int rk_crypto_debugfs_show(struct seq_file *seq, void *v)
drivers/crypto/rockchip/rk3288_crypto.h
19
#define _SBF(v, f) ((v) << (f))
drivers/crypto/rockchip/rk3288_crypto_ahash.c
271
u32 v;
drivers/crypto/rockchip/rk3288_crypto_ahash.c
327
readl_poll_timeout(rkc->reg + RK_CRYPTO_HASH_STS, v, v == 0, 10, 1000);
drivers/crypto/rockchip/rk3288_crypto_ahash.c
330
v = readl(rkc->reg + RK_CRYPTO_HASH_DOUT_0 + i * 4);
drivers/crypto/rockchip/rk3288_crypto_ahash.c
331
put_unaligned_le32(v, areq->result + i * 4);
drivers/crypto/s5p-sss.c
35
#define _SBF(s, v) ((v) << (s))
drivers/crypto/starfive/jh7110-aes.c
231
rctx->csr.aes.v = 0;
drivers/crypto/starfive/jh7110-aes.c
233
writel(rctx->csr.aes.v, cryp->base + STARFIVE_AES_CSR);
drivers/crypto/starfive/jh7110-aes.c
238
rctx->csr.aes.v = 0;
drivers/crypto/starfive/jh7110-aes.c
261
writel(rctx->csr.aes.v, cryp->base + STARFIVE_AES_CSR);
drivers/crypto/starfive/jh7110-aes.c
446
alg_cr.v = 0;
drivers/crypto/starfive/jh7110-aes.c
449
writel(alg_cr.v, cryp->base + STARFIVE_ALG_CR_OFFSET);
drivers/crypto/starfive/jh7110-aes.c
492
alg_cr.v = 0;
drivers/crypto/starfive/jh7110-aes.c
494
writel(alg_cr.v, cryp->base + STARFIVE_ALG_CR_OFFSET);
drivers/crypto/starfive/jh7110-cryp.h
105
u32 v;
drivers/crypto/starfive/jh7110-cryp.h
129
u32 v;
drivers/crypto/starfive/jh7110-cryp.h
148
u32 v;
drivers/crypto/starfive/jh7110-cryp.h
36
u32 v;
drivers/crypto/starfive/jh7110-cryp.h
73
u32 v;
drivers/crypto/starfive/jh7110-hash.c
101
writel(csr.v, cryp->base + STARFIVE_HASH_SHACSR);
drivers/crypto/starfive/jh7110-hash.c
131
alg_cr.v = 0;
drivers/crypto/starfive/jh7110-hash.c
134
writel(alg_cr.v, cryp->base + STARFIVE_ALG_CR_OFFSET);
drivers/crypto/starfive/jh7110-hash.c
158
alg_cr.v = 0;
drivers/crypto/starfive/jh7110-hash.c
160
writel(alg_cr.v, cryp->base + STARFIVE_ALG_CR_OFFSET);
drivers/crypto/starfive/jh7110-hash.c
210
rctx->csr.hash.v = 0;
drivers/crypto/starfive/jh7110-hash.c
220
writel(rctx->csr.hash.v, cryp->base + STARFIVE_HASH_SHACSR);
drivers/crypto/starfive/jh7110-hash.c
77
writel(rctx->csr.hash.v, cryp->base + STARFIVE_HASH_SHACSR);
drivers/crypto/starfive/jh7110-hash.c
98
csr.v = readl(cryp->base + STARFIVE_HASH_SHACSR);
drivers/crypto/starfive/jh7110-rsa.c
112
rctx->csr.pka.v = 0;
drivers/crypto/starfive/jh7110-rsa.c
120
writel(rctx->csr.pka.v, cryp->base + STARFIVE_PKA_CACR_OFFSET);
drivers/crypto/starfive/jh7110-rsa.c
125
rctx->csr.pka.v = 0;
drivers/crypto/starfive/jh7110-rsa.c
134
writel(rctx->csr.pka.v, cryp->base + STARFIVE_PKA_CACR_OFFSET);
drivers/crypto/starfive/jh7110-rsa.c
146
rctx->csr.pka.v = 0;
drivers/crypto/starfive/jh7110-rsa.c
154
writel(rctx->csr.pka.v, cryp->base + STARFIVE_PKA_CACR_OFFSET);
drivers/crypto/starfive/jh7110-rsa.c
199
rctx->csr.pka.v = 0;
drivers/crypto/starfive/jh7110-rsa.c
207
writel(rctx->csr.pka.v, cryp->base + STARFIVE_PKA_CACR_OFFSET);
drivers/crypto/starfive/jh7110-rsa.c
214
rctx->csr.pka.v = 0;
drivers/crypto/starfive/jh7110-rsa.c
222
writel(rctx->csr.pka.v, cryp->base + STARFIVE_PKA_CACR_OFFSET);
drivers/crypto/starfive/jh7110-rsa.c
82
rctx->csr.pka.v = 0;
drivers/crypto/starfive/jh7110-rsa.c
84
writel(rctx->csr.pka.v, cryp->base + STARFIVE_PKA_CACR_OFFSET);
drivers/crypto/starfive/jh7110-rsa.c
90
rctx->csr.pka.v = 0;
drivers/crypto/starfive/jh7110-rsa.c
99
writel(rctx->csr.pka.v, cryp->base + STARFIVE_PKA_CACR_OFFSET);
drivers/crypto/tegra/tegra-se.h
564
static inline u32 host1x_uclass_incr_syncpt_cond_f(u32 v)
drivers/crypto/tegra/tegra-se.h
566
return (v & 0xff) << 10;
drivers/crypto/tegra/tegra-se.h
569
static inline u32 host1x_uclass_incr_syncpt_indx_f(u32 v)
drivers/crypto/tegra/tegra-se.h
571
return (v & 0x3ff) << 0;
drivers/crypto/xilinx/zynqmp-sha.c
192
u32 v;
drivers/crypto/xilinx/zynqmp-sha.c
195
err = zynqmp_pm_get_api_version(&v);
drivers/dma/altera-msgdma.c
139
#define MSGDMA_CSR_WR_FILL_LEVEL_GET(v) (((v) & 0xffff0000) >> 16)
drivers/dma/altera-msgdma.c
140
#define MSGDMA_CSR_RD_FILL_LEVEL_GET(v) ((v) & 0x0000ffff)
drivers/dma/altera-msgdma.c
141
#define MSGDMA_CSR_RESP_FILL_LEVEL_GET(v) ((v) & 0x0000ffff)
drivers/dma/altera-msgdma.c
143
#define MSGDMA_CSR_SEQ_NUM_GET(v) (((v) & 0xffff0000) >> 16)
drivers/dma/amd/ae4dma/ae4dma-pci.c
19
int i, v, ret;
drivers/dma/amd/ae4dma/ae4dma-pci.c
23
for (v = 0; v < ARRAY_SIZE(ae4_msix->msix_entry); v++)
drivers/dma/amd/ae4dma/ae4dma-pci.c
24
ae4_msix->msix_entry[v].entry = v;
drivers/dma/amd/ae4dma/ae4dma-pci.c
26
ret = pci_alloc_irq_vectors(pdev, v, v, PCI_IRQ_MSIX);
drivers/dma/amd/ae4dma/ae4dma-pci.c
27
if (ret != v) {
drivers/dma/dw/regs.h
388
#define lli_set(d, reg, v) ((d)->lli.reg |= cpu_to_le32(v))
drivers/dma/dw/regs.h
389
#define lli_clear(d, reg, v) ((d)->lli.reg &= ~cpu_to_le32(v))
drivers/dma/dw/regs.h
391
#define lli_write(d, reg, v) ((d)->lli.reg = cpu_to_le32(v))
drivers/dma/fsl-dpaa2-qdma/dpdmai.h
19
#define DPDMAI_CMDID_FORMAT_V(x, v) (((x) << DPDMAI_CMD_ID_OFFSET) | (v))
drivers/dma/fsldma.h
198
#define fsl_iowrite32(v, p) out_le32(p, v)
drivers/dma/fsldma.h
199
#define fsl_iowrite32be(v, p) out_be32(p, v)
drivers/dma/fsldma.h
204
#define fsl_iowrite64(v, p) out_le64(p, v)
drivers/dma/fsldma.h
205
#define fsl_iowrite64be(v, p) out_be64(p, v)
drivers/dma/fsldma.h
240
#define fsl_iowrite32(v, p) iowrite32(v, p)
drivers/dma/fsldma.h
241
#define fsl_iowrite32be(v, p) iowrite32be(v, p)
drivers/dma/fsldma.h
244
#define fsl_iowrite64(v, p) iowrite64(v, p)
drivers/dma/fsldma.h
245
#define fsl_iowrite64be(v, p) iowrite64be(v, p)
drivers/dma/fsldma.h
259
be##width##_to_cpu((__force __be##width)(v##width)d) : \
drivers/dma/fsldma.h
260
le##width##_to_cpu((__force __le##width)(v##width)d))
drivers/dma/fsldma.h
263
(__force v##width)cpu_to_be##width(c) : \
drivers/dma/fsldma.h
264
(__force v##width)cpu_to_le##width(c))
drivers/dma/lpc18xx-dmamux.c
24
#define LPC18XX_DMAMUX_VAL(v, n) ((v) << (n * 2))
drivers/dma/sf-pdma/sf-pdma.c
231
u32 v;
drivers/dma/sf-pdma/sf-pdma.c
233
v = PDMA_CLAIM_MASK |
drivers/dma/sf-pdma/sf-pdma.c
238
writel(v, regs->ctrl);
drivers/dma/sf-pdma/sf-pdma.c
38
static inline void writeq(unsigned long long v, void __iomem *addr)
drivers/dma/sf-pdma/sf-pdma.c
40
writel(lower_32_bits(v), addr);
drivers/dma/sf-pdma/sf-pdma.c
41
writel(upper_32_bits(v), addr + 4);
drivers/dma/ti/omap-dma.c
1551
unsigned long cmd, void *v)
drivers/dma/ti/omap-dma.c
1603
unsigned long cmd, void *v)
drivers/dma/xgene-dma.c
31
#define XGENE_DMA_RING_ID_SETUP(v) ((v) | BIT(31))
drivers/dma/xgene-dma.c
33
#define XGENE_DMA_RING_ID_BUF_SETUP(v) (((v) << 9) | BIT(21))
drivers/dma/xgene-dma.c
43
#define XGENE_DMA_RING_NE_INT_MODE_SET(m, v) \
drivers/dma/xgene-dma.c
44
((m) = ((m) & ~BIT(31 - (v))) | BIT(31 - (v)))
drivers/dma/xgene-dma.c
45
#define XGENE_DMA_RING_NE_INT_MODE_RESET(m, v) \
drivers/dma/xgene-dma.c
46
((m) &= (~BIT(31 - (v))))
drivers/dma/xgene-dma.c
53
#define XGENE_DMA_RING_DST_ID(v) ((1 << 10) | (v))
drivers/dma/xgene-dma.c
55
#define XGENE_DMA_RING_CMD_BASE_OFFSET(v) ((v) << 6)
drivers/dma/xgene-dma.c
58
#define XGENE_DMA_RING_ADDRL_SET(m, v) \
drivers/dma/xgene-dma.c
59
(((u32 *)(m))[2] |= (((v) >> 8) << 5))
drivers/dma/xgene-dma.c
60
#define XGENE_DMA_RING_ADDRH_SET(m, v) \
drivers/dma/xgene-dma.c
61
(((u32 *)(m))[3] |= ((v) >> 35))
drivers/dma/xgene-dma.c
64
#define XGENE_DMA_RING_SIZE_SET(m, v) \
drivers/dma/xgene-dma.c
65
(((u32 *)(m))[3] |= ((v) << 23))
drivers/dma/xgene-dma.c
74
#define XGENE_DMA_RING_TYPE_SET(m, v) \
drivers/dma/xgene-dma.c
75
(((u32 *)(m))[4] |= ((v) << 19))
drivers/dma/xgene-dma.c
79
#define XGENE_DMA_DEV_ID_RD(v) ((v) & 0x00000FFF)
drivers/dma/xgene-dma.c
80
#define XGENE_DMA_BUS_ID_RD(v) (((v) >> 12) & 3)
drivers/dma/xgene-dma.c
81
#define XGENE_DMA_REV_NO_RD(v) (((v) >> 14) & 3)
drivers/dma/xgene-dma.c
83
#define XGENE_DMA_CH_SETUP(v) \
drivers/dma/xgene-dma.c
84
((v) = ((v) & ~0x000FFFFF) | 0x000AAFFF)
drivers/dma/xgene-dma.c
85
#define XGENE_DMA_ENABLE(v) ((v) |= BIT(31))
drivers/dma/xgene-dma.c
86
#define XGENE_DMA_DISABLE(v) ((v) &= ~BIT(31))
drivers/dma/xgene-dma.c
88
#define XGENE_DMA_RAID6_MULTI_CTRL(v) ((v) << 24)
drivers/edac/i10nm_base.c
218
u32 offset = rrl->offsets[rrl_set][0], v;
drivers/edac/i10nm_base.c
227
v = read_imc_reg(imc, chan, offset, width);
drivers/edac/i10nm_base.c
231
*rrl_ctl = v;
drivers/edac/i10nm_base.c
232
v &= ~rrl->uc_mask;
drivers/edac/i10nm_base.c
235
v |= rrl->noover_mask;
drivers/edac/i10nm_base.c
237
v &= ~rrl->noover_mask;
drivers/edac/i10nm_base.c
240
v |= rrl->en_patspr_mask;
drivers/edac/i10nm_base.c
242
v &= ~rrl->en_patspr_mask;
drivers/edac/i10nm_base.c
244
v |= rrl->en_mask;
drivers/edac/i10nm_base.c
248
v |= rrl->uc_mask;
drivers/edac/i10nm_base.c
252
v &= ~rrl->noover_mask;
drivers/edac/i10nm_base.c
255
v |= rrl->noover_mask;
drivers/edac/i10nm_base.c
260
v &= ~rrl->en_patspr_mask;
drivers/edac/i10nm_base.c
263
v |= rrl->en_patspr_mask;
drivers/edac/i10nm_base.c
267
v &= ~rrl->en_mask;
drivers/edac/i10nm_base.c
270
write_imc_reg(imc, chan, offset, width, v);
drivers/edac/i10nm_base.c
54
#define I10NM_SET_REG32(m, i, offset, v) \
drivers/edac/i10nm_base.c
55
writel(v, (m)->mbase + (i) * (m)->chan_mmio_sz + (offset))
drivers/edac/i7300_edac.c
295
#define NRECMEMA_BANK(v) (((v) >> 12) & 7)
drivers/edac/i7300_edac.c
296
#define NRECMEMA_RANK(v) (((v) >> 8) & 15)
drivers/edac/i7300_edac.c
299
#define NRECMEMB_IS_WR(v) ((v) & (1 << 31))
drivers/edac/i7300_edac.c
300
#define NRECMEMB_CAS(v) (((v) >> 16) & 0x1fff)
drivers/edac/i7300_edac.c
301
#define NRECMEMB_RAS(v) ((v) & 0xffff)
drivers/edac/i7300_edac.c
308
#define RECMEMA_BANK(v) (((v) >> 12) & 7)
drivers/edac/i7300_edac.c
309
#define RECMEMA_RANK(v) (((v) >> 8) & 15)
drivers/edac/i7300_edac.c
312
#define RECMEMB_IS_WR(v) ((v) & (1 << 31))
drivers/edac/i7300_edac.c
313
#define RECMEMB_CAS(v) (((v) >> 16) & 0x1fff)
drivers/edac/i7300_edac.c
314
#define RECMEMB_RAS(v) ((v) & 0xffff)
drivers/edac/igen6_edac.c
100
#define MAD_INTRA_CH_DIMM_L_MAP(v) GET_BITFIELD(v, 0, 0)
drivers/edac/igen6_edac.c
104
#define MAD_DIMM_CH_DIMM_L_SIZE(v) ((u64)GET_BITFIELD(v, 0, 6) << 29)
drivers/edac/igen6_edac.c
105
#define MAD_DIMM_CH_DLW(v) GET_BITFIELD(v, 7, 8)
drivers/edac/igen6_edac.c
106
#define MAD_DIMM_CH_DIMM_S_SIZE(v) ((u64)GET_BITFIELD(v, 16, 22) << 29)
drivers/edac/igen6_edac.c
107
#define MAD_DIMM_CH_DSW(v) GET_BITFIELD(v, 24, 25)
drivers/edac/igen6_edac.c
111
#define MAC_MC_HASH_LSB(v) GET_BITFIELD(v, 1, 3)
drivers/edac/igen6_edac.c
117
#define CHANNEL_HASH_MASK(v) (GET_BITFIELD(v, 6, 19) << 6)
drivers/edac/igen6_edac.c
118
#define CHANNEL_HASH_LSB_MASK_BIT(v) GET_BITFIELD(v, 24, 26)
drivers/edac/igen6_edac.c
119
#define CHANNEL_HASH_MODE(v) GET_BITFIELD(v, 28, 28)
drivers/edac/igen6_edac.c
122
#define MEM_SLICE_HASH_MASK(v) (GET_BITFIELD(v, 6, 19) << 6)
drivers/edac/igen6_edac.c
1229
u64 v;
drivers/edac/igen6_edac.c
123
#define MEM_SLICE_HASH_LSB_MASK_BIT(v) GET_BITFIELD(v, 24, 26)
drivers/edac/igen6_edac.c
1260
igen6_tom = u.v & res_cfg->reg_tom_mask;
drivers/edac/igen6_edac.c
1271
igen6_touud = u.v & res_cfg->reg_touud_mask;
drivers/edac/igen6_edac.c
301
u64 v;
drivers/edac/igen6_edac.c
318
if (!(u.v & MCHBAR_EN)) {
drivers/edac/igen6_edac.c
323
*mchbar = u.v & res_cfg->reg_mchbar_mask;
drivers/edac/igen6_edac.c
324
edac_dbg(2, "MCHBAR 0x%llx (reg 0x%llx)\n", *mchbar, u.v);
drivers/edac/igen6_edac.c
331
u32 v;
drivers/edac/igen6_edac.c
333
if (pci_read_config_dword(pdev, CAPID_C_OFFSET, &v))
drivers/edac/igen6_edac.c
336
return !!(CAPID_C_IBECC & v);
drivers/edac/igen6_edac.c
360
u32 v;
drivers/edac/igen6_edac.c
362
if (pci_read_config_dword(pdev, CAPID_C_OFFSET, &v))
drivers/edac/igen6_edac.c
365
return !(CAPID_C_IBECC & v) &&
drivers/edac/igen6_edac.c
371
u32 v;
drivers/edac/igen6_edac.c
373
if (pci_read_config_dword(pdev, CAPID_E_OFFSET, &v))
drivers/edac/igen6_edac.c
376
return !(CAPID_E_IBECC & v);
drivers/edac/igen6_edac.c
381
u32 v;
drivers/edac/igen6_edac.c
383
if (pci_read_config_dword(pdev, CAPID_E_OFFSET, &v))
drivers/edac/igen6_edac.c
386
return !(CAPID_E_IBECC_BIT18 & v);
drivers/edac/igen6_edac.c
43
#define GET_BITFIELD(v, lo, hi) (((v) & GENMASK_ULL(hi, lo)) >> (lo))
drivers/edac/igen6_edac.c
83
#define ECC_ERROR_LOG_SYND(v) GET_BITFIELD(v, 46, 61)
drivers/edac/igen6_edac.c
93
#define MAD_INTER_CHANNEL_DDR_TYPE(v) GET_BITFIELD(v, 0, 2)
drivers/edac/igen6_edac.c
94
#define MAD_INTER_CHANNEL_ECHM(v) GET_BITFIELD(v, 3, 3)
drivers/edac/igen6_edac.c
95
#define MAD_INTER_CHANNEL_CH_L_MAP(v) GET_BITFIELD(v, 4, 4)
drivers/edac/igen6_edac.c
96
#define MAD_INTER_CHANNEL_CH_S_SIZE(v) ((u64)GET_BITFIELD(v, 12, 19) << 29)
drivers/edac/pnd2_edac.c
126
#define GET_BITFIELD(v, lo, hi) (((v) & GENMASK_ULL(hi, lo)) >> (lo))
drivers/edac/sb_edac.c
53
#define GET_BITFIELD(v, lo, hi) \
drivers/edac/sb_edac.c
54
(((v) & GENMASK_ULL(hi, lo)) >> (lo))
drivers/edac/skx_common.h
29
#define GET_BITFIELD(v, lo, hi) \
drivers/edac/skx_common.h
30
(((v) & GENMASK_ULL((hi), (lo))) >> (lo))
drivers/firewire/core-card.c
66
#define BIB_CRC(v) ((v) << 0)
drivers/firewire/core-card.c
67
#define BIB_CRC_LENGTH(v) ((v) << 16)
drivers/firewire/core-card.c
68
#define BIB_INFO_LENGTH(v) ((v) << 24)
drivers/firewire/core-card.c
70
#define BIB_LINK_SPEED(v) ((v) << 0)
drivers/firewire/core-card.c
71
#define BIB_GENERATION(v) ((v) << 4)
drivers/firewire/core-card.c
72
#define BIB_MAX_ROM(v) ((v) << 8)
drivers/firewire/core-card.c
73
#define BIB_MAX_RECEIVE(v) ((v) << 12)
drivers/firewire/core-card.c
74
#define BIB_CYC_CLK_ACC(v) ((v) << 16)
drivers/firewire/core-cdev.c
1108
#define GET_PAYLOAD_LENGTH(v) ((v) & 0xffff)
drivers/firewire/core-cdev.c
1109
#define GET_INTERRUPT(v) (((v) >> 16) & 0x01)
drivers/firewire/core-cdev.c
1110
#define GET_SKIP(v) (((v) >> 17) & 0x01)
drivers/firewire/core-cdev.c
1111
#define GET_TAG(v) (((v) >> 18) & 0x03)
drivers/firewire/core-cdev.c
1112
#define GET_SY(v) (((v) >> 20) & 0x0f)
drivers/firewire/core-cdev.c
1113
#define GET_HEADER_LENGTH(v) (((v) >> 24) & 0xff)
drivers/firewire/core-cdev.c
191
struct { void *data; size_t size; } v[2];
drivers/firewire/core-cdev.c
319
event->v[0].data = data0;
drivers/firewire/core-cdev.c
320
event->v[0].size = size0;
drivers/firewire/core-cdev.c
321
event->v[1].data = data1;
drivers/firewire/core-cdev.c
322
event->v[1].size = size1;
drivers/firewire/core-cdev.c
357
for (i = 0; i < ARRAY_SIZE(event->v) && total < count; i++) {
drivers/firewire/core-cdev.c
358
size = min(event->v[i].size, count - total);
drivers/firewire/core-cdev.c
359
if (copy_to_user(buffer + total, event->v[i].data, size)) {
drivers/firewire/net.c
1145
unsigned v;
drivers/firewire/net.c
1148
for (v = 0; v < num_packets / FWNET_ISO_PAGE_COUNT; v++)
drivers/firewire/net.c
1149
*ptrptr++ = (void *) ((char *)ptr + v * max_receive);
drivers/firewire/sbp2.c
236
#define STATUS_GET_ORB_HIGH(v) ((v).status & 0xffff)
drivers/firewire/sbp2.c
237
#define STATUS_GET_SBP_STATUS(v) (((v).status >> 16) & 0xff)
drivers/firewire/sbp2.c
238
#define STATUS_GET_LEN(v) (((v).status >> 24) & 0x07)
drivers/firewire/sbp2.c
239
#define STATUS_GET_DEAD(v) (((v).status >> 27) & 0x01)
drivers/firewire/sbp2.c
240
#define STATUS_GET_RESPONSE(v) (((v).status >> 28) & 0x03)
drivers/firewire/sbp2.c
241
#define STATUS_GET_SOURCE(v) (((v).status >> 30) & 0x03)
drivers/firewire/sbp2.c
242
#define STATUS_GET_ORB_LOW(v) ((v).orb_low)
drivers/firewire/sbp2.c
243
#define STATUS_GET_DATA(v) ((v).data)
drivers/firewire/sbp2.c
266
#define MANAGEMENT_ORB_LUN(v) ((v))
drivers/firewire/sbp2.c
267
#define MANAGEMENT_ORB_FUNCTION(v) ((v) << 16)
drivers/firewire/sbp2.c
268
#define MANAGEMENT_ORB_RECONNECT(v) ((v) << 20)
drivers/firewire/sbp2.c
269
#define MANAGEMENT_ORB_EXCLUSIVE(v) ((v) ? 1 << 28 : 0)
drivers/firewire/sbp2.c
270
#define MANAGEMENT_ORB_REQUEST_FORMAT(v) ((v) << 29)
drivers/firewire/sbp2.c
273
#define MANAGEMENT_ORB_RESPONSE_LENGTH(v) ((v))
drivers/firewire/sbp2.c
274
#define MANAGEMENT_ORB_PASSWORD_LENGTH(v) ((v) << 16)
drivers/firewire/sbp2.c
296
#define COMMAND_ORB_DATA_SIZE(v) ((v))
drivers/firewire/sbp2.c
297
#define COMMAND_ORB_PAGE_SIZE(v) ((v) << 16)
drivers/firewire/sbp2.c
299
#define COMMAND_ORB_MAX_PAYLOAD(v) ((v) << 20)
drivers/firewire/sbp2.c
300
#define COMMAND_ORB_SPEED(v) ((v) << 24)
drivers/firewire/sbp2.c
302
#define COMMAND_ORB_REQUEST_FORMAT(v) ((v) << 29)
drivers/firmware/arm_scmi/sensors.c
103
#define S32_EXT(v) \
drivers/firmware/arm_scmi/sensors.c
105
int __v = (v); \
drivers/firmware/arm_scmi/voltage.c
109
num_levels, num_returned, num_remaining, v->id);
drivers/firmware/arm_scmi/voltage.c
113
v->levels_uv = devm_kcalloc(dev, num_levels, sizeof(u32), GFP_KERNEL);
drivers/firmware/arm_scmi/voltage.c
114
if (!v->levels_uv)
drivers/firmware/arm_scmi/voltage.c
117
v->num_levels = num_levels;
drivers/firmware/arm_scmi/voltage.c
118
v->segmented = segmented;
drivers/firmware/arm_scmi/voltage.c
125
struct scmi_voltage_info *v;
drivers/firmware/arm_scmi/voltage.c
135
msg->domain_id = cpu_to_le32(p->v->id);
drivers/firmware/arm_scmi/voltage.c
152
if (!p->v->num_levels) {
drivers/firmware/arm_scmi/voltage.c
153
ret = scmi_init_voltage_levels(p->dev, p->v, st->num_returned,
drivers/firmware/arm_scmi/voltage.c
157
st->max_resources = p->v->num_levels;
drivers/firmware/arm_scmi/voltage.c
173
p->v->levels_uv[st->desc_index + st->loop_idx] = val;
drivers/firmware/arm_scmi/voltage.c
175
p->v->negative_volts_allowed = true;
drivers/firmware/arm_scmi/voltage.c
181
struct scmi_voltage_info *v)
drivers/firmware/arm_scmi/voltage.c
192
.v = v,
drivers/firmware/arm_scmi/voltage.c
195
iter = ph->hops->iter_response_init(ph, &ops, v->num_levels,
drivers/firmware/arm_scmi/voltage.c
204
v->num_levels = 0;
drivers/firmware/arm_scmi/voltage.c
205
devm_kfree(ph->dev, v->levels_uv);
drivers/firmware/arm_scmi/voltage.c
226
struct scmi_voltage_info *v;
drivers/firmware/arm_scmi/voltage.c
236
v = vinfo->domains + dom;
drivers/firmware/arm_scmi/voltage.c
237
v->id = dom;
drivers/firmware/arm_scmi/voltage.c
239
strscpy(v->name, resp_dom->name, SCMI_SHORT_NAME_MAX_SIZE);
drivers/firmware/arm_scmi/voltage.c
249
v->id, NULL, v->name,
drivers/firmware/arm_scmi/voltage.c
252
v->async_level_set = true;
drivers/firmware/arm_scmi/voltage.c
256
scmi_voltage_levels_get(ph, v);
drivers/firmware/arm_scmi/voltage.c
329
struct scmi_voltage_info *v;
drivers/firmware/arm_scmi/voltage.c
339
v = vinfo->domains + domain_id;
drivers/firmware/arm_scmi/voltage.c
345
if (!v->async_level_set || mode != SCMI_VOLTAGE_LEVEL_SET_AUTO) {
drivers/firmware/arm_scmi/voltage.c
358
v->id,
drivers/firmware/arm_scmi/voltage.c
94
struct scmi_voltage_info *v,
drivers/firmware/dmi_scan.c
426
static void __init count_mem_devices(const struct dmi_header *dm, void *v)
drivers/firmware/dmi_scan.c
433
static void __init save_mem_devices(const struct dmi_header *dm, void *v)
drivers/firmware/tegra/bpmp-debugfs.c
51
static int seqbuf_read_u32(struct seqbuf *seqbuf, u32 *v)
drivers/firmware/tegra/bpmp-debugfs.c
53
return seqbuf_read(seqbuf, v, 4);
drivers/fpga/dfl-afu-error.c
55
u64 v;
drivers/fpga/dfl-afu-error.c
75
v = readq(base_hdr + PORT_HDR_STS);
drivers/fpga/dfl-afu-error.c
76
if (FIELD_GET(PORT_STS_PWR_STATE, v) == PORT_STS_PWR_STATE_AP6) {
drivers/fpga/dfl-afu-error.c
90
v = readq(base_err + PORT_ERROR);
drivers/fpga/dfl-afu-error.c
92
if (v == err) {
drivers/fpga/dfl-afu-error.c
93
writeq(v, base_err + PORT_ERROR);
drivers/fpga/dfl-afu-error.c
95
v = readq(base_err + PORT_FIRST_ERROR);
drivers/fpga/dfl-afu-error.c
96
writeq(v, base_err + PORT_FIRST_ERROR);
drivers/fpga/dfl-afu-error.c
99
__func__, v, err);
drivers/fpga/dfl-afu-main.c
168
u64 v;
drivers/fpga/dfl-afu-main.c
173
v = readq(base + PORT_HDR_CTRL);
drivers/fpga/dfl-afu-main.c
176
return sprintf(buf, "%x\n", (u8)FIELD_GET(PORT_CTRL_LATENCY, v));
drivers/fpga/dfl-afu-main.c
186
u64 v;
drivers/fpga/dfl-afu-main.c
194
v = readq(base + PORT_HDR_CTRL);
drivers/fpga/dfl-afu-main.c
195
v &= ~PORT_CTRL_LATENCY;
drivers/fpga/dfl-afu-main.c
196
v |= FIELD_PREP(PORT_CTRL_LATENCY, ltr ? 1 : 0);
drivers/fpga/dfl-afu-main.c
197
writeq(v, base + PORT_HDR_CTRL);
drivers/fpga/dfl-afu-main.c
209
u64 v;
drivers/fpga/dfl-afu-main.c
214
v = readq(base + PORT_HDR_STS);
drivers/fpga/dfl-afu-main.c
217
return sprintf(buf, "%x\n", (u8)FIELD_GET(PORT_STS_AP1_EVT, v));
drivers/fpga/dfl-afu-main.c
247
u64 v;
drivers/fpga/dfl-afu-main.c
252
v = readq(base + PORT_HDR_STS);
drivers/fpga/dfl-afu-main.c
255
return sprintf(buf, "%x\n", (u8)FIELD_GET(PORT_STS_AP2_EVT, v));
drivers/fpga/dfl-afu-main.c
284
u64 v;
drivers/fpga/dfl-afu-main.c
289
v = readq(base + PORT_HDR_STS);
drivers/fpga/dfl-afu-main.c
292
return sprintf(buf, "0x%x\n", (u8)FIELD_GET(PORT_STS_PWR_STATE, v));
drivers/fpga/dfl-afu-main.c
41
u64 v;
drivers/fpga/dfl-afu-main.c
51
v = readq(base + PORT_HDR_CTRL);
drivers/fpga/dfl-afu-main.c
52
v &= ~PORT_CTRL_SFTRST;
drivers/fpga/dfl-afu-main.c
53
writeq(v, base + PORT_HDR_CTRL);
drivers/fpga/dfl-afu-main.c
59
if (readq_poll_timeout(base + PORT_HDR_CTRL, v,
drivers/fpga/dfl-afu-main.c
60
!(v & PORT_CTRL_SFTRST_ACK),
drivers/fpga/dfl-afu-main.c
81
u64 v;
drivers/fpga/dfl-afu-main.c
89
v = readq(base + PORT_HDR_CTRL);
drivers/fpga/dfl-afu-main.c
90
v |= PORT_CTRL_SFTRST;
drivers/fpga/dfl-afu-main.c
91
writeq(v, base + PORT_HDR_CTRL);
drivers/fpga/dfl-afu-main.c
98
if (readq_poll_timeout(base + PORT_HDR_CTRL, v,
drivers/fpga/dfl-afu-main.c
99
v & PORT_CTRL_SFTRST_ACK,
drivers/fpga/dfl-fme-error.c
110
u64 v, val;
drivers/fpga/dfl-fme-error.c
120
v = readq(base + PCIE1_ERROR);
drivers/fpga/dfl-fme-error.c
121
if (val == v)
drivers/fpga/dfl-fme-error.c
122
writeq(v, base + PCIE1_ERROR);
drivers/fpga/dfl-fme-error.c
163
u64 v;
drivers/fpga/dfl-fme-error.c
168
v = readq(base + RAS_ERROR_INJECT);
drivers/fpga/dfl-fme-error.c
172
(unsigned long long)FIELD_GET(INJECT_ERROR_MASK, v));
drivers/fpga/dfl-fme-error.c
182
u64 v;
drivers/fpga/dfl-fme-error.c
193
v = readq(base + RAS_ERROR_INJECT);
drivers/fpga/dfl-fme-error.c
194
v &= ~INJECT_ERROR_MASK;
drivers/fpga/dfl-fme-error.c
195
v |= FIELD_PREP(INJECT_ERROR_MASK, inject_error);
drivers/fpga/dfl-fme-error.c
196
writeq(v, base + RAS_ERROR_INJECT);
drivers/fpga/dfl-fme-error.c
225
u64 v, val;
drivers/fpga/dfl-fme-error.c
236
v = readq(base + FME_ERROR);
drivers/fpga/dfl-fme-error.c
237
if (val == v)
drivers/fpga/dfl-fme-error.c
238
writeq(v, base + FME_ERROR);
drivers/fpga/dfl-fme-error.c
65
u64 v, val;
drivers/fpga/dfl-fme-error.c
75
v = readq(base + PCIE0_ERROR);
drivers/fpga/dfl-fme-error.c
76
if (val == v)
drivers/fpga/dfl-fme-error.c
77
writeq(v, base + PCIE0_ERROR);
drivers/fpga/dfl-fme-main.c
103
u64 v;
drivers/fpga/dfl-fme-main.c
107
v = readq(base + FME_HDR_CAP);
drivers/fpga/dfl-fme-main.c
110
(unsigned int)FIELD_GET(FME_CAP_FABRIC_VERID, v));
drivers/fpga/dfl-fme-main.c
119
u64 v;
drivers/fpga/dfl-fme-main.c
123
v = readq(base + FME_HDR_CAP);
drivers/fpga/dfl-fme-main.c
126
(unsigned int)FIELD_GET(FME_CAP_SOCKET_ID, v));
drivers/fpga/dfl-fme-main.c
214
u64 v = readq(base + FME_THERM_CAP);
drivers/fpga/dfl-fme-main.c
216
return FIELD_GET(THERM_NO_THROTTLE, v) ? false : true;
drivers/fpga/dfl-fme-main.c
236
u64 v;
drivers/fpga/dfl-fme-main.c
240
v = readq(feature->ioaddr + FME_THERM_RDSENSOR_FMT1);
drivers/fpga/dfl-fme-main.c
241
*val = (long)(FIELD_GET(FPGA_TEMPERATURE, v) * MILLI);
drivers/fpga/dfl-fme-main.c
244
v = readq(feature->ioaddr + FME_THERM_THRESHOLD);
drivers/fpga/dfl-fme-main.c
245
*val = (long)(FIELD_GET(TEMP_THRESHOLD1, v) * MILLI);
drivers/fpga/dfl-fme-main.c
248
v = readq(feature->ioaddr + FME_THERM_THRESHOLD);
drivers/fpga/dfl-fme-main.c
249
*val = (long)(FIELD_GET(TEMP_THRESHOLD2, v) * MILLI);
drivers/fpga/dfl-fme-main.c
252
v = readq(feature->ioaddr + FME_THERM_THRESHOLD);
drivers/fpga/dfl-fme-main.c
253
*val = (long)(FIELD_GET(TRIP_THRESHOLD, v) * MILLI);
drivers/fpga/dfl-fme-main.c
256
v = readq(feature->ioaddr + FME_THERM_THRESHOLD);
drivers/fpga/dfl-fme-main.c
257
*val = (long)FIELD_GET(TEMP_THRESHOLD1_STATUS, v);
drivers/fpga/dfl-fme-main.c
260
v = readq(feature->ioaddr + FME_THERM_THRESHOLD);
drivers/fpga/dfl-fme-main.c
261
*val = (long)FIELD_GET(TEMP_THRESHOLD2_STATUS, v);
drivers/fpga/dfl-fme-main.c
291
u64 v;
drivers/fpga/dfl-fme-main.c
293
v = readq(feature->ioaddr + FME_THERM_THRESHOLD);
drivers/fpga/dfl-fme-main.c
296
(unsigned int)FIELD_GET(TEMP_THRESHOLD1_POLICY, v));
drivers/fpga/dfl-fme-main.c
33
u64 v;
drivers/fpga/dfl-fme-main.c
37
v = readq(base + FME_HDR_CAP);
drivers/fpga/dfl-fme-main.c
387
u64 v;
drivers/fpga/dfl-fme-main.c
391
v = readq(feature->ioaddr + FME_PWR_STATUS);
drivers/fpga/dfl-fme-main.c
392
*val = (long)(FIELD_GET(PWR_CONSUMED, v) * MICRO);
drivers/fpga/dfl-fme-main.c
395
v = readq(feature->ioaddr + FME_PWR_THRESHOLD);
drivers/fpga/dfl-fme-main.c
396
*val = (long)(FIELD_GET(PWR_THRESHOLD1, v) * MICRO);
drivers/fpga/dfl-fme-main.c
399
v = readq(feature->ioaddr + FME_PWR_THRESHOLD);
drivers/fpga/dfl-fme-main.c
40
(unsigned int)FIELD_GET(FME_CAP_NUM_PORTS, v));
drivers/fpga/dfl-fme-main.c
400
*val = (long)(FIELD_GET(PWR_THRESHOLD2, v) * MICRO);
drivers/fpga/dfl-fme-main.c
403
v = readq(feature->ioaddr + FME_PWR_THRESHOLD);
drivers/fpga/dfl-fme-main.c
404
*val = (long)FIELD_GET(PWR_THRESHOLD1_STATUS, v);
drivers/fpga/dfl-fme-main.c
407
v = readq(feature->ioaddr + FME_PWR_THRESHOLD);
drivers/fpga/dfl-fme-main.c
408
*val = (long)FIELD_GET(PWR_THRESHOLD2_STATUS, v);
drivers/fpga/dfl-fme-main.c
423
u64 v;
drivers/fpga/dfl-fme-main.c
431
v = readq(feature->ioaddr + FME_PWR_THRESHOLD);
drivers/fpga/dfl-fme-main.c
432
v &= ~PWR_THRESHOLD1;
drivers/fpga/dfl-fme-main.c
433
v |= FIELD_PREP(PWR_THRESHOLD1, val);
drivers/fpga/dfl-fme-main.c
434
writeq(v, feature->ioaddr + FME_PWR_THRESHOLD);
drivers/fpga/dfl-fme-main.c
437
v = readq(feature->ioaddr + FME_PWR_THRESHOLD);
drivers/fpga/dfl-fme-main.c
438
v &= ~PWR_THRESHOLD2;
drivers/fpga/dfl-fme-main.c
439
v |= FIELD_PREP(PWR_THRESHOLD2, val);
drivers/fpga/dfl-fme-main.c
440
writeq(v, feature->ioaddr + FME_PWR_THRESHOLD);
drivers/fpga/dfl-fme-main.c
492
u64 v;
drivers/fpga/dfl-fme-main.c
494
v = readq(feature->ioaddr + FME_PWR_XEON_LIMIT);
drivers/fpga/dfl-fme-main.c
496
if (FIELD_GET(XEON_PWR_EN, v))
drivers/fpga/dfl-fme-main.c
497
xeon_limit = FIELD_GET(XEON_PWR_LIMIT, v);
drivers/fpga/dfl-fme-main.c
507
u64 v;
drivers/fpga/dfl-fme-main.c
509
v = readq(feature->ioaddr + FME_PWR_FPGA_LIMIT);
drivers/fpga/dfl-fme-main.c
511
if (FIELD_GET(FPGA_PWR_EN, v))
drivers/fpga/dfl-fme-main.c
512
fpga_limit = FIELD_GET(FPGA_PWR_LIMIT, v);
drivers/fpga/dfl-fme-main.c
521
u64 v;
drivers/fpga/dfl-fme-main.c
523
v = readq(feature->ioaddr + FME_PWR_STATUS);
drivers/fpga/dfl-fme-main.c
526
(unsigned int)FIELD_GET(FME_LATENCY_TOLERANCE, v));
drivers/fpga/dfl-fme-main.c
53
u64 v;
drivers/fpga/dfl-fme-main.c
57
v = readq(base + FME_HDR_BITSTREAM_ID);
drivers/fpga/dfl-fme-main.c
59
return scnprintf(buf, PAGE_SIZE, "0x%llx\n", (unsigned long long)v);
drivers/fpga/dfl-fme-main.c
72
u64 v;
drivers/fpga/dfl-fme-main.c
76
v = readq(base + FME_HDR_BITSTREAM_MD);
drivers/fpga/dfl-fme-main.c
78
return scnprintf(buf, PAGE_SIZE, "0x%llx\n", (unsigned long long)v);
drivers/fpga/dfl-fme-main.c
87
u64 v;
drivers/fpga/dfl-fme-main.c
91
v = readq(base + FME_HDR_CAP);
drivers/fpga/dfl-fme-main.c
94
(unsigned int)FIELD_GET(FME_CAP_CACHE_SIZE, v));
drivers/fpga/dfl-fme-perf.c
272
u64 v;
drivers/fpga/dfl-fme-perf.c
281
v = readq(addr);
drivers/fpga/dfl-fme-perf.c
283
} while (((u32)v) > low);
drivers/fpga/dfl-fme-perf.c
285
return v;
drivers/fpga/dfl-fme-perf.c
317
u64 v, count;
drivers/fpga/dfl-fme-perf.c
328
v = readq(base + CACHE_CTRL);
drivers/fpga/dfl-fme-perf.c
329
v &= ~(CACHE_CHANNEL_SEL | CACHE_CTRL_EVNT);
drivers/fpga/dfl-fme-perf.c
330
v |= FIELD_PREP(CACHE_CHANNEL_SEL, channel);
drivers/fpga/dfl-fme-perf.c
331
v |= FIELD_PREP(CACHE_CTRL_EVNT, event);
drivers/fpga/dfl-fme-perf.c
332
writeq(v, base + CACHE_CTRL);
drivers/fpga/dfl-fme-perf.c
334
if (readq_poll_timeout_atomic(base + CACHE_CNTR0, v,
drivers/fpga/dfl-fme-perf.c
335
FIELD_GET(CACHE_CNTR_EVNT, v) == event,
drivers/fpga/dfl-fme-perf.c
341
v = fme_read_perf_cntr_reg(base + CACHE_CNTR0);
drivers/fpga/dfl-fme-perf.c
342
count = FIELD_GET(CACHE_CNTR_EVNT_CNTR, v);
drivers/fpga/dfl-fme-perf.c
343
v = fme_read_perf_cntr_reg(base + CACHE_CNTR1);
drivers/fpga/dfl-fme-perf.c
344
count += FIELD_GET(CACHE_CNTR_EVNT_CNTR, v);
drivers/fpga/dfl-fme-perf.c
367
u64 v;
drivers/fpga/dfl-fme-perf.c
398
v = readq(base + FAB_CTRL);
drivers/fpga/dfl-fme-perf.c
399
v &= ~(FAB_PORT_FILTER | FAB_PORT_ID);
drivers/fpga/dfl-fme-perf.c
402
v |= FIELD_PREP(FAB_PORT_FILTER, FAB_PORT_FILTER_DISABLE);
drivers/fpga/dfl-fme-perf.c
404
v |= FIELD_PREP(FAB_PORT_FILTER, FAB_PORT_FILTER_ENABLE);
drivers/fpga/dfl-fme-perf.c
405
v |= FIELD_PREP(FAB_PORT_ID, portid);
drivers/fpga/dfl-fme-perf.c
407
writeq(v, base + FAB_CTRL);
drivers/fpga/dfl-fme-perf.c
426
u64 v;
drivers/fpga/dfl-fme-perf.c
428
v = readq(base + FAB_CTRL);
drivers/fpga/dfl-fme-perf.c
429
v &= ~FAB_CTRL_EVNT;
drivers/fpga/dfl-fme-perf.c
430
v |= FIELD_PREP(FAB_CTRL_EVNT, event);
drivers/fpga/dfl-fme-perf.c
431
writeq(v, base + FAB_CTRL);
drivers/fpga/dfl-fme-perf.c
433
if (readq_poll_timeout_atomic(base + FAB_CNTR, v,
drivers/fpga/dfl-fme-perf.c
434
FIELD_GET(FAB_CNTR_EVNT, v) == event,
drivers/fpga/dfl-fme-perf.c
440
v = fme_read_perf_cntr_reg(base + FAB_CNTR);
drivers/fpga/dfl-fme-perf.c
441
return FIELD_GET(FAB_CNTR_EVNT_CNTR, v);
drivers/fpga/dfl-fme-perf.c
457
u64 v;
drivers/fpga/dfl-fme-perf.c
461
v = readq(base + VTD_CTRL);
drivers/fpga/dfl-fme-perf.c
462
v &= ~VTD_CTRL_EVNT;
drivers/fpga/dfl-fme-perf.c
463
v |= FIELD_PREP(VTD_CTRL_EVNT, event);
drivers/fpga/dfl-fme-perf.c
464
writeq(v, base + VTD_CTRL);
drivers/fpga/dfl-fme-perf.c
466
if (readq_poll_timeout_atomic(base + VTD_CNTR, v,
drivers/fpga/dfl-fme-perf.c
467
FIELD_GET(VTD_CNTR_EVNT, v) == event,
drivers/fpga/dfl-fme-perf.c
473
v = fme_read_perf_cntr_reg(base + VTD_CNTR);
drivers/fpga/dfl-fme-perf.c
474
return FIELD_GET(VTD_CNTR_EVNT_CNTR, v);
drivers/fpga/dfl-fme-perf.c
490
u64 v;
drivers/fpga/dfl-fme-perf.c
492
v = readq(base + VTD_SIP_CTRL);
drivers/fpga/dfl-fme-perf.c
493
v &= ~VTD_SIP_CTRL_EVNT;
drivers/fpga/dfl-fme-perf.c
494
v |= FIELD_PREP(VTD_SIP_CTRL_EVNT, event);
drivers/fpga/dfl-fme-perf.c
495
writeq(v, base + VTD_SIP_CTRL);
drivers/fpga/dfl-fme-perf.c
497
if (readq_poll_timeout_atomic(base + VTD_SIP_CNTR, v,
drivers/fpga/dfl-fme-perf.c
498
FIELD_GET(VTD_SIP_CNTR_EVNT, v) == event,
drivers/fpga/dfl-fme-perf.c
504
v = fme_read_perf_cntr_reg(base + VTD_SIP_CNTR);
drivers/fpga/dfl-fme-perf.c
505
return FIELD_GET(VTD_SIP_CNTR_EVNT_CNTR, v);
drivers/fpga/dfl-fme-perf.c
893
u64 v;
drivers/fpga/dfl-fme-perf.c
896
v = readq(base + FAB_CTRL);
drivers/fpga/dfl-fme-perf.c
898
if (FIELD_GET(FAB_PORT_FILTER, v) == FAB_PORT_FILTER_DISABLE)
drivers/fpga/dfl-fme-perf.c
901
priv->fab_port_id = FIELD_GET(FAB_PORT_ID, v);
drivers/fpga/dfl-fme-pr.c
79
u64 v;
drivers/fpga/dfl-fme-pr.c
93
v = readq(fme_hdr + FME_HDR_CAP);
drivers/fpga/dfl-fme-pr.c
94
if (port_pr.port_id >= FIELD_GET(FME_CAP_NUM_PORTS, v)) {
drivers/fpga/dfl-n3000-nios.c
420
u64 v;
drivers/fpga/dfl-n3000-nios.c
422
v = readq(base + N3000_NS_PARAM);
drivers/fpga/dfl-n3000-nios.c
425
if (FIELD_GET(N3000_NS_PARAM_CLK_POL, v))
drivers/fpga/dfl-n3000-nios.c
427
if (FIELD_GET(N3000_NS_PARAM_CLK_PHASE, v))
drivers/fpga/dfl-n3000-nios.c
430
pdata.num_chipselect = FIELD_GET(N3000_NS_PARAM_NUM_CS, v);
drivers/fpga/dfl-n3000-nios.c
432
SPI_BPW_RANGE_MASK(1, FIELD_GET(N3000_NS_PARAM_DATA_WIDTH, v));
drivers/fpga/dfl-n3000-nios.c
456
static int n3000_nios_poll_stat_timeout(void __iomem *base, u64 *v)
drivers/fpga/dfl-n3000-nios.c
469
*v = readq(base + N3000_NS_STAT);
drivers/fpga/dfl-n3000-nios.c
470
if (*v & N3000_NS_STAT_RW_VAL)
drivers/fpga/dfl-n3000-nios.c
481
u64 v;
drivers/fpga/dfl-n3000-nios.c
484
v = FIELD_PREP(N3000_NS_CTRL_CMD_MSK, N3000_NS_CTRL_CMD_WR) |
drivers/fpga/dfl-n3000-nios.c
487
writeq(v, nn->base + N3000_NS_CTRL);
drivers/fpga/dfl-n3000-nios.c
489
ret = n3000_nios_poll_stat_timeout(nn->base, &v);
drivers/fpga/dfl-n3000-nios.c
500
u64 v;
drivers/fpga/dfl-n3000-nios.c
503
v = FIELD_PREP(N3000_NS_CTRL_CMD_MSK, N3000_NS_CTRL_CMD_RD) |
drivers/fpga/dfl-n3000-nios.c
505
writeq(v, nn->base + N3000_NS_CTRL);
drivers/fpga/dfl-n3000-nios.c
507
ret = n3000_nios_poll_stat_timeout(nn->base, &v);
drivers/fpga/dfl-n3000-nios.c
511
*val = FIELD_GET(N3000_NS_STAT_RD_DATA, v);
drivers/fpga/dfl-pci.c
227
u64 v;
drivers/fpga/dfl-pci.c
249
v = readq(base + FME_HDR_CAP);
drivers/fpga/dfl-pci.c
250
port_num = FIELD_GET(FME_CAP_NUM_PORTS, v);
drivers/fpga/dfl-pci.c
255
v = readq(base + FME_HDR_PORT_OFST(i));
drivers/fpga/dfl-pci.c
258
if (!(v & FME_PORT_OFST_IMP))
drivers/fpga/dfl-pci.c
265
bar = FIELD_GET(FME_PORT_OFST_BAR_ID, v);
drivers/fpga/dfl-pci.c
266
offset = FIELD_GET(FME_PORT_OFST_DFH_OFST, v);
drivers/fpga/dfl.c
1033
u64 v;
drivers/fpga/dfl.c
1047
v = readq(base + PORT_UINT_CAP);
drivers/fpga/dfl.c
1048
ibase = FIELD_GET(PORT_UINT_CAP_FST_VECT, v);
drivers/fpga/dfl.c
1049
inr = FIELD_GET(PORT_UINT_CAP_INT_NUM, v);
drivers/fpga/dfl.c
1052
v = readq(base + PORT_ERROR_CAP);
drivers/fpga/dfl.c
1053
ibase = FIELD_GET(PORT_ERROR_CAP_INT_VECT, v);
drivers/fpga/dfl.c
1054
inr = FIELD_GET(PORT_ERROR_CAP_SUPP_INT, v);
drivers/fpga/dfl.c
1060
v = readq(base + FME_ERROR_CAP);
drivers/fpga/dfl.c
1061
ibase = FIELD_GET(FME_ERROR_CAP_INT_VECT, v);
drivers/fpga/dfl.c
1062
inr = FIELD_GET(FME_ERROR_CAP_SUPP_INT, v);
drivers/fpga/dfl.c
1121
u64 v, next;
drivers/fpga/dfl.c
1128
v = readq(dfh_base + DFHv1_PARAM_HDR + size);
drivers/fpga/dfl.c
1130
next = FIELD_GET(DFHv1_PARAM_HDR_NEXT_OFFSET, v);
drivers/fpga/dfl.c
1136
if (FIELD_GET(DFHv1_PARAM_HDR_NEXT_EOP, v))
drivers/fpga/dfl.c
1158
u64 v, addr_off;
drivers/fpga/dfl.c
1163
v = readq(binfo->ioaddr + ofst);
drivers/fpga/dfl.c
1164
revision = FIELD_GET(DFH_REVISION, v);
drivers/fpga/dfl.c
1165
dfh_ver = FIELD_GET(DFH_VERSION, v);
drivers/fpga/dfl.c
1167
size = size ? size : feature_size(v);
drivers/fpga/dfl.c
1168
fid = fid ? fid : feature_id(v);
drivers/fpga/dfl.c
1195
v = readq(binfo->ioaddr + ofst + DFHv1_CSR_ADDR);
drivers/fpga/dfl.c
1196
addr_off = FIELD_GET(DFHv1_CSR_ADDR_MASK, v);
drivers/fpga/dfl.c
1197
if (FIELD_GET(DFHv1_CSR_ADDR_REL, v))
drivers/fpga/dfl.c
1202
v = readq(binfo->ioaddr + ofst + DFHv1_CSR_SIZE_GRP);
drivers/fpga/dfl.c
1203
end = start + FIELD_GET(DFHv1_CSR_SIZE_GRP_SIZE, v) - 1;
drivers/fpga/dfl.c
1227
u64 v = readq(binfo->ioaddr + PORT_HDR_CAP);
drivers/fpga/dfl.c
1228
u32 size = FIELD_GET(PORT_CAP_MMIO_SIZE, v) << 10;
drivers/fpga/dfl.c
1294
u64 v;
drivers/fpga/dfl.c
1309
v = readq(binfo->ioaddr + DFH);
drivers/fpga/dfl.c
1310
id = FIELD_GET(DFH_ID, v);
drivers/fpga/dfl.c
1327
v = readq(binfo->ioaddr + NEXT_AFU);
drivers/fpga/dfl.c
1329
offset = FIELD_GET(NEXT_AFU_NEXT_DFH_OFST, v);
drivers/fpga/dfl.c
1359
u64 v;
drivers/fpga/dfl.c
1362
v = readq(binfo->ioaddr + ofst + DFH);
drivers/fpga/dfl.c
1363
type = FIELD_GET(DFH_TYPE, v);
drivers/fpga/dfl.c
1386
u64 v;
drivers/fpga/dfl.c
1403
v = readq(binfo->ioaddr + start - binfo->start + DFH);
drivers/fpga/dfl.c
1404
ofst = FIELD_GET(DFH_NEXT_HDR_OFST, v);
drivers/fpga/dfl.c
1407
if ((v & DFH_EOL) || !ofst)
drivers/fpga/dfl.c
1781
u64 v;
drivers/fpga/dfl.c
1785
v = readq(base + FME_HDR_PORT_OFST(port_id));
drivers/fpga/dfl.c
1787
v &= ~FME_PORT_OFST_ACC_CTRL;
drivers/fpga/dfl.c
1788
v |= FIELD_PREP(FME_PORT_OFST_ACC_CTRL,
drivers/fpga/dfl.c
1791
writeq(v, base + FME_HDR_PORT_OFST(port_id));
drivers/fpga/dfl.c
984
u64 v, next;
drivers/fpga/dfl.c
987
v = *params;
drivers/fpga/dfl.c
988
if (param_id == FIELD_GET(DFHv1_PARAM_HDR_ID, v))
drivers/fpga/dfl.c
991
if (FIELD_GET(DFHv1_PARAM_HDR_NEXT_EOP, v))
drivers/fpga/dfl.c
994
next = FIELD_GET(DFHv1_PARAM_HDR_NEXT_OFFSET, v);
drivers/fpga/dfl.h
477
u64 v = readq(base + DFH);
drivers/fpga/dfl.h
479
return (FIELD_GET(DFH_TYPE, v) == DFH_TYPE_FIU) &&
drivers/fpga/dfl.h
480
(FIELD_GET(DFH_ID, v) == DFH_ID_FIU_FME);
drivers/fpga/dfl.h
485
u64 v = readq(base + DFH);
drivers/fpga/dfl.h
487
return (FIELD_GET(DFH_TYPE, v) == DFH_TYPE_FIU) &&
drivers/fpga/dfl.h
488
(FIELD_GET(DFH_ID, v) == DFH_ID_FIU_PORT);
drivers/fsi/fsi-master-ast-cf.c
455
uint8_t v;
drivers/fsi/fsi-master-ast-cf.c
458
v = ioread8(master->sram + TRACEBUF + i);
drivers/fsi/fsi-master-ast-cf.c
459
p += sprintf(p, "%02x ", v);
drivers/fsi/fsi-master-ast-cf.c
460
if (((i % 16) == 15) || v == TR_END)
drivers/fsi/fsi-master-ast-cf.c
462
if (v == TR_END)
drivers/fsi/fsi-master-i2cr.c
39
static bool i2cr_check_parity32(u32 v, bool parity)
drivers/fsi/fsi-master-i2cr.c
44
if (v & (1u << i))
drivers/fsi/fsi-master-i2cr.c
51
static bool i2cr_check_parity64(u64 v)
drivers/fsi/fsi-master-i2cr.c
57
if (v & (1llu << i))
drivers/gpio/gpio-omap.c
1280
unsigned long cmd, void *v)
drivers/gpio/gpio-realtek-otto.c
281
u32 v;
drivers/gpio/gpio-realtek-otto.c
290
v = ctrl->bank_read(irq_cpu_mask);
drivers/gpio/gpio-realtek-otto.c
293
v |= BIT(line);
drivers/gpio/gpio-realtek-otto.c
295
v &= ~BIT(line);
drivers/gpio/gpio-realtek-otto.c
297
ctrl->bank_write(irq_cpu_mask, v);
drivers/gpio/gpio-tps65219.c
104
v = value ? mask : 0;
drivers/gpio/gpio-tps65219.c
107
TPS65219_REG_GENERAL_CONFIG, mask, v);
drivers/gpio/gpio-tps65219.c
99
int v, mask, bit;
drivers/gpio/gpio-tqmx86.c
45
#define TQMX86_GPIIC_CONFIG(i, v) ((v) << (2 * (i)))
drivers/gpio/gpiolib.c
5391
static void *gpiolib_seq_next(struct seq_file *s, void *v, loff_t *pos)
drivers/gpio/gpiolib.c
5394
struct gpio_device *gdev = v, *next;
drivers/gpio/gpiolib.c
5404
static void gpiolib_seq_stop(struct seq_file *s, void *v)
drivers/gpio/gpiolib.c
5416
static int gpiolib_seq_show(struct seq_file *s, void *v)
drivers/gpio/gpiolib.c
5419
struct gpio_device *gdev = v;
drivers/gpu/drm/amd/amdgpu/amdgpu.h
1311
uint32_t reg, uint32_t v,
drivers/gpu/drm/amd/amdgpu/amdgpu.h
1316
uint32_t reg, uint32_t v,
drivers/gpu/drm/amd/amdgpu/amdgpu.h
1320
uint32_t reg, uint32_t v, uint32_t xcc_id);
drivers/gpu/drm/amd/amdgpu/amdgpu.h
1360
#define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)
drivers/gpu/drm/amd/amdgpu/amdgpu.h
1363
#define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v), 0)
drivers/gpu/drm/amd/amdgpu/amdgpu.h
1366
#define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v))
drivers/gpu/drm/amd/amdgpu/amdgpu.h
1370
#define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0)
drivers/gpu/drm/amd/amdgpu/amdgpu.h
1371
#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
drivers/gpu/drm/amd/amdgpu/amdgpu.h
1372
#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
drivers/gpu/drm/amd/amdgpu/amdgpu.h
1374
#define WREG32_XCC(reg, v, inst) amdgpu_device_xcc_wreg(adev, (reg), (v), 0, inst)
drivers/gpu/drm/amd/amdgpu/amdgpu.h
1376
#define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
drivers/gpu/drm/amd/amdgpu/amdgpu.h
1378
#define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v))
drivers/gpu/drm/amd/amdgpu/amdgpu.h
1380
#define WREG32_PCIE_EXT(reg, v) adev->pcie_wreg_ext(adev, (reg), (v))
drivers/gpu/drm/amd/amdgpu/amdgpu.h
1382
#define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v))
drivers/gpu/drm/amd/amdgpu/amdgpu.h
1384
#define WREG64_PCIE_EXT(reg, v) adev->pcie_wreg64_ext(adev, (reg), (v))
drivers/gpu/drm/amd/amdgpu/amdgpu.h
1386
#define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
drivers/gpu/drm/amd/amdgpu/amdgpu.h
1388
#define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
drivers/gpu/drm/amd/amdgpu/amdgpu.h
1390
#define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
drivers/gpu/drm/amd/amdgpu/amdgpu.h
1392
#define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v))
drivers/gpu/drm/amd/amdgpu/amdgpu.h
1394
#define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v))
drivers/gpu/drm/amd/amdgpu/amdgpu.h
1396
#define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
drivers/gpu/drm/amd/amdgpu/amdgpu.h
1456
#define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
drivers/gpu/drm/amd/amdgpu/amdgpu.h
1463
#define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
drivers/gpu/drm/amd/amdgpu/amdgpu.h
1529
u32 reg, u32 v);
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
1000
writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
1003
adev->pcie_wreg(adev, reg * 4, v);
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
1006
trace_amdgpu_device_wreg(adev->pdev->device, reg, v);
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
1020
uint32_t reg, uint32_t v,
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
1030
return amdgpu_sriov_wreg(adev, reg, v, 0, 0, xcc_id);
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
1032
adev->pcie_wreg(adev, reg * 4, v);
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
1034
writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
1050
uint32_t reg, uint32_t v,
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
1065
amdgpu_virt_rlcg_reg_rw(adev, reg, v, rlcg_flag, GET_INST(GC, xcc_id));
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
1069
amdgpu_kiq_wreg(adev, reg, v, xcc_id);
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
1072
writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
1075
adev->pcie_wreg(adev, reg * 4, v);
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
1447
static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
1451
v);
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
1455
static void amdgpu_invalid_wreg_ext(struct amdgpu_device *adev, uint64_t reg, uint32_t v)
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
1459
v);
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
1498
static void amdgpu_invalid_wreg64(struct amdgpu_device *adev, uint32_t reg, uint64_t v)
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
1502
reg, v);
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
1506
static void amdgpu_invalid_wreg64_ext(struct amdgpu_device *adev, uint64_t reg, uint64_t v)
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
1510
reg, v);
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
1548
uint32_t reg, uint32_t v)
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
1552
reg, block, v);
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
7418
u32 reg, u32 v)
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
7428
WREG32(data, v);
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
987
uint32_t reg, uint32_t v,
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
997
amdgpu_kiq_wreg(adev, reg, v, 0);
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
1812
int v;
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
1842
for (v = 0; v < adev->vcn.num_vcn_inst; v++) {
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
1843
adev->vcn.inst[v].vcn_codec_disable_mask =
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
1844
le32_to_cpu(vcn_info->v1.instance_info[v].fuse_data.all_bits);
drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h
382
void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);
drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h
384
void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v);
drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h
398
#define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v))
drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h
400
#define WDOORBELL64(index, v) amdgpu_mm_wdoorbell64(adev, (index), (v))
drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell_mgr.c
103
void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v)
drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell_mgr.c
109
atomic64_set((atomic64_t *)(adev->doorbell.cpu_addr + index), v);
drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell_mgr.c
59
void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v)
drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell_mgr.c
65
writel(v, adev->doorbell.cpu_addr + index);
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
1138
void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, uint32_t xcc_id)
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
1152
amdgpu_mes_wreg(adev, reg, v, xcc_id);
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
1161
amdgpu_ring_emit_wreg(ring, reg, v);
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
621
void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, uint32_t xcc_id);
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
441
#define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
445
#define amdgpu_ring_emit_gfx_shadow(r, s, c, g, i, v) ((r)->funcs->emit_gfx_shadow((r), (s), (c), (g), (i), (v)))
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
447
#define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v))
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
448
#define amdgpu_ring_emit_reg_wait(r, d, v, m) (r)->funcs->emit_reg_wait((r), (d), (v), (m))
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
449
#define amdgpu_ring_emit_reg_write_reg_wait(r, d0, d1, v, m) (r)->funcs->emit_reg_write_reg_wait((r), (d0), (d1), (v), (m))
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
457
#define amdgpu_ring_reset(r, v, f) (r)->funcs->reset((r), (v), (f))
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
493
static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v)
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
495
ring->ring[ring->wptr++ & ring->buf_mask] = v;
drivers/gpu/drm/amd/amdgpu/amdgpu_utils.h
67
unsigned long v; \
drivers/gpu/drm/amd/amdgpu/amdgpu_utils.h
72
v = bitmap_read(c->bmap, NAME##_ATTR_START(cap), AMDGPU_CAP_ATTR_BITS); \
drivers/gpu/drm/amd/amdgpu/amdgpu_utils.h
73
*out = (enum amdgpu_cap_attr)v; \
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
1342
static u32 amdgpu_virt_rlcg_vfi_reg_rw(struct amdgpu_device *adev, u32 offset, u32 v, u32 flag, u32 xcc_id)
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
1388
data = v;
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
1469
u32 amdgpu_virt_rlcg_reg_rw(struct amdgpu_device *adev, u32 offset, u32 v, u32 flag, u32 xcc_id)
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
1483
return amdgpu_virt_rlcg_vfi_reg_rw(adev, offset, v, flag, xcc_id);
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
1512
writel(v, scratch_reg2);
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
1514
writel(v, ((void __iomem *)adev->rmmio) + (offset * 4));
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
1517
writel(v, scratch_reg3);
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
1519
writel(v, ((void __iomem *)adev->rmmio) + (offset * 4));
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
1527
writel(v, scratch_reg0);
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
487
u32 amdgpu_virt_rlcg_reg_rw(struct amdgpu_device *adev, u32 offset, u32 v, u32 flag, u32 xcc_id);
drivers/gpu/drm/amd/amdgpu/atombios_dp.c
207
u8 v = 0;
drivers/gpu/drm/amd/amdgpu/atombios_dp.c
220
if (this_v > v)
drivers/gpu/drm/amd/amdgpu/atombios_dp.c
221
v = this_v;
drivers/gpu/drm/amd/amdgpu/atombios_dp.c
226
if (v >= DP_VOLTAGE_MAX)
drivers/gpu/drm/amd/amdgpu/atombios_dp.c
227
v |= DP_TRAIN_MAX_SWING_REACHED;
drivers/gpu/drm/amd/amdgpu/atombios_dp.c
233
voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
drivers/gpu/drm/amd/amdgpu/atombios_dp.c
237
train_set[lane] = v | p;
drivers/gpu/drm/amd/amdgpu/cik.c
165
static void cik_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
drivers/gpu/drm/amd/amdgpu/cik.c
172
WREG32(mmPCIE_DATA, v);
drivers/gpu/drm/amd/amdgpu/cik.c
189
static void cik_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
drivers/gpu/drm/amd/amdgpu/cik.c
195
WREG32(mmSMC_IND_DATA_0, (v));
drivers/gpu/drm/amd/amdgpu/cik.c
211
static void cik_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
drivers/gpu/drm/amd/amdgpu/cik.c
217
WREG32(mmUVD_CTX_DATA, (v));
drivers/gpu/drm/amd/amdgpu/cik.c
233
static void cik_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
drivers/gpu/drm/amd/amdgpu/cik.c
239
WREG32(mmDIDT_IND_DATA, (v));
drivers/gpu/drm/amd/amdgpu/cikd.h
227
#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
187
u32 block_offset, u32 reg, u32 v)
drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
193
WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
150
u32 block_offset, u32 reg, u32 v)
drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
157
WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
138
u32 block_offset, u32 reg, u32 v)
drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
144
WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
8971
uint32_t v = secure ? FRAME_TMZ : 0;
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
8974
amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1));
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
6251
uint32_t v = secure ? FRAME_TMZ : 0;
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
6254
amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1));
drivers/gpu/drm/amd/amdgpu/gfx_v12_1_pkt.h
46
#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
5823
uint32_t v = secure ? FRAME_TMZ : 0;
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
5826
amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1));
drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
488
uint32_t v = 0;
drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
496
v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr);
drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
497
if ((v < ih->ring_size) && (v != ih->rptr))
drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
457
uint32_t v = 0;
drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
465
v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr);
drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
466
if ((v < ih->ring_size) && (v != ih->rptr))
drivers/gpu/drm/amd/amdgpu/ih_v7_0.c
481
uint32_t v = 0;
drivers/gpu/drm/amd/amdgpu/ih_v7_0.c
489
v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr);
drivers/gpu/drm/amd/amdgpu/ih_v7_0.c
490
if ((v < ih->ring_size) && (v != ih->rptr))
drivers/gpu/drm/amd/amdgpu/navi10_ih.c
464
uint32_t v = 0;
drivers/gpu/drm/amd/amdgpu/navi10_ih.c
472
v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr);
drivers/gpu/drm/amd/amdgpu/navi10_ih.c
473
if ((v < ih->ring_size) && (v != ih->rptr))
drivers/gpu/drm/amd/amdgpu/nv.c
293
static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
drivers/gpu/drm/amd/amdgpu/nv.c
302
WREG32(data, (v));
drivers/gpu/drm/amd/amdgpu/nvd.h
46
#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
drivers/gpu/drm/amd/amdgpu/si.c
1038
static void si_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
drivers/gpu/drm/amd/amdgpu/si.c
1045
WREG32(AMDGPU_PCIE_DATA, v);
drivers/gpu/drm/amd/amdgpu/si.c
1063
static void si_pciep_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
drivers/gpu/drm/amd/amdgpu/si.c
1070
WREG32(PCIE_PORT_DATA, (v));
drivers/gpu/drm/amd/amdgpu/si.c
1087
static void si_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
drivers/gpu/drm/amd/amdgpu/si.c
1093
WREG32(mmSMC_IND_DATA_0, (v));
drivers/gpu/drm/amd/amdgpu/si.c
1109
static void si_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
drivers/gpu/drm/amd/amdgpu/si.c
1115
WREG32(mmUVD_CTX_DATA, (v));
drivers/gpu/drm/amd/amdgpu/si.c
2392
static inline void si_pif_phy0_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
drivers/gpu/drm/amd/amdgpu/si.c
2398
WREG32(EVERGREEN_PIF_PHY0_DATA, (v));
drivers/gpu/drm/amd/amdgpu/si.c
2414
static inline void si_pif_phy1_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
drivers/gpu/drm/amd/amdgpu/si.c
2420
WREG32(EVERGREEN_PIF_PHY1_DATA, (v));
drivers/gpu/drm/amd/amdgpu/si.c
2628
u16 v;
drivers/gpu/drm/amd/amdgpu/si.c
2631
v = ffs(readrq) - 8;
drivers/gpu/drm/amd/amdgpu/si.c
2632
if ((v == 0) || (v == 6) || (v == 7))
drivers/gpu/drm/amd/amdgpu/sid.h
334
#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
drivers/gpu/drm/amd/amdgpu/soc15.c
255
static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
drivers/gpu/drm/amd/amdgpu/soc15.c
264
WREG32(data, (v));
drivers/gpu/drm/amd/amdgpu/soc15.c
283
static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
drivers/gpu/drm/amd/amdgpu/soc15.c
292
WREG32(data, (v));
drivers/gpu/drm/amd/amdgpu/soc15.c
308
static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
drivers/gpu/drm/amd/amdgpu/soc15.c
314
WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v));
drivers/gpu/drm/amd/amdgpu/soc15.c
330
static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
drivers/gpu/drm/amd/amdgpu/soc15.c
336
WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v));
drivers/gpu/drm/amd/amdgpu/soc15d.h
48
#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
drivers/gpu/drm/amd/amdgpu/soc21.c
239
static void soc21_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
drivers/gpu/drm/amd/amdgpu/soc21.c
248
WREG32(data, (v));
drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
112
u32 v;
drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
122
v = RREG32(mmVCE_RB_WPTR);
drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
124
v = RREG32(mmVCE_RB_WPTR2);
drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
126
v = RREG32(mmVCE_RB_WPTR3);
drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
131
return v;
drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
80
u32 v;
drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
90
v = RREG32(mmVCE_RB_RPTR);
drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
92
v = RREG32(mmVCE_RB_RPTR2);
drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
94
v = RREG32(mmVCE_RB_RPTR3);
drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
99
return v;
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
121
struct amdgpu_vcn_inst *v = &adev->vcn.inst[i];
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
126
for (j = 0; j < v->num_enc_rings; ++j)
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
127
fence[i] += amdgpu_fence_count_emitted(&v->ring_enc[j]);
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
131
!v->using_unified_queue) {
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
135
unlikely(atomic_read(&v->dpg_enc_submission_cnt)))
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
140
v->pause_dpg_mode(v, &new_state);
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
143
fence[i] += amdgpu_fence_count_emitted(&v->ring_dec);
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
160
struct amdgpu_vcn_inst *v = &adev->vcn.inst[ring->me];
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
176
!v->using_unified_queue) {
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
180
atomic_inc(&v->dpg_enc_submission_cnt);
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
186
for (i = 0; i < v->num_enc_rings; ++i)
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
187
fences += amdgpu_fence_count_emitted(&v->ring_enc[i]);
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
189
if (fences || atomic_read(&v->dpg_enc_submission_cnt))
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
194
v->pause_dpg_mode(v, &new_state);
drivers/gpu/drm/amd/amdgpu/vega10_ih.c
395
uint32_t v = 0;
drivers/gpu/drm/amd/amdgpu/vega10_ih.c
402
v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr);
drivers/gpu/drm/amd/amdgpu/vega10_ih.c
403
if ((v < ih->ring_size) && (v != ih->rptr))
drivers/gpu/drm/amd/amdgpu/vega20_ih.c
479
uint32_t v = 0;
drivers/gpu/drm/amd/amdgpu/vega20_ih.c
487
v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr);
drivers/gpu/drm/amd/amdgpu/vega20_ih.c
488
if ((v < ih->ring_size) && (v != ih->rptr))
drivers/gpu/drm/amd/amdgpu/vi.c
310
static void vi_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
drivers/gpu/drm/amd/amdgpu/vi.c
317
WREG32_NO_KIQ(mmPCIE_DATA, v);
drivers/gpu/drm/amd/amdgpu/vi.c
334
static void vi_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
drivers/gpu/drm/amd/amdgpu/vi.c
340
WREG32_NO_KIQ(mmSMC_IND_DATA_11, (v));
drivers/gpu/drm/amd/amdgpu/vi.c
360
static void cz_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
drivers/gpu/drm/amd/amdgpu/vi.c
366
WREG32(mmMP0PUB_IND_DATA, (v));
drivers/gpu/drm/amd/amdgpu/vi.c
382
static void vi_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
drivers/gpu/drm/amd/amdgpu/vi.c
388
WREG32(mmUVD_CTX_DATA, (v));
drivers/gpu/drm/amd/amdgpu/vi.c
404
static void vi_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
drivers/gpu/drm/amd/amdgpu/vi.c
410
WREG32(mmDIDT_IND_DATA, (v));
drivers/gpu/drm/amd/amdgpu/vi.c
426
static void vi_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
drivers/gpu/drm/amd/amdgpu/vi.c
432
WREG32(mmGC_CAC_IND_DATA, (v));
drivers/gpu/drm/amd/amdgpu/vid.h
103
#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
1366
&data->inits.v,
drivers/gpu/drm/amd/display/dc/dc_helper.c
759
bool dc_supports_vrr(const enum dce_version v)
drivers/gpu/drm/amd/display/dc/dc_helper.c
761
return v >= DCE_VERSION_8_0;
drivers/gpu/drm/amd/display/dc/dc_spl_translate.c
62
inits->v = dc_fixpt_from_int_dy(spl_inits->v_filter_init_int, spl_inits->v_filter_init_frac >> 5, 0, 19);
drivers/gpu/drm/amd/display/dc/dm_services.h
315
bool dc_supports_vrr(const enum dce_version v);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1000
v->voltage_level = v->voltage_level_without_immediate_flip;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1003
v->immediate_flip_supported = dcn_bw_yes;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1004
v->voltage_level = v->voltage_level_with_immediate_flip;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1006
v->dcfclk = v->dcfclk_per_state[v->voltage_level];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1007
v->fabric_and_dram_bandwidth = v->fabric_and_dram_bandwidth_per_state[v->voltage_level];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1009
v->required_dispclk_per_ratio[j] = v->required_dispclk[v->voltage_level][j];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1010
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1011
v->dpp_per_plane_per_ratio[j][k] = v->no_of_dpp[v->voltage_level][j][k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1013
v->dispclk_dppclk_support_per_ratio[j] = v->dispclk_dppclk_support[v->voltage_level][j];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1015
v->max_phyclk = v->phyclk_per_state[v->voltage_level];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1017
void display_pipe_configuration(struct dcn_bw_internal_vars *v)
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
102
v->vtaps[k] = v->acceptable_quality_vta_ps;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1024
v->total_number_of_active_dpp_per_ratio[j] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1025
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1026
v->total_number_of_active_dpp_per_ratio[j] = v->total_number_of_active_dpp_per_ratio[j] + v->dpp_per_plane_per_ratio[j][k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1029
if ((v->dispclk_dppclk_support_per_ratio[0] == dcn_bw_yes && v->dispclk_dppclk_support_per_ratio[1] == dcn_bw_no) || (v->dispclk_dppclk_support_per_ratio[0] == v->dispclk_dppclk_support_per_ratio[1] && (v->total_number_of_active_dpp_per_ratio[0] < v->total_number_of_active_dpp_per_ratio[1] || (((v->total_number_of_active_dpp_per_ratio[0] == v->total_number_of_active_dpp_per_ratio[1]) && v->required_dispclk_per_ratio[0] <= 0.5 * v->required_dispclk_per_ratio[1]))))) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1030
v->dispclk_dppclk_ratio = 1;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1031
v->final_error_message = v->error_message[0];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1034
v->dispclk_dppclk_ratio = 2;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1035
v->final_error_message = v->error_message[1];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1037
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1038
v->dpp_per_plane[k] = v->dpp_per_plane_per_ratio[v->dispclk_dppclk_ratio - 1][k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
104
if (v->source_pixel_format[k] == dcn_bw_rgb_sub_64 || v->source_pixel_format[k] == dcn_bw_rgb_sub_32 || v->source_pixel_format[k] == dcn_bw_rgb_sub_16) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1040
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1041
if (v->source_pixel_format[k] == dcn_bw_rgb_sub_64) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1042
v->byte_per_pix_dety = 8.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1043
v->byte_per_pix_detc = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1045
else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_32) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1046
v->byte_per_pix_dety = 4.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1047
v->byte_per_pix_detc = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1049
else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_16) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
105
v->vta_pschroma[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1050
v->byte_per_pix_dety = 2.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1051
v->byte_per_pix_detc = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1053
else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1054
v->byte_per_pix_dety = 1.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1055
v->byte_per_pix_detc = 2.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1058
v->byte_per_pix_dety = 4.0f / 3.0f;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1059
v->byte_per_pix_detc = 8.0f / 3.0f;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
106
v->hta_pschroma[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1061
if ((v->source_pixel_format[k] == dcn_bw_rgb_sub_64 || v->source_pixel_format[k] == dcn_bw_rgb_sub_32 || v->source_pixel_format[k] == dcn_bw_rgb_sub_16)) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1062
if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1063
v->read256_bytes_block_height_y = 1.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1065
else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_64) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1066
v->read256_bytes_block_height_y = 4.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1069
v->read256_bytes_block_height_y = 8.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1071
v->read256_bytes_block_width_y = 256.0 /dcn_bw_ceil2(v->byte_per_pix_dety, 1.0) / v->read256_bytes_block_height_y;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1072
v->read256_bytes_block_height_c = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1073
v->read256_bytes_block_width_c = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1076
if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1077
v->read256_bytes_block_height_y = 1.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1078
v->read256_bytes_block_height_c = 1.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1080
else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1081
v->read256_bytes_block_height_y = 16.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1082
v->read256_bytes_block_height_c = 8.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1085
v->read256_bytes_block_height_y = 8.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1086
v->read256_bytes_block_height_c = 8.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1088
v->read256_bytes_block_width_y = 256.0 /dcn_bw_ceil2(v->byte_per_pix_dety, 1.0) / v->read256_bytes_block_height_y;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1089
v->read256_bytes_block_width_c = 256.0 /dcn_bw_ceil2(v->byte_per_pix_detc, 2.0) / v->read256_bytes_block_height_c;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
109
if (v->ta_pscalculation == dcn_bw_override) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1091
if (v->source_scan[k] == dcn_bw_hor) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1092
v->maximum_swath_height_y = v->read256_bytes_block_height_y;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1093
v->maximum_swath_height_c = v->read256_bytes_block_height_c;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1096
v->maximum_swath_height_y = v->read256_bytes_block_width_y;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1097
v->maximum_swath_height_c = v->read256_bytes_block_width_c;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1099
if ((v->source_pixel_format[k] == dcn_bw_rgb_sub_64 || v->source_pixel_format[k] == dcn_bw_rgb_sub_32 || v->source_pixel_format[k] == dcn_bw_rgb_sub_16)) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
110
v->vta_pschroma[k] = v->override_vta_pschroma[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1100
if (v->source_surface_mode[k] == dcn_bw_sw_linear || (v->source_pixel_format[k] == dcn_bw_rgb_sub_64 && (v->source_surface_mode[k] == dcn_bw_sw_4_kb_s || v->source_surface_mode[k] == dcn_bw_sw_4_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_var_s || v->source_surface_mode[k] == dcn_bw_sw_var_s_x) && v->source_scan[k] == dcn_bw_hor)) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1101
v->minimum_swath_height_y = v->maximum_swath_height_y;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1104
v->minimum_swath_height_y = v->maximum_swath_height_y / 2.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1106
v->minimum_swath_height_c = v->maximum_swath_height_c;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1109
if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
111
v->hta_pschroma[k] = v->override_hta_pschroma[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1110
v->minimum_swath_height_y = v->maximum_swath_height_y;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1111
v->minimum_swath_height_c = v->maximum_swath_height_c;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1113
else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8 && v->source_scan[k] == dcn_bw_hor) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1114
v->minimum_swath_height_y = v->maximum_swath_height_y / 2.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1115
if (v->bug_forcing_luma_and_chroma_request_to_same_size_fixed == dcn_bw_yes) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1116
v->minimum_swath_height_c = v->maximum_swath_height_c;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1119
v->minimum_swath_height_c = v->maximum_swath_height_c / 2.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1122
else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_10 && v->source_scan[k] == dcn_bw_hor) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1123
v->minimum_swath_height_c = v->maximum_swath_height_c / 2.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1124
if (v->bug_forcing_luma_and_chroma_request_to_same_size_fixed == dcn_bw_yes) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1125
v->minimum_swath_height_y = v->maximum_swath_height_y;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1128
v->minimum_swath_height_y = v->maximum_swath_height_y / 2.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1132
v->minimum_swath_height_y = v->maximum_swath_height_y;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1133
v->minimum_swath_height_c = v->maximum_swath_height_c;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1136
if (v->source_scan[k] == dcn_bw_hor) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1137
v->swath_width = v->viewport_width[k] / v->dpp_per_plane[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
114
v->vta_pschroma[k] = v->acceptable_quality_vta_ps;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1140
v->swath_width = v->viewport_height[k] / v->dpp_per_plane[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1142
v->swath_width_granularity_y = 256.0 /dcn_bw_ceil2(v->byte_per_pix_dety, 1.0) / v->maximum_swath_height_y;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1143
v->rounded_up_max_swath_size_bytes_y = (dcn_bw_ceil2(v->swath_width - 1.0, v->swath_width_granularity_y) + v->swath_width_granularity_y) * v->byte_per_pix_dety * v->maximum_swath_height_y;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1144
if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_10) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1145
v->rounded_up_max_swath_size_bytes_y =dcn_bw_ceil2(v->rounded_up_max_swath_size_bytes_y, 256.0) + 256;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1147
if (v->maximum_swath_height_c > 0.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1148
v->swath_width_granularity_c = 256.0 /dcn_bw_ceil2(v->byte_per_pix_detc, 2.0) / v->maximum_swath_height_c;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1149
v->rounded_up_max_swath_size_bytes_c = (dcn_bw_ceil2(v->swath_width / 2.0 - 1.0, v->swath_width_granularity_c) + v->swath_width_granularity_c) * v->byte_per_pix_detc * v->maximum_swath_height_c;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
115
v->hta_pschroma[k] = v->acceptable_quality_hta_ps;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1150
if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_10) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1151
v->rounded_up_max_swath_size_bytes_c = dcn_bw_ceil2(v->rounded_up_max_swath_size_bytes_c, 256.0) + 256;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1154
if (v->rounded_up_max_swath_size_bytes_y + v->rounded_up_max_swath_size_bytes_c <= v->det_buffer_size_in_kbyte * 1024.0 / 2.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1155
v->swath_height_y[k] = v->maximum_swath_height_y;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1156
v->swath_height_c[k] = v->maximum_swath_height_c;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1159
v->swath_height_y[k] = v->minimum_swath_height_y;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1160
v->swath_height_c[k] = v->minimum_swath_height_c;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1162
if (v->swath_height_c[k] == 0.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1163
v->det_buffer_size_y[k] = v->det_buffer_size_in_kbyte * 1024.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1164
v->det_buffer_size_c[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1166
else if (v->swath_height_y[k] <= v->swath_height_c[k]) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1167
v->det_buffer_size_y[k] = v->det_buffer_size_in_kbyte * 1024.0 / 2.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1168
v->det_buffer_size_c[k] = v->det_buffer_size_in_kbyte * 1024.0 / 2.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1171
v->det_buffer_size_y[k] = v->det_buffer_size_in_kbyte * 1024.0 * 2.0 / 3.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1172
v->det_buffer_size_c[k] = v->det_buffer_size_in_kbyte * 1024.0 / 3.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1176
void dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(struct dcn_bw_internal_vars *v)
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1181
v->dispclk_with_ramping = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1182
v->dispclk_without_ramping = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1183
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1184
if (v->h_ratio[k] > 1.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1185
v->pscl_throughput[k] =dcn_bw_min2(v->max_dchub_topscl_throughput, v->max_pscl_tolb_throughput * v->h_ratio[k] /dcn_bw_ceil2(v->htaps[k] / 6.0, 1.0));
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1188
v->pscl_throughput[k] =dcn_bw_min2(v->max_dchub_topscl_throughput, v->max_pscl_tolb_throughput);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1190
v->dppclk_using_single_dpp_luma = v->pixel_clock[k] *dcn_bw_max3(v->vtaps[k] / 6.0 *dcn_bw_min2(1.0, v->h_ratio[k]), v->h_ratio[k] * v->v_ratio[k] / v->pscl_throughput[k], 1.0);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1191
if ((v->source_pixel_format[k] != dcn_bw_yuv420_sub_8 && v->source_pixel_format[k] != dcn_bw_yuv420_sub_10)) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1192
v->pscl_throughput_chroma[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1193
v->dppclk_using_single_dpp = v->dppclk_using_single_dpp_luma;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1196
if (v->h_ratio[k] > 1.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1197
v->pscl_throughput_chroma[k] =dcn_bw_min2(v->max_dchub_topscl_throughput, v->max_pscl_tolb_throughput * v->h_ratio[k] / 2.0 /dcn_bw_ceil2(v->hta_pschroma[k] / 6.0, 1.0));
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1200
v->pscl_throughput_chroma[k] =dcn_bw_min2(v->max_dchub_topscl_throughput, v->max_pscl_tolb_throughput);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1202
v->dppclk_using_single_dpp_chroma = v->pixel_clock[k] *dcn_bw_max3(v->vta_pschroma[k] / 6.0 *dcn_bw_min2(1.0, v->h_ratio[k] / 2.0), v->h_ratio[k] * v->v_ratio[k] / 4.0 / v->pscl_throughput_chroma[k], 1.0);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1203
v->dppclk_using_single_dpp =dcn_bw_max2(v->dppclk_using_single_dpp_luma, v->dppclk_using_single_dpp_chroma);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1205
if (v->odm_capable == dcn_bw_yes) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1206
v->dispclk_with_ramping =dcn_bw_max2(v->dispclk_with_ramping,dcn_bw_max2(v->dppclk_using_single_dpp / v->dpp_per_plane[k] * v->dispclk_dppclk_ratio, v->pixel_clock[k] / v->dpp_per_plane[k]) * (1.0 + v->downspreading / 100.0) * (1.0 + v->dispclk_ramping_margin / 100.0));
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1207
v->dispclk_without_ramping =dcn_bw_max2(v->dispclk_without_ramping,dcn_bw_max2(v->dppclk_using_single_dpp / v->dpp_per_plane[k] * v->dispclk_dppclk_ratio, v->pixel_clock[k] / v->dpp_per_plane[k]) * (1.0 + v->downspreading / 100.0));
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
121
void mode_support_and_system_configuration(struct dcn_bw_internal_vars *v)
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1210
v->dispclk_with_ramping =dcn_bw_max2(v->dispclk_with_ramping,dcn_bw_max2(v->dppclk_using_single_dpp / v->dpp_per_plane[k] * v->dispclk_dppclk_ratio, v->pixel_clock[k]) * (1.0 + v->downspreading / 100.0) * (1.0 + v->dispclk_ramping_margin / 100.0));
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1211
v->dispclk_without_ramping =dcn_bw_max2(v->dispclk_without_ramping,dcn_bw_max2(v->dppclk_using_single_dpp / v->dpp_per_plane[k] * v->dispclk_dppclk_ratio, v->pixel_clock[k]) * (1.0 + v->downspreading / 100.0));
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1214
if (v->dispclk_without_ramping > v->max_dispclk[number_of_states]) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1215
v->dispclk = v->dispclk_without_ramping;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1217
else if (v->dispclk_with_ramping > v->max_dispclk[number_of_states]) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1218
v->dispclk = v->max_dispclk[number_of_states];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1221
v->dispclk = v->dispclk_with_ramping;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1223
v->dppclk = v->dispclk / v->dispclk_dppclk_ratio;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1226
v->return_bandwidth_to_dcn =dcn_bw_min2(v->return_bus_width * v->dcfclk, v->fabric_and_dram_bandwidth * 1000.0 * v->percent_of_ideal_drambw_received_after_urg_latency / 100.0);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1227
v->dcc_enabled_any_plane = dcn_bw_no;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1228
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1229
if (v->dcc_enable[k] == dcn_bw_yes) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1230
v->dcc_enabled_any_plane = dcn_bw_yes;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1233
v->return_bw = v->return_bandwidth_to_dcn;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1234
if (v->dcc_enabled_any_plane == dcn_bw_yes && v->return_bandwidth_to_dcn > v->dcfclk * v->return_bus_width / 4.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1235
v->return_bw =dcn_bw_min2(v->return_bw, v->return_bandwidth_to_dcn * 4.0 * (1.0 - v->urgent_latency / ((v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0 / (v->return_bandwidth_to_dcn - v->dcfclk * v->return_bus_width / 4.0) + v->urgent_latency)));
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1237
v->critical_compression = 2.0 * v->return_bus_width * v->dcfclk * v->urgent_latency / (v->return_bandwidth_to_dcn * v->urgent_latency + (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1238
if (v->dcc_enabled_any_plane == dcn_bw_yes && v->critical_compression > 1.0 && v->critical_compression < 4.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1239
v->return_bw =dcn_bw_min2(v->return_bw, dcn_bw_pow(4.0 * v->return_bandwidth_to_dcn * (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0 * v->return_bus_width * v->dcfclk * v->urgent_latency / (v->return_bandwidth_to_dcn * v->urgent_latency + (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0), 2));
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1241
v->return_bandwidth_to_dcn =dcn_bw_min2(v->return_bus_width * v->dcfclk, v->fabric_and_dram_bandwidth * 1000.0);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1242
if (v->dcc_enabled_any_plane == dcn_bw_yes && v->return_bandwidth_to_dcn > v->dcfclk * v->return_bus_width / 4.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1243
v->return_bw =dcn_bw_min2(v->return_bw, v->return_bandwidth_to_dcn * 4.0 * (1.0 - v->urgent_latency / ((v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0 / (v->return_bandwidth_to_dcn - v->dcfclk * v->return_bus_width / 4.0) + v->urgent_latency)));
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1245
v->critical_compression = 2.0 * v->return_bus_width * v->dcfclk * v->urgent_latency / (v->return_bandwidth_to_dcn * v->urgent_latency + (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1246
if (v->dcc_enabled_any_plane == dcn_bw_yes && v->critical_compression > 1.0 && v->critical_compression < 4.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1247
v->return_bw =dcn_bw_min2(v->return_bw, dcn_bw_pow(4.0 * v->return_bandwidth_to_dcn * (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0 * v->return_bus_width * v->dcfclk * v->urgent_latency / (v->return_bandwidth_to_dcn * v->urgent_latency + (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0), 2));
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1249
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1250
if (v->source_scan[k] == dcn_bw_hor) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1251
v->swath_width_y[k] = v->viewport_width[k] / v->dpp_per_plane[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1254
v->swath_width_y[k] = v->viewport_height[k] / v->dpp_per_plane[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1257
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1258
if (v->source_pixel_format[k] == dcn_bw_rgb_sub_64) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1259
v->byte_per_pixel_dety[k] = 8.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1260
v->byte_per_pixel_detc[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1262
else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_32) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1263
v->byte_per_pixel_dety[k] = 4.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1264
v->byte_per_pixel_detc[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1266
else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_16) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1267
v->byte_per_pixel_dety[k] = 2.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1268
v->byte_per_pixel_detc[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1270
else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1271
v->byte_per_pixel_dety[k] = 1.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1272
v->byte_per_pixel_detc[k] = 2.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1275
v->byte_per_pixel_dety[k] = 4.0f / 3.0f;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1276
v->byte_per_pixel_detc[k] = 8.0f / 3.0f;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1279
v->total_data_read_bandwidth = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1280
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1281
v->read_bandwidth_plane_luma[k] = v->swath_width_y[k] * v->dpp_per_plane[k] *dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) / (v->htotal[k] / v->pixel_clock[k]) * v->v_ratio[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1282
v->read_bandwidth_plane_chroma[k] = v->swath_width_y[k] / 2.0 * v->dpp_per_plane[k] *dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0) / (v->htotal[k] / v->pixel_clock[k]) * v->v_ratio[k] / 2.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1283
v->total_data_read_bandwidth = v->total_data_read_bandwidth + v->read_bandwidth_plane_luma[k] + v->read_bandwidth_plane_chroma[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1285
v->total_active_dpp = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1286
v->total_dcc_active_dpp = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1287
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1288
v->total_active_dpp = v->total_active_dpp + v->dpp_per_plane[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1289
if (v->dcc_enable[k] == dcn_bw_yes) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1290
v->total_dcc_active_dpp = v->total_dcc_active_dpp + v->dpp_per_plane[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1293
v->urgent_round_trip_and_out_of_order_latency = (v->round_trip_ping_latency_cycles + 32.0) / v->dcfclk + v->urgent_out_of_order_return_per_channel * v->number_of_channels / v->return_bw;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1294
v->last_pixel_of_line_extra_watermark = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1295
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1296
if (v->v_ratio[k] <= 1.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1297
v->display_pipe_line_delivery_time_luma[k] = v->swath_width_y[k] * v->dpp_per_plane[k] / v->h_ratio[k] / v->pixel_clock[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
130
v->scale_ratio_support = dcn_bw_yes;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1300
v->display_pipe_line_delivery_time_luma[k] = v->swath_width_y[k] / v->pscl_throughput[k] / v->dppclk;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1302
v->data_fabric_line_delivery_time_luma = v->swath_width_y[k] * v->swath_height_y[k] *dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) / (v->return_bw * v->read_bandwidth_plane_luma[k] / v->dpp_per_plane[k] / v->total_data_read_bandwidth);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1303
v->last_pixel_of_line_extra_watermark =dcn_bw_max2(v->last_pixel_of_line_extra_watermark, v->data_fabric_line_delivery_time_luma - v->display_pipe_line_delivery_time_luma[k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1304
if (v->byte_per_pixel_detc[k] == 0.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1305
v->display_pipe_line_delivery_time_chroma[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1308
if (v->v_ratio[k] / 2.0 <= 1.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1309
v->display_pipe_line_delivery_time_chroma[k] = v->swath_width_y[k] / 2.0 * v->dpp_per_plane[k] / (v->h_ratio[k] / 2.0) / v->pixel_clock[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
131
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1312
v->display_pipe_line_delivery_time_chroma[k] = v->swath_width_y[k] / 2.0 / v->pscl_throughput_chroma[k] / v->dppclk;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1314
v->data_fabric_line_delivery_time_chroma = v->swath_width_y[k] / 2.0 * v->swath_height_c[k] *dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0) / (v->return_bw * v->read_bandwidth_plane_chroma[k] / v->dpp_per_plane[k] / v->total_data_read_bandwidth);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1315
v->last_pixel_of_line_extra_watermark =dcn_bw_max2(v->last_pixel_of_line_extra_watermark, v->data_fabric_line_delivery_time_chroma - v->display_pipe_line_delivery_time_chroma[k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1318
v->urgent_extra_latency = v->urgent_round_trip_and_out_of_order_latency + (v->total_active_dpp * v->pixel_chunk_size_in_kbyte + v->total_dcc_active_dpp * v->meta_chunk_size) * 1024.0 / v->return_bw;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1319
if (v->pte_enable == dcn_bw_yes) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
132
if (v->h_ratio[k] > v->max_hscl_ratio || v->v_ratio[k] > v->max_vscl_ratio || v->h_ratio[k] > v->htaps[k] || v->v_ratio[k] > v->vtaps[k] || (v->source_pixel_format[k] != dcn_bw_rgb_sub_64 && v->source_pixel_format[k] != dcn_bw_rgb_sub_32 && v->source_pixel_format[k] != dcn_bw_rgb_sub_16 && (v->h_ratio[k] / 2.0 > v->hta_pschroma[k] || v->v_ratio[k] / 2.0 > v->vta_pschroma[k]))) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1320
v->urgent_extra_latency = v->urgent_extra_latency + v->total_active_dpp * v->pte_chunk_size * 1024.0 / v->return_bw;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1322
v->urgent_watermark = v->urgent_latency + v->last_pixel_of_line_extra_watermark + v->urgent_extra_latency;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1323
v->ptemeta_urgent_watermark = v->urgent_watermark + 2.0 * v->urgent_latency;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1326
v->dram_clock_change_watermark = v->dram_clock_change_latency + v->urgent_watermark;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1327
v->total_active_writeback = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1328
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1329
if (v->output[k] == dcn_bw_writeback) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
133
v->scale_ratio_support = dcn_bw_no;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1330
v->total_active_writeback = v->total_active_writeback + 1.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1333
if (v->total_active_writeback <= 1.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1334
v->writeback_dram_clock_change_watermark = v->dram_clock_change_latency + v->write_back_latency;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1337
v->writeback_dram_clock_change_watermark = v->dram_clock_change_latency + v->write_back_latency + v->writeback_chunk_size * 1024.0 / 32.0 / v->socclk;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1341
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1342
v->lines_in_dety[k] = v->det_buffer_size_y[k] / v->byte_per_pixel_dety[k] / v->swath_width_y[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1343
v->lines_in_dety_rounded_down_to_swath[k] =dcn_bw_floor2(v->lines_in_dety[k], v->swath_height_y[k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1344
v->full_det_buffering_time_y[k] = v->lines_in_dety_rounded_down_to_swath[k] * (v->htotal[k] / v->pixel_clock[k]) / v->v_ratio[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1345
if (v->byte_per_pixel_detc[k] > 0.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1346
v->lines_in_detc[k] = v->det_buffer_size_c[k] / v->byte_per_pixel_detc[k] / (v->swath_width_y[k] / 2.0);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1347
v->lines_in_detc_rounded_down_to_swath[k] =dcn_bw_floor2(v->lines_in_detc[k], v->swath_height_c[k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1348
v->full_det_buffering_time_c[k] = v->lines_in_detc_rounded_down_to_swath[k] * (v->htotal[k] / v->pixel_clock[k]) / (v->v_ratio[k] / 2.0);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1351
v->lines_in_detc[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1352
v->lines_in_detc_rounded_down_to_swath[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1353
v->full_det_buffering_time_c[k] = 999999.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1356
v->min_full_det_buffering_time = 999999.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1357
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1358
if (v->full_det_buffering_time_y[k] < v->min_full_det_buffering_time) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1359
v->min_full_det_buffering_time = v->full_det_buffering_time_y[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1360
v->frame_time_for_min_full_det_buffering_time = v->vtotal[k] * v->htotal[k] / v->pixel_clock[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1362
if (v->full_det_buffering_time_c[k] < v->min_full_det_buffering_time) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1363
v->min_full_det_buffering_time = v->full_det_buffering_time_c[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1364
v->frame_time_for_min_full_det_buffering_time = v->vtotal[k] * v->htotal[k] / v->pixel_clock[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1367
v->average_read_bandwidth_gbyte_per_second = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1368
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1369
if (v->dcc_enable[k] == dcn_bw_yes) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1370
v->average_read_bandwidth_gbyte_per_second = v->average_read_bandwidth_gbyte_per_second + v->read_bandwidth_plane_luma[k] / v->dcc_rate[k] / 1000.0 + v->read_bandwidth_plane_chroma[k] / v->dcc_rate[k] / 1000.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1373
v->average_read_bandwidth_gbyte_per_second = v->average_read_bandwidth_gbyte_per_second + v->read_bandwidth_plane_luma[k] / 1000.0 + v->read_bandwidth_plane_chroma[k] / 1000.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1375
if (v->dcc_enable[k] == dcn_bw_yes) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1376
v->average_read_bandwidth_gbyte_per_second = v->average_read_bandwidth_gbyte_per_second + v->read_bandwidth_plane_luma[k] / 1000.0 / 256.0 + v->read_bandwidth_plane_chroma[k] / 1000.0 / 256.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1378
if (v->pte_enable == dcn_bw_yes) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1379
v->average_read_bandwidth_gbyte_per_second = v->average_read_bandwidth_gbyte_per_second + v->read_bandwidth_plane_luma[k] / 1000.0 / 512.0 + v->read_bandwidth_plane_chroma[k] / 1000.0 / 512.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
138
v->source_format_pixel_and_scan_support = dcn_bw_yes;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1382
v->part_of_burst_that_fits_in_rob =dcn_bw_min2(v->min_full_det_buffering_time * v->total_data_read_bandwidth, v->rob_buffer_size_in_kbyte * 1024.0 * v->total_data_read_bandwidth / (v->average_read_bandwidth_gbyte_per_second * 1000.0));
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1383
v->stutter_burst_time = v->part_of_burst_that_fits_in_rob * (v->average_read_bandwidth_gbyte_per_second * 1000.0) / v->total_data_read_bandwidth / v->return_bw + (v->min_full_det_buffering_time * v->total_data_read_bandwidth - v->part_of_burst_that_fits_in_rob) / (v->dcfclk * 64.0);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1384
if (v->total_active_writeback == 0.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1385
v->stutter_efficiency_not_including_vblank = (1.0 - (v->sr_exit_time + v->stutter_burst_time) / v->min_full_det_buffering_time) * 100.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1388
v->stutter_efficiency_not_including_vblank = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
139
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1390
v->smallest_vblank = 999999.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1391
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1392
if (v->synchronized_vblank == dcn_bw_yes || v->number_of_active_planes == 1) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1393
v->v_blank_time = (v->vtotal[k] - v->vactive[k]) * v->htotal[k] / v->pixel_clock[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1396
v->v_blank_time = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1398
v->smallest_vblank =dcn_bw_min2(v->smallest_vblank, v->v_blank_time);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
140
if ((v->source_surface_mode[k] == dcn_bw_sw_linear && v->source_scan[k] != dcn_bw_hor) || ((v->source_surface_mode[k] == dcn_bw_sw_4_kb_d || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d_x || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_x || v->source_surface_mode[k] == dcn_bw_sw_var_d || v->source_surface_mode[k] == dcn_bw_sw_var_d_x) && v->source_pixel_format[k] != dcn_bw_rgb_sub_64)) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1400
v->stutter_efficiency = (v->stutter_efficiency_not_including_vblank / 100.0 * (v->frame_time_for_min_full_det_buffering_time - v->smallest_vblank) + v->smallest_vblank) / v->frame_time_for_min_full_det_buffering_time * 100.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1403
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1404
if (v->byte_per_pixel_detc[k] > 0.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1405
v->dcfclk_deep_sleep_per_plane[k] =dcn_bw_max2(1.1 * v->swath_width_y[k] *dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) / 32.0 / v->display_pipe_line_delivery_time_luma[k], 1.1 * v->swath_width_y[k] / 2.0 *dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0) / 32.0 / v->display_pipe_line_delivery_time_chroma[k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1408
v->dcfclk_deep_sleep_per_plane[k] = 1.1 * v->swath_width_y[k] *dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) / 64.0 / v->display_pipe_line_delivery_time_luma[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
141
v->source_format_pixel_and_scan_support = dcn_bw_no;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1410
v->dcfclk_deep_sleep_per_plane[k] =dcn_bw_max2(v->dcfclk_deep_sleep_per_plane[k], v->pixel_clock[k] / 16.0);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1412
v->dcf_clk_deep_sleep = 8.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1413
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1414
v->dcf_clk_deep_sleep =dcn_bw_max2(v->dcf_clk_deep_sleep, v->dcfclk_deep_sleep_per_plane[k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1418
v->stutter_exit_watermark = v->sr_exit_time + v->last_pixel_of_line_extra_watermark + v->urgent_extra_latency + 10.0 / v->dcf_clk_deep_sleep;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1419
v->stutter_enter_plus_exit_watermark = v->sr_enter_plus_exit_time + v->last_pixel_of_line_extra_watermark + v->urgent_extra_latency;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1422
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1423
v->effective_det_plus_lb_lines_luma =dcn_bw_floor2(v->lines_in_dety[k] +dcn_bw_min2(v->lines_in_dety[k] * v->dppclk * v->byte_per_pixel_dety[k] * v->pscl_throughput[k] / (v->return_bw / v->dpp_per_plane[k]), v->effective_lb_latency_hiding_source_lines_luma), v->swath_height_y[k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1424
v->urgent_latency_support_us_luma = v->effective_det_plus_lb_lines_luma * (v->htotal[k] / v->pixel_clock[k]) / v->v_ratio[k] - v->effective_det_plus_lb_lines_luma * v->swath_width_y[k] * v->byte_per_pixel_dety[k] / (v->return_bw / v->dpp_per_plane[k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1425
if (v->byte_per_pixel_detc[k] > 0.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1426
v->effective_det_plus_lb_lines_chroma =dcn_bw_floor2(v->lines_in_detc[k] +dcn_bw_min2(v->lines_in_detc[k] * v->dppclk * v->byte_per_pixel_detc[k] * v->pscl_throughput_chroma[k] / (v->return_bw / v->dpp_per_plane[k]), v->effective_lb_latency_hiding_source_lines_chroma), v->swath_height_c[k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1427
v->urgent_latency_support_us_chroma = v->effective_det_plus_lb_lines_chroma * (v->htotal[k] / v->pixel_clock[k]) / (v->v_ratio[k] / 2.0) - v->effective_det_plus_lb_lines_chroma * (v->swath_width_y[k] / 2.0) * v->byte_per_pixel_detc[k] / (v->return_bw / v->dpp_per_plane[k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1428
v->urgent_latency_support_us[k] =dcn_bw_min2(v->urgent_latency_support_us_luma, v->urgent_latency_support_us_chroma);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1431
v->urgent_latency_support_us[k] = v->urgent_latency_support_us_luma;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1434
v->min_urgent_latency_support_us = 999999.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1435
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1436
v->min_urgent_latency_support_us =dcn_bw_min2(v->min_urgent_latency_support_us, v->urgent_latency_support_us[k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1440
v->non_urgent_latency_tolerance = v->min_urgent_latency_support_us - v->urgent_watermark;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1443
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1444
if ((v->source_pixel_format[k] == dcn_bw_rgb_sub_64 || v->source_pixel_format[k] == dcn_bw_rgb_sub_32 || v->source_pixel_format[k] == dcn_bw_rgb_sub_16)) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1445
if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1446
v->block_height256_bytes_y = 1.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1448
else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_64) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1449
v->block_height256_bytes_y = 4.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1452
v->block_height256_bytes_y = 8.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1454
v->block_height256_bytes_c = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1457
if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1458
v->block_height256_bytes_y = 1.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1459
v->block_height256_bytes_c = 1.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
146
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1461
else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1462
v->block_height256_bytes_y = 16.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1463
v->block_height256_bytes_c = 8.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1466
v->block_height256_bytes_y = 8.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1467
v->block_height256_bytes_c = 8.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
147
if (v->source_scan[k] == dcn_bw_hor) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1470
if (v->dcc_enable[k] == dcn_bw_yes) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1471
v->meta_request_width_y = 64.0 * 256.0 /dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) / (8.0 * v->block_height256_bytes_y);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1472
v->meta_surf_width_y =dcn_bw_ceil2(v->swath_width_y[k] - 1.0, v->meta_request_width_y) + v->meta_request_width_y;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1473
v->meta_surf_height_y =dcn_bw_ceil2(v->viewport_height[k] - 1.0, 8.0 * v->block_height256_bytes_y) + 8.0 * v->block_height256_bytes_y;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1474
if (v->pte_enable == dcn_bw_yes) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1475
v->meta_pte_bytes_frame_y = (dcn_bw_ceil2((v->meta_surf_width_y * v->meta_surf_height_y *dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) / 256.0 - 4096.0) / 8.0 / 4096.0, 1.0) + 1) * 64.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1478
v->meta_pte_bytes_frame_y = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
148
v->swath_width_ysingle_dpp[k] = v->viewport_width[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1480
if (v->source_scan[k] == dcn_bw_hor) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1481
v->meta_row_byte_y = v->meta_surf_width_y * 8.0 * v->block_height256_bytes_y *dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) / 256.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1484
v->meta_row_byte_y = v->meta_surf_height_y * v->meta_request_width_y *dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) / 256.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1488
v->meta_pte_bytes_frame_y = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1489
v->meta_row_byte_y = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1491
if (v->pte_enable == dcn_bw_yes) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1492
if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1493
v->macro_tile_size_byte_y = 256.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1494
v->macro_tile_height_y = 1.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1496
else if (v->source_surface_mode[k] == dcn_bw_sw_4_kb_s || v->source_surface_mode[k] == dcn_bw_sw_4_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d_x) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1497
v->macro_tile_size_byte_y = 4096.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1498
v->macro_tile_height_y = 4.0 * v->block_height256_bytes_y;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1500
else if (v->source_surface_mode[k] == dcn_bw_sw_64_kb_s || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_x) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1501
v->macro_tile_size_byte_y = 64.0 * 1024;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1502
v->macro_tile_height_y = 16.0 * v->block_height256_bytes_y;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1505
v->macro_tile_size_byte_y = 256.0 * 1024;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1506
v->macro_tile_height_y = 32.0 * v->block_height256_bytes_y;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1508
if (v->macro_tile_size_byte_y <= 65536.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1509
v->pixel_pte_req_height_y = v->macro_tile_height_y;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
151
v->swath_width_ysingle_dpp[k] = v->viewport_height[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1512
v->pixel_pte_req_height_y = 16.0 * v->block_height256_bytes_y;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1514
v->pixel_pte_req_width_y = 4096.0 /dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) / v->pixel_pte_req_height_y * 8;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1515
if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1516
v->pixel_pte_bytes_per_row_y = 64.0 * (dcn_bw_ceil2((v->swath_width_y[k] *dcn_bw_min2(128.0, dcn_bw_pow(2.0,dcn_bw_floor2(dcn_bw_log(v->pte_buffer_size_in_requests * v->pixel_pte_req_width_y / v->swath_width_y[k], 2.0), 1.0))) - 1.0) / v->pixel_pte_req_width_y, 1.0) + 1);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1518
else if (v->source_scan[k] == dcn_bw_hor) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1519
v->pixel_pte_bytes_per_row_y = 64.0 * (dcn_bw_ceil2((v->swath_width_y[k] - 1.0) / v->pixel_pte_req_width_y, 1.0) + 1);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1522
v->pixel_pte_bytes_per_row_y = 64.0 * (dcn_bw_ceil2((v->viewport_height[k] - 1.0) / v->pixel_pte_req_height_y, 1.0) + 1);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1526
v->pixel_pte_bytes_per_row_y = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1528
if ((v->source_pixel_format[k] != dcn_bw_rgb_sub_64 && v->source_pixel_format[k] != dcn_bw_rgb_sub_32 && v->source_pixel_format[k] != dcn_bw_rgb_sub_16)) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1529
if (v->dcc_enable[k] == dcn_bw_yes) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
153
if (v->source_pixel_format[k] == dcn_bw_rgb_sub_64) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1530
v->meta_request_width_c = 64.0 * 256.0 /dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0) / (8.0 * v->block_height256_bytes_c);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1531
v->meta_surf_width_c =dcn_bw_ceil2(v->swath_width_y[k] / 2.0 - 1.0, v->meta_request_width_c) + v->meta_request_width_c;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1532
v->meta_surf_height_c =dcn_bw_ceil2(v->viewport_height[k] / 2.0 - 1.0, 8.0 * v->block_height256_bytes_c) + 8.0 * v->block_height256_bytes_c;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1533
if (v->pte_enable == dcn_bw_yes) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1534
v->meta_pte_bytes_frame_c = (dcn_bw_ceil2((v->meta_surf_width_c * v->meta_surf_height_c *dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0) / 256.0 - 4096.0) / 8.0 / 4096.0, 1.0) + 1) * 64.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1537
v->meta_pte_bytes_frame_c = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1539
if (v->source_scan[k] == dcn_bw_hor) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
154
v->byte_per_pixel_in_dety[k] = 8.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1540
v->meta_row_byte_c = v->meta_surf_width_c * 8.0 * v->block_height256_bytes_c *dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0) / 256.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1543
v->meta_row_byte_c = v->meta_surf_height_c * v->meta_request_width_c *dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0) / 256.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1547
v->meta_pte_bytes_frame_c = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1548
v->meta_row_byte_c = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
155
v->byte_per_pixel_in_detc[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1550
if (v->pte_enable == dcn_bw_yes) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1551
if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1552
v->macro_tile_size_bytes_c = 256.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1553
v->macro_tile_height_c = 1.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1555
else if (v->source_surface_mode[k] == dcn_bw_sw_4_kb_s || v->source_surface_mode[k] == dcn_bw_sw_4_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d_x) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1556
v->macro_tile_size_bytes_c = 4096.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1557
v->macro_tile_height_c = 4.0 * v->block_height256_bytes_c;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1559
else if (v->source_surface_mode[k] == dcn_bw_sw_64_kb_s || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_x) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1560
v->macro_tile_size_bytes_c = 64.0 * 1024;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1561
v->macro_tile_height_c = 16.0 * v->block_height256_bytes_c;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1564
v->macro_tile_size_bytes_c = 256.0 * 1024;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1565
v->macro_tile_height_c = 32.0 * v->block_height256_bytes_c;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1567
if (v->macro_tile_size_bytes_c <= 65536.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1568
v->pixel_pte_req_height_c = v->macro_tile_height_c;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
157
else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_32) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1571
v->pixel_pte_req_height_c = 16.0 * v->block_height256_bytes_c;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1573
v->pixel_pte_req_width_c = 4096.0 /dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0) / v->pixel_pte_req_height_c * 8;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1574
if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1575
v->pixel_pte_bytes_per_row_c = 64.0 * (dcn_bw_ceil2((v->swath_width_y[k] / 2.0 * dcn_bw_min2(128.0, dcn_bw_pow(2.0,dcn_bw_floor2(dcn_bw_log(v->pte_buffer_size_in_requests * v->pixel_pte_req_width_c / (v->swath_width_y[k] / 2.0), 2.0), 1.0))) - 1.0) / v->pixel_pte_req_width_c, 1.0) + 1);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1577
else if (v->source_scan[k] == dcn_bw_hor) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1578
v->pixel_pte_bytes_per_row_c = 64.0 * (dcn_bw_ceil2((v->swath_width_y[k] / 2.0 - 1.0) / v->pixel_pte_req_width_c, 1.0) + 1);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
158
v->byte_per_pixel_in_dety[k] = 4.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1581
v->pixel_pte_bytes_per_row_c = 64.0 * (dcn_bw_ceil2((v->viewport_height[k] / 2.0 - 1.0) / v->pixel_pte_req_height_c, 1.0) + 1);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1585
v->pixel_pte_bytes_per_row_c = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1589
v->pixel_pte_bytes_per_row_c = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
159
v->byte_per_pixel_in_detc[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1590
v->meta_pte_bytes_frame_c = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1591
v->meta_row_byte_c = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1593
v->pixel_pte_bytes_per_row[k] = v->pixel_pte_bytes_per_row_y + v->pixel_pte_bytes_per_row_c;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1594
v->meta_pte_bytes_frame[k] = v->meta_pte_bytes_frame_y + v->meta_pte_bytes_frame_c;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1595
v->meta_row_byte[k] = v->meta_row_byte_y + v->meta_row_byte_c;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1596
v->v_init_pre_fill_y[k] =dcn_bw_floor2((v->v_ratio[k] + v->vtaps[k] + 1.0 + v->interlace_output[k] * 0.5 * v->v_ratio[k]) / 2.0, 1.0);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1597
v->max_num_swath_y[k] =dcn_bw_ceil2((v->v_init_pre_fill_y[k] - 1.0) / v->swath_height_y[k], 1.0) + 1;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1598
if (v->v_init_pre_fill_y[k] > 1.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1599
v->max_partial_swath_y =dcn_bw_mod((v->v_init_pre_fill_y[k] - 2.0), v->swath_height_y[k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1602
v->max_partial_swath_y =dcn_bw_mod((v->v_init_pre_fill_y[k] + v->swath_height_y[k] - 2.0), v->swath_height_y[k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1604
v->max_partial_swath_y =dcn_bw_max2(1.0, v->max_partial_swath_y);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1605
v->prefetch_source_lines_y[k] = v->max_num_swath_y[k] * v->swath_height_y[k] + v->max_partial_swath_y;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1606
if ((v->source_pixel_format[k] != dcn_bw_rgb_sub_64 && v->source_pixel_format[k] != dcn_bw_rgb_sub_32 && v->source_pixel_format[k] != dcn_bw_rgb_sub_16)) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1607
v->v_init_pre_fill_c[k] =dcn_bw_floor2((v->v_ratio[k] / 2.0 + v->vtaps[k] + 1.0 + v->interlace_output[k] * 0.5 * v->v_ratio[k] / 2.0) / 2.0, 1.0);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1608
v->max_num_swath_c[k] =dcn_bw_ceil2((v->v_init_pre_fill_c[k] - 1.0) / v->swath_height_c[k], 1.0) + 1;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1609
if (v->v_init_pre_fill_c[k] > 1.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
161
else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_16) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1610
v->max_partial_swath_c =dcn_bw_mod((v->v_init_pre_fill_c[k] - 2.0), v->swath_height_c[k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1613
v->max_partial_swath_c =dcn_bw_mod((v->v_init_pre_fill_c[k] + v->swath_height_c[k] - 2.0), v->swath_height_c[k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1615
v->max_partial_swath_c =dcn_bw_max2(1.0, v->max_partial_swath_c);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1618
v->max_num_swath_c[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1619
v->max_partial_swath_c = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
162
v->byte_per_pixel_in_dety[k] = 2.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1621
v->prefetch_source_lines_c[k] = v->max_num_swath_c[k] * v->swath_height_c[k] + v->max_partial_swath_c;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1623
v->t_calc = 24.0 / v->dcf_clk_deep_sleep;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1624
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1625
if (v->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one == dcn_bw_yes) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1626
v->max_vstartup_lines[k] = v->vtotal[k] - v->vactive[k] - 1.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1629
v->max_vstartup_lines[k] = v->v_sync_plus_back_porch[k] - 1.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
163
v->byte_per_pixel_in_detc[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1632
v->next_prefetch_mode = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1634
v->v_startup_lines = 13.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1636
v->planes_with_room_to_increase_vstartup_prefetch_bw_less_than_active_bw = dcn_bw_yes;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1637
v->planes_with_room_to_increase_vstartup_vratio_prefetch_more_than4 = dcn_bw_no;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1638
v->planes_with_room_to_increase_vstartup_destination_line_times_for_prefetch_less_than2 = dcn_bw_no;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1639
v->v_ratio_prefetch_more_than4 = dcn_bw_no;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1640
v->destination_line_times_for_prefetch_less_than2 = dcn_bw_no;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1641
v->prefetch_mode = v->next_prefetch_mode;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1642
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1643
v->dstx_after_scaler = 90.0 * v->pixel_clock[k] / v->dppclk + 42.0 * v->pixel_clock[k] / v->dispclk;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1644
if (v->dpp_per_plane[k] > 1.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1645
v->dstx_after_scaler = v->dstx_after_scaler + v->scaler_rec_out_width[k] / 2.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1647
if (v->output_format[k] == dcn_bw_420) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1648
v->dsty_after_scaler = 1.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
165
else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1651
v->dsty_after_scaler = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1653
v->v_update_offset_pix[k] = dcn_bw_ceil2(v->htotal[k] / 4.0, 1.0);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1654
v->total_repeater_delay_time = v->max_inter_dcn_tile_repeaters * (2.0 / v->dppclk + 3.0 / v->dispclk);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1655
v->v_update_width_pix[k] = (14.0 / v->dcf_clk_deep_sleep + 12.0 / v->dppclk + v->total_repeater_delay_time) * v->pixel_clock[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1656
v->v_ready_offset_pix[k] = dcn_bw_max2(150.0 / v->dppclk, v->total_repeater_delay_time + 20.0 / v->dcf_clk_deep_sleep + 10.0 / v->dppclk) * v->pixel_clock[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1657
v->t_setup = (v->v_update_offset_pix[k] + v->v_update_width_pix[k] + v->v_ready_offset_pix[k]) / v->pixel_clock[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1658
v->v_startup[k] =dcn_bw_min2(v->v_startup_lines, v->max_vstartup_lines[k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1659
if (v->prefetch_mode == 0.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
166
v->byte_per_pixel_in_dety[k] = 1.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1660
v->t_wait =dcn_bw_max3(v->dram_clock_change_latency + v->urgent_latency, v->sr_enter_plus_exit_time, v->urgent_latency);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1662
else if (v->prefetch_mode == 1.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1663
v->t_wait =dcn_bw_max2(v->sr_enter_plus_exit_time, v->urgent_latency);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1666
v->t_wait = v->urgent_latency;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1668
v->destination_lines_for_prefetch[k] =dcn_bw_floor2(4.0 * (v->v_startup[k] - v->t_wait / (v->htotal[k] / v->pixel_clock[k]) - (v->t_calc + v->t_setup) / (v->htotal[k] / v->pixel_clock[k]) - (v->dsty_after_scaler + v->dstx_after_scaler / v->htotal[k]) + 0.125), 1.0) / 4;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1669
if (v->destination_lines_for_prefetch[k] > 0.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
167
v->byte_per_pixel_in_detc[k] = 2.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1670
v->prefetch_bandwidth[k] = (v->meta_pte_bytes_frame[k] + 2.0 * v->meta_row_byte[k] + 2.0 * v->pixel_pte_bytes_per_row[k] + v->prefetch_source_lines_y[k] * v->swath_width_y[k] *dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) + v->prefetch_source_lines_c[k] * v->swath_width_y[k] / 2.0 *dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0)) / (v->destination_lines_for_prefetch[k] * v->htotal[k] / v->pixel_clock[k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1673
v->prefetch_bandwidth[k] = 999999.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1676
v->bandwidth_available_for_immediate_flip = v->return_bw;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1677
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1678
v->bandwidth_available_for_immediate_flip = v->bandwidth_available_for_immediate_flip -dcn_bw_max2(v->read_bandwidth_plane_luma[k] + v->read_bandwidth_plane_chroma[k], v->prefetch_bandwidth[k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1680
v->tot_immediate_flip_bytes = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1681
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1682
if (v->immediate_flip_supported == dcn_bw_yes && (v->source_pixel_format[k] != dcn_bw_yuv420_sub_8 && v->source_pixel_format[k] != dcn_bw_yuv420_sub_10)) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1683
v->tot_immediate_flip_bytes = v->tot_immediate_flip_bytes + v->meta_pte_bytes_frame[k] + v->meta_row_byte[k] + v->pixel_pte_bytes_per_row[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1686
v->max_rd_bandwidth = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1687
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1688
if (v->pte_enable == dcn_bw_yes && v->dcc_enable[k] == dcn_bw_yes) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1689
if (v->immediate_flip_supported == dcn_bw_yes && (v->source_pixel_format[k] != dcn_bw_yuv420_sub_8 && v->source_pixel_format[k] != dcn_bw_yuv420_sub_10)) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1690
v->time_for_fetching_meta_pte =dcn_bw_max5(v->meta_pte_bytes_frame[k] / v->prefetch_bandwidth[k], v->meta_pte_bytes_frame[k] * v->tot_immediate_flip_bytes / (v->bandwidth_available_for_immediate_flip * (v->meta_pte_bytes_frame[k] + v->meta_row_byte[k] + v->pixel_pte_bytes_per_row[k])), v->urgent_extra_latency, v->urgent_latency, v->htotal[k] / v->pixel_clock[k] / 4.0);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1693
v->time_for_fetching_meta_pte =dcn_bw_max3(v->meta_pte_bytes_frame[k] / v->prefetch_bandwidth[k], v->urgent_extra_latency, v->htotal[k] / v->pixel_clock[k] / 4.0);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1697
v->time_for_fetching_meta_pte = v->htotal[k] / v->pixel_clock[k] / 4.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1699
v->destination_lines_to_request_vm_inv_blank[k] =dcn_bw_floor2(4.0 * (v->time_for_fetching_meta_pte / (v->htotal[k] / v->pixel_clock[k]) + 0.125), 1.0) / 4;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
170
v->byte_per_pixel_in_dety[k] = 4.0f / 3.0f;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1700
if ((v->pte_enable == dcn_bw_yes || v->dcc_enable[k] == dcn_bw_yes)) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1701
if (v->immediate_flip_supported == dcn_bw_yes && (v->source_pixel_format[k] != dcn_bw_yuv420_sub_8 && v->source_pixel_format[k] != dcn_bw_yuv420_sub_10)) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1702
v->time_for_fetching_row_in_vblank =dcn_bw_max5((v->meta_row_byte[k] + v->pixel_pte_bytes_per_row[k]) / v->prefetch_bandwidth[k], (v->meta_row_byte[k] + v->pixel_pte_bytes_per_row[k]) * v->tot_immediate_flip_bytes / (v->bandwidth_available_for_immediate_flip * (v->meta_pte_bytes_frame[k] + v->meta_row_byte[k] + v->pixel_pte_bytes_per_row[k])), v->urgent_extra_latency, 2.0 * v->urgent_latency, v->htotal[k] / v->pixel_clock[k] - v->time_for_fetching_meta_pte);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1705
v->time_for_fetching_row_in_vblank =dcn_bw_max3((v->meta_row_byte[k] + v->pixel_pte_bytes_per_row[k]) / v->prefetch_bandwidth[k], v->urgent_extra_latency, v->htotal[k] / v->pixel_clock[k] - v->time_for_fetching_meta_pte);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1709
v->time_for_fetching_row_in_vblank =dcn_bw_max2(v->urgent_extra_latency - v->time_for_fetching_meta_pte, v->htotal[k] / v->pixel_clock[k] - v->time_for_fetching_meta_pte);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
171
v->byte_per_pixel_in_detc[k] = 8.0f / 3.0f;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1711
v->destination_lines_to_request_row_in_vblank[k] =dcn_bw_floor2(4.0 * (v->time_for_fetching_row_in_vblank / (v->htotal[k] / v->pixel_clock[k]) + 0.125), 1.0) / 4;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1712
v->lines_to_request_prefetch_pixel_data = v->destination_lines_for_prefetch[k] - v->destination_lines_to_request_vm_inv_blank[k] - v->destination_lines_to_request_row_in_vblank[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1713
if (v->lines_to_request_prefetch_pixel_data > 0.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1714
v->v_ratio_prefetch_y[k] = v->prefetch_source_lines_y[k] / v->lines_to_request_prefetch_pixel_data;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1715
if ((v->swath_height_y[k] > 4.0)) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1716
if (v->lines_to_request_prefetch_pixel_data > (v->v_init_pre_fill_y[k] - 3.0) / 2.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1717
v->v_ratio_prefetch_y[k] =dcn_bw_max2(v->v_ratio_prefetch_y[k], v->max_num_swath_y[k] * v->swath_height_y[k] / (v->lines_to_request_prefetch_pixel_data - (v->v_init_pre_fill_y[k] - 3.0) / 2.0));
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1720
v->v_ratio_prefetch_y[k] = 999999.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1725
v->v_ratio_prefetch_y[k] = 999999.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1727
v->v_ratio_prefetch_y[k] =dcn_bw_max2(v->v_ratio_prefetch_y[k], 1.0);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1728
if (v->lines_to_request_prefetch_pixel_data > 0.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1729
v->v_ratio_prefetch_c[k] = v->prefetch_source_lines_c[k] / v->lines_to_request_prefetch_pixel_data;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1730
if ((v->swath_height_c[k] > 4.0)) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1731
if (v->lines_to_request_prefetch_pixel_data > (v->v_init_pre_fill_c[k] - 3.0) / 2.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1732
v->v_ratio_prefetch_c[k] =dcn_bw_max2(v->v_ratio_prefetch_c[k], v->max_num_swath_c[k] * v->swath_height_c[k] / (v->lines_to_request_prefetch_pixel_data - (v->v_init_pre_fill_c[k] - 3.0) / 2.0));
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1735
v->v_ratio_prefetch_c[k] = 999999.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
174
v->total_read_bandwidth_consumed_gbyte_per_second = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1740
v->v_ratio_prefetch_c[k] = 999999.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1742
v->v_ratio_prefetch_c[k] =dcn_bw_max2(v->v_ratio_prefetch_c[k], 1.0);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1743
if (v->lines_to_request_prefetch_pixel_data > 0.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1744
v->required_prefetch_pix_data_bw = v->dpp_per_plane[k] * (v->prefetch_source_lines_y[k] / v->lines_to_request_prefetch_pixel_data *dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) + v->prefetch_source_lines_c[k] / v->lines_to_request_prefetch_pixel_data *dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0) / 2.0) * v->swath_width_y[k] / (v->htotal[k] / v->pixel_clock[k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1747
v->required_prefetch_pix_data_bw = 999999.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1749
v->max_rd_bandwidth = v->max_rd_bandwidth +dcn_bw_max2(v->read_bandwidth_plane_luma[k] + v->read_bandwidth_plane_chroma[k], v->required_prefetch_pix_data_bw);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
175
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1750
if (v->immediate_flip_supported == dcn_bw_yes && (v->source_pixel_format[k] != dcn_bw_yuv420_sub_8 && v->source_pixel_format[k] != dcn_bw_yuv420_sub_10)) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1751
v->max_rd_bandwidth = v->max_rd_bandwidth +dcn_bw_max2(v->meta_pte_bytes_frame[k] / (v->destination_lines_to_request_vm_inv_blank[k] * v->htotal[k] / v->pixel_clock[k]), (v->meta_row_byte[k] + v->pixel_pte_bytes_per_row[k]) / (v->destination_lines_to_request_row_in_vblank[k] * v->htotal[k] / v->pixel_clock[k]));
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1753
if (v->v_ratio_prefetch_y[k] > 4.0 || v->v_ratio_prefetch_c[k] > 4.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1754
v->v_ratio_prefetch_more_than4 = dcn_bw_yes;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1756
if (v->destination_lines_for_prefetch[k] < 2.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1757
v->destination_line_times_for_prefetch_less_than2 = dcn_bw_yes;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1759
if (v->max_vstartup_lines[k] > v->v_startup_lines) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
176
v->read_bandwidth[k] = v->swath_width_ysingle_dpp[k] * (dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) * v->v_ratio[k] +dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / 2.0 * v->v_ratio[k] / 2) / (v->htotal[k] / v->pixel_clock[k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1760
if (v->required_prefetch_pix_data_bw > (v->read_bandwidth_plane_luma[k] + v->read_bandwidth_plane_chroma[k])) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1761
v->planes_with_room_to_increase_vstartup_prefetch_bw_less_than_active_bw = dcn_bw_no;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1763
if (v->v_ratio_prefetch_y[k] > 4.0 || v->v_ratio_prefetch_c[k] > 4.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1764
v->planes_with_room_to_increase_vstartup_vratio_prefetch_more_than4 = dcn_bw_yes;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1766
if (v->destination_lines_for_prefetch[k] < 2.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1767
v->planes_with_room_to_increase_vstartup_destination_line_times_for_prefetch_less_than2 = dcn_bw_yes;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
177
if (v->dcc_enable[k] == dcn_bw_yes) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1771
if (v->max_rd_bandwidth <= v->return_bw && v->v_ratio_prefetch_more_than4 == dcn_bw_no && v->destination_line_times_for_prefetch_less_than2 == dcn_bw_no) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1772
v->prefetch_mode_supported = dcn_bw_yes;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1775
v->prefetch_mode_supported = dcn_bw_no;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1777
v->v_startup_lines = v->v_startup_lines + 1.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1778
} while (!(v->prefetch_mode_supported == dcn_bw_yes || (v->planes_with_room_to_increase_vstartup_prefetch_bw_less_than_active_bw == dcn_bw_yes && v->planes_with_room_to_increase_vstartup_vratio_prefetch_more_than4 == dcn_bw_no && v->planes_with_room_to_increase_vstartup_destination_line_times_for_prefetch_less_than2 == dcn_bw_no)));
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1779
v->next_prefetch_mode = v->next_prefetch_mode + 1.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
178
v->read_bandwidth[k] = v->read_bandwidth[k] * (1 + 1 / 256);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1780
} while (!(v->prefetch_mode_supported == dcn_bw_yes || v->prefetch_mode == 2.0));
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1781
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1782
if (v->v_ratio_prefetch_y[k] <= 1.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1783
v->display_pipe_line_delivery_time_luma_prefetch[k] = v->swath_width_y[k] * v->dpp_per_plane[k] / v->h_ratio[k] / v->pixel_clock[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1786
v->display_pipe_line_delivery_time_luma_prefetch[k] = v->swath_width_y[k] / v->pscl_throughput[k] / v->dppclk;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1788
if (v->byte_per_pixel_detc[k] == 0.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1789
v->display_pipe_line_delivery_time_chroma_prefetch[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1792
if (v->v_ratio_prefetch_c[k] <= 1.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1793
v->display_pipe_line_delivery_time_chroma_prefetch[k] = v->swath_width_y[k] * v->dpp_per_plane[k] / v->h_ratio[k] / v->pixel_clock[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1796
v->display_pipe_line_delivery_time_chroma_prefetch[k] = v->swath_width_y[k] / v->pscl_throughput[k] / v->dppclk;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
180
if (v->pte_enable == dcn_bw_yes && v->source_scan[k] != dcn_bw_hor && (v->source_surface_mode[k] == dcn_bw_sw_4_kb_s || v->source_surface_mode[k] == dcn_bw_sw_4_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d_x)) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1802
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1803
if (v->prefetch_mode == 0.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1804
v->allow_dram_clock_change_during_vblank[k] = dcn_bw_yes;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1805
v->allow_dram_self_refresh_during_vblank[k] = dcn_bw_yes;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1806
v->min_ttuv_blank[k] = v->t_calc +dcn_bw_max3(v->dram_clock_change_watermark, v->stutter_enter_plus_exit_watermark, v->urgent_watermark);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1808
else if (v->prefetch_mode == 1.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1809
v->allow_dram_clock_change_during_vblank[k] = dcn_bw_no;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
181
v->read_bandwidth[k] = v->read_bandwidth[k] * (1 + 1 / 64);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1810
v->allow_dram_self_refresh_during_vblank[k] = dcn_bw_yes;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1811
v->min_ttuv_blank[k] = v->t_calc +dcn_bw_max2(v->stutter_enter_plus_exit_watermark, v->urgent_watermark);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1814
v->allow_dram_clock_change_during_vblank[k] = dcn_bw_no;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1815
v->allow_dram_self_refresh_during_vblank[k] = dcn_bw_no;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1816
v->min_ttuv_blank[k] = v->t_calc + v->urgent_watermark;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1821
v->active_dp_ps = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1822
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1823
v->active_dp_ps = v->active_dp_ps + v->dpp_per_plane[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1825
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1826
v->lb_latency_hiding_source_lines_y =dcn_bw_min2(v->max_line_buffer_lines,dcn_bw_floor2(v->line_buffer_size / v->lb_bit_per_pixel[k] / (v->swath_width_y[k] /dcn_bw_max2(v->h_ratio[k], 1.0)), 1.0)) - (v->vtaps[k] - 1.0);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1827
v->lb_latency_hiding_source_lines_c =dcn_bw_min2(v->max_line_buffer_lines,dcn_bw_floor2(v->line_buffer_size / v->lb_bit_per_pixel[k] / (v->swath_width_y[k] / 2.0 /dcn_bw_max2(v->h_ratio[k] / 2.0, 1.0)), 1.0)) - (v->vta_pschroma[k] - 1.0);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1828
v->effective_lb_latency_hiding_y = v->lb_latency_hiding_source_lines_y / v->v_ratio[k] * (v->htotal[k] / v->pixel_clock[k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1829
v->effective_lb_latency_hiding_c = v->lb_latency_hiding_source_lines_c / (v->v_ratio[k] / 2.0) * (v->htotal[k] / v->pixel_clock[k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
183
else if (v->pte_enable == dcn_bw_yes && v->source_scan[k] == dcn_bw_hor && (v->source_pixel_format[k] == dcn_bw_rgb_sub_64 || v->source_pixel_format[k] == dcn_bw_rgb_sub_32) && (v->source_surface_mode[k] == dcn_bw_sw_64_kb_s || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_x)) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1830
if (v->swath_width_y[k] > 2.0 * v->dpp_output_buffer_pixels) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1831
v->dpp_output_buffer_lines_y = v->dpp_output_buffer_pixels / v->swath_width_y[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1833
else if (v->swath_width_y[k] > v->dpp_output_buffer_pixels) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1834
v->dpp_output_buffer_lines_y = 0.5;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1837
v->dpp_output_buffer_lines_y = 1.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1839
if (v->swath_width_y[k] / 2.0 > 2.0 * v->dpp_output_buffer_pixels) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
184
v->read_bandwidth[k] = v->read_bandwidth[k] * (1 + 1 / 256);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1840
v->dpp_output_buffer_lines_c = v->dpp_output_buffer_pixels / (v->swath_width_y[k] / 2.0);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1842
else if (v->swath_width_y[k] / 2.0 > v->dpp_output_buffer_pixels) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1843
v->dpp_output_buffer_lines_c = 0.5;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1846
v->dpp_output_buffer_lines_c = 1.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1848
v->dppopp_buffering_y = (v->htotal[k] / v->pixel_clock[k]) * (v->dpp_output_buffer_lines_y + v->opp_output_buffer_lines);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1849
v->max_det_buffering_time_y = v->full_det_buffering_time_y[k] + (v->lines_in_dety[k] - v->lines_in_dety_rounded_down_to_swath[k]) / v->swath_height_y[k] * (v->htotal[k] / v->pixel_clock[k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1850
v->active_dram_clock_change_latency_margin_y = v->dppopp_buffering_y + v->effective_lb_latency_hiding_y + v->max_det_buffering_time_y - v->dram_clock_change_watermark;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1851
if (v->active_dp_ps > 1.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1852
v->active_dram_clock_change_latency_margin_y = v->active_dram_clock_change_latency_margin_y - (1.0 - 1.0 / (v->active_dp_ps - 1.0)) * v->swath_height_y[k] * (v->htotal[k] / v->pixel_clock[k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1854
if (v->byte_per_pixel_detc[k] > 0.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1855
v->dppopp_buffering_c = (v->htotal[k] / v->pixel_clock[k]) * (v->dpp_output_buffer_lines_c + v->opp_output_buffer_lines);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1856
v->max_det_buffering_time_c = v->full_det_buffering_time_c[k] + (v->lines_in_detc[k] - v->lines_in_detc_rounded_down_to_swath[k]) / v->swath_height_c[k] * (v->htotal[k] / v->pixel_clock[k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1857
v->active_dram_clock_change_latency_margin_c = v->dppopp_buffering_c + v->effective_lb_latency_hiding_c + v->max_det_buffering_time_c - v->dram_clock_change_watermark;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1858
if (v->active_dp_ps > 1.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1859
v->active_dram_clock_change_latency_margin_c = v->active_dram_clock_change_latency_margin_c - (1.0 - 1.0 / (v->active_dp_ps - 1.0)) * v->swath_height_c[k] * (v->htotal[k] / v->pixel_clock[k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
186
else if (v->pte_enable == dcn_bw_yes) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1861
v->active_dram_clock_change_latency_margin[k] =dcn_bw_min2(v->active_dram_clock_change_latency_margin_y, v->active_dram_clock_change_latency_margin_c);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1864
v->active_dram_clock_change_latency_margin[k] = v->active_dram_clock_change_latency_margin_y;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1866
if (v->output_format[k] == dcn_bw_444) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1867
v->writeback_dram_clock_change_latency_margin = (v->writeback_luma_buffer_size + v->writeback_chroma_buffer_size) * 1024.0 / (v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_clock[k]) * 4.0) - v->writeback_dram_clock_change_watermark;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
187
v->read_bandwidth[k] = v->read_bandwidth[k] * (1 + 1 / 512);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1870
v->writeback_dram_clock_change_latency_margin =dcn_bw_min2(v->writeback_luma_buffer_size, 2.0 * v->writeback_chroma_buffer_size) * 1024.0 / (v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_clock[k])) - v->writeback_dram_clock_change_watermark;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1872
if (v->output[k] == dcn_bw_writeback) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1873
v->active_dram_clock_change_latency_margin[k] =dcn_bw_min2(v->active_dram_clock_change_latency_margin[k], v->writeback_dram_clock_change_latency_margin);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1876
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1877
if (v->allow_dram_clock_change_during_vblank[k] == dcn_bw_yes) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1878
v->v_blank_dram_clock_change_latency_margin[k] = (v->vtotal[k] - v->scaler_recout_height[k]) * (v->htotal[k] / v->pixel_clock[k]) -dcn_bw_max2(v->dram_clock_change_watermark, v->writeback_dram_clock_change_watermark);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1881
v->v_blank_dram_clock_change_latency_margin[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1884
v->min_active_dram_clock_change_margin = 999999.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1885
v->v_blank_of_min_active_dram_clock_change_margin = 999999.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1886
v->second_min_active_dram_clock_change_margin = 999999.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1887
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1888
if (v->active_dram_clock_change_latency_margin[k] < v->min_active_dram_clock_change_margin) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1889
v->second_min_active_dram_clock_change_margin = v->min_active_dram_clock_change_margin;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
189
v->total_read_bandwidth_consumed_gbyte_per_second = v->total_read_bandwidth_consumed_gbyte_per_second + v->read_bandwidth[k] / 1000.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1890
v->min_active_dram_clock_change_margin = v->active_dram_clock_change_latency_margin[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1891
v->v_blank_of_min_active_dram_clock_change_margin = v->v_blank_dram_clock_change_latency_margin[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1893
else if (v->active_dram_clock_change_latency_margin[k] < v->second_min_active_dram_clock_change_margin) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1894
v->second_min_active_dram_clock_change_margin = v->active_dram_clock_change_latency_margin[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1897
v->min_vblank_dram_clock_change_margin = 999999.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1898
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1899
if (v->min_vblank_dram_clock_change_margin > v->v_blank_dram_clock_change_latency_margin[k]) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1900
v->min_vblank_dram_clock_change_margin = v->v_blank_dram_clock_change_latency_margin[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1903
if (v->synchronized_vblank == dcn_bw_yes || v->number_of_active_planes == 1) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1904
v->dram_clock_change_margin =dcn_bw_max2(v->min_active_dram_clock_change_margin, v->min_vblank_dram_clock_change_margin);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1906
else if (v->v_blank_of_min_active_dram_clock_change_margin > v->min_active_dram_clock_change_margin) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1907
v->dram_clock_change_margin =dcn_bw_min2(v->second_min_active_dram_clock_change_margin, v->v_blank_of_min_active_dram_clock_change_margin);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
191
v->total_write_bandwidth_consumed_gbyte_per_second = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1910
v->dram_clock_change_margin = v->min_active_dram_clock_change_margin;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1912
if (v->min_active_dram_clock_change_margin > 0.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1913
v->dram_clock_change_support = dcn_bw_supported_in_v_active;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1915
else if (v->dram_clock_change_margin > 0.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1916
v->dram_clock_change_support = dcn_bw_supported_in_v_blank;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1919
v->dram_clock_change_support = dcn_bw_not_supported;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
192
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1923
v->wr_bandwidth = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1924
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1925
if (v->output[k] == dcn_bw_writeback && v->output_format[k] == dcn_bw_444) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1926
v->wr_bandwidth = v->wr_bandwidth + v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_clock[k]) * 4.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1928
else if (v->output[k] == dcn_bw_writeback) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1929
v->wr_bandwidth = v->wr_bandwidth + v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_clock[k]) * 1.5;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
193
if (v->output[k] == dcn_bw_writeback && v->output_format[k] == dcn_bw_444) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
1932
v->max_used_bw = v->max_rd_bandwidth + v->wr_bandwidth;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
194
v->write_bandwidth[k] = v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_clock[k]) * 4.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
196
else if (v->output[k] == dcn_bw_writeback) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
197
v->write_bandwidth[k] = v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_clock[k]) * 1.5;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
200
v->write_bandwidth[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
202
v->total_write_bandwidth_consumed_gbyte_per_second = v->total_write_bandwidth_consumed_gbyte_per_second + v->write_bandwidth[k] / 1000.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
204
v->total_bandwidth_consumed_gbyte_per_second = v->total_read_bandwidth_consumed_gbyte_per_second + v->total_write_bandwidth_consumed_gbyte_per_second;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
205
v->dcc_enabled_in_any_plane = dcn_bw_no;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
206
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
207
if (v->dcc_enable[k] == dcn_bw_yes) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
208
v->dcc_enabled_in_any_plane = dcn_bw_yes;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
212
v->return_bw_todcn_per_state =dcn_bw_min2(v->return_bus_width * v->dcfclk_per_state[i], v->fabric_and_dram_bandwidth_per_state[i] * 1000.0 * v->percent_of_ideal_drambw_received_after_urg_latency / 100.0);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
213
v->return_bw_per_state[i] = v->return_bw_todcn_per_state;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
214
if (v->dcc_enabled_in_any_plane == dcn_bw_yes && v->return_bw_todcn_per_state > v->dcfclk_per_state[i] * v->return_bus_width / 4.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
215
v->return_bw_per_state[i] =dcn_bw_min2(v->return_bw_per_state[i], v->return_bw_todcn_per_state * 4.0 * (1.0 - v->urgent_latency / ((v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0 / (v->return_bw_todcn_per_state - v->dcfclk_per_state[i] * v->return_bus_width / 4.0) + v->urgent_latency)));
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
217
v->critical_point = 2.0 * v->return_bus_width * v->dcfclk_per_state[i] * v->urgent_latency / (v->return_bw_todcn_per_state * v->urgent_latency + (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
218
if (v->dcc_enabled_in_any_plane == dcn_bw_yes && v->critical_point > 1.0 && v->critical_point < 4.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
219
v->return_bw_per_state[i] =dcn_bw_min2(v->return_bw_per_state[i], dcn_bw_pow(4.0 * v->return_bw_todcn_per_state * (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0 * v->return_bus_width * v->dcfclk_per_state[i] * v->urgent_latency / (v->return_bw_todcn_per_state * v->urgent_latency + (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0), 2));
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
221
v->return_bw_todcn_per_state =dcn_bw_min2(v->return_bus_width * v->dcfclk_per_state[i], v->fabric_and_dram_bandwidth_per_state[i] * 1000.0);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
222
if (v->dcc_enabled_in_any_plane == dcn_bw_yes && v->return_bw_todcn_per_state > v->dcfclk_per_state[i] * v->return_bus_width / 4.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
223
v->return_bw_per_state[i] =dcn_bw_min2(v->return_bw_per_state[i], v->return_bw_todcn_per_state * 4.0 * (1.0 - v->urgent_latency / ((v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0 / (v->return_bw_todcn_per_state - v->dcfclk_per_state[i] * v->return_bus_width / 4.0) + v->urgent_latency)));
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
225
v->critical_point = 2.0 * v->return_bus_width * v->dcfclk_per_state[i] * v->urgent_latency / (v->return_bw_todcn_per_state * v->urgent_latency + (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
226
if (v->dcc_enabled_in_any_plane == dcn_bw_yes && v->critical_point > 1.0 && v->critical_point < 4.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
227
v->return_bw_per_state[i] =dcn_bw_min2(v->return_bw_per_state[i], dcn_bw_pow(4.0 * v->return_bw_todcn_per_state * (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0 * v->return_bus_width * v->dcfclk_per_state[i] * v->urgent_latency / (v->return_bw_todcn_per_state * v->urgent_latency + (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0), 2));
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
231
if ((v->total_read_bandwidth_consumed_gbyte_per_second * 1000.0 <= v->return_bw_per_state[i]) && (v->total_bandwidth_consumed_gbyte_per_second * 1000.0 <= v->fabric_and_dram_bandwidth_per_state[i] * 1000.0 * v->percent_of_ideal_drambw_received_after_urg_latency / 100.0)) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
232
v->bandwidth_support[i] = dcn_bw_yes;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
235
v->bandwidth_support[i] = dcn_bw_no;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
240
v->writeback_latency_support = dcn_bw_yes;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
241
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
242
if (v->output[k] == dcn_bw_writeback && v->output_format[k] == dcn_bw_444 && v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_clock[k]) * 4.0 > (v->writeback_luma_buffer_size + v->writeback_chroma_buffer_size) * 1024.0 / v->write_back_latency) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
243
v->writeback_latency_support = dcn_bw_no;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
245
else if (v->output[k] == dcn_bw_writeback && v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_clock[k]) >dcn_bw_min2(v->writeback_luma_buffer_size, 2.0 * v->writeback_chroma_buffer_size) * 1024.0 / v->write_back_latency) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
246
v->writeback_latency_support = dcn_bw_no;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
252
v->urgent_round_trip_and_out_of_order_latency_per_state[i] = (v->round_trip_ping_latency_cycles + 32.0) / v->dcfclk_per_state[i] + v->urgent_out_of_order_return_per_channel * v->number_of_channels / v->return_bw_per_state[i];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
253
if ((v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0 / v->return_bw_per_state[i] > v->urgent_round_trip_and_out_of_order_latency_per_state[i]) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
254
v->rob_support[i] = dcn_bw_yes;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
257
v->rob_support[i] = dcn_bw_no;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
262
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
263
if (v->output[k] == dcn_bw_dp && v->dsc_capability == dcn_bw_yes) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
264
if (v->output_format[k] == dcn_bw_420) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
265
v->required_output_bw = v->pixel_clock[k] / 2.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
268
v->required_output_bw = v->pixel_clock[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
271
else if (v->output_format[k] == dcn_bw_420) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
272
v->required_output_bw = v->pixel_clock[k] * 3.0 / 2.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
275
v->required_output_bw = v->pixel_clock[k] * 3.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
277
if (v->output[k] == dcn_bw_hdmi) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
278
v->required_phyclk[k] = v->required_output_bw;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
279
switch (v->output_deep_color[k]) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
281
v->required_phyclk[k] = v->required_phyclk[k] * 5.0 / 4;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
284
v->required_phyclk[k] = v->required_phyclk[k] * 3.0 / 2;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
289
v->required_phyclk[k] = v->required_phyclk[k] / 3.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
291
else if (v->output[k] == dcn_bw_dp) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
292
v->required_phyclk[k] = v->required_output_bw / 4.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
295
v->required_phyclk[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
299
v->dio_support[i] = dcn_bw_yes;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
300
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
301
if (v->required_phyclk[k] > v->phyclk_per_state[i] || (v->output[k] == dcn_bw_hdmi && v->required_phyclk[k] > 600.0)) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
302
v->dio_support[i] = dcn_bw_no;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
308
v->total_number_of_active_writeback = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
309
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
310
if (v->output[k] == dcn_bw_writeback) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
311
v->total_number_of_active_writeback = v->total_number_of_active_writeback + 1.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
314
if (v->total_number_of_active_writeback <= v->max_num_writeback) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
315
v->total_available_writeback_support = dcn_bw_yes;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
318
v->total_available_writeback_support = dcn_bw_no;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
322
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
323
if (v->h_ratio[k] > 1.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
324
v->pscl_factor[k] =dcn_bw_min2(v->max_dchub_topscl_throughput, v->max_pscl_tolb_throughput * v->h_ratio[k] /dcn_bw_ceil2(v->htaps[k] / 6.0, 1.0));
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
327
v->pscl_factor[k] =dcn_bw_min2(v->max_dchub_topscl_throughput, v->max_pscl_tolb_throughput);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
329
if (v->byte_per_pixel_in_detc[k] == 0.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
330
v->pscl_factor_chroma[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
331
v->min_dppclk_using_single_dpp[k] = v->pixel_clock[k] *dcn_bw_max3(v->vtaps[k] / 6.0 *dcn_bw_min2(1.0, v->h_ratio[k]), v->h_ratio[k] * v->v_ratio[k] / v->pscl_factor[k], 1.0);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
334
if (v->h_ratio[k] / 2.0 > 1.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
335
v->pscl_factor_chroma[k] =dcn_bw_min2(v->max_dchub_topscl_throughput, v->max_pscl_tolb_throughput * v->h_ratio[k] / 2.0 /dcn_bw_ceil2(v->hta_pschroma[k] / 6.0, 1.0));
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
338
v->pscl_factor_chroma[k] =dcn_bw_min2(v->max_dchub_topscl_throughput, v->max_pscl_tolb_throughput);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
340
v->min_dppclk_using_single_dpp[k] = v->pixel_clock[k] *dcn_bw_max5(v->vtaps[k] / 6.0 *dcn_bw_min2(1.0, v->h_ratio[k]), v->h_ratio[k] * v->v_ratio[k] / v->pscl_factor[k], v->vta_pschroma[k] / 6.0 *dcn_bw_min2(1.0, v->h_ratio[k] / 2.0), v->h_ratio[k] * v->v_ratio[k] / 4.0 / v->pscl_factor_chroma[k], 1.0);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
343
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
344
if ((v->source_pixel_format[k] == dcn_bw_rgb_sub_64 || v->source_pixel_format[k] == dcn_bw_rgb_sub_32 || v->source_pixel_format[k] == dcn_bw_rgb_sub_16)) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
345
if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
346
v->read256_block_height_y[k] = 1.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
348
else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_64) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
349
v->read256_block_height_y[k] = 4.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
352
v->read256_block_height_y[k] = 8.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
354
v->read256_block_width_y[k] = 256.0 /dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / v->read256_block_height_y[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
355
v->read256_block_height_c[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
356
v->read256_block_width_c[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
359
if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
360
v->read256_block_height_y[k] = 1.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
361
v->read256_block_height_c[k] = 1.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
363
else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
364
v->read256_block_height_y[k] = 16.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
365
v->read256_block_height_c[k] = 8.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
368
v->read256_block_height_y[k] = 8.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
369
v->read256_block_height_c[k] = 8.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
371
v->read256_block_width_y[k] = 256.0 /dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / v->read256_block_height_y[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
372
v->read256_block_width_c[k] = 256.0 /dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / v->read256_block_height_c[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
374
if (v->source_scan[k] == dcn_bw_hor) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
375
v->max_swath_height_y[k] = v->read256_block_height_y[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
376
v->max_swath_height_c[k] = v->read256_block_height_c[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
379
v->max_swath_height_y[k] = v->read256_block_width_y[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
380
v->max_swath_height_c[k] = v->read256_block_width_c[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
382
if ((v->source_pixel_format[k] == dcn_bw_rgb_sub_64 || v->source_pixel_format[k] == dcn_bw_rgb_sub_32 || v->source_pixel_format[k] == dcn_bw_rgb_sub_16)) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
383
if (v->source_surface_mode[k] == dcn_bw_sw_linear || (v->source_pixel_format[k] == dcn_bw_rgb_sub_64 && (v->source_surface_mode[k] == dcn_bw_sw_4_kb_s || v->source_surface_mode[k] == dcn_bw_sw_4_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_var_s || v->source_surface_mode[k] == dcn_bw_sw_var_s_x) && v->source_scan[k] == dcn_bw_hor)) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
384
v->min_swath_height_y[k] = v->max_swath_height_y[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
387
v->min_swath_height_y[k] = v->max_swath_height_y[k] / 2.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
389
v->min_swath_height_c[k] = v->max_swath_height_c[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
392
if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
393
v->min_swath_height_y[k] = v->max_swath_height_y[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
394
v->min_swath_height_c[k] = v->max_swath_height_c[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
396
else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8 && v->source_scan[k] == dcn_bw_hor) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
397
v->min_swath_height_y[k] = v->max_swath_height_y[k] / 2.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
398
if (v->bug_forcing_luma_and_chroma_request_to_same_size_fixed == dcn_bw_yes) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
399
v->min_swath_height_c[k] = v->max_swath_height_c[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
40
void scaler_settings_calculation(struct dcn_bw_internal_vars *v)
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
402
v->min_swath_height_c[k] = v->max_swath_height_c[k] / 2.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
405
else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_10 && v->source_scan[k] == dcn_bw_hor) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
406
v->min_swath_height_c[k] = v->max_swath_height_c[k] / 2.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
407
if (v->bug_forcing_luma_and_chroma_request_to_same_size_fixed == dcn_bw_yes) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
408
v->min_swath_height_y[k] = v->max_swath_height_y[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
411
v->min_swath_height_y[k] = v->max_swath_height_y[k] / 2.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
415
v->min_swath_height_y[k] = v->max_swath_height_y[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
416
v->min_swath_height_c[k] = v->max_swath_height_c[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
419
if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
420
v->maximum_swath_width = 8192.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
423
v->maximum_swath_width = 5120.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
425
v->number_of_dpp_required_for_det_size =dcn_bw_ceil2(v->swath_width_ysingle_dpp[k] /dcn_bw_min2(v->maximum_swath_width, v->det_buffer_size_in_kbyte * 1024.0 / 2.0 / (v->byte_per_pixel_in_dety[k] * v->min_swath_height_y[k] + v->byte_per_pixel_in_detc[k] / 2.0 * v->min_swath_height_c[k])), 1.0);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
426
if (v->byte_per_pixel_in_detc[k] == 0.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
427
v->number_of_dpp_required_for_lb_size =dcn_bw_ceil2((v->vtaps[k] +dcn_bw_max2(dcn_bw_ceil2(v->v_ratio[k], 1.0) - 2, 0.0)) * v->swath_width_ysingle_dpp[k] /dcn_bw_max2(v->h_ratio[k], 1.0) * v->lb_bit_per_pixel[k] / v->line_buffer_size, 1.0);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
43
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
430
v->number_of_dpp_required_for_lb_size =dcn_bw_max2(dcn_bw_ceil2((v->vtaps[k] +dcn_bw_max2(dcn_bw_ceil2(v->v_ratio[k], 1.0) - 2, 0.0)) * v->swath_width_ysingle_dpp[k] /dcn_bw_max2(v->h_ratio[k], 1.0) * v->lb_bit_per_pixel[k] / v->line_buffer_size, 1.0),dcn_bw_ceil2((v->vta_pschroma[k] +dcn_bw_max2(dcn_bw_ceil2(v->v_ratio[k] / 2.0, 1.0) - 2, 0.0)) * v->swath_width_ysingle_dpp[k] / 2.0 /dcn_bw_max2(v->h_ratio[k] / 2.0, 1.0) * v->lb_bit_per_pixel[k] / v->line_buffer_size, 1.0));
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
432
v->number_of_dpp_required_for_det_and_lb_size[k] =dcn_bw_max2(v->number_of_dpp_required_for_det_size, v->number_of_dpp_required_for_lb_size);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
436
v->total_number_of_active_dpp[i][j] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
437
v->required_dispclk[i][j] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
438
v->dispclk_dppclk_support[i][j] = dcn_bw_yes;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
439
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
44
if (v->allow_different_hratio_vratio == dcn_bw_yes) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
440
v->min_dispclk_using_single_dpp =dcn_bw_max2(v->pixel_clock[k], v->min_dppclk_using_single_dpp[k] * (j + 1)) * (1.0 + v->downspreading / 100.0);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
441
if (v->odm_capability == dcn_bw_yes) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
442
v->min_dispclk_using_dual_dpp =dcn_bw_max2(v->pixel_clock[k] / 2.0, v->min_dppclk_using_single_dpp[k] / 2.0 * (j + 1)) * (1.0 + v->downspreading / 100.0);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
445
v->min_dispclk_using_dual_dpp =dcn_bw_max2(v->pixel_clock[k], v->min_dppclk_using_single_dpp[k] / 2.0 * (j + 1)) * (1.0 + v->downspreading / 100.0);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
448
v->min_dispclk_using_single_dpp = v->min_dispclk_using_single_dpp * (1.0 + v->dispclk_ramping_margin / 100.0);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
449
v->min_dispclk_using_dual_dpp = v->min_dispclk_using_dual_dpp * (1.0 + v->dispclk_ramping_margin / 100.0);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
45
if (v->source_scan[k] == dcn_bw_hor) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
451
if (v->min_dispclk_using_single_dpp <=dcn_bw_min2(v->max_dispclk[i], (j + 1) * v->max_dppclk[i]) && v->number_of_dpp_required_for_det_and_lb_size[k] <= 1.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
452
v->no_of_dpp[i][j][k] = 1.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
453
v->required_dispclk[i][j] =dcn_bw_max2(v->required_dispclk[i][j], v->min_dispclk_using_single_dpp);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
455
else if (v->min_dispclk_using_dual_dpp <=dcn_bw_min2(v->max_dispclk[i], (j + 1) * v->max_dppclk[i])) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
456
v->no_of_dpp[i][j][k] = 2.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
457
v->required_dispclk[i][j] =dcn_bw_max2(v->required_dispclk[i][j], v->min_dispclk_using_dual_dpp);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
46
v->h_ratio[k] = v->viewport_width[k] / v->scaler_rec_out_width[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
460
v->no_of_dpp[i][j][k] = 2.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
461
v->required_dispclk[i][j] =dcn_bw_max2(v->required_dispclk[i][j], v->min_dispclk_using_dual_dpp);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
462
v->dispclk_dppclk_support[i][j] = dcn_bw_no;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
464
v->total_number_of_active_dpp[i][j] = v->total_number_of_active_dpp[i][j] + v->no_of_dpp[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
466
if (v->total_number_of_active_dpp[i][j] > v->max_num_dpp) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
467
v->total_number_of_active_dpp[i][j] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
468
v->required_dispclk[i][j] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
469
v->dispclk_dppclk_support[i][j] = dcn_bw_yes;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
47
v->v_ratio[k] = v->viewport_height[k] / v->scaler_recout_height[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
470
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
471
v->min_dispclk_using_single_dpp =dcn_bw_max2(v->pixel_clock[k], v->min_dppclk_using_single_dpp[k] * (j + 1)) * (1.0 + v->downspreading / 100.0);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
472
v->min_dispclk_using_dual_dpp =dcn_bw_max2(v->pixel_clock[k], v->min_dppclk_using_single_dpp[k] / 2.0 * (j + 1)) * (1.0 + v->downspreading / 100.0);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
474
v->min_dispclk_using_single_dpp = v->min_dispclk_using_single_dpp * (1.0 + v->dispclk_ramping_margin / 100.0);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
475
v->min_dispclk_using_dual_dpp = v->min_dispclk_using_dual_dpp * (1.0 + v->dispclk_ramping_margin / 100.0);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
477
if (v->number_of_dpp_required_for_det_and_lb_size[k] <= 1.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
478
v->no_of_dpp[i][j][k] = 1.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
479
v->required_dispclk[i][j] =dcn_bw_max2(v->required_dispclk[i][j], v->min_dispclk_using_single_dpp);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
480
if (v->min_dispclk_using_single_dpp >dcn_bw_min2(v->max_dispclk[i], (j + 1) * v->max_dppclk[i])) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
481
v->dispclk_dppclk_support[i][j] = dcn_bw_no;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
485
v->no_of_dpp[i][j][k] = 2.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
486
v->required_dispclk[i][j] =dcn_bw_max2(v->required_dispclk[i][j], v->min_dispclk_using_dual_dpp);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
487
if (v->min_dispclk_using_dual_dpp >dcn_bw_min2(v->max_dispclk[i], (j + 1) * v->max_dppclk[i])) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
488
v->dispclk_dppclk_support[i][j] = dcn_bw_no;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
491
v->total_number_of_active_dpp[i][j] = v->total_number_of_active_dpp[i][j] + v->no_of_dpp[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
498
v->viewport_size_support = dcn_bw_yes;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
499
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
50
v->h_ratio[k] = v->viewport_height[k] / v->scaler_rec_out_width[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
500
if (v->number_of_dpp_required_for_det_and_lb_size[k] > 2.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
501
v->viewport_size_support = dcn_bw_no;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
508
if (v->total_number_of_active_dpp[i][j] <= v->max_num_dpp) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
509
v->total_available_pipes_support[i][j] = dcn_bw_yes;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
51
v->v_ratio[k] = v->viewport_width[k] / v->scaler_recout_height[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
512
v->total_available_pipes_support[i][j] = dcn_bw_no;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
518
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
521
v->swath_width_yper_state[i][j][k] = v->swath_width_ysingle_dpp[k] / v->no_of_dpp[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
522
v->swath_width_granularity_y = 256.0 /dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / v->max_swath_height_y[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
523
v->rounded_up_max_swath_size_bytes_y = (dcn_bw_ceil2(v->swath_width_yper_state[i][j][k] - 1.0, v->swath_width_granularity_y) + v->swath_width_granularity_y) * v->byte_per_pixel_in_dety[k] * v->max_swath_height_y[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
524
if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_10) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
525
v->rounded_up_max_swath_size_bytes_y =dcn_bw_ceil2(v->rounded_up_max_swath_size_bytes_y, 256.0) + 256;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
527
if (v->max_swath_height_c[k] > 0.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
528
v->swath_width_granularity_c = 256.0 /dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / v->max_swath_height_c[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
529
v->rounded_up_max_swath_size_bytes_c = (dcn_bw_ceil2(v->swath_width_yper_state[i][j][k] / 2.0 - 1.0, v->swath_width_granularity_c) + v->swath_width_granularity_c) * v->byte_per_pixel_in_detc[k] * v->max_swath_height_c[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
530
if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_10) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
531
v->rounded_up_max_swath_size_bytes_c = dcn_bw_ceil2(v->rounded_up_max_swath_size_bytes_c, 256.0) + 256;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
534
if (v->rounded_up_max_swath_size_bytes_y + v->rounded_up_max_swath_size_bytes_c <= v->det_buffer_size_in_kbyte * 1024.0 / 2.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
535
v->swath_height_yper_state[i][j][k] = v->max_swath_height_y[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
536
v->swath_height_cper_state[i][j][k] = v->max_swath_height_c[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
539
v->swath_height_yper_state[i][j][k] = v->min_swath_height_y[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
540
v->swath_height_cper_state[i][j][k] = v->min_swath_height_c[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
542
if (v->byte_per_pixel_in_detc[k] == 0.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
543
v->lines_in_det_luma = v->det_buffer_size_in_kbyte * 1024.0 / v->byte_per_pixel_in_dety[k] / v->swath_width_yper_state[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
544
v->lines_in_det_chroma = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
546
else if (v->swath_height_yper_state[i][j][k] <= v->swath_height_cper_state[i][j][k]) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
547
v->lines_in_det_luma = v->det_buffer_size_in_kbyte * 1024.0 / 2.0 / v->byte_per_pixel_in_dety[k] / v->swath_width_yper_state[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
548
v->lines_in_det_chroma = v->det_buffer_size_in_kbyte * 1024.0 / 2.0 / v->byte_per_pixel_in_detc[k] / (v->swath_width_yper_state[i][j][k] / 2.0);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
55
if (v->source_scan[k] == dcn_bw_hor) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
551
v->lines_in_det_luma = v->det_buffer_size_in_kbyte * 1024.0 * 2.0 / 3.0 / v->byte_per_pixel_in_dety[k] / v->swath_width_yper_state[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
552
v->lines_in_det_chroma = v->det_buffer_size_in_kbyte * 1024.0 / 3.0 / v->byte_per_pixel_in_dety[k] / (v->swath_width_yper_state[i][j][k] / 2.0);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
554
v->effective_lb_latency_hiding_source_lines_luma =dcn_bw_min2(v->max_line_buffer_lines,dcn_bw_floor2(v->line_buffer_size / v->lb_bit_per_pixel[k] / (v->swath_width_yper_state[i][j][k] /dcn_bw_max2(v->h_ratio[k], 1.0)), 1.0)) - (v->vtaps[k] - 1.0);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
555
v->effective_detlb_lines_luma =dcn_bw_floor2(v->lines_in_det_luma +dcn_bw_min2(v->lines_in_det_luma * v->required_dispclk[i][j] * v->byte_per_pixel_in_dety[k] * v->pscl_factor[k] / v->return_bw_per_state[i], v->effective_lb_latency_hiding_source_lines_luma), v->swath_height_yper_state[i][j][k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
556
if (v->byte_per_pixel_in_detc[k] == 0.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
557
v->urgent_latency_support_us_per_state[i][j][k] = v->effective_detlb_lines_luma * (v->htotal[k] / v->pixel_clock[k]) / v->v_ratio[k] - v->effective_detlb_lines_luma * v->swath_width_yper_state[i][j][k] *dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / (v->return_bw_per_state[i] / v->no_of_dpp[i][j][k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
56
v->h_ratio[k] =dcn_bw_max2(v->viewport_width[k] / v->scaler_rec_out_width[k], v->viewport_height[k] / v->scaler_recout_height[k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
560
v->effective_lb_latency_hiding_source_lines_chroma = dcn_bw_min2(v->max_line_buffer_lines, dcn_bw_floor2(v->line_buffer_size / v->lb_bit_per_pixel[k] / (v->swath_width_yper_state[i][j][k] / 2.0 / dcn_bw_max2(v->h_ratio[k] / 2.0, 1.0)), 1.0)) - (v->vta_pschroma[k] - 1.0);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
561
v->effective_detlb_lines_chroma = dcn_bw_floor2(v->lines_in_det_chroma + dcn_bw_min2(v->lines_in_det_chroma * v->required_dispclk[i][j] * v->byte_per_pixel_in_detc[k] * v->pscl_factor_chroma[k] / v->return_bw_per_state[i], v->effective_lb_latency_hiding_source_lines_chroma), v->swath_height_cper_state[i][j][k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
562
v->urgent_latency_support_us_per_state[i][j][k] = dcn_bw_min2(v->effective_detlb_lines_luma * (v->htotal[k] / v->pixel_clock[k]) / v->v_ratio[k] - v->effective_detlb_lines_luma * v->swath_width_yper_state[i][j][k] * dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / (v->return_bw_per_state[i] / v->no_of_dpp[i][j][k]), v->effective_detlb_lines_chroma * (v->htotal[k] / v->pixel_clock[k]) / (v->v_ratio[k] / 2.0) - v->effective_detlb_lines_chroma * v->swath_width_yper_state[i][j][k] / 2.0 * dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / (v->return_bw_per_state[i] / v->no_of_dpp[i][j][k]));
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
569
v->urgent_latency_support[i][j] = dcn_bw_yes;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
570
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
571
if (v->urgent_latency_support_us_per_state[i][j][k] < v->urgent_latency / 1.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
572
v->urgent_latency_support[i][j] = dcn_bw_no;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
581
v->total_number_of_dcc_active_dpp[i][j] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
582
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
583
if (v->dcc_enable[k] == dcn_bw_yes) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
584
v->total_number_of_dcc_active_dpp[i][j] = v->total_number_of_dcc_active_dpp[i][j] + v->no_of_dpp[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
59
v->h_ratio[k] =dcn_bw_max2(v->viewport_height[k] / v->scaler_rec_out_width[k], v->viewport_width[k] / v->scaler_recout_height[k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
591
v->projected_dcfclk_deep_sleep = 8.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
592
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
593
v->projected_dcfclk_deep_sleep =dcn_bw_max2(v->projected_dcfclk_deep_sleep, v->pixel_clock[k] / 16.0);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
594
if (v->byte_per_pixel_in_detc[k] == 0.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
595
if (v->v_ratio[k] <= 1.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
596
v->projected_dcfclk_deep_sleep =dcn_bw_max2(v->projected_dcfclk_deep_sleep, 1.1 *dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / 64.0 * v->h_ratio[k] * v->pixel_clock[k] / v->no_of_dpp[i][j][k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
599
v->projected_dcfclk_deep_sleep =dcn_bw_max2(v->projected_dcfclk_deep_sleep, 1.1 *dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / 64.0 * v->pscl_factor[k] * v->required_dispclk[i][j] / (1 + j));
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
603
if (v->v_ratio[k] <= 1.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
604
v->projected_dcfclk_deep_sleep =dcn_bw_max2(v->projected_dcfclk_deep_sleep, 1.1 *dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / 32.0 * v->h_ratio[k] * v->pixel_clock[k] / v->no_of_dpp[i][j][k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
607
v->projected_dcfclk_deep_sleep =dcn_bw_max2(v->projected_dcfclk_deep_sleep, 1.1 *dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / 32.0 * v->pscl_factor[k] * v->required_dispclk[i][j] / (1 + j));
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
609
if (v->v_ratio[k] / 2.0 <= 1.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
61
v->v_ratio[k] = v->h_ratio[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
610
v->projected_dcfclk_deep_sleep =dcn_bw_max2(v->projected_dcfclk_deep_sleep, 1.1 *dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / 32.0 * v->h_ratio[k] / 2.0 * v->pixel_clock[k] / v->no_of_dpp[i][j][k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
613
v->projected_dcfclk_deep_sleep =dcn_bw_max2(v->projected_dcfclk_deep_sleep, 1.1 *dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / 32.0 * v->pscl_factor_chroma[k] * v->required_dispclk[i][j] / (1 + j));
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
617
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
618
if (v->dcc_enable[k] == dcn_bw_yes) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
619
v->meta_req_height_y = 8.0 * v->read256_block_height_y[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
620
v->meta_req_width_y = 64.0 * 256.0 /dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / v->meta_req_height_y;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
621
v->meta_surface_width_y =dcn_bw_ceil2(v->viewport_width[k] / v->no_of_dpp[i][j][k] - 1.0, v->meta_req_width_y) + v->meta_req_width_y;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
622
v->meta_surface_height_y =dcn_bw_ceil2(v->viewport_height[k] - 1.0, v->meta_req_height_y) + v->meta_req_height_y;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
623
if (v->pte_enable == dcn_bw_yes) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
624
v->meta_pte_bytes_per_frame_y = (dcn_bw_ceil2((v->meta_surface_width_y * v->meta_surface_height_y *dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / 256.0 - 4096.0) / 8.0 / 4096.0, 1.0) + 1) * 64.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
627
v->meta_pte_bytes_per_frame_y = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
629
if (v->source_scan[k] == dcn_bw_hor) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
63
if (v->interlace_output[k] == 1.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
630
v->meta_row_bytes_y = v->meta_surface_width_y * v->meta_req_height_y *dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / 256.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
633
v->meta_row_bytes_y = v->meta_surface_height_y * v->meta_req_width_y *dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / 256.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
637
v->meta_pte_bytes_per_frame_y = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
638
v->meta_row_bytes_y = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
64
v->v_ratio[k] = 2.0 * v->v_ratio[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
640
if (v->pte_enable == dcn_bw_yes) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
641
if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
642
v->macro_tile_block_size_bytes_y = 256.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
643
v->macro_tile_block_height_y = 1.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
645
else if (v->source_surface_mode[k] == dcn_bw_sw_4_kb_s || v->source_surface_mode[k] == dcn_bw_sw_4_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d_x) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
646
v->macro_tile_block_size_bytes_y = 4096.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
647
v->macro_tile_block_height_y = 4.0 * v->read256_block_height_y[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
649
else if (v->source_surface_mode[k] == dcn_bw_sw_64_kb_s || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_x) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
650
v->macro_tile_block_size_bytes_y = 64.0 * 1024;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
651
v->macro_tile_block_height_y = 16.0 * v->read256_block_height_y[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
654
v->macro_tile_block_size_bytes_y = 256.0 * 1024;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
655
v->macro_tile_block_height_y = 32.0 * v->read256_block_height_y[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
657
if (v->macro_tile_block_size_bytes_y <= 65536.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
658
v->data_pte_req_height_y = v->macro_tile_block_height_y;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
66
if (v->underscan_output[k] == 1.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
661
v->data_pte_req_height_y = 16.0 * v->read256_block_height_y[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
663
v->data_pte_req_width_y = 4096.0 /dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / v->data_pte_req_height_y * 8;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
664
if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
665
v->dpte_bytes_per_row_y = 64.0 * (dcn_bw_ceil2((v->viewport_width[k] / v->no_of_dpp[i][j][k] *dcn_bw_min2(128.0, dcn_bw_pow(2.0,dcn_bw_floor2(dcn_bw_log(v->pte_buffer_size_in_requests * v->data_pte_req_width_y / (v->viewport_width[k] / v->no_of_dpp[i][j][k]), 2.0), 1.0))) - 1.0) / v->data_pte_req_width_y, 1.0) + 1);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
667
else if (v->source_scan[k] == dcn_bw_hor) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
668
v->dpte_bytes_per_row_y = 64.0 * (dcn_bw_ceil2((v->viewport_width[k] / v->no_of_dpp[i][j][k] - 1.0) / v->data_pte_req_width_y, 1.0) + 1);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
67
v->h_ratio[k] = v->h_ratio[k] * v->under_scan_factor;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
671
v->dpte_bytes_per_row_y = 64.0 * (dcn_bw_ceil2((v->viewport_height[k] - 1.0) / v->data_pte_req_height_y, 1.0) + 1);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
675
v->dpte_bytes_per_row_y = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
677
if ((v->source_pixel_format[k] != dcn_bw_rgb_sub_64 && v->source_pixel_format[k] != dcn_bw_rgb_sub_32 && v->source_pixel_format[k] != dcn_bw_rgb_sub_16)) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
678
if (v->dcc_enable[k] == dcn_bw_yes) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
679
v->meta_req_height_c = 8.0 * v->read256_block_height_c[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
68
v->v_ratio[k] = v->v_ratio[k] * v->under_scan_factor;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
680
v->meta_req_width_c = 64.0 * 256.0 /dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / v->meta_req_height_c;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
681
v->meta_surface_width_c =dcn_bw_ceil2(v->viewport_width[k] / v->no_of_dpp[i][j][k] / 2.0 - 1.0, v->meta_req_width_c) + v->meta_req_width_c;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
682
v->meta_surface_height_c =dcn_bw_ceil2(v->viewport_height[k] / 2.0 - 1.0, v->meta_req_height_c) + v->meta_req_height_c;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
683
if (v->pte_enable == dcn_bw_yes) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
684
v->meta_pte_bytes_per_frame_c = (dcn_bw_ceil2((v->meta_surface_width_c * v->meta_surface_height_c *dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / 256.0 - 4096.0) / 8.0 / 4096.0, 1.0) + 1) * 64.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
687
v->meta_pte_bytes_per_frame_c = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
689
if (v->source_scan[k] == dcn_bw_hor) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
690
v->meta_row_bytes_c = v->meta_surface_width_c * v->meta_req_height_c *dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / 256.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
693
v->meta_row_bytes_c = v->meta_surface_height_c * v->meta_req_width_c *dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / 256.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
697
v->meta_pte_bytes_per_frame_c = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
698
v->meta_row_bytes_c = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
700
if (v->pte_enable == dcn_bw_yes) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
701
if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
702
v->macro_tile_block_size_bytes_c = 256.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
703
v->macro_tile_block_height_c = 1.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
705
else if (v->source_surface_mode[k] == dcn_bw_sw_4_kb_s || v->source_surface_mode[k] == dcn_bw_sw_4_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d_x) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
706
v->macro_tile_block_size_bytes_c = 4096.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
707
v->macro_tile_block_height_c = 4.0 * v->read256_block_height_c[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
709
else if (v->source_surface_mode[k] == dcn_bw_sw_64_kb_s || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_x) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
710
v->macro_tile_block_size_bytes_c = 64.0 * 1024;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
711
v->macro_tile_block_height_c = 16.0 * v->read256_block_height_c[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
714
v->macro_tile_block_size_bytes_c = 256.0 * 1024;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
715
v->macro_tile_block_height_c = 32.0 * v->read256_block_height_c[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
717
v->macro_tile_block_width_c = v->macro_tile_block_size_bytes_c /dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / v->macro_tile_block_height_c;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
718
if (v->macro_tile_block_size_bytes_c <= 65536.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
719
v->data_pte_req_height_c = v->macro_tile_block_height_c;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
722
v->data_pte_req_height_c = 16.0 * v->read256_block_height_c[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
724
v->data_pte_req_width_c = 4096.0 /dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / v->data_pte_req_height_c * 8;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
725
if (v->source_surface_mode[k] == dcn_bw_sw_linear) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
726
v->dpte_bytes_per_row_c = 64.0 * (dcn_bw_ceil2((v->viewport_width[k] / v->no_of_dpp[i][j][k] / 2.0 * dcn_bw_min2(128.0, dcn_bw_pow(2.0,dcn_bw_floor2(dcn_bw_log(v->pte_buffer_size_in_requests * v->data_pte_req_width_c / (v->viewport_width[k] / v->no_of_dpp[i][j][k] / 2.0), 2.0), 1.0))) - 1.0) / v->data_pte_req_width_c, 1.0) + 1);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
728
else if (v->source_scan[k] == dcn_bw_hor) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
729
v->dpte_bytes_per_row_c = 64.0 * (dcn_bw_ceil2((v->viewport_width[k] / v->no_of_dpp[i][j][k] / 2.0 - 1.0) / v->data_pte_req_width_c, 1.0) + 1);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
73
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
732
v->dpte_bytes_per_row_c = 64.0 * (dcn_bw_ceil2((v->viewport_height[k] / 2.0 - 1.0) / v->data_pte_req_height_c, 1.0) + 1);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
736
v->dpte_bytes_per_row_c = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
74
if (v->h_ratio[k] > 1.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
740
v->dpte_bytes_per_row_c = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
741
v->meta_pte_bytes_per_frame_c = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
742
v->meta_row_bytes_c = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
744
v->dpte_bytes_per_row[k] = v->dpte_bytes_per_row_y + v->dpte_bytes_per_row_c;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
745
v->meta_pte_bytes_per_frame[k] = v->meta_pte_bytes_per_frame_y + v->meta_pte_bytes_per_frame_c;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
746
v->meta_row_bytes[k] = v->meta_row_bytes_y + v->meta_row_bytes_c;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
747
v->v_init_y = (v->v_ratio[k] + v->vtaps[k] + 1.0 + v->interlace_output[k] * 0.5 * v->v_ratio[k]) / 2.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
748
v->prefill_y[k] =dcn_bw_floor2(v->v_init_y, 1.0);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
749
v->max_num_sw_y[k] =dcn_bw_ceil2((v->prefill_y[k] - 1.0) / v->swath_height_yper_state[i][j][k], 1.0) + 1;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
75
v->acceptable_quality_hta_ps =dcn_bw_min2(v->max_hscl_taps, 2.0 *dcn_bw_ceil2(v->h_ratio[k], 1.0));
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
750
if (v->prefill_y[k] > 1.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
751
v->max_partial_sw_y =dcn_bw_mod((v->prefill_y[k] - 2.0), v->swath_height_yper_state[i][j][k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
754
v->max_partial_sw_y =dcn_bw_mod((v->prefill_y[k] + v->swath_height_yper_state[i][j][k] - 2.0), v->swath_height_yper_state[i][j][k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
756
v->max_partial_sw_y =dcn_bw_max2(1.0, v->max_partial_sw_y);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
757
v->prefetch_lines_y[k] = v->max_num_sw_y[k] * v->swath_height_yper_state[i][j][k] + v->max_partial_sw_y;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
758
if ((v->source_pixel_format[k] != dcn_bw_rgb_sub_64 && v->source_pixel_format[k] != dcn_bw_rgb_sub_32 && v->source_pixel_format[k] != dcn_bw_rgb_sub_16)) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
759
v->v_init_c = (v->v_ratio[k] / 2.0 + v->vtaps[k] + 1.0 + v->interlace_output[k] * 0.5 * v->v_ratio[k] / 2.0) / 2.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
760
v->prefill_c[k] =dcn_bw_floor2(v->v_init_c, 1.0);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
761
v->max_num_sw_c[k] =dcn_bw_ceil2((v->prefill_c[k] - 1.0) / v->swath_height_cper_state[i][j][k], 1.0) + 1;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
762
if (v->prefill_c[k] > 1.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
763
v->max_partial_sw_c =dcn_bw_mod((v->prefill_c[k] - 2.0), v->swath_height_cper_state[i][j][k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
766
v->max_partial_sw_c =dcn_bw_mod((v->prefill_c[k] + v->swath_height_cper_state[i][j][k] - 2.0), v->swath_height_cper_state[i][j][k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
768
v->max_partial_sw_c =dcn_bw_max2(1.0, v->max_partial_sw_c);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
769
v->prefetch_lines_c[k] = v->max_num_sw_c[k] * v->swath_height_cper_state[i][j][k] + v->max_partial_sw_c;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
77
else if (v->h_ratio[k] < 1.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
772
v->prefetch_lines_c[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
774
v->dst_x_after_scaler = 90.0 * v->pixel_clock[k] / (v->required_dispclk[i][j] / (j + 1)) + 42.0 * v->pixel_clock[k] / v->required_dispclk[i][j];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
775
if (v->no_of_dpp[i][j][k] > 1.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
776
v->dst_x_after_scaler = v->dst_x_after_scaler + v->scaler_rec_out_width[k] / 2.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
778
if (v->output_format[k] == dcn_bw_420) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
779
v->dst_y_after_scaler = 1.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
78
v->acceptable_quality_hta_ps = 4.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
782
v->dst_y_after_scaler = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
784
v->time_calc = 24.0 / v->projected_dcfclk_deep_sleep;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
785
v->v_update_offset[k][j] = dcn_bw_ceil2(v->htotal[k] / 4.0, 1.0);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
786
v->total_repeater_delay = v->max_inter_dcn_tile_repeaters * (2.0 / (v->required_dispclk[i][j] / (j + 1)) + 3.0 / v->required_dispclk[i][j]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
787
v->v_update_width[k][j] = (14.0 / v->projected_dcfclk_deep_sleep + 12.0 / (v->required_dispclk[i][j] / (j + 1)) + v->total_repeater_delay) * v->pixel_clock[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
788
v->v_ready_offset[k][j] = dcn_bw_max2(150.0 / (v->required_dispclk[i][j] / (j + 1)), v->total_repeater_delay + 20.0 / v->projected_dcfclk_deep_sleep + 10.0 / (v->required_dispclk[i][j] / (j + 1))) * v->pixel_clock[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
789
v->time_setup = (v->v_update_offset[k][j] + v->v_update_width[k][j] + v->v_ready_offset[k][j]) / v->pixel_clock[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
790
v->extra_latency = v->urgent_round_trip_and_out_of_order_latency_per_state[i] + (v->total_number_of_active_dpp[i][j] * v->pixel_chunk_size_in_kbyte + v->total_number_of_dcc_active_dpp[i][j] * v->meta_chunk_size) * 1024.0 / v->return_bw_per_state[i];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
791
if (v->pte_enable == dcn_bw_yes) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
792
v->extra_latency = v->extra_latency + v->total_number_of_active_dpp[i][j] * v->pte_chunk_size * 1024.0 / v->return_bw_per_state[i];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
794
if (v->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one == dcn_bw_yes) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
795
v->maximum_vstartup = v->vtotal[k] - v->vactive[k] - 1.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
798
v->maximum_vstartup = v->v_sync_plus_back_porch[k] - 1.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
802
v->line_times_for_prefetch[k] = v->maximum_vstartup - v->urgent_latency / (v->htotal[k] / v->pixel_clock[k]) - (v->time_calc + v->time_setup) / (v->htotal[k] / v->pixel_clock[k]) - (v->dst_y_after_scaler + v->dst_x_after_scaler / v->htotal[k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
803
v->line_times_for_prefetch[k] =dcn_bw_floor2(4.0 * (v->line_times_for_prefetch[k] + 0.125), 1.0) / 4;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
804
v->prefetch_bw[k] = (v->meta_pte_bytes_per_frame[k] + 2.0 * v->meta_row_bytes[k] + 2.0 * v->dpte_bytes_per_row[k] + v->prefetch_lines_y[k] * v->swath_width_yper_state[i][j][k] *dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) + v->prefetch_lines_c[k] * v->swath_width_yper_state[i][j][k] / 2.0 *dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0)) / (v->line_times_for_prefetch[k] * v->htotal[k] / v->pixel_clock[k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
806
if (v->pte_enable == dcn_bw_yes && v->dcc_enable[k] == dcn_bw_yes) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
807
v->time_for_meta_pte_without_immediate_flip = dcn_bw_max3(
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
808
v->meta_pte_bytes_frame[k] / v->prefetch_bw[k],
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
809
v->extra_latency,
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
81
v->acceptable_quality_hta_ps = 1.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
810
v->htotal[k] / v->pixel_clock[k] / 4.0);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
812
v->time_for_meta_pte_without_immediate_flip = v->htotal[k] / v->pixel_clock[k] / 4.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
815
if (v->pte_enable == dcn_bw_yes || v->dcc_enable[k] == dcn_bw_yes) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
816
v->time_for_meta_and_dpte_row_without_immediate_flip = dcn_bw_max3((
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
817
v->meta_row_bytes[k] + v->dpte_bytes_per_row[k]) / v->prefetch_bw[k],
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
818
v->htotal[k] / v->pixel_clock[k] - v->time_for_meta_pte_without_immediate_flip,
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
819
v->extra_latency);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
821
v->time_for_meta_and_dpte_row_without_immediate_flip = dcn_bw_max2(
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
822
v->htotal[k] / v->pixel_clock[k] - v->time_for_meta_pte_without_immediate_flip,
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
823
v->extra_latency - v->time_for_meta_pte_with_immediate_flip);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
826
v->lines_for_meta_pte_without_immediate_flip[k] =dcn_bw_floor2(4.0 * (v->time_for_meta_pte_without_immediate_flip / (v->htotal[k] / v->pixel_clock[k]) + 0.125), 1.0) / 4;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
827
v->lines_for_meta_and_dpte_row_without_immediate_flip[k] =dcn_bw_floor2(4.0 * (v->time_for_meta_and_dpte_row_without_immediate_flip / (v->htotal[k] / v->pixel_clock[k]) + 0.125), 1.0) / 4;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
828
v->maximum_vstartup = v->maximum_vstartup - 1;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
83
if (v->ta_pscalculation == dcn_bw_override) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
830
if (v->lines_for_meta_pte_without_immediate_flip[k] < 32.0 && v->lines_for_meta_and_dpte_row_without_immediate_flip[k] < 16.0)
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
835
v->bw_available_for_immediate_flip = v->return_bw_per_state[i];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
836
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
837
v->bw_available_for_immediate_flip = v->bw_available_for_immediate_flip -dcn_bw_max2(v->read_bandwidth[k], v->prefetch_bw[k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
839
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
84
v->htaps[k] = v->override_hta_ps[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
840
v->total_immediate_flip_bytes[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
841
if ((v->source_pixel_format[k] != dcn_bw_yuv420_sub_8 && v->source_pixel_format[k] != dcn_bw_yuv420_sub_10)) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
842
v->total_immediate_flip_bytes[k] = v->total_immediate_flip_bytes[k] + v->meta_pte_bytes_per_frame[k] + v->meta_row_bytes[k] + v->dpte_bytes_per_row[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
845
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
846
if (v->pte_enable == dcn_bw_yes && v->dcc_enable[k] == dcn_bw_yes) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
847
v->time_for_meta_pte_with_immediate_flip =dcn_bw_max5(v->meta_pte_bytes_per_frame[k] / v->prefetch_bw[k], v->meta_pte_bytes_per_frame[k] * v->total_immediate_flip_bytes[k] / (v->bw_available_for_immediate_flip * (v->meta_pte_bytes_per_frame[k] + v->meta_row_bytes[k] + v->dpte_bytes_per_row[k])), v->extra_latency, v->urgent_latency, v->htotal[k] / v->pixel_clock[k] / 4.0);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
850
v->time_for_meta_pte_with_immediate_flip = v->htotal[k] / v->pixel_clock[k] / 4.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
852
if (v->pte_enable == dcn_bw_yes || v->dcc_enable[k] == dcn_bw_yes) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
853
v->time_for_meta_and_dpte_row_with_immediate_flip =dcn_bw_max5((v->meta_row_bytes[k] + v->dpte_bytes_per_row[k]) / v->prefetch_bw[k], (v->meta_row_bytes[k] + v->dpte_bytes_per_row[k]) * v->total_immediate_flip_bytes[k] / (v->bw_available_for_immediate_flip * (v->meta_pte_bytes_per_frame[k] + v->meta_row_bytes[k] + v->dpte_bytes_per_row[k])), v->htotal[k] / v->pixel_clock[k] - v->time_for_meta_pte_with_immediate_flip, v->extra_latency, 2.0 * v->urgent_latency);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
856
v->time_for_meta_and_dpte_row_with_immediate_flip =dcn_bw_max2(v->htotal[k] / v->pixel_clock[k] - v->time_for_meta_pte_with_immediate_flip, v->extra_latency - v->time_for_meta_pte_with_immediate_flip);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
858
v->lines_for_meta_pte_with_immediate_flip[k] =dcn_bw_floor2(4.0 * (v->time_for_meta_pte_with_immediate_flip / (v->htotal[k] / v->pixel_clock[k]) + 0.125), 1.0) / 4;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
859
v->lines_for_meta_and_dpte_row_with_immediate_flip[k] =dcn_bw_floor2(4.0 * (v->time_for_meta_and_dpte_row_with_immediate_flip / (v->htotal[k] / v->pixel_clock[k]) + 0.125), 1.0) / 4;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
860
v->line_times_to_request_prefetch_pixel_data_with_immediate_flip = v->line_times_for_prefetch[k] - v->lines_for_meta_pte_with_immediate_flip[k] - v->lines_for_meta_and_dpte_row_with_immediate_flip[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
861
v->line_times_to_request_prefetch_pixel_data_without_immediate_flip = v->line_times_for_prefetch[k] - v->lines_for_meta_pte_without_immediate_flip[k] - v->lines_for_meta_and_dpte_row_without_immediate_flip[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
862
if (v->line_times_to_request_prefetch_pixel_data_with_immediate_flip > 0.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
863
v->v_ratio_pre_ywith_immediate_flip[i][j][k] = v->prefetch_lines_y[k] / v->line_times_to_request_prefetch_pixel_data_with_immediate_flip;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
864
if ((v->swath_height_yper_state[i][j][k] > 4.0)) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
865
if (v->line_times_to_request_prefetch_pixel_data_with_immediate_flip - (v->prefill_y[k] - 3.0) / 2.0 > 0.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
866
v->v_ratio_pre_ywith_immediate_flip[i][j][k] =dcn_bw_max2(v->v_ratio_pre_ywith_immediate_flip[i][j][k], (v->max_num_sw_y[k] * v->swath_height_yper_state[i][j][k]) / (v->line_times_to_request_prefetch_pixel_data_with_immediate_flip - (v->prefill_y[k] - 3.0) / 2.0));
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
869
v->v_ratio_pre_ywith_immediate_flip[i][j][k] = 999999.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
87
v->htaps[k] = v->acceptable_quality_hta_ps;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
872
v->v_ratio_pre_cwith_immediate_flip[i][j][k] = v->prefetch_lines_c[k] / v->line_times_to_request_prefetch_pixel_data_with_immediate_flip;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
873
if ((v->swath_height_cper_state[i][j][k] > 4.0)) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
874
if (v->line_times_to_request_prefetch_pixel_data_with_immediate_flip - (v->prefill_c[k] - 3.0) / 2.0 > 0.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
875
v->v_ratio_pre_cwith_immediate_flip[i][j][k] =dcn_bw_max2(v->v_ratio_pre_cwith_immediate_flip[i][j][k], (v->max_num_sw_c[k] * v->swath_height_cper_state[i][j][k]) / (v->line_times_to_request_prefetch_pixel_data_with_immediate_flip - (v->prefill_c[k] - 3.0) / 2.0));
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
878
v->v_ratio_pre_cwith_immediate_flip[i][j][k] = 999999.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
881
v->required_prefetch_pixel_data_bw_with_immediate_flip[i][j][k] = v->no_of_dpp[i][j][k] * (v->prefetch_lines_y[k] / v->line_times_to_request_prefetch_pixel_data_with_immediate_flip *dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) + v->prefetch_lines_c[k] / v->line_times_to_request_prefetch_pixel_data_with_immediate_flip *dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / 2.0) * v->swath_width_yper_state[i][j][k] / (v->htotal[k] / v->pixel_clock[k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
884
v->v_ratio_pre_ywith_immediate_flip[i][j][k] = 999999.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
885
v->v_ratio_pre_cwith_immediate_flip[i][j][k] = 999999.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
886
v->required_prefetch_pixel_data_bw_with_immediate_flip[i][j][k] = 999999.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
888
if (v->line_times_to_request_prefetch_pixel_data_without_immediate_flip > 0.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
889
v->v_ratio_pre_ywithout_immediate_flip[i][j][k] = v->prefetch_lines_y[k] / v->line_times_to_request_prefetch_pixel_data_without_immediate_flip;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
89
if (v->v_ratio[k] > 1.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
890
if ((v->swath_height_yper_state[i][j][k] > 4.0)) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
891
if (v->line_times_to_request_prefetch_pixel_data_without_immediate_flip - (v->prefill_y[k] - 3.0) / 2.0 > 0.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
892
v->v_ratio_pre_ywithout_immediate_flip[i][j][k] =dcn_bw_max2(v->v_ratio_pre_ywithout_immediate_flip[i][j][k], (v->max_num_sw_y[k] * v->swath_height_yper_state[i][j][k]) / (v->line_times_to_request_prefetch_pixel_data_without_immediate_flip - (v->prefill_y[k] - 3.0) / 2.0));
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
895
v->v_ratio_pre_ywithout_immediate_flip[i][j][k] = 999999.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
898
v->v_ratio_pre_cwithout_immediate_flip[i][j][k] = v->prefetch_lines_c[k] / v->line_times_to_request_prefetch_pixel_data_without_immediate_flip;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
899
if ((v->swath_height_cper_state[i][j][k] > 4.0)) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
90
v->acceptable_quality_vta_ps =dcn_bw_min2(v->max_vscl_taps, 2.0 *dcn_bw_ceil2(v->v_ratio[k], 1.0));
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
900
if (v->line_times_to_request_prefetch_pixel_data_without_immediate_flip - (v->prefill_c[k] - 3.0) / 2.0 > 0.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
901
v->v_ratio_pre_cwithout_immediate_flip[i][j][k] =dcn_bw_max2(v->v_ratio_pre_cwithout_immediate_flip[i][j][k], (v->max_num_sw_c[k] * v->swath_height_cper_state[i][j][k]) / (v->line_times_to_request_prefetch_pixel_data_without_immediate_flip - (v->prefill_c[k] - 3.0) / 2.0));
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
904
v->v_ratio_pre_cwithout_immediate_flip[i][j][k] = 999999.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
907
v->required_prefetch_pixel_data_bw_without_immediate_flip[i][j][k] = v->no_of_dpp[i][j][k] * (v->prefetch_lines_y[k] / v->line_times_to_request_prefetch_pixel_data_without_immediate_flip *dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) + v->prefetch_lines_c[k] / v->line_times_to_request_prefetch_pixel_data_without_immediate_flip *dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / 2.0) * v->swath_width_yper_state[i][j][k] / (v->htotal[k] / v->pixel_clock[k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
910
v->v_ratio_pre_ywithout_immediate_flip[i][j][k] = 999999.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
911
v->v_ratio_pre_cwithout_immediate_flip[i][j][k] = 999999.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
912
v->required_prefetch_pixel_data_bw_without_immediate_flip[i][j][k] = 999999.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
915
v->maximum_read_bandwidth_with_prefetch_with_immediate_flip = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
916
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
917
if ((v->source_pixel_format[k] != dcn_bw_yuv420_sub_8 && v->source_pixel_format[k] != dcn_bw_yuv420_sub_10)) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
918
v->maximum_read_bandwidth_with_prefetch_with_immediate_flip = v->maximum_read_bandwidth_with_prefetch_with_immediate_flip +dcn_bw_max2(v->read_bandwidth[k], v->required_prefetch_pixel_data_bw_with_immediate_flip[i][j][k]) +dcn_bw_max2(v->meta_pte_bytes_per_frame[k] / (v->lines_for_meta_pte_with_immediate_flip[k] * v->htotal[k] / v->pixel_clock[k]), (v->meta_row_bytes[k] + v->dpte_bytes_per_row[k]) / (v->lines_for_meta_and_dpte_row_with_immediate_flip[k] * v->htotal[k] / v->pixel_clock[k]));
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
92
else if (v->v_ratio[k] < 1.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
921
v->maximum_read_bandwidth_with_prefetch_with_immediate_flip = v->maximum_read_bandwidth_with_prefetch_with_immediate_flip +dcn_bw_max2(v->read_bandwidth[k], v->required_prefetch_pixel_data_bw_without_immediate_flip[i][j][k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
924
v->maximum_read_bandwidth_with_prefetch_without_immediate_flip = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
925
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
926
v->maximum_read_bandwidth_with_prefetch_without_immediate_flip = v->maximum_read_bandwidth_with_prefetch_without_immediate_flip +dcn_bw_max2(v->read_bandwidth[k], v->required_prefetch_pixel_data_bw_without_immediate_flip[i][j][k]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
928
v->prefetch_supported_with_immediate_flip[i][j] = dcn_bw_yes;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
929
if (v->maximum_read_bandwidth_with_prefetch_with_immediate_flip > v->return_bw_per_state[i]) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
93
v->acceptable_quality_vta_ps = 4.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
930
v->prefetch_supported_with_immediate_flip[i][j] = dcn_bw_no;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
932
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
933
if (v->line_times_for_prefetch[k] < 2.0 || v->lines_for_meta_pte_with_immediate_flip[k] >= 8.0 || v->lines_for_meta_and_dpte_row_with_immediate_flip[k] >= 16.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
934
v->prefetch_supported_with_immediate_flip[i][j] = dcn_bw_no;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
937
v->prefetch_supported_without_immediate_flip[i][j] = dcn_bw_yes;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
938
if (v->maximum_read_bandwidth_with_prefetch_without_immediate_flip > v->return_bw_per_state[i]) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
939
v->prefetch_supported_without_immediate_flip[i][j] = dcn_bw_no;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
941
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
942
if (v->line_times_for_prefetch[k] < 2.0 || v->lines_for_meta_pte_without_immediate_flip[k] >= 8.0 || v->lines_for_meta_and_dpte_row_without_immediate_flip[k] >= 16.0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
943
v->prefetch_supported_without_immediate_flip[i][j] = dcn_bw_no;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
950
v->v_ratio_in_prefetch_supported_with_immediate_flip[i][j] = dcn_bw_yes;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
951
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
952
if ((((v->source_pixel_format[k] != dcn_bw_yuv420_sub_8 && v->source_pixel_format[k] != dcn_bw_yuv420_sub_10) && (v->v_ratio_pre_ywith_immediate_flip[i][j][k] > 4.0 || v->v_ratio_pre_cwith_immediate_flip[i][j][k] > 4.0)) || ((v->source_pixel_format[k] == dcn_bw_yuv420_sub_8 || v->source_pixel_format[k] == dcn_bw_yuv420_sub_10) && (v->v_ratio_pre_ywithout_immediate_flip[i][j][k] > 4.0 || v->v_ratio_pre_cwithout_immediate_flip[i][j][k] > 4.0)))) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
953
v->v_ratio_in_prefetch_supported_with_immediate_flip[i][j] = dcn_bw_no;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
956
v->v_ratio_in_prefetch_supported_without_immediate_flip[i][j] = dcn_bw_yes;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
957
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
958
if ((v->v_ratio_pre_ywithout_immediate_flip[i][j][k] > 4.0 || v->v_ratio_pre_cwithout_immediate_flip[i][j][k] > 4.0)) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
959
v->v_ratio_in_prefetch_supported_without_immediate_flip[i][j] = dcn_bw_no;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
96
v->acceptable_quality_vta_ps = 1.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
968
if (v->scale_ratio_support == dcn_bw_yes && v->source_format_pixel_and_scan_support == dcn_bw_yes && v->viewport_size_support == dcn_bw_yes && v->bandwidth_support[i] == dcn_bw_yes && v->dio_support[i] == dcn_bw_yes && v->urgent_latency_support[i][j] == dcn_bw_yes && v->rob_support[i] == dcn_bw_yes && v->dispclk_dppclk_support[i][j] == dcn_bw_yes && v->total_available_pipes_support[i][j] == dcn_bw_yes && v->total_available_writeback_support == dcn_bw_yes && v->writeback_latency_support == dcn_bw_yes) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
969
if (v->prefetch_supported_with_immediate_flip[i][j] == dcn_bw_yes && v->v_ratio_in_prefetch_supported_with_immediate_flip[i][j] == dcn_bw_yes) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
970
v->mode_support_with_immediate_flip[i][j] = dcn_bw_yes;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
973
v->mode_support_with_immediate_flip[i][j] = dcn_bw_no;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
975
if (v->prefetch_supported_without_immediate_flip[i][j] == dcn_bw_yes && v->v_ratio_in_prefetch_supported_without_immediate_flip[i][j] == dcn_bw_yes) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
976
v->mode_support_without_immediate_flip[i][j] = dcn_bw_yes;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
979
v->mode_support_without_immediate_flip[i][j] = dcn_bw_no;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
98
if (v->ta_pscalculation == dcn_bw_override) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
983
v->mode_support_with_immediate_flip[i][j] = dcn_bw_no;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
984
v->mode_support_without_immediate_flip[i][j] = dcn_bw_no;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
989
if ((i == number_of_states_plus_one || v->mode_support_with_immediate_flip[i][1] == dcn_bw_yes || v->mode_support_with_immediate_flip[i][0] == dcn_bw_yes) && i >= v->voltage_override_level) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
99
v->vtaps[k] = v->override_vta_ps[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
990
v->voltage_level_with_immediate_flip = i;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
994
if ((i == number_of_states_plus_one || v->mode_support_without_immediate_flip[i][1] == dcn_bw_yes || v->mode_support_without_immediate_flip[i][0] == dcn_bw_yes) && i >= v->voltage_override_level) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
995
v->voltage_level_without_immediate_flip = i;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
998
if (v->voltage_level_with_immediate_flip == number_of_states_plus_one) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c
999
v->immediate_flip_supported = dcn_bw_no;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.h
32
void scaler_settings_calculation(struct dcn_bw_internal_vars *v);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.h
33
void mode_support_and_system_configuration(struct dcn_bw_internal_vars *v);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.h
34
void display_pipe_configuration(struct dcn_bw_internal_vars *v);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.h
36
struct dcn_bw_internal_vars *v);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1003
v->dcc_enable[input_idx] = dc->res_pool->hubbub->funcs->dcc_support_pixel_format(
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1007
v->source_pixel_format[input_idx] = tl_pixel_format_to_bw_defs(
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1009
v->source_surface_mode[input_idx] = tl_sw_mode_to_bw_defs(
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1011
v->lb_bit_per_pixel[input_idx] = tl_lb_bpp_to_int(pipe->plane_res.scl_data.lb_params.depth);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1012
v->override_hta_ps[input_idx] = pipe->plane_res.scl_data.taps.h_taps;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1013
v->override_vta_ps[input_idx] = pipe->plane_res.scl_data.taps.v_taps;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1014
v->override_hta_pschroma[input_idx] = pipe->plane_res.scl_data.taps.h_taps_c;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1015
v->override_vta_pschroma[input_idx] = pipe->plane_res.scl_data.taps.v_taps_c;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1021
if (v->override_hta_pschroma[input_idx] == 1)
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1022
v->override_hta_pschroma[input_idx] = 2;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1023
if (v->override_vta_pschroma[input_idx] == 1)
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1024
v->override_vta_pschroma[input_idx] = 2;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1025
v->source_scan[input_idx] = (pipe->plane_state->rotation % 2) ? dcn_bw_vert : dcn_bw_hor;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1027
if (v->is_line_buffer_bpp_fixed == dcn_bw_yes)
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1028
v->lb_bit_per_pixel[input_idx] = v->line_buffer_fixed_bpp;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1029
v->dcc_rate[input_idx] = 1; /*TODO: Worst case? does this change?*/
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1030
v->output_format[input_idx] = pipe->stream->timing.pixel_encoding ==
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1032
v->output[input_idx] = pipe->stream->signal ==
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1034
v->output_deep_color[input_idx] = dcn_bw_encoder_8bpc;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1035
if (v->output[input_idx] == dcn_bw_hdmi) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1038
v->output_deep_color[input_idx] = dcn_bw_encoder_10bpc;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1041
v->output_deep_color[input_idx] = dcn_bw_encoder_12bpc;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1044
v->output_deep_color[input_idx] = dcn_bw_encoder_16bpc;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1053
v->number_of_active_planes = input_idx;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1055
scaler_settings_calculation(v);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1057
hack_bounding_box(v, &dc->debug, context);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1059
mode_support_and_system_configuration(v);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1062
if (v->voltage_level != 0
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1065
v->max_dppclk[0] = v->max_dppclk_vmin0p65;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1066
mode_support_and_system_configuration(v);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1069
if (v->voltage_level == 0 &&
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1074
v->sr_enter_plus_exit_time =
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1077
v->sr_exit_time = dc->debug.sr_exit_time_dpm0_ns / 1000.0f;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1078
context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = v->sr_enter_plus_exit_time;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1079
context->bw_ctx.dml.soc.sr_exit_time_us = v->sr_exit_time;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1080
mode_support_and_system_configuration(v);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1083
display_pipe_configuration(v);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1085
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1086
if (v->source_scan[k] == dcn_bw_hor)
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1087
v->swath_width_y[k] = v->viewport_width[k] / v->dpp_per_plane[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1089
v->swath_width_y[k] = v->viewport_height[k] / v->dpp_per_plane[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1091
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1092
if (v->source_pixel_format[k] == dcn_bw_rgb_sub_64) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1093
v->byte_per_pixel_dety[k] = 8.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1094
v->byte_per_pixel_detc[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1095
} else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_32) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1096
v->byte_per_pixel_dety[k] = 4.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1097
v->byte_per_pixel_detc[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1098
} else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_16) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1099
v->byte_per_pixel_dety[k] = 2.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1100
v->byte_per_pixel_detc[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1101
} else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1102
v->byte_per_pixel_dety[k] = 1.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1103
v->byte_per_pixel_detc[k] = 2.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1105
v->byte_per_pixel_dety[k] = 4.0f / 3.0f;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1106
v->byte_per_pixel_detc[k] = 8.0f / 3.0f;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1110
v->total_data_read_bandwidth = 0.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1111
for (k = 0; k <= v->number_of_active_planes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1112
v->read_bandwidth_plane_luma[k] = v->swath_width_y[k] * v->dpp_per_plane[k] *
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1113
dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) / (v->htotal[k] / v->pixel_clock[k]) * v->v_ratio[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1114
v->read_bandwidth_plane_chroma[k] = v->swath_width_y[k] / 2.0 * v->dpp_per_plane[k] *
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1115
dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0) / (v->htotal[k] / v->pixel_clock[k]) * v->v_ratio[k] / 2.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1116
v->total_data_read_bandwidth = v->total_data_read_bandwidth +
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1117
v->read_bandwidth_plane_luma[k] + v->read_bandwidth_plane_chroma[k];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1122
if (v->voltage_level != number_of_states_plus_one && validate_mode == DC_VALIDATE_MODE_AND_PROGRAMMING) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1123
float bw_consumed = v->total_bandwidth_consumed_gbyte_per_second;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1125
if (bw_consumed < v->fabric_and_dram_bandwidth_vmin0p65)
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1126
bw_consumed = v->fabric_and_dram_bandwidth_vmin0p65;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1127
else if (bw_consumed < v->fabric_and_dram_bandwidth_vmid0p72)
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1128
bw_consumed = v->fabric_and_dram_bandwidth_vmid0p72;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1129
else if (bw_consumed < v->fabric_and_dram_bandwidth_vnom0p8)
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1130
bw_consumed = v->fabric_and_dram_bandwidth_vnom0p8;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1132
bw_consumed = v->fabric_and_dram_bandwidth_vmax0p9;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1134
if (bw_consumed < v->fabric_and_dram_bandwidth)
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1136
bw_consumed = v->fabric_and_dram_bandwidth;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1138
display_pipe_configuration(v);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1143
dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1146
v->stutter_exit_watermark * 1000;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1148
v->stutter_enter_plus_exit_watermark * 1000;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1150
v->dram_clock_change_watermark * 1000;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1151
context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1152
context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = v->urgent_watermark * 1000;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1158
(ddr4_dram_factor_single_Channel * v->number_of_channels));
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1159
if (bw_consumed == v->fabric_and_dram_bandwidth_vmin0p65)
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1162
context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = (int)(v->dcf_clk_deep_sleep * 1000);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1163
context->bw_ctx.bw.dcn.clk.dcfclk_khz = (int)(v->dcfclk * 1000);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1165
context->bw_ctx.bw.dcn.clk.dispclk_khz = (int)(v->dispclk * 1000);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1176
v->dispclk_dppclk_ratio;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1177
context->bw_ctx.bw.dcn.clk.phyclk_khz = v->phyclk_per_state[v->voltage_level];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1178
switch (v->voltage_level) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1209
pipe->pipe_dlg_param.vupdate_width = v->v_update_width_pix[input_idx];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1210
pipe->pipe_dlg_param.vupdate_offset = v->v_update_offset_pix[input_idx];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1211
pipe->pipe_dlg_param.vready_offset = v->v_ready_offset_pix[input_idx];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1212
pipe->pipe_dlg_param.vstartup_start = v->v_startup[input_idx];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1239
if (v->dpp_per_plane[input_idx] == 2 ||
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1250
hsplit_pipe->pipe_dlg_param.vupdate_width = v->v_update_width_pix[input_idx];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1251
hsplit_pipe->pipe_dlg_param.vupdate_offset = v->v_update_offset_pix[input_idx];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1252
hsplit_pipe->pipe_dlg_param.vready_offset = v->v_ready_offset_pix[input_idx];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1253
hsplit_pipe->pipe_dlg_param.vstartup_start = v->v_startup[input_idx];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1266
dcn_bw_calc_rq_dlg_ttu(dc, v, hsplit_pipe, input_idx);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1282
dcn_bw_calc_rq_dlg_ttu(dc, v, pipe, input_idx);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1287
} else if (v->voltage_level == number_of_states_plus_one) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1293
if (v->voltage_level == 0) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1303
bw_limit = dc->dcn_soc->percent_disp_bw_limit * v->fabric_and_dram_bandwidth_vmax0p9;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1304
bw_limit_pass = (v->total_data_read_bandwidth / 1000.0) < bw_limit;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
1309
if (bw_limit_pass && v->voltage_level <= get_highest_allowed_voltage_level(dc->config.is_vmin_only_asic))
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
401
input->scale_ratio_depth.vinit = pipe->plane_res.scl_data.inits.v.value/4294967296.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
454
const struct dcn_bw_internal_vars *v,
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
478
total_active_bw += v->read_bandwidth[i];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
479
total_prefetch_bw += v->prefetch_bandwidth[i];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
480
total_flip_bytes += v->total_immediate_flip_bytes[i];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
482
dlg_sys_param->total_flip_bw = v->return_bw - dcn_bw_max2(total_active_bw, total_prefetch_bw);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
486
dlg_sys_param->t_mclk_wm_us = v->dram_clock_change_watermark;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
487
dlg_sys_param->t_sr_wm_us = v->stutter_enter_plus_exit_watermark;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
488
dlg_sys_param->t_urg_wm_us = v->urgent_watermark;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
489
dlg_sys_param->t_extra_us = v->urgent_extra_latency;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
490
dlg_sys_param->deepsleep_dcfclk_mhz = v->dcf_clk_deep_sleep;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
494
input->clks_cfg.dcfclk_mhz = v->dcfclk;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
495
input->clks_cfg.dispclk_mhz = v->dispclk;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
496
input->clks_cfg.dppclk_mhz = v->dppclk;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
498
input->clks_cfg.socclk_mhz = v->socclk;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
499
input->clks_cfg.voltage = v->voltage_level;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
501
input->dout.output_format = (v->output_format[in_idx] == dcn_bw_420) ? dm_420 : dm_444;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
502
input->dout.output_type = (v->output[in_idx] == dcn_bw_hdmi) ? dm_hdmi : dm_dp;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
518
v->pte_enable == dcn_bw_yes,
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
557
struct dcn_bw_internal_vars *v)
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
560
if (v->voltage_level < 2) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
561
v->fabric_and_dram_bandwidth_per_state[1] = v->fabric_and_dram_bandwidth_vnom0p8;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
562
v->fabric_and_dram_bandwidth_per_state[0] = v->fabric_and_dram_bandwidth_vnom0p8;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
563
v->fabric_and_dram_bandwidth = v->fabric_and_dram_bandwidth_vnom0p8;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
564
dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
567
v->stutter_exit_watermark * 1000;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
569
v->stutter_enter_plus_exit_watermark * 1000;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
571
v->dram_clock_change_watermark * 1000;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
572
context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
573
context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = v->urgent_watermark * 1000;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
575
v->dcfclk_per_state[1] = v->dcfclkv_nom0p8;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
576
v->dcfclk_per_state[0] = v->dcfclkv_nom0p8;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
577
v->dcfclk = v->dcfclkv_nom0p8;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
578
dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
581
v->stutter_exit_watermark * 1000;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
583
v->stutter_enter_plus_exit_watermark * 1000;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
585
v->dram_clock_change_watermark * 1000;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
586
context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
587
context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = v->urgent_watermark * 1000;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
590
if (v->voltage_level < 3) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
591
v->fabric_and_dram_bandwidth_per_state[2] = v->fabric_and_dram_bandwidth_vmax0p9;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
592
v->fabric_and_dram_bandwidth_per_state[1] = v->fabric_and_dram_bandwidth_vmax0p9;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
593
v->fabric_and_dram_bandwidth_per_state[0] = v->fabric_and_dram_bandwidth_vmax0p9;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
594
v->fabric_and_dram_bandwidth = v->fabric_and_dram_bandwidth_vmax0p9;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
595
v->dcfclk_per_state[2] = v->dcfclkv_max0p9;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
596
v->dcfclk_per_state[1] = v->dcfclkv_max0p9;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
597
v->dcfclk_per_state[0] = v->dcfclkv_max0p9;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
598
v->dcfclk = v->dcfclkv_max0p9;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
599
dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
602
v->stutter_exit_watermark * 1000;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
604
v->stutter_enter_plus_exit_watermark * 1000;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
606
v->dram_clock_change_watermark * 1000;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
607
context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
608
context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = v->urgent_watermark * 1000;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
611
v->fabric_and_dram_bandwidth_per_state[2] = v->fabric_and_dram_bandwidth_vnom0p8;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
612
v->fabric_and_dram_bandwidth_per_state[1] = v->fabric_and_dram_bandwidth_vmid0p72;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
613
v->fabric_and_dram_bandwidth_per_state[0] = v->fabric_and_dram_bandwidth_vmin0p65;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
614
v->fabric_and_dram_bandwidth = v->fabric_and_dram_bandwidth_per_state[v->voltage_level];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
615
v->dcfclk_per_state[2] = v->dcfclkv_nom0p8;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
616
v->dcfclk_per_state[1] = v->dcfclkv_mid0p72;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
617
v->dcfclk_per_state[0] = v->dcfclkv_min0p65;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
618
v->dcfclk = v->dcfclk_per_state[v->voltage_level];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
619
dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
622
v->stutter_exit_watermark * 1000;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
624
v->stutter_enter_plus_exit_watermark * 1000;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
626
v->dram_clock_change_watermark * 1000;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
627
context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
628
context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = v->urgent_watermark * 1000;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
629
if (v->voltage_level >= 2) {
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
633
if (v->voltage_level >= 3)
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
681
static void hack_disable_optional_pipe_split(struct dcn_bw_internal_vars *v)
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
687
v->max_dispclk[0] = v->max_dppclk_vmin0p65;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
690
static void hack_force_pipe_split(struct dcn_bw_internal_vars *v,
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
699
if (pixel_rate_mhz < v->max_dppclk[0])
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
700
v->max_dppclk[0] = pixel_rate_mhz;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
703
static void hack_bounding_box(struct dcn_bw_internal_vars *v,
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
722
hack_disable_optional_pipe_split(v);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
728
hack_disable_optional_pipe_split(v);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
732
hack_disable_optional_pipe_split(v);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
736
hack_force_pipe_split(v, context->streams[0]->timing.pix_clk_100hz);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
760
struct dcn_bw_internal_vars *v = &context->dcn_bw_vars;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
773
memset(v, 0, sizeof(*v));
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
775
v->sr_exit_time = dc->dcn_soc->sr_exit_time;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
776
v->sr_enter_plus_exit_time = dc->dcn_soc->sr_enter_plus_exit_time;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
777
v->urgent_latency = dc->dcn_soc->urgent_latency;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
778
v->write_back_latency = dc->dcn_soc->write_back_latency;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
779
v->percent_of_ideal_drambw_received_after_urg_latency =
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
782
v->dcfclkv_min0p65 = dc->dcn_soc->dcfclkv_min0p65;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
783
v->dcfclkv_mid0p72 = dc->dcn_soc->dcfclkv_mid0p72;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
784
v->dcfclkv_nom0p8 = dc->dcn_soc->dcfclkv_nom0p8;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
785
v->dcfclkv_max0p9 = dc->dcn_soc->dcfclkv_max0p9;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
787
v->max_dispclk_vmin0p65 = dc->dcn_soc->max_dispclk_vmin0p65;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
788
v->max_dispclk_vmid0p72 = dc->dcn_soc->max_dispclk_vmid0p72;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
789
v->max_dispclk_vnom0p8 = dc->dcn_soc->max_dispclk_vnom0p8;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
790
v->max_dispclk_vmax0p9 = dc->dcn_soc->max_dispclk_vmax0p9;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
792
v->max_dppclk_vmin0p65 = dc->dcn_soc->max_dppclk_vmin0p65;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
793
v->max_dppclk_vmid0p72 = dc->dcn_soc->max_dppclk_vmid0p72;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
794
v->max_dppclk_vnom0p8 = dc->dcn_soc->max_dppclk_vnom0p8;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
795
v->max_dppclk_vmax0p9 = dc->dcn_soc->max_dppclk_vmax0p9;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
797
v->socclk = dc->dcn_soc->socclk;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
799
v->fabric_and_dram_bandwidth_vmin0p65 = dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
800
v->fabric_and_dram_bandwidth_vmid0p72 = dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
801
v->fabric_and_dram_bandwidth_vnom0p8 = dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
802
v->fabric_and_dram_bandwidth_vmax0p9 = dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
804
v->phyclkv_min0p65 = dc->dcn_soc->phyclkv_min0p65;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
805
v->phyclkv_mid0p72 = dc->dcn_soc->phyclkv_mid0p72;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
806
v->phyclkv_nom0p8 = dc->dcn_soc->phyclkv_nom0p8;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
807
v->phyclkv_max0p9 = dc->dcn_soc->phyclkv_max0p9;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
809
v->downspreading = dc->dcn_soc->downspreading;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
810
v->round_trip_ping_latency_cycles = dc->dcn_soc->round_trip_ping_latency_cycles;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
811
v->urgent_out_of_order_return_per_channel = dc->dcn_soc->urgent_out_of_order_return_per_channel;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
812
v->number_of_channels = dc->dcn_soc->number_of_channels;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
813
v->vmm_page_size = dc->dcn_soc->vmm_page_size;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
814
v->dram_clock_change_latency = dc->dcn_soc->dram_clock_change_latency;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
815
v->return_bus_width = dc->dcn_soc->return_bus_width;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
817
v->rob_buffer_size_in_kbyte = dc->dcn_ip->rob_buffer_size_in_kbyte;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
818
v->det_buffer_size_in_kbyte = dc->dcn_ip->det_buffer_size_in_kbyte;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
819
v->dpp_output_buffer_pixels = dc->dcn_ip->dpp_output_buffer_pixels;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
820
v->opp_output_buffer_lines = dc->dcn_ip->opp_output_buffer_lines;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
821
v->pixel_chunk_size_in_kbyte = dc->dcn_ip->pixel_chunk_size_in_kbyte;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
822
v->pte_enable = dc->dcn_ip->pte_enable;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
823
v->pte_chunk_size = dc->dcn_ip->pte_chunk_size;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
824
v->meta_chunk_size = dc->dcn_ip->meta_chunk_size;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
825
v->writeback_chunk_size = dc->dcn_ip->writeback_chunk_size;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
826
v->odm_capability = dc->dcn_ip->odm_capability;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
827
v->dsc_capability = dc->dcn_ip->dsc_capability;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
828
v->line_buffer_size = dc->dcn_ip->line_buffer_size;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
829
v->is_line_buffer_bpp_fixed = dc->dcn_ip->is_line_buffer_bpp_fixed;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
830
v->line_buffer_fixed_bpp = dc->dcn_ip->line_buffer_fixed_bpp;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
831
v->max_line_buffer_lines = dc->dcn_ip->max_line_buffer_lines;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
832
v->writeback_luma_buffer_size = dc->dcn_ip->writeback_luma_buffer_size;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
833
v->writeback_chroma_buffer_size = dc->dcn_ip->writeback_chroma_buffer_size;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
834
v->max_num_dpp = dc->dcn_ip->max_num_dpp;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
835
v->max_num_writeback = dc->dcn_ip->max_num_writeback;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
836
v->max_dchub_topscl_throughput = dc->dcn_ip->max_dchub_topscl_throughput;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
837
v->max_pscl_tolb_throughput = dc->dcn_ip->max_pscl_tolb_throughput;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
838
v->max_lb_tovscl_throughput = dc->dcn_ip->max_lb_tovscl_throughput;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
839
v->max_vscl_tohscl_throughput = dc->dcn_ip->max_vscl_tohscl_throughput;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
840
v->max_hscl_ratio = dc->dcn_ip->max_hscl_ratio;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
841
v->max_vscl_ratio = dc->dcn_ip->max_vscl_ratio;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
842
v->max_hscl_taps = dc->dcn_ip->max_hscl_taps;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
843
v->max_vscl_taps = dc->dcn_ip->max_vscl_taps;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
844
v->under_scan_factor = dc->dcn_ip->under_scan_factor;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
845
v->pte_buffer_size_in_requests = dc->dcn_ip->pte_buffer_size_in_requests;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
846
v->dispclk_ramping_margin = dc->dcn_ip->dispclk_ramping_margin;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
847
v->max_inter_dcn_tile_repeaters = dc->dcn_ip->max_inter_dcn_tile_repeaters;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
848
v->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one =
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
850
v->bug_forcing_luma_and_chroma_request_to_same_size_fixed =
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
853
v->voltage[5] = dcn_bw_no_support;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
854
v->voltage[4] = dcn_bw_v_max0p9;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
855
v->voltage[3] = dcn_bw_v_max0p9;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
856
v->voltage[2] = dcn_bw_v_nom0p8;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
857
v->voltage[1] = dcn_bw_v_mid0p72;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
858
v->voltage[0] = dcn_bw_v_min0p65;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
859
v->fabric_and_dram_bandwidth_per_state[5] = v->fabric_and_dram_bandwidth_vmax0p9;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
860
v->fabric_and_dram_bandwidth_per_state[4] = v->fabric_and_dram_bandwidth_vmax0p9;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
861
v->fabric_and_dram_bandwidth_per_state[3] = v->fabric_and_dram_bandwidth_vmax0p9;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
862
v->fabric_and_dram_bandwidth_per_state[2] = v->fabric_and_dram_bandwidth_vnom0p8;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
863
v->fabric_and_dram_bandwidth_per_state[1] = v->fabric_and_dram_bandwidth_vmid0p72;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
864
v->fabric_and_dram_bandwidth_per_state[0] = v->fabric_and_dram_bandwidth_vmin0p65;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
865
v->dcfclk_per_state[5] = v->dcfclkv_max0p9;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
866
v->dcfclk_per_state[4] = v->dcfclkv_max0p9;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
867
v->dcfclk_per_state[3] = v->dcfclkv_max0p9;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
868
v->dcfclk_per_state[2] = v->dcfclkv_nom0p8;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
869
v->dcfclk_per_state[1] = v->dcfclkv_mid0p72;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
870
v->dcfclk_per_state[0] = v->dcfclkv_min0p65;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
871
v->max_dispclk[5] = v->max_dispclk_vmax0p9;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
872
v->max_dispclk[4] = v->max_dispclk_vmax0p9;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
873
v->max_dispclk[3] = v->max_dispclk_vmax0p9;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
874
v->max_dispclk[2] = v->max_dispclk_vnom0p8;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
875
v->max_dispclk[1] = v->max_dispclk_vmid0p72;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
876
v->max_dispclk[0] = v->max_dispclk_vmin0p65;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
877
v->max_dppclk[5] = v->max_dppclk_vmax0p9;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
878
v->max_dppclk[4] = v->max_dppclk_vmax0p9;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
879
v->max_dppclk[3] = v->max_dppclk_vmax0p9;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
880
v->max_dppclk[2] = v->max_dppclk_vnom0p8;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
881
v->max_dppclk[1] = v->max_dppclk_vmid0p72;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
882
v->max_dppclk[0] = v->max_dppclk_vmin0p65;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
883
v->phyclk_per_state[5] = v->phyclkv_max0p9;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
884
v->phyclk_per_state[4] = v->phyclkv_max0p9;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
885
v->phyclk_per_state[3] = v->phyclkv_max0p9;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
886
v->phyclk_per_state[2] = v->phyclkv_nom0p8;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
887
v->phyclk_per_state[1] = v->phyclkv_mid0p72;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
888
v->phyclk_per_state[0] = v->phyclkv_min0p65;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
889
v->synchronized_vblank = dcn_bw_no;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
890
v->ta_pscalculation = dcn_bw_override;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
891
v->allow_different_hratio_vratio = dcn_bw_yes;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
902
v->underscan_output[input_idx] = false; /* taken care of in recout already*/
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
903
v->interlace_output[input_idx] = false;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
905
v->htotal[input_idx] = pipe->stream->timing.h_total;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
906
v->vtotal[input_idx] = pipe->stream->timing.v_total;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
907
v->vactive[input_idx] = pipe->stream->timing.v_addressable +
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
909
v->v_sync_plus_back_porch[input_idx] = pipe->stream->timing.v_total
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
910
- v->vactive[input_idx]
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
912
v->pixel_clock[input_idx] = pipe->stream->timing.pix_clk_100hz/10000.0;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
914
v->pixel_clock[input_idx] *= 2;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
916
v->dcc_enable[input_idx] = dcn_bw_yes;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
917
v->source_pixel_format[input_idx] = dcn_bw_rgb_sub_32;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
918
v->source_surface_mode[input_idx] = dcn_bw_sw_4_kb_s;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
919
v->lb_bit_per_pixel[input_idx] = 30;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
920
v->viewport_width[input_idx] = pipe->stream->timing.h_addressable;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
921
v->viewport_height[input_idx] = pipe->stream->timing.v_addressable;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
929
if (v->viewport_width[input_idx] > 1920)
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
930
v->viewport_width[input_idx] = 1920;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
931
if (v->viewport_height[input_idx] > 1080)
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
932
v->viewport_height[input_idx] = 1080;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
933
v->scaler_rec_out_width[input_idx] = v->viewport_width[input_idx];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
934
v->scaler_recout_height[input_idx] = v->viewport_height[input_idx];
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
935
v->override_hta_ps[input_idx] = 1;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
936
v->override_vta_ps[input_idx] = 1;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
937
v->override_hta_pschroma[input_idx] = 1;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
938
v->override_vta_pschroma[input_idx] = 1;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
939
v->source_scan[input_idx] = dcn_bw_hor;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
942
v->viewport_height[input_idx] = pipe->plane_res.scl_data.viewport.height;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
943
v->viewport_width[input_idx] = pipe->plane_res.scl_data.viewport.width;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
944
v->scaler_rec_out_width[input_idx] = pipe->plane_res.scl_data.recout.width;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
945
v->scaler_recout_height[input_idx] = pipe->plane_res.scl_data.recout.height;
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
954
v->viewport_width[input_idx] = viewport_end
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
957
v->viewport_width[input_idx] = viewport_b_end
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
966
v->viewport_height[input_idx] = viewport_end
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
969
v->viewport_height[input_idx] = viewport_b_end
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
972
v->scaler_rec_out_width[input_idx] = pipe->plane_res.scl_data.recout.width
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
978
|| v->scaler_rec_out_width[input_idx] == v->viewport_width[input_idx]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
980
|| v->scaler_recout_height[input_idx] == v->viewport_height[input_idx]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
983
|| v->scaler_recout_height[input_idx] == v->viewport_width[input_idx]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
985
|| v->scaler_rec_out_width[input_idx] == v->viewport_height[input_idx]);
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
993
v->dcc_enable[input_idx] = pipe->plane_state->dcc.enable ? dcn_bw_yes : dcn_bw_no;
drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
2140
void dcn20_fpu_adjust_dppclk(struct vba_vars_st *v,
drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
2149
v->RequiredDPPCLK[vlevel][max_mpc_comb][pipe_idx] *= 2;
drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
2151
v->RequiredDPPCLK[vlevel][max_mpc_comb][pipe_idx] /= 2;
drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.h
69
void dcn20_fpu_adjust_dppclk(struct vba_vars_st *v,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1005
PrefetchBandwidth4 = (PrefetchSourceLinesY * swath_width_luma_ub * BytePerPixelY + PrefetchSourceLinesC * swath_width_chroma_ub * v->BytePerPixelC[k])
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1016
if (v->Tno_bw[k] + PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / PrefetchBandwidth1
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1027
if (v->Tno_bw[k] + PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / PrefetchBandwidth2
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1038
if (v->Tno_bw[k] + PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / PrefetchBandwidth3
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1061
if (v->GPUVMEnable) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1062
Tvm_equ = dml_max3(v->Tno_bw[k] + PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / prefetch_bw_equ, Tvm_trips, LineTime / 4);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1067
if ((v->GPUVMEnable || myPipe->DCCEnable)) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1136
*RequiredPrefetchPixDataBWChroma = (double) PrefetchSourceLinesC / LinesToRequestPrefetchPixelData * v->BytePerPixelC[k] * swath_width_chroma_ub / LineTime;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1152
dml_print("DML: To: %fus - time for propagation from scaler to optc\n", (v->DSTYAfterScaler[k] + ((v->DSTXAfterScaler[k]) / (double) myPipe->HTotal)) * LineTime);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1154
dml_print("DML: Tslack(pre): %fus - time left over in schedule\n", VStartup * LineTime - TimeForFetchingMetaPTE - 2 * TimeForFetchingRowInVBlank - (v->DSTYAfterScaler[k] + ((v->DSTXAfterScaler[k]) / (double) myPipe->HTotal)) * LineTime - TWait - TCalc - Tsetup);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1185
v->prefetch_vmrow_bw[k] = dml_max(prefetch_vm_bw, prefetch_row_bw);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1750
struct vba_vars_st *v = &mode_lib->vba;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1753
unsigned int PrefetchMode = v->PrefetchModePerState[v->VoltageLevel][v->maxMpcComb];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1760
v->WritebackDISPCLK = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1761
v->DISPCLKWithRamping = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1762
v->DISPCLKWithoutRamping = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1763
v->GlobalDPPCLK = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1765
v->IdealSDPPortBandwidthPerState[v->VoltageLevel][v->maxMpcComb] = dml_min3(
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1766
v->ReturnBusWidth * v->DCFCLK,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1767
v->DRAMSpeedPerState[v->VoltageLevel] * v->NumberOfChannels * v->DRAMChannelWidth,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1768
v->FabricClockPerState[v->VoltageLevel] * v->FabricDatapathToDCNDataReturn);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1769
if (v->HostVMEnable != true) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1770
v->ReturnBW = v->IdealSDPPortBandwidthPerState[v->VoltageLevel][v->maxMpcComb] * v->PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelDataOnly / 100;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1772
v->ReturnBW = v->IdealSDPPortBandwidthPerState[v->VoltageLevel][v->maxMpcComb] * v->PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData / 100;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1778
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1779
if (v->WritebackEnable[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1780
v->WritebackDISPCLK = dml_max(v->WritebackDISPCLK,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1782
v->WritebackPixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1783
v->PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1784
v->WritebackHRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1785
v->WritebackVRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1786
v->WritebackHTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1787
v->WritebackVTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1788
v->WritebackSourceWidth[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1789
v->WritebackDestinationWidth[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1790
v->HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1791
v->WritebackLineBufferSize));
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1795
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1796
if (v->HRatio[k] > 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1797
v->PSCL_THROUGHPUT_LUMA[k] = dml_min(v->MaxDCHUBToPSCLThroughput,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1798
v->MaxPSCLToLBThroughput * v->HRatio[k] / dml_ceil(v->htaps[k] / 6.0, 1));
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1800
v->PSCL_THROUGHPUT_LUMA[k] = dml_min(
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1801
v->MaxDCHUBToPSCLThroughput,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1802
v->MaxPSCLToLBThroughput);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1805
v->DPPCLKUsingSingleDPPLuma = v->PixelClock[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1806
* dml_max(v->vtaps[k] / 6.0 * dml_min(1.0, v->HRatio[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1807
dml_max(v->HRatio[k] * v->VRatio[k] / v->PSCL_THROUGHPUT_LUMA[k], 1.0));
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1809
if ((v->htaps[k] > 6 || v->vtaps[k] > 6)
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1810
&& v->DPPCLKUsingSingleDPPLuma < 2 * v->PixelClock[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1811
v->DPPCLKUsingSingleDPPLuma = 2 * v->PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1814
if ((v->SourcePixelFormat[k] != dm_420_8
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1815
&& v->SourcePixelFormat[k] != dm_420_10
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1816
&& v->SourcePixelFormat[k] != dm_420_12
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1817
&& v->SourcePixelFormat[k] != dm_rgbe_alpha)) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1818
v->PSCL_THROUGHPUT_CHROMA[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1819
v->DPPCLKUsingSingleDPP[k] = v->DPPCLKUsingSingleDPPLuma;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1821
if (v->HRatioChroma[k] > 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1822
v->PSCL_THROUGHPUT_CHROMA[k] = dml_min(v->MaxDCHUBToPSCLThroughput,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1823
v->MaxPSCLToLBThroughput * v->HRatioChroma[k] / dml_ceil(v->HTAPsChroma[k] / 6.0, 1.0));
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1825
v->PSCL_THROUGHPUT_CHROMA[k] = dml_min(
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1826
v->MaxDCHUBToPSCLThroughput,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1827
v->MaxPSCLToLBThroughput);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1829
v->DPPCLKUsingSingleDPPChroma = v->PixelClock[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1830
* dml_max3(v->VTAPsChroma[k] / 6.0 * dml_min(1.0, v->HRatioChroma[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1831
v->HRatioChroma[k] * v->VRatioChroma[k] / v->PSCL_THROUGHPUT_CHROMA[k], 1.0);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1833
if ((v->HTAPsChroma[k] > 6 || v->VTAPsChroma[k] > 6)
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1834
&& v->DPPCLKUsingSingleDPPChroma
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1835
< 2 * v->PixelClock[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1836
v->DPPCLKUsingSingleDPPChroma = 2
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1837
* v->PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1840
v->DPPCLKUsingSingleDPP[k] = dml_max(
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1841
v->DPPCLKUsingSingleDPPLuma,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1842
v->DPPCLKUsingSingleDPPChroma);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1846
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1847
if (v->BlendingAndTiming[k] != k)
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1849
if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_4to1) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1850
v->DISPCLKWithRamping = dml_max(v->DISPCLKWithRamping,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1851
v->PixelClock[k] / 4 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100)
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1852
* (1 + v->DISPCLKRampingMargin / 100));
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1853
v->DISPCLKWithoutRamping = dml_max(v->DISPCLKWithoutRamping,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1854
v->PixelClock[k] / 4 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100));
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1855
} else if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_2to1) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1856
v->DISPCLKWithRamping = dml_max(v->DISPCLKWithRamping,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1857
v->PixelClock[k] / 2 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100)
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1858
* (1 + v->DISPCLKRampingMargin / 100));
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1859
v->DISPCLKWithoutRamping = dml_max(v->DISPCLKWithoutRamping,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1860
v->PixelClock[k] / 2 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100));
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1862
v->DISPCLKWithRamping = dml_max(v->DISPCLKWithRamping,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1863
v->PixelClock[k] * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100)
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1864
* (1 + v->DISPCLKRampingMargin / 100));
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1865
v->DISPCLKWithoutRamping = dml_max(v->DISPCLKWithoutRamping,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1866
v->PixelClock[k] * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100));
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1870
v->DISPCLKWithRamping = dml_max(
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1871
v->DISPCLKWithRamping,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1872
v->WritebackDISPCLK);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1873
v->DISPCLKWithoutRamping = dml_max(
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1874
v->DISPCLKWithoutRamping,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1875
v->WritebackDISPCLK);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1877
ASSERT(v->DISPCLKDPPCLKVCOSpeed != 0);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1878
v->DISPCLKWithRampingRoundedToDFSGranularity = RoundToDFSGranularityUp(
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1879
v->DISPCLKWithRamping,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1880
v->DISPCLKDPPCLKVCOSpeed);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1881
v->DISPCLKWithoutRampingRoundedToDFSGranularity = RoundToDFSGranularityUp(
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1882
v->DISPCLKWithoutRamping,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1883
v->DISPCLKDPPCLKVCOSpeed);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1884
v->MaxDispclkRoundedToDFSGranularity = RoundToDFSGranularityDown(
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1885
v->soc.clock_limits[mode_lib->soc.num_states - 1].dispclk_mhz,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1886
v->DISPCLKDPPCLKVCOSpeed);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1887
if (v->DISPCLKWithoutRampingRoundedToDFSGranularity
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1888
> v->MaxDispclkRoundedToDFSGranularity) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1889
v->DISPCLK_calculated =
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1890
v->DISPCLKWithoutRampingRoundedToDFSGranularity;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1891
} else if (v->DISPCLKWithRampingRoundedToDFSGranularity
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1892
> v->MaxDispclkRoundedToDFSGranularity) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1893
v->DISPCLK_calculated = v->MaxDispclkRoundedToDFSGranularity;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1895
v->DISPCLK_calculated =
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1896
v->DISPCLKWithRampingRoundedToDFSGranularity;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1898
v->DISPCLK = v->DISPCLK_calculated;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1899
DTRACE(" dispclk_mhz (calculated) = %f", v->DISPCLK_calculated);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1901
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1902
v->DPPCLK_calculated[k] = v->DPPCLKUsingSingleDPP[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1903
/ v->DPPPerPlane[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1904
* (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1905
v->GlobalDPPCLK = dml_max(
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1906
v->GlobalDPPCLK,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1907
v->DPPCLK_calculated[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1909
v->GlobalDPPCLK = RoundToDFSGranularityUp(
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1910
v->GlobalDPPCLK,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1911
v->DISPCLKDPPCLKVCOSpeed);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1912
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1913
v->DPPCLK_calculated[k] = v->GlobalDPPCLK / 255
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1915
v->DPPCLK_calculated[k] * 255.0
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1916
/ v->GlobalDPPCLK,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1918
DTRACE(" dppclk_mhz[%i] (calculated) = %f", k, v->DPPCLK_calculated[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1919
v->DPPCLK[k] = v->DPPCLK_calculated[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1923
DTRACE(" dcfclk_mhz = %f", v->DCFCLK);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1924
DTRACE(" return_bus_bw = %f", v->ReturnBW);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1926
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1928
v->SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1929
v->SurfaceTiling[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1930
&v->BytePerPixelY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1931
&v->BytePerPixelC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1932
&v->BytePerPixelDETY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1933
&v->BytePerPixelDETC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1934
&v->BlockHeight256BytesY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1935
&v->BlockHeight256BytesC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1936
&v->BlockWidth256BytesY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1937
&v->BlockWidth256BytesC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1942
v->NumberOfActivePlanes,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1943
v->SourcePixelFormat,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1944
v->SourceScan,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1945
v->ViewportWidth,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1946
v->ViewportHeight,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1947
v->SurfaceWidthY,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1948
v->SurfaceWidthC,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1949
v->SurfaceHeightY,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1950
v->SurfaceHeightC,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1951
v->ODMCombineEnabled,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1952
v->BytePerPixelY,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1953
v->BytePerPixelC,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1954
v->BlockHeight256BytesY,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1955
v->BlockHeight256BytesC,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1956
v->BlockWidth256BytesY,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1957
v->BlockWidth256BytesC,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1958
v->BlendingAndTiming,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1959
v->HActive,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1960
v->HRatio,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1961
v->DPPPerPlane,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1962
v->SwathWidthSingleDPPY,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1963
v->SwathWidthSingleDPPC,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1964
v->SwathWidthY,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1965
v->SwathWidthC,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1966
v->dummyinteger3,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1967
v->dummyinteger4,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1968
v->swath_width_luma_ub,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1969
v->swath_width_chroma_ub);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1972
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1973
v->ReadBandwidthPlaneLuma[k] = v->SwathWidthSingleDPPY[k] * v->BytePerPixelY[k] / (v->HTotal[k] / v->PixelClock[k]) * v->VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1974
v->ReadBandwidthPlaneChroma[k] = v->SwathWidthSingleDPPC[k] * v->BytePerPixelC[k] / (v->HTotal[k] / v->PixelClock[k]) * v->VRatioChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1975
DTRACE("read_bw[%i] = %fBps", k, v->ReadBandwidthPlaneLuma[k] + v->ReadBandwidthPlaneChroma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1982
v->NumberOfActivePlanes,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1983
v->BytePerPixelY,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1984
v->BytePerPixelC,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1985
v->VRatio,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1986
v->VRatioChroma,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1987
v->SwathWidthY,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1988
v->SwathWidthC,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1989
v->DPPPerPlane,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1990
v->HRatio,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1991
v->HRatioChroma,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1992
v->PixelClock,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1993
v->PSCL_THROUGHPUT_LUMA,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1994
v->PSCL_THROUGHPUT_CHROMA,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1995
v->DPPCLK,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1996
v->ReadBandwidthPlaneLuma,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1997
v->ReadBandwidthPlaneChroma,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1998
v->ReturnBusWidth,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
1999
&v->DCFCLKDeepSleep);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2002
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2003
if ((v->BlendingAndTiming[k] != k) || !v->DSCEnabled[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2004
v->DSCCLK_calculated[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2006
if (v->OutputFormat[k] == dm_420)
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2007
v->DSCFormatFactor = 2;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2008
else if (v->OutputFormat[k] == dm_444)
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2009
v->DSCFormatFactor = 1;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2010
else if (v->OutputFormat[k] == dm_n422)
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2011
v->DSCFormatFactor = 2;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2013
v->DSCFormatFactor = 1;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2014
if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_4to1)
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2015
v->DSCCLK_calculated[k] = v->PixelClockBackEnd[k] / 12
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2016
/ v->DSCFormatFactor / (1 - v->DISPCLKDPPCLKDSCCLKDownSpreading / 100);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2017
else if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_2to1)
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2018
v->DSCCLK_calculated[k] = v->PixelClockBackEnd[k] / 6
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2019
/ v->DSCFormatFactor / (1 - v->DISPCLKDPPCLKDSCCLKDownSpreading / 100);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2021
v->DSCCLK_calculated[k] = v->PixelClockBackEnd[k] / 3
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2022
/ v->DSCFormatFactor / (1 - v->DISPCLKDPPCLKDSCCLKDownSpreading / 100);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2027
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2028
double BPP = v->OutputBppPerState[k][v->VoltageLevel];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2030
if (v->DSCEnabled[k] && BPP != 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2031
if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_disabled) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2032
v->DSCDelay[k] = dscceComputeDelay(v->DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2034
dml_ceil((double) v->HActive[k] / v->NumberOfDSCSlices[k], 1),
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2035
v->NumberOfDSCSlices[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2036
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2037
v->Output[k])
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2038
+ dscComputeDelay(v->OutputFormat[k], v->Output[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2039
} else if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_2to1) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2040
v->DSCDelay[k] = 2 * dscceComputeDelay(v->DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2042
dml_ceil((double) v->HActive[k] / v->NumberOfDSCSlices[k], 1),
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2043
v->NumberOfDSCSlices[k] / 2.0,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2044
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2045
v->Output[k])
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2046
+ dscComputeDelay(v->OutputFormat[k], v->Output[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2048
v->DSCDelay[k] = 4 * dscceComputeDelay(v->DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2050
dml_ceil((double) v->HActive[k] / v->NumberOfDSCSlices[k], 1),
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2051
v->NumberOfDSCSlices[k] / 4.0,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2052
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2053
v->Output[k])
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2054
+ dscComputeDelay(v->OutputFormat[k], v->Output[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2056
v->DSCDelay[k] = v->DSCDelay[k] * v->PixelClock[k] / v->PixelClockBackEnd[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2058
v->DSCDelay[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2062
for (k = 0; k < v->NumberOfActivePlanes; ++k)
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2063
for (j = 0; j < v->NumberOfActivePlanes; ++j) // NumberOfPlanes
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2064
if (j != k && v->BlendingAndTiming[k] == j
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2065
&& v->DSCEnabled[j])
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2066
v->DSCDelay[k] = v->DSCDelay[j];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2069
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2080
if (v->SourcePixelFormat[k] == dm_420_8 || v->SourcePixelFormat[k] == dm_420_10 || v->SourcePixelFormat[k] == dm_420_12 || v->SourcePixelFormat[k] == dm_rgbe_alpha) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2081
if ((v->SourcePixelFormat[k] == dm_420_10 || v->SourcePixelFormat[k] == dm_420_12) && v->SourceScan[k] != dm_vert) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2082
v->PTEBufferSizeInRequestsForLuma = (v->PTEBufferSizeInRequestsLuma + v->PTEBufferSizeInRequestsChroma) / 2;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2083
v->PTEBufferSizeInRequestsForChroma = v->PTEBufferSizeInRequestsForLuma;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2085
v->PTEBufferSizeInRequestsForLuma = v->PTEBufferSizeInRequestsLuma;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2086
v->PTEBufferSizeInRequestsForChroma = v->PTEBufferSizeInRequestsChroma;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2091
v->DCCEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2092
v->BlockHeight256BytesC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2093
v->BlockWidth256BytesC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2094
v->SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2095
v->SurfaceTiling[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2096
v->BytePerPixelC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2097
v->SourceScan[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2098
v->SwathWidthC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2099
v->ViewportHeightChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2100
v->GPUVMEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2101
v->HostVMEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2102
v->HostVMMaxNonCachedPageTableLevels,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2103
v->GPUVMMinPageSize,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2104
v->HostVMMinPageSize,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2105
v->PTEBufferSizeInRequestsForChroma,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2106
v->PitchC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2107
v->DCCMetaPitchC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2108
&v->MacroTileWidthC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2112
&v->dpte_row_width_chroma_ub[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2113
&v->dpte_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2114
&v->meta_req_width_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2115
&v->meta_req_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2116
&v->meta_row_width_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2117
&v->meta_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2118
&v->dummyinteger1,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2119
&v->dummyinteger2,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2120
&v->PixelPTEReqWidthC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2121
&v->PixelPTEReqHeightC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2122
&v->PTERequestSizeC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2123
&v->dpde0_bytes_per_frame_ub_c[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2124
&v->meta_pte_bytes_per_frame_ub_c[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2126
v->PrefetchSourceLinesC[k] = CalculatePrefetchSourceLines(
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2128
v->VRatioChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2129
v->VTAPsChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2130
v->Interlace[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2131
v->ProgressiveToInterlaceUnitInOPP,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2132
v->SwathHeightC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2133
v->ViewportYStartC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2134
&v->VInitPreFillC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2135
&v->MaxNumSwathC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2137
v->PTEBufferSizeInRequestsForLuma = v->PTEBufferSizeInRequestsLuma + v->PTEBufferSizeInRequestsChroma;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2138
v->PTEBufferSizeInRequestsForChroma = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2142
v->MaxNumSwathC[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2143
v->PrefetchSourceLinesC[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2148
v->DCCEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2149
v->BlockHeight256BytesY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2150
v->BlockWidth256BytesY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2151
v->SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2152
v->SurfaceTiling[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2153
v->BytePerPixelY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2154
v->SourceScan[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2155
v->SwathWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2156
v->ViewportHeight[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2157
v->GPUVMEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2158
v->HostVMEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2159
v->HostVMMaxNonCachedPageTableLevels,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2160
v->GPUVMMinPageSize,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2161
v->HostVMMinPageSize,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2162
v->PTEBufferSizeInRequestsForLuma,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2163
v->PitchY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2164
v->DCCMetaPitchY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2165
&v->MacroTileWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2169
&v->dpte_row_width_luma_ub[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2170
&v->dpte_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2171
&v->meta_req_width[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2172
&v->meta_req_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2173
&v->meta_row_width[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2174
&v->meta_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2175
&v->vm_group_bytes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2176
&v->dpte_group_bytes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2177
&v->PixelPTEReqWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2178
&v->PixelPTEReqHeightY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2179
&v->PTERequestSizeY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2180
&v->dpde0_bytes_per_frame_ub_l[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2181
&v->meta_pte_bytes_per_frame_ub_l[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2183
v->PrefetchSourceLinesY[k] = CalculatePrefetchSourceLines(
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2185
v->VRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2186
v->vtaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2187
v->Interlace[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2188
v->ProgressiveToInterlaceUnitInOPP,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2189
v->SwathHeightY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2190
v->ViewportYStartY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2191
&v->VInitPreFillY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2192
&v->MaxNumSwathY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2193
v->PixelPTEBytesPerRow[k] = PixelPTEBytesPerRowY + PixelPTEBytesPerRowC;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2194
v->PDEAndMetaPTEBytesFrame[k] = PDEAndMetaPTEBytesFrameY
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2196
v->MetaRowByte[k] = MetaRowByteY + MetaRowByteC;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2199
v->GPUVMEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2200
v->SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2201
v->VRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2202
v->VRatioChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2203
v->DCCEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2204
v->HTotal[k] / v->PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2207
v->meta_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2208
v->meta_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2211
v->dpte_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2212
v->dpte_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2213
&v->meta_row_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2214
&v->dpte_row_bw[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2217
v->TotalDCCActiveDPP = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2218
v->TotalActiveDPP = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2219
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2220
v->TotalActiveDPP = v->TotalActiveDPP
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2221
+ v->DPPPerPlane[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2222
if (v->DCCEnable[k])
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2223
v->TotalDCCActiveDPP = v->TotalDCCActiveDPP
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2224
+ v->DPPPerPlane[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2228
ReorderBytes = v->NumberOfChannels * dml_max3(
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2229
v->UrgentOutOfOrderReturnPerChannelPixelDataOnly,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2230
v->UrgentOutOfOrderReturnPerChannelPixelMixedWithVMData,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2231
v->UrgentOutOfOrderReturnPerChannelVMDataOnly);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2233
v->UrgentExtraLatency = CalculateExtraLatency(
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2234
v->RoundTripPingLatencyCycles,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2236
v->DCFCLK,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2237
v->TotalActiveDPP,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2238
v->PixelChunkSizeInKByte,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2239
v->TotalDCCActiveDPP,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2240
v->MetaChunkSize,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2241
v->ReturnBW,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2242
v->GPUVMEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2243
v->HostVMEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2244
v->NumberOfActivePlanes,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2245
v->DPPPerPlane,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2246
v->dpte_group_bytes,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2247
v->PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2248
v->PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2249
v->HostVMMinPageSize,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2250
v->HostVMMaxNonCachedPageTableLevels);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2252
v->TCalc = 24.0 / v->DCFCLKDeepSleep;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2254
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2255
if (v->BlendingAndTiming[k] == k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2256
if (v->WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2257
v->WritebackDelay[v->VoltageLevel][k] = v->WritebackLatency +
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2258
CalculateWriteBackDelay(v->WritebackPixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2259
v->WritebackHRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2260
v->WritebackVRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2261
v->WritebackVTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2262
v->WritebackDestinationWidth[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2263
v->WritebackDestinationHeight[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2264
v->WritebackSourceHeight[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2265
v->HTotal[k]) / v->DISPCLK;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2267
v->WritebackDelay[v->VoltageLevel][k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2268
for (j = 0; j < v->NumberOfActivePlanes; ++j) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2269
if (v->BlendingAndTiming[j] == k
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2270
&& v->WritebackEnable[j] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2271
v->WritebackDelay[v->VoltageLevel][k] = dml_max(v->WritebackDelay[v->VoltageLevel][k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2272
v->WritebackLatency + CalculateWriteBackDelay(
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2273
v->WritebackPixelFormat[j],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2274
v->WritebackHRatio[j],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2275
v->WritebackVRatio[j],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2276
v->WritebackVTaps[j],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2277
v->WritebackDestinationWidth[j],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2278
v->WritebackDestinationHeight[j],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2279
v->WritebackSourceHeight[j],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2280
v->HTotal[k]) / v->DISPCLK);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2286
for (k = 0; k < v->NumberOfActivePlanes; ++k)
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2287
for (j = 0; j < v->NumberOfActivePlanes; ++j)
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2288
if (v->BlendingAndTiming[k] == j)
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2289
v->WritebackDelay[v->VoltageLevel][k] = v->WritebackDelay[v->VoltageLevel][j];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2291
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2292
v->MaxVStartupLines[k] = v->VTotal[k] - v->VActive[k] - dml_max(1.0, dml_ceil((double) v->WritebackDelay[v->VoltageLevel][k] / (v->HTotal[k] / v->PixelClock[k]), 1));
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2295
v->MaximumMaxVStartupLines = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2296
for (k = 0; k < v->NumberOfActivePlanes; ++k)
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2297
v->MaximumMaxVStartupLines = dml_max(v->MaximumMaxVStartupLines, v->MaxVStartupLines[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2299
if (v->DRAMClockChangeLatencyOverride > 0.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2300
v->FinalDRAMClockChangeLatency = v->DRAMClockChangeLatencyOverride;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2302
v->FinalDRAMClockChangeLatency = v->DRAMClockChangeLatency;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2304
v->UrgentLatency = CalculateUrgentLatency(v->UrgentLatencyPixelDataOnly, v->UrgentLatencyPixelMixedWithVMData, v->UrgentLatencyVMDataOnly, v->DoUrgentLatencyAdjustment, v->UrgentLatencyAdjustmentFabricClockComponent, v->UrgentLatencyAdjustmentFabricClockReference, v->FabricClock);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2307
v->FractionOfUrgentBandwidth = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2308
v->FractionOfUrgentBandwidthImmediateFlip = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2310
v->VStartupLines = 13;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2319
v->FinalDRAMClockChangeLatency,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2320
v->UrgentLatency,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2321
v->SREnterPlusExitTime);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2323
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2326
myPipe.DPPCLK = v->DPPCLK[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2327
myPipe.DISPCLK = v->DISPCLK;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2328
myPipe.PixelClock = v->PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2329
myPipe.DCFCLKDeepSleep = v->DCFCLKDeepSleep;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2330
myPipe.DPPPerPlane = v->DPPPerPlane[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2331
myPipe.ScalerEnabled = v->ScalerEnabled[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2332
myPipe.SourceScan = v->SourceScan[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2333
myPipe.BlockWidth256BytesY = v->BlockWidth256BytesY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2334
myPipe.BlockHeight256BytesY = v->BlockHeight256BytesY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2335
myPipe.BlockWidth256BytesC = v->BlockWidth256BytesC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2336
myPipe.BlockHeight256BytesC = v->BlockHeight256BytesC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2337
myPipe.InterlaceEnable = v->Interlace[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2338
myPipe.NumberOfCursors = v->NumberOfCursors[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2339
myPipe.VBlank = v->VTotal[k] - v->VActive[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2340
myPipe.HTotal = v->HTotal[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2341
myPipe.DCCEnable = v->DCCEnable[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2342
myPipe.ODMCombineEnabled = !!v->ODMCombineEnabled[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2344
v->ErrorResult[k] = CalculatePrefetchSchedule(
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2348
v->DSCDelay[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2349
(unsigned int) (v->SwathWidthY[k] / v->HRatio[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2350
dml_min(v->VStartupLines, v->MaxVStartupLines[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2351
v->MaxVStartupLines[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2352
v->UrgentLatency,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2353
v->UrgentExtraLatency,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2354
v->TCalc,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2355
v->PDEAndMetaPTEBytesFrame[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2356
v->MetaRowByte[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2357
v->PixelPTEBytesPerRow[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2358
v->PrefetchSourceLinesY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2359
v->SwathWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2360
v->BytePerPixelY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2361
v->VInitPreFillY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2362
v->MaxNumSwathY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2363
v->PrefetchSourceLinesC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2364
v->SwathWidthC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2365
v->VInitPreFillC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2366
v->MaxNumSwathC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2367
v->swath_width_luma_ub[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2368
v->swath_width_chroma_ub[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2369
v->SwathHeightY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2370
v->SwathHeightC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2372
&v->DestinationLinesForPrefetch[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2373
&v->PrefetchBandwidth[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2374
&v->DestinationLinesToRequestVMInVBlank[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2375
&v->DestinationLinesToRequestRowInVBlank[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2376
&v->VRatioPrefetchY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2377
&v->VRatioPrefetchC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2378
&v->RequiredPrefetchPixDataBWLuma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2379
&v->RequiredPrefetchPixDataBWChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2380
&v->NotEnoughTimeForDynamicMetadata[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2381
if (v->BlendingAndTiming[k] == k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2382
double TotalRepeaterDelayTime = v->MaxInterDCNTileRepeaters * (2 / v->DPPCLK[k] + 3 / v->DISPCLK);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2383
v->VUpdateWidthPix[k] = (14 / v->DCFCLKDeepSleep + 12 / v->DPPCLK[k] + TotalRepeaterDelayTime) * v->PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2384
v->VReadyOffsetPix[k] = dml_max(150.0 / v->DPPCLK[k], TotalRepeaterDelayTime + 20 / v->DCFCLKDeepSleep + 10 / v->DPPCLK[k]) * v->PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2385
v->VUpdateOffsetPix[k] = dml_ceil(v->HTotal[k] / 4.0, 1);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2386
v->VStartup[k] = dml_min(v->VStartupLines, v->MaxVStartupLines[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2388
int x = v->BlendingAndTiming[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2389
double TotalRepeaterDelayTime = v->MaxInterDCNTileRepeaters * (2 / v->DPPCLK[k] + 3 / v->DISPCLK);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2390
v->VUpdateWidthPix[k] = (14 / v->DCFCLKDeepSleep + 12 / v->DPPCLK[k] + TotalRepeaterDelayTime) * v->PixelClock[x];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2391
v->VReadyOffsetPix[k] = dml_max(150.0 / v->DPPCLK[k], TotalRepeaterDelayTime + 20 / v->DCFCLKDeepSleep + 10 / v->DPPCLK[k]) * v->PixelClock[x];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2392
v->VUpdateOffsetPix[k] = dml_ceil(v->HTotal[x] / 4.0, 1);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2393
if (!v->MaxVStartupLines[x])
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2394
v->MaxVStartupLines[x] = v->MaxVStartupLines[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2395
v->VStartup[k] = dml_min(v->VStartupLines, v->MaxVStartupLines[x]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2399
v->NotEnoughUrgentLatencyHiding[0][0] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2400
v->NotEnoughUrgentLatencyHidingPre = false;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2402
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2403
v->cursor_bw[k] = v->NumberOfCursors[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2404
* v->CursorWidth[k][0] * v->CursorBPP[k][0]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2406
/ (v->HTotal[k] / v->PixelClock[k])
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2407
* v->VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2408
v->cursor_bw_pre[k] = v->NumberOfCursors[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2409
* v->CursorWidth[k][0] * v->CursorBPP[k][0]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2411
/ (v->HTotal[k] / v->PixelClock[k])
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2412
* v->VRatioPrefetchY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2415
v->swath_width_luma_ub[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2416
v->swath_width_chroma_ub[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2417
v->DETBufferSizeInKByte[0],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2418
v->SwathHeightY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2419
v->SwathHeightC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2420
v->HTotal[k] / v->PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2421
v->UrgentLatency,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2422
v->CursorBufferSize,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2423
v->CursorWidth[k][0],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2424
v->CursorBPP[k][0],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2425
v->VRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2426
v->VRatioChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2427
v->BytePerPixelDETY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2428
v->BytePerPixelDETC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2429
v->DETBufferSizeY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2430
v->DETBufferSizeC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2431
&v->UrgentBurstFactorCursor[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2432
&v->UrgentBurstFactorLuma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2433
&v->UrgentBurstFactorChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2434
&v->NoUrgentLatencyHiding[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2437
v->swath_width_luma_ub[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2438
v->swath_width_chroma_ub[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2439
v->DETBufferSizeInKByte[0],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2440
v->SwathHeightY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2441
v->SwathHeightC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2442
v->HTotal[k] / v->PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2443
v->UrgentLatency,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2444
v->CursorBufferSize,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2445
v->CursorWidth[k][0],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2446
v->CursorBPP[k][0],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2447
v->VRatioPrefetchY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2448
v->VRatioPrefetchC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2449
v->BytePerPixelDETY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2450
v->BytePerPixelDETC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2451
v->DETBufferSizeY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2452
v->DETBufferSizeC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2453
&v->UrgentBurstFactorCursorPre[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2454
&v->UrgentBurstFactorLumaPre[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2455
&v->UrgentBurstFactorChromaPre[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2456
&v->NoUrgentLatencyHidingPre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2459
dml_max3(v->DPPPerPlane[k] * v->prefetch_vmrow_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2460
v->ReadBandwidthPlaneLuma[k] *
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2461
v->UrgentBurstFactorLuma[k] +
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2462
v->ReadBandwidthPlaneChroma[k] *
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2463
v->UrgentBurstFactorChroma[k] +
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2464
v->cursor_bw[k] *
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2465
v->UrgentBurstFactorCursor[k] +
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2466
v->DPPPerPlane[k] * (v->meta_row_bw[k] + v->dpte_row_bw[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2467
v->DPPPerPlane[k] * (v->RequiredPrefetchPixDataBWLuma[k] * v->UrgentBurstFactorLumaPre[k] +
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2468
v->RequiredPrefetchPixDataBWChroma[k] * v->UrgentBurstFactorChromaPre[k]) + v->cursor_bw_pre[k] *
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2469
v->UrgentBurstFactorCursorPre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2472
dml_max3(v->DPPPerPlane[k] * v->prefetch_vmrow_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2473
v->ReadBandwidthPlaneLuma[k] +
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2474
v->ReadBandwidthPlaneChroma[k] +
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2475
v->cursor_bw[k] +
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2476
v->DPPPerPlane[k] * (v->meta_row_bw[k] + v->dpte_row_bw[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2477
v->DPPPerPlane[k] * (v->RequiredPrefetchPixDataBWLuma[k] + v->RequiredPrefetchPixDataBWChroma[k]) + v->cursor_bw_pre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2479
if (v->DestinationLinesForPrefetch[k] < 2)
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2481
if (v->VRatioPrefetchY[k] > 4 || v->VRatioPrefetchC[k] > 4)
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2483
if (v->NoUrgentLatencyHiding[k] == true)
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2484
v->NotEnoughUrgentLatencyHiding[0][0] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2486
if (v->NoUrgentLatencyHidingPre[k] == true)
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2487
v->NotEnoughUrgentLatencyHidingPre = true;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2489
v->FractionOfUrgentBandwidth = MaxTotalRDBandwidthNoUrgentBurst / v->ReturnBW;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2492
if (MaxTotalRDBandwidth <= v->ReturnBW && v->NotEnoughUrgentLatencyHiding[0][0] == 0
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2493
&& v->NotEnoughUrgentLatencyHidingPre == 0 && !VRatioPrefetchMoreThan4
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2495
v->PrefetchModeSupported = true;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2497
v->PrefetchModeSupported = false;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2499
dml_print("DML: MaxTotalRDBandwidth:%f AvailReturnBandwidth:%f\n", MaxTotalRDBandwidth, v->ReturnBW);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2504
if (v->PrefetchModeSupported == true && v->ImmediateFlipSupport == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2505
v->BandwidthAvailableForImmediateFlip = v->ReturnBW;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2506
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2507
v->BandwidthAvailableForImmediateFlip =
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2508
v->BandwidthAvailableForImmediateFlip
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2510
v->ReadBandwidthPlaneLuma[k] * v->UrgentBurstFactorLuma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2511
+ v->ReadBandwidthPlaneChroma[k] * v->UrgentBurstFactorChroma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2512
+ v->cursor_bw[k] * v->UrgentBurstFactorCursor[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2513
v->DPPPerPlane[k] * (v->RequiredPrefetchPixDataBWLuma[k] * v->UrgentBurstFactorLumaPre[k] +
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2514
v->RequiredPrefetchPixDataBWChroma[k] * v->UrgentBurstFactorChromaPre[k]) +
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2515
v->cursor_bw_pre[k] * v->UrgentBurstFactorCursorPre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2518
v->TotImmediateFlipBytes = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2519
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2520
v->TotImmediateFlipBytes = v->TotImmediateFlipBytes + v->DPPPerPlane[k] * (v->PDEAndMetaPTEBytesFrame[k] + v->MetaRowByte[k] + v->PixelPTEBytesPerRow[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2522
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2525
v->PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2526
v->PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2527
v->UrgentExtraLatency,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2528
v->UrgentLatency,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2529
v->GPUVMMaxPageTableLevels,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2530
v->HostVMEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2531
v->HostVMMaxNonCachedPageTableLevels,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2532
v->GPUVMEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2533
v->HostVMMinPageSize,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2534
v->PDEAndMetaPTEBytesFrame[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2535
v->MetaRowByte[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2536
v->PixelPTEBytesPerRow[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2537
v->BandwidthAvailableForImmediateFlip,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2538
v->TotImmediateFlipBytes,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2539
v->SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2540
v->HTotal[k] / v->PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2541
v->VRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2542
v->VRatioChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2543
v->Tno_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2544
v->DCCEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2545
v->dpte_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2546
v->meta_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2547
v->dpte_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2548
v->meta_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2549
&v->DestinationLinesToRequestVMInImmediateFlip[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2550
&v->DestinationLinesToRequestRowInImmediateFlip[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2551
&v->final_flip_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2552
&v->ImmediateFlipSupportedForPipe[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2554
v->total_dcn_read_bw_with_flip = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2555
v->total_dcn_read_bw_with_flip_no_urgent_burst = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2556
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2557
v->total_dcn_read_bw_with_flip = v->total_dcn_read_bw_with_flip + dml_max3(
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2558
v->DPPPerPlane[k] * v->prefetch_vmrow_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2559
v->DPPPerPlane[k] * v->final_flip_bw[k] +
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2560
v->ReadBandwidthLuma[k] * v->UrgentBurstFactorLuma[k] +
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2561
v->ReadBandwidthChroma[k] * v->UrgentBurstFactorChroma[k] +
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2562
v->cursor_bw[k] * v->UrgentBurstFactorCursor[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2563
v->DPPPerPlane[k] * (v->final_flip_bw[k] +
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2564
v->RequiredPrefetchPixDataBWLuma[k] * v->UrgentBurstFactorLumaPre[k] +
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2565
v->RequiredPrefetchPixDataBWChroma[k] * v->UrgentBurstFactorChromaPre[k]) +
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2566
v->cursor_bw_pre[k] * v->UrgentBurstFactorCursorPre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2567
v->total_dcn_read_bw_with_flip_no_urgent_burst =
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2568
v->total_dcn_read_bw_with_flip_no_urgent_burst +
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2569
dml_max3(v->DPPPerPlane[k] * v->prefetch_vmrow_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2570
v->DPPPerPlane[k] * v->final_flip_bw[k] + v->ReadBandwidthPlaneLuma[k] + v->ReadBandwidthPlaneChroma[k] + v->cursor_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2571
v->DPPPerPlane[k] * (v->final_flip_bw[k] + v->RequiredPrefetchPixDataBWLuma[k] + v->RequiredPrefetchPixDataBWChroma[k]) + v->cursor_bw_pre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2574
v->FractionOfUrgentBandwidthImmediateFlip = v->total_dcn_read_bw_with_flip_no_urgent_burst / v->ReturnBW;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2576
v->ImmediateFlipSupported = true;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2577
if (v->total_dcn_read_bw_with_flip > v->ReturnBW) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2578
v->ImmediateFlipSupported = false;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2579
v->total_dcn_read_bw_with_flip = MaxTotalRDBandwidth;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2581
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2582
if (v->ImmediateFlipSupportedForPipe[k] == false) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2583
v->ImmediateFlipSupported = false;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2587
v->ImmediateFlipSupported = false;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2590
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2591
if (v->ErrorResult[k] || v->NotEnoughTimeForDynamicMetadata[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2592
v->PrefetchModeSupported = false;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2597
v->VStartupLines = v->VStartupLines + 1;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2598
v->PrefetchModeSupported = (v->PrefetchModeSupported == true && ((!v->ImmediateFlipSupport &&
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2599
!v->HostVMEnable && v->ImmediateFlipRequirement[0] != dm_immediate_flip_required) ||
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2600
v->ImmediateFlipSupported)) ? true : false;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2601
} while (!v->PrefetchModeSupported && v->VStartupLines <= v->MaximumMaxVStartupLines);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2602
ASSERT(v->PrefetchModeSupported);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2610
v->DCFCLK,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2611
v->ReturnBW,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2612
v->UrgentLatency,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2613
v->UrgentExtraLatency,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2614
v->SOCCLK,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2615
v->DCFCLKDeepSleep,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2616
v->DPPPerPlane,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2617
v->DPPCLK,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2618
v->DETBufferSizeY,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2619
v->DETBufferSizeC,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2620
v->SwathHeightY,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2621
v->SwathHeightC,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2622
v->SwathWidthY,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2623
v->SwathWidthC,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2624
v->BytePerPixelDETY,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2625
v->BytePerPixelDETC,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2628
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2629
if (v->WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2630
if (v->BlendingAndTiming[k] == k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2631
v->ThisVStartup = v->VStartup[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2633
for (j = 0; j < v->NumberOfActivePlanes; ++j) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2634
if (v->BlendingAndTiming[k] == j) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2635
v->ThisVStartup = v->VStartup[j];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2639
v->WritebackAllowDRAMClockChangeEndPosition[k] = dml_max(0,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2640
v->ThisVStartup * v->HTotal[k] / v->PixelClock[k] - v->WritebackDRAMClockChangeWatermark);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2642
v->WritebackAllowDRAMClockChangeEndPosition[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2651
v->NumberOfActivePlanes,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2652
v->VRatio,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2653
v->VRatioChroma,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2654
v->VRatioPrefetchY,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2655
v->VRatioPrefetchC,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2656
v->swath_width_luma_ub,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2657
v->swath_width_chroma_ub,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2658
v->DPPPerPlane,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2659
v->HRatio,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2660
v->HRatioChroma,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2661
v->PixelClock,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2662
v->PSCL_THROUGHPUT_LUMA,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2663
v->PSCL_THROUGHPUT_CHROMA,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2664
v->DPPCLK,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2665
v->BytePerPixelC,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2666
v->SourceScan,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2667
v->NumberOfCursors,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2668
v->CursorWidth,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2669
v->CursorBPP,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2670
v->BlockWidth256BytesY,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2671
v->BlockHeight256BytesY,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2672
v->BlockWidth256BytesC,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2673
v->BlockHeight256BytesC,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2674
v->DisplayPipeLineDeliveryTimeLuma,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2675
v->DisplayPipeLineDeliveryTimeChroma,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2676
v->DisplayPipeLineDeliveryTimeLumaPrefetch,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2677
v->DisplayPipeLineDeliveryTimeChromaPrefetch,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2678
v->DisplayPipeRequestDeliveryTimeLuma,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2679
v->DisplayPipeRequestDeliveryTimeChroma,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2680
v->DisplayPipeRequestDeliveryTimeLumaPrefetch,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2681
v->DisplayPipeRequestDeliveryTimeChromaPrefetch,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2682
v->CursorRequestDeliveryTime,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2683
v->CursorRequestDeliveryTimePrefetch);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2686
v->NumberOfActivePlanes,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2687
v->GPUVMEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2688
v->MetaChunkSize,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2689
v->MinMetaChunkSizeBytes,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2690
v->HTotal,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2691
v->VRatio,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2692
v->VRatioChroma,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2693
v->DestinationLinesToRequestRowInVBlank,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2694
v->DestinationLinesToRequestRowInImmediateFlip,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2695
v->DCCEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2696
v->PixelClock,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2697
v->BytePerPixelY,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2698
v->BytePerPixelC,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2699
v->SourceScan,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2700
v->dpte_row_height,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2701
v->dpte_row_height_chroma,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2702
v->meta_row_width,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2703
v->meta_row_width_chroma,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2704
v->meta_row_height,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2705
v->meta_row_height_chroma,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2706
v->meta_req_width,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2707
v->meta_req_width_chroma,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2708
v->meta_req_height,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2709
v->meta_req_height_chroma,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2710
v->dpte_group_bytes,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2711
v->PTERequestSizeY,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2712
v->PTERequestSizeC,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2713
v->PixelPTEReqWidthY,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2714
v->PixelPTEReqHeightY,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2715
v->PixelPTEReqWidthC,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2716
v->PixelPTEReqHeightC,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2717
v->dpte_row_width_luma_ub,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2718
v->dpte_row_width_chroma_ub,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2719
v->DST_Y_PER_PTE_ROW_NOM_L,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2720
v->DST_Y_PER_PTE_ROW_NOM_C,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2721
v->DST_Y_PER_META_ROW_NOM_L,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2722
v->DST_Y_PER_META_ROW_NOM_C,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2723
v->TimePerMetaChunkNominal,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2724
v->TimePerChromaMetaChunkNominal,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2725
v->TimePerMetaChunkVBlank,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2726
v->TimePerChromaMetaChunkVBlank,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2727
v->TimePerMetaChunkFlip,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2728
v->TimePerChromaMetaChunkFlip,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2729
v->time_per_pte_group_nom_luma,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2730
v->time_per_pte_group_vblank_luma,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2731
v->time_per_pte_group_flip_luma,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2732
v->time_per_pte_group_nom_chroma,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2733
v->time_per_pte_group_vblank_chroma,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2734
v->time_per_pte_group_flip_chroma);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2737
v->NumberOfActivePlanes,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2738
v->GPUVMEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2739
v->GPUVMMaxPageTableLevels,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2740
v->HTotal,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2741
v->BytePerPixelC,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2742
v->DestinationLinesToRequestVMInVBlank,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2743
v->DestinationLinesToRequestVMInImmediateFlip,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2744
v->DCCEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2745
v->PixelClock,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2746
v->dpte_row_width_luma_ub,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2747
v->dpte_row_width_chroma_ub,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2748
v->vm_group_bytes,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2749
v->dpde0_bytes_per_frame_ub_l,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2750
v->dpde0_bytes_per_frame_ub_c,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2751
v->meta_pte_bytes_per_frame_ub_l,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2752
v->meta_pte_bytes_per_frame_ub_c,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2753
v->TimePerVMGroupVBlank,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2754
v->TimePerVMGroupFlip,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2755
v->TimePerVMRequestVBlank,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2756
v->TimePerVMRequestFlip);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2760
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2762
v->AllowDRAMClockChangeDuringVBlank[k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2763
v->AllowDRAMSelfRefreshDuringVBlank[k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2764
v->MinTTUVBlank[k] = dml_max(
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2765
v->DRAMClockChangeWatermark,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2767
v->StutterEnterPlusExitWatermark,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2768
v->UrgentWatermark));
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2770
v->AllowDRAMClockChangeDuringVBlank[k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2771
v->AllowDRAMSelfRefreshDuringVBlank[k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2772
v->MinTTUVBlank[k] = dml_max(
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2773
v->StutterEnterPlusExitWatermark,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2774
v->UrgentWatermark);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2776
v->AllowDRAMClockChangeDuringVBlank[k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2777
v->AllowDRAMSelfRefreshDuringVBlank[k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2778
v->MinTTUVBlank[k] = v->UrgentWatermark;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2780
if (!v->DynamicMetadataEnable[k])
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2781
v->MinTTUVBlank[k] = v->TCalc
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2782
+ v->MinTTUVBlank[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2786
v->ActiveDPPs = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2787
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2788
CalculateDCCConfiguration(v->DCCEnable[k], false, // We should always know the direction DCCProgrammingAssumesScanDirectionUnknown,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2789
v->SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2790
v->SurfaceWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2791
v->SurfaceWidthC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2792
v->SurfaceHeightY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2793
v->SurfaceHeightC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2794
v->DETBufferSizeInKByte[0] * 1024,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2795
v->BlockHeight256BytesY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2796
v->BlockHeight256BytesC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2797
v->SurfaceTiling[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2798
v->BytePerPixelY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2799
v->BytePerPixelC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2800
v->BytePerPixelDETY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2801
v->BytePerPixelDETC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2802
v->SourceScan[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2803
&v->DCCYMaxUncompressedBlock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2804
&v->DCCCMaxUncompressedBlock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2805
&v->DCCYMaxCompressedBlock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2806
&v->DCCCMaxCompressedBlock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2807
&v->DCCYIndependentBlock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2808
&v->DCCCIndependentBlock[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2813
v->TotalDataReadBandwidth = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2814
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2815
v->TotalDataReadBandwidth = v->TotalDataReadBandwidth
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2816
+ v->ReadBandwidthPlaneLuma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2817
+ v->ReadBandwidthPlaneChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2822
v->VStartupMargin = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2823
v->FirstMainPlane = true;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2824
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2825
if (v->BlendingAndTiming[k] == k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2826
double margin = (v->MaxVStartupLines[k] - v->VStartup[k]) * v->HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2827
/ v->PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2828
if (v->FirstMainPlane == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2829
v->VStartupMargin = margin;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2830
v->FirstMainPlane = false;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2832
v->VStartupMargin = dml_min(v->VStartupMargin, margin);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2839
v->NumberOfActivePlanes,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2840
v->ROBBufferSizeInKByte,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2841
v->TotalDataReadBandwidth,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2842
v->DCFCLK,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2843
v->ReturnBW,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2844
v->SRExitTime,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2845
v->SynchronizedVBlank,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2846
v->DPPPerPlane,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2847
v->DETBufferSizeY,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2848
v->BytePerPixelY,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2849
v->BytePerPixelDETY,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2850
v->SwathWidthY,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2851
v->SwathHeightY,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2852
v->SwathHeightC,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2853
v->DCCRateLuma,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2854
v->DCCRateChroma,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2855
v->HTotal,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2856
v->VTotal,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2857
v->PixelClock,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2858
v->VRatio,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2859
v->SourceScan,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2860
v->BlockHeight256BytesY,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2861
v->BlockWidth256BytesY,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2862
v->BlockHeight256BytesC,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2863
v->BlockWidth256BytesC,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2864
v->DCCYMaxUncompressedBlock,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2865
v->DCCCMaxUncompressedBlock,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2866
v->VActive,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2867
v->DCCEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2868
v->WritebackEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2869
v->ReadBandwidthPlaneLuma,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2870
v->ReadBandwidthPlaneChroma,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2871
v->meta_row_bw,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2872
v->dpte_row_bw,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2873
&v->StutterEfficiencyNotIncludingVBlank,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2874
&v->StutterEfficiency,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
2875
&v->StutterPeriod);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
329
struct vba_vars_st *v,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3369
struct vba_vars_st *v = &mode_lib->vba;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3383
start_state = v->soc.num_states - 1;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3393
v->ScaleRatioAndTapsSupport = true;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3394
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3395
if (v->ScalerEnabled[k] == false
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3396
&& ((v->SourcePixelFormat[k] != dm_444_64
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3397
&& v->SourcePixelFormat[k] != dm_444_32
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3398
&& v->SourcePixelFormat[k] != dm_444_16
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3399
&& v->SourcePixelFormat[k] != dm_mono_16
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3400
&& v->SourcePixelFormat[k] != dm_mono_8
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3401
&& v->SourcePixelFormat[k] != dm_rgbe
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3402
&& v->SourcePixelFormat[k] != dm_rgbe_alpha)
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3403
|| v->HRatio[k] != 1.0
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3404
|| v->htaps[k] != 1.0
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3405
|| v->VRatio[k] != 1.0
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3406
|| v->vtaps[k] != 1.0)) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3407
v->ScaleRatioAndTapsSupport = false;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3408
} else if (v->vtaps[k] < 1.0 || v->vtaps[k] > 8.0
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3409
|| v->htaps[k] < 1.0 || v->htaps[k] > 8.0
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3410
|| (v->htaps[k] > 1.0
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3411
&& (v->htaps[k] % 2) == 1)
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3412
|| v->HRatio[k] > v->MaxHSCLRatio
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3413
|| v->VRatio[k] > v->MaxVSCLRatio
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3414
|| v->HRatio[k] > v->htaps[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3415
|| v->VRatio[k] > v->vtaps[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3416
|| (v->SourcePixelFormat[k] != dm_444_64
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3417
&& v->SourcePixelFormat[k] != dm_444_32
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3418
&& v->SourcePixelFormat[k] != dm_444_16
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3419
&& v->SourcePixelFormat[k] != dm_mono_16
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3420
&& v->SourcePixelFormat[k] != dm_mono_8
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3421
&& v->SourcePixelFormat[k] != dm_rgbe
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3422
&& (v->VTAPsChroma[k] < 1
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3423
|| v->VTAPsChroma[k] > 8
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3424
|| v->HTAPsChroma[k] < 1
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3425
|| v->HTAPsChroma[k] > 8
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3426
|| (v->HTAPsChroma[k] > 1 && v->HTAPsChroma[k] % 2 == 1)
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3427
|| v->HRatioChroma[k] > v->MaxHSCLRatio
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3428
|| v->VRatioChroma[k] > v->MaxVSCLRatio
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3429
|| v->HRatioChroma[k] > v->HTAPsChroma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3430
|| v->VRatioChroma[k] > v->VTAPsChroma[k]))) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3431
v->ScaleRatioAndTapsSupport = false;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3436
v->SourceFormatPixelAndScanSupport = true;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3437
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3438
if ((v->SurfaceTiling[k] == dm_sw_linear && (!(v->SourceScan[k] != dm_vert) || v->DCCEnable[k] == true))
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3439
|| ((v->SurfaceTiling[k] == dm_sw_64kb_d || v->SurfaceTiling[k] == dm_sw_64kb_d_t || v->SurfaceTiling[k] == dm_sw_64kb_d_x)
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3440
&& !(v->SourcePixelFormat[k] == dm_444_64))) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3441
v->SourceFormatPixelAndScanSupport = false;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3446
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3448
v->SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3449
v->SurfaceTiling[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3450
&v->BytePerPixelY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3451
&v->BytePerPixelC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3452
&v->BytePerPixelInDETY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3453
&v->BytePerPixelInDETC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3454
&v->Read256BlockHeightY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3455
&v->Read256BlockHeightC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3456
&v->Read256BlockWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3457
&v->Read256BlockWidthC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3459
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3460
if (v->SourceScan[k] != dm_vert) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3461
v->SwathWidthYSingleDPP[k] = v->ViewportWidth[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3462
v->SwathWidthCSingleDPP[k] = v->ViewportWidthChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3464
v->SwathWidthYSingleDPP[k] = v->ViewportHeight[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3465
v->SwathWidthCSingleDPP[k] = v->ViewportHeightChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3468
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3469
v->ReadBandwidthLuma[k] = v->SwathWidthYSingleDPP[k] * dml_ceil(v->BytePerPixelInDETY[k], 1.0) / (v->HTotal[k] / v->PixelClock[k]) * v->VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3470
v->ReadBandwidthChroma[k] = v->SwathWidthYSingleDPP[k] / 2 * dml_ceil(v->BytePerPixelInDETC[k], 2.0) / (v->HTotal[k] / v->PixelClock[k]) * v->VRatio[k] / 2.0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3472
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3473
if (v->WritebackEnable[k] == true
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3474
&& v->WritebackPixelFormat[k] == dm_444_64) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3475
v->WriteBandwidth[k] = v->WritebackDestinationWidth[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3476
* v->WritebackDestinationHeight[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3477
/ (v->WritebackSourceHeight[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3478
* v->HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3479
/ v->PixelClock[k]) * 8.0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3480
} else if (v->WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3481
v->WriteBandwidth[k] = v->WritebackDestinationWidth[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3482
* v->WritebackDestinationHeight[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3483
/ (v->WritebackSourceHeight[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3484
* v->HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3485
/ v->PixelClock[k]) * 4.0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3487
v->WriteBandwidth[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3493
v->WritebackLatencySupport = true;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3494
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3495
if (v->WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3496
if (v->WritebackConfiguration == dm_whole_buffer_for_single_stream_no_interleave ||
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3497
v->WritebackConfiguration == dm_whole_buffer_for_single_stream_interleave) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3498
if (v->WriteBandwidth[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3499
> 2.0 * v->WritebackInterfaceBufferSize * 1024
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3500
/ v->WritebackLatency) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3501
v->WritebackLatencySupport = false;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3504
if (v->WriteBandwidth[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3505
> v->WritebackInterfaceBufferSize * 1024
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3506
/ v->WritebackLatency) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3507
v->WritebackLatencySupport = false;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3515
v->TotalNumberOfActiveWriteback = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3516
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3517
if (v->WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3518
v->TotalNumberOfActiveWriteback =
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3519
v->TotalNumberOfActiveWriteback + 1;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3523
if (v->TotalNumberOfActiveWriteback > v->MaxNumWriteback) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3526
if (!v->WritebackSupportInterleaveAndUsingWholeBufferForASingleStream
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3527
&& (v->WritebackConfiguration == dm_whole_buffer_for_single_stream_no_interleave
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3528
|| v->WritebackConfiguration == dm_whole_buffer_for_single_stream_interleave)) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3532
if (v->WritebackConfiguration == dm_whole_buffer_for_single_stream_no_interleave && v->TotalNumberOfActiveWriteback > 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3538
v->WritebackScaleRatioAndTapsSupport = true;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3539
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3540
if (v->WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3541
if (v->WritebackHRatio[k] > v->WritebackMaxHSCLRatio
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3542
|| v->WritebackVRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3543
> v->WritebackMaxVSCLRatio
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3544
|| v->WritebackHRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3545
< v->WritebackMinHSCLRatio
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3546
|| v->WritebackVRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3547
< v->WritebackMinVSCLRatio
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3548
|| v->WritebackHTaps[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3549
> v->WritebackMaxHSCLTaps
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3550
|| v->WritebackVTaps[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3551
> v->WritebackMaxVSCLTaps
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3552
|| v->WritebackHRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3553
> v->WritebackHTaps[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3554
|| v->WritebackVRatio[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3555
> v->WritebackVTaps[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3556
|| (v->WritebackHTaps[k] > 2.0
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3557
&& ((v->WritebackHTaps[k] % 2)
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3559
v->WritebackScaleRatioAndTapsSupport = false;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3561
if (2.0 * v->WritebackDestinationWidth[k] * (v->WritebackVTaps[k] - 1) * 57 > v->WritebackLineBufferSize) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3562
v->WritebackScaleRatioAndTapsSupport = false;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3568
v->WritebackRequiredDISPCLK = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3569
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3570
if (v->WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3571
v->WritebackRequiredDISPCLK = dml_max(v->WritebackRequiredDISPCLK,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3573
v->WritebackPixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3574
v->PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3575
v->WritebackHRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3576
v->WritebackVRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3577
v->WritebackHTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3578
v->WritebackVTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3579
v->WritebackSourceWidth[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3580
v->WritebackDestinationWidth[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3581
v->HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3582
v->WritebackLineBufferSize));
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3585
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3586
if (v->HRatio[k] > 1.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3587
v->PSCL_FACTOR[k] = dml_min(v->MaxDCHUBToPSCLThroughput, v->MaxPSCLToLBThroughput * v->HRatio[k] / dml_ceil(v->htaps[k] / 6.0, 1.0));
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3589
v->PSCL_FACTOR[k] = dml_min(v->MaxDCHUBToPSCLThroughput, v->MaxPSCLToLBThroughput);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3591
if (v->BytePerPixelC[k] == 0.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3592
v->PSCL_FACTOR_CHROMA[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3593
v->MinDPPCLKUsingSingleDPP[k] = v->PixelClock[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3594
* dml_max3(v->vtaps[k] / 6.0 * dml_min(1.0, v->HRatio[k]), v->HRatio[k] * v->VRatio[k] / v->PSCL_FACTOR[k], 1.0);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3595
if ((v->htaps[k] > 6.0 || v->vtaps[k] > 6.0) && v->MinDPPCLKUsingSingleDPP[k] < 2.0 * v->PixelClock[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3596
v->MinDPPCLKUsingSingleDPP[k] = 2.0 * v->PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3599
if (v->HRatioChroma[k] > 1.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3600
v->PSCL_FACTOR_CHROMA[k] = dml_min(v->MaxDCHUBToPSCLThroughput,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3601
v->MaxPSCLToLBThroughput * v->HRatioChroma[k] / dml_ceil(v->HTAPsChroma[k] / 6.0, 1.0));
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3603
v->PSCL_FACTOR_CHROMA[k] = dml_min(v->MaxDCHUBToPSCLThroughput, v->MaxPSCLToLBThroughput);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3605
v->MinDPPCLKUsingSingleDPP[k] = v->PixelClock[k] * dml_max5(v->vtaps[k] / 6.0 * dml_min(1.0, v->HRatio[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3606
v->HRatio[k] * v->VRatio[k] / v->PSCL_FACTOR[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3607
v->VTAPsChroma[k] / 6.0 * dml_min(1.0, v->HRatioChroma[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3608
v->HRatioChroma[k] * v->VRatioChroma[k] / v->PSCL_FACTOR_CHROMA[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3610
if ((v->htaps[k] > 6.0 || v->vtaps[k] > 6.0 || v->HTAPsChroma[k] > 6.0 || v->VTAPsChroma[k] > 6.0)
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3611
&& v->MinDPPCLKUsingSingleDPP[k] < 2.0 * v->PixelClock[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3612
v->MinDPPCLKUsingSingleDPP[k] = 2.0 * v->PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3616
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3620
if (v->SurfaceTiling[k] == dm_sw_linear) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3622
} else if (v->SourceScan[k] == dm_vert && v->BytePerPixelC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3628
if (v->SourcePixelFormat[k] == dm_420_8 || v->SourcePixelFormat[k] == dm_420_10 || v->SourcePixelFormat[k] == dm_420_12) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3633
v->MaximumSwathWidthInLineBufferLuma = v->LineBufferSize * dml_max(v->HRatio[k], 1.0) / v->LBBitPerPixel[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3634
/ (v->vtaps[k] + dml_max(dml_ceil(v->VRatio[k], 1.0) - 2, 0.0));
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3635
if (v->BytePerPixelC[k] == 0.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3636
v->MaximumSwathWidthInLineBufferChroma = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3638
v->MaximumSwathWidthInLineBufferChroma = v->LineBufferSize * dml_max(v->HRatioChroma[k], 1.0) / v->LBBitPerPixel[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3639
/ (v->VTAPsChroma[k] + dml_max(dml_ceil(v->VRatioChroma[k], 1.0) - 2, 0.0));
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3641
v->MaximumSwathWidthLuma[k] = dml_min(MaximumSwathWidthSupportLuma, v->MaximumSwathWidthInLineBufferLuma);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3642
v->MaximumSwathWidthChroma[k] = dml_min(MaximumSwathWidthSupportChroma, v->MaximumSwathWidthInLineBufferChroma);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3647
v->NumberOfActivePlanes,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3648
v->DETBufferSizeInKByte[0],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3649
v->MaximumSwathWidthLuma,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3650
v->MaximumSwathWidthChroma,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3651
v->SourceScan,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3652
v->SourcePixelFormat,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3653
v->SurfaceTiling,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3654
v->ViewportWidth,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3655
v->ViewportHeight,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3656
v->SurfaceWidthY,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3657
v->SurfaceWidthC,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3658
v->SurfaceHeightY,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3659
v->SurfaceHeightC,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3660
v->Read256BlockHeightY,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3661
v->Read256BlockHeightC,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3662
v->Read256BlockWidthY,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3663
v->Read256BlockWidthC,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3664
v->odm_combine_dummy,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3665
v->BlendingAndTiming,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3666
v->BytePerPixelY,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3667
v->BytePerPixelC,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3668
v->BytePerPixelInDETY,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3669
v->BytePerPixelInDETC,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3670
v->HActive,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3671
v->HRatio,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3672
v->HRatioChroma,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3673
v->DPPPerPlane,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3674
v->swath_width_luma_ub,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3675
v->swath_width_chroma_ub,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3676
v->SwathWidthY,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3677
v->SwathWidthC,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3678
v->SwathHeightY,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3679
v->SwathHeightC,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3680
v->DETBufferSizeY,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3681
v->DETBufferSizeC,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3682
v->SingleDPPViewportSizeSupportPerPlane,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3683
&v->ViewportSizeSupport[0][0]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3685
for (i = start_state; i < v->soc.num_states; i++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3687
v->MaxDispclkRoundedDownToDFSGranularity = RoundToDFSGranularityDown(v->MaxDispclk[i], v->DISPCLKDPPCLKVCOSpeed);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3688
v->MaxDppclkRoundedDownToDFSGranularity = RoundToDFSGranularityDown(v->MaxDppclk[i], v->DISPCLKDPPCLKVCOSpeed);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3689
v->RequiredDISPCLK[i][j] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3690
v->DISPCLK_DPPCLK_Support[i][j] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3691
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3692
v->PlaneRequiredDISPCLKWithoutODMCombine = v->PixelClock[k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3693
* (1.0 + v->DISPCLKRampingMargin / 100.0);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3694
if ((v->PlaneRequiredDISPCLKWithoutODMCombine >= v->MaxDispclk[i] && v->MaxDispclk[i] == v->MaxDispclk[mode_lib->soc.num_states - 1]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3695
&& v->MaxDppclk[i] == v->MaxDppclk[mode_lib->soc.num_states - 1])) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3696
v->PlaneRequiredDISPCLKWithoutODMCombine = v->PixelClock[k] * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3698
v->PlaneRequiredDISPCLKWithODMCombine2To1 = v->PixelClock[k] / 2 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3699
* (1 + v->DISPCLKRampingMargin / 100.0);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3700
if ((v->PlaneRequiredDISPCLKWithODMCombine2To1 >= v->MaxDispclk[i] && v->MaxDispclk[i] == v->MaxDispclk[mode_lib->soc.num_states - 1]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3701
&& v->MaxDppclk[i] == v->MaxDppclk[mode_lib->soc.num_states - 1])) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3702
v->PlaneRequiredDISPCLKWithODMCombine2To1 = v->PixelClock[k] / 2 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3704
v->PlaneRequiredDISPCLKWithODMCombine4To1 = v->PixelClock[k] / 4 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3705
* (1 + v->DISPCLKRampingMargin / 100.0);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3706
if ((v->PlaneRequiredDISPCLKWithODMCombine4To1 >= v->MaxDispclk[i] && v->MaxDispclk[i] == v->MaxDispclk[mode_lib->soc.num_states - 1]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3707
&& v->MaxDppclk[i] == v->MaxDppclk[mode_lib->soc.num_states - 1])) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3708
v->PlaneRequiredDISPCLKWithODMCombine4To1 = v->PixelClock[k] / 4 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3711
if (v->ODMCombinePolicy == dm_odm_combine_policy_none) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3712
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_disabled;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3713
v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithoutODMCombine;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3714
} else if (v->ODMCombinePolicy == dm_odm_combine_policy_2to1) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3715
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3716
v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithODMCombine2To1;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3717
} else if (v->ODMCombinePolicy == dm_odm_combine_policy_4to1
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3718
|| v->PlaneRequiredDISPCLKWithODMCombine2To1 > v->MaxDispclkRoundedDownToDFSGranularity) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3719
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_4to1;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3720
v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithODMCombine4To1;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3721
} else if (v->PlaneRequiredDISPCLKWithoutODMCombine > v->MaxDispclkRoundedDownToDFSGranularity) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3722
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3723
v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithODMCombine2To1;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3725
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_disabled;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3726
v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithoutODMCombine;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3728
if (v->DSCEnabled[k] && v->HActive[k] > DCN30_MAX_DSC_IMAGE_WIDTH
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3729
&& v->ODMCombineEnablePerState[i][k] != dm_odm_combine_mode_4to1) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3730
if (v->HActive[k] / 2 > DCN30_MAX_DSC_IMAGE_WIDTH) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3731
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_4to1;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3732
v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithODMCombine4To1;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3734
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3735
v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithODMCombine2To1;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3738
if (v->OutputFormat[k] == dm_420 && v->HActive[k] > DCN30_MAX_FMT_420_BUFFER_WIDTH
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3739
&& v->ODMCombineEnablePerState[i][k] != dm_odm_combine_mode_4to1) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3740
if (v->HActive[k] / 2 > DCN30_MAX_FMT_420_BUFFER_WIDTH) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3741
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_4to1;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3742
v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithODMCombine4To1;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3744
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3745
v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithODMCombine2To1;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3748
if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3749
v->MPCCombine[i][j][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3750
v->NoOfDPP[i][j][k] = 4;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3751
v->RequiredDPPCLK[i][j][k] = v->MinDPPCLKUsingSingleDPP[k] * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) / 4;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3752
} else if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3753
v->MPCCombine[i][j][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3754
v->NoOfDPP[i][j][k] = 2;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3755
v->RequiredDPPCLK[i][j][k] = v->MinDPPCLKUsingSingleDPP[k] * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) / 2;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3756
} else if ((v->WhenToDoMPCCombine == dm_mpc_never
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3757
|| (v->MinDPPCLKUsingSingleDPP[k] * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) <= v->MaxDppclkRoundedDownToDFSGranularity
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3758
&& v->SingleDPPViewportSizeSupportPerPlane[k] == true))) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3759
v->MPCCombine[i][j][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3760
v->NoOfDPP[i][j][k] = 1;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3761
v->RequiredDPPCLK[i][j][k] = v->MinDPPCLKUsingSingleDPP[k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3763
v->MPCCombine[i][j][k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3764
v->NoOfDPP[i][j][k] = 2;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3765
v->RequiredDPPCLK[i][j][k] = v->MinDPPCLKUsingSingleDPP[k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) / 2.0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3767
v->RequiredDISPCLK[i][j] = dml_max(v->RequiredDISPCLK[i][j], v->PlaneRequiredDISPCLK);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3768
if ((v->MinDPPCLKUsingSingleDPP[k] / v->NoOfDPP[i][j][k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3769
> v->MaxDppclkRoundedDownToDFSGranularity) || (v->PlaneRequiredDISPCLK > v->MaxDispclkRoundedDownToDFSGranularity)) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3770
v->DISPCLK_DPPCLK_Support[i][j] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3773
v->TotalNumberOfActiveDPP[i][j] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3774
v->TotalNumberOfSingleDPPPlanes[i][j] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3775
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3776
v->TotalNumberOfActiveDPP[i][j] = v->TotalNumberOfActiveDPP[i][j] + v->NoOfDPP[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3777
if (v->NoOfDPP[i][j][k] == 1)
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3778
v->TotalNumberOfSingleDPPPlanes[i][j] = v->TotalNumberOfSingleDPPPlanes[i][j] + 1;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3780
if (j == 1 && v->WhenToDoMPCCombine != dm_mpc_never) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3781
while (!(v->TotalNumberOfActiveDPP[i][j] >= v->MaxNumDPP || v->TotalNumberOfSingleDPPPlanes[i][j] == 0)) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3786
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3787
if (v->ReadBandwidthLuma[k] + v->ReadBandwidthChroma[k] > BWOfNonSplitPlaneOfMaximumBandwidth
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3788
&& v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_disabled && v->MPCCombine[i][j][k] == false) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3789
BWOfNonSplitPlaneOfMaximumBandwidth = v->ReadBandwidthLuma[k] + v->ReadBandwidthChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3793
v->MPCCombine[i][j][NumberOfNonSplitPlaneOfMaximumBandwidth] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3794
v->NoOfDPP[i][j][NumberOfNonSplitPlaneOfMaximumBandwidth] = 2;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3795
v->RequiredDPPCLK[i][j][NumberOfNonSplitPlaneOfMaximumBandwidth] = v->MinDPPCLKUsingSingleDPP[NumberOfNonSplitPlaneOfMaximumBandwidth]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3796
* (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100) / 2;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3797
v->TotalNumberOfActiveDPP[i][j] = v->TotalNumberOfActiveDPP[i][j] + 1;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3798
v->TotalNumberOfSingleDPPPlanes[i][j] = v->TotalNumberOfSingleDPPPlanes[i][j] - 1;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3801
if (v->TotalNumberOfActiveDPP[i][j] > v->MaxNumDPP) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3802
v->RequiredDISPCLK[i][j] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3803
v->DISPCLK_DPPCLK_Support[i][j] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3804
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3805
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_disabled;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3806
if (v->SingleDPPViewportSizeSupportPerPlane[k] == false && v->WhenToDoMPCCombine != dm_mpc_never) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3807
v->MPCCombine[i][j][k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3808
v->NoOfDPP[i][j][k] = 2;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3809
v->RequiredDPPCLK[i][j][k] = v->MinDPPCLKUsingSingleDPP[k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) / 2.0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3811
v->MPCCombine[i][j][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3812
v->NoOfDPP[i][j][k] = 1;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3813
v->RequiredDPPCLK[i][j][k] = v->MinDPPCLKUsingSingleDPP[k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3815
if (!(v->MaxDispclk[i] == v->MaxDispclk[v->soc.num_states - 1] && v->MaxDppclk[i] == v->MaxDppclk[v->soc.num_states - 1])) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3816
v->PlaneRequiredDISPCLK = v->PixelClock[k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3817
* (1.0 + v->DISPCLKRampingMargin / 100.0);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3819
v->PlaneRequiredDISPCLK = v->PixelClock[k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3821
v->RequiredDISPCLK[i][j] = dml_max(v->RequiredDISPCLK[i][j], v->PlaneRequiredDISPCLK);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3822
if ((v->MinDPPCLKUsingSingleDPP[k] / v->NoOfDPP[i][j][k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3823
> v->MaxDppclkRoundedDownToDFSGranularity) || (v->PlaneRequiredDISPCLK > v->MaxDispclkRoundedDownToDFSGranularity)) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3824
v->DISPCLK_DPPCLK_Support[i][j] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3827
v->TotalNumberOfActiveDPP[i][j] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3828
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3829
v->TotalNumberOfActiveDPP[i][j] = v->TotalNumberOfActiveDPP[i][j] + v->NoOfDPP[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3832
v->RequiredDISPCLK[i][j] = dml_max(v->RequiredDISPCLK[i][j], v->WritebackRequiredDISPCLK);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3833
if (v->MaxDispclkRoundedDownToDFSGranularity < v->WritebackRequiredDISPCLK) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3834
v->DISPCLK_DPPCLK_Support[i][j] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3841
for (i = start_state; i < v->soc.num_states; i++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3843
if (v->TotalNumberOfActiveDPP[i][j] <= v->MaxNumDPP) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3844
v->TotalAvailablePipesSupport[i][j] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3846
v->TotalAvailablePipesSupport[i][j] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3852
v->NonsupportedDSCInputBPC = false;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3853
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3854
if (!(v->DSCInputBitPerComponent[k] == 12.0
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3855
|| v->DSCInputBitPerComponent[k] == 10.0
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3856
|| v->DSCInputBitPerComponent[k] == 8.0)) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3857
v->NonsupportedDSCInputBPC = true;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3862
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3863
if (v->BlendingAndTiming[k] == k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3864
if (v->PixelClockBackEnd[k] > 3200) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3865
v->NumberOfDSCSlices[k] = dml_ceil(v->PixelClockBackEnd[k] / 400.0, 4.0);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3866
} else if (v->PixelClockBackEnd[k] > 1360) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3867
v->NumberOfDSCSlices[k] = 8;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3868
} else if (v->PixelClockBackEnd[k] > 680) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3869
v->NumberOfDSCSlices[k] = 4;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3870
} else if (v->PixelClockBackEnd[k] > 340) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3871
v->NumberOfDSCSlices[k] = 2;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3873
v->NumberOfDSCSlices[k] = 1;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3876
v->NumberOfDSCSlices[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3880
for (i = start_state; i < v->soc.num_states; i++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3881
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3882
v->RequiresDSC[i][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3883
v->RequiresFEC[i][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3884
if (v->BlendingAndTiming[k] == k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3885
if (v->Output[k] == dm_hdmi) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3886
v->RequiresDSC[i][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3887
v->RequiresFEC[i][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3888
v->OutputBppPerState[i][k] = TruncToValidBPP(
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3889
dml_min(600.0, v->PHYCLKPerState[i]) * 10,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3891
v->HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3892
v->HActive[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3893
v->PixelClockBackEnd[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3894
v->ForcedOutputLinkBPP[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3896
v->Output[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3897
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3898
v->DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3899
v->NumberOfDSCSlices[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3900
v->AudioSampleRate[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3901
v->AudioSampleLayout[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3902
v->ODMCombineEnablePerState[i][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3903
} else if (v->Output[k] == dm_dp || v->Output[k] == dm_edp) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3904
if (v->DSCEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3905
v->RequiresDSC[i][k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3906
v->LinkDSCEnable = true;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3907
if (v->Output[k] == dm_dp) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3908
v->RequiresFEC[i][k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3910
v->RequiresFEC[i][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3913
v->RequiresDSC[i][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3914
v->LinkDSCEnable = false;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3915
v->RequiresFEC[i][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3918
v->Outbpp = BPP_INVALID;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3919
if (v->PHYCLKPerState[i] >= 270.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3920
v->Outbpp = TruncToValidBPP(
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3921
(1.0 - v->Downspreading / 100.0) * 2700,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3922
v->OutputLinkDPLanes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3923
v->HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3924
v->HActive[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3925
v->PixelClockBackEnd[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3926
v->ForcedOutputLinkBPP[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3927
v->LinkDSCEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3928
v->Output[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3929
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3930
v->DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3931
v->NumberOfDSCSlices[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3932
v->AudioSampleRate[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3933
v->AudioSampleLayout[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3934
v->ODMCombineEnablePerState[i][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3935
v->OutputBppPerState[i][k] = v->Outbpp;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3939
if (v->Outbpp == BPP_INVALID && v->PHYCLKPerState[i] >= 540.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3940
v->Outbpp = TruncToValidBPP(
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3941
(1.0 - v->Downspreading / 100.0) * 5400,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3942
v->OutputLinkDPLanes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3943
v->HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3944
v->HActive[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3945
v->PixelClockBackEnd[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3946
v->ForcedOutputLinkBPP[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3947
v->LinkDSCEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3948
v->Output[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3949
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3950
v->DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3951
v->NumberOfDSCSlices[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3952
v->AudioSampleRate[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3953
v->AudioSampleLayout[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3954
v->ODMCombineEnablePerState[i][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3955
v->OutputBppPerState[i][k] = v->Outbpp;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3959
if (v->Outbpp == BPP_INVALID && v->PHYCLKPerState[i] >= 810.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3960
v->Outbpp = TruncToValidBPP(
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3961
(1.0 - v->Downspreading / 100.0) * 8100,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3962
v->OutputLinkDPLanes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3963
v->HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3964
v->HActive[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3965
v->PixelClockBackEnd[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3966
v->ForcedOutputLinkBPP[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3967
v->LinkDSCEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3968
v->Output[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3969
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3970
v->DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3971
v->NumberOfDSCSlices[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3972
v->AudioSampleRate[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3973
v->AudioSampleLayout[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3974
v->ODMCombineEnablePerState[i][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3975
if (v->Outbpp == BPP_INVALID && v->ForcedOutputLinkBPP[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3977
v->RequiresDSC[i][k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3978
v->LinkDSCEnable = true;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3979
if (v->Output[k] == dm_dp) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3980
v->RequiresFEC[i][k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3982
v->Outbpp = TruncToValidBPP(
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3983
(1.0 - v->Downspreading / 100.0) * 8100,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3984
v->OutputLinkDPLanes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3985
v->HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3986
v->HActive[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3987
v->PixelClockBackEnd[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3988
v->ForcedOutputLinkBPP[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3989
v->LinkDSCEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3990
v->Output[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3991
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3992
v->DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3993
v->NumberOfDSCSlices[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3994
v->AudioSampleRate[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3995
v->AudioSampleLayout[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3996
v->ODMCombineEnablePerState[i][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
3998
v->OutputBppPerState[i][k] = v->Outbpp;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4004
v->OutputBppPerState[i][k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4008
for (i = start_state; i < v->soc.num_states; i++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4009
v->DIOSupport[i] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4010
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4011
if (!v->skip_dio_check[k] && v->BlendingAndTiming[k] == k && (v->Output[k] == dm_dp || v->Output[k] == dm_edp || v->Output[k] == dm_hdmi)
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4012
&& (v->OutputBppPerState[i][k] == 0
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4013
|| (v->OutputFormat[k] == dm_420 && v->Interlace[k] == true && v->ProgressiveToInterlaceUnitInOPP == true))) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4014
v->DIOSupport[i] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4019
for (i = start_state; i < v->soc.num_states; ++i) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4020
v->ODMCombine4To1SupportCheckOK[i] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4021
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4022
if (v->BlendingAndTiming[k] == k && v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4023
&& (v->ODMCombine4To1Supported == false || v->Output[k] == dm_dp || v->Output[k] == dm_edp || v->Output[k] == dm_hdmi)) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4024
v->ODMCombine4To1SupportCheckOK[i] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4031
for (i = start_state; i < v->soc.num_states; i++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4032
v->NotEnoughDSCUnits[i] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4033
v->TotalDSCUnitsRequired = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4034
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4035
if (v->RequiresDSC[i][k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4036
if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4037
v->TotalDSCUnitsRequired = v->TotalDSCUnitsRequired + 4.0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4038
} else if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4039
v->TotalDSCUnitsRequired = v->TotalDSCUnitsRequired + 2.0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4041
v->TotalDSCUnitsRequired = v->TotalDSCUnitsRequired + 1.0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4045
if (v->TotalDSCUnitsRequired > v->NumberOfDSC) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4046
v->NotEnoughDSCUnits[i] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4051
for (i = start_state; i < v->soc.num_states; i++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4052
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4053
if (v->OutputBppPerState[i][k] == BPP_INVALID) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4054
v->BPP = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4056
v->BPP = v->OutputBppPerState[i][k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4058
if (v->RequiresDSC[i][k] == true && v->BPP != 0.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4059
if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_disabled) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4060
v->DSCDelayPerState[i][k] = dscceComputeDelay(
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4061
v->DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4062
v->BPP,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4063
dml_ceil(1.0 * v->HActive[k] / v->NumberOfDSCSlices[k], 1.0),
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4064
v->NumberOfDSCSlices[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4065
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4066
v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4067
} else if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4068
v->DSCDelayPerState[i][k] = 2.0
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4070
v->DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4071
v->BPP,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4072
dml_ceil(1.0 * v->HActive[k] / v->NumberOfDSCSlices[k], 1.0),
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4073
v->NumberOfDSCSlices[k] / 2,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4074
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4075
v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4077
v->DSCDelayPerState[i][k] = 4.0
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4079
v->DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4080
v->BPP,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4081
dml_ceil(1.0 * v->HActive[k] / v->NumberOfDSCSlices[k], 1.0),
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4082
v->NumberOfDSCSlices[k] / 4,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4083
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4084
v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k]));
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4086
v->DSCDelayPerState[i][k] = v->DSCDelayPerState[i][k] * v->PixelClock[k] / v->PixelClockBackEnd[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4088
v->DSCDelayPerState[i][k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4091
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4092
for (m = 0; m <= v->NumberOfActivePlanes - 1; m++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4093
if (v->BlendingAndTiming[k] == m && v->RequiresDSC[i][m] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4094
v->DSCDelayPerState[i][k] = v->DSCDelayPerState[i][m];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4104
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4105
v->RequiredDPPCLKThisState[k] = v->RequiredDPPCLK[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4106
v->NoOfDPPThisState[k] = v->NoOfDPP[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4107
v->ODMCombineEnableThisState[k] = v->ODMCombineEnablePerState[i][k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4112
v->NumberOfActivePlanes,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4113
v->DETBufferSizeInKByte[0],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4114
v->MaximumSwathWidthLuma,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4115
v->MaximumSwathWidthChroma,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4116
v->SourceScan,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4117
v->SourcePixelFormat,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4118
v->SurfaceTiling,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4119
v->ViewportWidth,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4120
v->ViewportHeight,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4121
v->SurfaceWidthY,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4122
v->SurfaceWidthC,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4123
v->SurfaceHeightY,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4124
v->SurfaceHeightC,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4125
v->Read256BlockHeightY,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4126
v->Read256BlockHeightC,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4127
v->Read256BlockWidthY,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4128
v->Read256BlockWidthC,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4129
v->ODMCombineEnableThisState,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4130
v->BlendingAndTiming,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4131
v->BytePerPixelY,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4132
v->BytePerPixelC,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4133
v->BytePerPixelInDETY,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4134
v->BytePerPixelInDETC,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4135
v->HActive,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4136
v->HRatio,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4137
v->HRatioChroma,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4138
v->NoOfDPPThisState,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4139
v->swath_width_luma_ub_this_state,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4140
v->swath_width_chroma_ub_this_state,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4141
v->SwathWidthYThisState,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4142
v->SwathWidthCThisState,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4143
v->SwathHeightYThisState,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4144
v->SwathHeightCThisState,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4145
v->DETBufferSizeYThisState,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4146
v->DETBufferSizeCThisState,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4147
v->dummystring,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4148
&v->ViewportSizeSupport[i][j]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4150
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4151
v->swath_width_luma_ub_all_states[i][j][k] = v->swath_width_luma_ub_this_state[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4152
v->swath_width_chroma_ub_all_states[i][j][k] = v->swath_width_chroma_ub_this_state[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4153
v->SwathWidthYAllStates[i][j][k] = v->SwathWidthYThisState[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4154
v->SwathWidthCAllStates[i][j][k] = v->SwathWidthCThisState[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4155
v->SwathHeightYAllStates[i][j][k] = v->SwathHeightYThisState[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4156
v->SwathHeightCAllStates[i][j][k] = v->SwathHeightCThisState[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4157
v->DETBufferSizeYAllStates[i][j][k] = v->DETBufferSizeYThisState[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4158
v->DETBufferSizeCAllStates[i][j][k] = v->DETBufferSizeCThisState[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4163
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4164
v->cursor_bw[k] = v->NumberOfCursors[k] * v->CursorWidth[k][0] * v->CursorBPP[k][0] / 8.0 / (v->HTotal[k] / v->PixelClock[k]) * v->VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4167
for (i = start_state; i < v->soc.num_states; i++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4169
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4170
v->swath_width_luma_ub_this_state[k] = v->swath_width_luma_ub_all_states[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4171
v->swath_width_chroma_ub_this_state[k] = v->swath_width_chroma_ub_all_states[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4172
v->SwathWidthYThisState[k] = v->SwathWidthYAllStates[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4173
v->SwathWidthCThisState[k] = v->SwathWidthCAllStates[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4174
v->SwathHeightYThisState[k] = v->SwathHeightYAllStates[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4175
v->SwathHeightCThisState[k] = v->SwathHeightCAllStates[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4176
v->DETBufferSizeYThisState[k] = v->DETBufferSizeYAllStates[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4177
v->DETBufferSizeCThisState[k] = v->DETBufferSizeCAllStates[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4180
v->TotalNumberOfDCCActiveDPP[i][j] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4181
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4182
if (v->DCCEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4183
v->TotalNumberOfDCCActiveDPP[i][j] = v->TotalNumberOfDCCActiveDPP[i][j] + v->NoOfDPP[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4187
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4188
if (v->SourcePixelFormat[k] == dm_420_8 || v->SourcePixelFormat[k] == dm_420_10 || v->SourcePixelFormat[k] == dm_420_12
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4189
|| v->SourcePixelFormat[k] == dm_rgbe_alpha) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4191
if ((v->SourcePixelFormat[k] == dm_420_10 || v->SourcePixelFormat[k] == dm_420_12) && v->SourceScan[k] != dm_vert) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4192
v->PTEBufferSizeInRequestsForLuma = (v->PTEBufferSizeInRequestsLuma + v->PTEBufferSizeInRequestsChroma) / 2;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4193
v->PTEBufferSizeInRequestsForChroma = v->PTEBufferSizeInRequestsForLuma;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4195
v->PTEBufferSizeInRequestsForLuma = v->PTEBufferSizeInRequestsLuma;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4196
v->PTEBufferSizeInRequestsForChroma = v->PTEBufferSizeInRequestsChroma;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4199
v->PDEAndMetaPTEBytesPerFrameC = CalculateVMAndRowBytes(
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4201
v->DCCEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4202
v->Read256BlockHeightC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4203
v->Read256BlockWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4204
v->SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4205
v->SurfaceTiling[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4206
v->BytePerPixelC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4207
v->SourceScan[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4208
v->SwathWidthCThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4209
v->ViewportHeightChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4210
v->GPUVMEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4211
v->HostVMEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4212
v->HostVMMaxNonCachedPageTableLevels,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4213
v->GPUVMMinPageSize,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4214
v->HostVMMinPageSize,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4215
v->PTEBufferSizeInRequestsForChroma,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4216
v->PitchC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4218
&v->MacroTileWidthC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4219
&v->MetaRowBytesC,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4220
&v->DPTEBytesPerRowC,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4221
&v->PTEBufferSizeNotExceededC[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4222
&v->dummyinteger7,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4223
&v->dpte_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4224
&v->dummyinteger28,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4225
&v->dummyinteger26,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4226
&v->dummyinteger23,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4227
&v->meta_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4228
&v->dummyinteger8,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4229
&v->dummyinteger9,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4230
&v->dummyinteger19,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4231
&v->dummyinteger20,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4232
&v->dummyinteger17,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4233
&v->dummyinteger10,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4234
&v->dummyinteger11);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4236
v->PrefetchLinesC[i][j][k] = CalculatePrefetchSourceLines(
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4238
v->VRatioChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4239
v->VTAPsChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4240
v->Interlace[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4241
v->ProgressiveToInterlaceUnitInOPP,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4242
v->SwathHeightCThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4243
v->ViewportYStartC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4244
&v->PrefillC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4245
&v->MaxNumSwC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4247
v->PTEBufferSizeInRequestsForLuma = v->PTEBufferSizeInRequestsLuma + v->PTEBufferSizeInRequestsChroma;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4248
v->PTEBufferSizeInRequestsForChroma = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4249
v->PDEAndMetaPTEBytesPerFrameC = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4250
v->MetaRowBytesC = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4251
v->DPTEBytesPerRowC = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4252
v->PrefetchLinesC[i][j][k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4253
v->PTEBufferSizeNotExceededC[i][j][k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4255
v->PDEAndMetaPTEBytesPerFrameY = CalculateVMAndRowBytes(
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4257
v->DCCEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4258
v->Read256BlockHeightY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4259
v->Read256BlockWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4260
v->SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4261
v->SurfaceTiling[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4262
v->BytePerPixelY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4263
v->SourceScan[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4264
v->SwathWidthYThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4265
v->ViewportHeight[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4266
v->GPUVMEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4267
v->HostVMEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4268
v->HostVMMaxNonCachedPageTableLevels,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4269
v->GPUVMMinPageSize,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4270
v->HostVMMinPageSize,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4271
v->PTEBufferSizeInRequestsForLuma,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4272
v->PitchY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4273
v->DCCMetaPitchY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4274
&v->MacroTileWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4275
&v->MetaRowBytesY,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4276
&v->DPTEBytesPerRowY,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4277
&v->PTEBufferSizeNotExceededY[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4278
v->dummyinteger4,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4279
&v->dpte_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4280
&v->dummyinteger29,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4281
&v->dummyinteger27,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4282
&v->dummyinteger24,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4283
&v->meta_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4284
&v->dummyinteger25,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4285
&v->dpte_group_bytes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4286
&v->dummyinteger21,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4287
&v->dummyinteger22,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4288
&v->dummyinteger18,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4289
&v->dummyinteger5,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4290
&v->dummyinteger6);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4291
v->PrefetchLinesY[i][j][k] = CalculatePrefetchSourceLines(
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4293
v->VRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4294
v->vtaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4295
v->Interlace[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4296
v->ProgressiveToInterlaceUnitInOPP,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4297
v->SwathHeightYThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4298
v->ViewportYStartY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4299
&v->PrefillY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4300
&v->MaxNumSwY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4301
v->PDEAndMetaPTEBytesPerFrame[i][j][k] = v->PDEAndMetaPTEBytesPerFrameY + v->PDEAndMetaPTEBytesPerFrameC;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4302
v->MetaRowBytes[i][j][k] = v->MetaRowBytesY + v->MetaRowBytesC;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4303
v->DPTEBytesPerRow[i][j][k] = v->DPTEBytesPerRowY + v->DPTEBytesPerRowC;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4306
v->GPUVMEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4307
v->SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4308
v->VRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4309
v->VRatioChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4310
v->DCCEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4311
v->HTotal[k] / v->PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4312
v->MetaRowBytesY,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4313
v->MetaRowBytesC,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4314
v->meta_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4315
v->meta_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4316
v->DPTEBytesPerRowY,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4317
v->DPTEBytesPerRowC,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4318
v->dpte_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4319
v->dpte_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4320
&v->meta_row_bandwidth[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4321
&v->dpte_row_bandwidth[i][j][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4323
v->UrgLatency[i] = CalculateUrgentLatency(
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4324
v->UrgentLatencyPixelDataOnly,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4325
v->UrgentLatencyPixelMixedWithVMData,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4326
v->UrgentLatencyVMDataOnly,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4327
v->DoUrgentLatencyAdjustment,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4328
v->UrgentLatencyAdjustmentFabricClockComponent,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4329
v->UrgentLatencyAdjustmentFabricClockReference,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4330
v->FabricClockPerState[i]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4332
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4334
v->swath_width_luma_ub_this_state[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4335
v->swath_width_chroma_ub_this_state[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4336
v->DETBufferSizeInKByte[0],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4337
v->SwathHeightYThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4338
v->SwathHeightCThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4339
v->HTotal[k] / v->PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4340
v->UrgLatency[i],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4341
v->CursorBufferSize,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4342
v->CursorWidth[k][0],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4343
v->CursorBPP[k][0],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4344
v->VRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4345
v->VRatioChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4346
v->BytePerPixelInDETY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4347
v->BytePerPixelInDETC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4348
v->DETBufferSizeYThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4349
v->DETBufferSizeCThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4350
&v->UrgentBurstFactorCursor[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4351
&v->UrgentBurstFactorLuma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4352
&v->UrgentBurstFactorChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4356
v->NotUrgentLatencyHiding[i][j] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4357
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4359
v->NotUrgentLatencyHiding[i][j] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4363
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4364
v->VActivePixelBandwidth[i][j][k] = v->ReadBandwidthLuma[k] * v->UrgentBurstFactorLuma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4365
+ v->ReadBandwidthChroma[k] * v->UrgentBurstFactorChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4366
v->VActiveCursorBandwidth[i][j][k] = v->cursor_bw[k] * v->UrgentBurstFactorCursor[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4369
v->TotalVActivePixelBandwidth[i][j] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4370
v->TotalVActiveCursorBandwidth[i][j] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4371
v->TotalMetaRowBandwidth[i][j] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4372
v->TotalDPTERowBandwidth[i][j] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4373
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4374
v->TotalVActivePixelBandwidth[i][j] = v->TotalVActivePixelBandwidth[i][j] + v->VActivePixelBandwidth[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4375
v->TotalVActiveCursorBandwidth[i][j] = v->TotalVActiveCursorBandwidth[i][j] + v->VActiveCursorBandwidth[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4376
v->TotalMetaRowBandwidth[i][j] = v->TotalMetaRowBandwidth[i][j] + v->NoOfDPP[i][j][k] * v->meta_row_bandwidth[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4377
v->TotalDPTERowBandwidth[i][j] = v->TotalDPTERowBandwidth[i][j] + v->NoOfDPP[i][j][k] * v->dpte_row_bandwidth[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4382
v->NumberOfActivePlanes,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4383
v->BytePerPixelY,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4384
v->BytePerPixelC,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4385
v->VRatio,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4386
v->VRatioChroma,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4387
v->SwathWidthYThisState,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4388
v->SwathWidthCThisState,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4389
v->NoOfDPPThisState,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4390
v->HRatio,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4391
v->HRatioChroma,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4392
v->PixelClock,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4393
v->PSCL_FACTOR,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4394
v->PSCL_FACTOR_CHROMA,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4395
v->RequiredDPPCLKThisState,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4396
v->ReadBandwidthLuma,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4397
v->ReadBandwidthChroma,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4398
v->ReturnBusWidth,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4399
&v->ProjectedDCFCLKDeepSleep[i][j]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4407
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4408
if (v->BlendingAndTiming[k] == k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4409
if (v->WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4410
v->WritebackDelayTime[k] = v->WritebackLatency
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4412
v->WritebackPixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4413
v->WritebackHRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4414
v->WritebackVRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4415
v->WritebackVTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4416
v->WritebackDestinationWidth[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4417
v->WritebackDestinationHeight[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4418
v->WritebackSourceHeight[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4419
v->HTotal[k]) / v->RequiredDISPCLK[i][j];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4421
v->WritebackDelayTime[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4423
for (m = 0; m <= v->NumberOfActivePlanes - 1; m++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4424
if (v->BlendingAndTiming[m] == k && v->WritebackEnable[m] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4425
v->WritebackDelayTime[k] = dml_max(
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4426
v->WritebackDelayTime[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4427
v->WritebackLatency
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4429
v->WritebackPixelFormat[m],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4430
v->WritebackHRatio[m],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4431
v->WritebackVRatio[m],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4432
v->WritebackVTaps[m],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4433
v->WritebackDestinationWidth[m],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4434
v->WritebackDestinationHeight[m],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4435
v->WritebackSourceHeight[m],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4436
v->HTotal[m]) / v->RequiredDISPCLK[i][j]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4441
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4442
for (m = 0; m <= v->NumberOfActivePlanes - 1; m++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4443
if (v->BlendingAndTiming[k] == m) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4444
v->WritebackDelayTime[k] = v->WritebackDelayTime[m];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4448
v->MaxMaxVStartup[i][j] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4449
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4450
v->MaximumVStartup[i][j][k] = v->VTotal[k] - v->VActive[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4451
- dml_max(1.0, dml_ceil(1.0 * v->WritebackDelayTime[k] / (v->HTotal[k] / v->PixelClock[k]), 1.0));
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4452
v->MaxMaxVStartup[i][j] = dml_max(v->MaxMaxVStartup[i][j], v->MaximumVStartup[i][j][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4457
ReorderingBytes = v->NumberOfChannels
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4459
v->UrgentOutOfOrderReturnPerChannelPixelDataOnly,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4460
v->UrgentOutOfOrderReturnPerChannelPixelMixedWithVMData,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4461
v->UrgentOutOfOrderReturnPerChannelVMDataOnly);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4462
v->FinalDRAMClockChangeLatency = (v->DRAMClockChangeLatencyOverride > 0 ? v->DRAMClockChangeLatencyOverride : v->DRAMClockChangeLatency);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4466
v->DCFCLKState[i][j] = v->DCFCLKPerState[i];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4470
if (v->UseMinimumRequiredDCFCLK == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4471
UseMinimumDCFCLK(mode_lib, v, MaxPrefetchMode, ReorderingBytes);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4473
if (v->ClampMinDCFCLK) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4477
if (v->DCFCLKState[i][j] < mode_lib->soc.min_dcfclk) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4478
v->DCFCLKState[i][j] = mode_lib->soc.min_dcfclk;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4487
v->IdealSDPPortBandwidthPerState[i][j] = dml_min3(
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4488
v->ReturnBusWidth * v->DCFCLKState[i][j],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4489
v->DRAMSpeedPerState[i] * v->NumberOfChannels * v->DRAMChannelWidth,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4490
v->FabricClockPerState[i] * v->FabricDatapathToDCNDataReturn);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4491
if (v->HostVMEnable != true) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4492
v->ReturnBWPerState[i][j] = v->IdealSDPPortBandwidthPerState[i][j] * v->PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelDataOnly
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4495
v->ReturnBWPerState[i][j] = v->IdealSDPPortBandwidthPerState[i][j]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4496
* v->PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData / 100;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4505
if ((v->ROBBufferSizeInKByte - v->PixelChunkSizeInKByte) * 1024 / v->ReturnBWPerState[i][j]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4506
> (v->RoundTripPingLatencyCycles + 32) / v->DCFCLKState[i][j] + ReorderingBytes / v->ReturnBWPerState[i][j]) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4507
v->ROBSupport[i][j] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4509
v->ROBSupport[i][j] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4517
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4518
MaxTotalVActiveRDBandwidth = MaxTotalVActiveRDBandwidth + v->ReadBandwidthLuma[k] + v->ReadBandwidthChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4523
v->MaxTotalVerticalActiveAvailableBandwidth[i][j] = dml_min(
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4524
v->IdealSDPPortBandwidthPerState[i][j] * v->MaxAveragePercentOfIdealSDPPortBWDisplayCanUseInNormalSystemOperation / 100,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4525
v->DRAMSpeedPerState[i] * v->NumberOfChannels * v->DRAMChannelWidth * v->MaxAveragePercentOfIdealDRAMBWDisplayCanUseInNormalSystemOperation
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4527
if (MaxTotalVActiveRDBandwidth <= v->MaxTotalVerticalActiveAvailableBandwidth[i][j]) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4528
v->TotalVerticalActiveBandwidthSupport[i][j] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4530
v->TotalVerticalActiveBandwidthSupport[i][j] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4541
v->TimeCalc = 24 / v->ProjectedDCFCLKDeepSleep[i][j];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4543
v->BandwidthWithoutPrefetchSupported[i][j] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4544
if (v->TotalVActivePixelBandwidth[i][j] + v->TotalVActiveCursorBandwidth[i][j] + v->TotalMetaRowBandwidth[i][j] + v->TotalDPTERowBandwidth[i][j]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4545
> v->ReturnBWPerState[i][j] || v->NotUrgentLatencyHiding[i][j]) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4546
v->BandwidthWithoutPrefetchSupported[i][j] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4549
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4550
v->NoOfDPPThisState[k] = v->NoOfDPP[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4551
v->swath_width_luma_ub_this_state[k] = v->swath_width_luma_ub_all_states[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4552
v->swath_width_chroma_ub_this_state[k] = v->swath_width_chroma_ub_all_states[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4553
v->SwathWidthYThisState[k] = v->SwathWidthYAllStates[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4554
v->SwathWidthCThisState[k] = v->SwathWidthCAllStates[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4555
v->SwathHeightYThisState[k] = v->SwathHeightYAllStates[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4556
v->SwathHeightCThisState[k] = v->SwathHeightCAllStates[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4557
v->DETBufferSizeYThisState[k] = v->DETBufferSizeYAllStates[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4558
v->DETBufferSizeCThisState[k] = v->DETBufferSizeCAllStates[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4559
v->ODMCombineEnabled[k] = v->ODMCombineEnablePerState[i][k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4562
v->ExtraLatency = CalculateExtraLatency(
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4563
v->RoundTripPingLatencyCycles,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4565
v->DCFCLKState[i][j],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4566
v->TotalNumberOfActiveDPP[i][j],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4567
v->PixelChunkSizeInKByte,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4568
v->TotalNumberOfDCCActiveDPP[i][j],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4569
v->MetaChunkSize,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4570
v->ReturnBWPerState[i][j],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4571
v->GPUVMEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4572
v->HostVMEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4573
v->NumberOfActivePlanes,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4574
v->NoOfDPPThisState,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4575
v->dpte_group_bytes,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4576
v->PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4577
v->PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4578
v->HostVMMinPageSize,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4579
v->HostVMMaxNonCachedPageTableLevels);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4581
v->NextMaxVStartup = v->MaxMaxVStartup[i][j];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4583
v->PrefetchModePerState[i][j] = NextPrefetchModeState;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4584
v->MaxVStartup = v->NextMaxVStartup;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4586
v->TWait = CalculateTWait(v->PrefetchModePerState[i][j], v->FinalDRAMClockChangeLatency, v->UrgLatency[i], v->SREnterPlusExitTime);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4588
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4591
myPipe.DPPCLK = v->RequiredDPPCLK[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4592
myPipe.DISPCLK = v->RequiredDISPCLK[i][j];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4593
myPipe.PixelClock = v->PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4594
myPipe.DCFCLKDeepSleep = v->ProjectedDCFCLKDeepSleep[i][j];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4595
myPipe.DPPPerPlane = v->NoOfDPP[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4596
myPipe.ScalerEnabled = v->ScalerEnabled[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4597
myPipe.SourceScan = v->SourceScan[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4598
myPipe.BlockWidth256BytesY = v->Read256BlockWidthY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4599
myPipe.BlockHeight256BytesY = v->Read256BlockHeightY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4600
myPipe.BlockWidth256BytesC = v->Read256BlockWidthC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4601
myPipe.BlockHeight256BytesC = v->Read256BlockHeightC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4602
myPipe.InterlaceEnable = v->Interlace[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4603
myPipe.NumberOfCursors = v->NumberOfCursors[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4604
myPipe.VBlank = v->VTotal[k] - v->VActive[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4605
myPipe.HTotal = v->HTotal[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4606
myPipe.DCCEnable = v->DCCEnable[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4607
myPipe.ODMCombineEnabled = !!v->ODMCombineEnabled[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4609
v->NoTimeForPrefetch[i][j][k] = CalculatePrefetchSchedule(
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4613
v->DSCDelayPerState[i][k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4614
v->SwathWidthYThisState[k] / v->HRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4615
dml_min(v->MaxVStartup, v->MaximumVStartup[i][j][k]),
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4616
v->MaximumVStartup[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4617
v->UrgLatency[i],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4618
v->ExtraLatency,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4619
v->TimeCalc,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4620
v->PDEAndMetaPTEBytesPerFrame[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4621
v->MetaRowBytes[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4622
v->DPTEBytesPerRow[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4623
v->PrefetchLinesY[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4624
v->SwathWidthYThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4625
v->BytePerPixelY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4626
v->PrefillY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4627
v->MaxNumSwY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4628
v->PrefetchLinesC[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4629
v->SwathWidthCThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4630
v->PrefillC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4631
v->MaxNumSwC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4632
v->swath_width_luma_ub_this_state[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4633
v->swath_width_chroma_ub_this_state[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4634
v->SwathHeightYThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4635
v->SwathHeightCThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4636
v->TWait,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4637
&v->LineTimesForPrefetch[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4638
&v->PrefetchBW[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4639
&v->LinesForMetaPTE[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4640
&v->LinesForMetaAndDPTERow[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4641
&v->VRatioPreY[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4642
&v->VRatioPreC[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4643
&v->RequiredPrefetchPixelDataBWLuma[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4644
&v->RequiredPrefetchPixelDataBWChroma[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4645
&v->NoTimeForDynamicMetadata[i][j][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4648
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4650
v->swath_width_luma_ub_this_state[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4651
v->swath_width_chroma_ub_this_state[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4652
v->DETBufferSizeInKByte[0],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4653
v->SwathHeightYThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4654
v->SwathHeightCThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4655
v->HTotal[k] / v->PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4656
v->UrgLatency[i],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4657
v->CursorBufferSize,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4658
v->CursorWidth[k][0],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4659
v->CursorBPP[k][0],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4660
v->VRatioPreY[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4661
v->VRatioPreC[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4662
v->BytePerPixelInDETY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4663
v->BytePerPixelInDETC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4664
v->DETBufferSizeYThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4665
v->DETBufferSizeCThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4666
&v->UrgentBurstFactorCursorPre[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4667
&v->UrgentBurstFactorLumaPre[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4668
&v->UrgentBurstFactorChromaPre[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4669
&v->NoUrgentLatencyHidingPre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4672
v->MaximumReadBandwidthWithPrefetch = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4673
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4674
v->cursor_bw_pre[k] = v->NumberOfCursors[k] * v->CursorWidth[k][0] * v->CursorBPP[k][0] / 8.0 / (v->HTotal[k] / v->PixelClock[k])
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4675
* v->VRatioPreY[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4677
v->MaximumReadBandwidthWithPrefetch = v->MaximumReadBandwidthWithPrefetch
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4679
v->VActivePixelBandwidth[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4680
v->VActiveCursorBandwidth[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4681
+ v->NoOfDPP[i][j][k] * (v->meta_row_bandwidth[i][j][k] + v->dpte_row_bandwidth[i][j][k]),
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4682
v->NoOfDPP[i][j][k] * v->prefetch_vmrow_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4683
v->NoOfDPP[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4684
* (v->RequiredPrefetchPixelDataBWLuma[i][j][k] * v->UrgentBurstFactorLumaPre[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4685
+ v->RequiredPrefetchPixelDataBWChroma[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4686
* v->UrgentBurstFactorChromaPre[k])
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4687
+ v->cursor_bw_pre[k] * v->UrgentBurstFactorCursorPre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4690
v->NotEnoughUrgentLatencyHidingPre = false;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4691
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4692
if (v->NoUrgentLatencyHidingPre[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4693
v->NotEnoughUrgentLatencyHidingPre = true;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4697
v->PrefetchSupported[i][j] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4698
if (v->BandwidthWithoutPrefetchSupported[i][j] == false || v->MaximumReadBandwidthWithPrefetch > v->ReturnBWPerState[i][j]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4699
|| v->NotEnoughUrgentLatencyHidingPre == 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4700
v->PrefetchSupported[i][j] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4702
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4703
if (v->LineTimesForPrefetch[k] < 2.0 || v->LinesForMetaPTE[k] >= 32.0 || v->LinesForMetaAndDPTERow[k] >= 16.0
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4704
|| v->NoTimeForPrefetch[i][j][k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4705
v->PrefetchSupported[i][j] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4709
v->DynamicMetadataSupported[i][j] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4710
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4711
if (v->NoTimeForDynamicMetadata[i][j][k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4712
v->DynamicMetadataSupported[i][j] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4716
v->VRatioInPrefetchSupported[i][j] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4717
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4718
if (v->VRatioPreY[i][j][k] > 4.0 || v->VRatioPreC[i][j][k] > 4.0 || v->NoTimeForPrefetch[i][j][k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4719
v->VRatioInPrefetchSupported[i][j] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4722
v->AnyLinesForVMOrRowTooLarge = false;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4723
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4724
if (v->LinesForMetaAndDPTERow[k] >= 16 || v->LinesForMetaPTE[k] >= 32) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4725
v->AnyLinesForVMOrRowTooLarge = true;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4729
if (v->PrefetchSupported[i][j] == true && v->VRatioInPrefetchSupported[i][j] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4730
v->BandwidthAvailableForImmediateFlip = v->ReturnBWPerState[i][j];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4731
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4732
v->BandwidthAvailableForImmediateFlip = v->BandwidthAvailableForImmediateFlip
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4734
v->VActivePixelBandwidth[i][j][k] + v->VActiveCursorBandwidth[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4735
v->NoOfDPP[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4736
* (v->RequiredPrefetchPixelDataBWLuma[i][j][k] * v->UrgentBurstFactorLumaPre[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4737
+ v->RequiredPrefetchPixelDataBWChroma[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4738
* v->UrgentBurstFactorChromaPre[k])
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4739
+ v->cursor_bw_pre[k] * v->UrgentBurstFactorCursorPre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4741
v->TotImmediateFlipBytes = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4742
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4743
v->TotImmediateFlipBytes = v->TotImmediateFlipBytes + v->NoOfDPP[i][j][k] * (v->PDEAndMetaPTEBytesPerFrame[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4744
+ v->MetaRowBytes[i][j][k] + v->DPTEBytesPerRow[i][j][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4747
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4750
v->PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4751
v->PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4752
v->ExtraLatency,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4753
v->UrgLatency[i],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4754
v->GPUVMMaxPageTableLevels,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4755
v->HostVMEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4756
v->HostVMMaxNonCachedPageTableLevels,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4757
v->GPUVMEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4758
v->HostVMMinPageSize,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4759
v->PDEAndMetaPTEBytesPerFrame[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4760
v->MetaRowBytes[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4761
v->DPTEBytesPerRow[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4762
v->BandwidthAvailableForImmediateFlip,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4763
v->TotImmediateFlipBytes,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4764
v->SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4765
v->HTotal[k] / v->PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4766
v->VRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4767
v->VRatioChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4768
v->Tno_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4769
v->DCCEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4770
v->dpte_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4771
v->meta_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4772
v->dpte_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4773
v->meta_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4774
&v->DestinationLinesToRequestVMInImmediateFlip[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4775
&v->DestinationLinesToRequestRowInImmediateFlip[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4776
&v->final_flip_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4777
&v->ImmediateFlipSupportedForPipe[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4779
v->total_dcn_read_bw_with_flip = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4780
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4781
v->total_dcn_read_bw_with_flip = v->total_dcn_read_bw_with_flip
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4783
v->NoOfDPP[i][j][k] * v->prefetch_vmrow_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4784
v->NoOfDPP[i][j][k] * v->final_flip_bw[k] + v->VActivePixelBandwidth[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4785
+ v->VActiveCursorBandwidth[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4786
v->NoOfDPP[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4787
* (v->final_flip_bw[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4788
+ v->RequiredPrefetchPixelDataBWLuma[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4789
* v->UrgentBurstFactorLumaPre[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4790
+ v->RequiredPrefetchPixelDataBWChroma[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4791
* v->UrgentBurstFactorChromaPre[k])
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4792
+ v->cursor_bw_pre[k] * v->UrgentBurstFactorCursorPre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4794
v->ImmediateFlipSupportedForState[i][j] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4795
if (v->total_dcn_read_bw_with_flip > v->ReturnBWPerState[i][j]) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4796
v->ImmediateFlipSupportedForState[i][j] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4798
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4799
if (v->ImmediateFlipSupportedForPipe[k] == false) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4800
v->ImmediateFlipSupportedForState[i][j] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4804
v->ImmediateFlipSupportedForState[i][j] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4806
if (v->MaxVStartup <= 13 || v->AnyLinesForVMOrRowTooLarge == false) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4807
v->NextMaxVStartup = v->MaxMaxVStartup[i][j];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4810
v->NextMaxVStartup = v->NextMaxVStartup - 1;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4812
} while (!((v->PrefetchSupported[i][j] == true && v->DynamicMetadataSupported[i][j] == true && v->VRatioInPrefetchSupported[i][j] == true
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4813
&& ((v->HostVMEnable == false && v->ImmediateFlipRequirement[0] != dm_immediate_flip_required)
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4814
|| v->ImmediateFlipSupportedForState[i][j] == true))
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4815
|| (v->NextMaxVStartup == v->MaxMaxVStartup[i][j] && NextPrefetchModeState > MaxPrefetchMode)));
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4819
v->PrefetchModePerState[i][j],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4820
v->DCFCLKState[i][j],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4821
v->ReturnBWPerState[i][j],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4822
v->UrgLatency[i],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4823
v->ExtraLatency,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4824
v->SOCCLKPerState[i],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4825
v->ProjectedDCFCLKDeepSleep[i][j],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4826
v->NoOfDPPThisState,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4827
v->RequiredDPPCLKThisState,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4828
v->DETBufferSizeYThisState,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4829
v->DETBufferSizeCThisState,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4830
v->SwathHeightYThisState,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4831
v->SwathHeightCThisState,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4832
v->SwathWidthYThisState,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4833
v->SwathWidthCThisState,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4834
v->BytePerPixelInDETY,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4835
v->BytePerPixelInDETC,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4836
&v->DRAMClockChangeSupport[i][j]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4842
for (i = start_state; i < v->soc.num_states; i++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4844
v->PTEBufferSizeNotExceeded[i][j] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4845
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4846
if (v->PTEBufferSizeNotExceededY[i][j][k] == false || v->PTEBufferSizeNotExceededC[i][j][k] == false) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4847
v->PTEBufferSizeNotExceeded[i][j] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4854
v->CursorSupport = true;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4855
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4856
if (v->CursorWidth[k][0] > 0.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4857
if (v->CursorBPP[k][0] == 64 && v->Cursor64BppSupport == false) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4858
v->CursorSupport = false;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4864
v->PitchSupport = true;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4865
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4866
v->AlignedYPitch[k] = dml_ceil(dml_max(v->PitchY[k], v->SurfaceWidthY[k]), v->MacroTileWidthY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4867
if (v->DCCEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4868
v->AlignedDCCMetaPitchY[k] = dml_ceil(dml_max(v->DCCMetaPitchY[k], v->SurfaceWidthY[k]), 64.0 * v->Read256BlockWidthY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4870
v->AlignedDCCMetaPitchY[k] = v->DCCMetaPitchY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4872
if (v->SourcePixelFormat[k] != dm_444_64 && v->SourcePixelFormat[k] != dm_444_32 && v->SourcePixelFormat[k] != dm_444_16 && v->SourcePixelFormat[k] != dm_mono_16
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4873
&& v->SourcePixelFormat[k] != dm_rgbe && v->SourcePixelFormat[k] != dm_mono_8) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4874
v->AlignedCPitch[k] = dml_ceil(dml_max(v->PitchC[k], v->SurfaceWidthC[k]), v->MacroTileWidthC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4875
if (v->DCCEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4876
v->AlignedDCCMetaPitchC[k] = dml_ceil(dml_max(v->DCCMetaPitchC[k], v->SurfaceWidthC[k]), 64.0 * v->Read256BlockWidthC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4878
v->AlignedDCCMetaPitchC[k] = v->DCCMetaPitchC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4881
v->AlignedCPitch[k] = v->PitchC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4882
v->AlignedDCCMetaPitchC[k] = v->DCCMetaPitchC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4884
if (v->AlignedYPitch[k] > v->PitchY[k] || v->AlignedCPitch[k] > v->PitchC[k] || v->AlignedDCCMetaPitchY[k] > v->DCCMetaPitchY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4885
|| v->AlignedDCCMetaPitchC[k] > v->DCCMetaPitchC[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4886
v->PitchSupport = false;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4890
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4891
if (v->ViewportWidth[k] > v->SurfaceWidthY[k] || v->ViewportHeight[k] > v->SurfaceHeightY[k])
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4894
if (v->SourcePixelFormat[k] != dm_444_64 && v->SourcePixelFormat[k] != dm_444_32 && v->SourcePixelFormat[k] != dm_444_16
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4895
&& v->SourcePixelFormat[k] != dm_444_8 && v->SourcePixelFormat[k] != dm_rgbe) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4896
if (v->ViewportWidthChroma[k] > v->SurfaceWidthC[k] || v->ViewportHeightChroma[k] > v->SurfaceHeightC[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4903
for (i = v->soc.num_states - 1; i >= start_state; i--) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4905
if (v->ScaleRatioAndTapsSupport == 1 && v->SourceFormatPixelAndScanSupport == 1 && v->ViewportSizeSupport[i][j] == 1
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4906
&& v->DIOSupport[i] == 1 && v->ODMCombine4To1SupportCheckOK[i] == 1
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4907
&& v->NotEnoughDSCUnits[i] == 0
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4908
&& v->DTBCLKRequiredMoreThanSupported[i] == 0
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4909
&& v->ROBSupport[i][j] == 1 && v->DISPCLK_DPPCLK_Support[i][j] == 1 && v->TotalAvailablePipesSupport[i][j] == 1
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4911
&& v->WritebackLatencySupport == 1 && v->WritebackScaleRatioAndTapsSupport == 1 && v->CursorSupport == 1 && v->PitchSupport == 1
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4912
&& ViewportExceedsSurface == 0 && v->PrefetchSupported[i][j] == 1 && v->DynamicMetadataSupported[i][j] == 1
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4913
&& v->TotalVerticalActiveBandwidthSupport[i][j] == 1 && v->VRatioInPrefetchSupported[i][j] == 1
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4914
&& v->PTEBufferSizeNotExceeded[i][j] == 1 && v->NonsupportedDSCInputBPC == 0
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4915
&& ((v->HostVMEnable == 0 && v->ImmediateFlipRequirement[0] != dm_immediate_flip_required)
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4916
|| v->ImmediateFlipSupportedForState[i][j] == true)) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4917
v->ModeSupport[i][j] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4919
v->ModeSupport[i][j] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4925
for (i = v->soc.num_states; i >= start_state; i--) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4926
if (i == v->soc.num_states || v->ModeSupport[i][0] == true || v->ModeSupport[i][1] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4927
v->VoltageLevel = i;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4928
v->ModeIsSupported = v->ModeSupport[i][0] == true || v->ModeSupport[i][1] == true;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4929
if (v->ModeSupport[i][1] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4936
v->ImmediateFlipSupport = v->ImmediateFlipSupportedForState[v->VoltageLevel][MaximumMPCCombine];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4937
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4938
v->MPCCombineEnable[k] = v->MPCCombine[v->VoltageLevel][MaximumMPCCombine][k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4939
v->DPPPerPlane[k] = v->NoOfDPP[v->VoltageLevel][MaximumMPCCombine][k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4941
v->DCFCLK = v->DCFCLKState[v->VoltageLevel][MaximumMPCCombine];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4942
v->DRAMSpeed = v->DRAMSpeedPerState[v->VoltageLevel];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4943
v->FabricClock = v->FabricClockPerState[v->VoltageLevel];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4944
v->SOCCLK = v->SOCCLKPerState[v->VoltageLevel];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4945
v->ReturnBW = v->ReturnBWPerState[v->VoltageLevel][MaximumMPCCombine];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4946
v->maxMpcComb = MaximumMPCCombine;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4971
struct vba_vars_st *v = &mode_lib->vba;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4990
v->TotalActiveDPP = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4991
v->TotalDCCActiveDPP = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4992
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4993
v->TotalActiveDPP = v->TotalActiveDPP + DPPPerPlane[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4994
if (v->DCCEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4995
v->TotalDCCActiveDPP = v->TotalDCCActiveDPP + DPPPerPlane[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
4999
v->UrgentWatermark = UrgentLatency + ExtraLatency;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5001
v->DRAMClockChangeWatermark = v->FinalDRAMClockChangeLatency + v->UrgentWatermark;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5003
v->TotalActiveWriteback = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5004
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5005
if (v->WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5006
v->TotalActiveWriteback = v->TotalActiveWriteback + 1;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5010
if (v->TotalActiveWriteback <= 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5011
v->WritebackUrgentWatermark = v->WritebackLatency;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5013
v->WritebackUrgentWatermark = v->WritebackLatency + v->WritebackChunkSize * 1024.0 / 32.0 / SOCCLK;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5016
if (v->TotalActiveWriteback <= 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5017
v->WritebackDRAMClockChangeWatermark = v->FinalDRAMClockChangeLatency + v->WritebackLatency;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5019
v->WritebackDRAMClockChangeWatermark = v->FinalDRAMClockChangeLatency + v->WritebackLatency + v->WritebackChunkSize * 1024.0 / 32.0 / SOCCLK;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5022
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5024
v->LBLatencyHidingSourceLinesY = dml_min((double) v->MaxLineBufferLines, dml_floor(v->LineBufferSize / v->LBBitPerPixel[k] / (SwathWidthY[k] / dml_max(v->HRatio[k], 1.0)), 1)) - (v->vtaps[k] - 1);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5026
v->LBLatencyHidingSourceLinesC = dml_min((double) v->MaxLineBufferLines, dml_floor(v->LineBufferSize / v->LBBitPerPixel[k] / (SwathWidthC[k] / dml_max(v->HRatioChroma[k], 1.0)), 1)) - (v->VTAPsChroma[k] - 1);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5028
EffectiveLBLatencyHidingY = v->LBLatencyHidingSourceLinesY / v->VRatio[k] * (v->HTotal[k] / v->PixelClock[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5030
EffectiveLBLatencyHidingC = v->LBLatencyHidingSourceLinesC / v->VRatioChroma[k] * (v->HTotal[k] / v->PixelClock[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5034
FullDETBufferingTimeY[k] = LinesInDETYRoundedDownToSwath[k] * (v->HTotal[k] / v->PixelClock[k]) / v->VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5036
LinesInDETC = v->DETBufferSizeC[k] / BytePerPixelDETC[k] / SwathWidthC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5038
FullDETBufferingTimeC = LinesInDETCRoundedDownToSwath * (v->HTotal[k] / v->PixelClock[k]) / v->VRatioChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5044
ActiveDRAMClockChangeLatencyMarginY = EffectiveLBLatencyHidingY + FullDETBufferingTimeY[k] - v->UrgentWatermark - (v->HTotal[k] / v->PixelClock[k]) * (v->DSTXAfterScaler[k] / v->HTotal[k] + v->DSTYAfterScaler[k]) - v->DRAMClockChangeWatermark;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5046
if (v->NumberOfActivePlanes > 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5047
ActiveDRAMClockChangeLatencyMarginY = ActiveDRAMClockChangeLatencyMarginY - (1 - 1.0 / v->NumberOfActivePlanes) * SwathHeightY[k] * v->HTotal[k] / v->PixelClock[k] / v->VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5051
ActiveDRAMClockChangeLatencyMarginC = EffectiveLBLatencyHidingC + FullDETBufferingTimeC - v->UrgentWatermark - (v->HTotal[k] / v->PixelClock[k]) * (v->DSTXAfterScaler[k] / v->HTotal[k] + v->DSTYAfterScaler[k]) - v->DRAMClockChangeWatermark;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5053
if (v->NumberOfActivePlanes > 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5054
ActiveDRAMClockChangeLatencyMarginC = ActiveDRAMClockChangeLatencyMarginC - (1 - 1.0 / v->NumberOfActivePlanes) * SwathHeightC[k] * v->HTotal[k] / v->PixelClock[k] / v->VRatioChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5056
v->ActiveDRAMClockChangeLatencyMargin[k] = dml_min(ActiveDRAMClockChangeLatencyMarginY, ActiveDRAMClockChangeLatencyMarginC);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5058
v->ActiveDRAMClockChangeLatencyMargin[k] = ActiveDRAMClockChangeLatencyMarginY;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5061
if (v->WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5063
WritebackDRAMClockChangeLatencyHiding = v->WritebackInterfaceBufferSize * 1024 / (v->WritebackDestinationWidth[k] * v->WritebackDestinationHeight[k] / (v->WritebackSourceHeight[k] * v->HTotal[k] / v->PixelClock[k]) * 4);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5064
if (v->WritebackPixelFormat[k] == dm_444_64) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5067
if (v->WritebackConfiguration == dm_whole_buffer_for_single_stream_interleave) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5070
WritebackDRAMClockChangeLatencyMargin = WritebackDRAMClockChangeLatencyHiding - v->WritebackDRAMClockChangeWatermark;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5071
v->ActiveDRAMClockChangeLatencyMargin[k] = dml_min(v->ActiveDRAMClockChangeLatencyMargin[k], WritebackDRAMClockChangeLatencyMargin);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5075
v->MinActiveDRAMClockChangeMargin = 999999;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5077
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5078
if (v->ActiveDRAMClockChangeLatencyMargin[k] < v->MinActiveDRAMClockChangeMargin) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5079
v->MinActiveDRAMClockChangeMargin = v->ActiveDRAMClockChangeLatencyMargin[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5080
if (v->BlendingAndTiming[k] == k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5083
for (j = 0; j < v->NumberOfActivePlanes; ++j) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5084
if (v->BlendingAndTiming[k] == j) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5092
v->MinActiveDRAMClockChangeLatencySupported = v->MinActiveDRAMClockChangeMargin + v->FinalDRAMClockChangeLatency;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5095
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5096
if (!((k == PlaneWithMinActiveDRAMClockChangeMargin) && (v->BlendingAndTiming[k] == k)) && !(v->BlendingAndTiming[k] == PlaneWithMinActiveDRAMClockChangeMargin) && v->ActiveDRAMClockChangeLatencyMargin[k] < SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5097
SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank = v->ActiveDRAMClockChangeLatencyMargin[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5101
v->TotalNumberOfActiveOTG = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5102
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5103
if (v->BlendingAndTiming[k] == k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5104
v->TotalNumberOfActiveOTG = v->TotalNumberOfActiveOTG + 1;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5108
if (v->MinActiveDRAMClockChangeMargin > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5110
} else if (((v->SynchronizedVBlank == true || v->TotalNumberOfActiveOTG == 1 || SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank > 0) && PrefetchMode == 0)) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5117
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5120
TimeToFinishSwathTransferStutterCriticalPlane = (SwathHeightY[k] - (LinesInDETY[k] - LinesInDETYRoundedDownToSwath[k])) * (v->HTotal[k] / v->PixelClock[k]) / v->VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5124
v->StutterExitWatermark = v->SRExitTime + ExtraLatency + 10 / DCFCLKDeepSleep;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
5125
v->StutterEnterPlusExitWatermark = dml_max(v->SREnterPlusExitTime + ExtraLatency + 10 / DCFCLKDeepSleep, TimeToFinishSwathTransferStutterCriticalPlane);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6223
struct vba_vars_st *v,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6232
NormalEfficiency = (v->HostVMEnable == true ? v->PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6233
: v->PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelDataOnly) / 100.0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6234
PTEEfficiency = (v->HostVMEnable == true ? v->PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6235
/ v->PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData : 1.0);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6253
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6255
+ v->NoOfDPP[i][j][k] * v->DPTEBytesPerRow[i][j][k] / (15.75 * v->HTotal[k] / v->PixelClock[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6258
for (k = 0; k <= v->NumberOfActivePlanes - 1; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6259
NoOfDPPState[k] = v->NoOfDPP[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6262
MinimumTWait = CalculateTWait(MaxPrefetchMode, v->FinalDRAMClockChangeLatency, v->UrgLatency[i], v->SREnterPlusExitTime);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6263
NonDPTEBandwidth = v->TotalVActivePixelBandwidth[i][j] + v->TotalVActiveCursorBandwidth[i][j] + v->TotalMetaRowBandwidth[i][j];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6264
DPTEBandwidth = (v->HostVMEnable == true || v->ImmediateFlipRequirement[0] == dm_immediate_flip_required) ?
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6265
TotalMaxPrefetchFlipDPTERowBandwidth[i][j] : v->TotalDPTERowBandwidth[i][j];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6266
DCFCLKRequiredForAverageBandwidth = dml_max3(v->ProjectedDCFCLKDeepSleep[i][j],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6267
(NonDPTEBandwidth + v->TotalDPTERowBandwidth[i][j]) / v->ReturnBusWidth / (v->MaxAveragePercentOfIdealSDPPortBWDisplayCanUseInNormalSystemOperation / 100),
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6268
(NonDPTEBandwidth + DPTEBandwidth / PTEEfficiency) / NormalEfficiency / v->ReturnBusWidth);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6270
ExtraLatencyBytes = CalculateExtraLatencyBytes(ReorderingBytes, v->TotalNumberOfActiveDPP[i][j], v->PixelChunkSizeInKByte, v->TotalNumberOfDCCActiveDPP[i][j],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6271
v->MetaChunkSize, v->GPUVMEnable, v->HostVMEnable, v->NumberOfActivePlanes, NoOfDPPState, v->dpte_group_bytes,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6272
v->PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData, v->PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6273
v->HostVMMinPageSize, v->HostVMMaxNonCachedPageTableLevels);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6274
ExtraLatencyCycles = v->RoundTripPingLatencyCycles + 32 + ExtraLatencyBytes / NormalEfficiency / v->ReturnBusWidth;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6275
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6280
PixelDCFCLKCyclesRequiredInPrefetch[k] = (v->PrefetchLinesY[i][j][k] * v->swath_width_luma_ub_all_states[i][j][k] * v->BytePerPixelY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6281
+ v->PrefetchLinesC[i][j][k] * v->swath_width_chroma_ub_all_states[i][j][k] * v->BytePerPixelC[k]) / NormalEfficiency / v->ReturnBusWidth;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6282
DCFCLKCyclesRequiredInPrefetch = 2 * ExtraLatencyCycles / NoOfDPPState[k] + v->PDEAndMetaPTEBytesPerFrame[i][j][k] / PTEEfficiency
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6283
/ NormalEfficiency / v->ReturnBusWidth * (v->GPUVMMaxPageTableLevels > 2 ? 1 : 0) + 2 * v->DPTEBytesPerRow[i][j][k] / PTEEfficiency
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6284
/ NormalEfficiency / v->ReturnBusWidth + 2 * v->MetaRowBytes[i][j][k] / NormalEfficiency / v->ReturnBusWidth + PixelDCFCLKCyclesRequiredInPrefetch[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6285
PrefetchPixelLinesTime[k] = dml_max(v->PrefetchLinesY[i][j][k], v->PrefetchLinesC[i][j][k]) * v->HTotal[k] / v->PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6286
ExpectedPrefetchBWAcceleration = (v->VActivePixelBandwidth[i][j][k] + v->VActiveCursorBandwidth[i][j][k]) / (v->ReadBandwidthLuma[k] + v->ReadBandwidthChroma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6287
DynamicMetadataVMExtraLatency[k] = (v->GPUVMEnable == true && v->DynamicMetadataEnable[k] == true && v->DynamicMetadataVMEnabled == true) ?
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6288
v->UrgLatency[i] * v->GPUVMMaxPageTableLevels * (v->HostVMEnable == true ? v->HostVMMaxNonCachedPageTableLevels + 1 : 1) : 0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6289
PrefetchTime = (v->MaximumVStartup[i][j][k] - 1) * v->HTotal[k] / v->PixelClock[k] - MinimumTWait - v->UrgLatency[i] * ((v->GPUVMMaxPageTableLevels <= 2 ? v->GPUVMMaxPageTableLevels
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6290
: v->GPUVMMaxPageTableLevels - 2) * (v->HostVMEnable == true ? v->HostVMMaxNonCachedPageTableLevels + 1 : 1) - 1) - DynamicMetadataVMExtraLatency[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6297
if (v->HostVMEnable == true || v->ImmediateFlipRequirement[0] == dm_immediate_flip_required) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6299
+ NoOfDPPState[k] * DPTEBandwidth / PTEEfficiency / NormalEfficiency / v->ReturnBusWidth;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6302
DCFCLKRequiredForPeakBandwidthPerPlane[k] = v->DCFCLKPerState[i];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6304
if (v->DynamicMetadataEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6312
v->MaxInterDCNTileRepeaters,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6313
v->RequiredDPPCLK[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6314
v->RequiredDISPCLK[i][j],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6315
v->ProjectedDCFCLKDeepSleep[i][j],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6316
v->PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6317
v->HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6318
v->VTotal[k] - v->VActive[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6319
v->DynamicMetadataTransmittedBytes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6320
v->DynamicMetadataLinesBeforeActiveRequired[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6321
v->Interlace[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6322
v->ProgressiveToInterlaceUnitInOPP,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6327
AllowedTimeForUrgentExtraLatency = v->MaximumVStartup[i][j][k] * v->HTotal[k] / v->PixelClock[k] - MinimumTWait - TsetupPipe
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6333
DCFCLKRequiredForPeakBandwidthPerPlane[k] = v->DCFCLKPerState[i];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6338
for (k = 0; k <= v->NumberOfActivePlanes - 1; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6341
MinimumTvmPlus2Tr0 = v->UrgLatency[i] * (v->GPUVMEnable == true ? (v->HostVMEnable == true ?
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6342
(v->GPUVMMaxPageTableLevels + 2) * (v->HostVMMaxNonCachedPageTableLevels + 1) - 1 : v->GPUVMMaxPageTableLevels + 1) : 0);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6343
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6345
MaximumTvmPlus2Tr0PlusTsw = (v->MaximumVStartup[i][j][k] - 2) * v->HTotal[k] / v->PixelClock[k] - MinimumTWait - DynamicMetadataVMExtraLatency[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6347
DCFCLKRequiredForPeakBandwidth = v->DCFCLKPerState[i];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
6354
v->DCFCLKState[i][j] = dml_min(v->DCFCLKPerState[i], 1.05 * (1 + mode_lib->vba.PercentMarginOverMinimumRequiredDCFCLK / 100)
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
781
struct vba_vars_st *v = &mode_lib->vba;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
782
double DPPCLKDelaySubtotalPlusCNVCFormater = v->DPPCLKDelaySubtotal + v->DPPCLKDelayCNVCFormater;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
814
if (v->GPUVMEnable == true && v->HostVMEnable == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
815
HostVMInefficiencyFactor = v->PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData / v->PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
816
HostVMDynamicLevelsTrips = v->HostVMMaxNonCachedPageTableLevels;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
823
v->MaxInterDCNTileRepeaters,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
830
v->DynamicMetadataTransmittedBytes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
831
v->DynamicMetadataLinesBeforeActiveRequired[k],
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
833
v->ProgressiveToInterlaceUnitInOPP,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
841
Tvm_trips = UrgentExtraLatency + trip_to_mem * (v->GPUVMMaxPageTableLevels * (HostVMDynamicLevelsTrips + 1) - 1);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
843
if (v->DynamicMetadataVMEnabled == true && v->GPUVMEnable == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
844
v->Tdmdl[k] = TWait + Tvm_trips + trip_to_mem;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
846
v->Tdmdl[k] = TWait + UrgentExtraLatency;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
849
if (v->DynamicMetadataEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
850
if (VStartup * LineTime < Tsetup + v->Tdmdl[k] + Tdmbf + Tdmec + Tdmsks) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
858
dml_print("DML: Tdmdl: %fus - time for fabric to become ready and fetch dmd \n", v->Tdmdl[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
864
v->Tdmdl_vm[k] = (v->DynamicMetadataEnable[k] == true && v->DynamicMetadataVMEnabled == true && v->GPUVMEnable == true ? TWait + Tvm_trips : 0);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
867
DPPCycles = DPPCLKDelaySubtotalPlusCNVCFormater + v->DPPCLKDelaySCL;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
869
DPPCycles = DPPCLKDelaySubtotalPlusCNVCFormater + v->DPPCLKDelaySCLLBOnly;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
871
DPPCycles = DPPCycles + myPipe->NumberOfCursors * v->DPPCLKDelayCNVCCursor;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
873
DISPCLKCycles = v->DISPCLKDelaySubtotal;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
878
v->DSTXAfterScaler[k] = DPPCycles * myPipe->PixelClock / myPipe->DPPCLK + DISPCLKCycles * myPipe->PixelClock / myPipe->DISPCLK
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
881
v->DSTXAfterScaler[k] = v->DSTXAfterScaler[k] + ((myPipe->ODMCombineEnabled)?18:0) + (myPipe->DPPPerPlane - 1) * DPP_RECOUT_WIDTH;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
883
if (v->OutputFormat[k] == dm_420 || (myPipe->InterlaceEnable && v->ProgressiveToInterlaceUnitInOPP))
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
884
v->DSTYAfterScaler[k] = 1;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
886
v->DSTYAfterScaler[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
888
DSTTotalPixelsAfterScaler = v->DSTYAfterScaler[k] * myPipe->HTotal + v->DSTXAfterScaler[k];
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
889
v->DSTYAfterScaler[k] = dml_floor(DSTTotalPixelsAfterScaler / myPipe->HTotal, 1);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
890
v->DSTXAfterScaler[k] = DSTTotalPixelsAfterScaler - ((double) (v->DSTYAfterScaler[k] * myPipe->HTotal));
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
899
if (v->GPUVMEnable) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
900
if (v->GPUVMMaxPageTableLevels >= 3) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
901
v->Tno_bw[k] = UrgentExtraLatency + trip_to_mem * ((v->GPUVMMaxPageTableLevels - 2) - 1);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
903
v->Tno_bw[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
905
v->Tno_bw[k] = LineTime;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
907
v->Tno_bw[k] = LineTime / 4;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
909
dst_y_prefetch_equ = VStartup - (Tsetup + dml_max(TWait + TCalc, v->Tdmdl[k])) / LineTime
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
910
- (v->DSTYAfterScaler[k] + v->DSTXAfterScaler[k] / myPipe->HTotal);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
916
prefetch_bw_oto = (PrefetchSourceLinesY * swath_width_luma_ub * BytePerPixelY + PrefetchSourceLinesC * swath_width_chroma_ub * v->BytePerPixelC[k]) / Tsw_oto;
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
918
if (v->GPUVMEnable == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
919
Tvm_oto = dml_max3(v->Tno_bw[k] + PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / prefetch_bw_oto,
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
925
if ((v->GPUVMEnable == true || myPipe->DCCEnable == true)) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
951
dml_print("DML: Tdmdl_vm: %fus - time for vm stages of dmd \n", v->Tdmdl_vm[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
952
dml_print("DML: Tdmdl: %fus - time for fabric to become ready and fetch dmd \n", v->Tdmdl[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
953
dml_print("DML: dst_x_after_scl: %f pixels - number of pixel clocks pipeline and buffer delay after scaler \n", v->DSTXAfterScaler[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
954
dml_print("DML: dst_y_after_scl: %d lines - number of lines of pipeline and buffer delay after scaler \n", (int)v->DSTYAfterScaler[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
968
if (Tpre_rounded - v->Tno_bw[k] > 0)
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
972
+ PrefetchSourceLinesC * swath_width_chroma_ub * v->BytePerPixelC[k])
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
973
/ (Tpre_rounded - v->Tno_bw[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
977
if (VStartup == MaxVStartup && (PrefetchBandwidth1 > 4 * prefetch_bw_oto) && (Tpre_rounded - Tsw_oto / 4 - 0.75 * LineTime - v->Tno_bw[k]) > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
978
PrefetchBandwidth1 = (PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor + 2 * MetaRowByte + 2 * PixelPTEBytesPerRow * HostVMInefficiencyFactor) / (Tpre_rounded - Tsw_oto / 4 - 0.75 * LineTime - v->Tno_bw[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
981
if (Tpre_rounded - v->Tno_bw[k] - 2 * Tr0_trips_rounded > 0)
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
986
v->BytePerPixelC[k]) /
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
987
(Tpre_rounded - v->Tno_bw[k] - 2 * Tr0_trips_rounded);
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
995
swath_width_chroma_ub * v->BytePerPixelC[k]) / (Tpre_rounded -
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
1744
struct vba_vars_st *v = &mode_lib->vba;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
1752
if (!v->IgnoreViewportPositioning) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
1780
dml_print("DML::%s: IgnoreViewportPositioning = %d\n", __func__, v->IgnoreViewportPositioning);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
1826
struct vba_vars_st *v = &mode_lib->vba;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
1861
MPDEBytesFrame = 128 * (v->GPUVMMaxPageTableLevels - 1);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
1882
if (GPUVMEnable == true && v->GPUVMMaxPageTableLevels > 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
1896
ExtraDPDEBytesFrame = 128 * (v->GPUVMMaxPageTableLevels - 2);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
1989
struct vba_vars_st *v = &mode_lib->vba;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
1996
int PrefetchMode = v->PrefetchModePerState[v->VoltageLevel][v->maxMpcComb];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
1998
v->WritebackDISPCLK = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
1999
v->DISPCLKWithRamping = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2000
v->DISPCLKWithoutRamping = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2001
v->GlobalDPPCLK = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2005
v->ReturnBusWidth * v->DCFCLKState[v->VoltageLevel][v->maxMpcComb],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2006
v->FabricClockPerState[v->VoltageLevel] * v->FabricDatapathToDCNDataReturn);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2007
double IdealDRAMBandwidthPerState = v->DRAMSpeedPerState[v->VoltageLevel] * v->NumberOfChannels * v->DRAMChannelWidth;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2008
if (v->HostVMEnable != true) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2009
v->ReturnBW = dml_min(
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2010
IdealFabricAndSDPPortBandwidthPerState * v->PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency / 100.0,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2011
IdealDRAMBandwidthPerState * v->PercentOfIdealDRAMBWReceivedAfterUrgLatencyPixelDataOnly / 100.0);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2013
v->ReturnBW = dml_min(
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2014
IdealFabricAndSDPPortBandwidthPerState * v->PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency / 100.0,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2015
IdealDRAMBandwidthPerState * v->PercentOfIdealDRAMBWReceivedAfterUrgLatencyPixelMixedWithVMData / 100.0);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2022
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2023
if (v->WritebackEnable[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2024
v->WritebackDISPCLK = dml_max(
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2025
v->WritebackDISPCLK,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2027
v->WritebackPixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2028
v->PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2029
v->WritebackHRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2030
v->WritebackVRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2031
v->WritebackHTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2032
v->WritebackVTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2033
v->WritebackSourceWidth[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2034
v->WritebackDestinationWidth[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2035
v->HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2036
v->WritebackLineBufferSize));
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2040
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2041
if (v->HRatio[k] > 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2042
v->PSCL_THROUGHPUT_LUMA[k] = dml_min(
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2043
v->MaxDCHUBToPSCLThroughput,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2044
v->MaxPSCLToLBThroughput * v->HRatio[k] / dml_ceil(v->htaps[k] / 6.0, 1));
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2046
v->PSCL_THROUGHPUT_LUMA[k] = dml_min(v->MaxDCHUBToPSCLThroughput, v->MaxPSCLToLBThroughput);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2049
v->DPPCLKUsingSingleDPPLuma = v->PixelClock[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2051
v->vtaps[k] / 6.0 * dml_min(1.0, v->HRatio[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2052
dml_max(v->HRatio[k] * v->VRatio[k] / v->PSCL_THROUGHPUT_LUMA[k], 1.0));
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2054
if ((v->htaps[k] > 6 || v->vtaps[k] > 6) && v->DPPCLKUsingSingleDPPLuma < 2 * v->PixelClock[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2055
v->DPPCLKUsingSingleDPPLuma = 2 * v->PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2058
if ((v->SourcePixelFormat[k] != dm_420_8 && v->SourcePixelFormat[k] != dm_420_10 && v->SourcePixelFormat[k] != dm_420_12
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2059
&& v->SourcePixelFormat[k] != dm_rgbe_alpha)) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2060
v->PSCL_THROUGHPUT_CHROMA[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2061
v->DPPCLKUsingSingleDPP[k] = v->DPPCLKUsingSingleDPPLuma;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2063
if (v->HRatioChroma[k] > 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2064
v->PSCL_THROUGHPUT_CHROMA[k] = dml_min(
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2065
v->MaxDCHUBToPSCLThroughput,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2066
v->MaxPSCLToLBThroughput * v->HRatioChroma[k] / dml_ceil(v->HTAPsChroma[k] / 6.0, 1.0));
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2068
v->PSCL_THROUGHPUT_CHROMA[k] = dml_min(v->MaxDCHUBToPSCLThroughput, v->MaxPSCLToLBThroughput);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2070
v->DPPCLKUsingSingleDPPChroma = v->PixelClock[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2072
v->VTAPsChroma[k] / 6.0 * dml_min(1.0, v->HRatioChroma[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2073
v->HRatioChroma[k] * v->VRatioChroma[k] / v->PSCL_THROUGHPUT_CHROMA[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2076
if ((v->HTAPsChroma[k] > 6 || v->VTAPsChroma[k] > 6) && v->DPPCLKUsingSingleDPPChroma < 2 * v->PixelClock[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2077
v->DPPCLKUsingSingleDPPChroma = 2 * v->PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2080
v->DPPCLKUsingSingleDPP[k] = dml_max(v->DPPCLKUsingSingleDPPLuma, v->DPPCLKUsingSingleDPPChroma);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2084
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2085
if (v->BlendingAndTiming[k] != k)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2087
if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_4to1) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2088
v->DISPCLKWithRamping = dml_max(
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2089
v->DISPCLKWithRamping,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2090
v->PixelClock[k] / 4 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2091
* (1 + v->DISPCLKRampingMargin / 100));
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2092
v->DISPCLKWithoutRamping = dml_max(
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2093
v->DISPCLKWithoutRamping,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2094
v->PixelClock[k] / 4 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100));
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2095
} else if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_2to1) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2096
v->DISPCLKWithRamping = dml_max(
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2097
v->DISPCLKWithRamping,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2098
v->PixelClock[k] / 2 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2099
* (1 + v->DISPCLKRampingMargin / 100));
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2100
v->DISPCLKWithoutRamping = dml_max(
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2101
v->DISPCLKWithoutRamping,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2102
v->PixelClock[k] / 2 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100));
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2104
v->DISPCLKWithRamping = dml_max(
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2105
v->DISPCLKWithRamping,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2106
v->PixelClock[k] * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100) * (1 + v->DISPCLKRampingMargin / 100));
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2107
v->DISPCLKWithoutRamping = dml_max(
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2108
v->DISPCLKWithoutRamping,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2109
v->PixelClock[k] * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100));
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2113
v->DISPCLKWithRamping = dml_max(v->DISPCLKWithRamping, v->WritebackDISPCLK);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2114
v->DISPCLKWithoutRamping = dml_max(v->DISPCLKWithoutRamping, v->WritebackDISPCLK);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2116
ASSERT(v->DISPCLKDPPCLKVCOSpeed != 0);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2117
v->DISPCLKWithRampingRoundedToDFSGranularity = RoundToDFSGranularityUp(v->DISPCLKWithRamping, v->DISPCLKDPPCLKVCOSpeed);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2118
v->DISPCLKWithoutRampingRoundedToDFSGranularity = RoundToDFSGranularityUp(v->DISPCLKWithoutRamping, v->DISPCLKDPPCLKVCOSpeed);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2119
v->MaxDispclkRoundedToDFSGranularity = RoundToDFSGranularityDown(
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2120
v->soc.clock_limits[v->soc.num_states - 1].dispclk_mhz,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2121
v->DISPCLKDPPCLKVCOSpeed);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2122
if (v->DISPCLKWithoutRampingRoundedToDFSGranularity > v->MaxDispclkRoundedToDFSGranularity) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2123
v->DISPCLK_calculated = v->DISPCLKWithoutRampingRoundedToDFSGranularity;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2124
} else if (v->DISPCLKWithRampingRoundedToDFSGranularity > v->MaxDispclkRoundedToDFSGranularity) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2125
v->DISPCLK_calculated = v->MaxDispclkRoundedToDFSGranularity;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2127
v->DISPCLK_calculated = v->DISPCLKWithRampingRoundedToDFSGranularity;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2129
v->DISPCLK = v->DISPCLK_calculated;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2130
DTRACE(" dispclk_mhz (calculated) = %f", v->DISPCLK_calculated);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2132
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2133
v->DPPCLK_calculated[k] = v->DPPCLKUsingSingleDPP[k] / v->DPPPerPlane[k] * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2134
v->GlobalDPPCLK = dml_max(v->GlobalDPPCLK, v->DPPCLK_calculated[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2136
v->GlobalDPPCLK = RoundToDFSGranularityUp(v->GlobalDPPCLK, v->DISPCLKDPPCLKVCOSpeed);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2137
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2138
v->DPPCLK_calculated[k] = v->GlobalDPPCLK / 255 * dml_ceil(v->DPPCLK_calculated[k] * 255.0 / v->GlobalDPPCLK, 1);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2139
DTRACE(" dppclk_mhz[%i] (calculated) = %f", k, v->DPPCLK_calculated[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2142
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2143
v->DPPCLK[k] = v->DPPCLK_calculated[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2147
DTRACE(" dcfclk_mhz = %f", v->DCFCLK);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2148
DTRACE(" return_bus_bw = %f", v->ReturnBW);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2150
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2152
v->SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2153
v->SurfaceTiling[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2154
&v->BytePerPixelY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2155
&v->BytePerPixelC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2156
&v->BytePerPixelDETY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2157
&v->BytePerPixelDETC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2158
&v->BlockHeight256BytesY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2159
&v->BlockHeight256BytesC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2160
&v->BlockWidth256BytesY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2161
&v->BlockWidth256BytesC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2166
v->NumberOfActivePlanes,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2167
v->SourcePixelFormat,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2168
v->SourceScan,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2169
v->ViewportWidth,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2170
v->ViewportHeight,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2171
v->SurfaceWidthY,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2172
v->SurfaceWidthC,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2173
v->SurfaceHeightY,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2174
v->SurfaceHeightC,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2175
v->ODMCombineEnabled,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2176
v->BytePerPixelY,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2177
v->BytePerPixelC,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2178
v->BlockHeight256BytesY,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2179
v->BlockHeight256BytesC,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2180
v->BlockWidth256BytesY,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2181
v->BlockWidth256BytesC,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2182
v->BlendingAndTiming,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2183
v->HActive,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2184
v->HRatio,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2185
v->DPPPerPlane,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2186
v->SwathWidthSingleDPPY,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2187
v->SwathWidthSingleDPPC,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2188
v->SwathWidthY,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2189
v->SwathWidthC,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2190
v->dummyinteger3,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2191
v->dummyinteger4,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2192
v->swath_width_luma_ub,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2193
v->swath_width_chroma_ub);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2195
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2196
v->ReadBandwidthPlaneLuma[k] = v->SwathWidthSingleDPPY[k] * v->BytePerPixelY[k] / (v->HTotal[k] / v->PixelClock[k])
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2197
* v->VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2198
v->ReadBandwidthPlaneChroma[k] = v->SwathWidthSingleDPPC[k] * v->BytePerPixelC[k] / (v->HTotal[k] / v->PixelClock[k])
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2199
* v->VRatioChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2200
DTRACE(" read_bw[%i] = %fBps", k, v->ReadBandwidthPlaneLuma[k] + v->ReadBandwidthPlaneChroma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2206
v->NumberOfActivePlanes,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2207
v->BytePerPixelY,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2208
v->BytePerPixelC,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2209
v->VRatio,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2210
v->VRatioChroma,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2211
v->SwathWidthY,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2212
v->SwathWidthC,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2213
v->DPPPerPlane,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2214
v->HRatio,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2215
v->HRatioChroma,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2216
v->PixelClock,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2217
v->PSCL_THROUGHPUT_LUMA,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2218
v->PSCL_THROUGHPUT_CHROMA,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2219
v->DPPCLK,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2220
v->ReadBandwidthPlaneLuma,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2221
v->ReadBandwidthPlaneChroma,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2222
v->ReturnBusWidth,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2223
&v->DCFCLKDeepSleep);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2226
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2227
if ((v->BlendingAndTiming[k] != k) || !v->DSCEnabled[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2228
v->DSCCLK_calculated[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2230
if (v->OutputFormat[k] == dm_420)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2231
v->DSCFormatFactor = 2;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2232
else if (v->OutputFormat[k] == dm_444)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2233
v->DSCFormatFactor = 1;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2234
else if (v->OutputFormat[k] == dm_n422)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2235
v->DSCFormatFactor = 2;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2237
v->DSCFormatFactor = 1;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2238
if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_4to1)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2239
v->DSCCLK_calculated[k] = v->PixelClockBackEnd[k] / 12 / v->DSCFormatFactor
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2240
/ (1 - v->DISPCLKDPPCLKDSCCLKDownSpreading / 100);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2241
else if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_2to1)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2242
v->DSCCLK_calculated[k] = v->PixelClockBackEnd[k] / 6 / v->DSCFormatFactor
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2243
/ (1 - v->DISPCLKDPPCLKDSCCLKDownSpreading / 100);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2245
v->DSCCLK_calculated[k] = v->PixelClockBackEnd[k] / 3 / v->DSCFormatFactor
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2246
/ (1 - v->DISPCLKDPPCLKDSCCLKDownSpreading / 100);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2251
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2252
double BPP = v->OutputBpp[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2254
if (v->DSCEnabled[k] && BPP != 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2255
if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_disabled) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2256
v->DSCDelay[k] = dscceComputeDelay(
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2257
v->DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2259
dml_ceil((double) v->HActive[k] / v->NumberOfDSCSlices[k], 1),
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2260
v->NumberOfDSCSlices[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2261
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2262
v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2263
} else if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_2to1) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2264
v->DSCDelay[k] = 2
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2266
v->DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2268
dml_ceil((double) v->HActive[k] / v->NumberOfDSCSlices[k], 1),
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2269
v->NumberOfDSCSlices[k] / 2.0,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2270
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2271
v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k]));
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2273
v->DSCDelay[k] = 4
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2275
v->DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2277
dml_ceil((double) v->HActive[k] / v->NumberOfDSCSlices[k], 1),
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2278
v->NumberOfDSCSlices[k] / 4.0,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2279
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2280
v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k]));
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2282
v->DSCDelay[k] = v->DSCDelay[k] * v->PixelClock[k] / v->PixelClockBackEnd[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2284
v->DSCDelay[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2288
for (k = 0; k < v->NumberOfActivePlanes; ++k)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2289
for (j = 0; j < v->NumberOfActivePlanes; ++j) // NumberOfPlanes
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2290
if (j != k && v->BlendingAndTiming[k] == j && v->DSCEnabled[j])
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2291
v->DSCDelay[k] = v->DSCDelay[j];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2294
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2304
if (v->SourcePixelFormat[k] == dm_420_8 || v->SourcePixelFormat[k] == dm_420_10 || v->SourcePixelFormat[k] == dm_420_12
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2305
|| v->SourcePixelFormat[k] == dm_rgbe_alpha) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2306
if ((v->SourcePixelFormat[k] == dm_420_10 || v->SourcePixelFormat[k] == dm_420_12) && v->SourceScan[k] != dm_vert) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2307
v->PTEBufferSizeInRequestsForLuma = (v->PTEBufferSizeInRequestsLuma + v->PTEBufferSizeInRequestsChroma) / 2;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2308
v->PTEBufferSizeInRequestsForChroma = v->PTEBufferSizeInRequestsForLuma;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2310
v->PTEBufferSizeInRequestsForLuma = v->PTEBufferSizeInRequestsLuma;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2311
v->PTEBufferSizeInRequestsForChroma = v->PTEBufferSizeInRequestsChroma;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2316
v->DCCEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2317
v->BlockHeight256BytesC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2318
v->BlockWidth256BytesC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2319
v->SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2320
v->SurfaceTiling[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2321
v->BytePerPixelC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2322
v->SourceScan[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2323
v->SwathWidthC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2324
v->ViewportHeightChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2325
v->GPUVMEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2326
v->HostVMEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2327
v->HostVMMaxNonCachedPageTableLevels,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2328
v->GPUVMMinPageSize,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2329
v->HostVMMinPageSize,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2330
v->PTEBufferSizeInRequestsForChroma,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2331
v->PitchC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2332
v->DCCMetaPitchC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2333
&v->MacroTileWidthC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2337
&v->dpte_row_width_chroma_ub[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2338
&v->dpte_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2339
&v->meta_req_width_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2340
&v->meta_req_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2341
&v->meta_row_width_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2342
&v->meta_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2343
&v->dummyinteger1,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2344
&v->dummyinteger2,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2345
&v->PixelPTEReqWidthC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2346
&v->PixelPTEReqHeightC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2347
&v->PTERequestSizeC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2348
&v->dpde0_bytes_per_frame_ub_c[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2349
&v->meta_pte_bytes_per_frame_ub_c[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2351
v->PrefetchSourceLinesC[k] = CalculatePrefetchSourceLines(
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2353
v->VRatioChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2354
v->VTAPsChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2355
v->Interlace[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2356
v->ProgressiveToInterlaceUnitInOPP,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2357
v->SwathHeightC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2358
v->ViewportYStartC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2359
&v->VInitPreFillC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2360
&v->MaxNumSwathC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2362
v->PTEBufferSizeInRequestsForLuma = v->PTEBufferSizeInRequestsLuma + v->PTEBufferSizeInRequestsChroma;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2363
v->PTEBufferSizeInRequestsForChroma = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2367
v->MaxNumSwathC[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2368
v->PrefetchSourceLinesC[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2373
v->DCCEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2374
v->BlockHeight256BytesY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2375
v->BlockWidth256BytesY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2376
v->SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2377
v->SurfaceTiling[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2378
v->BytePerPixelY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2379
v->SourceScan[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2380
v->SwathWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2381
v->ViewportHeight[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2382
v->GPUVMEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2383
v->HostVMEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2384
v->HostVMMaxNonCachedPageTableLevels,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2385
v->GPUVMMinPageSize,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2386
v->HostVMMinPageSize,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2387
v->PTEBufferSizeInRequestsForLuma,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2388
v->PitchY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2389
v->DCCMetaPitchY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2390
&v->MacroTileWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2394
&v->dpte_row_width_luma_ub[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2395
&v->dpte_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2396
&v->meta_req_width[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2397
&v->meta_req_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2398
&v->meta_row_width[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2399
&v->meta_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2400
&v->vm_group_bytes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2401
&v->dpte_group_bytes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2402
&v->PixelPTEReqWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2403
&v->PixelPTEReqHeightY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2404
&v->PTERequestSizeY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2405
&v->dpde0_bytes_per_frame_ub_l[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2406
&v->meta_pte_bytes_per_frame_ub_l[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2408
v->PrefetchSourceLinesY[k] = CalculatePrefetchSourceLines(
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2410
v->VRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2411
v->vtaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2412
v->Interlace[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2413
v->ProgressiveToInterlaceUnitInOPP,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2414
v->SwathHeightY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2415
v->ViewportYStartY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2416
&v->VInitPreFillY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2417
&v->MaxNumSwathY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2418
v->PixelPTEBytesPerRow[k] = PixelPTEBytesPerRowY + PixelPTEBytesPerRowC;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2419
v->PDEAndMetaPTEBytesFrame[k] = PDEAndMetaPTEBytesFrameY + PDEAndMetaPTEBytesFrameC;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2420
v->MetaRowByte[k] = MetaRowByteY + MetaRowByteC;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2423
v->GPUVMEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2424
v->SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2425
v->VRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2426
v->VRatioChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2427
v->DCCEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2428
v->HTotal[k] / v->PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2431
v->meta_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2432
v->meta_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2435
v->dpte_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2436
v->dpte_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2437
&v->meta_row_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2438
&v->dpte_row_bw[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2441
v->TotalDCCActiveDPP = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2442
v->TotalActiveDPP = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2443
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2444
v->TotalActiveDPP = v->TotalActiveDPP + v->DPPPerPlane[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2445
if (v->DCCEnable[k])
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2446
v->TotalDCCActiveDPP = v->TotalDCCActiveDPP + v->DPPPerPlane[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2447
if (v->SourcePixelFormat[k] == dm_420_8 || v->SourcePixelFormat[k] == dm_420_10 || v->SourcePixelFormat[k] == dm_420_12
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2448
|| v->SourcePixelFormat[k] == dm_rgbe_alpha)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2452
ReorderBytes = v->NumberOfChannels
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2454
v->UrgentOutOfOrderReturnPerChannelPixelDataOnly,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2455
v->UrgentOutOfOrderReturnPerChannelPixelMixedWithVMData,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2456
v->UrgentOutOfOrderReturnPerChannelVMDataOnly);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2459
dml_min(v->ReturnBusWidth * v->DCFCLK, v->FabricClock * v->FabricDatapathToDCNDataReturn)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2460
* v->PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency / 100.0,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2461
v->DRAMSpeed * v->NumberOfChannels * v->DRAMChannelWidth
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2462
* v->PercentOfIdealDRAMBWReceivedAfterUrgLatencyVMDataOnly / 100.0);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2465
dml_print("DML::%s: v->ReturnBusWidth = %f\n", __func__, v->ReturnBusWidth);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2466
dml_print("DML::%s: v->DCFCLK = %f\n", __func__, v->DCFCLK);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2467
dml_print("DML::%s: v->FabricClock = %f\n", __func__, v->FabricClock);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2468
dml_print("DML::%s: v->FabricDatapathToDCNDataReturn = %f\n", __func__, v->FabricDatapathToDCNDataReturn);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2469
dml_print("DML::%s: v->PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency = %f\n", __func__, v->PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2470
dml_print("DML::%s: v->DRAMSpeed = %f\n", __func__, v->DRAMSpeed);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2471
dml_print("DML::%s: v->NumberOfChannels = %f\n", __func__, v->NumberOfChannels);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2472
dml_print("DML::%s: v->DRAMChannelWidth = %f\n", __func__, v->DRAMChannelWidth);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2473
dml_print("DML::%s: v->PercentOfIdealDRAMBWReceivedAfterUrgLatencyVMDataOnly = %f\n", __func__, v->PercentOfIdealDRAMBWReceivedAfterUrgLatencyVMDataOnly);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2475
dml_print("DML::%s: ReturnBW = %f\n", __func__, v->ReturnBW);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2478
if (v->GPUVMEnable && v->HostVMEnable)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2479
HostVMInefficiencyFactor = v->ReturnBW / VMDataOnlyReturnBW;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2481
v->UrgentExtraLatency = CalculateExtraLatency(
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2482
v->RoundTripPingLatencyCycles,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2484
v->DCFCLK,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2485
v->TotalActiveDPP,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2486
v->PixelChunkSizeInKByte,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2487
v->TotalDCCActiveDPP,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2488
v->MetaChunkSize,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2489
v->ReturnBW,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2490
v->GPUVMEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2491
v->HostVMEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2492
v->NumberOfActivePlanes,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2493
v->DPPPerPlane,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2494
v->dpte_group_bytes,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2496
v->HostVMMinPageSize,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2497
v->HostVMMaxNonCachedPageTableLevels);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2499
v->TCalc = 24.0 / v->DCFCLKDeepSleep;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2501
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2502
if (v->BlendingAndTiming[k] == k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2503
if (v->WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2504
v->WritebackDelay[v->VoltageLevel][k] = v->WritebackLatency
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2506
v->WritebackPixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2507
v->WritebackHRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2508
v->WritebackVRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2509
v->WritebackVTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2510
v->WritebackDestinationWidth[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2511
v->WritebackDestinationHeight[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2512
v->WritebackSourceHeight[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2513
v->HTotal[k]) / v->DISPCLK;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2515
v->WritebackDelay[v->VoltageLevel][k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2516
for (j = 0; j < v->NumberOfActivePlanes; ++j) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2517
if (v->BlendingAndTiming[j] == k && v->WritebackEnable[j] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2518
v->WritebackDelay[v->VoltageLevel][k] = dml_max(
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2519
v->WritebackDelay[v->VoltageLevel][k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2520
v->WritebackLatency
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2522
v->WritebackPixelFormat[j],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2523
v->WritebackHRatio[j],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2524
v->WritebackVRatio[j],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2525
v->WritebackVTaps[j],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2526
v->WritebackDestinationWidth[j],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2527
v->WritebackDestinationHeight[j],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2528
v->WritebackSourceHeight[j],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2529
v->HTotal[k]) / v->DISPCLK);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2535
for (k = 0; k < v->NumberOfActivePlanes; ++k)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2536
for (j = 0; j < v->NumberOfActivePlanes; ++j)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2537
if (v->BlendingAndTiming[k] == j)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2538
v->WritebackDelay[v->VoltageLevel][k] = v->WritebackDelay[v->VoltageLevel][j];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2540
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2541
v->MaxVStartupLines[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2542
(v->Interlace[k] && !v->ProgressiveToInterlaceUnitInOPP) ?
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2543
dml_floor((v->VTotal[k] - v->VActive[k]) / 2.0, 1.0) :
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2544
v->VTotal[k] - v->VActive[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2548
(double) v->WritebackDelay[v->VoltageLevel][k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2549
/ (v->HTotal[k] / v->PixelClock[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2551
if (v->MaxVStartupLines[k] > 1023)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2552
v->MaxVStartupLines[k] = 1023;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2555
dml_print("DML::%s: k=%d MaxVStartupLines = %d\n", __func__, k, v->MaxVStartupLines[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2556
dml_print("DML::%s: k=%d VoltageLevel = %d\n", __func__, k, v->VoltageLevel);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2557
dml_print("DML::%s: k=%d WritebackDelay = %f\n", __func__, k, v->WritebackDelay[v->VoltageLevel][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2561
v->MaximumMaxVStartupLines = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2562
for (k = 0; k < v->NumberOfActivePlanes; ++k)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2563
v->MaximumMaxVStartupLines = dml_max(v->MaximumMaxVStartupLines, v->MaxVStartupLines[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2569
v->UrgentLatency = CalculateUrgentLatency(
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2570
v->UrgentLatencyPixelDataOnly,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2571
v->UrgentLatencyPixelMixedWithVMData,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2572
v->UrgentLatencyVMDataOnly,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2573
v->DoUrgentLatencyAdjustment,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2574
v->UrgentLatencyAdjustmentFabricClockComponent,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2575
v->UrgentLatencyAdjustmentFabricClockReference,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2576
v->FabricClock);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2578
v->FractionOfUrgentBandwidth = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2579
v->FractionOfUrgentBandwidthImmediateFlip = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2581
v->VStartupLines = __DML_VBA_MIN_VSTARTUP__;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2587
double TWait = CalculateTWait(PrefetchMode, v->DRAMClockChangeLatency, v->UrgentLatency, v->SREnterPlusExitTime);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2590
dml_print("DML::%s: Start loop: VStartup = %d\n", __func__, v->VStartupLines);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2592
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2595
myPipe.DPPCLK = v->DPPCLK[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2596
myPipe.DISPCLK = v->DISPCLK;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2597
myPipe.PixelClock = v->PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2598
myPipe.DCFCLKDeepSleep = v->DCFCLKDeepSleep;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2599
myPipe.DPPPerPlane = v->DPPPerPlane[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2600
myPipe.ScalerEnabled = v->ScalerEnabled[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2601
myPipe.VRatio = v->VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2602
myPipe.VRatioChroma = v->VRatioChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2603
myPipe.SourceScan = v->SourceScan[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2604
myPipe.BlockWidth256BytesY = v->BlockWidth256BytesY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2605
myPipe.BlockHeight256BytesY = v->BlockHeight256BytesY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2606
myPipe.BlockWidth256BytesC = v->BlockWidth256BytesC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2607
myPipe.BlockHeight256BytesC = v->BlockHeight256BytesC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2608
myPipe.InterlaceEnable = v->Interlace[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2609
myPipe.NumberOfCursors = v->NumberOfCursors[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2610
myPipe.VBlank = v->VTotal[k] - v->VActive[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2611
myPipe.HTotal = v->HTotal[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2612
myPipe.DCCEnable = v->DCCEnable[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2613
myPipe.ODMCombineIsEnabled = v->ODMCombineEnabled[k] == dm_odm_combine_mode_4to1
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2614
|| v->ODMCombineEnabled[k] == dm_odm_combine_mode_2to1;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2615
myPipe.SourcePixelFormat = v->SourcePixelFormat[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2616
myPipe.BytePerPixelY = v->BytePerPixelY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2617
myPipe.BytePerPixelC = v->BytePerPixelC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2618
myPipe.ProgressiveToInterlaceUnitInOPP = v->ProgressiveToInterlaceUnitInOPP;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2619
v->ErrorResult[k] = CalculatePrefetchSchedule(
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2623
v->DSCDelay[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2624
v->DPPCLKDelaySubtotal + v->DPPCLKDelayCNVCFormater,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2625
v->DPPCLKDelaySCL,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2626
v->DPPCLKDelaySCLLBOnly,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2627
v->DPPCLKDelayCNVCCursor,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2628
v->DISPCLKDelaySubtotal,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2629
(unsigned int) (v->SwathWidthY[k] / v->HRatio[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2630
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2631
v->MaxInterDCNTileRepeaters,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2632
dml_min(v->VStartupLines, v->MaxVStartupLines[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2633
v->MaxVStartupLines[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2634
v->GPUVMMaxPageTableLevels,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2635
v->GPUVMEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2636
v->HostVMEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2637
v->HostVMMaxNonCachedPageTableLevels,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2638
v->HostVMMinPageSize,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2639
v->DynamicMetadataEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2640
v->DynamicMetadataVMEnabled,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2641
v->DynamicMetadataLinesBeforeActiveRequired[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2642
v->DynamicMetadataTransmittedBytes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2643
v->UrgentLatency,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2644
v->UrgentExtraLatency,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2645
v->TCalc,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2646
v->PDEAndMetaPTEBytesFrame[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2647
v->MetaRowByte[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2648
v->PixelPTEBytesPerRow[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2649
v->PrefetchSourceLinesY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2650
v->SwathWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2651
v->VInitPreFillY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2652
v->MaxNumSwathY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2653
v->PrefetchSourceLinesC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2654
v->SwathWidthC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2655
v->VInitPreFillC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2656
v->MaxNumSwathC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2657
v->swath_width_luma_ub[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2658
v->swath_width_chroma_ub[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2659
v->SwathHeightY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2660
v->SwathHeightC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2662
&v->DSTXAfterScaler[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2663
&v->DSTYAfterScaler[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2664
&v->DestinationLinesForPrefetch[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2665
&v->PrefetchBandwidth[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2666
&v->DestinationLinesToRequestVMInVBlank[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2667
&v->DestinationLinesToRequestRowInVBlank[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2668
&v->VRatioPrefetchY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2669
&v->VRatioPrefetchC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2670
&v->RequiredPrefetchPixDataBWLuma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2671
&v->RequiredPrefetchPixDataBWChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2672
&v->NotEnoughTimeForDynamicMetadata[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2673
&v->Tno_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2674
&v->prefetch_vmrow_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2675
&v->Tdmdl_vm[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2676
&v->Tdmdl[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2677
&v->TSetup[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2678
&v->VUpdateOffsetPix[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2679
&v->VUpdateWidthPix[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2680
&v->VReadyOffsetPix[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2683
dml_print("DML::%s: k=%0d Prefetch cal result=%0d\n", __func__, k, v->ErrorResult[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2685
v->VStartup[k] = dml_min(v->VStartupLines, v->MaxVStartupLines[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2688
v->NoEnoughUrgentLatencyHiding = false;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2689
v->NoEnoughUrgentLatencyHidingPre = false;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2691
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2692
v->cursor_bw[k] = v->NumberOfCursors[k] * v->CursorWidth[k][0] * v->CursorBPP[k][0] / 8.0
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2693
/ (v->HTotal[k] / v->PixelClock[k]) * v->VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2694
v->cursor_bw_pre[k] = v->NumberOfCursors[k] * v->CursorWidth[k][0] * v->CursorBPP[k][0] / 8.0
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2695
/ (v->HTotal[k] / v->PixelClock[k]) * v->VRatioPrefetchY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2698
v->swath_width_luma_ub[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2699
v->swath_width_chroma_ub[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2700
v->SwathHeightY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2701
v->SwathHeightC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2702
v->HTotal[k] / v->PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2703
v->UrgentLatency,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2704
v->CursorBufferSize,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2705
v->CursorWidth[k][0],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2706
v->CursorBPP[k][0],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2707
v->VRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2708
v->VRatioChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2709
v->BytePerPixelDETY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2710
v->BytePerPixelDETC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2711
v->DETBufferSizeY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2712
v->DETBufferSizeC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2713
&v->UrgBurstFactorCursor[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2714
&v->UrgBurstFactorLuma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2715
&v->UrgBurstFactorChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2716
&v->NoUrgentLatencyHiding[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2719
v->swath_width_luma_ub[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2720
v->swath_width_chroma_ub[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2721
v->SwathHeightY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2722
v->SwathHeightC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2723
v->HTotal[k] / v->PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2724
v->UrgentLatency,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2725
v->CursorBufferSize,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2726
v->CursorWidth[k][0],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2727
v->CursorBPP[k][0],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2728
v->VRatioPrefetchY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2729
v->VRatioPrefetchC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2730
v->BytePerPixelDETY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2731
v->BytePerPixelDETC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2732
v->DETBufferSizeY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2733
v->DETBufferSizeC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2734
&v->UrgBurstFactorCursorPre[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2735
&v->UrgBurstFactorLumaPre[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2736
&v->UrgBurstFactorChromaPre[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2737
&v->NoUrgentLatencyHidingPre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2741
v->DPPPerPlane[k] * v->prefetch_vmrow_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2742
v->ReadBandwidthPlaneLuma[k] * v->UrgBurstFactorLuma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2743
+ v->ReadBandwidthPlaneChroma[k] * v->UrgBurstFactorChroma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2744
+ v->cursor_bw[k] * v->UrgBurstFactorCursor[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2745
+ v->DPPPerPlane[k] * (v->meta_row_bw[k] + v->dpte_row_bw[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2746
v->DPPPerPlane[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2747
* (v->RequiredPrefetchPixDataBWLuma[k] * v->UrgBurstFactorLumaPre[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2748
+ v->RequiredPrefetchPixDataBWChroma[k] * v->UrgBurstFactorChromaPre[k])
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2749
+ v->cursor_bw_pre[k] * v->UrgBurstFactorCursorPre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2753
v->DPPPerPlane[k] * v->prefetch_vmrow_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2754
v->ReadBandwidthPlaneLuma[k] + v->ReadBandwidthPlaneChroma[k] + v->cursor_bw[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2755
+ v->DPPPerPlane[k] * (v->meta_row_bw[k] + v->dpte_row_bw[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2756
v->DPPPerPlane[k] * (v->RequiredPrefetchPixDataBWLuma[k] + v->RequiredPrefetchPixDataBWChroma[k])
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2757
+ v->cursor_bw_pre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2760
dml_print("DML::%s: k=%0d DPPPerPlane=%d\n", __func__, k, v->DPPPerPlane[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2761
dml_print("DML::%s: k=%0d UrgBurstFactorLuma=%f\n", __func__, k, v->UrgBurstFactorLuma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2762
dml_print("DML::%s: k=%0d UrgBurstFactorChroma=%f\n", __func__, k, v->UrgBurstFactorChroma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2763
dml_print("DML::%s: k=%0d UrgBurstFactorLumaPre=%f\n", __func__, k, v->UrgBurstFactorLumaPre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2764
dml_print("DML::%s: k=%0d UrgBurstFactorChromaPre=%f\n", __func__, k, v->UrgBurstFactorChromaPre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2766
dml_print("DML::%s: k=%0d VRatioPrefetchY=%f\n", __func__, k, v->VRatioPrefetchY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2767
dml_print("DML::%s: k=%0d VRatioY=%f\n", __func__, k, v->VRatio[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2769
dml_print("DML::%s: k=%0d prefetch_vmrow_bw=%f\n", __func__, k, v->prefetch_vmrow_bw[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2770
dml_print("DML::%s: k=%0d ReadBandwidthPlaneLuma=%f\n", __func__, k, v->ReadBandwidthPlaneLuma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2771
dml_print("DML::%s: k=%0d ReadBandwidthPlaneChroma=%f\n", __func__, k, v->ReadBandwidthPlaneChroma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2772
dml_print("DML::%s: k=%0d cursor_bw=%f\n", __func__, k, v->cursor_bw[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2773
dml_print("DML::%s: k=%0d meta_row_bw=%f\n", __func__, k, v->meta_row_bw[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2774
dml_print("DML::%s: k=%0d dpte_row_bw=%f\n", __func__, k, v->dpte_row_bw[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2775
dml_print("DML::%s: k=%0d RequiredPrefetchPixDataBWLuma=%f\n", __func__, k, v->RequiredPrefetchPixDataBWLuma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2776
dml_print("DML::%s: k=%0d RequiredPrefetchPixDataBWChroma=%f\n", __func__, k, v->RequiredPrefetchPixDataBWChroma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2777
dml_print("DML::%s: k=%0d cursor_bw_pre=%f\n", __func__, k, v->cursor_bw_pre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2781
if (v->DestinationLinesForPrefetch[k] < 2)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2784
if (v->VRatioPrefetchY[k] > 4 || v->VRatioPrefetchC[k] > 4)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2787
if (v->NoUrgentLatencyHiding[k] == true)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2788
v->NoEnoughUrgentLatencyHiding = true;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2790
if (v->NoUrgentLatencyHidingPre[k] == true)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2791
v->NoEnoughUrgentLatencyHidingPre = true;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2794
v->FractionOfUrgentBandwidth = MaxTotalRDBandwidthNoUrgentBurst / v->ReturnBW;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2798
dml_print("DML::%s: ReturnBW=%f \n", __func__, v->ReturnBW);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2799
dml_print("DML::%s: FractionOfUrgentBandwidth=%f \n", __func__, v->FractionOfUrgentBandwidth);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2802
if (MaxTotalRDBandwidth <= v->ReturnBW && v->NoEnoughUrgentLatencyHiding == 0 && v->NoEnoughUrgentLatencyHidingPre == 0
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2804
v->PrefetchModeSupported = true;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2806
v->PrefetchModeSupported = false;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2808
dml_print("DML::%s: MaxTotalRDBandwidth:%f AvailReturnBandwidth:%f\n", __func__, MaxTotalRDBandwidth, v->ReturnBW);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2816
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2817
if (v->ErrorResult[k] == true || v->NotEnoughTimeForDynamicMetadata[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2818
v->PrefetchModeSupported = false;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2823
if (v->PrefetchModeSupported == true && v->ImmediateFlipSupport == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2824
v->BandwidthAvailableForImmediateFlip = v->ReturnBW;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2825
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2826
v->BandwidthAvailableForImmediateFlip = v->BandwidthAvailableForImmediateFlip
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2828
v->ReadBandwidthPlaneLuma[k] * v->UrgBurstFactorLuma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2829
+ v->ReadBandwidthPlaneChroma[k] * v->UrgBurstFactorChroma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2830
+ v->cursor_bw[k] * v->UrgBurstFactorCursor[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2831
v->DPPPerPlane[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2832
* (v->RequiredPrefetchPixDataBWLuma[k] * v->UrgBurstFactorLumaPre[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2833
+ v->RequiredPrefetchPixDataBWChroma[k] * v->UrgBurstFactorChromaPre[k])
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2834
+ v->cursor_bw_pre[k] * v->UrgBurstFactorCursorPre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2837
v->TotImmediateFlipBytes = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2838
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2839
v->TotImmediateFlipBytes = v->TotImmediateFlipBytes
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2840
+ v->DPPPerPlane[k] * (v->PDEAndMetaPTEBytesFrame[k] + v->MetaRowByte[k] + v->PixelPTEBytesPerRow[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2842
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2847
v->UrgentExtraLatency,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2848
v->UrgentLatency,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2849
v->PDEAndMetaPTEBytesFrame[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2850
v->MetaRowByte[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2851
v->PixelPTEBytesPerRow[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2854
v->total_dcn_read_bw_with_flip = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2855
v->total_dcn_read_bw_with_flip_no_urgent_burst = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2856
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2857
v->total_dcn_read_bw_with_flip = v->total_dcn_read_bw_with_flip
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2859
v->DPPPerPlane[k] * v->prefetch_vmrow_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2860
v->DPPPerPlane[k] * v->final_flip_bw[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2861
+ v->ReadBandwidthLuma[k] * v->UrgBurstFactorLuma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2862
+ v->ReadBandwidthChroma[k] * v->UrgBurstFactorChroma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2863
+ v->cursor_bw[k] * v->UrgBurstFactorCursor[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2864
v->DPPPerPlane[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2865
* (v->final_flip_bw[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2866
+ v->RequiredPrefetchPixDataBWLuma[k] * v->UrgBurstFactorLumaPre[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2867
+ v->RequiredPrefetchPixDataBWChroma[k] * v->UrgBurstFactorChromaPre[k])
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2868
+ v->cursor_bw_pre[k] * v->UrgBurstFactorCursorPre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2869
v->total_dcn_read_bw_with_flip_no_urgent_burst = v->total_dcn_read_bw_with_flip_no_urgent_burst
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2871
v->DPPPerPlane[k] * v->prefetch_vmrow_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2872
v->DPPPerPlane[k] * v->final_flip_bw[k] + v->ReadBandwidthPlaneLuma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2873
+ v->ReadBandwidthPlaneChroma[k] + v->cursor_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2874
v->DPPPerPlane[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2875
* (v->final_flip_bw[k] + v->RequiredPrefetchPixDataBWLuma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2876
+ v->RequiredPrefetchPixDataBWChroma[k]) + v->cursor_bw_pre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2878
v->FractionOfUrgentBandwidthImmediateFlip = v->total_dcn_read_bw_with_flip_no_urgent_burst / v->ReturnBW;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2880
v->ImmediateFlipSupported = true;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2881
if (v->total_dcn_read_bw_with_flip > v->ReturnBW) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2883
dml_print("DML::%s: total_dcn_read_bw_with_flip %f (bw w/ flip too high!)\n", __func__, v->total_dcn_read_bw_with_flip);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2885
v->ImmediateFlipSupported = false;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2886
v->total_dcn_read_bw_with_flip = MaxTotalRDBandwidth;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2888
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2889
if (v->ImmediateFlipSupportedForPipe[k] == false) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2894
v->ImmediateFlipSupported = false;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2898
v->ImmediateFlipSupported = false;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2901
v->PrefetchAndImmediateFlipSupported =
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2902
(v->PrefetchModeSupported == true && ((!v->ImmediateFlipSupport && !v->HostVMEnable
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2903
&& v->ImmediateFlipRequirement[0] != dm_immediate_flip_required) ||
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2904
v->ImmediateFlipSupported)) ? true : false;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2906
dml_print("DML::%s: PrefetchModeSupported %d\n", __func__, v->PrefetchModeSupported);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2907
dml_print("DML::%s: ImmediateFlipRequirement[0] %d\n", __func__, v->ImmediateFlipRequirement[0] == dm_immediate_flip_required);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2908
dml_print("DML::%s: ImmediateFlipSupported %d\n", __func__, v->ImmediateFlipSupported);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2909
dml_print("DML::%s: ImmediateFlipSupport %d\n", __func__, v->ImmediateFlipSupport);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2910
dml_print("DML::%s: HostVMEnable %d\n", __func__, v->HostVMEnable);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2911
dml_print("DML::%s: PrefetchAndImmediateFlipSupported %d\n", __func__, v->PrefetchAndImmediateFlipSupported);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2913
dml_print("DML::%s: Done loop: Vstartup=%d, Max Vstartup is %d\n", __func__, v->VStartupLines, v->MaximumMaxVStartupLines);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2915
v->VStartupLines = v->VStartupLines + 1;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2916
} while (!v->PrefetchAndImmediateFlipSupported && v->VStartupLines <= v->MaximumMaxVStartupLines);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2917
ASSERT(v->PrefetchAndImmediateFlipSupported);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2921
v->DETBufferSizeInKByte[0],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2922
v->ConfigReturnBufferSizeInKByte,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2923
v->UseUnboundedRequesting,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2924
v->TotalActiveDPP,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2926
v->MaxNumDPP,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2927
v->CompressedBufferSegmentSizeInkByte,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2928
v->Output,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2929
&v->UnboundedRequestEnabled,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2930
&v->CompressedBufferSizeInkByte);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2938
v->DCFCLK,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2939
v->ReturnBW,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2940
v->UrgentLatency,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2941
v->UrgentExtraLatency,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2942
v->SOCCLK,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2943
v->DCFCLKDeepSleep,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2944
v->DETBufferSizeY,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2945
v->DETBufferSizeC,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2946
v->SwathHeightY,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2947
v->SwathHeightC,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2948
v->SwathWidthY,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2949
v->SwathWidthC,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2950
v->DPPPerPlane,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2951
v->BytePerPixelDETY,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2952
v->BytePerPixelDETC,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2953
v->UnboundedRequestEnabled,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2954
v->CompressedBufferSizeInkByte,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2956
&v->StutterExitWatermark,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2957
&v->StutterEnterPlusExitWatermark,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2958
&v->Z8StutterExitWatermark,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2959
&v->Z8StutterEnterPlusExitWatermark);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2961
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2962
if (v->WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2963
v->WritebackAllowDRAMClockChangeEndPosition[k] = dml_max(
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2965
v->VStartup[k] * v->HTotal[k] / v->PixelClock[k] - v->WritebackDRAMClockChangeWatermark);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2967
v->WritebackAllowDRAMClockChangeEndPosition[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2974
v->NumberOfActivePlanes,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2975
v->VRatio,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2976
v->VRatioChroma,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2977
v->VRatioPrefetchY,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2978
v->VRatioPrefetchC,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2979
v->swath_width_luma_ub,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2980
v->swath_width_chroma_ub,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2981
v->DPPPerPlane,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2982
v->HRatio,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2983
v->HRatioChroma,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2984
v->PixelClock,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2985
v->PSCL_THROUGHPUT_LUMA,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2986
v->PSCL_THROUGHPUT_CHROMA,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2987
v->DPPCLK,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2988
v->BytePerPixelC,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2989
v->SourceScan,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2990
v->NumberOfCursors,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2991
v->CursorWidth,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2992
v->CursorBPP,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2993
v->BlockWidth256BytesY,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2994
v->BlockHeight256BytesY,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2995
v->BlockWidth256BytesC,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2996
v->BlockHeight256BytesC,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2997
v->DisplayPipeLineDeliveryTimeLuma,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2998
v->DisplayPipeLineDeliveryTimeChroma,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
2999
v->DisplayPipeLineDeliveryTimeLumaPrefetch,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3000
v->DisplayPipeLineDeliveryTimeChromaPrefetch,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3001
v->DisplayPipeRequestDeliveryTimeLuma,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3002
v->DisplayPipeRequestDeliveryTimeChroma,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3003
v->DisplayPipeRequestDeliveryTimeLumaPrefetch,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3004
v->DisplayPipeRequestDeliveryTimeChromaPrefetch,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3005
v->CursorRequestDeliveryTime,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3006
v->CursorRequestDeliveryTimePrefetch);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3009
v->NumberOfActivePlanes,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3010
v->GPUVMEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3011
v->MetaChunkSize,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3012
v->MinMetaChunkSizeBytes,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3013
v->HTotal,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3014
v->VRatio,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3015
v->VRatioChroma,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3016
v->DestinationLinesToRequestRowInVBlank,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3017
v->DestinationLinesToRequestRowInImmediateFlip,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3018
v->DCCEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3019
v->PixelClock,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3020
v->BytePerPixelY,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3021
v->BytePerPixelC,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3022
v->SourceScan,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3023
v->dpte_row_height,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3024
v->dpte_row_height_chroma,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3025
v->meta_row_width,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3026
v->meta_row_width_chroma,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3027
v->meta_row_height,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3028
v->meta_row_height_chroma,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3029
v->meta_req_width,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3030
v->meta_req_width_chroma,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3031
v->meta_req_height,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3032
v->meta_req_height_chroma,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3033
v->dpte_group_bytes,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3034
v->PTERequestSizeY,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3035
v->PTERequestSizeC,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3036
v->PixelPTEReqWidthY,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3037
v->PixelPTEReqHeightY,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3038
v->PixelPTEReqWidthC,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3039
v->PixelPTEReqHeightC,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3040
v->dpte_row_width_luma_ub,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3041
v->dpte_row_width_chroma_ub,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3042
v->DST_Y_PER_PTE_ROW_NOM_L,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3043
v->DST_Y_PER_PTE_ROW_NOM_C,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3044
v->DST_Y_PER_META_ROW_NOM_L,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3045
v->DST_Y_PER_META_ROW_NOM_C,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3046
v->TimePerMetaChunkNominal,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3047
v->TimePerChromaMetaChunkNominal,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3048
v->TimePerMetaChunkVBlank,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3049
v->TimePerChromaMetaChunkVBlank,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3050
v->TimePerMetaChunkFlip,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3051
v->TimePerChromaMetaChunkFlip,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3052
v->time_per_pte_group_nom_luma,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3053
v->time_per_pte_group_vblank_luma,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3054
v->time_per_pte_group_flip_luma,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3055
v->time_per_pte_group_nom_chroma,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3056
v->time_per_pte_group_vblank_chroma,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3057
v->time_per_pte_group_flip_chroma);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3060
v->NumberOfActivePlanes,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3061
v->GPUVMEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3062
v->GPUVMMaxPageTableLevels,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3063
v->HTotal,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3064
v->BytePerPixelC,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3065
v->DestinationLinesToRequestVMInVBlank,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3066
v->DestinationLinesToRequestVMInImmediateFlip,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3067
v->DCCEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3068
v->PixelClock,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3069
v->dpte_row_width_luma_ub,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3070
v->dpte_row_width_chroma_ub,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3071
v->vm_group_bytes,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3072
v->dpde0_bytes_per_frame_ub_l,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3073
v->dpde0_bytes_per_frame_ub_c,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3074
v->meta_pte_bytes_per_frame_ub_l,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3075
v->meta_pte_bytes_per_frame_ub_c,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3076
v->TimePerVMGroupVBlank,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3077
v->TimePerVMGroupFlip,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3078
v->TimePerVMRequestVBlank,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3079
v->TimePerVMRequestFlip);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3082
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3084
v->AllowDRAMClockChangeDuringVBlank[k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3085
v->AllowDRAMSelfRefreshDuringVBlank[k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3086
v->MinTTUVBlank[k] = dml_max(
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3087
v->DRAMClockChangeWatermark,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3088
dml_max(v->StutterEnterPlusExitWatermark, v->UrgentWatermark));
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3090
v->AllowDRAMClockChangeDuringVBlank[k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3091
v->AllowDRAMSelfRefreshDuringVBlank[k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3092
v->MinTTUVBlank[k] = dml_max(v->StutterEnterPlusExitWatermark, v->UrgentWatermark);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3094
v->AllowDRAMClockChangeDuringVBlank[k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3095
v->AllowDRAMSelfRefreshDuringVBlank[k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3096
v->MinTTUVBlank[k] = v->UrgentWatermark;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3098
if (!v->DynamicMetadataEnable[k])
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3099
v->MinTTUVBlank[k] = v->TCalc + v->MinTTUVBlank[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3103
v->ActiveDPPs = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3104
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3105
CalculateDCCConfiguration(v->DCCEnable[k], false, // We should always know the direction DCCProgrammingAssumesScanDirectionUnknown,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3106
v->SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3107
v->SurfaceWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3108
v->SurfaceWidthC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3109
v->SurfaceHeightY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3110
v->SurfaceHeightC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3111
v->DETBufferSizeInKByte[k] * 1024,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3112
v->BlockHeight256BytesY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3113
v->BlockHeight256BytesC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3114
v->SurfaceTiling[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3115
v->BytePerPixelY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3116
v->BytePerPixelC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3117
v->BytePerPixelDETY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3118
v->BytePerPixelDETC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3119
v->SourceScan[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3120
&v->DCCYMaxUncompressedBlock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3121
&v->DCCCMaxUncompressedBlock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3122
&v->DCCYMaxCompressedBlock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3123
&v->DCCCMaxCompressedBlock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3124
&v->DCCYIndependentBlock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3125
&v->DCCCIndependentBlock[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3129
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3131
double Tvstartup_margin = (v->MaxVStartupLines[k] - v->VStartup[k]) * v->HTotal[k] / v->PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3133
dml_print("DML::%s: k=%d, MinTTUVBlank = %f (before margin)\n", __func__, k, v->MinTTUVBlank[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3136
v->MinTTUVBlank[k] = v->MinTTUVBlank[k] + Tvstartup_margin;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3140
dml_print("DML::%s: k=%d, MaxVStartupLines = %d\n", __func__, k, v->MaxVStartupLines[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3141
dml_print("DML::%s: k=%d, VStartup = %d\n", __func__, k, v->VStartup[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3142
dml_print("DML::%s: k=%d, MinTTUVBlank = %f\n", __func__, k, v->MinTTUVBlank[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3145
v->Tdmdl[k] = v->Tdmdl[k] + Tvstartup_margin;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3146
if (v->DynamicMetadataEnable[k] && v->DynamicMetadataVMEnabled) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3147
v->Tdmdl_vm[k] = v->Tdmdl_vm[k] + Tvstartup_margin;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3150
isInterlaceTiming = (v->Interlace[k] && !v->ProgressiveToInterlaceUnitInOPP);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3152
v->MIN_DST_Y_NEXT_START[k] = ((isInterlaceTiming ? dml_floor((v->VTotal[k] - v->VFrontPorch[k]) / 2.0, 1.0) : v->VTotal[k])
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3153
- v->VFrontPorch[k])
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3154
+ dml_max(1.0, dml_ceil(v->WritebackDelay[v->VoltageLevel][k] / (v->HTotal[k] / v->PixelClock[k]), 1.0))
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3155
+ dml_floor(4.0 * v->TSetup[k] / (v->HTotal[k] / v->PixelClock[k]), 1.0) / 4.0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3157
v->VStartup[k] = (isInterlaceTiming ? (2 * v->MaxVStartupLines[k]) : v->MaxVStartupLines[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3159
if (((v->VUpdateOffsetPix[k] + v->VUpdateWidthPix[k] + v->VReadyOffsetPix[k]) / v->HTotal[k])
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3161
dml_floor((v->VTotal[k] - v->VActive[k] - v->VFrontPorch[k] - v->VStartup[k]) / 2.0, 1.0) :
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3162
(int) (v->VTotal[k] - v->VActive[k] - v->VFrontPorch[k] - v->VStartup[k]))) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3163
v->VREADY_AT_OR_AFTER_VSYNC[k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3165
v->VREADY_AT_OR_AFTER_VSYNC[k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3168
dml_print("DML::%s: k=%d, VStartup = %d (max)\n", __func__, k, v->VStartup[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3169
dml_print("DML::%s: k=%d, VUpdateOffsetPix = %d\n", __func__, k, v->VUpdateOffsetPix[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3170
dml_print("DML::%s: k=%d, VUpdateWidthPix = %d\n", __func__, k, v->VUpdateWidthPix[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3171
dml_print("DML::%s: k=%d, VReadyOffsetPix = %d\n", __func__, k, v->VReadyOffsetPix[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3172
dml_print("DML::%s: k=%d, HTotal = %d\n", __func__, k, v->HTotal[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3173
dml_print("DML::%s: k=%d, VTotal = %d\n", __func__, k, v->VTotal[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3174
dml_print("DML::%s: k=%d, VActive = %d\n", __func__, k, v->VActive[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3175
dml_print("DML::%s: k=%d, VFrontPorch = %d\n", __func__, k, v->VFrontPorch[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3176
dml_print("DML::%s: k=%d, VStartup = %d\n", __func__, k, v->VStartup[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3177
dml_print("DML::%s: k=%d, MIN_DST_Y_NEXT_START = %f\n", __func__, k, v->MIN_DST_Y_NEXT_START[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3178
dml_print("DML::%s: k=%d, VREADY_AT_OR_AFTER_VSYNC = %d\n", __func__, k, v->VREADY_AT_OR_AFTER_VSYNC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3187
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3188
if (v->WritebackEnable[k] == true && v->WritebackPixelFormat[k] == dm_444_32) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3189
WRBandwidth = v->WritebackDestinationWidth[k] * v->WritebackDestinationHeight[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3190
/ (v->HTotal[k] * v->WritebackSourceHeight[k] / v->PixelClock[k]) * 4;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3191
} else if (v->WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3192
WRBandwidth = v->WritebackDestinationWidth[k] * v->WritebackDestinationHeight[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3193
/ (v->HTotal[k] * v->WritebackSourceHeight[k] / v->PixelClock[k]) * 8;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3199
v->TotalDataReadBandwidth = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3200
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3201
v->TotalDataReadBandwidth = v->TotalDataReadBandwidth + v->ReadBandwidthPlaneLuma[k] + v->ReadBandwidthPlaneChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3207
v->CompressedBufferSizeInkByte,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3208
v->UnboundedRequestEnabled,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3209
v->ConfigReturnBufferSizeInKByte,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3210
v->MetaFIFOSizeInKEntries,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3211
v->ZeroSizeBufferEntries,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3212
v->NumberOfActivePlanes,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3213
v->ROBBufferSizeInKByte,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3214
v->TotalDataReadBandwidth,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3215
v->DCFCLK,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3216
v->ReturnBW,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3217
v->COMPBUF_RESERVED_SPACE_64B,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3218
v->COMPBUF_RESERVED_SPACE_ZS,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3219
v->SRExitTime,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3220
v->SRExitZ8Time,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3221
v->SynchronizedVBlank,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3222
v->StutterEnterPlusExitWatermark,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3223
v->Z8StutterEnterPlusExitWatermark,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3224
v->ProgressiveToInterlaceUnitInOPP,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3225
v->Interlace,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3226
v->MinTTUVBlank,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3227
v->DPPPerPlane,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3228
v->DETBufferSizeY,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3229
v->BytePerPixelY,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3230
v->BytePerPixelDETY,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3231
v->SwathWidthY,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3232
v->SwathHeightY,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3233
v->SwathHeightC,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3234
v->DCCRateLuma,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3235
v->DCCRateChroma,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3236
v->DCCFractionOfZeroSizeRequestsLuma,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3237
v->DCCFractionOfZeroSizeRequestsChroma,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3238
v->HTotal,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3239
v->VTotal,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3240
v->PixelClock,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3241
v->VRatio,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3242
v->SourceScan,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3243
v->BlockHeight256BytesY,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3244
v->BlockWidth256BytesY,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3245
v->BlockHeight256BytesC,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3246
v->BlockWidth256BytesC,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3247
v->DCCYMaxUncompressedBlock,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3248
v->DCCCMaxUncompressedBlock,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3249
v->VActive,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3250
v->DCCEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3251
v->WritebackEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3252
v->ReadBandwidthPlaneLuma,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3253
v->ReadBandwidthPlaneChroma,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3254
v->meta_row_bw,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3255
v->dpte_row_bw,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3256
&v->StutterEfficiencyNotIncludingVBlank,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3257
&v->StutterEfficiency,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3258
&v->NumberOfStutterBurstsPerFrame,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3259
&v->Z8StutterEfficiencyNotIncludingVBlank,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3260
&v->Z8StutterEfficiency,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3261
&v->Z8NumberOfStutterBurstsPerFrame,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3262
&v->StutterPeriod);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3267
struct vba_vars_st *v = &mode_lib->vba;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3288
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3291
v->SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3292
v->SurfaceTiling[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3305
v->NumberOfActivePlanes,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3306
mode_lib->project == DML_PROJECT_DCN315 && v->DETSizeOverride[0],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3307
v->DETBufferSizeInKByte,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3310
v->SourceScan,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3311
v->SourcePixelFormat,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3312
v->SurfaceTiling,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3313
v->ViewportWidth,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3314
v->ViewportHeight,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3315
v->SurfaceWidthY,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3316
v->SurfaceWidthC,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3317
v->SurfaceHeightY,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3318
v->SurfaceHeightC,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3323
v->ODMCombineEnabled,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3324
v->BlendingAndTiming,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3329
v->HActive,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3330
v->HRatio,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3331
v->HRatioChroma,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3332
v->DPPPerPlane,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3337
v->SwathHeightY,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3338
v->SwathHeightC,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3339
v->DETBufferSizeY,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3340
v->DETBufferSizeC,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3492
struct vba_vars_st *v = &mode_lib->vba;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3498
double LineTime = v->HTotal[k] / v->PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3500
if (v->GPUVMEnable == true && v->HostVMEnable == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3501
HostVMDynamicLevelsTrips = v->HostVMMaxNonCachedPageTableLevels;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3506
if (v->GPUVMEnable == true || v->DCCEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3507
ImmediateFlipBW = (PDEAndMetaPTEBytesPerFrame + MetaRowBytes + DPTEBytesPerRow) * v->BandwidthAvailableForImmediateFlip / v->TotImmediateFlipBytes;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3510
if (v->GPUVMEnable == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3512
v->Tno_bw[k] + PDEAndMetaPTEBytesPerFrame * HostVMInefficiencyFactor / ImmediateFlipBW,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3513
UrgentExtraLatency + UrgentLatency * (v->GPUVMMaxPageTableLevels * (HostVMDynamicLevelsTrips + 1) - 1),
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3519
v->DestinationLinesToRequestVMInImmediateFlip[k] = dml_ceil(4.0 * (TimeForFetchingMetaPTEImmediateFlip / LineTime), 1) / 4.0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3520
if ((v->GPUVMEnable == true || v->DCCEnable[k] == true)) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3529
v->DestinationLinesToRequestRowInImmediateFlip[k] = dml_ceil(4.0 * (TimeForFetchingRowInVBlankImmediateFlip / LineTime), 1) / 4.0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3531
if (v->GPUVMEnable == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3532
v->final_flip_bw[k] = dml_max(
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3533
PDEAndMetaPTEBytesPerFrame * HostVMInefficiencyFactor / (v->DestinationLinesToRequestVMInImmediateFlip[k] * LineTime),
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3534
(MetaRowBytes + DPTEBytesPerRow * HostVMInefficiencyFactor) / (v->DestinationLinesToRequestRowInImmediateFlip[k] * LineTime));
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3535
} else if ((v->GPUVMEnable == true || v->DCCEnable[k] == true)) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3536
v->final_flip_bw[k] = (MetaRowBytes + DPTEBytesPerRow * HostVMInefficiencyFactor) / (v->DestinationLinesToRequestRowInImmediateFlip[k] * LineTime);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3538
v->final_flip_bw[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3541
if (v->SourcePixelFormat[k] == dm_420_8 || v->SourcePixelFormat[k] == dm_420_10 || v->SourcePixelFormat[k] == dm_rgbe_alpha) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3542
if (v->GPUVMEnable == true && v->DCCEnable[k] != true) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3543
min_row_time = dml_min(v->dpte_row_height[k] * LineTime / v->VRatio[k], v->dpte_row_height_chroma[k] * LineTime / v->VRatioChroma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3544
} else if (v->GPUVMEnable != true && v->DCCEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3545
min_row_time = dml_min(v->meta_row_height[k] * LineTime / v->VRatio[k], v->meta_row_height_chroma[k] * LineTime / v->VRatioChroma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3548
v->dpte_row_height[k] * LineTime / v->VRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3549
v->meta_row_height[k] * LineTime / v->VRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3550
v->dpte_row_height_chroma[k] * LineTime / v->VRatioChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3551
v->meta_row_height_chroma[k] * LineTime / v->VRatioChroma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3554
if (v->GPUVMEnable == true && v->DCCEnable[k] != true) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3555
min_row_time = v->dpte_row_height[k] * LineTime / v->VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3556
} else if (v->GPUVMEnable != true && v->DCCEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3557
min_row_time = v->meta_row_height[k] * LineTime / v->VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3559
min_row_time = dml_min(v->dpte_row_height[k] * LineTime / v->VRatio[k], v->meta_row_height[k] * LineTime / v->VRatio[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3563
if (v->DestinationLinesToRequestVMInImmediateFlip[k] >= 32 || v->DestinationLinesToRequestRowInImmediateFlip[k] >= 16
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3565
v->ImmediateFlipSupportedForPipe[k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3567
v->ImmediateFlipSupportedForPipe[k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3571
dml_print("DML::%s: DestinationLinesToRequestVMInImmediateFlip = %f\n", __func__, v->DestinationLinesToRequestVMInImmediateFlip[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3572
dml_print("DML::%s: DestinationLinesToRequestRowInImmediateFlip = %f\n", __func__, v->DestinationLinesToRequestRowInImmediateFlip[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3576
dml_print("DML::%s: ImmediateFlipSupportedForPipe = %d\n", __func__, v->ImmediateFlipSupportedForPipe[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3680
struct vba_vars_st *v = &mode_lib->vba;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3683
myPipe.DPPCLK = v->RequiredDPPCLK[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3684
myPipe.DISPCLK = v->RequiredDISPCLK[i][j];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3685
myPipe.PixelClock = v->PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3686
myPipe.DCFCLKDeepSleep = v->ProjectedDCFCLKDeepSleep[i][j];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3687
myPipe.DPPPerPlane = v->NoOfDPP[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3688
myPipe.ScalerEnabled = v->ScalerEnabled[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3692
myPipe.SourceScan = v->SourceScan[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3693
myPipe.BlockWidth256BytesY = v->Read256BlockWidthY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3694
myPipe.BlockHeight256BytesY = v->Read256BlockHeightY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3695
myPipe.BlockWidth256BytesC = v->Read256BlockWidthC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3696
myPipe.BlockHeight256BytesC = v->Read256BlockHeightC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3697
myPipe.InterlaceEnable = v->Interlace[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3698
myPipe.NumberOfCursors = v->NumberOfCursors[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3699
myPipe.VBlank = v->VTotal[k] - v->VActive[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3700
myPipe.HTotal = v->HTotal[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3701
myPipe.DCCEnable = v->DCCEnable[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3702
myPipe.ODMCombineIsEnabled = v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3703
|| v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3704
myPipe.SourcePixelFormat = v->SourcePixelFormat[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3705
myPipe.BytePerPixelY = v->BytePerPixelY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3706
myPipe.BytePerPixelC = v->BytePerPixelC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3707
myPipe.ProgressiveToInterlaceUnitInOPP = v->ProgressiveToInterlaceUnitInOPP;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3708
v->NoTimeForPrefetch[i][j][k] = CalculatePrefetchSchedule(
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3712
v->DSCDelayPerState[i][k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3713
v->DPPCLKDelaySubtotal + v->DPPCLKDelayCNVCFormater,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3714
v->DPPCLKDelaySCL,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3715
v->DPPCLKDelaySCLLBOnly,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3716
v->DPPCLKDelayCNVCCursor,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3717
v->DISPCLKDelaySubtotal,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3718
v->SwathWidthYThisState[k] / v->HRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3719
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3720
v->MaxInterDCNTileRepeaters,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3721
dml_min(v->MaxVStartup, v->MaximumVStartup[i][j][k]),
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3722
v->MaximumVStartup[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3723
v->GPUVMMaxPageTableLevels,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3724
v->GPUVMEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3725
v->HostVMEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3726
v->HostVMMaxNonCachedPageTableLevels,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3727
v->HostVMMinPageSize,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3728
v->DynamicMetadataEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3729
v->DynamicMetadataVMEnabled,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3730
v->DynamicMetadataLinesBeforeActiveRequired[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3731
v->DynamicMetadataTransmittedBytes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3732
v->UrgLatency[i],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3733
v->ExtraLatency,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3734
v->TimeCalc,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3735
v->PDEAndMetaPTEBytesPerFrame[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3736
v->MetaRowBytes[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3737
v->DPTEBytesPerRow[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3738
v->PrefetchLinesY[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3739
v->SwathWidthYThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3740
v->PrefillY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3741
v->MaxNumSwY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3742
v->PrefetchLinesC[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3743
v->SwathWidthCThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3744
v->PrefillC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3745
v->MaxNumSwC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3746
v->swath_width_luma_ub_this_state[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3747
v->swath_width_chroma_ub_this_state[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3748
v->SwathHeightYThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3749
v->SwathHeightCThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3750
v->TWait,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3751
&v->DSTXAfterScaler[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3752
&v->DSTYAfterScaler[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3753
&v->LineTimesForPrefetch[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3754
&v->PrefetchBW[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3755
&v->LinesForMetaPTE[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3756
&v->LinesForMetaAndDPTERow[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3757
&v->VRatioPreY[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3758
&v->VRatioPreC[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3759
&v->RequiredPrefetchPixelDataBWLuma[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3760
&v->RequiredPrefetchPixelDataBWChroma[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3761
&v->NoTimeForDynamicMetadata[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3762
&v->Tno_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3763
&v->prefetch_vmrow_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3764
&v->dummy7[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3765
&v->dummy8[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3766
&v->dummy13[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3767
&v->VUpdateOffsetPix[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3768
&v->VUpdateWidthPix[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3769
&v->VReadyOffsetPix[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3787
struct vba_vars_st *v = &mode_lib->vba;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3810
v->ScaleRatioAndTapsSupport = true;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3811
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3812
if (v->ScalerEnabled[k] == false
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3813
&& ((v->SourcePixelFormat[k] != dm_444_64 && v->SourcePixelFormat[k] != dm_444_32
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3814
&& v->SourcePixelFormat[k] != dm_444_16 && v->SourcePixelFormat[k] != dm_mono_16
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3815
&& v->SourcePixelFormat[k] != dm_mono_8 && v->SourcePixelFormat[k] != dm_rgbe
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3816
&& v->SourcePixelFormat[k] != dm_rgbe_alpha) || v->HRatio[k] != 1.0 || v->htaps[k] != 1.0
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3817
|| v->VRatio[k] != 1.0 || v->vtaps[k] != 1.0)) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3818
v->ScaleRatioAndTapsSupport = false;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3819
} else if (v->vtaps[k] < 1.0 || v->vtaps[k] > 8.0 || v->htaps[k] < 1.0 || v->htaps[k] > 8.0
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3820
|| (v->htaps[k] > 1.0 && (v->htaps[k] % 2) == 1) || v->HRatio[k] > v->MaxHSCLRatio
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3821
|| v->VRatio[k] > v->MaxVSCLRatio || v->HRatio[k] > v->htaps[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3822
|| v->VRatio[k] > v->vtaps[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3823
|| (v->SourcePixelFormat[k] != dm_444_64 && v->SourcePixelFormat[k] != dm_444_32
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3824
&& v->SourcePixelFormat[k] != dm_444_16 && v->SourcePixelFormat[k] != dm_mono_16
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3825
&& v->SourcePixelFormat[k] != dm_mono_8 && v->SourcePixelFormat[k] != dm_rgbe
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3826
&& (v->VTAPsChroma[k] < 1 || v->VTAPsChroma[k] > 8 || v->HTAPsChroma[k] < 1
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3827
|| v->HTAPsChroma[k] > 8 || (v->HTAPsChroma[k] > 1 && v->HTAPsChroma[k] % 2 == 1)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3828
|| v->HRatioChroma[k] > v->MaxHSCLRatio
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3829
|| v->VRatioChroma[k] > v->MaxVSCLRatio
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3830
|| v->HRatioChroma[k] > v->HTAPsChroma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3831
|| v->VRatioChroma[k] > v->VTAPsChroma[k]))) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3832
v->ScaleRatioAndTapsSupport = false;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3837
v->SourceFormatPixelAndScanSupport = true;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3838
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3839
if ((v->SurfaceTiling[k] == dm_sw_linear && (!(v->SourceScan[k] != dm_vert) || v->DCCEnable[k] == true))
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3840
|| ((v->SurfaceTiling[k] == dm_sw_64kb_d || v->SurfaceTiling[k] == dm_sw_64kb_d_t
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3841
|| v->SurfaceTiling[k] == dm_sw_64kb_d_x) && !(v->SourcePixelFormat[k] == dm_444_64))) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3842
v->SourceFormatPixelAndScanSupport = false;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3847
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3849
v->SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3850
v->SurfaceTiling[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3851
&v->BytePerPixelY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3852
&v->BytePerPixelC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3853
&v->BytePerPixelInDETY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3854
&v->BytePerPixelInDETC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3855
&v->Read256BlockHeightY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3856
&v->Read256BlockHeightC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3857
&v->Read256BlockWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3858
&v->Read256BlockWidthC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3860
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3861
if (v->SourceScan[k] != dm_vert) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3862
v->SwathWidthYSingleDPP[k] = v->ViewportWidth[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3863
v->SwathWidthCSingleDPP[k] = v->ViewportWidthChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3865
v->SwathWidthYSingleDPP[k] = v->ViewportHeight[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3866
v->SwathWidthCSingleDPP[k] = v->ViewportHeightChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3869
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3870
v->ReadBandwidthLuma[k] = v->SwathWidthYSingleDPP[k] * dml_ceil(v->BytePerPixelInDETY[k], 1.0)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3871
/ (v->HTotal[k] / v->PixelClock[k]) * v->VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3872
v->ReadBandwidthChroma[k] = v->SwathWidthYSingleDPP[k] / 2 * dml_ceil(v->BytePerPixelInDETC[k], 2.0)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3873
/ (v->HTotal[k] / v->PixelClock[k]) * v->VRatio[k] / 2.0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3875
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3876
if (v->WritebackEnable[k] == true && v->WritebackPixelFormat[k] == dm_444_64) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3877
v->WriteBandwidth[k] = v->WritebackDestinationWidth[k] * v->WritebackDestinationHeight[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3878
/ (v->WritebackSourceHeight[k] * v->HTotal[k] / v->PixelClock[k]) * 8.0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3879
} else if (v->WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3880
v->WriteBandwidth[k] = v->WritebackDestinationWidth[k] * v->WritebackDestinationHeight[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3881
/ (v->WritebackSourceHeight[k] * v->HTotal[k] / v->PixelClock[k]) * 4.0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3883
v->WriteBandwidth[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3889
v->WritebackLatencySupport = true;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3890
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3891
if (v->WritebackEnable[k] == true && (v->WriteBandwidth[k] > v->WritebackInterfaceBufferSize * 1024 / v->WritebackLatency)) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3892
v->WritebackLatencySupport = false;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3898
v->TotalNumberOfActiveWriteback = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3899
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3900
if (v->WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3901
v->TotalNumberOfActiveWriteback = v->TotalNumberOfActiveWriteback + 1;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3905
if (v->TotalNumberOfActiveWriteback > v->MaxNumWriteback) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3911
v->WritebackScaleRatioAndTapsSupport = true;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3912
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3913
if (v->WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3914
if (v->WritebackHRatio[k] > v->WritebackMaxHSCLRatio || v->WritebackVRatio[k] > v->WritebackMaxVSCLRatio
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3915
|| v->WritebackHRatio[k] < v->WritebackMinHSCLRatio
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3916
|| v->WritebackVRatio[k] < v->WritebackMinVSCLRatio
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3917
|| v->WritebackHTaps[k] > v->WritebackMaxHSCLTaps
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3918
|| v->WritebackVTaps[k] > v->WritebackMaxVSCLTaps
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3919
|| v->WritebackHRatio[k] > v->WritebackHTaps[k] || v->WritebackVRatio[k] > v->WritebackVTaps[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3920
|| (v->WritebackHTaps[k] > 2.0 && ((v->WritebackHTaps[k] % 2) == 1))) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3921
v->WritebackScaleRatioAndTapsSupport = false;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3923
if (2.0 * v->WritebackDestinationWidth[k] * (v->WritebackVTaps[k] - 1) * 57 > v->WritebackLineBufferSize) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3924
v->WritebackScaleRatioAndTapsSupport = false;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3930
v->WritebackRequiredDISPCLK = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3931
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3932
if (v->WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3933
v->WritebackRequiredDISPCLK = dml_max(
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3934
v->WritebackRequiredDISPCLK,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3936
v->WritebackPixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3937
v->PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3938
v->WritebackHRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3939
v->WritebackVRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3940
v->WritebackHTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3941
v->WritebackVTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3942
v->WritebackSourceWidth[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3943
v->WritebackDestinationWidth[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3944
v->HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3945
v->WritebackLineBufferSize));
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3948
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3949
if (v->HRatio[k] > 1.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3950
v->PSCL_FACTOR[k] = dml_min(
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3951
v->MaxDCHUBToPSCLThroughput,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3952
v->MaxPSCLToLBThroughput * v->HRatio[k] / dml_ceil(v->htaps[k] / 6.0, 1.0));
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3954
v->PSCL_FACTOR[k] = dml_min(v->MaxDCHUBToPSCLThroughput, v->MaxPSCLToLBThroughput);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3956
if (v->BytePerPixelC[k] == 0.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3957
v->PSCL_FACTOR_CHROMA[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3958
v->MinDPPCLKUsingSingleDPP[k] = v->PixelClock[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3960
v->vtaps[k] / 6.0 * dml_min(1.0, v->HRatio[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3961
v->HRatio[k] * v->VRatio[k] / v->PSCL_FACTOR[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3963
if ((v->htaps[k] > 6.0 || v->vtaps[k] > 6.0) && v->MinDPPCLKUsingSingleDPP[k] < 2.0 * v->PixelClock[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3964
v->MinDPPCLKUsingSingleDPP[k] = 2.0 * v->PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3967
if (v->HRatioChroma[k] > 1.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3968
v->PSCL_FACTOR_CHROMA[k] = dml_min(
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3969
v->MaxDCHUBToPSCLThroughput,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3970
v->MaxPSCLToLBThroughput * v->HRatioChroma[k] / dml_ceil(v->HTAPsChroma[k] / 6.0, 1.0));
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3972
v->PSCL_FACTOR_CHROMA[k] = dml_min(v->MaxDCHUBToPSCLThroughput, v->MaxPSCLToLBThroughput);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3974
v->MinDPPCLKUsingSingleDPP[k] = v->PixelClock[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3976
v->vtaps[k] / 6.0 * dml_min(1.0, v->HRatio[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3977
v->HRatio[k] * v->VRatio[k] / v->PSCL_FACTOR[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3978
v->VTAPsChroma[k] / 6.0 * dml_min(1.0, v->HRatioChroma[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3979
v->HRatioChroma[k] * v->VRatioChroma[k] / v->PSCL_FACTOR_CHROMA[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3981
if ((v->htaps[k] > 6.0 || v->vtaps[k] > 6.0 || v->HTAPsChroma[k] > 6.0 || v->VTAPsChroma[k] > 6.0)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3982
&& v->MinDPPCLKUsingSingleDPP[k] < 2.0 * v->PixelClock[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3983
v->MinDPPCLKUsingSingleDPP[k] = 2.0 * v->PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3987
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3991
if (v->SurfaceTiling[k] == dm_sw_linear) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3993
} else if (v->SourceScan[k] == dm_vert && v->BytePerPixelC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
3995
} else if (v->SourcePixelFormat[k] == dm_rgbe_alpha) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4001
if (v->SourcePixelFormat[k] == dm_420_8 || v->SourcePixelFormat[k] == dm_420_10 || v->SourcePixelFormat[k] == dm_420_12) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4006
v->MaximumSwathWidthInLineBufferLuma = v->LineBufferSize * dml_max(v->HRatio[k], 1.0) / v->LBBitPerPixel[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4007
/ (v->vtaps[k] + dml_max(dml_ceil(v->VRatio[k], 1.0) - 2, 0.0));
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4008
if (v->BytePerPixelC[k] == 0.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4009
v->MaximumSwathWidthInLineBufferChroma = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4011
v->MaximumSwathWidthInLineBufferChroma = v->LineBufferSize * dml_max(v->HRatioChroma[k], 1.0) / v->LBBitPerPixel[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4012
/ (v->VTAPsChroma[k] + dml_max(dml_ceil(v->VRatioChroma[k], 1.0) - 2, 0.0));
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4014
v->MaximumSwathWidthLuma[k] = dml_min(MaximumSwathWidthSupportLuma, v->MaximumSwathWidthInLineBufferLuma);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4015
v->MaximumSwathWidthChroma[k] = dml_min(MaximumSwathWidthSupportChroma, v->MaximumSwathWidthInLineBufferChroma);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4020
v->NumberOfActivePlanes,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4021
mode_lib->project == DML_PROJECT_DCN315 && v->DETSizeOverride[0],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4022
v->DETBufferSizeInKByte,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4023
v->MaximumSwathWidthLuma,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4024
v->MaximumSwathWidthChroma,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4025
v->SourceScan,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4026
v->SourcePixelFormat,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4027
v->SurfaceTiling,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4028
v->ViewportWidth,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4029
v->ViewportHeight,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4030
v->SurfaceWidthY,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4031
v->SurfaceWidthC,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4032
v->SurfaceHeightY,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4033
v->SurfaceHeightC,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4034
v->Read256BlockHeightY,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4035
v->Read256BlockHeightC,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4036
v->Read256BlockWidthY,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4037
v->Read256BlockWidthC,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4038
v->odm_combine_dummy,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4039
v->BlendingAndTiming,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4040
v->BytePerPixelY,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4041
v->BytePerPixelC,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4042
v->BytePerPixelInDETY,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4043
v->BytePerPixelInDETC,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4044
v->HActive,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4045
v->HRatio,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4046
v->HRatioChroma,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4047
v->NoOfDPPThisState,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4048
v->swath_width_luma_ub_this_state,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4049
v->swath_width_chroma_ub_this_state,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4050
v->SwathWidthYThisState,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4051
v->SwathWidthCThisState,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4052
v->SwathHeightYThisState,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4053
v->SwathHeightCThisState,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4054
v->DETBufferSizeYThisState,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4055
v->DETBufferSizeCThisState,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4056
v->SingleDPPViewportSizeSupportPerPlane,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4057
&v->ViewportSizeSupport[0][0]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4059
for (i = 0; i < v->soc.num_states; i++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4061
v->MaxDispclkRoundedDownToDFSGranularity = RoundToDFSGranularityDown(v->MaxDispclk[i], v->DISPCLKDPPCLKVCOSpeed);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4062
v->MaxDppclkRoundedDownToDFSGranularity = RoundToDFSGranularityDown(v->MaxDppclk[i], v->DISPCLKDPPCLKVCOSpeed);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4063
v->RequiredDISPCLK[i][j] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4064
v->DISPCLK_DPPCLK_Support[i][j] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4065
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4066
v->PlaneRequiredDISPCLKWithoutODMCombine = v->PixelClock[k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4067
* (1.0 + v->DISPCLKRampingMargin / 100.0);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4068
if ((v->PlaneRequiredDISPCLKWithoutODMCombine >= v->MaxDispclk[i]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4069
&& v->MaxDispclk[i] == v->MaxDispclk[v->soc.num_states - 1]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4070
&& v->MaxDppclk[i] == v->MaxDppclk[v->soc.num_states - 1])) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4071
v->PlaneRequiredDISPCLKWithoutODMCombine = v->PixelClock[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4072
* (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4074
v->PlaneRequiredDISPCLKWithODMCombine2To1 = v->PixelClock[k] / 2 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4075
* (1 + v->DISPCLKRampingMargin / 100.0);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4076
if ((v->PlaneRequiredDISPCLKWithODMCombine2To1 >= v->MaxDispclk[i]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4077
&& v->MaxDispclk[i] == v->MaxDispclk[v->soc.num_states - 1]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4078
&& v->MaxDppclk[i] == v->MaxDppclk[v->soc.num_states - 1])) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4079
v->PlaneRequiredDISPCLKWithODMCombine2To1 = v->PixelClock[k] / 2
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4080
* (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4082
v->PlaneRequiredDISPCLKWithODMCombine4To1 = v->PixelClock[k] / 4 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4083
* (1 + v->DISPCLKRampingMargin / 100.0);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4084
if ((v->PlaneRequiredDISPCLKWithODMCombine4To1 >= v->MaxDispclk[i]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4085
&& v->MaxDispclk[i] == v->MaxDispclk[v->soc.num_states - 1]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4086
&& v->MaxDppclk[i] == v->MaxDppclk[v->soc.num_states - 1])) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4087
v->PlaneRequiredDISPCLKWithODMCombine4To1 = v->PixelClock[k] / 4
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4088
* (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4091
if (v->ODMCombinePolicy == dm_odm_combine_policy_none
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4092
|| !(v->Output[k] == dm_dp ||
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4093
v->Output[k] == dm_dp2p0 ||
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4094
v->Output[k] == dm_edp)) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4095
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_disabled;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4096
v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithoutODMCombine;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4098
if (v->HActive[k] / 2 > DCN31_MAX_FMT_420_BUFFER_WIDTH)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4100
} else if (v->ODMCombinePolicy == dm_odm_combine_policy_2to1) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4101
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4102
v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithODMCombine2To1;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4103
} else if (v->ODMCombinePolicy == dm_odm_combine_policy_4to1
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4104
|| v->PlaneRequiredDISPCLKWithODMCombine2To1 > v->MaxDispclkRoundedDownToDFSGranularity) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4105
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_4to1;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4106
v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithODMCombine4To1;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4107
} else if (v->PlaneRequiredDISPCLKWithoutODMCombine > v->MaxDispclkRoundedDownToDFSGranularity) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4108
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4109
v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithODMCombine2To1;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4111
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_disabled;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4112
v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithoutODMCombine;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4114
if (v->DSCEnabled[k] && v->HActive[k] > DCN31_MAX_DSC_IMAGE_WIDTH
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4115
&& v->ODMCombineEnablePerState[i][k] != dm_odm_combine_mode_4to1) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4116
if (v->HActive[k] / 2 > DCN31_MAX_DSC_IMAGE_WIDTH) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4117
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_4to1;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4118
v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithODMCombine4To1;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4120
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4121
v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithODMCombine2To1;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4124
if (v->OutputFormat[k] == dm_420 && v->HActive[k] > DCN31_MAX_FMT_420_BUFFER_WIDTH
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4125
&& v->ODMCombineEnablePerState[i][k] != dm_odm_combine_mode_4to1) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4126
if (v->Output[k] == dm_hdmi) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4128
} else if (v->HActive[k] / 2 > DCN31_MAX_FMT_420_BUFFER_WIDTH) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4129
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_4to1;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4130
v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithODMCombine4To1;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4132
if (v->HActive[k] / 4 > DCN31_MAX_FMT_420_BUFFER_WIDTH)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4135
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4136
v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithODMCombine2To1;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4139
if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4140
v->MPCCombine[i][j][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4141
v->NoOfDPP[i][j][k] = 4;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4142
v->RequiredDPPCLK[i][j][k] = v->MinDPPCLKUsingSingleDPP[k] * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) / 4;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4143
} else if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4144
v->MPCCombine[i][j][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4145
v->NoOfDPP[i][j][k] = 2;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4146
v->RequiredDPPCLK[i][j][k] = v->MinDPPCLKUsingSingleDPP[k] * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) / 2;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4147
} else if ((v->WhenToDoMPCCombine == dm_mpc_never
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4148
|| (v->MinDPPCLKUsingSingleDPP[k] * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4149
<= v->MaxDppclkRoundedDownToDFSGranularity && v->SingleDPPViewportSizeSupportPerPlane[k] == true))) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4150
v->MPCCombine[i][j][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4151
v->NoOfDPP[i][j][k] = 1;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4152
v->RequiredDPPCLK[i][j][k] = v->MinDPPCLKUsingSingleDPP[k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4154
v->MPCCombine[i][j][k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4155
v->NoOfDPP[i][j][k] = 2;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4156
v->RequiredDPPCLK[i][j][k] = v->MinDPPCLKUsingSingleDPP[k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) / 2.0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4158
v->RequiredDISPCLK[i][j] = dml_max(v->RequiredDISPCLK[i][j], v->PlaneRequiredDISPCLK);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4159
if ((v->MinDPPCLKUsingSingleDPP[k] / v->NoOfDPP[i][j][k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4160
> v->MaxDppclkRoundedDownToDFSGranularity)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4161
|| (v->PlaneRequiredDISPCLK > v->MaxDispclkRoundedDownToDFSGranularity)) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4162
v->DISPCLK_DPPCLK_Support[i][j] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4164
if (mode_lib->project == DML_PROJECT_DCN315 && v->DETSizeOverride[k] > DCN3_15_MAX_DET_SIZE && v->NoOfDPP[i][j][k] < 2) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4165
v->MPCCombine[i][j][k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4166
v->NoOfDPP[i][j][k] = 2;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4169
v->TotalNumberOfActiveDPP[i][j] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4170
v->TotalNumberOfSingleDPPPlanes[i][j] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4171
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4172
v->TotalNumberOfActiveDPP[i][j] = v->TotalNumberOfActiveDPP[i][j] + v->NoOfDPP[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4173
if (v->NoOfDPP[i][j][k] == 1)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4174
v->TotalNumberOfSingleDPPPlanes[i][j] = v->TotalNumberOfSingleDPPPlanes[i][j] + 1;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4175
if (v->SourcePixelFormat[k] == dm_420_8 || v->SourcePixelFormat[k] == dm_420_10
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4176
|| v->SourcePixelFormat[k] == dm_420_12 || v->SourcePixelFormat[k] == dm_rgbe_alpha)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4181
if (j == 1 && v->WhenToDoMPCCombine != dm_mpc_never
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4182
&& !UnboundedRequest(v->UseUnboundedRequesting, v->TotalNumberOfActiveDPP[i][j], NoChroma, v->Output[0])) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4183
while (!(v->TotalNumberOfActiveDPP[i][j] >= v->MaxNumDPP || v->TotalNumberOfSingleDPPPlanes[i][j] == 0)) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4188
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4189
if (v->ReadBandwidthLuma[k] + v->ReadBandwidthChroma[k] > BWOfNonSplitPlaneOfMaximumBandwidth
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4190
&& v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_disabled && v->MPCCombine[i][j][k] == false) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4191
BWOfNonSplitPlaneOfMaximumBandwidth = v->ReadBandwidthLuma[k] + v->ReadBandwidthChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4195
v->MPCCombine[i][j][NumberOfNonSplitPlaneOfMaximumBandwidth] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4196
v->NoOfDPP[i][j][NumberOfNonSplitPlaneOfMaximumBandwidth] = 2;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4197
v->RequiredDPPCLK[i][j][NumberOfNonSplitPlaneOfMaximumBandwidth] =
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4198
v->MinDPPCLKUsingSingleDPP[NumberOfNonSplitPlaneOfMaximumBandwidth]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4199
* (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100) / 2;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4200
v->TotalNumberOfActiveDPP[i][j] = v->TotalNumberOfActiveDPP[i][j] + 1;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4201
v->TotalNumberOfSingleDPPPlanes[i][j] = v->TotalNumberOfSingleDPPPlanes[i][j] - 1;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4204
if (v->TotalNumberOfActiveDPP[i][j] > v->MaxNumDPP) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4205
v->RequiredDISPCLK[i][j] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4206
v->DISPCLK_DPPCLK_Support[i][j] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4207
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4208
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_disabled;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4209
if (v->SingleDPPViewportSizeSupportPerPlane[k] == false && v->WhenToDoMPCCombine != dm_mpc_never) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4210
v->MPCCombine[i][j][k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4211
v->NoOfDPP[i][j][k] = 2;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4212
v->RequiredDPPCLK[i][j][k] = v->MinDPPCLKUsingSingleDPP[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4213
* (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) / 2.0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4215
v->MPCCombine[i][j][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4216
v->NoOfDPP[i][j][k] = 1;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4217
v->RequiredDPPCLK[i][j][k] = v->MinDPPCLKUsingSingleDPP[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4218
* (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4220
if (!(v->MaxDispclk[i] == v->MaxDispclk[v->soc.num_states - 1]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4221
&& v->MaxDppclk[i] == v->MaxDppclk[v->soc.num_states - 1])) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4222
v->PlaneRequiredDISPCLK = v->PixelClock[k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4223
* (1.0 + v->DISPCLKRampingMargin / 100.0);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4225
v->PlaneRequiredDISPCLK = v->PixelClock[k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4227
v->RequiredDISPCLK[i][j] = dml_max(v->RequiredDISPCLK[i][j], v->PlaneRequiredDISPCLK);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4228
if ((v->MinDPPCLKUsingSingleDPP[k] / v->NoOfDPP[i][j][k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4229
> v->MaxDppclkRoundedDownToDFSGranularity)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4230
|| (v->PlaneRequiredDISPCLK > v->MaxDispclkRoundedDownToDFSGranularity)) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4231
v->DISPCLK_DPPCLK_Support[i][j] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4234
v->TotalNumberOfActiveDPP[i][j] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4235
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4236
v->TotalNumberOfActiveDPP[i][j] = v->TotalNumberOfActiveDPP[i][j] + v->NoOfDPP[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4239
v->RequiredDISPCLK[i][j] = dml_max(v->RequiredDISPCLK[i][j], v->WritebackRequiredDISPCLK);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4240
if (v->MaxDispclkRoundedDownToDFSGranularity < v->WritebackRequiredDISPCLK) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4241
v->DISPCLK_DPPCLK_Support[i][j] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4248
for (i = 0; i < v->soc.num_states; i++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4250
if (v->TotalNumberOfActiveDPP[i][j] <= v->MaxNumDPP) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4251
v->TotalAvailablePipesSupport[i][j] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4253
v->TotalAvailablePipesSupport[i][j] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4259
v->NonsupportedDSCInputBPC = false;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4260
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4261
if (!(v->DSCInputBitPerComponent[k] == 12.0 || v->DSCInputBitPerComponent[k] == 10.0 || v->DSCInputBitPerComponent[k] == 8.0)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4262
|| v->DSCInputBitPerComponent[k] > v->MaximumDSCBitsPerComponent) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4263
v->NonsupportedDSCInputBPC = true;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4268
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4269
if (v->BlendingAndTiming[k] == k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4270
if (v->PixelClockBackEnd[k] > 3200) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4271
v->NumberOfDSCSlices[k] = dml_ceil(v->PixelClockBackEnd[k] / 400.0, 4.0);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4272
} else if (v->PixelClockBackEnd[k] > 1360) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4273
v->NumberOfDSCSlices[k] = 8;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4274
} else if (v->PixelClockBackEnd[k] > 680) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4275
v->NumberOfDSCSlices[k] = 4;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4276
} else if (v->PixelClockBackEnd[k] > 340) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4277
v->NumberOfDSCSlices[k] = 2;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4279
v->NumberOfDSCSlices[k] = 1;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4282
v->NumberOfDSCSlices[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4286
for (i = 0; i < v->soc.num_states; i++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4287
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4288
v->RequiresDSC[i][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4289
v->RequiresFEC[i][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4290
if (v->BlendingAndTiming[k] == k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4291
if (v->Output[k] == dm_hdmi) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4292
v->RequiresDSC[i][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4293
v->RequiresFEC[i][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4294
v->OutputBppPerState[i][k] = TruncToValidBPP(
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4295
dml_min(600.0, v->PHYCLKPerState[i]) * 10,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4297
v->HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4298
v->HActive[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4299
v->PixelClockBackEnd[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4300
v->ForcedOutputLinkBPP[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4302
v->Output[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4303
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4304
v->DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4305
v->NumberOfDSCSlices[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4306
v->AudioSampleRate[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4307
v->AudioSampleLayout[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4308
v->ODMCombineEnablePerState[i][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4309
} else if (v->Output[k] == dm_dp || v->Output[k] == dm_edp || v->Output[k] == dm_dp2p0) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4310
if (v->DSCEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4311
v->RequiresDSC[i][k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4312
v->LinkDSCEnable = true;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4313
if (v->Output[k] == dm_dp || v->Output[k] == dm_dp2p0) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4314
v->RequiresFEC[i][k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4316
v->RequiresFEC[i][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4319
v->RequiresDSC[i][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4320
v->LinkDSCEnable = false;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4321
if (v->Output[k] == dm_dp2p0) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4322
v->RequiresFEC[i][k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4324
v->RequiresFEC[i][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4327
if (v->Output[k] == dm_dp2p0) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4328
v->Outbpp = BPP_INVALID;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4329
if ((v->OutputLinkDPRate[k] == dm_dp_rate_na || v->OutputLinkDPRate[k] == dm_dp_rate_uhbr10) &&
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4330
v->PHYCLKD18PerState[k] >= 10000.0 / 18.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4331
v->Outbpp = TruncToValidBPP(
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4332
(1.0 - v->Downspreading / 100.0) * 10000,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4333
v->OutputLinkDPLanes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4334
v->HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4335
v->HActive[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4336
v->PixelClockBackEnd[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4337
v->ForcedOutputLinkBPP[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4338
v->LinkDSCEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4339
v->Output[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4340
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4341
v->DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4342
v->NumberOfDSCSlices[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4343
v->AudioSampleRate[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4344
v->AudioSampleLayout[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4345
v->ODMCombineEnablePerState[i][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4346
if (v->Outbpp == BPP_INVALID && v->PHYCLKD18PerState[k] < 13500.0 / 18.0 &&
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4347
v->DSCEnable[k] == true && v->ForcedOutputLinkBPP[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4348
v->RequiresDSC[i][k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4349
v->LinkDSCEnable = true;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4350
v->Outbpp = TruncToValidBPP(
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4351
(1.0 - v->Downspreading / 100.0) * 10000,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4352
v->OutputLinkDPLanes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4353
v->HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4354
v->HActive[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4355
v->PixelClockBackEnd[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4356
v->ForcedOutputLinkBPP[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4357
v->LinkDSCEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4358
v->Output[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4359
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4360
v->DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4361
v->NumberOfDSCSlices[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4362
v->AudioSampleRate[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4363
v->AudioSampleLayout[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4364
v->ODMCombineEnablePerState[i][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4366
v->OutputBppPerState[i][k] = v->Outbpp;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4370
if (v->Outbpp == BPP_INVALID &&
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4371
(v->OutputLinkDPRate[k] == dm_dp_rate_na || v->OutputLinkDPRate[k] == dm_dp_rate_uhbr13p5) &&
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4372
v->PHYCLKD18PerState[k] >= 13500.0 / 18.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4373
v->Outbpp = TruncToValidBPP(
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4374
(1.0 - v->Downspreading / 100.0) * 13500,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4375
v->OutputLinkDPLanes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4376
v->HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4377
v->HActive[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4378
v->PixelClockBackEnd[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4379
v->ForcedOutputLinkBPP[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4380
v->LinkDSCEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4381
v->Output[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4382
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4383
v->DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4384
v->NumberOfDSCSlices[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4385
v->AudioSampleRate[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4386
v->AudioSampleLayout[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4387
v->ODMCombineEnablePerState[i][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4388
if (v->Outbpp == BPP_INVALID && v->PHYCLKD18PerState[k] < 20000.0 / 18.0 &&
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4389
v->DSCEnable[k] == true && v->ForcedOutputLinkBPP[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4390
v->RequiresDSC[i][k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4391
v->LinkDSCEnable = true;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4392
v->Outbpp = TruncToValidBPP(
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4393
(1.0 - v->Downspreading / 100.0) * 13500,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4394
v->OutputLinkDPLanes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4395
v->HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4396
v->HActive[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4397
v->PixelClockBackEnd[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4398
v->ForcedOutputLinkBPP[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4399
v->LinkDSCEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4400
v->Output[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4401
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4402
v->DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4403
v->NumberOfDSCSlices[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4404
v->AudioSampleRate[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4405
v->AudioSampleLayout[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4406
v->ODMCombineEnablePerState[i][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4408
v->OutputBppPerState[i][k] = v->Outbpp;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4412
if (v->Outbpp == BPP_INVALID &&
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4413
(v->OutputLinkDPRate[k] == dm_dp_rate_na || v->OutputLinkDPRate[k] == dm_dp_rate_uhbr20) &&
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4414
v->PHYCLKD18PerState[k] >= 20000.0 / 18.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4415
v->Outbpp = TruncToValidBPP(
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4416
(1.0 - v->Downspreading / 100.0) * 20000,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4417
v->OutputLinkDPLanes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4418
v->HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4419
v->HActive[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4420
v->PixelClockBackEnd[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4421
v->ForcedOutputLinkBPP[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4422
v->LinkDSCEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4423
v->Output[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4424
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4425
v->DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4426
v->NumberOfDSCSlices[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4427
v->AudioSampleRate[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4428
v->AudioSampleLayout[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4429
v->ODMCombineEnablePerState[i][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4430
if (v->Outbpp == BPP_INVALID && v->DSCEnable[k] == true &&
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4431
v->ForcedOutputLinkBPP[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4432
v->RequiresDSC[i][k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4433
v->LinkDSCEnable = true;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4434
v->Outbpp = TruncToValidBPP(
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4435
(1.0 - v->Downspreading / 100.0) * 20000,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4436
v->OutputLinkDPLanes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4437
v->HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4438
v->HActive[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4439
v->PixelClockBackEnd[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4440
v->ForcedOutputLinkBPP[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4441
v->LinkDSCEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4442
v->Output[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4443
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4444
v->DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4445
v->NumberOfDSCSlices[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4446
v->AudioSampleRate[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4447
v->AudioSampleLayout[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4448
v->ODMCombineEnablePerState[i][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4450
v->OutputBppPerState[i][k] = v->Outbpp;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4455
v->Outbpp = BPP_INVALID;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4456
if (v->PHYCLKPerState[i] >= 270.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4457
v->Outbpp = TruncToValidBPP(
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4458
(1.0 - v->Downspreading / 100.0) * 2700,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4459
v->OutputLinkDPLanes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4460
v->HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4461
v->HActive[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4462
v->PixelClockBackEnd[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4463
v->ForcedOutputLinkBPP[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4464
v->LinkDSCEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4465
v->Output[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4466
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4467
v->DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4468
v->NumberOfDSCSlices[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4469
v->AudioSampleRate[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4470
v->AudioSampleLayout[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4471
v->ODMCombineEnablePerState[i][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4472
v->OutputBppPerState[i][k] = v->Outbpp;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4476
if (v->Outbpp == BPP_INVALID && v->PHYCLKPerState[i] >= 540.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4477
v->Outbpp = TruncToValidBPP(
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4478
(1.0 - v->Downspreading / 100.0) * 5400,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4479
v->OutputLinkDPLanes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4480
v->HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4481
v->HActive[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4482
v->PixelClockBackEnd[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4483
v->ForcedOutputLinkBPP[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4484
v->LinkDSCEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4485
v->Output[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4486
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4487
v->DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4488
v->NumberOfDSCSlices[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4489
v->AudioSampleRate[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4490
v->AudioSampleLayout[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4491
v->ODMCombineEnablePerState[i][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4492
v->OutputBppPerState[i][k] = v->Outbpp;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4496
if (v->Outbpp == BPP_INVALID && v->PHYCLKPerState[i] >= 810.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4497
v->Outbpp = TruncToValidBPP(
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4498
(1.0 - v->Downspreading / 100.0) * 8100,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4499
v->OutputLinkDPLanes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4500
v->HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4501
v->HActive[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4502
v->PixelClockBackEnd[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4503
v->ForcedOutputLinkBPP[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4504
v->LinkDSCEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4505
v->Output[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4506
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4507
v->DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4508
v->NumberOfDSCSlices[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4509
v->AudioSampleRate[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4510
v->AudioSampleLayout[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4511
v->ODMCombineEnablePerState[i][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4512
v->OutputBppPerState[i][k] = v->Outbpp;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4519
v->OutputBppPerState[i][k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4524
for (i = 0; i < v->soc.num_states; i++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4525
v->LinkCapacitySupport[i] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4526
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4527
if (v->BlendingAndTiming[k] == k
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4528
&& (v->Output[k] == dm_dp ||
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4529
v->Output[k] == dm_edp ||
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4530
v->Output[k] == dm_hdmi) && v->OutputBppPerState[i][k] == 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4531
v->LinkCapacitySupport[i] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4537
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4538
if (v->BlendingAndTiming[k] == k
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4539
&& (v->Output[k] == dm_dp ||
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4540
v->Output[k] == dm_edp ||
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4541
v->Output[k] == dm_hdmi)) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4542
if (v->OutputFormat[k] == dm_420 && v->Interlace[k] == 1 && v->ProgressiveToInterlaceUnitInOPP == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4545
if (v->DSCEnable[k] == true && v->OutputFormat[k] == dm_n422
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4546
&& !v->DSC422NativeSupport) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4552
for (i = 0; i < v->soc.num_states; ++i) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4553
v->ODMCombine4To1SupportCheckOK[i] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4554
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4555
if (v->BlendingAndTiming[k] == k && v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4556
&& (v->ODMCombine4To1Supported == false || v->Output[k] == dm_dp || v->Output[k] == dm_edp
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4557
|| v->Output[k] == dm_hdmi)) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4558
v->ODMCombine4To1SupportCheckOK[i] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4565
for (i = 0; i < v->soc.num_states; i++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4566
v->NotEnoughDSCUnits[i] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4567
v->TotalDSCUnitsRequired = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4568
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4569
if (v->RequiresDSC[i][k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4570
if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4571
v->TotalDSCUnitsRequired = v->TotalDSCUnitsRequired + 4.0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4572
} else if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4573
v->TotalDSCUnitsRequired = v->TotalDSCUnitsRequired + 2.0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4575
v->TotalDSCUnitsRequired = v->TotalDSCUnitsRequired + 1.0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4579
if (v->TotalDSCUnitsRequired > v->NumberOfDSC) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4580
v->NotEnoughDSCUnits[i] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4585
for (i = 0; i < v->soc.num_states; i++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4586
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4587
if (v->OutputBppPerState[i][k] == BPP_INVALID) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4588
v->BPP = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4590
v->BPP = v->OutputBppPerState[i][k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4592
if (v->RequiresDSC[i][k] == true && v->BPP != 0.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4593
if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_disabled) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4594
v->DSCDelayPerState[i][k] = dscceComputeDelay(
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4595
v->DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4596
v->BPP,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4597
dml_ceil(1.0 * v->HActive[k] / v->NumberOfDSCSlices[k], 1.0),
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4598
v->NumberOfDSCSlices[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4599
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4600
v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4601
} else if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4602
v->DSCDelayPerState[i][k] = 2.0
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4604
v->DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4605
v->BPP,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4606
dml_ceil(1.0 * v->HActive[k] / v->NumberOfDSCSlices[k], 1.0),
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4607
v->NumberOfDSCSlices[k] / 2,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4608
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4609
v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k]));
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4611
v->DSCDelayPerState[i][k] = 4.0
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4613
v->DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4614
v->BPP,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4615
dml_ceil(1.0 * v->HActive[k] / v->NumberOfDSCSlices[k], 1.0),
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4616
v->NumberOfDSCSlices[k] / 4,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4617
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4618
v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k]));
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4620
v->DSCDelayPerState[i][k] = v->DSCDelayPerState[i][k] * v->PixelClock[k] / v->PixelClockBackEnd[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4622
v->DSCDelayPerState[i][k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4625
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4626
for (m = 0; m < v->NumberOfActivePlanes; m++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4627
if (v->BlendingAndTiming[k] == m && v->RequiresDSC[i][m] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4628
v->DSCDelayPerState[i][k] = v->DSCDelayPerState[i][m];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4636
for (i = 0; i < v->soc.num_states; ++i) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4638
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4639
v->RequiredDPPCLKThisState[k] = v->RequiredDPPCLK[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4640
v->NoOfDPPThisState[k] = v->NoOfDPP[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4641
v->ODMCombineEnableThisState[k] = v->ODMCombineEnablePerState[i][k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4644
if (v->NumberOfActivePlanes > 1 && mode_lib->project == DML_PROJECT_DCN315 && !v->DETSizeOverride[0])
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4645
PatchDETBufferSizeInKByte(v->NumberOfActivePlanes, v->NoOfDPPThisState, v->ip.config_return_buffer_size_in_kbytes, v->DETBufferSizeInKByte);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4648
v->NumberOfActivePlanes,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4649
mode_lib->project == DML_PROJECT_DCN315 && v->DETSizeOverride[0],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4650
v->DETBufferSizeInKByte,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4651
v->MaximumSwathWidthLuma,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4652
v->MaximumSwathWidthChroma,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4653
v->SourceScan,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4654
v->SourcePixelFormat,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4655
v->SurfaceTiling,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4656
v->ViewportWidth,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4657
v->ViewportHeight,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4658
v->SurfaceWidthY,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4659
v->SurfaceWidthC,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4660
v->SurfaceHeightY,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4661
v->SurfaceHeightC,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4662
v->Read256BlockHeightY,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4663
v->Read256BlockHeightC,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4664
v->Read256BlockWidthY,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4665
v->Read256BlockWidthC,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4666
v->ODMCombineEnableThisState,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4667
v->BlendingAndTiming,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4668
v->BytePerPixelY,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4669
v->BytePerPixelC,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4670
v->BytePerPixelInDETY,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4671
v->BytePerPixelInDETC,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4672
v->HActive,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4673
v->HRatio,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4674
v->HRatioChroma,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4675
v->NoOfDPPThisState,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4676
v->swath_width_luma_ub_this_state,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4677
v->swath_width_chroma_ub_this_state,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4678
v->SwathWidthYThisState,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4679
v->SwathWidthCThisState,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4680
v->SwathHeightYThisState,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4681
v->SwathHeightCThisState,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4682
v->DETBufferSizeYThisState,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4683
v->DETBufferSizeCThisState,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4684
v->dummystring,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4685
&v->ViewportSizeSupport[i][j]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4689
v->NumberOfActivePlanes,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4690
v->BytePerPixelY,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4691
v->BytePerPixelC,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4692
v->VRatio,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4693
v->VRatioChroma,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4694
v->SwathWidthYThisState,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4695
v->SwathWidthCThisState,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4696
v->NoOfDPPThisState,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4697
v->HRatio,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4698
v->HRatioChroma,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4699
v->PixelClock,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4700
v->PSCL_FACTOR,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4701
v->PSCL_FACTOR_CHROMA,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4702
v->RequiredDPPCLKThisState,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4703
v->ReadBandwidthLuma,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4704
v->ReadBandwidthChroma,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4705
v->ReturnBusWidth,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4706
&v->ProjectedDCFCLKDeepSleep[i][j]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4708
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4709
v->swath_width_luma_ub_all_states[i][j][k] = v->swath_width_luma_ub_this_state[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4710
v->swath_width_chroma_ub_all_states[i][j][k] = v->swath_width_chroma_ub_this_state[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4711
v->SwathWidthYAllStates[i][j][k] = v->SwathWidthYThisState[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4712
v->SwathWidthCAllStates[i][j][k] = v->SwathWidthCThisState[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4713
v->SwathHeightYAllStates[i][j][k] = v->SwathHeightYThisState[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4714
v->SwathHeightCAllStates[i][j][k] = v->SwathHeightCThisState[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4715
v->DETBufferSizeYAllStates[i][j][k] = v->DETBufferSizeYThisState[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4716
v->DETBufferSizeCAllStates[i][j][k] = v->DETBufferSizeCThisState[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4721
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4722
v->cursor_bw[k] = v->NumberOfCursors[k] * v->CursorWidth[k][0] * v->CursorBPP[k][0] / 8.0
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4723
/ (v->HTotal[k] / v->PixelClock[k]) * v->VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4726
for (i = 0; i < v->soc.num_states; i++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4730
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4731
v->swath_width_luma_ub_this_state[k] = v->swath_width_luma_ub_all_states[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4732
v->swath_width_chroma_ub_this_state[k] = v->swath_width_chroma_ub_all_states[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4733
v->SwathWidthYThisState[k] = v->SwathWidthYAllStates[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4734
v->SwathWidthCThisState[k] = v->SwathWidthCAllStates[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4735
v->SwathHeightYThisState[k] = v->SwathHeightYAllStates[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4736
v->SwathHeightCThisState[k] = v->SwathHeightCAllStates[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4737
v->DETBufferSizeYThisState[k] = v->DETBufferSizeYAllStates[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4738
v->DETBufferSizeCThisState[k] = v->DETBufferSizeCAllStates[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4741
v->TotalNumberOfDCCActiveDPP[i][j] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4742
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4743
if (v->DCCEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4744
v->TotalNumberOfDCCActiveDPP[i][j] = v->TotalNumberOfDCCActiveDPP[i][j] + v->NoOfDPP[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4748
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4749
if (v->SourcePixelFormat[k] == dm_420_8 || v->SourcePixelFormat[k] == dm_420_10
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4750
|| v->SourcePixelFormat[k] == dm_420_12 || v->SourcePixelFormat[k] == dm_rgbe_alpha) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4752
if ((v->SourcePixelFormat[k] == dm_420_10 || v->SourcePixelFormat[k] == dm_420_12)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4753
&& v->SourceScan[k] != dm_vert) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4754
v->PTEBufferSizeInRequestsForLuma = (v->PTEBufferSizeInRequestsLuma + v->PTEBufferSizeInRequestsChroma)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4756
v->PTEBufferSizeInRequestsForChroma = v->PTEBufferSizeInRequestsForLuma;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4758
v->PTEBufferSizeInRequestsForLuma = v->PTEBufferSizeInRequestsLuma;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4759
v->PTEBufferSizeInRequestsForChroma = v->PTEBufferSizeInRequestsChroma;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4762
v->PDEAndMetaPTEBytesPerFrameC = CalculateVMAndRowBytes(
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4764
v->DCCEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4765
v->Read256BlockHeightC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4766
v->Read256BlockWidthC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4767
v->SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4768
v->SurfaceTiling[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4769
v->BytePerPixelC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4770
v->SourceScan[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4771
v->SwathWidthCThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4772
v->ViewportHeightChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4773
v->GPUVMEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4774
v->HostVMEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4775
v->HostVMMaxNonCachedPageTableLevels,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4776
v->GPUVMMinPageSize,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4777
v->HostVMMinPageSize,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4778
v->PTEBufferSizeInRequestsForChroma,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4779
v->PitchC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4781
&v->MacroTileWidthC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4782
&v->MetaRowBytesC,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4783
&v->DPTEBytesPerRowC,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4784
&v->PTEBufferSizeNotExceededC[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4785
&v->dummyinteger7,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4786
&v->dpte_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4787
&v->dummyinteger28,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4788
&v->dummyinteger26,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4789
&v->dummyinteger23,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4790
&v->meta_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4791
&v->dummyinteger8,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4792
&v->dummyinteger9,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4793
&v->dummyinteger19,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4794
&v->dummyinteger20,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4795
&v->dummyinteger17,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4796
&v->dummyinteger10,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4797
&v->dummyinteger11);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4799
v->PrefetchLinesC[i][j][k] = CalculatePrefetchSourceLines(
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4801
v->VRatioChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4802
v->VTAPsChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4803
v->Interlace[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4804
v->ProgressiveToInterlaceUnitInOPP,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4805
v->SwathHeightCThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4806
v->ViewportYStartC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4807
&v->PrefillC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4808
&v->MaxNumSwC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4810
v->PTEBufferSizeInRequestsForLuma = v->PTEBufferSizeInRequestsLuma + v->PTEBufferSizeInRequestsChroma;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4811
v->PTEBufferSizeInRequestsForChroma = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4812
v->PDEAndMetaPTEBytesPerFrameC = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4813
v->MetaRowBytesC = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4814
v->DPTEBytesPerRowC = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4815
v->PrefetchLinesC[i][j][k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4816
v->PTEBufferSizeNotExceededC[i][j][k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4818
v->PDEAndMetaPTEBytesPerFrameY = CalculateVMAndRowBytes(
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4820
v->DCCEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4821
v->Read256BlockHeightY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4822
v->Read256BlockWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4823
v->SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4824
v->SurfaceTiling[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4825
v->BytePerPixelY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4826
v->SourceScan[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4827
v->SwathWidthYThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4828
v->ViewportHeight[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4829
v->GPUVMEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4830
v->HostVMEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4831
v->HostVMMaxNonCachedPageTableLevels,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4832
v->GPUVMMinPageSize,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4833
v->HostVMMinPageSize,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4834
v->PTEBufferSizeInRequestsForLuma,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4835
v->PitchY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4836
v->DCCMetaPitchY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4837
&v->MacroTileWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4838
&v->MetaRowBytesY,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4839
&v->DPTEBytesPerRowY,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4840
&v->PTEBufferSizeNotExceededY[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4841
&v->dummyinteger7,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4842
&v->dpte_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4843
&v->dummyinteger29,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4844
&v->dummyinteger27,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4845
&v->dummyinteger24,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4846
&v->meta_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4847
&v->dummyinteger25,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4848
&v->dpte_group_bytes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4849
&v->dummyinteger21,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4850
&v->dummyinteger22,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4851
&v->dummyinteger18,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4852
&v->dummyinteger5,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4853
&v->dummyinteger6);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4854
v->PrefetchLinesY[i][j][k] = CalculatePrefetchSourceLines(
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4856
v->VRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4857
v->vtaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4858
v->Interlace[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4859
v->ProgressiveToInterlaceUnitInOPP,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4860
v->SwathHeightYThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4861
v->ViewportYStartY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4862
&v->PrefillY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4863
&v->MaxNumSwY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4864
v->PDEAndMetaPTEBytesPerFrame[i][j][k] = v->PDEAndMetaPTEBytesPerFrameY + v->PDEAndMetaPTEBytesPerFrameC;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4865
v->MetaRowBytes[i][j][k] = v->MetaRowBytesY + v->MetaRowBytesC;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4866
v->DPTEBytesPerRow[i][j][k] = v->DPTEBytesPerRowY + v->DPTEBytesPerRowC;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4869
v->GPUVMEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4870
v->SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4871
v->VRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4872
v->VRatioChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4873
v->DCCEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4874
v->HTotal[k] / v->PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4875
v->MetaRowBytesY,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4876
v->MetaRowBytesC,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4877
v->meta_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4878
v->meta_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4879
v->DPTEBytesPerRowY,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4880
v->DPTEBytesPerRowC,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4881
v->dpte_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4882
v->dpte_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4883
&v->meta_row_bandwidth[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4884
&v->dpte_row_bandwidth[i][j][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4892
v->DCCMetaBufferSizeSupport[i][j] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4893
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4894
if (v->MetaRowBytes[i][j][k] > 24064)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4895
v->DCCMetaBufferSizeSupport[i][j] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4897
v->UrgLatency[i] = CalculateUrgentLatency(
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4898
v->UrgentLatencyPixelDataOnly,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4899
v->UrgentLatencyPixelMixedWithVMData,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4900
v->UrgentLatencyVMDataOnly,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4901
v->DoUrgentLatencyAdjustment,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4902
v->UrgentLatencyAdjustmentFabricClockComponent,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4903
v->UrgentLatencyAdjustmentFabricClockReference,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4904
v->FabricClockPerState[i]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4906
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4908
v->swath_width_luma_ub_this_state[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4909
v->swath_width_chroma_ub_this_state[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4910
v->SwathHeightYThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4911
v->SwathHeightCThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4912
v->HTotal[k] / v->PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4913
v->UrgLatency[i],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4914
v->CursorBufferSize,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4915
v->CursorWidth[k][0],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4916
v->CursorBPP[k][0],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4917
v->VRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4918
v->VRatioChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4919
v->BytePerPixelInDETY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4920
v->BytePerPixelInDETC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4921
v->DETBufferSizeYThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4922
v->DETBufferSizeCThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4923
&v->UrgentBurstFactorCursor[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4924
&v->UrgentBurstFactorLuma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4925
&v->UrgentBurstFactorChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4929
v->NotEnoughUrgentLatencyHidingA[i][j] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4930
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4932
v->NotEnoughUrgentLatencyHidingA[i][j] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4936
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4937
v->VActivePixelBandwidth[i][j][k] = v->ReadBandwidthLuma[k] * v->UrgentBurstFactorLuma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4938
+ v->ReadBandwidthChroma[k] * v->UrgentBurstFactorChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4939
v->VActiveCursorBandwidth[i][j][k] = v->cursor_bw[k] * v->UrgentBurstFactorCursor[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4942
v->TotalVActivePixelBandwidth[i][j] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4943
v->TotalVActiveCursorBandwidth[i][j] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4944
v->TotalMetaRowBandwidth[i][j] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4945
v->TotalDPTERowBandwidth[i][j] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4946
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4947
v->TotalVActivePixelBandwidth[i][j] = v->TotalVActivePixelBandwidth[i][j] + v->VActivePixelBandwidth[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4948
v->TotalVActiveCursorBandwidth[i][j] = v->TotalVActiveCursorBandwidth[i][j] + v->VActiveCursorBandwidth[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4949
v->TotalMetaRowBandwidth[i][j] = v->TotalMetaRowBandwidth[i][j] + v->NoOfDPP[i][j][k] * v->meta_row_bandwidth[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4950
v->TotalDPTERowBandwidth[i][j] = v->TotalDPTERowBandwidth[i][j] + v->NoOfDPP[i][j][k] * v->dpte_row_bandwidth[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4956
for (i = 0; i < v->soc.num_states; ++i) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4958
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4959
if (v->BlendingAndTiming[k] == k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4960
if (v->WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4961
v->WritebackDelayTime[k] = v->WritebackLatency
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4963
v->WritebackPixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4964
v->WritebackHRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4965
v->WritebackVRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4966
v->WritebackVTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4967
v->WritebackDestinationWidth[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4968
v->WritebackDestinationHeight[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4969
v->WritebackSourceHeight[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4970
v->HTotal[k]) / v->RequiredDISPCLK[i][j];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4972
v->WritebackDelayTime[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4974
for (m = 0; m < v->NumberOfActivePlanes; m++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4975
if (v->BlendingAndTiming[m] == k && v->WritebackEnable[m] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4976
v->WritebackDelayTime[k] = dml_max(
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4977
v->WritebackDelayTime[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4978
v->WritebackLatency
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4980
v->WritebackPixelFormat[m],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4981
v->WritebackHRatio[m],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4982
v->WritebackVRatio[m],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4983
v->WritebackVTaps[m],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4984
v->WritebackDestinationWidth[m],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4985
v->WritebackDestinationHeight[m],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4986
v->WritebackSourceHeight[m],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4987
v->HTotal[m]) / v->RequiredDISPCLK[i][j]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4992
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4993
for (m = 0; m < v->NumberOfActivePlanes; m++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4994
if (v->BlendingAndTiming[k] == m) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4995
v->WritebackDelayTime[k] = v->WritebackDelayTime[m];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
4999
v->MaxMaxVStartup[i][j] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5000
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5001
v->MaximumVStartup[i][j][k] =
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5002
(v->Interlace[k] && !v->ProgressiveToInterlaceUnitInOPP) ?
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5003
dml_floor((v->VTotal[k] - v->VActive[k]) / 2.0, 1.0) :
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5004
v->VTotal[k] - v->VActive[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5008
1.0 * v->WritebackDelayTime[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5009
/ (v->HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5010
/ v->PixelClock[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5012
if (v->MaximumVStartup[i][j][k] > 1023)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5013
v->MaximumVStartup[i][j][k] = 1023;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5014
v->MaxMaxVStartup[i][j] = dml_max(v->MaxMaxVStartup[i][j], v->MaximumVStartup[i][j][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5019
ReorderingBytes = v->NumberOfChannels
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5021
v->UrgentOutOfOrderReturnPerChannelPixelDataOnly,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5022
v->UrgentOutOfOrderReturnPerChannelPixelMixedWithVMData,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5023
v->UrgentOutOfOrderReturnPerChannelVMDataOnly);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5025
for (i = 0; i < v->soc.num_states; ++i) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5027
v->DCFCLKState[i][j] = v->DCFCLKPerState[i];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5031
if (v->UseMinimumRequiredDCFCLK == true)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5034
for (i = 0; i < v->soc.num_states; ++i) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5037
v->ReturnBusWidth * v->DCFCLKState[i][j],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5038
v->FabricClockPerState[i] * v->FabricDatapathToDCNDataReturn);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5039
double IdealDRAMBandwidthPerState = v->DRAMSpeedPerState[i] * v->NumberOfChannels * v->DRAMChannelWidth;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5041
IdealFabricAndSDPPortBandwidthPerState * v->PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency / 100.0,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5042
IdealDRAMBandwidthPerState * v->PercentOfIdealDRAMBWReceivedAfterUrgLatencyPixelDataOnly / 100.0);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5044
IdealFabricAndSDPPortBandwidthPerState * v->PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency / 100.0,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5045
IdealDRAMBandwidthPerState * v->PercentOfIdealDRAMBWReceivedAfterUrgLatencyPixelMixedWithVMData / 100.0);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5047
if (v->HostVMEnable != true) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5048
v->ReturnBWPerState[i][j] = PixelDataOnlyReturnBWPerState;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5050
v->ReturnBWPerState[i][j] = PixelMixedWithVMDataReturnBWPerState;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5056
for (i = 0; i < v->soc.num_states; ++i) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5058
if ((v->ROBBufferSizeInKByte - v->PixelChunkSizeInKByte) * 1024 / v->ReturnBWPerState[i][j]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5059
> (v->RoundTripPingLatencyCycles + __DML_ARB_TO_RET_DELAY__) / v->DCFCLKState[i][j] + ReorderingBytes / v->ReturnBWPerState[i][j]) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5060
v->ROBSupport[i][j] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5062
v->ROBSupport[i][j] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5070
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5071
MaxTotalVActiveRDBandwidth = MaxTotalVActiveRDBandwidth + v->ReadBandwidthLuma[k] + v->ReadBandwidthChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5074
for (i = 0; i < v->soc.num_states; ++i) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5076
v->MaxTotalVerticalActiveAvailableBandwidth[i][j] = dml_min(
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5078
v->ReturnBusWidth * v->DCFCLKState[i][j],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5079
v->FabricClockPerState[i] * v->FabricDatapathToDCNDataReturn)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5080
* v->MaxAveragePercentOfIdealFabricAndSDPPortBWDisplayCanUseInNormalSystemOperation / 100,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5081
v->DRAMSpeedPerState[i] * v->NumberOfChannels * v->DRAMChannelWidth
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5082
* v->MaxAveragePercentOfIdealDRAMBWDisplayCanUseInNormalSystemOperation / 100);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5084
if (MaxTotalVActiveRDBandwidth <= v->MaxTotalVerticalActiveAvailableBandwidth[i][j]) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5085
v->TotalVerticalActiveBandwidthSupport[i][j] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5087
v->TotalVerticalActiveBandwidthSupport[i][j] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5092
v->UrgentLatency = CalculateUrgentLatency(
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5093
v->UrgentLatencyPixelDataOnly,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5094
v->UrgentLatencyPixelMixedWithVMData,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5095
v->UrgentLatencyVMDataOnly,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5096
v->DoUrgentLatencyAdjustment,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5097
v->UrgentLatencyAdjustmentFabricClockComponent,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5098
v->UrgentLatencyAdjustmentFabricClockReference,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5099
v->FabricClock);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5101
for (i = 0; i < v->soc.num_states; ++i) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5110
v->TimeCalc = 24 / v->ProjectedDCFCLKDeepSleep[i][j];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5112
v->BandwidthWithoutPrefetchSupported[i][j] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5113
if (v->TotalVActivePixelBandwidth[i][j] + v->TotalVActiveCursorBandwidth[i][j] + v->TotalMetaRowBandwidth[i][j]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5114
+ v->TotalDPTERowBandwidth[i][j] > v->ReturnBWPerState[i][j] || v->NotEnoughUrgentLatencyHidingA[i][j]) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5115
v->BandwidthWithoutPrefetchSupported[i][j] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5118
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5119
v->NoOfDPPThisState[k] = v->NoOfDPP[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5120
v->swath_width_luma_ub_this_state[k] = v->swath_width_luma_ub_all_states[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5121
v->swath_width_chroma_ub_this_state[k] = v->swath_width_chroma_ub_all_states[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5122
v->SwathWidthYThisState[k] = v->SwathWidthYAllStates[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5123
v->SwathWidthCThisState[k] = v->SwathWidthCAllStates[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5124
v->SwathHeightYThisState[k] = v->SwathHeightYAllStates[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5125
v->SwathHeightCThisState[k] = v->SwathHeightCAllStates[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5126
v->DETBufferSizeYThisState[k] = v->DETBufferSizeYAllStates[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5127
v->DETBufferSizeCThisState[k] = v->DETBufferSizeCAllStates[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5132
v->ReturnBusWidth * v->DCFCLKState[i][j],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5133
v->FabricClockPerState[i] * v->FabricDatapathToDCNDataReturn)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5134
* v->PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency / 100.0,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5135
v->DRAMSpeedPerState[i] * v->NumberOfChannels * v->DRAMChannelWidth
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5136
* v->PercentOfIdealDRAMBWReceivedAfterUrgLatencyVMDataOnly / 100.0);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5137
if (v->GPUVMEnable && v->HostVMEnable)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5138
HostVMInefficiencyFactor = v->ReturnBWPerState[i][j] / VMDataOnlyReturnBWPerState;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5140
v->ExtraLatency = CalculateExtraLatency(
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5141
v->RoundTripPingLatencyCycles,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5143
v->DCFCLKState[i][j],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5144
v->TotalNumberOfActiveDPP[i][j],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5145
v->PixelChunkSizeInKByte,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5146
v->TotalNumberOfDCCActiveDPP[i][j],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5147
v->MetaChunkSize,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5148
v->ReturnBWPerState[i][j],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5149
v->GPUVMEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5150
v->HostVMEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5151
v->NumberOfActivePlanes,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5152
v->NoOfDPPThisState,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5153
v->dpte_group_bytes,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5155
v->HostVMMinPageSize,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5156
v->HostVMMaxNonCachedPageTableLevels);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5158
v->NextMaxVStartup = v->MaxMaxVStartup[i][j];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5160
v->PrefetchModePerState[i][j] = NextPrefetchModeState;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5161
v->MaxVStartup = v->NextMaxVStartup;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5163
v->TWait = CalculateTWait(
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5164
v->PrefetchModePerState[i][j],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5165
v->DRAMClockChangeLatency,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5166
v->UrgLatency[i],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5167
v->SREnterPlusExitTime);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5169
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5175
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5177
v->swath_width_luma_ub_this_state[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5178
v->swath_width_chroma_ub_this_state[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5179
v->SwathHeightYThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5180
v->SwathHeightCThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5181
v->HTotal[k] / v->PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5182
v->UrgLatency[i],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5183
v->CursorBufferSize,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5184
v->CursorWidth[k][0],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5185
v->CursorBPP[k][0],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5186
v->VRatioPreY[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5187
v->VRatioPreC[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5188
v->BytePerPixelInDETY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5189
v->BytePerPixelInDETC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5190
v->DETBufferSizeYThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5191
v->DETBufferSizeCThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5192
&v->UrgentBurstFactorCursorPre[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5193
&v->UrgentBurstFactorLumaPre[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5194
&v->UrgentBurstFactorChromaPre[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5195
&v->NotUrgentLatencyHidingPre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5198
v->MaximumReadBandwidthWithPrefetch = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5199
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5200
v->cursor_bw_pre[k] = v->NumberOfCursors[k] * v->CursorWidth[k][0] * v->CursorBPP[k][0] / 8.0
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5201
/ (v->HTotal[k] / v->PixelClock[k]) * v->VRatioPreY[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5203
v->MaximumReadBandwidthWithPrefetch =
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5204
v->MaximumReadBandwidthWithPrefetch
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5206
v->VActivePixelBandwidth[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5207
+ v->VActiveCursorBandwidth[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5208
+ v->NoOfDPP[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5209
* (v->meta_row_bandwidth[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5210
+ v->dpte_row_bandwidth[i][j][k]),
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5211
v->NoOfDPP[i][j][k] * v->prefetch_vmrow_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5212
v->NoOfDPP[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5213
* (v->RequiredPrefetchPixelDataBWLuma[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5214
* v->UrgentBurstFactorLumaPre[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5215
+ v->RequiredPrefetchPixelDataBWChroma[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5216
* v->UrgentBurstFactorChromaPre[k])
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5217
+ v->cursor_bw_pre[k] * v->UrgentBurstFactorCursorPre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5220
v->NotEnoughUrgentLatencyHidingPre = false;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5221
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5222
if (v->NotUrgentLatencyHidingPre[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5223
v->NotEnoughUrgentLatencyHidingPre = true;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5227
v->PrefetchSupported[i][j] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5228
if (v->BandwidthWithoutPrefetchSupported[i][j] == false || v->MaximumReadBandwidthWithPrefetch > v->ReturnBWPerState[i][j]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5229
|| v->NotEnoughUrgentLatencyHidingPre == 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5230
v->PrefetchSupported[i][j] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5232
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5233
if (v->LineTimesForPrefetch[k] < 2.0 || v->LinesForMetaPTE[k] >= 32.0 || v->LinesForMetaAndDPTERow[k] >= 16.0
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5234
|| v->NoTimeForPrefetch[i][j][k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5235
v->PrefetchSupported[i][j] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5239
v->DynamicMetadataSupported[i][j] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5240
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5241
if (v->NoTimeForDynamicMetadata[i][j][k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5242
v->DynamicMetadataSupported[i][j] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5246
v->VRatioInPrefetchSupported[i][j] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5247
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5248
if (v->VRatioPreY[i][j][k] > 4.0 || v->VRatioPreC[i][j][k] > 4.0 || v->NoTimeForPrefetch[i][j][k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5249
v->VRatioInPrefetchSupported[i][j] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5252
v->AnyLinesForVMOrRowTooLarge = false;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5253
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5254
if (v->LinesForMetaAndDPTERow[k] >= 16 || v->LinesForMetaPTE[k] >= 32) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5255
v->AnyLinesForVMOrRowTooLarge = true;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5259
v->NextPrefetchMode = v->NextPrefetchMode + 1;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5261
if (v->PrefetchSupported[i][j] == true && v->VRatioInPrefetchSupported[i][j] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5262
v->BandwidthAvailableForImmediateFlip = v->ReturnBWPerState[i][j];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5263
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5264
v->BandwidthAvailableForImmediateFlip = v->BandwidthAvailableForImmediateFlip
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5266
v->VActivePixelBandwidth[i][j][k] + v->VActiveCursorBandwidth[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5267
v->NoOfDPP[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5268
* (v->RequiredPrefetchPixelDataBWLuma[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5269
* v->UrgentBurstFactorLumaPre[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5270
+ v->RequiredPrefetchPixelDataBWChroma[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5271
* v->UrgentBurstFactorChromaPre[k])
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5272
+ v->cursor_bw_pre[k] * v->UrgentBurstFactorCursorPre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5274
v->TotImmediateFlipBytes = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5275
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5276
v->TotImmediateFlipBytes = v->TotImmediateFlipBytes
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5277
+ v->NoOfDPP[i][j][k] * (v->PDEAndMetaPTEBytesPerFrame[i][j][k] + v->MetaRowBytes[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5278
+ v->DPTEBytesPerRow[i][j][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5281
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5286
v->ExtraLatency,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5287
v->UrgLatency[i],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5288
v->PDEAndMetaPTEBytesPerFrame[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5289
v->MetaRowBytes[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5290
v->DPTEBytesPerRow[i][j][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5292
v->total_dcn_read_bw_with_flip = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5293
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5294
v->total_dcn_read_bw_with_flip = v->total_dcn_read_bw_with_flip
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5296
v->NoOfDPP[i][j][k] * v->prefetch_vmrow_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5297
v->NoOfDPP[i][j][k] * v->final_flip_bw[k] + v->VActivePixelBandwidth[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5298
+ v->VActiveCursorBandwidth[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5299
v->NoOfDPP[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5300
* (v->final_flip_bw[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5301
+ v->RequiredPrefetchPixelDataBWLuma[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5302
* v->UrgentBurstFactorLumaPre[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5303
+ v->RequiredPrefetchPixelDataBWChroma[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5304
* v->UrgentBurstFactorChromaPre[k])
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5305
+ v->cursor_bw_pre[k] * v->UrgentBurstFactorCursorPre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5307
v->ImmediateFlipSupportedForState[i][j] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5308
if (v->total_dcn_read_bw_with_flip > v->ReturnBWPerState[i][j]) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5309
v->ImmediateFlipSupportedForState[i][j] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5311
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5312
if (v->ImmediateFlipSupportedForPipe[k] == false) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5313
v->ImmediateFlipSupportedForState[i][j] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5317
v->ImmediateFlipSupportedForState[i][j] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5320
if (v->MaxVStartup <= __DML_VBA_MIN_VSTARTUP__ || v->AnyLinesForVMOrRowTooLarge == false) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5321
v->NextMaxVStartup = v->MaxMaxVStartup[i][j];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5324
v->NextMaxVStartup = v->NextMaxVStartup - 1;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5326
v->NextPrefetchMode = v->NextPrefetchMode + 1;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5327
} while (!((v->PrefetchSupported[i][j] == true && v->DynamicMetadataSupported[i][j] == true && v->VRatioInPrefetchSupported[i][j] == true
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5328
&& ((v->HostVMEnable == false &&
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5329
v->ImmediateFlipRequirement[0] != dm_immediate_flip_required)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5330
|| v->ImmediateFlipSupportedForState[i][j] == true))
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5331
|| (v->NextMaxVStartup == v->MaxMaxVStartup[i][j] && NextPrefetchModeState > MaxPrefetchMode)));
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5334
v->DETBufferSizeInKByte[0],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5335
v->ConfigReturnBufferSizeInKByte,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5336
v->UseUnboundedRequesting,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5337
v->TotalNumberOfActiveDPP[i][j],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5339
v->MaxNumDPP,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5340
v->CompressedBufferSegmentSizeInkByte,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5341
v->Output,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5347
v->PrefetchModePerState[i][j],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5348
v->DCFCLKState[i][j],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5349
v->ReturnBWPerState[i][j],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5350
v->UrgLatency[i],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5351
v->ExtraLatency,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5352
v->SOCCLKPerState[i],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5353
v->ProjectedDCFCLKDeepSleep[i][j],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5354
v->DETBufferSizeYThisState,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5355
v->DETBufferSizeCThisState,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5356
v->SwathHeightYThisState,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5357
v->SwathHeightCThisState,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5358
v->SwathWidthYThisState,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5359
v->SwathWidthCThisState,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5360
v->NoOfDPPThisState,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5361
v->BytePerPixelInDETY,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5362
v->BytePerPixelInDETC,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5365
&v->DRAMClockChangeSupport[i][j],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5374
for (i = 0; i < v->soc.num_states; i++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5376
v->PTEBufferSizeNotExceeded[i][j] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5377
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5378
if (v->PTEBufferSizeNotExceededY[i][j][k] == false || v->PTEBufferSizeNotExceededC[i][j][k] == false) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5379
v->PTEBufferSizeNotExceeded[i][j] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5386
v->CursorSupport = true;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5387
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5388
if (v->CursorWidth[k][0] > 0.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5389
if (v->CursorBPP[k][0] == 64 && v->Cursor64BppSupport == false) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5390
v->CursorSupport = false;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5396
v->PitchSupport = true;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5397
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5398
v->AlignedYPitch[k] = dml_ceil(dml_max(v->PitchY[k], v->SurfaceWidthY[k]), v->MacroTileWidthY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5399
if (v->DCCEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5400
v->AlignedDCCMetaPitchY[k] = dml_ceil(dml_max(v->DCCMetaPitchY[k], v->SurfaceWidthY[k]), 64.0 * v->Read256BlockWidthY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5402
v->AlignedDCCMetaPitchY[k] = v->DCCMetaPitchY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5404
if (v->SourcePixelFormat[k] != dm_444_64 && v->SourcePixelFormat[k] != dm_444_32 && v->SourcePixelFormat[k] != dm_444_16
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5405
&& v->SourcePixelFormat[k] != dm_mono_16 && v->SourcePixelFormat[k] != dm_rgbe
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5406
&& v->SourcePixelFormat[k] != dm_mono_8) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5407
v->AlignedCPitch[k] = dml_ceil(dml_max(v->PitchC[k], v->SurfaceWidthC[k]), v->MacroTileWidthC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5408
if (v->DCCEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5409
v->AlignedDCCMetaPitchC[k] = dml_ceil(
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5410
dml_max(v->DCCMetaPitchC[k], v->SurfaceWidthC[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5411
64.0 * v->Read256BlockWidthC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5413
v->AlignedDCCMetaPitchC[k] = v->DCCMetaPitchC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5416
v->AlignedCPitch[k] = v->PitchC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5417
v->AlignedDCCMetaPitchC[k] = v->DCCMetaPitchC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5419
if (v->AlignedYPitch[k] > v->PitchY[k] || v->AlignedCPitch[k] > v->PitchC[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5420
|| v->AlignedDCCMetaPitchY[k] > v->DCCMetaPitchY[k] || v->AlignedDCCMetaPitchC[k] > v->DCCMetaPitchC[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5421
v->PitchSupport = false;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5425
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5426
if (v->ViewportWidth[k] > v->SurfaceWidthY[k] || v->ViewportHeight[k] > v->SurfaceHeightY[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5428
if (v->SourcePixelFormat[k] != dm_444_64 && v->SourcePixelFormat[k] != dm_444_32
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5429
&& v->SourcePixelFormat[k] != dm_444_16 && v->SourcePixelFormat[k] != dm_444_8
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5430
&& v->SourcePixelFormat[k] != dm_rgbe) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5431
if (v->ViewportWidthChroma[k] > v->SurfaceWidthC[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5432
|| v->ViewportHeightChroma[k] > v->SurfaceHeightC[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5440
for (i = v->soc.num_states - 1; i >= 0; i--) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5442
if (v->ScaleRatioAndTapsSupport == true && v->SourceFormatPixelAndScanSupport == true && v->ViewportSizeSupport[i][j] == true
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5443
&& v->LinkCapacitySupport[i] == true && !P2IWith420 && !DSCOnlyIfNecessaryWithBPP
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5444
&& !DSC422NativeNotSupported && v->ODMCombine4To1SupportCheckOK[i] == true && v->NotEnoughDSCUnits[i] == false
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5445
&& v->DTBCLKRequiredMoreThanSupported[i] == false
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5446
&& v->ROBSupport[i][j] == true && v->DISPCLK_DPPCLK_Support[i][j] == true
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5447
&& v->TotalAvailablePipesSupport[i][j] == true && EnoughWritebackUnits == true
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5448
&& v->WritebackLatencySupport == true && v->WritebackScaleRatioAndTapsSupport == true
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5449
&& v->CursorSupport == true && v->PitchSupport == true && ViewportExceedsSurface == false
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5450
&& v->PrefetchSupported[i][j] == true && v->DynamicMetadataSupported[i][j] == true
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5451
&& v->TotalVerticalActiveBandwidthSupport[i][j] == true && v->VRatioInPrefetchSupported[i][j] == true
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5452
&& v->PTEBufferSizeNotExceeded[i][j] == true && v->NonsupportedDSCInputBPC == false
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5453
&& ((v->HostVMEnable == false
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5454
&& v->ImmediateFlipRequirement[0] != dm_immediate_flip_required)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5455
|| v->ImmediateFlipSupportedForState[i][j] == true)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5457
v->ModeSupport[i][j] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5459
v->ModeSupport[i][j] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5461
if (v->ScaleRatioAndTapsSupport == false)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5463
if (v->SourceFormatPixelAndScanSupport == false)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5465
if (v->ViewportSizeSupport[i][j] == false)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5467
if (v->LinkCapacitySupport[i] == false)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5469
if (v->ODMCombine4To1SupportCheckOK[i] == false)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5471
if (v->NotEnoughDSCUnits[i] == true)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5473
if (v->DTBCLKRequiredMoreThanSupported[i] == true)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5475
if (v->ROBSupport[i][j] == false)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5477
if (v->DISPCLK_DPPCLK_Support[i][j] == false)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5479
if (v->TotalAvailablePipesSupport[i][j] == false)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5483
if (v->WritebackLatencySupport == false)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5485
if (v->WritebackScaleRatioAndTapsSupport == false)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5487
if (v->CursorSupport == false)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5489
if (v->PitchSupport == false)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5493
if (v->PrefetchSupported[i][j] == false)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5495
if (v->DynamicMetadataSupported[i][j] == false)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5497
if (v->TotalVerticalActiveBandwidthSupport[i][j] == false)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5499
if (v->VRatioInPrefetchSupported[i][j] == false)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5501
if (v->PTEBufferSizeNotExceeded[i][j] == false)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5503
if (v->NonsupportedDSCInputBPC == true)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5505
if (!((v->HostVMEnable == false
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5506
&& v->ImmediateFlipRequirement[0] != dm_immediate_flip_required)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5507
|| v->ImmediateFlipSupportedForState[i][j] == true))
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5518
for (i = v->soc.num_states; i >= 0; i--) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5519
if (i == v->soc.num_states || v->ModeSupport[i][0] == true || v->ModeSupport[i][1] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5520
v->VoltageLevel = i;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5521
v->ModeIsSupported = v->ModeSupport[i][0] == true || v->ModeSupport[i][1] == true;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5522
if (v->ModeSupport[i][0] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5529
v->ImmediateFlipSupport = v->ImmediateFlipSupportedForState[v->VoltageLevel][MaximumMPCCombine];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5530
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5531
v->MPCCombineEnable[k] = v->MPCCombine[v->VoltageLevel][MaximumMPCCombine][k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5532
v->DPPPerPlane[k] = v->NoOfDPP[v->VoltageLevel][MaximumMPCCombine][k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5534
v->DCFCLK = v->DCFCLKState[v->VoltageLevel][MaximumMPCCombine];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5535
v->DRAMSpeed = v->DRAMSpeedPerState[v->VoltageLevel];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5536
v->FabricClock = v->FabricClockPerState[v->VoltageLevel];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5537
v->SOCCLK = v->SOCCLKPerState[v->VoltageLevel];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5538
v->ReturnBW = v->ReturnBWPerState[v->VoltageLevel][MaximumMPCCombine];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5539
v->maxMpcComb = MaximumMPCCombine;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5569
struct vba_vars_st *v = &mode_lib->vba;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5587
v->UrgentWatermark = UrgentLatency + ExtraLatency;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5592
dml_print("DML::%s: UrgentWatermark = %f\n", __func__, v->UrgentWatermark);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5595
v->DRAMClockChangeWatermark = v->DRAMClockChangeLatency + v->UrgentWatermark;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5598
dml_print("DML::%s: v->DRAMClockChangeLatency = %f\n", __func__, v->DRAMClockChangeLatency);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5599
dml_print("DML::%s: DRAMClockChangeWatermark = %f\n", __func__, v->DRAMClockChangeWatermark);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5602
v->TotalActiveWriteback = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5603
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5604
if (v->WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5605
v->TotalActiveWriteback = v->TotalActiveWriteback + 1;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5609
if (v->TotalActiveWriteback <= 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5610
v->WritebackUrgentWatermark = v->WritebackLatency;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5612
v->WritebackUrgentWatermark = v->WritebackLatency + v->WritebackChunkSize * 1024.0 / 32.0 / SOCCLK;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5615
if (v->TotalActiveWriteback <= 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5616
v->WritebackDRAMClockChangeWatermark = v->DRAMClockChangeLatency + v->WritebackLatency;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5618
v->WritebackDRAMClockChangeWatermark = v->DRAMClockChangeLatency + v->WritebackLatency + v->WritebackChunkSize * 1024.0 / 32.0 / SOCCLK;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5621
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5623
+ DPPPerPlane[k] * (SwathWidthY[k] * BytePerPixelDETY[k] * v->VRatio[k] + SwathWidthC[k] * BytePerPixelDETC[k] * v->VRatioChroma[k])
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5624
/ (v->HTotal[k] / v->PixelClock[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5627
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5630
v->LBLatencyHidingSourceLinesY = dml_min(
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5631
(double) v->MaxLineBufferLines,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5632
dml_floor(v->LineBufferSize / v->LBBitPerPixel[k] / (SwathWidthY[k] / dml_max(v->HRatio[k], 1.0)), 1)) - (v->vtaps[k] - 1);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5634
v->LBLatencyHidingSourceLinesC = dml_min(
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5635
(double) v->MaxLineBufferLines,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5636
dml_floor(v->LineBufferSize / v->LBBitPerPixel[k] / (SwathWidthC[k] / dml_max(v->HRatioChroma[k], 1.0)), 1)) - (v->VTAPsChroma[k] - 1);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5638
EffectiveLBLatencyHidingY = v->LBLatencyHidingSourceLinesY / v->VRatio[k] * (v->HTotal[k] / v->PixelClock[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5640
EffectiveLBLatencyHidingC = v->LBLatencyHidingSourceLinesC / v->VRatioChroma[k] * (v->HTotal[k] / v->PixelClock[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5644
+ CompressedBufferSizeInkByte * 1024 * SwathWidthY[k] * BytePerPixelDETY[k] * v->VRatio[k] / (v->HTotal[k] / v->PixelClock[k]) / TotalPixelBW;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5649
FullDETBufferingTimeY = LinesInDETYRoundedDownToSwath[k] * (v->HTotal[k] / v->PixelClock[k]) / v->VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5651
LinesInDETC = v->DETBufferSizeC[k] / BytePerPixelDETC[k] / SwathWidthC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5653
FullDETBufferingTimeC = LinesInDETCRoundedDownToSwath * (v->HTotal[k] / v->PixelClock[k]) / v->VRatioChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5660
- ((double) v->DSTXAfterScaler[k] / v->HTotal[k] + v->DSTYAfterScaler[k]) * v->HTotal[k] / v->PixelClock[k] - v->UrgentWatermark - v->DRAMClockChangeWatermark;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5662
if (v->NumberOfActivePlanes > 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5664
- (1 - 1.0 / v->NumberOfActivePlanes) * SwathHeightY[k] * v->HTotal[k] / v->PixelClock[k] / v->VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5669
- ((double) v->DSTXAfterScaler[k] / v->HTotal[k] + v->DSTYAfterScaler[k]) * v->HTotal[k] / v->PixelClock[k] - v->UrgentWatermark - v->DRAMClockChangeWatermark;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5671
if (v->NumberOfActivePlanes > 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5673
- (1 - 1.0 / v->NumberOfActivePlanes) * SwathHeightC[k] * v->HTotal[k] / v->PixelClock[k] / v->VRatioChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5675
v->ActiveDRAMClockChangeLatencyMargin[k] = dml_min(ActiveDRAMClockChangeLatencyMarginY, ActiveDRAMClockChangeLatencyMarginC);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5677
v->ActiveDRAMClockChangeLatencyMargin[k] = ActiveDRAMClockChangeLatencyMarginY;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5680
if (v->WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5681
WritebackDRAMClockChangeLatencyHiding = v->WritebackInterfaceBufferSize * 1024
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5682
/ (v->WritebackDestinationWidth[k] * v->WritebackDestinationHeight[k] / (v->WritebackSourceHeight[k] * v->HTotal[k] / v->PixelClock[k]) * 4);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5683
if (v->WritebackPixelFormat[k] == dm_444_64) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5686
WritebackDRAMClockChangeLatencyMargin = WritebackDRAMClockChangeLatencyHiding - v->WritebackDRAMClockChangeWatermark;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5687
v->ActiveDRAMClockChangeLatencyMargin[k] = dml_min(v->ActiveDRAMClockChangeLatencyMargin[k], WritebackDRAMClockChangeLatencyMargin);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5691
v->MinActiveDRAMClockChangeMargin = 999999;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5693
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5694
if (v->ActiveDRAMClockChangeLatencyMargin[k] < v->MinActiveDRAMClockChangeMargin) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5695
v->MinActiveDRAMClockChangeMargin = v->ActiveDRAMClockChangeLatencyMargin[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5696
if (v->BlendingAndTiming[k] == k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5699
for (j = 0; j < v->NumberOfActivePlanes; ++j) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5700
if (v->BlendingAndTiming[k] == j) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5708
v->MinActiveDRAMClockChangeLatencySupported = v->MinActiveDRAMClockChangeMargin + v->DRAMClockChangeLatency ;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5711
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5712
if (!((k == PlaneWithMinActiveDRAMClockChangeMargin) && (v->BlendingAndTiming[k] == k)) && !(v->BlendingAndTiming[k] == PlaneWithMinActiveDRAMClockChangeMargin)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5713
&& v->ActiveDRAMClockChangeLatencyMargin[k] < SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5714
SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank = v->ActiveDRAMClockChangeLatencyMargin[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5718
v->TotalNumberOfActiveOTG = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5720
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5721
if (v->BlendingAndTiming[k] == k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5722
v->TotalNumberOfActiveOTG = v->TotalNumberOfActiveOTG + 1;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5726
if (v->MinActiveDRAMClockChangeMargin > 0 && PrefetchMode == 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5728
} else if ((v->SynchronizedVBlank == true || v->TotalNumberOfActiveOTG == 1
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5735
*StutterExitWatermark = v->SRExitTime + ExtraLatency + 10 / DCFCLKDeepSleep;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5736
*StutterEnterPlusExitWatermark = (v->SREnterPlusExitTime + ExtraLatency + 10 / DCFCLKDeepSleep);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5737
*Z8StutterExitWatermark = v->SRExitZ8Time + ExtraLatency + 10 / DCFCLKDeepSleep;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5738
*Z8StutterEnterPlusExitWatermark = v->SREnterPlusExitZ8Time + ExtraLatency + 10 / DCFCLKDeepSleep;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5769
struct vba_vars_st *v = &mode_lib->vba;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5793
v->DCFCLKDeepSleepPerPlane[k] = dml_max(__DML_MIN_DCFCLK_FACTOR__ * SwathWidthY[k] * BytePerPixelY[k] / 32.0 / DisplayPipeLineDeliveryTimeLuma,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5796
v->DCFCLKDeepSleepPerPlane[k] = __DML_MIN_DCFCLK_FACTOR__ * SwathWidthY[k] * BytePerPixelY[k] / 64.0 / DisplayPipeLineDeliveryTimeLuma;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5798
v->DCFCLKDeepSleepPerPlane[k] = dml_max(v->DCFCLKDeepSleepPerPlane[k], PixelClock[k] / 16);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
5809
*DCFCLKDeepSleep = dml_max(*DCFCLKDeepSleep, v->DCFCLKDeepSleepPerPlane[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6353
struct vba_vars_st *v = &mode_lib->vba;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
6571
if (v->BlendingAndTiming[k] == k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7030
struct vba_vars_st *v = &mode_lib->vba;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7035
NormalEfficiency = v->PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency / 100.0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7036
for (i = 0; i < v->soc.num_states; ++i) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7053
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7055
+ v->NoOfDPP[i][j][k] * v->DPTEBytesPerRow[i][j][k] / (15.75 * v->HTotal[k] / v->PixelClock[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7058
for (k = 0; k <= v->NumberOfActivePlanes - 1; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7059
NoOfDPPState[k] = v->NoOfDPP[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7062
MinimumTWait = CalculateTWait(MaxPrefetchMode, v->FinalDRAMClockChangeLatency, v->UrgLatency[i], v->SREnterPlusExitTime);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7063
NonDPTEBandwidth = v->TotalVActivePixelBandwidth[i][j] + v->TotalVActiveCursorBandwidth[i][j] + v->TotalMetaRowBandwidth[i][j];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7064
DPTEBandwidth = (v->HostVMEnable == true || v->ImmediateFlipRequirement[0] == dm_immediate_flip_required) ?
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7065
TotalMaxPrefetchFlipDPTERowBandwidth[i][j] : v->TotalDPTERowBandwidth[i][j];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7067
v->ProjectedDCFCLKDeepSleep[i][j],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7068
(NonDPTEBandwidth + v->TotalDPTERowBandwidth[i][j]) / v->ReturnBusWidth
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7069
/ (v->MaxAveragePercentOfIdealFabricAndSDPPortBWDisplayCanUseInNormalSystemOperation / 100),
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7070
(NonDPTEBandwidth + DPTEBandwidth / NormalEfficiency) / NormalEfficiency / v->ReturnBusWidth);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7074
v->TotalNumberOfActiveDPP[i][j],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7075
v->PixelChunkSizeInKByte,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7076
v->TotalNumberOfDCCActiveDPP[i][j],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7077
v->MetaChunkSize,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7078
v->GPUVMEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7079
v->HostVMEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7080
v->NumberOfActivePlanes,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7082
v->dpte_group_bytes,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7084
v->HostVMMinPageSize,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7085
v->HostVMMaxNonCachedPageTableLevels);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7086
ExtraLatencyCycles = v->RoundTripPingLatencyCycles + __DML_ARB_TO_RET_DELAY__ + ExtraLatencyBytes / NormalEfficiency / v->ReturnBusWidth;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7087
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7092
PixelDCFCLKCyclesRequiredInPrefetch[k] = (v->PrefetchLinesY[i][j][k] * v->swath_width_luma_ub_all_states[i][j][k] * v->BytePerPixelY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7093
+ v->PrefetchLinesC[i][j][k] * v->swath_width_chroma_ub_all_states[i][j][k] * v->BytePerPixelC[k]) / NormalEfficiency / v->ReturnBusWidth;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7095
+ v->PDEAndMetaPTEBytesPerFrame[i][j][k] / NormalEfficiency / NormalEfficiency / v->ReturnBusWidth * (v->GPUVMMaxPageTableLevels > 2 ? 1 : 0)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7096
+ 2 * v->DPTEBytesPerRow[i][j][k] / NormalEfficiency / NormalEfficiency / v->ReturnBusWidth
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7097
+ 2 * v->MetaRowBytes[i][j][k] / NormalEfficiency / v->ReturnBusWidth + PixelDCFCLKCyclesRequiredInPrefetch[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7098
PrefetchPixelLinesTime[k] = dml_max(v->PrefetchLinesY[i][j][k], v->PrefetchLinesC[i][j][k]) * v->HTotal[k] / v->PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7099
ExpectedPrefetchBWAcceleration = (v->VActivePixelBandwidth[i][j][k] + v->VActiveCursorBandwidth[i][j][k])
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7100
/ (v->ReadBandwidthLuma[k] + v->ReadBandwidthChroma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7102
(v->GPUVMEnable == true && v->DynamicMetadataEnable[k] == true && v->DynamicMetadataVMEnabled == true) ?
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7103
v->UrgLatency[i] * v->GPUVMMaxPageTableLevels * (v->HostVMEnable == true ? v->HostVMMaxNonCachedPageTableLevels + 1 : 1) : 0;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7104
PrefetchTime = (v->MaximumVStartup[i][j][k] - 1) * v->HTotal[k] / v->PixelClock[k] - MinimumTWait
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7105
- v->UrgLatency[i]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7106
* ((v->GPUVMMaxPageTableLevels <= 2 ? v->GPUVMMaxPageTableLevels : v->GPUVMMaxPageTableLevels - 2)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7107
* (v->HostVMEnable == true ? v->HostVMMaxNonCachedPageTableLevels + 1 : 1) - 1)
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7116
if (v->HostVMEnable == true || v->ImmediateFlipRequirement[0] == dm_immediate_flip_required) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7118
+ NoOfDPPState[k] * DPTEBandwidth / NormalEfficiency / NormalEfficiency / v->ReturnBusWidth;
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7121
DCFCLKRequiredForPeakBandwidthPerPlane[k] = v->DCFCLKPerState[i];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7123
if (v->DynamicMetadataEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7131
v->MaxInterDCNTileRepeaters,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7132
v->RequiredDPPCLK[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7133
v->RequiredDISPCLK[i][j],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7134
v->ProjectedDCFCLKDeepSleep[i][j],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7135
v->PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7136
v->HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7137
v->VTotal[k] - v->VActive[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7138
v->DynamicMetadataTransmittedBytes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7139
v->DynamicMetadataLinesBeforeActiveRequired[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7140
v->Interlace[k],
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7141
v->ProgressiveToInterlaceUnitInOPP,
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7149
AllowedTimeForUrgentExtraLatency = v->MaximumVStartup[i][j][k] * v->HTotal[k] / v->PixelClock[k] - MinimumTWait - TSetupPipe - TdmbfPipe - TdmecPipe
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7156
DCFCLKRequiredForPeakBandwidthPerPlane[k] = v->DCFCLKPerState[i];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7161
for (k = 0; k <= v->NumberOfActivePlanes - 1; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7164
MinimumTvmPlus2Tr0 = v->UrgLatency[i]
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7165
* (v->GPUVMEnable == true ?
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7166
(v->HostVMEnable == true ?
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7167
(v->GPUVMMaxPageTableLevels + 2) * (v->HostVMMaxNonCachedPageTableLevels + 1) - 1 : v->GPUVMMaxPageTableLevels + 1) :
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7169
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7171
MaximumTvmPlus2Tr0PlusTsw = (v->MaximumVStartup[i][j][k] - 2) * v->HTotal[k] / v->PixelClock[k] - MinimumTWait - DynamicMetadataVMExtraLatency[k];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7173
DCFCLKRequiredForPeakBandwidth = v->DCFCLKPerState[i];
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
7181
v->DCFCLKState[i][j] = dml_min(v->DCFCLKPerState[i], 1.05 * dml_max(DCFCLKRequiredForAverageBandwidth, DCFCLKRequiredForPeakBandwidth));
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
1761
struct vba_vars_st *v = &mode_lib->vba;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
1769
if (!v->IgnoreViewportPositioning) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
1797
dml_print("DML::%s: IgnoreViewportPositioning = %d\n", __func__, v->IgnoreViewportPositioning);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
1843
struct vba_vars_st *v = &mode_lib->vba;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
1878
MPDEBytesFrame = 128 * (v->GPUVMMaxPageTableLevels - 1);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
1899
if (GPUVMEnable == true && v->GPUVMMaxPageTableLevels > 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
1913
ExtraDPDEBytesFrame = 128 * (v->GPUVMMaxPageTableLevels - 2);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2006
struct vba_vars_st *v = &mode_lib->vba;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2013
int PrefetchMode = v->PrefetchModePerState[v->VoltageLevel][v->maxMpcComb];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2015
v->WritebackDISPCLK = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2016
v->DISPCLKWithRamping = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2017
v->DISPCLKWithoutRamping = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2018
v->GlobalDPPCLK = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2022
v->ReturnBusWidth * v->DCFCLKState[v->VoltageLevel][v->maxMpcComb],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2023
v->FabricClockPerState[v->VoltageLevel] * v->FabricDatapathToDCNDataReturn);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2024
double IdealDRAMBandwidthPerState = v->DRAMSpeedPerState[v->VoltageLevel] * v->NumberOfChannels * v->DRAMChannelWidth;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2026
if (v->HostVMEnable != true) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2027
v->ReturnBW = dml_min(
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2028
IdealFabricAndSDPPortBandwidthPerState * v->PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency / 100.0,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2029
IdealDRAMBandwidthPerState * v->PercentOfIdealDRAMBWReceivedAfterUrgLatencyPixelDataOnly / 100.0);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2031
v->ReturnBW = dml_min(
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2032
IdealFabricAndSDPPortBandwidthPerState * v->PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency / 100.0,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2033
IdealDRAMBandwidthPerState * v->PercentOfIdealDRAMBWReceivedAfterUrgLatencyPixelMixedWithVMData / 100.0);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2040
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2041
if (v->WritebackEnable[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2042
v->WritebackDISPCLK = dml_max(
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2043
v->WritebackDISPCLK,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2045
v->WritebackPixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2046
v->PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2047
v->WritebackHRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2048
v->WritebackVRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2049
v->WritebackHTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2050
v->WritebackVTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2051
v->WritebackSourceWidth[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2052
v->WritebackDestinationWidth[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2053
v->HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2054
v->WritebackLineBufferSize));
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2058
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2059
if (v->HRatio[k] > 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2060
v->PSCL_THROUGHPUT_LUMA[k] = dml_min(
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2061
v->MaxDCHUBToPSCLThroughput,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2062
v->MaxPSCLToLBThroughput * v->HRatio[k] / dml_ceil(v->htaps[k] / 6.0, 1));
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2064
v->PSCL_THROUGHPUT_LUMA[k] = dml_min(v->MaxDCHUBToPSCLThroughput, v->MaxPSCLToLBThroughput);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2067
v->DPPCLKUsingSingleDPPLuma = v->PixelClock[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2069
v->vtaps[k] / 6.0 * dml_min(1.0, v->HRatio[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2070
dml_max(v->HRatio[k] * v->VRatio[k] / v->PSCL_THROUGHPUT_LUMA[k], 1.0));
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2072
if ((v->htaps[k] > 6 || v->vtaps[k] > 6) && v->DPPCLKUsingSingleDPPLuma < 2 * v->PixelClock[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2073
v->DPPCLKUsingSingleDPPLuma = 2 * v->PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2076
if ((v->SourcePixelFormat[k] != dm_420_8 && v->SourcePixelFormat[k] != dm_420_10 && v->SourcePixelFormat[k] != dm_420_12
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2077
&& v->SourcePixelFormat[k] != dm_rgbe_alpha)) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2078
v->PSCL_THROUGHPUT_CHROMA[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2079
v->DPPCLKUsingSingleDPP[k] = v->DPPCLKUsingSingleDPPLuma;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2081
if (v->HRatioChroma[k] > 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2082
v->PSCL_THROUGHPUT_CHROMA[k] = dml_min(
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2083
v->MaxDCHUBToPSCLThroughput,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2084
v->MaxPSCLToLBThroughput * v->HRatioChroma[k] / dml_ceil(v->HTAPsChroma[k] / 6.0, 1.0));
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2086
v->PSCL_THROUGHPUT_CHROMA[k] = dml_min(v->MaxDCHUBToPSCLThroughput, v->MaxPSCLToLBThroughput);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2088
v->DPPCLKUsingSingleDPPChroma = v->PixelClock[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2090
v->VTAPsChroma[k] / 6.0 * dml_min(1.0, v->HRatioChroma[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2091
v->HRatioChroma[k] * v->VRatioChroma[k] / v->PSCL_THROUGHPUT_CHROMA[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2094
if ((v->HTAPsChroma[k] > 6 || v->VTAPsChroma[k] > 6) && v->DPPCLKUsingSingleDPPChroma < 2 * v->PixelClock[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2095
v->DPPCLKUsingSingleDPPChroma = 2 * v->PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2098
v->DPPCLKUsingSingleDPP[k] = dml_max(v->DPPCLKUsingSingleDPPLuma, v->DPPCLKUsingSingleDPPChroma);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2102
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2103
if (v->BlendingAndTiming[k] != k)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2105
if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_4to1) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2106
v->DISPCLKWithRamping = dml_max(
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2107
v->DISPCLKWithRamping,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2108
v->PixelClock[k] / 4 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2109
* (1 + v->DISPCLKRampingMargin / 100));
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2110
v->DISPCLKWithoutRamping = dml_max(
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2111
v->DISPCLKWithoutRamping,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2112
v->PixelClock[k] / 4 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100));
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2113
} else if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_2to1) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2114
v->DISPCLKWithRamping = dml_max(
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2115
v->DISPCLKWithRamping,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2116
v->PixelClock[k] / 2 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2117
* (1 + v->DISPCLKRampingMargin / 100));
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2118
v->DISPCLKWithoutRamping = dml_max(
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2119
v->DISPCLKWithoutRamping,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2120
v->PixelClock[k] / 2 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100));
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2122
v->DISPCLKWithRamping = dml_max(
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2123
v->DISPCLKWithRamping,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2124
v->PixelClock[k] * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100) * (1 + v->DISPCLKRampingMargin / 100));
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2125
v->DISPCLKWithoutRamping = dml_max(
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2126
v->DISPCLKWithoutRamping,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2127
v->PixelClock[k] * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100));
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2131
v->DISPCLKWithRamping = dml_max(v->DISPCLKWithRamping, v->WritebackDISPCLK);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2132
v->DISPCLKWithoutRamping = dml_max(v->DISPCLKWithoutRamping, v->WritebackDISPCLK);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2134
ASSERT(v->DISPCLKDPPCLKVCOSpeed != 0);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2135
v->DISPCLKWithRampingRoundedToDFSGranularity = RoundToDFSGranularityUp(v->DISPCLKWithRamping, v->DISPCLKDPPCLKVCOSpeed);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2136
v->DISPCLKWithoutRampingRoundedToDFSGranularity = RoundToDFSGranularityUp(v->DISPCLKWithoutRamping, v->DISPCLKDPPCLKVCOSpeed);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2137
v->MaxDispclkRoundedToDFSGranularity = RoundToDFSGranularityDown(
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2138
v->soc.clock_limits[v->soc.num_states - 1].dispclk_mhz,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2139
v->DISPCLKDPPCLKVCOSpeed);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2140
if (v->DISPCLKWithoutRampingRoundedToDFSGranularity > v->MaxDispclkRoundedToDFSGranularity) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2141
v->DISPCLK_calculated = v->DISPCLKWithoutRampingRoundedToDFSGranularity;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2142
} else if (v->DISPCLKWithRampingRoundedToDFSGranularity > v->MaxDispclkRoundedToDFSGranularity) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2143
v->DISPCLK_calculated = v->MaxDispclkRoundedToDFSGranularity;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2145
v->DISPCLK_calculated = v->DISPCLKWithRampingRoundedToDFSGranularity;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2147
v->DISPCLK = v->DISPCLK_calculated;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2148
DTRACE(" dispclk_mhz (calculated) = %f", v->DISPCLK_calculated);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2150
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2151
v->DPPCLK_calculated[k] = v->DPPCLKUsingSingleDPP[k] / v->DPPPerPlane[k] * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2152
v->GlobalDPPCLK = dml_max(v->GlobalDPPCLK, v->DPPCLK_calculated[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2154
v->GlobalDPPCLK = RoundToDFSGranularityUp(v->GlobalDPPCLK, v->DISPCLKDPPCLKVCOSpeed);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2155
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2156
v->DPPCLK_calculated[k] = v->GlobalDPPCLK / 255 * dml_ceil(v->DPPCLK_calculated[k] * 255.0 / v->GlobalDPPCLK, 1);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2157
DTRACE(" dppclk_mhz[%i] (calculated) = %f", k, v->DPPCLK_calculated[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2160
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2161
v->DPPCLK[k] = v->DPPCLK_calculated[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2165
DTRACE(" dcfclk_mhz = %f", v->DCFCLK);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2166
DTRACE(" return_bus_bw = %f", v->ReturnBW);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2168
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2170
v->SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2171
v->SurfaceTiling[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2172
&v->BytePerPixelY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2173
&v->BytePerPixelC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2174
&v->BytePerPixelDETY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2175
&v->BytePerPixelDETC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2176
&v->BlockHeight256BytesY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2177
&v->BlockHeight256BytesC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2178
&v->BlockWidth256BytesY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2179
&v->BlockWidth256BytesC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2184
v->NumberOfActivePlanes,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2185
v->SourcePixelFormat,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2186
v->SourceScan,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2187
v->ViewportWidth,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2188
v->ViewportHeight,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2189
v->SurfaceWidthY,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2190
v->SurfaceWidthC,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2191
v->SurfaceHeightY,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2192
v->SurfaceHeightC,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2193
v->ODMCombineEnabled,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2194
v->BytePerPixelY,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2195
v->BytePerPixelC,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2196
v->BlockHeight256BytesY,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2197
v->BlockHeight256BytesC,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2198
v->BlockWidth256BytesY,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2199
v->BlockWidth256BytesC,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2200
v->BlendingAndTiming,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2201
v->HActive,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2202
v->HRatio,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2203
v->DPPPerPlane,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2204
v->SwathWidthSingleDPPY,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2205
v->SwathWidthSingleDPPC,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2206
v->SwathWidthY,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2207
v->SwathWidthC,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2208
v->dummyinteger3,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2209
v->dummyinteger4,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2210
v->swath_width_luma_ub,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2211
v->swath_width_chroma_ub);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2213
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2214
v->ReadBandwidthPlaneLuma[k] = v->SwathWidthSingleDPPY[k] * v->BytePerPixelY[k] / (v->HTotal[k] / v->PixelClock[k])
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2215
* v->VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2216
v->ReadBandwidthPlaneChroma[k] = v->SwathWidthSingleDPPC[k] * v->BytePerPixelC[k] / (v->HTotal[k] / v->PixelClock[k])
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2217
* v->VRatioChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2218
DTRACE(" read_bw[%i] = %fBps", k, v->ReadBandwidthPlaneLuma[k] + v->ReadBandwidthPlaneChroma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2224
v->NumberOfActivePlanes,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2225
v->BytePerPixelY,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2226
v->BytePerPixelC,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2227
v->VRatio,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2228
v->VRatioChroma,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2229
v->SwathWidthY,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2230
v->SwathWidthC,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2231
v->DPPPerPlane,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2232
v->HRatio,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2233
v->HRatioChroma,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2234
v->PixelClock,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2235
v->PSCL_THROUGHPUT_LUMA,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2236
v->PSCL_THROUGHPUT_CHROMA,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2237
v->DPPCLK,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2238
v->ReadBandwidthPlaneLuma,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2239
v->ReadBandwidthPlaneChroma,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2240
v->ReturnBusWidth,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2241
&v->DCFCLKDeepSleep);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2244
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2245
if ((v->BlendingAndTiming[k] != k) || !v->DSCEnabled[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2246
v->DSCCLK_calculated[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2248
if (v->OutputFormat[k] == dm_420)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2249
v->DSCFormatFactor = 2;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2250
else if (v->OutputFormat[k] == dm_444)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2251
v->DSCFormatFactor = 1;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2252
else if (v->OutputFormat[k] == dm_n422)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2253
v->DSCFormatFactor = 2;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2255
v->DSCFormatFactor = 1;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2256
if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_4to1)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2257
v->DSCCLK_calculated[k] = v->PixelClockBackEnd[k] / 12 / v->DSCFormatFactor
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2258
/ (1 - v->DISPCLKDPPCLKDSCCLKDownSpreading / 100);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2259
else if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_2to1)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2260
v->DSCCLK_calculated[k] = v->PixelClockBackEnd[k] / 6 / v->DSCFormatFactor
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2261
/ (1 - v->DISPCLKDPPCLKDSCCLKDownSpreading / 100);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2263
v->DSCCLK_calculated[k] = v->PixelClockBackEnd[k] / 3 / v->DSCFormatFactor
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2264
/ (1 - v->DISPCLKDPPCLKDSCCLKDownSpreading / 100);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2269
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2270
double BPP = v->OutputBpp[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2272
if (v->DSCEnabled[k] && BPP != 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2273
if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_disabled) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2274
v->DSCDelay[k] = dscceComputeDelay(
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2275
v->DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2277
dml_ceil((double) v->HActive[k] / v->NumberOfDSCSlices[k], 1),
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2278
v->NumberOfDSCSlices[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2279
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2280
v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2281
} else if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_2to1) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2282
v->DSCDelay[k] = 2
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2284
v->DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2286
dml_ceil((double) v->HActive[k] / v->NumberOfDSCSlices[k], 1),
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2287
v->NumberOfDSCSlices[k] / 2.0,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2288
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2289
v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k]));
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2291
v->DSCDelay[k] = 4
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2293
v->DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2295
dml_ceil((double) v->HActive[k] / v->NumberOfDSCSlices[k], 1),
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2296
v->NumberOfDSCSlices[k] / 4.0,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2297
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2298
v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k]));
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2300
v->DSCDelay[k] = v->DSCDelay[k] + (v->HTotal[k] - v->HActive[k]) * dml_ceil((double) v->DSCDelay[k] / v->HActive[k], 1);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2301
v->DSCDelay[k] = v->DSCDelay[k] * v->PixelClock[k] / v->PixelClockBackEnd[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2303
v->DSCDelay[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2307
for (k = 0; k < v->NumberOfActivePlanes; ++k)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2308
for (j = 0; j < v->NumberOfActivePlanes; ++j) // NumberOfPlanes
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2309
if (j != k && v->BlendingAndTiming[k] == j && v->DSCEnabled[j])
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2310
v->DSCDelay[k] = v->DSCDelay[j];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2313
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2323
if (v->SourcePixelFormat[k] == dm_420_8 || v->SourcePixelFormat[k] == dm_420_10 || v->SourcePixelFormat[k] == dm_420_12
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2324
|| v->SourcePixelFormat[k] == dm_rgbe_alpha) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2325
if ((v->SourcePixelFormat[k] == dm_420_10 || v->SourcePixelFormat[k] == dm_420_12) && v->SourceScan[k] != dm_vert) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2326
v->PTEBufferSizeInRequestsForLuma = (v->PTEBufferSizeInRequestsLuma + v->PTEBufferSizeInRequestsChroma) / 2;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2327
v->PTEBufferSizeInRequestsForChroma = v->PTEBufferSizeInRequestsForLuma;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2329
v->PTEBufferSizeInRequestsForLuma = v->PTEBufferSizeInRequestsLuma;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2330
v->PTEBufferSizeInRequestsForChroma = v->PTEBufferSizeInRequestsChroma;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2335
v->DCCEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2336
v->BlockHeight256BytesC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2337
v->BlockWidth256BytesC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2338
v->SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2339
v->SurfaceTiling[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2340
v->BytePerPixelC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2341
v->SourceScan[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2342
v->SwathWidthC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2343
v->ViewportHeightChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2344
v->GPUVMEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2345
v->HostVMEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2346
v->HostVMMaxNonCachedPageTableLevels,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2347
v->GPUVMMinPageSize,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2348
v->HostVMMinPageSize,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2349
v->PTEBufferSizeInRequestsForChroma,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2350
v->PitchC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2351
v->DCCMetaPitchC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2352
&v->MacroTileWidthC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2356
&v->dpte_row_width_chroma_ub[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2357
&v->dpte_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2358
&v->meta_req_width_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2359
&v->meta_req_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2360
&v->meta_row_width_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2361
&v->meta_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2362
&v->dummyinteger1,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2363
&v->dummyinteger2,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2364
&v->PixelPTEReqWidthC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2365
&v->PixelPTEReqHeightC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2366
&v->PTERequestSizeC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2367
&v->dpde0_bytes_per_frame_ub_c[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2368
&v->meta_pte_bytes_per_frame_ub_c[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2370
v->PrefetchSourceLinesC[k] = CalculatePrefetchSourceLines(
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2372
v->VRatioChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2373
v->VTAPsChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2374
v->Interlace[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2375
v->ProgressiveToInterlaceUnitInOPP,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2376
v->SwathHeightC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2377
v->ViewportYStartC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2378
&v->VInitPreFillC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2379
&v->MaxNumSwathC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2381
v->PTEBufferSizeInRequestsForLuma = v->PTEBufferSizeInRequestsLuma + v->PTEBufferSizeInRequestsChroma;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2382
v->PTEBufferSizeInRequestsForChroma = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2386
v->MaxNumSwathC[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2387
v->PrefetchSourceLinesC[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2392
v->DCCEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2393
v->BlockHeight256BytesY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2394
v->BlockWidth256BytesY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2395
v->SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2396
v->SurfaceTiling[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2397
v->BytePerPixelY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2398
v->SourceScan[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2399
v->SwathWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2400
v->ViewportHeight[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2401
v->GPUVMEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2402
v->HostVMEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2403
v->HostVMMaxNonCachedPageTableLevels,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2404
v->GPUVMMinPageSize,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2405
v->HostVMMinPageSize,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2406
v->PTEBufferSizeInRequestsForLuma,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2407
v->PitchY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2408
v->DCCMetaPitchY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2409
&v->MacroTileWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2413
&v->dpte_row_width_luma_ub[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2414
&v->dpte_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2415
&v->meta_req_width[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2416
&v->meta_req_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2417
&v->meta_row_width[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2418
&v->meta_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2419
&v->vm_group_bytes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2420
&v->dpte_group_bytes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2421
&v->PixelPTEReqWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2422
&v->PixelPTEReqHeightY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2423
&v->PTERequestSizeY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2424
&v->dpde0_bytes_per_frame_ub_l[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2425
&v->meta_pte_bytes_per_frame_ub_l[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2427
v->PrefetchSourceLinesY[k] = CalculatePrefetchSourceLines(
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2429
v->VRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2430
v->vtaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2431
v->Interlace[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2432
v->ProgressiveToInterlaceUnitInOPP,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2433
v->SwathHeightY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2434
v->ViewportYStartY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2435
&v->VInitPreFillY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2436
&v->MaxNumSwathY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2437
v->PixelPTEBytesPerRow[k] = PixelPTEBytesPerRowY + PixelPTEBytesPerRowC;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2438
v->PDEAndMetaPTEBytesFrame[k] = PDEAndMetaPTEBytesFrameY + PDEAndMetaPTEBytesFrameC;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2439
v->MetaRowByte[k] = MetaRowByteY + MetaRowByteC;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2442
v->GPUVMEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2443
v->SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2444
v->VRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2445
v->VRatioChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2446
v->DCCEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2447
v->HTotal[k] / v->PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2450
v->meta_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2451
v->meta_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2454
v->dpte_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2455
v->dpte_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2456
&v->meta_row_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2457
&v->dpte_row_bw[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2460
v->TotalDCCActiveDPP = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2461
v->TotalActiveDPP = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2462
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2463
v->TotalActiveDPP = v->TotalActiveDPP + v->DPPPerPlane[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2464
if (v->DCCEnable[k])
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2465
v->TotalDCCActiveDPP = v->TotalDCCActiveDPP + v->DPPPerPlane[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2466
if (v->SourcePixelFormat[k] == dm_420_8 || v->SourcePixelFormat[k] == dm_420_10 || v->SourcePixelFormat[k] == dm_420_12
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2467
|| v->SourcePixelFormat[k] == dm_rgbe_alpha)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2471
ReorderBytes = v->NumberOfChannels
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2473
v->UrgentOutOfOrderReturnPerChannelPixelDataOnly,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2474
v->UrgentOutOfOrderReturnPerChannelPixelMixedWithVMData,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2475
v->UrgentOutOfOrderReturnPerChannelVMDataOnly);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2478
dml_min(v->ReturnBusWidth * v->DCFCLK, v->FabricClock * v->FabricDatapathToDCNDataReturn)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2479
* v->PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency / 100.0,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2480
v->DRAMSpeed * v->NumberOfChannels * v->DRAMChannelWidth
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2481
* v->PercentOfIdealDRAMBWReceivedAfterUrgLatencyVMDataOnly / 100.0);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2484
dml_print("DML::%s: v->ReturnBusWidth = %f\n", __func__, v->ReturnBusWidth);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2485
dml_print("DML::%s: v->DCFCLK = %f\n", __func__, v->DCFCLK);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2486
dml_print("DML::%s: v->FabricClock = %f\n", __func__, v->FabricClock);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2487
dml_print("DML::%s: v->FabricDatapathToDCNDataReturn = %f\n", __func__, v->FabricDatapathToDCNDataReturn);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2488
dml_print("DML::%s: v->PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency = %f\n", __func__, v->PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2489
dml_print("DML::%s: v->DRAMSpeed = %f\n", __func__, v->DRAMSpeed);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2490
dml_print("DML::%s: v->NumberOfChannels = %f\n", __func__, v->NumberOfChannels);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2491
dml_print("DML::%s: v->DRAMChannelWidth = %f\n", __func__, v->DRAMChannelWidth);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2492
dml_print("DML::%s: v->PercentOfIdealDRAMBWReceivedAfterUrgLatencyVMDataOnly = %f\n", __func__, v->PercentOfIdealDRAMBWReceivedAfterUrgLatencyVMDataOnly);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2494
dml_print("DML::%s: ReturnBW = %f\n", __func__, v->ReturnBW);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2497
if (v->GPUVMEnable && v->HostVMEnable)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2498
HostVMInefficiencyFactor = v->ReturnBW / VMDataOnlyReturnBW;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2500
v->UrgentExtraLatency = CalculateExtraLatency(
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2501
v->RoundTripPingLatencyCycles,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2503
v->DCFCLK,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2504
v->TotalActiveDPP,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2505
v->PixelChunkSizeInKByte,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2506
v->TotalDCCActiveDPP,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2507
v->MetaChunkSize,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2508
v->ReturnBW,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2509
v->GPUVMEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2510
v->HostVMEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2511
v->NumberOfActivePlanes,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2512
v->DPPPerPlane,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2513
v->dpte_group_bytes,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2515
v->HostVMMinPageSize,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2516
v->HostVMMaxNonCachedPageTableLevels);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2518
v->TCalc = 24.0 / v->DCFCLKDeepSleep;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2520
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2521
if (v->BlendingAndTiming[k] == k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2522
if (v->WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2523
v->WritebackDelay[v->VoltageLevel][k] = v->WritebackLatency
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2525
v->WritebackPixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2526
v->WritebackHRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2527
v->WritebackVRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2528
v->WritebackVTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2529
v->WritebackDestinationWidth[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2530
v->WritebackDestinationHeight[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2531
v->WritebackSourceHeight[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2532
v->HTotal[k]) / v->DISPCLK;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2534
v->WritebackDelay[v->VoltageLevel][k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2535
for (j = 0; j < v->NumberOfActivePlanes; ++j) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2536
if (v->BlendingAndTiming[j] == k && v->WritebackEnable[j] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2537
v->WritebackDelay[v->VoltageLevel][k] = dml_max(
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2538
v->WritebackDelay[v->VoltageLevel][k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2539
v->WritebackLatency
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2541
v->WritebackPixelFormat[j],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2542
v->WritebackHRatio[j],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2543
v->WritebackVRatio[j],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2544
v->WritebackVTaps[j],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2545
v->WritebackDestinationWidth[j],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2546
v->WritebackDestinationHeight[j],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2547
v->WritebackSourceHeight[j],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2548
v->HTotal[k]) / v->DISPCLK);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2554
for (k = 0; k < v->NumberOfActivePlanes; ++k)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2555
for (j = 0; j < v->NumberOfActivePlanes; ++j)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2556
if (v->BlendingAndTiming[k] == j)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2557
v->WritebackDelay[v->VoltageLevel][k] = v->WritebackDelay[v->VoltageLevel][j];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2559
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2560
v->MaxVStartupLines[k] =
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2562
v->VTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2563
v->VActive[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2564
v->VBlankNom[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2565
v->HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2566
v->PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2567
v->ProgressiveToInterlaceUnitInOPP,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2568
v->Interlace[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2569
v->ip.VBlankNomDefaultUS,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2570
v->WritebackDelay[v->VoltageLevel][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2573
dml_print("DML::%s: k=%d MaxVStartupLines = %d\n", __func__, k, v->MaxVStartupLines[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2574
dml_print("DML::%s: k=%d VoltageLevel = %d\n", __func__, k, v->VoltageLevel);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2575
dml_print("DML::%s: k=%d WritebackDelay = %f\n", __func__, k, v->WritebackDelay[v->VoltageLevel][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2579
v->MaximumMaxVStartupLines = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2580
for (k = 0; k < v->NumberOfActivePlanes; ++k)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2581
v->MaximumMaxVStartupLines = dml_max(v->MaximumMaxVStartupLines, v->MaxVStartupLines[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2587
v->UrgentLatency = CalculateUrgentLatency(
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2588
v->UrgentLatencyPixelDataOnly,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2589
v->UrgentLatencyPixelMixedWithVMData,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2590
v->UrgentLatencyVMDataOnly,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2591
v->DoUrgentLatencyAdjustment,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2592
v->UrgentLatencyAdjustmentFabricClockComponent,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2593
v->UrgentLatencyAdjustmentFabricClockReference,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2594
v->FabricClock);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2596
v->FractionOfUrgentBandwidth = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2597
v->FractionOfUrgentBandwidthImmediateFlip = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2599
v->VStartupLines = __DML_VBA_MIN_VSTARTUP__;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2605
double TWait = CalculateTWait(PrefetchMode, v->DRAMClockChangeLatency, v->UrgentLatency, v->SREnterPlusExitTime);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2609
dml_print("DML::%s: Start loop: VStartup = %d\n", __func__, v->VStartupLines);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2611
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2614
myPipe.DPPCLK = v->DPPCLK[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2615
myPipe.DISPCLK = v->DISPCLK;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2616
myPipe.PixelClock = v->PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2617
myPipe.DCFCLKDeepSleep = v->DCFCLKDeepSleep;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2618
myPipe.DPPPerPlane = v->DPPPerPlane[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2619
myPipe.ScalerEnabled = v->ScalerEnabled[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2620
myPipe.VRatio = v->VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2621
myPipe.VRatioChroma = v->VRatioChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2622
myPipe.SourceScan = v->SourceScan[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2623
myPipe.BlockWidth256BytesY = v->BlockWidth256BytesY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2624
myPipe.BlockHeight256BytesY = v->BlockHeight256BytesY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2625
myPipe.BlockWidth256BytesC = v->BlockWidth256BytesC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2626
myPipe.BlockHeight256BytesC = v->BlockHeight256BytesC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2627
myPipe.InterlaceEnable = v->Interlace[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2628
myPipe.NumberOfCursors = v->NumberOfCursors[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2629
myPipe.VBlank = v->VTotal[k] - v->VActive[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2630
myPipe.HTotal = v->HTotal[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2631
myPipe.DCCEnable = v->DCCEnable[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2632
myPipe.ODMCombineIsEnabled = v->ODMCombineEnabled[k] == dm_odm_combine_mode_4to1
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2633
|| v->ODMCombineEnabled[k] == dm_odm_combine_mode_2to1;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2634
myPipe.SourcePixelFormat = v->SourcePixelFormat[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2635
myPipe.BytePerPixelY = v->BytePerPixelY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2636
myPipe.BytePerPixelC = v->BytePerPixelC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2637
myPipe.ProgressiveToInterlaceUnitInOPP = v->ProgressiveToInterlaceUnitInOPP;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2638
v->ErrorResult[k] = CalculatePrefetchSchedule(
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2642
v->DSCDelay[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2643
v->DPPCLKDelaySubtotal + v->DPPCLKDelayCNVCFormater,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2644
v->DPPCLKDelaySCL,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2645
v->DPPCLKDelaySCLLBOnly,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2646
v->DPPCLKDelayCNVCCursor,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2647
v->DISPCLKDelaySubtotal,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2648
(unsigned int) (v->SwathWidthY[k] / v->HRatio[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2649
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2650
v->MaxInterDCNTileRepeaters,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2651
dml_min(v->VStartupLines, v->MaxVStartupLines[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2652
v->MaxVStartupLines[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2653
v->GPUVMMaxPageTableLevels,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2654
v->GPUVMEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2655
v->HostVMEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2656
v->HostVMMaxNonCachedPageTableLevels,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2657
v->HostVMMinPageSize,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2658
v->DynamicMetadataEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2659
v->DynamicMetadataVMEnabled,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2660
v->DynamicMetadataLinesBeforeActiveRequired[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2661
v->DynamicMetadataTransmittedBytes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2662
v->UrgentLatency,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2663
v->UrgentExtraLatency,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2664
v->TCalc,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2665
v->PDEAndMetaPTEBytesFrame[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2666
v->MetaRowByte[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2667
v->PixelPTEBytesPerRow[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2668
v->PrefetchSourceLinesY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2669
v->SwathWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2670
v->VInitPreFillY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2671
v->MaxNumSwathY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2672
v->PrefetchSourceLinesC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2673
v->SwathWidthC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2674
v->VInitPreFillC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2675
v->MaxNumSwathC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2676
v->swath_width_luma_ub[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2677
v->swath_width_chroma_ub[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2678
v->SwathHeightY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2679
v->SwathHeightC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2681
&v->DSTXAfterScaler[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2682
&v->DSTYAfterScaler[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2683
&v->DestinationLinesForPrefetch[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2684
&v->PrefetchBandwidth[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2685
&v->DestinationLinesToRequestVMInVBlank[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2686
&v->DestinationLinesToRequestRowInVBlank[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2687
&v->VRatioPrefetchY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2688
&v->VRatioPrefetchC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2689
&v->RequiredPrefetchPixDataBWLuma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2690
&v->RequiredPrefetchPixDataBWChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2691
&v->NotEnoughTimeForDynamicMetadata[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2692
&v->Tno_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2693
&v->prefetch_vmrow_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2694
&v->Tdmdl_vm[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2695
&v->Tdmdl[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2696
&v->TSetup[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2697
&v->VUpdateOffsetPix[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2698
&v->VUpdateWidthPix[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2699
&v->VReadyOffsetPix[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2702
dml_print("DML::%s: k=%0d Prefetch cal result=%0d\n", __func__, k, v->ErrorResult[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2704
v->VStartup[k] = dml_min(v->VStartupLines, v->MaxVStartupLines[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2707
v->NoEnoughUrgentLatencyHiding = false;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2708
v->NoEnoughUrgentLatencyHidingPre = false;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2710
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2711
v->cursor_bw[k] = v->NumberOfCursors[k] * v->CursorWidth[k][0] * v->CursorBPP[k][0] / 8.0
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2712
/ (v->HTotal[k] / v->PixelClock[k]) * v->VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2713
v->cursor_bw_pre[k] = v->NumberOfCursors[k] * v->CursorWidth[k][0] * v->CursorBPP[k][0] / 8.0
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2714
/ (v->HTotal[k] / v->PixelClock[k]) * v->VRatioPrefetchY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2717
v->swath_width_luma_ub[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2718
v->swath_width_chroma_ub[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2719
v->SwathHeightY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2720
v->SwathHeightC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2721
v->HTotal[k] / v->PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2722
v->UrgentLatency,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2723
v->CursorBufferSize,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2724
v->CursorWidth[k][0],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2725
v->CursorBPP[k][0],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2726
v->VRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2727
v->VRatioChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2728
v->BytePerPixelDETY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2729
v->BytePerPixelDETC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2730
v->DETBufferSizeY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2731
v->DETBufferSizeC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2732
&v->UrgBurstFactorCursor[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2733
&v->UrgBurstFactorLuma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2734
&v->UrgBurstFactorChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2735
&v->NoUrgentLatencyHiding[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2738
v->swath_width_luma_ub[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2739
v->swath_width_chroma_ub[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2740
v->SwathHeightY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2741
v->SwathHeightC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2742
v->HTotal[k] / v->PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2743
v->UrgentLatency,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2744
v->CursorBufferSize,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2745
v->CursorWidth[k][0],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2746
v->CursorBPP[k][0],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2747
v->VRatioPrefetchY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2748
v->VRatioPrefetchC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2749
v->BytePerPixelDETY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2750
v->BytePerPixelDETC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2751
v->DETBufferSizeY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2752
v->DETBufferSizeC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2753
&v->UrgBurstFactorCursorPre[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2754
&v->UrgBurstFactorLumaPre[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2755
&v->UrgBurstFactorChromaPre[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2756
&v->NoUrgentLatencyHidingPre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2760
v->DPPPerPlane[k] * v->prefetch_vmrow_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2761
v->ReadBandwidthPlaneLuma[k] * v->UrgBurstFactorLuma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2762
+ v->ReadBandwidthPlaneChroma[k] * v->UrgBurstFactorChroma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2763
+ v->cursor_bw[k] * v->UrgBurstFactorCursor[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2764
+ v->DPPPerPlane[k] * (v->meta_row_bw[k] + v->dpte_row_bw[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2765
v->DPPPerPlane[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2766
* (v->RequiredPrefetchPixDataBWLuma[k] * v->UrgBurstFactorLumaPre[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2767
+ v->RequiredPrefetchPixDataBWChroma[k] * v->UrgBurstFactorChromaPre[k])
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2768
+ v->cursor_bw_pre[k] * v->UrgBurstFactorCursorPre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2772
v->DPPPerPlane[k] * v->prefetch_vmrow_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2773
v->ReadBandwidthPlaneLuma[k] + v->ReadBandwidthPlaneChroma[k] + v->cursor_bw[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2774
+ v->DPPPerPlane[k] * (v->meta_row_bw[k] + v->dpte_row_bw[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2775
v->DPPPerPlane[k] * (v->RequiredPrefetchPixDataBWLuma[k] + v->RequiredPrefetchPixDataBWChroma[k])
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2776
+ v->cursor_bw_pre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2779
dml_print("DML::%s: k=%0d DPPPerPlane=%d\n", __func__, k, v->DPPPerPlane[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2780
dml_print("DML::%s: k=%0d UrgBurstFactorLuma=%f\n", __func__, k, v->UrgBurstFactorLuma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2781
dml_print("DML::%s: k=%0d UrgBurstFactorChroma=%f\n", __func__, k, v->UrgBurstFactorChroma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2782
dml_print("DML::%s: k=%0d UrgBurstFactorLumaPre=%f\n", __func__, k, v->UrgBurstFactorLumaPre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2783
dml_print("DML::%s: k=%0d UrgBurstFactorChromaPre=%f\n", __func__, k, v->UrgBurstFactorChromaPre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2785
dml_print("DML::%s: k=%0d VRatioPrefetchY=%f\n", __func__, k, v->VRatioPrefetchY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2786
dml_print("DML::%s: k=%0d VRatioY=%f\n", __func__, k, v->VRatio[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2788
dml_print("DML::%s: k=%0d prefetch_vmrow_bw=%f\n", __func__, k, v->prefetch_vmrow_bw[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2789
dml_print("DML::%s: k=%0d ReadBandwidthPlaneLuma=%f\n", __func__, k, v->ReadBandwidthPlaneLuma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2790
dml_print("DML::%s: k=%0d ReadBandwidthPlaneChroma=%f\n", __func__, k, v->ReadBandwidthPlaneChroma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2791
dml_print("DML::%s: k=%0d cursor_bw=%f\n", __func__, k, v->cursor_bw[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2792
dml_print("DML::%s: k=%0d meta_row_bw=%f\n", __func__, k, v->meta_row_bw[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2793
dml_print("DML::%s: k=%0d dpte_row_bw=%f\n", __func__, k, v->dpte_row_bw[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2794
dml_print("DML::%s: k=%0d RequiredPrefetchPixDataBWLuma=%f\n", __func__, k, v->RequiredPrefetchPixDataBWLuma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2795
dml_print("DML::%s: k=%0d RequiredPrefetchPixDataBWChroma=%f\n", __func__, k, v->RequiredPrefetchPixDataBWChroma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2796
dml_print("DML::%s: k=%0d cursor_bw_pre=%f\n", __func__, k, v->cursor_bw_pre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2800
if (v->DestinationLinesForPrefetch[k] < 2)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2803
if (v->VRatioPrefetchY[k] > 4 || v->VRatioPrefetchC[k] > 4)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2806
if (v->NoUrgentLatencyHiding[k] == true)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2807
v->NoEnoughUrgentLatencyHiding = true;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2809
if (v->NoUrgentLatencyHidingPre[k] == true)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2810
v->NoEnoughUrgentLatencyHidingPre = true;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2813
v->FractionOfUrgentBandwidth = MaxTotalRDBandwidthNoUrgentBurst / v->ReturnBW;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2817
dml_print("DML::%s: ReturnBW=%f\n", __func__, v->ReturnBW);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2818
dml_print("DML::%s: FractionOfUrgentBandwidth=%f\n", __func__, v->FractionOfUrgentBandwidth);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2821
if (MaxTotalRDBandwidth <= v->ReturnBW && v->NoEnoughUrgentLatencyHiding == 0 && v->NoEnoughUrgentLatencyHidingPre == 0
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2823
v->PrefetchModeSupported = true;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2825
v->PrefetchModeSupported = false;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2827
dml_print("DML::%s: MaxTotalRDBandwidth:%f AvailReturnBandwidth:%f\n", __func__, MaxTotalRDBandwidth, v->ReturnBW);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2835
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2836
if (v->ErrorResult[k] == true || v->NotEnoughTimeForDynamicMetadata[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2837
v->PrefetchModeSupported = false;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2842
if (v->PrefetchModeSupported == true && v->ImmediateFlipSupport == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2843
v->BandwidthAvailableForImmediateFlip = v->ReturnBW;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2844
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2845
v->BandwidthAvailableForImmediateFlip = v->BandwidthAvailableForImmediateFlip
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2847
v->ReadBandwidthPlaneLuma[k] * v->UrgBurstFactorLuma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2848
+ v->ReadBandwidthPlaneChroma[k] * v->UrgBurstFactorChroma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2849
+ v->cursor_bw[k] * v->UrgBurstFactorCursor[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2850
v->DPPPerPlane[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2851
* (v->RequiredPrefetchPixDataBWLuma[k] * v->UrgBurstFactorLumaPre[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2852
+ v->RequiredPrefetchPixDataBWChroma[k] * v->UrgBurstFactorChromaPre[k])
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2853
+ v->cursor_bw_pre[k] * v->UrgBurstFactorCursorPre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2856
v->TotImmediateFlipBytes = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2857
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2858
v->TotImmediateFlipBytes = v->TotImmediateFlipBytes
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2859
+ v->DPPPerPlane[k] * (v->PDEAndMetaPTEBytesFrame[k] + v->MetaRowByte[k] + v->PixelPTEBytesPerRow[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2861
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2866
v->UrgentExtraLatency,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2867
v->UrgentLatency,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2868
v->PDEAndMetaPTEBytesFrame[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2869
v->MetaRowByte[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2870
v->PixelPTEBytesPerRow[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2873
v->total_dcn_read_bw_with_flip = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2874
v->total_dcn_read_bw_with_flip_no_urgent_burst = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2875
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2876
v->total_dcn_read_bw_with_flip = v->total_dcn_read_bw_with_flip
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2878
v->DPPPerPlane[k] * v->prefetch_vmrow_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2879
v->DPPPerPlane[k] * v->final_flip_bw[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2880
+ v->ReadBandwidthLuma[k] * v->UrgBurstFactorLuma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2881
+ v->ReadBandwidthChroma[k] * v->UrgBurstFactorChroma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2882
+ v->cursor_bw[k] * v->UrgBurstFactorCursor[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2883
v->DPPPerPlane[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2884
* (v->final_flip_bw[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2885
+ v->RequiredPrefetchPixDataBWLuma[k] * v->UrgBurstFactorLumaPre[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2886
+ v->RequiredPrefetchPixDataBWChroma[k] * v->UrgBurstFactorChromaPre[k])
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2887
+ v->cursor_bw_pre[k] * v->UrgBurstFactorCursorPre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2888
v->total_dcn_read_bw_with_flip_no_urgent_burst = v->total_dcn_read_bw_with_flip_no_urgent_burst
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2890
v->DPPPerPlane[k] * v->prefetch_vmrow_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2891
v->DPPPerPlane[k] * v->final_flip_bw[k] + v->ReadBandwidthPlaneLuma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2892
+ v->ReadBandwidthPlaneChroma[k] + v->cursor_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2893
v->DPPPerPlane[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2894
* (v->final_flip_bw[k] + v->RequiredPrefetchPixDataBWLuma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2895
+ v->RequiredPrefetchPixDataBWChroma[k]) + v->cursor_bw_pre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2897
v->FractionOfUrgentBandwidthImmediateFlip = v->total_dcn_read_bw_with_flip_no_urgent_burst / v->ReturnBW;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2899
v->ImmediateFlipSupported = true;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2900
if (v->total_dcn_read_bw_with_flip > v->ReturnBW) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2902
dml_print("DML::%s: total_dcn_read_bw_with_flip %f (bw w/ flip too high!)\n", __func__, v->total_dcn_read_bw_with_flip);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2904
v->ImmediateFlipSupported = false;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2905
v->total_dcn_read_bw_with_flip = MaxTotalRDBandwidth;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2907
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2908
if (v->ImmediateFlipSupportedForPipe[k] == false) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2912
v->ImmediateFlipSupported = false;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2916
v->ImmediateFlipSupported = false;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2919
v->PrefetchAndImmediateFlipSupported =
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2920
(v->PrefetchModeSupported == true && ((!v->ImmediateFlipSupport && !v->HostVMEnable
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2921
&& v->ImmediateFlipRequirement[0] != dm_immediate_flip_required) ||
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2922
v->ImmediateFlipSupported)) ? true : false;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2924
dml_print("DML::%s: PrefetchModeSupported %d\n", __func__, v->PrefetchModeSupported);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2925
dml_print("DML::%s: ImmediateFlipRequirement %d\n", __func__, v->ImmediateFlipRequirement == dm_immediate_flip_required);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2926
dml_print("DML::%s: ImmediateFlipSupported %d\n", __func__, v->ImmediateFlipSupported);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2927
dml_print("DML::%s: ImmediateFlipSupport %d\n", __func__, v->ImmediateFlipSupport);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2928
dml_print("DML::%s: HostVMEnable %d\n", __func__, v->HostVMEnable);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2929
dml_print("DML::%s: PrefetchAndImmediateFlipSupported %d\n", __func__, v->PrefetchAndImmediateFlipSupported);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2931
dml_print("DML::%s: Done loop: Vstartup=%d, Max Vstartup is %d\n", __func__, v->VStartupLines, v->MaximumMaxVStartupLines);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2933
v->VStartupLines = v->VStartupLines + 1;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2934
} while (!v->PrefetchAndImmediateFlipSupported && v->VStartupLines <= v->MaximumMaxVStartupLines);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2935
ASSERT(v->PrefetchAndImmediateFlipSupported);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2939
v->DETBufferSizeInKByte[0],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2940
v->ConfigReturnBufferSizeInKByte,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2941
v->UseUnboundedRequesting,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2942
v->TotalActiveDPP,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2944
v->MaxNumDPP,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2945
v->CompressedBufferSegmentSizeInkByte,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2946
v->Output,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2947
&v->UnboundedRequestEnabled,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2948
&v->CompressedBufferSizeInkByte);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2957
v->DCFCLK,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2958
v->ReturnBW,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2959
v->UrgentLatency,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2960
v->UrgentExtraLatency,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2961
v->SOCCLK,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2962
v->DCFCLKDeepSleep,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2963
v->DETBufferSizeY,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2964
v->DETBufferSizeC,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2965
v->SwathHeightY,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2966
v->SwathHeightC,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2967
v->SwathWidthY,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2968
v->SwathWidthC,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2969
v->DPPPerPlane,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2970
v->BytePerPixelDETY,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2971
v->BytePerPixelDETC,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2972
v->UnboundedRequestEnabled,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2973
v->CompressedBufferSizeInkByte,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2975
&v->StutterExitWatermark,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2976
&v->StutterEnterPlusExitWatermark,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2977
&v->Z8StutterExitWatermark,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2978
&v->Z8StutterEnterPlusExitWatermark);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2980
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2981
if (v->WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2982
v->WritebackAllowDRAMClockChangeEndPosition[k] = dml_max(
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2984
v->VStartup[k] * v->HTotal[k] / v->PixelClock[k] - v->WritebackDRAMClockChangeWatermark);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2986
v->WritebackAllowDRAMClockChangeEndPosition[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2993
v->NumberOfActivePlanes,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2994
v->VRatio,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2995
v->VRatioChroma,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2996
v->VRatioPrefetchY,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2997
v->VRatioPrefetchC,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2998
v->swath_width_luma_ub,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
2999
v->swath_width_chroma_ub,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3000
v->DPPPerPlane,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3001
v->HRatio,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3002
v->HRatioChroma,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3003
v->PixelClock,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3004
v->PSCL_THROUGHPUT_LUMA,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3005
v->PSCL_THROUGHPUT_CHROMA,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3006
v->DPPCLK,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3007
v->BytePerPixelC,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3008
v->SourceScan,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3009
v->NumberOfCursors,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3010
v->CursorWidth,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3011
v->CursorBPP,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3012
v->BlockWidth256BytesY,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3013
v->BlockHeight256BytesY,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3014
v->BlockWidth256BytesC,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3015
v->BlockHeight256BytesC,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3016
v->DisplayPipeLineDeliveryTimeLuma,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3017
v->DisplayPipeLineDeliveryTimeChroma,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3018
v->DisplayPipeLineDeliveryTimeLumaPrefetch,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3019
v->DisplayPipeLineDeliveryTimeChromaPrefetch,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3020
v->DisplayPipeRequestDeliveryTimeLuma,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3021
v->DisplayPipeRequestDeliveryTimeChroma,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3022
v->DisplayPipeRequestDeliveryTimeLumaPrefetch,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3023
v->DisplayPipeRequestDeliveryTimeChromaPrefetch,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3024
v->CursorRequestDeliveryTime,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3025
v->CursorRequestDeliveryTimePrefetch);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3028
v->NumberOfActivePlanes,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3029
v->GPUVMEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3030
v->MetaChunkSize,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3031
v->MinMetaChunkSizeBytes,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3032
v->HTotal,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3033
v->VRatio,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3034
v->VRatioChroma,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3035
v->DestinationLinesToRequestRowInVBlank,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3036
v->DestinationLinesToRequestRowInImmediateFlip,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3037
v->DCCEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3038
v->PixelClock,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3039
v->BytePerPixelY,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3040
v->BytePerPixelC,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3041
v->SourceScan,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3042
v->dpte_row_height,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3043
v->dpte_row_height_chroma,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3044
v->meta_row_width,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3045
v->meta_row_width_chroma,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3046
v->meta_row_height,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3047
v->meta_row_height_chroma,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3048
v->meta_req_width,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3049
v->meta_req_width_chroma,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3050
v->meta_req_height,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3051
v->meta_req_height_chroma,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3052
v->dpte_group_bytes,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3053
v->PTERequestSizeY,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3054
v->PTERequestSizeC,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3055
v->PixelPTEReqWidthY,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3056
v->PixelPTEReqHeightY,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3057
v->PixelPTEReqWidthC,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3058
v->PixelPTEReqHeightC,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3059
v->dpte_row_width_luma_ub,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3060
v->dpte_row_width_chroma_ub,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3061
v->DST_Y_PER_PTE_ROW_NOM_L,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3062
v->DST_Y_PER_PTE_ROW_NOM_C,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3063
v->DST_Y_PER_META_ROW_NOM_L,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3064
v->DST_Y_PER_META_ROW_NOM_C,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3065
v->TimePerMetaChunkNominal,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3066
v->TimePerChromaMetaChunkNominal,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3067
v->TimePerMetaChunkVBlank,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3068
v->TimePerChromaMetaChunkVBlank,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3069
v->TimePerMetaChunkFlip,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3070
v->TimePerChromaMetaChunkFlip,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3071
v->time_per_pte_group_nom_luma,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3072
v->time_per_pte_group_vblank_luma,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3073
v->time_per_pte_group_flip_luma,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3074
v->time_per_pte_group_nom_chroma,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3075
v->time_per_pte_group_vblank_chroma,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3076
v->time_per_pte_group_flip_chroma);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3079
v->NumberOfActivePlanes,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3080
v->GPUVMEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3081
v->GPUVMMaxPageTableLevels,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3082
v->HTotal,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3083
v->BytePerPixelC,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3084
v->DestinationLinesToRequestVMInVBlank,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3085
v->DestinationLinesToRequestVMInImmediateFlip,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3086
v->DCCEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3087
v->PixelClock,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3088
v->dpte_row_width_luma_ub,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3089
v->dpte_row_width_chroma_ub,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3090
v->vm_group_bytes,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3091
v->dpde0_bytes_per_frame_ub_l,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3092
v->dpde0_bytes_per_frame_ub_c,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3093
v->meta_pte_bytes_per_frame_ub_l,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3094
v->meta_pte_bytes_per_frame_ub_c,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3095
v->TimePerVMGroupVBlank,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3096
v->TimePerVMGroupFlip,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3097
v->TimePerVMRequestVBlank,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3098
v->TimePerVMRequestFlip);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3101
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3103
v->AllowDRAMClockChangeDuringVBlank[k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3104
v->AllowDRAMSelfRefreshDuringVBlank[k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3105
v->MinTTUVBlank[k] = dml_max(
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3106
v->DRAMClockChangeWatermark,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3107
dml_max(v->StutterEnterPlusExitWatermark, v->UrgentWatermark));
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3109
v->AllowDRAMClockChangeDuringVBlank[k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3110
v->AllowDRAMSelfRefreshDuringVBlank[k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3111
v->MinTTUVBlank[k] = dml_max(v->StutterEnterPlusExitWatermark, v->UrgentWatermark);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3113
v->AllowDRAMClockChangeDuringVBlank[k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3114
v->AllowDRAMSelfRefreshDuringVBlank[k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3115
v->MinTTUVBlank[k] = v->UrgentWatermark;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3117
if (!v->DynamicMetadataEnable[k])
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3118
v->MinTTUVBlank[k] = v->TCalc + v->MinTTUVBlank[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3122
v->ActiveDPPs = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3123
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3124
CalculateDCCConfiguration(v->DCCEnable[k], false, // We should always know the direction DCCProgrammingAssumesScanDirectionUnknown,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3125
v->SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3126
v->SurfaceWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3127
v->SurfaceWidthC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3128
v->SurfaceHeightY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3129
v->SurfaceHeightC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3130
v->DETBufferSizeInKByte[0] * 1024,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3131
v->BlockHeight256BytesY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3132
v->BlockHeight256BytesC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3133
v->SurfaceTiling[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3134
v->BytePerPixelY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3135
v->BytePerPixelC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3136
v->BytePerPixelDETY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3137
v->BytePerPixelDETC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3138
v->SourceScan[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3139
&v->DCCYMaxUncompressedBlock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3140
&v->DCCCMaxUncompressedBlock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3141
&v->DCCYMaxCompressedBlock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3142
&v->DCCCMaxCompressedBlock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3143
&v->DCCYIndependentBlock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3144
&v->DCCCIndependentBlock[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3148
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3150
double Tvstartup_margin = (v->MaxVStartupLines[k] - v->VStartup[k]) * v->HTotal[k] / v->PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3152
dml_print("DML::%s: k=%d, MinTTUVBlank = %f (before margin)\n", __func__, k, v->MinTTUVBlank[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3155
v->MinTTUVBlank[k] = v->MinTTUVBlank[k] + Tvstartup_margin;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3159
dml_print("DML::%s: k=%d, MaxVStartupLines = %d\n", __func__, k, v->MaxVStartupLines[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3160
dml_print("DML::%s: k=%d, VStartup = %d\n", __func__, k, v->VStartup[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3161
dml_print("DML::%s: k=%d, MinTTUVBlank = %f\n", __func__, k, v->MinTTUVBlank[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3164
v->Tdmdl[k] = v->Tdmdl[k] + Tvstartup_margin;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3165
if (v->DynamicMetadataEnable[k] && v->DynamicMetadataVMEnabled) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3166
v->Tdmdl_vm[k] = v->Tdmdl_vm[k] + Tvstartup_margin;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3169
isInterlaceTiming = (v->Interlace[k] && !v->ProgressiveToInterlaceUnitInOPP);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3170
v->VStartup[k] = (isInterlaceTiming ? (2 * v->MaxVStartupLines[k]) : v->MaxVStartupLines[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3171
if (v->Interlace[k] && !v->ProgressiveToInterlaceUnitInOPP) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3172
v->MIN_DST_Y_NEXT_START[k] = dml_floor((v->VTotal[k] - v->VFrontPorch[k] + v->VTotal[k] - v->VActive[k] - v->VStartup[k]) / 2.0, 1.0);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3174
v->MIN_DST_Y_NEXT_START[k] = v->VTotal[k] - v->VFrontPorch[k] + v->VTotal[k] - v->VActive[k] - v->VStartup[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3176
v->MIN_DST_Y_NEXT_START[k] += dml_floor(4.0 * v->TSetup[k] / ((double)v->HTotal[k] / v->PixelClock[k]), 1.0) / 4.0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3177
if (((v->VUpdateOffsetPix[k] + v->VUpdateWidthPix[k] + v->VReadyOffsetPix[k]) / v->HTotal[k])
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3179
dml_floor((v->VTotal[k] - v->VActive[k] - v->VFrontPorch[k] - v->VStartup[k]) / 2.0, 1.0) :
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3180
(int) (v->VTotal[k] - v->VActive[k] - v->VFrontPorch[k] - v->VStartup[k]))) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3181
v->VREADY_AT_OR_AFTER_VSYNC[k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3183
v->VREADY_AT_OR_AFTER_VSYNC[k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3186
dml_print("DML::%s: k=%d, VStartup = %d (max)\n", __func__, k, v->VStartup[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3187
dml_print("DML::%s: k=%d, VUpdateOffsetPix = %d\n", __func__, k, v->VUpdateOffsetPix[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3188
dml_print("DML::%s: k=%d, VUpdateWidthPix = %d\n", __func__, k, v->VUpdateWidthPix[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3189
dml_print("DML::%s: k=%d, VReadyOffsetPix = %d\n", __func__, k, v->VReadyOffsetPix[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3190
dml_print("DML::%s: k=%d, HTotal = %d\n", __func__, k, v->HTotal[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3191
dml_print("DML::%s: k=%d, VTotal = %d\n", __func__, k, v->VTotal[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3192
dml_print("DML::%s: k=%d, VActive = %d\n", __func__, k, v->VActive[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3193
dml_print("DML::%s: k=%d, VFrontPorch = %d\n", __func__, k, v->VFrontPorch[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3194
dml_print("DML::%s: k=%d, VStartup = %d\n", __func__, k, v->VStartup[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3195
dml_print("DML::%s: k=%d, MIN_DST_Y_NEXT_START = %f\n", __func__, k, v->MIN_DST_Y_NEXT_START[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3196
dml_print("DML::%s: k=%d, VREADY_AT_OR_AFTER_VSYNC = %d\n", __func__, k, v->VREADY_AT_OR_AFTER_VSYNC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3206
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3207
if (v->WritebackEnable[k] == true && v->WritebackPixelFormat[k] == dm_444_32) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3208
WRBandwidth = v->WritebackDestinationWidth[k] * v->WritebackDestinationHeight[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3209
/ (v->HTotal[k] * v->WritebackSourceHeight[k] / v->PixelClock[k]) * 4;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3210
} else if (v->WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3211
WRBandwidth = v->WritebackDestinationWidth[k] * v->WritebackDestinationHeight[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3212
/ (v->HTotal[k] * v->WritebackSourceHeight[k] / v->PixelClock[k]) * 8;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3218
v->TotalDataReadBandwidth = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3219
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3220
v->TotalDataReadBandwidth = v->TotalDataReadBandwidth + v->ReadBandwidthPlaneLuma[k] + v->ReadBandwidthPlaneChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3226
v->CompressedBufferSizeInkByte,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3227
v->UnboundedRequestEnabled,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3228
v->ConfigReturnBufferSizeInKByte,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3229
v->MetaFIFOSizeInKEntries,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3230
v->ZeroSizeBufferEntries,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3231
v->NumberOfActivePlanes,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3232
v->ROBBufferSizeInKByte,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3233
v->TotalDataReadBandwidth,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3234
v->DCFCLK,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3235
v->ReturnBW,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3236
v->COMPBUF_RESERVED_SPACE_64B,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3237
v->COMPBUF_RESERVED_SPACE_ZS,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3238
v->SRExitTime,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3239
v->SRExitZ8Time,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3240
v->SynchronizedVBlank,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3241
v->StutterEnterPlusExitWatermark,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3242
v->Z8StutterEnterPlusExitWatermark,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3243
v->ProgressiveToInterlaceUnitInOPP,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3244
v->Interlace,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3245
v->MinTTUVBlank,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3246
v->DPPPerPlane,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3247
v->DETBufferSizeY,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3248
v->BytePerPixelY,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3249
v->BytePerPixelDETY,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3250
v->SwathWidthY,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3251
v->SwathHeightY,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3252
v->SwathHeightC,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3253
v->DCCRateLuma,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3254
v->DCCRateChroma,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3255
v->DCCFractionOfZeroSizeRequestsLuma,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3256
v->DCCFractionOfZeroSizeRequestsChroma,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3257
v->HTotal,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3258
v->VTotal,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3259
v->PixelClock,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3260
v->VRatio,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3261
v->SourceScan,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3262
v->BlockHeight256BytesY,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3263
v->BlockWidth256BytesY,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3264
v->BlockHeight256BytesC,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3265
v->BlockWidth256BytesC,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3266
v->DCCYMaxUncompressedBlock,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3267
v->DCCCMaxUncompressedBlock,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3268
v->VActive,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3269
v->DCCEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3270
v->WritebackEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3271
v->ReadBandwidthPlaneLuma,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3272
v->ReadBandwidthPlaneChroma,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3273
v->meta_row_bw,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3274
v->dpte_row_bw,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3275
&v->StutterEfficiencyNotIncludingVBlank,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3276
&v->StutterEfficiency,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3277
&v->NumberOfStutterBurstsPerFrame,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3278
&v->Z8StutterEfficiencyNotIncludingVBlank,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3279
&v->Z8StutterEfficiency,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3280
&v->Z8NumberOfStutterBurstsPerFrame,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3281
&v->StutterPeriod);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3286
struct vba_vars_st *v = &mode_lib->vba;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3307
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3310
v->SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3311
v->SurfaceTiling[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3324
v->NumberOfActivePlanes,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3325
v->DETBufferSizeInKByte[0],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3328
v->SourceScan,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3329
v->SourcePixelFormat,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3330
v->SurfaceTiling,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3331
v->ViewportWidth,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3332
v->ViewportHeight,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3333
v->SurfaceWidthY,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3334
v->SurfaceWidthC,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3335
v->SurfaceHeightY,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3336
v->SurfaceHeightC,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3341
v->ODMCombineEnabled,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3342
v->BlendingAndTiming,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3347
v->HActive,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3348
v->HRatio,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3349
v->HRatioChroma,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3350
v->DPPPerPlane,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3355
v->SwathHeightY,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3356
v->SwathHeightC,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3357
v->DETBufferSizeY,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3358
v->DETBufferSizeC,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3598
struct vba_vars_st *v = &mode_lib->vba;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3604
double LineTime = v->HTotal[k] / v->PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3606
if (v->GPUVMEnable == true && v->HostVMEnable == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3607
HostVMDynamicLevelsTrips = v->HostVMMaxNonCachedPageTableLevels;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3612
if (v->GPUVMEnable == true || v->DCCEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3613
ImmediateFlipBW = (PDEAndMetaPTEBytesPerFrame + MetaRowBytes + DPTEBytesPerRow) * v->BandwidthAvailableForImmediateFlip / v->TotImmediateFlipBytes;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3616
if (v->GPUVMEnable == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3618
v->Tno_bw[k] + PDEAndMetaPTEBytesPerFrame * HostVMInefficiencyFactor / ImmediateFlipBW,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3619
UrgentExtraLatency + UrgentLatency * (v->GPUVMMaxPageTableLevels * (HostVMDynamicLevelsTrips + 1) - 1),
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3625
v->DestinationLinesToRequestVMInImmediateFlip[k] = dml_ceil(4.0 * (TimeForFetchingMetaPTEImmediateFlip / LineTime), 1) / 4.0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3626
if ((v->GPUVMEnable == true || v->DCCEnable[k] == true)) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3635
v->DestinationLinesToRequestRowInImmediateFlip[k] = dml_ceil(4.0 * (TimeForFetchingRowInVBlankImmediateFlip / LineTime), 1) / 4.0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3637
if (v->GPUVMEnable == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3638
v->final_flip_bw[k] = dml_max(
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3639
PDEAndMetaPTEBytesPerFrame * HostVMInefficiencyFactor / (v->DestinationLinesToRequestVMInImmediateFlip[k] * LineTime),
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3640
(MetaRowBytes + DPTEBytesPerRow * HostVMInefficiencyFactor) / (v->DestinationLinesToRequestRowInImmediateFlip[k] * LineTime));
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3641
} else if ((v->GPUVMEnable == true || v->DCCEnable[k] == true)) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3642
v->final_flip_bw[k] = (MetaRowBytes + DPTEBytesPerRow * HostVMInefficiencyFactor) / (v->DestinationLinesToRequestRowInImmediateFlip[k] * LineTime);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3644
v->final_flip_bw[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3647
if (v->SourcePixelFormat[k] == dm_420_8 || v->SourcePixelFormat[k] == dm_420_10 || v->SourcePixelFormat[k] == dm_rgbe_alpha) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3648
if (v->GPUVMEnable == true && v->DCCEnable[k] != true) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3649
min_row_time = dml_min(v->dpte_row_height[k] * LineTime / v->VRatio[k], v->dpte_row_height_chroma[k] * LineTime / v->VRatioChroma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3650
} else if (v->GPUVMEnable != true && v->DCCEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3651
min_row_time = dml_min(v->meta_row_height[k] * LineTime / v->VRatio[k], v->meta_row_height_chroma[k] * LineTime / v->VRatioChroma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3654
v->dpte_row_height[k] * LineTime / v->VRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3655
v->meta_row_height[k] * LineTime / v->VRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3656
v->dpte_row_height_chroma[k] * LineTime / v->VRatioChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3657
v->meta_row_height_chroma[k] * LineTime / v->VRatioChroma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3660
if (v->GPUVMEnable == true && v->DCCEnable[k] != true) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3661
min_row_time = v->dpte_row_height[k] * LineTime / v->VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3662
} else if (v->GPUVMEnable != true && v->DCCEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3663
min_row_time = v->meta_row_height[k] * LineTime / v->VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3665
min_row_time = dml_min(v->dpte_row_height[k] * LineTime / v->VRatio[k], v->meta_row_height[k] * LineTime / v->VRatio[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3669
if (v->DestinationLinesToRequestVMInImmediateFlip[k] >= 32 || v->DestinationLinesToRequestRowInImmediateFlip[k] >= 16
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3671
v->ImmediateFlipSupportedForPipe[k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3673
v->ImmediateFlipSupportedForPipe[k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3677
dml_print("DML::%s: DestinationLinesToRequestVMInImmediateFlip = %f\n", __func__, v->DestinationLinesToRequestVMInImmediateFlip[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3678
dml_print("DML::%s: DestinationLinesToRequestRowInImmediateFlip = %f\n", __func__, v->DestinationLinesToRequestRowInImmediateFlip[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3682
dml_print("DML::%s: ImmediateFlipSupportedForPipe = %d\n", __func__, v->ImmediateFlipSupportedForPipe[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3786
struct vba_vars_st *v = &mode_lib->vba;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3789
myPipe.DPPCLK = v->RequiredDPPCLK[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3790
myPipe.DISPCLK = v->RequiredDISPCLK[i][j];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3791
myPipe.PixelClock = v->PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3792
myPipe.DCFCLKDeepSleep = v->ProjectedDCFCLKDeepSleep[i][j];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3793
myPipe.DPPPerPlane = v->NoOfDPP[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3794
myPipe.ScalerEnabled = v->ScalerEnabled[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3798
myPipe.SourceScan = v->SourceScan[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3799
myPipe.BlockWidth256BytesY = v->Read256BlockWidthY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3800
myPipe.BlockHeight256BytesY = v->Read256BlockHeightY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3801
myPipe.BlockWidth256BytesC = v->Read256BlockWidthC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3802
myPipe.BlockHeight256BytesC = v->Read256BlockHeightC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3803
myPipe.InterlaceEnable = v->Interlace[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3804
myPipe.NumberOfCursors = v->NumberOfCursors[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3805
myPipe.VBlank = v->VTotal[k] - v->VActive[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3806
myPipe.HTotal = v->HTotal[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3807
myPipe.DCCEnable = v->DCCEnable[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3808
myPipe.ODMCombineIsEnabled = v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3809
|| v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3810
myPipe.SourcePixelFormat = v->SourcePixelFormat[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3811
myPipe.BytePerPixelY = v->BytePerPixelY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3812
myPipe.BytePerPixelC = v->BytePerPixelC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3813
myPipe.ProgressiveToInterlaceUnitInOPP = v->ProgressiveToInterlaceUnitInOPP;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3814
v->NoTimeForPrefetch[i][j][k] = CalculatePrefetchSchedule(
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3818
v->DSCDelayPerState[i][k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3819
v->DPPCLKDelaySubtotal + v->DPPCLKDelayCNVCFormater,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3820
v->DPPCLKDelaySCL,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3821
v->DPPCLKDelaySCLLBOnly,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3822
v->DPPCLKDelayCNVCCursor,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3823
v->DISPCLKDelaySubtotal,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3824
v->SwathWidthYThisState[k] / v->HRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3825
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3826
v->MaxInterDCNTileRepeaters,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3827
dml_min(v->MaxVStartup, v->MaximumVStartup[i][j][k]),
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3828
v->MaximumVStartup[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3829
v->GPUVMMaxPageTableLevels,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3830
v->GPUVMEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3831
v->HostVMEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3832
v->HostVMMaxNonCachedPageTableLevels,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3833
v->HostVMMinPageSize,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3834
v->DynamicMetadataEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3835
v->DynamicMetadataVMEnabled,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3836
v->DynamicMetadataLinesBeforeActiveRequired[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3837
v->DynamicMetadataTransmittedBytes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3838
v->UrgLatency[i],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3839
v->ExtraLatency,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3840
v->TimeCalc,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3841
v->PDEAndMetaPTEBytesPerFrame[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3842
v->MetaRowBytes[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3843
v->DPTEBytesPerRow[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3844
v->PrefetchLinesY[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3845
v->SwathWidthYThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3846
v->PrefillY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3847
v->MaxNumSwY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3848
v->PrefetchLinesC[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3849
v->SwathWidthCThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3850
v->PrefillC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3851
v->MaxNumSwC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3852
v->swath_width_luma_ub_this_state[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3853
v->swath_width_chroma_ub_this_state[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3854
v->SwathHeightYThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3855
v->SwathHeightCThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3856
v->TWait,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3857
&v->DSTXAfterScaler[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3858
&v->DSTYAfterScaler[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3859
&v->LineTimesForPrefetch[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3860
&v->PrefetchBW[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3861
&v->LinesForMetaPTE[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3862
&v->LinesForMetaAndDPTERow[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3863
&v->VRatioPreY[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3864
&v->VRatioPreC[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3865
&v->RequiredPrefetchPixelDataBWLuma[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3866
&v->RequiredPrefetchPixelDataBWChroma[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3867
&v->NoTimeForDynamicMetadata[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3868
&v->Tno_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3869
&v->prefetch_vmrow_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3870
&v->dummy7[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3871
&v->dummy8[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3872
&v->dummy13[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3873
&v->VUpdateOffsetPix[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3874
&v->VUpdateWidthPix[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3875
&v->VReadyOffsetPix[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3880
struct vba_vars_st *v = &mode_lib->vba;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3903
v->ScaleRatioAndTapsSupport = true;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3904
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3905
if (v->ScalerEnabled[k] == false
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3906
&& ((v->SourcePixelFormat[k] != dm_444_64 && v->SourcePixelFormat[k] != dm_444_32
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3907
&& v->SourcePixelFormat[k] != dm_444_16 && v->SourcePixelFormat[k] != dm_mono_16
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3908
&& v->SourcePixelFormat[k] != dm_mono_8 && v->SourcePixelFormat[k] != dm_rgbe
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3909
&& v->SourcePixelFormat[k] != dm_rgbe_alpha) || v->HRatio[k] != 1.0 || v->htaps[k] != 1.0
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3910
|| v->VRatio[k] != 1.0 || v->vtaps[k] != 1.0)) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3911
v->ScaleRatioAndTapsSupport = false;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3912
} else if (v->vtaps[k] < 1.0 || v->vtaps[k] > 8.0 || v->htaps[k] < 1.0 || v->htaps[k] > 8.0
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3913
|| (v->htaps[k] > 1.0 && (v->htaps[k] % 2) == 1) || v->HRatio[k] > v->MaxHSCLRatio
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3914
|| v->VRatio[k] > v->MaxVSCLRatio || v->HRatio[k] > v->htaps[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3915
|| v->VRatio[k] > v->vtaps[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3916
|| (v->SourcePixelFormat[k] != dm_444_64 && v->SourcePixelFormat[k] != dm_444_32
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3917
&& v->SourcePixelFormat[k] != dm_444_16 && v->SourcePixelFormat[k] != dm_mono_16
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3918
&& v->SourcePixelFormat[k] != dm_mono_8 && v->SourcePixelFormat[k] != dm_rgbe
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3919
&& (v->VTAPsChroma[k] < 1 || v->VTAPsChroma[k] > 8 || v->HTAPsChroma[k] < 1
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3920
|| v->HTAPsChroma[k] > 8 || (v->HTAPsChroma[k] > 1 && v->HTAPsChroma[k] % 2 == 1)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3921
|| v->HRatioChroma[k] > v->MaxHSCLRatio
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3922
|| v->VRatioChroma[k] > v->MaxVSCLRatio
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3923
|| v->HRatioChroma[k] > v->HTAPsChroma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3924
|| v->VRatioChroma[k] > v->VTAPsChroma[k]))) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3925
v->ScaleRatioAndTapsSupport = false;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3930
v->SourceFormatPixelAndScanSupport = true;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3931
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3932
if (v->SurfaceTiling[k] == dm_sw_linear && (!(v->SourceScan[k] != dm_vert) || v->DCCEnable[k] == true)) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3933
v->SourceFormatPixelAndScanSupport = false;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3938
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3940
v->SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3941
v->SurfaceTiling[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3942
&v->BytePerPixelY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3943
&v->BytePerPixelC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3944
&v->BytePerPixelInDETY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3945
&v->BytePerPixelInDETC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3946
&v->Read256BlockHeightY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3947
&v->Read256BlockHeightC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3948
&v->Read256BlockWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3949
&v->Read256BlockWidthC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3951
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3952
if (v->SourceScan[k] != dm_vert) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3953
v->SwathWidthYSingleDPP[k] = v->ViewportWidth[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3954
v->SwathWidthCSingleDPP[k] = v->ViewportWidthChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3956
v->SwathWidthYSingleDPP[k] = v->ViewportHeight[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3957
v->SwathWidthCSingleDPP[k] = v->ViewportHeightChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3960
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3961
v->ReadBandwidthLuma[k] = v->SwathWidthYSingleDPP[k] * dml_ceil(v->BytePerPixelInDETY[k], 1.0)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3962
/ (v->HTotal[k] / v->PixelClock[k]) * v->VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3963
v->ReadBandwidthChroma[k] = v->SwathWidthYSingleDPP[k] / 2 * dml_ceil(v->BytePerPixelInDETC[k], 2.0)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3964
/ (v->HTotal[k] / v->PixelClock[k]) * v->VRatio[k] / 2.0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3966
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3967
if (v->WritebackEnable[k] == true && v->WritebackPixelFormat[k] == dm_444_64) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3968
v->WriteBandwidth[k] = v->WritebackDestinationWidth[k] * v->WritebackDestinationHeight[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3969
/ (v->WritebackSourceHeight[k] * v->HTotal[k] / v->PixelClock[k]) * 8.0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3970
} else if (v->WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3971
v->WriteBandwidth[k] = v->WritebackDestinationWidth[k] * v->WritebackDestinationHeight[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3972
/ (v->WritebackSourceHeight[k] * v->HTotal[k] / v->PixelClock[k]) * 4.0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3974
v->WriteBandwidth[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3980
v->WritebackLatencySupport = true;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3981
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3982
if (v->WritebackEnable[k] == true && (v->WriteBandwidth[k] > v->WritebackInterfaceBufferSize * 1024 / v->WritebackLatency)) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3983
v->WritebackLatencySupport = false;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3989
v->TotalNumberOfActiveWriteback = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3990
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3991
if (v->WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3992
v->TotalNumberOfActiveWriteback = v->TotalNumberOfActiveWriteback + 1;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
3996
if (v->TotalNumberOfActiveWriteback > v->MaxNumWriteback) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4002
v->WritebackScaleRatioAndTapsSupport = true;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4003
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4004
if (v->WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4005
if (v->WritebackHRatio[k] > v->WritebackMaxHSCLRatio || v->WritebackVRatio[k] > v->WritebackMaxVSCLRatio
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4006
|| v->WritebackHRatio[k] < v->WritebackMinHSCLRatio
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4007
|| v->WritebackVRatio[k] < v->WritebackMinVSCLRatio
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4008
|| v->WritebackHTaps[k] > v->WritebackMaxHSCLTaps
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4009
|| v->WritebackVTaps[k] > v->WritebackMaxVSCLTaps
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4010
|| v->WritebackHRatio[k] > v->WritebackHTaps[k] || v->WritebackVRatio[k] > v->WritebackVTaps[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4011
|| (v->WritebackHTaps[k] > 2.0 && ((v->WritebackHTaps[k] % 2) == 1))) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4012
v->WritebackScaleRatioAndTapsSupport = false;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4014
if (2.0 * v->WritebackDestinationWidth[k] * (v->WritebackVTaps[k] - 1) * 57 > v->WritebackLineBufferSize) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4015
v->WritebackScaleRatioAndTapsSupport = false;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4021
v->WritebackRequiredDISPCLK = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4022
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4023
if (v->WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4024
v->WritebackRequiredDISPCLK = dml_max(
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4025
v->WritebackRequiredDISPCLK,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4027
v->WritebackPixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4028
v->PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4029
v->WritebackHRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4030
v->WritebackVRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4031
v->WritebackHTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4032
v->WritebackVTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4033
v->WritebackSourceWidth[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4034
v->WritebackDestinationWidth[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4035
v->HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4036
v->WritebackLineBufferSize));
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4039
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4040
if (v->HRatio[k] > 1.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4041
v->PSCL_FACTOR[k] = dml_min(
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4042
v->MaxDCHUBToPSCLThroughput,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4043
v->MaxPSCLToLBThroughput * v->HRatio[k] / dml_ceil(v->htaps[k] / 6.0, 1.0));
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4045
v->PSCL_FACTOR[k] = dml_min(v->MaxDCHUBToPSCLThroughput, v->MaxPSCLToLBThroughput);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4047
if (v->BytePerPixelC[k] == 0.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4048
v->PSCL_FACTOR_CHROMA[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4049
v->MinDPPCLKUsingSingleDPP[k] = v->PixelClock[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4051
v->vtaps[k] / 6.0 * dml_min(1.0, v->HRatio[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4052
v->HRatio[k] * v->VRatio[k] / v->PSCL_FACTOR[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4054
if ((v->htaps[k] > 6.0 || v->vtaps[k] > 6.0) && v->MinDPPCLKUsingSingleDPP[k] < 2.0 * v->PixelClock[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4055
v->MinDPPCLKUsingSingleDPP[k] = 2.0 * v->PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4058
if (v->HRatioChroma[k] > 1.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4059
v->PSCL_FACTOR_CHROMA[k] = dml_min(
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4060
v->MaxDCHUBToPSCLThroughput,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4061
v->MaxPSCLToLBThroughput * v->HRatioChroma[k] / dml_ceil(v->HTAPsChroma[k] / 6.0, 1.0));
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4063
v->PSCL_FACTOR_CHROMA[k] = dml_min(v->MaxDCHUBToPSCLThroughput, v->MaxPSCLToLBThroughput);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4065
v->MinDPPCLKUsingSingleDPP[k] = v->PixelClock[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4067
v->vtaps[k] / 6.0 * dml_min(1.0, v->HRatio[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4068
v->HRatio[k] * v->VRatio[k] / v->PSCL_FACTOR[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4069
v->VTAPsChroma[k] / 6.0 * dml_min(1.0, v->HRatioChroma[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4070
v->HRatioChroma[k] * v->VRatioChroma[k] / v->PSCL_FACTOR_CHROMA[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4072
if ((v->htaps[k] > 6.0 || v->vtaps[k] > 6.0 || v->HTAPsChroma[k] > 6.0 || v->VTAPsChroma[k] > 6.0)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4073
&& v->MinDPPCLKUsingSingleDPP[k] < 2.0 * v->PixelClock[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4074
v->MinDPPCLKUsingSingleDPP[k] = 2.0 * v->PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4078
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4082
if (v->SurfaceTiling[k] == dm_sw_linear) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4084
} else if (v->SourceScan[k] == dm_vert && v->BytePerPixelC[k] > 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4086
} else if (v->SourcePixelFormat[k] == dm_rgbe_alpha) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4092
if (v->SourcePixelFormat[k] == dm_420_8 || v->SourcePixelFormat[k] == dm_420_10 || v->SourcePixelFormat[k] == dm_420_12) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4097
v->MaximumSwathWidthInLineBufferLuma = v->LineBufferSize * dml_max(v->HRatio[k], 1.0) / v->LBBitPerPixel[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4098
/ (v->vtaps[k] + dml_max(dml_ceil(v->VRatio[k], 1.0) - 2, 0.0));
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4099
if (v->BytePerPixelC[k] == 0.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4100
v->MaximumSwathWidthInLineBufferChroma = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4102
v->MaximumSwathWidthInLineBufferChroma = v->LineBufferSize * dml_max(v->HRatioChroma[k], 1.0) / v->LBBitPerPixel[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4103
/ (v->VTAPsChroma[k] + dml_max(dml_ceil(v->VRatioChroma[k], 1.0) - 2, 0.0));
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4105
v->MaximumSwathWidthLuma[k] = dml_min(MaximumSwathWidthSupportLuma, v->MaximumSwathWidthInLineBufferLuma);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4106
v->MaximumSwathWidthChroma[k] = dml_min(MaximumSwathWidthSupportChroma, v->MaximumSwathWidthInLineBufferChroma);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4111
v->NumberOfActivePlanes,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4112
v->DETBufferSizeInKByte[0],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4113
v->MaximumSwathWidthLuma,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4114
v->MaximumSwathWidthChroma,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4115
v->SourceScan,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4116
v->SourcePixelFormat,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4117
v->SurfaceTiling,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4118
v->ViewportWidth,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4119
v->ViewportHeight,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4120
v->SurfaceWidthY,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4121
v->SurfaceWidthC,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4122
v->SurfaceHeightY,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4123
v->SurfaceHeightC,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4124
v->Read256BlockHeightY,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4125
v->Read256BlockHeightC,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4126
v->Read256BlockWidthY,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4127
v->Read256BlockWidthC,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4128
v->odm_combine_dummy,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4129
v->BlendingAndTiming,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4130
v->BytePerPixelY,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4131
v->BytePerPixelC,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4132
v->BytePerPixelInDETY,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4133
v->BytePerPixelInDETC,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4134
v->HActive,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4135
v->HRatio,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4136
v->HRatioChroma,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4137
v->NoOfDPPThisState,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4138
v->swath_width_luma_ub_this_state,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4139
v->swath_width_chroma_ub_this_state,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4140
v->SwathWidthYThisState,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4141
v->SwathWidthCThisState,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4142
v->SwathHeightYThisState,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4143
v->SwathHeightCThisState,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4144
v->DETBufferSizeYThisState,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4145
v->DETBufferSizeCThisState,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4146
v->SingleDPPViewportSizeSupportPerPlane,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4147
&v->ViewportSizeSupport[0][0]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4149
for (i = 0; i < v->soc.num_states; i++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4151
v->MaxDispclkRoundedDownToDFSGranularity = RoundToDFSGranularityDown(v->MaxDispclk[i], v->DISPCLKDPPCLKVCOSpeed);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4152
v->MaxDppclkRoundedDownToDFSGranularity = RoundToDFSGranularityDown(v->MaxDppclk[i], v->DISPCLKDPPCLKVCOSpeed);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4153
v->RequiredDISPCLK[i][j] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4154
v->DISPCLK_DPPCLK_Support[i][j] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4155
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4156
v->PlaneRequiredDISPCLKWithoutODMCombine = v->PixelClock[k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4157
* (1.0 + v->DISPCLKRampingMargin / 100.0);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4158
if ((v->PlaneRequiredDISPCLKWithoutODMCombine >= v->MaxDispclk[i]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4159
&& v->MaxDispclk[i] == v->MaxDispclk[v->soc.num_states - 1]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4160
&& v->MaxDppclk[i] == v->MaxDppclk[v->soc.num_states - 1])) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4161
v->PlaneRequiredDISPCLKWithoutODMCombine = v->PixelClock[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4162
* (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4164
v->PlaneRequiredDISPCLKWithODMCombine2To1 = v->PixelClock[k] / 2 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4165
* (1 + v->DISPCLKRampingMargin / 100.0);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4166
if ((v->PlaneRequiredDISPCLKWithODMCombine2To1 >= v->MaxDispclk[i]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4167
&& v->MaxDispclk[i] == v->MaxDispclk[v->soc.num_states - 1]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4168
&& v->MaxDppclk[i] == v->MaxDppclk[v->soc.num_states - 1])) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4169
v->PlaneRequiredDISPCLKWithODMCombine2To1 = v->PixelClock[k] / 2
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4170
* (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4172
v->PlaneRequiredDISPCLKWithODMCombine4To1 = v->PixelClock[k] / 4 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4173
* (1 + v->DISPCLKRampingMargin / 100.0);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4174
if ((v->PlaneRequiredDISPCLKWithODMCombine4To1 >= v->MaxDispclk[i]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4175
&& v->MaxDispclk[i] == v->MaxDispclk[v->soc.num_states - 1]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4176
&& v->MaxDppclk[i] == v->MaxDppclk[v->soc.num_states - 1])) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4177
v->PlaneRequiredDISPCLKWithODMCombine4To1 = v->PixelClock[k] / 4
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4178
* (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4181
if (v->ODMCombinePolicy == dm_odm_combine_policy_none
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4182
|| !(v->Output[k] == dm_dp ||
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4183
v->Output[k] == dm_dp2p0 ||
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4184
v->Output[k] == dm_edp)) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4185
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_disabled;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4186
v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithoutODMCombine;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4188
if (v->HActive[k] / 2 > DCN314_MAX_FMT_420_BUFFER_WIDTH)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4190
} else if (v->ODMCombinePolicy == dm_odm_combine_policy_2to1) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4191
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4192
v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithODMCombine2To1;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4193
} else if (v->ODMCombinePolicy == dm_odm_combine_policy_4to1
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4194
|| v->PlaneRequiredDISPCLKWithODMCombine2To1 > v->MaxDispclkRoundedDownToDFSGranularity) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4195
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_4to1;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4196
v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithODMCombine4To1;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4197
} else if (v->PlaneRequiredDISPCLKWithoutODMCombine > v->MaxDispclkRoundedDownToDFSGranularity) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4198
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4199
v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithODMCombine2To1;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4201
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_disabled;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4202
v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithoutODMCombine;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4204
if (v->DSCEnabled[k] && v->HActive[k] > DCN314_MAX_DSC_IMAGE_WIDTH
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4205
&& v->ODMCombineEnablePerState[i][k] != dm_odm_combine_mode_4to1) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4206
if (v->HActive[k] / 2 > DCN314_MAX_DSC_IMAGE_WIDTH) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4207
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_4to1;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4208
v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithODMCombine4To1;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4210
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4211
v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithODMCombine2To1;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4214
if (v->OutputFormat[k] == dm_420 && v->HActive[k] > DCN314_MAX_FMT_420_BUFFER_WIDTH
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4215
&& v->ODMCombineEnablePerState[i][k] != dm_odm_combine_mode_4to1) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4216
if (v->Output[k] == dm_hdmi) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4218
} else if (v->HActive[k] / 2 > DCN314_MAX_FMT_420_BUFFER_WIDTH) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4219
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_4to1;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4220
v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithODMCombine4To1;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4222
if (v->HActive[k] / 4 > DCN314_MAX_FMT_420_BUFFER_WIDTH)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4225
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4226
v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithODMCombine2To1;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4229
if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4230
v->MPCCombine[i][j][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4231
v->NoOfDPP[i][j][k] = 4;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4232
v->RequiredDPPCLK[i][j][k] = v->MinDPPCLKUsingSingleDPP[k] * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) / 4;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4233
} else if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4234
v->MPCCombine[i][j][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4235
v->NoOfDPP[i][j][k] = 2;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4236
v->RequiredDPPCLK[i][j][k] = v->MinDPPCLKUsingSingleDPP[k] * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) / 2;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4237
} else if ((v->WhenToDoMPCCombine == dm_mpc_never
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4238
|| (v->MinDPPCLKUsingSingleDPP[k] * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4239
<= v->MaxDppclkRoundedDownToDFSGranularity && v->SingleDPPViewportSizeSupportPerPlane[k] == true))) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4240
v->MPCCombine[i][j][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4241
v->NoOfDPP[i][j][k] = 1;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4242
v->RequiredDPPCLK[i][j][k] = v->MinDPPCLKUsingSingleDPP[k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4244
v->MPCCombine[i][j][k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4245
v->NoOfDPP[i][j][k] = 2;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4246
v->RequiredDPPCLK[i][j][k] = v->MinDPPCLKUsingSingleDPP[k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) / 2.0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4248
v->RequiredDISPCLK[i][j] = dml_max(v->RequiredDISPCLK[i][j], v->PlaneRequiredDISPCLK);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4249
if ((v->MinDPPCLKUsingSingleDPP[k] / v->NoOfDPP[i][j][k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4250
> v->MaxDppclkRoundedDownToDFSGranularity)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4251
|| (v->PlaneRequiredDISPCLK > v->MaxDispclkRoundedDownToDFSGranularity)) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4252
v->DISPCLK_DPPCLK_Support[i][j] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4255
v->TotalNumberOfActiveDPP[i][j] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4256
v->TotalNumberOfSingleDPPPlanes[i][j] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4257
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4258
v->TotalNumberOfActiveDPP[i][j] = v->TotalNumberOfActiveDPP[i][j] + v->NoOfDPP[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4259
if (v->NoOfDPP[i][j][k] == 1)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4260
v->TotalNumberOfSingleDPPPlanes[i][j] = v->TotalNumberOfSingleDPPPlanes[i][j] + 1;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4261
if (v->SourcePixelFormat[k] == dm_420_8 || v->SourcePixelFormat[k] == dm_420_10
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4262
|| v->SourcePixelFormat[k] == dm_420_12 || v->SourcePixelFormat[k] == dm_rgbe_alpha)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4267
if (j == 1 && v->WhenToDoMPCCombine != dm_mpc_never
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4268
&& !UnboundedRequest(v->UseUnboundedRequesting, v->TotalNumberOfActiveDPP[i][j], NoChroma, v->Output[0])) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4269
while (!(v->TotalNumberOfActiveDPP[i][j] >= v->MaxNumDPP || v->TotalNumberOfSingleDPPPlanes[i][j] == 0)) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4275
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4276
if (v->ReadBandwidthLuma[k] + v->ReadBandwidthChroma[k] > BWOfNonSplitPlaneOfMaximumBandwidth
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4277
&& v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_disabled && v->MPCCombine[i][j][k] == false) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4278
BWOfNonSplitPlaneOfMaximumBandwidth = v->ReadBandwidthLuma[k] + v->ReadBandwidthChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4282
v->MPCCombine[i][j][NumberOfNonSplitPlaneOfMaximumBandwidth] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4283
v->NoOfDPP[i][j][NumberOfNonSplitPlaneOfMaximumBandwidth] = 2;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4284
v->RequiredDPPCLK[i][j][NumberOfNonSplitPlaneOfMaximumBandwidth] =
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4285
v->MinDPPCLKUsingSingleDPP[NumberOfNonSplitPlaneOfMaximumBandwidth]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4286
* (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100) / 2;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4287
v->TotalNumberOfActiveDPP[i][j] = v->TotalNumberOfActiveDPP[i][j] + 1;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4288
v->TotalNumberOfSingleDPPPlanes[i][j] = v->TotalNumberOfSingleDPPPlanes[i][j] - 1;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4291
if (v->TotalNumberOfActiveDPP[i][j] > v->MaxNumDPP) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4292
v->RequiredDISPCLK[i][j] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4293
v->DISPCLK_DPPCLK_Support[i][j] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4294
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4295
v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_disabled;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4296
if (v->SingleDPPViewportSizeSupportPerPlane[k] == false && v->WhenToDoMPCCombine != dm_mpc_never) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4297
v->MPCCombine[i][j][k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4298
v->NoOfDPP[i][j][k] = 2;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4299
v->RequiredDPPCLK[i][j][k] = v->MinDPPCLKUsingSingleDPP[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4300
* (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) / 2.0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4302
v->MPCCombine[i][j][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4303
v->NoOfDPP[i][j][k] = 1;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4304
v->RequiredDPPCLK[i][j][k] = v->MinDPPCLKUsingSingleDPP[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4305
* (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4307
if (!(v->MaxDispclk[i] == v->MaxDispclk[v->soc.num_states - 1]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4308
&& v->MaxDppclk[i] == v->MaxDppclk[v->soc.num_states - 1])) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4309
v->PlaneRequiredDISPCLK = v->PixelClock[k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4310
* (1.0 + v->DISPCLKRampingMargin / 100.0);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4312
v->PlaneRequiredDISPCLK = v->PixelClock[k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4314
v->RequiredDISPCLK[i][j] = dml_max(v->RequiredDISPCLK[i][j], v->PlaneRequiredDISPCLK);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4315
if ((v->MinDPPCLKUsingSingleDPP[k] / v->NoOfDPP[i][j][k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4316
> v->MaxDppclkRoundedDownToDFSGranularity)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4317
|| (v->PlaneRequiredDISPCLK > v->MaxDispclkRoundedDownToDFSGranularity)) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4318
v->DISPCLK_DPPCLK_Support[i][j] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4321
v->TotalNumberOfActiveDPP[i][j] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4322
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4323
v->TotalNumberOfActiveDPP[i][j] = v->TotalNumberOfActiveDPP[i][j] + v->NoOfDPP[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4326
v->RequiredDISPCLK[i][j] = dml_max(v->RequiredDISPCLK[i][j], v->WritebackRequiredDISPCLK);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4327
if (v->MaxDispclkRoundedDownToDFSGranularity < v->WritebackRequiredDISPCLK) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4328
v->DISPCLK_DPPCLK_Support[i][j] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4335
for (i = 0; i < v->soc.num_states; i++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4337
if (v->TotalNumberOfActiveDPP[i][j] <= v->MaxNumDPP) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4338
v->TotalAvailablePipesSupport[i][j] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4340
v->TotalAvailablePipesSupport[i][j] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4346
v->NonsupportedDSCInputBPC = false;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4347
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4348
if (!(v->DSCInputBitPerComponent[k] == 12.0 || v->DSCInputBitPerComponent[k] == 10.0 || v->DSCInputBitPerComponent[k] == 8.0)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4349
|| v->DSCInputBitPerComponent[k] > v->MaximumDSCBitsPerComponent) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4350
v->NonsupportedDSCInputBPC = true;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4355
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4356
if (v->BlendingAndTiming[k] == k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4357
if (v->PixelClockBackEnd[k] > 3200) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4358
v->NumberOfDSCSlices[k] = dml_ceil(v->PixelClockBackEnd[k] / 400.0, 4.0);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4359
} else if (v->PixelClockBackEnd[k] > 1360) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4360
v->NumberOfDSCSlices[k] = 8;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4361
} else if (v->PixelClockBackEnd[k] > 680) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4362
v->NumberOfDSCSlices[k] = 4;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4363
} else if (v->PixelClockBackEnd[k] > 340) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4364
v->NumberOfDSCSlices[k] = 2;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4366
v->NumberOfDSCSlices[k] = 1;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4369
v->NumberOfDSCSlices[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4373
for (i = 0; i < v->soc.num_states; i++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4374
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4375
v->RequiresDSC[i][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4376
v->RequiresFEC[i][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4377
if (v->BlendingAndTiming[k] == k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4378
if (v->Output[k] == dm_hdmi) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4379
v->RequiresDSC[i][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4380
v->RequiresFEC[i][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4381
v->OutputBppPerState[i][k] = TruncToValidBPP(
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4382
dml_min(600.0, v->PHYCLKPerState[i]) * 10,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4384
v->HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4385
v->HActive[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4386
v->PixelClockBackEnd[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4387
v->ForcedOutputLinkBPP[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4389
v->Output[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4390
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4391
v->DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4392
v->NumberOfDSCSlices[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4393
v->AudioSampleRate[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4394
v->AudioSampleLayout[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4395
v->ODMCombineEnablePerState[i][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4396
} else if (v->Output[k] == dm_dp || v->Output[k] == dm_edp || v->Output[k] == dm_dp2p0) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4397
if (v->DSCEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4398
v->RequiresDSC[i][k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4399
v->LinkDSCEnable = true;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4400
if (v->Output[k] == dm_dp || v->Output[k] == dm_dp2p0) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4401
v->RequiresFEC[i][k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4403
v->RequiresFEC[i][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4406
v->RequiresDSC[i][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4407
v->LinkDSCEnable = false;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4408
if (v->Output[k] == dm_dp2p0) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4409
v->RequiresFEC[i][k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4411
v->RequiresFEC[i][k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4414
if (v->Output[k] == dm_dp2p0) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4415
v->Outbpp = BPP_INVALID;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4416
if ((v->OutputLinkDPRate[k] == dm_dp_rate_na || v->OutputLinkDPRate[k] == dm_dp_rate_uhbr10) &&
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4417
v->PHYCLKD18PerState[k] >= 10000.0 / 18.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4418
v->Outbpp = TruncToValidBPP(
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4419
(1.0 - v->Downspreading / 100.0) * 10000,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4420
v->OutputLinkDPLanes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4421
v->HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4422
v->HActive[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4423
v->PixelClockBackEnd[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4424
v->ForcedOutputLinkBPP[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4425
v->LinkDSCEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4426
v->Output[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4427
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4428
v->DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4429
v->NumberOfDSCSlices[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4430
v->AudioSampleRate[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4431
v->AudioSampleLayout[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4432
v->ODMCombineEnablePerState[i][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4433
if (v->Outbpp == BPP_INVALID && v->PHYCLKD18PerState[k] < 13500.0 / 18.0 &&
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4434
v->DSCEnable[k] == true && v->ForcedOutputLinkBPP[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4435
v->RequiresDSC[i][k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4436
v->LinkDSCEnable = true;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4437
v->Outbpp = TruncToValidBPP(
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4438
(1.0 - v->Downspreading / 100.0) * 10000,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4439
v->OutputLinkDPLanes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4440
v->HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4441
v->HActive[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4442
v->PixelClockBackEnd[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4443
v->ForcedOutputLinkBPP[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4444
v->LinkDSCEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4445
v->Output[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4446
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4447
v->DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4448
v->NumberOfDSCSlices[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4449
v->AudioSampleRate[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4450
v->AudioSampleLayout[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4451
v->ODMCombineEnablePerState[i][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4453
v->OutputBppPerState[i][k] = v->Outbpp;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4457
if (v->Outbpp == BPP_INVALID &&
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4458
(v->OutputLinkDPRate[k] == dm_dp_rate_na || v->OutputLinkDPRate[k] == dm_dp_rate_uhbr13p5) &&
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4459
v->PHYCLKD18PerState[k] >= 13500.0 / 18.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4460
v->Outbpp = TruncToValidBPP(
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4461
(1.0 - v->Downspreading / 100.0) * 13500,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4462
v->OutputLinkDPLanes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4463
v->HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4464
v->HActive[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4465
v->PixelClockBackEnd[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4466
v->ForcedOutputLinkBPP[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4467
v->LinkDSCEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4468
v->Output[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4469
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4470
v->DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4471
v->NumberOfDSCSlices[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4472
v->AudioSampleRate[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4473
v->AudioSampleLayout[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4474
v->ODMCombineEnablePerState[i][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4475
if (v->Outbpp == BPP_INVALID && v->PHYCLKD18PerState[k] < 20000.0 / 18.0 &&
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4476
v->DSCEnable[k] == true && v->ForcedOutputLinkBPP[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4477
v->RequiresDSC[i][k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4478
v->LinkDSCEnable = true;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4479
v->Outbpp = TruncToValidBPP(
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4480
(1.0 - v->Downspreading / 100.0) * 13500,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4481
v->OutputLinkDPLanes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4482
v->HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4483
v->HActive[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4484
v->PixelClockBackEnd[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4485
v->ForcedOutputLinkBPP[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4486
v->LinkDSCEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4487
v->Output[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4488
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4489
v->DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4490
v->NumberOfDSCSlices[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4491
v->AudioSampleRate[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4492
v->AudioSampleLayout[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4493
v->ODMCombineEnablePerState[i][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4495
v->OutputBppPerState[i][k] = v->Outbpp;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4499
if (v->Outbpp == BPP_INVALID &&
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4500
(v->OutputLinkDPRate[k] == dm_dp_rate_na || v->OutputLinkDPRate[k] == dm_dp_rate_uhbr20) &&
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4501
v->PHYCLKD18PerState[k] >= 20000.0 / 18.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4502
v->Outbpp = TruncToValidBPP(
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4503
(1.0 - v->Downspreading / 100.0) * 20000,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4504
v->OutputLinkDPLanes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4505
v->HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4506
v->HActive[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4507
v->PixelClockBackEnd[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4508
v->ForcedOutputLinkBPP[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4509
v->LinkDSCEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4510
v->Output[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4511
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4512
v->DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4513
v->NumberOfDSCSlices[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4514
v->AudioSampleRate[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4515
v->AudioSampleLayout[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4516
v->ODMCombineEnablePerState[i][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4517
if (v->Outbpp == BPP_INVALID && v->DSCEnable[k] == true &&
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4518
v->ForcedOutputLinkBPP[k] == 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4519
v->RequiresDSC[i][k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4520
v->LinkDSCEnable = true;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4521
v->Outbpp = TruncToValidBPP(
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4522
(1.0 - v->Downspreading / 100.0) * 20000,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4523
v->OutputLinkDPLanes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4524
v->HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4525
v->HActive[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4526
v->PixelClockBackEnd[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4527
v->ForcedOutputLinkBPP[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4528
v->LinkDSCEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4529
v->Output[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4530
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4531
v->DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4532
v->NumberOfDSCSlices[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4533
v->AudioSampleRate[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4534
v->AudioSampleLayout[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4535
v->ODMCombineEnablePerState[i][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4537
v->OutputBppPerState[i][k] = v->Outbpp;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4542
v->Outbpp = BPP_INVALID;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4543
if (v->PHYCLKPerState[i] >= 270.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4544
v->Outbpp = TruncToValidBPP(
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4545
(1.0 - v->Downspreading / 100.0) * 2700,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4546
v->OutputLinkDPLanes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4547
v->HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4548
v->HActive[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4549
v->PixelClockBackEnd[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4550
v->ForcedOutputLinkBPP[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4551
v->LinkDSCEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4552
v->Output[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4553
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4554
v->DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4555
v->NumberOfDSCSlices[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4556
v->AudioSampleRate[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4557
v->AudioSampleLayout[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4558
v->ODMCombineEnablePerState[i][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4559
v->OutputBppPerState[i][k] = v->Outbpp;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4563
if (v->Outbpp == BPP_INVALID && v->PHYCLKPerState[i] >= 540.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4564
v->Outbpp = TruncToValidBPP(
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4565
(1.0 - v->Downspreading / 100.0) * 5400,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4566
v->OutputLinkDPLanes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4567
v->HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4568
v->HActive[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4569
v->PixelClockBackEnd[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4570
v->ForcedOutputLinkBPP[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4571
v->LinkDSCEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4572
v->Output[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4573
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4574
v->DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4575
v->NumberOfDSCSlices[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4576
v->AudioSampleRate[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4577
v->AudioSampleLayout[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4578
v->ODMCombineEnablePerState[i][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4579
v->OutputBppPerState[i][k] = v->Outbpp;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4583
if (v->Outbpp == BPP_INVALID && v->PHYCLKPerState[i] >= 810.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4584
v->Outbpp = TruncToValidBPP(
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4585
(1.0 - v->Downspreading / 100.0) * 8100,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4586
v->OutputLinkDPLanes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4587
v->HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4588
v->HActive[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4589
v->PixelClockBackEnd[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4590
v->ForcedOutputLinkBPP[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4591
v->LinkDSCEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4592
v->Output[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4593
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4594
v->DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4595
v->NumberOfDSCSlices[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4596
v->AudioSampleRate[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4597
v->AudioSampleLayout[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4598
v->ODMCombineEnablePerState[i][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4599
v->OutputBppPerState[i][k] = v->Outbpp;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4606
v->OutputBppPerState[i][k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4611
for (i = 0; i < v->soc.num_states; i++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4612
v->LinkCapacitySupport[i] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4613
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4614
if (v->BlendingAndTiming[k] == k
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4615
&& (v->Output[k] == dm_dp ||
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4616
v->Output[k] == dm_edp ||
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4617
v->Output[k] == dm_hdmi) && v->OutputBppPerState[i][k] == 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4618
v->LinkCapacitySupport[i] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4624
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4625
if (v->BlendingAndTiming[k] == k
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4626
&& (v->Output[k] == dm_dp ||
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4627
v->Output[k] == dm_edp ||
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4628
v->Output[k] == dm_hdmi)) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4629
if (v->OutputFormat[k] == dm_420 && v->Interlace[k] == 1 && v->ProgressiveToInterlaceUnitInOPP == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4632
if (v->DSCEnable[k] == true && v->OutputFormat[k] == dm_n422
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4633
&& !v->DSC422NativeSupport) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4640
for (i = 0; i < v->soc.num_states; ++i) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4641
v->ODMCombine4To1SupportCheckOK[i] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4642
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4643
if (v->BlendingAndTiming[k] == k && v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4644
&& (v->ODMCombine4To1Supported == false || v->Output[k] == dm_dp || v->Output[k] == dm_edp
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4645
|| v->Output[k] == dm_hdmi)) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4646
v->ODMCombine4To1SupportCheckOK[i] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4653
for (i = 0; i < v->soc.num_states; i++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4654
v->NotEnoughDSCUnits[i] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4655
v->TotalDSCUnitsRequired = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4656
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4657
if (v->RequiresDSC[i][k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4658
if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4659
v->TotalDSCUnitsRequired = v->TotalDSCUnitsRequired + 4.0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4660
} else if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4661
v->TotalDSCUnitsRequired = v->TotalDSCUnitsRequired + 2.0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4663
v->TotalDSCUnitsRequired = v->TotalDSCUnitsRequired + 1.0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4667
if (v->TotalDSCUnitsRequired > v->NumberOfDSC) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4668
v->NotEnoughDSCUnits[i] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4673
for (i = 0; i < v->soc.num_states; i++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4674
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4675
if (v->OutputBppPerState[i][k] == BPP_INVALID) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4676
v->BPP = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4678
v->BPP = v->OutputBppPerState[i][k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4680
if (v->RequiresDSC[i][k] == true && v->BPP != 0.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4681
if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_disabled) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4682
v->DSCDelayPerState[i][k] = dscceComputeDelay(
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4683
v->DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4684
v->BPP,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4685
dml_ceil(1.0 * v->HActive[k] / v->NumberOfDSCSlices[k], 1.0),
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4686
v->NumberOfDSCSlices[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4687
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4688
v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4689
} else if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4690
v->DSCDelayPerState[i][k] = 2.0
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4692
v->DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4693
v->BPP,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4694
dml_ceil(1.0 * v->HActive[k] / v->NumberOfDSCSlices[k], 1.0),
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4695
v->NumberOfDSCSlices[k] / 2,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4696
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4697
v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k]));
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4699
v->DSCDelayPerState[i][k] = 4.0
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4701
v->DSCInputBitPerComponent[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4702
v->BPP,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4703
dml_ceil(1.0 * v->HActive[k] / v->NumberOfDSCSlices[k], 1.0),
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4704
v->NumberOfDSCSlices[k] / 4,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4705
v->OutputFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4706
v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k]));
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4708
v->DSCDelayPerState[i][k] = v->DSCDelayPerState[i][k] + (v->HTotal[k] - v->HActive[k]) * dml_ceil((double) v->DSCDelayPerState[i][k] / v->HActive[k], 1.0);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4709
v->DSCDelayPerState[i][k] = v->DSCDelayPerState[i][k] * v->PixelClock[k] / v->PixelClockBackEnd[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4711
v->DSCDelayPerState[i][k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4714
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4715
for (m = 0; m < v->NumberOfActivePlanes; m++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4716
if (v->BlendingAndTiming[k] == m && v->RequiresDSC[i][m] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4717
v->DSCDelayPerState[i][k] = v->DSCDelayPerState[i][m];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4725
for (i = 0; i < v->soc.num_states; ++i) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4727
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4728
v->RequiredDPPCLKThisState[k] = v->RequiredDPPCLK[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4729
v->NoOfDPPThisState[k] = v->NoOfDPP[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4730
v->ODMCombineEnableThisState[k] = v->ODMCombineEnablePerState[i][k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4735
v->NumberOfActivePlanes,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4736
v->DETBufferSizeInKByte[0],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4737
v->MaximumSwathWidthLuma,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4738
v->MaximumSwathWidthChroma,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4739
v->SourceScan,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4740
v->SourcePixelFormat,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4741
v->SurfaceTiling,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4742
v->ViewportWidth,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4743
v->ViewportHeight,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4744
v->SurfaceWidthY,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4745
v->SurfaceWidthC,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4746
v->SurfaceHeightY,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4747
v->SurfaceHeightC,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4748
v->Read256BlockHeightY,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4749
v->Read256BlockHeightC,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4750
v->Read256BlockWidthY,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4751
v->Read256BlockWidthC,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4752
v->ODMCombineEnableThisState,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4753
v->BlendingAndTiming,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4754
v->BytePerPixelY,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4755
v->BytePerPixelC,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4756
v->BytePerPixelInDETY,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4757
v->BytePerPixelInDETC,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4758
v->HActive,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4759
v->HRatio,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4760
v->HRatioChroma,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4761
v->NoOfDPPThisState,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4762
v->swath_width_luma_ub_this_state,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4763
v->swath_width_chroma_ub_this_state,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4764
v->SwathWidthYThisState,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4765
v->SwathWidthCThisState,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4766
v->SwathHeightYThisState,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4767
v->SwathHeightCThisState,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4768
v->DETBufferSizeYThisState,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4769
v->DETBufferSizeCThisState,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4770
v->dummystring,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4771
&v->ViewportSizeSupport[i][j]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4775
v->NumberOfActivePlanes,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4776
v->BytePerPixelY,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4777
v->BytePerPixelC,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4778
v->VRatio,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4779
v->VRatioChroma,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4780
v->SwathWidthYThisState,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4781
v->SwathWidthCThisState,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4782
v->NoOfDPPThisState,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4783
v->HRatio,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4784
v->HRatioChroma,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4785
v->PixelClock,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4786
v->PSCL_FACTOR,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4787
v->PSCL_FACTOR_CHROMA,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4788
v->RequiredDPPCLKThisState,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4789
v->ReadBandwidthLuma,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4790
v->ReadBandwidthChroma,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4791
v->ReturnBusWidth,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4792
&v->ProjectedDCFCLKDeepSleep[i][j]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4794
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4795
v->swath_width_luma_ub_all_states[i][j][k] = v->swath_width_luma_ub_this_state[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4796
v->swath_width_chroma_ub_all_states[i][j][k] = v->swath_width_chroma_ub_this_state[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4797
v->SwathWidthYAllStates[i][j][k] = v->SwathWidthYThisState[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4798
v->SwathWidthCAllStates[i][j][k] = v->SwathWidthCThisState[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4799
v->SwathHeightYAllStates[i][j][k] = v->SwathHeightYThisState[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4800
v->SwathHeightCAllStates[i][j][k] = v->SwathHeightCThisState[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4801
v->DETBufferSizeYAllStates[i][j][k] = v->DETBufferSizeYThisState[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4802
v->DETBufferSizeCAllStates[i][j][k] = v->DETBufferSizeCThisState[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4807
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4808
v->cursor_bw[k] = v->NumberOfCursors[k] * v->CursorWidth[k][0] * v->CursorBPP[k][0] / 8.0
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4809
/ (v->HTotal[k] / v->PixelClock[k]) * v->VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4812
for (i = 0; i < v->soc.num_states; i++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4816
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4817
v->swath_width_luma_ub_this_state[k] = v->swath_width_luma_ub_all_states[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4818
v->swath_width_chroma_ub_this_state[k] = v->swath_width_chroma_ub_all_states[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4819
v->SwathWidthYThisState[k] = v->SwathWidthYAllStates[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4820
v->SwathWidthCThisState[k] = v->SwathWidthCAllStates[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4821
v->SwathHeightYThisState[k] = v->SwathHeightYAllStates[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4822
v->SwathHeightCThisState[k] = v->SwathHeightCAllStates[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4823
v->DETBufferSizeYThisState[k] = v->DETBufferSizeYAllStates[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4824
v->DETBufferSizeCThisState[k] = v->DETBufferSizeCAllStates[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4827
v->TotalNumberOfDCCActiveDPP[i][j] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4828
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4829
if (v->DCCEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4830
v->TotalNumberOfDCCActiveDPP[i][j] = v->TotalNumberOfDCCActiveDPP[i][j] + v->NoOfDPP[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4834
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4835
if (v->SourcePixelFormat[k] == dm_420_8 || v->SourcePixelFormat[k] == dm_420_10
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4836
|| v->SourcePixelFormat[k] == dm_420_12 || v->SourcePixelFormat[k] == dm_rgbe_alpha) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4838
if ((v->SourcePixelFormat[k] == dm_420_10 || v->SourcePixelFormat[k] == dm_420_12)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4839
&& v->SourceScan[k] != dm_vert) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4840
v->PTEBufferSizeInRequestsForLuma = (v->PTEBufferSizeInRequestsLuma + v->PTEBufferSizeInRequestsChroma)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4842
v->PTEBufferSizeInRequestsForChroma = v->PTEBufferSizeInRequestsForLuma;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4844
v->PTEBufferSizeInRequestsForLuma = v->PTEBufferSizeInRequestsLuma;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4845
v->PTEBufferSizeInRequestsForChroma = v->PTEBufferSizeInRequestsChroma;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4848
v->PDEAndMetaPTEBytesPerFrameC = CalculateVMAndRowBytes(
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4850
v->DCCEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4851
v->Read256BlockHeightC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4852
v->Read256BlockWidthC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4853
v->SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4854
v->SurfaceTiling[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4855
v->BytePerPixelC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4856
v->SourceScan[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4857
v->SwathWidthCThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4858
v->ViewportHeightChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4859
v->GPUVMEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4860
v->HostVMEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4861
v->HostVMMaxNonCachedPageTableLevels,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4862
v->GPUVMMinPageSize,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4863
v->HostVMMinPageSize,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4864
v->PTEBufferSizeInRequestsForChroma,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4865
v->PitchC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4867
&v->MacroTileWidthC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4868
&v->MetaRowBytesC,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4869
&v->DPTEBytesPerRowC,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4870
&v->PTEBufferSizeNotExceededC[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4871
&v->dummyinteger7,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4872
&v->dpte_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4873
&v->dummyinteger28,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4874
&v->dummyinteger26,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4875
&v->dummyinteger23,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4876
&v->meta_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4877
&v->dummyinteger8,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4878
&v->dummyinteger9,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4879
&v->dummyinteger19,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4880
&v->dummyinteger20,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4881
&v->dummyinteger17,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4882
&v->dummyinteger10,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4883
&v->dummyinteger11);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4885
v->PrefetchLinesC[i][j][k] = CalculatePrefetchSourceLines(
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4887
v->VRatioChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4888
v->VTAPsChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4889
v->Interlace[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4890
v->ProgressiveToInterlaceUnitInOPP,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4891
v->SwathHeightCThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4892
v->ViewportYStartC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4893
&v->PrefillC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4894
&v->MaxNumSwC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4896
v->PTEBufferSizeInRequestsForLuma = v->PTEBufferSizeInRequestsLuma + v->PTEBufferSizeInRequestsChroma;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4897
v->PTEBufferSizeInRequestsForChroma = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4898
v->PDEAndMetaPTEBytesPerFrameC = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4899
v->MetaRowBytesC = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4900
v->DPTEBytesPerRowC = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4901
v->PrefetchLinesC[i][j][k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4902
v->PTEBufferSizeNotExceededC[i][j][k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4904
v->PDEAndMetaPTEBytesPerFrameY = CalculateVMAndRowBytes(
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4906
v->DCCEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4907
v->Read256BlockHeightY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4908
v->Read256BlockWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4909
v->SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4910
v->SurfaceTiling[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4911
v->BytePerPixelY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4912
v->SourceScan[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4913
v->SwathWidthYThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4914
v->ViewportHeight[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4915
v->GPUVMEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4916
v->HostVMEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4917
v->HostVMMaxNonCachedPageTableLevels,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4918
v->GPUVMMinPageSize,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4919
v->HostVMMinPageSize,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4920
v->PTEBufferSizeInRequestsForLuma,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4921
v->PitchY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4922
v->DCCMetaPitchY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4923
&v->MacroTileWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4924
&v->MetaRowBytesY,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4925
&v->DPTEBytesPerRowY,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4926
&v->PTEBufferSizeNotExceededY[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4927
&v->dummyinteger7,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4928
&v->dpte_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4929
&v->dummyinteger29,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4930
&v->dummyinteger27,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4931
&v->dummyinteger24,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4932
&v->meta_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4933
&v->dummyinteger25,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4934
&v->dpte_group_bytes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4935
&v->dummyinteger21,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4936
&v->dummyinteger22,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4937
&v->dummyinteger18,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4938
&v->dummyinteger5,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4939
&v->dummyinteger6);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4940
v->PrefetchLinesY[i][j][k] = CalculatePrefetchSourceLines(
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4942
v->VRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4943
v->vtaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4944
v->Interlace[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4945
v->ProgressiveToInterlaceUnitInOPP,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4946
v->SwathHeightYThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4947
v->ViewportYStartY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4948
&v->PrefillY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4949
&v->MaxNumSwY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4950
v->PDEAndMetaPTEBytesPerFrame[i][j][k] = v->PDEAndMetaPTEBytesPerFrameY + v->PDEAndMetaPTEBytesPerFrameC;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4951
v->MetaRowBytes[i][j][k] = v->MetaRowBytesY + v->MetaRowBytesC;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4952
v->DPTEBytesPerRow[i][j][k] = v->DPTEBytesPerRowY + v->DPTEBytesPerRowC;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4955
v->GPUVMEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4956
v->SourcePixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4957
v->VRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4958
v->VRatioChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4959
v->DCCEnable[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4960
v->HTotal[k] / v->PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4961
v->MetaRowBytesY,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4962
v->MetaRowBytesC,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4963
v->meta_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4964
v->meta_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4965
v->DPTEBytesPerRowY,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4966
v->DPTEBytesPerRowC,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4967
v->dpte_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4968
v->dpte_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4969
&v->meta_row_bandwidth[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4970
&v->dpte_row_bandwidth[i][j][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4980
v->DCCMetaBufferSizeSupport[i][j] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4981
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4982
if (v->MetaRowBytes[i][j][k] > 24064)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4983
v->DCCMetaBufferSizeSupport[i][j] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4985
v->UrgLatency[i] = CalculateUrgentLatency(
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4986
v->UrgentLatencyPixelDataOnly,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4987
v->UrgentLatencyPixelMixedWithVMData,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4988
v->UrgentLatencyVMDataOnly,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4989
v->DoUrgentLatencyAdjustment,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4990
v->UrgentLatencyAdjustmentFabricClockComponent,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4991
v->UrgentLatencyAdjustmentFabricClockReference,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4992
v->FabricClockPerState[i]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4994
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4996
v->swath_width_luma_ub_this_state[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4997
v->swath_width_chroma_ub_this_state[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4998
v->SwathHeightYThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
4999
v->SwathHeightCThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5000
v->HTotal[k] / v->PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5001
v->UrgLatency[i],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5002
v->CursorBufferSize,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5003
v->CursorWidth[k][0],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5004
v->CursorBPP[k][0],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5005
v->VRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5006
v->VRatioChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5007
v->BytePerPixelInDETY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5008
v->BytePerPixelInDETC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5009
v->DETBufferSizeYThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5010
v->DETBufferSizeCThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5011
&v->UrgentBurstFactorCursor[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5012
&v->UrgentBurstFactorLuma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5013
&v->UrgentBurstFactorChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5017
v->NotEnoughUrgentLatencyHidingA[i][j] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5018
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5020
v->NotEnoughUrgentLatencyHidingA[i][j] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5024
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5025
v->VActivePixelBandwidth[i][j][k] = v->ReadBandwidthLuma[k] * v->UrgentBurstFactorLuma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5026
+ v->ReadBandwidthChroma[k] * v->UrgentBurstFactorChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5027
v->VActiveCursorBandwidth[i][j][k] = v->cursor_bw[k] * v->UrgentBurstFactorCursor[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5030
v->TotalVActivePixelBandwidth[i][j] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5031
v->TotalVActiveCursorBandwidth[i][j] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5032
v->TotalMetaRowBandwidth[i][j] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5033
v->TotalDPTERowBandwidth[i][j] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5034
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5035
v->TotalVActivePixelBandwidth[i][j] = v->TotalVActivePixelBandwidth[i][j] + v->VActivePixelBandwidth[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5036
v->TotalVActiveCursorBandwidth[i][j] = v->TotalVActiveCursorBandwidth[i][j] + v->VActiveCursorBandwidth[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5037
v->TotalMetaRowBandwidth[i][j] = v->TotalMetaRowBandwidth[i][j] + v->NoOfDPP[i][j][k] * v->meta_row_bandwidth[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5038
v->TotalDPTERowBandwidth[i][j] = v->TotalDPTERowBandwidth[i][j] + v->NoOfDPP[i][j][k] * v->dpte_row_bandwidth[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5044
for (i = 0; i < v->soc.num_states; ++i) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5046
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5047
if (v->BlendingAndTiming[k] == k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5048
if (v->WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5049
v->WritebackDelayTime[k] = v->WritebackLatency
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5051
v->WritebackPixelFormat[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5052
v->WritebackHRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5053
v->WritebackVRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5054
v->WritebackVTaps[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5055
v->WritebackDestinationWidth[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5056
v->WritebackDestinationHeight[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5057
v->WritebackSourceHeight[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5058
v->HTotal[k]) / v->RequiredDISPCLK[i][j];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5060
v->WritebackDelayTime[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5062
for (m = 0; m < v->NumberOfActivePlanes; m++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5063
if (v->BlendingAndTiming[m] == k && v->WritebackEnable[m] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5064
v->WritebackDelayTime[k] = dml_max(
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5065
v->WritebackDelayTime[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5066
v->WritebackLatency
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5068
v->WritebackPixelFormat[m],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5069
v->WritebackHRatio[m],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5070
v->WritebackVRatio[m],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5071
v->WritebackVTaps[m],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5072
v->WritebackDestinationWidth[m],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5073
v->WritebackDestinationHeight[m],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5074
v->WritebackSourceHeight[m],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5075
v->HTotal[m]) / v->RequiredDISPCLK[i][j]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5080
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5081
for (m = 0; m < v->NumberOfActivePlanes; m++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5082
if (v->BlendingAndTiming[k] == m) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5083
v->WritebackDelayTime[k] = v->WritebackDelayTime[m];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5087
v->MaxMaxVStartup[i][j] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5088
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5089
v->MaximumVStartup[i][j][k] =
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5091
v->VTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5092
v->VActive[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5093
v->VBlankNom[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5094
v->HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5095
v->PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5096
v->ProgressiveToInterlaceUnitInOPP,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5097
v->Interlace[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5098
v->ip.VBlankNomDefaultUS,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5099
v->WritebackDelayTime[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5100
v->MaxMaxVStartup[i][j] = dml_max(v->MaxMaxVStartup[i][j], v->MaximumVStartup[i][j][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5105
ReorderingBytes = v->NumberOfChannels
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5107
v->UrgentOutOfOrderReturnPerChannelPixelDataOnly,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5108
v->UrgentOutOfOrderReturnPerChannelPixelMixedWithVMData,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5109
v->UrgentOutOfOrderReturnPerChannelVMDataOnly);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5111
for (i = 0; i < v->soc.num_states; ++i) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5113
v->DCFCLKState[i][j] = v->DCFCLKPerState[i];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5117
if (v->UseMinimumRequiredDCFCLK == true)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5120
for (i = 0; i < v->soc.num_states; ++i) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5123
v->ReturnBusWidth * v->DCFCLKState[i][j],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5124
v->FabricClockPerState[i] * v->FabricDatapathToDCNDataReturn);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5125
double IdealDRAMBandwidthPerState = v->DRAMSpeedPerState[i] * v->NumberOfChannels * v->DRAMChannelWidth;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5127
IdealFabricAndSDPPortBandwidthPerState * v->PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency / 100.0,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5128
IdealDRAMBandwidthPerState * v->PercentOfIdealDRAMBWReceivedAfterUrgLatencyPixelDataOnly / 100.0);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5130
IdealFabricAndSDPPortBandwidthPerState * v->PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency / 100.0,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5131
IdealDRAMBandwidthPerState * v->PercentOfIdealDRAMBWReceivedAfterUrgLatencyPixelMixedWithVMData / 100.0);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5133
if (v->HostVMEnable != true) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5134
v->ReturnBWPerState[i][j] = PixelDataOnlyReturnBWPerState;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5136
v->ReturnBWPerState[i][j] = PixelMixedWithVMDataReturnBWPerState;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5142
for (i = 0; i < v->soc.num_states; ++i) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5144
if ((v->ROBBufferSizeInKByte - v->PixelChunkSizeInKByte) * 1024 / v->ReturnBWPerState[i][j]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5145
> (v->RoundTripPingLatencyCycles + __DML_ARB_TO_RET_DELAY__) / v->DCFCLKState[i][j] + ReorderingBytes / v->ReturnBWPerState[i][j]) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5146
v->ROBSupport[i][j] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5148
v->ROBSupport[i][j] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5156
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5157
MaxTotalVActiveRDBandwidth = MaxTotalVActiveRDBandwidth + v->ReadBandwidthLuma[k] + v->ReadBandwidthChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5160
for (i = 0; i < v->soc.num_states; ++i) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5162
v->MaxTotalVerticalActiveAvailableBandwidth[i][j] = dml_min(
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5164
v->ReturnBusWidth * v->DCFCLKState[i][j],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5165
v->FabricClockPerState[i] * v->FabricDatapathToDCNDataReturn)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5166
* v->MaxAveragePercentOfIdealFabricAndSDPPortBWDisplayCanUseInNormalSystemOperation / 100,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5167
v->DRAMSpeedPerState[i] * v->NumberOfChannels * v->DRAMChannelWidth
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5168
* v->MaxAveragePercentOfIdealDRAMBWDisplayCanUseInNormalSystemOperation / 100);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5170
if (MaxTotalVActiveRDBandwidth <= v->MaxTotalVerticalActiveAvailableBandwidth[i][j]) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5171
v->TotalVerticalActiveBandwidthSupport[i][j] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5173
v->TotalVerticalActiveBandwidthSupport[i][j] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5178
v->UrgentLatency = CalculateUrgentLatency(
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5179
v->UrgentLatencyPixelDataOnly,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5180
v->UrgentLatencyPixelMixedWithVMData,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5181
v->UrgentLatencyVMDataOnly,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5182
v->DoUrgentLatencyAdjustment,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5183
v->UrgentLatencyAdjustmentFabricClockComponent,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5184
v->UrgentLatencyAdjustmentFabricClockReference,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5185
v->FabricClock);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5187
for (i = 0; i < v->soc.num_states; ++i) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5196
v->TimeCalc = 24 / v->ProjectedDCFCLKDeepSleep[i][j];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5198
v->BandwidthWithoutPrefetchSupported[i][j] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5199
if (v->TotalVActivePixelBandwidth[i][j] + v->TotalVActiveCursorBandwidth[i][j] + v->TotalMetaRowBandwidth[i][j]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5200
+ v->TotalDPTERowBandwidth[i][j] > v->ReturnBWPerState[i][j] || v->NotEnoughUrgentLatencyHidingA[i][j]) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5201
v->BandwidthWithoutPrefetchSupported[i][j] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5204
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5205
v->NoOfDPPThisState[k] = v->NoOfDPP[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5206
v->swath_width_luma_ub_this_state[k] = v->swath_width_luma_ub_all_states[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5207
v->swath_width_chroma_ub_this_state[k] = v->swath_width_chroma_ub_all_states[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5208
v->SwathWidthYThisState[k] = v->SwathWidthYAllStates[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5209
v->SwathWidthCThisState[k] = v->SwathWidthCAllStates[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5210
v->SwathHeightYThisState[k] = v->SwathHeightYAllStates[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5211
v->SwathHeightCThisState[k] = v->SwathHeightCAllStates[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5212
v->DETBufferSizeYThisState[k] = v->DETBufferSizeYAllStates[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5213
v->DETBufferSizeCThisState[k] = v->DETBufferSizeCAllStates[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5218
v->ReturnBusWidth * v->DCFCLKState[i][j],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5219
v->FabricClockPerState[i] * v->FabricDatapathToDCNDataReturn)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5220
* v->PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency / 100.0,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5221
v->DRAMSpeedPerState[i] * v->NumberOfChannels * v->DRAMChannelWidth
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5222
* v->PercentOfIdealDRAMBWReceivedAfterUrgLatencyVMDataOnly / 100.0);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5223
if (v->GPUVMEnable && v->HostVMEnable)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5224
HostVMInefficiencyFactor = v->ReturnBWPerState[i][j] / VMDataOnlyReturnBWPerState;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5226
v->ExtraLatency = CalculateExtraLatency(
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5227
v->RoundTripPingLatencyCycles,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5229
v->DCFCLKState[i][j],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5230
v->TotalNumberOfActiveDPP[i][j],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5231
v->PixelChunkSizeInKByte,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5232
v->TotalNumberOfDCCActiveDPP[i][j],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5233
v->MetaChunkSize,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5234
v->ReturnBWPerState[i][j],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5235
v->GPUVMEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5236
v->HostVMEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5237
v->NumberOfActivePlanes,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5238
v->NoOfDPPThisState,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5239
v->dpte_group_bytes,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5241
v->HostVMMinPageSize,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5242
v->HostVMMaxNonCachedPageTableLevels);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5244
v->NextMaxVStartup = v->MaxMaxVStartup[i][j];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5246
v->PrefetchModePerState[i][j] = NextPrefetchModeState;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5247
v->MaxVStartup = v->NextMaxVStartup;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5249
v->TWait = CalculateTWait(
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5250
v->PrefetchModePerState[i][j],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5251
v->DRAMClockChangeLatency,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5252
v->UrgLatency[i],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5253
v->SREnterPlusExitTime);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5255
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5261
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5263
v->swath_width_luma_ub_this_state[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5264
v->swath_width_chroma_ub_this_state[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5265
v->SwathHeightYThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5266
v->SwathHeightCThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5267
v->HTotal[k] / v->PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5268
v->UrgLatency[i],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5269
v->CursorBufferSize,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5270
v->CursorWidth[k][0],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5271
v->CursorBPP[k][0],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5272
v->VRatioPreY[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5273
v->VRatioPreC[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5274
v->BytePerPixelInDETY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5275
v->BytePerPixelInDETC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5276
v->DETBufferSizeYThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5277
v->DETBufferSizeCThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5278
&v->UrgentBurstFactorCursorPre[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5279
&v->UrgentBurstFactorLumaPre[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5280
&v->UrgentBurstFactorChromaPre[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5281
&v->NotUrgentLatencyHidingPre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5284
v->MaximumReadBandwidthWithPrefetch = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5285
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5286
v->cursor_bw_pre[k] = v->NumberOfCursors[k] * v->CursorWidth[k][0] * v->CursorBPP[k][0] / 8.0
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5287
/ (v->HTotal[k] / v->PixelClock[k]) * v->VRatioPreY[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5289
v->MaximumReadBandwidthWithPrefetch =
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5290
v->MaximumReadBandwidthWithPrefetch
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5292
v->VActivePixelBandwidth[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5293
+ v->VActiveCursorBandwidth[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5294
+ v->NoOfDPP[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5295
* (v->meta_row_bandwidth[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5296
+ v->dpte_row_bandwidth[i][j][k]),
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5297
v->NoOfDPP[i][j][k] * v->prefetch_vmrow_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5298
v->NoOfDPP[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5299
* (v->RequiredPrefetchPixelDataBWLuma[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5300
* v->UrgentBurstFactorLumaPre[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5301
+ v->RequiredPrefetchPixelDataBWChroma[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5302
* v->UrgentBurstFactorChromaPre[k])
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5303
+ v->cursor_bw_pre[k] * v->UrgentBurstFactorCursorPre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5306
v->NotEnoughUrgentLatencyHidingPre = false;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5307
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5308
if (v->NotUrgentLatencyHidingPre[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5309
v->NotEnoughUrgentLatencyHidingPre = true;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5313
v->PrefetchSupported[i][j] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5314
if (v->BandwidthWithoutPrefetchSupported[i][j] == false || v->MaximumReadBandwidthWithPrefetch > v->ReturnBWPerState[i][j]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5315
|| v->NotEnoughUrgentLatencyHidingPre == 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5316
v->PrefetchSupported[i][j] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5318
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5319
if (v->LineTimesForPrefetch[k] < 2.0 || v->LinesForMetaPTE[k] >= 32.0 || v->LinesForMetaAndDPTERow[k] >= 16.0
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5320
|| v->NoTimeForPrefetch[i][j][k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5321
v->PrefetchSupported[i][j] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5325
v->DynamicMetadataSupported[i][j] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5326
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5327
if (v->NoTimeForDynamicMetadata[i][j][k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5328
v->DynamicMetadataSupported[i][j] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5332
v->VRatioInPrefetchSupported[i][j] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5333
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5334
if (v->VRatioPreY[i][j][k] > 4.0 || v->VRatioPreC[i][j][k] > 4.0 || v->NoTimeForPrefetch[i][j][k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5335
v->VRatioInPrefetchSupported[i][j] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5338
v->AnyLinesForVMOrRowTooLarge = false;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5339
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5340
if (v->LinesForMetaAndDPTERow[k] >= 16 || v->LinesForMetaPTE[k] >= 32) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5341
v->AnyLinesForVMOrRowTooLarge = true;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5345
v->NextPrefetchMode = v->NextPrefetchMode + 1;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5347
if (v->PrefetchSupported[i][j] == true && v->VRatioInPrefetchSupported[i][j] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5348
v->BandwidthAvailableForImmediateFlip = v->ReturnBWPerState[i][j];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5349
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5350
v->BandwidthAvailableForImmediateFlip = v->BandwidthAvailableForImmediateFlip
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5352
v->VActivePixelBandwidth[i][j][k] + v->VActiveCursorBandwidth[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5353
v->NoOfDPP[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5354
* (v->RequiredPrefetchPixelDataBWLuma[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5355
* v->UrgentBurstFactorLumaPre[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5356
+ v->RequiredPrefetchPixelDataBWChroma[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5357
* v->UrgentBurstFactorChromaPre[k])
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5358
+ v->cursor_bw_pre[k] * v->UrgentBurstFactorCursorPre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5360
v->TotImmediateFlipBytes = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5361
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5362
v->TotImmediateFlipBytes = v->TotImmediateFlipBytes
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5363
+ v->NoOfDPP[i][j][k] * (v->PDEAndMetaPTEBytesPerFrame[i][j][k] + v->MetaRowBytes[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5364
+ v->DPTEBytesPerRow[i][j][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5367
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5372
v->ExtraLatency,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5373
v->UrgLatency[i],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5374
v->PDEAndMetaPTEBytesPerFrame[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5375
v->MetaRowBytes[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5376
v->DPTEBytesPerRow[i][j][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5378
v->total_dcn_read_bw_with_flip = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5379
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5380
v->total_dcn_read_bw_with_flip = v->total_dcn_read_bw_with_flip
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5382
v->NoOfDPP[i][j][k] * v->prefetch_vmrow_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5383
v->NoOfDPP[i][j][k] * v->final_flip_bw[k] + v->VActivePixelBandwidth[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5384
+ v->VActiveCursorBandwidth[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5385
v->NoOfDPP[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5386
* (v->final_flip_bw[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5387
+ v->RequiredPrefetchPixelDataBWLuma[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5388
* v->UrgentBurstFactorLumaPre[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5389
+ v->RequiredPrefetchPixelDataBWChroma[i][j][k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5390
* v->UrgentBurstFactorChromaPre[k])
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5391
+ v->cursor_bw_pre[k] * v->UrgentBurstFactorCursorPre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5393
v->ImmediateFlipSupportedForState[i][j] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5394
if (v->total_dcn_read_bw_with_flip > v->ReturnBWPerState[i][j]) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5395
v->ImmediateFlipSupportedForState[i][j] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5397
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5398
if (v->ImmediateFlipSupportedForPipe[k] == false) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5399
v->ImmediateFlipSupportedForState[i][j] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5403
v->ImmediateFlipSupportedForState[i][j] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5406
if (v->MaxVStartup <= __DML_VBA_MIN_VSTARTUP__ || v->AnyLinesForVMOrRowTooLarge == false) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5407
v->NextMaxVStartup = v->MaxMaxVStartup[i][j];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5410
v->NextMaxVStartup = v->NextMaxVStartup - 1;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5412
v->NextPrefetchMode = v->NextPrefetchMode + 1;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5413
} while (!((v->PrefetchSupported[i][j] == true && v->DynamicMetadataSupported[i][j] == true && v->VRatioInPrefetchSupported[i][j] == true
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5414
&& ((v->HostVMEnable == false &&
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5415
v->ImmediateFlipRequirement[0] != dm_immediate_flip_required)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5416
|| v->ImmediateFlipSupportedForState[i][j] == true))
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5417
|| (v->NextMaxVStartup == v->MaxMaxVStartup[i][j] && NextPrefetchModeState > MaxPrefetchMode)));
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5420
v->DETBufferSizeInKByte[0],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5421
v->ConfigReturnBufferSizeInKByte,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5422
v->UseUnboundedRequesting,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5423
v->TotalNumberOfActiveDPP[i][j],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5425
v->MaxNumDPP,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5426
v->CompressedBufferSegmentSizeInkByte,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5427
v->Output,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5433
v->PrefetchModePerState[i][j],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5434
v->DCFCLKState[i][j],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5435
v->ReturnBWPerState[i][j],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5436
v->UrgLatency[i],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5437
v->ExtraLatency,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5438
v->SOCCLKPerState[i],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5439
v->ProjectedDCFCLKDeepSleep[i][j],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5440
v->DETBufferSizeYThisState,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5441
v->DETBufferSizeCThisState,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5442
v->SwathHeightYThisState,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5443
v->SwathHeightCThisState,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5444
v->SwathWidthYThisState,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5445
v->SwathWidthCThisState,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5446
v->NoOfDPPThisState,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5447
v->BytePerPixelInDETY,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5448
v->BytePerPixelInDETC,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5451
&v->DRAMClockChangeSupport[i][j],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5460
for (i = 0; i < v->soc.num_states; i++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5462
v->PTEBufferSizeNotExceeded[i][j] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5463
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5464
if (v->PTEBufferSizeNotExceededY[i][j][k] == false || v->PTEBufferSizeNotExceededC[i][j][k] == false) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5465
v->PTEBufferSizeNotExceeded[i][j] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5472
v->CursorSupport = true;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5473
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5474
if (v->CursorWidth[k][0] > 0.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5475
if (v->CursorBPP[k][0] == 64 && v->Cursor64BppSupport == false) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5476
v->CursorSupport = false;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5482
v->PitchSupport = true;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5483
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5484
v->AlignedYPitch[k] = dml_ceil(dml_max(v->PitchY[k], v->SurfaceWidthY[k]), v->MacroTileWidthY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5485
if (v->DCCEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5486
v->AlignedDCCMetaPitchY[k] = dml_ceil(dml_max(v->DCCMetaPitchY[k], v->SurfaceWidthY[k]), 64.0 * v->Read256BlockWidthY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5488
v->AlignedDCCMetaPitchY[k] = v->DCCMetaPitchY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5490
if (v->SourcePixelFormat[k] != dm_444_64 && v->SourcePixelFormat[k] != dm_444_32 && v->SourcePixelFormat[k] != dm_444_16
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5491
&& v->SourcePixelFormat[k] != dm_mono_16 && v->SourcePixelFormat[k] != dm_rgbe
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5492
&& v->SourcePixelFormat[k] != dm_mono_8) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5493
v->AlignedCPitch[k] = dml_ceil(dml_max(v->PitchC[k], v->SurfaceWidthC[k]), v->MacroTileWidthC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5494
if (v->DCCEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5495
v->AlignedDCCMetaPitchC[k] = dml_ceil(
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5496
dml_max(v->DCCMetaPitchC[k], v->SurfaceWidthC[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5497
64.0 * v->Read256BlockWidthC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5499
v->AlignedDCCMetaPitchC[k] = v->DCCMetaPitchC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5502
v->AlignedCPitch[k] = v->PitchC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5503
v->AlignedDCCMetaPitchC[k] = v->DCCMetaPitchC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5505
if (v->AlignedYPitch[k] > v->PitchY[k] || v->AlignedCPitch[k] > v->PitchC[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5506
|| v->AlignedDCCMetaPitchY[k] > v->DCCMetaPitchY[k] || v->AlignedDCCMetaPitchC[k] > v->DCCMetaPitchC[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5507
v->PitchSupport = false;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5511
for (k = 0; k < v->NumberOfActivePlanes; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5512
if (v->ViewportWidth[k] > v->SurfaceWidthY[k] || v->ViewportHeight[k] > v->SurfaceHeightY[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5514
if (v->SourcePixelFormat[k] != dm_444_64 && v->SourcePixelFormat[k] != dm_444_32
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5515
&& v->SourcePixelFormat[k] != dm_444_16 && v->SourcePixelFormat[k] != dm_444_8
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5516
&& v->SourcePixelFormat[k] != dm_rgbe) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5517
if (v->ViewportWidthChroma[k] > v->SurfaceWidthC[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5518
|| v->ViewportHeightChroma[k] > v->SurfaceHeightC[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5526
for (i = v->soc.num_states - 1; i >= 0; i--) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5528
if (v->ScaleRatioAndTapsSupport == true && v->SourceFormatPixelAndScanSupport == true && v->ViewportSizeSupport[i][j] == true
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5529
&& v->LinkCapacitySupport[i] == true && !P2IWith420 && !DSCOnlyIfNecessaryWithBPP
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5530
&& !DSC422NativeNotSupported && v->ODMCombine4To1SupportCheckOK[i] == true && v->NotEnoughDSCUnits[i] == false
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5531
&& v->DTBCLKRequiredMoreThanSupported[i] == false
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5532
&& v->ROBSupport[i][j] == true && v->DISPCLK_DPPCLK_Support[i][j] == true
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5533
&& v->TotalAvailablePipesSupport[i][j] == true && EnoughWritebackUnits == true
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5534
&& v->WritebackLatencySupport == true && v->WritebackScaleRatioAndTapsSupport == true
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5535
&& v->CursorSupport == true && v->PitchSupport == true && ViewportExceedsSurface == false
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5536
&& v->PrefetchSupported[i][j] == true && v->DynamicMetadataSupported[i][j] == true
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5537
&& v->TotalVerticalActiveBandwidthSupport[i][j] == true && v->VRatioInPrefetchSupported[i][j] == true
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5538
&& v->PTEBufferSizeNotExceeded[i][j] == true && v->NonsupportedDSCInputBPC == false
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5539
&& ((v->HostVMEnable == false
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5540
&& v->ImmediateFlipRequirement[0] != dm_immediate_flip_required)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5541
|| v->ImmediateFlipSupportedForState[i][j] == true)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5543
v->ModeSupport[i][j] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5545
v->ModeSupport[i][j] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5549
for (i = v->soc.num_states; i >= 0; i--) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5553
if (!v->ScaleRatioAndTapsSupport) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5555
} else if (!v->SourceFormatPixelAndScanSupport) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5557
} else if (!v->ViewportSizeSupport[i][j]) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5565
} else if (!v->ODMCombine4To1SupportCheckOK[i]) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5567
} else if (v->NotEnoughDSCUnits[i]) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5569
} else if (!v->ROBSupport[i][j]) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5571
} else if (!v->DISPCLK_DPPCLK_Support[i][j]) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5573
} else if (!v->TotalAvailablePipesSupport[i][j]) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5577
} else if (!v->WritebackLatencySupport) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5579
} else if (!v->WritebackScaleRatioAndTapsSupport) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5581
} else if (!v->CursorSupport) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5583
} else if (!v->PitchSupport) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5587
} else if (!v->PrefetchSupported[i][j]) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5589
} else if (!v->DynamicMetadataSupported[i][j]) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5591
} else if (!v->TotalVerticalActiveBandwidthSupport[i][j]) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5593
} else if (!v->VRatioInPrefetchSupported[i][j]) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5595
} else if (!v->PTEBufferSizeNotExceeded[i][j]) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5597
} else if (v->NonsupportedDSCInputBPC) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5599
} else if ((v->HostVMEnable
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5600
&& !v->ImmediateFlipSupportedForState[i][j])) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5612
for (i = v->soc.num_states; i >= 0; i--) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5613
if (i == v->soc.num_states || v->ModeSupport[i][0] == true || v->ModeSupport[i][1] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5614
v->VoltageLevel = i;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5615
v->ModeIsSupported = v->ModeSupport[i][0] == true || v->ModeSupport[i][1] == true;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5616
if (v->ModeSupport[i][0] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5623
v->ImmediateFlipSupport = v->ImmediateFlipSupportedForState[v->VoltageLevel][MaximumMPCCombine];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5624
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5625
v->MPCCombineEnable[k] = v->MPCCombine[v->VoltageLevel][MaximumMPCCombine][k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5626
v->DPPPerPlane[k] = v->NoOfDPP[v->VoltageLevel][MaximumMPCCombine][k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5628
v->DCFCLK = v->DCFCLKState[v->VoltageLevel][MaximumMPCCombine];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5629
v->DRAMSpeed = v->DRAMSpeedPerState[v->VoltageLevel];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5630
v->FabricClock = v->FabricClockPerState[v->VoltageLevel];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5631
v->SOCCLK = v->SOCCLKPerState[v->VoltageLevel];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5632
v->ReturnBW = v->ReturnBWPerState[v->VoltageLevel][MaximumMPCCombine];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5633
v->maxMpcComb = MaximumMPCCombine;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5663
struct vba_vars_st *v = &mode_lib->vba;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5681
v->UrgentWatermark = UrgentLatency + ExtraLatency;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5686
dml_print("DML::%s: UrgentWatermark = %f\n", __func__, v->UrgentWatermark);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5689
v->DRAMClockChangeWatermark = v->DRAMClockChangeLatency + v->UrgentWatermark;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5692
dml_print("DML::%s: v->DRAMClockChangeLatency = %f\n", __func__, v->DRAMClockChangeLatency);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5693
dml_print("DML::%s: DRAMClockChangeWatermark = %f\n", __func__, v->DRAMClockChangeWatermark);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5696
v->TotalActiveWriteback = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5697
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5698
if (v->WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5699
v->TotalActiveWriteback = v->TotalActiveWriteback + 1;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5703
if (v->TotalActiveWriteback <= 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5704
v->WritebackUrgentWatermark = v->WritebackLatency;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5706
v->WritebackUrgentWatermark = v->WritebackLatency + v->WritebackChunkSize * 1024.0 / 32.0 / SOCCLK;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5709
if (v->TotalActiveWriteback <= 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5710
v->WritebackDRAMClockChangeWatermark = v->DRAMClockChangeLatency + v->WritebackLatency;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5712
v->WritebackDRAMClockChangeWatermark = v->DRAMClockChangeLatency + v->WritebackLatency + v->WritebackChunkSize * 1024.0 / 32.0 / SOCCLK;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5715
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5717
+ DPPPerPlane[k] * (SwathWidthY[k] * BytePerPixelDETY[k] * v->VRatio[k] + SwathWidthC[k] * BytePerPixelDETC[k] * v->VRatioChroma[k])
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5718
/ (v->HTotal[k] / v->PixelClock[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5721
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5724
v->LBLatencyHidingSourceLinesY = dml_min(
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5725
(double) v->MaxLineBufferLines,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5726
dml_floor(v->LineBufferSize / v->LBBitPerPixel[k] / (SwathWidthY[k] / dml_max(v->HRatio[k], 1.0)), 1)) - (v->vtaps[k] - 1);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5728
v->LBLatencyHidingSourceLinesC = dml_min(
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5729
(double) v->MaxLineBufferLines,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5730
dml_floor(v->LineBufferSize / v->LBBitPerPixel[k] / (SwathWidthC[k] / dml_max(v->HRatioChroma[k], 1.0)), 1)) - (v->VTAPsChroma[k] - 1);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5732
EffectiveLBLatencyHidingY = v->LBLatencyHidingSourceLinesY / v->VRatio[k] * (v->HTotal[k] / v->PixelClock[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5734
EffectiveLBLatencyHidingC = v->LBLatencyHidingSourceLinesC / v->VRatioChroma[k] * (v->HTotal[k] / v->PixelClock[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5738
+ CompressedBufferSizeInkByte * 1024 * SwathWidthY[k] * BytePerPixelDETY[k] * v->VRatio[k] / (v->HTotal[k] / v->PixelClock[k]) / TotalPixelBW;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5743
FullDETBufferingTimeY = LinesInDETYRoundedDownToSwath[k] * (v->HTotal[k] / v->PixelClock[k]) / v->VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5745
LinesInDETC = v->DETBufferSizeC[k] / BytePerPixelDETC[k] / SwathWidthC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5747
FullDETBufferingTimeC = LinesInDETCRoundedDownToSwath * (v->HTotal[k] / v->PixelClock[k]) / v->VRatioChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5754
- ((double) v->DSTXAfterScaler[k] / v->HTotal[k] + v->DSTYAfterScaler[k]) * v->HTotal[k] / v->PixelClock[k] - v->UrgentWatermark - v->DRAMClockChangeWatermark;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5756
if (v->NumberOfActivePlanes > 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5758
- (1 - 1.0 / v->NumberOfActivePlanes) * SwathHeightY[k] * v->HTotal[k] / v->PixelClock[k] / v->VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5763
- ((double) v->DSTXAfterScaler[k] / v->HTotal[k] + v->DSTYAfterScaler[k]) * v->HTotal[k] / v->PixelClock[k] - v->UrgentWatermark - v->DRAMClockChangeWatermark;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5765
if (v->NumberOfActivePlanes > 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5767
- (1 - 1.0 / v->NumberOfActivePlanes) * SwathHeightC[k] * v->HTotal[k] / v->PixelClock[k] / v->VRatioChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5769
v->ActiveDRAMClockChangeLatencyMargin[k] = dml_min(ActiveDRAMClockChangeLatencyMarginY, ActiveDRAMClockChangeLatencyMarginC);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5771
v->ActiveDRAMClockChangeLatencyMargin[k] = ActiveDRAMClockChangeLatencyMarginY;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5774
if (v->WritebackEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5775
WritebackDRAMClockChangeLatencyHiding = v->WritebackInterfaceBufferSize * 1024
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5776
/ (v->WritebackDestinationWidth[k] * v->WritebackDestinationHeight[k] / (v->WritebackSourceHeight[k] * v->HTotal[k] / v->PixelClock[k]) * 4);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5777
if (v->WritebackPixelFormat[k] == dm_444_64) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5780
WritebackDRAMClockChangeLatencyMargin = WritebackDRAMClockChangeLatencyHiding - v->WritebackDRAMClockChangeWatermark;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5781
v->ActiveDRAMClockChangeLatencyMargin[k] = dml_min(v->ActiveDRAMClockChangeLatencyMargin[k], WritebackDRAMClockChangeLatencyMargin);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5785
v->MinActiveDRAMClockChangeMargin = 999999;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5787
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5788
if (v->ActiveDRAMClockChangeLatencyMargin[k] < v->MinActiveDRAMClockChangeMargin) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5789
v->MinActiveDRAMClockChangeMargin = v->ActiveDRAMClockChangeLatencyMargin[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5790
if (v->BlendingAndTiming[k] == k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5793
for (j = 0; j < v->NumberOfActivePlanes; ++j) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5794
if (v->BlendingAndTiming[k] == j) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5802
v->MinActiveDRAMClockChangeLatencySupported = v->MinActiveDRAMClockChangeMargin + v->DRAMClockChangeLatency ;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5805
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5806
if (!((k == PlaneWithMinActiveDRAMClockChangeMargin) && (v->BlendingAndTiming[k] == k)) && !(v->BlendingAndTiming[k] == PlaneWithMinActiveDRAMClockChangeMargin)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5807
&& v->ActiveDRAMClockChangeLatencyMargin[k] < SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5808
SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank = v->ActiveDRAMClockChangeLatencyMargin[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5812
v->TotalNumberOfActiveOTG = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5814
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5815
if (v->BlendingAndTiming[k] == k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5816
v->TotalNumberOfActiveOTG = v->TotalNumberOfActiveOTG + 1;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5820
if (v->MinActiveDRAMClockChangeMargin > 0 && PrefetchMode == 0) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5822
} else if ((v->SynchronizedVBlank == true || v->TotalNumberOfActiveOTG == 1
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5829
*StutterExitWatermark = v->SRExitTime + ExtraLatency + 10 / DCFCLKDeepSleep;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5830
*StutterEnterPlusExitWatermark = (v->SREnterPlusExitTime + ExtraLatency + 10 / DCFCLKDeepSleep);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5831
*Z8StutterExitWatermark = v->SRExitZ8Time + ExtraLatency + 10 / DCFCLKDeepSleep;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5832
*Z8StutterEnterPlusExitWatermark = v->SREnterPlusExitZ8Time + ExtraLatency + 10 / DCFCLKDeepSleep;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5863
struct vba_vars_st *v = &mode_lib->vba;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5887
v->DCFCLKDeepSleepPerPlane[k] = dml_max(__DML_MIN_DCFCLK_FACTOR__ * SwathWidthY[k] * BytePerPixelY[k] / 32.0 / DisplayPipeLineDeliveryTimeLuma,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5890
v->DCFCLKDeepSleepPerPlane[k] = __DML_MIN_DCFCLK_FACTOR__ * SwathWidthY[k] * BytePerPixelY[k] / 64.0 / DisplayPipeLineDeliveryTimeLuma;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5892
v->DCFCLKDeepSleepPerPlane[k] = dml_max(v->DCFCLKDeepSleepPerPlane[k], PixelClock[k] / 16);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
5903
*DCFCLKDeepSleep = dml_max(*DCFCLKDeepSleep, v->DCFCLKDeepSleepPerPlane[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6448
struct vba_vars_st *v = &mode_lib->vba;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
6666
if (v->BlendingAndTiming[k] == k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7117
struct vba_vars_st *v = &mode_lib->vba;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7122
NormalEfficiency = v->PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency / 100.0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7123
for (i = 0; i < v->soc.num_states; ++i) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7140
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7142
+ v->NoOfDPP[i][j][k] * v->DPTEBytesPerRow[i][j][k] / (15.75 * v->HTotal[k] / v->PixelClock[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7145
for (k = 0; k <= v->NumberOfActivePlanes - 1; ++k)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7146
NoOfDPPState[k] = v->NoOfDPP[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7148
MinimumTWait = CalculateTWait(MaxPrefetchMode, v->FinalDRAMClockChangeLatency, v->UrgLatency[i], v->SREnterPlusExitTime);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7149
NonDPTEBandwidth = v->TotalVActivePixelBandwidth[i][j] + v->TotalVActiveCursorBandwidth[i][j] + v->TotalMetaRowBandwidth[i][j];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7150
DPTEBandwidth = (v->HostVMEnable == true || v->ImmediateFlipRequirement[0] == dm_immediate_flip_required) ?
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7151
TotalMaxPrefetchFlipDPTERowBandwidth[i][j] : v->TotalDPTERowBandwidth[i][j];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7153
v->ProjectedDCFCLKDeepSleep[i][j],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7154
(NonDPTEBandwidth + v->TotalDPTERowBandwidth[i][j]) / v->ReturnBusWidth
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7155
/ (v->MaxAveragePercentOfIdealFabricAndSDPPortBWDisplayCanUseInNormalSystemOperation / 100),
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7156
(NonDPTEBandwidth + DPTEBandwidth / NormalEfficiency) / NormalEfficiency / v->ReturnBusWidth);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7160
v->TotalNumberOfActiveDPP[i][j],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7161
v->PixelChunkSizeInKByte,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7162
v->TotalNumberOfDCCActiveDPP[i][j],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7163
v->MetaChunkSize,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7164
v->GPUVMEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7165
v->HostVMEnable,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7166
v->NumberOfActivePlanes,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7168
v->dpte_group_bytes,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7170
v->HostVMMinPageSize,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7171
v->HostVMMaxNonCachedPageTableLevels);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7172
ExtraLatencyCycles = v->RoundTripPingLatencyCycles + __DML_ARB_TO_RET_DELAY__ + ExtraLatencyBytes / NormalEfficiency / v->ReturnBusWidth;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7173
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7178
PixelDCFCLKCyclesRequiredInPrefetch[k] = (v->PrefetchLinesY[i][j][k] * v->swath_width_luma_ub_all_states[i][j][k] * v->BytePerPixelY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7179
+ v->PrefetchLinesC[i][j][k] * v->swath_width_chroma_ub_all_states[i][j][k] * v->BytePerPixelC[k]) / NormalEfficiency / v->ReturnBusWidth;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7181
+ v->PDEAndMetaPTEBytesPerFrame[i][j][k] / NormalEfficiency / NormalEfficiency / v->ReturnBusWidth * (v->GPUVMMaxPageTableLevels > 2 ? 1 : 0)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7182
+ 2 * v->DPTEBytesPerRow[i][j][k] / NormalEfficiency / NormalEfficiency / v->ReturnBusWidth
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7183
+ 2 * v->MetaRowBytes[i][j][k] / NormalEfficiency / v->ReturnBusWidth + PixelDCFCLKCyclesRequiredInPrefetch[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7184
PrefetchPixelLinesTime[k] = dml_max(v->PrefetchLinesY[i][j][k], v->PrefetchLinesC[i][j][k]) * v->HTotal[k] / v->PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7185
ExpectedPrefetchBWAcceleration = (v->VActivePixelBandwidth[i][j][k] + v->VActiveCursorBandwidth[i][j][k])
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7186
/ (v->ReadBandwidthLuma[k] + v->ReadBandwidthChroma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7188
(v->GPUVMEnable == true && v->DynamicMetadataEnable[k] == true && v->DynamicMetadataVMEnabled == true) ?
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7189
v->UrgLatency[i] * v->GPUVMMaxPageTableLevels * (v->HostVMEnable == true ? v->HostVMMaxNonCachedPageTableLevels + 1 : 1) : 0;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7190
PrefetchTime = (v->MaximumVStartup[i][j][k] - 1) * v->HTotal[k] / v->PixelClock[k] - MinimumTWait
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7191
- v->UrgLatency[i]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7192
* ((v->GPUVMMaxPageTableLevels <= 2 ? v->GPUVMMaxPageTableLevels : v->GPUVMMaxPageTableLevels - 2)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7193
* (v->HostVMEnable == true ? v->HostVMMaxNonCachedPageTableLevels + 1 : 1) - 1)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7203
if (v->HostVMEnable == true || v->ImmediateFlipRequirement[0] == dm_immediate_flip_required) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7205
+ NoOfDPPState[k] * DPTEBandwidth / NormalEfficiency / NormalEfficiency / v->ReturnBusWidth;
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7208
DCFCLKRequiredForPeakBandwidthPerPlane[k] = v->DCFCLKPerState[i];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7210
if (v->DynamicMetadataEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7218
v->MaxInterDCNTileRepeaters,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7219
v->RequiredDPPCLK[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7220
v->RequiredDISPCLK[i][j],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7221
v->ProjectedDCFCLKDeepSleep[i][j],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7222
v->PixelClock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7223
v->HTotal[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7224
v->VTotal[k] - v->VActive[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7225
v->DynamicMetadataTransmittedBytes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7226
v->DynamicMetadataLinesBeforeActiveRequired[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7227
v->Interlace[k],
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7228
v->ProgressiveToInterlaceUnitInOPP,
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7236
AllowedTimeForUrgentExtraLatency = v->MaximumVStartup[i][j][k] * v->HTotal[k] / v->PixelClock[k] - MinimumTWait - TSetupPipe - TdmbfPipe - TdmecPipe
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7243
DCFCLKRequiredForPeakBandwidthPerPlane[k] = v->DCFCLKPerState[i];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7248
for (k = 0; k <= v->NumberOfActivePlanes - 1; ++k)
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7251
MinimumTvmPlus2Tr0 = v->UrgLatency[i]
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7252
* (v->GPUVMEnable == true ?
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7253
(v->HostVMEnable == true ?
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7254
(v->GPUVMMaxPageTableLevels + 2) * (v->HostVMMaxNonCachedPageTableLevels + 1) - 1 : v->GPUVMMaxPageTableLevels + 1) :
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7256
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7259
MaximumTvmPlus2Tr0PlusTsw = (v->MaximumVStartup[i][j][k] - 2) * v->HTotal[k] / v->PixelClock[k] - MinimumTWait - DynamicMetadataVMExtraLatency[k];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7261
DCFCLKRequiredForPeakBandwidth = v->DCFCLKPerState[i];
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
7269
v->DCFCLKState[i][j] = dml_min(v->DCFCLKPerState[i], 1.05 * dml_max(DCFCLKRequiredForAverageBandwidth, DCFCLKRequiredForPeakBandwidth));
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
1301
struct dc_state *context, struct vba_vars_st *v, int *split,
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
1361
&slice_table, dc, context, v,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1001
if (v->PrefetchModeSupported == true && mode_lib->vba.ImmediateFlipSupport == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1005
v->ReadBandwidthSurfaceLuma,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1006
v->ReadBandwidthSurfaceChroma,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1007
v->RequiredPrefetchPixDataBWLuma,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1008
v->RequiredPrefetchPixDataBWChroma,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1009
v->cursor_bw,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
101
v->DISPCLK_calculated = v->WritebackDISPCLK;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1010
v->cursor_bw_pre,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1012
v->UrgBurstFactorLuma,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1013
v->UrgBurstFactorChroma,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1014
v->UrgBurstFactorCursor,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1015
v->UrgBurstFactorLumaPre,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1016
v->UrgBurstFactorChromaPre,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1017
v->UrgBurstFactorCursorPre);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1024
* (v->PDEAndMetaPTEBytesFrame[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1025
+ v->MetaRowByte[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1026
if (v->use_one_row_for_frame_flip[k][0][0]) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1029
+ 2 * v->PixelPTEBytesPerRow[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1033
+ v->PixelPTEBytesPerRow[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1038
dml32_CalculateFlipSchedule(v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.HostVMInefficiencyFactor,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1039
v->UrgentExtraLatency,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1040
v->UrgentLatency,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1046
v->PDEAndMetaPTEBytesFrame[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1047
v->MetaRowByte[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1048
v->PixelPTEBytesPerRow[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
105
v->DISPCLK_calculated = dml_max(v->DISPCLK_calculated,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1055
v->Tno_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1057
v->dpte_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1058
v->meta_row_height[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1059
v->dpte_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1060
v->meta_row_height_chroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1061
v->Use_One_Row_For_Frame_Flip[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1064
&v->DestinationLinesToRequestVMInImmediateFlip[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1065
&v->DestinationLinesToRequestRowInImmediateFlip[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1066
&v->final_flip_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1067
&v->ImmediateFlipSupportedForPipe[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1074
v->final_flip_bw,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1075
v->ReadBandwidthSurfaceLuma,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1076
v->ReadBandwidthSurfaceChroma,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1077
v->RequiredPrefetchPixDataBWLuma,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1078
v->RequiredPrefetchPixDataBWChroma,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1079
v->cursor_bw,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1080
v->meta_row_bw,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1081
v->dpte_row_bw,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1082
v->cursor_bw_pre,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1083
v->prefetch_vmrow_bw,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1085
v->UrgBurstFactorLuma,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1086
v->UrgBurstFactorChroma,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1087
v->UrgBurstFactorCursor,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1088
v->UrgBurstFactorLumaPre,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1089
v->UrgBurstFactorChromaPre,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1090
v->UrgBurstFactorCursorPre,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1093
&v->total_dcn_read_bw_with_flip, // Single *TotalBandwidth
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1094
&v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.dummy_single[0], // Single *FractionOfUrgentBandwidth
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1095
&v->ImmediateFlipSupported); // Boolean *ImmediateFlipBandwidthSupport
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1100
v->final_flip_bw,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1101
v->ReadBandwidthSurfaceLuma,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1102
v->ReadBandwidthSurfaceChroma,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1103
v->RequiredPrefetchPixDataBWLuma,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1104
v->RequiredPrefetchPixDataBWChroma,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1105
v->cursor_bw,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1106
v->meta_row_bw,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1107
v->dpte_row_bw,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1108
v->cursor_bw_pre,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1109
v->prefetch_vmrow_bw,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1111
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.dummy_unit_vector,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1112
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.dummy_unit_vector,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1113
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.dummy_unit_vector,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1114
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.dummy_unit_vector,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1115
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.dummy_unit_vector,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1116
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.dummy_unit_vector,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1119
&v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.dummy_single[1], // Single *TotalBandwidth
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
112
mode_lib->vba.MaxDppclk[v->soc.num_states - 1]));
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1120
&v->FractionOfUrgentBandwidthImmediateFlip, // Single *FractionOfUrgentBandwidth
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1121
&v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.dummy_boolean); // Boolean *ImmediateFlipBandwidthSupport
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1125
if (mode_lib->vba.ImmediateFlipRequirement[k] != dm_immediate_flip_not_required && v->ImmediateFlipSupportedForPipe[k] == false) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1126
v->ImmediateFlipSupported = false;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1133
v->ImmediateFlipSupported = false;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1137
v->PrefetchAndImmediateFlipSupported = (v->PrefetchModeSupported == true &&
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1139
v->ImmediateFlipSupported)) ? true : false;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1152
v->VStartupLines = v->VStartupLines + 1;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1154
if (v->VStartupLines > v->MaximumMaxVStartupLines) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1167
} while (!(v->PrefetchAndImmediateFlipSupported || NextPrefetchMode > mode_lib->vba.MaxPrefetchMode));
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1170
if (v->VStartupLines <= v->MaximumMaxVStartupLines) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1179
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.mmSOCParameters.UrgentLatency = v->UrgentLatency;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1180
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.mmSOCParameters.ExtraLatency = v->UrgentExtraLatency;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1181
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.mmSOCParameters.WritebackLatency = mode_lib->vba.WritebackLatency;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1182
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.mmSOCParameters.DRAMClockChangeLatency = mode_lib->vba.DRAMClockChangeLatency;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1183
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.mmSOCParameters.FCLKChangeLatency = mode_lib->vba.FCLKChangeLatency;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1184
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.mmSOCParameters.SRExitTime = mode_lib->vba.SRExitTime;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1185
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.mmSOCParameters.SREnterPlusExitTime = mode_lib->vba.SREnterPlusExitTime;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1186
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.mmSOCParameters.SRExitZ8Time = mode_lib->vba.SRExitZ8Time;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1187
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.mmSOCParameters.SREnterPlusExitZ8Time = mode_lib->vba.SREnterPlusExitZ8Time;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1188
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.mmSOCParameters.USRRetrainingLatency = mode_lib->vba.USRRetrainingLatency;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1189
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.mmSOCParameters.SMNLatency = mode_lib->vba.SMNLatency;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1192
v,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1193
v->PrefetchModePerState[v->VoltageLevel][v->maxMpcComb],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1194
v->DCFCLK,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1195
v->ReturnBW,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1196
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.mmSOCParameters,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1197
v->SOCCLK,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1198
v->DCFCLKDeepSleep,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1199
v->DETBufferSizeY,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1200
v->DETBufferSizeC,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1201
v->SwathHeightY,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1202
v->SwathHeightC,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1203
v->SwathWidthY,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1204
v->SwathWidthC,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1205
v->DPPPerPlane,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1206
v->BytePerPixelDETY,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1207
v->BytePerPixelDETC,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1208
v->DSTXAfterScaler,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1209
v->DSTYAfterScaler,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1210
v->UnboundedRequestEnabled,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1211
v->CompressedBufferSizeInkByte,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1214
&v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.dummy_dramchange_support,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1215
v->MaxActiveDRAMClockChangeLatencySupported,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1216
v->SubViewportLinesNeededInMALL,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1217
&v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.dummy_fclkchange_support,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1218
&v->MinActiveFCLKChangeLatencySupported,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1219
&v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.dummy_USRRetrainingSupport,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1226
v->UrgentWatermark = v->Watermark.UrgentWatermark;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1227
v->WritebackUrgentWatermark = v->Watermark.WritebackUrgentWatermark;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1228
v->DRAMClockChangeWatermark = v->Watermark.DRAMClockChangeWatermark;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1229
v->WritebackDRAMClockChangeWatermark = v->Watermark.WritebackDRAMClockChangeWatermark;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1230
v->StutterExitWatermark = v->Watermark.StutterExitWatermark;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1231
v->StutterEnterPlusExitWatermark = v->Watermark.StutterEnterPlusExitWatermark;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1232
v->Z8StutterExitWatermark = v->Watermark.Z8StutterExitWatermark;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1233
v->Z8StutterEnterPlusExitWatermark = v->Watermark.Z8StutterEnterPlusExitWatermark;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1237
v->WritebackAllowDRAMClockChangeEndPosition[k] = dml_max(0,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1238
v->VStartup[k] * mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1239
- v->Watermark.WritebackDRAMClockChangeWatermark);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1240
v->WritebackAllowFCLKChangeEndPosition[k] = dml_max(0,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1241
v->VStartup[k] * mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1242
- v->Watermark.WritebackFCLKChangeWatermark);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1244
v->WritebackAllowDRAMClockChangeEndPosition[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1245
v->WritebackAllowFCLKChangeEndPosition[k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1255
v->VRatioPrefetchY,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1256
v->VRatioPrefetchC,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1257
v->swath_width_luma_ub,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1258
v->swath_width_chroma_ub,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1263
v->PSCL_THROUGHPUT_LUMA,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1264
v->PSCL_THROUGHPUT_CHROMA,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1266
v->BytePerPixelC,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1271
v->BlockWidth256BytesY,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1272
v->BlockHeight256BytesY,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1273
v->BlockWidth256BytesC,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1274
v->BlockHeight256BytesC,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1277
v->DisplayPipeLineDeliveryTimeLuma,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1278
v->DisplayPipeLineDeliveryTimeChroma,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1279
v->DisplayPipeLineDeliveryTimeLumaPrefetch,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1280
v->DisplayPipeLineDeliveryTimeChromaPrefetch,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1281
v->DisplayPipeRequestDeliveryTimeLuma,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1282
v->DisplayPipeRequestDeliveryTimeChroma,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1283
v->DisplayPipeRequestDeliveryTimeLumaPrefetch,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1284
v->DisplayPipeRequestDeliveryTimeChromaPrefetch,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1285
v->CursorRequestDeliveryTime,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1286
v->CursorRequestDeliveryTimePrefetch);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1288
dml32_CalculateMetaAndPTETimes(v->Use_One_Row_For_Frame,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1296
v->DestinationLinesToRequestRowInVBlank,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1297
v->DestinationLinesToRequestRowInImmediateFlip,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1300
v->BytePerPixelY,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1301
v->BytePerPixelC,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1303
v->dpte_row_height,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1304
v->dpte_row_height_chroma,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1305
v->meta_row_width,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1306
v->meta_row_width_chroma,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1307
v->meta_row_height,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1308
v->meta_row_height_chroma,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1309
v->meta_req_width,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
131
&v->PSCL_THROUGHPUT_LUMA[k], &v->PSCL_THROUGHPUT_CHROMA[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1310
v->meta_req_width_chroma,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1311
v->meta_req_height,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1312
v->meta_req_height_chroma,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1313
v->dpte_group_bytes,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1314
v->PTERequestSizeY,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1315
v->PTERequestSizeC,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1316
v->PixelPTEReqWidthY,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1317
v->PixelPTEReqHeightY,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1318
v->PixelPTEReqWidthC,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1319
v->PixelPTEReqHeightC,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
132
&v->DPPCLKUsingSingleDPP[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1320
v->dpte_row_width_luma_ub,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1321
v->dpte_row_width_chroma_ub,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1324
v->DST_Y_PER_PTE_ROW_NOM_L,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1325
v->DST_Y_PER_PTE_ROW_NOM_C,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1326
v->DST_Y_PER_META_ROW_NOM_L,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1327
v->DST_Y_PER_META_ROW_NOM_C,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1328
v->TimePerMetaChunkNominal,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1329
v->TimePerChromaMetaChunkNominal,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1330
v->TimePerMetaChunkVBlank,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1331
v->TimePerChromaMetaChunkVBlank,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1332
v->TimePerMetaChunkFlip,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1333
v->TimePerChromaMetaChunkFlip,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1334
v->time_per_pte_group_nom_luma,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1335
v->time_per_pte_group_vblank_luma,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1336
v->time_per_pte_group_flip_luma,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1337
v->time_per_pte_group_nom_chroma,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1338
v->time_per_pte_group_vblank_chroma,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1339
v->time_per_pte_group_flip_chroma);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1346
v->BytePerPixelC,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1347
v->DestinationLinesToRequestVMInVBlank,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1348
v->DestinationLinesToRequestVMInImmediateFlip,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1351
v->dpte_row_width_luma_ub,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1352
v->dpte_row_width_chroma_ub,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1353
v->vm_group_bytes,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1354
v->dpde0_bytes_per_frame_ub_l,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1355
v->dpde0_bytes_per_frame_ub_c,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1356
v->meta_pte_bytes_per_frame_ub_l,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1357
v->meta_pte_bytes_per_frame_ub_c,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
136
mode_lib->vba.DISPCLKDPPCLKVCOSpeed, v->DPPCLKUsingSingleDPP, mode_lib->vba.DPPPerPlane,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1360
v->TimePerVMGroupVBlank,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1361
v->TimePerVMGroupFlip,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1362
v->TimePerVMRequestVBlank,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1363
v->TimePerVMRequestFlip);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1368
v->MinTTUVBlank[k] = dml_max4(v->Watermark.DRAMClockChangeWatermark,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1369
v->Watermark.FCLKChangeWatermark, v->Watermark.StutterEnterPlusExitWatermark,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1370
v->Watermark.UrgentWatermark);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1373
v->MinTTUVBlank[k] = dml_max3(v->Watermark.FCLKChangeWatermark,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1374
v->Watermark.StutterEnterPlusExitWatermark, v->Watermark.UrgentWatermark);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1377
v->MinTTUVBlank[k] = dml_max(v->Watermark.StutterEnterPlusExitWatermark,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1378
v->Watermark.UrgentWatermark);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
138
&v->GlobalDPPCLK, v->DPPCLK);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1380
v->MinTTUVBlank[k] = v->Watermark.UrgentWatermark;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1383
v->MinTTUVBlank[k] = mode_lib->vba.TCalc + v->MinTTUVBlank[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1399
v->BlockHeight256BytesY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
140
for (k = 0; k < v->NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1400
v->BlockHeight256BytesC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1402
v->BytePerPixelY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1403
v->BytePerPixelC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1404
v->BytePerPixelDETY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1405
v->BytePerPixelDETC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1408
&v->DCCYMaxUncompressedBlock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1409
&v->DCCCMaxUncompressedBlock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
141
v->DPPCLK_calculated[k] = v->DPPCLK[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1410
&v->DCCYMaxCompressedBlock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1411
&v->DCCCMaxCompressedBlock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1412
&v->DCCYIndependentBlock[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1413
&v->DCCCIndependentBlock[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1419
double Tvstartup_margin = (v->MaxVStartupLines[k] - v->VStartup[k]) * mode_lib->vba.HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1423
v->MinTTUVBlank[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1426
v->MinTTUVBlank[k] = v->MinTTUVBlank[k] + Tvstartup_margin;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1430
dml_print("DML::%s: k=%d, MaxVStartupLines = %d\n", __func__, k, v->MaxVStartupLines[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1431
dml_print("DML::%s: k=%d, VStartup = %d\n", __func__, k, v->VStartup[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1432
dml_print("DML::%s: k=%d, MinTTUVBlank = %f\n", __func__, k, v->MinTTUVBlank[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1435
v->Tdmdl[k] = v->Tdmdl[k] + Tvstartup_margin;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1437
v->Tdmdl_vm[k] = v->Tdmdl_vm[k] + Tvstartup_margin;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1442
v->MIN_DST_Y_NEXT_START[k] = ((isInterlaceTiming ? dml_floor((mode_lib->vba.VTotal[k] -
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1446
dml_ceil(v->WritebackDelay[mode_lib->vba.VoltageLevel][k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1448
+ dml_floor(4.0 * v->TSetup[k] / (mode_lib->vba.HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1451
v->VStartup[k] = (isInterlaceTiming ? (2 * v->MaxVStartupLines[k]) : v->MaxVStartupLines[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1453
if (((v->VUpdateOffsetPix[k] + v->VUpdateWidthPix[k] + v->VReadyOffsetPix[k])
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1455
- mode_lib->vba.VActive[k] - mode_lib->vba.VFrontPorch[k] - v->VStartup[k]) / 2.0, 1.0) :
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1457
- mode_lib->vba.VFrontPorch[k] - v->VStartup[k]))) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1458
v->VREADY_AT_OR_AFTER_VSYNC[k] = true;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1460
v->VREADY_AT_OR_AFTER_VSYNC[k] = false;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1463
dml_print("DML::%s: k=%d, VStartup = %d (max)\n", __func__, k, v->VStartup[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1464
dml_print("DML::%s: k=%d, VUpdateOffsetPix = %d\n", __func__, k, v->VUpdateOffsetPix[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1465
dml_print("DML::%s: k=%d, VUpdateWidthPix = %d\n", __func__, k, v->VUpdateWidthPix[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1466
dml_print("DML::%s: k=%d, VReadyOffsetPix = %d\n", __func__, k, v->VReadyOffsetPix[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1471
dml_print("DML::%s: k=%d, VStartup = %d\n", __func__, k, v->VStartup[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1472
dml_print("DML::%s: k=%d, TSetup = %f\n", __func__, k, v->TSetup[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1473
dml_print("DML::%s: k=%d, MIN_DST_Y_NEXT_START = %f\n", __func__, k, v->MIN_DST_Y_NEXT_START[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1475
v->VREADY_AT_OR_AFTER_VSYNC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1497
v->TotalDataReadBandwidth = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1499
v->TotalDataReadBandwidth = v->TotalDataReadBandwidth + v->ReadBandwidthSurfaceLuma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
150
&v->BytePerPixelY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1500
+ v->ReadBandwidthSurfaceChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1503
__func__, k, v->TotalDataReadBandwidth);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1505
__func__, k, v->ReadBandwidthSurfaceLuma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1507
__func__, k, v->ReadBandwidthSurfaceChroma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
151
&v->BytePerPixelC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1513
dml32_CalculateStutterEfficiency(v->CompressedBufferSizeInkByte,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1515
v->UnboundedRequestEnabled,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
152
&v->BytePerPixelDETY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1521
v->TotalDataReadBandwidth,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1524
v->CompbufReservedSpace64B,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1525
v->CompbufReservedSpaceZs,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
153
&v->BytePerPixelDETC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1530
v->Watermark.StutterEnterPlusExitWatermark,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1531
v->Watermark.Z8StutterEnterPlusExitWatermark,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1534
v->MinTTUVBlank, mode_lib->vba.DPPPerPlane,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1536
v->BytePerPixelY,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1537
v->BytePerPixelDETY,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1538
v->SwathWidthY,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
154
&v->BlockHeight256BytesY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1549
v->BlockHeight256BytesY,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
155
&v->BlockHeight256BytesC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1550
v->BlockWidth256BytesY,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1551
v->BlockHeight256BytesC,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1552
v->BlockWidth256BytesC,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1553
v->DCCYMaxUncompressedBlock,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1554
v->DCCCMaxUncompressedBlock,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1558
v->ReadBandwidthSurfaceLuma,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1559
v->ReadBandwidthSurfaceChroma,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
156
&v->BlockWidth256BytesY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1560
v->meta_row_bw,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1561
v->dpte_row_bw,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1563
&v->StutterEfficiencyNotIncludingVBlank,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1564
&v->StutterEfficiency,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1565
&v->NumberOfStutterBurstsPerFrame,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1566
&v->Z8StutterEfficiencyNotIncludingVBlank,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1567
&v->Z8StutterEfficiency,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1568
&v->Z8NumberOfStutterBurstsPerFrame,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1569
&v->StutterPeriod,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
157
&v->BlockWidth256BytesC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1570
&v->DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1577
dml32_CalculateStutterEfficiency(v->CompressedBufferSizeInkByte,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1579
v->UnboundedRequestEnabled,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
158
&v->BlockHeightY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1585
v->TotalDataReadBandwidth,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
159
&v->BlockHeightC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1594
v->Watermark.StutterEnterPlusExitWatermark,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1595
v->Watermark.Z8StutterEnterPlusExitWatermark,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1598
v->MinTTUVBlank,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
160
&v->BlockWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1601
v->BytePerPixelY, v->BytePerPixelDETY,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1602
v->SwathWidthY, mode_lib->vba.SwathHeightY,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
161
&v->BlockWidthC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1613
v->BlockHeight256BytesY,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1614
v->BlockWidth256BytesY,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1615
v->BlockHeight256BytesC,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1616
v->BlockWidth256BytesC,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1617
v->DCCYMaxUncompressedBlock,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1618
v->DCCCMaxUncompressedBlock,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1622
v->ReadBandwidthSurfaceLuma,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1623
v->ReadBandwidthSurfaceChroma,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1624
v->meta_row_bw, v->dpte_row_bw,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1627
&v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.dummy_single[0],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1628
&v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.dummy_single[1],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1630
&v->Z8StutterEfficiencyNotIncludingVBlankBestCase,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1631
&v->Z8StutterEfficiencyBestCase,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1632
&v->Z8NumberOfStutterBurstsPerFrameBestCase,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1633
&v->StutterPeriodBestCase,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1634
&v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.dummy_boolean);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1637
v->Z8StutterEfficiencyNotIncludingVBlankBestCase = v->Z8StutterEfficiencyNotIncludingVBlank;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1638
v->Z8StutterEfficiencyBestCase = v->Z8StutterEfficiency;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1639
v->Z8NumberOfStutterBurstsPerFrameBestCase = v->Z8NumberOfStutterBurstsPerFrame;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1640
v->StutterPeriodBestCase = v->StutterPeriod;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1648
static void mode_support_configuration(struct vba_vars_st *v,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1654
start_state = v->soc.num_states - 1;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1658
for (i = v->soc.num_states - 1; i >= start_state; i--) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1705
|| i == v->soc.num_states - 1)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1710
|| i == v->soc.num_states - 1
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1712
&& (!mode_lib->vba.FCLKChangeRequirementFinal || i == v->soc.num_states - 1
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1726
struct vba_vars_st *v = &mode_lib->vba;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1741
start_state = v->soc.num_states - 1;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1825
v->SwathWidthYSingleDPP[k] = mode_lib->vba.ViewportWidth[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1826
v->SwathWidthCSingleDPP[k] = mode_lib->vba.ViewportWidthChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1828
v->SwathWidthYSingleDPP[k] = mode_lib->vba.ViewportHeight[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1829
v->SwathWidthCSingleDPP[k] = mode_lib->vba.ViewportHeightChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1833
v->ReadBandwidthLuma[k] = v->SwathWidthYSingleDPP[k] * dml_ceil(v->BytePerPixelInDETY[k], 1.0)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1835
v->ReadBandwidthChroma[k] = v->SwathWidthYSingleDPP[k] / 2 * dml_ceil(v->BytePerPixelInDETC[k], 2.0)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
184
v->BytePerPixelY,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1841
v->WriteBandwidth[k] = mode_lib->vba.WritebackDestinationWidth[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1846
v->WriteBandwidth[k] = mode_lib->vba.WritebackDestinationWidth[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
185
v->BytePerPixelC,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1851
v->WriteBandwidth[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
186
v->BlockHeight256BytesY,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1860
&& (v->WriteBandwidth[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
187
v->BlockHeight256BytesC,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
188
v->BlockWidth256BytesY,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
189
v->BlockWidth256BytesC,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1916
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MaximumSwathWidthSupportLuma = 8192;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1917
} else if (!IsVertical(mode_lib->vba.SourceRotation[k]) && v->BytePerPixelC[k] > 0
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1919
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MaximumSwathWidthSupportLuma = 7680;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1920
} else if (IsVertical(mode_lib->vba.SourceRotation[k]) && v->BytePerPixelC[k] > 0
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1922
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MaximumSwathWidthSupportLuma = 4320;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1924
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MaximumSwathWidthSupportLuma = 3840;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1925
} else if (IsVertical(mode_lib->vba.SourceRotation[k]) && v->BytePerPixelY[k] == 8 &&
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1927
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MaximumSwathWidthSupportLuma = 3072;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1929
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MaximumSwathWidthSupportLuma = 6144;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1934
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MaximumSwathWidthSupportChroma = v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MaximumSwathWidthSupportLuma / 2.0;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1936
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MaximumSwathWidthSupportChroma = v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MaximumSwathWidthSupportLuma;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1938
v->MaximumSwathWidthInLineBufferLuma = mode_lib->vba.LineBufferSizeFinal
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1941
if (v->BytePerPixelC[k] == 0.0) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1942
v->MaximumSwathWidthInLineBufferChroma = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1944
v->MaximumSwathWidthInLineBufferChroma = mode_lib->vba.LineBufferSizeFinal
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1950
v->MaximumSwathWidthLuma[k] = dml_min(v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MaximumSwathWidthSupportLuma,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1951
v->MaximumSwathWidthInLineBufferLuma);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1952
v->MaximumSwathWidthChroma[k] = dml_min(v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MaximumSwathWidthSupportChroma,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1953
v->MaximumSwathWidthInLineBufferChroma);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
196
v->SwathWidthSingleDPPY, v->SwathWidthSingleDPPC, v->SwathWidthY, v->SwathWidthC,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
197
v->dummy_vars
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
1993
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_odm_mode,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
200
v->dummy_vars
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2002
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[0], /* Integer DPPPerSurface[] */
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2005
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[1], /* Long swath_width_luma_ub[] */
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2006
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[2], /* Long swath_width_chroma_ub[] */
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2007
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_double_array[0], /* Long SwathWidth[] */
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2008
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_double_array[1], /* Long SwathWidthChroma[] */
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2009
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[3], /* Integer SwathHeightY[] */
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2010
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[4], /* Integer SwathHeightC[] */
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2011
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[5], /* Long DETBufferSizeInKByte[] */
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2012
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[6], /* Long DETBufferSizeY[] */
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2013
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[7], /* Long DETBufferSizeC[] */
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2014
&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_boolean_array[0][0], /* bool *UnboundedRequestEnabled */
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2015
&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[0][0], /* Long *CompressedBufferSizeInkByte */
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2016
&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[1][0], /* Long *CompBufReservedSpaceKBytes */
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2019
&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_boolean_array[1][0]); /* bool *ViewportSizeSupport */
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2021
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MPCCombineMethodAsNeededForPStateChangeAndVoltage = false;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2022
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MPCCombineMethodAsPossible = false;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2026
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MPCCombineMethodAsNeededForPStateChangeAndVoltage = true;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2028
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MPCCombineMethodAsPossible = true;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
203
v->swath_width_luma_ub, v->swath_width_chroma_ub);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2030
mode_lib->vba.MPCCombineMethodIncompatible = v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MPCCombineMethodAsNeededForPStateChangeAndVoltage
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2031
&& v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MPCCombineMethodAsPossible;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2033
for (i = start_state; i < v->soc.num_states; i++) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2037
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.ODMModeNoDSC = dm_odm_combine_mode_disabled;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2038
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.ODMModeDSC = dm_odm_combine_mode_disabled;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2048
mode_lib->vba.MaxDispclk[v->soc.num_states - 1],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2059
&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.TotalAvailablePipesSupportNoDSC,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
206
v->ReadBandwidthSurfaceLuma[k] = v->SwathWidthSingleDPPY[k] * v->BytePerPixelY[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2060
&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.NumberOfDPPNoDSC,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2061
&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.ODMModeNoDSC,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2062
&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.RequiredDISPCLKPerSurfaceNoDSC);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2071
mode_lib->vba.MaxDispclk[v->soc.num_states - 1],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
208
v->ReadBandwidthSurfaceChroma[k] = v->SwathWidthSingleDPPC[k] * v->BytePerPixelC[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2082
&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.TotalAvailablePipesSupportDSC,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2083
&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.NumberOfDPPDSC,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2084
&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.ODMModeDSC,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2085
&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.RequiredDISPCLKPerSurfaceDSC);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2103
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.ODMModeNoDSC,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2104
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.ODMModeDSC,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2118
mode_lib->vba.ODMCombineEnablePerState[i][k] = v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.ODMModeNoDSC;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2120
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.RequiredDISPCLKPerSurfaceNoDSC;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2121
if (!v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.TotalAvailablePipesSupportNoDSC)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2124
mode_lib->vba.TotalNumberOfActiveDPP[i][j] + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.NumberOfDPPNoDSC;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2126
mode_lib->vba.ODMCombineEnablePerState[i][k] = v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.ODMModeDSC;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2128
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.RequiredDISPCLKPerSurfaceDSC;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2129
if (!v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.TotalAvailablePipesSupportDSC)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
213
__func__, k, v->ReadBandwidthSurfaceLuma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2132
mode_lib->vba.TotalNumberOfActiveDPP[i][j] + v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.NumberOfDPPDSC;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
215
__func__, k, v->ReadBandwidthSurfaceChroma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2167
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.NoChroma = true;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2177
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.NoChroma = false;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2188
mode_lib->vba.TotalNumberOfActiveDPP[i][j], v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.NoChroma,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2195
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.BWOfNonCombinedSurfaceOfMaximumBandwidth = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2204
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.BWOfNonCombinedSurfaceOfMaximumBandwidth &&
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2210
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.BWOfNonCombinedSurfaceOfMaximumBandwidth =
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2276
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.TotalNumberOfActiveOTG = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2277
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.TotalNumberOfActiveHDMIFRL = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2278
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.TotalNumberOfActiveDP2p0 = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2279
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.TotalNumberOfActiveDP2p0Outputs = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2283
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.TotalNumberOfActiveOTG = v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.TotalNumberOfActiveOTG + 1;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2285
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.TotalNumberOfActiveDP2p0 = v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.TotalNumberOfActiveDP2p0 + 1;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2288
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.TotalNumberOfActiveDP2p0Outputs = v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.TotalNumberOfActiveDP2p0Outputs + 1;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2294
mode_lib->vba.NumberOfOTGSupport = (v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.TotalNumberOfActiveOTG <= mode_lib->vba.MaxNumOTG);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2295
mode_lib->vba.NumberOfHDMIFRLSupport = (v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.TotalNumberOfActiveHDMIFRL <= mode_lib->vba.MaxNumHDMIFRLOutputs);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2296
mode_lib->vba.NumberOfDP2p0Support = (v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.TotalNumberOfActiveDP2p0 <= mode_lib->vba.MaxNumDP2p0Streams
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2297
&& v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.TotalNumberOfActiveDP2p0Outputs <= mode_lib->vba.MaxNumDP2p0Outputs);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2310
for (i = start_state; i < v->soc.num_states; ++i) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
236
v->dummy_vars
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
239
v->ReadBandwidthSurfaceLuma,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
240
v->ReadBandwidthSurfaceChroma,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
241
v->dummy_vars
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2413
for (i = start_state; i < v->soc.num_states; ++i) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2430
for (i = start_state; i < v->soc.num_states; ++i) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
244
v->dummy_vars
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2448
for (i = start_state; i < v->soc.num_states; i++) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2483
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.TotalDSCUnitsRequired = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2485
for (i = start_state; i < v->soc.num_states; ++i) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2488
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.TotalDSCUnitsRequired = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2496
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.TotalDSCUnitsRequired = v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.TotalDSCUnitsRequired + 4;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2503
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.TotalDSCUnitsRequired = v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.TotalDSCUnitsRequired + 2;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2509
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.TotalDSCUnitsRequired = v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.TotalDSCUnitsRequired + 1;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2515
if (v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.TotalDSCUnitsRequired > mode_lib->vba.NumberOfDSC)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2520
for (i = start_state; i < v->soc.num_states; ++i) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2547
for (i = start_state; i < (int) v->soc.num_states; ++i) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
261
v->BlockHeight256BytesY,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2615
&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer[0], /* Long CompBufReservedSpaceKBytes */
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2616
&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_boolean[0], /* bool CompBufReservedSpaceNeedAdjustment */
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2617
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_boolean_array[0],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
262
v->BlockHeight256BytesC,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
263
v->BlockWidth256BytesY,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
264
v->BlockWidth256BytesC,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
267
v->BytePerPixelY,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
268
v->BytePerPixelC,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2685
for (i = start_state; i < v->soc.num_states; i++) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
269
v->BytePerPixelDETY,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
270
v->BytePerPixelDETC,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2717
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].PixelClock = mode_lib->vba.PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2718
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].DPPPerSurface = mode_lib->vba.NoOfDPP[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2719
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].SourceRotation = mode_lib->vba.SourceRotation[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2720
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].ViewportHeight = mode_lib->vba.ViewportHeight[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2721
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].ViewportHeightChroma = mode_lib->vba.ViewportHeightChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2722
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BlockWidth256BytesY = mode_lib->vba.Read256BlockWidthY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2723
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BlockHeight256BytesY = mode_lib->vba.Read256BlockHeightY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2724
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BlockWidth256BytesC = mode_lib->vba.Read256BlockWidthC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2725
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BlockHeight256BytesC = mode_lib->vba.Read256BlockHeightC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2726
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BlockWidthY = mode_lib->vba.MacroTileWidthY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2727
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BlockHeightY = mode_lib->vba.MacroTileHeightY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2728
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BlockWidthC = mode_lib->vba.MacroTileWidthC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2729
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BlockHeightC = mode_lib->vba.MacroTileHeightC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2730
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].InterlaceEnable = mode_lib->vba.Interlace[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2731
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].HTotal = mode_lib->vba.HTotal[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2732
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].DCCEnable = mode_lib->vba.DCCEnable[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2733
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].SourcePixelFormat = mode_lib->vba.SourcePixelFormat[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2734
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].SurfaceTiling = mode_lib->vba.SurfaceTiling[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2735
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BytePerPixelY = mode_lib->vba.BytePerPixelY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2736
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].BytePerPixelC = mode_lib->vba.BytePerPixelC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2737
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].ProgressiveToInterlaceUnitInOPP =
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2739
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].VRatio = mode_lib->vba.VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2740
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].VRatioChroma = mode_lib->vba.VRatioChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2741
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].VTaps = mode_lib->vba.vtaps[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2742
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].VTapsChroma = mode_lib->vba.VTAPsChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2743
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].PitchY = mode_lib->vba.PitchY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2744
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].DCCMetaPitchY = mode_lib->vba.DCCMetaPitchY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2745
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].PitchC = mode_lib->vba.PitchC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2746
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].DCCMetaPitchC = mode_lib->vba.DCCMetaPitchC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2747
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].ViewportStationary = mode_lib->vba.ViewportStationary[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2748
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].ViewportXStart = mode_lib->vba.ViewportXStartY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2749
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].ViewportYStart = mode_lib->vba.ViewportYStartY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2750
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].ViewportXStartC = mode_lib->vba.ViewportXStartC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2751
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].ViewportYStartC = mode_lib->vba.ViewportYStartC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2752
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].FORCE_ONE_ROW_FOR_FRAME = mode_lib->vba.ForceOneRowForFrame[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2753
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].SwathHeightY = mode_lib->vba.SwathHeightYThisState[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2754
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].SwathHeightC = mode_lib->vba.SwathHeightCThisState[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2760
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
277
v->dummy_vars
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2780
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[0],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2781
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[1],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2784
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[2],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2785
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[3],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2786
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[4],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2787
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[5],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2788
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[6],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2789
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[7],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2790
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[8],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2791
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[9],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2794
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[10],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2796
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[11],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2797
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[12],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2798
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[13],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2799
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[14],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
280
v->dummy_vars
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2800
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[15],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2801
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[16],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2802
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[17],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2803
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[18],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2804
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[19],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2805
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[20],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2819
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_boolean_array[0], // Boolean UsesMALLForStaticScreen[]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2820
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_boolean_array[1], // Boolean PTE_BUFFER_MODE[]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2821
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer_array[21]); // Long BIGK_FRAGMENT_SIZE[]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
283
v->dummy_vars
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
286
v->dummy_vars
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2912
for (i = start_state; i < (int) v->soc.num_states; ++i) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
294
&v->UnboundedRequestEnabled,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
295
&v->CompressedBufferSizeInkByte,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
296
&v->CompBufReservedSpaceKBytes,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
297
&v->dummy_vars
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2982
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.ReorderingBytes = mode_lib->vba.NumberOfChannels
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
2991
for (i = start_state; i < (int) v->soc.num_states; ++i) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
300
v->dummy_vars
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
303
&v->dummy_vars
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3038
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.FullFrameMALLPStateMethod = false;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3039
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SubViewportMALLPStateMethod = false;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3040
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.PhantomPipeMALLPStateMethod = false;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3044
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.FullFrameMALLPStateMethod = true;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3046
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SubViewportMALLPStateMethod = true;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3048
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.PhantomPipeMALLPStateMethod = true;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3050
mode_lib->vba.InvalidCombinationOfMALLUseForPState = (v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SubViewportMALLPStateMethod
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3051
!= v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.PhantomPipeMALLPStateMethod) || (v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SubViewportMALLPStateMethod && v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.FullFrameMALLPStateMethod);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3065
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.ReorderingBytes,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
308
v->CompBufReservedSpaceZs = v->CompBufReservedSpaceKBytes * 1024.0 / 256.0;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
309
v->CompBufReservedSpace64B = v->CompBufReservedSpaceKBytes * 1024.0 / 64.0;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3113
for (i = start_state; i < (int) v->soc.num_states; ++i) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3122
for (i = start_state; i < (int) v->soc.num_states; ++i) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3128
+ v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.ReorderingBytes / mode_lib->vba.ReturnBWPerState[i][j]) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3137
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MaxTotalVActiveRDBandwidth = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
314
v->BytePerPixelY,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3140
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MaxTotalVActiveRDBandwidth += mode_lib->vba.ReadBandwidthLuma[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3144
for (i = start_state; i < (int) v->soc.num_states; ++i) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
315
v->BytePerPixelC,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3157
if (v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.MaxTotalVActiveRDBandwidth
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3168
for (i = start_state; i < (int) v->soc.num_states; ++i) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
318
v->SwathWidthY,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
319
v->SwathWidthC,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3229
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.VMDataOnlyReturnBWPerState = dml32_get_return_bw_mbps_vm_only(&mode_lib->vba.soc, i,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3232
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.HostVMInefficiencyFactor = 1;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3235
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.HostVMInefficiencyFactor = mode_lib->vba.ReturnBWPerState[i][j]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3236
/ v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.VMDataOnlyReturnBWPerState;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3239
mode_lib->vba.RoundTripPingLatencyCycles, v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.ReorderingBytes,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
324
v->PSCL_THROUGHPUT_LUMA,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3246
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.HostVMInefficiencyFactor, mode_lib->vba.HostVMMinPageSize,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3249
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.NextPrefetchModeState = mode_lib->vba.MinPrefetchMode;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
325
v->PSCL_THROUGHPUT_CHROMA,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3254
mode_lib->vba.PrefetchModePerState[i][j] = v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.NextPrefetchModeState;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3267
memset(&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull, 0, sizeof(DmlPipe));
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3268
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.myPipe.Dppclk = mode_lib->vba.RequiredDPPCLK[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3269
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.myPipe.Dispclk = mode_lib->vba.RequiredDISPCLK[i][j];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
327
v->ReadBandwidthSurfaceLuma,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3270
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.myPipe.PixelClock = mode_lib->vba.PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3271
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.myPipe.DCFClkDeepSleep = mode_lib->vba.ProjectedDCFCLKDeepSleep[i][j];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3272
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.myPipe.DPPPerSurface = mode_lib->vba.NoOfDPP[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3273
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.myPipe.ScalerEnabled = mode_lib->vba.ScalerEnabled[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3274
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.myPipe.SourceRotation = mode_lib->vba.SourceRotation[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3275
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.myPipe.BlockWidth256BytesY = mode_lib->vba.Read256BlockWidthY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3276
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.myPipe.BlockHeight256BytesY = mode_lib->vba.Read256BlockHeightY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3277
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.myPipe.BlockWidth256BytesC = mode_lib->vba.Read256BlockWidthC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3278
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.myPipe.BlockHeight256BytesC = mode_lib->vba.Read256BlockHeightC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3279
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.myPipe.InterlaceEnable = mode_lib->vba.Interlace[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
328
v->ReadBandwidthSurfaceChroma,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3280
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.myPipe.NumberOfCursors = mode_lib->vba.NumberOfCursors[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3281
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.myPipe.VBlank = mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3282
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.myPipe.HTotal = mode_lib->vba.HTotal[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3283
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.myPipe.HActive = mode_lib->vba.HActive[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3284
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.myPipe.DCCEnable = mode_lib->vba.DCCEnable[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3285
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.myPipe.ODMMode = mode_lib->vba.ODMCombineEnablePerState[i][k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3286
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.myPipe.SourcePixelFormat = mode_lib->vba.SourcePixelFormat[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3287
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.myPipe.BytePerPixelY = mode_lib->vba.BytePerPixelY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3288
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.myPipe.BytePerPixelC = mode_lib->vba.BytePerPixelC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3289
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.myPipe.ProgressiveToInterlaceUnitInOPP =
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3294
v,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3296
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.HostVMInefficiencyFactor,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3297
&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.myPipe,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3298
v->DSCDelayPerState[i][k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3299
v->SwathWidthYThisState[k] / v->HRatio[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3300
dml_min(v->MaxVStartup, v->MaximumVStartup[i][j][k]),
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3301
v->MaximumVStartup[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3302
v->UrgLatency[i],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3303
v->ExtraLatency,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3304
v->TimeCalc,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3305
v->PDEAndMetaPTEBytesPerFrame[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3306
v->MetaRowBytes[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3307
v->DPTEBytesPerRow[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3308
v->PrefetchLinesY[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3309
v->SwathWidthYThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3310
v->PrefillY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3311
v->MaxNumSwY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3312
v->PrefetchLinesC[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3313
v->SwathWidthCThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3314
v->PrefillC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3315
v->MaxNumSwC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3316
v->swath_width_luma_ub_this_state[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3317
v->swath_width_chroma_ub_this_state[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3318
v->SwathHeightYThisState[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3319
v->SwathHeightCThisState[k], v->TWait,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
332
&v->DCFCLKDeepSleep);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3320
(v->DRAMSpeedPerState[i] <= MEM_STROBE_FREQ_MHZ || v->DCFCLKState[i][j] <= DCFCLK_FREQ_EXTRA_PREFETCH_REQ_MHZ) ?
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3325
&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.DSTXAfterScaler[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3326
&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.DSTYAfterScaler[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3327
&v->LineTimesForPrefetch[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3328
&v->PrefetchBW[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3329
&v->LinesForMetaPTE[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3330
&v->LinesForMetaAndDPTERow[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3331
&v->VRatioPreY[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3332
&v->VRatioPreC[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3333
&v->RequiredPrefetchPixelDataBWLuma[0][0][k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3334
&v->RequiredPrefetchPixelDataBWChroma[0][0][k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3335
&v->NoTimeForDynamicMetadata[i][j][k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3336
&v->Tno_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3337
&v->prefetch_vmrow_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3338
&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_single[0], // double *Tdmdl_vm
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3339
&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_single[1], // double *Tdmdl
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3340
&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_single[2], // double *TSetup
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3341
&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer[0], // unsigned int *VUpdateOffsetPix
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3342
&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_single[3], // unsigned int *VUpdateWidthPix
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3343
&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_single[4]); // unsigned int *VReadyOffsetPix
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3368
v->cursor_bw_pre[k] = mode_lib->vba.NumberOfCursors[k] * mode_lib->vba.CursorWidth[k][0] * mode_lib->vba.CursorBPP[k][0] /
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3369
8.0 / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * v->VRatioPreY[i][j][k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
337
v->DSCCLK_calculated[k] = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3393
v->PrefetchBW,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3394
v->VRatio,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3395
v->MaxVRatioPre,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3398
&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_single[0], // Single *PrefetchBandwidth
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3399
&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_single[1], // Single *FractionOfUrgentBandwidth
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3476
dml32_CalculateFlipSchedule(v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.HostVMInefficiencyFactor,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
348
v->DSCCLK_calculated[k] = mode_lib->vba.PixelClockBackEnd[k] / 12
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
352
v->DSCCLK_calculated[k] = mode_lib->vba.PixelClockBackEnd[k] / 6
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3531
&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_single[0], // Single *TotalBandwidth
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3532
&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_single[1], // Single *FractionOfUrgentBandwidth
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3550
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.NextPrefetchModeState = v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.NextPrefetchModeState + 1;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
356
v->DSCCLK_calculated[k] = mode_lib->vba.PixelClockBackEnd[k] / 3
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3564
&& v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.NextPrefetchModeState > mode_lib->vba.MaxPrefetchMode)));
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3572
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.mSOCParameters.UrgentLatency = mode_lib->vba.UrgLatency[i];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3573
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.mSOCParameters.ExtraLatency = mode_lib->vba.ExtraLatency;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3574
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.mSOCParameters.WritebackLatency = mode_lib->vba.WritebackLatency;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3575
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.mSOCParameters.DRAMClockChangeLatency = mode_lib->vba.DRAMClockChangeLatency;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3576
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.mSOCParameters.FCLKChangeLatency = mode_lib->vba.FCLKChangeLatency;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3577
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.mSOCParameters.SRExitTime = mode_lib->vba.SRExitTime;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3578
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.mSOCParameters.SREnterPlusExitTime = mode_lib->vba.SREnterPlusExitTime;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3579
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.mSOCParameters.SRExitZ8Time = mode_lib->vba.SRExitZ8Time;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3580
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.mSOCParameters.SREnterPlusExitZ8Time = mode_lib->vba.SREnterPlusExitZ8Time;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3581
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.mSOCParameters.USRRetrainingLatency = mode_lib->vba.USRRetrainingLatency;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3582
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.mSOCParameters.SMNLatency = mode_lib->vba.SMNLatency;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3586
v,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3587
v->PrefetchModePerState[i][j],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3588
v->DCFCLKState[i][j],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3589
v->ReturnBWPerState[i][j],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3590
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.mSOCParameters,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3591
v->SOCCLKPerState[i],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3592
v->ProjectedDCFCLKDeepSleep[i][j],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3593
v->DETBufferSizeYThisState,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3594
v->DETBufferSizeCThisState,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3595
v->SwathHeightYThisState,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3596
v->SwathHeightCThisState,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3597
v->SwathWidthYThisState, // 24
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3598
v->SwathWidthCThisState,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3599
v->NoOfDPPThisState,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3600
v->BytePerPixelInDETY,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3601
v->BytePerPixelInDETC,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3602
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.DSTXAfterScaler,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3603
v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.DSTYAfterScaler,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3604
v->UnboundedRequestEnabledThisState,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3605
v->CompressedBufferSizeInkByteThisState,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3608
&v->DRAMClockChangeSupport[i][j],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3609
&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_single2[0], // double *MaxActiveDRAMClockChangeLatencySupported
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3610
&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_integer[0], // Long SubViewportLinesNeededInMALL[]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3611
&v->FCLKChangeSupport[i][j],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3612
&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_single2[1], // double *MinActiveFCLKChangeLatencySupported
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
364
v->DSCDelay[k] = dml32_DSCDelayRequirement(mode_lib->vba.DSCEnabled[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3689
mode_support_configuration(v, mode_lib);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3693
for (i = v->soc.num_states; i >= start_state; i--) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
3694
if (i == v->soc.num_states || mode_lib->vba.ModeSupport[i][0] == true ||
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
376
v->DSCDelay[k] = v->DSCDelay[j];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
380
v->ImmediateFlipSupportedSurface[k] = mode_lib->vba.ImmediateFlipSupport
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
398
v->BytePerPixelY,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
401
v->BytePerPixelC,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
406
v->BlockWidth256BytesY,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
407
v->BlockWidth256BytesC,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
408
v->BlockHeight256BytesY,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
409
v->BlockHeight256BytesC,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
410
v->BlockWidthY,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
411
v->BlockWidthC,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
412
v->BlockHeightY,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
413
v->BlockHeightC,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
418
v->SurfaceSizeInMALL,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
419
&v->dummy_vars.
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
424
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].PixelClock = mode_lib->vba.PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
425
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].DPPPerSurface = mode_lib->vba.DPPPerPlane[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
426
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].SourceRotation = mode_lib->vba.SourceRotation[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
427
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].ViewportHeight = mode_lib->vba.ViewportHeight[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
428
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].ViewportHeightChroma = mode_lib->vba.ViewportHeightChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
429
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].BlockWidth256BytesY = v->BlockWidth256BytesY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
430
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].BlockHeight256BytesY = v->BlockHeight256BytesY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
431
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].BlockWidth256BytesC = v->BlockWidth256BytesC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
432
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].BlockHeight256BytesC = v->BlockHeight256BytesC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
433
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].BlockWidthY = v->BlockWidthY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
434
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].BlockHeightY = v->BlockHeightY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
435
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].BlockWidthC = v->BlockWidthC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
436
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].BlockHeightC = v->BlockHeightC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
437
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].InterlaceEnable = mode_lib->vba.Interlace[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
438
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].HTotal = mode_lib->vba.HTotal[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
439
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].DCCEnable = mode_lib->vba.DCCEnable[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
440
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].SourcePixelFormat = mode_lib->vba.SourcePixelFormat[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
441
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].SurfaceTiling = mode_lib->vba.SurfaceTiling[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
442
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].BytePerPixelY = v->BytePerPixelY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
443
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].BytePerPixelC = v->BytePerPixelC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
444
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].ProgressiveToInterlaceUnitInOPP = mode_lib->vba.ProgressiveToInterlaceUnitInOPP;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
445
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].VRatio = mode_lib->vba.VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
446
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].VRatioChroma = mode_lib->vba.VRatioChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
447
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].VTaps = mode_lib->vba.vtaps[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
448
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].VTapsChroma = mode_lib->vba.VTAPsChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
449
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].PitchY = mode_lib->vba.PitchY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
450
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].DCCMetaPitchY = mode_lib->vba.DCCMetaPitchY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
451
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].PitchC = mode_lib->vba.PitchC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
452
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].DCCMetaPitchC = mode_lib->vba.DCCMetaPitchC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
453
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].ViewportStationary = mode_lib->vba.ViewportStationary[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
454
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].ViewportXStart = mode_lib->vba.ViewportXStartY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
455
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].ViewportYStart = mode_lib->vba.ViewportYStartY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
456
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].ViewportXStartC = mode_lib->vba.ViewportXStartC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
457
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].ViewportYStartC = mode_lib->vba.ViewportYStartC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
458
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].FORCE_ONE_ROW_FOR_FRAME = mode_lib->vba.ForceOneRowForFrame[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
459
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].SwathHeightY = mode_lib->vba.SwathHeightY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
460
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].SwathHeightC = mode_lib->vba.SwathHeightC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
467
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
468
v->SurfaceSizeInMALL,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
475
v->SwathWidthY,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
476
v->SwathWidthC,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
485
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.dummy_boolean_array2[0], // Boolean PTEBufferSizeNotExceeded[]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
486
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.dummy_boolean_array2[1], // Boolean DCCMetaBufferSizeNotExceeded[]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
487
v->dpte_row_width_luma_ub,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
488
v->dpte_row_width_chroma_ub,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
489
v->dpte_row_height,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
490
v->dpte_row_height_chroma,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
491
v->dpte_row_height_linear,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
492
v->dpte_row_height_linear_chroma,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
493
v->meta_req_width,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
494
v->meta_req_width_chroma,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
495
v->meta_req_height,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
496
v->meta_req_height_chroma,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
497
v->meta_row_width,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
498
v->meta_row_width_chroma,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
499
v->meta_row_height,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
500
v->meta_row_height_chroma,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
501
v->vm_group_bytes,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
502
v->dpte_group_bytes,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
503
v->PixelPTEReqWidthY,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
504
v->PixelPTEReqHeightY,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
505
v->PTERequestSizeY,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
506
v->PixelPTEReqWidthC,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
507
v->PixelPTEReqHeightC,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
508
v->PTERequestSizeC,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
509
v->dpde0_bytes_per_frame_ub_l,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
510
v->meta_pte_bytes_per_frame_ub_l,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
511
v->dpde0_bytes_per_frame_ub_c,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
512
v->meta_pte_bytes_per_frame_ub_c,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
513
v->PrefetchSourceLinesY,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
514
v->PrefetchSourceLinesC,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
515
v->VInitPreFillY, v->VInitPreFillC,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
516
v->MaxNumSwathY,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
517
v->MaxNumSwathC,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
518
v->meta_row_bw,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
519
v->dpte_row_bw,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
520
v->PixelPTEBytesPerRow,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
521
v->PDEAndMetaPTEBytesFrame,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
522
v->MetaRowByte,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
523
v->Use_One_Row_For_Frame,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
524
v->Use_One_Row_For_Frame_Flip,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
525
v->UsesMALLForStaticScreen,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
526
v->PTE_BUFFER_MODE,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
527
v->BIGK_FRAGMENT_SIZE);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
531
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.ReorderBytes = mode_lib->vba.NumberOfChannels
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
536
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.VMDataOnlyReturnBW = dml32_get_return_bw_mbps_vm_only(
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
560
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.HostVMInefficiencyFactor = 1.0;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
563
v->dummy_vars
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
566
mode_lib->vba.ReturnBW / v->dummy_vars
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
579
v->UrgentExtraLatency = dml32_CalculateExtraLatency(
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
581
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.ReorderBytes,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
592
v->dpte_group_bytes,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
593
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.HostVMInefficiencyFactor,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
597
mode_lib->vba.TCalc = 24.0 / v->DCFCLKDeepSleep;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
602
v->WritebackDelay[mode_lib->vba.VoltageLevel][k] = mode_lib->vba.WritebackLatency
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
61
struct vba_vars_st *v = &mode_lib->vba;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
613
v->WritebackDelay[mode_lib->vba.VoltageLevel][k] = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
617
v->WritebackDelay[mode_lib->vba.VoltageLevel][k] =
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
618
dml_max(v->WritebackDelay[mode_lib->vba.VoltageLevel][k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
637
v->WritebackDelay[mode_lib->vba.VoltageLevel][k] =
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
638
v->WritebackDelay[mode_lib->vba.VoltageLevel][j];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
640
v->UrgentLatency = dml32_CalculateUrgentLatency(mode_lib->vba.UrgentLatencyPixelDataOnly,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
650
v->swath_width_luma_ub[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
651
v->swath_width_chroma_ub[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
655
v->UrgentLatency,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
661
v->BytePerPixelDETY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
662
v->BytePerPixelDETC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
667
&v->UrgBurstFactorCursor[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
668
&v->UrgBurstFactorLuma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
669
&v->UrgBurstFactorChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
670
&v->NoUrgentLatencyHiding[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
672
v->cursor_bw[k] = mode_lib->vba.NumberOfCursors[k] * mode_lib->vba.CursorWidth[k][0] * mode_lib->vba.CursorBPP[k][0] / 8 / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * mode_lib->vba.VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
675
v->NotEnoughDETSwathFillLatencyHiding = dml32_CalculateDETSwathFillLatencyHiding(
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
678
v->UrgentLatency,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
681
v->swath_width_luma_ub,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
682
v->swath_width_chroma_ub,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
683
v->BytePerPixelDETY,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
684
v->BytePerPixelDETC,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
696
v->MaxVStartupLines[k] = ((mode_lib->vba.Interlace[k] &&
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
700
dml_ceil((double) v->WritebackDelay[mode_lib->vba.VoltageLevel][k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
704
if (v->MaxVStartupLines[k] > 1023)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
705
v->MaxVStartupLines[k] = 1023;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
708
dml_print("DML::%s: k=%d MaxVStartupLines = %d\n", __func__, k, v->MaxVStartupLines[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
711
k, v->WritebackDelay[mode_lib->vba.VoltageLevel][k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
715
v->MaximumMaxVStartupLines = 0;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
717
v->MaximumMaxVStartupLines = dml_max(v->MaximumMaxVStartupLines, v->MaxVStartupLines[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
735
v->VStartupLines = __DML_VBA_MIN_VSTARTUP__;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
758
mode_lib->vba.FCLKChangeLatency, v->UrgentLatency,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
761
memset(&v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.myPipe, 0, sizeof(DmlPipe));
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
763
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.myPipe.Dppclk = mode_lib->vba.DPPCLK[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
764
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.myPipe.Dispclk = mode_lib->vba.DISPCLK;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
765
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.myPipe.PixelClock = mode_lib->vba.PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
766
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.myPipe.DCFClkDeepSleep = v->DCFCLKDeepSleep;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
767
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.myPipe.DPPPerSurface = mode_lib->vba.DPPPerPlane[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
768
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.myPipe.ScalerEnabled = mode_lib->vba.ScalerEnabled[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
769
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.myPipe.SourceRotation = mode_lib->vba.SourceRotation[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
770
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.myPipe.BlockWidth256BytesY = v->BlockWidth256BytesY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
771
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.myPipe.BlockHeight256BytesY = v->BlockHeight256BytesY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
772
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.myPipe.BlockWidth256BytesC = v->BlockWidth256BytesC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
773
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.myPipe.BlockHeight256BytesC = v->BlockHeight256BytesC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
774
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.myPipe.InterlaceEnable = mode_lib->vba.Interlace[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
775
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.myPipe.NumberOfCursors = mode_lib->vba.NumberOfCursors[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
776
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.myPipe.VBlank = mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
777
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.myPipe.HTotal = mode_lib->vba.HTotal[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
778
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.myPipe.HActive = mode_lib->vba.HActive[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
779
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.myPipe.DCCEnable = mode_lib->vba.DCCEnable[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
780
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.myPipe.ODMMode = mode_lib->vba.ODMCombineEnabled[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
781
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.myPipe.SourcePixelFormat = mode_lib->vba.SourcePixelFormat[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
782
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.myPipe.BytePerPixelY = v->BytePerPixelY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
783
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.myPipe.BytePerPixelC = v->BytePerPixelC[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
784
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.myPipe.ProgressiveToInterlaceUnitInOPP = mode_lib->vba.ProgressiveToInterlaceUnitInOPP;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
785
v->ErrorResult[k] = dml32_CalculatePrefetchSchedule(
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
786
v,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
788
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.HostVMInefficiencyFactor,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
789
&v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.myPipe,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
790
v->DSCDelay[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
791
(unsigned int) (v->SwathWidthY[k] / v->HRatio[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
792
dml_min(v->VStartupLines, v->MaxVStartupLines[k]),
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
793
v->MaxVStartupLines[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
794
v->UrgentLatency,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
795
v->UrgentExtraLatency,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
796
v->TCalc,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
797
v->PDEAndMetaPTEBytesFrame[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
798
v->MetaRowByte[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
799
v->PixelPTEBytesPerRow[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
800
v->PrefetchSourceLinesY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
801
v->SwathWidthY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
802
v->VInitPreFillY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
803
v->MaxNumSwathY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
804
v->PrefetchSourceLinesC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
805
v->SwathWidthC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
806
v->VInitPreFillC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
807
v->MaxNumSwathC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
808
v->swath_width_luma_ub[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
809
v->swath_width_chroma_ub[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
81
v->WritebackDISPCLK = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
810
v->SwathHeightY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
811
v->SwathHeightC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
813
(v->DRAMSpeedPerState[mode_lib->vba.VoltageLevel] <= MEM_STROBE_FREQ_MHZ ||
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
814
v->DCFCLKPerState[mode_lib->vba.VoltageLevel] <= DCFCLK_FREQ_EXTRA_PREFETCH_REQ_MHZ) ?
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
819
&v->DSTXAfterScaler[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
82
v->GlobalDPPCLK = 0.0;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
820
&v->DSTYAfterScaler[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
821
&v->DestinationLinesForPrefetch[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
822
&v->PrefetchBandwidth[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
823
&v->DestinationLinesToRequestVMInVBlank[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
824
&v->DestinationLinesToRequestRowInVBlank[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
825
&v->VRatioPrefetchY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
826
&v->VRatioPrefetchC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
827
&v->RequiredPrefetchPixDataBWLuma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
828
&v->RequiredPrefetchPixDataBWChroma[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
829
&v->NotEnoughTimeForDynamicMetadata[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
830
&v->Tno_bw[k], &v->prefetch_vmrow_bw[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
831
&v->Tdmdl_vm[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
832
&v->Tdmdl[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
833
&v->TSetup[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
834
&v->VUpdateOffsetPix[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
835
&v->VUpdateWidthPix[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
836
&v->VReadyOffsetPix[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
842
v->VStartup[k] = dml_min(v->VStartupLines, v->MaxVStartupLines[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
847
v->swath_width_luma_ub[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
848
v->swath_width_chroma_ub[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
852
v->UrgentLatency,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
856
v->VRatioPrefetchY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
857
v->VRatioPrefetchC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
858
v->BytePerPixelDETY[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
859
v->BytePerPixelDETC[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
863
&v->UrgBurstFactorCursorPre[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
864
&v->UrgBurstFactorLumaPre[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
865
&v->UrgBurstFactorChromaPre[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
866
&v->NoUrgentLatencyHidingPre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
868
v->cursor_bw_pre[k] = mode_lib->vba.NumberOfCursors[k] * mode_lib->vba.CursorWidth[k][0] * mode_lib->vba.CursorBPP[k][0] /
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
869
8.0 / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * v->VRatioPrefetchY[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
87
v->WritebackDISPCLK = dml_max(v->WritebackDISPCLK,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
873
dml_print("DML::%s: k=%0d UrgBurstFactorLuma=%f\n", __func__, k, v->UrgBurstFactorLuma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
874
dml_print("DML::%s: k=%0d UrgBurstFactorChroma=%f\n", __func__, k, v->UrgBurstFactorChroma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
876
v->UrgBurstFactorLumaPre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
878
v->UrgBurstFactorChromaPre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
880
dml_print("DML::%s: k=%0d VRatioPrefetchY=%f\n", __func__, k, v->VRatioPrefetchY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
883
dml_print("DML::%s: k=%0d prefetch_vmrow_bw=%f\n", __func__, k, v->prefetch_vmrow_bw[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
885
v->ReadBandwidthSurfaceLuma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
887
v->ReadBandwidthSurfaceChroma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
888
dml_print("DML::%s: k=%0d cursor_bw=%f\n", __func__, k, v->cursor_bw[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
889
dml_print("DML::%s: k=%0d meta_row_bw=%f\n", __func__, k, v->meta_row_bw[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
890
dml_print("DML::%s: k=%0d dpte_row_bw=%f\n", __func__, k, v->dpte_row_bw[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
892
v->RequiredPrefetchPixDataBWLuma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
894
v->RequiredPrefetchPixDataBWChroma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
895
dml_print("DML::%s: k=%0d cursor_bw_pre=%f\n", __func__, k, v->cursor_bw_pre[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
899
if (v->DestinationLinesForPrefetch[k] < 2)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
902
if (v->VRatioPrefetchY[k] > v->MaxVRatioPre
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
903
|| v->VRatioPrefetchC[k] > v->MaxVRatioPre)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
917
v->FractionOfUrgentBandwidth = MaxTotalRDBandwidthNoUrgentBurst / mode_lib->vba.ReturnBW;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
931
v->NoUrgentLatencyHidingPre,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
932
v->ReadBandwidthSurfaceLuma,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
933
v->ReadBandwidthSurfaceChroma,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
934
v->RequiredPrefetchPixDataBWLuma,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
935
v->RequiredPrefetchPixDataBWChroma,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
936
v->cursor_bw,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
937
v->meta_row_bw,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
938
v->dpte_row_bw,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
939
v->cursor_bw_pre,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
940
v->prefetch_vmrow_bw,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
942
v->UrgBurstFactorLuma,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
943
v->UrgBurstFactorChroma,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
944
v->UrgBurstFactorCursor,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
945
v->UrgBurstFactorLumaPre,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
946
v->UrgBurstFactorChromaPre,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
947
v->UrgBurstFactorCursorPre,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
948
v->PrefetchBandwidth,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
949
v->VRatio,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
950
v->MaxVRatioPre,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
954
&v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.dummy_single[0],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
955
&v->PrefetchModeSupported);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
959
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.dummy_unit_vector[k] = 1.0;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
964
v->NoUrgentLatencyHidingPre,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
965
v->ReadBandwidthSurfaceLuma,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
966
v->ReadBandwidthSurfaceChroma,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
967
v->RequiredPrefetchPixDataBWLuma,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
968
v->RequiredPrefetchPixDataBWChroma,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
969
v->cursor_bw,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
970
v->meta_row_bw,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
971
v->dpte_row_bw,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
972
v->cursor_bw_pre,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
973
v->prefetch_vmrow_bw,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
975
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.dummy_unit_vector,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
976
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.dummy_unit_vector,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
977
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.dummy_unit_vector,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
978
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.dummy_unit_vector,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
979
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.dummy_unit_vector,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
980
v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.dummy_unit_vector,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
981
v->PrefetchBandwidth,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
982
v->VRatio,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
983
v->MaxVRatioPre,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
986
&v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.dummy_single[0],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
987
&v->FractionOfUrgentBandwidth,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
988
&v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.dummy_boolean);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
992
v->PrefetchModeSupported = false;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
996
if (v->ErrorResult[k] == true || v->NotEnoughTimeForDynamicMetadata[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
997
v->PrefetchModeSupported = false;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3400
struct vba_vars_st *v,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3450
double DPPCLKDelaySubtotalPlusCNVCFormater = v->DPPCLKDelaySubtotal + v->DPPCLKDelayCNVCFormater;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3483
unsigned int max_vratio_pre = v->MaxVRatioPre;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3488
if (v->GPUVMEnable == true && v->HostVMEnable == true)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3489
HostVMDynamicLevelsTrips = v->HostVMMaxNonCachedPageTableLevels;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3493
dml_print("DML::%s: v->GPUVMEnable = %d\n", __func__, v->GPUVMEnable);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3494
dml_print("DML::%s: v->GPUVMMaxPageTableLevels = %d\n", __func__, v->GPUVMMaxPageTableLevels);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3497
__func__, v->HostVMEnable, HostVMInefficiencyFactor);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3500
v->MaxInterDCNTileRepeaters,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3507
v->DynamicMetadataTransmittedBytes[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3508
v->DynamicMetadataLinesBeforeActiveRequired[k],
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3523
Tvm_trips = UrgentExtraLatency + trip_to_mem * (v->GPUVMMaxPageTableLevels * (HostVMDynamicLevelsTrips + 1) - 1);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3525
if (v->DynamicMetadataVMEnabled == true)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3531
if (v->DynamicMetadataEnable[k] == false)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3535
if (v->DynamicMetadataEnable[k] == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3555
*Tdmdl_vm = (v->DynamicMetadataEnable[k] == true && v->DynamicMetadataVMEnabled == true &&
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3556
v->GPUVMEnable == true ? TWait + Tvm_trips : 0);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3559
DPPCycles = DPPCLKDelaySubtotalPlusCNVCFormater + v->DPPCLKDelaySCL;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3561
DPPCycles = DPPCLKDelaySubtotalPlusCNVCFormater + v->DPPCLKDelaySCLLBOnly;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3563
DPPCycles = DPPCycles + myPipe->NumberOfCursors * v->DPPCLKDelayCNVCCursor;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3565
DISPCLKCycles = v->DISPCLKDelaySubtotal;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3591
if (v->OutputFormat[k] == dm_420 || (myPipe->InterlaceEnable && myPipe->ProgressiveToInterlaceUnitInOPP))
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3608
if (v->GPUVMEnable == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3611
if (v->GPUVMMaxPageTableLevels >= 3) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3613
(double) ((v->GPUVMMaxPageTableLevels - 2) * (HostVMDynamicLevelsTrips + 1) - 1);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3614
} else if (v->GPUVMMaxPageTableLevels == 1 && myPipe->DCCEnable != true) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3649
if (v->GPUVMEnable == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3657
if ((v->GPUVMEnable == true || myPipe->DCCEnable == true)) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3862
if (v->GPUVMEnable == true) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
3870
if ((v->GPUVMEnable == true || myPipe->DCCEnable == true)) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4260
struct vba_vars_st *v,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4323
v->Watermark.UrgentWatermark = mmSOCParameters.UrgentLatency + mmSOCParameters.ExtraLatency;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4324
v->Watermark.USRRetrainingWatermark = mmSOCParameters.UrgentLatency + mmSOCParameters.ExtraLatency
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4326
v->Watermark.DRAMClockChangeWatermark = mmSOCParameters.DRAMClockChangeLatency + v->Watermark.UrgentWatermark;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4327
v->Watermark.FCLKChangeWatermark = mmSOCParameters.FCLKChangeLatency + v->Watermark.UrgentWatermark;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4328
v->Watermark.StutterExitWatermark = mmSOCParameters.SRExitTime + mmSOCParameters.ExtraLatency
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4330
v->Watermark.StutterEnterPlusExitWatermark = mmSOCParameters.SREnterPlusExitTime + mmSOCParameters.ExtraLatency
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4332
v->Watermark.Z8StutterExitWatermark = mmSOCParameters.SRExitZ8Time + mmSOCParameters.ExtraLatency
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4334
v->Watermark.Z8StutterEnterPlusExitWatermark = mmSOCParameters.SREnterPlusExitZ8Time
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4341
dml_print("DML::%s: UrgentWatermark = %f\n", __func__, v->Watermark.UrgentWatermark);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4342
dml_print("DML::%s: USRRetrainingWatermark = %f\n", __func__, v->Watermark.USRRetrainingWatermark);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4343
dml_print("DML::%s: DRAMClockChangeWatermark = %f\n", __func__, v->Watermark.DRAMClockChangeWatermark);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4344
dml_print("DML::%s: FCLKChangeWatermark = %f\n", __func__, v->Watermark.FCLKChangeWatermark);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4345
dml_print("DML::%s: StutterExitWatermark = %f\n", __func__, v->Watermark.StutterExitWatermark);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4346
dml_print("DML::%s: StutterEnterPlusExitWatermark = %f\n", __func__, v->Watermark.StutterEnterPlusExitWatermark);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4347
dml_print("DML::%s: Z8StutterExitWatermark = %f\n", __func__, v->Watermark.Z8StutterExitWatermark);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4349
__func__, v->Watermark.Z8StutterEnterPlusExitWatermark);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4354
for (k = 0; k < v->NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4355
if (v->WritebackEnable[k] == true)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4360
v->Watermark.WritebackUrgentWatermark = mmSOCParameters.WritebackLatency;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4362
v->Watermark.WritebackUrgentWatermark = mmSOCParameters.WritebackLatency
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4363
+ v->WritebackChunkSize * 1024.0 / 32.0 / SOCCLK;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4365
if (v->USRRetrainingRequiredFinal)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4366
v->Watermark.WritebackDRAMClockChangeWatermark = v->Watermark.WritebackDRAMClockChangeWatermark
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4370
v->Watermark.WritebackDRAMClockChangeWatermark = mmSOCParameters.DRAMClockChangeLatency
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4372
v->Watermark.WritebackFCLKChangeWatermark = mmSOCParameters.FCLKChangeLatency
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4375
v->Watermark.WritebackDRAMClockChangeWatermark = mmSOCParameters.DRAMClockChangeLatency
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4376
+ mmSOCParameters.WritebackLatency + v->WritebackChunkSize * 1024.0 / 32.0 / SOCCLK;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4377
v->Watermark.WritebackFCLKChangeWatermark = mmSOCParameters.FCLKChangeLatency
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4378
+ mmSOCParameters.WritebackLatency + v->WritebackChunkSize * 1024 / 32 / SOCCLK;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4381
if (v->USRRetrainingRequiredFinal)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4382
v->Watermark.WritebackDRAMClockChangeWatermark = v->Watermark.WritebackDRAMClockChangeWatermark
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4385
if (v->USRRetrainingRequiredFinal)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4386
v->Watermark.WritebackFCLKChangeWatermark = v->Watermark.WritebackFCLKChangeWatermark
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4391
__func__, v->Watermark.WritebackDRAMClockChangeWatermark);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4392
dml_print("DML::%s: WritebackFCLKChangeWatermark = %f\n", __func__, v->Watermark.WritebackFCLKChangeWatermark);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4393
dml_print("DML::%s: WritebackUrgentWatermark = %f\n", __func__, v->Watermark.WritebackUrgentWatermark);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4394
dml_print("DML::%s: v->USRRetrainingRequiredFinal = %d\n", __func__, v->USRRetrainingRequiredFinal);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4398
for (k = 0; k < v->NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4399
TotalPixelBW = TotalPixelBW + DPPPerSurface[k] * (SwathWidthY[k] * BytePerPixelDETY[k] * v->VRatio[k] +
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4400
SwathWidthC[k] * BytePerPixelDETC[k] * v->VRatioChroma[k]) / (v->HTotal[k] / v->PixelClock[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4403
for (k = 0; k < v->NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4405
LBLatencyHidingSourceLinesY[k] = dml_min((double) v->MaxLineBufferLines, dml_floor(v->LineBufferSizeFinal / v->LBBitPerPixel[k] / (SwathWidthY[k] / dml_max(v->HRatio[k], 1.0)), 1)) - (v->vtaps[k] - 1);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4406
LBLatencyHidingSourceLinesC[k] = dml_min((double) v->MaxLineBufferLines, dml_floor(v->LineBufferSizeFinal / v->LBBitPerPixel[k] / (SwathWidthC[k] / dml_max(v->HRatioChroma[k], 1.0)), 1)) - (v->VTAPsChroma[k] - 1);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4410
dml_print("DML::%s: k=%d, v->MaxLineBufferLines = %d\n", __func__, k, v->MaxLineBufferLines);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4411
dml_print("DML::%s: k=%d, v->LineBufferSizeFinal = %d\n", __func__, k, v->LineBufferSizeFinal);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4412
dml_print("DML::%s: k=%d, v->LBBitPerPixel = %d\n", __func__, k, v->LBBitPerPixel[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4413
dml_print("DML::%s: k=%d, v->HRatio = %f\n", __func__, k, v->HRatio[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4414
dml_print("DML::%s: k=%d, v->vtaps = %d\n", __func__, k, v->vtaps[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4417
EffectiveLBLatencyHidingY = LBLatencyHidingSourceLinesY[k] / v->VRatio[k] * (v->HTotal[k] / v->PixelClock[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4418
EffectiveLBLatencyHidingC = LBLatencyHidingSourceLinesC[k] / v->VRatioChroma[k] * (v->HTotal[k] / v->PixelClock[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4424
* (SwathWidthY[k] * BytePerPixelDETY[k] * v->VRatio[k])
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4425
/ (v->HTotal[k] / v->PixelClock[k]) / TotalPixelBW;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4430
FullDETBufferingTimeY = LinesInDETYRoundedDownToSwath[k] * (v->HTotal[k] / v->PixelClock[k]) / v->VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4433
- (DSTXAfterScaler[k] / v->HTotal[k] + DSTYAfterScaler[k]) * v->HTotal[k] / v->PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4435
if (v->NumberOfActiveSurfaces > 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4437
- (1.0 - 1.0 / v->NumberOfActiveSurfaces) * SwathHeightY[k] * v->HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4438
/ v->PixelClock[k] / v->VRatio[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4444
FullDETBufferingTimeC = LinesInDETCRoundedDownToSwath[k] * (v->HTotal[k] / v->PixelClock[k])
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4445
/ v->VRatioChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4447
- (DSTXAfterScaler[k] / v->HTotal[k] + DSTYAfterScaler[k]) * v->HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4448
/ v->PixelClock[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4449
if (v->NumberOfActiveSurfaces > 1) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4451
- (1 - 1 / v->NumberOfActiveSurfaces) * SwathHeightC[k] * v->HTotal[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4452
/ v->PixelClock[k] / v->VRatioChroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4460
ActiveDRAMClockChangeLatencyMargin[k] = ActiveClockChangeLatencyHiding - v->Watermark.UrgentWatermark
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4461
- v->Watermark.DRAMClockChangeWatermark;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4462
ActiveFCLKChangeLatencyMargin[k] = ActiveClockChangeLatencyHiding - v->Watermark.UrgentWatermark
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4463
- v->Watermark.FCLKChangeWatermark;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4464
USRRetrainingLatencyMargin[k] = ActiveClockChangeLatencyHiding - v->Watermark.USRRetrainingWatermark;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4466
if (v->WritebackEnable[k]) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4467
WritebackLatencyHiding = v->WritebackInterfaceBufferSize * 1024
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4468
/ (v->WritebackDestinationWidth[k] * v->WritebackDestinationHeight[k]
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4469
/ (v->WritebackSourceHeight[k] * v->HTotal[k] / v->PixelClock[k]) * 4);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4470
if (v->WritebackPixelFormat[k] == dm_444_64)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4474
- v->Watermark.WritebackDRAMClockChangeWatermark;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4477
- v->Watermark.WritebackFCLKChangeWatermark;
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4485
(v->UsesMALLForPStateChange[k] == dm_use_mall_pstate_change_phantom_pipe) ?
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4491
for (i = 0; i < v->NumberOfActiveSurfaces; ++i) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4492
for (j = 0; j < v->NumberOfActiveSurfaces; ++j) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4494
(v->BlendingAndTiming[i] == i && v->BlendingAndTiming[j] == i) ||
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4495
(v->BlendingAndTiming[j] == j && v->BlendingAndTiming[i] == j) ||
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4496
(v->BlendingAndTiming[i] == v->BlendingAndTiming[j] && v->BlendingAndTiming[i] != i) ||
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4497
(v->SynchronizeTimingsFinal && v->PixelClock[i] == v->PixelClock[j] &&
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4498
v->HTotal[i] == v->HTotal[j] && v->VTotal[i] == v->VTotal[j] &&
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4499
v->VActive[i] == v->VActive[j]) || (v->SynchronizeDRRDisplaysForUCLKPStateChangeFinal &&
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4500
(v->DRRDisplay[i] || v->DRRDisplay[j]))) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4508
for (k = 0; k < v->NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4509
if ((v->UsesMALLForPStateChange[k] != dm_use_mall_pstate_change_phantom_pipe) &&
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4521
for (k = 0; k < v->NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4523
if ((v->UsesMALLForPStateChange[k] != dm_use_mall_pstate_change_phantom_pipe) &&
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4543
for (k = 0; k < v->NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4544
if ((v->UsesMALLForPStateChange[k] != dm_use_mall_pstate_change_phantom_pipe) &&
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4550
for (k = 0; k < v->NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4551
if (v->UsesMALLForPStateChange[k] != dm_use_mall_pstate_change_full_frame &&
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4552
v->UsesMALLForPStateChange[k] != dm_use_mall_pstate_change_sub_viewport &&
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4553
v->UsesMALLForPStateChange[k] != dm_use_mall_pstate_change_phantom_pipe &&
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4567
for (k = 0; k < v->NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4568
if (v->UsesMALLForPStateChange[k] == dm_use_mall_pstate_change_full_frame)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4570
else if (v->UsesMALLForPStateChange[k] == dm_use_mall_pstate_change_sub_viewport)
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4597
for (k = 0; k < v->NumberOfActiveSurfaces; ++k) {
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4603
dst_y_pstate = dml_ceil((mmSOCParameters.DRAMClockChangeLatency + mmSOCParameters.UrgentLatency) / (v->HTotal[k] / v->PixelClock[k]), 1);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4604
src_y_pstate_l = dml_ceil(dst_y_pstate * v->VRatio[k], SwathHeightY[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4606
sub_vp_lines_l = src_y_pstate_l + src_y_ahead_l + v->meta_row_height[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4617
dml_print("DML::%s: k=%d, v->meta_row_height = %d\n", __func__, k, v->meta_row_height[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4623
src_y_pstate_c = dml_ceil(dst_y_pstate * v->VRatioChroma[k], SwathHeightC[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4625
sub_vp_lines_c = src_y_pstate_c + src_y_ahead_c + v->meta_row_height_chroma[k];
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
4631
dml_print("DML::%s: k=%d, v->meta_row_height_chroma = %d\n", __func__, k, v->meta_row_height_chroma[k]);
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
722
struct vba_vars_st *v,
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
805
struct vba_vars_st *v,
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c
543
init_frac = dc_fixpt_u0d19(data->inits.v) << 5;
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c
544
init_int = dc_fixpt_floor(data->inits.v);
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c
550
struct fixed31_32 bot = dc_fixpt_add(data->inits.v, data->ratios.vert);
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
590
init_frac = dc_fixpt_u0d19(data->inits.v) << 5;
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
591
init_int = dc_fixpt_floor(data->inits.v);
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
597
struct fixed31_32 bot = dc_fixpt_add(data->inits.v, data->ratios.vert);
drivers/gpu/drm/amd/display/dc/inc/hw/transform.h
149
struct fixed31_32 v;
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
1862
struct vba_vars_st *v = &context->bw_ctx.dml.vba;
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
1863
int max_mpc_comb = v->maxMpcComb;
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
1918
if (v->NoOfDPP[vlevel][0][pipe_idx] == 1 &&
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
1919
v->ModeSupport[vlevel][0])
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
1928
v->maxMpcComb = max_mpc_comb;
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
1934
int pipe_plane = v->pipe_plane[pipe_idx];
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
1941
if (split4mpc || v->NoOfDPP[vlevel][max_mpc_comb][pipe_plane] == 4)
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
1943
else if (force_split || v->NoOfDPP[vlevel][max_mpc_comb][pipe_plane] == 2)
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
1957
v->ODMCombineEnablePerState[vlevel][pipe_plane] = dm_odm_combine_mode_2to1;
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
1961
v->ODMCombineEnablePerState[vlevel][pipe_plane] = dm_odm_combine_mode_4to1;
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
1968
v->ODMCombineEnabled[pipe_plane] =
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
1969
v->ODMCombineEnablePerState[vlevel][pipe_plane];
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
1971
if (v->ODMCombineEnabled[pipe_plane] == dm_odm_combine_mode_disabled) {
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
2028
if (split[i] != 0 && v->NoOfDPP[vlevel][max_mpc_comb][pipe_idx] == 1) {
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
2030
dcn20_fpu_adjust_dppclk(v, vlevel, max_mpc_comb, pipe_idx, false);
drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c
1220
SPL_NAMESPACE(spl_fixpt_u0d19(scl_data->inits.v)) << 5;
drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c
1222
spl_fixpt_floor(scl_data->inits.v);
drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c
1228
bot = spl_fixpt_add(scl_data->inits.v, scl_data->ratios.vert);
drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c
703
&spl_scratch->scl_data.inits.v,
drivers/gpu/drm/amd/display/dc/sspl/dc_spl_types.h
33
struct spl_fixed31_32 v;
drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h
118
u16 v;
drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h
157
u16 v;
drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h
168
u16 v;
drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
104
if (vddc_sclk_table->entries[i].v == vid_7bit)
drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
1040
pi->high_voltage_t < table->entries[i].v)
drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
1044
pi->samu_level[i].MinVoltage = cpu_to_be16(table->entries[i].v);
drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
1106
pi->acp_level[i].MinVoltage = cpu_to_be16(table->entries[i].v);
drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
126
u32 v = RREG32(mmDOUT_SCRATCH3);
drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
129
v |= 0x4;
drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
131
v &= 0xFFFFFFFB;
drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
133
WREG32(mmDOUT_SCRATCH3, v);
drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
2057
uvd_table->entries[i].v =
drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
2059
uvd_table->entries[i].v);
drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
2064
vce_table->entries[i].v =
drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
2066
vce_table->entries[i].v);
drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
2071
samu_table->entries[i].v =
drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
2073
samu_table->entries[i].v);
drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
2078
acp_table->entries[i].v =
drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
2080
acp_table->entries[i].v);
drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
2172
(kv_convert_8bit_index_to_voltage(adev, table->entries[i].v) <=
drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
2420
kv_convert_8bit_index_to_voltage(adev, table->entries[i].v)))
drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
2426
table->entries[i].v);
drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
82
return vddc_sclk_table->entries[vid_2bit].v;
drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
84
return vddc_sclk_table->entries[vddc_sclk_table->count - 1].v;
drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
906
(pi->high_voltage_t < table->entries[i].v))
drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
911
pi->uvd_level[i].MinVddNb = cpu_to_be16(table->entries[i].v);
drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
977
pi->high_voltage_t < table->entries[i].v)
drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
981
pi->vce_level[i].MinVoltage = cpu_to_be16(table->entries[i].v);
drivers/gpu/drm/amd/pm/legacy-dpm/legacy_dpm.c
175
amdgpu_table->entries[i].v = le16_to_cpu(entry->usVoltage);
drivers/gpu/drm/amd/pm/legacy-dpm/legacy_dpm.c
416
adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].v =
drivers/gpu/drm/amd/pm/legacy-dpm/legacy_dpm.c
468
adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].v =
drivers/gpu/drm/amd/pm/legacy-dpm/legacy_dpm.c
493
adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].v =
drivers/gpu/drm/amd/pm/legacy-dpm/legacy_dpm.c
547
adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].v =
drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
1875
u16 v, s32 t, u32 ileakage, u32 *leakage)
drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
1882
vddc = div64_s64(drm_int2fixp(v), 1000);
drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
1903
u16 v,
drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
1908
si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage);
drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
1912
const u32 fixed_kt, u16 v,
drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
1918
vddc = div64_s64(drm_int2fixp(v), 1000);
drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
1932
u16 v,
drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
1936
si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage);
drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
3057
*voltage = table->entries[i].v;
drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
3065
*voltage = table->entries[table->count - 1].v;
drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
3288
if (*voltage < table->entries[i].v)
drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
3289
*voltage = (u16)((table->entries[i].v < max_voltage) ?
drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
3290
table->entries[i].v : max_voltage);
drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
4458
voltage_table->entries[i].value = voltage_dependency_table->entries[i].v;
drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
4670
(u16)adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
4685
(u16)adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
5695
adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v)
drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
6396
table->entries[i].v,
drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
6399
table->entries[i].v = leakage_voltage;
drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
6410
table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ?
drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
6411
table->entries[j].v : table->entries[j + 1].v;
drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
7453
adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
7455
adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
7457
adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
7459
adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c
744
if (hwmgr->dyn_state.vddc_dependency_on_sclk->entries[entry_id].v == virtual_voltage_id) {
drivers/gpu/drm/amd/pm/powerplay/hwmgr/processpptables.c
1220
uvd_table->entries[i].v = (unsigned long)le16_to_cpu(table->entries[i].usVoltage);
drivers/gpu/drm/amd/pm/powerplay/hwmgr/processpptables.c
1248
vce_table->entries[i].v = (unsigned long)le16_to_cpu(table->entries[i].usVoltage);
drivers/gpu/drm/amd/pm/powerplay/hwmgr/processpptables.c
1274
samu_table->entries[i].v = (unsigned long)le16_to_cpu(table->entries[i].usVoltage);
drivers/gpu/drm/amd/pm/powerplay/hwmgr/processpptables.c
1298
acp_table->entries[i].v = (unsigned long)le16_to_cpu(table->entries[i].usVoltage);
drivers/gpu/drm/amd/pm/powerplay/hwmgr/processpptables.c
395
dep_table->entries[i].v =
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
145
table_clk_vlt->entries[0].v = 0;
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
147
table_clk_vlt->entries[1].v = 1;
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
149
table_clk_vlt->entries[2].v = 2;
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
151
table_clk_vlt->entries[3].v = 3;
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
153
table_clk_vlt->entries[4].v = 4;
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
155
table_clk_vlt->entries[5].v = 5;
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
157
table_clk_vlt->entries[6].v = 6;
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
159
table_clk_vlt->entries[7].v = 7;
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
2657
smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v,
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
2671
smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v,
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
2685
smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v,
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
2700
smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v,
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
2728
smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v,
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
2742
smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v,
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
2863
data->min_vddc_in_pptable = (uint16_t)allowed_sclk_vddc_table->entries[0].v;
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
2864
data->max_vddc_in_pptable = (uint16_t)allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
2871
allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
2874
data->min_vddci_in_pptable = (uint16_t)allowed_mclk_vddci_table->entries[0].v;
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
2875
data->max_vddci_in_pptable = (uint16_t)allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v;
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
2879
hwmgr->dyn_state.max_clock_voltage_on_ac.vddci = hwmgr->dyn_state.vddci_dependency_on_mclk->entries[hwmgr->dyn_state.vddci_dependency_on_mclk->count - 1].v;
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
302
voltage_dependency_table->entries[i].v;
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
3864
if (dep_mclk_table->entries[0].v !=
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
832
data->dpm_table.vddc_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].v;
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
844
data->dpm_table.vddci_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].v;
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
858
data->dpm_table.mvdd_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].v;
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
1402
smu8_ps->levels[index].vddcIndex = (uint8_t)table->entries[clock_info_index].v;
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
1537
if (limits->vddc >= table->entries[i].v) {
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
267
(uint16_t)dep_table->entries[dep_table->count-1].v);
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
288
table_clk_vlt->entries[0].v = 0;
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
290
table_clk_vlt->entries[1].v = 1;
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
292
table_clk_vlt->entries[2].v = 2;
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
294
table_clk_vlt->entries[3].v = 3;
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
296
table_clk_vlt->entries[4].v = 4;
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
298
table_clk_vlt->entries[5].v = 5;
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
300
table_clk_vlt->entries[6].v = 6;
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
302
table_clk_vlt->entries[7].v = 7;
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
479
(i < vddc_table->count) ? (uint8_t)vddc_table->entries[i].v : 0;
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
492
(i < vdd_gfx_table->count) ? (uint8_t)vdd_gfx_table->entries[i].v : 0;
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
496
(i < acp_table->count) ? (uint8_t)acp_table->entries[i].v : 0;
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
510
(i < uvd_table->count) ? (uint8_t)uvd_table->entries[i].v : 0;
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
522
(i < uvd_table->count) ? (uint8_t)uvd_table->entries[i].v : 0;
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
535
(i < vce_table->count) ? (uint8_t)vce_table->entries[i].v : 0;
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu_helper.c
508
table_clk_vlt->entries[0].v = 700;
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu_helper.c
510
table_clk_vlt->entries[0].v = 0;
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu_helper.c
514
table_clk_vlt->entries[1].v = 740;
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu_helper.c
516
table_clk_vlt->entries[1].v = 720;
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu_helper.c
520
table_clk_vlt->entries[2].v = 800;
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu_helper.c
522
table_clk_vlt->entries[2].v = 810;
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu_helper.c
524
table_clk_vlt->entries[3].v = 900;
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu_helper.c
560
req_vddc = table->entries[i].v;
drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h
105
uint32_t v;
drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h
111
uint32_t v;
drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h
116
uint32_t v;
drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h
121
uint32_t v;
drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h
138
uint32_t v;
drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h
148
uint32_t v;
drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h
159
uint32_t v;
drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h
400
uint32_t v;
drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h
99
uint32_t v;
drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
1535
uvd_table->entries[count].v * VOLTAGE_SCALE;
drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
1574
vce_table->entries[count].v * VOLTAGE_SCALE;
drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
1605
table->AcpLevel[count].MinVoltage = acp_table->entries[count].v;
drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
288
*vol = allowed_clock_voltage_table->entries[i].v;
drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
2882
if (uvd_table->entries[i].v <= max_vddc)
drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
2914
if (vce_table->entries[i].v <= max_vddc)
drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
293
*vol = allowed_clock_voltage_table->entries[i - 1].v;
drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
783
if (tab->value == hwmgr->dyn_state.vddc_dependency_on_sclk->entries[v_index].v) {
drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
799
if (tab->value <= hwmgr->dyn_state.vddc_dependency_on_sclk->entries[v_index].v) {
drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
967
if (ulv_voltage > hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v)
drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
971
state->VddcOffset = (uint16_t)(hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v - ulv_voltage);
drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
974
if (ulv_voltage > hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v)
drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
978
(hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v - ulv_voltage)
drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
519
*vol = allowed_clock_voltage_table->entries[i].v;
drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
525
*vol = allowed_clock_voltage_table->entries[i - 1].v;
drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
555
if (tab->value == hwmgr->dyn_state.vddc_dependency_on_sclk->entries[v_index].v) {
drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
575
if (tab->value <= hwmgr->dyn_state.vddc_dependency_on_sclk->entries[v_index].v) {
drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
734
if (ulv_voltage > hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v)
drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
738
state->VddcOffset = (uint16_t)(hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v - ulv_voltage);
drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
741
if (ulv_voltage > hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v)
drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
745
(hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v - ulv_voltage)
drivers/gpu/drm/arm/display/include/malidp_io.h
19
malidp_write32(u32 __iomem *base, u32 offset, u32 v)
drivers/gpu/drm/arm/display/include/malidp_io.h
21
writel(v, (base + (offset >> 2)));
drivers/gpu/drm/arm/display/include/malidp_io.h
25
malidp_write64(u32 __iomem *base, u32 offset, u64 v)
drivers/gpu/drm/arm/display/include/malidp_io.h
27
writel(lower_32_bits(v), (base + (offset >> 2)));
drivers/gpu/drm/arm/display/include/malidp_io.h
28
writel(upper_32_bits(v), (base + (offset >> 2) + 1));
drivers/gpu/drm/arm/display/include/malidp_io.h
32
malidp_write32_mask(u32 __iomem *base, u32 offset, u32 m, u32 v)
drivers/gpu/drm/arm/display/include/malidp_io.h
37
malidp_write32(base, offset, v | tmp);
drivers/gpu/drm/arm/display/include/malidp_utils.h
38
static inline bool malidp_in_range(struct malidp_range *rg, u32 v)
drivers/gpu/drm/arm/display/include/malidp_utils.h
40
return (v >= rg->start) && (v <= rg->end);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
1000
seq_printf(sf, "MG_INPUT_ID1:\t\t0x%X\n", v);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
1002
get_values_from_reg(c->reg, BLK_CONTROL, 1, &v);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
1003
seq_printf(sf, "MG_CONTROL:\t\t0x%X\n", v);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
1005
get_values_from_reg(c->reg, MG_SIZE, 1, &v);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
1006
seq_printf(sf, "MG_SIZE:\t\t0x%X\n", v);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
1095
u32 v[12], i;
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
1099
get_values_from_reg(c->reg, 0x80, 2, v);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
1100
seq_printf(sf, "IPS_INPUT_ID0:\t\t0x%X\n", v[0]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
1101
seq_printf(sf, "IPS_INPUT_ID1:\t\t0x%X\n", v[1]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
1103
get_values_from_reg(c->reg, 0xC0, 1, v);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
1104
seq_printf(sf, "IPS_INFO:\t\t0x%X\n", v[0]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
1106
get_values_from_reg(c->reg, 0xD0, 3, v);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
1107
seq_printf(sf, "IPS_CONTROL:\t\t0x%X\n", v[0]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
1108
seq_printf(sf, "IPS_SIZE:\t\t0x%X\n", v[1]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
1109
seq_printf(sf, "IPS_DEPTH:\t\t0x%X\n", v[2]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
1111
get_values_from_reg(c->reg, 0x130, 12, v);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
1113
seq_printf(sf, "IPS_RGB_RGB_COEFF%u:\t0x%X\n", i, v[i]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
1115
get_values_from_reg(c->reg, 0x170, 12, v);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
1117
seq_printf(sf, "IPS_RGB_YUV_COEFF%u:\t0x%X\n", i, v[i]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
1213
u32 v[8], i;
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
1217
get_values_from_reg(c->reg, 0xC0, 1, v);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
1218
seq_printf(sf, "BS_INFO:\t\t0x%X\n", v[0]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
1220
get_values_from_reg(c->reg, 0xD0, 8, v);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
1221
seq_printf(sf, "BS_CONTROL:\t\t0x%X\n", v[0]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
1222
seq_printf(sf, "BS_PROG_LINE:\t\t0x%X\n", v[1]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
1223
seq_printf(sf, "BS_PREFETCH_LINE:\t0x%X\n", v[2]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
1224
seq_printf(sf, "BS_BG_COLOR:\t\t0x%X\n", v[3]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
1225
seq_printf(sf, "BS_ACTIVESIZE:\t\t0x%X\n", v[4]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
1226
seq_printf(sf, "BS_HINTERVALS:\t\t0x%X\n", v[5]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
1227
seq_printf(sf, "BS_VINTERVALS:\t\t0x%X\n", v[6]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
1228
seq_printf(sf, "BS_SYNC:\t\t0x%X\n", v[7]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
1230
get_values_from_reg(c->reg, 0x100, 3, v);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
1231
seq_printf(sf, "BS_DRIFT_TO:\t\t0x%X\n", v[0]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
1232
seq_printf(sf, "BS_FRAME_TO:\t\t0x%X\n", v[1]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
1233
seq_printf(sf, "BS_TE_TO:\t\t0x%X\n", v[2]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
1235
get_values_from_reg(c->reg, 0x110, 3, v);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
1237
seq_printf(sf, "BS_T%u_INTERVAL:\t\t0x%X\n", i, v[i]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
1239
get_values_from_reg(c->reg, 0x120, 5, v);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
1241
seq_printf(sf, "BS_CRC%u_LOW:\t\t0x%X\n", i, v[i << 1]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
1242
seq_printf(sf, "BS_CRC%u_HIGH:\t\t0x%X\n", i, v[(i << 1) + 1]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
1244
seq_printf(sf, "BS_USER:\t\t0x%X\n", v[4]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
1360
u32 v[5];
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
1364
get_values_from_reg(d71->gcu_addr, 0, 3, v);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
1365
seq_printf(sf, "GLB_ARCH_ID:\t\t0x%X\n", v[0]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
1366
seq_printf(sf, "GLB_CORE_ID:\t\t0x%X\n", v[1]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
1367
seq_printf(sf, "GLB_CORE_INFO:\t\t0x%X\n", v[2]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
1369
get_values_from_reg(d71->gcu_addr, 0x10, 1, v);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
1370
seq_printf(sf, "GLB_IRQ_STATUS:\t\t0x%X\n", v[0]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
1372
get_values_from_reg(d71->gcu_addr, 0xA0, 5, v);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
1373
seq_printf(sf, "GCU_IRQ_RAW_STATUS:\t0x%X\n", v[0]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
1374
seq_printf(sf, "GCU_IRQ_CLEAR:\t\t0x%X\n", v[1]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
1375
seq_printf(sf, "GCU_IRQ_MASK:\t\t0x%X\n", v[2]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
1376
seq_printf(sf, "GCU_IRQ_STATUS:\t\t0x%X\n", v[3]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
1377
seq_printf(sf, "GCU_STATUS:\t\t0x%X\n", v[4]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
1379
get_values_from_reg(d71->gcu_addr, 0xD0, 3, v);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
1380
seq_printf(sf, "GCU_CONTROL:\t\t0x%X\n", v[0]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
1381
seq_printf(sf, "GCU_CONFIG_VALID0:\t0x%X\n", v[1]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
1382
seq_printf(sf, "GCU_CONFIG_VALID1:\t0x%X\n", v[2]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
1387
u32 v[6];
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
1393
get_values_from_reg(pipe->lpu_addr, 0xA0, 6, v);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
1394
seq_printf(sf, "LPU_IRQ_RAW_STATUS:\t0x%X\n", v[0]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
1395
seq_printf(sf, "LPU_IRQ_CLEAR:\t\t0x%X\n", v[1]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
1396
seq_printf(sf, "LPU_IRQ_MASK:\t\t0x%X\n", v[2]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
1397
seq_printf(sf, "LPU_IRQ_STATUS:\t\t0x%X\n", v[3]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
1398
seq_printf(sf, "LPU_STATUS:\t\t0x%X\n", v[4]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
1399
seq_printf(sf, "LPU_TBU_STATUS:\t\t0x%X\n", v[5]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
1401
get_values_from_reg(pipe->lpu_addr, 0xC0, 1, v);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
1402
seq_printf(sf, "LPU_INFO:\t\t0x%X\n", v[0]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
1404
get_values_from_reg(pipe->lpu_addr, 0xD0, 3, v);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
1405
seq_printf(sf, "LPU_RAXI_CONTROL:\t0x%X\n", v[0]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
1406
seq_printf(sf, "LPU_WAXI_CONTROL:\t0x%X\n", v[1]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
1407
seq_printf(sf, "LPU_TBU_CONTROL:\t0x%X\n", v[2]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
1412
u32 v[5];
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
1418
get_values_from_reg(pipe->dou_addr, 0xA0, 5, v);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
1419
seq_printf(sf, "DOU_IRQ_RAW_STATUS:\t0x%X\n", v[0]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
1420
seq_printf(sf, "DOU_IRQ_CLEAR:\t\t0x%X\n", v[1]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
1421
seq_printf(sf, "DOU_IRQ_MASK:\t\t0x%X\n", v[2]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
1422
seq_printf(sf, "DOU_IRQ_STATUS:\t\t0x%X\n", v[3]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
1423
seq_printf(sf, "DOU_STATUS:\t\t0x%X\n", v[4]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
290
u32 v[15], i;
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
294
get_values_from_reg(c->reg, LAYER_INFO, 1, &v[14]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
295
if (v[14] & 0x1) {
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
303
rgb2rgb = !!(v[14] & L_INFO_CM);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
307
seq_printf(sf, "%sLAYER_INFO:\t\t0x%X\n", prefix, v[14]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
309
get_values_from_reg(c->reg, 0xD0, 1, v);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
310
seq_printf(sf, "%sCONTROL:\t\t0x%X\n", prefix, v[0]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
312
get_values_from_reg(c->reg, 0xD4, 1, v);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
313
seq_printf(sf, "LR_RICH_CONTROL:\t0x%X\n", v[0]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
315
get_values_from_reg(c->reg, 0xD8, 4, v);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
316
seq_printf(sf, "%sFORMAT:\t\t0x%X\n", prefix, v[0]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
317
seq_printf(sf, "%sIT_COEFFTAB:\t\t0x%X\n", prefix, v[1]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
318
seq_printf(sf, "%sIN_SIZE:\t\t0x%X\n", prefix, v[2]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
319
seq_printf(sf, "%sPALPHA:\t\t0x%X\n", prefix, v[3]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
321
get_values_from_reg(c->reg, 0x100, 3, v);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
322
seq_printf(sf, "%sP0_PTR_LOW:\t\t0x%X\n", prefix, v[0]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
323
seq_printf(sf, "%sP0_PTR_HIGH:\t\t0x%X\n", prefix, v[1]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
324
seq_printf(sf, "%sP0_STRIDE:\t\t0x%X\n", prefix, v[2]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
326
get_values_from_reg(c->reg, 0x110, 2, v);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
327
seq_printf(sf, "%sP1_PTR_LOW:\t\t0x%X\n", prefix, v[0]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
328
seq_printf(sf, "%sP1_PTR_HIGH:\t\t0x%X\n", prefix, v[1]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
330
get_values_from_reg(c->reg, 0x118, 1, v);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
331
seq_printf(sf, "LR_P1_STRIDE:\t\t0x%X\n", v[0]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
333
get_values_from_reg(c->reg, 0x120, 2, v);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
334
seq_printf(sf, "LR_P2_PTR_LOW:\t\t0x%X\n", v[0]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
335
seq_printf(sf, "LR_P2_PTR_HIGH:\t\t0x%X\n", v[1]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
337
get_values_from_reg(c->reg, 0x130, 12, v);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
339
seq_printf(sf, "LR_YUV_RGB_COEFF%u:\t0x%X\n", i, v[i]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
343
get_values_from_reg(c->reg, LAYER_RGB_RGB_COEFF0, 12, v);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
345
seq_printf(sf, "LS_RGB_RGB_COEFF%u:\t0x%X\n", i, v[i]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
348
get_values_from_reg(c->reg, 0x160, 3, v);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
349
seq_printf(sf, "%sAD_CONTROL:\t\t0x%X\n", prefix, v[0]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
350
seq_printf(sf, "%sAD_H_CROP:\t\t0x%X\n", prefix, v[1]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
351
seq_printf(sf, "%sAD_V_CROP:\t\t0x%X\n", prefix, v[2]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
488
u32 v[12], i;
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
492
get_values_from_reg(c->reg, 0x80, 1, v);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
493
seq_printf(sf, "LW_INPUT_ID0:\t\t0x%X\n", v[0]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
495
get_values_from_reg(c->reg, 0xD0, 3, v);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
496
seq_printf(sf, "LW_CONTROL:\t\t0x%X\n", v[0]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
497
seq_printf(sf, "LW_PROG_LINE:\t\t0x%X\n", v[1]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
498
seq_printf(sf, "LW_FORMAT:\t\t0x%X\n", v[2]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
500
get_values_from_reg(c->reg, 0xE0, 1, v);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
501
seq_printf(sf, "LW_IN_SIZE:\t\t0x%X\n", v[0]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
504
get_values_from_reg(c->reg, 0x100 + i * 0x10, 3, v);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
505
seq_printf(sf, "LW_P%u_PTR_LOW:\t\t0x%X\n", i, v[0]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
506
seq_printf(sf, "LW_P%u_PTR_HIGH:\t\t0x%X\n", i, v[1]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
507
seq_printf(sf, "LW_P%u_STRIDE:\t\t0x%X\n", i, v[2]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
510
get_values_from_reg(c->reg, 0x130, 12, v);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
512
seq_printf(sf, "LW_RGB_YUV_COEFF%u:\t0x%X\n", i, v[i]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
628
u32 v[8], i;
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
632
get_values_from_reg(c->reg, 0x80, 5, v);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
634
seq_printf(sf, "CU_INPUT_ID%u:\t\t0x%X\n", i, v[i]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
636
get_values_from_reg(c->reg, 0xA0, 5, v);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
637
seq_printf(sf, "CU_IRQ_RAW_STATUS:\t0x%X\n", v[0]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
638
seq_printf(sf, "CU_IRQ_CLEAR:\t\t0x%X\n", v[1]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
639
seq_printf(sf, "CU_IRQ_MASK:\t\t0x%X\n", v[2]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
640
seq_printf(sf, "CU_IRQ_STATUS:\t\t0x%X\n", v[3]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
641
seq_printf(sf, "CU_STATUS:\t\t0x%X\n", v[4]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
643
get_values_from_reg(c->reg, 0xD0, 2, v);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
644
seq_printf(sf, "CU_CONTROL:\t\t0x%X\n", v[0]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
645
seq_printf(sf, "CU_SIZE:\t\t0x%X\n", v[1]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
647
get_values_from_reg(c->reg, 0xDC, 1, v);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
648
seq_printf(sf, "CU_BG_COLOR:\t\t0x%X\n", v[0]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
650
for (i = 0, v[4] = 0xE0; i < 5; i++, v[4] += 0x10) {
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
651
get_values_from_reg(c->reg, v[4], 3, v);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
652
seq_printf(sf, "CU_INPUT%u_SIZE:\t\t0x%X\n", i, v[0]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
653
seq_printf(sf, "CU_INPUT%u_OFFSET:\t0x%X\n", i, v[1]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
654
seq_printf(sf, "CU_INPUT%u_CONTROL:\t0x%X\n", i, v[2]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
657
get_values_from_reg(c->reg, 0x130, 2, v);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
658
seq_printf(sf, "CU_USER_LOW:\t\t0x%X\n", v[0]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
659
seq_printf(sf, "CU_USER_HIGH:\t\t0x%X\n", v[1]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
797
u32 v[10];
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
801
get_values_from_reg(c->reg, 0x80, 1, v);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
802
seq_printf(sf, "SC_INPUT_ID0:\t\t0x%X\n", v[0]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
804
get_values_from_reg(c->reg, 0xD0, 1, v);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
805
seq_printf(sf, "SC_CONTROL:\t\t0x%X\n", v[0]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
807
get_values_from_reg(c->reg, 0xDC, 9, v);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
808
seq_printf(sf, "SC_COEFFTAB:\t\t0x%X\n", v[0]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
809
seq_printf(sf, "SC_IN_SIZE:\t\t0x%X\n", v[1]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
810
seq_printf(sf, "SC_OUT_SIZE:\t\t0x%X\n", v[2]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
811
seq_printf(sf, "SC_H_CROP:\t\t0x%X\n", v[3]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
812
seq_printf(sf, "SC_V_CROP:\t\t0x%X\n", v[4]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
813
seq_printf(sf, "SC_H_INIT_PH:\t\t0x%X\n", v[5]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
814
seq_printf(sf, "SC_H_DELTA_PH:\t\t0x%X\n", v[6]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
815
seq_printf(sf, "SC_V_INIT_PH:\t\t0x%X\n", v[7]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
816
seq_printf(sf, "SC_V_DELTA_PH:\t\t0x%X\n", v[8]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
818
get_values_from_reg(c->reg, 0x130, 10, v);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
819
seq_printf(sf, "SC_ENH_LIMITS:\t\t0x%X\n", v[0]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
820
seq_printf(sf, "SC_ENH_COEFF0:\t\t0x%X\n", v[1]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
821
seq_printf(sf, "SC_ENH_COEFF1:\t\t0x%X\n", v[2]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
822
seq_printf(sf, "SC_ENH_COEFF2:\t\t0x%X\n", v[3]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
823
seq_printf(sf, "SC_ENH_COEFF3:\t\t0x%X\n", v[4]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
824
seq_printf(sf, "SC_ENH_COEFF4:\t\t0x%X\n", v[5]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
825
seq_printf(sf, "SC_ENH_COEFF5:\t\t0x%X\n", v[6]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
826
seq_printf(sf, "SC_ENH_COEFF6:\t\t0x%X\n", v[7]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
827
seq_printf(sf, "SC_ENH_COEFF7:\t\t0x%X\n", v[8]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
828
seq_printf(sf, "SC_ENH_COEFF8:\t\t0x%X\n", v[9]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
926
u32 v[3];
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
930
get_values_from_reg(c->reg, BLK_INPUT_ID0, 1, v);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
931
seq_printf(sf, "SP_INPUT_ID0:\t\t0x%X\n", v[0]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
933
get_values_from_reg(c->reg, BLK_CONTROL, 3, v);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
934
seq_printf(sf, "SP_CONTROL:\t\t0x%X\n", v[0]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
935
seq_printf(sf, "SP_SIZE:\t\t0x%X\n", v[1]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
936
seq_printf(sf, "SP_OVERLAP_SIZE:\t0x%X\n", v[2]);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
992
u32 v;
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
996
get_values_from_reg(c->reg, MG_INPUT_ID0, 1, &v);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
997
seq_printf(sf, "MG_INPUT_ID0:\t\t0x%X\n", v);
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
999
get_values_from_reg(c->reg, MG_INPUT_ID1, 1, &v);
drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h
48
#define HV_SIZE(h, v) (((h) & 0x1FFF) + (((v) & 0x1FFF) << 16))
drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h
49
#define HV_OFFSET(h, v) (((h) & 0xFFF) + (((v) & 0xFFF) << 16))
drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h
50
#define HV_CROP(h, v) (((h) & 0xFFF) + (((v) & 0xFFF) << 16))
drivers/gpu/drm/arm/malidp_hw.c
453
u8 v = (u8)se_config->vcoeff - 1;
drivers/gpu/drm/arm/malidp_hw.c
456
v >= ARRAY_SIZE(dp500_se_scaling_coeffs)))
drivers/gpu/drm/arm/malidp_hw.c
459
if ((h == v) && (se_config->hcoeff != old_config->hcoeff ||
drivers/gpu/drm/arm/malidp_hw.c
464
0, v);
drivers/gpu/drm/arm/malidp_hw.c
469
0, v);
drivers/gpu/drm/armada/armada_510.c
104
struct armada510_variant_data *v = dcrtc->variant_data;
drivers/gpu/drm/armada/armada_510.c
110
v->clks, ARRAY_SIZE(v->clks),
drivers/gpu/drm/armada/armada_510.c
125
v->sel_clk = res.clk;
drivers/gpu/drm/armada/armada_510.c
145
struct armada510_variant_data *v = dcrtc->variant_data;
drivers/gpu/drm/armada/armada_510.c
147
if (!dcrtc->clk && v->sel_clk) {
drivers/gpu/drm/armada/armada_510.c
148
if (!WARN_ON(clk_prepare_enable(v->sel_clk)))
drivers/gpu/drm/armada/armada_510.c
149
dcrtc->clk = v->sel_clk;
drivers/gpu/drm/armada/armada_510.c
22
struct armada510_variant_data *v;
drivers/gpu/drm/armada/armada_510.c
26
v = devm_kzalloc(dev, sizeof(*v), GFP_KERNEL);
drivers/gpu/drm/armada/armada_510.c
27
if (!v)
drivers/gpu/drm/armada/armada_510.c
30
dcrtc->variant_data = v;
drivers/gpu/drm/armada/armada_510.c
53
v->clks[idx] = clk;
drivers/gpu/drm/armada/armada_510.c
61
v->clks[1] = clk;
drivers/gpu/drm/armada/armada_crtc.c
265
writel_relaxed(dcrtc->v[i].spu_v_porch, base + LCD_SPU_V_PORCH);
drivers/gpu/drm/armada/armada_crtc.c
266
writel_relaxed(dcrtc->v[i].spu_v_h_total,
drivers/gpu/drm/armada/armada_crtc.c
271
val |= dcrtc->v[i].spu_adv_reg;
drivers/gpu/drm/armada/armada_crtc.c
309
u32 v, stat = readl_relaxed(dcrtc->base + LCD_SPU_IRQ_ISR);
drivers/gpu/drm/armada/armada_crtc.c
321
v = stat & dcrtc->irq_ena;
drivers/gpu/drm/armada/armada_crtc.c
323
if (v & (VSYNC_IRQ|GRA_FRAME_IRQ|DUMB_FRAMEDONE)) {
drivers/gpu/drm/armada/armada_crtc.c
360
dcrtc->v[1].spu_v_h_total = adj->crtc_vtotal << 16 |
drivers/gpu/drm/armada/armada_crtc.c
362
dcrtc->v[1].spu_v_porch = tm << 16 | bm;
drivers/gpu/drm/armada/armada_crtc.c
364
dcrtc->v[1].spu_adv_reg = val << 20 | val | ADV_VSYNCOFFEN;
drivers/gpu/drm/armada/armada_crtc.c
369
dcrtc->v[0].spu_adv_reg = val << 20 | val | ADV_VSYNCOFFEN;
drivers/gpu/drm/armada/armada_crtc.c
370
dcrtc->v[0].spu_v_h_total = dcrtc->v[1].spu_v_h_total +
drivers/gpu/drm/armada/armada_crtc.c
372
dcrtc->v[0].spu_v_porch = dcrtc->v[1].spu_v_porch + 1;
drivers/gpu/drm/armada/armada_crtc.c
374
dcrtc->v[0] = dcrtc->v[1];
drivers/gpu/drm/armada/armada_crtc.c
381
armada_reg_queue_set(regs, i, dcrtc->v[0].spu_v_porch, LCD_SPU_V_PORCH);
drivers/gpu/drm/armada/armada_crtc.c
382
armada_reg_queue_set(regs, i, dcrtc->v[0].spu_v_h_total,
drivers/gpu/drm/armada/armada_crtc.c
386
armada_reg_queue_mod(regs, i, dcrtc->v[0].spu_adv_reg,
drivers/gpu/drm/armada/armada_crtc.h
47
} v[2];
drivers/gpu/drm/armada/armada_debugfs.c
40
u32 v = readl_relaxed(dcrtc->base + i);
drivers/gpu/drm/armada/armada_debugfs.c
41
seq_printf(m, "0x%04x: 0x%08x\n", i, v);
drivers/gpu/drm/armada/armada_debugfs.c
60
u32 v;
drivers/gpu/drm/armada/armada_debugfs.c
79
v = readl(dcrtc->base + reg);
drivers/gpu/drm/armada/armada_debugfs.c
80
v &= ~mask;
drivers/gpu/drm/armada/armada_debugfs.c
81
v |= val & mask;
drivers/gpu/drm/armada/armada_debugfs.c
82
writel(v, dcrtc->base + reg);
drivers/gpu/drm/armada/armada_drm.h
25
uint32_t ov, v;
drivers/gpu/drm/armada/armada_drm.h
27
ov = v = readl_relaxed(ptr);
drivers/gpu/drm/armada/armada_drm.h
28
v = (v & ~mask) | val;
drivers/gpu/drm/armada/armada_drm.h
29
if (ov != v)
drivers/gpu/drm/armada/armada_drm.h
30
writel_relaxed(v, ptr);
drivers/gpu/drm/armada/armada_overlay.c
355
#define CCC(v) ((v) << 24 | (v) << 16 | (v) << 8)
drivers/gpu/drm/ast/ast_drv.h
521
void ast_moutdwm(struct ast_device *ast, u32 r, u32 v);
drivers/gpu/drm/ast/ast_post.c
51
void __ast_moutdwm(void __iomem *regs, u32 r, u32 v)
drivers/gpu/drm/ast/ast_post.c
62
__ast_write32(regs, 0x10000 + (r & 0x0000ffff), v);
drivers/gpu/drm/ast/ast_post.c
70
void ast_moutdwm(struct ast_device *ast, u32 r, u32 v)
drivers/gpu/drm/ast/ast_post.c
72
__ast_moutdwm(ast->regs, r, v);
drivers/gpu/drm/ast/ast_post.h
39
void __ast_moutdwm(void __iomem *regs, u32 r, u32 v);
drivers/gpu/drm/bridge/samsung-dsim.c
1259
u32 v = samsung_dsim_read(dsi, DSIM_ESCMODE_REG);
drivers/gpu/drm/bridge/samsung-dsim.c
1262
v |= DSIM_CMD_LPDT_LP;
drivers/gpu/drm/bridge/samsung-dsim.c
1264
v &= ~DSIM_CMD_LPDT_LP;
drivers/gpu/drm/bridge/samsung-dsim.c
1266
samsung_dsim_write(dsi, DSIM_ESCMODE_REG, v);
drivers/gpu/drm/bridge/samsung-dsim.c
1271
u32 v = samsung_dsim_read(dsi, DSIM_ESCMODE_REG);
drivers/gpu/drm/bridge/samsung-dsim.c
1273
v |= DSIM_FORCE_BTA;
drivers/gpu/drm/bridge/samsung-dsim.c
1274
samsung_dsim_write(dsi, DSIM_ESCMODE_REG, v);
drivers/gpu/drm/bridge/synopsys/dw-dp.c
749
u8 v = 0;
drivers/gpu/drm/bridge/synopsys/dw-dp.c
753
v = drm_dp_get_adjust_request_voltage(status, i);
drivers/gpu/drm/bridge/synopsys/dw-dp.c
754
v >>= DP_TRAIN_VOLTAGE_SWING_SHIFT;
drivers/gpu/drm/bridge/synopsys/dw-dp.c
758
if (v != adj->voltage_swing[i] || p != adj->pre_emphasis[i])
drivers/gpu/drm/bridge/synopsys/dw-dp.c
770
v = min(v, dw_dp_voltage_max(p));
drivers/gpu/drm/bridge/synopsys/dw-dp.c
771
if (v >= (DP_TRAIN_VOLTAGE_SWING_LEVEL_3 >> DP_TRAIN_VOLTAGE_SWING_SHIFT)) {
drivers/gpu/drm/bridge/synopsys/dw-dp.c
776
adj->voltage_swing[i] = v;
drivers/gpu/drm/bridge/tc358762.c
54
#define LCDCTRL_VSDELAY(v) (((v) & 0xfff) << 20) /* VSYNC delay */
drivers/gpu/drm/bridge/tc358764.c
112
#define LV_PHY0_RST(v) FLD_VAL(v, 22, 22) /* PHY reset */
drivers/gpu/drm/bridge/tc358764.c
113
#define LV_PHY0_IS(v) FLD_VAL(v, 15, 14)
drivers/gpu/drm/bridge/tc358764.c
114
#define LV_PHY0_ND(v) FLD_VAL(v, 4, 0) /* Frequency range select */
drivers/gpu/drm/bridge/tc358764.c
115
#define LV_PHY0_PRBS_ON(v) FLD_VAL(v, 20, 16) /* Clock/Data Flag pins */
drivers/gpu/drm/bridge/tc358764.c
210
u32 v = 0;
drivers/gpu/drm/bridge/tc358764.c
212
tc358764_read(ctx, SYS_ID, &v);
drivers/gpu/drm/bridge/tc358764.c
215
dev_info(ctx->dev, "ID: %#x\n", v);
drivers/gpu/drm/bridge/tc358764.c
49
#define VP_CTRL_VSDELAY(v) FLD_VAL(v, 31, 20) /* VSYNC delay */
drivers/gpu/drm/bridge/tc358764.c
54
#define VP_HTIM1_HBP(v) FLD_VAL(v, 24, 16)
drivers/gpu/drm/bridge/tc358764.c
55
#define VP_HTIM1_HSYNC(v) FLD_VAL(v, 8, 0)
drivers/gpu/drm/bridge/tc358764.c
57
#define VP_HTIM2_HFP(v) FLD_VAL(v, 24, 16)
drivers/gpu/drm/bridge/tc358764.c
58
#define VP_HTIM2_HACT(v) FLD_VAL(v, 10, 0)
drivers/gpu/drm/bridge/tc358764.c
60
#define VP_VTIM1_VBP(v) FLD_VAL(v, 23, 16)
drivers/gpu/drm/bridge/tc358764.c
61
#define VP_VTIM1_VSYNC(v) FLD_VAL(v, 7, 0)
drivers/gpu/drm/bridge/tc358764.c
63
#define VP_VTIM2_VFP(v) FLD_VAL(v, 23, 16)
drivers/gpu/drm/bridge/tc358764.c
64
#define VP_VTIM2_VACT(v) FLD_VAL(v, 10, 0)
drivers/gpu/drm/bridge/tc358775.c
163
#define LV_PHY0_RST(v) FLD_VAL(v, 22, 22) /* PHY reset */
drivers/gpu/drm/bridge/tc358775.c
164
#define LV_PHY0_IS(v) FLD_VAL(v, 15, 14)
drivers/gpu/drm/bridge/tc358775.c
165
#define LV_PHY0_ND(v) FLD_VAL(v, 4, 0) /* Frequency range select */
drivers/gpu/drm/bridge/tc358775.c
166
#define LV_PHY0_PRBS_ON(v) FLD_VAL(v, 20, 16) /* Clock/Data Flag pins */
drivers/gpu/drm/drm_atomic_helper.c
1787
ktime_t v;
drivers/gpu/drm/drm_atomic_helper.c
1795
if (drm_crtc_next_vblank_start(crtc, &v))
drivers/gpu/drm/drm_atomic_helper.c
1798
if (!vbltime || ktime_before(v, vbltime))
drivers/gpu/drm/drm_atomic_helper.c
1799
vbltime = v;
drivers/gpu/drm/drm_edid.c
5861
int a, v;
drivers/gpu/drm/drm_edid.c
5869
v = connector->video_latency[i];
drivers/gpu/drm/drm_edid.c
5874
if (a == 255 || v == 255)
drivers/gpu/drm/drm_edid.c
5883
if (v)
drivers/gpu/drm/drm_edid.c
5884
v = min(2 * (v - 1), 500);
drivers/gpu/drm/drm_edid.c
5886
return max(v - a, 0);
drivers/gpu/drm/drm_ioc32.c
102
memset(&v, 0, sizeof(v));
drivers/gpu/drm/drm_ioc32.c
104
v = (struct drm_version) {
drivers/gpu/drm/drm_ioc32.c
112
err = drm_ioctl_kernel(file, drm_version, &v,
drivers/gpu/drm/drm_ioc32.c
117
v32.version_major = v.version_major;
drivers/gpu/drm/drm_ioc32.c
118
v32.version_minor = v.version_minor;
drivers/gpu/drm/drm_ioc32.c
119
v32.version_patchlevel = v.version_patchlevel;
drivers/gpu/drm/drm_ioc32.c
120
v32.name_len = v.name_len;
drivers/gpu/drm/drm_ioc32.c
121
v32.date_len = v.date_len;
drivers/gpu/drm/drm_ioc32.c
122
v32.desc_len = v.desc_len;
drivers/gpu/drm/drm_ioc32.c
96
struct drm_version v;
drivers/gpu/drm/exynos/exynos_drm_fimc.c
1235
{ IPP_SIZE_LIMIT(BUFFER, .h = { 16, 8192, 8 }, .v = { 16, 8192, 2 }) },
drivers/gpu/drm/exynos/exynos_drm_fimc.c
1236
{ IPP_SIZE_LIMIT(AREA, .h = { 16, 4224, 2 }, .v = { 16, 0, 2 }) },
drivers/gpu/drm/exynos/exynos_drm_fimc.c
1237
{ IPP_SIZE_LIMIT(ROTATED, .h = { 128, 1920 }, .v = { 128, 0 }) },
drivers/gpu/drm/exynos/exynos_drm_fimc.c
1239
.v = { (1 << 16) / 64, (1 << 16) * 64 }) },
drivers/gpu/drm/exynos/exynos_drm_fimc.c
1243
{ IPP_SIZE_LIMIT(BUFFER, .h = { 16, 8192, 8 }, .v = { 16, 8192, 2 }) },
drivers/gpu/drm/exynos/exynos_drm_fimc.c
1244
{ IPP_SIZE_LIMIT(AREA, .h = { 16, 1920, 2 }, .v = { 16, 0, 2 }) },
drivers/gpu/drm/exynos/exynos_drm_fimc.c
1245
{ IPP_SIZE_LIMIT(ROTATED, .h = { 128, 1366 }, .v = { 128, 0 }) },
drivers/gpu/drm/exynos/exynos_drm_fimc.c
1247
.v = { (1 << 16) / 64, (1 << 16) * 64 }) },
drivers/gpu/drm/exynos/exynos_drm_fimc.c
1251
{ IPP_SIZE_LIMIT(BUFFER, .h = { 128, 1920, 128 }, .v = { 32, 1920, 32 }) },
drivers/gpu/drm/exynos/exynos_drm_fimc.c
1252
{ IPP_SIZE_LIMIT(AREA, .h = { 128, 1920, 2 }, .v = { 128, 0, 2 }) },
drivers/gpu/drm/exynos/exynos_drm_fimc.c
1254
.v = { (1 << 16) / 64, (1 << 16) * 64 }) },
drivers/gpu/drm/exynos/exynos_drm_fimc.c
1258
{ IPP_SIZE_LIMIT(BUFFER, .h = { 128, 1920, 128 }, .v = { 32, 1920, 32 }) },
drivers/gpu/drm/exynos/exynos_drm_fimc.c
1259
{ IPP_SIZE_LIMIT(AREA, .h = { 128, 1366, 2 }, .v = { 128, 0, 2 }) },
drivers/gpu/drm/exynos/exynos_drm_fimc.c
1261
.v = { (1 << 16) / 64, (1 << 16) * 64 }) },
drivers/gpu/drm/exynos/exynos_drm_gsc.c
1359
{ IPP_SIZE_LIMIT(BUFFER, .h = { 32, 4800, 8 }, .v = { 16, 3344, 8 }) },
drivers/gpu/drm/exynos/exynos_drm_gsc.c
1360
{ IPP_SIZE_LIMIT(AREA, .h = { 16, 4800, 2 }, .v = { 8, 3344, 2 }) },
drivers/gpu/drm/exynos/exynos_drm_gsc.c
1361
{ IPP_SIZE_LIMIT(ROTATED, .h = { 32, 2048 }, .v = { 16, 2048 }) },
drivers/gpu/drm/exynos/exynos_drm_gsc.c
1363
.v = { (1 << 16) / 16, (1 << 16) * 8 }) },
drivers/gpu/drm/exynos/exynos_drm_gsc.c
1367
{ IPP_SIZE_LIMIT(BUFFER, .h = { 32, 4800, 8 }, .v = { 16, 3344, 8 }) },
drivers/gpu/drm/exynos/exynos_drm_gsc.c
1368
{ IPP_SIZE_LIMIT(AREA, .h = { 16, 4800, 2 }, .v = { 8, 3344, 2 }) },
drivers/gpu/drm/exynos/exynos_drm_gsc.c
1369
{ IPP_SIZE_LIMIT(ROTATED, .h = { 16, 2016 }, .v = { 8, 2016 }) },
drivers/gpu/drm/exynos/exynos_drm_gsc.c
1371
.v = { (1 << 16) / 16, (1 << 16) * 8 }) },
drivers/gpu/drm/exynos/exynos_drm_gsc.c
1375
{ IPP_SIZE_LIMIT(BUFFER, .h = { 32, 8191, 16 }, .v = { 16, 8191, 2 }) },
drivers/gpu/drm/exynos/exynos_drm_gsc.c
1376
{ IPP_SIZE_LIMIT(AREA, .h = { 16, 4800, 1 }, .v = { 8, 3344, 1 }) },
drivers/gpu/drm/exynos/exynos_drm_gsc.c
1377
{ IPP_SIZE_LIMIT(ROTATED, .h = { 32, 2047 }, .v = { 8, 8191 }) },
drivers/gpu/drm/exynos/exynos_drm_gsc.c
1379
.v = { (1 << 16) / 16, (1 << 16) * 8 }) },
drivers/gpu/drm/exynos/exynos_drm_ipp.c
409
struct drm_exynos_ipp_limit_val v;
drivers/gpu/drm/exynos/exynos_drm_ipp.c
449
__limit_set_val(&res->v.min, l->v.min);
drivers/gpu/drm/exynos/exynos_drm_ipp.c
450
__limit_set_val(&res->v.max, l->v.max);
drivers/gpu/drm/exynos/exynos_drm_ipp.c
451
__limit_set_val(&res->v.align, l->v.align);
drivers/gpu/drm/exynos/exynos_drm_ipp.c
482
struct drm_exynos_ipp_limit_val *lh = &l.h, *lv = &l.v;
drivers/gpu/drm/exynos/exynos_drm_ipp.c
490
!__size_limit_check(buf->buf.height, &l.v))
drivers/gpu/drm/exynos/exynos_drm_ipp.c
495
lh = &l.v;
drivers/gpu/drm/exynos/exynos_drm_ipp.c
537
lh = (!swap) ? &limits->h : &limits->v;
drivers/gpu/drm/exynos/exynos_drm_ipp.c
538
lv = (!swap) ? &limits->v : &limits->h;
drivers/gpu/drm/exynos/exynos_drm_rotator.c
357
{ IPP_SIZE_LIMIT(BUFFER, .h = { 8, SZ_16K }, .v = { 8, SZ_16K }) },
drivers/gpu/drm/exynos/exynos_drm_rotator.c
358
{ IPP_SIZE_LIMIT(AREA, .h.align = 2, .v.align = 2) },
drivers/gpu/drm/exynos/exynos_drm_rotator.c
362
{ IPP_SIZE_LIMIT(BUFFER, .h = { 8, SZ_16K }, .v = { 8, SZ_16K }) },
drivers/gpu/drm/exynos/exynos_drm_rotator.c
363
{ IPP_SIZE_LIMIT(AREA, .h.align = 4, .v.align = 4) },
drivers/gpu/drm/exynos/exynos_drm_rotator.c
367
{ IPP_SIZE_LIMIT(BUFFER, .h = { 8, SZ_8K }, .v = { 8, SZ_8K }) },
drivers/gpu/drm/exynos/exynos_drm_rotator.c
368
{ IPP_SIZE_LIMIT(AREA, .h.align = 4, .v.align = 4) },
drivers/gpu/drm/exynos/exynos_drm_rotator.c
372
{ IPP_SIZE_LIMIT(BUFFER, .h = { 8, SZ_8K }, .v = { 8, SZ_8K }) },
drivers/gpu/drm/exynos/exynos_drm_rotator.c
373
{ IPP_SIZE_LIMIT(AREA, .h.align = 2, .v.align = 2) },
drivers/gpu/drm/exynos/exynos_drm_rotator.c
377
{ IPP_SIZE_LIMIT(BUFFER, .h = { 32, SZ_64K }, .v = { 32, SZ_64K }) },
drivers/gpu/drm/exynos/exynos_drm_rotator.c
378
{ IPP_SIZE_LIMIT(AREA, .h.align = 8, .v.align = 8) },
drivers/gpu/drm/exynos/exynos_drm_rotator.c
382
{ IPP_SIZE_LIMIT(BUFFER, .h = { 32, SZ_64K }, .v = { 32, SZ_64K }) },
drivers/gpu/drm/exynos/exynos_drm_rotator.c
383
{ IPP_SIZE_LIMIT(AREA, .h.align = 8, .v.align = 8) },
drivers/gpu/drm/exynos/exynos_drm_rotator.c
387
{ IPP_SIZE_LIMIT(BUFFER, .h = { 32, SZ_32K }, .v = { 32, SZ_32K }) },
drivers/gpu/drm/exynos/exynos_drm_rotator.c
388
{ IPP_SIZE_LIMIT(AREA, .h.align = 8, .v.align = 8) },
drivers/gpu/drm/exynos/exynos_drm_scaler.c
588
{ IPP_SIZE_LIMIT(BUFFER, .h = { 16, SZ_8K }, .v = { 16, SZ_8K }) },
drivers/gpu/drm/exynos/exynos_drm_scaler.c
589
{ IPP_SIZE_LIMIT(AREA, .h.align = 2, .v.align = 2) },
drivers/gpu/drm/exynos/exynos_drm_scaler.c
591
.v = { 65536 * 1 / 4, 65536 * 16 }) },
drivers/gpu/drm/exynos/exynos_drm_scaler.c
595
{ IPP_SIZE_LIMIT(BUFFER, .h = { 16, SZ_8K }, .v = { 16, SZ_8K }) },
drivers/gpu/drm/exynos/exynos_drm_scaler.c
596
{ IPP_SIZE_LIMIT(AREA, .h.align = 2, .v.align = 1) },
drivers/gpu/drm/exynos/exynos_drm_scaler.c
598
.v = { 65536 * 1 / 4, 65536 * 16 }) },
drivers/gpu/drm/exynos/exynos_drm_scaler.c
602
{ IPP_SIZE_LIMIT(BUFFER, .h = { 16, SZ_8K }, .v = { 16, SZ_8K }) },
drivers/gpu/drm/exynos/exynos_drm_scaler.c
604
.v = { 65536 * 1 / 4, 65536 * 16 }) },
drivers/gpu/drm/exynos/exynos_drm_scaler.c
608
{ IPP_SIZE_LIMIT(BUFFER, .h = { 16, SZ_8K }, .v = { 16, SZ_8K })},
drivers/gpu/drm/exynos/exynos_drm_scaler.c
609
{ IPP_SIZE_LIMIT(AREA, .h.align = 16, .v.align = 16) },
drivers/gpu/drm/exynos/exynos_drm_scaler.c
610
{ IPP_SCALE_LIMIT(.h = {1, 1}, .v = {1, 1})},
drivers/gpu/drm/exynos/exynos_hdmi.c
1434
u8 v = enable ? HDMI_PHY_ENABLE_MODE_SET : HDMI_PHY_DISABLE_MODE_SET;
drivers/gpu/drm/exynos/exynos_hdmi.c
1437
writel(v, hdata->regs_hdmiphy + HDMIPHY5433_MODE_SET_DONE);
drivers/gpu/drm/exynos/regs-scaler.h
206
#define SCALER_SRC_CFG_SET_BYTE_SWAP(v) SCALER_SET(v, 6, 5)
drivers/gpu/drm/exynos/regs-scaler.h
208
#define SCALER_SRC_CFG_SET_COLOR_FORMAT(v) SCALER_SET(v, 4, 0)
drivers/gpu/drm/exynos/regs-scaler.h
232
#define SCALER_SRC_SPAN_SET_C_SPAN(v) SCALER_SET(v, 29, 16)
drivers/gpu/drm/exynos/regs-scaler.h
234
#define SCALER_SRC_SPAN_SET_Y_SPAN(v) SCALER_SET(v, 13, 0)
drivers/gpu/drm/exynos/regs-scaler.h
238
#define SCALER_SRC_Y_POS_SET_YH_POS(v) SCALER_SET(v, 31, 16)
drivers/gpu/drm/exynos/regs-scaler.h
240
#define SCALER_SRC_Y_POS_SET_YV_POS(v) SCALER_SET(v, 15, 0)
drivers/gpu/drm/exynos/regs-scaler.h
244
#define SCALER_SRC_WH_SET_WIDTH(v) SCALER_SET(v, 29, 16)
drivers/gpu/drm/exynos/regs-scaler.h
246
#define SCALER_SRC_WH_SET_HEIGHT(v) SCALER_SET(v, 13, 0)
drivers/gpu/drm/exynos/regs-scaler.h
250
#define SCALER_SRC_C_POS_SET_CH_POS(v) SCALER_SET(v, 31, 16)
drivers/gpu/drm/exynos/regs-scaler.h
252
#define SCALER_SRC_C_POS_SET_CV_POS(v) SCALER_SET(v, 15, 0)
drivers/gpu/drm/exynos/regs-scaler.h
256
#define SCALER_DST_CFG_SET_BYTE_SWAP(v) SCALER_SET(v, 6, 5)
drivers/gpu/drm/exynos/regs-scaler.h
258
#define SCALER_DST_CFG_SET_COLOR_FORMAT(v) SCALER_SET(v, 4, 0)
drivers/gpu/drm/exynos/regs-scaler.h
262
#define SCALER_DST_SPAN_SET_C_SPAN(v) SCALER_SET(v, 29, 16)
drivers/gpu/drm/exynos/regs-scaler.h
264
#define SCALER_DST_SPAN_SET_Y_SPAN(v) SCALER_SET(v, 13, 0)
drivers/gpu/drm/exynos/regs-scaler.h
268
#define SCALER_DST_WH_SET_WIDTH(v) SCALER_SET(v, 29, 16)
drivers/gpu/drm/exynos/regs-scaler.h
270
#define SCALER_DST_WH_SET_HEIGHT(v) SCALER_SET(v, 13, 0)
drivers/gpu/drm/exynos/regs-scaler.h
274
#define SCALER_DST_POS_SET_H_POS(v) SCALER_SET(v, 29, 16)
drivers/gpu/drm/exynos/regs-scaler.h
276
#define SCALER_DST_POS_SET_V_POS(v) SCALER_SET(v, 13, 0)
drivers/gpu/drm/exynos/regs-scaler.h
280
#define SCALER_H_RATIO_SET(v) SCALER_SET(v, 18, 0)
drivers/gpu/drm/exynos/regs-scaler.h
284
#define SCALER_V_RATIO_SET(v) SCALER_SET(v, 18, 0)
drivers/gpu/drm/exynos/regs-scaler.h
290
#define SCALER_ROT_CFG_SET_ROTMODE(v) SCALER_SET(v, 1, 0)
drivers/gpu/drm/exynos/regs-scaler.h
299
#define SCALER_COEF_SET(v, i) \
drivers/gpu/drm/exynos/regs-scaler.h
300
(((v) & 0x1ff) << SCALER_COEF_SHIFT(i))
drivers/gpu/drm/exynos/regs-scaler.h
304
#define SCALER_CSC_COEF_SET(v) SCALER_SET(v, 11, 0)
drivers/gpu/drm/exynos/regs-scaler.h
308
#define SCALER_DITH_CFG_SET_R_TYPE(v) SCALER_SET(v, 8, 6)
drivers/gpu/drm/exynos/regs-scaler.h
310
#define SCALER_DITH_CFG_SET_G_TYPE(v) SCALER_SET(v, 5, 3)
drivers/gpu/drm/exynos/regs-scaler.h
312
#define SCALER_DITH_CFG_SET_B_TYPE(v) SCALER_SET(v, 2, 0)
drivers/gpu/drm/exynos/regs-scaler.h
316
#define SCALER_TIMEOUT_CTRL_SET_TIMER_VALUE(v) SCALER_SET(v, 31, 16)
drivers/gpu/drm/exynos/regs-scaler.h
318
#define SCALER_TIMEOUT_CTRL_SET_TIMER_DIV(v) SCALER_SET(v, 7, 4)
drivers/gpu/drm/exynos/regs-scaler.h
327
#define SCALER_SRC_BLEND_COLOR_SET_SEL(v) SCALER_SET(v, 30, 29)
drivers/gpu/drm/exynos/regs-scaler.h
330
#define SCALER_SRC_BLEND_COLOR_SET_OP_SEL(v) SCALER_SET(v, 27, 24)
drivers/gpu/drm/exynos/regs-scaler.h
332
#define SCALER_SRC_BLEND_COLOR_SET_COLOR0(v) SCALER_SET(v, 23, 16)
drivers/gpu/drm/exynos/regs-scaler.h
334
#define SCALER_SRC_BLEND_COLOR_SET_COLOR1(v) SCALER_SET(v, 15, 8)
drivers/gpu/drm/exynos/regs-scaler.h
336
#define SCALER_SRC_BLEND_COLOR_SET_COLOR2(v) SCALER_SET(v, 7, 0)
drivers/gpu/drm/exynos/regs-scaler.h
341
#define SCALER_SRC_BLEND_ALPHA_SET_SEL(v) SCALER_SET(v, 30, 29)
drivers/gpu/drm/exynos/regs-scaler.h
344
#define SCALER_SRC_BLEND_ALPHA_SET_OP_SEL(v) SCALER_SET(v, 27, 24)
drivers/gpu/drm/exynos/regs-scaler.h
346
#define SCALER_SRC_BLEND_ALPHA_SET_ALPHA(v) SCALER_SET(v, 7, 0)
drivers/gpu/drm/exynos/regs-scaler.h
351
#define SCALER_DST_BLEND_COLOR_SET_SEL(v) SCALER_SET(v, 30, 29)
drivers/gpu/drm/exynos/regs-scaler.h
354
#define SCALER_DST_BLEND_COLOR_SET_OP_SEL(v) SCALER_SET(v, 27, 24)
drivers/gpu/drm/exynos/regs-scaler.h
356
#define SCALER_DST_BLEND_COLOR_SET_COLOR0(v) SCALER_SET(v, 23, 16)
drivers/gpu/drm/exynos/regs-scaler.h
358
#define SCALER_DST_BLEND_COLOR_SET_COLOR1(v) SCALER_SET(v, 15, 8)
drivers/gpu/drm/exynos/regs-scaler.h
360
#define SCALER_DST_BLEND_COLOR_SET_COLOR2(v) SCALER_SET(v, 7, 0)
drivers/gpu/drm/exynos/regs-scaler.h
365
#define SCALER_DST_BLEND_ALPHA_SET_SEL(v) SCALER_SET(v, 30, 29)
drivers/gpu/drm/exynos/regs-scaler.h
368
#define SCALER_DST_BLEND_ALPHA_SET_OP_SEL(v) SCALER_SET(v, 27, 24)
drivers/gpu/drm/exynos/regs-scaler.h
370
#define SCALER_DST_BLEND_ALPHA_SET_ALPHA(v) SCALER_SET(v, 7, 0)
drivers/gpu/drm/exynos/regs-scaler.h
374
#define SCALER_FILL_COLOR_SET_ALPHA(v) SCALER_SET(v, 31, 24)
drivers/gpu/drm/exynos/regs-scaler.h
376
#define SCALER_FILL_COLOR_SET_FILL_COLOR0(v) SCALER_SET(v, 23, 16)
drivers/gpu/drm/exynos/regs-scaler.h
378
#define SCALER_FILL_COLOR_SET_FILL_COLOR1(v) SCALER_SET(v, 15, 8)
drivers/gpu/drm/exynos/regs-scaler.h
380
#define SCALER_FILL_COLOR_SET_FILL_COLOR2(v) SCALER_SET(v, 7, 0)
drivers/gpu/drm/gma500/backlight.c
38
void gma_backlight_set(struct drm_device *dev, int v)
drivers/gpu/drm/gma500/backlight.c
42
dev_priv->backlight_level = v;
drivers/gpu/drm/gma500/backlight.c
44
dev_priv->ops->backlight_set(dev, v);
drivers/gpu/drm/gma500/cdv_intel_dp.c
1276
uint8_t v = 0;
drivers/gpu/drm/gma500/cdv_intel_dp.c
1284
if (this_v > v)
drivers/gpu/drm/gma500/cdv_intel_dp.c
1285
v = this_v;
drivers/gpu/drm/gma500/cdv_intel_dp.c
1290
if (v >= CDV_DP_VOLTAGE_MAX)
drivers/gpu/drm/gma500/cdv_intel_dp.c
1291
v = CDV_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED;
drivers/gpu/drm/gma500/cdv_intel_dp.c
1297
intel_dp->train_set[lane] = v | p;
drivers/gpu/drm/gma500/cdv_intel_dp.c
547
uint32_t v = 0;
drivers/gpu/drm/gma500/cdv_intel_dp.c
552
v |= ((uint32_t) src[i]) << ((3-i) * 8);
drivers/gpu/drm/gma500/cdv_intel_dp.c
553
return v;
drivers/gpu/drm/gma500/mmu.c
162
uint32_t *v;
drivers/gpu/drm/gma500/mmu.c
188
v = kmap_local_page(pd->dummy_pt);
drivers/gpu/drm/gma500/mmu.c
190
v[i] = pd->invalid_pte;
drivers/gpu/drm/gma500/mmu.c
192
kunmap_local(v);
drivers/gpu/drm/gma500/mmu.c
194
v = kmap_local_page(pd->p);
drivers/gpu/drm/gma500/mmu.c
196
v[i] = pd->invalid_pde;
drivers/gpu/drm/gma500/mmu.c
198
kunmap_local(v);
drivers/gpu/drm/gma500/mmu.c
264
void *v;
drivers/gpu/drm/gma500/mmu.c
283
v = kmap_atomic(pt->p);
drivers/gpu/drm/gma500/mmu.c
284
clf = (uint8_t *) v;
drivers/gpu/drm/gma500/mmu.c
285
ptes = (uint32_t *) v;
drivers/gpu/drm/gma500/mmu.c
297
kunmap_atomic(v);
drivers/gpu/drm/gma500/mmu.c
312
uint32_t *v;
drivers/gpu/drm/gma500/mmu.c
332
v = kmap_atomic(pd->p);
drivers/gpu/drm/gma500/mmu.c
334
v[index] = (page_to_pfn(pt->p) << 12) | pd->pd_mask;
drivers/gpu/drm/gma500/mmu.c
336
kunmap_atomic((void *) v);
drivers/gpu/drm/gma500/mmu.c
339
psb_mmu_clflush(pd->driver, (void *)&v[index]);
drivers/gpu/drm/gma500/mmu.c
343
pt->v = kmap_atomic(pt->p);
drivers/gpu/drm/gma500/mmu.c
360
pt->v = kmap_atomic(pt->p);
drivers/gpu/drm/gma500/mmu.c
367
uint32_t *v;
drivers/gpu/drm/gma500/mmu.c
369
kunmap_atomic(pt->v);
drivers/gpu/drm/gma500/mmu.c
371
v = kmap_atomic(pd->p);
drivers/gpu/drm/gma500/mmu.c
372
v[pt->index] = pd->invalid_pde;
drivers/gpu/drm/gma500/mmu.c
376
psb_mmu_clflush(pd->driver, (void *)&v[pt->index]);
drivers/gpu/drm/gma500/mmu.c
379
kunmap_atomic(v);
drivers/gpu/drm/gma500/mmu.c
390
pt->v[psb_mmu_pt_index(addr)] = pte;
drivers/gpu/drm/gma500/mmu.c
396
pt->v[psb_mmu_pt_index(addr)] = pt->pd->invalid_pte;
drivers/gpu/drm/gma500/mmu.c
515
psb_clflush(&pt->v[psb_mmu_pt_index(addr)]);
drivers/gpu/drm/gma500/mmu.h
40
uint32_t *v;
drivers/gpu/drm/gma500/oaktrail_lvds.c
129
dev->mode_config.scaling_mode_property, &v);
drivers/gpu/drm/gma500/oaktrail_lvds.c
132
if (v == DRM_MODE_SCALE_NO_SCALE)
drivers/gpu/drm/gma500/oaktrail_lvds.c
134
else if (v == DRM_MODE_SCALE_ASPECT) {
drivers/gpu/drm/gma500/oaktrail_lvds.c
92
uint64_t v = DRM_MODE_SCALE_FULLSCREEN;
drivers/gpu/drm/gma500/psb_drv.h
617
void gma_backlight_set(struct drm_device *dev, int v);
drivers/gpu/drm/i915/display/intel_color.c
3982
u32 v = (i * ((1 << 24) - 1)) / (lut_size - 1);
drivers/gpu/drm/i915/display/intel_color.c
3985
PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0), v);
drivers/gpu/drm/i915/display/intel_color.c
4036
u32 v = (i * ((1 << 24) - 1)) / (lut_size - 1);
drivers/gpu/drm/i915/display/intel_color.c
4039
PLANE_POST_CSC_GAMC_DATA_ENH(pipe, plane, 0), v);
drivers/gpu/drm/i915/display/intel_display_power_well.c
689
u32 v;
drivers/gpu/drm/i915/display/intel_display_power_well.c
699
v = intel_de_read(display, DC_STATE_EN);
drivers/gpu/drm/i915/display/intel_display_power_well.c
701
if (v != state) {
drivers/gpu/drm/i915/display/intel_display_power_well.c
711
if (v != state)
drivers/gpu/drm/i915/display/intel_display_power_well.c
714
state, v);
drivers/gpu/drm/i915/display/intel_dp_aux.c
38
u32 v = 0;
drivers/gpu/drm/i915/display/intel_dp_aux.c
43
v |= ((u32)src[i]) << ((3 - i) * 8);
drivers/gpu/drm/i915/display/intel_dp_aux.c
44
return v;
drivers/gpu/drm/i915/display/intel_dp_link_training.c
416
u8 v = 0;
drivers/gpu/drm/i915/display/intel_dp_link_training.c
424
v = drm_dp_get_adjust_request_voltage(link_status, lane);
drivers/gpu/drm/i915/display/intel_dp_link_training.c
428
v = max(v, drm_dp_get_adjust_request_voltage(link_status, lane));
drivers/gpu/drm/i915/display/intel_dp_link_training.c
437
v = min(v, dp_voltage_max(p));
drivers/gpu/drm/i915/display/intel_dp_link_training.c
440
if (v >= voltage_max)
drivers/gpu/drm/i915/display/intel_dp_link_training.c
441
v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
drivers/gpu/drm/i915/display/intel_dp_link_training.c
443
return v | p;
drivers/gpu/drm/i915/display/intel_dp_link_training.c
679
u8 v = (train_set_lane & DP_TRAIN_VOLTAGE_SWING_MASK) >>
drivers/gpu/drm/i915/display/intel_dp_link_training.c
687
if (v + p != 3)
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
449
memcpy(rep_send_ack->v, verify_repeater_out.v,
drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
352
u64 v,
drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
361
return v;
drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
363
y = div64_u64_rem(v, stride, &x);
drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
366
v = div64_u64_rem(y, 8, &y) * stride * 8;
drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
367
v += y * 512;
drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
368
v += div64_u64_rem(x, 512, &x) << 12;
drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
369
v += x;
drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
374
v = linear_x_y_to_ftiled_pos(x_pos, y_pos, stride, 32);
drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
382
v = div64_u64_rem(y, 32, &y) * stride * 32;
drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
383
v += y * ytile_span;
drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
384
v += div64_u64_rem(x, ytile_span, &x) * ytile_height;
drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
385
v += x;
drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
392
v ^= swizzle_bit(9, v);
drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
395
v ^= swizzle_bit(9, v) ^ swizzle_bit(10, v);
drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
398
v ^= swizzle_bit(9, v) ^ swizzle_bit(11, v);
drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
401
v ^= swizzle_bit(9, v) ^ swizzle_bit(10, v) ^ swizzle_bit(11, v);
drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
405
return v;
drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
437
u64 v = tiled_offset(buf->vma->vm->gt,
drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
441
if (vaddr[v / sizeof(*vaddr)] != buf->start_val + p)
drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c
108
iowrite32(v, &map[offset / sizeof(*map)]);
drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c
116
static int gtt_get(struct context *ctx, unsigned long offset, u32 *v)
drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c
142
*v = ioread32(&map[offset / sizeof(*map)]);
drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c
150
static int wc_set(struct context *ctx, unsigned long offset, u32 v)
drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c
165
map[offset / sizeof(*map)] = v;
drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c
173
static int wc_get(struct context *ctx, unsigned long offset, u32 *v)
drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c
188
*v = map[offset / sizeof(*map)];
drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c
194
static int gpu_set(struct context *ctx, unsigned long offset, u32 v)
drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c
226
*cs++ = v;
drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c
23
static int cpu_set(struct context *ctx, unsigned long offset, u32 v)
drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c
231
*cs++ = v;
drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c
235
*cs++ = v;
drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c
277
int (*set)(struct context *ctx, unsigned long offset, u32 v);
drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c
278
int (*get)(struct context *ctx, unsigned long offset, u32 *v);
drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c
41
*cpu = v;
drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c
54
static int cpu_get(struct context *ctx, unsigned long offset, u32 *v)
drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c
72
*v = *cpu;
drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c
82
static int gtt_set(struct context *ctx, unsigned long offset, u32 v)
drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
46
static u64 tiled_offset(const struct tile *tile, u64 v)
drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
51
return v;
drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
53
y = div64_u64_rem(v, tile->stride, &x);
drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
54
v = div64_u64_rem(y, tile->height, &y) * tile->stride * tile->height;
drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
57
v += y * tile->width;
drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
58
v += div64_u64_rem(x, tile->width, &x) << tile->size;
drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
59
v += x;
drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
64
v += y * ytile_span;
drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
65
v += div64_u64_rem(x, ytile_span, &x) * ytile_height;
drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
66
v += x;
drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
71
v += y * ytile_span;
drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
72
v += div64_u64_rem(x, ytile_span, &x) * ytile_height;
drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
73
v += x;
drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
78
v ^= swizzle_bit(9, v);
drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
81
v ^= swizzle_bit(9, v) ^ swizzle_bit(10, v);
drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
84
v ^= swizzle_bit(9, v) ^ swizzle_bit(11, v);
drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
87
v ^= swizzle_bit(9, v) ^ swizzle_bit(10, v) ^ swizzle_bit(11, v);
drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
91
return v;
drivers/gpu/drm/i915/gt/intel_gtt.h
625
#define fill_px(px, v) fill_page_dma(px_base(px), (v), PAGE_SIZE / sizeof(u64))
drivers/gpu/drm/i915/gt/intel_gtt.h
626
#define fill32_px(px, v) do { \
drivers/gpu/drm/i915/gt/intel_gtt.h
627
u64 v__ = lower_32_bits(v); \
drivers/gpu/drm/i915/gt/intel_lrc.c
87
u8 v;
drivers/gpu/drm/i915/gt/intel_lrc.c
90
v = *data++;
drivers/gpu/drm/i915/gt/intel_lrc.c
92
offset |= v & ~BIT(7);
drivers/gpu/drm/i915/gt/intel_lrc.c
93
} while (v & BIT(7));
drivers/gpu/drm/i915/gt/selftest_workarounds.c
505
int err = 0, i, v, sz;
drivers/gpu/drm/i915/gt/selftest_workarounds.c
578
for (v = 0; v < ARRAY_SIZE(values); v++) {
drivers/gpu/drm/i915/gt/selftest_workarounds.c
582
*cs++ = values[v];
drivers/gpu/drm/i915/gt/selftest_workarounds.c
591
for (v = 0; v < ARRAY_SIZE(values); v++) {
drivers/gpu/drm/i915/gt/selftest_workarounds.c
595
*cs++ = ~values[v];
drivers/gpu/drm/i915/gt/selftest_workarounds.c
671
for (v = 0; v < ARRAY_SIZE(values); v++) {
drivers/gpu/drm/i915/gt/selftest_workarounds.c
675
expect = reg_write(expect, values[v], rsvd);
drivers/gpu/drm/i915/gt/selftest_workarounds.c
681
for (v = 0; v < ARRAY_SIZE(values); v++) {
drivers/gpu/drm/i915/gt/selftest_workarounds.c
685
expect = reg_write(expect, ~values[v], rsvd);
drivers/gpu/drm/i915/gt/selftest_workarounds.c
704
for (v = 0; v < ARRAY_SIZE(values); v++) {
drivers/gpu/drm/i915/gt/selftest_workarounds.c
705
u32 w = values[v];
drivers/gpu/drm/i915/gt/selftest_workarounds.c
715
for (v = 0; v < ARRAY_SIZE(values); v++) {
drivers/gpu/drm/i915/gt/selftest_workarounds.c
716
u32 w = ~values[v];
drivers/gpu/drm/i915/gvt/cmd_parser.c
1305
u32 v;
drivers/gpu/drm/i915/gvt/cmd_parser.c
1311
v = (dword0 & GENMASK(21, 19)) >> 19;
drivers/gpu/drm/i915/gvt/cmd_parser.c
1312
if (drm_WARN_ON(&dev_priv->drm, v >= ARRAY_SIZE(gen8_plane_code)))
drivers/gpu/drm/i915/gvt/cmd_parser.c
1315
info->pipe = gen8_plane_code[v].pipe;
drivers/gpu/drm/i915/gvt/cmd_parser.c
1316
info->plane = gen8_plane_code[v].plane;
drivers/gpu/drm/i915/gvt/cmd_parser.c
1317
info->event = gen8_plane_code[v].event;
drivers/gpu/drm/i915/gvt/edid.c
48
#define gmbus1_total_byte_count(v) (((v) >> \
drivers/gpu/drm/i915/gvt/edid.c
50
#define gmbus1_target_addr(v) (((v) & 0xff) >> 1)
drivers/gpu/drm/i915/gvt/edid.c
51
#define gmbus1_target_index(v) (((v) >> 8) & 0xff)
drivers/gpu/drm/i915/gvt/edid.c
52
#define gmbus1_bus_cycle(v) (((v) >> 25) & 0x7)
drivers/gpu/drm/i915/gvt/gtt.c
867
int v = atomic_read(&spt->refcount);
drivers/gpu/drm/i915/gvt/gtt.c
869
trace_spt_refcount(spt->vgpu->id, "inc", spt, v, (v + 1));
drivers/gpu/drm/i915/gvt/gtt.c
875
int v = atomic_read(&spt->refcount);
drivers/gpu/drm/i915/gvt/gtt.c
877
trace_spt_refcount(spt->vgpu->id, "dec", spt, v, (v - 1));
drivers/gpu/drm/i915/gvt/gtt.c
91
#define gtt_init_entry(e, t, p, v) do { \
drivers/gpu/drm/i915/gvt/gtt.c
94
memcpy(&(e)->val64, &v, sizeof(v)); \
drivers/gpu/drm/i915/gvt/handlers.c
1686
u32 v = 0;
drivers/gpu/drm/i915/gvt/handlers.c
1689
v |= (1 << 0);
drivers/gpu/drm/i915/gvt/handlers.c
1692
v |= (1 << 8);
drivers/gpu/drm/i915/gvt/handlers.c
1695
v |= (1 << 16);
drivers/gpu/drm/i915/gvt/handlers.c
1698
v |= (1 << 24);
drivers/gpu/drm/i915/gvt/handlers.c
1700
vgpu_vreg(vgpu, offset) = v;
drivers/gpu/drm/i915/gvt/handlers.c
1797
u32 v = *(u32 *)p_data;
drivers/gpu/drm/i915/gvt/handlers.c
1800
v &= (1 << 31) | (1 << 29);
drivers/gpu/drm/i915/gvt/handlers.c
1802
v &= (1 << 31) | (1 << 29) | (1 << 9) |
drivers/gpu/drm/i915/gvt/handlers.c
1804
v |= (v >> 1);
drivers/gpu/drm/i915/gvt/handlers.c
1806
return intel_vgpu_default_mmio_write(vgpu, offset, &v, bytes);
drivers/gpu/drm/i915/gvt/handlers.c
1812
u32 v = *(u32 *)p_data;
drivers/gpu/drm/i915/gvt/handlers.c
1815
v &= (1 << 31) | (1 << 30);
drivers/gpu/drm/i915/gvt/handlers.c
1816
v & (1 << 31) ? (v |= (1 << 30)) : (v &= ~(1 << 30));
drivers/gpu/drm/i915/gvt/handlers.c
1818
vgpu_vreg(vgpu, offset) = v;
drivers/gpu/drm/i915/gvt/handlers.c
1826
u32 v = *(u32 *)p_data;
drivers/gpu/drm/i915/gvt/handlers.c
1828
if (v & BXT_DE_PLL_PLL_ENABLE)
drivers/gpu/drm/i915/gvt/handlers.c
1829
v |= BXT_DE_PLL_LOCK;
drivers/gpu/drm/i915/gvt/handlers.c
1831
vgpu_vreg(vgpu, offset) = v;
drivers/gpu/drm/i915/gvt/handlers.c
1839
u32 v = *(u32 *)p_data;
drivers/gpu/drm/i915/gvt/handlers.c
1841
if (v & PORT_PLL_ENABLE)
drivers/gpu/drm/i915/gvt/handlers.c
1842
v |= PORT_PLL_LOCK;
drivers/gpu/drm/i915/gvt/handlers.c
1844
vgpu_vreg(vgpu, offset) = v;
drivers/gpu/drm/i915/gvt/handlers.c
1852
u32 v = *(u32 *)p_data;
drivers/gpu/drm/i915/gvt/handlers.c
1853
u32 data = v & COMMON_RESET_DIS ? BXT_PHY_LANE_ENABLED : 0;
drivers/gpu/drm/i915/gvt/handlers.c
1865
vgpu_vreg(vgpu, offset) = v;
drivers/gpu/drm/i915/gvt/handlers.c
1873
u32 v = vgpu_vreg(vgpu, offset);
drivers/gpu/drm/i915/gvt/handlers.c
1875
v &= ~UNIQUE_TRANGE_EN_METHOD;
drivers/gpu/drm/i915/gvt/handlers.c
1877
vgpu_vreg(vgpu, offset) = v;
drivers/gpu/drm/i915/gvt/handlers.c
1885
u32 v = *(u32 *)p_data;
drivers/gpu/drm/i915/gvt/handlers.c
1888
vgpu_vreg(vgpu, offset - 0x600) = v;
drivers/gpu/drm/i915/gvt/handlers.c
1889
vgpu_vreg(vgpu, offset - 0x800) = v;
drivers/gpu/drm/i915/gvt/handlers.c
1891
vgpu_vreg(vgpu, offset - 0x400) = v;
drivers/gpu/drm/i915/gvt/handlers.c
1892
vgpu_vreg(vgpu, offset - 0x600) = v;
drivers/gpu/drm/i915/gvt/handlers.c
1895
vgpu_vreg(vgpu, offset) = v;
drivers/gpu/drm/i915/gvt/handlers.c
1903
u32 v = *(u32 *)p_data;
drivers/gpu/drm/i915/gvt/handlers.c
1905
if (v & BIT(0)) {
drivers/gpu/drm/i915/gvt/handlers.c
1912
if (v & BIT(1)) {
drivers/gpu/drm/i915/gvt/handlers.c
1920
vgpu_vreg(vgpu, offset) = v;
drivers/gpu/drm/i915/gvt/opregion.c
137
static void virt_vbt_generation(struct vbt *v)
drivers/gpu/drm/i915/gvt/opregion.c
141
memset(v, 0, sizeof(struct vbt));
drivers/gpu/drm/i915/gvt/opregion.c
143
v->header.signature[0] = '$';
drivers/gpu/drm/i915/gvt/opregion.c
144
v->header.signature[1] = 'V';
drivers/gpu/drm/i915/gvt/opregion.c
145
v->header.signature[2] = 'B';
drivers/gpu/drm/i915/gvt/opregion.c
146
v->header.signature[3] = 'T';
drivers/gpu/drm/i915/gvt/opregion.c
149
v->header.version = 155;
drivers/gpu/drm/i915/gvt/opregion.c
150
v->header.header_size = sizeof(v->header);
drivers/gpu/drm/i915/gvt/opregion.c
151
v->header.vbt_size = sizeof(struct vbt);
drivers/gpu/drm/i915/gvt/opregion.c
152
v->header.bdb_offset = offsetof(struct vbt, bdb_header);
drivers/gpu/drm/i915/gvt/opregion.c
154
strcpy(&v->bdb_header.signature[0], "BIOS_DATA_BLOCK");
drivers/gpu/drm/i915/gvt/opregion.c
155
v->bdb_header.version = 186; /* child_dev_size = 33 */
drivers/gpu/drm/i915/gvt/opregion.c
156
v->bdb_header.header_size = sizeof(v->bdb_header);
drivers/gpu/drm/i915/gvt/opregion.c
158
v->bdb_header.bdb_size = sizeof(struct vbt) - sizeof(struct vbt_header);
drivers/gpu/drm/i915/gvt/opregion.c
161
v->general_features_header.id = BDB_GENERAL_FEATURES;
drivers/gpu/drm/i915/gvt/opregion.c
162
v->general_features_header.size = sizeof(struct bdb_general_features);
drivers/gpu/drm/i915/gvt/opregion.c
163
v->general_features.int_crt_support = 0;
drivers/gpu/drm/i915/gvt/opregion.c
164
v->general_features.int_tv_support = 0;
drivers/gpu/drm/i915/gvt/opregion.c
168
v->general_definitions.child_dev_size =
drivers/gpu/drm/i915/gvt/opregion.c
170
v->general_definitions_header.id = BDB_GENERAL_DEFINITIONS;
drivers/gpu/drm/i915/gvt/opregion.c
172
v->general_definitions_header.size =
drivers/gpu/drm/i915/gvt/opregion.c
174
num_child * v->general_definitions.child_dev_size;
drivers/gpu/drm/i915/gvt/opregion.c
177
v->child0.handle = DEVICE_TYPE_EFP1;
drivers/gpu/drm/i915/gvt/opregion.c
178
v->child0.device_type = DEVICE_TYPE_DP;
drivers/gpu/drm/i915/gvt/opregion.c
179
v->child0.dvo_port = DVO_PORT_DPA;
drivers/gpu/drm/i915/gvt/opregion.c
180
v->child0.aux_channel = DP_AUX_A;
drivers/gpu/drm/i915/gvt/opregion.c
181
v->child0.dp_compat = true;
drivers/gpu/drm/i915/gvt/opregion.c
182
v->child0.integrated_encoder = true;
drivers/gpu/drm/i915/gvt/opregion.c
185
v->child1.handle = DEVICE_TYPE_EFP2;
drivers/gpu/drm/i915/gvt/opregion.c
186
v->child1.device_type = DEVICE_TYPE_DP;
drivers/gpu/drm/i915/gvt/opregion.c
187
v->child1.dvo_port = DVO_PORT_DPB;
drivers/gpu/drm/i915/gvt/opregion.c
188
v->child1.aux_channel = DP_AUX_B;
drivers/gpu/drm/i915/gvt/opregion.c
189
v->child1.dp_compat = true;
drivers/gpu/drm/i915/gvt/opregion.c
190
v->child1.integrated_encoder = true;
drivers/gpu/drm/i915/gvt/opregion.c
193
v->child2.handle = DEVICE_TYPE_EFP3;
drivers/gpu/drm/i915/gvt/opregion.c
194
v->child2.device_type = DEVICE_TYPE_DP;
drivers/gpu/drm/i915/gvt/opregion.c
195
v->child2.dvo_port = DVO_PORT_DPC;
drivers/gpu/drm/i915/gvt/opregion.c
196
v->child2.aux_channel = DP_AUX_C;
drivers/gpu/drm/i915/gvt/opregion.c
197
v->child2.dp_compat = true;
drivers/gpu/drm/i915/gvt/opregion.c
198
v->child2.integrated_encoder = true;
drivers/gpu/drm/i915/gvt/opregion.c
201
v->child3.handle = DEVICE_TYPE_EFP4;
drivers/gpu/drm/i915/gvt/opregion.c
202
v->child3.device_type = DEVICE_TYPE_DP;
drivers/gpu/drm/i915/gvt/opregion.c
203
v->child3.dvo_port = DVO_PORT_DPD;
drivers/gpu/drm/i915/gvt/opregion.c
204
v->child3.aux_channel = DP_AUX_D;
drivers/gpu/drm/i915/gvt/opregion.c
205
v->child3.dp_compat = true;
drivers/gpu/drm/i915/gvt/opregion.c
206
v->child3.integrated_encoder = true;
drivers/gpu/drm/i915/gvt/opregion.c
209
v->driver_features_header.id = BDB_DRIVER_FEATURES;
drivers/gpu/drm/i915/gvt/opregion.c
210
v->driver_features_header.size = sizeof(struct bdb_driver_features);
drivers/gpu/drm/i915/gvt/opregion.c
211
v->driver_features.lvds_config = BDB_DRIVER_FEATURE_NO_LVDS;
drivers/gpu/drm/i915/gvt/opregion.c
225
struct vbt v;
drivers/gpu/drm/i915/gvt/opregion.c
254
virt_vbt_generation(&v);
drivers/gpu/drm/i915/gvt/opregion.c
255
memcpy(buf + INTEL_GVT_OPREGION_VBT_OFFSET, &v, sizeof(struct vbt));
drivers/gpu/drm/i915/gvt/trace.h
172
TP_PROTO(int id, const char *tag, void *spt, int type, u64 v,
drivers/gpu/drm/i915/gvt/trace.h
175
TP_ARGS(id, tag, spt, type, v, index),
drivers/gpu/drm/i915/gvt/trace.h
184
id, tag, spt, type, v, index);
drivers/gpu/drm/i915/gvt/trace.h
209
TP_PROTO(int id, int page_id, void *gpt, int type, u64 v,
drivers/gpu/drm/i915/gvt/trace.h
212
TP_ARGS(id, page_id, gpt, type, v, index),
drivers/gpu/drm/i915/gvt/trace.h
221
id, page_id, gpt, type, v, index);
drivers/gpu/drm/i915/i915_vma.h
71
#define __i915_vma_flags(v) ((unsigned long *)&(v)->flags.counter)
drivers/gpu/drm/imagination/pvr_device.c
349
gpu_id->v, gpu_id->n, gpu_id->c, major);
drivers/gpu/drm/imagination/pvr_device.c
427
gpu_id->v = PVR_CR_FIELD_GET(bvnc, CORE_ID__PBVNC__VERSION_ID);
drivers/gpu/drm/imagination/pvr_device.c
436
gpu_id->v = PVR_CR_FIELD_GET(core_rev, CORE_REVISION_MINOR);
drivers/gpu/drm/imagination/pvr_device.c
503
gpu_id->v = user_bvnc_u16[1];
drivers/gpu/drm/imagination/pvr_device.h
496
#define PVR_PACKED_BVNC(b, v, n, c) \
drivers/gpu/drm/imagination/pvr_device.h
498
(((u64)(v) & GENMASK_ULL(15, 0)) << 32) | \
drivers/gpu/drm/imagination/pvr_device.h
524
return PVR_PACKED_BVNC(gpu_id->b, gpu_id->v, gpu_id->n, gpu_id->c);
drivers/gpu/drm/imagination/pvr_device.h
53
u16 b, v, n, c;
drivers/gpu/drm/imagination/pvr_device.h
531
gpu_id->v = (bvnc & GENMASK_ULL(47, 32)) >> 32;
drivers/gpu/drm/imagination/pvr_fw.c
133
fw_gpu_id.b, fw_gpu_id.v, fw_gpu_id.n, fw_gpu_id.c,
drivers/gpu/drm/imagination/pvr_fw.c
134
pvr_dev->gpu_id.b, pvr_dev->gpu_id.v, pvr_dev->gpu_id.n, pvr_dev->gpu_id.c);
drivers/gpu/drm/imagination/pvr_fw_trace.c
370
static void *fw_trace_seq_next(struct seq_file *s, void *v, loff_t *pos)
drivers/gpu/drm/imagination/pvr_fw_trace.c
381
static void fw_trace_seq_stop(struct seq_file *s, void *v)
drivers/gpu/drm/imagination/pvr_fw_trace.c
385
static int fw_trace_seq_show(struct seq_file *s, void *v)
drivers/gpu/drm/imx/dcss/dcss-dev.h
19
#define dcss_writel(v, c) writel((v), (c))
drivers/gpu/drm/imx/dcss/dcss-dev.h
21
#define dcss_set(v, c) writel((v), (c) + SET)
drivers/gpu/drm/imx/dcss/dcss-dev.h
22
#define dcss_clr(v, c) writel((v), (c) + CLR)
drivers/gpu/drm/imx/dcss/dcss-dev.h
23
#define dcss_toggle(v, c) writel((v), (c) + TGL)
drivers/gpu/drm/imx/dcss/dcss-dev.h
25
static inline void dcss_update(u32 v, u32 m, void __iomem *c)
drivers/gpu/drm/imx/dcss/dcss-dev.h
27
writel((readl(c) & ~(m)) | (v), (c));
drivers/gpu/drm/lima/lima_gp.c
83
u32 v;
drivers/gpu/drm/lima/lima_gp.c
88
err = readl_poll_timeout(ip->iomem + LIMA_GP_INT_RAWSTAT, v,
drivers/gpu/drm/lima/lima_gp.c
89
v & LIMA_GP_IRQ_RESET_COMPLETED,
drivers/gpu/drm/lima/lima_l2_cache.c
18
u32 v;
drivers/gpu/drm/lima/lima_l2_cache.c
20
err = readl_poll_timeout(ip->iomem + LIMA_L2_CACHE_STATUS, v,
drivers/gpu/drm/lima/lima_l2_cache.c
21
!(v & LIMA_L2_CACHE_STATUS_COMMAND_BUSY),
drivers/gpu/drm/lima/lima_mmu.c
137
u32 v;
drivers/gpu/drm/lima/lima_mmu.c
140
LIMA_MMU_STATUS, v,
drivers/gpu/drm/lima/lima_mmu.c
141
v & LIMA_MMU_STATUS_STALL_ACTIVE);
drivers/gpu/drm/lima/lima_mmu.c
149
LIMA_MMU_STATUS, v,
drivers/gpu/drm/lima/lima_mmu.c
150
!(v & LIMA_MMU_STATUS_STALL_ACTIVE));
drivers/gpu/drm/lima/lima_mmu.c
157
u32 v;
drivers/gpu/drm/lima/lima_mmu.c
165
LIMA_MMU_DTE_ADDR, v, v == 0);
drivers/gpu/drm/lima/lima_mmu.c
169
LIMA_MMU_STATUS, v,
drivers/gpu/drm/lima/lima_mmu.c
170
v & LIMA_MMU_STATUS_PAGING_ENABLED);
drivers/gpu/drm/lima/lima_mmu.c
66
u32 v;
drivers/gpu/drm/lima/lima_mmu.c
70
LIMA_MMU_DTE_ADDR, v, v == 0);
drivers/gpu/drm/lima/lima_mmu.c
78
LIMA_MMU_STATUS, v,
drivers/gpu/drm/lima/lima_mmu.c
79
v & LIMA_MMU_STATUS_PAGING_ENABLED);
drivers/gpu/drm/lima/lima_pmu.c
18
u32 v;
drivers/gpu/drm/lima/lima_pmu.c
21
v, v & LIMA_PMU_INT_CMD_MASK,
drivers/gpu/drm/logicvc/logicvc_regs.h
38
#define LOGICVC_BUFFER_SEL_VALUE(i, v) \
drivers/gpu/drm/logicvc/logicvc_regs.h
39
(BIT(10 + (i)) | ((v) << (2 * (i))))
drivers/gpu/drm/mgag200/mgag200_drv.h
105
#define WREG_GFX(reg, v) \
drivers/gpu/drm/mgag200/mgag200_drv.h
108
WREG8(GFX_DATA, v); \
drivers/gpu/drm/mgag200/mgag200_drv.h
120
#define WREG_DAC(reg, v) \
drivers/gpu/drm/mgag200/mgag200_drv.h
123
WREG8(DAC_DATA, v); \
drivers/gpu/drm/mgag200/mgag200_drv.h
34
#define WREG8(reg, v) iowrite8(v, ((void __iomem *)mdev->rmmio) + (reg))
drivers/gpu/drm/mgag200/mgag200_drv.h
36
#define WREG32(reg, v) iowrite32(v, ((void __iomem *)mdev->rmmio) + (reg))
drivers/gpu/drm/mgag200/mgag200_drv.h
43
#define WREG_MISC(v) \
drivers/gpu/drm/mgag200/mgag200_drv.h
44
WREG8(MGA_MISC_OUT, v)
drivers/gpu/drm/mgag200/mgag200_drv.h
46
#define RREG_MISC(v) \
drivers/gpu/drm/mgag200/mgag200_drv.h
47
((v) = RREG8(MGA_MISC_IN))
drivers/gpu/drm/mgag200/mgag200_drv.h
49
#define WREG_MISC_MASKED(v, mask) \
drivers/gpu/drm/mgag200/mgag200_drv.h
55
misc_ |= ((v) & mask_); \
drivers/gpu/drm/mgag200/mgag200_drv.h
59
#define WREG_ATTR(reg, v) \
drivers/gpu/drm/mgag200/mgag200_drv.h
63
WREG8(ATTR_DATA, v); \
drivers/gpu/drm/mgag200/mgag200_drv.h
66
#define RREG_SEQ(reg, v) \
drivers/gpu/drm/mgag200/mgag200_drv.h
69
v = RREG8(MGAREG_SEQ_DATA); \
drivers/gpu/drm/mgag200/mgag200_drv.h
72
#define WREG_SEQ(reg, v) \
drivers/gpu/drm/mgag200/mgag200_drv.h
75
WREG8(MGAREG_SEQ_DATA, v); \
drivers/gpu/drm/mgag200/mgag200_drv.h
78
#define RREG_CRT(reg, v) \
drivers/gpu/drm/mgag200/mgag200_drv.h
81
v = RREG8(MGAREG_CRTC_DATA); \
drivers/gpu/drm/mgag200/mgag200_drv.h
84
#define WREG_CRT(reg, v) \
drivers/gpu/drm/mgag200/mgag200_drv.h
87
WREG8(MGAREG_CRTC_DATA, v); \
drivers/gpu/drm/mgag200/mgag200_drv.h
90
#define RREG_ECRT(reg, v) \
drivers/gpu/drm/mgag200/mgag200_drv.h
93
v = RREG8(MGAREG_CRTCEXT_DATA); \
drivers/gpu/drm/mgag200/mgag200_drv.h
96
#define WREG_ECRT(reg, v) \
drivers/gpu/drm/mgag200/mgag200_drv.h
99
WREG8(MGAREG_CRTCEXT_DATA, v); \
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
1778
static int dpu_crtc_debugfs_state_show(struct seq_file *s, void *v)
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
730
static int dpu_debugfs_core_irq_show(struct seq_file *s, void *v)
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
100
static int dpu_debugfs_danger_stats_show(struct seq_file *s, void *v)
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
106
static int dpu_debugfs_safe_stats_show(struct seq_file *s, void *v)
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
20
s32 v;
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
22
v = (tmax - tmin) * percent;
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
23
v = S_DIV_ROUND_UP(v, 100) + tmin;
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
24
if (even && (v & 0x1))
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
25
return max_t(s32, min_result, v - 1);
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
27
return max_t(s32, min_result, v);
drivers/gpu/drm/nouveau/dispnv50/atom.h
52
} v;
drivers/gpu/drm/nouveau/dispnv50/head.c
303
m->v.active = mode->crtc_vtotal;
drivers/gpu/drm/nouveau/dispnv50/head.c
304
m->v.synce = mode->crtc_vsync_end - mode->crtc_vsync_start - 1;
drivers/gpu/drm/nouveau/dispnv50/head.c
305
m->v.blanke = mode->crtc_vblank_end - mode->crtc_vsync_start - 1;
drivers/gpu/drm/nouveau/dispnv50/head.c
306
m->v.blanks = m->v.blanke + mode->crtc_vdisplay;
drivers/gpu/drm/nouveau/dispnv50/head.c
309
blankus = (m->v.active - mode->crtc_vdisplay - 2) * m->h.active;
drivers/gpu/drm/nouveau/dispnv50/head.c
312
m->v.blankus = blankus;
drivers/gpu/drm/nouveau/dispnv50/head.c
315
m->v.blank2e = m->v.active + m->v.blanke;
drivers/gpu/drm/nouveau/dispnv50/head.c
316
m->v.blank2s = m->v.blank2e + mode->crtc_vdisplay;
drivers/gpu/drm/nouveau/dispnv50/head.c
317
m->v.active = (m->v.active * 2) + 1;
drivers/gpu/drm/nouveau/dispnv50/head.c
320
m->v.blank2e = 0;
drivers/gpu/drm/nouveau/dispnv50/head.c
321
m->v.blank2s = 1;
drivers/gpu/drm/nouveau/dispnv50/head507d.c
372
NVVAL(NV507D, HEAD_SET_RASTER_SIZE, HEIGHT, m->v.active),
drivers/gpu/drm/nouveau/dispnv50/head507d.c
376
NVVAL(NV507D, HEAD_SET_RASTER_SYNC_END, Y, m->v.synce),
drivers/gpu/drm/nouveau/dispnv50/head507d.c
380
NVVAL(NV507D, HEAD_SET_RASTER_BLANK_END, Y, m->v.blanke),
drivers/gpu/drm/nouveau/dispnv50/head507d.c
384
NVVAL(NV507D, HEAD_SET_RASTER_BLANK_START, Y, m->v.blanks),
drivers/gpu/drm/nouveau/dispnv50/head507d.c
387
NVVAL(NV507D, HEAD_SET_RASTER_VERT_BLANK2, YSTART, m->v.blank2s) |
drivers/gpu/drm/nouveau/dispnv50/head507d.c
388
NVVAL(NV507D, HEAD_SET_RASTER_VERT_BLANK2, YEND, m->v.blank2e),
drivers/gpu/drm/nouveau/dispnv50/head507d.c
391
NVVAL(NV507D, HEAD_SET_RASTER_VERT_BLANK_DMI, DURATION, m->v.blankus));
drivers/gpu/drm/nouveau/dispnv50/head907d.c
340
NVVAL(NV907D, HEAD_SET_RASTER_SIZE, HEIGHT, m->v.active),
drivers/gpu/drm/nouveau/dispnv50/head907d.c
344
NVVAL(NV907D, HEAD_SET_RASTER_SYNC_END, Y, m->v.synce),
drivers/gpu/drm/nouveau/dispnv50/head907d.c
348
NVVAL(NV907D, HEAD_SET_RASTER_BLANK_END, Y, m->v.blanke),
drivers/gpu/drm/nouveau/dispnv50/head907d.c
352
NVVAL(NV907D, HEAD_SET_RASTER_BLANK_START, Y, m->v.blanks),
drivers/gpu/drm/nouveau/dispnv50/head907d.c
355
NVVAL(NV907D, HEAD_SET_RASTER_VERT_BLANK2, YSTART, m->v.blank2s) |
drivers/gpu/drm/nouveau/dispnv50/head907d.c
356
NVVAL(NV907D, HEAD_SET_RASTER_VERT_BLANK2, YEND, m->v.blank2e));
drivers/gpu/drm/nouveau/dispnv50/headc37d.c
222
NVVAL(NVC37D, HEAD_SET_RASTER_SIZE, HEIGHT, m->v.active),
drivers/gpu/drm/nouveau/dispnv50/headc37d.c
226
NVVAL(NVC37D, HEAD_SET_RASTER_SYNC_END, Y, m->v.synce),
drivers/gpu/drm/nouveau/dispnv50/headc37d.c
230
NVVAL(NVC37D, HEAD_SET_RASTER_BLANK_END, Y, m->v.blanke),
drivers/gpu/drm/nouveau/dispnv50/headc37d.c
234
NVVAL(NVC37D, HEAD_SET_RASTER_BLANK_START, Y, m->v.blanks));
drivers/gpu/drm/nouveau/dispnv50/headc37d.c
237
PUSH_NVSQ(push, NVC37D, 0x2074 + (i * 0x400), m->v.blank2e << 16 | m->v.blank2s);
drivers/gpu/drm/nouveau/dispnv50/headc57d.c
214
NVVAL(NVC57D, HEAD_SET_RASTER_SIZE, HEIGHT, m->v.active),
drivers/gpu/drm/nouveau/dispnv50/headc57d.c
218
NVVAL(NVC57D, HEAD_SET_RASTER_SYNC_END, Y, m->v.synce),
drivers/gpu/drm/nouveau/dispnv50/headc57d.c
222
NVVAL(NVC57D, HEAD_SET_RASTER_BLANK_END, Y, m->v.blanke),
drivers/gpu/drm/nouveau/dispnv50/headc57d.c
226
NVVAL(NVC57D, HEAD_SET_RASTER_BLANK_START, Y, m->v.blanks));
drivers/gpu/drm/nouveau/dispnv50/headc57d.c
229
PUSH_NVSQ(push, NVC57D, 0x2074 + (i * 0x400), m->v.blank2e << 16 | m->v.blank2s);
drivers/gpu/drm/nouveau/dispnv50/headca7d.c
231
NVVAL(NVCA7D, HEAD_SET_RASTER_SIZE, HEIGHT, m->v.active),
drivers/gpu/drm/nouveau/dispnv50/headca7d.c
235
NVVAL(NVCA7D, HEAD_SET_RASTER_SYNC_END, Y, m->v.synce),
drivers/gpu/drm/nouveau/dispnv50/headca7d.c
239
NVVAL(NVCA7D, HEAD_SET_RASTER_BLANK_END, Y, m->v.blanke),
drivers/gpu/drm/nouveau/dispnv50/headca7d.c
243
NVVAL(NVCA7D, HEAD_SET_RASTER_BLANK_START, Y, m->v.blanks));
drivers/gpu/drm/nouveau/include/nvhw/drf.h
110
#define NVVAL_MW_SET_X(o,drf,v) do { \
drivers/gpu/drm/nouveau/include/nvhw/drf.h
111
(o)[DRF_LW_IDX((o),drf)] = DRF_LW_SET((o),drf,(v)); \
drivers/gpu/drm/nouveau/include/nvhw/drf.h
113
(o)[DRF_HW_IDX((o),drf)] = DRF_HW_SET((o),drf,(v)); \
drivers/gpu/drm/nouveau/include/nvhw/drf.h
115
#define NVVAL_MW_SET_N(X,o,d,r,f, v) NVVAL_MW_SET_X((o), d##_##r##_##f, (v))
drivers/gpu/drm/nouveau/include/nvhw/drf.h
116
#define NVVAL_MW_SET_I(X,o,d,r,f,i,v) NVVAL_MW_SET_X((o), d##_##r##_##f(i), (v))
drivers/gpu/drm/nouveau/include/nvhw/drf.h
120
#define NVDEF_MW_SET_N(X,o,d,r,f, v) NVVAL_MW_SET_X(o, d##_##r##_##f, d##_##r##_##f##_##v)
drivers/gpu/drm/nouveau/include/nvhw/drf.h
121
#define NVDEF_MW_SET_I(X,o,d,r,f,i,v) NVVAL_MW_SET_X(o, d##_##r##_##f(i), d##_##r##_##f##_##v)
drivers/gpu/drm/nouveau/include/nvhw/drf.h
133
#define DRF_WR_X(e,p,o,dr,v) e((p), (o), dr, (v))
drivers/gpu/drm/nouveau/include/nvhw/drf.h
134
#define DRF_WR_N(X,e,p,o,d,r, v) DRF_WR_X(e, (p), (o), d##_##r , (v))
drivers/gpu/drm/nouveau/include/nvhw/drf.h
135
#define DRF_WR_I(X,e,p,o,d,r,i,v) DRF_WR_X(e, (p), (o), d##_##r(i), (v))
drivers/gpu/drm/nouveau/include/nvhw/drf.h
140
#define DRF_MR_X(er,ew,ty,p,o,dr,m,v) ({ \
drivers/gpu/drm/nouveau/include/nvhw/drf.h
142
DRF_WR_X(ew, (p), (o), dr, (_t & ~(m)) | (v)); \
drivers/gpu/drm/nouveau/include/nvhw/drf.h
145
#define DRF_MR_N(X,er,ew,ty,p,o,d,r ,m,v) DRF_MR_X(er, ew, ty, (p), (o), d##_##r , (m), (v))
drivers/gpu/drm/nouveau/include/nvhw/drf.h
146
#define DRF_MR_I(X,er,ew,ty,p,o,d,r,i,m,v) DRF_MR_X(er, ew, ty, (p), (o), d##_##r(i), (m), (v))
drivers/gpu/drm/nouveau/include/nvhw/drf.h
158
#define DRF_WV_N(X,e,p,o,d,r, f,v) \
drivers/gpu/drm/nouveau/include/nvhw/drf.h
159
DRF_WR_X(e, (p), (o), d##_##r , NVVAL_X(d##_##r##_##f, (v)))
drivers/gpu/drm/nouveau/include/nvhw/drf.h
160
#define DRF_WV_I(X,e,p,o,d,r,i,f,v) \
drivers/gpu/drm/nouveau/include/nvhw/drf.h
161
DRF_WR_X(e, (p), (o), d##_##r(i), NVVAL_X(d##_##r##_##f, (v)))
drivers/gpu/drm/nouveau/include/nvhw/drf.h
166
#define DRF_WD_N(X,e,p,o,d,r, f,v) \
drivers/gpu/drm/nouveau/include/nvhw/drf.h
167
DRF_WR_X(e, (p), (o), d##_##r , NVVAL_X(d##_##r##_##f, d##_##r##_##f##_##v))
drivers/gpu/drm/nouveau/include/nvhw/drf.h
168
#define DRF_WD_I(X,e,p,o,d,r,i,f,v) \
drivers/gpu/drm/nouveau/include/nvhw/drf.h
169
DRF_WR_X(e, (p), (o), d##_##r(i), NVVAL_X(d##_##r##_##f, d##_##r##_##f##_##v))
drivers/gpu/drm/nouveau/include/nvhw/drf.h
174
#define DRF_MV_N(X,er,ew,ty,p,o,d,r, f,v) \
drivers/gpu/drm/nouveau/include/nvhw/drf.h
176
NVVAL_X(d##_##r##_##f, (v))), d##_##r##_##f)
drivers/gpu/drm/nouveau/include/nvhw/drf.h
177
#define DRF_MV_I(X,er,ew,ty,p,o,d,r,i,f,v) \
drivers/gpu/drm/nouveau/include/nvhw/drf.h
179
NVVAL_X(d##_##r##_##f, (v))), d##_##r##_##f)
drivers/gpu/drm/nouveau/include/nvhw/drf.h
184
#define DRF_MD_N(X,er,ew,ty,p,o,d,r, f,v) \
drivers/gpu/drm/nouveau/include/nvhw/drf.h
186
NVVAL_X(d##_##r##_##f, d##_##r##_##f##_##v)), d##_##r##_##f)
drivers/gpu/drm/nouveau/include/nvhw/drf.h
187
#define DRF_MD_I(X,er,ew,ty,p,o,d,r,i,f,v) \
drivers/gpu/drm/nouveau/include/nvhw/drf.h
189
NVVAL_X(d##_##r##_##f, d##_##r##_##f##_##v)), d##_##r##_##f)
drivers/gpu/drm/nouveau/include/nvhw/drf.h
194
#define DRF_TV_N(X,e,p,o,d,r, f,cmp,v) \
drivers/gpu/drm/nouveau/include/nvhw/drf.h
195
NVVAL_TEST_X(DRF_RD_X(e, (p), (o), d##_##r ), d##_##r##_##f, cmp, (v))
drivers/gpu/drm/nouveau/include/nvhw/drf.h
196
#define DRF_TV_I(X,e,p,o,d,r,i,f,cmp,v) \
drivers/gpu/drm/nouveau/include/nvhw/drf.h
197
NVVAL_TEST_X(DRF_RD_X(e, (p), (o), d##_##r(i)), d##_##r##_##f, cmp, (v))
drivers/gpu/drm/nouveau/include/nvhw/drf.h
202
#define DRF_TD_N(X,e,p,o,d,r, f,cmp,v) \
drivers/gpu/drm/nouveau/include/nvhw/drf.h
203
NVVAL_TEST_X(DRF_RD_X(e, (p), (o), d##_##r ), d##_##r##_##f, cmp, d##_##r##_##f##_##v)
drivers/gpu/drm/nouveau/include/nvhw/drf.h
204
#define DRF_TD_I(X,e,p,o,d,r,i,f,cmp,v) \
drivers/gpu/drm/nouveau/include/nvhw/drf.h
205
NVVAL_TEST_X(DRF_RD_X(e, (p), (o), d##_##r(i)), d##_##r##_##f, cmp, d##_##r##_##f##_##v)
drivers/gpu/drm/nouveau/include/nvhw/drf.h
46
#define DRF_LW_VAL(o,drf,v) (((v) & DRF_LW_MASK((o),drf)) << DRF_LW_LO((o),drf))
drivers/gpu/drm/nouveau/include/nvhw/drf.h
48
#define DRF_LW_SET(o,drf,v) (DRF_LW_CLR((o),drf) | DRF_LW_VAL((o),drf,(v)))
drivers/gpu/drm/nouveau/include/nvhw/drf.h
57
#define DRF_HW_VAL(o,drf,v) (((long long)(v) >> DRF_LW_BITS((o),drf)) & DRF_HW_SMASK((o),drf))
drivers/gpu/drm/nouveau/include/nvhw/drf.h
59
#define DRF_HW_SET(o,drf,v) (DRF_HW_CLR((o),drf) | DRF_HW_VAL((o),drf,(v)))
drivers/gpu/drm/nouveau/include/nvhw/drf.h
62
#define NVVAL_X(drf,v) (((v) & DRF_MASK(drf)) << DRF_LO(drf))
drivers/gpu/drm/nouveau/include/nvhw/drf.h
63
#define NVVAL_N(X,d,r,f, v) NVVAL_X(d##_##r##_##f, (v))
drivers/gpu/drm/nouveau/include/nvhw/drf.h
64
#define NVVAL_I(X,d,r,f,i,v) NVVAL_X(d##_##r##_##f(i), (v))
drivers/gpu/drm/nouveau/include/nvhw/drf.h
68
#define NVDEF_N(X,d,r,f, v) NVVAL_X(d##_##r##_##f, d##_##r##_##f##_##v)
drivers/gpu/drm/nouveau/include/nvhw/drf.h
69
#define NVDEF_I(X,d,r,f,i,v) NVVAL_X(d##_##r##_##f(i), d##_##r##_##f##_##v)
drivers/gpu/drm/nouveau/include/nvhw/drf.h
80
#define NVVAL_TEST_N(X,o,d,r,f, cmp,v) NVVAL_TEST_X(o, d##_##r##_##f , cmp, (v))
drivers/gpu/drm/nouveau/include/nvhw/drf.h
81
#define NVVAL_TEST_I(X,o,d,r,f,i,cmp,v) NVVAL_TEST_X(o, d##_##r##_##f(i), cmp, (v))
drivers/gpu/drm/nouveau/include/nvhw/drf.h
85
#define NVDEF_TEST_N(X,o,d,r,f, cmp,v) NVVAL_TEST_X(o, d##_##r##_##f , cmp, d##_##r##_##f##_##v)
drivers/gpu/drm/nouveau/include/nvhw/drf.h
86
#define NVDEF_TEST_I(X,o,d,r,f,i,cmp,v) NVVAL_TEST_X(o, d##_##r##_##f(i), cmp, d##_##r##_##f##_##v)
drivers/gpu/drm/nouveau/include/nvhw/drf.h
90
#define NVVAL_SET_X(o,drf,v) (((o) & ~DRF_SMASK(drf)) | NVVAL_X(drf, (v)))
drivers/gpu/drm/nouveau/include/nvhw/drf.h
91
#define NVVAL_SET_N(X,o,d,r,f, v) NVVAL_SET_X(o, d##_##r##_##f, (v))
drivers/gpu/drm/nouveau/include/nvhw/drf.h
92
#define NVVAL_SET_I(X,o,d,r,f,i,v) NVVAL_SET_X(o, d##_##r##_##f(i), (v))
drivers/gpu/drm/nouveau/include/nvhw/drf.h
96
#define NVDEF_SET_N(X,o,d,r,f, v) NVVAL_SET_X(o, d##_##r##_##f, d##_##r##_##f##_##v)
drivers/gpu/drm/nouveau/include/nvhw/drf.h
97
#define NVDEF_SET_I(X,o,d,r,f,i,v) NVVAL_SET_X(o, d##_##r##_##f(i), d##_##r##_##f##_##v)
drivers/gpu/drm/nouveau/include/nvif/os.h
50
#define iowrite64_native(v,p) do { \
drivers/gpu/drm/nouveau/include/nvif/os.h
52
u64 _v = (v); \
drivers/gpu/drm/nouveau/include/nvkm/core/device.h
128
#define nvkm_wr08(d,a,v) iowrite8((v), (d)->pri + (a))
drivers/gpu/drm/nouveau/include/nvkm/core/device.h
129
#define nvkm_wr16(d,a,v) iowrite16_native((v), (d)->pri + (a))
drivers/gpu/drm/nouveau/include/nvkm/core/device.h
130
#define nvkm_wr32(d,a,v) iowrite32_native((v), (d)->pri + (a))
drivers/gpu/drm/nouveau/include/nvkm/core/device.h
131
#define nvkm_mask(d,a,m,v) ({ \
drivers/gpu/drm/nouveau/include/nvkm/core/device.h
134
nvkm_wr32(_device, _addr, (_temp & ~(m)) | (v)); \
drivers/gpu/drm/nouveau/include/nvkm/core/memory.h
65
#define nvkm_memory_boot(p,v) (p)->func->boot((p),(v))
drivers/gpu/drm/nouveau/nvif/fifo.c
32
} v;
drivers/gpu/drm/nouveau/nvif/fifo.c
42
a->m.count = sizeof(a->v) / sizeof(a->v.runlists);
drivers/gpu/drm/nouveau/nvif/fifo.c
43
a->v.runlists.mthd = NV_DEVICE_HOST_RUNLISTS;
drivers/gpu/drm/nouveau/nvif/fifo.c
44
for (i = 0; i < ARRAY_SIZE(a->v.runlist); i++) {
drivers/gpu/drm/nouveau/nvif/fifo.c
45
a->v.runlist[i].mthd = NV_DEVICE_HOST_RUNLIST_ENGINES;
drivers/gpu/drm/nouveau/nvif/fifo.c
46
a->v.runlist[i].data = i;
drivers/gpu/drm/nouveau/nvif/fifo.c
53
device->runlists = fls64(a->v.runlists.data);
drivers/gpu/drm/nouveau/nvif/fifo.c
61
if (a->v.runlist[i].mthd != NV_DEVICE_INFO_INVALID)
drivers/gpu/drm/nouveau/nvif/fifo.c
62
device->runlist[i].engines = a->v.runlist[i].data;
drivers/gpu/drm/nouveau/nvkm/engine/disp/g94.c
54
g94_sor_dp_audio_sym(struct nvkm_ior *sor, int head, u16 h, u32 v)
drivers/gpu/drm/nouveau/nvkm/engine/disp/g94.c
60
nvkm_mask(device, 0x61c1ec + soff, 0x00ffffff, v);
drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c
100
nvkm_mask(device, 0x616624 + hoff, 0x00ffffff, v);
drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c
94
gf119_sor_dp_audio_sym(struct nvkm_ior *sor, int head, u16 h, u32 v)
drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c
63
gv100_sor_dp_audio_sym(struct nvkm_ior *sor, int head, u16 h, u32 v)
drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c
69
nvkm_mask(device, 0x61656c + hoff, 0x00ffffff, v);
drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.h
92
void (*audio_sym)(struct nvkm_ior *, int head, u16 h, u32 v);
drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c
1167
u64 h, v;
drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c
1176
v = head->asy.vblanks - head->asy.vblanke - 25;
drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c
1177
v = v * linkKBps;
drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c
1178
do_div(v, khz);
drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c
1179
v = v - ((36 / ior->dp.nr) + 3) - 1;
drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c
1181
ior->func->dp->audio_sym(ior, head->id, h, v);
drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c
506
long v;
drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c
509
if (!kstrtol(mode, 0, &v)) {
drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c
510
ret = nvkm_clk_ustate_update(clk, v);
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv05.c
106
v = nvkm_rd32(device, NV04_PFB_BOOT_0) & NV04_PFB_BOOT_0_RAM_AMOUNT;
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv05.c
108
if (v == NV04_PFB_BOOT_0_RAM_AMOUNT_32MB &&
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv05.c
114
if (v == NV04_PFB_BOOT_0_RAM_AMOUNT_16MB &&
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv05.c
54
int i, v;
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.h
315
#define VMM_PRINT(l,v,p,f,a...) do { \
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.h
316
struct nvkm_vmm *_vmm = (v); \
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.h
322
#define VMM_DEBUG(v,f,a...) VMM_PRINT(NV_DBG_DEBUG, (v), info, f, ##a)
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.h
323
#define VMM_TRACE(v,f,a...) VMM_PRINT(NV_DBG_TRACE, (v), info, f, ##a)
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.h
324
#define VMM_SPAM(v,f,a...) VMM_PRINT(NV_DBG_SPAM , (v), dbg, f, ##a)
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.h
364
#define VMM_XO(m,v,o,d,c,b,fn,f,a...) do { \
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.h
366
VMM_SPAM((v), " %010llx "f, (m)->addr + _pteo, _data, ##a); \
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.h
370
#define VMM_WO032(m,v,o,d) VMM_XO((m),(v),(o),(d), 1, 32, WO, "%08x")
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.h
371
#define VMM_FO032(m,v,o,d,c) \
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.h
372
VMM_XO((m),(v),(o),(d),(c), 32, FO, "%08x %08x", (c))
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.h
374
#define VMM_WO064(m,v,o,d) VMM_XO((m),(v),(o),(d), 1, 64, WO, "%016llx")
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.h
375
#define VMM_FO064(m,v,o,d,c) \
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.h
376
VMM_XO((m),(v),(o),(d),(c), 64, FO, "%016llx %08x", (c))
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.h
378
#define VMM_XO128(m,v,o,lo,hi,c,f,a...) do { \
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.h
381
VMM_SPAM((v), " %010llx %016llx%016llx"f, _addr, (hi), (lo), ##a); \
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.h
389
#define VMM_WO128(m,v,o,lo,hi) VMM_XO128((m),(v),(o),(lo),(hi), 1, "")
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.h
390
#define VMM_FO128(m,v,o,lo,hi,c) do { \
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.h
392
VMM_XO128((m),(v),(o),(lo),(hi),(c), " %08x", (c)); \
drivers/gpu/drm/omapdrm/dss/dispc.c
1373
u32 v;
drivers/gpu/drm/omapdrm/dss/dispc.c
1375
v = dispc_read_reg(dispc, DISPC_GLOBAL_BUFFER);
drivers/gpu/drm/omapdrm/dss/dispc.c
1377
v = FLD_MOD(v, 4, 2, 0); /* GFX BUF top to WB */
drivers/gpu/drm/omapdrm/dss/dispc.c
1378
v = FLD_MOD(v, 4, 5, 3); /* GFX BUF bottom to WB */
drivers/gpu/drm/omapdrm/dss/dispc.c
1379
v = FLD_MOD(v, 0, 26, 24); /* WB BUF top to GFX */
drivers/gpu/drm/omapdrm/dss/dispc.c
1380
v = FLD_MOD(v, 0, 29, 27); /* WB BUF bottom to GFX */
drivers/gpu/drm/omapdrm/dss/dispc.c
1382
dispc_write_reg(dispc, DISPC_GLOBAL_BUFFER, v);
drivers/gpu/drm/omapdrm/dss/dispc.c
3671
u32 v = table[i];
drivers/gpu/drm/omapdrm/dss/dispc.c
3674
v |= i << 24;
drivers/gpu/drm/omapdrm/dss/dispc.c
3676
v |= 1 << 31;
drivers/gpu/drm/omapdrm/dss/dispc.c
3678
dispc_write_reg(dispc, gdesc->reg, v);
drivers/gpu/drm/omapdrm/dss/dispc.c
813
u32 v;
drivers/gpu/drm/omapdrm/dss/dispc.c
814
v = FLD_VAL(v_coef[i].hc0_vc00, 7, 0)
drivers/gpu/drm/omapdrm/dss/dispc.c
817
dispc_ovl_write_firv_reg(dispc, plane, i, v);
drivers/gpu/drm/omapdrm/dss/dispc.c
819
dispc_ovl_write_firv2_reg(dispc, plane, i, v);
drivers/gpu/drm/omapdrm/dss/dsi.c
1662
u8 v;
drivers/gpu/drm/omapdrm/dss/dsi.c
1671
v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
drivers/gpu/drm/omapdrm/dss/dsi.c
1672
r |= v << (8 * i);
drivers/gpu/drm/omapdrm/dss/dsi.c
1694
u8 v;
drivers/gpu/drm/omapdrm/dss/dsi.c
1703
v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
drivers/gpu/drm/omapdrm/dss/dsi.c
1704
r |= v << (8 * i);
drivers/gpu/drm/omapdrm/dss/hdmi.h
286
u32 t = 0, v;
drivers/gpu/drm/omapdrm/dss/hdmi.h
287
while (val != (v = REG_GET(base_addr, idx, b2, b1))) {
drivers/gpu/drm/omapdrm/dss/hdmi.h
289
return v;
drivers/gpu/drm/omapdrm/dss/hdmi.h
292
return v;
drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c
247
u32 v;
drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c
255
v = hdmi_read_reg(core->base, HDMI_CEC_CA_7_0);
drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c
256
v |= 1 << log_addr;
drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c
257
hdmi_write_reg(core->base, HDMI_CEC_CA_7_0, v);
drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c
259
v = hdmi_read_reg(core->base, HDMI_CEC_CA_15_8);
drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c
260
v |= 1 << (log_addr - 8);
drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c
261
hdmi_write_reg(core->base, HDMI_CEC_CA_15_8, v);
drivers/gpu/drm/omapdrm/dss/hdmi5.c
76
u32 v;
drivers/gpu/drm/omapdrm/dss/hdmi5.c
91
v = hdmi_read_reg(hdmi->phy.base, HDMI_TXPHY_PAD_CFG_CTRL);
drivers/gpu/drm/omapdrm/dss/hdmi5.c
92
v = FLD_MOD(v, 1, 15, 15); /* FORCE_RXDET_HIGH */
drivers/gpu/drm/omapdrm/dss/hdmi5.c
93
v = FLD_MOD(v, 0, 14, 7); /* RXDET_LINE */
drivers/gpu/drm/omapdrm/dss/hdmi5.c
94
hdmi_write_reg(hdmi->phy.base, HDMI_TXPHY_PAD_CFG_CTRL, v);
drivers/gpu/drm/omapdrm/dss/hdmi5_core.c
37
unsigned int v;
drivers/gpu/drm/omapdrm/dss/hdmi5_core.c
52
v = DIV_ROUND_UP_ULL(ss_scl_high * sfr, 1000000);
drivers/gpu/drm/omapdrm/dss/hdmi5_core.c
54
(v >> 8) & 0xff, 7, 0);
drivers/gpu/drm/omapdrm/dss/hdmi5_core.c
56
v & 0xff, 7, 0);
drivers/gpu/drm/omapdrm/dss/hdmi5_core.c
59
v = DIV_ROUND_UP_ULL(ss_scl_low * sfr, 1000000);
drivers/gpu/drm/omapdrm/dss/hdmi5_core.c
61
(v >> 8) & 0xff, 7, 0);
drivers/gpu/drm/omapdrm/dss/hdmi5_core.c
63
v & 0xff, 7, 0);
drivers/gpu/drm/omapdrm/dss/hdmi5_core.c
66
v = DIV_ROUND_UP_ULL(fs_scl_high * sfr, 1000000);
drivers/gpu/drm/omapdrm/dss/hdmi5_core.c
68
(v >> 8) & 0xff, 7, 0);
drivers/gpu/drm/omapdrm/dss/hdmi5_core.c
70
v & 0xff, 7, 0);
drivers/gpu/drm/omapdrm/dss/hdmi5_core.c
73
v = DIV_ROUND_UP_ULL(fs_scl_low * sfr, 1000000);
drivers/gpu/drm/omapdrm/dss/hdmi5_core.c
75
(v >> 8) & 0xff, 7, 0);
drivers/gpu/drm/omapdrm/dss/hdmi5_core.c
77
v & 0xff, 7, 0);
drivers/gpu/drm/omapdrm/dss/hdmi5_core.c
80
v = DIV_ROUND_UP_ULL(sda_hold * sfr, 1000000);
drivers/gpu/drm/omapdrm/dss/hdmi5_core.c
81
REG_FLD_MOD(base, HDMI_CORE_I2CM_SDA_HOLD_ADDR, v & 0xff, 7, 0);
drivers/gpu/drm/omapdrm/dss/hdmi_wp.c
118
u32 v;
drivers/gpu/drm/omapdrm/dss/hdmi_wp.c
122
v = hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS_RAW);
drivers/gpu/drm/omapdrm/dss/hdmi_wp.c
123
if (v & HDMI_IRQ_VIDEO_FRAME_DONE)
drivers/gpu/drm/omapdrm/dss/pll.c
371
u32 v = readl_relaxed(pll->base + PLL_STATUS);
drivers/gpu/drm/omapdrm/dss/pll.c
372
v &= hsdiv_ack_mask;
drivers/gpu/drm/omapdrm/dss/pll.c
373
if (v == hsdiv_ack_mask)
drivers/gpu/drm/omapdrm/omap_dmm_tiler.c
154
u32 v;
drivers/gpu/drm/omapdrm/omap_dmm_tiler.c
158
v = dmm_read_wa(dmm, reg);
drivers/gpu/drm/omapdrm/omap_dmm_tiler.c
161
return v;
drivers/gpu/drm/panthor/panthor_fw.c
210
#define CSF_IFACE_VERSION_MAJOR(v) ((v) >> 24)
drivers/gpu/drm/panthor/panthor_fw.c
211
#define CSF_IFACE_VERSION_MINOR(v) (((v) >> 16) & 0xff)
drivers/gpu/drm/panthor/panthor_fw.c
212
#define CSF_IFACE_VERSION_PATCH(v) ((v) & 0xffff)
drivers/gpu/drm/radeon/atombios_dp.c
256
u8 v = 0;
drivers/gpu/drm/radeon/atombios_dp.c
269
if (this_v > v)
drivers/gpu/drm/radeon/atombios_dp.c
270
v = this_v;
drivers/gpu/drm/radeon/atombios_dp.c
275
if (v >= DP_VOLTAGE_MAX)
drivers/gpu/drm/radeon/atombios_dp.c
276
v |= DP_TRAIN_MAX_SWING_REACHED;
drivers/gpu/drm/radeon/atombios_dp.c
282
voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
drivers/gpu/drm/radeon/atombios_dp.c
286
train_set[lane] = v | p;
drivers/gpu/drm/radeon/btc_dpm.c
1171
if (*voltage < table->entries[i].v)
drivers/gpu/drm/radeon/btc_dpm.c
1172
*voltage = (u16)((table->entries[i].v < max_voltage) ?
drivers/gpu/drm/radeon/btc_dpm.c
1173
table->entries[i].v : max_voltage);
drivers/gpu/drm/radeon/btc_dpm.c
2562
rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
drivers/gpu/drm/radeon/btc_dpm.c
2564
rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 800;
drivers/gpu/drm/radeon/btc_dpm.c
2566
rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 800;
drivers/gpu/drm/radeon/btc_dpm.c
2568
rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 800;
drivers/gpu/drm/radeon/ci_dpm.c
2083
voltage_table->entries[i].value = voltage_dependency_table->entries[i].v;
drivers/gpu/drm/radeon/ci_dpm.c
2299
rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
drivers/gpu/drm/radeon/ci_dpm.c
2316
rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
drivers/gpu/drm/radeon/ci_dpm.c
2398
*voltage = allowed_clock_voltage_table->entries[i].v;
drivers/gpu/drm/radeon/ci_dpm.c
2403
*voltage = allowed_clock_voltage_table->entries[i-1].v;
drivers/gpu/drm/radeon/ci_dpm.c
2620
rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
drivers/gpu/drm/radeon/ci_dpm.c
2661
(u16)rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
drivers/gpu/drm/radeon/ci_dpm.c
2694
rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].v;
drivers/gpu/drm/radeon/ci_dpm.c
2726
rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
drivers/gpu/drm/radeon/ci_dpm.c
3093
if (ulv_voltage > rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v)
drivers/gpu/drm/radeon/ci_dpm.c
3097
rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage;
drivers/gpu/drm/radeon/ci_dpm.c
3099
if (ulv_voltage > rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v)
drivers/gpu/drm/radeon/ci_dpm.c
3103
((rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage) *
drivers/gpu/drm/radeon/ci_dpm.c
3461
allowed_sclk_vddc_table->entries[i].v;
drivers/gpu/drm/radeon/ci_dpm.c
3471
allowed_mclk_table->entries[i].v;
drivers/gpu/drm/radeon/ci_dpm.c
3479
allowed_mclk_table->entries[i].v;
drivers/gpu/drm/radeon/ci_dpm.c
3749
requested_voltage = disp_voltage_table->entries[i].v;
drivers/gpu/drm/radeon/ci_dpm.c
3753
if (requested_voltage <= vddc_table->entries[i].v) {
drivers/gpu/drm/radeon/ci_dpm.c
3754
requested_voltage = vddc_table->entries[i].v;
drivers/gpu/drm/radeon/ci_dpm.c
3896
if (rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
drivers/gpu/drm/radeon/ci_dpm.c
3944
if (rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
drivers/gpu/drm/radeon/ci_dpm.c
3977
if (rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
drivers/gpu/drm/radeon/ci_dpm.c
4008
if (rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
drivers/gpu/drm/radeon/ci_dpm.c
4884
pi->min_vddc_in_pp_table = allowed_sclk_vddc_table->entries[0].v;
drivers/gpu/drm/radeon/ci_dpm.c
4886
allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
drivers/gpu/drm/radeon/ci_dpm.c
4888
pi->min_vddci_in_pp_table = allowed_mclk_vddci_table->entries[0].v;
drivers/gpu/drm/radeon/ci_dpm.c
4890
allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v;
drivers/gpu/drm/radeon/ci_dpm.c
4897
allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
drivers/gpu/drm/radeon/ci_dpm.c
4899
allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v;
drivers/gpu/drm/radeon/ci_dpm.c
4939
ci_patch_with_vddc_leakage(rdev, &table->entries[i].v);
drivers/gpu/drm/radeon/ci_dpm.c
4950
ci_patch_with_vddci_leakage(rdev, &table->entries[i].v);
drivers/gpu/drm/radeon/ci_dpm.c
4961
ci_patch_with_vddc_leakage(rdev, &table->entries[i].v);
drivers/gpu/drm/radeon/ci_dpm.c
4972
ci_patch_with_vddc_leakage(rdev, &table->entries[i].v);
drivers/gpu/drm/radeon/ci_dpm.c
5750
rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
drivers/gpu/drm/radeon/ci_dpm.c
5752
rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
drivers/gpu/drm/radeon/ci_dpm.c
5754
rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
drivers/gpu/drm/radeon/ci_dpm.c
5756
rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
drivers/gpu/drm/radeon/cik.c
1748
void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v)
drivers/gpu/drm/radeon/cik.c
1751
writel(v, rdev->doorbell.ptr + index);
drivers/gpu/drm/radeon/cik.c
191
void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v)
drivers/gpu/drm/radeon/cik.c
197
WREG32(CIK_DIDT_IND_DATA, (v));
drivers/gpu/drm/radeon/cik.c
250
void cik_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
drivers/gpu/drm/radeon/cik.c
257
WREG32(PCIE_DATA, v);
drivers/gpu/drm/radeon/cikd.h
1689
#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
drivers/gpu/drm/radeon/dce6_afmt.c
49
u32 block_offset, u32 reg, u32 v)
drivers/gpu/drm/radeon/dce6_afmt.c
59
WREG32(AZ_F0_CODEC_ENDPOINT_DATA + block_offset, v);
drivers/gpu/drm/radeon/dce6_afmt.h
36
void dce6_endpoint_wreg(struct radeon_device *rdev, u32 offset, u32 reg, u32 v);
drivers/gpu/drm/radeon/evergreen.c
113
void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v)
drivers/gpu/drm/radeon/evergreen.c
119
WREG32(EVERGREEN_PIF_PHY1_DATA, (v));
drivers/gpu/drm/radeon/evergreen.c
1281
u16 v;
drivers/gpu/drm/radeon/evergreen.c
1284
v = ffs(readrq) - 8;
drivers/gpu/drm/radeon/evergreen.c
1288
if ((v == 0) || (v == 6) || (v == 7))
drivers/gpu/drm/radeon/evergreen.c
69
void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v)
drivers/gpu/drm/radeon/evergreen.c
75
WREG32(EVERGREEN_CG_IND_DATA, (v));
drivers/gpu/drm/radeon/evergreen.c
91
void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v)
drivers/gpu/drm/radeon/evergreen.c
97
WREG32(EVERGREEN_PIF_PHY0_DATA, (v));
drivers/gpu/drm/radeon/evergreend.h
1541
#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
drivers/gpu/drm/radeon/kv_dpm.c
1794
uvd_table->entries[i].v =
drivers/gpu/drm/radeon/kv_dpm.c
1796
uvd_table->entries[i].v);
drivers/gpu/drm/radeon/kv_dpm.c
1801
vce_table->entries[i].v =
drivers/gpu/drm/radeon/kv_dpm.c
1803
vce_table->entries[i].v);
drivers/gpu/drm/radeon/kv_dpm.c
1808
samu_table->entries[i].v =
drivers/gpu/drm/radeon/kv_dpm.c
1810
samu_table->entries[i].v);
drivers/gpu/drm/radeon/kv_dpm.c
1815
acp_table->entries[i].v =
drivers/gpu/drm/radeon/kv_dpm.c
1817
acp_table->entries[i].v);
drivers/gpu/drm/radeon/kv_dpm.c
1910
(kv_convert_8bit_index_to_voltage(rdev, table->entries[i].v) <=
drivers/gpu/drm/radeon/kv_dpm.c
2158
kv_convert_8bit_index_to_voltage(rdev, table->entries[i].v)))
drivers/gpu/drm/radeon/kv_dpm.c
2164
table->entries[i].v);
drivers/gpu/drm/radeon/kv_dpm.c
403
return vddc_sclk_table->entries[vid_2bit].v;
drivers/gpu/drm/radeon/kv_dpm.c
405
return vddc_sclk_table->entries[vddc_sclk_table->count - 1].v;
drivers/gpu/drm/radeon/kv_dpm.c
425
if (vddc_sclk_table->entries[i].v == vid_7bit)
drivers/gpu/drm/radeon/kv_dpm.c
674
(pi->high_voltage_t < table->entries[i].v))
drivers/gpu/drm/radeon/kv_dpm.c
679
pi->uvd_level[i].MinVddNb = cpu_to_be16(table->entries[i].v);
drivers/gpu/drm/radeon/kv_dpm.c
745
pi->high_voltage_t < table->entries[i].v)
drivers/gpu/drm/radeon/kv_dpm.c
749
pi->vce_level[i].MinVoltage = cpu_to_be16(table->entries[i].v);
drivers/gpu/drm/radeon/kv_dpm.c
808
pi->high_voltage_t < table->entries[i].v)
drivers/gpu/drm/radeon/kv_dpm.c
812
pi->samu_level[i].MinVoltage = cpu_to_be16(table->entries[i].v);
drivers/gpu/drm/radeon/kv_dpm.c
874
pi->acp_level[i].MinVoltage = cpu_to_be16(table->entries[i].v);
drivers/gpu/drm/radeon/ni.c
59
void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
drivers/gpu/drm/radeon/ni.c
65
WREG32(TN_SMC_IND_DATA_0, (v));
drivers/gpu/drm/radeon/ni_dpm.c
1000
table->entries[i].v = pi->max_vddc;
drivers/gpu/drm/radeon/ni_dpm.c
4087
rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
drivers/gpu/drm/radeon/ni_dpm.c
4089
rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
drivers/gpu/drm/radeon/ni_dpm.c
4091
rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
drivers/gpu/drm/radeon/ni_dpm.c
4093
rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
drivers/gpu/drm/radeon/ni_dpm.c
741
u16 v, s32 t,
drivers/gpu/drm/radeon/ni_dpm.c
748
vddc = div64_s64(drm_int2fixp(v), 1000);
drivers/gpu/drm/radeon/ni_dpm.c
763
u16 v,
drivers/gpu/drm/radeon/ni_dpm.c
768
ni_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage);
drivers/gpu/drm/radeon/ni_dpm.c
997
if (0xff01 == table->entries[i].v) {
drivers/gpu/drm/radeon/nid.h
1155
#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
drivers/gpu/drm/radeon/r100.c
2923
void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
drivers/gpu/drm/radeon/r100.c
2930
WREG32(RADEON_CLOCK_CNTL_DATA, v);
drivers/gpu/drm/radeon/r100.c
4134
void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v)
drivers/gpu/drm/radeon/r100.c
4140
writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
drivers/gpu/drm/radeon/r100.c
4154
void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v)
drivers/gpu/drm/radeon/r100.c
4157
iowrite32(v, rdev->rio_mem + reg);
drivers/gpu/drm/radeon/r100.c
4160
iowrite32(v, rdev->rio_mem + RADEON_MM_DATA);
drivers/gpu/drm/radeon/r100d.h
62
#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
drivers/gpu/drm/radeon/r300.c
72
void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
drivers/gpu/drm/radeon/r300.c
78
WREG32(RADEON_PCIE_DATA, (v));
drivers/gpu/drm/radeon/r300d.h
63
#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
drivers/gpu/drm/radeon/r420.c
177
void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
drivers/gpu/drm/radeon/r420.c
184
WREG32(R_0001FC_MC_IND_DATA, v);
drivers/gpu/drm/radeon/r600.c
1290
void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
drivers/gpu/drm/radeon/r600.c
1297
WREG32(R_0028FC_MC_DATA, v);
drivers/gpu/drm/radeon/r600.c
132
void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v)
drivers/gpu/drm/radeon/r600.c
138
WREG32(R600_RCU_DATA, (v));
drivers/gpu/drm/radeon/r600.c
154
void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v)
drivers/gpu/drm/radeon/r600.c
160
WREG32(R600_UVD_CTX_DATA, (v));
drivers/gpu/drm/radeon/r600.c
2408
void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
drivers/gpu/drm/radeon/r600.c
2415
WREG32(PCIE_PORT_DATA, (v));
drivers/gpu/drm/radeon/r600_dpm.c
1107
rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].v =
drivers/gpu/drm/radeon/r600_dpm.c
1160
rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].v =
drivers/gpu/drm/radeon/r600_dpm.c
1187
rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].v =
drivers/gpu/drm/radeon/r600_dpm.c
1245
rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].v =
drivers/gpu/drm/radeon/r600_dpm.c
833
radeon_table->entries[i].v = le16_to_cpu(entry->usVoltage);
drivers/gpu/drm/radeon/r600d.h
34
#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
drivers/gpu/drm/radeon/radeon.h
1381
u16 v;
drivers/gpu/drm/radeon/radeon.h
1420
u16 v;
drivers/gpu/drm/radeon/radeon.h
1431
u16 v;
drivers/gpu/drm/radeon/radeon.h
2453
void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v);
drivers/gpu/drm/radeon/radeon.h
2463
static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
drivers/gpu/drm/radeon/radeon.h
2467
writel(v, ((void __iomem *)rdev->rmmio) + reg);
drivers/gpu/drm/radeon/radeon.h
2469
r100_mm_wreg_slow(rdev, reg, v);
drivers/gpu/drm/radeon/radeon.h
2473
void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
drivers/gpu/drm/radeon/radeon.h
2476
void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v);
drivers/gpu/drm/radeon/radeon.h
2502
#define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
drivers/gpu/drm/radeon/radeon.h
2504
#define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
drivers/gpu/drm/radeon/radeon.h
2509
#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
drivers/gpu/drm/radeon/radeon.h
2510
#define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
drivers/gpu/drm/radeon/radeon.h
2511
#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
drivers/gpu/drm/radeon/radeon.h
2512
#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
drivers/gpu/drm/radeon/radeon.h
2514
#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
drivers/gpu/drm/radeon/radeon.h
2516
#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
drivers/gpu/drm/radeon/radeon.h
2518
#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
drivers/gpu/drm/radeon/radeon.h
2520
#define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
drivers/gpu/drm/radeon/radeon.h
2522
#define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
drivers/gpu/drm/radeon/radeon.h
2524
#define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
drivers/gpu/drm/radeon/radeon.h
2526
#define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
drivers/gpu/drm/radeon/radeon.h
2528
#define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
drivers/gpu/drm/radeon/radeon.h
2530
#define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
drivers/gpu/drm/radeon/radeon.h
2532
#define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
drivers/gpu/drm/radeon/radeon.h
2534
#define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v))
drivers/gpu/drm/radeon/radeon.h
2560
#define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
drivers/gpu/drm/radeon/radeon.h
2563
#define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v))
drivers/gpu/drm/radeon/radeon.h
2574
void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
drivers/gpu/drm/radeon/radeon.h
2576
void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
drivers/gpu/drm/radeon/radeon.h
2578
void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v);
drivers/gpu/drm/radeon/radeon.h
2580
void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v);
drivers/gpu/drm/radeon/radeon.h
2582
void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v);
drivers/gpu/drm/radeon/radeon.h
2584
void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v);
drivers/gpu/drm/radeon/radeon.h
2586
void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v);
drivers/gpu/drm/radeon/radeon.h
2588
void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v);
drivers/gpu/drm/radeon/radeon.h
2678
static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
drivers/gpu/drm/radeon/radeon.h
2683
ring->ring[ring->wptr++] = v;
drivers/gpu/drm/radeon/radeon.h
2740
#define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
drivers/gpu/drm/radeon/radeon.h
2762
#define radeon_get_allowed_info_register(rdev, r, v) (rdev)->asic->get_allowed_info_register((rdev), (r), (v))
drivers/gpu/drm/radeon/radeon_asic.c
70
static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
drivers/gpu/drm/radeon/radeon_asic.c
73
reg, v);
drivers/gpu/drm/radeon/radeon_asic.h
201
extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
drivers/gpu/drm/radeon/radeon_asic.h
217
void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
drivers/gpu/drm/radeon/radeon_asic.h
242
void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
drivers/gpu/drm/radeon/radeon_asic.h
267
void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
drivers/gpu/drm/radeon/radeon_asic.h
286
void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
drivers/gpu/drm/radeon/radeon_asic.h
319
void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
drivers/gpu/drm/radeon/radeon_asic.h
366
extern void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
drivers/gpu/drm/radeon/radeon_asic.h
785
void cik_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
drivers/gpu/drm/radeon/radeon_asic.h
83
void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
drivers/gpu/drm/radeon/radeon_atombios.c
3308
if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].v ==
drivers/gpu/drm/radeon/radeon_audio.c
297
u32 reg, u32 v)
drivers/gpu/drm/radeon/radeon_audio.c
300
rdev->audio.funcs->endpoint_wreg(rdev, offset, reg, v);
drivers/gpu/drm/radeon/radeon_audio.c
63
u32 reg, u32 v)
drivers/gpu/drm/radeon/radeon_audio.c
65
WREG32(reg, v);
drivers/gpu/drm/radeon/radeon_audio.h
34
#define WREG32_ENDPOINT(block, reg, v) \
drivers/gpu/drm/radeon/radeon_audio.h
35
radeon_audio_endpoint_wreg(rdev, (block), (reg), (v))
drivers/gpu/drm/radeon/radeon_audio.h
40
u32 offset, u32 reg, u32 v);
drivers/gpu/drm/radeon/radeon_audio.h
76
u32 offset, u32 reg, u32 v);
drivers/gpu/drm/radeon/rs400.c
311
void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
drivers/gpu/drm/radeon/rs400.c
317
WREG32(RS480_NB_MC_DATA, (v));
drivers/gpu/drm/radeon/rs600.c
943
void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
drivers/gpu/drm/radeon/rs600.c
950
WREG32(R_000074_MC_IND_DATA, v);
drivers/gpu/drm/radeon/rs690.c
664
void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
drivers/gpu/drm/radeon/rs690.c
671
WREG32(R_00007C_MC_DATA, v);
drivers/gpu/drm/radeon/rv515.c
210
void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
drivers/gpu/drm/radeon/rv515.c
216
WREG32(MC_IND_DATA, (v));
drivers/gpu/drm/radeon/rv515d.h
203
#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
drivers/gpu/drm/radeon/si_dpm.c
1707
u16 v, s32 t, u32 ileakage, u32 *leakage)
drivers/gpu/drm/radeon/si_dpm.c
1714
vddc = div64_s64(drm_int2fixp(v), 1000);
drivers/gpu/drm/radeon/si_dpm.c
1735
u16 v,
drivers/gpu/drm/radeon/si_dpm.c
1740
si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage);
drivers/gpu/drm/radeon/si_dpm.c
1744
const u32 fixed_kt, u16 v,
drivers/gpu/drm/radeon/si_dpm.c
1750
vddc = div64_s64(drm_int2fixp(v), 1000);
drivers/gpu/drm/radeon/si_dpm.c
1764
u16 v,
drivers/gpu/drm/radeon/si_dpm.c
1768
si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage);
drivers/gpu/drm/radeon/si_dpm.c
2887
*voltage = table->entries[i].v;
drivers/gpu/drm/radeon/si_dpm.c
2895
*voltage = table->entries[table->count - 1].v;
drivers/gpu/drm/radeon/si_dpm.c
3893
voltage_table->entries[i].value = voltage_dependency_table->entries[i].v;
drivers/gpu/drm/radeon/si_dpm.c
4105
(u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
drivers/gpu/drm/radeon/si_dpm.c
4120
(u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
drivers/gpu/drm/radeon/si_dpm.c
5108
rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v)
drivers/gpu/drm/radeon/si_dpm.c
5823
table->entries[i].v,
drivers/gpu/drm/radeon/si_dpm.c
5826
table->entries[i].v = leakage_voltage;
drivers/gpu/drm/radeon/si_dpm.c
5837
table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ?
drivers/gpu/drm/radeon/si_dpm.c
5838
table->entries[j].v : table->entries[j + 1].v;
drivers/gpu/drm/radeon/si_dpm.c
6910
rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
drivers/gpu/drm/radeon/si_dpm.c
6912
rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
drivers/gpu/drm/radeon/si_dpm.c
6914
rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
drivers/gpu/drm/radeon/si_dpm.c
6916
rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
drivers/gpu/drm/radeon/sid.h
1593
#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
drivers/gpu/drm/radeon/sumo_dpm.c
875
u32 v = RREG32(DOUT_SCRATCH3);
drivers/gpu/drm/radeon/sumo_dpm.c
878
v |= 0x4;
drivers/gpu/drm/radeon/sumo_dpm.c
880
v &= 0xFFFFFFFB;
drivers/gpu/drm/radeon/sumo_dpm.c
882
WREG32(DOUT_SCRATCH3, v);
drivers/gpu/drm/radeon/trinity_dpm.c
1473
*voltage = table->entries[i].v;
drivers/gpu/drm/radeon/trinity_dpm.c
1481
*voltage = table->entries[table->count - 1].v;
drivers/gpu/drm/radeon/trinity_smc.c
32
u32 v = 0;
drivers/gpu/drm/radeon/trinity_smc.c
40
v = RREG32(SMC_RESP_0);
drivers/gpu/drm/radeon/trinity_smc.c
42
if (v != 1) {
drivers/gpu/drm/radeon/trinity_smc.c
43
if (v == 0xFF) {
drivers/gpu/drm/radeon/trinity_smc.c
46
} else if (v == 0xFE) {
drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi.c
32
#define MHZ(v) ((u32)((v) * 1000000U))
drivers/gpu/drm/rockchip/rockchip_drm_vop.c
100
#define VOP_AFBC_SET(vop, name, v) \
drivers/gpu/drm/rockchip/rockchip_drm_vop.c
104
0, ~0, v, #name); \
drivers/gpu/drm/rockchip/rockchip_drm_vop.c
203
uint32_t _offset, uint32_t _mask, uint32_t v,
drivers/gpu/drm/rockchip/rockchip_drm_vop.c
218
v = ((v << shift) & 0xffff) | (mask << (shift + 16));
drivers/gpu/drm/rockchip/rockchip_drm_vop.c
222
v = (cached_val & ~(mask << shift)) | ((v & mask) << shift);
drivers/gpu/drm/rockchip/rockchip_drm_vop.c
223
vop->regsbak[offset >> 2] = v;
drivers/gpu/drm/rockchip/rockchip_drm_vop.c
227
writel_relaxed(v, vop->regs + offset);
drivers/gpu/drm/rockchip/rockchip_drm_vop.c
229
writel(v, vop->regs + offset);
drivers/gpu/drm/rockchip/rockchip_drm_vop.c
45
#define VOP_WIN_SET(vop, win, name, v) \
drivers/gpu/drm/rockchip/rockchip_drm_vop.c
46
vop_reg_set(vop, &win->phy->name, win->base, ~0, v, #name)
drivers/gpu/drm/rockchip/rockchip_drm_vop.c
47
#define VOP_SCL_SET(vop, win, name, v) \
drivers/gpu/drm/rockchip/rockchip_drm_vop.c
48
vop_reg_set(vop, &win->phy->scl->name, win->base, ~0, v, #name)
drivers/gpu/drm/rockchip/rockchip_drm_vop.c
49
#define VOP_SCL_SET_EXT(vop, win, name, v) \
drivers/gpu/drm/rockchip/rockchip_drm_vop.c
51
win->base, ~0, v, #name)
drivers/gpu/drm/rockchip/rockchip_drm_vop.c
53
#define VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, name, v) \
drivers/gpu/drm/rockchip/rockchip_drm_vop.c
56
vop_reg_set(vop, &win_yuv2yuv->name, 0, ~0, v, #name); \
drivers/gpu/drm/rockchip/rockchip_drm_vop.c
59
#define VOP_WIN_YUV2YUV_COEFFICIENT_SET(vop, win_yuv2yuv, name, v) \
drivers/gpu/drm/rockchip/rockchip_drm_vop.c
62
vop_reg_set(vop, &win_yuv2yuv->phy->name, win_yuv2yuv->base, ~0, v, #name); \
drivers/gpu/drm/rockchip/rockchip_drm_vop.c
65
#define VOP_INTR_SET_MASK(vop, name, mask, v) \
drivers/gpu/drm/rockchip/rockchip_drm_vop.c
66
vop_reg_set(vop, &vop->data->intr->name, 0, mask, v, #name)
drivers/gpu/drm/rockchip/rockchip_drm_vop.c
68
#define VOP_REG_SET(vop, group, name, v) \
drivers/gpu/drm/rockchip/rockchip_drm_vop.c
69
vop_reg_set(vop, &vop->data->group->name, 0, ~0, v, #name)
drivers/gpu/drm/rockchip/rockchip_drm_vop.c
74
#define VOP_INTR_SET_TYPE(vop, name, type, v) \
drivers/gpu/drm/rockchip/rockchip_drm_vop.c
79
reg |= (v) << i; \
drivers/gpu/drm/rockchip/rockchip_drm_vop2.h
799
static inline void vop2_writel(struct vop2 *vop2, u32 offset, u32 v)
drivers/gpu/drm/rockchip/rockchip_drm_vop2.h
801
regmap_write(vop2->map, offset, v);
drivers/gpu/drm/rockchip/rockchip_drm_vop2.h
804
static inline void vop2_vp_write(struct vop2_video_port *vp, u32 offset, u32 v)
drivers/gpu/drm/rockchip/rockchip_drm_vop2.h
806
regmap_write(vp->vop2->map, vp->data->offset + offset, v);
drivers/gpu/drm/rockchip/rockchip_drm_vop2.h
827
static inline void vop2_win_write(const struct vop2_win *win, unsigned int reg, u32 v)
drivers/gpu/drm/rockchip/rockchip_drm_vop2.h
829
regmap_field_write(win->reg[reg], v);
drivers/gpu/drm/tegra/dc.c
128
static inline u32 compute_dda_inc(unsigned int in, unsigned int out, bool v,
drivers/gpu/drm/tegra/dc.c
136
if (v)
drivers/gpu/drm/tegra/falcon.h
21
#define FALCON_IRQMSET_EXT(v) (((v) & 0xff) << 8)
drivers/gpu/drm/tegra/falcon.h
28
#define FALCON_IRQDEST_EXT(v) (((v) & 0xff) << 8)
drivers/gpu/drm/tegra/falcon.h
54
#define FALCON_DMATRFCMD_DMACTX(v) (((v) & 0x7) << 12)
drivers/gpu/drm/tegra/riscv.c
30
#define RISCV_BCR_DMACFG_SEC_GSCID(v) ((v) << 16)
drivers/gpu/drm/tegra/vic.h
25
#define TRANSCFG_ATT(i, v) (((v) & 0x3) << (i * 4))
drivers/gpu/drm/tidss/tidss_dispc.c
1066
int v;
drivers/gpu/drm/tidss/tidss_dispc.c
1070
v = 0; break;
drivers/gpu/drm/tidss/tidss_dispc.c
1072
v = 1; break;
drivers/gpu/drm/tidss/tidss_dispc.c
1074
v = 2; break;
drivers/gpu/drm/tidss/tidss_dispc.c
1076
v = 3; break;
drivers/gpu/drm/tidss/tidss_dispc.c
1078
v = 4; break;
drivers/gpu/drm/tidss/tidss_dispc.c
1080
v = 5; break;
drivers/gpu/drm/tidss/tidss_dispc.c
1083
v = 3;
drivers/gpu/drm/tidss/tidss_dispc.c
1086
VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, v,
drivers/gpu/drm/tidss/tidss_dispc.c
1267
u64 v;
drivers/gpu/drm/tidss/tidss_dispc.c
1274
v = ((u64)c8_to_c12(a, m) << 36) | ((u64)c8_to_c12(r, m) << 24) |
drivers/gpu/drm/tidss/tidss_dispc.c
1277
return v;
drivers/gpu/drm/tidss/tidss_dispc.c
1283
u64 v;
drivers/gpu/drm/tidss/tidss_dispc.c
1285
v = argb8888_to_argb12121212(default_color, C8_TO_C12_REPLICATE);
drivers/gpu/drm/tidss/tidss_dispc.c
1288
DISPC_OVR_DEFAULT_COLOR, v & 0xffffffff);
drivers/gpu/drm/tidss/tidss_dispc.c
1290
DISPC_OVR_DEFAULT_COLOR2, (v >> 32) & 0xffff);
drivers/gpu/drm/tidss/tidss_dispc.c
2471
u32 v = table[i];
drivers/gpu/drm/tidss/tidss_dispc.c
2473
v |= i << 24;
drivers/gpu/drm/tidss/tidss_dispc.c
2476
v);
drivers/gpu/drm/tidss/tidss_dispc.c
2493
u32 v = table[i];
drivers/gpu/drm/tidss/tidss_dispc.c
2495
v |= i << 24;
drivers/gpu/drm/tidss/tidss_dispc.c
2497
dispc_vp_write(dispc, hw_videoport, DISPC_VP_GAMMA_TABLE, v);
drivers/gpu/drm/tidss/tidss_dispc.c
2514
u32 v = table[i];
drivers/gpu/drm/tidss/tidss_dispc.c
2517
v |= 1 << 31;
drivers/gpu/drm/tidss/tidss_dispc.c
2519
dispc_vp_write(dispc, hw_videoport, DISPC_VP_GAMMA_TABLE, v);
drivers/gpu/drm/vkms/tests/vkms_format_test.c
238
color->yuv.v);
drivers/gpu/drm/vkms/tests/vkms_format_test.c
26
u16 y, u, v;
drivers/gpu/drm/xe/xe_lrc.c
211
u8 v;
drivers/gpu/drm/xe/xe_lrc.c
214
v = *data++;
drivers/gpu/drm/xe/xe_lrc.c
216
offset |= v & ~BIT(7);
drivers/gpu/drm/xe/xe_lrc.c
217
} while (v & BIT(7));
drivers/gpu/drm/xlnx/zynqmp_dp_audio.c
176
u32 v;
drivers/gpu/drm/xlnx/zynqmp_dp_audio.c
178
v = (iec.status[(i * 4) + 0] << 0) |
drivers/gpu/drm/xlnx/zynqmp_dp_audio.c
183
zynqmp_dp_audio_write(audio, ZYNQMP_DISP_AUD_CH_STATUS(i), v);
drivers/gpu/host1x/dev.c
45
void host1x_common_writel(struct host1x *host1x, u32 v, u32 r)
drivers/gpu/host1x/dev.c
47
writel(v, host1x->common_regs + r);
drivers/gpu/host1x/dev.c
50
void host1x_hypervisor_writel(struct host1x *host1x, u32 v, u32 r)
drivers/gpu/host1x/dev.c
52
writel(v, host1x->hv_regs + r);
drivers/gpu/host1x/dev.c
60
void host1x_sync_writel(struct host1x *host1x, u32 v, u32 r)
drivers/gpu/host1x/dev.c
64
writel(v, sync_regs + r);
drivers/gpu/host1x/dev.c
83
void host1x_ch_writel(struct host1x_channel *ch, u32 v, u32 r)
drivers/gpu/host1x/dev.c
85
writel(v, ch->regs + r);
drivers/gpu/host1x/dev.h
177
void host1x_common_writel(struct host1x *host1x, u32 v, u32 r);
drivers/gpu/host1x/dev.h
178
void host1x_hypervisor_writel(struct host1x *host1x, u32 v, u32 r);
drivers/gpu/host1x/dev.h
180
void host1x_sync_writel(struct host1x *host1x, u32 v, u32 r);
drivers/gpu/host1x/dev.h
185
void host1x_ch_writel(struct host1x_channel *ch, u32 v, u32 r);
drivers/gpu/host1x/hw/hw_host1x01_sync.h
122
static inline u32 host1x_sync_mlock_owner_chid_v(u32 v)
drivers/gpu/host1x/hw/hw_host1x01_sync.h
124
return (v >> 8) & 0xf;
drivers/gpu/host1x/hw/hw_host1x01_sync.h
126
#define HOST1X_SYNC_MLOCK_OWNER_CHID_V(v) \
drivers/gpu/host1x/hw/hw_host1x01_sync.h
127
host1x_sync_mlock_owner_chid_v(v)
drivers/gpu/host1x/hw/hw_host1x01_sync.h
170
static inline u32 host1x_sync_cfpeek_ctrl_addr_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x01_sync.h
172
return (v & 0x1ff) << 0;
drivers/gpu/host1x/hw/hw_host1x01_sync.h
174
#define HOST1X_SYNC_CFPEEK_CTRL_ADDR_F(v) \
drivers/gpu/host1x/hw/hw_host1x01_sync.h
175
host1x_sync_cfpeek_ctrl_addr_f(v)
drivers/gpu/host1x/hw/hw_host1x01_sync.h
176
static inline u32 host1x_sync_cfpeek_ctrl_channr_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x01_sync.h
178
return (v & 0x7) << 16;
drivers/gpu/host1x/hw/hw_host1x01_sync.h
180
#define HOST1X_SYNC_CFPEEK_CTRL_CHANNR_F(v) \
drivers/gpu/host1x/hw/hw_host1x01_sync.h
181
host1x_sync_cfpeek_ctrl_channr_f(v)
drivers/gpu/host1x/hw/hw_host1x01_sync.h
182
static inline u32 host1x_sync_cfpeek_ctrl_ena_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x01_sync.h
184
return (v & 0x1) << 31;
drivers/gpu/host1x/hw/hw_host1x01_sync.h
186
#define HOST1X_SYNC_CFPEEK_CTRL_ENA_F(v) \
drivers/gpu/host1x/hw/hw_host1x01_sync.h
187
host1x_sync_cfpeek_ctrl_ena_f(v)
drivers/gpu/host1x/hw/hw_host1x01_uclass.h
100
#define HOST1X_UCLASS_WAIT_SYNCPT_BASE_OFFSET_F(v) \
drivers/gpu/host1x/hw/hw_host1x01_uclass.h
101
host1x_uclass_wait_syncpt_base_offset_f(v)
drivers/gpu/host1x/hw/hw_host1x01_uclass.h
108
static inline u32 host1x_uclass_load_syncpt_base_base_indx_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x01_uclass.h
110
return (v & 0xff) << 24;
drivers/gpu/host1x/hw/hw_host1x01_uclass.h
112
#define HOST1X_UCLASS_LOAD_SYNCPT_BASE_BASE_INDX_F(v) \
drivers/gpu/host1x/hw/hw_host1x01_uclass.h
113
host1x_uclass_load_syncpt_base_base_indx_f(v)
drivers/gpu/host1x/hw/hw_host1x01_uclass.h
114
static inline u32 host1x_uclass_load_syncpt_base_value_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x01_uclass.h
116
return (v & 0xffffff) << 0;
drivers/gpu/host1x/hw/hw_host1x01_uclass.h
118
#define HOST1X_UCLASS_LOAD_SYNCPT_BASE_VALUE_F(v) \
drivers/gpu/host1x/hw/hw_host1x01_uclass.h
119
host1x_uclass_load_syncpt_base_value_f(v)
drivers/gpu/host1x/hw/hw_host1x01_uclass.h
120
static inline u32 host1x_uclass_incr_syncpt_base_base_indx_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x01_uclass.h
122
return (v & 0xff) << 24;
drivers/gpu/host1x/hw/hw_host1x01_uclass.h
124
#define HOST1X_UCLASS_INCR_SYNCPT_BASE_BASE_INDX_F(v) \
drivers/gpu/host1x/hw/hw_host1x01_uclass.h
125
host1x_uclass_incr_syncpt_base_base_indx_f(v)
drivers/gpu/host1x/hw/hw_host1x01_uclass.h
126
static inline u32 host1x_uclass_incr_syncpt_base_offset_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x01_uclass.h
128
return (v & 0xffffff) << 0;
drivers/gpu/host1x/hw/hw_host1x01_uclass.h
130
#define HOST1X_UCLASS_INCR_SYNCPT_BASE_OFFSET_F(v) \
drivers/gpu/host1x/hw/hw_host1x01_uclass.h
131
host1x_uclass_incr_syncpt_base_offset_f(v)
drivers/gpu/host1x/hw/hw_host1x01_uclass.h
138
static inline u32 host1x_uclass_indoff_indbe_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x01_uclass.h
140
return (v & 0xf) << 28;
drivers/gpu/host1x/hw/hw_host1x01_uclass.h
142
#define HOST1X_UCLASS_INDOFF_INDBE_F(v) \
drivers/gpu/host1x/hw/hw_host1x01_uclass.h
143
host1x_uclass_indoff_indbe_f(v)
drivers/gpu/host1x/hw/hw_host1x01_uclass.h
144
static inline u32 host1x_uclass_indoff_autoinc_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x01_uclass.h
146
return (v & 0x1) << 27;
drivers/gpu/host1x/hw/hw_host1x01_uclass.h
148
#define HOST1X_UCLASS_INDOFF_AUTOINC_F(v) \
drivers/gpu/host1x/hw/hw_host1x01_uclass.h
149
host1x_uclass_indoff_autoinc_f(v)
drivers/gpu/host1x/hw/hw_host1x01_uclass.h
150
static inline u32 host1x_uclass_indoff_indmodid_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x01_uclass.h
152
return (v & 0xff) << 18;
drivers/gpu/host1x/hw/hw_host1x01_uclass.h
154
#define HOST1X_UCLASS_INDOFF_INDMODID_F(v) \
drivers/gpu/host1x/hw/hw_host1x01_uclass.h
155
host1x_uclass_indoff_indmodid_f(v)
drivers/gpu/host1x/hw/hw_host1x01_uclass.h
156
static inline u32 host1x_uclass_indoff_indroffset_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x01_uclass.h
158
return (v & 0xffff) << 2;
drivers/gpu/host1x/hw/hw_host1x01_uclass.h
160
#define HOST1X_UCLASS_INDOFF_INDROFFSET_F(v) \
drivers/gpu/host1x/hw/hw_host1x01_uclass.h
161
host1x_uclass_indoff_indroffset_f(v)
drivers/gpu/host1x/hw/hw_host1x01_uclass.h
166
#define HOST1X_UCLASS_INDOFF_INDROFFSET_F(v) \
drivers/gpu/host1x/hw/hw_host1x01_uclass.h
167
host1x_uclass_indoff_indroffset_f(v)
drivers/gpu/host1x/hw/hw_host1x01_uclass.h
48
static inline u32 host1x_uclass_incr_syncpt_cond_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x01_uclass.h
50
return (v & 0xff) << 8;
drivers/gpu/host1x/hw/hw_host1x01_uclass.h
52
#define HOST1X_UCLASS_INCR_SYNCPT_COND_F(v) \
drivers/gpu/host1x/hw/hw_host1x01_uclass.h
53
host1x_uclass_incr_syncpt_cond_f(v)
drivers/gpu/host1x/hw/hw_host1x01_uclass.h
54
static inline u32 host1x_uclass_incr_syncpt_indx_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x01_uclass.h
56
return (v & 0xff) << 0;
drivers/gpu/host1x/hw/hw_host1x01_uclass.h
58
#define HOST1X_UCLASS_INCR_SYNCPT_INDX_F(v) \
drivers/gpu/host1x/hw/hw_host1x01_uclass.h
59
host1x_uclass_incr_syncpt_indx_f(v)
drivers/gpu/host1x/hw/hw_host1x01_uclass.h
66
static inline u32 host1x_uclass_wait_syncpt_indx_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x01_uclass.h
68
return (v & 0xff) << 24;
drivers/gpu/host1x/hw/hw_host1x01_uclass.h
70
#define HOST1X_UCLASS_WAIT_SYNCPT_INDX_F(v) \
drivers/gpu/host1x/hw/hw_host1x01_uclass.h
71
host1x_uclass_wait_syncpt_indx_f(v)
drivers/gpu/host1x/hw/hw_host1x01_uclass.h
72
static inline u32 host1x_uclass_wait_syncpt_thresh_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x01_uclass.h
74
return (v & 0xffffff) << 0;
drivers/gpu/host1x/hw/hw_host1x01_uclass.h
76
#define HOST1X_UCLASS_WAIT_SYNCPT_THRESH_F(v) \
drivers/gpu/host1x/hw/hw_host1x01_uclass.h
77
host1x_uclass_wait_syncpt_thresh_f(v)
drivers/gpu/host1x/hw/hw_host1x01_uclass.h
84
static inline u32 host1x_uclass_wait_syncpt_base_indx_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x01_uclass.h
86
return (v & 0xff) << 24;
drivers/gpu/host1x/hw/hw_host1x01_uclass.h
88
#define HOST1X_UCLASS_WAIT_SYNCPT_BASE_INDX_F(v) \
drivers/gpu/host1x/hw/hw_host1x01_uclass.h
89
host1x_uclass_wait_syncpt_base_indx_f(v)
drivers/gpu/host1x/hw/hw_host1x01_uclass.h
90
static inline u32 host1x_uclass_wait_syncpt_base_base_indx_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x01_uclass.h
92
return (v & 0xff) << 16;
drivers/gpu/host1x/hw/hw_host1x01_uclass.h
94
#define HOST1X_UCLASS_WAIT_SYNCPT_BASE_BASE_INDX_F(v) \
drivers/gpu/host1x/hw/hw_host1x01_uclass.h
95
host1x_uclass_wait_syncpt_base_base_indx_f(v)
drivers/gpu/host1x/hw/hw_host1x01_uclass.h
96
static inline u32 host1x_uclass_wait_syncpt_base_offset_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x01_uclass.h
98
return (v & 0xffff) << 0;
drivers/gpu/host1x/hw/hw_host1x02_sync.h
122
static inline u32 host1x_sync_mlock_owner_chid_v(u32 v)
drivers/gpu/host1x/hw/hw_host1x02_sync.h
124
return (v >> 8) & 0xf;
drivers/gpu/host1x/hw/hw_host1x02_sync.h
126
#define HOST1X_SYNC_MLOCK_OWNER_CHID_V(v) \
drivers/gpu/host1x/hw/hw_host1x02_sync.h
127
host1x_sync_mlock_owner_chid_v(v)
drivers/gpu/host1x/hw/hw_host1x02_sync.h
170
static inline u32 host1x_sync_cfpeek_ctrl_addr_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x02_sync.h
172
return (v & 0x3ff) << 0;
drivers/gpu/host1x/hw/hw_host1x02_sync.h
174
#define HOST1X_SYNC_CFPEEK_CTRL_ADDR_F(v) \
drivers/gpu/host1x/hw/hw_host1x02_sync.h
175
host1x_sync_cfpeek_ctrl_addr_f(v)
drivers/gpu/host1x/hw/hw_host1x02_sync.h
176
static inline u32 host1x_sync_cfpeek_ctrl_channr_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x02_sync.h
178
return (v & 0xf) << 16;
drivers/gpu/host1x/hw/hw_host1x02_sync.h
180
#define HOST1X_SYNC_CFPEEK_CTRL_CHANNR_F(v) \
drivers/gpu/host1x/hw/hw_host1x02_sync.h
181
host1x_sync_cfpeek_ctrl_channr_f(v)
drivers/gpu/host1x/hw/hw_host1x02_sync.h
182
static inline u32 host1x_sync_cfpeek_ctrl_ena_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x02_sync.h
184
return (v & 0x1) << 31;
drivers/gpu/host1x/hw/hw_host1x02_sync.h
186
#define HOST1X_SYNC_CFPEEK_CTRL_ENA_F(v) \
drivers/gpu/host1x/hw/hw_host1x02_sync.h
187
host1x_sync_cfpeek_ctrl_ena_f(v)
drivers/gpu/host1x/hw/hw_host1x02_uclass.h
100
#define HOST1X_UCLASS_WAIT_SYNCPT_BASE_OFFSET_F(v) \
drivers/gpu/host1x/hw/hw_host1x02_uclass.h
101
host1x_uclass_wait_syncpt_base_offset_f(v)
drivers/gpu/host1x/hw/hw_host1x02_uclass.h
108
static inline u32 host1x_uclass_load_syncpt_base_base_indx_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x02_uclass.h
110
return (v & 0xff) << 24;
drivers/gpu/host1x/hw/hw_host1x02_uclass.h
112
#define HOST1X_UCLASS_LOAD_SYNCPT_BASE_BASE_INDX_F(v) \
drivers/gpu/host1x/hw/hw_host1x02_uclass.h
113
host1x_uclass_load_syncpt_base_base_indx_f(v)
drivers/gpu/host1x/hw/hw_host1x02_uclass.h
114
static inline u32 host1x_uclass_load_syncpt_base_value_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x02_uclass.h
116
return (v & 0xffffff) << 0;
drivers/gpu/host1x/hw/hw_host1x02_uclass.h
118
#define HOST1X_UCLASS_LOAD_SYNCPT_BASE_VALUE_F(v) \
drivers/gpu/host1x/hw/hw_host1x02_uclass.h
119
host1x_uclass_load_syncpt_base_value_f(v)
drivers/gpu/host1x/hw/hw_host1x02_uclass.h
120
static inline u32 host1x_uclass_incr_syncpt_base_base_indx_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x02_uclass.h
122
return (v & 0xff) << 24;
drivers/gpu/host1x/hw/hw_host1x02_uclass.h
124
#define HOST1X_UCLASS_INCR_SYNCPT_BASE_BASE_INDX_F(v) \
drivers/gpu/host1x/hw/hw_host1x02_uclass.h
125
host1x_uclass_incr_syncpt_base_base_indx_f(v)
drivers/gpu/host1x/hw/hw_host1x02_uclass.h
126
static inline u32 host1x_uclass_incr_syncpt_base_offset_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x02_uclass.h
128
return (v & 0xffffff) << 0;
drivers/gpu/host1x/hw/hw_host1x02_uclass.h
130
#define HOST1X_UCLASS_INCR_SYNCPT_BASE_OFFSET_F(v) \
drivers/gpu/host1x/hw/hw_host1x02_uclass.h
131
host1x_uclass_incr_syncpt_base_offset_f(v)
drivers/gpu/host1x/hw/hw_host1x02_uclass.h
138
static inline u32 host1x_uclass_indoff_indbe_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x02_uclass.h
140
return (v & 0xf) << 28;
drivers/gpu/host1x/hw/hw_host1x02_uclass.h
142
#define HOST1X_UCLASS_INDOFF_INDBE_F(v) \
drivers/gpu/host1x/hw/hw_host1x02_uclass.h
143
host1x_uclass_indoff_indbe_f(v)
drivers/gpu/host1x/hw/hw_host1x02_uclass.h
144
static inline u32 host1x_uclass_indoff_autoinc_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x02_uclass.h
146
return (v & 0x1) << 27;
drivers/gpu/host1x/hw/hw_host1x02_uclass.h
148
#define HOST1X_UCLASS_INDOFF_AUTOINC_F(v) \
drivers/gpu/host1x/hw/hw_host1x02_uclass.h
149
host1x_uclass_indoff_autoinc_f(v)
drivers/gpu/host1x/hw/hw_host1x02_uclass.h
150
static inline u32 host1x_uclass_indoff_indmodid_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x02_uclass.h
152
return (v & 0xff) << 18;
drivers/gpu/host1x/hw/hw_host1x02_uclass.h
154
#define HOST1X_UCLASS_INDOFF_INDMODID_F(v) \
drivers/gpu/host1x/hw/hw_host1x02_uclass.h
155
host1x_uclass_indoff_indmodid_f(v)
drivers/gpu/host1x/hw/hw_host1x02_uclass.h
156
static inline u32 host1x_uclass_indoff_indroffset_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x02_uclass.h
158
return (v & 0xffff) << 2;
drivers/gpu/host1x/hw/hw_host1x02_uclass.h
160
#define HOST1X_UCLASS_INDOFF_INDROFFSET_F(v) \
drivers/gpu/host1x/hw/hw_host1x02_uclass.h
161
host1x_uclass_indoff_indroffset_f(v)
drivers/gpu/host1x/hw/hw_host1x02_uclass.h
166
#define HOST1X_UCLASS_INDOFF_INDROFFSET_F(v) \
drivers/gpu/host1x/hw/hw_host1x02_uclass.h
167
host1x_uclass_indoff_indroffset_f(v)
drivers/gpu/host1x/hw/hw_host1x02_uclass.h
48
static inline u32 host1x_uclass_incr_syncpt_cond_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x02_uclass.h
50
return (v & 0xff) << 8;
drivers/gpu/host1x/hw/hw_host1x02_uclass.h
52
#define HOST1X_UCLASS_INCR_SYNCPT_COND_F(v) \
drivers/gpu/host1x/hw/hw_host1x02_uclass.h
53
host1x_uclass_incr_syncpt_cond_f(v)
drivers/gpu/host1x/hw/hw_host1x02_uclass.h
54
static inline u32 host1x_uclass_incr_syncpt_indx_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x02_uclass.h
56
return (v & 0xff) << 0;
drivers/gpu/host1x/hw/hw_host1x02_uclass.h
58
#define HOST1X_UCLASS_INCR_SYNCPT_INDX_F(v) \
drivers/gpu/host1x/hw/hw_host1x02_uclass.h
59
host1x_uclass_incr_syncpt_indx_f(v)
drivers/gpu/host1x/hw/hw_host1x02_uclass.h
66
static inline u32 host1x_uclass_wait_syncpt_indx_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x02_uclass.h
68
return (v & 0xff) << 24;
drivers/gpu/host1x/hw/hw_host1x02_uclass.h
70
#define HOST1X_UCLASS_WAIT_SYNCPT_INDX_F(v) \
drivers/gpu/host1x/hw/hw_host1x02_uclass.h
71
host1x_uclass_wait_syncpt_indx_f(v)
drivers/gpu/host1x/hw/hw_host1x02_uclass.h
72
static inline u32 host1x_uclass_wait_syncpt_thresh_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x02_uclass.h
74
return (v & 0xffffff) << 0;
drivers/gpu/host1x/hw/hw_host1x02_uclass.h
76
#define HOST1X_UCLASS_WAIT_SYNCPT_THRESH_F(v) \
drivers/gpu/host1x/hw/hw_host1x02_uclass.h
77
host1x_uclass_wait_syncpt_thresh_f(v)
drivers/gpu/host1x/hw/hw_host1x02_uclass.h
84
static inline u32 host1x_uclass_wait_syncpt_base_indx_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x02_uclass.h
86
return (v & 0xff) << 24;
drivers/gpu/host1x/hw/hw_host1x02_uclass.h
88
#define HOST1X_UCLASS_WAIT_SYNCPT_BASE_INDX_F(v) \
drivers/gpu/host1x/hw/hw_host1x02_uclass.h
89
host1x_uclass_wait_syncpt_base_indx_f(v)
drivers/gpu/host1x/hw/hw_host1x02_uclass.h
90
static inline u32 host1x_uclass_wait_syncpt_base_base_indx_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x02_uclass.h
92
return (v & 0xff) << 16;
drivers/gpu/host1x/hw/hw_host1x02_uclass.h
94
#define HOST1X_UCLASS_WAIT_SYNCPT_BASE_BASE_INDX_F(v) \
drivers/gpu/host1x/hw/hw_host1x02_uclass.h
95
host1x_uclass_wait_syncpt_base_base_indx_f(v)
drivers/gpu/host1x/hw/hw_host1x02_uclass.h
96
static inline u32 host1x_uclass_wait_syncpt_base_offset_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x02_uclass.h
98
return (v & 0xffff) << 0;
drivers/gpu/host1x/hw/hw_host1x04_channel.h
114
static inline u32 host1x_channel_channelctrl_kernel_filter_gbuffer_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x04_channel.h
116
return (v & 0x1) << 2;
drivers/gpu/host1x/hw/hw_host1x04_channel.h
118
#define HOST1X_CHANNEL_CHANNELCTRL_KERNEL_FILTER_GBUFFER(v) \
drivers/gpu/host1x/hw/hw_host1x04_channel.h
119
host1x_channel_channelctrl_kernel_filter_gbuffer_f(v)
drivers/gpu/host1x/hw/hw_host1x04_sync.h
122
static inline u32 host1x_sync_mlock_owner_chid_v(u32 v)
drivers/gpu/host1x/hw/hw_host1x04_sync.h
124
return (v >> 8) & 0xf;
drivers/gpu/host1x/hw/hw_host1x04_sync.h
126
#define HOST1X_SYNC_MLOCK_OWNER_CHID_V(v) \
drivers/gpu/host1x/hw/hw_host1x04_sync.h
127
host1x_sync_mlock_owner_chid_v(v)
drivers/gpu/host1x/hw/hw_host1x04_sync.h
170
static inline u32 host1x_sync_cfpeek_ctrl_addr_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x04_sync.h
172
return (v & 0x3ff) << 0;
drivers/gpu/host1x/hw/hw_host1x04_sync.h
174
#define HOST1X_SYNC_CFPEEK_CTRL_ADDR_F(v) \
drivers/gpu/host1x/hw/hw_host1x04_sync.h
175
host1x_sync_cfpeek_ctrl_addr_f(v)
drivers/gpu/host1x/hw/hw_host1x04_sync.h
176
static inline u32 host1x_sync_cfpeek_ctrl_channr_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x04_sync.h
178
return (v & 0xf) << 16;
drivers/gpu/host1x/hw/hw_host1x04_sync.h
180
#define HOST1X_SYNC_CFPEEK_CTRL_CHANNR_F(v) \
drivers/gpu/host1x/hw/hw_host1x04_sync.h
181
host1x_sync_cfpeek_ctrl_channr_f(v)
drivers/gpu/host1x/hw/hw_host1x04_sync.h
182
static inline u32 host1x_sync_cfpeek_ctrl_ena_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x04_sync.h
184
return (v & 0x1) << 31;
drivers/gpu/host1x/hw/hw_host1x04_sync.h
186
#define HOST1X_SYNC_CFPEEK_CTRL_ENA_F(v) \
drivers/gpu/host1x/hw/hw_host1x04_sync.h
187
host1x_sync_cfpeek_ctrl_ena_f(v)
drivers/gpu/host1x/hw/hw_host1x04_uclass.h
100
#define HOST1X_UCLASS_WAIT_SYNCPT_BASE_OFFSET_F(v) \
drivers/gpu/host1x/hw/hw_host1x04_uclass.h
101
host1x_uclass_wait_syncpt_base_offset_f(v)
drivers/gpu/host1x/hw/hw_host1x04_uclass.h
108
static inline u32 host1x_uclass_load_syncpt_base_base_indx_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x04_uclass.h
110
return (v & 0xff) << 24;
drivers/gpu/host1x/hw/hw_host1x04_uclass.h
112
#define HOST1X_UCLASS_LOAD_SYNCPT_BASE_BASE_INDX_F(v) \
drivers/gpu/host1x/hw/hw_host1x04_uclass.h
113
host1x_uclass_load_syncpt_base_base_indx_f(v)
drivers/gpu/host1x/hw/hw_host1x04_uclass.h
114
static inline u32 host1x_uclass_load_syncpt_base_value_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x04_uclass.h
116
return (v & 0xffffff) << 0;
drivers/gpu/host1x/hw/hw_host1x04_uclass.h
118
#define HOST1X_UCLASS_LOAD_SYNCPT_BASE_VALUE_F(v) \
drivers/gpu/host1x/hw/hw_host1x04_uclass.h
119
host1x_uclass_load_syncpt_base_value_f(v)
drivers/gpu/host1x/hw/hw_host1x04_uclass.h
120
static inline u32 host1x_uclass_incr_syncpt_base_base_indx_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x04_uclass.h
122
return (v & 0xff) << 24;
drivers/gpu/host1x/hw/hw_host1x04_uclass.h
124
#define HOST1X_UCLASS_INCR_SYNCPT_BASE_BASE_INDX_F(v) \
drivers/gpu/host1x/hw/hw_host1x04_uclass.h
125
host1x_uclass_incr_syncpt_base_base_indx_f(v)
drivers/gpu/host1x/hw/hw_host1x04_uclass.h
126
static inline u32 host1x_uclass_incr_syncpt_base_offset_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x04_uclass.h
128
return (v & 0xffffff) << 0;
drivers/gpu/host1x/hw/hw_host1x04_uclass.h
130
#define HOST1X_UCLASS_INCR_SYNCPT_BASE_OFFSET_F(v) \
drivers/gpu/host1x/hw/hw_host1x04_uclass.h
131
host1x_uclass_incr_syncpt_base_offset_f(v)
drivers/gpu/host1x/hw/hw_host1x04_uclass.h
138
static inline u32 host1x_uclass_indoff_indbe_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x04_uclass.h
140
return (v & 0xf) << 28;
drivers/gpu/host1x/hw/hw_host1x04_uclass.h
142
#define HOST1X_UCLASS_INDOFF_INDBE_F(v) \
drivers/gpu/host1x/hw/hw_host1x04_uclass.h
143
host1x_uclass_indoff_indbe_f(v)
drivers/gpu/host1x/hw/hw_host1x04_uclass.h
144
static inline u32 host1x_uclass_indoff_autoinc_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x04_uclass.h
146
return (v & 0x1) << 27;
drivers/gpu/host1x/hw/hw_host1x04_uclass.h
148
#define HOST1X_UCLASS_INDOFF_AUTOINC_F(v) \
drivers/gpu/host1x/hw/hw_host1x04_uclass.h
149
host1x_uclass_indoff_autoinc_f(v)
drivers/gpu/host1x/hw/hw_host1x04_uclass.h
150
static inline u32 host1x_uclass_indoff_indmodid_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x04_uclass.h
152
return (v & 0xff) << 18;
drivers/gpu/host1x/hw/hw_host1x04_uclass.h
154
#define HOST1X_UCLASS_INDOFF_INDMODID_F(v) \
drivers/gpu/host1x/hw/hw_host1x04_uclass.h
155
host1x_uclass_indoff_indmodid_f(v)
drivers/gpu/host1x/hw/hw_host1x04_uclass.h
156
static inline u32 host1x_uclass_indoff_indroffset_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x04_uclass.h
158
return (v & 0xffff) << 2;
drivers/gpu/host1x/hw/hw_host1x04_uclass.h
160
#define HOST1X_UCLASS_INDOFF_INDROFFSET_F(v) \
drivers/gpu/host1x/hw/hw_host1x04_uclass.h
161
host1x_uclass_indoff_indroffset_f(v)
drivers/gpu/host1x/hw/hw_host1x04_uclass.h
166
#define HOST1X_UCLASS_INDOFF_INDROFFSET_F(v) \
drivers/gpu/host1x/hw/hw_host1x04_uclass.h
167
host1x_uclass_indoff_indroffset_f(v)
drivers/gpu/host1x/hw/hw_host1x04_uclass.h
48
static inline u32 host1x_uclass_incr_syncpt_cond_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x04_uclass.h
50
return (v & 0xff) << 8;
drivers/gpu/host1x/hw/hw_host1x04_uclass.h
52
#define HOST1X_UCLASS_INCR_SYNCPT_COND_F(v) \
drivers/gpu/host1x/hw/hw_host1x04_uclass.h
53
host1x_uclass_incr_syncpt_cond_f(v)
drivers/gpu/host1x/hw/hw_host1x04_uclass.h
54
static inline u32 host1x_uclass_incr_syncpt_indx_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x04_uclass.h
56
return (v & 0xff) << 0;
drivers/gpu/host1x/hw/hw_host1x04_uclass.h
58
#define HOST1X_UCLASS_INCR_SYNCPT_INDX_F(v) \
drivers/gpu/host1x/hw/hw_host1x04_uclass.h
59
host1x_uclass_incr_syncpt_indx_f(v)
drivers/gpu/host1x/hw/hw_host1x04_uclass.h
66
static inline u32 host1x_uclass_wait_syncpt_indx_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x04_uclass.h
68
return (v & 0xff) << 24;
drivers/gpu/host1x/hw/hw_host1x04_uclass.h
70
#define HOST1X_UCLASS_WAIT_SYNCPT_INDX_F(v) \
drivers/gpu/host1x/hw/hw_host1x04_uclass.h
71
host1x_uclass_wait_syncpt_indx_f(v)
drivers/gpu/host1x/hw/hw_host1x04_uclass.h
72
static inline u32 host1x_uclass_wait_syncpt_thresh_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x04_uclass.h
74
return (v & 0xffffff) << 0;
drivers/gpu/host1x/hw/hw_host1x04_uclass.h
76
#define HOST1X_UCLASS_WAIT_SYNCPT_THRESH_F(v) \
drivers/gpu/host1x/hw/hw_host1x04_uclass.h
77
host1x_uclass_wait_syncpt_thresh_f(v)
drivers/gpu/host1x/hw/hw_host1x04_uclass.h
84
static inline u32 host1x_uclass_wait_syncpt_base_indx_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x04_uclass.h
86
return (v & 0xff) << 24;
drivers/gpu/host1x/hw/hw_host1x04_uclass.h
88
#define HOST1X_UCLASS_WAIT_SYNCPT_BASE_INDX_F(v) \
drivers/gpu/host1x/hw/hw_host1x04_uclass.h
89
host1x_uclass_wait_syncpt_base_indx_f(v)
drivers/gpu/host1x/hw/hw_host1x04_uclass.h
90
static inline u32 host1x_uclass_wait_syncpt_base_base_indx_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x04_uclass.h
92
return (v & 0xff) << 16;
drivers/gpu/host1x/hw/hw_host1x04_uclass.h
94
#define HOST1X_UCLASS_WAIT_SYNCPT_BASE_BASE_INDX_F(v) \
drivers/gpu/host1x/hw/hw_host1x04_uclass.h
95
host1x_uclass_wait_syncpt_base_base_indx_f(v)
drivers/gpu/host1x/hw/hw_host1x04_uclass.h
96
static inline u32 host1x_uclass_wait_syncpt_base_offset_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x04_uclass.h
98
return (v & 0xffff) << 0;
drivers/gpu/host1x/hw/hw_host1x05_channel.h
114
static inline u32 host1x_channel_channelctrl_kernel_filter_gbuffer_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x05_channel.h
116
return (v & 0x1) << 2;
drivers/gpu/host1x/hw/hw_host1x05_channel.h
118
#define HOST1X_CHANNEL_CHANNELCTRL_KERNEL_FILTER_GBUFFER(v) \
drivers/gpu/host1x/hw/hw_host1x05_channel.h
119
host1x_channel_channelctrl_kernel_filter_gbuffer_f(v)
drivers/gpu/host1x/hw/hw_host1x05_sync.h
126
#define HOST1X_SYNC_MLOCK_OWNER_CHID_V(v) \
drivers/gpu/host1x/hw/hw_host1x05_sync.h
127
host1x_sync_mlock_owner_chid_v(v)
drivers/gpu/host1x/hw/hw_host1x05_sync.h
170
static inline u32 host1x_sync_cfpeek_ctrl_addr_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x05_sync.h
172
return (v & 0x3ff) << 0;
drivers/gpu/host1x/hw/hw_host1x05_sync.h
174
#define HOST1X_SYNC_CFPEEK_CTRL_ADDR_F(v) \
drivers/gpu/host1x/hw/hw_host1x05_sync.h
175
host1x_sync_cfpeek_ctrl_addr_f(v)
drivers/gpu/host1x/hw/hw_host1x05_sync.h
176
static inline u32 host1x_sync_cfpeek_ctrl_channr_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x05_sync.h
178
return (v & 0xf) << 16;
drivers/gpu/host1x/hw/hw_host1x05_sync.h
180
#define HOST1X_SYNC_CFPEEK_CTRL_CHANNR_F(v) \
drivers/gpu/host1x/hw/hw_host1x05_sync.h
181
host1x_sync_cfpeek_ctrl_channr_f(v)
drivers/gpu/host1x/hw/hw_host1x05_sync.h
182
static inline u32 host1x_sync_cfpeek_ctrl_ena_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x05_sync.h
184
return (v & 0x1) << 31;
drivers/gpu/host1x/hw/hw_host1x05_sync.h
186
#define HOST1X_SYNC_CFPEEK_CTRL_ENA_F(v) \
drivers/gpu/host1x/hw/hw_host1x05_sync.h
187
host1x_sync_cfpeek_ctrl_ena_f(v)
drivers/gpu/host1x/hw/hw_host1x05_uclass.h
100
#define HOST1X_UCLASS_WAIT_SYNCPT_BASE_OFFSET_F(v) \
drivers/gpu/host1x/hw/hw_host1x05_uclass.h
101
host1x_uclass_wait_syncpt_base_offset_f(v)
drivers/gpu/host1x/hw/hw_host1x05_uclass.h
108
static inline u32 host1x_uclass_load_syncpt_base_base_indx_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x05_uclass.h
110
return (v & 0xff) << 24;
drivers/gpu/host1x/hw/hw_host1x05_uclass.h
112
#define HOST1X_UCLASS_LOAD_SYNCPT_BASE_BASE_INDX_F(v) \
drivers/gpu/host1x/hw/hw_host1x05_uclass.h
113
host1x_uclass_load_syncpt_base_base_indx_f(v)
drivers/gpu/host1x/hw/hw_host1x05_uclass.h
114
static inline u32 host1x_uclass_load_syncpt_base_value_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x05_uclass.h
116
return (v & 0xffffff) << 0;
drivers/gpu/host1x/hw/hw_host1x05_uclass.h
118
#define HOST1X_UCLASS_LOAD_SYNCPT_BASE_VALUE_F(v) \
drivers/gpu/host1x/hw/hw_host1x05_uclass.h
119
host1x_uclass_load_syncpt_base_value_f(v)
drivers/gpu/host1x/hw/hw_host1x05_uclass.h
120
static inline u32 host1x_uclass_incr_syncpt_base_base_indx_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x05_uclass.h
122
return (v & 0xff) << 24;
drivers/gpu/host1x/hw/hw_host1x05_uclass.h
124
#define HOST1X_UCLASS_INCR_SYNCPT_BASE_BASE_INDX_F(v) \
drivers/gpu/host1x/hw/hw_host1x05_uclass.h
125
host1x_uclass_incr_syncpt_base_base_indx_f(v)
drivers/gpu/host1x/hw/hw_host1x05_uclass.h
126
static inline u32 host1x_uclass_incr_syncpt_base_offset_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x05_uclass.h
128
return (v & 0xffffff) << 0;
drivers/gpu/host1x/hw/hw_host1x05_uclass.h
130
#define HOST1X_UCLASS_INCR_SYNCPT_BASE_OFFSET_F(v) \
drivers/gpu/host1x/hw/hw_host1x05_uclass.h
131
host1x_uclass_incr_syncpt_base_offset_f(v)
drivers/gpu/host1x/hw/hw_host1x05_uclass.h
138
static inline u32 host1x_uclass_indoff_indbe_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x05_uclass.h
140
return (v & 0xf) << 28;
drivers/gpu/host1x/hw/hw_host1x05_uclass.h
142
#define HOST1X_UCLASS_INDOFF_INDBE_F(v) \
drivers/gpu/host1x/hw/hw_host1x05_uclass.h
143
host1x_uclass_indoff_indbe_f(v)
drivers/gpu/host1x/hw/hw_host1x05_uclass.h
144
static inline u32 host1x_uclass_indoff_autoinc_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x05_uclass.h
146
return (v & 0x1) << 27;
drivers/gpu/host1x/hw/hw_host1x05_uclass.h
148
#define HOST1X_UCLASS_INDOFF_AUTOINC_F(v) \
drivers/gpu/host1x/hw/hw_host1x05_uclass.h
149
host1x_uclass_indoff_autoinc_f(v)
drivers/gpu/host1x/hw/hw_host1x05_uclass.h
150
static inline u32 host1x_uclass_indoff_indmodid_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x05_uclass.h
152
return (v & 0xff) << 18;
drivers/gpu/host1x/hw/hw_host1x05_uclass.h
154
#define HOST1X_UCLASS_INDOFF_INDMODID_F(v) \
drivers/gpu/host1x/hw/hw_host1x05_uclass.h
155
host1x_uclass_indoff_indmodid_f(v)
drivers/gpu/host1x/hw/hw_host1x05_uclass.h
156
static inline u32 host1x_uclass_indoff_indroffset_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x05_uclass.h
158
return (v & 0xffff) << 2;
drivers/gpu/host1x/hw/hw_host1x05_uclass.h
160
#define HOST1X_UCLASS_INDOFF_INDROFFSET_F(v) \
drivers/gpu/host1x/hw/hw_host1x05_uclass.h
161
host1x_uclass_indoff_indroffset_f(v)
drivers/gpu/host1x/hw/hw_host1x05_uclass.h
166
#define HOST1X_UCLASS_INDOFF_INDROFFSET_F(v) \
drivers/gpu/host1x/hw/hw_host1x05_uclass.h
167
host1x_uclass_indoff_indroffset_f(v)
drivers/gpu/host1x/hw/hw_host1x05_uclass.h
48
static inline u32 host1x_uclass_incr_syncpt_cond_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x05_uclass.h
50
return (v & 0xff) << 8;
drivers/gpu/host1x/hw/hw_host1x05_uclass.h
52
#define HOST1X_UCLASS_INCR_SYNCPT_COND_F(v) \
drivers/gpu/host1x/hw/hw_host1x05_uclass.h
53
host1x_uclass_incr_syncpt_cond_f(v)
drivers/gpu/host1x/hw/hw_host1x05_uclass.h
54
static inline u32 host1x_uclass_incr_syncpt_indx_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x05_uclass.h
56
return (v & 0xff) << 0;
drivers/gpu/host1x/hw/hw_host1x05_uclass.h
58
#define HOST1X_UCLASS_INCR_SYNCPT_INDX_F(v) \
drivers/gpu/host1x/hw/hw_host1x05_uclass.h
59
host1x_uclass_incr_syncpt_indx_f(v)
drivers/gpu/host1x/hw/hw_host1x05_uclass.h
66
static inline u32 host1x_uclass_wait_syncpt_indx_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x05_uclass.h
68
return (v & 0xff) << 24;
drivers/gpu/host1x/hw/hw_host1x05_uclass.h
70
#define HOST1X_UCLASS_WAIT_SYNCPT_INDX_F(v) \
drivers/gpu/host1x/hw/hw_host1x05_uclass.h
71
host1x_uclass_wait_syncpt_indx_f(v)
drivers/gpu/host1x/hw/hw_host1x05_uclass.h
72
static inline u32 host1x_uclass_wait_syncpt_thresh_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x05_uclass.h
74
return (v & 0xffffff) << 0;
drivers/gpu/host1x/hw/hw_host1x05_uclass.h
76
#define HOST1X_UCLASS_WAIT_SYNCPT_THRESH_F(v) \
drivers/gpu/host1x/hw/hw_host1x05_uclass.h
77
host1x_uclass_wait_syncpt_thresh_f(v)
drivers/gpu/host1x/hw/hw_host1x05_uclass.h
84
static inline u32 host1x_uclass_wait_syncpt_base_indx_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x05_uclass.h
86
return (v & 0xff) << 24;
drivers/gpu/host1x/hw/hw_host1x05_uclass.h
88
#define HOST1X_UCLASS_WAIT_SYNCPT_BASE_INDX_F(v) \
drivers/gpu/host1x/hw/hw_host1x05_uclass.h
89
host1x_uclass_wait_syncpt_base_indx_f(v)
drivers/gpu/host1x/hw/hw_host1x05_uclass.h
90
static inline u32 host1x_uclass_wait_syncpt_base_base_indx_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x05_uclass.h
92
return (v & 0xff) << 16;
drivers/gpu/host1x/hw/hw_host1x05_uclass.h
94
#define HOST1X_UCLASS_WAIT_SYNCPT_BASE_BASE_INDX_F(v) \
drivers/gpu/host1x/hw/hw_host1x05_uclass.h
95
host1x_uclass_wait_syncpt_base_base_indx_f(v)
drivers/gpu/host1x/hw/hw_host1x05_uclass.h
96
static inline u32 host1x_uclass_wait_syncpt_base_offset_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x05_uclass.h
98
return (v & 0xffff) << 0;
drivers/gpu/host1x/hw/hw_host1x06_uclass.h
100
#define HOST1X_UCLASS_WAIT_SYNCPT_BASE_OFFSET_F(v) \
drivers/gpu/host1x/hw/hw_host1x06_uclass.h
101
host1x_uclass_wait_syncpt_base_offset_f(v)
drivers/gpu/host1x/hw/hw_host1x06_uclass.h
108
static inline u32 host1x_uclass_load_syncpt_base_base_indx_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x06_uclass.h
110
return (v & 0xff) << 24;
drivers/gpu/host1x/hw/hw_host1x06_uclass.h
112
#define HOST1X_UCLASS_LOAD_SYNCPT_BASE_BASE_INDX_F(v) \
drivers/gpu/host1x/hw/hw_host1x06_uclass.h
113
host1x_uclass_load_syncpt_base_base_indx_f(v)
drivers/gpu/host1x/hw/hw_host1x06_uclass.h
114
static inline u32 host1x_uclass_load_syncpt_base_value_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x06_uclass.h
116
return (v & 0xffffff) << 0;
drivers/gpu/host1x/hw/hw_host1x06_uclass.h
118
#define HOST1X_UCLASS_LOAD_SYNCPT_BASE_VALUE_F(v) \
drivers/gpu/host1x/hw/hw_host1x06_uclass.h
119
host1x_uclass_load_syncpt_base_value_f(v)
drivers/gpu/host1x/hw/hw_host1x06_uclass.h
120
static inline u32 host1x_uclass_incr_syncpt_base_base_indx_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x06_uclass.h
122
return (v & 0xff) << 24;
drivers/gpu/host1x/hw/hw_host1x06_uclass.h
124
#define HOST1X_UCLASS_INCR_SYNCPT_BASE_BASE_INDX_F(v) \
drivers/gpu/host1x/hw/hw_host1x06_uclass.h
125
host1x_uclass_incr_syncpt_base_base_indx_f(v)
drivers/gpu/host1x/hw/hw_host1x06_uclass.h
126
static inline u32 host1x_uclass_incr_syncpt_base_offset_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x06_uclass.h
128
return (v & 0xffffff) << 0;
drivers/gpu/host1x/hw/hw_host1x06_uclass.h
130
#define HOST1X_UCLASS_INCR_SYNCPT_BASE_OFFSET_F(v) \
drivers/gpu/host1x/hw/hw_host1x06_uclass.h
131
host1x_uclass_incr_syncpt_base_offset_f(v)
drivers/gpu/host1x/hw/hw_host1x06_uclass.h
138
static inline u32 host1x_uclass_indoff_indbe_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x06_uclass.h
140
return (v & 0xf) << 28;
drivers/gpu/host1x/hw/hw_host1x06_uclass.h
142
#define HOST1X_UCLASS_INDOFF_INDBE_F(v) \
drivers/gpu/host1x/hw/hw_host1x06_uclass.h
143
host1x_uclass_indoff_indbe_f(v)
drivers/gpu/host1x/hw/hw_host1x06_uclass.h
144
static inline u32 host1x_uclass_indoff_autoinc_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x06_uclass.h
146
return (v & 0x1) << 27;
drivers/gpu/host1x/hw/hw_host1x06_uclass.h
148
#define HOST1X_UCLASS_INDOFF_AUTOINC_F(v) \
drivers/gpu/host1x/hw/hw_host1x06_uclass.h
149
host1x_uclass_indoff_autoinc_f(v)
drivers/gpu/host1x/hw/hw_host1x06_uclass.h
150
static inline u32 host1x_uclass_indoff_indmodid_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x06_uclass.h
152
return (v & 0xff) << 18;
drivers/gpu/host1x/hw/hw_host1x06_uclass.h
154
#define HOST1X_UCLASS_INDOFF_INDMODID_F(v) \
drivers/gpu/host1x/hw/hw_host1x06_uclass.h
155
host1x_uclass_indoff_indmodid_f(v)
drivers/gpu/host1x/hw/hw_host1x06_uclass.h
156
static inline u32 host1x_uclass_indoff_indroffset_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x06_uclass.h
158
return (v & 0xffff) << 2;
drivers/gpu/host1x/hw/hw_host1x06_uclass.h
160
#define HOST1X_UCLASS_INDOFF_INDROFFSET_F(v) \
drivers/gpu/host1x/hw/hw_host1x06_uclass.h
161
host1x_uclass_indoff_indroffset_f(v)
drivers/gpu/host1x/hw/hw_host1x06_uclass.h
166
#define HOST1X_UCLASS_INDOFF_INDROFFSET_F(v) \
drivers/gpu/host1x/hw/hw_host1x06_uclass.h
167
host1x_uclass_indoff_indroffset_f(v)
drivers/gpu/host1x/hw/hw_host1x06_uclass.h
48
static inline u32 host1x_uclass_incr_syncpt_cond_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x06_uclass.h
50
return (v & 0xff) << 10;
drivers/gpu/host1x/hw/hw_host1x06_uclass.h
52
#define HOST1X_UCLASS_INCR_SYNCPT_COND_F(v) \
drivers/gpu/host1x/hw/hw_host1x06_uclass.h
53
host1x_uclass_incr_syncpt_cond_f(v)
drivers/gpu/host1x/hw/hw_host1x06_uclass.h
54
static inline u32 host1x_uclass_incr_syncpt_indx_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x06_uclass.h
56
return (v & 0x3ff) << 0;
drivers/gpu/host1x/hw/hw_host1x06_uclass.h
58
#define HOST1X_UCLASS_INCR_SYNCPT_INDX_F(v) \
drivers/gpu/host1x/hw/hw_host1x06_uclass.h
59
host1x_uclass_incr_syncpt_indx_f(v)
drivers/gpu/host1x/hw/hw_host1x06_uclass.h
66
static inline u32 host1x_uclass_wait_syncpt_indx_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x06_uclass.h
68
return (v & 0xff) << 24;
drivers/gpu/host1x/hw/hw_host1x06_uclass.h
70
#define HOST1X_UCLASS_WAIT_SYNCPT_INDX_F(v) \
drivers/gpu/host1x/hw/hw_host1x06_uclass.h
71
host1x_uclass_wait_syncpt_indx_f(v)
drivers/gpu/host1x/hw/hw_host1x06_uclass.h
72
static inline u32 host1x_uclass_wait_syncpt_thresh_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x06_uclass.h
74
return (v & 0xffffff) << 0;
drivers/gpu/host1x/hw/hw_host1x06_uclass.h
76
#define HOST1X_UCLASS_WAIT_SYNCPT_THRESH_F(v) \
drivers/gpu/host1x/hw/hw_host1x06_uclass.h
77
host1x_uclass_wait_syncpt_thresh_f(v)
drivers/gpu/host1x/hw/hw_host1x06_uclass.h
84
static inline u32 host1x_uclass_wait_syncpt_base_indx_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x06_uclass.h
86
return (v & 0xff) << 24;
drivers/gpu/host1x/hw/hw_host1x06_uclass.h
88
#define HOST1X_UCLASS_WAIT_SYNCPT_BASE_INDX_F(v) \
drivers/gpu/host1x/hw/hw_host1x06_uclass.h
89
host1x_uclass_wait_syncpt_base_indx_f(v)
drivers/gpu/host1x/hw/hw_host1x06_uclass.h
90
static inline u32 host1x_uclass_wait_syncpt_base_base_indx_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x06_uclass.h
92
return (v & 0xff) << 16;
drivers/gpu/host1x/hw/hw_host1x06_uclass.h
94
#define HOST1X_UCLASS_WAIT_SYNCPT_BASE_BASE_INDX_F(v) \
drivers/gpu/host1x/hw/hw_host1x06_uclass.h
95
host1x_uclass_wait_syncpt_base_base_indx_f(v)
drivers/gpu/host1x/hw/hw_host1x06_uclass.h
96
static inline u32 host1x_uclass_wait_syncpt_base_offset_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x06_uclass.h
98
return (v & 0xffff) << 0;
drivers/gpu/host1x/hw/hw_host1x06_vm.h
35
#define HOST1X_SYNC_SYNCPT_CH_APP_CH(v) (((v) & 0x3f) << 8)
drivers/gpu/host1x/hw/hw_host1x07_uclass.h
100
#define HOST1X_UCLASS_WAIT_SYNCPT_BASE_OFFSET_F(v) \
drivers/gpu/host1x/hw/hw_host1x07_uclass.h
101
host1x_uclass_wait_syncpt_base_offset_f(v)
drivers/gpu/host1x/hw/hw_host1x07_uclass.h
108
static inline u32 host1x_uclass_load_syncpt_base_base_indx_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x07_uclass.h
110
return (v & 0xff) << 24;
drivers/gpu/host1x/hw/hw_host1x07_uclass.h
112
#define HOST1X_UCLASS_LOAD_SYNCPT_BASE_BASE_INDX_F(v) \
drivers/gpu/host1x/hw/hw_host1x07_uclass.h
113
host1x_uclass_load_syncpt_base_base_indx_f(v)
drivers/gpu/host1x/hw/hw_host1x07_uclass.h
114
static inline u32 host1x_uclass_load_syncpt_base_value_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x07_uclass.h
116
return (v & 0xffffff) << 0;
drivers/gpu/host1x/hw/hw_host1x07_uclass.h
118
#define HOST1X_UCLASS_LOAD_SYNCPT_BASE_VALUE_F(v) \
drivers/gpu/host1x/hw/hw_host1x07_uclass.h
119
host1x_uclass_load_syncpt_base_value_f(v)
drivers/gpu/host1x/hw/hw_host1x07_uclass.h
120
static inline u32 host1x_uclass_incr_syncpt_base_base_indx_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x07_uclass.h
122
return (v & 0xff) << 24;
drivers/gpu/host1x/hw/hw_host1x07_uclass.h
124
#define HOST1X_UCLASS_INCR_SYNCPT_BASE_BASE_INDX_F(v) \
drivers/gpu/host1x/hw/hw_host1x07_uclass.h
125
host1x_uclass_incr_syncpt_base_base_indx_f(v)
drivers/gpu/host1x/hw/hw_host1x07_uclass.h
126
static inline u32 host1x_uclass_incr_syncpt_base_offset_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x07_uclass.h
128
return (v & 0xffffff) << 0;
drivers/gpu/host1x/hw/hw_host1x07_uclass.h
130
#define HOST1X_UCLASS_INCR_SYNCPT_BASE_OFFSET_F(v) \
drivers/gpu/host1x/hw/hw_host1x07_uclass.h
131
host1x_uclass_incr_syncpt_base_offset_f(v)
drivers/gpu/host1x/hw/hw_host1x07_uclass.h
138
static inline u32 host1x_uclass_indoff_indbe_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x07_uclass.h
140
return (v & 0xf) << 28;
drivers/gpu/host1x/hw/hw_host1x07_uclass.h
142
#define HOST1X_UCLASS_INDOFF_INDBE_F(v) \
drivers/gpu/host1x/hw/hw_host1x07_uclass.h
143
host1x_uclass_indoff_indbe_f(v)
drivers/gpu/host1x/hw/hw_host1x07_uclass.h
144
static inline u32 host1x_uclass_indoff_autoinc_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x07_uclass.h
146
return (v & 0x1) << 27;
drivers/gpu/host1x/hw/hw_host1x07_uclass.h
148
#define HOST1X_UCLASS_INDOFF_AUTOINC_F(v) \
drivers/gpu/host1x/hw/hw_host1x07_uclass.h
149
host1x_uclass_indoff_autoinc_f(v)
drivers/gpu/host1x/hw/hw_host1x07_uclass.h
150
static inline u32 host1x_uclass_indoff_indmodid_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x07_uclass.h
152
return (v & 0xff) << 18;
drivers/gpu/host1x/hw/hw_host1x07_uclass.h
154
#define HOST1X_UCLASS_INDOFF_INDMODID_F(v) \
drivers/gpu/host1x/hw/hw_host1x07_uclass.h
155
host1x_uclass_indoff_indmodid_f(v)
drivers/gpu/host1x/hw/hw_host1x07_uclass.h
156
static inline u32 host1x_uclass_indoff_indroffset_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x07_uclass.h
158
return (v & 0xffff) << 2;
drivers/gpu/host1x/hw/hw_host1x07_uclass.h
160
#define HOST1X_UCLASS_INDOFF_INDROFFSET_F(v) \
drivers/gpu/host1x/hw/hw_host1x07_uclass.h
161
host1x_uclass_indoff_indroffset_f(v)
drivers/gpu/host1x/hw/hw_host1x07_uclass.h
166
#define HOST1X_UCLASS_INDOFF_INDROFFSET_F(v) \
drivers/gpu/host1x/hw/hw_host1x07_uclass.h
167
host1x_uclass_indoff_indroffset_f(v)
drivers/gpu/host1x/hw/hw_host1x07_uclass.h
48
static inline u32 host1x_uclass_incr_syncpt_cond_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x07_uclass.h
50
return (v & 0xff) << 10;
drivers/gpu/host1x/hw/hw_host1x07_uclass.h
52
#define HOST1X_UCLASS_INCR_SYNCPT_COND_F(v) \
drivers/gpu/host1x/hw/hw_host1x07_uclass.h
53
host1x_uclass_incr_syncpt_cond_f(v)
drivers/gpu/host1x/hw/hw_host1x07_uclass.h
54
static inline u32 host1x_uclass_incr_syncpt_indx_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x07_uclass.h
56
return (v & 0x3ff) << 0;
drivers/gpu/host1x/hw/hw_host1x07_uclass.h
58
#define HOST1X_UCLASS_INCR_SYNCPT_INDX_F(v) \
drivers/gpu/host1x/hw/hw_host1x07_uclass.h
59
host1x_uclass_incr_syncpt_indx_f(v)
drivers/gpu/host1x/hw/hw_host1x07_uclass.h
66
static inline u32 host1x_uclass_wait_syncpt_indx_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x07_uclass.h
68
return (v & 0xff) << 24;
drivers/gpu/host1x/hw/hw_host1x07_uclass.h
70
#define HOST1X_UCLASS_WAIT_SYNCPT_INDX_F(v) \
drivers/gpu/host1x/hw/hw_host1x07_uclass.h
71
host1x_uclass_wait_syncpt_indx_f(v)
drivers/gpu/host1x/hw/hw_host1x07_uclass.h
72
static inline u32 host1x_uclass_wait_syncpt_thresh_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x07_uclass.h
74
return (v & 0xffffff) << 0;
drivers/gpu/host1x/hw/hw_host1x07_uclass.h
76
#define HOST1X_UCLASS_WAIT_SYNCPT_THRESH_F(v) \
drivers/gpu/host1x/hw/hw_host1x07_uclass.h
77
host1x_uclass_wait_syncpt_thresh_f(v)
drivers/gpu/host1x/hw/hw_host1x07_uclass.h
84
static inline u32 host1x_uclass_wait_syncpt_base_indx_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x07_uclass.h
86
return (v & 0xff) << 24;
drivers/gpu/host1x/hw/hw_host1x07_uclass.h
88
#define HOST1X_UCLASS_WAIT_SYNCPT_BASE_INDX_F(v) \
drivers/gpu/host1x/hw/hw_host1x07_uclass.h
89
host1x_uclass_wait_syncpt_base_indx_f(v)
drivers/gpu/host1x/hw/hw_host1x07_uclass.h
90
static inline u32 host1x_uclass_wait_syncpt_base_base_indx_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x07_uclass.h
92
return (v & 0xff) << 16;
drivers/gpu/host1x/hw/hw_host1x07_uclass.h
94
#define HOST1X_UCLASS_WAIT_SYNCPT_BASE_BASE_INDX_F(v) \
drivers/gpu/host1x/hw/hw_host1x07_uclass.h
95
host1x_uclass_wait_syncpt_base_base_indx_f(v)
drivers/gpu/host1x/hw/hw_host1x07_uclass.h
96
static inline u32 host1x_uclass_wait_syncpt_base_offset_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x07_uclass.h
98
return (v & 0xffff) << 0;
drivers/gpu/host1x/hw/hw_host1x07_vm.h
34
#define HOST1X_SYNC_SYNCPT_CH_APP_CH(v) (((v) & 0x3f) << 8)
drivers/gpu/host1x/hw/hw_host1x08_uclass.h
100
#define HOST1X_UCLASS_WAIT_SYNCPT_BASE_OFFSET_F(v) \
drivers/gpu/host1x/hw/hw_host1x08_uclass.h
101
host1x_uclass_wait_syncpt_base_offset_f(v)
drivers/gpu/host1x/hw/hw_host1x08_uclass.h
108
static inline u32 host1x_uclass_load_syncpt_base_base_indx_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x08_uclass.h
110
return (v & 0xff) << 24;
drivers/gpu/host1x/hw/hw_host1x08_uclass.h
112
#define HOST1X_UCLASS_LOAD_SYNCPT_BASE_BASE_INDX_F(v) \
drivers/gpu/host1x/hw/hw_host1x08_uclass.h
113
host1x_uclass_load_syncpt_base_base_indx_f(v)
drivers/gpu/host1x/hw/hw_host1x08_uclass.h
114
static inline u32 host1x_uclass_load_syncpt_base_value_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x08_uclass.h
116
return (v & 0xffffff) << 0;
drivers/gpu/host1x/hw/hw_host1x08_uclass.h
118
#define HOST1X_UCLASS_LOAD_SYNCPT_BASE_VALUE_F(v) \
drivers/gpu/host1x/hw/hw_host1x08_uclass.h
119
host1x_uclass_load_syncpt_base_value_f(v)
drivers/gpu/host1x/hw/hw_host1x08_uclass.h
120
static inline u32 host1x_uclass_incr_syncpt_base_base_indx_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x08_uclass.h
122
return (v & 0xff) << 24;
drivers/gpu/host1x/hw/hw_host1x08_uclass.h
124
#define HOST1X_UCLASS_INCR_SYNCPT_BASE_BASE_INDX_F(v) \
drivers/gpu/host1x/hw/hw_host1x08_uclass.h
125
host1x_uclass_incr_syncpt_base_base_indx_f(v)
drivers/gpu/host1x/hw/hw_host1x08_uclass.h
126
static inline u32 host1x_uclass_incr_syncpt_base_offset_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x08_uclass.h
128
return (v & 0xffffff) << 0;
drivers/gpu/host1x/hw/hw_host1x08_uclass.h
130
#define HOST1X_UCLASS_INCR_SYNCPT_BASE_OFFSET_F(v) \
drivers/gpu/host1x/hw/hw_host1x08_uclass.h
131
host1x_uclass_incr_syncpt_base_offset_f(v)
drivers/gpu/host1x/hw/hw_host1x08_uclass.h
138
static inline u32 host1x_uclass_indoff_indbe_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x08_uclass.h
140
return (v & 0xf) << 28;
drivers/gpu/host1x/hw/hw_host1x08_uclass.h
142
#define HOST1X_UCLASS_INDOFF_INDBE_F(v) \
drivers/gpu/host1x/hw/hw_host1x08_uclass.h
143
host1x_uclass_indoff_indbe_f(v)
drivers/gpu/host1x/hw/hw_host1x08_uclass.h
144
static inline u32 host1x_uclass_indoff_autoinc_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x08_uclass.h
146
return (v & 0x1) << 27;
drivers/gpu/host1x/hw/hw_host1x08_uclass.h
148
#define HOST1X_UCLASS_INDOFF_AUTOINC_F(v) \
drivers/gpu/host1x/hw/hw_host1x08_uclass.h
149
host1x_uclass_indoff_autoinc_f(v)
drivers/gpu/host1x/hw/hw_host1x08_uclass.h
150
static inline u32 host1x_uclass_indoff_indmodid_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x08_uclass.h
152
return (v & 0xff) << 18;
drivers/gpu/host1x/hw/hw_host1x08_uclass.h
154
#define HOST1X_UCLASS_INDOFF_INDMODID_F(v) \
drivers/gpu/host1x/hw/hw_host1x08_uclass.h
155
host1x_uclass_indoff_indmodid_f(v)
drivers/gpu/host1x/hw/hw_host1x08_uclass.h
156
static inline u32 host1x_uclass_indoff_indroffset_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x08_uclass.h
158
return (v & 0xffff) << 2;
drivers/gpu/host1x/hw/hw_host1x08_uclass.h
160
#define HOST1X_UCLASS_INDOFF_INDROFFSET_F(v) \
drivers/gpu/host1x/hw/hw_host1x08_uclass.h
161
host1x_uclass_indoff_indroffset_f(v)
drivers/gpu/host1x/hw/hw_host1x08_uclass.h
166
#define HOST1X_UCLASS_INDOFF_INDROFFSET_F(v) \
drivers/gpu/host1x/hw/hw_host1x08_uclass.h
167
host1x_uclass_indoff_indroffset_f(v)
drivers/gpu/host1x/hw/hw_host1x08_uclass.h
48
static inline u32 host1x_uclass_incr_syncpt_cond_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x08_uclass.h
50
return (v & 0xff) << 10;
drivers/gpu/host1x/hw/hw_host1x08_uclass.h
52
#define HOST1X_UCLASS_INCR_SYNCPT_COND_F(v) \
drivers/gpu/host1x/hw/hw_host1x08_uclass.h
53
host1x_uclass_incr_syncpt_cond_f(v)
drivers/gpu/host1x/hw/hw_host1x08_uclass.h
54
static inline u32 host1x_uclass_incr_syncpt_indx_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x08_uclass.h
56
return (v & 0x3ff) << 0;
drivers/gpu/host1x/hw/hw_host1x08_uclass.h
58
#define HOST1X_UCLASS_INCR_SYNCPT_INDX_F(v) \
drivers/gpu/host1x/hw/hw_host1x08_uclass.h
59
host1x_uclass_incr_syncpt_indx_f(v)
drivers/gpu/host1x/hw/hw_host1x08_uclass.h
66
static inline u32 host1x_uclass_wait_syncpt_indx_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x08_uclass.h
68
return (v & 0xff) << 24;
drivers/gpu/host1x/hw/hw_host1x08_uclass.h
70
#define HOST1X_UCLASS_WAIT_SYNCPT_INDX_F(v) \
drivers/gpu/host1x/hw/hw_host1x08_uclass.h
71
host1x_uclass_wait_syncpt_indx_f(v)
drivers/gpu/host1x/hw/hw_host1x08_uclass.h
72
static inline u32 host1x_uclass_wait_syncpt_thresh_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x08_uclass.h
74
return (v & 0xffffff) << 0;
drivers/gpu/host1x/hw/hw_host1x08_uclass.h
76
#define HOST1X_UCLASS_WAIT_SYNCPT_THRESH_F(v) \
drivers/gpu/host1x/hw/hw_host1x08_uclass.h
77
host1x_uclass_wait_syncpt_thresh_f(v)
drivers/gpu/host1x/hw/hw_host1x08_uclass.h
84
static inline u32 host1x_uclass_wait_syncpt_base_indx_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x08_uclass.h
86
return (v & 0xff) << 24;
drivers/gpu/host1x/hw/hw_host1x08_uclass.h
88
#define HOST1X_UCLASS_WAIT_SYNCPT_BASE_INDX_F(v) \
drivers/gpu/host1x/hw/hw_host1x08_uclass.h
89
host1x_uclass_wait_syncpt_base_indx_f(v)
drivers/gpu/host1x/hw/hw_host1x08_uclass.h
90
static inline u32 host1x_uclass_wait_syncpt_base_base_indx_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x08_uclass.h
92
return (v & 0xff) << 16;
drivers/gpu/host1x/hw/hw_host1x08_uclass.h
94
#define HOST1X_UCLASS_WAIT_SYNCPT_BASE_BASE_INDX_F(v) \
drivers/gpu/host1x/hw/hw_host1x08_uclass.h
95
host1x_uclass_wait_syncpt_base_base_indx_f(v)
drivers/gpu/host1x/hw/hw_host1x08_uclass.h
96
static inline u32 host1x_uclass_wait_syncpt_base_offset_f(u32 v)
drivers/gpu/host1x/hw/hw_host1x08_uclass.h
98
return (v & 0xffff) << 0;
drivers/gpu/host1x/hw/hw_host1x08_vm.h
36
#define HOST1X_SYNC_SYNCPT_CH_APP_CH(v) (((v) & 0x3f) << 8)
drivers/gpu/host1x/hw/opcodes.h
52
u32 v = host1x_uclass_indoff_indbe_f(0xf)
drivers/gpu/host1x/hw/opcodes.h
56
v |= host1x_uclass_indoff_autoinc_f(1);
drivers/gpu/host1x/hw/opcodes.h
57
return v;
drivers/gpu/host1x/hw/opcodes.h
63
u32 v = host1x_uclass_indoff_indmodid_f(mod_id)
drivers/gpu/host1x/hw/opcodes.h
67
v |= host1x_uclass_indoff_autoinc_f(1);
drivers/gpu/host1x/hw/opcodes.h
68
return v;
drivers/gpu/ipu-v3/ipu-cpmem.c
100
static void ipu_ch_param_write_field(struct ipuv3_channel *ch, u32 wbs, u32 v)
drivers/gpu/ipu-v3/ipu-cpmem.c
115
val |= v << ofs;
drivers/gpu/ipu-v3/ipu-cpmem.c
121
val |= v >> (ofs ? (32 - ofs) : 0);
drivers/gpu/ipu-v3/ipu-pre.c
31
#define IPU_PRE_CTRL_HANDSHAKE_LINE_NUM(v) ((v & 0x3) << 9)
drivers/gpu/ipu-v3/ipu-pre.c
43
#define IPU_PRE_TPR_CTRL_TILE_FORMAT(v) ((v & 0xff) << 0)
drivers/gpu/ipu-v3/ipu-pre.c
52
#define IPU_PRE_PREF_ENG_CTRL_RD_NUM_BYTES(v) ((v & 0x7) << 1)
drivers/gpu/ipu-v3/ipu-pre.c
53
#define IPU_PRE_PREF_ENG_CTRL_INPUT_ACTIVE_BPP(v) ((v & 0x3) << 4)
drivers/gpu/ipu-v3/ipu-pre.c
54
#define IPU_PRE_PREF_ENG_CTRL_INPUT_PIXEL_FORMAT(v) ((v & 0x7) << 8)
drivers/gpu/ipu-v3/ipu-pre.c
61
#define IPU_PRE_PREFETCH_ENG_INPUT_SIZE_WIDTH(v) ((v & 0xffff) << 0)
drivers/gpu/ipu-v3/ipu-pre.c
62
#define IPU_PRE_PREFETCH_ENG_INPUT_SIZE_HEIGHT(v) ((v & 0xffff) << 16)
drivers/gpu/ipu-v3/ipu-pre.c
65
#define IPU_PRE_PREFETCH_ENG_PITCH_Y(v) ((v & 0xffff) << 0)
drivers/gpu/ipu-v3/ipu-pre.c
66
#define IPU_PRE_PREFETCH_ENG_PITCH_UV(v) ((v & 0xffff) << 16)
drivers/gpu/ipu-v3/ipu-pre.c
70
#define IPU_PRE_STORE_ENG_CTRL_WR_NUM_BYTES(v) ((v & 0x7) << 1)
drivers/gpu/ipu-v3/ipu-pre.c
71
#define IPU_PRE_STORE_ENG_CTRL_OUTPUT_ACTIVE_BPP(v) ((v & 0x3) << 4)
drivers/gpu/ipu-v3/ipu-pre.c
82
#define IPU_PRE_STORE_ENG_SIZE_INPUT_WIDTH(v) ((v & 0xffff) << 0)
drivers/gpu/ipu-v3/ipu-pre.c
83
#define IPU_PRE_STORE_ENG_SIZE_INPUT_HEIGHT(v) ((v & 0xffff) << 16)
drivers/gpu/ipu-v3/ipu-pre.c
86
#define IPU_PRE_STORE_ENG_PITCH_OUT_PITCH(v) ((v & 0xffff) << 0)
drivers/gpu/ipu-v3/ipu-prg.c
25
#define IPU_PRG_CTL_SOFT_ARID(i, v) ((v & 0x3) << (8 + 2 * i))
drivers/gpu/vga/vga_switcheroo.c
646
static int vga_switcheroo_show(struct seq_file *m, void *v)
drivers/hid/bpf/progs/WALTOP__Batteryless-Tablet.bpf.c
210
static unsigned int scaled_log2(__u16 v)
drivers/hid/bpf/progs/WALTOP__Batteryless-Tablet.bpf.c
215
unsigned int x = v + 1;
drivers/hid/hid-core.c
1086
__s32 v = *multiplier->value;
drivers/hid/hid-core.c
1105
m = ((v - lmin)/(lmax - lmin) * (pmax - pmin) + pmin);
drivers/hid/hid-logitech-hidpp.c
3265
int v;
drivers/hid/hid-logitech-hidpp.c
3282
v = sign_extend32(hid_field_extract(hdev, data + 3, 0, 12), 11);
drivers/hid/hid-logitech-hidpp.c
3283
input_report_rel(hidpp->input, REL_X, v);
drivers/hid/hid-logitech-hidpp.c
3285
v = sign_extend32(hid_field_extract(hdev, data + 3, 12, 12), 11);
drivers/hid/hid-logitech-hidpp.c
3286
input_report_rel(hidpp->input, REL_Y, v);
drivers/hid/hid-logitech-hidpp.c
3288
v = sign_extend32(data[6], 7);
drivers/hid/hid-logitech-hidpp.c
3289
if (v != 0)
drivers/hid/hid-logitech-hidpp.c
3291
&hidpp->vertical_wheel_counter, v);
drivers/hid/hid-multitouch.c
250
#define MT_USB_DEVICE(v, p) HID_DEVICE(BUS_USB, HID_GROUP_MULTITOUCH, v, p)
drivers/hid/hid-multitouch.c
251
#define MT_BT_DEVICE(v, p) HID_DEVICE(BUS_BLUETOOTH, HID_GROUP_MULTITOUCH, v, p)
drivers/hid/hid-uclogic-rdesc.c
1390
s32 v;
drivers/hid/hid-uclogic-rdesc.c
1400
v = param_list[p[sizeof(pen_head)]];
drivers/hid/hid-uclogic-rdesc.c
1401
put_unaligned((__force u32)cpu_to_le32(v), (s32 *)p);
drivers/hid/hid-uclogic-rdesc.c
1405
v = param_list[p[sizeof(btn_head)]];
drivers/hid/hid-uclogic-rdesc.c
1407
put_unaligned((__force u16)cpu_to_le16(v), (s16 *)(p + 1));
drivers/hv/hv_balloon.c
637
void *v)
drivers/hv/hv_balloon.c
639
struct memory_notify *mem = (struct memory_notify *)v;
drivers/hv/mshv_debugfs.c
192
static int vp_stats_show(struct seq_file *m, void *v)
drivers/hv/mshv_debugfs.c
261
static int partition_stats_show(struct seq_file *m, void *v)
drivers/hv/mshv_debugfs.c
41
static int lp_stats_show(struct seq_file *m, void *v)
drivers/hv/mshv_debugfs.c
549
static int hv_stats_show(struct seq_file *m, void *v)
drivers/hv/mshv_root.h
61
#define vp_devprintk(level, v, fmt, ...) \
drivers/hv/mshv_root.h
63
const struct mshv_vp *__vp = (v); \
drivers/hv/mshv_root.h
68
#define vp_emerg(v, fmt, ...) vp_devprintk(emerg, v, fmt, ##__VA_ARGS__)
drivers/hv/mshv_root.h
69
#define vp_crit(v, fmt, ...) vp_devprintk(crit, v, fmt, ##__VA_ARGS__)
drivers/hv/mshv_root.h
70
#define vp_alert(v, fmt, ...) vp_devprintk(alert, v, fmt, ##__VA_ARGS__)
drivers/hv/mshv_root.h
71
#define vp_err(v, fmt, ...) vp_devprintk(err, v, fmt, ##__VA_ARGS__)
drivers/hv/mshv_root.h
72
#define vp_warn(v, fmt, ...) vp_devprintk(warn, v, fmt, ##__VA_ARGS__)
drivers/hv/mshv_root.h
73
#define vp_notice(v, fmt, ...) vp_devprintk(notice, v, fmt, ##__VA_ARGS__)
drivers/hv/mshv_root.h
74
#define vp_info(v, fmt, ...) vp_devprintk(info, v, fmt, ##__VA_ARGS__)
drivers/hv/mshv_root.h
75
#define vp_dbg(v, fmt, ...) vp_devprintk(dbg, v, fmt, ##__VA_ARGS__)
drivers/hwmon/adt7475.c
2018
unsigned int v;
drivers/hwmon/adt7475.c
2026
v = (data->pwm[CONTROL][index] >> 5) & 7;
drivers/hwmon/adt7475.c
2028
if (v == 3)
drivers/hwmon/adt7475.c
2030
else if (v == 7)
drivers/hwmon/adt7475.c
2032
else if (v == 4) {
drivers/hwmon/adt7475.c
2052
switch (v) {
drivers/hwmon/fschmd.c
362
long v;
drivers/hwmon/fschmd.c
365
err = kstrtol(buf, 10, &v);
drivers/hwmon/fschmd.c
369
v = clamp_val(v / 1000, -128, 127) + 128;
drivers/hwmon/fschmd.c
373
FSCHMD_REG_TEMP_LIMIT[data->kind][index], v);
drivers/hwmon/fschmd.c
374
data->temp_max[index] = v;
drivers/hwmon/fschmd.c
436
unsigned long v;
drivers/hwmon/fschmd.c
439
err = kstrtoul(buf, 10, &v);
drivers/hwmon/fschmd.c
443
switch (v) {
drivers/hwmon/fschmd.c
445
v = 1;
drivers/hwmon/fschmd.c
448
v = 2;
drivers/hwmon/fschmd.c
451
v = 3;
drivers/hwmon/fschmd.c
456
v);
drivers/hwmon/fschmd.c
467
reg |= v;
drivers/hwmon/fschmd.c
525
unsigned long v;
drivers/hwmon/fschmd.c
528
err = kstrtoul(buf, 10, &v);
drivers/hwmon/fschmd.c
533
if (v || data->kind == fscsyl) {
drivers/hwmon/fschmd.c
534
v = clamp_val(v, 128, 255);
drivers/hwmon/fschmd.c
535
v = (v - 128) * 2 + 1;
drivers/hwmon/fschmd.c
541
FSCHMD_REG_FAN_MIN[data->kind][index], v);
drivers/hwmon/fschmd.c
542
data->fan_min[index] = v;
drivers/hwmon/fschmd.c
570
unsigned long v;
drivers/hwmon/fschmd.c
573
err = kstrtoul(buf, 10, &v);
drivers/hwmon/fschmd.c
581
if (v)
drivers/hwmon/gl520sm.c
251
long v;
drivers/hwmon/gl520sm.c
254
err = kstrtol(buf, 10, &v);
drivers/hwmon/gl520sm.c
261
r = VDD_TO_REG(v);
drivers/hwmon/gl520sm.c
263
r = IN_TO_REG(v);
drivers/hwmon/gl520sm.c
285
long v;
drivers/hwmon/gl520sm.c
288
err = kstrtol(buf, 10, &v);
drivers/hwmon/gl520sm.c
293
r = VDD_TO_REG(v);
drivers/hwmon/gl520sm.c
295
r = IN_TO_REG(v);
drivers/hwmon/gl520sm.c
382
unsigned long v;
drivers/hwmon/gl520sm.c
385
err = kstrtoul(buf, 10, &v);
drivers/hwmon/gl520sm.c
390
r = FAN_TO_REG(v, data->fan_div[n]);
drivers/hwmon/gl520sm.c
422
unsigned long v;
drivers/hwmon/gl520sm.c
425
err = kstrtoul(buf, 10, &v);
drivers/hwmon/gl520sm.c
429
switch (v) {
drivers/hwmon/gl520sm.c
444
"fan_div value %ld not supported. Choose one of 1, 2, 4 or 8!\n", v);
drivers/hwmon/gl520sm.c
471
unsigned long v;
drivers/hwmon/gl520sm.c
474
err = kstrtoul(buf, 10, &v);
drivers/hwmon/gl520sm.c
478
r = (v ? 1 : 0);
drivers/hwmon/gl520sm.c
535
long v;
drivers/hwmon/gl520sm.c
538
err = kstrtol(buf, 10, &v);
drivers/hwmon/gl520sm.c
543
data->temp_max[n] = TEMP_TO_REG(v);
drivers/hwmon/gl520sm.c
556
long v;
drivers/hwmon/gl520sm.c
559
err = kstrtol(buf, 10, &v);
drivers/hwmon/gl520sm.c
564
data->temp_max_hyst[n] = TEMP_TO_REG(v);
drivers/hwmon/gl520sm.c
606
unsigned long v;
drivers/hwmon/gl520sm.c
609
err = kstrtoul(buf, 10, &v);
drivers/hwmon/gl520sm.c
613
r = (v ? 0 : 1);
drivers/hwmon/nct7802.c
296
u8 v[2];
drivers/hwmon/nct7802.c
302
ret = regmap_multi_reg_read(data->regmap, regs, v, 2);
drivers/hwmon/nct7802.c
305
ret = ((v[0] << 2) | (v[1] >> 6)) * nct7802_vmul[nr];
drivers/hwmon/nct7802.c
311
ret = regmap_multi_reg_read(data->regmap, regs, v, 2);
drivers/hwmon/nct7802.c
314
ret = (v[0] | ((v[1] << shift) & 0x300)) * nct7802_vmul[nr];
drivers/hwmon/pmbus/max20730.c
401
static u16 val_to_direct(int v, enum pmbus_sensor_classes class,
drivers/hwmon/pmbus/max20730.c
408
d = v * info->m[class] + b;
drivers/hwmon/pmbus/stpddc60.c
45
long v, l;
drivers/hwmon/pmbus/stpddc60.c
47
v = 250 + (vout - 1) * 5; /* Convert VID to mv */
drivers/hwmon/pmbus/stpddc60.c
50
if (over == (l < v))
drivers/hwmon/pmbus/stpddc60.c
53
offset = DIV_ROUND_CLOSEST(abs(l - v), 50);
drivers/hwmon/sch56xx-common.c
102
static int sch56xx_send_cmd(u16 addr, u8 cmd, u16 reg, u8 v)
drivers/hwmon/sch56xx-common.c
131
outb(v, addr + 4);
drivers/hwmon/xgene-hwmon.c
34
#define MSG_TYPE(v) (((v) & 0xF0000000) >> 28)
drivers/hwmon/xgene-hwmon.c
35
#define MSG_TYPE_SET(v) (((v) << 28) & 0xF0000000)
drivers/hwmon/xgene-hwmon.c
36
#define MSG_SUBTYPE(v) (((v) & 0x0F000000) >> 24)
drivers/hwmon/xgene-hwmon.c
37
#define MSG_SUBTYPE_SET(v) (((v) << 24) & 0x0F000000)
drivers/hwmon/xgene-hwmon.c
54
#define TPC_CMD(v) (((v) & 0x00FF0000) >> 16)
drivers/hwmon/xgene-hwmon.c
55
#define TPC_CMD_SET(v) (((v) << 16) & 0x00FF0000)
drivers/hwtracing/coresight/coresight-core.c
1591
unsigned long v, void *p)
drivers/hwtracing/coresight/coresight-cpu-debug.c
381
unsigned long v, void *p)
drivers/hwtracing/coresight/coresight-cti-core.c
663
void *v)
drivers/hwtracing/coresight/coresight-etm4x-core.c
2138
void *v)
drivers/hwtracing/coresight/coresight-tmc.h
74
#define TMC_AXICTL_WR_BURST(v) (((v) & 0xf) << 8)
drivers/i2c/busses/i2c-at91.h
93
#define AT91_TWI_FILTR_THRES(v) ((v) << 8)
drivers/i2c/busses/i2c-au1550.c
44
static inline void WR(struct i2c_au1550_data *a, int r, unsigned long v)
drivers/i2c/busses/i2c-au1550.c
46
__raw_writel(v, a->psc_base + r);
drivers/i2c/busses/i2c-ibm_iic.c
243
u8 mask, v, sda;
drivers/i2c/busses/i2c-ibm_iic.c
270
v = i2c_8bit_addr_from_msg(p);
drivers/i2c/busses/i2c-ibm_iic.c
274
sda = (v & mask) ? DIRCNTL_SDAC : 0;
drivers/i2c/busses/i2c-ibm_iic.h
116
#define DIRCTNL_FREE(v) (((v) & 0x0f) == 0x0f)
drivers/i2c/busses/i2c-mxs.c
44
#define MXS_I2C_CTRL0_XFER_COUNT(v) ((v) & 0x0000FFFF)
drivers/i2c/busses/i2c-stm32f7.c
478
struct stm32f7_i2c_timings *v, *_v, *s;
drivers/i2c/busses/i2c-stm32f7.c
547
v = kmalloc_obj(*v);
drivers/i2c/busses/i2c-stm32f7.c
548
if (!v) {
drivers/i2c/busses/i2c-stm32f7.c
553
v->presc = p;
drivers/i2c/busses/i2c-stm32f7.c
554
v->scldel = l;
drivers/i2c/busses/i2c-stm32f7.c
555
v->sdadel = a;
drivers/i2c/busses/i2c-stm32f7.c
558
list_add_tail(&v->node,
drivers/i2c/busses/i2c-stm32f7.c
590
list_for_each_entry(v, &solutions, node) {
drivers/i2c/busses/i2c-stm32f7.c
591
u32 prescaler = (v->presc + 1) * i2cclk;
drivers/i2c/busses/i2c-stm32f7.c
617
v->scll = l;
drivers/i2c/busses/i2c-stm32f7.c
618
v->sclh = h;
drivers/i2c/busses/i2c-stm32f7.c
619
s = v;
drivers/i2c/busses/i2c-stm32f7.c
646
list_for_each_entry_safe(v, _v, &solutions, node) {
drivers/i2c/busses/i2c-stm32f7.c
647
list_del(&v->node);
drivers/i2c/busses/i2c-stm32f7.c
648
kfree(v);
drivers/i2c/busses/i2c-sun6i-p2wi.c
54
#define P2WI_CCR_SDA_OUT_DELAY(v) (((v) & 0x7) << 8)
drivers/i2c/busses/i2c-sun6i-p2wi.c
56
#define P2WI_CCR_CLK_DIV(v) ((v) & P2WI_CCR_MAX_CLK_DIV)
drivers/i2c/busses/i2c-sun6i-p2wi.c
59
#define P2WI_INTS_TRANS_ERR_ID(v) (((v) >> 8) & 0xff)
drivers/i2c/busses/i2c-sun6i-p2wi.c
66
#define P2WI_DLEN_DATA_LENGTH(v) ((v - 1) & 0x7)
drivers/i2c/busses/i2c-sun6i-p2wi.c
78
#define P2WI_PMCR_PMU_INIT_DATA(v) (((v) & 0xff) << 16)
drivers/i2c/busses/i2c-sun6i-p2wi.c
79
#define P2WI_PMCR_PMU_MODE_REG(v) (((v) & 0xff) << 8)
drivers/i2c/busses/i2c-sun6i-p2wi.c
80
#define P2WI_PMCR_PMU_DEV_ADDR(v) ((v) & 0xff)
drivers/i2c/busses/i2c-xgene-slimpro.c
80
#define SLIMPRO_MSG_TYPE(v) (((v) & 0xF0000000) >> 28)
drivers/i3c/master/mipi-i3c-hci/cmd_v1.c
100
#define CMD_M0_TID(v) FIELD_PREP(W0_MASK( 6, 3), v)
drivers/i3c/master/mipi-i3c-hci/cmd_v1.c
26
#define CMD_A0_DEV_COUNT(v) FIELD_PREP(W0_MASK(29, 26), v)
drivers/i3c/master/mipi-i3c-hci/cmd_v1.c
27
#define CMD_A0_DEV_INDEX(v) FIELD_PREP(W0_MASK(20, 16), v)
drivers/i3c/master/mipi-i3c-hci/cmd_v1.c
28
#define CMD_A0_CMD(v) FIELD_PREP(W0_MASK(14, 7), v)
drivers/i3c/master/mipi-i3c-hci/cmd_v1.c
29
#define CMD_A0_TID(v) FIELD_PREP(W0_MASK( 6, 3), v)
drivers/i3c/master/mipi-i3c-hci/cmd_v1.c
37
#define CMD_I1_DATA_BYTE_4(v) FIELD_PREP(W1_MASK(63, 56), v)
drivers/i3c/master/mipi-i3c-hci/cmd_v1.c
38
#define CMD_I1_DATA_BYTE_3(v) FIELD_PREP(W1_MASK(55, 48), v)
drivers/i3c/master/mipi-i3c-hci/cmd_v1.c
39
#define CMD_I1_DATA_BYTE_2(v) FIELD_PREP(W1_MASK(47, 40), v)
drivers/i3c/master/mipi-i3c-hci/cmd_v1.c
40
#define CMD_I1_DATA_BYTE_1(v) FIELD_PREP(W1_MASK(39, 32), v)
drivers/i3c/master/mipi-i3c-hci/cmd_v1.c
41
#define CMD_I1_DEF_BYTE(v) FIELD_PREP(W1_MASK(39, 32), v)
drivers/i3c/master/mipi-i3c-hci/cmd_v1.c
45
#define CMD_I0_MODE(v) FIELD_PREP(W0_MASK(28, 26), v)
drivers/i3c/master/mipi-i3c-hci/cmd_v1.c
46
#define CMD_I0_DTT(v) FIELD_PREP(W0_MASK(25, 23), v)
drivers/i3c/master/mipi-i3c-hci/cmd_v1.c
47
#define CMD_I0_DEV_INDEX(v) FIELD_PREP(W0_MASK(20, 16), v)
drivers/i3c/master/mipi-i3c-hci/cmd_v1.c
49
#define CMD_I0_CMD(v) FIELD_PREP(W0_MASK(14, 7), v)
drivers/i3c/master/mipi-i3c-hci/cmd_v1.c
50
#define CMD_I0_TID(v) FIELD_PREP(W0_MASK( 6, 3), v)
drivers/i3c/master/mipi-i3c-hci/cmd_v1.c
58
#define CMD_R1_DATA_LENGTH(v) FIELD_PREP(W1_MASK(63, 48), v)
drivers/i3c/master/mipi-i3c-hci/cmd_v1.c
59
#define CMD_R1_DEF_BYTE(v) FIELD_PREP(W1_MASK(39, 32), v)
drivers/i3c/master/mipi-i3c-hci/cmd_v1.c
63
#define CMD_R0_MODE(v) FIELD_PREP(W0_MASK(28, 26), v)
drivers/i3c/master/mipi-i3c-hci/cmd_v1.c
65
#define CMD_R0_DEV_INDEX(v) FIELD_PREP(W0_MASK(20, 16), v)
drivers/i3c/master/mipi-i3c-hci/cmd_v1.c
67
#define CMD_R0_CMD(v) FIELD_PREP(W0_MASK(14, 7), v)
drivers/i3c/master/mipi-i3c-hci/cmd_v1.c
68
#define CMD_R0_TID(v) FIELD_PREP(W0_MASK( 6, 3), v)
drivers/i3c/master/mipi-i3c-hci/cmd_v1.c
76
#define CMD_C1_DATA_LENGTH(v) FIELD_PREP(W1_MASK(63, 48), v)
drivers/i3c/master/mipi-i3c-hci/cmd_v1.c
77
#define CMD_C1_OFFSET(v) FIELD_PREP(W1_MASK(47, 32), v)
drivers/i3c/master/mipi-i3c-hci/cmd_v1.c
81
#define CMD_C0_MODE(v) FIELD_PREP(W0_MASK(28, 26), v)
drivers/i3c/master/mipi-i3c-hci/cmd_v1.c
84
#define CMD_C0_DATA_LENGTH_POSITION(v) FIELD_PREP(W0_MASK(23, 22), v)
drivers/i3c/master/mipi-i3c-hci/cmd_v1.c
85
#define CMD_C0_DEV_INDEX(v) FIELD_PREP(W0_MASK(20, 16), v)
drivers/i3c/master/mipi-i3c-hci/cmd_v1.c
87
#define CMD_C0_CMD(v) FIELD_PREP(W0_MASK(14, 7), v)
drivers/i3c/master/mipi-i3c-hci/cmd_v1.c
88
#define CMD_C0_TID(v) FIELD_PREP(W0_MASK( 6, 3), v)
drivers/i3c/master/mipi-i3c-hci/cmd_v2.c
25
#define CMD_U3_HDR_TSP_ML_CTRL(v) FIELD_PREP(W3_MASK(107, 104), v)
drivers/i3c/master/mipi-i3c-hci/cmd_v2.c
26
#define CMD_U3_IDB4(v) FIELD_PREP(W3_MASK(103, 96), v)
drivers/i3c/master/mipi-i3c-hci/cmd_v2.c
27
#define CMD_U3_HDR_CMD(v) FIELD_PREP(W3_MASK(103, 96), v)
drivers/i3c/master/mipi-i3c-hci/cmd_v2.c
28
#define CMD_U2_IDB3(v) FIELD_PREP(W2_MASK( 95, 88), v)
drivers/i3c/master/mipi-i3c-hci/cmd_v2.c
29
#define CMD_U2_HDR_BT(v) FIELD_PREP(W2_MASK( 95, 88), v)
drivers/i3c/master/mipi-i3c-hci/cmd_v2.c
30
#define CMD_U2_IDB2(v) FIELD_PREP(W2_MASK( 87, 80), v)
drivers/i3c/master/mipi-i3c-hci/cmd_v2.c
31
#define CMD_U2_BT_CMD2(v) FIELD_PREP(W2_MASK( 87, 80), v)
drivers/i3c/master/mipi-i3c-hci/cmd_v2.c
32
#define CMD_U2_IDB1(v) FIELD_PREP(W2_MASK( 79, 72), v)
drivers/i3c/master/mipi-i3c-hci/cmd_v2.c
33
#define CMD_U2_BT_CMD1(v) FIELD_PREP(W2_MASK( 79, 72), v)
drivers/i3c/master/mipi-i3c-hci/cmd_v2.c
34
#define CMD_U2_IDB0(v) FIELD_PREP(W2_MASK( 71, 64), v)
drivers/i3c/master/mipi-i3c-hci/cmd_v2.c
35
#define CMD_U2_BT_CMD0(v) FIELD_PREP(W2_MASK( 71, 64), v)
drivers/i3c/master/mipi-i3c-hci/cmd_v2.c
36
#define CMD_U1_ERR_HANDLING(v) FIELD_PREP(W1_MASK( 63, 62), v)
drivers/i3c/master/mipi-i3c-hci/cmd_v2.c
37
#define CMD_U1_ADD_FUNC(v) FIELD_PREP(W1_MASK( 61, 56), v)
drivers/i3c/master/mipi-i3c-hci/cmd_v2.c
39
#define CMD_U1_DATA_LENGTH(v) FIELD_PREP(W1_MASK( 53, 32), v)
drivers/i3c/master/mipi-i3c-hci/cmd_v2.c
43
#define CMD_U0_NACK_RCNT(v) FIELD_PREP(W0_MASK( 28, 27), v)
drivers/i3c/master/mipi-i3c-hci/cmd_v2.c
44
#define CMD_U0_IDB_COUNT(v) FIELD_PREP(W0_MASK( 26, 24), v)
drivers/i3c/master/mipi-i3c-hci/cmd_v2.c
45
#define CMD_U0_MODE_INDEX(v) FIELD_PREP(W0_MASK( 22, 18), v)
drivers/i3c/master/mipi-i3c-hci/cmd_v2.c
46
#define CMD_U0_XFER_RATE(v) FIELD_PREP(W0_MASK( 17, 15), v)
drivers/i3c/master/mipi-i3c-hci/cmd_v2.c
47
#define CMD_U0_DEV_ADDRESS(v) FIELD_PREP(W0_MASK( 14, 8), v)
drivers/i3c/master/mipi-i3c-hci/cmd_v2.c
49
#define CMD_U0_TID(v) FIELD_PREP(W0_MASK( 6, 3), v)
drivers/i3c/master/mipi-i3c-hci/cmd_v2.c
57
#define CMD_A1_DATA_LENGTH(v) FIELD_PREP(W1_MASK( 53, 32), v)
drivers/i3c/master/mipi-i3c-hci/cmd_v2.c
60
#define CMD_A0_XFER_RATE(v) FIELD_PREP(W0_MASK( 17, 15), v)
drivers/i3c/master/mipi-i3c-hci/cmd_v2.c
61
#define CMD_A0_ASSIGN_ADDRESS(v) FIELD_PREP(W0_MASK( 14, 8), v)
drivers/i3c/master/mipi-i3c-hci/cmd_v2.c
62
#define CMD_A0_TID(v) FIELD_PREP(W0_MASK( 6, 3), v)
drivers/i3c/master/mipi-i3c-hci/core.c
45
#define MASTER_DYNAMIC_ADDR(v) FIELD_PREP(GENMASK(22, 16), v)
drivers/i3c/master/mipi-i3c-hci/dat_v1.c
39
#define dat_w0_write(i, v) hci_dat_w0_write(hci, i, v)
drivers/i3c/master/mipi-i3c-hci/dat_v1.c
40
#define dat_w1_write(i, v) hci_dat_w1_write(hci, i, v)
drivers/i3c/master/mipi-i3c-hci/dat_v1.c
42
static inline void hci_dat_w0_write(struct i3c_hci *hci, int i, u32 v)
drivers/i3c/master/mipi-i3c-hci/dat_v1.c
44
hci->DAT[i].w0 = v;
drivers/i3c/master/mipi-i3c-hci/dat_v1.c
45
writel(v, hci->DAT_regs + i * 8);
drivers/i3c/master/mipi-i3c-hci/dat_v1.c
48
static inline void hci_dat_w1_write(struct i3c_hci *hci, int i, u32 v)
drivers/i3c/master/mipi-i3c-hci/dat_v1.c
50
hci->DAT[i].w1 = v;
drivers/i3c/master/mipi-i3c-hci/dat_v1.c
51
writel(v, hci->DAT_regs + i * 8 + 4);
drivers/i3c/master/mipi-i3c-hci/dma.c
41
#define rhs_reg_write(r, v) writel(v, hci->RHS_regs + (RHS_##r))
drivers/i3c/master/mipi-i3c-hci/dma.c
56
#define rh_reg_write(r, v) writel(v, rh->regs + (RH_##r))
drivers/i3c/master/mipi-i3c-hci/hci.h
28
#define reg_write(r, v) writel(v, hci->base_regs + (r))
drivers/i3c/master/mipi-i3c-hci/hci.h
29
#define reg_set(r, v) reg_write(r, reg_read(r) | (v))
drivers/i3c/master/mipi-i3c-hci/hci.h
30
#define reg_clear(r, v) reg_write(r, reg_read(r) & ~(v))
drivers/i3c/master/mipi-i3c-hci/pio.c
23
#define pio_reg_write(r, v) writel(v, hci->PIO_regs + (PIO_##r))
drivers/iio/accel/mma9551_core.c
295
__be16 v;
drivers/iio/accel/mma9551_core.c
298
reg, NULL, 0, (u8 *)&v, 2);
drivers/iio/accel/mma9551_core.c
302
*val = be16_to_cpu(v);
drivers/iio/accel/mma9551_core.c
328
__be16 v = cpu_to_be16(val);
drivers/iio/accel/mma9551_core.c
331
(u8 *)&v, 2, NULL, 0);
drivers/iio/accel/mma9551_core.c
356
__be16 v;
drivers/iio/accel/mma9551_core.c
359
reg, NULL, 0, (u8 *)&v, 2);
drivers/iio/accel/mma9551_core.c
363
*val = be16_to_cpu(v);
drivers/iio/adc/at91-sama5d2_adc.c
54
#define AT91_SAMA5D2_MR_TRGSEL(v) ((v) << 1)
drivers/iio/adc/at91-sama5d2_adc.c
76
#define AT91_SAMA5D2_MR_PRESCAL(v) ((v) << AT91_SAMA5D2_MR_PRESCAL_OFFSET)
drivers/iio/adc/at91-sama5d2_adc.c
81
#define AT91_SAMA5D2_MR_STARTUP(v) ((v) << 16)
drivers/iio/adc/at91-sama5d2_adc.c
88
#define AT91_SAMA5D2_MR_TRACKTIM(v) ((v) << 24)
drivers/iio/adc/at91-sama5d2_adc.c
92
#define AT91_SAMA5D2_MR_TRANSFER(v) ((v) << 28)
drivers/iio/adc/rzn1-adc.c
132
u32 v;
drivers/iio/adc/rzn1-adc.c
139
v, !(v & RZN1_ADC_CONTROL_ADC_BUSY),
drivers/iio/adc/rzn1-adc.c
182
u32 v;
drivers/iio/adc/rzn1-adc.c
201
v, !(v & RZN1_ADC_FORCE_VC(ch)),
drivers/iio/adc/stm32-adc-core.h
169
#define STM32H7_OVSR(v) FIELD_PREP(STM32H7_OVSR_MASK, v)
drivers/iio/adc/stm32-adc-core.h
171
#define STM32H7_OVSS(v) FIELD_PREP(STM32H7_OVSS_MASK, v)
drivers/iio/adc/stm32-adc-core.h
242
#define STM32MP13_OVSR(v) FIELD_PREP(STM32MP13_OVSR_MASK, v)
drivers/iio/adc/stm32-adc-core.h
244
#define STM32MP13_OVSS(v) FIELD_PREP(STM32MP13_OVSS_MASK, v)
drivers/iio/adc/stm32-dfsdm.h
115
#define DFSDM_CR1_DFEN(v) FIELD_PREP(DFSDM_CR1_DFEN_MASK, v)
drivers/iio/adc/stm32-dfsdm.h
117
#define DFSDM_CR1_JSWSTART(v) FIELD_PREP(DFSDM_CR1_JSWSTART_MASK, v)
drivers/iio/adc/stm32-dfsdm.h
119
#define DFSDM_CR1_JSYNC(v) FIELD_PREP(DFSDM_CR1_JSYNC_MASK, v)
drivers/iio/adc/stm32-dfsdm.h
121
#define DFSDM_CR1_JSCAN(v) FIELD_PREP(DFSDM_CR1_JSCAN_MASK, v)
drivers/iio/adc/stm32-dfsdm.h
123
#define DFSDM_CR1_JDMAEN(v) FIELD_PREP(DFSDM_CR1_JDMAEN_MASK, v)
drivers/iio/adc/stm32-dfsdm.h
125
#define DFSDM_CR1_JEXTSEL(v) FIELD_PREP(DFSDM_CR1_JEXTSEL_MASK, v)
drivers/iio/adc/stm32-dfsdm.h
127
#define DFSDM_CR1_JEXTEN(v) FIELD_PREP(DFSDM_CR1_JEXTEN_MASK, v)
drivers/iio/adc/stm32-dfsdm.h
129
#define DFSDM_CR1_RSWSTART(v) FIELD_PREP(DFSDM_CR1_RSWSTART_MASK, v)
drivers/iio/adc/stm32-dfsdm.h
131
#define DFSDM_CR1_RCONT(v) FIELD_PREP(DFSDM_CR1_RCONT_MASK, v)
drivers/iio/adc/stm32-dfsdm.h
133
#define DFSDM_CR1_RSYNC(v) FIELD_PREP(DFSDM_CR1_RSYNC_MASK, v)
drivers/iio/adc/stm32-dfsdm.h
135
#define DFSDM_CR1_RDMAEN(v) FIELD_PREP(DFSDM_CR1_RDMAEN_MASK, v)
drivers/iio/adc/stm32-dfsdm.h
137
#define DFSDM_CR1_RCH(v) FIELD_PREP(DFSDM_CR1_RCH_MASK, v)
drivers/iio/adc/stm32-dfsdm.h
139
#define DFSDM_CR1_FAST(v) FIELD_PREP(DFSDM_CR1_FAST_MASK, v)
drivers/iio/adc/stm32-dfsdm.h
141
#define DFSDM_CR1_AWFSEL(v) FIELD_PREP(DFSDM_CR1_AWFSEL_MASK, v)
drivers/iio/adc/stm32-dfsdm.h
145
#define DFSDM_CR2_IE(v) FIELD_PREP(DFSDM_CR2_IE_MASK, v)
drivers/iio/adc/stm32-dfsdm.h
147
#define DFSDM_CR2_JEOCIE(v) FIELD_PREP(DFSDM_CR2_JEOCIE_MASK, v)
drivers/iio/adc/stm32-dfsdm.h
149
#define DFSDM_CR2_REOCIE(v) FIELD_PREP(DFSDM_CR2_REOCIE_MASK, v)
drivers/iio/adc/stm32-dfsdm.h
151
#define DFSDM_CR2_JOVRIE(v) FIELD_PREP(DFSDM_CR2_JOVRIE_MASK, v)
drivers/iio/adc/stm32-dfsdm.h
153
#define DFSDM_CR2_ROVRIE(v) FIELD_PREP(DFSDM_CR2_ROVRIE_MASK, v)
drivers/iio/adc/stm32-dfsdm.h
155
#define DFSDM_CR2_AWDIE(v) FIELD_PREP(DFSDM_CR2_AWDIE_MASK, v)
drivers/iio/adc/stm32-dfsdm.h
157
#define DFSDM_CR2_SCDIE(v) FIELD_PREP(DFSDM_CR2_SCDIE_MASK, v)
drivers/iio/adc/stm32-dfsdm.h
159
#define DFSDM_CR2_CKABIE(v) FIELD_PREP(DFSDM_CR2_CKABIE_MASK, v)
drivers/iio/adc/stm32-dfsdm.h
161
#define DFSDM_CR2_EXCH(v) FIELD_PREP(DFSDM_CR2_EXCH_MASK, v)
drivers/iio/adc/stm32-dfsdm.h
163
#define DFSDM_CR2_AWDCH(v) FIELD_PREP(DFSDM_CR2_AWDCH_MASK, v)
drivers/iio/adc/stm32-dfsdm.h
167
#define DFSDM_ISR_JEOCF(v) FIELD_PREP(DFSDM_ISR_JEOCF_MASK, v)
drivers/iio/adc/stm32-dfsdm.h
169
#define DFSDM_ISR_REOCF(v) FIELD_PREP(DFSDM_ISR_REOCF_MASK, v)
drivers/iio/adc/stm32-dfsdm.h
171
#define DFSDM_ISR_JOVRF(v) FIELD_PREP(DFSDM_ISR_JOVRF_MASK, v)
drivers/iio/adc/stm32-dfsdm.h
173
#define DFSDM_ISR_ROVRF(v) FIELD_PREP(DFSDM_ISR_ROVRF_MASK, v)
drivers/iio/adc/stm32-dfsdm.h
175
#define DFSDM_ISR_AWDF(v) FIELD_PREP(DFSDM_ISR_AWDF_MASK, v)
drivers/iio/adc/stm32-dfsdm.h
177
#define DFSDM_ISR_JCIP(v) FIELD_PREP(DFSDM_ISR_JCIP_MASK, v)
drivers/iio/adc/stm32-dfsdm.h
179
#define DFSDM_ISR_RCIP(v) FIELD_PREP(DFSDM_ISR_RCIP, v)
drivers/iio/adc/stm32-dfsdm.h
181
#define DFSDM_ISR_CKABF(v) FIELD_PREP(DFSDM_ISR_CKABF_MASK, v)
drivers/iio/adc/stm32-dfsdm.h
183
#define DFSDM_ISR_SCDF(v) FIELD_PREP(DFSDM_ISR_SCDF_MASK, v)
drivers/iio/adc/stm32-dfsdm.h
187
#define DFSDM_ICR_CLRJOVRF(v) FIELD_PREP(DFSDM_ICR_CLRJOVRF_MASK, v)
drivers/iio/adc/stm32-dfsdm.h
189
#define DFSDM_ICR_CLRROVRF(v) FIELD_PREP(DFSDM_ICR_CLRROVRF_MASK, v)
drivers/iio/adc/stm32-dfsdm.h
191
#define DFSDM_ICR_CLRCKABF(v) FIELD_PREP(DFSDM_ICR_CLRCKABF_MASK, v)
drivers/iio/adc/stm32-dfsdm.h
193
#define DFSDM_ICR_CLRCKABF_CH(v, y) \
drivers/iio/adc/stm32-dfsdm.h
194
(((v) << (16 + (y))) & DFSDM_ICR_CLRCKABF_CH_MASK(y))
drivers/iio/adc/stm32-dfsdm.h
196
#define DFSDM_ICR_CLRSCDF(v) FIELD_PREP(DFSDM_ICR_CLRSCDF_MASK, v)
drivers/iio/adc/stm32-dfsdm.h
198
#define DFSDM_ICR_CLRSCDF_CH(v, y) \
drivers/iio/adc/stm32-dfsdm.h
199
(((v) << (24 + (y))) & DFSDM_ICR_CLRSCDF_MASK(y))
drivers/iio/adc/stm32-dfsdm.h
203
#define DFSDM_FCR_IOSR(v) FIELD_PREP(DFSDM_FCR_IOSR_MASK, v)
drivers/iio/adc/stm32-dfsdm.h
205
#define DFSDM_FCR_FOSR(v) FIELD_PREP(DFSDM_FCR_FOSR_MASK, v)
drivers/iio/adc/stm32-dfsdm.h
207
#define DFSDM_FCR_FORD(v) FIELD_PREP(DFSDM_FCR_FORD_MASK, v)
drivers/iio/adc/stm32-dfsdm.h
216
#define DFSDM_AWLTR_BKAWL(v) FIELD_PREP(DFSDM_AWLTR_BKAWL_MASK, v)
drivers/iio/adc/stm32-dfsdm.h
218
#define DFSDM_AWLTR_AWLT(v) FIELD_PREP(DFSDM_AWLTR_AWLT_MASK, v)
drivers/iio/adc/stm32-dfsdm.h
222
#define DFSDM_AWHTR_BKAWH(v) FIELD_PREP(DFSDM_AWHTR_BKAWH_MASK, v)
drivers/iio/adc/stm32-dfsdm.h
224
#define DFSDM_AWHTR_AWHT(v) FIELD_PREP(DFSDM_AWHTR_AWHT_MASK, v)
drivers/iio/adc/stm32-dfsdm.h
228
#define DFSDM_AWSR_AWLTF(v) FIELD_PREP(DFSDM_AWSR_AWLTF_MASK, v)
drivers/iio/adc/stm32-dfsdm.h
230
#define DFSDM_AWSR_AWHTF(v) FIELD_PREP(DFSDM_AWSR_AWHTF_MASK, v)
drivers/iio/adc/stm32-dfsdm.h
234
#define DFSDM_AWCFR_AWLTF(v) FIELD_PREP(DFSDM_AWCFR_AWLTF_MASK, v)
drivers/iio/adc/stm32-dfsdm.h
236
#define DFSDM_AWCFR_AWHTF(v) FIELD_PREP(DFSDM_AWCFR_AWHTF_MASK, v)
drivers/iio/adc/stm32-dfsdm.h
52
#define DFSDM_CHCFGR1_SITP(v) FIELD_PREP(DFSDM_CHCFGR1_SITP_MASK, v)
drivers/iio/adc/stm32-dfsdm.h
54
#define DFSDM_CHCFGR1_SPICKSEL(v) FIELD_PREP(DFSDM_CHCFGR1_SPICKSEL_MASK, v)
drivers/iio/adc/stm32-dfsdm.h
56
#define DFSDM_CHCFGR1_SCDEN(v) FIELD_PREP(DFSDM_CHCFGR1_SCDEN_MASK, v)
drivers/iio/adc/stm32-dfsdm.h
58
#define DFSDM_CHCFGR1_CKABEN(v) FIELD_PREP(DFSDM_CHCFGR1_CKABEN_MASK, v)
drivers/iio/adc/stm32-dfsdm.h
60
#define DFSDM_CHCFGR1_CHEN(v) FIELD_PREP(DFSDM_CHCFGR1_CHEN_MASK, v)
drivers/iio/adc/stm32-dfsdm.h
62
#define DFSDM_CHCFGR1_CHINSEL(v) FIELD_PREP(DFSDM_CHCFGR1_CHINSEL_MASK, v)
drivers/iio/adc/stm32-dfsdm.h
64
#define DFSDM_CHCFGR1_DATMPX(v) FIELD_PREP(DFSDM_CHCFGR1_DATMPX_MASK, v)
drivers/iio/adc/stm32-dfsdm.h
66
#define DFSDM_CHCFGR1_DATPACK(v) FIELD_PREP(DFSDM_CHCFGR1_DATPACK_MASK, v)
drivers/iio/adc/stm32-dfsdm.h
68
#define DFSDM_CHCFGR1_CKOUTDIV(v) FIELD_PREP(DFSDM_CHCFGR1_CKOUTDIV_MASK, v)
drivers/iio/adc/stm32-dfsdm.h
70
#define DFSDM_CHCFGR1_CKOUTSRC(v) FIELD_PREP(DFSDM_CHCFGR1_CKOUTSRC_MASK, v)
drivers/iio/adc/stm32-dfsdm.h
72
#define DFSDM_CHCFGR1_DFSDMEN(v) FIELD_PREP(DFSDM_CHCFGR1_DFSDMEN_MASK, v)
drivers/iio/adc/stm32-dfsdm.h
76
#define DFSDM_CHCFGR2_DTRBS(v) FIELD_PREP(DFSDM_CHCFGR2_DTRBS_MASK, v)
drivers/iio/adc/stm32-dfsdm.h
78
#define DFSDM_CHCFGR2_OFFSET(v) FIELD_PREP(DFSDM_CHCFGR2_OFFSET_MASK, v)
drivers/iio/adc/stm32-dfsdm.h
82
#define DFSDM_AWSCDR_SCDT(v) FIELD_PREP(DFSDM_AWSCDR_SCDT_MASK, v)
drivers/iio/adc/stm32-dfsdm.h
84
#define DFSDM_AWSCDR_BKSCD(v) FIELD_PREP(DFSDM_AWSCDR_BKSCD_MASK, v)
drivers/iio/adc/stm32-dfsdm.h
86
#define DFSDM_AWSCDR_AWFOSR(v) FIELD_PREP(DFSDM_AWSCDR_AWFOSR_MASK, v)
drivers/iio/adc/stm32-dfsdm.h
88
#define DFSDM_AWSCDR_AWFORD(v) FIELD_PREP(DFSDM_AWSCDR_AWFORD_MASK, v)
drivers/iio/addac/ad74115.c
1118
unsigned int v = 2 * ad74115_adc_gain_tbl[range][0];
drivers/iio/addac/ad74115.c
1121
v *= AD74115_ADC_CODE_HALF;
drivers/iio/addac/ad74115.c
1123
v *= AD74115_ADC_CODE_MAX;
drivers/iio/addac/ad74115.c
1125
*val += v;
drivers/iio/potentiometer/x9250.c
79
u8 v;
drivers/iio/potentiometer/x9250.c
83
ret = x9250_read8(x9250, X9250_CMD_RD_WCR(ch), &v);
drivers/iio/potentiometer/x9250.c
86
*val = v;
drivers/iio/pressure/zpa2326.c
1009
u8 v[3];
drivers/iio/pressure/zpa2326.c
1015
err = regmap_bulk_read(regs, ZPA2326_PRESS_OUT_XL_REG, v, sizeof(v));
drivers/iio/pressure/zpa2326.c
1022
*value = get_unaligned_le24(&v[0]);
drivers/infiniband/core/nldev.c
2278
u64 v;
drivers/infiniband/core/nldev.c
2334
v = stats->value[i] +
drivers/infiniband/core/nldev.c
2337
stats->descs[i].name, v)) {
drivers/infiniband/core/sysfs.c
781
u64 v = rdma_counter_get_hwstat_value(dev, port_num, index);
drivers/infiniband/core/sysfs.c
783
return sysfs_emit(buf, "%llu\n", stats->value[index] + v);
drivers/infiniband/hw/bng_re/bng_fw.h
25
(!!((hdr)->v & CREQ_BASE_V) == \
drivers/infiniband/hw/bng_re/bng_roce_hsi.h
1136
u8 v;
drivers/infiniband/hw/bng_re/bng_roce_hsi.h
1170
u8 v;
drivers/infiniband/hw/bng_re/bng_roce_hsi.h
1207
u8 v;
drivers/infiniband/hw/bng_re/bng_roce_hsi.h
1309
u8 v;
drivers/infiniband/hw/bng_re/bng_roce_hsi.h
1343
u8 v;
drivers/infiniband/hw/bng_re/bng_roce_hsi.h
1415
u8 v;
drivers/infiniband/hw/bng_re/bng_roce_hsi.h
1463
u8 v;
drivers/infiniband/hw/bng_re/bng_roce_hsi.h
1508
u8 v;
drivers/infiniband/hw/bng_re/bng_roce_hsi.h
153
u8 v;
drivers/infiniband/hw/bng_re/bng_roce_hsi.h
1591
u8 v;
drivers/infiniband/hw/bng_re/bng_roce_hsi.h
1626
u8 v;
drivers/infiniband/hw/bng_re/bng_roce_hsi.h
1686
u8 v;
drivers/infiniband/hw/bng_re/bng_roce_hsi.h
1720
u8 v;
drivers/infiniband/hw/bng_re/bng_roce_hsi.h
1775
u8 v;
drivers/infiniband/hw/bng_re/bng_roce_hsi.h
1808
u8 v;
drivers/infiniband/hw/bng_re/bng_roce_hsi.h
1934
u8 v;
drivers/infiniband/hw/bng_re/bng_roce_hsi.h
1967
u8 v;
drivers/infiniband/hw/bng_re/bng_roce_hsi.h
2018
u8 v;
drivers/infiniband/hw/bng_re/bng_roce_hsi.h
2051
u8 v;
drivers/infiniband/hw/bng_re/bng_roce_hsi.h
2091
u8 v;
drivers/infiniband/hw/bng_re/bng_roce_hsi.h
219
u8 v;
drivers/infiniband/hw/bng_re/bng_roce_hsi.h
2191
u8 v;
drivers/infiniband/hw/bng_re/bng_roce_hsi.h
2270
u8 v;
drivers/infiniband/hw/bng_re/bng_roce_hsi.h
2461
u8 v;
drivers/infiniband/hw/bng_re/bng_roce_hsi.h
2501
u8 v;
drivers/infiniband/hw/bng_re/bng_roce_hsi.h
2541
u8 v;
drivers/infiniband/hw/bng_re/bng_roce_hsi.h
2572
u8 v;
drivers/infiniband/hw/bng_re/bng_roce_hsi.h
3316
u8 v;
drivers/infiniband/hw/bng_re/bng_roce_hsi.h
3371
u8 v;
drivers/infiniband/hw/bng_re/bng_roce_hsi.h
3407
u8 v;
drivers/infiniband/hw/bng_re/bng_roce_hsi.h
3441
u8 v;
drivers/infiniband/hw/bng_re/bng_roce_hsi.h
3475
u8 v;
drivers/infiniband/hw/bng_re/bng_roce_hsi.h
3556
u8 v;
drivers/infiniband/hw/bng_re/bng_roce_hsi.h
3597
u8 v;
drivers/infiniband/hw/bng_re/bng_roce_hsi.h
3618
u8 v;
drivers/infiniband/hw/bng_re/bng_roce_hsi.h
3657
u8 v;
drivers/infiniband/hw/bng_re/bng_roce_hsi.h
3755
u8 v;
drivers/infiniband/hw/bng_re/bng_roce_hsi.h
3815
u8 v;
drivers/infiniband/hw/bng_re/bng_roce_hsi.h
404
u8 v;
drivers/infiniband/hw/bng_re/bng_roce_hsi.h
436
u8 v;
drivers/infiniband/hw/bng_re/bng_roce_hsi.h
585
u8 v;
drivers/infiniband/hw/bng_re/bng_roce_hsi.h
620
u8 v;
drivers/infiniband/hw/bng_re/bng_roce_hsi.h
6321
__le32 v;
drivers/infiniband/hw/bng_re/bng_roce_hsi.h
6340
__le32 v;
drivers/infiniband/hw/bng_re/bng_roce_hsi.h
6361
__le32 v;
drivers/infiniband/hw/bng_re/bng_roce_hsi.h
6379
__le32 v;
drivers/infiniband/hw/bng_re/bng_roce_hsi.h
791
u8 v;
drivers/infiniband/hw/bng_re/bng_roce_hsi.h
833
u8 v;
drivers/infiniband/hw/bng_re/bng_roce_hsi.h
960
u8 v;
drivers/infiniband/hw/bnxt_re/qplib_rcfw.h
147
(!!((hdr)->v & CREQ_BASE_V) == \
drivers/infiniband/hw/bnxt_re/roce_hsi.h
1044
u8 v;
drivers/infiniband/hw/bnxt_re/roce_hsi.h
1077
u8 v;
drivers/infiniband/hw/bnxt_re/roce_hsi.h
1114
u8 v;
drivers/infiniband/hw/bnxt_re/roce_hsi.h
1205
u8 v;
drivers/infiniband/hw/bnxt_re/roce_hsi.h
1238
u8 v;
drivers/infiniband/hw/bnxt_re/roce_hsi.h
1295
u8 v;
drivers/infiniband/hw/bnxt_re/roce_hsi.h
1343
u8 v;
drivers/infiniband/hw/bnxt_re/roce_hsi.h
1387
u8 v;
drivers/infiniband/hw/bnxt_re/roce_hsi.h
1468
u8 v;
drivers/infiniband/hw/bnxt_re/roce_hsi.h
1501
u8 v;
drivers/infiniband/hw/bnxt_re/roce_hsi.h
1560
u8 v;
drivers/infiniband/hw/bnxt_re/roce_hsi.h
1593
u8 v;
drivers/infiniband/hw/bnxt_re/roce_hsi.h
1648
u8 v;
drivers/infiniband/hw/bnxt_re/roce_hsi.h
166
u8 v;
drivers/infiniband/hw/bnxt_re/roce_hsi.h
1681
u8 v;
drivers/infiniband/hw/bnxt_re/roce_hsi.h
1807
u8 v;
drivers/infiniband/hw/bnxt_re/roce_hsi.h
1840
u8 v;
drivers/infiniband/hw/bnxt_re/roce_hsi.h
1891
u8 v;
drivers/infiniband/hw/bnxt_re/roce_hsi.h
1924
u8 v;
drivers/infiniband/hw/bnxt_re/roce_hsi.h
1964
u8 v;
drivers/infiniband/hw/bnxt_re/roce_hsi.h
198
u8 v;
drivers/infiniband/hw/bnxt_re/roce_hsi.h
2066
u8 v;
drivers/infiniband/hw/bnxt_re/roce_hsi.h
2144
u8 v;
drivers/infiniband/hw/bnxt_re/roce_hsi.h
2176
u8 v;
drivers/infiniband/hw/bnxt_re/roce_hsi.h
2307
u8 v;
drivers/infiniband/hw/bnxt_re/roce_hsi.h
2347
u8 v;
drivers/infiniband/hw/bnxt_re/roce_hsi.h
2387
u8 v;
drivers/infiniband/hw/bnxt_re/roce_hsi.h
2418
u8 v;
drivers/infiniband/hw/bnxt_re/roce_hsi.h
2914
u8 v;
drivers/infiniband/hw/bnxt_re/roce_hsi.h
2970
u8 v;
drivers/infiniband/hw/bnxt_re/roce_hsi.h
2987
u8 v;
drivers/infiniband/hw/bnxt_re/roce_hsi.h
3026
u8 v;
drivers/infiniband/hw/bnxt_re/roce_hsi.h
3110
u8 v;
drivers/infiniband/hw/bnxt_re/roce_hsi.h
3170
u8 v;
drivers/infiniband/hw/bnxt_re/roce_hsi.h
374
u8 v;
drivers/infiniband/hw/bnxt_re/roce_hsi.h
407
u8 v;
drivers/infiniband/hw/bnxt_re/roce_hsi.h
4619
__le32 v;
drivers/infiniband/hw/bnxt_re/roce_hsi.h
4638
__le32 v;
drivers/infiniband/hw/bnxt_re/roce_hsi.h
4659
__le32 v;
drivers/infiniband/hw/bnxt_re/roce_hsi.h
517
u8 v;
drivers/infiniband/hw/bnxt_re/roce_hsi.h
551
u8 v;
drivers/infiniband/hw/bnxt_re/roce_hsi.h
710
u8 v;
drivers/infiniband/hw/bnxt_re/roce_hsi.h
750
u8 v;
drivers/infiniband/hw/bnxt_re/roce_hsi.h
878
u8 v;
drivers/infiniband/hw/cxgb4/cm.c
3840
u32 v;
drivers/infiniband/hw/cxgb4/cm.c
3845
v = (t >> shift) & mask;
drivers/infiniband/hw/cxgb4/cm.c
3846
return v;
drivers/infiniband/hw/cxgb4/device.c
122
static int wr_log_show(struct seq_file *seq, void *v)
drivers/infiniband/hw/cxgb4/device.c
469
static int stats_show(struct seq_file *seq, void *v)
drivers/infiniband/hw/hfi1/debugfs.c
100
static int _tx_opcode_stats_seq_show(struct seq_file *s, void *v)
drivers/infiniband/hw/hfi1/debugfs.c
102
loff_t *spos = v;
drivers/infiniband/hw/hfi1/debugfs.c
1123
static void *_sdma_cpu_list_seq_next(struct seq_file *s, void *v, loff_t *pos)
drivers/infiniband/hw/hfi1/debugfs.c
1132
static void _sdma_cpu_list_seq_stop(struct seq_file *s, void *v)
drivers/infiniband/hw/hfi1/debugfs.c
1137
static int _sdma_cpu_list_seq_show(struct seq_file *s, void *v)
drivers/infiniband/hw/hfi1/debugfs.c
1141
loff_t *spos = v;
drivers/infiniband/hw/hfi1/debugfs.c
1247
void *v,
drivers/infiniband/hw/hfi1/debugfs.c
1256
static void _driver_stats_names_seq_stop(struct seq_file *s, void *v)
drivers/infiniband/hw/hfi1/debugfs.c
1260
static int _driver_stats_names_seq_show(struct seq_file *s, void *v)
drivers/infiniband/hw/hfi1/debugfs.c
1262
loff_t *spos = v;
drivers/infiniband/hw/hfi1/debugfs.c
1279
static void *_driver_stats_seq_next(struct seq_file *s, void *v, loff_t *pos)
drivers/infiniband/hw/hfi1/debugfs.c
1287
static void _driver_stats_seq_stop(struct seq_file *s, void *v)
drivers/infiniband/hw/hfi1/debugfs.c
1305
static int _driver_stats_seq_show(struct seq_file *s, void *v)
drivers/infiniband/hw/hfi1/debugfs.c
1307
loff_t *spos = v;
drivers/infiniband/hw/hfi1/debugfs.c
134
static void *_ctx_stats_seq_next(struct seq_file *s, void *v, loff_t *pos)
drivers/infiniband/hw/hfi1/debugfs.c
139
if (v == SEQ_START_TOKEN)
drivers/infiniband/hw/hfi1/debugfs.c
148
static void _ctx_stats_seq_stop(struct seq_file *s, void *v)
drivers/infiniband/hw/hfi1/debugfs.c
153
static int _ctx_stats_seq_show(struct seq_file *s, void *v)
drivers/infiniband/hw/hfi1/debugfs.c
162
if (v == SEQ_START_TOKEN) {
drivers/infiniband/hw/hfi1/debugfs.c
167
spos = v;
drivers/infiniband/hw/hfi1/debugfs.c
264
static void *_sdes_seq_next(struct seq_file *s, void *v, loff_t *pos)
drivers/infiniband/hw/hfi1/debugfs.c
275
static void _sdes_seq_stop(struct seq_file *s, void *v)
drivers/infiniband/hw/hfi1/debugfs.c
279
static int _sdes_seq_show(struct seq_file *s, void *v)
drivers/infiniband/hw/hfi1/debugfs.c
283
loff_t *spos = v;
drivers/infiniband/hw/hfi1/debugfs.c
306
static void *_rcds_seq_next(struct seq_file *s, void *v, loff_t *pos)
drivers/infiniband/hw/hfi1/debugfs.c
317
static void _rcds_seq_stop(struct seq_file *s, void *v)
drivers/infiniband/hw/hfi1/debugfs.c
321
static int _rcds_seq_show(struct seq_file *s, void *v)
drivers/infiniband/hw/hfi1/debugfs.c
326
loff_t *spos = v;
drivers/infiniband/hw/hfi1/debugfs.c
352
static void *_pios_seq_next(struct seq_file *s, void *v, loff_t *pos)
drivers/infiniband/hw/hfi1/debugfs.c
363
static void _pios_seq_stop(struct seq_file *s, void *v)
drivers/infiniband/hw/hfi1/debugfs.c
367
static int _pios_seq_show(struct seq_file *s, void *v)
drivers/infiniband/hw/hfi1/debugfs.c
37
static void *_opcode_stats_seq_next(struct seq_file *s, void *v, loff_t *pos)
drivers/infiniband/hw/hfi1/debugfs.c
372
loff_t *spos = v;
drivers/infiniband/hw/hfi1/debugfs.c
47
static void _opcode_stats_seq_stop(struct seq_file *s, void *v)
drivers/infiniband/hw/hfi1/debugfs.c
62
static int _opcode_stats_seq_show(struct seq_file *s, void *v)
drivers/infiniband/hw/hfi1/debugfs.c
64
loff_t *spos = v;
drivers/infiniband/hw/hfi1/debugfs.c
91
static void *_tx_opcode_stats_seq_next(struct seq_file *s, void *v, loff_t *pos)
drivers/infiniband/hw/hfi1/debugfs.c
93
return _opcode_stats_seq_next(s, v, pos);
drivers/infiniband/hw/hfi1/debugfs.c
96
static void _tx_opcode_stats_seq_stop(struct seq_file *s, void *v)
drivers/infiniband/hw/hfi1/fault.c
29
static void *_fault_stats_seq_next(struct seq_file *s, void *v, loff_t *pos)
drivers/infiniband/hw/hfi1/fault.c
39
static void _fault_stats_seq_stop(struct seq_file *s, void *v)
drivers/infiniband/hw/hfi1/fault.c
43
static int _fault_stats_seq_show(struct seq_file *s, void *v)
drivers/infiniband/hw/hfi1/fault.c
45
loff_t *spos = v;
drivers/infiniband/hw/hfi1/qp.c
879
static void hfi1_qp_iter_cb(struct rvt_qp *qp, u64 v)
drivers/infiniband/hw/hfi1/qp.c
886
u8 sl = (u8)v;
drivers/infiniband/hw/mthca/mthca_reset.c
163
u32 v;
drivers/infiniband/hw/mthca/mthca_reset.c
167
if (pci_read_config_dword(bridge ? bridge : mdev->pdev, 0, &v)) {
drivers/infiniband/hw/mthca/mthca_reset.c
174
if (v != 0xffffffff)
drivers/infiniband/sw/rdmavt/mr.c
412
static void rvt_dereg_clean_qp_cb(struct rvt_qp *qp, u64 v)
drivers/infiniband/sw/rdmavt/mr.c
414
struct rvt_mregion *mr = (struct rvt_mregion *)v;
drivers/infiniband/sw/rdmavt/qp.c
2648
u64 v,
drivers/infiniband/sw/rdmavt/qp.c
2649
void (*cb)(struct rvt_qp *qp, u64 v))
drivers/infiniband/sw/rdmavt/qp.c
2660
i->v = v;
drivers/infiniband/sw/rdmavt/qp.c
2747
u64 v,
drivers/infiniband/sw/rdmavt/qp.c
2748
void (*cb)(struct rvt_qp *qp, u64 v))
drivers/infiniband/sw/rdmavt/qp.c
2754
.v = v,
drivers/infiniband/sw/rdmavt/qp.c
2764
i.cb(i.qp, i.v);
drivers/infiniband/sw/rdmavt/qp.c
423
static void rvt_free_qp_cb(struct rvt_qp *qp, u64 v)
drivers/infiniband/sw/rdmavt/qp.c
425
unsigned int *qp_inuse = (unsigned int *)v;
drivers/infiniband/sw/rdmavt/trace_mr.h
21
TP_PROTO(struct rvt_mregion *mr, u16 m, u16 n, void *v, size_t len),
drivers/infiniband/sw/rdmavt/trace_mr.h
22
TP_ARGS(mr, m, n, v, len),
drivers/infiniband/sw/rdmavt/trace_mr.h
38
__entry->vaddr = v;
drivers/infiniband/sw/rdmavt/trace_mr.h
39
__entry->page = virt_to_page(v);
drivers/infiniband/sw/rdmavt/trace_mr.h
67
TP_PROTO(struct rvt_mregion *mr, u16 m, u16 n, void *v, size_t len),
drivers/infiniband/sw/rdmavt/trace_mr.h
68
TP_ARGS(mr, m, n, v, len));
drivers/infiniband/sw/rdmavt/trace_mr.h
72
TP_PROTO(struct rvt_mregion *mr, u16 m, u16 n, void *v, size_t len),
drivers/infiniband/sw/rdmavt/trace_mr.h
73
TP_ARGS(mr, m, n, v, len));
drivers/infiniband/sw/rdmavt/trace_mr.h
77
TP_PROTO(struct rvt_mregion *mr, u16 m, u16 n, void *v, size_t len),
drivers/infiniband/sw/rdmavt/trace_mr.h
78
TP_ARGS(mr, m, n, v, len));
drivers/infiniband/ulp/rtrs/rtrs-srv.c
1374
int v;
drivers/infiniband/ulp/rtrs/rtrs-srv.c
1376
v = cpumask_next(srv_path->cur_cq_vector, &cq_affinity_mask);
drivers/infiniband/ulp/rtrs/rtrs-srv.c
1377
if (v >= nr_cpu_ids || v >= ib_dev->num_comp_vectors)
drivers/infiniband/ulp/rtrs/rtrs-srv.c
1378
v = cpumask_first(&cq_affinity_mask);
drivers/infiniband/ulp/rtrs/rtrs-srv.c
1379
return v;
drivers/input/evdev.c
1037
unsigned int i, t, u, v;
drivers/input/evdev.c
1066
if (get_user(v, ip + 1))
drivers/input/evdev.c
1070
input_inject_event(&evdev->handle, EV_REP, REP_PERIOD, v);
drivers/input/evdev.c
248
const struct input_value *v;
drivers/input/evdev.c
263
for (v = vals; v != vals + count; v++) {
drivers/input/evdev.c
264
if (__evdev_is_filtered(client, v->type, v->code))
drivers/input/evdev.c
267
if (v->type == EV_SYN && v->code == SYN_REPORT) {
drivers/input/evdev.c
275
event.type = v->type;
drivers/input/evdev.c
276
event.code = v->code;
drivers/input/evdev.c
277
event.value = v->value;
drivers/input/gameport/ns558.c
48
unsigned char c, u, v;
drivers/input/gameport/ns558.c
66
if (~(u = v = inb(io)) & 3) {
drivers/input/gameport/ns558.c
75
for (i = 0; i < 1000; i++) v &= inb(io);
drivers/input/gameport/ns558.c
77
if (u == v) {
drivers/input/input.c
1050
static void *input_devices_seq_next(struct seq_file *seq, void *v, loff_t *pos)
drivers/input/input.c
1052
return seq_list_next(v, &input_dev_list, pos);
drivers/input/input.c
1055
static void input_seq_stop(struct seq_file *seq, void *v)
drivers/input/input.c
1089
static int input_devices_seq_show(struct seq_file *seq, void *v)
drivers/input/input.c
1091
struct input_dev *dev = container_of(v, struct input_dev, node);
drivers/input/input.c
115
struct input_value *v;
drivers/input/input.c
1172
static void *input_handlers_seq_next(struct seq_file *seq, void *v, loff_t *pos)
drivers/input/input.c
1177
return seq_list_next(v, &input_handler_list, pos);
drivers/input/input.c
1180
static int input_handlers_seq_show(struct seq_file *seq, void *v)
drivers/input/input.c
1182
struct input_handler *handler = container_of(v, struct input_handler, node);
drivers/input/input.c
138
for (v = vals; v != vals + count; v++) {
drivers/input/input.c
139
if (v->type == EV_KEY && v->value != 2) {
drivers/input/input.c
140
if (v->value)
drivers/input/input.c
141
input_start_autorepeat(dev, v->code);
drivers/input/input.c
2538
struct input_value *v;
drivers/input/input.c
2540
for (v = vals; v != vals + count; v++)
drivers/input/input.c
2541
handler->event(handle, v->type, v->code, v->value);
drivers/input/input.c
2557
struct input_value *v;
drivers/input/input.c
2559
for (v = vals; v != vals + count; v++) {
drivers/input/input.c
2560
if (handler->filter(handle, v->type, v->code, v->value))
drivers/input/input.c
2562
if (end != v)
drivers/input/input.c
2563
*end = *v;
drivers/input/input.c
325
struct input_value *v;
drivers/input/input.c
328
v = &dev->vals[dev->num_vals++];
drivers/input/input.c
329
v->type = EV_ABS;
drivers/input/input.c
330
v->code = ABS_MT_SLOT;
drivers/input/input.c
331
v->value = dev->mt->slot;
drivers/input/input.c
334
v = &dev->vals[dev->num_vals++];
drivers/input/input.c
335
v->type = type;
drivers/input/input.c
336
v->code = code;
drivers/input/input.c
337
v->value = value;
drivers/input/joystick/a3d.c
55
unsigned char u, v;
drivers/input/joystick/a3d.c
65
v = gameport_read(gameport);
drivers/input/joystick/a3d.c
69
u = v; v = gameport_read(gameport);
drivers/input/joystick/a3d.c
70
if (~v & u & 0x10) {
drivers/input/joystick/a3d.c
71
data[i++] = v >> 5;
drivers/input/joystick/adi.c
123
unsigned char u, v, w, x;
drivers/input/joystick/adi.c
136
v = gameport_read(gameport);
drivers/input/joystick/adi.c
139
u = v;
drivers/input/joystick/adi.c
140
w = u ^ (v = x = gameport_read(gameport));
drivers/input/joystick/analog.c
366
int i, j, t, v, w, x, y, z;
drivers/input/joystick/analog.c
401
v = (x >> 3);
drivers/input/joystick/analog.c
409
v = x - (x >> 2);
drivers/input/joystick/analog.c
413
input_set_abs_params(input_dev, t, v, (x << 1) - v, port->fuzz, w);
drivers/input/joystick/analog.c
518
int i, t, u, v;
drivers/input/joystick/analog.c
540
u = v = 0;
drivers/input/joystick/analog.c
550
while ((gameport_read(port->gameport) & port->mask) && (v < t))
drivers/input/joystick/analog.c
551
v++;
drivers/input/joystick/analog.c
553
if (v < (u >> 1)) { /* FIXME - more than one port */
drivers/input/joystick/cobra.c
40
unsigned char u, v, w;
drivers/input/joystick/cobra.c
58
v = gameport_read(gameport);
drivers/input/joystick/cobra.c
59
for (i = 0, w = u ^ v; i < 2 && w; i++, w >>= 2)
drivers/input/joystick/cobra.c
64
u = v;
drivers/input/joystick/gf2k.c
77
unsigned char u, v;
drivers/input/joystick/gf2k.c
90
v = gameport_read(gameport);
drivers/input/joystick/gf2k.c
93
t--; u = v;
drivers/input/joystick/gf2k.c
94
v = gameport_read(gameport);
drivers/input/joystick/gf2k.c
95
if (v & ~u & 0x10) {
drivers/input/joystick/gf2k.c
96
data[i++] = v >> 5;
drivers/input/joystick/grip.c
108
unsigned char u, v, w;
drivers/input/joystick/grip.c
121
v = w = (gameport_read(gameport) >> shift) & 3;
drivers/input/joystick/grip.c
127
if (u ^ v) {
drivers/input/joystick/grip.c
129
if ((u ^ v) & 1) {
drivers/input/joystick/grip.c
135
if ((((u ^ v) & (v ^ w)) >> 1) & ~(u | v | w) & 1) {
drivers/input/joystick/grip.c
148
w = v;
drivers/input/joystick/grip.c
149
v = u;
drivers/input/joystick/grip.c
68
unsigned char u, v;
drivers/input/joystick/grip.c
80
v = gameport_read(gameport) >> shift;
drivers/input/joystick/grip.c
84
u = v; v = (gameport_read(gameport) >> shift) & 3;
drivers/input/joystick/grip.c
85
if (~v & u & 1) {
drivers/input/joystick/grip.c
86
data[0] |= (v >> 1) << i++;
drivers/input/joystick/guillemot.c
68
unsigned char u, v;
drivers/input/joystick/guillemot.c
81
v = gameport_read(gameport);
drivers/input/joystick/guillemot.c
85
u = v; v = gameport_read(gameport);
drivers/input/joystick/guillemot.c
86
if (v & ~u & 0x10) {
drivers/input/joystick/guillemot.c
87
data[i >> 3] |= ((v >> 5) & 1) << (i & 7);
drivers/input/joystick/interact.c
75
unsigned char u, v;
drivers/input/joystick/interact.c
86
v = gameport_read(gameport);
drivers/input/joystick/interact.c
90
u = v; v = gameport_read(gameport);
drivers/input/joystick/interact.c
91
if (v & ~u & 0x40) {
drivers/input/joystick/interact.c
92
data[0] = (data[0] << 1) | ((v >> 4) & 1);
drivers/input/joystick/interact.c
93
data[1] = (data[1] << 1) | ((v >> 5) & 1);
drivers/input/joystick/interact.c
94
data[2] = (data[2] << 1) | ((v >> 7) & 1);
drivers/input/joystick/sidewinder.c
121
unsigned char pending, u, v;
drivers/input/joystick/sidewinder.c
135
v = gameport_read(gameport);
drivers/input/joystick/sidewinder.c
139
u = v;
drivers/input/joystick/sidewinder.c
140
v = gameport_read(gameport);
drivers/input/joystick/sidewinder.c
141
} while (!(~v & u & 0x10) && (bitout > 0)); /* Wait for first falling edge on clock */
drivers/input/joystick/sidewinder.c
152
u = v;
drivers/input/joystick/sidewinder.c
153
v = gameport_read(gameport);
drivers/input/joystick/sidewinder.c
155
if ((~u & v & 0x10) && (bitout > 0)) { /* Rising edge on clock - data bit */
drivers/input/joystick/sidewinder.c
157
buf[i] = v >> 5; /* Store it */
drivers/input/joystick/sidewinder.c
162
if (kick && (~v & u & 0x01)) { /* Falling edge on axis 0 */
drivers/input/joystick/tmdc.c
129
unsigned char u, v, w, x;
drivers/input/joystick/tmdc.c
149
for (k = 0, v = w, u = x; k < 2; k++, v >>= 2, u >>= 2) {
drivers/input/joystick/tmdc.c
150
if (~v & u & 2) {
drivers/input/joystick/tmdc.c
154
if (~v & 1) t[k] = 0;
drivers/input/joystick/tmdc.c
158
if (v & 1) t[k] = 0;
drivers/input/joystick/tmdc.c
161
data[k][i[k]] |= (~v & 1) << (j[k]++ - 1); /* Data bit */
drivers/input/keyboard/hilkbd.c
48
#define hil_writeb(v,p) gsc_writeb((v),(p))
drivers/input/keyboard/hilkbd.c
57
#define hil_writeb(v, p) writeb((v), (volatile void __iomem *)(p))
drivers/input/keyboard/lm8323.c
90
#define PWM_SET(v) (0x4000 | ((v) & 0xff))
drivers/input/keyboard/pxa27x_keypad.c
101
#define keypad_writel(off, v) __raw_writel((v), keypad->mmio_base + (off))
drivers/input/misc/hp_sdc_rtc.c
268
static int __maybe_unused hp_sdc_rtc_proc_show(struct seq_file *m, void *v)
drivers/input/misc/mma8450.c
57
static int mma8450_write(struct i2c_client *c, unsigned int off, u8 v)
drivers/input/misc/mma8450.c
61
error = i2c_smbus_write_byte_data(c, off, v);
drivers/input/mouse/sentelic.c
131
unsigned char v;
drivers/input/mouse/sentelic.c
139
if ((v = fsp_test_invert_cmd(reg_addr)) != reg_addr) {
drivers/input/mouse/sentelic.c
143
if ((v = fsp_test_swap_cmd(reg_addr)) != reg_addr) {
drivers/input/mouse/sentelic.c
152
ps2_sendbyte(ps2dev, v, FSP_CMD_TIMEOUT2);
drivers/input/mouse/sentelic.c
157
if ((v = fsp_test_invert_cmd(reg_val)) != reg_val) {
drivers/input/mouse/sentelic.c
160
} else if ((v = fsp_test_swap_cmd(reg_val)) != reg_val) {
drivers/input/mouse/sentelic.c
169
ps2_sendbyte(ps2dev, v, FSP_CMD_TIMEOUT2);
drivers/input/mouse/sentelic.c
183
int v, nv;
drivers/input/mouse/sentelic.c
185
if (fsp_reg_read(psmouse, FSP_REG_SYSCTL1, &v) == -1)
drivers/input/mouse/sentelic.c
189
nv = v | FSP_BIT_EN_REG_CLK;
drivers/input/mouse/sentelic.c
191
nv = v & ~FSP_BIT_EN_REG_CLK;
drivers/input/mouse/sentelic.c
194
if (nv != v)
drivers/input/mouse/sentelic.c
242
unsigned char v;
drivers/input/mouse/sentelic.c
256
if ((v = fsp_test_invert_cmd(reg_val)) != reg_val) {
drivers/input/mouse/sentelic.c
258
} else if ((v = fsp_test_swap_cmd(reg_val)) != reg_val) {
drivers/input/mouse/sentelic.c
266
ps2_sendbyte(ps2dev, v, FSP_CMD_TIMEOUT2);
drivers/input/mouse/sentelic.c
334
int v, nv;
drivers/input/mouse/sentelic.c
337
if (fsp_reg_read(psmouse, FSP_REG_OPC_QDOWN, &v) == -1) {
drivers/input/mouse/sentelic.c
343
nv = v | FSP_BIT_EN_OPC_TAG;
drivers/input/mouse/sentelic.c
345
nv = v & ~FSP_BIT_EN_OPC_TAG;
drivers/input/mouse/sentelic.c
348
if (nv != v) {
drivers/input/serio/hp_sdc.c
81
# define sdc_writeb(v,p) gsc_writeb((v),(p))
drivers/input/serio/hp_sdc.c
85
# define sdc_writeb(v,p) out_8((p),(v))
drivers/input/touchscreen/ad7877.c
446
ssize_t v = ad7877_read_adc(ts->spi, \
drivers/input/touchscreen/ad7877.c
448
if (v < 0) \
drivers/input/touchscreen/ad7877.c
449
return v; \
drivers/input/touchscreen/ad7877.c
450
return sprintf(buf, "%u\n", (unsigned) v); \
drivers/input/touchscreen/ads7846.c
480
ssize_t v = ads7846_read12_ser(&ts->spi->dev, \
drivers/input/touchscreen/ads7846.c
482
if (v < 0) \
drivers/input/touchscreen/ads7846.c
483
return v; \
drivers/input/touchscreen/ads7846.c
484
return sprintf(buf, "%u\n", adjust(ts, v)); \
drivers/input/touchscreen/ads7846.c
494
static inline unsigned null_adjust(struct ads7846 *ts, ssize_t v)
drivers/input/touchscreen/ads7846.c
496
return v;
drivers/input/touchscreen/ads7846.c
507
static inline unsigned vaux_adjust(struct ads7846 *ts, ssize_t v)
drivers/input/touchscreen/ads7846.c
509
unsigned retval = v;
drivers/input/touchscreen/ads7846.c
518
static inline unsigned vbatt_adjust(struct ads7846 *ts, ssize_t v)
drivers/input/touchscreen/ads7846.c
520
unsigned retval = vaux_adjust(ts, v);
drivers/input/touchscreen/da9052_tsi.c
56
u8 v;
drivers/input/touchscreen/da9052_tsi.c
80
v = (u8) ret;
drivers/input/touchscreen/da9052_tsi.c
82
x = ((x << 2) & 0x3fc) | (v & 0x3);
drivers/input/touchscreen/da9052_tsi.c
83
y = ((y << 2) & 0x3fc) | ((v & 0xc) >> 2);
drivers/input/touchscreen/da9052_tsi.c
84
z = ((z << 2) & 0x3fc) | ((v & 0x30) >> 4);
drivers/input/touchscreen/eeti_ts.c
42
#define REPORT_RES_BITS(v) (((v) >> 1) + EETI_TS_BITDEPTH)
drivers/input/touchscreen/melfas_mip4.c
214
static void mip4_parse_fw_version(const u8 *buf, struct mip4_fw_version *v)
drivers/input/touchscreen/melfas_mip4.c
216
v->boot = get_unaligned_le16(buf + 0);
drivers/input/touchscreen/melfas_mip4.c
217
v->core = get_unaligned_le16(buf + 2);
drivers/input/touchscreen/melfas_mip4.c
218
v->app = get_unaligned_le16(buf + 4);
drivers/input/touchscreen/melfas_mip4.c
219
v->param = get_unaligned_le16(buf + 6);
drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c
149
#define hw_queue_to_vcmdq(v) container_of(v, struct tegra241_vcmdq, core)
drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c
181
#define viommu_to_vintf(v) container_of(v, struct tegra241_vintf, vsmmu.core)
drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c
196
#define vdev_to_vsid(v) container_of(v, struct tegra241_vintf_sid, core)
drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c
47
#define TEGRA241_VINTF(v) (0x1000 + 0x100*(v))
drivers/iommu/arm/arm-smmu/arm-smmu.h
522
#define arm_smmu_gr0_write(s, o, v) \
drivers/iommu/arm/arm-smmu/arm-smmu.h
523
arm_smmu_writel((s), ARM_SMMU_GR0, (o), (v))
drivers/iommu/arm/arm-smmu/arm-smmu.h
527
#define arm_smmu_gr1_write(s, o, v) \
drivers/iommu/arm/arm-smmu/arm-smmu.h
528
arm_smmu_writel((s), ARM_SMMU_GR1, (o), (v))
drivers/iommu/arm/arm-smmu/arm-smmu.h
532
#define arm_smmu_cb_write(s, n, o, v) \
drivers/iommu/arm/arm-smmu/arm-smmu.h
533
arm_smmu_writel((s), ARM_SMMU_CB((s), (n)), (o), (v))
drivers/iommu/arm/arm-smmu/arm-smmu.h
536
#define arm_smmu_cb_writeq(s, n, o, v) \
drivers/iommu/arm/arm-smmu/arm-smmu.h
537
arm_smmu_writeq((s), ARM_SMMU_CB((s), (n)), (o), (v))
drivers/iommu/fsl_pamu.h
18
#define set_bf(v, m, x) (v = ((v) & ~(m)) | (((x) << m##_SHIFT) & (m)))
drivers/iommu/fsl_pamu.h
19
#define get_bf(v, m) (((v) & (m)) >> m##_SHIFT)
drivers/iommu/intel/debugfs.c
669
static int latency_show(struct seq_file *m, void *v)
drivers/iommu/intel/iommu.h
152
#define dmar_writeq(a,v) writeq(v,a)
drivers/iommu/intel/iommu.h
154
#define dmar_writel(a, v) writel(v, a)
drivers/iommu/intel/iommu.h
156
#define DMAR_VER_MAJOR(v) (((v) & 0xf0) >> 4)
drivers/iommu/intel/iommu.h
157
#define DMAR_VER_MINOR(v) ((v) & 0x0f)
drivers/iommu/intel/iommu.h
242
#define vccap_pasid(v) (((v) & DMA_VCS_PAS)) /* PASID allocation */
drivers/iommu/msm_iommu_hw-8xxx.h
121
#define SET_SCTLR(b, c, v) SET_CTX_REG(SCTLR, (b), (c), (v))
drivers/iommu/msm_iommu_hw-8xxx.h
122
#define SET_ACTLR(b, c, v) SET_CTX_REG(ACTLR, (b), (c), (v))
drivers/iommu/msm_iommu_hw-8xxx.h
123
#define SET_CONTEXTIDR(b, c, v) SET_CTX_REG(CONTEXTIDR, (b), (c), (v))
drivers/iommu/msm_iommu_hw-8xxx.h
124
#define SET_TTBR0(b, c, v) SET_CTX_REG(TTBR0, (b), (c), (v))
drivers/iommu/msm_iommu_hw-8xxx.h
125
#define SET_TTBR1(b, c, v) SET_CTX_REG(TTBR1, (b), (c), (v))
drivers/iommu/msm_iommu_hw-8xxx.h
126
#define SET_TTBCR(b, c, v) SET_CTX_REG(TTBCR, (b), (c), (v))
drivers/iommu/msm_iommu_hw-8xxx.h
127
#define SET_PAR(b, c, v) SET_CTX_REG(PAR, (b), (c), (v))
drivers/iommu/msm_iommu_hw-8xxx.h
128
#define SET_FSR(b, c, v) SET_CTX_REG(FSR, (b), (c), (v))
drivers/iommu/msm_iommu_hw-8xxx.h
129
#define SET_FSRRESTORE(b, c, v) SET_CTX_REG(FSRRESTORE, (b), (c), (v))
drivers/iommu/msm_iommu_hw-8xxx.h
130
#define SET_FAR(b, c, v) SET_CTX_REG(FAR, (b), (c), (v))
drivers/iommu/msm_iommu_hw-8xxx.h
131
#define SET_FSYNR0(b, c, v) SET_CTX_REG(FSYNR0, (b), (c), (v))
drivers/iommu/msm_iommu_hw-8xxx.h
132
#define SET_FSYNR1(b, c, v) SET_CTX_REG(FSYNR1, (b), (c), (v))
drivers/iommu/msm_iommu_hw-8xxx.h
133
#define SET_PRRR(b, c, v) SET_CTX_REG(PRRR, (b), (c), (v))
drivers/iommu/msm_iommu_hw-8xxx.h
134
#define SET_NMRR(b, c, v) SET_CTX_REG(NMRR, (b), (c), (v))
drivers/iommu/msm_iommu_hw-8xxx.h
135
#define SET_TLBLKCR(b, c, v) SET_CTX_REG(TLBLCKR, (b), (c), (v))
drivers/iommu/msm_iommu_hw-8xxx.h
136
#define SET_V2PSR(b, c, v) SET_CTX_REG(V2PSR, (b), (c), (v))
drivers/iommu/msm_iommu_hw-8xxx.h
137
#define SET_TLBFLPTER(b, c, v) SET_CTX_REG(TLBFLPTER, (b), (c), (v))
drivers/iommu/msm_iommu_hw-8xxx.h
138
#define SET_TLBSLPTER(b, c, v) SET_CTX_REG(TLBSLPTER, (b), (c), (v))
drivers/iommu/msm_iommu_hw-8xxx.h
139
#define SET_BFBCR(b, c, v) SET_CTX_REG(BFBCR, (b), (c), (v))
drivers/iommu/msm_iommu_hw-8xxx.h
140
#define SET_CTX_TLBIALL(b, c, v) SET_CTX_REG(CTX_TLBIALL, (b), (c), (v))
drivers/iommu/msm_iommu_hw-8xxx.h
141
#define SET_TLBIASID(b, c, v) SET_CTX_REG(TLBIASID, (b), (c), (v))
drivers/iommu/msm_iommu_hw-8xxx.h
142
#define SET_TLBIVA(b, c, v) SET_CTX_REG(TLBIVA, (b), (c), (v))
drivers/iommu/msm_iommu_hw-8xxx.h
143
#define SET_TLBIVAA(b, c, v) SET_CTX_REG(TLBIVAA, (b), (c), (v))
drivers/iommu/msm_iommu_hw-8xxx.h
144
#define SET_V2PPR(b, c, v) SET_CTX_REG(V2PPR, (b), (c), (v))
drivers/iommu/msm_iommu_hw-8xxx.h
145
#define SET_V2PPW(b, c, v) SET_CTX_REG(V2PPW, (b), (c), (v))
drivers/iommu/msm_iommu_hw-8xxx.h
146
#define SET_V2PUR(b, c, v) SET_CTX_REG(V2PUR, (b), (c), (v))
drivers/iommu/msm_iommu_hw-8xxx.h
147
#define SET_V2PUW(b, c, v) SET_CTX_REG(V2PUW, (b), (c), (v))
drivers/iommu/msm_iommu_hw-8xxx.h
148
#define SET_RESUME(b, c, v) SET_CTX_REG(RESUME, (b), (c), (v))
drivers/iommu/msm_iommu_hw-8xxx.h
183
#define SET_RWVMID(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), RWVMID, v)
drivers/iommu/msm_iommu_hw-8xxx.h
184
#define SET_RWE(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), RWE, v)
drivers/iommu/msm_iommu_hw-8xxx.h
185
#define SET_RWGE(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), RWGE, v)
drivers/iommu/msm_iommu_hw-8xxx.h
186
#define SET_CBVMID(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), CBVMID, v)
drivers/iommu/msm_iommu_hw-8xxx.h
187
#define SET_IRPTNDX(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), IRPTNDX, v)
drivers/iommu/msm_iommu_hw-8xxx.h
191
#define SET_VMID(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), VMID, v)
drivers/iommu/msm_iommu_hw-8xxx.h
192
#define SET_CBNDX(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), CBNDX, v)
drivers/iommu/msm_iommu_hw-8xxx.h
193
#define SET_BYPASSD(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BYPASSD, v)
drivers/iommu/msm_iommu_hw-8xxx.h
194
#define SET_BPRCOSH(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPRCOSH, v)
drivers/iommu/msm_iommu_hw-8xxx.h
195
#define SET_BPRCISH(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPRCISH, v)
drivers/iommu/msm_iommu_hw-8xxx.h
196
#define SET_BPRCNSH(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPRCNSH, v)
drivers/iommu/msm_iommu_hw-8xxx.h
197
#define SET_BPSHCFG(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPSHCFG, v)
drivers/iommu/msm_iommu_hw-8xxx.h
198
#define SET_NSCFG(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), NSCFG, v)
drivers/iommu/msm_iommu_hw-8xxx.h
199
#define SET_BPMTCFG(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPMTCFG, v)
drivers/iommu/msm_iommu_hw-8xxx.h
20
#define SET_GLOBAL_REG_N(b, n, r, v) SET_GLOBAL_REG(b, ((r) + (n << 2)), (v))
drivers/iommu/msm_iommu_hw-8xxx.h
200
#define SET_BPMEMTYPE(b, n, v) \
drivers/iommu/msm_iommu_hw-8xxx.h
201
SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPMEMTYPE, v)
drivers/iommu/msm_iommu_hw-8xxx.h
205
#define SET_RPUE(b, v) SET_GLOBAL_FIELD(b, CR, RPUE, v)
drivers/iommu/msm_iommu_hw-8xxx.h
206
#define SET_RPUERE(b, v) SET_GLOBAL_FIELD(b, CR, RPUERE, v)
drivers/iommu/msm_iommu_hw-8xxx.h
207
#define SET_RPUEIE(b, v) SET_GLOBAL_FIELD(b, CR, RPUEIE, v)
drivers/iommu/msm_iommu_hw-8xxx.h
208
#define SET_DCDEE(b, v) SET_GLOBAL_FIELD(b, CR, DCDEE, v)
drivers/iommu/msm_iommu_hw-8xxx.h
209
#define SET_CLIENTPD(b, v) SET_GLOBAL_FIELD(b, CR, CLIENTPD, v)
drivers/iommu/msm_iommu_hw-8xxx.h
210
#define SET_STALLD(b, v) SET_GLOBAL_FIELD(b, CR, STALLD, v)
drivers/iommu/msm_iommu_hw-8xxx.h
211
#define SET_TLBLKCRWE(b, v) SET_GLOBAL_FIELD(b, CR, TLBLKCRWE, v)
drivers/iommu/msm_iommu_hw-8xxx.h
212
#define SET_CR_TLBIALLCFG(b, v) SET_GLOBAL_FIELD(b, CR, CR_TLBIALLCFG, v)
drivers/iommu/msm_iommu_hw-8xxx.h
213
#define SET_TLBIVMIDCFG(b, v) SET_GLOBAL_FIELD(b, CR, TLBIVMIDCFG, v)
drivers/iommu/msm_iommu_hw-8xxx.h
214
#define SET_CR_HUME(b, v) SET_GLOBAL_FIELD(b, CR, CR_HUME, v)
drivers/iommu/msm_iommu_hw-8xxx.h
218
#define SET_CFG(b, v) SET_GLOBAL_FIELD(b, ESR, CFG, v)
drivers/iommu/msm_iommu_hw-8xxx.h
219
#define SET_BYPASS(b, v) SET_GLOBAL_FIELD(b, ESR, BYPASS, v)
drivers/iommu/msm_iommu_hw-8xxx.h
220
#define SET_ESR_MULTI(b, v) SET_GLOBAL_FIELD(b, ESR, ESR_MULTI, v)
drivers/iommu/msm_iommu_hw-8xxx.h
224
#define SET_ESYNR0_AMID(b, v) SET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_AMID, v)
drivers/iommu/msm_iommu_hw-8xxx.h
225
#define SET_ESYNR0_APID(b, v) SET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_APID, v)
drivers/iommu/msm_iommu_hw-8xxx.h
226
#define SET_ESYNR0_ABID(b, v) SET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_ABID, v)
drivers/iommu/msm_iommu_hw-8xxx.h
227
#define SET_ESYNR0_AVMID(b, v) SET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_AVMID, v)
drivers/iommu/msm_iommu_hw-8xxx.h
228
#define SET_ESYNR0_ATID(b, v) SET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_ATID, v)
drivers/iommu/msm_iommu_hw-8xxx.h
232
#define SET_ESYNR1_AMEMTYPE(b, v) \
drivers/iommu/msm_iommu_hw-8xxx.h
233
SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AMEMTYPE, v)
drivers/iommu/msm_iommu_hw-8xxx.h
234
#define SET_ESYNR1_ASHARED(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ASHARED, v)
drivers/iommu/msm_iommu_hw-8xxx.h
235
#define SET_ESYNR1_AINNERSHARED(b, v) \
drivers/iommu/msm_iommu_hw-8xxx.h
236
SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AINNERSHARED, v)
drivers/iommu/msm_iommu_hw-8xxx.h
237
#define SET_ESYNR1_APRIV(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_APRIV, v)
drivers/iommu/msm_iommu_hw-8xxx.h
238
#define SET_ESYNR1_APROTNS(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_APROTNS, v)
drivers/iommu/msm_iommu_hw-8xxx.h
239
#define SET_ESYNR1_AINST(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AINST, v)
drivers/iommu/msm_iommu_hw-8xxx.h
240
#define SET_ESYNR1_AWRITE(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AWRITE, v)
drivers/iommu/msm_iommu_hw-8xxx.h
241
#define SET_ESYNR1_ABURST(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ABURST, v)
drivers/iommu/msm_iommu_hw-8xxx.h
242
#define SET_ESYNR1_ALEN(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ALEN, v)
drivers/iommu/msm_iommu_hw-8xxx.h
243
#define SET_ESYNR1_ASIZE(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ASIZE, v)
drivers/iommu/msm_iommu_hw-8xxx.h
244
#define SET_ESYNR1_ALOCK(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ALOCK, v)
drivers/iommu/msm_iommu_hw-8xxx.h
245
#define SET_ESYNR1_AOOO(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AOOO, v)
drivers/iommu/msm_iommu_hw-8xxx.h
246
#define SET_ESYNR1_AFULL(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AFULL, v)
drivers/iommu/msm_iommu_hw-8xxx.h
247
#define SET_ESYNR1_AC(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AC, v)
drivers/iommu/msm_iommu_hw-8xxx.h
248
#define SET_ESYNR1_DCD(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_DCD, v)
drivers/iommu/msm_iommu_hw-8xxx.h
252
#define SET_TBE(b, v) SET_GLOBAL_FIELD(b, TESTBUSCR, TBE, v)
drivers/iommu/msm_iommu_hw-8xxx.h
253
#define SET_SPDMBE(b, v) SET_GLOBAL_FIELD(b, TESTBUSCR, SPDMBE, v)
drivers/iommu/msm_iommu_hw-8xxx.h
254
#define SET_WGSEL(b, v) SET_GLOBAL_FIELD(b, TESTBUSCR, WGSEL, v)
drivers/iommu/msm_iommu_hw-8xxx.h
255
#define SET_TBLSEL(b, v) SET_GLOBAL_FIELD(b, TESTBUSCR, TBLSEL, v)
drivers/iommu/msm_iommu_hw-8xxx.h
256
#define SET_TBHSEL(b, v) SET_GLOBAL_FIELD(b, TESTBUSCR, TBHSEL, v)
drivers/iommu/msm_iommu_hw-8xxx.h
257
#define SET_SPDM0SEL(b, v) SET_GLOBAL_FIELD(b, TESTBUSCR, SPDM0SEL, v)
drivers/iommu/msm_iommu_hw-8xxx.h
258
#define SET_SPDM1SEL(b, v) SET_GLOBAL_FIELD(b, TESTBUSCR, SPDM1SEL, v)
drivers/iommu/msm_iommu_hw-8xxx.h
259
#define SET_SPDM2SEL(b, v) SET_GLOBAL_FIELD(b, TESTBUSCR, SPDM2SEL, v)
drivers/iommu/msm_iommu_hw-8xxx.h
260
#define SET_SPDM3SEL(b, v) SET_GLOBAL_FIELD(b, TESTBUSCR, SPDM3SEL, v)
drivers/iommu/msm_iommu_hw-8xxx.h
264
#define SET_TLBIVMID_VMID(b, v) SET_GLOBAL_FIELD(b, TLBIVMID, TLBIVMID_VMID, v)
drivers/iommu/msm_iommu_hw-8xxx.h
268
#define SET_TLBRSW_INDEX(b, v) SET_GLOBAL_FIELD(b, TLBRSW, TLBRSW_INDEX, v)
drivers/iommu/msm_iommu_hw-8xxx.h
269
#define SET_TLBBFBS(b, v) SET_GLOBAL_FIELD(b, TLBRSW, TLBBFBS, v)
drivers/iommu/msm_iommu_hw-8xxx.h
273
#define SET_PR(b, v) SET_GLOBAL_FIELD(b, TLBTR0, PR, v)
drivers/iommu/msm_iommu_hw-8xxx.h
274
#define SET_PW(b, v) SET_GLOBAL_FIELD(b, TLBTR0, PW, v)
drivers/iommu/msm_iommu_hw-8xxx.h
275
#define SET_UR(b, v) SET_GLOBAL_FIELD(b, TLBTR0, UR, v)
drivers/iommu/msm_iommu_hw-8xxx.h
276
#define SET_UW(b, v) SET_GLOBAL_FIELD(b, TLBTR0, UW, v)
drivers/iommu/msm_iommu_hw-8xxx.h
277
#define SET_XN(b, v) SET_GLOBAL_FIELD(b, TLBTR0, XN, v)
drivers/iommu/msm_iommu_hw-8xxx.h
278
#define SET_NSDESC(b, v) SET_GLOBAL_FIELD(b, TLBTR0, NSDESC, v)
drivers/iommu/msm_iommu_hw-8xxx.h
279
#define SET_ISH(b, v) SET_GLOBAL_FIELD(b, TLBTR0, ISH, v)
drivers/iommu/msm_iommu_hw-8xxx.h
28
#define SET_GLOBAL_FIELD(b, r, F, v) \
drivers/iommu/msm_iommu_hw-8xxx.h
280
#define SET_SH(b, v) SET_GLOBAL_FIELD(b, TLBTR0, SH, v)
drivers/iommu/msm_iommu_hw-8xxx.h
281
#define SET_MT(b, v) SET_GLOBAL_FIELD(b, TLBTR0, MT, v)
drivers/iommu/msm_iommu_hw-8xxx.h
282
#define SET_DPSIZR(b, v) SET_GLOBAL_FIELD(b, TLBTR0, DPSIZR, v)
drivers/iommu/msm_iommu_hw-8xxx.h
283
#define SET_DPSIZC(b, v) SET_GLOBAL_FIELD(b, TLBTR0, DPSIZC, v)
drivers/iommu/msm_iommu_hw-8xxx.h
287
#define SET_TLBTR1_VMID(b, v) SET_GLOBAL_FIELD(b, TLBTR1, TLBTR1_VMID, v)
drivers/iommu/msm_iommu_hw-8xxx.h
288
#define SET_TLBTR1_PA(b, v) SET_GLOBAL_FIELD(b, TLBTR1, TLBTR1_PA, v)
drivers/iommu/msm_iommu_hw-8xxx.h
29
SET_FIELD(((b) + (r)), F##_MASK, F##_SHIFT, (v))
drivers/iommu/msm_iommu_hw-8xxx.h
292
#define SET_TLBTR2_ASID(b, v) SET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_ASID, v)
drivers/iommu/msm_iommu_hw-8xxx.h
293
#define SET_TLBTR2_V(b, v) SET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_V, v)
drivers/iommu/msm_iommu_hw-8xxx.h
294
#define SET_TLBTR2_NSTID(b, v) SET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_NSTID, v)
drivers/iommu/msm_iommu_hw-8xxx.h
295
#define SET_TLBTR2_NV(b, v) SET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_NV, v)
drivers/iommu/msm_iommu_hw-8xxx.h
296
#define SET_TLBTR2_VA(b, v) SET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_VA, v)
drivers/iommu/msm_iommu_hw-8xxx.h
30
#define SET_CONTEXT_FIELD(b, c, r, F, v) \
drivers/iommu/msm_iommu_hw-8xxx.h
31
SET_FIELD(((b) + (r) + ((c) << CTX_SHIFT)), F##_MASK, F##_SHIFT, (v))
drivers/iommu/msm_iommu_hw-8xxx.h
35
#define SET_FIELD(addr, mask, shift, v) \
drivers/iommu/msm_iommu_hw-8xxx.h
38
writel((t & ~((mask) << (shift))) + (((v) & (mask)) << (shift)), addr);\
drivers/iommu/msm_iommu_hw-8xxx.h
427
#define SET_CFERE(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, CFERE, v)
drivers/iommu/msm_iommu_hw-8xxx.h
428
#define SET_CFEIE(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, CFEIE, v)
drivers/iommu/msm_iommu_hw-8xxx.h
429
#define SET_PTSHCFG(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, PTSHCFG, v)
drivers/iommu/msm_iommu_hw-8xxx.h
430
#define SET_RCOSH(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, RCOSH, v)
drivers/iommu/msm_iommu_hw-8xxx.h
431
#define SET_RCISH(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, RCISH, v)
drivers/iommu/msm_iommu_hw-8xxx.h
432
#define SET_RCNSH(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, RCNSH, v)
drivers/iommu/msm_iommu_hw-8xxx.h
433
#define SET_PRIVCFG(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, PRIVCFG, v)
drivers/iommu/msm_iommu_hw-8xxx.h
434
#define SET_DNA(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, DNA, v)
drivers/iommu/msm_iommu_hw-8xxx.h
435
#define SET_DNLV2PA(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, DNLV2PA, v)
drivers/iommu/msm_iommu_hw-8xxx.h
436
#define SET_TLBMCFG(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, TLBMCFG, v)
drivers/iommu/msm_iommu_hw-8xxx.h
437
#define SET_CFCFG(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, CFCFG, v)
drivers/iommu/msm_iommu_hw-8xxx.h
438
#define SET_TIPCF(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, TIPCF, v)
drivers/iommu/msm_iommu_hw-8xxx.h
439
#define SET_V2PCFG(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, V2PCFG, v)
drivers/iommu/msm_iommu_hw-8xxx.h
440
#define SET_HUME(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, HUME, v)
drivers/iommu/msm_iommu_hw-8xxx.h
441
#define SET_PTMTCFG(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, PTMTCFG, v)
drivers/iommu/msm_iommu_hw-8xxx.h
442
#define SET_PTMEMTYPE(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, PTMEMTYPE, v)
drivers/iommu/msm_iommu_hw-8xxx.h
446
#define SET_BFBDFE(b, c, v) SET_CONTEXT_FIELD(b, c, BFBCR, BFBDFE, v)
drivers/iommu/msm_iommu_hw-8xxx.h
447
#define SET_BFBSFE(b, c, v) SET_CONTEXT_FIELD(b, c, BFBCR, BFBSFE, v)
drivers/iommu/msm_iommu_hw-8xxx.h
448
#define SET_SFVS(b, c, v) SET_CONTEXT_FIELD(b, c, BFBCR, SFVS, v)
drivers/iommu/msm_iommu_hw-8xxx.h
449
#define SET_FLVIC(b, c, v) SET_CONTEXT_FIELD(b, c, BFBCR, FLVIC, v)
drivers/iommu/msm_iommu_hw-8xxx.h
450
#define SET_SLVIC(b, c, v) SET_CONTEXT_FIELD(b, c, BFBCR, SLVIC, v)
drivers/iommu/msm_iommu_hw-8xxx.h
454
#define SET_CONTEXTIDR_ASID(b, c, v) \
drivers/iommu/msm_iommu_hw-8xxx.h
455
SET_CONTEXT_FIELD(b, c, CONTEXTIDR, CONTEXTIDR_ASID, v)
drivers/iommu/msm_iommu_hw-8xxx.h
456
#define SET_CONTEXTIDR_PROCID(b, c, v) \
drivers/iommu/msm_iommu_hw-8xxx.h
457
SET_CONTEXT_FIELD(b, c, CONTEXTIDR, PROCID, v)
drivers/iommu/msm_iommu_hw-8xxx.h
461
#define SET_TF(b, c, v) SET_CONTEXT_FIELD(b, c, FSR, TF, v)
drivers/iommu/msm_iommu_hw-8xxx.h
462
#define SET_AFF(b, c, v) SET_CONTEXT_FIELD(b, c, FSR, AFF, v)
drivers/iommu/msm_iommu_hw-8xxx.h
463
#define SET_APF(b, c, v) SET_CONTEXT_FIELD(b, c, FSR, APF, v)
drivers/iommu/msm_iommu_hw-8xxx.h
464
#define SET_TLBMF(b, c, v) SET_CONTEXT_FIELD(b, c, FSR, TLBMF, v)
drivers/iommu/msm_iommu_hw-8xxx.h
465
#define SET_HTWDEEF(b, c, v) SET_CONTEXT_FIELD(b, c, FSR, HTWDEEF, v)
drivers/iommu/msm_iommu_hw-8xxx.h
466
#define SET_HTWSEEF(b, c, v) SET_CONTEXT_FIELD(b, c, FSR, HTWSEEF, v)
drivers/iommu/msm_iommu_hw-8xxx.h
467
#define SET_MHF(b, c, v) SET_CONTEXT_FIELD(b, c, FSR, MHF, v)
drivers/iommu/msm_iommu_hw-8xxx.h
468
#define SET_SL(b, c, v) SET_CONTEXT_FIELD(b, c, FSR, SL, v)
drivers/iommu/msm_iommu_hw-8xxx.h
469
#define SET_SS(b, c, v) SET_CONTEXT_FIELD(b, c, FSR, SS, v)
drivers/iommu/msm_iommu_hw-8xxx.h
470
#define SET_MULTI(b, c, v) SET_CONTEXT_FIELD(b, c, FSR, MULTI, v)
drivers/iommu/msm_iommu_hw-8xxx.h
474
#define SET_AMID(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR0, AMID, v)
drivers/iommu/msm_iommu_hw-8xxx.h
475
#define SET_APID(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR0, APID, v)
drivers/iommu/msm_iommu_hw-8xxx.h
476
#define SET_ABID(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR0, ABID, v)
drivers/iommu/msm_iommu_hw-8xxx.h
477
#define SET_ATID(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR0, ATID, v)
drivers/iommu/msm_iommu_hw-8xxx.h
481
#define SET_AMEMTYPE(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR1, AMEMTYPE, v)
drivers/iommu/msm_iommu_hw-8xxx.h
482
#define SET_ASHARED(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR1, ASHARED, v)
drivers/iommu/msm_iommu_hw-8xxx.h
483
#define SET_AINNERSHARED(b, c, v) \
drivers/iommu/msm_iommu_hw-8xxx.h
484
SET_CONTEXT_FIELD(b, c, FSYNR1, AINNERSHARED, v)
drivers/iommu/msm_iommu_hw-8xxx.h
485
#define SET_APRIV(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR1, APRIV, v)
drivers/iommu/msm_iommu_hw-8xxx.h
486
#define SET_APROTNS(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR1, APROTNS, v)
drivers/iommu/msm_iommu_hw-8xxx.h
487
#define SET_AINST(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR1, AINST, v)
drivers/iommu/msm_iommu_hw-8xxx.h
488
#define SET_AWRITE(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR1, AWRITE, v)
drivers/iommu/msm_iommu_hw-8xxx.h
489
#define SET_ABURST(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR1, ABURST, v)
drivers/iommu/msm_iommu_hw-8xxx.h
490
#define SET_ALEN(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR1, ALEN, v)
drivers/iommu/msm_iommu_hw-8xxx.h
491
#define SET_FSYNR1_ASIZE(b, c, v) \
drivers/iommu/msm_iommu_hw-8xxx.h
492
SET_CONTEXT_FIELD(b, c, FSYNR1, FSYNR1_ASIZE, v)
drivers/iommu/msm_iommu_hw-8xxx.h
493
#define SET_ALOCK(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR1, ALOCK, v)
drivers/iommu/msm_iommu_hw-8xxx.h
494
#define SET_AFULL(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR1, AFULL, v)
drivers/iommu/msm_iommu_hw-8xxx.h
498
#define SET_ICPC0(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, ICPC0, v)
drivers/iommu/msm_iommu_hw-8xxx.h
499
#define SET_ICPC1(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, ICPC1, v)
drivers/iommu/msm_iommu_hw-8xxx.h
500
#define SET_ICPC2(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, ICPC2, v)
drivers/iommu/msm_iommu_hw-8xxx.h
501
#define SET_ICPC3(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, ICPC3, v)
drivers/iommu/msm_iommu_hw-8xxx.h
502
#define SET_ICPC4(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, ICPC4, v)
drivers/iommu/msm_iommu_hw-8xxx.h
503
#define SET_ICPC5(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, ICPC5, v)
drivers/iommu/msm_iommu_hw-8xxx.h
504
#define SET_ICPC6(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, ICPC6, v)
drivers/iommu/msm_iommu_hw-8xxx.h
505
#define SET_ICPC7(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, ICPC7, v)
drivers/iommu/msm_iommu_hw-8xxx.h
506
#define SET_OCPC0(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, OCPC0, v)
drivers/iommu/msm_iommu_hw-8xxx.h
507
#define SET_OCPC1(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, OCPC1, v)
drivers/iommu/msm_iommu_hw-8xxx.h
508
#define SET_OCPC2(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, OCPC2, v)
drivers/iommu/msm_iommu_hw-8xxx.h
509
#define SET_OCPC3(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, OCPC3, v)
drivers/iommu/msm_iommu_hw-8xxx.h
510
#define SET_OCPC4(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, OCPC4, v)
drivers/iommu/msm_iommu_hw-8xxx.h
511
#define SET_OCPC5(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, OCPC5, v)
drivers/iommu/msm_iommu_hw-8xxx.h
512
#define SET_OCPC6(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, OCPC6, v)
drivers/iommu/msm_iommu_hw-8xxx.h
513
#define SET_OCPC7(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, OCPC7, v)
drivers/iommu/msm_iommu_hw-8xxx.h
517
#define SET_FAULT(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, FAULT, v)
drivers/iommu/msm_iommu_hw-8xxx.h
519
#define SET_FAULT_TF(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, FAULT_TF, v)
drivers/iommu/msm_iommu_hw-8xxx.h
520
#define SET_FAULT_AFF(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, FAULT_AFF, v)
drivers/iommu/msm_iommu_hw-8xxx.h
521
#define SET_FAULT_APF(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, FAULT_APF, v)
drivers/iommu/msm_iommu_hw-8xxx.h
522
#define SET_FAULT_TLBMF(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, FAULT_TLBMF, v)
drivers/iommu/msm_iommu_hw-8xxx.h
523
#define SET_FAULT_HTWDEEF(b, c, v) \
drivers/iommu/msm_iommu_hw-8xxx.h
524
SET_CONTEXT_FIELD(b, c, PAR, FAULT_HTWDEEF, v)
drivers/iommu/msm_iommu_hw-8xxx.h
525
#define SET_FAULT_HTWSEEF(b, c, v) \
drivers/iommu/msm_iommu_hw-8xxx.h
526
SET_CONTEXT_FIELD(b, c, PAR, FAULT_HTWSEEF, v)
drivers/iommu/msm_iommu_hw-8xxx.h
527
#define SET_FAULT_MHF(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, FAULT_MHF, v)
drivers/iommu/msm_iommu_hw-8xxx.h
528
#define SET_FAULT_SL(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, FAULT_SL, v)
drivers/iommu/msm_iommu_hw-8xxx.h
529
#define SET_FAULT_SS(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, FAULT_SS, v)
drivers/iommu/msm_iommu_hw-8xxx.h
531
#define SET_NOFAULT_SS(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, NOFAULT_SS, v)
drivers/iommu/msm_iommu_hw-8xxx.h
532
#define SET_NOFAULT_MT(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, NOFAULT_MT, v)
drivers/iommu/msm_iommu_hw-8xxx.h
533
#define SET_NOFAULT_SH(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, NOFAULT_SH, v)
drivers/iommu/msm_iommu_hw-8xxx.h
534
#define SET_NOFAULT_NS(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, NOFAULT_NS, v)
drivers/iommu/msm_iommu_hw-8xxx.h
535
#define SET_NOFAULT_NOS(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, NOFAULT_NOS, v)
drivers/iommu/msm_iommu_hw-8xxx.h
536
#define SET_NPFAULT_PA(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, NPFAULT_PA, v)
drivers/iommu/msm_iommu_hw-8xxx.h
540
#define SET_MTC0(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, MTC0, v)
drivers/iommu/msm_iommu_hw-8xxx.h
541
#define SET_MTC1(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, MTC1, v)
drivers/iommu/msm_iommu_hw-8xxx.h
542
#define SET_MTC2(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, MTC2, v)
drivers/iommu/msm_iommu_hw-8xxx.h
543
#define SET_MTC3(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, MTC3, v)
drivers/iommu/msm_iommu_hw-8xxx.h
544
#define SET_MTC4(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, MTC4, v)
drivers/iommu/msm_iommu_hw-8xxx.h
545
#define SET_MTC5(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, MTC5, v)
drivers/iommu/msm_iommu_hw-8xxx.h
546
#define SET_MTC6(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, MTC6, v)
drivers/iommu/msm_iommu_hw-8xxx.h
547
#define SET_MTC7(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, MTC7, v)
drivers/iommu/msm_iommu_hw-8xxx.h
548
#define SET_SHDSH0(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, SHDSH0, v)
drivers/iommu/msm_iommu_hw-8xxx.h
549
#define SET_SHDSH1(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, SHDSH1, v)
drivers/iommu/msm_iommu_hw-8xxx.h
550
#define SET_SHNMSH0(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, SHNMSH0, v)
drivers/iommu/msm_iommu_hw-8xxx.h
551
#define SET_SHNMSH1(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, SHNMSH1, v)
drivers/iommu/msm_iommu_hw-8xxx.h
552
#define SET_NOS0(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, NOS0, v)
drivers/iommu/msm_iommu_hw-8xxx.h
553
#define SET_NOS1(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, NOS1, v)
drivers/iommu/msm_iommu_hw-8xxx.h
554
#define SET_NOS2(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, NOS2, v)
drivers/iommu/msm_iommu_hw-8xxx.h
555
#define SET_NOS3(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, NOS3, v)
drivers/iommu/msm_iommu_hw-8xxx.h
556
#define SET_NOS4(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, NOS4, v)
drivers/iommu/msm_iommu_hw-8xxx.h
557
#define SET_NOS5(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, NOS5, v)
drivers/iommu/msm_iommu_hw-8xxx.h
558
#define SET_NOS6(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, NOS6, v)
drivers/iommu/msm_iommu_hw-8xxx.h
559
#define SET_NOS7(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, NOS7, v)
drivers/iommu/msm_iommu_hw-8xxx.h
563
#define SET_TNR(b, c, v) SET_CONTEXT_FIELD(b, c, RESUME, TNR, v)
drivers/iommu/msm_iommu_hw-8xxx.h
567
#define SET_M(b, c, v) SET_CONTEXT_FIELD(b, c, SCTLR, M, v)
drivers/iommu/msm_iommu_hw-8xxx.h
568
#define SET_TRE(b, c, v) SET_CONTEXT_FIELD(b, c, SCTLR, TRE, v)
drivers/iommu/msm_iommu_hw-8xxx.h
569
#define SET_AFE(b, c, v) SET_CONTEXT_FIELD(b, c, SCTLR, AFE, v)
drivers/iommu/msm_iommu_hw-8xxx.h
570
#define SET_HAF(b, c, v) SET_CONTEXT_FIELD(b, c, SCTLR, HAF, v)
drivers/iommu/msm_iommu_hw-8xxx.h
571
#define SET_BE(b, c, v) SET_CONTEXT_FIELD(b, c, SCTLR, BE, v)
drivers/iommu/msm_iommu_hw-8xxx.h
572
#define SET_AFFD(b, c, v) SET_CONTEXT_FIELD(b, c, SCTLR, AFFD, v)
drivers/iommu/msm_iommu_hw-8xxx.h
576
#define SET_LKE(b, c, v) SET_CONTEXT_FIELD(b, c, TLBLKCR, LKE, v)
drivers/iommu/msm_iommu_hw-8xxx.h
577
#define SET_TLBLKCR_TLBIALLCFG(b, c, v) \
drivers/iommu/msm_iommu_hw-8xxx.h
578
SET_CONTEXT_FIELD(b, c, TLBLKCR, TLBLCKR_TLBIALLCFG, v)
drivers/iommu/msm_iommu_hw-8xxx.h
579
#define SET_TLBIASIDCFG(b, c, v) \
drivers/iommu/msm_iommu_hw-8xxx.h
580
SET_CONTEXT_FIELD(b, c, TLBLKCR, TLBIASIDCFG, v)
drivers/iommu/msm_iommu_hw-8xxx.h
581
#define SET_TLBIVAACFG(b, c, v) SET_CONTEXT_FIELD(b, c, TLBLKCR, TLBIVAACFG, v)
drivers/iommu/msm_iommu_hw-8xxx.h
582
#define SET_FLOOR(b, c, v) SET_CONTEXT_FIELD(b, c, TLBLKCR, FLOOR, v)
drivers/iommu/msm_iommu_hw-8xxx.h
583
#define SET_VICTIM(b, c, v) SET_CONTEXT_FIELD(b, c, TLBLKCR, VICTIM, v)
drivers/iommu/msm_iommu_hw-8xxx.h
587
#define SET_N(b, c, v) SET_CONTEXT_FIELD(b, c, TTBCR, N, v)
drivers/iommu/msm_iommu_hw-8xxx.h
588
#define SET_PD0(b, c, v) SET_CONTEXT_FIELD(b, c, TTBCR, PD0, v)
drivers/iommu/msm_iommu_hw-8xxx.h
589
#define SET_PD1(b, c, v) SET_CONTEXT_FIELD(b, c, TTBCR, PD1, v)
drivers/iommu/msm_iommu_hw-8xxx.h
593
#define SET_TTBR0_IRGNH(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_IRGNH, v)
drivers/iommu/msm_iommu_hw-8xxx.h
594
#define SET_TTBR0_SH(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_SH, v)
drivers/iommu/msm_iommu_hw-8xxx.h
595
#define SET_TTBR0_ORGN(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_ORGN, v)
drivers/iommu/msm_iommu_hw-8xxx.h
596
#define SET_TTBR0_NOS(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_NOS, v)
drivers/iommu/msm_iommu_hw-8xxx.h
597
#define SET_TTBR0_IRGNL(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_IRGNL, v)
drivers/iommu/msm_iommu_hw-8xxx.h
598
#define SET_TTBR0_PA(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_PA, v)
drivers/iommu/msm_iommu_hw-8xxx.h
602
#define SET_TTBR1_IRGNH(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_IRGNH, v)
drivers/iommu/msm_iommu_hw-8xxx.h
603
#define SET_TTBR1_SH(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_SH, v)
drivers/iommu/msm_iommu_hw-8xxx.h
604
#define SET_TTBR1_ORGN(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_ORGN, v)
drivers/iommu/msm_iommu_hw-8xxx.h
605
#define SET_TTBR1_NOS(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_NOS, v)
drivers/iommu/msm_iommu_hw-8xxx.h
606
#define SET_TTBR1_IRGNL(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_IRGNL, v)
drivers/iommu/msm_iommu_hw-8xxx.h
607
#define SET_TTBR1_PA(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_PA, v)
drivers/iommu/msm_iommu_hw-8xxx.h
611
#define SET_HIT(b, c, v) SET_CONTEXT_FIELD(b, c, V2PSR, HIT, v)
drivers/iommu/msm_iommu_hw-8xxx.h
612
#define SET_INDEX(b, c, v) SET_CONTEXT_FIELD(b, c, V2PSR, INDEX, v)
drivers/iommu/msm_iommu_hw-8xxx.h
84
#define SET_M2VCBR_N(b, N, v) SET_GLOBAL_REG_N(M2VCBR_N, N, (b), (v))
drivers/iommu/msm_iommu_hw-8xxx.h
85
#define SET_CBACR_N(b, N, v) SET_GLOBAL_REG_N(CBACR_N, N, (b), (v))
drivers/iommu/msm_iommu_hw-8xxx.h
86
#define SET_TLBRSW(b, v) SET_GLOBAL_REG(TLBRSW, (b), (v))
drivers/iommu/msm_iommu_hw-8xxx.h
87
#define SET_TLBTR0(b, v) SET_GLOBAL_REG(TLBTR0, (b), (v))
drivers/iommu/msm_iommu_hw-8xxx.h
88
#define SET_TLBTR1(b, v) SET_GLOBAL_REG(TLBTR1, (b), (v))
drivers/iommu/msm_iommu_hw-8xxx.h
89
#define SET_TLBTR2(b, v) SET_GLOBAL_REG(TLBTR2, (b), (v))
drivers/iommu/msm_iommu_hw-8xxx.h
90
#define SET_TESTBUSCR(b, v) SET_GLOBAL_REG(TESTBUSCR, (b), (v))
drivers/iommu/msm_iommu_hw-8xxx.h
91
#define SET_GLOBAL_TLBIALL(b, v) SET_GLOBAL_REG(GLOBAL_TLBIALL, (b), (v))
drivers/iommu/msm_iommu_hw-8xxx.h
92
#define SET_TLBIVMID(b, v) SET_GLOBAL_REG(TLBIVMID, (b), (v))
drivers/iommu/msm_iommu_hw-8xxx.h
93
#define SET_CR(b, v) SET_GLOBAL_REG(CR, (b), (v))
drivers/iommu/msm_iommu_hw-8xxx.h
94
#define SET_EAR(b, v) SET_GLOBAL_REG(EAR, (b), (v))
drivers/iommu/msm_iommu_hw-8xxx.h
95
#define SET_ESR(b, v) SET_GLOBAL_REG(ESR, (b), (v))
drivers/iommu/msm_iommu_hw-8xxx.h
96
#define SET_ESRRESTORE(b, v) SET_GLOBAL_REG(ESRRESTORE, (b), (v))
drivers/iommu/msm_iommu_hw-8xxx.h
97
#define SET_ESYNR0(b, v) SET_GLOBAL_REG(ESYNR0, (b), (v))
drivers/iommu/msm_iommu_hw-8xxx.h
98
#define SET_ESYNR1(b, v) SET_GLOBAL_REG(ESYNR1, (b), (v))
drivers/iommu/msm_iommu_hw-8xxx.h
99
#define SET_RPU_ACR(b, v) SET_GLOBAL_REG(RPU_ACR, (b), (v))
drivers/irqchip/irq-econet-en751221.c
60
u32 v;
drivers/irqchip/irq-econet-en751221.c
64
v = ioread32(econet_intc.membase + reg);
drivers/irqchip/irq-econet-en751221.c
65
v &= ~mask;
drivers/irqchip/irq-econet-en751221.c
66
v |= val & mask;
drivers/irqchip/irq-econet-en751221.c
67
iowrite32(v, econet_intc.membase + reg);
drivers/irqchip/irq-gic-v3.c
1483
unsigned long cmd, void *v)
drivers/irqchip/irq-gic.c
707
static int gic_notifier(struct notifier_block *self, unsigned long cmd, void *v)
drivers/irqchip/irq-mips-gic.c
846
unsigned int v[2], num_ipis;
drivers/irqchip/irq-mips-gic.c
860
!of_property_read_u32_array(node, "mti,reserved-ipi-vectors", v, 2)) {
drivers/irqchip/irq-mips-gic.c
861
bitmap_set(ipi_resrv, v[0], v[1]);
drivers/irqchip/irq-riscv-aplic-direct.c
240
u32 v, hwirq;
drivers/irqchip/irq-riscv-aplic-direct.c
293
v = FIELD_PREP(APLIC_TARGET_HART_IDX, idc->hart_index);
drivers/irqchip/irq-riscv-aplic-direct.c
294
v |= FIELD_PREP(APLIC_TARGET_IPRIO, APLIC_DEFAULT_PRIORITY);
drivers/irqchip/irq-riscv-aplic-direct.c
296
writel(v, priv->regs + APLIC_TARGET_BASE + (j - 1) * sizeof(u32));
drivers/irqchip/irq-riscv-imsic-early.c
167
static int imsic_pm_notifier(struct notifier_block *self, unsigned long cmd, void *v)
drivers/irqchip/irq-sp7021-intc.c
58
#define ASSIGN_STATE(irq, idx, v) assign_bit(STATE_BIT(irq, idx), sp_intc.states, v)
drivers/irqchip/irq-sun6i-r.c
314
const struct sun6i_r_intc_variant *v)
drivers/irqchip/irq-sun6i-r.c
330
bitmap_set(wake_irq_enabled, v->first_mux_irq, v->nr_mux_irqs);
drivers/irqchip/irq-sun6i-r.c
331
bitmap_from_arr32(wake_mux_valid, v->mux_valid, SUN6I_NR_MUX_BITS);
drivers/irqchip/irq-vf610-mscm-ir.c
67
unsigned long cmd, void *v)
drivers/irqchip/irq-vic.c
190
struct vic_device *v = d->host_data;
drivers/irqchip/irq-vic.c
193
if (!(v->valid_sources & (1 << hwirq)))
drivers/irqchip/irq-vic.c
196
irq_set_chip_data(irq, v->base);
drivers/irqchip/irq-vic.c
276
struct vic_device *v;
drivers/irqchip/irq-vic.c
284
v = &vic_devices[vic_id];
drivers/irqchip/irq-vic.c
285
v->base = base;
drivers/irqchip/irq-vic.c
286
v->valid_sources = valid_sources;
drivers/irqchip/irq-vic.c
287
v->resume_sources = resume_sources;
drivers/irqchip/irq-vic.c
293
vic_handle_irq_cascaded, v);
drivers/irqchip/irq-vic.c
296
v->domain = irq_domain_create_simple(of_fwnode_handle(node),
drivers/irqchip/irq-vic.c
298
&vic_irqdomain_ops, v);
drivers/irqchip/irq-vic.c
302
irq_create_mapping(v->domain, i);
drivers/irqchip/irq-vic.c
305
v->irq = irq;
drivers/irqchip/irq-vic.c
307
v->irq = irq_find_mapping(v->domain, 0);
drivers/irqchip/irq-vic.c
336
struct vic_device *v = vic_devices;
drivers/irqchip/irq-vic.c
340
for (id = 0; id < vic_id; id++, v++) {
drivers/irqchip/irq-vic.c
341
if (v->irq == base_irq)
drivers/irqchip/irq-vic.c
342
return v;
drivers/irqchip/irq-vic.c
350
struct vic_device *v = vic_from_irq(d->irq);
drivers/irqchip/irq-vic.c
354
if (!v)
drivers/irqchip/irq-vic.c
357
if (!(bit & v->resume_sources))
drivers/irqchip/irq-vic.c
361
v->resume_irqs |= bit;
drivers/irqchip/irq-vic.c
363
v->resume_irqs &= ~bit;
drivers/isdn/capi/capi.c
1320
static int __maybe_unused capi20_proc_show(struct seq_file *m, void *v)
drivers/isdn/capi/capi.c
1343
static int __maybe_unused capi20ncci_proc_show(struct seq_file *m, void *v)
drivers/isdn/capi/kcapi_proc.c
129
applications_next(struct seq_file *seq, void *v, loff_t *pos)
drivers/isdn/capi/kcapi_proc.c
138
static void applications_stop(struct seq_file *seq, void *v)
drivers/isdn/capi/kcapi_proc.c
145
applications_show(struct seq_file *seq, void *v)
drivers/isdn/capi/kcapi_proc.c
147
struct capi20_appl *ap = *(struct capi20_appl **) v;
drivers/isdn/capi/kcapi_proc.c
162
applstats_show(struct seq_file *seq, void *v)
drivers/isdn/capi/kcapi_proc.c
164
struct capi20_appl *ap = *(struct capi20_appl **) v;
drivers/isdn/capi/kcapi_proc.c
49
static void *controller_next(struct seq_file *seq, void *v, loff_t *pos)
drivers/isdn/capi/kcapi_proc.c
58
static void controller_stop(struct seq_file *seq, void *v)
drivers/isdn/capi/kcapi_proc.c
64
static int controller_show(struct seq_file *seq, void *v)
drivers/isdn/capi/kcapi_proc.c
66
struct capi_ctr *ctr = *(struct capi_ctr **) v;
drivers/isdn/capi/kcapi_proc.c
80
static int contrstats_show(struct seq_file *seq, void *v)
drivers/isdn/capi/kcapi_proc.c
82
struct capi_ctr *ctr = *(struct capi_ctr **) v;
drivers/isdn/hardware/mISDN/mISDNipac.c
28
#define WriteISAC(is, o, v) (is->write_reg(is->dch.hw, o + is->off, v))
drivers/isdn/hardware/mISDN/mISDNipac.c
30
#define WriteHSCX(h, o, v) (h->ip->write_reg(h->ip->hw, h->off + o, v))
drivers/isdn/hardware/mISDN/mISDNipac.c
32
#define WriteIPAC(ip, o, v) (ip->write_reg(ip->hw, o, v))
drivers/isdn/hardware/mISDN/netjet.c
492
u32 m, v;
drivers/isdn/hardware/mISDN/netjet.c
512
v = card->send.start[bc->idx];
drivers/isdn/hardware/mISDN/netjet.c
513
v &= m;
drivers/isdn/hardware/mISDN/netjet.c
514
v |= (bc->bch.nr & 1) ? (u32)(p[i]) : ((u32)(p[i])) << 8;
drivers/isdn/hardware/mISDN/netjet.c
515
card->send.start[bc->idx++] = v;
drivers/isdn/hardware/mISDN/netjet.c
529
u32 m, v, n = 0;
drivers/isdn/hardware/mISDN/netjet.c
575
v = card->send.start[bc->idx];
drivers/isdn/hardware/mISDN/netjet.c
576
v &= m;
drivers/isdn/hardware/mISDN/netjet.c
577
v |= n;
drivers/isdn/hardware/mISDN/netjet.c
578
card->send.start[bc->idx++] = v;
drivers/isdn/hardware/mISDN/netjet.c
584
v = card->send.start[bc->idx];
drivers/isdn/hardware/mISDN/netjet.c
585
v &= m;
drivers/isdn/hardware/mISDN/netjet.c
587
v |= (bc->bch.nr & 1) ? n : n << 8;
drivers/isdn/hardware/mISDN/netjet.c
588
card->send.start[bc->idx++] = v;
drivers/leds/flash/leds-max77693.c
151
int ret, v = 0, i;
drivers/leds/flash/leds-max77693.c
155
v |= FLASH_EN_ON << TORCH_EN_SHIFT(i);
drivers/leds/flash/leds-max77693.c
158
v |= FLASH_EN_ON << FLASH_EN_SHIFT(i);
drivers/leds/flash/leds-max77693.c
160
v |= FLASH_EN_FLASH << FLASH_EN_SHIFT(i);
drivers/leds/flash/leds-max77693.c
166
v |= FLASH_EN_TORCH << TORCH_EN_SHIFT(i);
drivers/leds/flash/leds-max77693.c
177
return regmap_write(rmap, MAX77693_LED_REG_FLASH_EN, v);
drivers/leds/flash/leds-max77693.c
323
u8 v;
drivers/leds/flash/leds-max77693.c
326
v = max77693_flash_timeout_to_reg(microsec) | FLASH_TMR_LEVEL;
drivers/leds/flash/leds-max77693.c
328
ret = regmap_write(rmap, MAX77693_LED_REG_FLASH_TIMER, v);
drivers/leds/flash/leds-max77693.c
341
unsigned int v;
drivers/leds/flash/leds-max77693.c
344
ret = regmap_read(rmap, MAX77693_LED_REG_FLASH_STATUS, &v);
drivers/leds/flash/leds-max77693.c
348
*state = v & FLASH_STATUS_FLASH_ON;
drivers/leds/flash/leds-max77693.c
357
unsigned int v;
drivers/leds/flash/leds-max77693.c
376
ret = regmap_read(rmap, MAX77693_LED_REG_FLASH_INT, &v);
drivers/leds/flash/leds-max77693.c
380
if (v & fault_open_mask)
drivers/leds/flash/leds-max77693.c
382
if (v & fault_short_mask)
drivers/leds/flash/leds-max77693.c
384
if (v & FLASH_INT_OVER_CURRENT)
drivers/leds/flash/leds-max77693.c
396
u8 v;
drivers/leds/flash/leds-max77693.c
422
v = TORCH_TMR_NO_TIMER | MAX77693_LED_TRIG_TYPE_LEVEL;
drivers/leds/flash/leds-max77693.c
423
ret = regmap_write(rmap, MAX77693_LED_REG_ITORCHTIMER, v);
drivers/leds/flash/leds-max77693.c
428
v = max77693_led_vsys_to_reg(led_cfg->low_vsys) |
drivers/leds/flash/leds-max77693.c
431
v = 0;
drivers/leds/flash/leds-max77693.c
433
ret = regmap_write(rmap, MAX77693_LED_REG_MAX_FLASH1, v);
drivers/leds/flash/leds-max77693.c
441
v = FLASH_BOOST_FIXED;
drivers/leds/flash/leds-max77693.c
443
v = led_cfg->boost_mode | led_cfg->boost_mode << 1;
drivers/leds/flash/leds-max77693.c
446
v |= FLASH_BOOST_LEDNUM_2;
drivers/leds/flash/leds-max77693.c
448
ret = regmap_write(rmap, MAX77693_LED_REG_VOUT_CNTL, v);
drivers/leds/flash/leds-max77693.c
452
v = max77693_led_vout_to_reg(led_cfg->boost_vout);
drivers/leds/flash/leds-max77693.c
453
ret = regmap_write(rmap, MAX77693_LED_REG_VOUT_FLASH1, v);
drivers/leds/flash/leds-max77693.c
693
static void clamp_align(u32 *v, u32 min, u32 max, u32 step)
drivers/leds/flash/leds-max77693.c
695
*v = clamp_val(*v, min, max);
drivers/leds/flash/leds-max77693.c
697
*v = (*v - min) / step * step + min;
drivers/leds/led-class-flash.c
379
u32 v, offset;
drivers/leds/led-class-flash.c
381
v = s->val + s->step / 2;
drivers/leds/led-class-flash.c
382
v = clamp(v, s->min, s->max);
drivers/leds/led-class-flash.c
383
offset = v - s->min;
drivers/leds/leds-sc27xx-bltc.c
136
u32 v, offset, t = *delta_t;
drivers/leds/leds-sc27xx-bltc.c
138
v = t + SC27XX_LEDS_STEP / 2;
drivers/leds/leds-sc27xx-bltc.c
139
v = clamp_t(u32, v, SC27XX_DELTA_T_MIN, SC27XX_DELTA_T_MAX);
drivers/leds/leds-sc27xx-bltc.c
140
offset = v - SC27XX_DELTA_T_MIN;
drivers/macintosh/mediabay.c
36
#define MB_OUT32(bay,r,v) (out_le32(MB_FCR32(bay,r), (v)))
drivers/macintosh/mediabay.c
37
#define MB_BIS(bay,r,v) (MB_OUT32((bay), (r), MB_IN32((bay), r) | (v)))
drivers/macintosh/mediabay.c
38
#define MB_BIC(bay,r,v) (MB_OUT32((bay), (r), MB_IN32((bay), r) & ~(v)))
drivers/macintosh/mediabay.c
40
#define MB_OUT8(bay,r,v) (out_8(MB_FCR8(bay,r), (v)))
drivers/macintosh/via-pmu.c
207
static int pmu_info_proc_show(struct seq_file *m, void *v);
drivers/macintosh/via-pmu.c
208
static int pmu_irqstats_proc_show(struct seq_file *m, void *v);
drivers/macintosh/via-pmu.c
209
static int pmu_battery_proc_show(struct seq_file *m, void *v);
drivers/macintosh/via-pmu.c
851
static int pmu_info_proc_show(struct seq_file *m, void *v)
drivers/macintosh/via-pmu.c
862
static int pmu_irqstats_proc_show(struct seq_file *m, void *v)
drivers/macintosh/via-pmu.c
888
static int pmu_battery_proc_show(struct seq_file *m, void *v)
drivers/macintosh/via-pmu.c
902
static int pmu_options_proc_show(struct seq_file *m, void *v)
drivers/macintosh/windfarm_smu_controls.c
161
const s32 *v;
drivers/macintosh/windfarm_smu_controls.c
232
v = of_get_property(node, "min-value", NULL);
drivers/macintosh/windfarm_smu_controls.c
233
if (v == NULL)
drivers/macintosh/windfarm_smu_controls.c
235
fct->min = *v;
drivers/macintosh/windfarm_smu_controls.c
236
v = of_get_property(node, "max-value", NULL);
drivers/macintosh/windfarm_smu_controls.c
237
if (v == NULL)
drivers/macintosh/windfarm_smu_controls.c
239
fct->max = *v;
drivers/macintosh/windfarm_smu_sensors.c
201
const u32 *v;
drivers/macintosh/windfarm_smu_sensors.c
256
v = of_get_property(node, "reg", NULL);
drivers/macintosh/windfarm_smu_sensors.c
257
if (v == NULL)
drivers/macintosh/windfarm_smu_sensors.c
259
ads->reg = *v;
drivers/mailbox/mtk-gpueb-mailbox.c
221
ebm->v = of_device_get_match_data(ebm->dev);
drivers/mailbox/mtk-gpueb-mailbox.c
243
ebm->ch = devm_kmalloc_array(ebm->dev, ebm->v->num_channels,
drivers/mailbox/mtk-gpueb-mailbox.c
248
ebm->mbox.chans = devm_kcalloc(ebm->dev, ebm->v->num_channels,
drivers/mailbox/mtk-gpueb-mailbox.c
253
for (i = 0; i < ebm->v->num_channels; i++) {
drivers/mailbox/mtk-gpueb-mailbox.c
255
ch->c = &ebm->v->channels[i];
drivers/mailbox/mtk-gpueb-mailbox.c
274
ebm->mbox.num_chans = ebm->v->num_channels;
drivers/mailbox/mtk-gpueb-mailbox.c
40
const struct mtk_gpueb_mbox_variant *v;
drivers/md/bcache/bcache_ondisk.h
15
static inline void SET_##name(type *k, __u64 v) \
drivers/md/bcache/bcache_ondisk.h
18
k->field |= (v & ~(~0ULL << size)) << offset; \
drivers/md/bcache/bcache_ondisk.h
36
static inline void SET_##name(struct bkey *k, unsigned int i, __u64 v) \
drivers/md/bcache/bcache_ondisk.h
39
k->ptr[i] |= (v & ~(~0ULL << size)) << offset; \
drivers/md/bcache/bcache_ondisk.h
61
static inline void SET_KEY_OFFSET(struct bkey *k, __u64 v)
drivers/md/bcache/bcache_ondisk.h
63
k->low = v;
drivers/md/bcache/debug.c
33
struct btree *v = b->c->verify_data;
drivers/md/bcache/debug.c
47
bkey_copy(&v->key, &b->key);
drivers/md/bcache/debug.c
48
v->written = 0;
drivers/md/bcache/debug.c
49
v->level = b->level;
drivers/md/bcache/debug.c
50
v->keys.ops = b->keys.ops;
drivers/md/bcache/debug.c
55
bio->bi_iter.bi_size = KEY_SIZE(&v->key) << 9;
drivers/md/bcache/debug.c
62
memcpy(ondisk, sorted, KEY_SIZE(&v->key) << 9);
drivers/md/bcache/debug.c
64
bch_btree_node_read_done(v);
drivers/md/bcache/debug.c
65
sorted = v->keys.set->data;
drivers/md/bcache/debug.c
81
bch_dump_bset(&v->keys, sorted, 0);
drivers/md/bcache/sysfs.c
1137
ssize_t v;
drivers/md/bcache/sysfs.c
1144
v = __sysfs_match_string(cache_replacement_policies, -1, buf);
drivers/md/bcache/sysfs.c
1145
if (v < 0)
drivers/md/bcache/sysfs.c
1146
return v;
drivers/md/bcache/sysfs.c
1148
if ((unsigned int) v != CACHE_REPLACEMENT(&ca->sb)) {
drivers/md/bcache/sysfs.c
1150
SET_CACHE_REPLACEMENT(&ca->sb, v);
drivers/md/bcache/sysfs.c
294
ssize_t v;
drivers/md/bcache/sysfs.c
319
long int v = atomic_long_read(&dc->writeback_rate.rate);
drivers/md/bcache/sysfs.c
321
ret = strtoul_safe_clamp(buf, v, 1, INT_MAX);
drivers/md/bcache/sysfs.c
324
atomic_long_set(&dc->writeback_rate.rate, v);
drivers/md/bcache/sysfs.c
357
int v = strtoul_or_return(buf);
drivers/md/bcache/sysfs.c
359
dc->io_disable = v ? 1 : 0;
drivers/md/bcache/sysfs.c
371
v = bch_cached_dev_run(dc);
drivers/md/bcache/sysfs.c
372
if (v)
drivers/md/bcache/sysfs.c
373
return v;
drivers/md/bcache/sysfs.c
377
v = __sysfs_match_string(bch_cache_modes, -1, buf);
drivers/md/bcache/sysfs.c
378
if (v < 0)
drivers/md/bcache/sysfs.c
379
return v;
drivers/md/bcache/sysfs.c
381
if ((unsigned int) v != BDEV_CACHE_MODE(&dc->sb)) {
drivers/md/bcache/sysfs.c
382
SET_BDEV_CACHE_MODE(&dc->sb, v);
drivers/md/bcache/sysfs.c
388
v = __sysfs_match_string(bch_reada_cache_policies, -1, buf);
drivers/md/bcache/sysfs.c
389
if (v < 0)
drivers/md/bcache/sysfs.c
390
return v;
drivers/md/bcache/sysfs.c
392
if ((unsigned int) v != dc->cache_readahead_policy)
drivers/md/bcache/sysfs.c
393
dc->cache_readahead_policy = v;
drivers/md/bcache/sysfs.c
397
v = __sysfs_match_string(bch_stop_on_failure_modes, -1, buf);
drivers/md/bcache/sysfs.c
398
if (v < 0)
drivers/md/bcache/sysfs.c
399
return v;
drivers/md/bcache/sysfs.c
401
dc->stop_when_cache_set_failed = v;
drivers/md/bcache/sysfs.c
436
v = -ENOENT;
drivers/md/bcache/sysfs.c
438
v = bch_cached_dev_attach(dc, c, set_uuid);
drivers/md/bcache/sysfs.c
439
if (!v)
drivers/md/bcache/sysfs.c
442
if (v == -ENOENT)
drivers/md/bcache/sysfs.c
444
return v;
drivers/md/bcache/sysfs.c
580
uint64_t v;
drivers/md/bcache/sysfs.c
582
strtoi_h_or_return(buf, v);
drivers/md/bcache/sysfs.c
584
u->sectors = v >> 9;
drivers/md/bcache/sysfs.c
814
ssize_t v;
drivers/md/bcache/sysfs.c
837
uint64_t v;
drivers/md/bcache/sysfs.c
839
strtoi_h_or_return(buf, v);
drivers/md/bcache/sysfs.c
841
r = bch_flash_dev_create(c, v);
drivers/md/bcache/sysfs.c
874
v = __sysfs_match_string(error_actions, -1, buf);
drivers/md/bcache/sysfs.c
875
if (v < 0)
drivers/md/bcache/sysfs.c
876
return v;
drivers/md/bcache/sysfs.c
878
c->on_error = v;
drivers/md/bcache/sysfs.c
885
unsigned long v = 0;
drivers/md/bcache/sysfs.c
888
ret = strtoul_safe_clamp(buf, v, 0, UINT_MAX);
drivers/md/bcache/sysfs.c
890
c->error_decay = v / 88;
drivers/md/bcache/sysfs.c
897
v = strtoul_or_return(buf);
drivers/md/bcache/sysfs.c
898
if (v) {
drivers/md/bcache/sysfs.h
101
var = v ? 1 : 0; \
drivers/md/bcache/sysfs.h
109
unsigned long v = 0; \
drivers/md/bcache/sysfs.h
111
ret = strtoul_safe_clamp(buf, v, min, max); \
drivers/md/bcache/sysfs.h
113
var = v; \
drivers/md/bcache/sysfs.h
129
#define strtoi_h_or_return(cp, v) \
drivers/md/bcache/sysfs.h
131
int _r = strtoi_h(cp, &v); \
drivers/md/bcache/sysfs.h
99
unsigned long v = strtoul_or_return(buf); \
drivers/md/bcache/util.c
100
q = -v;
drivers/md/bcache/util.c
102
q = v;
drivers/md/bcache/util.c
115
if (v < 0)
drivers/md/bcache/util.c
92
ssize_t bch_hprint(char *buf, int64_t v)
drivers/md/bcache/util.c
99
if (v < 0)
drivers/md/bcache/util.h
22
#define atomic_dec_bug(v) BUG_ON(atomic_dec_return(v) < 0)
drivers/md/bcache/util.h
23
#define atomic_inc_bug(v, i) BUG_ON(atomic_inc_return(v) <= i)
drivers/md/bcache/util.h
28
#define atomic_dec_bug(v) atomic_dec(v)
drivers/md/bcache/util.h
29
#define atomic_inc_bug(v, i) atomic_inc(v)
drivers/md/bcache/util.h
342
ssize_t bch_hprint(char *buf, int64_t v);
drivers/md/dm-cache-metadata.c
173
static void sb_prepare_for_write(const struct dm_block_validator *v,
drivers/md/dm-cache-metadata.c
198
static int sb_check(const struct dm_block_validator *v,
drivers/md/dm-clone-metadata.c
166
static void sb_prepare_for_write(const struct dm_block_validator *v,
drivers/md/dm-clone-metadata.c
180
static int sb_check(const struct dm_block_validator *v, struct dm_block *b,
drivers/md/dm-era-target.c
199
static void sb_prepare_for_write(const struct dm_block_validator *v,
drivers/md/dm-era-target.c
224
static int sb_check(const struct dm_block_validator *v,
drivers/md/dm-raid.c
317
static bool __within_range(long v, long min, long max)
drivers/md/dm-raid.c
319
return v >= min && v <= max;
drivers/md/dm-thin-metadata.c
252
static void sb_prepare_for_write(const struct dm_block_validator *v,
drivers/md/dm-thin-metadata.c
264
static int sb_check(const struct dm_block_validator *v,
drivers/md/dm-thin-metadata.c
313
static void unpack_block_time(uint64_t v, dm_block_t *b, uint32_t *t)
drivers/md/dm-thin-metadata.c
315
*b = v >> 24;
drivers/md/dm-thin-metadata.c
316
*t = v & ((1 << 24) - 1);
drivers/md/dm-verity-fec.c
108
struct bio *bio = dm_bio_from_per_bio_data(io, v->ti->per_io_data_size);
drivers/md/dm-verity-fec.c
110
par = fec_read_parity(v, rsb, block_offset, &offset,
drivers/md/dm-verity-fec.c
120
block = fec_buffer_rs_block(v, fio, n, i);
drivers/md/dm-verity-fec.c
121
for (j = 0; j < v->fec->roots - par_buf_offset; j++)
drivers/md/dm-verity-fec.c
124
res = decode_rs8(fio->rs, block, par_buf, v->fec->rsn,
drivers/md/dm-verity-fec.c
135
if (block_offset >= 1 << v->data_dev_block_bits)
drivers/md/dm-verity-fec.c
139
offset += (v->fec->roots - par_buf_offset);
drivers/md/dm-verity-fec.c
141
if (offset < v->fec->io_size && (offset + v->fec->roots) > v->fec->io_size) {
drivers/md/dm-verity-fec.c
142
par_buf_offset = v->fec->io_size - offset;
drivers/md/dm-verity-fec.c
149
if (offset >= v->fec->io_size) {
drivers/md/dm-verity-fec.c
152
par = fec_read_parity(v, rsb, block_offset, &offset,
drivers/md/dm-verity-fec.c
165
v->data_dev->name, (unsigned long long)rsb, r);
drivers/md/dm-verity-fec.c
168
v->data_dev->name, (unsigned long long)rsb, r);
drivers/md/dm-verity-fec.c
169
atomic64_inc(&v->fec->corrected);
drivers/md/dm-verity-fec.c
178
static int fec_is_erasure(struct dm_verity *v, struct dm_verity_io *io,
drivers/md/dm-verity-fec.c
181
if (unlikely(verity_hash(v, io, data, 1 << v->data_dev_block_bits,
drivers/md/dm-verity-fec.c
185
return memcmp(io->tmp_digest, want_digest, v->digest_size) != 0;
drivers/md/dm-verity-fec.c
192
static int fec_read_bufs(struct dm_verity *v, struct dm_verity_io *io,
drivers/md/dm-verity-fec.c
20
static inline unsigned int fec_max_nbufs(struct dm_verity *v)
drivers/md/dm-verity-fec.c
205
struct bio *bio = dm_bio_from_per_bio_data(io, v->ti->per_io_data_size);
drivers/md/dm-verity-fec.c
210
if (WARN_ON(v->digest_size > sizeof(want_digest)))
drivers/md/dm-verity-fec.c
217
for (i = 0; i < v->fec->rsn; i++) {
drivers/md/dm-verity-fec.c
218
ileaved = fec_interleave(v, rsb * v->fec->rsn + i);
drivers/md/dm-verity-fec.c
22
return 1 << (v->data_dev_block_bits - DM_VERITY_FEC_BUF_RS_BITS);
drivers/md/dm-verity-fec.c
227
block = ileaved >> v->data_dev_block_bits;
drivers/md/dm-verity-fec.c
228
bufio = v->fec->data_bufio;
drivers/md/dm-verity-fec.c
230
if (block >= v->data_blocks) {
drivers/md/dm-verity-fec.c
231
block -= v->data_blocks;
drivers/md/dm-verity-fec.c
237
if (unlikely(block >= v->fec->hash_blocks))
drivers/md/dm-verity-fec.c
240
block += v->hash_start;
drivers/md/dm-verity-fec.c
241
bufio = v->bufio;
drivers/md/dm-verity-fec.c
247
v->data_dev->name,
drivers/md/dm-verity-fec.c
252
if (neras && *neras <= v->fec->roots)
drivers/md/dm-verity-fec.c
259
if (bufio == v->fec->data_bufio &&
drivers/md/dm-verity-fec.c
260
verity_hash_for_block(v, io, block, want_digest,
drivers/md/dm-verity-fec.c
270
if (neras && *neras <= v->fec->roots &&
drivers/md/dm-verity-fec.c
271
fec_is_erasure(v, io, want_digest, bbuf))
drivers/md/dm-verity-fec.c
28
static inline u64 fec_interleave(struct dm_verity *v, u64 offset)
drivers/md/dm-verity-fec.c
282
if (k >= 1 << v->data_dev_block_bits)
drivers/md/dm-verity-fec.c
285
rs_block = fec_buffer_rs_block(v, fio, n, j);
drivers/md/dm-verity-fec.c
304
static struct dm_verity_fec_io *fec_alloc_and_init_io(struct dm_verity *v)
drivers/md/dm-verity-fec.c
306
const unsigned int max_nbufs = fec_max_nbufs(v);
drivers/md/dm-verity-fec.c
307
struct dm_verity_fec *f = v->fec;
drivers/md/dm-verity-fec.c
32
mod = do_div(offset, v->fec->rsn);
drivers/md/dm-verity-fec.c
33
return offset + mod * (v->fec->rounds << v->data_dev_block_bits);
drivers/md/dm-verity-fec.c
334
static void fec_init_bufs(struct dm_verity *v, struct dm_verity_fec_io *fio)
drivers/md/dm-verity-fec.c
339
memset(fio->bufs[n], 0, v->fec->rsn << DM_VERITY_FEC_BUF_RS_BITS);
drivers/md/dm-verity-fec.c
349
static int fec_decode_rsb(struct dm_verity *v, struct dm_verity_io *io,
drivers/md/dm-verity-fec.c
356
for (pos = 0; pos < 1 << v->data_dev_block_bits; ) {
drivers/md/dm-verity-fec.c
357
fec_init_bufs(v, fio);
drivers/md/dm-verity-fec.c
359
r = fec_read_bufs(v, io, rsb, offset, pos,
drivers/md/dm-verity-fec.c
364
r = fec_decode_bufs(v, io, fio, rsb, r, pos, neras);
drivers/md/dm-verity-fec.c
372
r = verity_hash(v, io, fio->output, 1 << v->data_dev_block_bits,
drivers/md/dm-verity-fec.c
377
if (memcmp(io->tmp_digest, want_digest, v->digest_size)) {
drivers/md/dm-verity-fec.c
379
v->data_dev->name, (unsigned long long)rsb, neras);
drivers/md/dm-verity-fec.c
387
int verity_fec_decode(struct dm_verity *v, struct dm_verity_io *io,
drivers/md/dm-verity-fec.c
395
if (!verity_fec_is_enabled(v))
drivers/md/dm-verity-fec.c
40
static u8 *fec_read_parity(struct dm_verity *v, u64 rsb, int index,
drivers/md/dm-verity-fec.c
400
fio = io->fec_io = fec_alloc_and_init_io(v);
drivers/md/dm-verity-fec.c
408
block = block - v->hash_start + v->data_blocks;
drivers/md/dm-verity-fec.c
420
offset = block << v->data_dev_block_bits;
drivers/md/dm-verity-fec.c
421
res = div64_u64(offset, v->fec->rounds << v->data_dev_block_bits);
drivers/md/dm-verity-fec.c
427
rsb = offset - res * (v->fec->rounds << v->data_dev_block_bits);
drivers/md/dm-verity-fec.c
434
r = fec_decode_rsb(v, io, fio, rsb, offset, want_digest, false);
drivers/md/dm-verity-fec.c
436
r = fec_decode_rsb(v, io, fio, rsb, offset, want_digest, true);
drivers/md/dm-verity-fec.c
441
memcpy(dest, fio->output, 1 << v->data_dev_block_bits);
drivers/md/dm-verity-fec.c
454
struct dm_verity_fec *f = io->v->fec;
drivers/md/dm-verity-fec.c
473
unsigned int verity_fec_status_table(struct dm_verity *v, unsigned int sz,
drivers/md/dm-verity-fec.c
476
if (!verity_fec_is_enabled(v))
drivers/md/dm-verity-fec.c
483
v->fec->dev->name,
drivers/md/dm-verity-fec.c
484
(unsigned long long)v->fec->blocks,
drivers/md/dm-verity-fec.c
485
(unsigned long long)v->fec->start,
drivers/md/dm-verity-fec.c
486
v->fec->roots);
drivers/md/dm-verity-fec.c
491
void verity_fec_dtr(struct dm_verity *v)
drivers/md/dm-verity-fec.c
493
struct dm_verity_fec *f = v->fec;
drivers/md/dm-verity-fec.c
495
if (!verity_fec_is_enabled(v))
drivers/md/dm-verity-fec.c
51
position = (index + rsb) * v->fec->roots;
drivers/md/dm-verity-fec.c
510
dm_put_device(v->ti, f->dev);
drivers/md/dm-verity-fec.c
513
v->fec = NULL;
drivers/md/dm-verity-fec.c
518
struct dm_verity *v = pool_data;
drivers/md/dm-verity-fec.c
52
block = div64_u64_rem(position, v->fec->io_size, &rem);
drivers/md/dm-verity-fec.c
520
return init_rs_gfp(8, 0x11d, 0, 1, v->fec->roots, gfp_mask);
drivers/md/dm-verity-fec.c
539
int verity_fec_parse_opt_args(struct dm_arg_set *as, struct dm_verity *v,
drivers/md/dm-verity-fec.c
543
struct dm_target *ti = v->ti;
drivers/md/dm-verity-fec.c
55
res = dm_bufio_read_with_ioprio(v->fec->bufio, block, buf, ioprio);
drivers/md/dm-verity-fec.c
558
if (v->fec->dev) {
drivers/md/dm-verity-fec.c
562
r = dm_get_device(ti, arg_value, BLK_OPEN_READ, &v->fec->dev);
drivers/md/dm-verity-fec.c
570
((sector_t)(num_ll << (v->data_dev_block_bits - SECTOR_SHIFT))
drivers/md/dm-verity-fec.c
571
>> (v->data_dev_block_bits - SECTOR_SHIFT) != num_ll)) {
drivers/md/dm-verity-fec.c
575
v->fec->blocks = num_ll;
drivers/md/dm-verity-fec.c
579
((sector_t)(num_ll << (v->data_dev_block_bits - SECTOR_SHIFT)) >>
drivers/md/dm-verity-fec.c
58
v->data_dev->name, (unsigned long long)rsb,
drivers/md/dm-verity-fec.c
580
(v->data_dev_block_bits - SECTOR_SHIFT) != num_ll)) {
drivers/md/dm-verity-fec.c
584
v->fec->start = num_ll;
drivers/md/dm-verity-fec.c
593
v->fec->roots = num_c;
drivers/md/dm-verity-fec.c
606
int verity_fec_ctr_alloc(struct dm_verity *v)
drivers/md/dm-verity-fec.c
612
v->ti->error = "Cannot allocate FEC structure";
drivers/md/dm-verity-fec.c
615
v->fec = f;
drivers/md/dm-verity-fec.c
624
int verity_fec_ctr(struct dm_verity *v)
drivers/md/dm-verity-fec.c
626
struct dm_verity_fec *f = v->fec;
drivers/md/dm-verity-fec.c
627
struct dm_target *ti = v->ti;
drivers/md/dm-verity-fec.c
631
if (!verity_fec_is_enabled(v)) {
drivers/md/dm-verity-fec.c
632
verity_fec_dtr(v);
drivers/md/dm-verity-fec.c
651
hash_blocks = v->hash_blocks - v->hash_start;
drivers/md/dm-verity-fec.c
657
if (v->data_dev_block_bits != v->hash_dev_block_bits) {
drivers/md/dm-verity-fec.c
681
if (f->blocks < v->data_blocks + hash_blocks || !f->rounds) {
drivers/md/dm-verity-fec.c
690
f->hash_blocks = f->blocks - v->data_blocks;
drivers/md/dm-verity-fec.c
691
if (dm_bufio_get_device_size(v->bufio) < f->hash_blocks) {
drivers/md/dm-verity-fec.c
697
f->io_size = 1 << v->data_dev_block_bits;
drivers/md/dm-verity-fec.c
707
dm_bufio_set_sector_offset(f->bufio, f->start << (v->data_dev_block_bits - SECTOR_SHIFT));
drivers/md/dm-verity-fec.c
709
fec_blocks = div64_u64(f->rounds * f->roots, v->fec->roots << SECTOR_SHIFT);
drivers/md/dm-verity-fec.c
715
f->data_bufio = dm_bufio_client_create(v->data_dev->bdev,
drivers/md/dm-verity-fec.c
716
1 << v->data_dev_block_bits,
drivers/md/dm-verity-fec.c
723
if (dm_bufio_get_device_size(f->data_bufio) < v->data_blocks) {
drivers/md/dm-verity-fec.c
731
bufs, fec_max_nbufs(v)));
drivers/md/dm-verity-fec.c
739
fec_rs_free, (void *) v);
drivers/md/dm-verity-fec.c
763
1 << v->data_dev_block_bits);
drivers/md/dm-verity-fec.c
79
static inline u8 *fec_buffer_rs_block(struct dm_verity *v,
drivers/md/dm-verity-fec.c
83
return &fio->bufs[i][j * v->fec->rsn];
drivers/md/dm-verity-fec.c
99
static int fec_decode_bufs(struct dm_verity *v, struct dm_verity_io *io,
drivers/md/dm-verity-fec.h
101
extern int verity_fec_ctr_alloc(struct dm_verity *v);
drivers/md/dm-verity-fec.h
102
extern int verity_fec_ctr(struct dm_verity *v);
drivers/md/dm-verity-fec.h
108
static inline bool verity_fec_is_enabled(struct dm_verity *v)
drivers/md/dm-verity-fec.h
113
static inline int verity_fec_decode(struct dm_verity *v,
drivers/md/dm-verity-fec.h
122
static inline unsigned int verity_fec_status_table(struct dm_verity *v,
drivers/md/dm-verity-fec.h
143
struct dm_verity *v,
drivers/md/dm-verity-fec.h
150
static inline void verity_fec_dtr(struct dm_verity *v)
drivers/md/dm-verity-fec.h
154
static inline int verity_fec_ctr_alloc(struct dm_verity *v)
drivers/md/dm-verity-fec.h
159
static inline int verity_fec_ctr(struct dm_verity *v)
drivers/md/dm-verity-fec.h
70
static inline bool verity_fec_is_enabled(struct dm_verity *v)
drivers/md/dm-verity-fec.h
72
return v->fec && v->fec->dev;
drivers/md/dm-verity-fec.h
75
extern int verity_fec_decode(struct dm_verity *v, struct dm_verity_io *io,
drivers/md/dm-verity-fec.h
79
extern unsigned int verity_fec_status_table(struct dm_verity *v, unsigned int sz,
drivers/md/dm-verity-fec.h
96
struct dm_verity *v, unsigned int *argc,
drivers/md/dm-verity-fec.h
99
extern void verity_fec_dtr(struct dm_verity *v);
drivers/md/dm-verity-target.c
1005
struct dm_verity *v = ti->private;
drivers/md/dm-verity-target.c
1007
return fn(ti, v->data_dev, 0, ti->len, data);
drivers/md/dm-verity-target.c
101
static sector_t verity_map_sector(struct dm_verity *v, sector_t bi_sector)
drivers/md/dm-verity-target.c
1012
struct dm_verity *v = ti->private;
drivers/md/dm-verity-target.c
1014
if (limits->logical_block_size < 1 << v->data_dev_block_bits)
drivers/md/dm-verity-target.c
1015
limits->logical_block_size = 1 << v->data_dev_block_bits;
drivers/md/dm-verity-target.c
1017
if (limits->physical_block_size < 1 << v->data_dev_block_bits)
drivers/md/dm-verity-target.c
1018
limits->physical_block_size = 1 << v->data_dev_block_bits;
drivers/md/dm-verity-target.c
103
return dm_target_offset(v->ti, bi_sector);
drivers/md/dm-verity-target.c
1033
static int verity_init_sig(struct dm_verity *v, const void *sig,
drivers/md/dm-verity-target.c
1036
v->sig_size = sig_size;
drivers/md/dm-verity-target.c
1039
v->root_digest_sig = kmemdup(sig, v->sig_size, GFP_KERNEL);
drivers/md/dm-verity-target.c
1040
if (!v->root_digest_sig)
drivers/md/dm-verity-target.c
1047
static void verity_free_sig(struct dm_verity *v)
drivers/md/dm-verity-target.c
1049
kfree(v->root_digest_sig);
drivers/md/dm-verity-target.c
1054
static inline int verity_init_sig(struct dm_verity *v, const void *sig,
drivers/md/dm-verity-target.c
1060
static inline void verity_free_sig(struct dm_verity *v)
drivers/md/dm-verity-target.c
1068
struct dm_verity *v = ti->private;
drivers/md/dm-verity-target.c
1070
if (v->verify_wq)
drivers/md/dm-verity-target.c
1071
destroy_workqueue(v->verify_wq);
drivers/md/dm-verity-target.c
1073
mempool_exit(&v->recheck_pool);
drivers/md/dm-verity-target.c
1074
if (v->io)
drivers/md/dm-verity-target.c
1075
dm_io_client_destroy(v->io);
drivers/md/dm-verity-target.c
1077
if (v->bufio)
drivers/md/dm-verity-target.c
1078
dm_bufio_client_destroy(v->bufio);
drivers/md/dm-verity-target.c
1080
kvfree(v->validated_blocks);
drivers/md/dm-verity-target.c
1081
kfree(v->salt);
drivers/md/dm-verity-target.c
1082
kfree(v->initial_hashstate.shash);
drivers/md/dm-verity-target.c
1083
kfree(v->root_digest);
drivers/md/dm-verity-target.c
1084
kfree(v->zero_digest);
drivers/md/dm-verity-target.c
1085
verity_free_sig(v);
drivers/md/dm-verity-target.c
1087
crypto_free_shash(v->shash_tfm);
drivers/md/dm-verity-target.c
1089
kfree(v->alg_name);
drivers/md/dm-verity-target.c
1091
if (v->hash_dev)
drivers/md/dm-verity-target.c
1092
dm_put_device(ti, v->hash_dev);
drivers/md/dm-verity-target.c
1094
if (v->data_dev)
drivers/md/dm-verity-target.c
1095
dm_put_device(ti, v->data_dev);
drivers/md/dm-verity-target.c
1097
verity_fec_dtr(v);
drivers/md/dm-verity-target.c
1099
kfree(v->signature_key_desc);
drivers/md/dm-verity-target.c
1101
if (v->use_bh_wq)
drivers/md/dm-verity-target.c
1104
kfree(v);
drivers/md/dm-verity-target.c
1109
static int verity_alloc_most_once(struct dm_verity *v)
drivers/md/dm-verity-target.c
1111
struct dm_target *ti = v->ti;
drivers/md/dm-verity-target.c
1113
if (v->validated_blocks)
drivers/md/dm-verity-target.c
1117
if (v->data_blocks > INT_MAX) {
drivers/md/dm-verity-target.c
112
static sector_t verity_position_at_level(struct dm_verity *v, sector_t block,
drivers/md/dm-verity-target.c
1122
v->validated_blocks = kvcalloc(BITS_TO_LONGS(v->data_blocks),
drivers/md/dm-verity-target.c
1125
if (!v->validated_blocks) {
drivers/md/dm-verity-target.c
1133
static int verity_alloc_zero_digest(struct dm_verity *v)
drivers/md/dm-verity-target.c
1139
if (v->zero_digest)
drivers/md/dm-verity-target.c
1142
v->zero_digest = kmalloc(v->digest_size, GFP_KERNEL);
drivers/md/dm-verity-target.c
1144
if (!v->zero_digest)
drivers/md/dm-verity-target.c
1147
io = kmalloc(v->ti->per_io_data_size, GFP_KERNEL);
drivers/md/dm-verity-target.c
115
return block >> (level * v->hash_per_block_bits);
drivers/md/dm-verity-target.c
1152
zero_data = kzalloc(1 << v->data_dev_block_bits, GFP_KERNEL);
drivers/md/dm-verity-target.c
1157
r = verity_hash(v, io, zero_data, 1 << v->data_dev_block_bits,
drivers/md/dm-verity-target.c
1158
v->zero_digest);
drivers/md/dm-verity-target.c
1174
static int verity_parse_verity_mode(struct dm_verity *v, const char *arg_name)
drivers/md/dm-verity-target.c
1176
if (v->mode)
drivers/md/dm-verity-target.c
118
int verity_hash(struct dm_verity *v, struct dm_verity_io *io,
drivers/md/dm-verity-target.c
1180
v->mode = DM_VERITY_MODE_LOGGING;
drivers/md/dm-verity-target.c
1182
v->mode = DM_VERITY_MODE_RESTART;
drivers/md/dm-verity-target.c
1184
v->mode = DM_VERITY_MODE_PANIC;
drivers/md/dm-verity-target.c
1195
static int verity_parse_verity_error_mode(struct dm_verity *v, const char *arg_name)
drivers/md/dm-verity-target.c
1197
if (v->error_mode)
drivers/md/dm-verity-target.c
1201
v->error_mode = DM_VERITY_MODE_RESTART;
drivers/md/dm-verity-target.c
1203
v->error_mode = DM_VERITY_MODE_PANIC;
drivers/md/dm-verity-target.c
1208
static int verity_parse_opt_args(struct dm_arg_set *as, struct dm_verity *v,
drivers/md/dm-verity-target.c
1214
struct dm_target *ti = v->ti;
drivers/md/dm-verity-target.c
1235
r = verity_parse_verity_mode(v, arg_name);
drivers/md/dm-verity-target.c
124
if (likely(v->use_sha256_lib)) {
drivers/md/dm-verity-target.c
1245
r = verity_parse_verity_error_mode(v, arg_name);
drivers/md/dm-verity-target.c
1255
r = verity_alloc_zero_digest(v);
drivers/md/dm-verity-target.c
1265
r = verity_alloc_most_once(v);
drivers/md/dm-verity-target.c
1271
v->use_bh_wq = true;
drivers/md/dm-verity-target.c
1278
r = verity_fec_parse_opt_args(as, v, &argc, arg_name);
drivers/md/dm-verity-target.c
1286
r = verity_verify_sig_parse_opt_args(as, v,
drivers/md/dm-verity-target.c
131
*ctx = *v->initial_hashstate.sha256;
drivers/md/dm-verity-target.c
1311
static int verity_setup_hash_alg(struct dm_verity *v, const char *alg_name)
drivers/md/dm-verity-target.c
1313
struct dm_target *ti = v->ti;
drivers/md/dm-verity-target.c
1316
v->alg_name = kstrdup(alg_name, GFP_KERNEL);
drivers/md/dm-verity-target.c
1317
if (!v->alg_name) {
drivers/md/dm-verity-target.c
1327
v->shash_tfm = shash;
drivers/md/dm-verity-target.c
1328
v->digest_size = crypto_shash_digestsize(shash);
drivers/md/dm-verity-target.c
1329
if ((1 << v->hash_dev_block_bits) < v->digest_size * 2) {
drivers/md/dm-verity-target.c
1333
if (likely(v->version && strcmp(alg_name, "sha256") == 0)) {
drivers/md/dm-verity-target.c
1338
v->use_sha256_lib = true;
drivers/md/dm-verity-target.c
1340
v->use_sha256_finup_2x = true;
drivers/md/dm-verity-target.c
1352
static int verity_setup_salt_and_hashstate(struct dm_verity *v, const char *arg)
drivers/md/dm-verity-target.c
1354
struct dm_target *ti = v->ti;
drivers/md/dm-verity-target.c
1357
v->salt_size = strlen(arg) / 2;
drivers/md/dm-verity-target.c
1358
v->salt = kmalloc(v->salt_size, GFP_KERNEL);
drivers/md/dm-verity-target.c
1359
if (!v->salt) {
drivers/md/dm-verity-target.c
1363
if (strlen(arg) != v->salt_size * 2 ||
drivers/md/dm-verity-target.c
1364
hex2bin(v->salt, arg, v->salt_size)) {
drivers/md/dm-verity-target.c
1369
if (likely(v->use_sha256_lib)) {
drivers/md/dm-verity-target.c
1371
v->initial_hashstate.sha256 =
drivers/md/dm-verity-target.c
1373
if (!v->initial_hashstate.sha256) {
drivers/md/dm-verity-target.c
1377
sha256_init(v->initial_hashstate.sha256);
drivers/md/dm-verity-target.c
1378
sha256_update(v->initial_hashstate.sha256,
drivers/md/dm-verity-target.c
1379
v->salt, v->salt_size);
drivers/md/dm-verity-target.c
138
desc->tfm = v->shash_tfm;
drivers/md/dm-verity-target.c
1380
} else if (v->version) { /* Version 1: salt at beginning */
drivers/md/dm-verity-target.c
1381
SHASH_DESC_ON_STACK(desc, v->shash_tfm);
drivers/md/dm-verity-target.c
1388
v->initial_hashstate.shash = kmalloc(
drivers/md/dm-verity-target.c
1389
crypto_shash_statesize(v->shash_tfm), GFP_KERNEL);
drivers/md/dm-verity-target.c
139
if (unlikely(v->initial_hashstate.shash == NULL)) {
drivers/md/dm-verity-target.c
1390
if (!v->initial_hashstate.shash) {
drivers/md/dm-verity-target.c
1394
desc->tfm = v->shash_tfm;
drivers/md/dm-verity-target.c
1396
crypto_shash_update(desc, v->salt, v->salt_size) ?:
drivers/md/dm-verity-target.c
1397
crypto_shash_export(desc, v->initial_hashstate.shash);
drivers/md/dm-verity-target.c
1422
struct dm_verity *v;
drivers/md/dm-verity-target.c
143
crypto_shash_update(desc, v->salt, v->salt_size) ?:
drivers/md/dm-verity-target.c
1433
v = kzalloc_obj(struct dm_verity);
drivers/md/dm-verity-target.c
1434
if (!v) {
drivers/md/dm-verity-target.c
1438
ti->private = v;
drivers/md/dm-verity-target.c
1439
v->ti = ti;
drivers/md/dm-verity-target.c
1441
r = verity_fec_ctr_alloc(v);
drivers/md/dm-verity-target.c
1461
r = verity_parse_opt_args(&as, v, &verify_args, true);
drivers/md/dm-verity-target.c
147
r = crypto_shash_import(desc, v->initial_hashstate.shash) ?:
drivers/md/dm-verity-target.c
1472
v->version = num;
drivers/md/dm-verity-target.c
1474
r = dm_get_device(ti, argv[1], BLK_OPEN_READ, &v->data_dev);
drivers/md/dm-verity-target.c
1480
r = dm_get_device(ti, argv[2], BLK_OPEN_READ, &v->hash_dev);
drivers/md/dm-verity-target.c
1488
num < bdev_logical_block_size(v->data_dev->bdev) ||
drivers/md/dm-verity-target.c
1494
v->data_dev_block_bits = __ffs(num);
drivers/md/dm-verity-target.c
1498
num < bdev_logical_block_size(v->hash_dev->bdev) ||
drivers/md/dm-verity-target.c
1504
v->hash_dev_block_bits = __ffs(num);
drivers/md/dm-verity-target.c
1507
(sector_t)(num_ll << (v->data_dev_block_bits - SECTOR_SHIFT))
drivers/md/dm-verity-target.c
1508
>> (v->data_dev_block_bits - SECTOR_SHIFT) != num_ll) {
drivers/md/dm-verity-target.c
1513
v->data_blocks = num_ll;
drivers/md/dm-verity-target.c
1515
if (ti->len > (v->data_blocks << (v->data_dev_block_bits - SECTOR_SHIFT))) {
drivers/md/dm-verity-target.c
1522
(sector_t)(num_ll << (v->hash_dev_block_bits - SECTOR_SHIFT))
drivers/md/dm-verity-target.c
1523
>> (v->hash_dev_block_bits - SECTOR_SHIFT) != num_ll) {
drivers/md/dm-verity-target.c
1528
v->hash_start = num_ll;
drivers/md/dm-verity-target.c
1530
r = verity_setup_hash_alg(v, argv[7]);
drivers/md/dm-verity-target.c
1534
v->root_digest = kmalloc(v->digest_size, GFP_KERNEL);
drivers/md/dm-verity-target.c
1535
if (!v->root_digest) {
drivers/md/dm-verity-target.c
1540
if (strlen(argv[8]) != v->digest_size * 2 ||
drivers/md/dm-verity-target.c
1541
hex2bin(v->root_digest, argv[8], v->digest_size)) {
drivers/md/dm-verity-target.c
1548
r = verity_setup_salt_and_hashstate(v, argv[9]);
drivers/md/dm-verity-target.c
155
static void verity_hash_at_level(struct dm_verity *v, sector_t block, int level,
drivers/md/dm-verity-target.c
1559
r = verity_parse_opt_args(&as, v, &verify_args, false);
drivers/md/dm-verity-target.c
1574
r = verity_init_sig(v, verify_args.sig, verify_args.sig_size);
drivers/md/dm-verity-target.c
158
sector_t position = verity_position_at_level(v, block, level);
drivers/md/dm-verity-target.c
1580
v->hash_per_block_bits =
drivers/md/dm-verity-target.c
1581
__fls((1 << v->hash_dev_block_bits) / v->digest_size);
drivers/md/dm-verity-target.c
1583
v->levels = 0;
drivers/md/dm-verity-target.c
1584
if (v->data_blocks)
drivers/md/dm-verity-target.c
1585
while (v->hash_per_block_bits * v->levels < 64 &&
drivers/md/dm-verity-target.c
1586
(unsigned long long)(v->data_blocks - 1) >>
drivers/md/dm-verity-target.c
1587
(v->hash_per_block_bits * v->levels))
drivers/md/dm-verity-target.c
1588
v->levels++;
drivers/md/dm-verity-target.c
1590
if (v->levels > DM_VERITY_MAX_LEVELS) {
drivers/md/dm-verity-target.c
1596
hash_position = v->hash_start;
drivers/md/dm-verity-target.c
1597
for (i = v->levels - 1; i >= 0; i--) {
drivers/md/dm-verity-target.c
1600
v->hash_level_block[i] = hash_position;
drivers/md/dm-verity-target.c
1601
s = (v->data_blocks + ((sector_t)1 << ((i + 1) * v->hash_per_block_bits)) - 1)
drivers/md/dm-verity-target.c
1602
>> ((i + 1) * v->hash_per_block_bits);
drivers/md/dm-verity-target.c
161
*hash_block = v->hash_level_block[level] + (position >> v->hash_per_block_bits);
drivers/md/dm-verity-target.c
1610
v->hash_blocks = hash_position;
drivers/md/dm-verity-target.c
1612
r = mempool_init_page_pool(&v->recheck_pool, 1, 0);
drivers/md/dm-verity-target.c
1618
v->io = dm_io_client_create();
drivers/md/dm-verity-target.c
1619
if (IS_ERR(v->io)) {
drivers/md/dm-verity-target.c
1620
r = PTR_ERR(v->io);
drivers/md/dm-verity-target.c
1621
v->io = NULL;
drivers/md/dm-verity-target.c
1626
v->bufio = dm_bufio_client_create(v->hash_dev->bdev,
drivers/md/dm-verity-target.c
1627
1 << v->hash_dev_block_bits, 1, sizeof(struct buffer_aux),
drivers/md/dm-verity-target.c
1629
v->use_bh_wq ? DM_BUFIO_CLIENT_NO_SLEEP : 0);
drivers/md/dm-verity-target.c
1630
if (IS_ERR(v->bufio)) {
drivers/md/dm-verity-target.c
1632
r = PTR_ERR(v->bufio);
drivers/md/dm-verity-target.c
1633
v->bufio = NULL;
drivers/md/dm-verity-target.c
1637
if (dm_bufio_get_device_size(v->bufio) < v->hash_blocks) {
drivers/md/dm-verity-target.c
1652
v->verify_wq = alloc_workqueue("kverityd",
drivers/md/dm-verity-target.c
1655
if (!v->verify_wq) {
drivers/md/dm-verity-target.c
166
idx = position & ((1 << v->hash_per_block_bits) - 1);
drivers/md/dm-verity-target.c
1661
r = verity_fec_ctr(v);
drivers/md/dm-verity-target.c
167
if (!v->version)
drivers/md/dm-verity-target.c
168
*offset = idx * v->digest_size;
drivers/md/dm-verity-target.c
1691
struct dm_verity *v = ti->private;
drivers/md/dm-verity-target.c
1696
return v->mode;
drivers/md/dm-verity-target.c
170
*offset = idx << (v->hash_dev_block_bits - v->hash_per_block_bits);
drivers/md/dm-verity-target.c
1707
struct dm_verity *v = ti->private;
drivers/md/dm-verity-target.c
1712
*root_digest = kmemdup(v->root_digest, v->digest_size, GFP_KERNEL);
drivers/md/dm-verity-target.c
1716
*digest_size = v->digest_size;
drivers/md/dm-verity-target.c
1726
struct dm_verity *v)
drivers/md/dm-verity-target.c
1736
v->root_digest_sig,
drivers/md/dm-verity-target.c
1737
v->sig_size);
drivers/md/dm-verity-target.c
1743
struct dm_verity *v)
drivers/md/dm-verity-target.c
1759
struct dm_verity *v;
drivers/md/dm-verity-target.c
176
static int verity_handle_err(struct dm_verity *v, enum verity_block_type type,
drivers/md/dm-verity-target.c
1762
v = ti->private;
drivers/md/dm-verity-target.c
1764
root_digest.digest = v->root_digest;
drivers/md/dm-verity-target.c
1765
root_digest.digest_len = v->digest_size;
drivers/md/dm-verity-target.c
1766
root_digest.alg = crypto_shash_alg_name(v->shash_tfm);
drivers/md/dm-verity-target.c
1773
r = verity_security_set_signature(bdev, v);
drivers/md/dm-verity-target.c
182
struct mapped_device *md = dm_table_get_md(v->ti->table);
drivers/md/dm-verity-target.c
185
v->hash_failed = true;
drivers/md/dm-verity-target.c
187
if (v->corrupted_errs >= DM_VERITY_MAX_CORRUPTED_ERRS)
drivers/md/dm-verity-target.c
190
v->corrupted_errs++;
drivers/md/dm-verity-target.c
203
DMERR_LIMIT("%s: %s block %llu is corrupted", v->data_dev->name,
drivers/md/dm-verity-target.c
206
if (v->corrupted_errs == DM_VERITY_MAX_CORRUPTED_ERRS) {
drivers/md/dm-verity-target.c
207
DMERR("%s: reached maximum errors", v->data_dev->name);
drivers/md/dm-verity-target.c
208
dm_audit_log_target(DM_MSG_PREFIX, "max-corrupted-errors", v->ti, 0);
drivers/md/dm-verity-target.c
217
if (v->mode == DM_VERITY_MODE_LOGGING)
drivers/md/dm-verity-target.c
220
if (v->mode == DM_VERITY_MODE_RESTART)
drivers/md/dm-verity-target.c
223
if (v->mode == DM_VERITY_MODE_PANIC)
drivers/md/dm-verity-target.c
240
static int verity_verify_level(struct dm_verity *v, struct dm_verity_io *io,
drivers/md/dm-verity-target.c
250
struct bio *bio = dm_bio_from_per_bio_data(io, v->ti->per_io_data_size);
drivers/md/dm-verity-target.c
252
verity_hash_at_level(v, block, level, &hash_block, &offset);
drivers/md/dm-verity-target.c
255
data = dm_bufio_get(v->bufio, hash_block, &buf);
drivers/md/dm-verity-target.c
265
data = dm_bufio_read_with_ioprio(v->bufio, hash_block,
drivers/md/dm-verity-target.c
273
data = dm_bufio_new(v->bufio, hash_block, &buf);
drivers/md/dm-verity-target.c
276
if (verity_fec_decode(v, io, DM_VERITY_BLOCK_TYPE_METADATA,
drivers/md/dm-verity-target.c
283
dm_bufio_forget(v->bufio, hash_block);
drivers/md/dm-verity-target.c
296
r = verity_hash(v, io, data, 1 << v->hash_dev_block_bits,
drivers/md/dm-verity-target.c
302
v->digest_size) == 0))
drivers/md/dm-verity-target.c
311
} else if (verity_fec_decode(v, io, DM_VERITY_BLOCK_TYPE_METADATA,
drivers/md/dm-verity-target.c
314
else if (verity_handle_err(v,
drivers/md/dm-verity-target.c
319
bio = dm_bio_from_per_bio_data(io, v->ti->per_io_data_size);
drivers/md/dm-verity-target.c
329
memcpy(want_digest, data, v->digest_size);
drivers/md/dm-verity-target.c
341
int verity_hash_for_block(struct dm_verity *v, struct dm_verity_io *io,
drivers/md/dm-verity-target.c
346
if (likely(v->levels)) {
drivers/md/dm-verity-target.c
354
r = verity_verify_level(v, io, block, 0, true, digest);
drivers/md/dm-verity-target.c
359
memcpy(digest, v->root_digest, v->digest_size);
drivers/md/dm-verity-target.c
361
for (i = v->levels - 1; i >= 0; i--) {
drivers/md/dm-verity-target.c
362
r = verity_verify_level(v, io, block, i, false, digest);
drivers/md/dm-verity-target.c
367
if (!r && v->zero_digest)
drivers/md/dm-verity-target.c
368
*is_zero = !memcmp(v->zero_digest, digest, v->digest_size);
drivers/md/dm-verity-target.c
375
static noinline int verity_recheck(struct dm_verity *v, struct dm_verity_io *io,
drivers/md/dm-verity-target.c
385
page = mempool_alloc(&v->recheck_pool, GFP_NOIO);
drivers/md/dm-verity-target.c
392
io_req.client = v->io;
drivers/md/dm-verity-target.c
393
io_loc.bdev = v->data_dev->bdev;
drivers/md/dm-verity-target.c
394
io_loc.sector = cur_block << (v->data_dev_block_bits - SECTOR_SHIFT);
drivers/md/dm-verity-target.c
395
io_loc.count = 1 << (v->data_dev_block_bits - SECTOR_SHIFT);
drivers/md/dm-verity-target.c
400
r = verity_hash(v, io, buffer, 1 << v->data_dev_block_bits,
drivers/md/dm-verity-target.c
405
if (memcmp(io->tmp_digest, want_digest, v->digest_size)) {
drivers/md/dm-verity-target.c
410
memcpy(dest, buffer, 1 << v->data_dev_block_bits);
drivers/md/dm-verity-target.c
413
mempool_free(page, &v->recheck_pool);
drivers/md/dm-verity-target.c
418
static int verity_handle_data_hash_mismatch(struct dm_verity *v,
drivers/md/dm-verity-target.c
434
if (verity_recheck(v, io, want_digest, blkno, data) == 0) {
drivers/md/dm-verity-target.c
435
if (v->validated_blocks)
drivers/md/dm-verity-target.c
436
set_bit(blkno, v->validated_blocks);
drivers/md/dm-verity-target.c
439
if (verity_fec_decode(v, io, DM_VERITY_BLOCK_TYPE_DATA, want_digest,
drivers/md/dm-verity-target.c
445
if (verity_handle_err(v, DM_VERITY_BLOCK_TYPE_DATA, blkno)) {
drivers/md/dm-verity-target.c
464
static int verity_verify_pending_blocks(struct dm_verity *v,
drivers/md/dm-verity-target.c
468
const unsigned int block_size = 1 << v->data_dev_block_bits;
drivers/md/dm-verity-target.c
473
sha256_finup_2x(v->initial_hashstate.sha256,
drivers/md/dm-verity-target.c
480
r = verity_hash(v, io, io->pending_blocks[i].data,
drivers/md/dm-verity-target.c
492
v->digest_size) == 0)) {
drivers/md/dm-verity-target.c
493
if (v->validated_blocks)
drivers/md/dm-verity-target.c
494
set_bit(block->blkno, v->validated_blocks);
drivers/md/dm-verity-target.c
496
r = verity_handle_data_hash_mismatch(v, io, bio, block);
drivers/md/dm-verity-target.c
510
struct dm_verity *v = io->v;
drivers/md/dm-verity-target.c
511
const unsigned int block_size = 1 << v->data_dev_block_bits;
drivers/md/dm-verity-target.c
512
const int max_pending = v->use_sha256_finup_2x ? 2 : 1;
drivers/md/dm-verity-target.c
515
struct bio *bio = dm_bio_from_per_bio_data(io, v->ti->per_io_data_size);
drivers/md/dm-verity-target.c
539
if (v->validated_blocks && bio->bi_status == BLK_STS_OK &&
drivers/md/dm-verity-target.c
540
likely(test_bit(blkno, v->validated_blocks)))
drivers/md/dm-verity-target.c
545
r = verity_hash_for_block(v, io, blkno, block->want_digest,
drivers/md/dm-verity-target.c
577
r = verity_verify_pending_blocks(v, io, bio);
drivers/md/dm-verity-target.c
584
r = verity_verify_pending_blocks(v, io, bio);
drivers/md/dm-verity-target.c
615
struct dm_verity *v = io->v;
drivers/md/dm-verity-target.c
616
struct bio *bio = dm_bio_from_per_bio_data(io, v->ti->per_io_data_size);
drivers/md/dm-verity-target.c
627
if (v->error_mode == DM_VERITY_MODE_PANIC) {
drivers/md/dm-verity-target.c
630
if (v->error_mode == DM_VERITY_MODE_RESTART) {
drivers/md/dm-verity-target.c
632
queue_work(v->verify_wq, &restart_work);
drivers/md/dm-verity-target.c
66
struct dm_verity *v;
drivers/md/dm-verity-target.c
663
queue_work(io->v->verify_wq, &io->work);
drivers/md/dm-verity-target.c
681
unsigned int bytes = io->n_blocks << io->v->data_dev_block_bits;
drivers/md/dm-verity-target.c
684
(!verity_fec_is_enabled(io->v) ||
drivers/md/dm-verity-target.c
691
if (static_branch_unlikely(&use_bh_wq_enabled) && io->v->use_bh_wq &&
drivers/md/dm-verity-target.c
701
queue_work(io->v->verify_wq, &io->work);
drivers/md/dm-verity-target.c
714
struct dm_verity *v = pw->v;
drivers/md/dm-verity-target.c
717
for (i = v->levels - 2; i >= 0; i--) {
drivers/md/dm-verity-target.c
721
verity_hash_at_level(v, pw->block, i, &hash_block_start, NULL);
drivers/md/dm-verity-target.c
722
verity_hash_at_level(v, pw->block + pw->n_blocks - 1, i, &hash_block_end, NULL);
drivers/md/dm-verity-target.c
727
cluster >>= v->data_dev_block_bits;
drivers/md/dm-verity-target.c
736
if (unlikely(hash_block_end >= v->hash_blocks))
drivers/md/dm-verity-target.c
737
hash_block_end = v->hash_blocks - 1;
drivers/md/dm-verity-target.c
740
dm_bufio_prefetch_with_ioprio(v->bufio, hash_block_start,
drivers/md/dm-verity-target.c
748
static void verity_submit_prefetch(struct dm_verity *v, struct dm_verity_io *io,
drivers/md/dm-verity-target.c
755
if (v->validated_blocks) {
drivers/md/dm-verity-target.c
756
while (n_blocks && test_bit(block, v->validated_blocks)) {
drivers/md/dm-verity-target.c
761
v->validated_blocks))
drivers/md/dm-verity-target.c
774
pw->v = v;
drivers/md/dm-verity-target.c
778
queue_work(v->verify_wq, &pw->work);
drivers/md/dm-verity-target.c
787
struct dm_verity *v = ti->private;
drivers/md/dm-verity-target.c
790
bio_set_dev(bio, v->data_dev->bdev);
drivers/md/dm-verity-target.c
791
bio->bi_iter.bi_sector = verity_map_sector(v, bio->bi_iter.bi_sector);
drivers/md/dm-verity-target.c
794
((1 << (v->data_dev_block_bits - SECTOR_SHIFT)) - 1)) {
drivers/md/dm-verity-target.c
800
(v->data_dev_block_bits - SECTOR_SHIFT) > v->data_blocks) {
drivers/md/dm-verity-target.c
809
io->v = v;
drivers/md/dm-verity-target.c
811
io->block = bio->bi_iter.bi_sector >> (v->data_dev_block_bits - SECTOR_SHIFT);
drivers/md/dm-verity-target.c
812
io->n_blocks = bio->bi_iter.bi_size >> v->data_dev_block_bits;
drivers/md/dm-verity-target.c
821
verity_submit_prefetch(v, io, bio->bi_ioprio);
drivers/md/dm-verity-target.c
830
struct dm_verity *v = ti->private;
drivers/md/dm-verity-target.c
831
flush_workqueue(v->verify_wq);
drivers/md/dm-verity-target.c
832
dm_bufio_client_reset(v->bufio);
drivers/md/dm-verity-target.c
841
struct dm_verity *v = ti->private;
drivers/md/dm-verity-target.c
848
DMEMIT("%c", v->hash_failed ? 'C' : 'V');
drivers/md/dm-verity-target.c
849
if (verity_fec_is_enabled(v))
drivers/md/dm-verity-target.c
850
DMEMIT(" %lld", atomic64_read(&v->fec->corrected));
drivers/md/dm-verity-target.c
856
v->version,
drivers/md/dm-verity-target.c
857
v->data_dev->name,
drivers/md/dm-verity-target.c
858
v->hash_dev->name,
drivers/md/dm-verity-target.c
859
1 << v->data_dev_block_bits,
drivers/md/dm-verity-target.c
860
1 << v->hash_dev_block_bits,
drivers/md/dm-verity-target.c
861
(unsigned long long)v->data_blocks,
drivers/md/dm-verity-target.c
862
(unsigned long long)v->hash_start,
drivers/md/dm-verity-target.c
863
v->alg_name
drivers/md/dm-verity-target.c
865
for (x = 0; x < v->digest_size; x++)
drivers/md/dm-verity-target.c
866
DMEMIT("%02x", v->root_digest[x]);
drivers/md/dm-verity-target.c
868
if (!v->salt_size)
drivers/md/dm-verity-target.c
871
for (x = 0; x < v->salt_size; x++)
drivers/md/dm-verity-target.c
872
DMEMIT("%02x", v->salt[x]);
drivers/md/dm-verity-target.c
873
if (v->mode != DM_VERITY_MODE_EIO)
drivers/md/dm-verity-target.c
875
if (v->error_mode != DM_VERITY_MODE_EIO)
drivers/md/dm-verity-target.c
877
if (verity_fec_is_enabled(v))
drivers/md/dm-verity-target.c
879
if (v->zero_digest)
drivers/md/dm-verity-target.c
881
if (v->validated_blocks)
drivers/md/dm-verity-target.c
883
if (v->use_bh_wq)
drivers/md/dm-verity-target.c
885
if (v->signature_key_desc)
drivers/md/dm-verity-target.c
890
if (v->mode != DM_VERITY_MODE_EIO) {
drivers/md/dm-verity-target.c
892
switch (v->mode) {
drivers/md/dm-verity-target.c
906
if (v->error_mode != DM_VERITY_MODE_EIO) {
drivers/md/dm-verity-target.c
908
switch (v->error_mode) {
drivers/md/dm-verity-target.c
919
if (v->zero_digest)
drivers/md/dm-verity-target.c
921
if (v->validated_blocks)
drivers/md/dm-verity-target.c
923
if (v->use_bh_wq)
drivers/md/dm-verity-target.c
925
sz = verity_fec_status_table(v, sz, result, maxlen);
drivers/md/dm-verity-target.c
926
if (v->signature_key_desc)
drivers/md/dm-verity-target.c
928
" %s", v->signature_key_desc);
drivers/md/dm-verity-target.c
933
DMEMIT(",hash_failed=%c", v->hash_failed ? 'C' : 'V');
drivers/md/dm-verity-target.c
934
DMEMIT(",verity_version=%u", v->version);
drivers/md/dm-verity-target.c
935
DMEMIT(",data_device_name=%s", v->data_dev->name);
drivers/md/dm-verity-target.c
936
DMEMIT(",hash_device_name=%s", v->hash_dev->name);
drivers/md/dm-verity-target.c
937
DMEMIT(",verity_algorithm=%s", v->alg_name);
drivers/md/dm-verity-target.c
940
for (x = 0; x < v->digest_size; x++)
drivers/md/dm-verity-target.c
941
DMEMIT("%02x", v->root_digest[x]);
drivers/md/dm-verity-target.c
944
if (!v->salt_size)
drivers/md/dm-verity-target.c
947
for (x = 0; x < v->salt_size; x++)
drivers/md/dm-verity-target.c
948
DMEMIT("%02x", v->salt[x]);
drivers/md/dm-verity-target.c
950
DMEMIT(",ignore_zero_blocks=%c", v->zero_digest ? 'y' : 'n');
drivers/md/dm-verity-target.c
951
DMEMIT(",check_at_most_once=%c", v->validated_blocks ? 'y' : 'n');
drivers/md/dm-verity-target.c
952
if (v->signature_key_desc)
drivers/md/dm-verity-target.c
953
DMEMIT(",root_hash_sig_key_desc=%s", v->signature_key_desc);
drivers/md/dm-verity-target.c
955
if (v->mode != DM_VERITY_MODE_EIO) {
drivers/md/dm-verity-target.c
957
switch (v->mode) {
drivers/md/dm-verity-target.c
971
if (v->error_mode != DM_VERITY_MODE_EIO) {
drivers/md/dm-verity-target.c
973
switch (v->error_mode) {
drivers/md/dm-verity-target.c
993
struct dm_verity *v = ti->private;
drivers/md/dm-verity-target.c
995
*bdev = v->data_dev->bdev;
drivers/md/dm-verity-target.c
997
if (ti->len != bdev_nr_sectors(v->data_dev->bdev))
drivers/md/dm-verity-verify-sig.c
103
v->signature_key_desc = kstrdup(sig_key, GFP_KERNEL);
drivers/md/dm-verity-verify-sig.c
104
if (!v->signature_key_desc) {
drivers/md/dm-verity-verify-sig.c
75
struct dm_verity *v,
drivers/md/dm-verity-verify-sig.c
80
struct dm_target *ti = v->ti;
drivers/md/dm-verity-verify-sig.c
84
if (v->signature_key_desc) {
drivers/md/dm-verity-verify-sig.h
27
int verity_verify_sig_parse_opt_args(struct dm_arg_set *as, struct dm_verity *v,
drivers/md/dm-verity-verify-sig.h
52
struct dm_verity *v, struct dm_verity_sig_opts *sig_opts,
drivers/md/dm-verity.h
137
extern int verity_hash(struct dm_verity *v, struct dm_verity_io *io,
drivers/md/dm-verity.h
140
extern int verity_hash_for_block(struct dm_verity *v, struct dm_verity_io *io,
drivers/md/dm-verity.h
95
struct dm_verity *v;
drivers/md/md.c
8791
static void *md_seq_next(struct seq_file *seq, void *v, loff_t *pos)
drivers/md/md.c
8793
return seq_list_next(v, &all_mddevs, pos);
drivers/md/md.c
8796
static void md_seq_stop(struct seq_file *seq, void *v)
drivers/md/md.c
8832
static int md_seq_show(struct seq_file *seq, void *v)
drivers/md/md.c
8838
if (v == &all_mddevs) {
drivers/md/md.c
8845
mddev = list_entry(v, struct mddev, all_mddevs);
drivers/md/persistent-data/dm-array.c
41
static void array_block_prepare_for_write(const struct dm_block_validator *v,
drivers/md/persistent-data/dm-array.c
53
static int array_block_check(const struct dm_block_validator *v,
drivers/md/persistent-data/dm-block-manager.c
444
const struct dm_block_validator *v)
drivers/md/persistent-data/dm-block-manager.c
449
if (!v)
drivers/md/persistent-data/dm-block-manager.c
451
r = v->check(v, (struct dm_block *) buf, dm_bufio_get_block_size(bm->bufio));
drivers/md/persistent-data/dm-block-manager.c
453
DMERR_LIMIT("%s validator check failed for block %llu", v->name,
drivers/md/persistent-data/dm-block-manager.c
457
aux->validator = v;
drivers/md/persistent-data/dm-block-manager.c
459
if (unlikely(aux->validator != v)) {
drivers/md/persistent-data/dm-block-manager.c
461
aux->validator->name, v ? v->name : "NULL",
drivers/md/persistent-data/dm-block-manager.c
470
const struct dm_block_validator *v,
drivers/md/persistent-data/dm-block-manager.c
491
r = dm_bm_validate_buffer(bm, to_buffer(*result), aux, v);
drivers/md/persistent-data/dm-block-manager.c
503
dm_block_t b, const struct dm_block_validator *v,
drivers/md/persistent-data/dm-block-manager.c
527
r = dm_bm_validate_buffer(bm, to_buffer(*result), aux, v);
drivers/md/persistent-data/dm-block-manager.c
539
dm_block_t b, const struct dm_block_validator *v,
drivers/md/persistent-data/dm-block-manager.c
561
r = dm_bm_validate_buffer(bm, to_buffer(*result), aux, v);
drivers/md/persistent-data/dm-block-manager.c
572
dm_block_t b, const struct dm_block_validator *v,
drivers/md/persistent-data/dm-block-manager.c
596
aux->validator = v;
drivers/md/persistent-data/dm-block-manager.h
54
void (*prepare_for_write)(const struct dm_block_validator *v,
drivers/md/persistent-data/dm-block-manager.h
60
int (*check)(const struct dm_block_validator *v,
drivers/md/persistent-data/dm-block-manager.h
78
const struct dm_block_validator *v,
drivers/md/persistent-data/dm-block-manager.h
82
const struct dm_block_validator *v,
drivers/md/persistent-data/dm-block-manager.h
90
const struct dm_block_validator *v,
drivers/md/persistent-data/dm-block-manager.h
98
const struct dm_block_validator *v,
drivers/md/persistent-data/dm-btree-spine.c
19
static void node_prepare_for_write(const struct dm_block_validator *v,
drivers/md/persistent-data/dm-btree-spine.c
32
static int node_check(const struct dm_block_validator *v,
drivers/md/persistent-data/dm-btree.c
345
uint64_t *result_key, void *v, size_t value_size)
drivers/md/persistent-data/dm-btree.c
368
if (v)
drivers/md/persistent-data/dm-btree.c
369
memcpy(v, value_ptr(ro_node(s), i), value_size);
drivers/md/persistent-data/dm-space-map-common.c
25
static void index_prepare_for_write(const struct dm_block_validator *v,
drivers/md/persistent-data/dm-space-map-common.c
37
static int index_check(const struct dm_block_validator *v,
drivers/md/persistent-data/dm-space-map-common.c
75
static void dm_bitmap_prepare_for_write(const struct dm_block_validator *v,
drivers/md/persistent-data/dm-space-map-common.c
87
static int dm_bitmap_check(const struct dm_block_validator *v,
drivers/md/persistent-data/dm-transaction-manager.c
260
const struct dm_block_validator *v,
drivers/md/persistent-data/dm-transaction-manager.c
273
r = dm_bm_write_lock_zero(tm->bm, new_block, v, result);
drivers/md/persistent-data/dm-transaction-manager.c
289
const struct dm_block_validator *v,
drivers/md/persistent-data/dm-transaction-manager.c
304
r = dm_bm_read_lock(tm->bm, orig, v, &orig_block);
drivers/md/persistent-data/dm-transaction-manager.c
315
r = dm_bm_write_lock_zero(tm->bm, new, v, result);
drivers/md/persistent-data/dm-transaction-manager.c
329
const struct dm_block_validator *v, struct dm_block **result,
drivers/md/persistent-data/dm-transaction-manager.c
342
return dm_bm_write_lock(tm->bm, orig, v, result);
drivers/md/persistent-data/dm-transaction-manager.c
344
r = __shadow_block(tm, orig, v, result);
drivers/md/persistent-data/dm-transaction-manager.c
354
const struct dm_block_validator *v,
drivers/md/persistent-data/dm-transaction-manager.c
358
int r = dm_bm_read_try_lock(tm->real->bm, b, v, blk);
drivers/md/persistent-data/dm-transaction-manager.c
366
return dm_bm_read_lock(tm->bm, b, v, blk);
drivers/md/persistent-data/dm-transaction-manager.h
67
const struct dm_block_validator *v,
drivers/md/persistent-data/dm-transaction-manager.h
87
const struct dm_block_validator *v,
drivers/md/persistent-data/dm-transaction-manager.h
95
const struct dm_block_validator *v,
drivers/media/cec/core/cec-pin.c
1106
u8 v = pin->work_pin_events[idx];
drivers/media/cec/core/cec-pin.c
1109
v & CEC_PIN_EVENT_FL_IS_HIGH,
drivers/media/cec/core/cec-pin.c
1110
v & CEC_PIN_EVENT_FL_DROPPED,
drivers/media/cec/core/cec-pin.c
112
static void cec_pin_update(struct cec_pin *pin, bool v, bool force)
drivers/media/cec/core/cec-pin.c
114
if (!force && v == pin->adap->cec_pin_is_high)
drivers/media/cec/core/cec-pin.c
117
pin->adap->cec_pin_is_high = v;
drivers/media/cec/core/cec-pin.c
119
u8 ev = v;
drivers/media/cec/core/cec-pin.c
139
bool v = call_pin_op(pin, read);
drivers/media/cec/core/cec-pin.c
141
cec_pin_update(pin, v, false);
drivers/media/cec/core/cec-pin.c
142
return v;
drivers/media/cec/core/cec-pin.c
400
bool v;
drivers/media/cec/core/cec-pin.c
532
v = val & (1 << (7 - (pin->tx_bit % 10)));
drivers/media/cec/core/cec-pin.c
534
pin->state = v ? CEC_ST_TX_DATA_BIT_1_LOW :
drivers/media/cec/core/cec-pin.c
543
v = !pin->tx_post_eom && tx_byte_idx == tot_len - 1;
drivers/media/cec/core/cec-pin.c
547
v = true;
drivers/media/cec/core/cec-pin.c
549
} else if (v && tx_no_eom(pin)) {
drivers/media/cec/core/cec-pin.c
551
v = false;
drivers/media/cec/core/cec-pin.c
553
pin->state = v ? CEC_ST_TX_DATA_BIT_1_LOW :
drivers/media/cec/core/cec-pin.c
568
v = pin->state == CEC_ST_TX_DATA_BIT_1_LOW;
drivers/media/cec/core/cec-pin.c
570
if (v && (pin->tx_bit < 4 || is_ack_bit)) {
drivers/media/cec/core/cec-pin.c
574
pin->state = v ? CEC_ST_TX_DATA_BIT_1_HIGH_SHORT :
drivers/media/cec/core/cec-pin.c
578
pin->state = v ? CEC_ST_TX_DATA_BIT_1_HIGH_LONG :
drivers/media/cec/core/cec-pin.c
581
pin->state = v ? CEC_ST_TX_DATA_BIT_1_HIGH :
drivers/media/cec/core/cec-pin.c
594
v = cec_pin_read(pin);
drivers/media/cec/core/cec-pin.c
604
if (!v && !is_ack_bit && !pin->tx_generated_poll) {
drivers/media/cec/core/cec-pin.c
631
ack = cec_msg_is_broadcast(&pin->tx_msg) ? v : !v;
drivers/media/cec/core/cec-pin.c
683
bool v;
drivers/media/cec/core/cec-pin.c
692
v = cec_pin_read(pin);
drivers/media/cec/core/cec-pin.c
693
if (!v)
drivers/media/cec/core/cec-pin.c
716
v = cec_pin_read(pin);
drivers/media/cec/core/cec-pin.c
722
if (v && delta > CEC_TIM_START_BIT_TOTAL_LONG) {
drivers/media/cec/core/cec-pin.c
727
if (v)
drivers/media/cec/core/cec-pin.c
751
v = cec_pin_read(pin);
drivers/media/cec/core/cec-pin.c
757
v << (7 - (pin->rx_bit % 10));
drivers/media/cec/core/cec-pin.c
760
pin->rx_eom = v;
drivers/media/cec/core/cec-pin.c
774
v = cec_pin_read(pin);
drivers/media/cec/core/cec-pin.c
780
if (v && delta > CEC_TIM_DATA_BIT_TOTAL_LONG) {
drivers/media/cec/core/cec-pin.c
785
if (v)
drivers/media/cec/core/cec-pin.c
844
v = cec_pin_read(pin);
drivers/media/cec/core/cec-pin.c
845
if (v && pin->rx_eom) {
drivers/media/cec/platform/tegra/tegra_cec.c
171
u32 v;
drivers/media/cec/platform/tegra/tegra_cec.c
175
v = cec_read(cec, TEGRA_CEC_RX_REGISTER);
drivers/media/cec/platform/tegra/tegra_cec.c
177
cec->rx_buf[cec->rx_buf_cnt++] = v & 0xff;
drivers/media/cec/platform/tegra/tegra_cec.c
178
if (v & TEGRA_CEC_RX_REGISTER_EOM) {
drivers/media/cec/usb/extron-da-hd-4k-plus/extron-da-hd-4k-plus.c
664
int v = hex2bin(&msg.msg[msg.len], data + 1, 1);
drivers/media/cec/usb/extron-da-hd-4k-plus/extron-da-hd-4k-plus.c
666
if (*data != '%' || v)
drivers/media/common/b2c2/flexcop-fe-tuner.c
103
v.lnb_switch_freq_200.LNB_CTLPrescaler_sig = 1; /* divide by 2 */
drivers/media/common/b2c2/flexcop-fe-tuner.c
104
v.lnb_switch_freq_200.LNB_CTLHighCount_sig = ax;
drivers/media/common/b2c2/flexcop-fe-tuner.c
105
v.lnb_switch_freq_200.LNB_CTLLowCount_sig = ax == 0 ? 0x1ff : ax;
drivers/media/common/b2c2/flexcop-fe-tuner.c
106
return fc->write_ibi_reg(fc,lnb_switch_freq_200,v);
drivers/media/common/b2c2/flexcop-fe-tuner.c
46
flexcop_ibi_value v;
drivers/media/common/b2c2/flexcop-fe-tuner.c
49
v = fc->read_ibi_reg(fc, misc_204);
drivers/media/common/b2c2/flexcop-fe-tuner.c
52
v.misc_204.ACPI1_sig = 1;
drivers/media/common/b2c2/flexcop-fe-tuner.c
55
v.misc_204.ACPI1_sig = 0;
drivers/media/common/b2c2/flexcop-fe-tuner.c
56
v.misc_204.LNB_L_H_sig = 0;
drivers/media/common/b2c2/flexcop-fe-tuner.c
59
v.misc_204.ACPI1_sig = 0;
drivers/media/common/b2c2/flexcop-fe-tuner.c
60
v.misc_204.LNB_L_H_sig = 1;
drivers/media/common/b2c2/flexcop-fe-tuner.c
66
return fc->write_ibi_reg(fc, misc_204, v);
drivers/media/common/b2c2/flexcop-fe-tuner.c
86
flexcop_ibi_value v;
drivers/media/common/b2c2/flexcop-fe-tuner.c
88
v.raw = 0;
drivers/media/common/b2c2/flexcop-hw-filter.c
227
flexcop_ibi_value v;
drivers/media/common/b2c2/flexcop-hw-filter.c
239
v = fc->read_ibi_reg(fc, pid_filter_308);
drivers/media/common/b2c2/flexcop-hw-filter.c
240
v.pid_filter_308.EMM_filter_4 = 1;
drivers/media/common/b2c2/flexcop-hw-filter.c
241
v.pid_filter_308.EMM_filter_6 = 0;
drivers/media/common/b2c2/flexcop-hw-filter.c
242
fc->write_ibi_reg(fc, pid_filter_308, v);
drivers/media/common/b2c2/flexcop-misc.c
11
flexcop_ibi_value v = fc->read_ibi_reg(fc,misc_204);
drivers/media/common/b2c2/flexcop-misc.c
13
switch (v.misc_204.Rev_N_sig_revision_hi) {
drivers/media/common/b2c2/flexcop-misc.c
28
v.misc_204.Rev_N_sig_revision_hi);
drivers/media/common/b2c2/flexcop-misc.c
32
if ((fc->has_32_hw_pid_filter = v.misc_204.Rev_N_sig_caps))
drivers/media/common/b2c2/flexcop-reg.h
163
flexcop_ibi_value v = fc->read_ibi_reg(fc,reg); \
drivers/media/common/b2c2/flexcop-reg.h
164
v.reg.attr = val; \
drivers/media/common/b2c2/flexcop-reg.h
165
fc->write_ibi_reg(fc,reg,v); \
drivers/media/common/b2c2/flexcop-sram.c
34
flexcop_ibi_value v;
drivers/media/common/b2c2/flexcop-sram.c
35
v = fc->read_ibi_reg(fc, sram_dest_reg_714);
drivers/media/common/b2c2/flexcop-sram.c
44
v.sram_dest_reg_714.NET_Dest = target;
drivers/media/common/b2c2/flexcop-sram.c
46
v.sram_dest_reg_714.CAI_Dest = target;
drivers/media/common/b2c2/flexcop-sram.c
48
v.sram_dest_reg_714.CAO_Dest = target;
drivers/media/common/b2c2/flexcop-sram.c
50
v.sram_dest_reg_714.MEDIA_Dest = target;
drivers/media/common/b2c2/flexcop-sram.c
52
fc->write_ibi_reg(fc,sram_dest_reg_714,v);
drivers/media/common/b2c2/flexcop-sram.c
67
flexcop_ibi_value v = fc->read_ibi_reg(fc,sram_dest_reg_714);
drivers/media/common/b2c2/flexcop-sram.c
68
v.sram_dest_reg_714.ctrl_usb_wan = usb_wan;
drivers/media/common/b2c2/flexcop-sram.c
69
v.sram_dest_reg_714.ctrl_sramdma = sramdma;
drivers/media/common/b2c2/flexcop-sram.c
70
v.sram_dest_reg_714.ctrl_maximumfill = maximumfill;
drivers/media/common/b2c2/flexcop-sram.c
71
fc->write_ibi_reg(fc,sram_dest_reg_714,v);
drivers/media/common/v4l2-tpg/v4l2-tpg-colors.c
1165
static double transfer_srgb_to_rgb(double v)
drivers/media/common/v4l2-tpg/v4l2-tpg-colors.c
1167
if (v < -0.04045)
drivers/media/common/v4l2-tpg/v4l2-tpg-colors.c
1168
return pow((-v + 0.055) / 1.055, 2.4);
drivers/media/common/v4l2-tpg/v4l2-tpg-colors.c
1169
return (v <= 0.04045) ? v / 12.92 : pow((v + 0.055) / 1.055, 2.4);
drivers/media/common/v4l2-tpg/v4l2-tpg-colors.c
1172
static double transfer_rgb_to_srgb(double v)
drivers/media/common/v4l2-tpg/v4l2-tpg-colors.c
1174
if (v <= -0.0031308)
drivers/media/common/v4l2-tpg/v4l2-tpg-colors.c
1175
return -1.055 * pow(-v, 1.0 / 2.4) + 0.055;
drivers/media/common/v4l2-tpg/v4l2-tpg-colors.c
1176
if (v <= 0.0031308)
drivers/media/common/v4l2-tpg/v4l2-tpg-colors.c
1177
return v * 12.92;
drivers/media/common/v4l2-tpg/v4l2-tpg-colors.c
1178
return 1.055 * pow(v, 1.0 / 2.4) - 0.055;
drivers/media/common/v4l2-tpg/v4l2-tpg-colors.c
1181
static double transfer_rgb_to_smpte240m(double v)
drivers/media/common/v4l2-tpg/v4l2-tpg-colors.c
1183
return (v <= 0.0228) ? v * 4.0 : 1.1115 * pow(v, 0.45) - 0.1115;
drivers/media/common/v4l2-tpg/v4l2-tpg-colors.c
1186
static double transfer_rgb_to_rec709(double v)
drivers/media/common/v4l2-tpg/v4l2-tpg-colors.c
1188
if (v <= -0.018)
drivers/media/common/v4l2-tpg/v4l2-tpg-colors.c
1189
return -1.099 * pow(-v, 0.45) + 0.099;
drivers/media/common/v4l2-tpg/v4l2-tpg-colors.c
1190
return (v < 0.018) ? v * 4.5 : 1.099 * pow(v, 0.45) - 0.099;
drivers/media/common/v4l2-tpg/v4l2-tpg-colors.c
1193
static double transfer_rec709_to_rgb(double v)
drivers/media/common/v4l2-tpg/v4l2-tpg-colors.c
1195
return (v < 0.081) ? v / 4.5 : pow((v + 0.099) / 1.099, 1.0 / 0.45);
drivers/media/common/v4l2-tpg/v4l2-tpg-colors.c
1198
static double transfer_rgb_to_oprgb(double v)
drivers/media/common/v4l2-tpg/v4l2-tpg-colors.c
1200
return pow(v, 1.0 / 2.19921875);
drivers/media/common/v4l2-tpg/v4l2-tpg-colors.c
1203
static double transfer_rgb_to_dcip3(double v)
drivers/media/common/v4l2-tpg/v4l2-tpg-colors.c
1205
return pow(v, 1.0 / 2.6);
drivers/media/common/v4l2-tpg/v4l2-tpg-colors.c
1208
static double transfer_rgb_to_smpte2084(double v)
drivers/media/common/v4l2-tpg/v4l2-tpg-colors.c
1221
v /= 100.0;
drivers/media/common/v4l2-tpg/v4l2-tpg-colors.c
1222
v = pow(v, m1);
drivers/media/common/v4l2-tpg/v4l2-tpg-colors.c
1223
return pow((c1 + c2 * v) / (1 + c3 * v), m2);
drivers/media/common/v4l2-tpg/v4l2-tpg-colors.c
1226
static double transfer_srgb_to_rec709(double v)
drivers/media/common/v4l2-tpg/v4l2-tpg-colors.c
1228
return transfer_rgb_to_rec709(transfer_srgb_to_rgb(v));
drivers/media/common/v4l2-tpg/v4l2-tpg-core.c
1001
tpg->colors[k][2] = v;
drivers/media/common/v4l2-tpg/v4l2-tpg-core.c
573
static inline int rec709_to_linear(int v)
drivers/media/common/v4l2-tpg/v4l2-tpg-core.c
575
v = clamp(v, 0, 0xff0);
drivers/media/common/v4l2-tpg/v4l2-tpg-core.c
576
return tpg_rec709_to_linear[v];
drivers/media/common/v4l2-tpg/v4l2-tpg-core.c
579
static inline int linear_to_rec709(int v)
drivers/media/common/v4l2-tpg/v4l2-tpg-core.c
581
v = clamp(v, 0, 0xff0);
drivers/media/common/v4l2-tpg/v4l2-tpg-core.c
582
return tpg_linear_to_rec709[v];
drivers/media/common/v4l2-tpg/v4l2-tpg-core.c
586
int *h, int *s, int *v)
drivers/media/common/v4l2-tpg/v4l2-tpg-core.c
599
*v = max_rgb;
drivers/media/common/v4l2-tpg/v4l2-tpg-core.c
661
#define COEFF(v, r) ((int)(0.5 + (v) * (r) * 256.0))
drivers/media/common/v4l2-tpg/v4l2-tpg-core.c
776
#define COEFF(v, r) ((int)(0.5 + (v) * ((255.0 * 255.0 * 16.0) / (r))))
drivers/media/common/v4l2-tpg/v4l2-tpg-core.c
996
int h, s, v;
drivers/media/common/v4l2-tpg/v4l2-tpg-core.c
998
color_to_hsv(tpg, r, g, b, &h, &s, &v);
drivers/media/dvb-frontends/bcm3510.c
126
static int bcm3510_writeB(struct bcm3510_state *state, u8 reg, bcm3510_register_value v)
drivers/media/dvb-frontends/bcm3510.c
128
return bcm3510_writebytes(state,reg,&v.raw,1);
drivers/media/dvb-frontends/bcm3510.c
131
static int bcm3510_readB(struct bcm3510_state *state, u8 reg, bcm3510_register_value *v)
drivers/media/dvb-frontends/bcm3510.c
133
return bcm3510_readbytes(state,reg,&v->raw,1);
drivers/media/dvb-frontends/bcm3510.c
139
bcm3510_register_value v;
drivers/media/dvb-frontends/bcm3510.c
142
v.HABADR_a6.HABADR = 0;
drivers/media/dvb-frontends/bcm3510.c
143
if ((ret = bcm3510_writeB(st,0xa6,v)) < 0)
drivers/media/dvb-frontends/bcm3510.c
147
if ((ret = bcm3510_readB(st,0xa7,&v)) < 0)
drivers/media/dvb-frontends/bcm3510.c
149
buf[i] = v.HABDATA_a7;
drivers/media/dvb-frontends/bcm3510.c
156
bcm3510_register_value v,hab;
drivers/media/dvb-frontends/bcm3510.c
162
if ((ret = bcm3510_readB(st,0xa8,&v)) < 0)
drivers/media/dvb-frontends/bcm3510.c
164
if (v.HABSTAT_a8.HABR) {
drivers/media/dvb-frontends/bcm3510.c
166
v.HABSTAT_a8.HABR = 0;
drivers/media/dvb-frontends/bcm3510.c
167
bcm3510_writeB(st,0xa8,v);
drivers/media/dvb-frontends/bcm3510.c
185
v.raw = 0; v.HABSTAT_a8.HABR = 1; v.HABSTAT_a8.LDHABR = 1;
drivers/media/dvb-frontends/bcm3510.c
186
if ((ret = bcm3510_writeB(st,0xa8,v)) < 0)
drivers/media/dvb-frontends/bcm3510.c
194
if ((ret = bcm3510_readB(st,0xa8,&v)) < 0)
drivers/media/dvb-frontends/bcm3510.c
197
if (!v.HABSTAT_a8.HABR)
drivers/media/dvb-frontends/bcm3510.c
684
bcm3510_register_value v;
drivers/media/dvb-frontends/bcm3510.c
686
bcm3510_readB(st,0xa0,&v); v.HCTL1_a0.RESET = 1;
drivers/media/dvb-frontends/bcm3510.c
687
if ((ret = bcm3510_writeB(st,0xa0,v)) < 0)
drivers/media/dvb-frontends/bcm3510.c
693
if ((ret = bcm3510_readB(st,0xa2,&v)) < 0)
drivers/media/dvb-frontends/bcm3510.c
696
if (v.APSTAT1_a2.RESET)
drivers/media/dvb-frontends/bcm3510.c
705
bcm3510_register_value v;
drivers/media/dvb-frontends/bcm3510.c
709
v.raw = 0;
drivers/media/dvb-frontends/bcm3510.c
710
if ((ret = bcm3510_writeB(st,0xa0,v)) < 0)
drivers/media/dvb-frontends/bcm3510.c
716
if ((ret = bcm3510_readB(st,0xa2,&v)) < 0)
drivers/media/dvb-frontends/bcm3510.c
720
if (!v.APSTAT1_a2.RESET)
drivers/media/dvb-frontends/bcm3510.c
730
bcm3510_register_value v;
drivers/media/dvb-frontends/bcm3510.c
733
if ((ret = bcm3510_readB(st,0xa2,&v)) < 0)
drivers/media/dvb-frontends/bcm3510.c
735
if (v.APSTAT1_a2.RUN) {
drivers/media/dvb-frontends/bcm3510.c
746
v.TSTCTL_2e.CTL = 0;
drivers/media/dvb-frontends/bcm3510.c
747
if ((ret = bcm3510_writeB(st,0x2e,v)) < 0)
drivers/media/dvb-frontends/bcm3510.c
800
bcm3510_register_value v;
drivers/media/dvb-frontends/bcm3510.c
818
if (bcm3510_readB(state, 0xe0, &v) < 0)
drivers/media/dvb-frontends/bcm3510.c
821
deb_info("Revision: 0x%1x, Layer: 0x%1x.\n",v.REVID_e0.REV,v.REVID_e0.LAYER);
drivers/media/dvb-frontends/bcm3510.c
823
if ((v.REVID_e0.REV != 0x1 && v.REVID_e0.LAYER != 0xb) && /* cold */
drivers/media/dvb-frontends/bcm3510.c
824
(v.REVID_e0.REV != 0x8 && v.REVID_e0.LAYER != 0x0)) /* warm */
drivers/media/dvb-frontends/bcm3510.c
827
info("Revision: 0x%1x, Layer: 0x%1x.",v.REVID_e0.REV,v.REVID_e0.LAYER);
drivers/media/dvb-frontends/dib0090.c
1012
v = gain_reg[i];
drivers/media/dvb-frontends/dib0090.c
1013
if (force || state->gain_reg[i] != v) {
drivers/media/dvb-frontends/dib0090.c
1014
state->gain_reg[i] = v;
drivers/media/dvb-frontends/dib0090.c
1015
dib0090_write_reg(state, gain_reg_addr[i], v);
drivers/media/dvb-frontends/dib0090.c
330
u16 v;
drivers/media/dvb-frontends/dib0090.c
333
v = dib0090_read_reg(state, 0x1a);
drivers/media/dvb-frontends/dib0090.c
338
dprintk("Tuner identification (Version = 0x%04x)\n", v);
drivers/media/dvb-frontends/dib0090.c
341
v &= ~KROSUS_PLL_LOCKED;
drivers/media/dvb-frontends/dib0090.c
343
identity->version = v & 0xff;
drivers/media/dvb-frontends/dib0090.c
344
identity->product = (v >> 8) & 0xf;
drivers/media/dvb-frontends/dib0090.c
424
u16 v = dib0090_fw_read_reg(state, 0x1a);
drivers/media/dvb-frontends/dib0090.c
428
dprintk("FE: Tuner identification (Version = 0x%04x)\n", v);
drivers/media/dvb-frontends/dib0090.c
431
v &= ~KROSUS_PLL_LOCKED;
drivers/media/dvb-frontends/dib0090.c
433
identity->version = v & 0xff;
drivers/media/dvb-frontends/dib0090.c
434
identity->product = (v >> 8) & 0xf;
drivers/media/dvb-frontends/dib0090.c
512
u16 PllCfg, i, v;
drivers/media/dvb-frontends/dib0090.c
555
v = !!(dib0090_read_reg(state, 0x1a) & 0x800);
drivers/media/dvb-frontends/dib0090.c
556
if (v)
drivers/media/dvb-frontends/dib0090.c
580
u16 v;
drivers/media/dvb-frontends/dib0090.c
592
v = (0 << 15) | ((!cfg->analog_output) << 14) | (1 << 9) | (0 << 8) | (cfg->clkouttobamse << 4) | (0 << 2) | (0);
drivers/media/dvb-frontends/dib0090.c
594
v |= cfg->clkoutdrive << 5;
drivers/media/dvb-frontends/dib0090.c
596
v |= 7 << 5;
drivers/media/dvb-frontends/dib0090.c
598
v |= 2 << 10;
drivers/media/dvb-frontends/dib0090.c
599
dib0090_fw_write_reg(state, 0x23, v);
drivers/media/dvb-frontends/dib0090.c
626
v = !!(dib0090_fw_read_reg(state, 0x1a) & 0x800);
drivers/media/dvb-frontends/dib0090.c
627
if (v)
drivers/media/dvb-frontends/dib0090.c
919
u16 i, v, gain_reg[4] = { 0 }, gain;
drivers/media/dvb-frontends/dib0090.c
973
v = 0; /* force the gain to write for the current amp to be null */
drivers/media/dvb-frontends/dib0090.c
975
v = g[2]; /* force this amp to be full gain */
drivers/media/dvb-frontends/dib0090.c
977
v = ((ref - (g[1] - g[0])) * g[2]) / g[0];
drivers/media/dvb-frontends/dib0090.c
980
gain_reg[0] = v;
drivers/media/dvb-frontends/dib0090.c
982
gain_reg[0] |= v << 7;
drivers/media/dvb-frontends/dib0090.c
984
gain_reg[1] = v;
drivers/media/dvb-frontends/dib0090.c
986
gain_reg[1] |= v << 7;
drivers/media/dvb-frontends/dib0090.c
988
gain_reg[2] = v | state->rf_lt_def;
drivers/media/dvb-frontends/dib0090.c
990
gain_reg[3] = v << 3;
drivers/media/dvb-frontends/dib0090.c
992
gain_reg[3] |= v << 8;
drivers/media/dvb-frontends/dib3000mb_priv.h
19
#define wr_foreach(a,v) { int i; \
drivers/media/dvb-frontends/dib3000mb_priv.h
20
if (sizeof(a) != sizeof(v)) \
drivers/media/dvb-frontends/dib3000mb_priv.h
21
pr_err("sizeof: %zu %zu is different", sizeof(a), sizeof(v));\
drivers/media/dvb-frontends/dib3000mb_priv.h
23
wr(a[i],v[i]); \
drivers/media/dvb-frontends/dib7000m.h
24
#define DIB7000M_GPIO_PWM_POS0(v) ((v & 0xf) << 12)
drivers/media/dvb-frontends/dib7000m.h
25
#define DIB7000M_GPIO_PWM_POS1(v) ((v & 0xf) << 8 )
drivers/media/dvb-frontends/dib7000m.h
26
#define DIB7000M_GPIO_PWM_POS2(v) ((v & 0xf) << 4 )
drivers/media/dvb-frontends/dib7000m.h
27
#define DIB7000M_GPIO_PWM_POS3(v) (v & 0xf)
drivers/media/dvb-frontends/dib7000p.c
436
static int dib7000p_set_agc1_min(struct dvb_frontend *fe, u16 v)
drivers/media/dvb-frontends/dib7000p.c
439
return dib7000p_write_word(state, 108, v);
drivers/media/dvb-frontends/dib7000p.h
21
#define DIB7000P_GPIO_PWM_POS0(v) ((v & 0xf) << 12)
drivers/media/dvb-frontends/dib7000p.h
22
#define DIB7000P_GPIO_PWM_POS1(v) ((v & 0xf) << 8 )
drivers/media/dvb-frontends/dib7000p.h
23
#define DIB7000P_GPIO_PWM_POS2(v) ((v & 0xf) << 4 )
drivers/media/dvb-frontends/dib7000p.h
24
#define DIB7000P_GPIO_PWM_POS3(v) (v & 0xf)
drivers/media/dvb-frontends/dib7000p.h
52
int (*set_agc1_min)(struct dvb_frontend *fe, u16 v);
drivers/media/dvb-frontends/dib8000.h
21
#define DIB8000_GPIO_PWM_POS0(v) ((v & 0xf) << 12)
drivers/media/dvb-frontends/dib8000.h
22
#define DIB8000_GPIO_PWM_POS1(v) ((v & 0xf) << 8 )
drivers/media/dvb-frontends/dib8000.h
23
#define DIB8000_GPIO_PWM_POS2(v) ((v & 0xf) << 4 )
drivers/media/dvb-frontends/dib8000.h
24
#define DIB8000_GPIO_PWM_POS3(v) (v & 0xf)
drivers/media/dvb-frontends/dibx000_common.h
148
#define BANDWIDTH_TO_KHZ(v) ((v) / 1000)
drivers/media/dvb-frontends/dibx000_common.h
149
#define BANDWIDTH_TO_HZ(v) ((v) * 1000)
drivers/media/dvb-frontends/itd1000.c
42
static int itd1000_write_regs(struct itd1000_state *state, u8 reg, u8 v[], u8 len)
drivers/media/dvb-frontends/itd1000.c
57
memcpy(&buf[1], v, len);
drivers/media/dvb-frontends/itd1000.c
86
static inline int itd1000_write_reg(struct itd1000_state *state, u8 r, u8 v)
drivers/media/dvb-frontends/itd1000.c
88
u8 tmp = v; /* see gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */
drivers/media/dvb-frontends/lgs8gxx.c
756
u16 v;
drivers/media/dvb-frontends/lgs8gxx.c
763
v = agc_lvl[0];
drivers/media/dvb-frontends/lgs8gxx.c
764
v <<= 8;
drivers/media/dvb-frontends/lgs8gxx.c
765
v |= agc_lvl[1];
drivers/media/dvb-frontends/lgs8gxx.c
767
dprintk("agc_lvl: 0x%04X\n", v);
drivers/media/dvb-frontends/lgs8gxx.c
769
if (v < 0x100)
drivers/media/dvb-frontends/lgs8gxx.c
771
else if (v < 0x190)
drivers/media/dvb-frontends/lgs8gxx.c
773
else if (v < 0x2A8)
drivers/media/dvb-frontends/lgs8gxx.c
775
else if (v < 0x381)
drivers/media/dvb-frontends/lgs8gxx.c
777
else if (v < 0x400)
drivers/media/dvb-frontends/lgs8gxx.c
779
else if (v == 0x400)
drivers/media/dvb-frontends/lgs8gxx.c
835
s16 v = 0;
drivers/media/dvb-frontends/lgs8gxx.c
840
v |= t;
drivers/media/dvb-frontends/lgs8gxx.c
841
v <<= 8;
drivers/media/dvb-frontends/lgs8gxx.c
843
v |= t;
drivers/media/dvb-frontends/lgs8gxx.c
845
*signal = v;
drivers/media/dvb-frontends/lgs8gxx.c
968
u8 v = 0x80 | priv->config->tuner_address;
drivers/media/dvb-frontends/lgs8gxx.c
969
return lgs8gxx_write_reg(priv, 0x01, v);
drivers/media/dvb-frontends/mb86a16.c
1025
int v, vmax, vmin;
drivers/media/dvb-frontends/mb86a16.c
1157
v = 0;
drivers/media/dvb-frontends/mb86a16.c
1161
v, R, swp_ofs, &fOSC,
drivers/media/dvb-frontends/mb86a16.c
1184
V[30 + v] = SIG1 ;
drivers/media/dvb-frontends/mb86a16.c
1185
swp_freq = swp_freq_calcuation(state, i, v, V, vmax, vmin,
drivers/media/dvb-frontends/mb86a16.c
1225
if (v > vmax)
drivers/media/dvb-frontends/mb86a16.c
1227
if (v < vmin)
drivers/media/dvb-frontends/mb86a16.c
1237
v = (i + 1) / 2;
drivers/media/dvb-frontends/mb86a16.c
1239
v = -i / 2;
drivers/media/dvb-frontends/mb86a16.c
730
int v, int R,
drivers/media/dvb-frontends/mb86a16.c
740
crnt_swp_freq = fOSC_start * 1000 + v * swp_ofs;
drivers/media/dvb-frontends/mb86a16.c
758
static int swp_freq_calcuation(struct mb86a16_state *state, int i, int v, int *V, int vmax, int vmin,
drivers/media/dvb-frontends/mb86a16.c
763
if ((i % 2 == 1) && (v <= vmax)) {
drivers/media/dvb-frontends/mb86a16.c
765
if ((v - 1 == vmin) &&
drivers/media/dvb-frontends/mb86a16.c
766
(*(V + 30 + v) >= 0) &&
drivers/media/dvb-frontends/mb86a16.c
767
(*(V + 30 + v - 1) >= 0) &&
drivers/media/dvb-frontends/mb86a16.c
768
(*(V + 30 + v - 1) > *(V + 30 + v)) &&
drivers/media/dvb-frontends/mb86a16.c
769
(*(V + 30 + v - 1) > SIGMIN)) {
drivers/media/dvb-frontends/mb86a16.c
772
*SIG1 = *(V + 30 + v - 1);
drivers/media/dvb-frontends/mb86a16.c
773
} else if ((v == vmax) &&
drivers/media/dvb-frontends/mb86a16.c
774
(*(V + 30 + v) >= 0) &&
drivers/media/dvb-frontends/mb86a16.c
775
(*(V + 30 + v - 1) >= 0) &&
drivers/media/dvb-frontends/mb86a16.c
776
(*(V + 30 + v) > *(V + 30 + v - 1)) &&
drivers/media/dvb-frontends/mb86a16.c
777
(*(V + 30 + v) > SIGMIN)) {
drivers/media/dvb-frontends/mb86a16.c
780
*SIG1 = *(V + 30 + v);
drivers/media/dvb-frontends/mb86a16.c
781
} else if ((*(V + 30 + v) > 0) &&
drivers/media/dvb-frontends/mb86a16.c
782
(*(V + 30 + v - 1) > 0) &&
drivers/media/dvb-frontends/mb86a16.c
783
(*(V + 30 + v - 2) > 0) &&
drivers/media/dvb-frontends/mb86a16.c
784
(*(V + 30 + v - 3) > 0) &&
drivers/media/dvb-frontends/mb86a16.c
785
(*(V + 30 + v - 1) > *(V + 30 + v)) &&
drivers/media/dvb-frontends/mb86a16.c
786
(*(V + 30 + v - 2) > *(V + 30 + v - 3)) &&
drivers/media/dvb-frontends/mb86a16.c
787
((*(V + 30 + v - 1) > SIGMIN) ||
drivers/media/dvb-frontends/mb86a16.c
788
(*(V + 30 + v - 2) > SIGMIN))) {
drivers/media/dvb-frontends/mb86a16.c
790
if (*(V + 30 + v - 1) >= *(V + 30 + v - 2)) {
drivers/media/dvb-frontends/mb86a16.c
792
*SIG1 = *(V + 30 + v - 1);
drivers/media/dvb-frontends/mb86a16.c
795
*SIG1 = *(V + 30 + v - 2);
drivers/media/dvb-frontends/mb86a16.c
797
} else if ((v == vmax) &&
drivers/media/dvb-frontends/mb86a16.c
798
(*(V + 30 + v) >= 0) &&
drivers/media/dvb-frontends/mb86a16.c
799
(*(V + 30 + v - 1) >= 0) &&
drivers/media/dvb-frontends/mb86a16.c
800
(*(V + 30 + v - 2) >= 0) &&
drivers/media/dvb-frontends/mb86a16.c
801
(*(V + 30 + v) > *(V + 30 + v - 2)) &&
drivers/media/dvb-frontends/mb86a16.c
802
(*(V + 30 + v - 1) > *(V + 30 + v - 2)) &&
drivers/media/dvb-frontends/mb86a16.c
803
((*(V + 30 + v) > SIGMIN) ||
drivers/media/dvb-frontends/mb86a16.c
804
(*(V + 30 + v - 1) > SIGMIN))) {
drivers/media/dvb-frontends/mb86a16.c
806
if (*(V + 30 + v) >= *(V + 30 + v - 1)) {
drivers/media/dvb-frontends/mb86a16.c
808
*SIG1 = *(V + 30 + v);
drivers/media/dvb-frontends/mb86a16.c
811
*SIG1 = *(V + 30 + v - 1);
drivers/media/dvb-frontends/mb86a16.c
816
} else if ((i % 2 == 0) && (v >= vmin)) {
drivers/media/dvb-frontends/mb86a16.c
818
if ((*(V + 30 + v) > 0) &&
drivers/media/dvb-frontends/mb86a16.c
819
(*(V + 30 + v + 1) > 0) &&
drivers/media/dvb-frontends/mb86a16.c
820
(*(V + 30 + v + 2) > 0) &&
drivers/media/dvb-frontends/mb86a16.c
821
(*(V + 30 + v + 1) > *(V + 30 + v)) &&
drivers/media/dvb-frontends/mb86a16.c
822
(*(V + 30 + v + 1) > *(V + 30 + v + 2)) &&
drivers/media/dvb-frontends/mb86a16.c
823
(*(V + 30 + v + 1) > SIGMIN)) {
drivers/media/dvb-frontends/mb86a16.c
826
*SIG1 = *(V + 30 + v + 1);
drivers/media/dvb-frontends/mb86a16.c
827
} else if ((v + 1 == vmax) &&
drivers/media/dvb-frontends/mb86a16.c
828
(*(V + 30 + v) >= 0) &&
drivers/media/dvb-frontends/mb86a16.c
829
(*(V + 30 + v + 1) >= 0) &&
drivers/media/dvb-frontends/mb86a16.c
830
(*(V + 30 + v + 1) > *(V + 30 + v)) &&
drivers/media/dvb-frontends/mb86a16.c
831
(*(V + 30 + v + 1) > SIGMIN)) {
drivers/media/dvb-frontends/mb86a16.c
834
*SIG1 = *(V + 30 + v);
drivers/media/dvb-frontends/mb86a16.c
835
} else if ((v == vmin) &&
drivers/media/dvb-frontends/mb86a16.c
836
(*(V + 30 + v) > 0) &&
drivers/media/dvb-frontends/mb86a16.c
837
(*(V + 30 + v + 1) > 0) &&
drivers/media/dvb-frontends/mb86a16.c
838
(*(V + 30 + v + 2) > 0) &&
drivers/media/dvb-frontends/mb86a16.c
839
(*(V + 30 + v) > *(V + 30 + v + 1)) &&
drivers/media/dvb-frontends/mb86a16.c
840
(*(V + 30 + v) > *(V + 30 + v + 2)) &&
drivers/media/dvb-frontends/mb86a16.c
841
(*(V + 30 + v) > SIGMIN)) {
drivers/media/dvb-frontends/mb86a16.c
844
*SIG1 = *(V + 30 + v);
drivers/media/dvb-frontends/mb86a16.c
845
} else if ((*(V + 30 + v) >= 0) &&
drivers/media/dvb-frontends/mb86a16.c
846
(*(V + 30 + v + 1) >= 0) &&
drivers/media/dvb-frontends/mb86a16.c
847
(*(V + 30 + v + 2) >= 0) &&
drivers/media/dvb-frontends/mb86a16.c
848
(*(V + 30 + v + 3) >= 0) &&
drivers/media/dvb-frontends/mb86a16.c
849
(*(V + 30 + v + 1) > *(V + 30 + v)) &&
drivers/media/dvb-frontends/mb86a16.c
850
(*(V + 30 + v + 2) > *(V + 30 + v + 3)) &&
drivers/media/dvb-frontends/mb86a16.c
851
((*(V + 30 + v + 1) > SIGMIN) ||
drivers/media/dvb-frontends/mb86a16.c
852
(*(V + 30 + v + 2) > SIGMIN))) {
drivers/media/dvb-frontends/mb86a16.c
854
if (*(V + 30 + v + 1) >= *(V + 30 + v + 2)) {
drivers/media/dvb-frontends/mb86a16.c
856
*SIG1 = *(V + 30 + v + 1);
drivers/media/dvb-frontends/mb86a16.c
859
*SIG1 = *(V + 30 + v + 2);
drivers/media/dvb-frontends/mb86a16.c
861
} else if ((*(V + 30 + v) >= 0) &&
drivers/media/dvb-frontends/mb86a16.c
862
(*(V + 30 + v + 1) >= 0) &&
drivers/media/dvb-frontends/mb86a16.c
863
(*(V + 30 + v + 2) >= 0) &&
drivers/media/dvb-frontends/mb86a16.c
864
(*(V + 30 + v + 3) >= 0) &&
drivers/media/dvb-frontends/mb86a16.c
865
(*(V + 30 + v) > *(V + 30 + v + 2)) &&
drivers/media/dvb-frontends/mb86a16.c
866
(*(V + 30 + v + 1) > *(V + 30 + v + 2)) &&
drivers/media/dvb-frontends/mb86a16.c
867
(*(V + 30 + v) > *(V + 30 + v + 3)) &&
drivers/media/dvb-frontends/mb86a16.c
868
(*(V + 30 + v + 1) > *(V + 30 + v + 3)) &&
drivers/media/dvb-frontends/mb86a16.c
869
((*(V + 30 + v) > SIGMIN) ||
drivers/media/dvb-frontends/mb86a16.c
870
(*(V + 30 + v + 1) > SIGMIN))) {
drivers/media/dvb-frontends/mb86a16.c
872
if (*(V + 30 + v) >= *(V + 30 + v + 1)) {
drivers/media/dvb-frontends/mb86a16.c
874
*SIG1 = *(V + 30 + v);
drivers/media/dvb-frontends/mb86a16.c
877
*SIG1 = *(V + 30 + v + 1);
drivers/media/dvb-frontends/mb86a16.c
879
} else if ((v + 2 == vmin) &&
drivers/media/dvb-frontends/mb86a16.c
880
(*(V + 30 + v) >= 0) &&
drivers/media/dvb-frontends/mb86a16.c
881
(*(V + 30 + v + 1) >= 0) &&
drivers/media/dvb-frontends/mb86a16.c
882
(*(V + 30 + v + 2) >= 0) &&
drivers/media/dvb-frontends/mb86a16.c
883
(*(V + 30 + v + 1) > *(V + 30 + v)) &&
drivers/media/dvb-frontends/mb86a16.c
884
(*(V + 30 + v + 2) > *(V + 30 + v)) &&
drivers/media/dvb-frontends/mb86a16.c
885
((*(V + 30 + v + 1) > SIGMIN) ||
drivers/media/dvb-frontends/mb86a16.c
886
(*(V + 30 + v + 2) > SIGMIN))) {
drivers/media/dvb-frontends/mb86a16.c
888
if (*(V + 30 + v + 1) >= *(V + 30 + v + 2)) {
drivers/media/dvb-frontends/mb86a16.c
890
*SIG1 = *(V + 30 + v + 1);
drivers/media/dvb-frontends/mb86a16.c
893
*SIG1 = *(V + 30 + v + 2);
drivers/media/dvb-frontends/mb86a16.c
895
} else if ((vmax == 0) && (vmin == 0) && (*(V + 30 + v) > SIGMIN)) {
drivers/media/dvb-frontends/mb86a16.c
897
*SIG1 = *(V + 30 + v);
drivers/media/dvb-frontends/mn88443x.c
404
u32 m, v;
drivers/media/dvb-frontends/mn88443x.c
442
v = ADCSET1_T_REFSEL_1_5V;
drivers/media/dvb-frontends/mn88443x.c
443
regmap_update_bits(r_t, ADCSET1_T, m, v);
drivers/media/dvb-frontends/mn88443x.c
446
v = AGCSET2_T_IFPOLINV_INC | AGCSET2_T_RFPOLINV_INC;
drivers/media/dvb-frontends/mn88443x.c
447
regmap_update_bits(r_t, AGCSET2_T, v, v);
drivers/media/dvb-frontends/mn88443x.c
461
u32 m, v;
drivers/media/dvb-frontends/mn88443x.c
464
v = MDSET_T_MDAUTO_AUTO | MDSET_T_FFTS_MODE3 | MDSET_T_GI_1_8;
drivers/media/dvb-frontends/mn88443x.c
465
regmap_update_bits(r_t, MDSET_T, m, v);
drivers/media/dvb-frontends/mt312.c
417
const enum fe_sec_voltage v)
drivers/media/dvb-frontends/mt312.c
423
if (v > SEC_VOLTAGE_OFF)
drivers/media/dvb-frontends/mt312.c
426
val = volt_tab[v];
drivers/media/dvb-frontends/mxl5xx.c
31
#define BYTE0(v) ((v >> 0) & 0xff)
drivers/media/dvb-frontends/mxl5xx.c
32
#define BYTE1(v) ((v >> 8) & 0xff)
drivers/media/dvb-frontends/mxl5xx.c
33
#define BYTE2(v) ((v >> 16) & 0xff)
drivers/media/dvb-frontends/mxl5xx.c
34
#define BYTE3(v) ((v >> 24) & 0xff)
drivers/media/dvb-frontends/rtl2832_sdr.c
1293
static void rtl2832_sdr_video_release(struct v4l2_device *v)
drivers/media/dvb-frontends/rtl2832_sdr.c
1296
container_of(v, struct rtl2832_sdr_dev, v4l2_dev);
drivers/media/dvb-frontends/rtl2832_sdr.c
953
struct v4l2_tuner *v)
drivers/media/dvb-frontends/rtl2832_sdr.c
959
dev_dbg(&pdev->dev, "index=%d type=%d\n", v->index, v->type);
drivers/media/dvb-frontends/rtl2832_sdr.c
961
if (v->index == 0) {
drivers/media/dvb-frontends/rtl2832_sdr.c
962
strscpy(v->name, "ADC: Realtek RTL2832", sizeof(v->name));
drivers/media/dvb-frontends/rtl2832_sdr.c
963
v->type = V4L2_TUNER_ADC;
drivers/media/dvb-frontends/rtl2832_sdr.c
964
v->capability = V4L2_TUNER_CAP_1HZ | V4L2_TUNER_CAP_FREQ_BANDS;
drivers/media/dvb-frontends/rtl2832_sdr.c
965
v->rangelow = 300000;
drivers/media/dvb-frontends/rtl2832_sdr.c
966
v->rangehigh = 3200000;
drivers/media/dvb-frontends/rtl2832_sdr.c
968
} else if (v->index == 1 &&
drivers/media/dvb-frontends/rtl2832_sdr.c
970
ret = v4l2_subdev_call(dev->v4l2_subdev, tuner, g_tuner, v);
drivers/media/dvb-frontends/rtl2832_sdr.c
971
} else if (v->index == 1) {
drivers/media/dvb-frontends/rtl2832_sdr.c
972
strscpy(v->name, "RF: <unknown>", sizeof(v->name));
drivers/media/dvb-frontends/rtl2832_sdr.c
973
v->type = V4L2_TUNER_RF;
drivers/media/dvb-frontends/rtl2832_sdr.c
974
v->capability = V4L2_TUNER_CAP_1HZ | V4L2_TUNER_CAP_FREQ_BANDS;
drivers/media/dvb-frontends/rtl2832_sdr.c
975
v->rangelow = 50000000;
drivers/media/dvb-frontends/rtl2832_sdr.c
976
v->rangehigh = 2000000000;
drivers/media/dvb-frontends/rtl2832_sdr.c
985
const struct v4l2_tuner *v)
drivers/media/dvb-frontends/rtl2832_sdr.c
993
if (v->index == 0) {
drivers/media/dvb-frontends/rtl2832_sdr.c
995
} else if (v->index == 1 &&
drivers/media/dvb-frontends/rtl2832_sdr.c
997
ret = v4l2_subdev_call(dev->v4l2_subdev, tuner, s_tuner, v);
drivers/media/dvb-frontends/rtl2832_sdr.c
998
} else if (v->index == 1) {
drivers/media/dvb-frontends/s5h1409.c
798
static int s5h1409_qam256_lookup_snr(struct dvb_frontend *fe, u16 *snr, u16 v)
drivers/media/dvb-frontends/s5h1409.c
804
if (v < qam256_snr_tab[i].val) {
drivers/media/dvb-frontends/s5h1409.c
813
static int s5h1409_qam64_lookup_snr(struct dvb_frontend *fe, u16 *snr, u16 v)
drivers/media/dvb-frontends/s5h1409.c
819
if (v < qam64_snr_tab[i].val) {
drivers/media/dvb-frontends/s5h1409.c
828
static int s5h1409_vsb_lookup_snr(struct dvb_frontend *fe, u16 *snr, u16 v)
drivers/media/dvb-frontends/s5h1409.c
834
if (v > vsb_snr_tab[i].val) {
drivers/media/dvb-frontends/s5h1411.c
712
static int s5h1411_qam256_lookup_snr(struct dvb_frontend *fe, u16 *snr, u16 v)
drivers/media/dvb-frontends/s5h1411.c
718
if (v < qam256_snr_tab[i].val) {
drivers/media/dvb-frontends/s5h1411.c
727
static int s5h1411_qam64_lookup_snr(struct dvb_frontend *fe, u16 *snr, u16 v)
drivers/media/dvb-frontends/s5h1411.c
733
if (v < qam64_snr_tab[i].val) {
drivers/media/dvb-frontends/s5h1411.c
742
static int s5h1411_vsb_lookup_snr(struct dvb_frontend *fe, u16 *snr, u16 v)
drivers/media/dvb-frontends/s5h1411.c
748
if (v > vsb_snr_tab[i].val) {
drivers/media/dvb-frontends/s5h1420.c
467
u8 v;
drivers/media/dvb-frontends/s5h1420.c
479
v = s5h1420_readreg(state, Loop01);
drivers/media/dvb-frontends/s5h1420.c
480
s5h1420_writereg(state, Loop01, v & 0x7f);
drivers/media/dvb-frontends/s5h1420.c
484
s5h1420_writereg(state, Loop01, v | 0x80);
drivers/media/dvb-frontends/s5h1420.c
496
u8 v;
drivers/media/dvb-frontends/s5h1420.c
506
v = s5h1420_readreg(state, Loop01);
drivers/media/dvb-frontends/s5h1420.c
507
s5h1420_writereg(state, Loop01, v & 0xbf);
drivers/media/dvb-frontends/s5h1420.c
511
s5h1420_writereg(state, Loop01, v | 0x40);
drivers/media/dvb-frontends/tc90522.c
212
u8 v;
drivers/media/dvb-frontends/tc90522.c
217
v = (val[2] & 0x70) >> 4;
drivers/media/dvb-frontends/tc90522.c
218
c->modulation = (v == 7) ? PSK_8 : QPSK;
drivers/media/dvb-frontends/tc90522.c
219
c->fec_inner = fec_conv_sat[v];
drivers/media/dvb-frontends/tc90522.c
225
v = (val[2] & 0x07);
drivers/media/dvb-frontends/tc90522.c
226
c->layer[1].fec = fec_conv_sat[v];
drivers/media/dvb-frontends/tc90522.c
227
if (v == 0) /* no low layer */
drivers/media/dvb-frontends/tc90522.c
236
layers = (v > 0) ? 2 : 1;
drivers/media/dvb-frontends/tc90522.c
354
u8 v;
drivers/media/dvb-frontends/tc90522.c
360
v = (val[2] & 0x78) >> 3;
drivers/media/dvb-frontends/tc90522.c
361
if (v == 0x0f)
drivers/media/dvb-frontends/tc90522.c
365
c->layer[0].segment_count = v;
drivers/media/dvb-frontends/tc90522.c
368
v = (val[1] & 0x03) << 1 | (val[2] & 0x80) >> 7;
drivers/media/dvb-frontends/tc90522.c
369
c->layer[0].interleaving = v;
drivers/media/dvb-frontends/tc90522.c
373
v = (val[3] & 0x03) << 2 | (val[4] & 0xc0) >> 6;
drivers/media/dvb-frontends/tc90522.c
374
if (v == 0x0f)
drivers/media/dvb-frontends/tc90522.c
378
c->layer[1].segment_count = v;
drivers/media/dvb-frontends/tc90522.c
385
v = (val[5] & 0x1e) >> 1;
drivers/media/dvb-frontends/tc90522.c
386
if (v == 0x0f)
drivers/media/dvb-frontends/tc90522.c
390
c->layer[2].segment_count = v;
drivers/media/dvb-frontends/tda10023.c
100
u8 r,m,v;
drivers/media/dvb-frontends/tda10023.c
104
v=*tab++;
drivers/media/dvb-frontends/tda10023.c
112
tda10023_writebit(state,r,m,v);
drivers/media/dvb-frontends/tda10048.c
1001
v = tda10048_readreg(state, TDA10048_NP_OUT);
drivers/media/dvb-frontends/tda10048.c
1003
if (v <= snr_tab[i].val) {
drivers/media/dvb-frontends/tda10048.c
850
u8 v;
drivers/media/dvb-frontends/tda10048.c
856
v = tda10048_readreg(state, TDA10048_NP_OUT);
drivers/media/dvb-frontends/tda10048.c
857
if (v > 0)
drivers/media/dvb-frontends/tda10048.c
858
*signal_strength -= (v << 8) | v;
drivers/media/dvb-frontends/tda10048.c
996
u8 v;
drivers/media/firewire/firedtv-avc.c
1370
#define get_opcr_online(v) get_opcr((v), 0x1, 31)
drivers/media/firewire/firedtv-avc.c
1371
#define get_opcr_p2p_connections(v) get_opcr((v), 0x3f, 24)
drivers/media/firewire/firedtv-avc.c
1372
#define get_opcr_channel(v) get_opcr((v), 0x3f, 16)
drivers/media/firewire/firedtv-avc.c
1374
#define set_opcr_p2p_connections(p, v) set_opcr((p), (v), 0x3f, 24)
drivers/media/firewire/firedtv-avc.c
1375
#define set_opcr_channel(p, v) set_opcr((p), (v), 0x3f, 16)
drivers/media/firewire/firedtv-avc.c
1376
#define set_opcr_data_rate(p, v) set_opcr((p), (v), 0x3, 14)
drivers/media/firewire/firedtv-avc.c
1377
#define set_opcr_overhead_id(p, v) set_opcr((p), (v), 0xf, 10)
drivers/media/i2c/adv748x/adv748x.h
395
#define io_write(s, r, v) adv748x_write(s, ADV748X_PAGE_IO, r, v)
drivers/media/i2c/adv748x/adv748x.h
396
#define io_clrset(s, r, m, v) io_write(s, r, (io_read(s, r) & ~(m)) | (v))
drivers/media/i2c/adv748x/adv748x.h
400
#define hdmi_write(s, r, v) adv748x_write(s, ADV748X_PAGE_HDMI, r, v)
drivers/media/i2c/adv748x/adv748x.h
403
#define repeater_write(s, r, v) adv748x_write(s, ADV748X_PAGE_REPEATER, r, v)
drivers/media/i2c/adv748x/adv748x.h
406
#define sdp_write(s, r, v) adv748x_write(s, ADV748X_PAGE_SDP, r, v)
drivers/media/i2c/adv748x/adv748x.h
407
#define sdp_clrset(s, r, m, v) sdp_write(s, r, (sdp_read(s, r) & ~(m)) | (v))
drivers/media/i2c/adv748x/adv748x.h
410
#define cp_write(s, r, v) adv748x_write(s, ADV748X_PAGE_CP, r, v)
drivers/media/i2c/adv748x/adv748x.h
411
#define cp_clrset(s, r, m, v) cp_write(s, r, (cp_read(s, r) & ~(m)) | (v))
drivers/media/i2c/adv748x/adv748x.h
414
#define tx_write(t, r, v) adv748x_write(t->state, t->page, r, v)
drivers/media/i2c/adv7604.c
3262
u32 v;
drivers/media/i2c/adv7604.c
3276
if (!of_property_read_u32(np, "default-input", &v))
drivers/media/i2c/adv7604.c
3277
state->pdata.default_input = v;
drivers/media/i2c/ar0521.c
149
static u32 div64_round(u64 v, u32 d)
drivers/media/i2c/ar0521.c
151
return div_u64(v + (d >> 1), d);
drivers/media/i2c/ar0521.c
154
static u32 div64_round_up(u64 v, u32 d)
drivers/media/i2c/ar0521.c
156
return div_u64(v + d - 1, d);
drivers/media/i2c/ccs/ccs-core.c
1408
u32 v;
drivers/media/i2c/ccs/ccs-core.c
1410
rval = ccs_read(sensor, DATA_TRANSFER_IF_1_DATA(i), &v);
drivers/media/i2c/ccs/ccs-core.c
1414
*nvm++ = v;
drivers/media/i2c/ccs/ccs-core.c
3521
u32 v;
drivers/media/i2c/ccs/ccs-core.c
3524
rval = ccs_read(sensor, PLL_MODE, &v);
drivers/media/i2c/ccs/ccs-core.c
3528
if (v == CCS_PLL_MODE_DUAL)
drivers/media/i2c/ccs/ccs-data.c
136
const struct __ccs_data_block_version *v = payload;
drivers/media/i2c/ccs/ccs-data.c
139
if (v + 1 != endp)
drivers/media/i2c/ccs/ccs-data.c
152
vv->version_major = ((u16)v->static_data_version_major[0] << 8) +
drivers/media/i2c/ccs/ccs-data.c
153
v->static_data_version_major[1];
drivers/media/i2c/ccs/ccs-data.c
154
vv->version_minor = ((u16)v->static_data_version_minor[0] << 8) +
drivers/media/i2c/ccs/ccs-data.c
155
v->static_data_version_minor[1];
drivers/media/i2c/ccs/ccs-data.c
156
vv->date_year = ((u16)v->year[0] << 8) + v->year[1];
drivers/media/i2c/ccs/ccs-data.c
157
vv->date_month = v->month;
drivers/media/i2c/ccs/ccs-data.c
158
vv->date_day = v->day;
drivers/media/i2c/ccs/ccs-data.c
164
struct ccs_data_block_version *v)
drivers/media/i2c/ccs/ccs-data.c
168
v->version_major, v->version_minor,
drivers/media/i2c/ccs/ccs-data.c
169
v->date_year, v->date_month, v->date_day);
drivers/media/i2c/cs5345.c
102
u8 v = cs5345_read(sd, 0x09) & 7;
drivers/media/i2c/cs5345.c
106
v4l2_info(sd, "Input: %d%s\n", v,
drivers/media/i2c/cs53l32a.c
155
u8 v = cs53l32a_read(sd, i);
drivers/media/i2c/cs53l32a.c
157
v4l2_dbg(1, debug, sd, "Read Reg %d %02x\n", i, v);
drivers/media/i2c/cs53l32a.c
186
u8 v = cs53l32a_read(sd, i);
drivers/media/i2c/cs53l32a.c
188
v4l2_dbg(1, debug, sd, "Read Reg %d %02x\n", i, v);
drivers/media/i2c/cs53l32a.c
96
u8 v = cs53l32a_read(sd, 0x01);
drivers/media/i2c/cs53l32a.c
98
v4l2_info(sd, "Input: %d\n", (v >> 4) & 3);
drivers/media/i2c/cx25840/cx25840-core.c
2363
u8 v;
drivers/media/i2c/cx25840/cx25840-core.c
2372
v = cx25840_read(client, 0x115) | 0x80;
drivers/media/i2c/cx25840/cx25840-core.c
2373
cx25840_write(client, 0x115, v);
drivers/media/i2c/cx25840/cx25840-core.c
2374
v = cx25840_read(client, 0x116) | 0x03;
drivers/media/i2c/cx25840/cx25840-core.c
2375
cx25840_write(client, 0x116, v);
drivers/media/i2c/cx25840/cx25840-core.c
2377
v = cx25840_read(client, 0x115) & ~(0x80);
drivers/media/i2c/cx25840/cx25840-core.c
2378
cx25840_write(client, 0x115, v);
drivers/media/i2c/cx25840/cx25840-core.c
2379
v = cx25840_read(client, 0x116) & ~(0x03);
drivers/media/i2c/cx25840/cx25840-core.c
2380
cx25840_write(client, 0x116, v);
drivers/media/i2c/cx25840/cx25840-core.c
2389
u8 v;
drivers/media/i2c/cx25840/cx25840-core.c
2405
v = cx25840_read(client, 0x115) | 0x0c;
drivers/media/i2c/cx25840/cx25840-core.c
2406
cx25840_write(client, 0x115, v);
drivers/media/i2c/cx25840/cx25840-core.c
2407
v = cx25840_read(client, 0x116) | 0x04;
drivers/media/i2c/cx25840/cx25840-core.c
2408
cx25840_write(client, 0x116, v);
drivers/media/i2c/cx25840/cx25840-core.c
2410
v = cx25840_read(client, 0x115) & ~(0x0c);
drivers/media/i2c/cx25840/cx25840-core.c
2411
cx25840_write(client, 0x115, v);
drivers/media/i2c/cx25840/cx25840-core.c
2412
v = cx25840_read(client, 0x116) & ~(0x04);
drivers/media/i2c/cx25840/cx25840-core.c
2413
cx25840_write(client, 0x116, v);
drivers/media/i2c/cx25840/cx25840-ir.c
360
u32 v;
drivers/media/i2c/cx25840/cx25840-ir.c
364
v = CNTRL_WIN_3_4;
drivers/media/i2c/cx25840/cx25840-ir.c
367
v = CNTRL_WIN_3_3;
drivers/media/i2c/cx25840/cx25840-ir.c
372
v |= CNTRL_WIN_4_3;
drivers/media/i2c/cx25840/cx25840-ir.c
375
v |= CNTRL_WIN_3_3;
drivers/media/i2c/cx25840/cx25840-ir.c
378
cx25840_and_or4(c, CX25840_IR_CNTRL_REG, ~CNTRL_WIN, v);
drivers/media/i2c/cx25840/cx25840-ir.c
497
u32 events, v;
drivers/media/i2c/cx25840/cx25840-ir.c
568
for (i = 0, v = FIFO_RX_NDV;
drivers/media/i2c/cx25840/cx25840-ir.c
569
(v & FIFO_RX_NDV) && !kror; i = 0) {
drivers/media/i2c/cx25840/cx25840-ir.c
571
(v & FIFO_RX_NDV) && j < FIFO_RX_DEPTH; j++) {
drivers/media/i2c/cx25840/cx25840-ir.c
572
v = cx25840_read4(c, CX25840_IR_FIFO_REG);
drivers/media/i2c/cx25840/cx25840-ir.c
573
rx_data[i].hw_fifo_data = v & ~FIFO_RX_NDV;
drivers/media/i2c/cx25840/cx25840-ir.c
589
v = 0;
drivers/media/i2c/cx25840/cx25840-ir.c
599
v |= CNTRL_RFE;
drivers/media/i2c/cx25840/cx25840-ir.c
608
v |= CNTRL_RXE;
drivers/media/i2c/cx25840/cx25840-ir.c
611
if (v) {
drivers/media/i2c/cx25840/cx25840-ir.c
613
cx25840_write4(c, CX25840_IR_CNTRL_REG, cntrl & ~v);
drivers/media/i2c/cx25840/cx25840-ir.c
636
unsigned u, v, w;
drivers/media/i2c/cx25840/cx25840-ir.c
670
v = (unsigned) pulse_width_count_to_ns(
drivers/media/i2c/cx25840/cx25840-ir.c
672
if (v > IR_MAX_DURATION)
drivers/media/i2c/cx25840/cx25840-ir.c
673
v = IR_MAX_DURATION;
drivers/media/i2c/cx25840/cx25840-ir.c
676
{ .pulse = u, .duration = v, .timeout = w };
drivers/media/i2c/cx25840/cx25840-ir.c
679
v, u ? "mark" : "space", w ? "(timed out)" : "");
drivers/media/i2c/cx25840/cx25840-vbi.c
105
u8 v = cx25840_read(client,
drivers/media/i2c/cx25840/cx25840-vbi.c
108
svbi->service_lines[0][i] = lcr2vbi[v >> 4];
drivers/media/i2c/cx25840/cx25840-vbi.c
109
svbi->service_lines[1][i] = lcr2vbi[v & 0xf];
drivers/media/i2c/cx25840/cx25840-vbi.c
95
u8 v = cx25840_read(client,
drivers/media/i2c/cx25840/cx25840-vbi.c
98
svbi->service_lines[0][i] = lcr2vbi[v >> 4];
drivers/media/i2c/cx25840/cx25840-vbi.c
99
svbi->service_lines[1][i] = lcr2vbi[v & 0xf];
drivers/media/i2c/ds90ub913.c
124
unsigned int v;
drivers/media/i2c/ds90ub913.c
130
ret = regmap_read(priv->regmap, reg, &v);
drivers/media/i2c/ds90ub913.c
137
*val = v;
drivers/media/i2c/ds90ub913.c
499
u8 v, v1, v2;
drivers/media/i2c/ds90ub913.c
502
ret = ub913_read(priv, UB913_REG_MODE_SEL, &v, NULL);
drivers/media/i2c/ds90ub913.c
506
dev_info(dev, "MODE_SEL %#02x\n", v);
drivers/media/i2c/ds90ub913.c
516
ub913_read(priv, UB913_REG_GENERAL_CFG, &v, &ret);
drivers/media/i2c/ds90ub913.c
518
v | UB913_REG_GENERAL_CFG_CRC_ERR_RESET, &ret);
drivers/media/i2c/ds90ub913.c
519
ub913_write(priv, UB913_REG_GENERAL_CFG, v, &ret);
drivers/media/i2c/ds90ub913.c
524
ret = ub913_read(priv, UB913_REG_GENERAL_STATUS, &v, NULL);
drivers/media/i2c/ds90ub913.c
528
dev_info(dev, "GENERAL_STATUS %#02x\n", v);
drivers/media/i2c/ds90ub913.c
530
ret = ub913_read(priv, UB913_REG_PLL_OVR, &v, NULL);
drivers/media/i2c/ds90ub913.c
534
dev_info(dev, "PLL_OVR %#02x\n", v);
drivers/media/i2c/ds90ub913.c
765
u8 v;
drivers/media/i2c/ds90ub913.c
767
ret = ub913_read(priv, UB913_REG_MODE_SEL, &v, NULL);
drivers/media/i2c/ds90ub913.c
771
if (!(v & UB913_REG_MODE_SEL_MODE_UP_TO_DATE))
drivers/media/i2c/ds90ub913.c
775
mode_override = v & UB913_REG_MODE_SEL_MODE_OVERRIDE;
drivers/media/i2c/ds90ub913.c
776
mode = v & UB913_REG_MODE_SEL_MODE_MASK;
drivers/media/i2c/ds90ub953.c
108
unsigned int v;
drivers/media/i2c/ds90ub953.c
116
ret = regmap_read(priv->regmap, reg, &v);
drivers/media/i2c/ds90ub953.c
1170
u8 v;
drivers/media/i2c/ds90ub953.c
1172
ret = ub953_read(priv, UB953_REG_MODE_SEL, &v, NULL);
drivers/media/i2c/ds90ub953.c
1176
if (!(v & UB953_REG_MODE_SEL_MODE_DONE))
drivers/media/i2c/ds90ub953.c
1179
mode_override = v & UB953_REG_MODE_SEL_MODE_OVERRIDE;
drivers/media/i2c/ds90ub953.c
1181
switch (v & UB953_REG_MODE_SEL_MODE_MASK) {
drivers/media/i2c/ds90ub953.c
1212
ret = ub953_read(priv, UB953_REG_REV_MASK_ID, &v, NULL);
drivers/media/i2c/ds90ub953.c
1216
dev_info(dev, "Found %s rev/mask %#04x\n", priv->hw_data->model, v);
drivers/media/i2c/ds90ub953.c
1218
ret = ub953_read(priv, UB953_REG_GENERAL_CFG, &v, NULL);
drivers/media/i2c/ds90ub953.c
1223
(v & UB953_REG_GENERAL_CFG_I2C_STRAP_MODE) ? "1.8" : "3.3");
drivers/media/i2c/ds90ub953.c
1229
v = 0;
drivers/media/i2c/ds90ub953.c
123
*val = v;
drivers/media/i2c/ds90ub953.c
1230
v |= priv->non_continous_clk ? 0 : UB953_REG_GENERAL_CFG_CONT_CLK;
drivers/media/i2c/ds90ub953.c
1231
v |= (priv->num_data_lanes - 1) <<
drivers/media/i2c/ds90ub953.c
1233
v |= UB953_REG_GENERAL_CFG_CRC_TX_GEN_ENABLE;
drivers/media/i2c/ds90ub953.c
1235
ret = ub953_write(priv, UB953_REG_GENERAL_CFG, v, NULL);
drivers/media/i2c/ds90ub953.c
1239
v = 1U << UB953_REG_I2C_CONTROL2_SDA_OUTPUT_SETUP_SHIFT;
drivers/media/i2c/ds90ub953.c
1240
v |= UB953_REG_I2C_CONTROL2_BUS_SPEEDUP;
drivers/media/i2c/ds90ub953.c
1242
ret = ub953_write(priv, UB953_REG_I2C_CONTROL2, v, NULL);
drivers/media/i2c/ds90ub953.c
180
unsigned int v;
drivers/media/i2c/ds90ub953.c
200
ret = regmap_read(priv->regmap, UB953_REG_IND_ACC_DATA, &v);
drivers/media/i2c/ds90ub953.c
208
*val = v;
drivers/media/i2c/ds90ub953.c
265
u8 v;
drivers/media/i2c/ds90ub953.c
267
ret = ub953_read(priv, UB953_REG_GPIO_INPUT_CTRL, &v, NULL);
drivers/media/i2c/ds90ub953.c
271
if (v & UB953_REG_GPIO_INPUT_CTRL_INPUT_EN(offset))
drivers/media/i2c/ds90ub953.c
311
u8 v;
drivers/media/i2c/ds90ub953.c
313
ret = ub953_read(priv, UB953_REG_GPIO_PIN_STS, &v, NULL);
drivers/media/i2c/ds90ub953.c
317
return !!(v & UB953_REG_GPIO_PIN_STS_GPIO_STS(offset));
drivers/media/i2c/ds90ub953.c
550
u8 v, v1, v2;
drivers/media/i2c/ds90ub953.c
561
ret = ub953_read(priv, UB953_REG_GENERAL_STATUS, &v, NULL);
drivers/media/i2c/ds90ub953.c
565
dev_info(dev, "GENERAL_STATUS %#02x\n", v);
drivers/media/i2c/ds90ub953.c
580
ret = ub953_read(priv, UB953_REG_CSI_ERR_CNT, &v, NULL);
drivers/media/i2c/ds90ub953.c
584
dev_info(dev, "CSI error count %u\n", v);
drivers/media/i2c/ds90ub953.c
586
ret = ub953_read(priv, UB953_REG_CSI_ERR_STATUS, &v, NULL);
drivers/media/i2c/ds90ub953.c
590
dev_info(dev, "CSI_ERR_STATUS %#02x\n", v);
drivers/media/i2c/ds90ub953.c
592
ret = ub953_read(priv, UB953_REG_CSI_ERR_DLANE01, &v, NULL);
drivers/media/i2c/ds90ub953.c
596
dev_info(dev, "CSI_ERR_DLANE01 %#02x\n", v);
drivers/media/i2c/ds90ub953.c
598
ret = ub953_read(priv, UB953_REG_CSI_ERR_DLANE23, &v, NULL);
drivers/media/i2c/ds90ub953.c
602
dev_info(dev, "CSI_ERR_DLANE23 %#02x\n", v);
drivers/media/i2c/ds90ub953.c
604
ret = ub953_read(priv, UB953_REG_CSI_ERR_CLK_LANE, &v, NULL);
drivers/media/i2c/ds90ub953.c
608
dev_info(dev, "CSI_ERR_CLK_LANE %#02x\n", v);
drivers/media/i2c/ds90ub953.c
610
ret = ub953_read(priv, UB953_REG_CSI_PKT_HDR_VC_ID, &v, NULL);
drivers/media/i2c/ds90ub953.c
614
dev_info(dev, "CSI packet header VC %u ID %u\n", v >> 6, v & 0x3f);
drivers/media/i2c/ds90ub953.c
623
ret = ub953_read(priv, UB953_REG_CSI_ECC, &v, NULL);
drivers/media/i2c/ds90ub953.c
627
dev_info(dev, "CSI ECC %#02x\n", v);
drivers/media/i2c/ds90ub960.c
1005
unsigned int v;
drivers/media/i2c/ds90ub960.c
1017
ret = regmap_read(priv->regmap, reg, &v);
drivers/media/i2c/ds90ub960.c
1024
*val = v;
drivers/media/i2c/ds90ub960.c
1119
unsigned int v;
drivers/media/i2c/ds90ub960.c
1139
ret = regmap_read(priv->regmap, UB960_SR_IND_ACC_DATA, &v);
drivers/media/i2c/ds90ub960.c
1147
*val = v;
drivers/media/i2c/ds90ub960.c
1242
unsigned int v;
drivers/media/i2c/ds90ub960.c
1255
ret = regmap_read_poll_timeout(priv->regmap, UB960_SR_RESET, v,
drivers/media/i2c/ds90ub960.c
1256
(v & bit) == 0, 2000, 100000);
drivers/media/i2c/ds90ub960.c
1501
u8 v;
drivers/media/i2c/ds90ub960.c
1503
ub960_rxport_read(priv, nport, UB960_RR_RX_PORT_STS1, &v, &ret);
drivers/media/i2c/ds90ub960.c
1504
ub960_rxport_read(priv, nport, UB960_RR_RX_PORT_STS2, &v, &ret);
drivers/media/i2c/ds90ub960.c
1505
ub960_rxport_read(priv, nport, UB960_RR_CSI_RX_STS, &v, &ret);
drivers/media/i2c/ds90ub960.c
1506
ub960_rxport_read(priv, nport, UB960_RR_BCC_STATUS, &v, &ret);
drivers/media/i2c/ds90ub960.c
1508
ub960_rxport_read(priv, nport, UB960_RR_RX_PAR_ERR_HI, &v, &ret);
drivers/media/i2c/ds90ub960.c
1509
ub960_rxport_read(priv, nport, UB960_RR_RX_PAR_ERR_LO, &v, &ret);
drivers/media/i2c/ds90ub960.c
1511
ub960_rxport_read(priv, nport, UB960_RR_CSI_ERR_COUNTER, &v, &ret);
drivers/media/i2c/ds90ub960.c
1532
u8 v;
drivers/media/i2c/ds90ub960.c
1537
UB960_IR_RX_ANA_STROBE_SET_CLK, &v, NULL);
drivers/media/i2c/ds90ub960.c
1541
clk_delay = (v & UB960_IR_RX_ANA_STROBE_SET_CLK_NO_EXTRA_DELAY) ?
drivers/media/i2c/ds90ub960.c
1545
UB960_IR_RX_ANA_STROBE_SET_DATA, &v, NULL);
drivers/media/i2c/ds90ub960.c
1549
data_delay = (v & UB960_IR_RX_ANA_STROBE_SET_DATA_NO_EXTRA_DELAY) ?
drivers/media/i2c/ds90ub960.c
1552
ret = ub960_rxport_read(priv, nport, UB960_RR_SFILTER_STS_0, &v, NULL);
drivers/media/i2c/ds90ub960.c
1556
clk_delay += v & UB960_IR_RX_ANA_STROBE_SET_CLK_DELAY_MASK;
drivers/media/i2c/ds90ub960.c
1558
ret = ub960_rxport_read(priv, nport, UB960_RR_SFILTER_STS_1, &v, NULL);
drivers/media/i2c/ds90ub960.c
1562
data_delay += v & UB960_IR_RX_ANA_STROBE_SET_DATA_DELAY_MASK;
drivers/media/i2c/ds90ub960.c
1613
u8 v;
drivers/media/i2c/ds90ub960.c
1615
ret = ub960_rxport_read(priv, nport, UB960_RR_AEQ_STATUS, &v, NULL);
drivers/media/i2c/ds90ub960.c
1619
*eq_level = (v & UB960_RR_AEQ_STATUS_STATUS_1) +
drivers/media/i2c/ds90ub960.c
1620
(v & UB960_RR_AEQ_STATUS_STATUS_2);
drivers/media/i2c/ds90ub960.c
1631
u8 v;
drivers/media/i2c/ds90ub960.c
1641
ret = ub960_rxport_read(priv, nport, UB960_RR_AEQ_BYPASS, &v, NULL);
drivers/media/i2c/ds90ub960.c
1645
v &= ~(UB960_RR_AEQ_BYPASS_EQ_STAGE1_VALUE_MASK |
drivers/media/i2c/ds90ub960.c
1647
v |= eq_stage_1_select_value << UB960_RR_AEQ_BYPASS_EQ_STAGE1_VALUE_SHIFT;
drivers/media/i2c/ds90ub960.c
1648
v |= eq_stage_2_select_value << UB960_RR_AEQ_BYPASS_EQ_STAGE2_VALUE_SHIFT;
drivers/media/i2c/ds90ub960.c
1649
v |= UB960_RR_AEQ_BYPASS_ENABLE;
drivers/media/i2c/ds90ub960.c
1651
ret = ub960_rxport_write(priv, nport, UB960_RR_AEQ_BYPASS, v, NULL);
drivers/media/i2c/ds90ub960.c
1911
u16 v;
drivers/media/i2c/ds90ub960.c
1922
&v, NULL);
drivers/media/i2c/ds90ub960.c
1929
nport, ((u64)v * HZ_PER_MHZ) >> 8);
drivers/media/i2c/ds90ub960.c
1943
((u64)v * HZ_PER_MHZ) >> 8);
drivers/media/i2c/ds90ub960.c
3296
u16 v;
drivers/media/i2c/ds90ub960.c
3299
&v, NULL);
drivers/media/i2c/ds90ub960.c
3301
dev_err(dev, "rx%u parity errors: %u\n", nport, v);
drivers/media/i2c/ds90ub960.c
3356
u16 v;
drivers/media/i2c/ds90ub960.c
3359
&v, NULL);
drivers/media/i2c/ds90ub960.c
3361
dev_dbg(dev, "rx%u line len changed: %u\n", nport, v);
drivers/media/i2c/ds90ub960.c
3365
u16 v;
drivers/media/i2c/ds90ub960.c
3368
&v, NULL);
drivers/media/i2c/ds90ub960.c
3370
dev_dbg(dev, "rx%u line count changed: %u\n", nport, v);
drivers/media/i2c/ds90ub960.c
4065
u8 v;
drivers/media/i2c/ds90ub960.c
4069
ret = ub960_read(priv, UB960_XR_AEQ_CTL1, &v, NULL);
drivers/media/i2c/ds90ub960.c
4074
(v & UB960_XR_AEQ_CTL1_AEQ_SFILTER_EN) ? "Adaptive" :
drivers/media/i2c/ds90ub960.c
4077
if (v & UB960_XR_AEQ_CTL1_AEQ_SFILTER_EN) {
drivers/media/i2c/ds90ub960.c
4078
ret = ub960_read(priv, UB960_XR_SFILTER_CFG, &v, NULL);
drivers/media/i2c/ds90ub960.c
4083
((v >> UB960_XR_SFILTER_CFG_SFILTER_MIN_SHIFT) & 0xf) - 7,
drivers/media/i2c/ds90ub960.c
4084
((v >> UB960_XR_SFILTER_CFG_SFILTER_MAX_SHIFT) & 0xf) - 7);
drivers/media/i2c/ds90ub960.c
4095
ret = ub960_rxport_read(priv, nport, UB960_RR_AEQ_BYPASS, &v, NULL);
drivers/media/i2c/ds90ub960.c
4100
(v & UB960_RR_AEQ_BYPASS_ENABLE) ? "Manual" :
drivers/media/i2c/ds90ub960.c
4103
if (!(v & UB960_RR_AEQ_BYPASS_ENABLE)) {
drivers/media/i2c/ds90ub960.c
4104
ret = ub960_rxport_read(priv, nport, UB960_RR_AEQ_MIN_MAX, &v,
drivers/media/i2c/ds90ub960.c
4110
(v >> UB960_RR_AEQ_MIN_MAX_AEQ_FLOOR_SHIFT) & 0xf,
drivers/media/i2c/ds90ub960.c
4111
(v >> UB960_RR_AEQ_MIN_MAX_AEQ_MAX_SHIFT) & 0xf);
drivers/media/i2c/ds90ub960.c
4129
u8 v = 0;
drivers/media/i2c/ds90ub960.c
4154
ret = ub960_txport_read(priv, nport, UB960_TR_CSI_STS, &v, NULL);
drivers/media/i2c/ds90ub960.c
4158
dev_info(dev, "\tsync %u, pass %u\n", v & (u8)BIT(1),
drivers/media/i2c/ds90ub960.c
4159
v & (u8)BIT(0));
drivers/media/i2c/ds90ub960.c
4200
ret = ub960_rxport_read(priv, nport, UB960_RR_RX_PORT_STS1, &v,
drivers/media/i2c/ds90ub960.c
4205
if (v & UB960_RR_RX_PORT_STS1_LOCK_STS)
drivers/media/i2c/ds90ub960.c
4210
dev_info(dev, "\trx_port_sts1 %#02x\n", v);
drivers/media/i2c/ds90ub960.c
4211
ret = ub960_rxport_read(priv, nport, UB960_RR_RX_PORT_STS2, &v,
drivers/media/i2c/ds90ub960.c
4216
dev_info(dev, "\trx_port_sts2 %#02x\n", v);
drivers/media/i2c/ds90ub960.c
4247
&v, NULL);
drivers/media/i2c/ds90ub960.c
4251
dev_info(dev, "\tcsi_err_counter %u\n", v);
drivers/media/i2c/ds90ub960.c
4267
ret = ub960_rxport_read(priv, nport, ctl_reg, &v, NULL);
drivers/media/i2c/ds90ub960.c
4272
(v >> ctl_shift) & 0xf);
drivers/media/i2c/ds90ub960.c
58
#define MHZ(v) ((u32)((v) * HZ_PER_MHZ))
drivers/media/i2c/ds90ub960.c
727
unsigned int v;
drivers/media/i2c/ds90ub960.c
735
ret = regmap_read(priv->regmap, reg, &v);
drivers/media/i2c/ds90ub960.c
742
*val = v;
drivers/media/i2c/ds90ub960.c
856
unsigned int v;
drivers/media/i2c/ds90ub960.c
868
ret = regmap_read(priv->regmap, reg, &v);
drivers/media/i2c/ds90ub960.c
875
*val = v;
drivers/media/i2c/max96714.c
82
#define MHZ(v) ((u32)((v) * 1000000U))
drivers/media/i2c/ov5648.c
101
#define OV5648_SRB_CTRL_SCLK_DIV(v) (((v) << 2) & GENMASK(3, 2))
drivers/media/i2c/ov5648.c
120
#define OV5648_EXPOSURE_CTRL_HH(v) (((v) & GENMASK(19, 16)) >> 16)
drivers/media/i2c/ov5648.c
121
#define OV5648_EXPOSURE_CTRL_HH_VALUE(v) (((v) << 16) & GENMASK(19, 16))
drivers/media/i2c/ov5648.c
123
#define OV5648_EXPOSURE_CTRL_H(v) (((v) & GENMASK(15, 8)) >> 8)
drivers/media/i2c/ov5648.c
124
#define OV5648_EXPOSURE_CTRL_H_VALUE(v) (((v) << 8) & GENMASK(15, 8))
drivers/media/i2c/ov5648.c
126
#define OV5648_EXPOSURE_CTRL_L(v) ((v) & GENMASK(7, 0))
drivers/media/i2c/ov5648.c
127
#define OV5648_EXPOSURE_CTRL_L_VALUE(v) ((v) & GENMASK(7, 0))
drivers/media/i2c/ov5648.c
129
#define OV5648_MANUAL_CTRL_FRAME_DELAY(v) (((v) << 4) & GENMASK(5, 4))
drivers/media/i2c/ov5648.c
133
#define OV5648_GAIN_CTRL_H(v) (((v) & GENMASK(9, 8)) >> 8)
drivers/media/i2c/ov5648.c
134
#define OV5648_GAIN_CTRL_H_VALUE(v) (((v) << 8) & GENMASK(9, 8))
drivers/media/i2c/ov5648.c
136
#define OV5648_GAIN_CTRL_L(v) ((v) & GENMASK(7, 0))
drivers/media/i2c/ov5648.c
137
#define OV5648_GAIN_CTRL_L_VALUE(v) ((v) & GENMASK(7, 0))
drivers/media/i2c/ov5648.c
217
#define OV5648_CROP_START_X_H(v) (((v) & GENMASK(11, 8)) >> 8)
drivers/media/i2c/ov5648.c
219
#define OV5648_CROP_START_X_L(v) ((v) & GENMASK(7, 0))
drivers/media/i2c/ov5648.c
221
#define OV5648_CROP_START_Y_H(v) (((v) & GENMASK(11, 8)) >> 8)
drivers/media/i2c/ov5648.c
223
#define OV5648_CROP_START_Y_L(v) ((v) & GENMASK(7, 0))
drivers/media/i2c/ov5648.c
225
#define OV5648_CROP_END_X_H(v) (((v) & GENMASK(11, 8)) >> 8)
drivers/media/i2c/ov5648.c
227
#define OV5648_CROP_END_X_L(v) ((v) & GENMASK(7, 0))
drivers/media/i2c/ov5648.c
229
#define OV5648_CROP_END_Y_H(v) (((v) & GENMASK(11, 8)) >> 8)
drivers/media/i2c/ov5648.c
231
#define OV5648_CROP_END_Y_L(v) ((v) & GENMASK(7, 0))
drivers/media/i2c/ov5648.c
233
#define OV5648_OUTPUT_SIZE_X_H(v) (((v) & GENMASK(11, 8)) >> 8)
drivers/media/i2c/ov5648.c
235
#define OV5648_OUTPUT_SIZE_X_L(v) ((v) & GENMASK(7, 0))
drivers/media/i2c/ov5648.c
237
#define OV5648_OUTPUT_SIZE_Y_H(v) (((v) & GENMASK(11, 8)) >> 8)
drivers/media/i2c/ov5648.c
239
#define OV5648_OUTPUT_SIZE_Y_L(v) ((v) & GENMASK(7, 0))
drivers/media/i2c/ov5648.c
241
#define OV5648_HTS_H(v) (((v) & GENMASK(12, 8)) >> 8)
drivers/media/i2c/ov5648.c
243
#define OV5648_HTS_L(v) ((v) & GENMASK(7, 0))
drivers/media/i2c/ov5648.c
245
#define OV5648_VTS_H(v) (((v) & GENMASK(15, 8)) >> 8)
drivers/media/i2c/ov5648.c
247
#define OV5648_VTS_L(v) ((v) & GENMASK(7, 0))
drivers/media/i2c/ov5648.c
249
#define OV5648_OFFSET_X_H(v) (((v) & GENMASK(11, 8)) >> 8)
drivers/media/i2c/ov5648.c
251
#define OV5648_OFFSET_X_L(v) ((v) & GENMASK(7, 0))
drivers/media/i2c/ov5648.c
253
#define OV5648_OFFSET_Y_H(v) (((v) & GENMASK(11, 8)) >> 8)
drivers/media/i2c/ov5648.c
255
#define OV5648_OFFSET_Y_L(v) ((v) & GENMASK(7, 0))
drivers/media/i2c/ov5648.c
257
#define OV5648_SUB_INC_X_ODD(v) (((v) << 4) & GENMASK(7, 4))
drivers/media/i2c/ov5648.c
258
#define OV5648_SUB_INC_X_EVEN(v) ((v) & GENMASK(3, 0))
drivers/media/i2c/ov5648.c
260
#define OV5648_SUB_INC_Y_ODD(v) (((v) << 4) & GENMASK(7, 4))
drivers/media/i2c/ov5648.c
261
#define OV5648_SUB_INC_Y_EVEN(v) ((v) & GENMASK(3, 0))
drivers/media/i2c/ov5648.c
263
#define OV5648_HSYNCST_H(v) (((v) >> 8) & 0xf)
drivers/media/i2c/ov5648.c
265
#define OV5648_HSYNCST_L(v) ((v) & GENMASK(7, 0))
drivers/media/i2c/ov5648.c
267
#define OV5648_HSYNCW_H(v) (((v) >> 8) & 0xf)
drivers/media/i2c/ov5648.c
269
#define OV5648_HSYNCW_L(v) ((v) & GENMASK(7, 0))
drivers/media/i2c/ov5648.c
318
#define OV5648_BLC_CTRL1_START_LINE(v) ((v) & GENMASK(5, 0))
drivers/media/i2c/ov5648.c
321
#define OV5648_BLC_CTRL2_RESET_FRAME_NUM(v) ((v) & GENMASK(5, 0))
drivers/media/i2c/ov5648.c
324
#define OV5648_BLC_LINE_NUM(v) ((v) & GENMASK(7, 0))
drivers/media/i2c/ov5648.c
476
#define OV5648_GAIN_RED_MAN_H(v) (((v) & GENMASK(11, 8)) >> 8)
drivers/media/i2c/ov5648.c
478
#define OV5648_GAIN_RED_MAN_L(v) ((v) & GENMASK(7, 0))
drivers/media/i2c/ov5648.c
480
#define OV5648_GAIN_GREEN_MAN_H(v) (((v) & GENMASK(11, 8)) >> 8)
drivers/media/i2c/ov5648.c
482
#define OV5648_GAIN_GREEN_MAN_L(v) ((v) & GENMASK(7, 0))
drivers/media/i2c/ov5648.c
484
#define OV5648_GAIN_BLUE_MAN_H(v) (((v) & GENMASK(11, 8)) >> 8)
drivers/media/i2c/ov5648.c
486
#define OV5648_GAIN_BLUE_MAN_L(v) ((v) & GENMASK(7, 0))
drivers/media/i2c/ov5648.c
64
#define OV5648_MIPI_SC_CTRL0_MIPI_LANES(v) (((v) << 5) & GENMASK(7, 5))
drivers/media/i2c/ov5648.c
76
#define OV5648_PLL_CTRL0_PLL_CHARGE_PUMP(v) (((v) << 4) & GENMASK(6, 4))
drivers/media/i2c/ov5648.c
77
#define OV5648_PLL_CTRL0_BITS(v) ((v) & GENMASK(3, 0))
drivers/media/i2c/ov5648.c
79
#define OV5648_PLL_CTRL1_SYS_DIV(v) (((v) << 4) & GENMASK(7, 4))
drivers/media/i2c/ov5648.c
80
#define OV5648_PLL_CTRL1_MIPI_DIV(v) ((v) & GENMASK(3, 0))
drivers/media/i2c/ov5648.c
82
#define OV5648_PLL_MUL(v) ((v) & GENMASK(7, 0))
drivers/media/i2c/ov5648.c
84
#define OV5648_PLL_DIV_ROOT_DIV(v) ((((v) - 1) << 4) & BIT(4))
drivers/media/i2c/ov5648.c
85
#define OV5648_PLL_DIV_PLL_PRE_DIV(v) ((v) & GENMASK(3, 0))
drivers/media/i2c/ov5648.c
91
#define OV5648_PLLS_MUL(v) ((v) & GENMASK(4, 0))
drivers/media/i2c/ov5648.c
93
#define OV5648_PLLS_CTRL_PLL_CHARGE_PUMP(v) (((v) << 4) & GENMASK(6, 4))
drivers/media/i2c/ov5648.c
94
#define OV5648_PLLS_CTRL_SYS_DIV(v) ((v) & GENMASK(3, 0))
drivers/media/i2c/ov5648.c
96
#define OV5648_PLLS_DIV_PLLS_PRE_DIV(v) (((v) << 4) & GENMASK(5, 4))
drivers/media/i2c/ov5648.c
97
#define OV5648_PLLS_DIV_PLLS_DIV_R(v) ((((v) - 1) << 2) & BIT(2))
drivers/media/i2c/ov5648.c
98
#define OV5648_PLLS_DIV_PLLS_SEL_DIV(v) ((v) & GENMASK(1, 0))
drivers/media/i2c/ov5670.c
34
#define OV5670_MIPI_SC_CTRL0_LANES(v) ((((v) - 1) << 5) & \
drivers/media/i2c/ov7670.c
1406
static unsigned char ov7670_abs_to_sm(unsigned char v)
drivers/media/i2c/ov7670.c
1408
if (v > 127)
drivers/media/i2c/ov7670.c
1409
return v & 0x7f;
drivers/media/i2c/ov7670.c
1410
return (128 - v) | 0x80;
drivers/media/i2c/ov7670.c
1415
unsigned char com8 = 0, v;
drivers/media/i2c/ov7670.c
1420
v = ov7670_abs_to_sm(value);
drivers/media/i2c/ov7670.c
1421
return ov7670_write(sd, REG_BRIGHT, v);
drivers/media/i2c/ov7670.c
1431
unsigned char v = 0;
drivers/media/i2c/ov7670.c
1434
ret = ov7670_read(sd, REG_MVFP, &v);
drivers/media/i2c/ov7670.c
1438
v |= MVFP_MIRROR;
drivers/media/i2c/ov7670.c
1440
v &= ~MVFP_MIRROR;
drivers/media/i2c/ov7670.c
1442
return ov7670_write(sd, REG_MVFP, v);
drivers/media/i2c/ov7670.c
1447
unsigned char v = 0;
drivers/media/i2c/ov7670.c
1450
ret = ov7670_read(sd, REG_MVFP, &v);
drivers/media/i2c/ov7670.c
1454
v |= MVFP_FLIP;
drivers/media/i2c/ov7670.c
1456
v &= ~MVFP_FLIP;
drivers/media/i2c/ov7670.c
1458
return ov7670_write(sd, REG_MVFP, v);
drivers/media/i2c/ov7670.c
622
unsigned char v;
drivers/media/i2c/ov7670.c
628
ret = ov7670_read(sd, REG_MIDH, &v);
drivers/media/i2c/ov7670.c
631
if (v != 0x7f) /* OV manuf. id. */
drivers/media/i2c/ov7670.c
633
ret = ov7670_read(sd, REG_MIDL, &v);
drivers/media/i2c/ov7670.c
636
if (v != 0xa2)
drivers/media/i2c/ov7670.c
641
ret = ov7670_read(sd, REG_PID, &v);
drivers/media/i2c/ov7670.c
644
if (v != 0x76) /* PID + VER = 0x76 / 0x73 */
drivers/media/i2c/ov7670.c
646
ret = ov7670_read(sd, REG_VER, &v);
drivers/media/i2c/ov7670.c
649
if (v != 0x73) /* PID + VER = 0x76 / 0x73 */
drivers/media/i2c/ov7670.c
919
unsigned char v;
drivers/media/i2c/ov7670.c
931
ret = ov7670_read(sd, REG_HREF, &v);
drivers/media/i2c/ov7670.c
934
v = (v & 0xc0) | ((hstop & 0x7) << 3) | (hstart & 0x7);
drivers/media/i2c/ov7670.c
936
ret = ov7670_write(sd, REG_HREF, v);
drivers/media/i2c/ov7670.c
946
ret = ov7670_read(sd, REG_VREF, &v);
drivers/media/i2c/ov7670.c
949
v = (v & 0xf0) | ((vstop & 0x3) << 2) | (vstart & 0x3);
drivers/media/i2c/ov7670.c
951
return ov7670_write(sd, REG_VREF, v);
drivers/media/i2c/ov8865.c
101
#define OV8865_MIPI_SC_CTRL0_LANES(v) ((((v) - 1) << 5) & \
drivers/media/i2c/ov8865.c
115
#define OV8865_PCLK_SEL_PCLK_DIV(v) ((((v) - 1) << 3) & BIT(3))
drivers/media/i2c/ov8865.c
123
#define OV8865_MIPI_BIT_SEL(v) (((v) << 0) & GENMASK(4, 0))
drivers/media/i2c/ov8865.c
125
#define OV8865_CLK_SEL0_PLL1_SYS_SEL(v) (((v) << 7) & BIT(7))
drivers/media/i2c/ov8865.c
130
#define OV8865_CLK_SEL1_PLL_SCLK_SEL(v) (((v) << 1) & BIT(1))
drivers/media/i2c/ov8865.c
133
#define OV8865_SCLK_CTRL_SCLK_DIV(v) (((v) << 4) & GENMASK(7, 4))
drivers/media/i2c/ov8865.c
134
#define OV8865_SCLK_CTRL_SCLK_PRE_DIV(v) (((v) << 2) & GENMASK(3, 2))
drivers/media/i2c/ov8865.c
140
#define OV8865_EXPOSURE_CTRL_HH(v) (((v) & GENMASK(19, 16)) >> 16)
drivers/media/i2c/ov8865.c
142
#define OV8865_EXPOSURE_CTRL_H(v) (((v) & GENMASK(15, 8)) >> 8)
drivers/media/i2c/ov8865.c
144
#define OV8865_EXPOSURE_CTRL_L(v) ((v) & GENMASK(7, 0))
drivers/media/i2c/ov8865.c
149
#define OV8865_GAIN_CTRL_H(v) (((v) & GENMASK(12, 8)) >> 8)
drivers/media/i2c/ov8865.c
151
#define OV8865_GAIN_CTRL_L(v) ((v) & GENMASK(7, 0))
drivers/media/i2c/ov8865.c
156
#define OV8865_CROP_START_X_H(v) (((v) & GENMASK(11, 8)) >> 8)
drivers/media/i2c/ov8865.c
158
#define OV8865_CROP_START_X_L(v) ((v) & GENMASK(7, 0))
drivers/media/i2c/ov8865.c
160
#define OV8865_CROP_START_Y_H(v) (((v) & GENMASK(11, 8)) >> 8)
drivers/media/i2c/ov8865.c
162
#define OV8865_CROP_START_Y_L(v) ((v) & GENMASK(7, 0))
drivers/media/i2c/ov8865.c
164
#define OV8865_CROP_END_X_H(v) (((v) & GENMASK(11, 8)) >> 8)
drivers/media/i2c/ov8865.c
166
#define OV8865_CROP_END_X_L(v) ((v) & GENMASK(7, 0))
drivers/media/i2c/ov8865.c
168
#define OV8865_CROP_END_Y_H(v) (((v) & GENMASK(11, 8)) >> 8)
drivers/media/i2c/ov8865.c
170
#define OV8865_CROP_END_Y_L(v) ((v) & GENMASK(7, 0))
drivers/media/i2c/ov8865.c
172
#define OV8865_OUTPUT_SIZE_X_H(v) (((v) & GENMASK(11, 8)) >> 8)
drivers/media/i2c/ov8865.c
174
#define OV8865_OUTPUT_SIZE_X_L(v) ((v) & GENMASK(7, 0))
drivers/media/i2c/ov8865.c
176
#define OV8865_OUTPUT_SIZE_Y_H(v) (((v) & GENMASK(11, 8)) >> 8)
drivers/media/i2c/ov8865.c
178
#define OV8865_OUTPUT_SIZE_Y_L(v) ((v) & GENMASK(7, 0))
drivers/media/i2c/ov8865.c
180
#define OV8865_HTS_H(v) (((v) & GENMASK(11, 8)) >> 8)
drivers/media/i2c/ov8865.c
182
#define OV8865_HTS_L(v) ((v) & GENMASK(7, 0))
drivers/media/i2c/ov8865.c
184
#define OV8865_VTS_H(v) (((v) & GENMASK(11, 8)) >> 8)
drivers/media/i2c/ov8865.c
186
#define OV8865_VTS_L(v) ((v) & GENMASK(7, 0))
drivers/media/i2c/ov8865.c
190
#define OV8865_OFFSET_X_H(v) (((v) & GENMASK(15, 8)) >> 8)
drivers/media/i2c/ov8865.c
192
#define OV8865_OFFSET_X_L(v) ((v) & GENMASK(7, 0))
drivers/media/i2c/ov8865.c
194
#define OV8865_OFFSET_Y_H(v) (((v) & GENMASK(14, 8)) >> 8)
drivers/media/i2c/ov8865.c
196
#define OV8865_OFFSET_Y_L(v) ((v) & GENMASK(7, 0))
drivers/media/i2c/ov8865.c
198
#define OV8865_INC_X_ODD(v) ((v) & GENMASK(4, 0))
drivers/media/i2c/ov8865.c
200
#define OV8865_INC_X_EVEN(v) ((v) & GENMASK(4, 0))
drivers/media/i2c/ov8865.c
202
#define OV8865_VSYNC_START_H(v) (((v) & GENMASK(15, 8)) >> 8)
drivers/media/i2c/ov8865.c
204
#define OV8865_VSYNC_START_L(v) ((v) & GENMASK(7, 0))
drivers/media/i2c/ov8865.c
206
#define OV8865_VSYNC_END_H(v) (((v) & GENMASK(15, 8)) >> 8)
drivers/media/i2c/ov8865.c
208
#define OV8865_VSYNC_END_L(v) ((v) & GENMASK(7, 0))
drivers/media/i2c/ov8865.c
210
#define OV8865_HSYNC_FIRST_H(v) (((v) & GENMASK(15, 8)) >> 8)
drivers/media/i2c/ov8865.c
212
#define OV8865_HSYNC_FIRST_L(v) ((v) & GENMASK(7, 0))
drivers/media/i2c/ov8865.c
227
#define OV8865_INC_Y_ODD(v) ((v) & GENMASK(4, 0))
drivers/media/i2c/ov8865.c
229
#define OV8865_INC_Y_EVEN(v) ((v) & GENMASK(4, 0))
drivers/media/i2c/ov8865.c
232
#define OV8865_ABLC_NUM(v) ((v) & GENMASK(4, 0))
drivers/media/i2c/ov8865.c
235
#define OV8865_ZLINE_NUM(v) ((v) & GENMASK(4, 0))
drivers/media/i2c/ov8865.c
249
#define OV8865_AUTO_SIZE_BOUNDARIES_Y(v) (((v) << 4) & GENMASK(7, 4))
drivers/media/i2c/ov8865.c
250
#define OV8865_AUTO_SIZE_BOUNDARIES_X(v) ((v) & GENMASK(3, 0))
drivers/media/i2c/ov8865.c
288
#define OV8865_BLC_CTRLD_OFFSET_TRIGGER(v) ((v) & GENMASK(7, 0))
drivers/media/i2c/ov8865.c
296
#define OV8865_BLC_ANCHOR_LEFT_START_H(v) (((v) & GENMASK(11, 8)) >> 8)
drivers/media/i2c/ov8865.c
298
#define OV8865_BLC_ANCHOR_LEFT_START_L(v) ((v) & GENMASK(7, 0))
drivers/media/i2c/ov8865.c
300
#define OV8865_BLC_ANCHOR_LEFT_END_H(v) (((v) & GENMASK(11, 8)) >> 8)
drivers/media/i2c/ov8865.c
302
#define OV8865_BLC_ANCHOR_LEFT_END_L(v) ((v) & GENMASK(7, 0))
drivers/media/i2c/ov8865.c
304
#define OV8865_BLC_ANCHOR_RIGHT_START_H(v) (((v) & GENMASK(11, 8)) >> 8)
drivers/media/i2c/ov8865.c
306
#define OV8865_BLC_ANCHOR_RIGHT_START_L(v) ((v) & GENMASK(7, 0))
drivers/media/i2c/ov8865.c
308
#define OV8865_BLC_ANCHOR_RIGHT_END_H(v) (((v) & GENMASK(11, 8)) >> 8)
drivers/media/i2c/ov8865.c
310
#define OV8865_BLC_ANCHOR_RIGHT_END_L(v) ((v) & GENMASK(7, 0))
drivers/media/i2c/ov8865.c
313
#define OV8865_BLC_TOP_ZLINE_START(v) ((v) & GENMASK(5, 0))
drivers/media/i2c/ov8865.c
315
#define OV8865_BLC_TOP_ZLINE_NUM(v) ((v) & GENMASK(4, 0))
drivers/media/i2c/ov8865.c
317
#define OV8865_BLC_TOP_BLKLINE_START(v) ((v) & GENMASK(5, 0))
drivers/media/i2c/ov8865.c
319
#define OV8865_BLC_TOP_BLKLINE_NUM(v) ((v) & GENMASK(4, 0))
drivers/media/i2c/ov8865.c
321
#define OV8865_BLC_BOT_ZLINE_START(v) ((v) & GENMASK(5, 0))
drivers/media/i2c/ov8865.c
323
#define OV8865_BLC_BOT_ZLINE_NUM(v) ((v) & GENMASK(4, 0))
drivers/media/i2c/ov8865.c
325
#define OV8865_BLC_BOT_BLKLINE_START(v) ((v) & GENMASK(5, 0))
drivers/media/i2c/ov8865.c
327
#define OV8865_BLC_BOT_BLKLINE_NUM(v) ((v) & GENMASK(4, 0))
drivers/media/i2c/ov8865.c
330
#define OV8865_BLC_OFFSET_LIMIT(v) ((v) & GENMASK(7, 0))
drivers/media/i2c/ov8865.c
335
#define OV8865_VFIFO_READ_START_H(v) (((v) & GENMASK(15, 8)) >> 8)
drivers/media/i2c/ov8865.c
337
#define OV8865_VFIFO_READ_START_L(v) ((v) & GENMASK(7, 0))
drivers/media/i2c/ov8865.c
35
#define OV8865_PLL_CTRL0_PRE_DIV(v) ((v) & GENMASK(2, 0))
drivers/media/i2c/ov8865.c
37
#define OV8865_PLL_CTRL1_MUL_H(v) (((v) & GENMASK(9, 8)) >> 8)
drivers/media/i2c/ov8865.c
39
#define OV8865_PLL_CTRL2_MUL_L(v) ((v) & GENMASK(7, 0))
drivers/media/i2c/ov8865.c
402
#define OV8865_MIPI_LANE_SEL01_LANE0(v) (((v) << 0) & GENMASK(2, 0))
drivers/media/i2c/ov8865.c
403
#define OV8865_MIPI_LANE_SEL01_LANE1(v) (((v) << 4) & GENMASK(6, 4))
drivers/media/i2c/ov8865.c
405
#define OV8865_MIPI_LANE_SEL23_LANE2(v) (((v) << 0) & GENMASK(2, 0))
drivers/media/i2c/ov8865.c
406
#define OV8865_MIPI_LANE_SEL23_LANE3(v) (((v) << 4) & GENMASK(6, 4))
drivers/media/i2c/ov8865.c
41
#define OV8865_PLL_CTRL3_M_DIV(v) (((v) - 1) & GENMASK(3, 0))
drivers/media/i2c/ov8865.c
424
#define OV8865_ISP_GAIN_RED_H(v) (((v) & GENMASK(13, 6)) >> 6)
drivers/media/i2c/ov8865.c
426
#define OV8865_ISP_GAIN_RED_L(v) ((v) & GENMASK(5, 0))
drivers/media/i2c/ov8865.c
428
#define OV8865_ISP_GAIN_GREEN_H(v) (((v) & GENMASK(13, 6)) >> 6)
drivers/media/i2c/ov8865.c
43
#define OV8865_PLL_CTRL4_MIPI_DIV(v) ((v) & GENMASK(1, 0))
drivers/media/i2c/ov8865.c
430
#define OV8865_ISP_GAIN_GREEN_L(v) ((v) & GENMASK(5, 0))
drivers/media/i2c/ov8865.c
432
#define OV8865_ISP_GAIN_BLUE_H(v) (((v) & GENMASK(13, 6)) >> 6)
drivers/media/i2c/ov8865.c
434
#define OV8865_ISP_GAIN_BLUE_L(v) ((v) & GENMASK(5, 0))
drivers/media/i2c/ov8865.c
440
#define OV8865_VAP_CTRL1_HSUB_COEF(v) ((((v) - 1) << 2) & \
drivers/media/i2c/ov8865.c
442
#define OV8865_VAP_CTRL1_VSUB_COEF(v) (((v) - 1) & GENMASK(1, 0))
drivers/media/i2c/ov8865.c
45
#define OV8865_PLL_CTRL5_SYS_PRE_DIV(v) ((v) & GENMASK(1, 0))
drivers/media/i2c/ov8865.c
47
#define OV8865_PLL_CTRL6_SYS_DIV(v) (((v) - 1) & BIT(0))
drivers/media/i2c/ov8865.c
52
#define OV8865_PLL_CTRLA_PRE_DIV_HALF(v) (((v) - 1) & BIT(0))
drivers/media/i2c/ov8865.c
54
#define OV8865_PLL_CTRLB_PRE_DIV(v) ((v) & GENMASK(2, 0))
drivers/media/i2c/ov8865.c
56
#define OV8865_PLL_CTRLC_MUL_H(v) (((v) & GENMASK(9, 8)) >> 8)
drivers/media/i2c/ov8865.c
58
#define OV8865_PLL_CTRLD_MUL_L(v) ((v) & GENMASK(7, 0))
drivers/media/i2c/ov8865.c
60
#define OV8865_PLL_CTRLE_SYS_DIV(v) ((v) & GENMASK(2, 0))
drivers/media/i2c/ov8865.c
62
#define OV8865_PLL_CTRLF_SYS_PRE_DIV(v) (((v) - 1) & GENMASK(3, 0))
drivers/media/i2c/ov8865.c
66
#define OV8865_PLL_CTRL12_PRE_DIV_HALF(v) ((((v) - 1) << 4) & BIT(4))
drivers/media/i2c/ov8865.c
67
#define OV8865_PLL_CTRL12_DAC_DIV(v) (((v) - 1) & GENMASK(3, 0))
drivers/media/i2c/ov8865.c
97
#define OV8865_PUMP_CLK_DIV_PUMP_N(v) (((v) << 4) & GENMASK(6, 4))
drivers/media/i2c/ov8865.c
98
#define OV8865_PUMP_CLK_DIV_PUMP_P(v) ((v) & GENMASK(2, 0))
drivers/media/i2c/s5k5baf.c
1445
struct v4l2_rect *v)
drivers/media/i2c/s5k5baf.c
1450
*rects[first] = *v;
drivers/media/i2c/s5k5baf.c
1456
*v = *rects[first];
drivers/media/i2c/s5k5baf.c
705
static void s5k5baf_hw_set_anti_flicker(struct s5k5baf *state, int v)
drivers/media/i2c/s5k5baf.c
707
if (v == V4L2_CID_POWER_LINE_FREQUENCY_AUTO) {
drivers/media/i2c/s5k5baf.c
712
s5k5baf_write_seq(state, REG_SF_FLICKER_QUANT, v, 1);
drivers/media/i2c/s5k5baf.c
840
static void s5k5baf_rescale(struct v4l2_rect *r, const struct v4l2_rect *v,
drivers/media/i2c/s5k5baf.c
844
r->left = v->left * n->width / d->width;
drivers/media/i2c/s5k5baf.c
845
r->top = v->top * n->height / d->height;
drivers/media/i2c/s5k5baf.c
846
r->width = v->width * n->width / d->width;
drivers/media/i2c/s5k5baf.c
847
r->height = v->height * n->height / d->height;
drivers/media/i2c/saa7115.c
1139
u8 v = saa711x_read(sd, i - 2 + R_41_LCR_BASE);
drivers/media/i2c/saa7115.c
1141
sliced->service_lines[0][i] = lcr2vbi[v >> 4];
drivers/media/i2c/saa7115.c
1142
sliced->service_lines[1][i] = lcr2vbi[v & 0xf];
drivers/media/i2c/tc358743.c
1087
unsigned int v;
drivers/media/i2c/tc358743.c
1089
v = i2c_rd32(sd, CECRCTR);
drivers/media/i2c/tc358743.c
1090
msg.len = v & 0x1f;
drivers/media/i2c/tc358743.c
1094
v = i2c_rd32(sd, CECRBUF1 + i * 4);
drivers/media/i2c/tc358743.c
1095
msg.msg[i] = v & 0xff;
drivers/media/i2c/tda1997x.c
2299
u32 v;
drivers/media/i2c/tda1997x.c
2365
if (!of_property_read_u32(np, "nxp,audout-layout", &v)) {
drivers/media/i2c/tda1997x.c
2366
switch (v) {
drivers/media/i2c/tda1997x.c
2375
pdata->audout_layout = v;
drivers/media/i2c/tda1997x.c
2377
if (!of_property_read_u32(np, "nxp,audout-width", &v)) {
drivers/media/i2c/tda1997x.c
2378
switch (v) {
drivers/media/i2c/tda1997x.c
2387
pdata->audout_width = v;
drivers/media/i2c/tda1997x.c
2389
if (!of_property_read_u32(np, "nxp,audout-mclk-fs", &v)) {
drivers/media/i2c/tda1997x.c
2390
switch (v) {
drivers/media/i2c/tda1997x.c
2403
pdata->audout_mclk_fs = v;
drivers/media/i2c/thp7312.c
119
#define THP7312_FW_VERSION_MAJOR(v) ((v) >> 8)
drivers/media/i2c/thp7312.c
120
#define THP7312_FW_VERSION_MINOR(v) ((v) & 0xff)
drivers/media/pci/b2c2/flexcop-dma.c
118
flexcop_ibi_value v = fc->read_ibi_reg(fc, r);
drivers/media/pci/b2c2/flexcop-dma.c
121
v.dma_0xc.remap_enable = onoff;
drivers/media/pci/b2c2/flexcop-dma.c
122
fc->write_ibi_reg(fc, r, v);
drivers/media/pci/b2c2/flexcop-dma.c
130
flexcop_ibi_value v = fc->read_ibi_reg(fc, ctrl_208);
drivers/media/pci/b2c2/flexcop-dma.c
133
v.ctrl_208.DMA1_Timer_Enable_sig = onoff;
drivers/media/pci/b2c2/flexcop-dma.c
136
v.ctrl_208.DMA2_Timer_Enable_sig = onoff;
drivers/media/pci/b2c2/flexcop-dma.c
138
fc->write_ibi_reg(fc, ctrl_208, v);
drivers/media/pci/b2c2/flexcop-dma.c
148
flexcop_ibi_value v = fc->read_ibi_reg(fc, r);
drivers/media/pci/b2c2/flexcop-dma.c
153
v.dma_0x4_write.dmatimer = cycles;
drivers/media/pci/b2c2/flexcop-dma.c
154
fc->write_ibi_reg(fc, r, v);
drivers/media/pci/b2c2/flexcop-pci.c
101
writel(v.raw, fc_pci->io_mem + r);
drivers/media/pci/b2c2/flexcop-pci.c
151
flexcop_ibi_value v;
drivers/media/pci/b2c2/flexcop-pci.c
155
v = fc->read_ibi_reg(fc, irq_20c);
drivers/media/pci/b2c2/flexcop-pci.c
158
if (v.irq_20c.Data_receiver_error)
drivers/media/pci/b2c2/flexcop-pci.c
160
if (v.irq_20c.Continuity_error_flag)
drivers/media/pci/b2c2/flexcop-pci.c
162
if (v.irq_20c.LLC_SNAP_FLAG_set)
drivers/media/pci/b2c2/flexcop-pci.c
164
if (v.irq_20c.Transport_Error)
drivers/media/pci/b2c2/flexcop-pci.c
170
if (v.irq_20c.DMA1_IRQ_Status == 1) {
drivers/media/pci/b2c2/flexcop-pci.c
184
} else if (v.irq_20c.DMA1_Timer_Status == 1) {
drivers/media/pci/b2c2/flexcop-pci.c
193
v.raw, (unsigned long long)cur_addr, cur_pos,
drivers/media/pci/b2c2/flexcop-pci.c
226
v.raw);
drivers/media/pci/b2c2/flexcop-pci.c
80
flexcop_ibi_value v;
drivers/media/pci/b2c2/flexcop-pci.c
81
v.raw = readl(fc_pci->io_mem + r);
drivers/media/pci/b2c2/flexcop-pci.c
83
if (lastrreg != r || lastrval != v.raw) {
drivers/media/pci/b2c2/flexcop-pci.c
84
lastrreg = r; lastrval = v.raw;
drivers/media/pci/b2c2/flexcop-pci.c
85
deb_reg("new rd: %3x: %08x\n", r, v.raw);
drivers/media/pci/b2c2/flexcop-pci.c
88
return v;
drivers/media/pci/b2c2/flexcop-pci.c
92
flexcop_ibi_register r, flexcop_ibi_value v)
drivers/media/pci/b2c2/flexcop-pci.c
96
if (lastwreg != r || lastwval != v.raw) {
drivers/media/pci/b2c2/flexcop-pci.c
97
lastwreg = r; lastwval = v.raw;
drivers/media/pci/b2c2/flexcop-pci.c
98
deb_reg("new wr: %3x: %08x\n", r, v.raw);
drivers/media/pci/cx18/cx18-audio.c
26
u32 u, v;
drivers/media/pci/cx18/cx18-audio.c
46
v = u & ~CX18_AI1_MUX_MASK;
drivers/media/pci/cx18/cx18-audio.c
49
v |= CX18_AI1_MUX_I2S1;
drivers/media/pci/cx18/cx18-audio.c
52
v |= CX18_AI1_MUX_I2S2;
drivers/media/pci/cx18/cx18-audio.c
55
v |= CX18_AI1_MUX_843_I2S;
drivers/media/pci/cx18/cx18-audio.c
58
if (v == u) {
drivers/media/pci/cx18/cx18-audio.c
75
cx18_write_reg_expect(cx, v | 0xb00, CX18_AUDIO_ENABLE,
drivers/media/pci/cx18/cx18-audio.c
76
v, CX18_AI1_MUX_MASK);
drivers/media/pci/cx18/cx18-av-audio.c
292
u8 v;
drivers/media/pci/cx18/cx18-av-audio.c
295
v = cx18_av_read(cx, 0x803) & ~0x10;
drivers/media/pci/cx18/cx18-av-audio.c
296
cx18_av_write_expect(cx, 0x803, v, v, 0x1f);
drivers/media/pci/cx18/cx18-av-audio.c
299
v = cx18_av_read(cx, 0x810) | 0x01;
drivers/media/pci/cx18/cx18-av-audio.c
300
cx18_av_write_expect(cx, 0x810, v, v, 0x0f);
drivers/media/pci/cx18/cx18-av-audio.c
320
v = cx18_av_read(cx, 0x810) & ~0x01;
drivers/media/pci/cx18/cx18-av-audio.c
321
cx18_av_write_expect(cx, 0x810, v, v, 0x0f);
drivers/media/pci/cx18/cx18-av-audio.c
326
v = cx18_av_read(cx, 0x803) | 0x10;
drivers/media/pci/cx18/cx18-av-audio.c
327
cx18_av_write_expect(cx, 0x803, v, v, 0x1f);
drivers/media/pci/cx18/cx18-av-audio.c
378
u8 v;
drivers/media/pci/cx18/cx18-av-audio.c
385
v = cx18_av_read(cx, 0x803);
drivers/media/pci/cx18/cx18-av-audio.c
388
v &= ~0x10;
drivers/media/pci/cx18/cx18-av-audio.c
389
cx18_av_write_expect(cx, 0x803, v, v, 0x1f);
drivers/media/pci/cx18/cx18-av-audio.c
393
v |= 0x10;
drivers/media/pci/cx18/cx18-av-audio.c
394
cx18_av_write_expect(cx, 0x803, v, v, 0x1f);
drivers/media/pci/cx18/cx18-av-audio.c
407
u8 v;
drivers/media/pci/cx18/cx18-av-audio.c
410
v = cx18_av_read(cx, 0x803) & ~0x10;
drivers/media/pci/cx18/cx18-av-audio.c
411
cx18_av_write_expect(cx, 0x803, v, v, 0x1f);
drivers/media/pci/cx18/cx18-av-audio.c
414
v = cx18_av_read(cx, 0x810) | 0x1;
drivers/media/pci/cx18/cx18-av-audio.c
415
cx18_av_write_expect(cx, 0x810, v, v, 0x0f);
drivers/media/pci/cx18/cx18-av-audio.c
419
v = cx18_av_read(cx, 0x810) & ~0x1;
drivers/media/pci/cx18/cx18-av-audio.c
420
cx18_av_write_expect(cx, 0x810, v, v, 0x0f);
drivers/media/pci/cx18/cx18-av-audio.c
422
v = cx18_av_read(cx, 0x803) | 0x10;
drivers/media/pci/cx18/cx18-av-audio.c
423
cx18_av_write_expect(cx, 0x803, v, v, 0x1f);
drivers/media/pci/cx18/cx18-av-core.c
118
u32 v;
drivers/media/pci/cx18/cx18-av-core.c
126
v = cx18_av_read4(cx, CXADEC_HOST_REG1);
drivers/media/pci/cx18/cx18-av-core.c
128
cx18_av_write4_expect(cx, CXADEC_HOST_REG1, v | 1, v, 0xfffe);
drivers/media/pci/cx18/cx18-av-core.c
130
cx18_av_write4_expect(cx, CXADEC_HOST_REG1, v & 0xfffe,
drivers/media/pci/cx18/cx18-av-core.c
131
v & 0xfffe, 0xffff);
drivers/media/pci/cx18/cx18-av-core.c
134
v = cx18_av_read4(cx, CXADEC_DLL1_DIAG_CTRL) & 0xE1FFFEFF;
drivers/media/pci/cx18/cx18-av-core.c
136
cx18_av_write4(cx, CXADEC_DLL1_DIAG_CTRL, v);
drivers/media/pci/cx18/cx18-av-core.c
138
cx18_av_write4(cx, CXADEC_DLL1_DIAG_CTRL, v | 0x10000100);
drivers/media/pci/cx18/cx18-av-core.c
140
v = cx18_av_read4(cx, CXADEC_DLL2_DIAG_CTRL) & 0xE1FFFEFF;
drivers/media/pci/cx18/cx18-av-core.c
142
cx18_av_write4(cx, CXADEC_DLL2_DIAG_CTRL, v);
drivers/media/pci/cx18/cx18-av-core.c
144
cx18_av_write4(cx, CXADEC_DLL2_DIAG_CTRL, v | 0x06000100);
drivers/media/pci/cx18/cx18-av-core.c
149
v = cx18_av_read4(cx, CXADEC_AFE_DIAG_CTRL3) | 1;
drivers/media/pci/cx18/cx18-av-core.c
151
cx18_av_write4_expect(cx, CXADEC_AFE_DIAG_CTRL3, v, v, 0x03009F0F);
drivers/media/pci/cx18/cx18-av-core.c
154
v & 0xFFFFFFFE, v & 0xFFFFFFFE, 0x03009F0F);
drivers/media/pci/cx18/cx18-av-core.c
520
u8 v;
drivers/media/pci/cx18/cx18-av-core.c
551
v = cx18_av_read(cx, 0x803);
drivers/media/pci/cx18/cx18-av-core.c
552
if (v & 0x10) {
drivers/media/pci/cx18/cx18-av-core.c
554
v &= ~0x10;
drivers/media/pci/cx18/cx18-av-core.c
555
cx18_av_write_expect(cx, 0x803, v, v, 0x1f);
drivers/media/pci/cx18/cx18-av-core.c
556
v |= 0x10;
drivers/media/pci/cx18/cx18-av-core.c
557
cx18_av_write_expect(cx, 0x803, v, v, 0x1f);
drivers/media/pci/cx18/cx18-av-core.c
799
u8 v;
drivers/media/pci/cx18/cx18-av-core.c
804
v = cx18_av_read(cx, 0x809);
drivers/media/pci/cx18/cx18-av-core.c
805
v &= ~0xf;
drivers/media/pci/cx18/cx18-av-core.c
818
v |= 0x4;
drivers/media/pci/cx18/cx18-av-core.c
824
v |= 0x7;
drivers/media/pci/cx18/cx18-av-core.c
830
v |= 0x1;
drivers/media/pci/cx18/cx18-av-core.c
835
cx18_av_write_expect(cx, 0x809, v, v, 0xff);
drivers/media/pci/cx18/cx18-av-firmware.c
171
v = cx18_read_reg(cx, CX18_AUDIO_ENABLE);
drivers/media/pci/cx18/cx18-av-firmware.c
173
if (v & 0x800)
drivers/media/pci/cx18/cx18-av-firmware.c
174
cx18_write_reg_expect(cx, v & 0xFFFFFBFF, CX18_AUDIO_ENABLE,
drivers/media/pci/cx18/cx18-av-firmware.c
178
v = cx18_read_reg(cx, CX18_AUDIO_ENABLE);
drivers/media/pci/cx18/cx18-av-firmware.c
179
u = v & CX18_AI1_MUX_MASK;
drivers/media/pci/cx18/cx18-av-firmware.c
180
v &= ~CX18_AI1_MUX_MASK;
drivers/media/pci/cx18/cx18-av-firmware.c
183
v |= CX18_AI1_MUX_I2S1;
drivers/media/pci/cx18/cx18-av-firmware.c
184
cx18_write_reg_expect(cx, v | 0xb00, CX18_AUDIO_ENABLE,
drivers/media/pci/cx18/cx18-av-firmware.c
185
v, CX18_AI1_MUX_MASK);
drivers/media/pci/cx18/cx18-av-firmware.c
187
v = (v & ~CX18_AI1_MUX_MASK) | CX18_AI1_MUX_843_I2S;
drivers/media/pci/cx18/cx18-av-firmware.c
190
v |= CX18_AI1_MUX_843_I2S;
drivers/media/pci/cx18/cx18-av-firmware.c
191
cx18_write_reg_expect(cx, v | 0xb00, CX18_AUDIO_ENABLE,
drivers/media/pci/cx18/cx18-av-firmware.c
192
v, CX18_AI1_MUX_MASK);
drivers/media/pci/cx18/cx18-av-firmware.c
194
v = (v & ~CX18_AI1_MUX_MASK) | u;
drivers/media/pci/cx18/cx18-av-firmware.c
196
cx18_write_reg_expect(cx, v | 0xb00, CX18_AUDIO_ENABLE,
drivers/media/pci/cx18/cx18-av-firmware.c
197
v, CX18_AI1_MUX_MASK);
drivers/media/pci/cx18/cx18-av-firmware.c
200
v = cx18_av_read4(cx, CXADEC_STD_DET_CTL);
drivers/media/pci/cx18/cx18-av-firmware.c
201
v |= 0xFF; /* Auto by default */
drivers/media/pci/cx18/cx18-av-firmware.c
202
v |= 0x400; /* Stereo by default */
drivers/media/pci/cx18/cx18-av-firmware.c
203
v |= 0x14000000;
drivers/media/pci/cx18/cx18-av-firmware.c
204
cx18_av_write4_expect(cx, CXADEC_STD_DET_CTL, v, v, 0x3F00FFFF);
drivers/media/pci/cx18/cx18-av-firmware.c
68
u32 u, v;
drivers/media/pci/cx18/cx18-av-vbi.c
133
u8 v = cx18_av_read(cx, 0x424 + i - 7);
drivers/media/pci/cx18/cx18-av-vbi.c
135
svbi->service_lines[0][i] = lcr2vbi[v >> 4];
drivers/media/pci/cx18/cx18-av-vbi.c
136
svbi->service_lines[1][i] = lcr2vbi[v & 0xf];
drivers/media/pci/cx18/cx18-av-vbi.c
142
u8 v = cx18_av_read(cx, 0x424 + i - 10);
drivers/media/pci/cx18/cx18-av-vbi.c
144
svbi->service_lines[0][i] = lcr2vbi[v >> 4];
drivers/media/pci/cx18/cx18-av-vbi.c
145
svbi->service_lines[1][i] = lcr2vbi[v & 0xf];
drivers/media/pci/cx18/cx18-dvb.c
240
u32 v;
drivers/media/pci/cx18/cx18-dvb.c
262
v = cx18_read_reg(cx, CX18_REG_DMUX_NUM_PORT_0_CONTROL);
drivers/media/pci/cx18/cx18-dvb.c
263
v |= 0x00400000; /* Serial Mode */
drivers/media/pci/cx18/cx18-dvb.c
264
v |= 0x00002000; /* Data Length - Byte */
drivers/media/pci/cx18/cx18-dvb.c
265
v |= 0x00010000; /* Error - Polarity */
drivers/media/pci/cx18/cx18-dvb.c
266
v |= 0x00020000; /* Error - Passthru */
drivers/media/pci/cx18/cx18-dvb.c
267
v |= 0x000c0000; /* Error - Ignore */
drivers/media/pci/cx18/cx18-dvb.c
268
cx18_write_reg(cx, v, CX18_REG_DMUX_NUM_PORT_0_CONTROL);
drivers/media/pci/cx23885/cx23885-core.c
330
u32 v;
drivers/media/pci/cx23885/cx23885-core.c
334
v = mask & dev->pci_irqmask;
drivers/media/pci/cx23885/cx23885-core.c
335
if (v)
drivers/media/pci/cx23885/cx23885-core.c
336
cx_set(PCI_INT_MSK, v);
drivers/media/pci/cx23885/cx23885-core.c
374
u32 v;
drivers/media/pci/cx23885/cx23885-core.c
378
v = cx_read(PCI_INT_MSK);
drivers/media/pci/cx23885/cx23885-core.c
381
return v;
drivers/media/pci/cx23885/cx23888-ir.c
373
u32 v;
drivers/media/pci/cx23885/cx23888-ir.c
377
v = CNTRL_WIN_3_4;
drivers/media/pci/cx23885/cx23888-ir.c
380
v = CNTRL_WIN_3_3;
drivers/media/pci/cx23885/cx23888-ir.c
385
v |= CNTRL_WIN_4_3;
drivers/media/pci/cx23885/cx23888-ir.c
388
v |= CNTRL_WIN_3_3;
drivers/media/pci/cx23885/cx23888-ir.c
391
cx23888_ir_and_or4(dev, CX23888_IR_CNTRL_REG, ~CNTRL_WIN, v);
drivers/media/pci/cx23885/cx23888-ir.c
513
u32 events, v;
drivers/media/pci/cx23885/cx23888-ir.c
568
for (i = 0, v = FIFO_RX_NDV;
drivers/media/pci/cx23885/cx23888-ir.c
569
(v & FIFO_RX_NDV) && !kror; i = 0) {
drivers/media/pci/cx23885/cx23888-ir.c
571
(v & FIFO_RX_NDV) && j < FIFO_RX_DEPTH; j++) {
drivers/media/pci/cx23885/cx23888-ir.c
572
v = cx23888_ir_read4(dev, CX23888_IR_FIFO_REG);
drivers/media/pci/cx23885/cx23888-ir.c
573
rx_data[i].hw_fifo_data = v & ~FIFO_RX_NDV;
drivers/media/pci/cx23885/cx23888-ir.c
589
v = 0;
drivers/media/pci/cx23885/cx23888-ir.c
599
v |= CNTRL_RFE;
drivers/media/pci/cx23885/cx23888-ir.c
608
v |= CNTRL_RXE;
drivers/media/pci/cx23885/cx23888-ir.c
611
if (v) {
drivers/media/pci/cx23885/cx23888-ir.c
613
cx23888_ir_write4(dev, CX23888_IR_CNTRL_REG, cntrl & ~v);
drivers/media/pci/cx23885/cx23888-ir.c
638
unsigned u, v, w;
drivers/media/pci/cx23885/cx23888-ir.c
665
v = (unsigned) pulse_width_count_to_ns(
drivers/media/pci/cx23885/cx23888-ir.c
667
if (v > IR_MAX_DURATION)
drivers/media/pci/cx23885/cx23888-ir.c
668
v = IR_MAX_DURATION;
drivers/media/pci/cx23885/cx23888-ir.c
671
{ .pulse = u, .duration = v, .timeout = w };
drivers/media/pci/cx23885/cx23888-ir.c
674
v, u ? "mark" : "space", w ? "(timed out)" : "");
drivers/media/pci/cx25821/cx25821-i2c.c
347
int v = 0;
drivers/media/pci/cx25821/cx25821-i2c.c
372
v = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
drivers/media/pci/cx25821/cx25821-i2c.c
373
*value = v;
drivers/media/pci/cx25821/cx25821-i2c.c
375
return v;
drivers/media/pci/cx88/cx88-alsa.c
653
int v, b;
drivers/media/pci/cx88/cx88-alsa.c
657
v = left << 10;
drivers/media/pci/cx88/cx88-alsa.c
660
v = right << 10;
drivers/media/pci/cx88/cx88-alsa.c
663
wm8775_s_ctrl(core, V4L2_CID_AUDIO_VOLUME, v);
drivers/media/pci/cx88/cx88-alsa.c
673
int left, right, v, b;
drivers/media/pci/cx88/cx88-alsa.c
684
v = 0x3f - left;
drivers/media/pci/cx88/cx88-alsa.c
687
v = 0x3f - right;
drivers/media/pci/cx88/cx88-alsa.c
692
if (v != (old & 0x3f)) {
drivers/media/pci/cx88/cx88-alsa.c
693
cx_swrite(SHADOW_AUD_VOL_CTL, AUD_VOL_CTL, (old & ~0x3f) | v);
drivers/media/pci/ddbridge/ddbridge-core.c
2868
u8 v;
drivers/media/pci/ddbridge/ddbridge-core.c
2870
i2c_read_reg(&dev->i2c[num].adap, 0x10, 0x08, &v);
drivers/media/pci/ddbridge/ddbridge-core.c
2871
v = (v & ~0x10) | (val ? 0x10 : 0);
drivers/media/pci/ddbridge/ddbridge-core.c
2872
i2c_write_reg(&dev->i2c[num].adap, 0x10, 0x08, v);
drivers/media/pci/ddbridge/ddbridge-max.c
51
u32 c, v = 0, tag = DDB_LINK_TAG(link);
drivers/media/pci/ddbridge/ddbridge-max.c
53
v = LNB_TONE & (dev->link[link].lnb.tone << (15 - lnb));
drivers/media/pci/ddbridge/ddbridge-max.c
54
ddbwritel(dev, cmd | v, tag | LNB_CONTROL(lnb));
drivers/media/pci/ddbridge/ddbridge-max.c
56
v = ddbreadl(dev, tag | LNB_CONTROL(lnb));
drivers/media/pci/ddbridge/ddbridge-max.c
57
if ((v & LNB_BUSY) == 0)
drivers/media/pci/pt3/pt3_i2c.c
129
u32 v;
drivers/media/pci/pt3/pt3_i2c.c
132
v = ioread32(pt3->regs[0] + REG_I2C_R);
drivers/media/pci/pt3/pt3_i2c.c
133
if (!(v & STAT_SEQ_RUNNING))
drivers/media/pci/pt3/pt3_i2c.c
140
*result = v;
drivers/media/pci/saa7164/saa7164-api.c
235
struct tmComResEncVideoBitRate v;
drivers/media/pci/saa7164/saa7164-api.c
265
EU_VIDEO_BIT_RATE_CONTROL, sizeof(v), &v);
drivers/media/pci/saa7164/saa7164-api.c
293
v.ucVideoBitRateMode);
drivers/media/pci/saa7164/saa7164-api.c
295
v.dwVideoBitRate);
drivers/media/pci/saa7164/saa7164-api.c
297
v.dwVideoBitRatePeak);
drivers/media/pci/saa7164/saa7164-api.c
460
u8 v = mute;
drivers/media/pci/saa7164/saa7164-api.c
466
MUTE_CONTROL, sizeof(u8), &v);
drivers/media/pci/saa7164/saa7164-api.c
477
s16 v, min, max;
drivers/media/pci/saa7164/saa7164-api.c
494
(0x01 << 8) | VOLUME_CONTROL, sizeof(u16), &v);
drivers/media/pci/saa7164/saa7164-api.c
499
level, min, max, v);
drivers/media/pci/saa7164/saa7164-api.c
501
v = level;
drivers/media/pci/saa7164/saa7164-api.c
502
if (v < min)
drivers/media/pci/saa7164/saa7164-api.c
503
v = min;
drivers/media/pci/saa7164/saa7164-api.c
504
if (v > max)
drivers/media/pci/saa7164/saa7164-api.c
505
v = max;
drivers/media/pci/saa7164/saa7164-api.c
509
(0x01 << 8) | VOLUME_CONTROL, sizeof(s16), &v);
drivers/media/pci/saa7164/saa7164-api.c
515
(0x02 << 8) | VOLUME_CONTROL, sizeof(s16), &v);
drivers/media/pci/saa7164/saa7164-api.c
520
(0x01 << 8) | VOLUME_CONTROL, sizeof(u16), &v);
drivers/media/pci/saa7164/saa7164-api.c
525
level, min, max, v);
drivers/media/pci/saa7164/saa7164-core.c
1061
static void *saa7164_seq_next(struct seq_file *s, void *v, loff_t *pos)
drivers/media/pci/saa7164/saa7164-core.c
1063
struct saa7164_dev *dev = v;
drivers/media/pci/saa7164/saa7164-core.c
1078
static void saa7164_seq_stop(struct seq_file *s, void *v)
drivers/media/pci/saa7164/saa7164-core.c
1082
static int saa7164_seq_show(struct seq_file *m, void *v)
drivers/media/pci/saa7164/saa7164-core.c
1084
struct saa7164_dev *dev = v;
drivers/media/pci/saa7164/saa7164-encoder.c
61
struct list_head *c, *n, *p, *q, *l, *v;
drivers/media/pci/saa7164/saa7164-encoder.c
84
list_for_each_safe(l, v, &port->list_buf_free.list) {
drivers/media/pci/saa7164/saa7164-vbi.c
30
struct list_head *c, *n, *p, *q, *l, *v;
drivers/media/pci/saa7164/saa7164-vbi.c
53
list_for_each_safe(l, v, &port->list_buf_free.list) {
drivers/media/pci/solo6x10/solo6x10-regs.h
193
#define SOLO_VI_PB_VSIZE(v) ((v)<<0)
drivers/media/pci/solo6x10/solo6x10-regs.h
245
#define SOLO_VI_MOTION_Y_VALUE(v) ((v)<<16)
drivers/media/pci/solo6x10/solo6x10-regs.h
246
#define SOLO_VI_MOTION_CB_VALUE(v) ((v)<<8)
drivers/media/pci/solo6x10/solo6x10-regs.h
247
#define SOLO_VI_MOTION_CR_VALUE(v) ((v)<<0)
drivers/media/pci/solo6x10/solo6x10-regs.h
296
#define SOLO_VO_ZOOM_SY(v) (((v)/2)<<0)
drivers/media/pci/solo6x10/solo6x10-regs.h
305
#define SOLO_BG_V(v) ((v)<<0)
drivers/media/pci/solo6x10/solo6x10-tw28.c
699
u8 v = solo_i2c_readbyte(solo_dev, SOLO_I2C_TW,
drivers/media/pci/solo6x10/solo6x10-tw28.c
702
v &= 0xf0;
drivers/media/pci/solo6x10/solo6x10-tw28.c
703
v |= val;
drivers/media/pci/solo6x10/solo6x10-tw28.c
706
TW286x_SHARPNESS(chip_num), v);
drivers/media/pci/solo6x10/solo6x10.h
378
#define CHK_FLAGS(v, flags) (((v) & (flags)) == (flags))
drivers/media/pci/zoran/zoran_card.c
1183
static int zoran_debugfs_show(struct seq_file *seq, void *v)
drivers/media/platform/arm/mali-c55/mali-c55-registers.h
103
#define MALI_C55_VC_START(v) ((v) & 0xffff)
drivers/media/platform/arm/mali-c55/mali-c55-registers.h
104
#define MALI_C55_VC_SIZE(v) (((v) & 0xffff) << 16)
drivers/media/platform/aspeed/aspeed-video.c
1034
static void aspeed_video_get_timings(struct aspeed_video *v,
drivers/media/platform/aspeed/aspeed-video.c
1039
mds = aspeed_video_read(v, VE_MODE_DETECT_STATUS);
drivers/media/platform/aspeed/aspeed-video.c
1040
sync = aspeed_video_read(v, VE_SYNC_STATUS);
drivers/media/platform/aspeed/aspeed-video.c
1041
htotal = aspeed_video_read(v, VE_H_TOTAL_PIXELS);
drivers/media/platform/aspeed/aspeed-video.c
1061
det->vbackporch = v->frame_top - vsync;
drivers/media/platform/aspeed/aspeed-video.c
1062
det->vfrontporch = vtotal - v->frame_bottom;
drivers/media/platform/aspeed/aspeed-video.c
1065
det->vbackporch = v->frame_top;
drivers/media/platform/aspeed/aspeed-video.c
1066
det->vfrontporch = vsync - v->frame_bottom;
drivers/media/platform/aspeed/aspeed-video.c
1071
det->hbackporch = v->frame_left - hsync;
drivers/media/platform/aspeed/aspeed-video.c
1072
det->hfrontporch = htotal - v->frame_right;
drivers/media/platform/aspeed/aspeed-video.c
1075
det->hbackporch = v->frame_left;
drivers/media/platform/aspeed/aspeed-video.c
1076
det->hfrontporch = hsync - v->frame_right;
drivers/media/platform/aspeed/aspeed-video.c
1094
#define res_check(v) test_and_clear_bit(VIDEO_MODE_DETECT_DONE, &(v)->flags)
drivers/media/platform/aspeed/aspeed-video.c
2037
struct aspeed_video *v = s->private;
drivers/media/platform/aspeed/aspeed-video.c
2043
val08 = aspeed_video_read(v, VE_CTRL);
drivers/media/platform/aspeed/aspeed-video.c
2046
seq_printf(s, " %-20s:\t%s\n", "Input", input_str[v->input]);
drivers/media/platform/aspeed/aspeed-video.c
2063
v->v4l2_input_status ? "Unlock" : "Lock");
drivers/media/platform/aspeed/aspeed-video.c
2064
seq_printf(s, " %-20s:\t%d\n", "Width", v->pix_fmt.width);
drivers/media/platform/aspeed/aspeed-video.c
2065
seq_printf(s, " %-20s:\t%d\n", "Height", v->pix_fmt.height);
drivers/media/platform/aspeed/aspeed-video.c
2066
seq_printf(s, " %-20s:\t%d\n", "FRC", v->frame_rate);
drivers/media/platform/aspeed/aspeed-video.c
2071
seq_printf(s, " %-20s:\t%s\n", "Format", format_str[v->format]);
drivers/media/platform/aspeed/aspeed-video.c
2073
v->yuv420 ? "420" : "444");
drivers/media/platform/aspeed/aspeed-video.c
2074
seq_printf(s, " %-20s:\t%d\n", "Quality", v->jpeg_quality);
drivers/media/platform/aspeed/aspeed-video.c
2075
if (v->format == VIDEO_FMT_ASPEED) {
drivers/media/platform/aspeed/aspeed-video.c
2077
v->hq_mode ? "on" : "off");
drivers/media/platform/aspeed/aspeed-video.c
2079
v->hq_mode ? v->jpeg_hq_quality : 0);
drivers/media/platform/aspeed/aspeed-video.c
2085
seq_printf(s, " %-20s:\t%d\n", "Frame#", v->sequence);
drivers/media/platform/aspeed/aspeed-video.c
2087
seq_printf(s, " %-18s:\t%d\n", "Now", v->perf.duration);
drivers/media/platform/aspeed/aspeed-video.c
2088
seq_printf(s, " %-18s:\t%d\n", "Min", v->perf.duration_min);
drivers/media/platform/aspeed/aspeed-video.c
2089
seq_printf(s, " %-18s:\t%d\n", "Max", v->perf.duration_max);
drivers/media/platform/aspeed/aspeed-video.c
2091
(v->perf.totaltime && v->sequence) ?
drivers/media/platform/aspeed/aspeed-video.c
2092
1000 / (v->perf.totaltime / v->sequence) : 0);
drivers/media/platform/aspeed/aspeed-video.c
601
struct aspeed_video *v = container_of(p, struct aspeed_video,
drivers/media/platform/aspeed/aspeed-video.c
610
v4l2_dbg(2, debug, &v->v4l2_dev, "time consumed: %d ms\n",
drivers/media/platform/aspeed/aspeed-video.c
725
static void aspeed_video_reset(struct aspeed_video *v)
drivers/media/platform/aspeed/aspeed-video.c
727
reset_control_assert(v->reset);
drivers/media/platform/aspeed/aspeed-video.c
729
reset_control_deassert(v->reset);
drivers/media/platform/aspeed/aspeed-video.c
762
static void aspeed_video_swap_src_buf(struct aspeed_video *v)
drivers/media/platform/aspeed/aspeed-video.c
764
if (v->format == VIDEO_FMT_STANDARD)
drivers/media/platform/aspeed/aspeed-video.c
768
if (IS_ALIGNED(v->sequence, 8))
drivers/media/platform/aspeed/aspeed-video.c
769
memset((u8 *)v->bcd.virt, 0x00, VE_BCD_BUFF_SIZE);
drivers/media/platform/aspeed/aspeed-video.c
771
if (v->sequence & 0x01) {
drivers/media/platform/aspeed/aspeed-video.c
772
aspeed_video_write(v, VE_SRC0_ADDR, v->srcs[1].dma);
drivers/media/platform/aspeed/aspeed-video.c
773
aspeed_video_write(v, VE_SRC1_ADDR, v->srcs[0].dma);
drivers/media/platform/aspeed/aspeed-video.c
775
aspeed_video_write(v, VE_SRC0_ADDR, v->srcs[0].dma);
drivers/media/platform/aspeed/aspeed-video.c
776
aspeed_video_write(v, VE_SRC1_ADDR, v->srcs[1].dma);
drivers/media/platform/marvell/mcam-core.c
329
dma_addr_t y, u = 0, v = 0;
drivers/media/platform/marvell/mcam-core.c
336
v = u + pixel_count / 4;
drivers/media/platform/marvell/mcam-core.c
339
v = y + pixel_count;
drivers/media/platform/marvell/mcam-core.c
340
u = v + pixel_count / 4;
drivers/media/platform/marvell/mcam-core.c
349
mcam_reg_write(cam, REG_V0BAR + frame * 4, v);
drivers/media/platform/marvell/mcam-core.h
215
unsigned int v = mcam_reg_read(cam, reg);
drivers/media/platform/marvell/mcam-core.h
217
v = (v & ~mask) | (val & mask);
drivers/media/platform/marvell/mcam-core.h
218
mcam_reg_write(cam, reg, v);
drivers/media/platform/microchip/microchip-csi2dc.c
30
#define CSI2DC_GCFG_HLC(v) ((v) << 4)
drivers/media/platform/microchip/microchip-csi2dc.c
62
#define CSI2DC_VPCFG_DT(v) ((v) << 0)
drivers/media/platform/microchip/microchip-csi2dc.c
65
#define CSI2DC_VPCFG_VC(v) ((v) << 6)
drivers/media/platform/microchip/microchip-csi2dc.c
70
#define CSI2DC_VPCFG_DM(v) ((v) << 9)
drivers/media/platform/microchip/microchip-csi2dc.c
82
#define CSI2DC_VPCOL_COL(v) ((v) << 0)
drivers/media/platform/microchip/microchip-csi2dc.c
88
#define CSI2DC_VPROW_ROW(v) ((v) << 0)
drivers/media/platform/microchip/microchip-isc-regs.h
47
#define ISC_PFE_CFG1_COLMIN(v) ((v))
drivers/media/platform/microchip/microchip-isc-regs.h
49
#define ISC_PFE_CFG1_COLMAX(v) ((v) << 16)
drivers/media/platform/microchip/microchip-isc-regs.h
55
#define ISC_PFE_CFG2_ROWMIN(v) ((v))
drivers/media/platform/microchip/microchip-isc-regs.h
57
#define ISC_PFE_CFG2_ROWMAX(v) ((v) << 16)
drivers/media/platform/microchip/microchip-isc.h
38
#define to_isc_clk(v) container_of(v, struct isc_clk, hw)
drivers/media/platform/nxp/dw100/dw100_regs.h
86
#define DW100_BOUNDARY_PIXEL_V(v) (((v) & GENMASK(7, 0)) << 0)
drivers/media/platform/nxp/imx-jpeg/mxc-jpeg.c
1106
sof->comp[0].v = 0x2;
drivers/media/platform/nxp/imx-jpeg/mxc-jpeg.c
1112
sof->comp[0].v = 0x1;
drivers/media/platform/nxp/imx-jpeg/mxc-jpeg.h
156
u8 v :4;
drivers/media/platform/nxp/imx-pxp.h
1003
#define BF_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE(v) \
drivers/media/platform/nxp/imx-pxp.h
1004
(((v) << 1) & BM_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE)
drivers/media/platform/nxp/imx-pxp.h
101
#define BF_PXP_CTRL_HANDSHAKE_ABORT_SKIP(v) \
drivers/media/platform/nxp/imx-pxp.h
1010
#define BF_PXP_ALPHA_B_CTRL_POTER_DUFF_ENABLE(v) \
drivers/media/platform/nxp/imx-pxp.h
1011
(((v) << 0) & BM_PXP_ALPHA_B_CTRL_POTER_DUFF_ENABLE)
drivers/media/platform/nxp/imx-pxp.h
1019
#define BF_PXP_ALPHA_B_CTRL_1_RSVD0(v) \
drivers/media/platform/nxp/imx-pxp.h
102
(((v) << 5) & BM_PXP_CTRL_HANDSHAKE_ABORT_SKIP)
drivers/media/platform/nxp/imx-pxp.h
1020
(((v) << 8) & BM_PXP_ALPHA_B_CTRL_1_RSVD0)
drivers/media/platform/nxp/imx-pxp.h
1023
#define BF_PXP_ALPHA_B_CTRL_1_ROP(v) \
drivers/media/platform/nxp/imx-pxp.h
1024
(((v) << 4) & BM_PXP_ALPHA_B_CTRL_1_ROP)
drivers/media/platform/nxp/imx-pxp.h
1039
#define BF_PXP_ALPHA_B_CTRL_1_RSVD1(v) \
drivers/media/platform/nxp/imx-pxp.h
104
#define BF_PXP_CTRL_ENABLE_LCD0_HANDSHAKE(v) \
drivers/media/platform/nxp/imx-pxp.h
1040
(((v) << 2) & BM_PXP_ALPHA_B_CTRL_1_RSVD1)
drivers/media/platform/nxp/imx-pxp.h
1042
#define BF_PXP_ALPHA_B_CTRL_1_OL_CLRKEY_ENABLE(v) \
drivers/media/platform/nxp/imx-pxp.h
1043
(((v) << 1) & BM_PXP_ALPHA_B_CTRL_1_OL_CLRKEY_ENABLE)
drivers/media/platform/nxp/imx-pxp.h
1045
#define BF_PXP_ALPHA_B_CTRL_1_ROP_ENABLE(v) \
drivers/media/platform/nxp/imx-pxp.h
1046
(((v) << 0) & BM_PXP_ALPHA_B_CTRL_1_ROP_ENABLE)
drivers/media/platform/nxp/imx-pxp.h
105
(((v) << 4) & BM_PXP_CTRL_ENABLE_LCD0_HANDSHAKE)
drivers/media/platform/nxp/imx-pxp.h
1052
#define BF_PXP_PS_BACKGROUND_1_RSVD(v) \
drivers/media/platform/nxp/imx-pxp.h
1053
(((v) << 24) & BM_PXP_PS_BACKGROUND_1_RSVD)
drivers/media/platform/nxp/imx-pxp.h
1056
#define BF_PXP_PS_BACKGROUND_1_COLOR(v) \
drivers/media/platform/nxp/imx-pxp.h
1057
(((v) << 0) & BM_PXP_PS_BACKGROUND_1_COLOR)
drivers/media/platform/nxp/imx-pxp.h
1063
#define BF_PXP_PS_CLRKEYLOW_1_RSVD1(v) \
drivers/media/platform/nxp/imx-pxp.h
1064
(((v) << 24) & BM_PXP_PS_CLRKEYLOW_1_RSVD1)
drivers/media/platform/nxp/imx-pxp.h
1067
#define BF_PXP_PS_CLRKEYLOW_1_PIXEL(v) \
drivers/media/platform/nxp/imx-pxp.h
1068
(((v) << 0) & BM_PXP_PS_CLRKEYLOW_1_PIXEL)
drivers/media/platform/nxp/imx-pxp.h
107
#define BF_PXP_CTRL_LUT_DMA_IRQ_ENABLE(v) \
drivers/media/platform/nxp/imx-pxp.h
1074
#define BF_PXP_PS_CLRKEYHIGH_1_RSVD1(v) \
drivers/media/platform/nxp/imx-pxp.h
1075
(((v) << 24) & BM_PXP_PS_CLRKEYHIGH_1_RSVD1)
drivers/media/platform/nxp/imx-pxp.h
1078
#define BF_PXP_PS_CLRKEYHIGH_1_PIXEL(v) \
drivers/media/platform/nxp/imx-pxp.h
1079
(((v) << 0) & BM_PXP_PS_CLRKEYHIGH_1_PIXEL)
drivers/media/platform/nxp/imx-pxp.h
108
(((v) << 3) & BM_PXP_CTRL_LUT_DMA_IRQ_ENABLE)
drivers/media/platform/nxp/imx-pxp.h
1085
#define BF_PXP_AS_CLRKEYLOW_1_RSVD1(v) \
drivers/media/platform/nxp/imx-pxp.h
1086
(((v) << 24) & BM_PXP_AS_CLRKEYLOW_1_RSVD1)
drivers/media/platform/nxp/imx-pxp.h
1089
#define BF_PXP_AS_CLRKEYLOW_1_PIXEL(v) \
drivers/media/platform/nxp/imx-pxp.h
1090
(((v) << 0) & BM_PXP_AS_CLRKEYLOW_1_PIXEL)
drivers/media/platform/nxp/imx-pxp.h
1096
#define BF_PXP_AS_CLRKEYHIGH_1_RSVD1(v) \
drivers/media/platform/nxp/imx-pxp.h
1097
(((v) << 24) & BM_PXP_AS_CLRKEYHIGH_1_RSVD1)
drivers/media/platform/nxp/imx-pxp.h
110
#define BF_PXP_CTRL_NEXT_IRQ_ENABLE(v) \
drivers/media/platform/nxp/imx-pxp.h
1100
#define BF_PXP_AS_CLRKEYHIGH_1_PIXEL(v) \
drivers/media/platform/nxp/imx-pxp.h
1101
(((v) << 0) & BM_PXP_AS_CLRKEYHIGH_1_PIXEL)
drivers/media/platform/nxp/imx-pxp.h
111
(((v) << 2) & BM_PXP_CTRL_NEXT_IRQ_ENABLE)
drivers/media/platform/nxp/imx-pxp.h
1110
#define BF_PXP_CTRL2_RSVD3(v) \
drivers/media/platform/nxp/imx-pxp.h
1111
(((v) << 28) & BM_PXP_CTRL2_RSVD3)
drivers/media/platform/nxp/imx-pxp.h
1113
#define BF_PXP_CTRL2_ENABLE_ROTATE1(v) \
drivers/media/platform/nxp/imx-pxp.h
1114
(((v) << 27) & BM_PXP_CTRL2_ENABLE_ROTATE1)
drivers/media/platform/nxp/imx-pxp.h
1116
#define BF_PXP_CTRL2_ENABLE_ROTATE0(v) \
drivers/media/platform/nxp/imx-pxp.h
1117
(((v) << 26) & BM_PXP_CTRL2_ENABLE_ROTATE0)
drivers/media/platform/nxp/imx-pxp.h
1119
#define BF_PXP_CTRL2_ENABLE_LUT(v) \
drivers/media/platform/nxp/imx-pxp.h
1120
(((v) << 25) & BM_PXP_CTRL2_ENABLE_LUT)
drivers/media/platform/nxp/imx-pxp.h
1122
#define BF_PXP_CTRL2_ENABLE_CSC2(v) \
drivers/media/platform/nxp/imx-pxp.h
1123
(((v) << 24) & BM_PXP_CTRL2_ENABLE_CSC2)
drivers/media/platform/nxp/imx-pxp.h
1125
#define BF_PXP_CTRL2_BLOCK_SIZE(v) \
drivers/media/platform/nxp/imx-pxp.h
1126
(((v) << 23) & BM_PXP_CTRL2_BLOCK_SIZE)
drivers/media/platform/nxp/imx-pxp.h
113
#define BF_PXP_CTRL_IRQ_ENABLE(v) \
drivers/media/platform/nxp/imx-pxp.h
1130
#define BF_PXP_CTRL2_RSVD2(v) \
drivers/media/platform/nxp/imx-pxp.h
1131
(((v) << 22) & BM_PXP_CTRL2_RSVD2)
drivers/media/platform/nxp/imx-pxp.h
1133
#define BF_PXP_CTRL2_ENABLE_ALPHA_B(v) \
drivers/media/platform/nxp/imx-pxp.h
1134
(((v) << 21) & BM_PXP_CTRL2_ENABLE_ALPHA_B)
drivers/media/platform/nxp/imx-pxp.h
1136
#define BF_PXP_CTRL2_ENABLE_INPUT_FETCH_STORE(v) \
drivers/media/platform/nxp/imx-pxp.h
1137
(((v) << 20) & BM_PXP_CTRL2_ENABLE_INPUT_FETCH_STORE)
drivers/media/platform/nxp/imx-pxp.h
1139
#define BF_PXP_CTRL2_ENABLE_WFE_B(v) \
drivers/media/platform/nxp/imx-pxp.h
114
(((v) << 1) & BM_PXP_CTRL_IRQ_ENABLE)
drivers/media/platform/nxp/imx-pxp.h
1140
(((v) << 19) & BM_PXP_CTRL2_ENABLE_WFE_B)
drivers/media/platform/nxp/imx-pxp.h
1142
#define BF_PXP_CTRL2_ENABLE_WFE_A(v) \
drivers/media/platform/nxp/imx-pxp.h
1143
(((v) << 18) & BM_PXP_CTRL2_ENABLE_WFE_A)
drivers/media/platform/nxp/imx-pxp.h
1145
#define BF_PXP_CTRL2_ENABLE_DITHER(v) \
drivers/media/platform/nxp/imx-pxp.h
1146
(((v) << 17) & BM_PXP_CTRL2_ENABLE_DITHER)
drivers/media/platform/nxp/imx-pxp.h
1148
#define BF_PXP_CTRL2_RSVD1(v) \
drivers/media/platform/nxp/imx-pxp.h
1149
(((v) << 16) & BM_PXP_CTRL2_RSVD1)
drivers/media/platform/nxp/imx-pxp.h
1151
#define BF_PXP_CTRL2_VFLIP1(v) \
drivers/media/platform/nxp/imx-pxp.h
1152
(((v) << 15) & BM_PXP_CTRL2_VFLIP1)
drivers/media/platform/nxp/imx-pxp.h
1154
#define BF_PXP_CTRL2_HFLIP1(v) \
drivers/media/platform/nxp/imx-pxp.h
1155
(((v) << 14) & BM_PXP_CTRL2_HFLIP1)
drivers/media/platform/nxp/imx-pxp.h
1158
#define BF_PXP_CTRL2_ROTATE1(v) \
drivers/media/platform/nxp/imx-pxp.h
1159
(((v) << 12) & BM_PXP_CTRL2_ROTATE1)
drivers/media/platform/nxp/imx-pxp.h
116
#define BF_PXP_CTRL_ENABLE(v) \
drivers/media/platform/nxp/imx-pxp.h
1165
#define BF_PXP_CTRL2_VFLIP0(v) \
drivers/media/platform/nxp/imx-pxp.h
1166
(((v) << 11) & BM_PXP_CTRL2_VFLIP0)
drivers/media/platform/nxp/imx-pxp.h
1168
#define BF_PXP_CTRL2_HFLIP0(v) \
drivers/media/platform/nxp/imx-pxp.h
1169
(((v) << 10) & BM_PXP_CTRL2_HFLIP0)
drivers/media/platform/nxp/imx-pxp.h
117
(((v) << 0) & BM_PXP_CTRL_ENABLE)
drivers/media/platform/nxp/imx-pxp.h
1172
#define BF_PXP_CTRL2_ROTATE0(v) \
drivers/media/platform/nxp/imx-pxp.h
1173
(((v) << 8) & BM_PXP_CTRL2_ROTATE0)
drivers/media/platform/nxp/imx-pxp.h
1180
#define BF_PXP_CTRL2_RSVD0(v) \
drivers/media/platform/nxp/imx-pxp.h
1181
(((v) << 1) & BM_PXP_CTRL2_RSVD0)
drivers/media/platform/nxp/imx-pxp.h
1183
#define BF_PXP_CTRL2_ENABLE(v) \
drivers/media/platform/nxp/imx-pxp.h
1184
(((v) << 0) & BM_PXP_CTRL2_ENABLE)
drivers/media/platform/nxp/imx-pxp.h
1190
#define BF_PXP_POWER_REG0_CTRL(v) \
drivers/media/platform/nxp/imx-pxp.h
1191
(((v) << 12) & BM_PXP_POWER_REG0_CTRL)
drivers/media/platform/nxp/imx-pxp.h
1194
#define BF_PXP_POWER_REG0_ROT0_MEM_LP_STATE(v) \
drivers/media/platform/nxp/imx-pxp.h
1195
(((v) << 9) & BM_PXP_POWER_REG0_ROT0_MEM_LP_STATE)
drivers/media/platform/nxp/imx-pxp.h
1202
#define BF_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN(v) \
drivers/media/platform/nxp/imx-pxp.h
1203
(((v) << 6) & BM_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN)
drivers/media/platform/nxp/imx-pxp.h
1210
#define BF_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN(v) \
drivers/media/platform/nxp/imx-pxp.h
1211
(((v) << 3) & BM_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN)
drivers/media/platform/nxp/imx-pxp.h
1218
#define BF_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0(v) \
drivers/media/platform/nxp/imx-pxp.h
1219
(((v) << 0) & BM_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0)
drivers/media/platform/nxp/imx-pxp.h
1229
#define BF_PXP_POWER_REG1_RSVD0(v) \
drivers/media/platform/nxp/imx-pxp.h
1230
(((v) << 24) & BM_PXP_POWER_REG1_RSVD0)
drivers/media/platform/nxp/imx-pxp.h
1233
#define BF_PXP_POWER_REG1_ALU_B_MEM_LP_STATE(v) \
drivers/media/platform/nxp/imx-pxp.h
1234
(((v) << 21) & BM_PXP_POWER_REG1_ALU_B_MEM_LP_STATE)
drivers/media/platform/nxp/imx-pxp.h
1241
#define BF_PXP_POWER_REG1_ALU_A_MEM_LP_STATE(v) \
drivers/media/platform/nxp/imx-pxp.h
1242
(((v) << 18) & BM_PXP_POWER_REG1_ALU_A_MEM_LP_STATE)
drivers/media/platform/nxp/imx-pxp.h
1249
#define BF_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE(v) \
drivers/media/platform/nxp/imx-pxp.h
1250
(((v) << 15) & BM_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE)
drivers/media/platform/nxp/imx-pxp.h
1257
#define BF_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE(v) \
drivers/media/platform/nxp/imx-pxp.h
1258
(((v) << 12) & BM_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE)
drivers/media/platform/nxp/imx-pxp.h
126
#define BF_PXP_STAT_BLOCKX(v) \
drivers/media/platform/nxp/imx-pxp.h
1265
#define BF_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE(v) \
drivers/media/platform/nxp/imx-pxp.h
1266
(((v) << 9) & BM_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE)
drivers/media/platform/nxp/imx-pxp.h
127
(((v) << 24) & BM_PXP_STAT_BLOCKX)
drivers/media/platform/nxp/imx-pxp.h
1273
#define BF_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE(v) \
drivers/media/platform/nxp/imx-pxp.h
1274
(((v) << 6) & BM_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE)
drivers/media/platform/nxp/imx-pxp.h
1281
#define BF_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE(v) \
drivers/media/platform/nxp/imx-pxp.h
1282
(((v) << 3) & BM_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE)
drivers/media/platform/nxp/imx-pxp.h
1289
#define BF_PXP_POWER_REG1_ROT1_MEM_LP_STATE(v) \
drivers/media/platform/nxp/imx-pxp.h
1290
(((v) << 0) & BM_PXP_POWER_REG1_ROT1_MEM_LP_STATE)
drivers/media/platform/nxp/imx-pxp.h
130
#define BF_PXP_STAT_BLOCKY(v) \
drivers/media/platform/nxp/imx-pxp.h
1303
#define BF_PXP_DATA_PATH_CTRL0_MUX15_SEL(v) \
drivers/media/platform/nxp/imx-pxp.h
1304
(((v) << 30) & BM_PXP_DATA_PATH_CTRL0_MUX15_SEL)
drivers/media/platform/nxp/imx-pxp.h
131
(((v) << 16) & BM_PXP_STAT_BLOCKY)
drivers/media/platform/nxp/imx-pxp.h
1311
#define BF_PXP_DATA_PATH_CTRL0_MUX14_SEL(v) \
drivers/media/platform/nxp/imx-pxp.h
1312
(((v) << 28) & BM_PXP_DATA_PATH_CTRL0_MUX14_SEL)
drivers/media/platform/nxp/imx-pxp.h
1319
#define BF_PXP_DATA_PATH_CTRL0_MUX13_SEL(v) \
drivers/media/platform/nxp/imx-pxp.h
1320
(((v) << 26) & BM_PXP_DATA_PATH_CTRL0_MUX13_SEL)
drivers/media/platform/nxp/imx-pxp.h
1327
#define BF_PXP_DATA_PATH_CTRL0_MUX12_SEL(v) \
drivers/media/platform/nxp/imx-pxp.h
1328
(((v) << 24) & BM_PXP_DATA_PATH_CTRL0_MUX12_SEL)
drivers/media/platform/nxp/imx-pxp.h
1335
#define BF_PXP_DATA_PATH_CTRL0_MUX11_SEL(v) \
drivers/media/platform/nxp/imx-pxp.h
1336
(((v) << 22) & BM_PXP_DATA_PATH_CTRL0_MUX11_SEL)
drivers/media/platform/nxp/imx-pxp.h
134
#define BF_PXP_STAT_AXI_ERROR_ID_1(v) \
drivers/media/platform/nxp/imx-pxp.h
1343
#define BF_PXP_DATA_PATH_CTRL0_MUX10_SEL(v) \
drivers/media/platform/nxp/imx-pxp.h
1344
(((v) << 20) & BM_PXP_DATA_PATH_CTRL0_MUX10_SEL)
drivers/media/platform/nxp/imx-pxp.h
135
(((v) << 12) & BM_PXP_STAT_AXI_ERROR_ID_1)
drivers/media/platform/nxp/imx-pxp.h
1351
#define BF_PXP_DATA_PATH_CTRL0_MUX9_SEL(v) \
drivers/media/platform/nxp/imx-pxp.h
1352
(((v) << 18) & BM_PXP_DATA_PATH_CTRL0_MUX9_SEL)
drivers/media/platform/nxp/imx-pxp.h
1359
#define BF_PXP_DATA_PATH_CTRL0_MUX8_SEL(v) \
drivers/media/platform/nxp/imx-pxp.h
1360
(((v) << 16) & BM_PXP_DATA_PATH_CTRL0_MUX8_SEL)
drivers/media/platform/nxp/imx-pxp.h
1367
#define BF_PXP_DATA_PATH_CTRL0_MUX7_SEL(v) \
drivers/media/platform/nxp/imx-pxp.h
1368
(((v) << 14) & BM_PXP_DATA_PATH_CTRL0_MUX7_SEL)
drivers/media/platform/nxp/imx-pxp.h
137
#define BF_PXP_STAT_RSVD2(v) \
drivers/media/platform/nxp/imx-pxp.h
1375
#define BF_PXP_DATA_PATH_CTRL0_MUX6_SEL(v) \
drivers/media/platform/nxp/imx-pxp.h
1376
(((v) << 12) & BM_PXP_DATA_PATH_CTRL0_MUX6_SEL)
drivers/media/platform/nxp/imx-pxp.h
138
(((v) << 11) & BM_PXP_STAT_RSVD2)
drivers/media/platform/nxp/imx-pxp.h
1383
#define BF_PXP_DATA_PATH_CTRL0_MUX5_SEL(v) \
drivers/media/platform/nxp/imx-pxp.h
1384
(((v) << 10) & BM_PXP_DATA_PATH_CTRL0_MUX5_SEL)
drivers/media/platform/nxp/imx-pxp.h
1391
#define BF_PXP_DATA_PATH_CTRL0_MUX4_SEL(v) \
drivers/media/platform/nxp/imx-pxp.h
1392
(((v) << 8) & BM_PXP_DATA_PATH_CTRL0_MUX4_SEL)
drivers/media/platform/nxp/imx-pxp.h
1399
#define BF_PXP_DATA_PATH_CTRL0_MUX3_SEL(v) \
drivers/media/platform/nxp/imx-pxp.h
140
#define BF_PXP_STAT_AXI_READ_ERROR_1(v) \
drivers/media/platform/nxp/imx-pxp.h
1400
(((v) << 6) & BM_PXP_DATA_PATH_CTRL0_MUX3_SEL)
drivers/media/platform/nxp/imx-pxp.h
1407
#define BF_PXP_DATA_PATH_CTRL0_MUX2_SEL(v) \
drivers/media/platform/nxp/imx-pxp.h
1408
(((v) << 4) & BM_PXP_DATA_PATH_CTRL0_MUX2_SEL)
drivers/media/platform/nxp/imx-pxp.h
141
(((v) << 10) & BM_PXP_STAT_AXI_READ_ERROR_1)
drivers/media/platform/nxp/imx-pxp.h
1415
#define BF_PXP_DATA_PATH_CTRL0_MUX1_SEL(v) \
drivers/media/platform/nxp/imx-pxp.h
1416
(((v) << 2) & BM_PXP_DATA_PATH_CTRL0_MUX1_SEL)
drivers/media/platform/nxp/imx-pxp.h
1423
#define BF_PXP_DATA_PATH_CTRL0_MUX0_SEL(v) \
drivers/media/platform/nxp/imx-pxp.h
1424
(((v) << 0) & BM_PXP_DATA_PATH_CTRL0_MUX0_SEL)
drivers/media/platform/nxp/imx-pxp.h
143
#define BF_PXP_STAT_AXI_WRITE_ERROR_1(v) \
drivers/media/platform/nxp/imx-pxp.h
1437
#define BF_PXP_DATA_PATH_CTRL1_RSVD0(v) \
drivers/media/platform/nxp/imx-pxp.h
1438
(((v) << 4) & BM_PXP_DATA_PATH_CTRL1_RSVD0)
drivers/media/platform/nxp/imx-pxp.h
144
(((v) << 9) & BM_PXP_STAT_AXI_WRITE_ERROR_1)
drivers/media/platform/nxp/imx-pxp.h
1441
#define BF_PXP_DATA_PATH_CTRL1_MUX17_SEL(v) \
drivers/media/platform/nxp/imx-pxp.h
1442
(((v) << 2) & BM_PXP_DATA_PATH_CTRL1_MUX17_SEL)
drivers/media/platform/nxp/imx-pxp.h
1449
#define BF_PXP_DATA_PATH_CTRL1_MUX16_SEL(v) \
drivers/media/platform/nxp/imx-pxp.h
1450
(((v) << 0) & BM_PXP_DATA_PATH_CTRL1_MUX16_SEL)
drivers/media/platform/nxp/imx-pxp.h
146
#define BF_PXP_STAT_LUT_DMA_LOAD_DONE_IRQ(v) \
drivers/media/platform/nxp/imx-pxp.h
1462
#define BF_PXP_INIT_MEM_CTRL_START(v) \
drivers/media/platform/nxp/imx-pxp.h
1463
(((v) << 31) & BM_PXP_INIT_MEM_CTRL_START)
drivers/media/platform/nxp/imx-pxp.h
1466
#define BF_PXP_INIT_MEM_CTRL_SELECT(v) \
drivers/media/platform/nxp/imx-pxp.h
1467
(((v) << 27) & BM_PXP_INIT_MEM_CTRL_SELECT)
drivers/media/platform/nxp/imx-pxp.h
147
(((v) << 8) & BM_PXP_STAT_LUT_DMA_LOAD_DONE_IRQ)
drivers/media/platform/nxp/imx-pxp.h
1480
#define BF_PXP_INIT_MEM_CTRL_RSVD0(v) \
drivers/media/platform/nxp/imx-pxp.h
1481
(((v) << 16) & BM_PXP_INIT_MEM_CTRL_RSVD0)
drivers/media/platform/nxp/imx-pxp.h
1484
#define BF_PXP_INIT_MEM_CTRL_ADDR(v) \
drivers/media/platform/nxp/imx-pxp.h
1485
(((v) << 0) & BM_PXP_INIT_MEM_CTRL_ADDR)
drivers/media/platform/nxp/imx-pxp.h
1491
#define BF_PXP_INIT_MEM_DATA_DATA(v) (v)
drivers/media/platform/nxp/imx-pxp.h
1497
#define BF_PXP_INIT_MEM_DATA_HIGH_DATA(v) (v)
drivers/media/platform/nxp/imx-pxp.h
150
#define BF_PXP_STAT_AXI_ERROR_ID_0(v) \
drivers/media/platform/nxp/imx-pxp.h
1505
#define BF_PXP_IRQ_MASK_COMPRESS_DONE_IRQ_EN(v) \
drivers/media/platform/nxp/imx-pxp.h
1506
(((v) << 31) & BM_PXP_IRQ_MASK_COMPRESS_DONE_IRQ_EN)
drivers/media/platform/nxp/imx-pxp.h
1509
#define BF_PXP_IRQ_MASK_RSVD1(v) \
drivers/media/platform/nxp/imx-pxp.h
151
(((v) << 4) & BM_PXP_STAT_AXI_ERROR_ID_0)
drivers/media/platform/nxp/imx-pxp.h
1510
(((v) << 16) & BM_PXP_IRQ_MASK_RSVD1)
drivers/media/platform/nxp/imx-pxp.h
1512
#define BF_PXP_IRQ_MASK_WFE_B_STORE_IRQ_EN(v) \
drivers/media/platform/nxp/imx-pxp.h
1513
(((v) << 15) & BM_PXP_IRQ_MASK_WFE_B_STORE_IRQ_EN)
drivers/media/platform/nxp/imx-pxp.h
1515
#define BF_PXP_IRQ_MASK_WFE_A_STORE_IRQ_EN(v) \
drivers/media/platform/nxp/imx-pxp.h
1516
(((v) << 14) & BM_PXP_IRQ_MASK_WFE_A_STORE_IRQ_EN)
drivers/media/platform/nxp/imx-pxp.h
1518
#define BF_PXP_IRQ_MASK_DITHER_STORE_IRQ_EN(v) \
drivers/media/platform/nxp/imx-pxp.h
1519
(((v) << 13) & BM_PXP_IRQ_MASK_DITHER_STORE_IRQ_EN)
drivers/media/platform/nxp/imx-pxp.h
1521
#define BF_PXP_IRQ_MASK_FIRST_STORE_IRQ_EN(v) \
drivers/media/platform/nxp/imx-pxp.h
1522
(((v) << 12) & BM_PXP_IRQ_MASK_FIRST_STORE_IRQ_EN)
drivers/media/platform/nxp/imx-pxp.h
1524
#define BF_PXP_IRQ_MASK_WFE_B_CH1_STORE_IRQ_EN(v) \
drivers/media/platform/nxp/imx-pxp.h
1525
(((v) << 11) & BM_PXP_IRQ_MASK_WFE_B_CH1_STORE_IRQ_EN)
drivers/media/platform/nxp/imx-pxp.h
1527
#define BF_PXP_IRQ_MASK_WFE_B_CH0_STORE_IRQ_EN(v) \
drivers/media/platform/nxp/imx-pxp.h
1528
(((v) << 10) & BM_PXP_IRQ_MASK_WFE_B_CH0_STORE_IRQ_EN)
drivers/media/platform/nxp/imx-pxp.h
153
#define BF_PXP_STAT_NEXT_IRQ(v) \
drivers/media/platform/nxp/imx-pxp.h
1530
#define BF_PXP_IRQ_MASK_WFE_A_CH1_STORE_IRQ_EN(v) \
drivers/media/platform/nxp/imx-pxp.h
1531
(((v) << 9) & BM_PXP_IRQ_MASK_WFE_A_CH1_STORE_IRQ_EN)
drivers/media/platform/nxp/imx-pxp.h
1533
#define BF_PXP_IRQ_MASK_WFE_A_CH0_STORE_IRQ_EN(v) \
drivers/media/platform/nxp/imx-pxp.h
1534
(((v) << 8) & BM_PXP_IRQ_MASK_WFE_A_CH0_STORE_IRQ_EN)
drivers/media/platform/nxp/imx-pxp.h
1536
#define BF_PXP_IRQ_MASK_DITHER_CH1_STORE_IRQ_EN(v) \
drivers/media/platform/nxp/imx-pxp.h
1537
(((v) << 7) & BM_PXP_IRQ_MASK_DITHER_CH1_STORE_IRQ_EN)
drivers/media/platform/nxp/imx-pxp.h
1539
#define BF_PXP_IRQ_MASK_DITHER_CH0_STORE_IRQ_EN(v) \
drivers/media/platform/nxp/imx-pxp.h
154
(((v) << 3) & BM_PXP_STAT_NEXT_IRQ)
drivers/media/platform/nxp/imx-pxp.h
1540
(((v) << 6) & BM_PXP_IRQ_MASK_DITHER_CH0_STORE_IRQ_EN)
drivers/media/platform/nxp/imx-pxp.h
1542
#define BF_PXP_IRQ_MASK_DITHER_CH1_PREFETCH_IRQ_EN(v) \
drivers/media/platform/nxp/imx-pxp.h
1543
(((v) << 5) & BM_PXP_IRQ_MASK_DITHER_CH1_PREFETCH_IRQ_EN)
drivers/media/platform/nxp/imx-pxp.h
1545
#define BF_PXP_IRQ_MASK_DITHER_CH0_PREFETCH_IRQ_EN(v) \
drivers/media/platform/nxp/imx-pxp.h
1546
(((v) << 4) & BM_PXP_IRQ_MASK_DITHER_CH0_PREFETCH_IRQ_EN)
drivers/media/platform/nxp/imx-pxp.h
1548
#define BF_PXP_IRQ_MASK_FIRST_CH1_STORE_IRQ_EN(v) \
drivers/media/platform/nxp/imx-pxp.h
1549
(((v) << 3) & BM_PXP_IRQ_MASK_FIRST_CH1_STORE_IRQ_EN)
drivers/media/platform/nxp/imx-pxp.h
1551
#define BF_PXP_IRQ_MASK_FIRST_CH0_STORE_IRQ_EN(v) \
drivers/media/platform/nxp/imx-pxp.h
1552
(((v) << 2) & BM_PXP_IRQ_MASK_FIRST_CH0_STORE_IRQ_EN)
drivers/media/platform/nxp/imx-pxp.h
1554
#define BF_PXP_IRQ_MASK_FIRST_CH1_PREFETCH_IRQ_EN(v) \
drivers/media/platform/nxp/imx-pxp.h
1555
(((v) << 1) & BM_PXP_IRQ_MASK_FIRST_CH1_PREFETCH_IRQ_EN)
drivers/media/platform/nxp/imx-pxp.h
1557
#define BF_PXP_IRQ_MASK_FIRST_CH0_PREFETCH_IRQ_EN(v) \
drivers/media/platform/nxp/imx-pxp.h
1558
(((v) << 0) & BM_PXP_IRQ_MASK_FIRST_CH0_PREFETCH_IRQ_EN)
drivers/media/platform/nxp/imx-pxp.h
156
#define BF_PXP_STAT_AXI_READ_ERROR_0(v) \
drivers/media/platform/nxp/imx-pxp.h
1566
#define BF_PXP_IRQ_COMPRESS_DONE_IRQ(v) \
drivers/media/platform/nxp/imx-pxp.h
1567
(((v) << 31) & BM_PXP_IRQ_COMPRESS_DONE_IRQ)
drivers/media/platform/nxp/imx-pxp.h
157
(((v) << 2) & BM_PXP_STAT_AXI_READ_ERROR_0)
drivers/media/platform/nxp/imx-pxp.h
1570
#define BF_PXP_IRQ_RSVD1(v) \
drivers/media/platform/nxp/imx-pxp.h
1571
(((v) << 16) & BM_PXP_IRQ_RSVD1)
drivers/media/platform/nxp/imx-pxp.h
1573
#define BF_PXP_IRQ_WFE_B_STORE_IRQ(v) \
drivers/media/platform/nxp/imx-pxp.h
1574
(((v) << 15) & BM_PXP_IRQ_WFE_B_STORE_IRQ)
drivers/media/platform/nxp/imx-pxp.h
1576
#define BF_PXP_IRQ_WFE_A_STORE_IRQ(v) \
drivers/media/platform/nxp/imx-pxp.h
1577
(((v) << 14) & BM_PXP_IRQ_WFE_A_STORE_IRQ)
drivers/media/platform/nxp/imx-pxp.h
1579
#define BF_PXP_IRQ_DITHER_STORE_IRQ(v) \
drivers/media/platform/nxp/imx-pxp.h
1580
(((v) << 13) & BM_PXP_IRQ_DITHER_STORE_IRQ)
drivers/media/platform/nxp/imx-pxp.h
1582
#define BF_PXP_IRQ_FIRST_STORE_IRQ(v) \
drivers/media/platform/nxp/imx-pxp.h
1583
(((v) << 12) & BM_PXP_IRQ_FIRST_STORE_IRQ)
drivers/media/platform/nxp/imx-pxp.h
1585
#define BF_PXP_IRQ_WFE_B_CH1_STORE_IRQ(v) \
drivers/media/platform/nxp/imx-pxp.h
1586
(((v) << 11) & BM_PXP_IRQ_WFE_B_CH1_STORE_IRQ)
drivers/media/platform/nxp/imx-pxp.h
1588
#define BF_PXP_IRQ_WFE_B_CH0_STORE_IRQ(v) \
drivers/media/platform/nxp/imx-pxp.h
1589
(((v) << 10) & BM_PXP_IRQ_WFE_B_CH0_STORE_IRQ)
drivers/media/platform/nxp/imx-pxp.h
159
#define BF_PXP_STAT_AXI_WRITE_ERROR_0(v) \
drivers/media/platform/nxp/imx-pxp.h
1591
#define BF_PXP_IRQ_WFE_A_CH1_STORE_IRQ(v) \
drivers/media/platform/nxp/imx-pxp.h
1592
(((v) << 9) & BM_PXP_IRQ_WFE_A_CH1_STORE_IRQ)
drivers/media/platform/nxp/imx-pxp.h
1594
#define BF_PXP_IRQ_WFE_A_CH0_STORE_IRQ(v) \
drivers/media/platform/nxp/imx-pxp.h
1595
(((v) << 8) & BM_PXP_IRQ_WFE_A_CH0_STORE_IRQ)
drivers/media/platform/nxp/imx-pxp.h
1597
#define BF_PXP_IRQ_DITHER_CH1_STORE_IRQ(v) \
drivers/media/platform/nxp/imx-pxp.h
1598
(((v) << 7) & BM_PXP_IRQ_DITHER_CH1_STORE_IRQ)
drivers/media/platform/nxp/imx-pxp.h
160
(((v) << 1) & BM_PXP_STAT_AXI_WRITE_ERROR_0)
drivers/media/platform/nxp/imx-pxp.h
1600
#define BF_PXP_IRQ_DITHER_CH0_STORE_IRQ(v) \
drivers/media/platform/nxp/imx-pxp.h
1601
(((v) << 6) & BM_PXP_IRQ_DITHER_CH0_STORE_IRQ)
drivers/media/platform/nxp/imx-pxp.h
1603
#define BF_PXP_IRQ_DITHER_CH1_PREFETCH_IRQ(v) \
drivers/media/platform/nxp/imx-pxp.h
1604
(((v) << 5) & BM_PXP_IRQ_DITHER_CH1_PREFETCH_IRQ)
drivers/media/platform/nxp/imx-pxp.h
1606
#define BF_PXP_IRQ_DITHER_CH0_PREFETCH_IRQ(v) \
drivers/media/platform/nxp/imx-pxp.h
1607
(((v) << 4) & BM_PXP_IRQ_DITHER_CH0_PREFETCH_IRQ)
drivers/media/platform/nxp/imx-pxp.h
1609
#define BF_PXP_IRQ_FIRST_CH1_STORE_IRQ(v) \
drivers/media/platform/nxp/imx-pxp.h
1610
(((v) << 3) & BM_PXP_IRQ_FIRST_CH1_STORE_IRQ)
drivers/media/platform/nxp/imx-pxp.h
1612
#define BF_PXP_IRQ_FIRST_CH0_STORE_IRQ(v) \
drivers/media/platform/nxp/imx-pxp.h
1613
(((v) << 2) & BM_PXP_IRQ_FIRST_CH0_STORE_IRQ)
drivers/media/platform/nxp/imx-pxp.h
1615
#define BF_PXP_IRQ_FIRST_CH1_PREFETCH_IRQ(v) \
drivers/media/platform/nxp/imx-pxp.h
1616
(((v) << 1) & BM_PXP_IRQ_FIRST_CH1_PREFETCH_IRQ)
drivers/media/platform/nxp/imx-pxp.h
1618
#define BF_PXP_IRQ_FIRST_CH0_PREFETCH_IRQ(v) \
drivers/media/platform/nxp/imx-pxp.h
1619
(((v) << 0) & BM_PXP_IRQ_FIRST_CH0_PREFETCH_IRQ)
drivers/media/platform/nxp/imx-pxp.h
162
#define BF_PXP_STAT_IRQ0(v) \
drivers/media/platform/nxp/imx-pxp.h
1625
#define BF_PXP_NEXT_POINTER(v) \
drivers/media/platform/nxp/imx-pxp.h
1626
(((v) << 2) & BM_PXP_NEXT_POINTER)
drivers/media/platform/nxp/imx-pxp.h
1628
#define BF_PXP_NEXT_RSVD(v) \
drivers/media/platform/nxp/imx-pxp.h
1629
(((v) << 1) & BM_PXP_NEXT_RSVD)
drivers/media/platform/nxp/imx-pxp.h
163
(((v) << 0) & BM_PXP_STAT_IRQ0)
drivers/media/platform/nxp/imx-pxp.h
1631
#define BF_PXP_NEXT_ENABLED(v) \
drivers/media/platform/nxp/imx-pxp.h
1632
(((v) << 0) & BM_PXP_NEXT_ENABLED)
drivers/media/platform/nxp/imx-pxp.h
1638
#define BF_PXP_DEBUGCTRL_RSVD(v) \
drivers/media/platform/nxp/imx-pxp.h
1639
(((v) << 12) & BM_PXP_DEBUGCTRL_RSVD)
drivers/media/platform/nxp/imx-pxp.h
1642
#define BF_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT(v) \
drivers/media/platform/nxp/imx-pxp.h
1643
(((v) << 8) & BM_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT)
drivers/media/platform/nxp/imx-pxp.h
1651
#define BF_PXP_DEBUGCTRL_SELECT(v) \
drivers/media/platform/nxp/imx-pxp.h
1652
(((v) << 0) & BM_PXP_DEBUGCTRL_SELECT)
drivers/media/platform/nxp/imx-pxp.h
1673
#define BF_PXP_DEBUG_DATA(v) (v)
drivers/media/platform/nxp/imx-pxp.h
1679
#define BF_PXP_VERSION_MAJOR(v) \
drivers/media/platform/nxp/imx-pxp.h
1680
(((v) << 24) & BM_PXP_VERSION_MAJOR)
drivers/media/platform/nxp/imx-pxp.h
1683
#define BF_PXP_VERSION_MINOR(v) \
drivers/media/platform/nxp/imx-pxp.h
1684
(((v) << 16) & BM_PXP_VERSION_MINOR)
drivers/media/platform/nxp/imx-pxp.h
1687
#define BF_PXP_VERSION_STEP(v) \
drivers/media/platform/nxp/imx-pxp.h
1688
(((v) << 0) & BM_PXP_VERSION_STEP)
drivers/media/platform/nxp/imx-pxp.h
172
#define BF_PXP_OUT_CTRL_ALPHA(v) \
drivers/media/platform/nxp/imx-pxp.h
173
(((v) << 24) & BM_PXP_OUT_CTRL_ALPHA)
drivers/media/platform/nxp/imx-pxp.h
175
#define BF_PXP_OUT_CTRL_ALPHA_OUTPUT(v) \
drivers/media/platform/nxp/imx-pxp.h
176
(((v) << 23) & BM_PXP_OUT_CTRL_ALPHA_OUTPUT)
drivers/media/platform/nxp/imx-pxp.h
179
#define BF_PXP_OUT_CTRL_RSVD1(v) \
drivers/media/platform/nxp/imx-pxp.h
180
(((v) << 10) & BM_PXP_OUT_CTRL_RSVD1)
drivers/media/platform/nxp/imx-pxp.h
183
#define BF_PXP_OUT_CTRL_INTERLACED_OUTPUT(v) \
drivers/media/platform/nxp/imx-pxp.h
184
(((v) << 8) & BM_PXP_OUT_CTRL_INTERLACED_OUTPUT)
drivers/media/platform/nxp/imx-pxp.h
19
#define BF_PXP_CTRL_SFTRST(v) \
drivers/media/platform/nxp/imx-pxp.h
191
#define BF_PXP_OUT_CTRL_RSVD0(v) \
drivers/media/platform/nxp/imx-pxp.h
192
(((v) << 5) & BM_PXP_OUT_CTRL_RSVD0)
drivers/media/platform/nxp/imx-pxp.h
195
#define BF_PXP_OUT_CTRL_FORMAT(v) \
drivers/media/platform/nxp/imx-pxp.h
196
(((v) << 0) & BM_PXP_OUT_CTRL_FORMAT)
drivers/media/platform/nxp/imx-pxp.h
20
(((v) << 31) & BM_PXP_CTRL_SFTRST)
drivers/media/platform/nxp/imx-pxp.h
219
#define BF_PXP_OUT_BUF_ADDR(v) (v)
drivers/media/platform/nxp/imx-pxp.h
22
#define BF_PXP_CTRL_CLKGATE(v) \
drivers/media/platform/nxp/imx-pxp.h
225
#define BF_PXP_OUT_BUF2_ADDR(v) (v)
drivers/media/platform/nxp/imx-pxp.h
23
(((v) << 30) & BM_PXP_CTRL_CLKGATE)
drivers/media/platform/nxp/imx-pxp.h
231
#define BF_PXP_OUT_PITCH_RSVD(v) \
drivers/media/platform/nxp/imx-pxp.h
232
(((v) << 16) & BM_PXP_OUT_PITCH_RSVD)
drivers/media/platform/nxp/imx-pxp.h
235
#define BF_PXP_OUT_PITCH_PITCH(v) \
drivers/media/platform/nxp/imx-pxp.h
236
(((v) << 0) & BM_PXP_OUT_PITCH_PITCH)
drivers/media/platform/nxp/imx-pxp.h
242
#define BF_PXP_OUT_LRC_RSVD1(v) \
drivers/media/platform/nxp/imx-pxp.h
243
(((v) << 30) & BM_PXP_OUT_LRC_RSVD1)
drivers/media/platform/nxp/imx-pxp.h
246
#define BF_PXP_OUT_LRC_X(v) \
drivers/media/platform/nxp/imx-pxp.h
247
(((v) << 16) & BM_PXP_OUT_LRC_X)
drivers/media/platform/nxp/imx-pxp.h
25
#define BF_PXP_CTRL_RSVD4(v) \
drivers/media/platform/nxp/imx-pxp.h
250
#define BF_PXP_OUT_LRC_RSVD0(v) \
drivers/media/platform/nxp/imx-pxp.h
251
(((v) << 14) & BM_PXP_OUT_LRC_RSVD0)
drivers/media/platform/nxp/imx-pxp.h
254
#define BF_PXP_OUT_LRC_Y(v) \
drivers/media/platform/nxp/imx-pxp.h
255
(((v) << 0) & BM_PXP_OUT_LRC_Y)
drivers/media/platform/nxp/imx-pxp.h
26
(((v) << 29) & BM_PXP_CTRL_RSVD4)
drivers/media/platform/nxp/imx-pxp.h
261
#define BF_PXP_OUT_PS_ULC_RSVD1(v) \
drivers/media/platform/nxp/imx-pxp.h
262
(((v) << 30) & BM_PXP_OUT_PS_ULC_RSVD1)
drivers/media/platform/nxp/imx-pxp.h
265
#define BF_PXP_OUT_PS_ULC_X(v) \
drivers/media/platform/nxp/imx-pxp.h
266
(((v) << 16) & BM_PXP_OUT_PS_ULC_X)
drivers/media/platform/nxp/imx-pxp.h
269
#define BF_PXP_OUT_PS_ULC_RSVD0(v) \
drivers/media/platform/nxp/imx-pxp.h
270
(((v) << 14) & BM_PXP_OUT_PS_ULC_RSVD0)
drivers/media/platform/nxp/imx-pxp.h
273
#define BF_PXP_OUT_PS_ULC_Y(v) \
drivers/media/platform/nxp/imx-pxp.h
274
(((v) << 0) & BM_PXP_OUT_PS_ULC_Y)
drivers/media/platform/nxp/imx-pxp.h
28
#define BF_PXP_CTRL_EN_REPEAT(v) \
drivers/media/platform/nxp/imx-pxp.h
280
#define BF_PXP_OUT_PS_LRC_RSVD1(v) \
drivers/media/platform/nxp/imx-pxp.h
281
(((v) << 30) & BM_PXP_OUT_PS_LRC_RSVD1)
drivers/media/platform/nxp/imx-pxp.h
284
#define BF_PXP_OUT_PS_LRC_X(v) \
drivers/media/platform/nxp/imx-pxp.h
285
(((v) << 16) & BM_PXP_OUT_PS_LRC_X)
drivers/media/platform/nxp/imx-pxp.h
288
#define BF_PXP_OUT_PS_LRC_RSVD0(v) \
drivers/media/platform/nxp/imx-pxp.h
289
(((v) << 14) & BM_PXP_OUT_PS_LRC_RSVD0)
drivers/media/platform/nxp/imx-pxp.h
29
(((v) << 28) & BM_PXP_CTRL_EN_REPEAT)
drivers/media/platform/nxp/imx-pxp.h
292
#define BF_PXP_OUT_PS_LRC_Y(v) \
drivers/media/platform/nxp/imx-pxp.h
293
(((v) << 0) & BM_PXP_OUT_PS_LRC_Y)
drivers/media/platform/nxp/imx-pxp.h
299
#define BF_PXP_OUT_AS_ULC_RSVD1(v) \
drivers/media/platform/nxp/imx-pxp.h
300
(((v) << 30) & BM_PXP_OUT_AS_ULC_RSVD1)
drivers/media/platform/nxp/imx-pxp.h
303
#define BF_PXP_OUT_AS_ULC_X(v) \
drivers/media/platform/nxp/imx-pxp.h
304
(((v) << 16) & BM_PXP_OUT_AS_ULC_X)
drivers/media/platform/nxp/imx-pxp.h
307
#define BF_PXP_OUT_AS_ULC_RSVD0(v) \
drivers/media/platform/nxp/imx-pxp.h
308
(((v) << 14) & BM_PXP_OUT_AS_ULC_RSVD0)
drivers/media/platform/nxp/imx-pxp.h
31
#define BF_PXP_CTRL_ENABLE_ROTATE1(v) \
drivers/media/platform/nxp/imx-pxp.h
311
#define BF_PXP_OUT_AS_ULC_Y(v) \
drivers/media/platform/nxp/imx-pxp.h
312
(((v) << 0) & BM_PXP_OUT_AS_ULC_Y)
drivers/media/platform/nxp/imx-pxp.h
318
#define BF_PXP_OUT_AS_LRC_RSVD1(v) \
drivers/media/platform/nxp/imx-pxp.h
319
(((v) << 30) & BM_PXP_OUT_AS_LRC_RSVD1)
drivers/media/platform/nxp/imx-pxp.h
32
(((v) << 27) & BM_PXP_CTRL_ENABLE_ROTATE1)
drivers/media/platform/nxp/imx-pxp.h
322
#define BF_PXP_OUT_AS_LRC_X(v) \
drivers/media/platform/nxp/imx-pxp.h
323
(((v) << 16) & BM_PXP_OUT_AS_LRC_X)
drivers/media/platform/nxp/imx-pxp.h
326
#define BF_PXP_OUT_AS_LRC_RSVD0(v) \
drivers/media/platform/nxp/imx-pxp.h
327
(((v) << 14) & BM_PXP_OUT_AS_LRC_RSVD0)
drivers/media/platform/nxp/imx-pxp.h
330
#define BF_PXP_OUT_AS_LRC_Y(v) \
drivers/media/platform/nxp/imx-pxp.h
331
(((v) << 0) & BM_PXP_OUT_AS_LRC_Y)
drivers/media/platform/nxp/imx-pxp.h
34
#define BF_PXP_CTRL_ENABLE_ROTATE0(v) \
drivers/media/platform/nxp/imx-pxp.h
340
#define BF_PXP_PS_CTRL_RSVD1(v) \
drivers/media/platform/nxp/imx-pxp.h
341
(((v) << 12) & BM_PXP_PS_CTRL_RSVD1)
drivers/media/platform/nxp/imx-pxp.h
344
#define BF_PXP_PS_CTRL_DECX(v) \
drivers/media/platform/nxp/imx-pxp.h
345
(((v) << 10) & BM_PXP_PS_CTRL_DECX)
drivers/media/platform/nxp/imx-pxp.h
35
(((v) << 26) & BM_PXP_CTRL_ENABLE_ROTATE0)
drivers/media/platform/nxp/imx-pxp.h
352
#define BF_PXP_PS_CTRL_DECY(v) \
drivers/media/platform/nxp/imx-pxp.h
353
(((v) << 8) & BM_PXP_PS_CTRL_DECY)
drivers/media/platform/nxp/imx-pxp.h
359
#define BF_PXP_PS_CTRL_RSVD0(v) \
drivers/media/platform/nxp/imx-pxp.h
360
(((v) << 7) & BM_PXP_PS_CTRL_RSVD0)
drivers/media/platform/nxp/imx-pxp.h
362
#define BF_PXP_PS_CTRL_WB_SWAP(v) \
drivers/media/platform/nxp/imx-pxp.h
363
(((v) << 6) & BM_PXP_PS_CTRL_WB_SWAP)
drivers/media/platform/nxp/imx-pxp.h
366
#define BF_PXP_PS_CTRL_FORMAT(v) \
drivers/media/platform/nxp/imx-pxp.h
367
(((v) << 0) & BM_PXP_PS_CTRL_FORMAT)
drivers/media/platform/nxp/imx-pxp.h
37
#define BF_PXP_CTRL_ENABLE_LUT(v) \
drivers/media/platform/nxp/imx-pxp.h
38
(((v) << 25) & BM_PXP_CTRL_ENABLE_LUT)
drivers/media/platform/nxp/imx-pxp.h
388
#define BF_PXP_PS_BUF_ADDR(v) (v)
drivers/media/platform/nxp/imx-pxp.h
394
#define BF_PXP_PS_UBUF_ADDR(v) (v)
drivers/media/platform/nxp/imx-pxp.h
40
#define BF_PXP_CTRL_ENABLE_CSC2(v) \
drivers/media/platform/nxp/imx-pxp.h
400
#define BF_PXP_PS_VBUF_ADDR(v) (v)
drivers/media/platform/nxp/imx-pxp.h
406
#define BF_PXP_PS_PITCH_RSVD(v) \
drivers/media/platform/nxp/imx-pxp.h
407
(((v) << 16) & BM_PXP_PS_PITCH_RSVD)
drivers/media/platform/nxp/imx-pxp.h
41
(((v) << 24) & BM_PXP_CTRL_ENABLE_CSC2)
drivers/media/platform/nxp/imx-pxp.h
410
#define BF_PXP_PS_PITCH_PITCH(v) \
drivers/media/platform/nxp/imx-pxp.h
411
(((v) << 0) & BM_PXP_PS_PITCH_PITCH)
drivers/media/platform/nxp/imx-pxp.h
417
#define BF_PXP_PS_BACKGROUND_0_RSVD(v) \
drivers/media/platform/nxp/imx-pxp.h
418
(((v) << 24) & BM_PXP_PS_BACKGROUND_0_RSVD)
drivers/media/platform/nxp/imx-pxp.h
421
#define BF_PXP_PS_BACKGROUND_0_COLOR(v) \
drivers/media/platform/nxp/imx-pxp.h
422
(((v) << 0) & BM_PXP_PS_BACKGROUND_0_COLOR)
drivers/media/platform/nxp/imx-pxp.h
427
#define BF_PXP_PS_SCALE_RSVD2(v) \
drivers/media/platform/nxp/imx-pxp.h
428
(((v) << 31) & BM_PXP_PS_SCALE_RSVD2)
drivers/media/platform/nxp/imx-pxp.h
43
#define BF_PXP_CTRL_BLOCK_SIZE(v) \
drivers/media/platform/nxp/imx-pxp.h
431
#define BF_PXP_PS_SCALE_YSCALE(v) \
drivers/media/platform/nxp/imx-pxp.h
432
(((v) << 16) & BM_PXP_PS_SCALE_YSCALE)
drivers/media/platform/nxp/imx-pxp.h
434
#define BF_PXP_PS_SCALE_RSVD1(v) \
drivers/media/platform/nxp/imx-pxp.h
435
(((v) << 15) & BM_PXP_PS_SCALE_RSVD1)
drivers/media/platform/nxp/imx-pxp.h
438
#define BF_PXP_PS_SCALE_XSCALE(v) \
drivers/media/platform/nxp/imx-pxp.h
439
(((v) << 0) & BM_PXP_PS_SCALE_XSCALE)
drivers/media/platform/nxp/imx-pxp.h
44
(((v) << 23) & BM_PXP_CTRL_BLOCK_SIZE)
drivers/media/platform/nxp/imx-pxp.h
445
#define BF_PXP_PS_OFFSET_RSVD2(v) \
drivers/media/platform/nxp/imx-pxp.h
446
(((v) << 28) & BM_PXP_PS_OFFSET_RSVD2)
drivers/media/platform/nxp/imx-pxp.h
449
#define BF_PXP_PS_OFFSET_YOFFSET(v) \
drivers/media/platform/nxp/imx-pxp.h
450
(((v) << 16) & BM_PXP_PS_OFFSET_YOFFSET)
drivers/media/platform/nxp/imx-pxp.h
453
#define BF_PXP_PS_OFFSET_RSVD1(v) \
drivers/media/platform/nxp/imx-pxp.h
454
(((v) << 12) & BM_PXP_PS_OFFSET_RSVD1)
drivers/media/platform/nxp/imx-pxp.h
457
#define BF_PXP_PS_OFFSET_XOFFSET(v) \
drivers/media/platform/nxp/imx-pxp.h
458
(((v) << 0) & BM_PXP_PS_OFFSET_XOFFSET)
drivers/media/platform/nxp/imx-pxp.h
464
#define BF_PXP_PS_CLRKEYLOW_0_RSVD1(v) \
drivers/media/platform/nxp/imx-pxp.h
465
(((v) << 24) & BM_PXP_PS_CLRKEYLOW_0_RSVD1)
drivers/media/platform/nxp/imx-pxp.h
468
#define BF_PXP_PS_CLRKEYLOW_0_PIXEL(v) \
drivers/media/platform/nxp/imx-pxp.h
469
(((v) << 0) & BM_PXP_PS_CLRKEYLOW_0_PIXEL)
drivers/media/platform/nxp/imx-pxp.h
475
#define BF_PXP_PS_CLRKEYHIGH_0_RSVD1(v) \
drivers/media/platform/nxp/imx-pxp.h
476
(((v) << 24) & BM_PXP_PS_CLRKEYHIGH_0_RSVD1)
drivers/media/platform/nxp/imx-pxp.h
479
#define BF_PXP_PS_CLRKEYHIGH_0_PIXEL(v) \
drivers/media/platform/nxp/imx-pxp.h
48
#define BF_PXP_CTRL_RSVD1(v) \
drivers/media/platform/nxp/imx-pxp.h
480
(((v) << 0) & BM_PXP_PS_CLRKEYHIGH_0_PIXEL)
drivers/media/platform/nxp/imx-pxp.h
486
#define BF_PXP_AS_CTRL_RSVD1(v) \
drivers/media/platform/nxp/imx-pxp.h
487
(((v) << 22) & BM_PXP_AS_CTRL_RSVD1)
drivers/media/platform/nxp/imx-pxp.h
489
#define BF_PXP_AS_CTRL_ALPHA1_INVERT(v) \
drivers/media/platform/nxp/imx-pxp.h
49
(((v) << 22) & BM_PXP_CTRL_RSVD1)
drivers/media/platform/nxp/imx-pxp.h
490
(((v) << 21) & BM_PXP_AS_CTRL_ALPHA1_INVERT)
drivers/media/platform/nxp/imx-pxp.h
492
#define BF_PXP_AS_CTRL_ALPHA0_INVERT(v) \
drivers/media/platform/nxp/imx-pxp.h
493
(((v) << 20) & BM_PXP_AS_CTRL_ALPHA0_INVERT)
drivers/media/platform/nxp/imx-pxp.h
496
#define BF_PXP_AS_CTRL_ROP(v) \
drivers/media/platform/nxp/imx-pxp.h
497
(((v) << 16) & BM_PXP_AS_CTRL_ROP)
drivers/media/platform/nxp/imx-pxp.h
51
#define BF_PXP_CTRL_ENABLE_ALPHA_B(v) \
drivers/media/platform/nxp/imx-pxp.h
512
#define BF_PXP_AS_CTRL_ALPHA(v) \
drivers/media/platform/nxp/imx-pxp.h
513
(((v) << 8) & BM_PXP_AS_CTRL_ALPHA)
drivers/media/platform/nxp/imx-pxp.h
516
#define BF_PXP_AS_CTRL_FORMAT(v) \
drivers/media/platform/nxp/imx-pxp.h
517
(((v) << 4) & BM_PXP_AS_CTRL_FORMAT)
drivers/media/platform/nxp/imx-pxp.h
52
(((v) << 21) & BM_PXP_CTRL_ENABLE_ALPHA_B)
drivers/media/platform/nxp/imx-pxp.h
527
#define BF_PXP_AS_CTRL_ENABLE_COLORKEY(v) \
drivers/media/platform/nxp/imx-pxp.h
528
(((v) << 3) & BM_PXP_AS_CTRL_ENABLE_COLORKEY)
drivers/media/platform/nxp/imx-pxp.h
531
#define BF_PXP_AS_CTRL_ALPHA_CTRL(v) \
drivers/media/platform/nxp/imx-pxp.h
532
(((v) << 1) & BM_PXP_AS_CTRL_ALPHA_CTRL)
drivers/media/platform/nxp/imx-pxp.h
538
#define BF_PXP_AS_CTRL_RSVD0(v) \
drivers/media/platform/nxp/imx-pxp.h
539
(((v) << 0) & BM_PXP_AS_CTRL_RSVD0)
drivers/media/platform/nxp/imx-pxp.h
54
#define BF_PXP_CTRL_ENABLE_INPUT_FETCH_STORE(v) \
drivers/media/platform/nxp/imx-pxp.h
545
#define BF_PXP_AS_BUF_ADDR(v) (v)
drivers/media/platform/nxp/imx-pxp.h
55
(((v) << 20) & BM_PXP_CTRL_ENABLE_INPUT_FETCH_STORE)
drivers/media/platform/nxp/imx-pxp.h
551
#define BF_PXP_AS_PITCH_RSVD(v) \
drivers/media/platform/nxp/imx-pxp.h
552
(((v) << 16) & BM_PXP_AS_PITCH_RSVD)
drivers/media/platform/nxp/imx-pxp.h
555
#define BF_PXP_AS_PITCH_PITCH(v) \
drivers/media/platform/nxp/imx-pxp.h
556
(((v) << 0) & BM_PXP_AS_PITCH_PITCH)
drivers/media/platform/nxp/imx-pxp.h
562
#define BF_PXP_AS_CLRKEYLOW_0_RSVD1(v) \
drivers/media/platform/nxp/imx-pxp.h
563
(((v) << 24) & BM_PXP_AS_CLRKEYLOW_0_RSVD1)
drivers/media/platform/nxp/imx-pxp.h
566
#define BF_PXP_AS_CLRKEYLOW_0_PIXEL(v) \
drivers/media/platform/nxp/imx-pxp.h
567
(((v) << 0) & BM_PXP_AS_CLRKEYLOW_0_PIXEL)
drivers/media/platform/nxp/imx-pxp.h
57
#define BF_PXP_CTRL_ENABLE_WFE_B(v) \
drivers/media/platform/nxp/imx-pxp.h
573
#define BF_PXP_AS_CLRKEYHIGH_0_RSVD1(v) \
drivers/media/platform/nxp/imx-pxp.h
574
(((v) << 24) & BM_PXP_AS_CLRKEYHIGH_0_RSVD1)
drivers/media/platform/nxp/imx-pxp.h
577
#define BF_PXP_AS_CLRKEYHIGH_0_PIXEL(v) \
drivers/media/platform/nxp/imx-pxp.h
578
(((v) << 0) & BM_PXP_AS_CLRKEYHIGH_0_PIXEL)
drivers/media/platform/nxp/imx-pxp.h
58
(((v) << 19) & BM_PXP_CTRL_ENABLE_WFE_B)
drivers/media/platform/nxp/imx-pxp.h
583
#define BF_PXP_CSC1_COEF0_YCBCR_MODE(v) \
drivers/media/platform/nxp/imx-pxp.h
584
(((v) << 31) & BM_PXP_CSC1_COEF0_YCBCR_MODE)
drivers/media/platform/nxp/imx-pxp.h
586
#define BF_PXP_CSC1_COEF0_BYPASS(v) \
drivers/media/platform/nxp/imx-pxp.h
587
(((v) << 30) & BM_PXP_CSC1_COEF0_BYPASS)
drivers/media/platform/nxp/imx-pxp.h
589
#define BF_PXP_CSC1_COEF0_RSVD1(v) \
drivers/media/platform/nxp/imx-pxp.h
590
(((v) << 29) & BM_PXP_CSC1_COEF0_RSVD1)
drivers/media/platform/nxp/imx-pxp.h
593
#define BF_PXP_CSC1_COEF0_C0(v) \
drivers/media/platform/nxp/imx-pxp.h
594
(((v) << 18) & BM_PXP_CSC1_COEF0_C0)
drivers/media/platform/nxp/imx-pxp.h
60
#define BF_PXP_CTRL_ENABLE_WFE_A(v) \
drivers/media/platform/nxp/imx-pxp.h
602
#define BF_PXP_CSC1_COEF0_UV_OFFSET(v) \
drivers/media/platform/nxp/imx-pxp.h
603
(((v) * (1 << 9)) & BM_PXP_CSC1_COEF0_UV_OFFSET)
drivers/media/platform/nxp/imx-pxp.h
606
#define BF_PXP_CSC1_COEF0_Y_OFFSET(v) \
drivers/media/platform/nxp/imx-pxp.h
607
((v) & BM_PXP_CSC1_COEF0_Y_OFFSET)
drivers/media/platform/nxp/imx-pxp.h
61
(((v) << 18) & BM_PXP_CTRL_ENABLE_WFE_A)
drivers/media/platform/nxp/imx-pxp.h
613
#define BF_PXP_CSC1_COEF1_RSVD1(v) \
drivers/media/platform/nxp/imx-pxp.h
614
(((v) << 27) & BM_PXP_CSC1_COEF1_RSVD1)
drivers/media/platform/nxp/imx-pxp.h
617
#define BF_PXP_CSC1_COEF1_C1(v) \
drivers/media/platform/nxp/imx-pxp.h
618
(((v) << 16) & BM_PXP_CSC1_COEF1_C1)
drivers/media/platform/nxp/imx-pxp.h
621
#define BF_PXP_CSC1_COEF1_RSVD0(v) \
drivers/media/platform/nxp/imx-pxp.h
622
(((v) << 11) & BM_PXP_CSC1_COEF1_RSVD0)
drivers/media/platform/nxp/imx-pxp.h
625
#define BF_PXP_CSC1_COEF1_C4(v) \
drivers/media/platform/nxp/imx-pxp.h
626
(((v) << 0) & BM_PXP_CSC1_COEF1_C4)
drivers/media/platform/nxp/imx-pxp.h
63
#define BF_PXP_CTRL_ENABLE_DITHER(v) \
drivers/media/platform/nxp/imx-pxp.h
632
#define BF_PXP_CSC1_COEF2_RSVD1(v) \
drivers/media/platform/nxp/imx-pxp.h
633
(((v) << 27) & BM_PXP_CSC1_COEF2_RSVD1)
drivers/media/platform/nxp/imx-pxp.h
636
#define BF_PXP_CSC1_COEF2_C2(v) \
drivers/media/platform/nxp/imx-pxp.h
637
(((v) << 16) & BM_PXP_CSC1_COEF2_C2)
drivers/media/platform/nxp/imx-pxp.h
64
(((v) << 17) & BM_PXP_CTRL_ENABLE_DITHER)
drivers/media/platform/nxp/imx-pxp.h
640
#define BF_PXP_CSC1_COEF2_RSVD0(v) \
drivers/media/platform/nxp/imx-pxp.h
641
(((v) << 11) & BM_PXP_CSC1_COEF2_RSVD0)
drivers/media/platform/nxp/imx-pxp.h
644
#define BF_PXP_CSC1_COEF2_C3(v) \
drivers/media/platform/nxp/imx-pxp.h
645
(((v) << 0) & BM_PXP_CSC1_COEF2_C3)
drivers/media/platform/nxp/imx-pxp.h
651
#define BF_PXP_CSC2_CTRL_RSVD(v) \
drivers/media/platform/nxp/imx-pxp.h
652
(((v) << 3) & BM_PXP_CSC2_CTRL_RSVD)
drivers/media/platform/nxp/imx-pxp.h
655
#define BF_PXP_CSC2_CTRL_CSC_MODE(v) \
drivers/media/platform/nxp/imx-pxp.h
656
(((v) << 1) & BM_PXP_CSC2_CTRL_CSC_MODE)
drivers/media/platform/nxp/imx-pxp.h
66
#define BF_PXP_CTRL_ENABLE_PS_AS_OUT(v) \
drivers/media/platform/nxp/imx-pxp.h
662
#define BF_PXP_CSC2_CTRL_BYPASS(v) \
drivers/media/platform/nxp/imx-pxp.h
663
(((v) << 0) & BM_PXP_CSC2_CTRL_BYPASS)
drivers/media/platform/nxp/imx-pxp.h
669
#define BF_PXP_CSC2_COEF0_RSVD1(v) \
drivers/media/platform/nxp/imx-pxp.h
67
(((v) << 16) & BM_PXP_CTRL_ENABLE_PS_AS_OUT)
drivers/media/platform/nxp/imx-pxp.h
670
(((v) << 27) & BM_PXP_CSC2_COEF0_RSVD1)
drivers/media/platform/nxp/imx-pxp.h
673
#define BF_PXP_CSC2_COEF0_A2(v) \
drivers/media/platform/nxp/imx-pxp.h
674
(((v) << 16) & BM_PXP_CSC2_COEF0_A2)
drivers/media/platform/nxp/imx-pxp.h
677
#define BF_PXP_CSC2_COEF0_RSVD0(v) \
drivers/media/platform/nxp/imx-pxp.h
678
(((v) << 11) & BM_PXP_CSC2_COEF0_RSVD0)
drivers/media/platform/nxp/imx-pxp.h
681
#define BF_PXP_CSC2_COEF0_A1(v) \
drivers/media/platform/nxp/imx-pxp.h
682
(((v) << 0) & BM_PXP_CSC2_COEF0_A1)
drivers/media/platform/nxp/imx-pxp.h
688
#define BF_PXP_CSC2_COEF1_RSVD1(v) \
drivers/media/platform/nxp/imx-pxp.h
689
(((v) << 27) & BM_PXP_CSC2_COEF1_RSVD1)
drivers/media/platform/nxp/imx-pxp.h
69
#define BF_PXP_CTRL_VFLIP1(v) \
drivers/media/platform/nxp/imx-pxp.h
692
#define BF_PXP_CSC2_COEF1_B1(v) \
drivers/media/platform/nxp/imx-pxp.h
693
(((v) << 16) & BM_PXP_CSC2_COEF1_B1)
drivers/media/platform/nxp/imx-pxp.h
696
#define BF_PXP_CSC2_COEF1_RSVD0(v) \
drivers/media/platform/nxp/imx-pxp.h
697
(((v) << 11) & BM_PXP_CSC2_COEF1_RSVD0)
drivers/media/platform/nxp/imx-pxp.h
70
(((v) << 15) & BM_PXP_CTRL_VFLIP1)
drivers/media/platform/nxp/imx-pxp.h
700
#define BF_PXP_CSC2_COEF1_A3(v) \
drivers/media/platform/nxp/imx-pxp.h
701
(((v) << 0) & BM_PXP_CSC2_COEF1_A3)
drivers/media/platform/nxp/imx-pxp.h
707
#define BF_PXP_CSC2_COEF2_RSVD1(v) \
drivers/media/platform/nxp/imx-pxp.h
708
(((v) << 27) & BM_PXP_CSC2_COEF2_RSVD1)
drivers/media/platform/nxp/imx-pxp.h
711
#define BF_PXP_CSC2_COEF2_B3(v) \
drivers/media/platform/nxp/imx-pxp.h
712
(((v) << 16) & BM_PXP_CSC2_COEF2_B3)
drivers/media/platform/nxp/imx-pxp.h
715
#define BF_PXP_CSC2_COEF2_RSVD0(v) \
drivers/media/platform/nxp/imx-pxp.h
716
(((v) << 11) & BM_PXP_CSC2_COEF2_RSVD0)
drivers/media/platform/nxp/imx-pxp.h
719
#define BF_PXP_CSC2_COEF2_B2(v) \
drivers/media/platform/nxp/imx-pxp.h
72
#define BF_PXP_CTRL_HFLIP1(v) \
drivers/media/platform/nxp/imx-pxp.h
720
(((v) << 0) & BM_PXP_CSC2_COEF2_B2)
drivers/media/platform/nxp/imx-pxp.h
726
#define BF_PXP_CSC2_COEF3_RSVD1(v) \
drivers/media/platform/nxp/imx-pxp.h
727
(((v) << 27) & BM_PXP_CSC2_COEF3_RSVD1)
drivers/media/platform/nxp/imx-pxp.h
73
(((v) << 14) & BM_PXP_CTRL_HFLIP1)
drivers/media/platform/nxp/imx-pxp.h
730
#define BF_PXP_CSC2_COEF3_C2(v) \
drivers/media/platform/nxp/imx-pxp.h
731
(((v) << 16) & BM_PXP_CSC2_COEF3_C2)
drivers/media/platform/nxp/imx-pxp.h
734
#define BF_PXP_CSC2_COEF3_RSVD0(v) \
drivers/media/platform/nxp/imx-pxp.h
735
(((v) << 11) & BM_PXP_CSC2_COEF3_RSVD0)
drivers/media/platform/nxp/imx-pxp.h
738
#define BF_PXP_CSC2_COEF3_C1(v) \
drivers/media/platform/nxp/imx-pxp.h
739
(((v) << 0) & BM_PXP_CSC2_COEF3_C1)
drivers/media/platform/nxp/imx-pxp.h
745
#define BF_PXP_CSC2_COEF4_RSVD1(v) \
drivers/media/platform/nxp/imx-pxp.h
746
(((v) << 25) & BM_PXP_CSC2_COEF4_RSVD1)
drivers/media/platform/nxp/imx-pxp.h
749
#define BF_PXP_CSC2_COEF4_D1(v) \
drivers/media/platform/nxp/imx-pxp.h
750
(((v) << 16) & BM_PXP_CSC2_COEF4_D1)
drivers/media/platform/nxp/imx-pxp.h
753
#define BF_PXP_CSC2_COEF4_RSVD0(v) \
drivers/media/platform/nxp/imx-pxp.h
754
(((v) << 11) & BM_PXP_CSC2_COEF4_RSVD0)
drivers/media/platform/nxp/imx-pxp.h
757
#define BF_PXP_CSC2_COEF4_C3(v) \
drivers/media/platform/nxp/imx-pxp.h
758
(((v) << 0) & BM_PXP_CSC2_COEF4_C3)
drivers/media/platform/nxp/imx-pxp.h
76
#define BF_PXP_CTRL_ROTATE1(v) \
drivers/media/platform/nxp/imx-pxp.h
764
#define BF_PXP_CSC2_COEF5_RSVD1(v) \
drivers/media/platform/nxp/imx-pxp.h
765
(((v) << 25) & BM_PXP_CSC2_COEF5_RSVD1)
drivers/media/platform/nxp/imx-pxp.h
768
#define BF_PXP_CSC2_COEF5_D3(v) \
drivers/media/platform/nxp/imx-pxp.h
769
(((v) << 16) & BM_PXP_CSC2_COEF5_D3)
drivers/media/platform/nxp/imx-pxp.h
77
(((v) << 12) & BM_PXP_CTRL_ROTATE1)
drivers/media/platform/nxp/imx-pxp.h
772
#define BF_PXP_CSC2_COEF5_RSVD0(v) \
drivers/media/platform/nxp/imx-pxp.h
773
(((v) << 9) & BM_PXP_CSC2_COEF5_RSVD0)
drivers/media/platform/nxp/imx-pxp.h
776
#define BF_PXP_CSC2_COEF5_D2(v) \
drivers/media/platform/nxp/imx-pxp.h
777
(((v) << 0) & BM_PXP_CSC2_COEF5_D2)
drivers/media/platform/nxp/imx-pxp.h
782
#define BF_PXP_LUT_CTRL_BYPASS(v) \
drivers/media/platform/nxp/imx-pxp.h
783
(((v) << 31) & BM_PXP_LUT_CTRL_BYPASS)
drivers/media/platform/nxp/imx-pxp.h
786
#define BF_PXP_LUT_CTRL_RSVD3(v) \
drivers/media/platform/nxp/imx-pxp.h
787
(((v) << 26) & BM_PXP_LUT_CTRL_RSVD3)
drivers/media/platform/nxp/imx-pxp.h
790
#define BF_PXP_LUT_CTRL_LOOKUP_MODE(v) \
drivers/media/platform/nxp/imx-pxp.h
791
(((v) << 24) & BM_PXP_LUT_CTRL_LOOKUP_MODE)
drivers/media/platform/nxp/imx-pxp.h
798
#define BF_PXP_LUT_CTRL_RSVD2(v) \
drivers/media/platform/nxp/imx-pxp.h
799
(((v) << 18) & BM_PXP_LUT_CTRL_RSVD2)
drivers/media/platform/nxp/imx-pxp.h
802
#define BF_PXP_LUT_CTRL_OUT_MODE(v) \
drivers/media/platform/nxp/imx-pxp.h
803
(((v) << 16) & BM_PXP_LUT_CTRL_OUT_MODE)
drivers/media/platform/nxp/imx-pxp.h
810
#define BF_PXP_LUT_CTRL_RSVD1(v) \
drivers/media/platform/nxp/imx-pxp.h
811
(((v) << 11) & BM_PXP_LUT_CTRL_RSVD1)
drivers/media/platform/nxp/imx-pxp.h
813
#define BF_PXP_LUT_CTRL_SEL_8KB(v) \
drivers/media/platform/nxp/imx-pxp.h
814
(((v) << 10) & BM_PXP_LUT_CTRL_SEL_8KB)
drivers/media/platform/nxp/imx-pxp.h
816
#define BF_PXP_LUT_CTRL_LRU_UPD(v) \
drivers/media/platform/nxp/imx-pxp.h
817
(((v) << 9) & BM_PXP_LUT_CTRL_LRU_UPD)
drivers/media/platform/nxp/imx-pxp.h
819
#define BF_PXP_LUT_CTRL_INVALID(v) \
drivers/media/platform/nxp/imx-pxp.h
820
(((v) << 8) & BM_PXP_LUT_CTRL_INVALID)
drivers/media/platform/nxp/imx-pxp.h
823
#define BF_PXP_LUT_CTRL_RSVD0(v) \
drivers/media/platform/nxp/imx-pxp.h
824
(((v) << 1) & BM_PXP_LUT_CTRL_RSVD0)
drivers/media/platform/nxp/imx-pxp.h
826
#define BF_PXP_LUT_CTRL_DMA_START(v) \
drivers/media/platform/nxp/imx-pxp.h
827
(((v) << 0) & BM_PXP_LUT_CTRL_DMA_START)
drivers/media/platform/nxp/imx-pxp.h
83
#define BF_PXP_CTRL_VFLIP0(v) \
drivers/media/platform/nxp/imx-pxp.h
832
#define BF_PXP_LUT_ADDR_RSVD2(v) \
drivers/media/platform/nxp/imx-pxp.h
833
(((v) << 31) & BM_PXP_LUT_ADDR_RSVD2)
drivers/media/platform/nxp/imx-pxp.h
836
#define BF_PXP_LUT_ADDR_NUM_BYTES(v) \
drivers/media/platform/nxp/imx-pxp.h
837
(((v) << 16) & BM_PXP_LUT_ADDR_NUM_BYTES)
drivers/media/platform/nxp/imx-pxp.h
84
(((v) << 11) & BM_PXP_CTRL_VFLIP0)
drivers/media/platform/nxp/imx-pxp.h
840
#define BF_PXP_LUT_ADDR_RSVD1(v) \
drivers/media/platform/nxp/imx-pxp.h
841
(((v) << 14) & BM_PXP_LUT_ADDR_RSVD1)
drivers/media/platform/nxp/imx-pxp.h
844
#define BF_PXP_LUT_ADDR_ADDR(v) \
drivers/media/platform/nxp/imx-pxp.h
845
(((v) << 0) & BM_PXP_LUT_ADDR_ADDR)
drivers/media/platform/nxp/imx-pxp.h
851
#define BF_PXP_LUT_DATA_DATA(v) (v)
drivers/media/platform/nxp/imx-pxp.h
857
#define BF_PXP_LUT_EXTMEM_ADDR(v) (v)
drivers/media/platform/nxp/imx-pxp.h
86
#define BF_PXP_CTRL_HFLIP0(v) \
drivers/media/platform/nxp/imx-pxp.h
863
#define BF_PXP_CFA_DATA(v) (v)
drivers/media/platform/nxp/imx-pxp.h
869
#define BF_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA(v) \
drivers/media/platform/nxp/imx-pxp.h
87
(((v) << 10) & BM_PXP_CTRL_HFLIP0)
drivers/media/platform/nxp/imx-pxp.h
870
(((v) << 24) & BM_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA)
drivers/media/platform/nxp/imx-pxp.h
873
#define BF_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA(v) \
drivers/media/platform/nxp/imx-pxp.h
874
(((v) << 16) & BM_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA)
drivers/media/platform/nxp/imx-pxp.h
877
#define BF_PXP_ALPHA_A_CTRL_RSVD0(v) \
drivers/media/platform/nxp/imx-pxp.h
878
(((v) << 14) & BM_PXP_ALPHA_A_CTRL_RSVD0)
drivers/media/platform/nxp/imx-pxp.h
880
#define BF_PXP_ALPHA_A_CTRL_S1_COLOR_MODE(v) \
drivers/media/platform/nxp/imx-pxp.h
881
(((v) << 13) & BM_PXP_ALPHA_A_CTRL_S1_COLOR_MODE)
drivers/media/platform/nxp/imx-pxp.h
885
#define BF_PXP_ALPHA_A_CTRL_S1_ALPHA_MODE(v) \
drivers/media/platform/nxp/imx-pxp.h
886
(((v) << 12) & BM_PXP_ALPHA_A_CTRL_S1_ALPHA_MODE)
drivers/media/platform/nxp/imx-pxp.h
891
#define BF_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE(v) \
drivers/media/platform/nxp/imx-pxp.h
892
(((v) << 10) & BM_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE)
drivers/media/platform/nxp/imx-pxp.h
899
#define BF_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE(v) \
drivers/media/platform/nxp/imx-pxp.h
90
#define BF_PXP_CTRL_ROTATE0(v) \
drivers/media/platform/nxp/imx-pxp.h
900
(((v) << 8) & BM_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE)
drivers/media/platform/nxp/imx-pxp.h
906
#define BF_PXP_ALPHA_A_CTRL_RSVD1(v) \
drivers/media/platform/nxp/imx-pxp.h
907
(((v) << 7) & BM_PXP_ALPHA_A_CTRL_RSVD1)
drivers/media/platform/nxp/imx-pxp.h
909
#define BF_PXP_ALPHA_A_CTRL_S0_COLOR_MODE(v) \
drivers/media/platform/nxp/imx-pxp.h
91
(((v) << 8) & BM_PXP_CTRL_ROTATE0)
drivers/media/platform/nxp/imx-pxp.h
910
(((v) << 6) & BM_PXP_ALPHA_A_CTRL_S0_COLOR_MODE)
drivers/media/platform/nxp/imx-pxp.h
914
#define BF_PXP_ALPHA_A_CTRL_S0_ALPHA_MODE(v) \
drivers/media/platform/nxp/imx-pxp.h
915
(((v) << 5) & BM_PXP_ALPHA_A_CTRL_S0_ALPHA_MODE)
drivers/media/platform/nxp/imx-pxp.h
920
#define BF_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE(v) \
drivers/media/platform/nxp/imx-pxp.h
921
(((v) << 3) & BM_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE)
drivers/media/platform/nxp/imx-pxp.h
928
#define BF_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE(v) \
drivers/media/platform/nxp/imx-pxp.h
929
(((v) << 1) & BM_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE)
drivers/media/platform/nxp/imx-pxp.h
935
#define BF_PXP_ALPHA_A_CTRL_POTER_DUFF_ENABLE(v) \
drivers/media/platform/nxp/imx-pxp.h
936
(((v) << 0) & BM_PXP_ALPHA_A_CTRL_POTER_DUFF_ENABLE)
drivers/media/platform/nxp/imx-pxp.h
944
#define BF_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA(v) \
drivers/media/platform/nxp/imx-pxp.h
945
(((v) << 24) & BM_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA)
drivers/media/platform/nxp/imx-pxp.h
948
#define BF_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA(v) \
drivers/media/platform/nxp/imx-pxp.h
949
(((v) << 16) & BM_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA)
drivers/media/platform/nxp/imx-pxp.h
952
#define BF_PXP_ALPHA_B_CTRL_RSVD0(v) \
drivers/media/platform/nxp/imx-pxp.h
953
(((v) << 14) & BM_PXP_ALPHA_B_CTRL_RSVD0)
drivers/media/platform/nxp/imx-pxp.h
955
#define BF_PXP_ALPHA_B_CTRL_S1_COLOR_MODE(v) \
drivers/media/platform/nxp/imx-pxp.h
956
(((v) << 13) & BM_PXP_ALPHA_B_CTRL_S1_COLOR_MODE)
drivers/media/platform/nxp/imx-pxp.h
960
#define BF_PXP_ALPHA_B_CTRL_S1_ALPHA_MODE(v) \
drivers/media/platform/nxp/imx-pxp.h
961
(((v) << 12) & BM_PXP_ALPHA_B_CTRL_S1_ALPHA_MODE)
drivers/media/platform/nxp/imx-pxp.h
966
#define BF_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE(v) \
drivers/media/platform/nxp/imx-pxp.h
967
(((v) << 10) & BM_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE)
drivers/media/platform/nxp/imx-pxp.h
974
#define BF_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE(v) \
drivers/media/platform/nxp/imx-pxp.h
975
(((v) << 8) & BM_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE)
drivers/media/platform/nxp/imx-pxp.h
98
#define BF_PXP_CTRL_RSVD0(v) \
drivers/media/platform/nxp/imx-pxp.h
981
#define BF_PXP_ALPHA_B_CTRL_RSVD1(v) \
drivers/media/platform/nxp/imx-pxp.h
982
(((v) << 7) & BM_PXP_ALPHA_B_CTRL_RSVD1)
drivers/media/platform/nxp/imx-pxp.h
984
#define BF_PXP_ALPHA_B_CTRL_S0_COLOR_MODE(v) \
drivers/media/platform/nxp/imx-pxp.h
985
(((v) << 6) & BM_PXP_ALPHA_B_CTRL_S0_COLOR_MODE)
drivers/media/platform/nxp/imx-pxp.h
989
#define BF_PXP_ALPHA_B_CTRL_S0_ALPHA_MODE(v) \
drivers/media/platform/nxp/imx-pxp.h
99
(((v) << 6) & BM_PXP_CTRL_RSVD0)
drivers/media/platform/nxp/imx-pxp.h
990
(((v) << 5) & BM_PXP_ALPHA_B_CTRL_S0_ALPHA_MODE)
drivers/media/platform/nxp/imx-pxp.h
995
#define BF_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE(v) \
drivers/media/platform/nxp/imx-pxp.h
996
(((v) << 3) & BM_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE)
drivers/media/platform/raspberrypi/rp1-cfe/csi2.c
239
u32 v;
drivers/media/platform/raspberrypi/rp1-cfe/csi2.c
244
v = csi2_reg_read(csi2, discard_regs[i]);
drivers/media/platform/raspberrypi/rp1-cfe/csi2.c
247
amount = (v & CSI2_DISCARDS_AMOUNT_MASK) >>
drivers/media/platform/raspberrypi/rp1-cfe/csi2.c
249
dt = (v & CSI2_DISCARDS_DT_MASK) >> CSI2_DISCARDS_DT_SHIFT;
drivers/media/platform/raspberrypi/rp1-cfe/csi2.c
250
vc = (v & CSI2_DISCARDS_VC_MASK) >> CSI2_DISCARDS_VC_SHIFT;
drivers/media/platform/samsung/exynos4-is/fimc-core.c
869
struct fimc_variant *v;
drivers/media/platform/samsung/exynos4-is/fimc-core.c
877
v = devm_kzalloc(dev, sizeof(*v) + sizeof(*lim), GFP_KERNEL);
drivers/media/platform/samsung/exynos4-is/fimc-core.c
878
if (!v)
drivers/media/platform/samsung/exynos4-is/fimc-core.c
890
lim = (struct fimc_pix_limit *)&v[1];
drivers/media/platform/samsung/exynos4-is/fimc-core.c
896
v->pix_limit = lim;
drivers/media/platform/samsung/exynos4-is/fimc-core.c
900
v->min_inp_pixsize = ret ? FIMC_DEF_MIN_SIZE : args[0];
drivers/media/platform/samsung/exynos4-is/fimc-core.c
901
v->min_out_pixsize = ret ? FIMC_DEF_MIN_SIZE : args[1];
drivers/media/platform/samsung/exynos4-is/fimc-core.c
904
v->min_vsize_align = ret ? FIMC_DEF_HEIGHT_ALIGN : args[0];
drivers/media/platform/samsung/exynos4-is/fimc-core.c
905
v->hor_offs_align = ret ? FIMC_DEF_HOR_OFFS_ALIGN : args[1];
drivers/media/platform/samsung/exynos4-is/fimc-core.c
908
v->has_inp_rot = ret ? 1 : args[1] & 0x01;
drivers/media/platform/samsung/exynos4-is/fimc-core.c
909
v->has_out_rot = ret ? 1 : args[1] & 0x10;
drivers/media/platform/samsung/exynos4-is/fimc-core.c
910
v->has_mainscaler_ext = of_property_read_bool(node,
drivers/media/platform/samsung/exynos4-is/fimc-core.c
913
v->has_isp_wb = of_property_read_bool(node, "samsung,isp-wb");
drivers/media/platform/samsung/exynos4-is/fimc-core.c
914
v->has_cam_if = of_property_read_bool(node, "samsung,cam-if");
drivers/media/platform/samsung/exynos4-is/fimc-core.c
918
fimc->variant = v;
drivers/media/platform/samsung/exynos4-is/fimc-is.h
329
static inline void mcuctl_write(u32 v, struct fimc_is *is, unsigned int offset)
drivers/media/platform/samsung/exynos4-is/fimc-is.h
331
writel(v, is->regs + offset);
drivers/media/platform/samsung/exynos4-is/fimc-is.h
339
static inline void pmuisp_write(u32 v, struct fimc_is *is, unsigned int offset)
drivers/media/platform/samsung/exynos4-is/fimc-is.h
341
writel(v, is->pmu_regs + offset);
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
36
#define writel(v, r) \
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
38
pr_err("MFCWRITE(%p): %08x\n", r, (unsigned int)v); \
drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c
39
__raw_writel(v, r); \
drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h
160
#define SUN6I_CSI_CH_FLD1_VSIZE_VER_LEN(v) (((v) << 16) & GENMASK(28, 16))
drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h
161
#define SUN6I_CSI_CH_FLD1_VSIZE_VER_START(v) ((v) & GENMASK(12, 0))
drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h
164
#define SUN6I_CSI_CH_HSIZE_LEN(v) (((v) << 16) & GENMASK(28, 16))
drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h
165
#define SUN6I_CSI_CH_HSIZE_START(v) ((v) & GENMASK(12, 0))
drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h
168
#define SUN6I_CSI_CH_VSIZE_LEN(v) (((v) << 16) & GENMASK(28, 16))
drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h
169
#define SUN6I_CSI_CH_VSIZE_START(v) ((v) & GENMASK(12, 0))
drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h
172
#define SUN6I_CSI_CH_BUF_LEN_CHROMA_LINE(v) (((v) << 16) & GENMASK(29, 16))
drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h
173
#define SUN6I_CSI_CH_BUF_LEN_LUMA_LINE(v) ((v) & GENMASK(13, 0))
drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h
176
#define SUN6I_CSI_CH_FLIP_SIZE_VER_LEN(v) (((v) << 16) & GENMASK(28, 16))
drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h
177
#define SUN6I_CSI_CH_FLIP_SIZE_VALID_LEN(v) ((v) & GENMASK(12, 0))
drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h
18
#define SUN6I_CSI_EN_PTN_CYCLE(v) (((v) << 16) & GENMASK(23, 16))
drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h
29
#define SUN6I_CSI_IF_CFG_FIELD_DT_PCLK_SHIFT(v) (((v) << 24) & GENMASK(27, 24))
drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h
57
#define SUN6I_CSI_CAP_MASK(v) (((v) << 2) & GENMASK(5, 2))
drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h
70
#define SUN6I_CSI_CH_CFG_PAD_VAL(v) (((v) << 24) & GENMASK(31, 24))
drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h
71
#define SUN6I_CSI_CH_CFG_INPUT_FMT(v) (((v) << 20) & GENMASK(23, 20))
drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h
72
#define SUN6I_CSI_CH_CFG_OUTPUT_FMT(v) (((v) << 16) & GENMASK(19, 16))
drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_reg.h
78
#define SUN6I_CSI_CH_CFG_INPUT_YUV_SEQ(v) (((v) << 8) & GENMASK(9, 8))
drivers/media/platform/sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2_reg.h
17
#define SUN6I_MIPI_CSI2_CFG_CHANNEL_MODE(v) ((((v) - 1) << 8) & \
drivers/media/platform/sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2_reg.h
19
#define SUN6I_MIPI_CSI2_CFG_LANE_COUNT(v) (((v) - 1) & GENMASK(1, 0))
drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/sun8i_a83t_dphy.h
34
#define SUN8I_A83T_DPHY_ANA0_RINT(v) (((v) << 28) & GENMASK(29, 28))
drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/sun8i_a83t_dphy.h
35
#define SUN8I_A83T_DPHY_ANA0_SNK(v) (((v) << 20) & GENMASK(22, 20))
drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/sun8i_a83t_mipi_csi2_reg.h
134
#define SUN8I_A83T_MIPI_CSI2_CFG_SYNC_DLY_CYCLE(v) (((v) << 18) & \
drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/sun8i_a83t_mipi_csi2_reg.h
136
#define SUN8I_A83T_MIPI_CSI2_CFG_N_CHANNEL(v) ((((v) - 1) << 16) & \
drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/sun8i_a83t_mipi_csi2_reg.h
138
#define SUN8I_A83T_MIPI_CSI2_CFG_N_LANE(v) ((((v) - 1) << 4) & \
drivers/media/platform/sunxi/sun8i-di/sun8i-di.h
100
#define DEINTERLACE_TEMP_DIFF_AMBIGUITY_TH(v) (((v) & 0x7f) << 8)
drivers/media/platform/sunxi/sun8i-di/sun8i-di.h
102
#define DEINTERLACE_TEMP_DIFF_DIRECT_DITHER_TH(v) (((v) & 0x7ff) << 16)
drivers/media/platform/sunxi/sun8i-di/sun8i-di.h
106
#define DEINTERLACE_LUMA_TH_MIN_LUMA(v) ((v) & 0xff)
drivers/media/platform/sunxi/sun8i-di/sun8i-di.h
108
#define DEINTERLACE_LUMA_TH_MAX_LUMA(v) (((v) & 0xff) << 8)
drivers/media/platform/sunxi/sun8i-di/sun8i-di.h
110
#define DEINTERLACE_LUMA_TH_AVG_LUMA_SHIFT(v) (((v) & 0xff) << 16)
drivers/media/platform/sunxi/sun8i-di/sun8i-di.h
112
#define DEINTERLACE_LUMA_TH_PIXEL_STATIC(v) (((v) & 3) << 24)
drivers/media/platform/sunxi/sun8i-di/sun8i-di.h
116
#define DEINTERLACE_SPAT_COMP_TH2(v) ((v) & 0xff)
drivers/media/platform/sunxi/sun8i-di/sun8i-di.h
118
#define DEINTERLACE_SPAT_COMP_TH3(v) (((v) & 0xff) << 16)
drivers/media/platform/sunxi/sun8i-di/sun8i-di.h
122
#define DEINTERLACE_CHROMA_DIFF_TH(v) ((v) & 0xff)
drivers/media/platform/sunxi/sun8i-di/sun8i-di.h
124
#define DEINTERLACE_CHROMA_DIFF_LUMA(v) (((v) & 0x3f) << 16)
drivers/media/platform/sunxi/sun8i-di/sun8i-di.h
126
#define DEINTERLACE_CHROMA_DIFF_CHROMA(v) (((v) & 0x3f) << 24)
drivers/media/platform/sunxi/sun8i-di/sun8i-di.h
43
#define DEINTERLACE_FIELD_CTRL_FIELD_CNT(v) ((v) & 0xff)
drivers/media/platform/sunxi/sun8i-di/sun8i-di.h
55
#define DEINTERLACE_IN_FMT_PS(v) ((v) & 3)
drivers/media/platform/sunxi/sun8i-di/sun8i-di.h
56
#define DEINTERLACE_IN_FMT_FMT(v) (((v) & 7) << 4)
drivers/media/platform/sunxi/sun8i-di/sun8i-di.h
57
#define DEINTERLACE_IN_FMT_MOD(v) (((v) & 7) << 8)
drivers/media/platform/sunxi/sun8i-di/sun8i-di.h
64
#define DEINTERLACE_OUT_FMT_FMT(v) ((v) & 0xf)
drivers/media/platform/sunxi/sun8i-di/sun8i-di.h
65
#define DEINTERLACE_OUT_FMT_PS(v) (((v) & 3) << 5)
drivers/media/platform/sunxi/sun8i-di/sun8i-di.h
90
#define DEINTERLACE_DIAG_INTP_TH0(v) ((v) & 0x7f)
drivers/media/platform/sunxi/sun8i-di/sun8i-di.h
92
#define DEINTERLACE_DIAG_INTP_TH1(v) (((v) & 0x7f) << 8)
drivers/media/platform/sunxi/sun8i-di/sun8i-di.h
94
#define DEINTERLACE_DIAG_INTP_TH3(v) (((v) & 0xff) << 24)
drivers/media/platform/sunxi/sun8i-di/sun8i-di.h
98
#define DEINTERLACE_TEMP_DIFF_SAD_CENTRAL_TH(v) ((v) & 0x7f)
drivers/media/platform/synopsys/hdmirx/snps_hdmirx.h
16
#define HIWORD_UPDATE(v, h, l) FIELD_PREP_WM16(GENMASK((h), (l)), (v))
drivers/media/platform/ti/omap3isp/isp.h
315
u32 v = isp_reg_readl(isp, mmio_range, reg);
drivers/media/platform/ti/omap3isp/isp.h
317
isp_reg_writel(isp, v & ~clr_bits, mmio_range, reg);
drivers/media/platform/ti/omap3isp/isp.h
331
u32 v = isp_reg_readl(isp, mmio_range, reg);
drivers/media/platform/ti/omap3isp/isp.h
333
isp_reg_writel(isp, v | set_bits, mmio_range, reg);
drivers/media/platform/ti/omap3isp/isp.h
350
u32 v = isp_reg_readl(isp, mmio_range, reg);
drivers/media/platform/ti/omap3isp/isp.h
352
isp_reg_writel(isp, (v & ~clr_bits) | set_bits, mmio_range, reg);
drivers/media/platform/verisilicon/hantro.h
446
u32 v;
drivers/media/platform/verisilicon/hantro.h
448
v = vdpu_read(vpu, reg->base);
drivers/media/platform/verisilicon/hantro.h
449
v &= ~(reg->mask << reg->shift);
drivers/media/platform/verisilicon/hantro.h
450
v |= ((val & reg->mask) << reg->shift);
drivers/media/platform/verisilicon/hantro.h
451
return v;
drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c
25
#define G1_REG_DEC_AXI_RD_ID(v) (((v) << 24) & GENMASK(31, 24))
drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c
26
#define G1_REG_DEC_TIMEOUT_E(v) ((v) ? BIT(23) : 0)
drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c
27
#define G1_REG_DEC_STRSWAP32_E(v) ((v) ? BIT(22) : 0)
drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c
28
#define G1_REG_DEC_STRENDIAN_E(v) ((v) ? BIT(21) : 0)
drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c
29
#define G1_REG_DEC_INSWAP32_E(v) ((v) ? BIT(20) : 0)
drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c
30
#define G1_REG_DEC_OUTSWAP32_E(v) ((v) ? BIT(19) : 0)
drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c
31
#define G1_REG_DEC_DATA_DISC_E(v) ((v) ? BIT(18) : 0)
drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c
32
#define G1_REG_DEC_LATENCY(v) (((v) << 11) & GENMASK(16, 11))
drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c
33
#define G1_REG_DEC_CLK_GATE_E(v) ((v) ? BIT(10) : 0)
drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c
34
#define G1_REG_DEC_IN_ENDIAN(v) ((v) ? BIT(9) : 0)
drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c
35
#define G1_REG_DEC_OUT_ENDIAN(v) ((v) ? BIT(8) : 0)
drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c
36
#define G1_REG_DEC_ADV_PRE_DIS(v) ((v) ? BIT(6) : 0)
drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c
37
#define G1_REG_DEC_SCMD_DIS(v) ((v) ? BIT(5) : 0)
drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c
38
#define G1_REG_DEC_MAX_BURST(v) (((v) << 0) & GENMASK(4, 0))
drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c
40
#define G1_REG_DEC_MODE(v) (((v) << 28) & GENMASK(31, 28))
drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c
41
#define G1_REG_RLC_MODE_E(v) ((v) ? BIT(27) : 0)
drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c
42
#define G1_REG_PIC_INTERLACE_E(v) ((v) ? BIT(23) : 0)
drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c
43
#define G1_REG_PIC_FIELDMODE_E(v) ((v) ? BIT(22) : 0)
drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c
44
#define G1_REG_PIC_B_E(v) ((v) ? BIT(21) : 0)
drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c
45
#define G1_REG_PIC_INTER_E(v) ((v) ? BIT(20) : 0)
drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c
46
#define G1_REG_PIC_TOPFIELD_E(v) ((v) ? BIT(19) : 0)
drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c
47
#define G1_REG_FWD_INTERLACE_E(v) ((v) ? BIT(18) : 0)
drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c
48
#define G1_REG_FILTERING_DIS(v) ((v) ? BIT(14) : 0)
drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c
49
#define G1_REG_WRITE_MVS_E(v) ((v) ? BIT(12) : 0)
drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c
50
#define G1_REG_DEC_AXI_WR_ID(v) (((v) << 0) & GENMASK(7, 0))
drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c
52
#define G1_REG_PIC_MB_WIDTH(v) (((v) << 23) & GENMASK(31, 23))
drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c
53
#define G1_REG_PIC_MB_HEIGHT_P(v) (((v) << 11) & GENMASK(18, 11))
drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c
54
#define G1_REG_ALT_SCAN_E(v) ((v) ? BIT(6) : 0)
drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c
55
#define G1_REG_TOPFIELDFIRST_E(v) ((v) ? BIT(5) : 0)
drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c
57
#define G1_REG_STRM_START_BIT(v) (((v) << 26) & GENMASK(31, 26))
drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c
58
#define G1_REG_QSCALE_TYPE(v) ((v) ? BIT(24) : 0)
drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c
59
#define G1_REG_CON_MV_E(v) ((v) ? BIT(4) : 0)
drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c
60
#define G1_REG_INTRA_DC_PREC(v) (((v) << 2) & GENMASK(3, 2))
drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c
61
#define G1_REG_INTRA_VLC_TAB(v) ((v) ? BIT(1) : 0)
drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c
62
#define G1_REG_FRAME_PRED_DCT(v) ((v) ? BIT(0) : 0)
drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c
64
#define G1_REG_INIT_QP(v) (((v) << 25) & GENMASK(30, 25))
drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c
65
#define G1_REG_STREAM_LEN(v) (((v) << 0) & GENMASK(23, 0))
drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c
67
#define G1_REG_ALT_SCAN_FLAG_E(v) ((v) ? BIT(19) : 0)
drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c
68
#define G1_REG_FCODE_FWD_HOR(v) (((v) << 15) & GENMASK(18, 15))
drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c
69
#define G1_REG_FCODE_FWD_VER(v) (((v) << 11) & GENMASK(14, 11))
drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c
70
#define G1_REG_FCODE_BWD_HOR(v) (((v) << 7) & GENMASK(10, 7))
drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c
71
#define G1_REG_FCODE_BWD_VER(v) (((v) << 3) & GENMASK(6, 3))
drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c
72
#define G1_REG_MV_ACCURACY_FWD(v) ((v) ? BIT(2) : 0)
drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c
73
#define G1_REG_MV_ACCURACY_BWD(v) ((v) ? BIT(1) : 0)
drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c
75
#define G1_REG_STARTMB_X(v) (((v) << 23) & GENMASK(31, 23))
drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c
76
#define G1_REG_STARTMB_Y(v) (((v) << 15) & GENMASK(22, 15))
drivers/media/platform/verisilicon/hantro_g1_mpeg2_dec.c
78
#define G1_REG_APF_THRESHOLD(v) (((v) << 0) & GENMASK(13, 0))
drivers/media/platform/verisilicon/hantro_g1_regs.h
313
#define G1_REG_PP_AXI_RD_ID(v) (((v) << 24) & GENMASK(31, 24))
drivers/media/platform/verisilicon/hantro_g1_regs.h
314
#define G1_REG_PP_AXI_WR_ID(v) (((v) << 16) & GENMASK(23, 16))
drivers/media/platform/verisilicon/hantro_g1_regs.h
315
#define G1_REG_PP_INSWAP32_E(v) ((v) ? BIT(10) : 0)
drivers/media/platform/verisilicon/hantro_g1_regs.h
316
#define G1_REG_PP_DATA_DISC_E(v) ((v) ? BIT(9) : 0)
drivers/media/platform/verisilicon/hantro_g1_regs.h
317
#define G1_REG_PP_CLK_GATE_E(v) ((v) ? BIT(8) : 0)
drivers/media/platform/verisilicon/hantro_g1_regs.h
318
#define G1_REG_PP_IN_ENDIAN(v) ((v) ? BIT(7) : 0)
drivers/media/platform/verisilicon/hantro_g1_regs.h
319
#define G1_REG_PP_OUT_ENDIAN(v) ((v) ? BIT(6) : 0)
drivers/media/platform/verisilicon/hantro_g1_regs.h
320
#define G1_REG_PP_OUTSWAP32_E(v) ((v) ? BIT(5) : 0)
drivers/media/platform/verisilicon/hantro_g1_regs.h
321
#define G1_REG_PP_MAX_BURST(v) (((v) << 0) & GENMASK(4, 0))
drivers/media/platform/verisilicon/hantro_g1_regs.h
332
#define G1_REG_PP_INPUT_SIZE_HEIGHT(v) (((v) << 9) & GENMASK(16, 9))
drivers/media/platform/verisilicon/hantro_g1_regs.h
333
#define G1_REG_PP_INPUT_SIZE_WIDTH(v) (((v) << 0) & GENMASK(8, 0))
drivers/media/platform/verisilicon/hantro_g1_regs.h
335
#define G1_REG_PP_PADD_R(v) (((v) << 23) & GENMASK(27, 23))
drivers/media/platform/verisilicon/hantro_g1_regs.h
336
#define G1_REG_PP_PADD_G(v) (((v) << 18) & GENMASK(22, 18))
drivers/media/platform/verisilicon/hantro_g1_regs.h
337
#define G1_REG_PP_RANGEMAP_Y(v) ((v) ? BIT(31) : 0)
drivers/media/platform/verisilicon/hantro_g1_regs.h
338
#define G1_REG_PP_RANGEMAP_C(v) ((v) ? BIT(30) : 0)
drivers/media/platform/verisilicon/hantro_g1_regs.h
339
#define G1_REG_PP_YCBCR_RANGE(v) ((v) ? BIT(29) : 0)
drivers/media/platform/verisilicon/hantro_g1_regs.h
340
#define G1_REG_PP_RGB_16(v) ((v) ? BIT(28) : 0)
drivers/media/platform/verisilicon/hantro_g1_regs.h
342
#define G1_REG_PP_PADD_B(v) (((v) << 18) & GENMASK(22, 18))
drivers/media/platform/verisilicon/hantro_g1_regs.h
347
#define G1_REG_PP_CONTROL_IN_FMT(v) (((v) << 29) & GENMASK(31, 29))
drivers/media/platform/verisilicon/hantro_g1_regs.h
348
#define G1_REG_PP_CONTROL_OUT_FMT(v) (((v) << 26) & GENMASK(28, 26))
drivers/media/platform/verisilicon/hantro_g1_regs.h
349
#define G1_REG_PP_CONTROL_OUT_HEIGHT(v) (((v) << 15) & GENMASK(25, 15))
drivers/media/platform/verisilicon/hantro_g1_regs.h
350
#define G1_REG_PP_CONTROL_OUT_WIDTH(v) (((v) << 4) & GENMASK(14, 4))
drivers/media/platform/verisilicon/hantro_g1_regs.h
352
#define G1_REG_PP_ORIG_WIDTH(v) (((v) << 23) & GENMASK(31, 23))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
101
#define VDPU_REG_REFER9_NBR(v) (((v) << 16) & GENMASK(31, 16))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
102
#define VDPU_REG_REFER8_NBR(v) (((v) << 0) & GENMASK(15, 0))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
104
#define VDPU_REG_REFER11_NBR(v) (((v) << 16) & GENMASK(31, 16))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
105
#define VDPU_REG_REFER10_NBR(v) (((v) << 0) & GENMASK(15, 0))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
107
#define VDPU_REG_REFER13_NBR(v) (((v) << 16) & GENMASK(31, 16))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
108
#define VDPU_REG_REFER12_NBR(v) (((v) << 0) & GENMASK(15, 0))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
110
#define VDPU_REG_REFER15_NBR(v) (((v) << 16) & GENMASK(31, 16))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
111
#define VDPU_REG_REFER14_NBR(v) (((v) << 0) & GENMASK(15, 0))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
113
#define VDPU_REG_BINIT_RLIST_F5(v) (((v) << 25) & GENMASK(29, 25))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
114
#define VDPU_REG_BINIT_RLIST_F4(v) (((v) << 20) & GENMASK(24, 20))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
115
#define VDPU_REG_BINIT_RLIST_F3(v) (((v) << 15) & GENMASK(19, 15))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
116
#define VDPU_REG_BINIT_RLIST_F2(v) (((v) << 10) & GENMASK(14, 10))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
117
#define VDPU_REG_BINIT_RLIST_F1(v) (((v) << 5) & GENMASK(9, 5))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
118
#define VDPU_REG_BINIT_RLIST_F0(v) (((v) << 0) & GENMASK(4, 0))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
120
#define VDPU_REG_BINIT_RLIST_F11(v) (((v) << 25) & GENMASK(29, 25))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
121
#define VDPU_REG_BINIT_RLIST_F10(v) (((v) << 20) & GENMASK(24, 20))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
122
#define VDPU_REG_BINIT_RLIST_F9(v) (((v) << 15) & GENMASK(19, 15))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
123
#define VDPU_REG_BINIT_RLIST_F8(v) (((v) << 10) & GENMASK(14, 10))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
124
#define VDPU_REG_BINIT_RLIST_F7(v) (((v) << 5) & GENMASK(9, 5))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
125
#define VDPU_REG_BINIT_RLIST_F6(v) (((v) << 0) & GENMASK(4, 0))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
127
#define VDPU_REG_BINIT_RLIST_F15(v) (((v) << 15) & GENMASK(19, 15))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
128
#define VDPU_REG_BINIT_RLIST_F14(v) (((v) << 10) & GENMASK(14, 10))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
129
#define VDPU_REG_BINIT_RLIST_F13(v) (((v) << 5) & GENMASK(9, 5))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
130
#define VDPU_REG_BINIT_RLIST_F12(v) (((v) << 0) & GENMASK(4, 0))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
132
#define VDPU_REG_BINIT_RLIST_B5(v) (((v) << 25) & GENMASK(29, 25))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
133
#define VDPU_REG_BINIT_RLIST_B4(v) (((v) << 20) & GENMASK(24, 20))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
134
#define VDPU_REG_BINIT_RLIST_B3(v) (((v) << 15) & GENMASK(19, 15))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
135
#define VDPU_REG_BINIT_RLIST_B2(v) (((v) << 10) & GENMASK(14, 10))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
136
#define VDPU_REG_BINIT_RLIST_B1(v) (((v) << 5) & GENMASK(9, 5))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
137
#define VDPU_REG_BINIT_RLIST_B0(v) (((v) << 0) & GENMASK(4, 0))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
139
#define VDPU_REG_BINIT_RLIST_B11(v) (((v) << 25) & GENMASK(29, 25))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
140
#define VDPU_REG_BINIT_RLIST_B10(v) (((v) << 20) & GENMASK(24, 20))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
141
#define VDPU_REG_BINIT_RLIST_B9(v) (((v) << 15) & GENMASK(19, 15))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
142
#define VDPU_REG_BINIT_RLIST_B8(v) (((v) << 10) & GENMASK(14, 10))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
143
#define VDPU_REG_BINIT_RLIST_B7(v) (((v) << 5) & GENMASK(9, 5))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
144
#define VDPU_REG_BINIT_RLIST_B6(v) (((v) << 0) & GENMASK(4, 0))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
146
#define VDPU_REG_BINIT_RLIST_B15(v) (((v) << 15) & GENMASK(19, 15))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
147
#define VDPU_REG_BINIT_RLIST_B14(v) (((v) << 10) & GENMASK(14, 10))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
148
#define VDPU_REG_BINIT_RLIST_B13(v) (((v) << 5) & GENMASK(9, 5))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
149
#define VDPU_REG_BINIT_RLIST_B12(v) (((v) << 0) & GENMASK(4, 0))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
151
#define VDPU_REG_PINIT_RLIST_F3(v) (((v) << 15) & GENMASK(19, 15))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
152
#define VDPU_REG_PINIT_RLIST_F2(v) (((v) << 10) & GENMASK(14, 10))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
153
#define VDPU_REG_PINIT_RLIST_F1(v) (((v) << 5) & GENMASK(9, 5))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
154
#define VDPU_REG_PINIT_RLIST_F0(v) (((v) << 0) & GENMASK(4, 0))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
156
#define VDPU_REG_REFER_LTERM_E(v) (((v) << 0) & GENMASK(31, 0))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
158
#define VDPU_REG_REFER_VALID_E(v) (((v) << 0) & GENMASK(31, 0))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
160
#define VDPU_REG_STRM_START_BIT(v) (((v) << 0) & GENMASK(5, 0))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
162
#define VDPU_REG_CH_QP_OFFSET2(v) (((v) << 22) & GENMASK(26, 22))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
163
#define VDPU_REG_CH_QP_OFFSET(v) (((v) << 17) & GENMASK(21, 17))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
164
#define VDPU_REG_PIC_MB_HEIGHT_P(v) (((v) << 9) & GENMASK(16, 9))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
165
#define VDPU_REG_PIC_MB_WIDTH(v) (((v) << 0) & GENMASK(8, 0))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
167
#define VDPU_REG_WEIGHT_BIPR_IDC(v) (((v) << 16) & GENMASK(17, 16))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
168
#define VDPU_REG_REF_FRAMES(v) (((v) << 0) & GENMASK(4, 0))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
170
#define VDPU_REG_FILT_CTRL_PRES(v) ((v) ? BIT(31) : 0)
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
171
#define VDPU_REG_RDPIC_CNT_PRES(v) ((v) ? BIT(30) : 0)
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
172
#define VDPU_REG_FRAMENUM_LEN(v) (((v) << 16) & GENMASK(20, 16))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
173
#define VDPU_REG_FRAMENUM(v) (((v) << 0) & GENMASK(15, 0))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
175
#define VDPU_REG_REFPIC_MK_LEN(v) (((v) << 16) & GENMASK(26, 16))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
176
#define VDPU_REG_IDR_PIC_ID(v) (((v) << 0) & GENMASK(15, 0))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
178
#define VDPU_REG_PPS_ID(v) (((v) << 24) & GENMASK(31, 24))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
179
#define VDPU_REG_REFIDX1_ACTIVE(v) (((v) << 19) & GENMASK(23, 19))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
180
#define VDPU_REG_REFIDX0_ACTIVE(v) (((v) << 14) & GENMASK(18, 14))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
181
#define VDPU_REG_POC_LENGTH(v) (((v) << 0) & GENMASK(7, 0))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
183
#define VDPU_REG_IDR_PIC_E(v) ((v) ? BIT(8) : 0)
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
184
#define VDPU_REG_DIR_8X8_INFER_E(v) ((v) ? BIT(7) : 0)
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
185
#define VDPU_REG_BLACKWHITE_E(v) ((v) ? BIT(6) : 0)
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
186
#define VDPU_REG_CABAC_E(v) ((v) ? BIT(5) : 0)
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
187
#define VDPU_REG_WEIGHT_PRED_E(v) ((v) ? BIT(4) : 0)
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
188
#define VDPU_REG_CONST_INTRA_E(v) ((v) ? BIT(3) : 0)
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
189
#define VDPU_REG_8X8TRANS_FLAG_E(v) ((v) ? BIT(2) : 0)
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
190
#define VDPU_REG_TYPE1_QUANT_E(v) ((v) ? BIT(1) : 0)
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
191
#define VDPU_REG_FIELDPIC_FLAG_E(v) ((v) ? BIT(0) : 0)
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
28
#define VDPU_REG_DEC_E(v) ((v) ? BIT(0) : 0)
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
30
#define VDPU_REG_DEC_ADV_PRE_DIS(v) ((v) ? BIT(11) : 0)
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
31
#define VDPU_REG_DEC_SCMD_DIS(v) ((v) ? BIT(10) : 0)
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
32
#define VDPU_REG_FILTERING_DIS(v) ((v) ? BIT(8) : 0)
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
33
#define VDPU_REG_PIC_FIXED_QUANT(v) ((v) ? BIT(7) : 0)
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
34
#define VDPU_REG_DEC_LATENCY(v) (((v) << 1) & GENMASK(6, 1))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
36
#define VDPU_REG_INIT_QP(v) (((v) << 25) & GENMASK(30, 25))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
37
#define VDPU_REG_STREAM_LEN(v) (((v) << 0) & GENMASK(23, 0))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
39
#define VDPU_REG_APF_THRESHOLD(v) (((v) << 17) & GENMASK(30, 17))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
40
#define VDPU_REG_STARTMB_X(v) (((v) << 8) & GENMASK(16, 8))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
41
#define VDPU_REG_STARTMB_Y(v) (((v) << 0) & GENMASK(7, 0))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
43
#define VDPU_REG_DEC_MODE(v) (((v) << 0) & GENMASK(3, 0))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
45
#define VDPU_REG_DEC_STRENDIAN_E(v) ((v) ? BIT(5) : 0)
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
46
#define VDPU_REG_DEC_STRSWAP32_E(v) ((v) ? BIT(4) : 0)
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
47
#define VDPU_REG_DEC_OUTSWAP32_E(v) ((v) ? BIT(3) : 0)
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
48
#define VDPU_REG_DEC_INSWAP32_E(v) ((v) ? BIT(2) : 0)
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
49
#define VDPU_REG_DEC_OUT_ENDIAN(v) ((v) ? BIT(1) : 0)
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
50
#define VDPU_REG_DEC_IN_ENDIAN(v) ((v) ? BIT(0) : 0)
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
52
#define VDPU_REG_DEC_DATA_DISC_E(v) ((v) ? BIT(22) : 0)
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
53
#define VDPU_REG_DEC_MAX_BURST(v) (((v) << 16) & GENMASK(20, 16))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
54
#define VDPU_REG_DEC_AXI_WR_ID(v) (((v) << 8) & GENMASK(15, 8))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
55
#define VDPU_REG_DEC_AXI_RD_ID(v) (((v) << 0) & GENMASK(7, 0))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
57
#define VDPU_REG_START_CODE_E(v) ((v) ? BIT(22) : 0)
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
58
#define VDPU_REG_CH_8PIX_ILEAV_E(v) ((v) ? BIT(21) : 0)
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
59
#define VDPU_REG_RLC_MODE_E(v) ((v) ? BIT(20) : 0)
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
60
#define VDPU_REG_PIC_INTERLACE_E(v) ((v) ? BIT(17) : 0)
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
61
#define VDPU_REG_PIC_FIELDMODE_E(v) ((v) ? BIT(16) : 0)
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
62
#define VDPU_REG_PIC_TOPFIELD_E(v) ((v) ? BIT(13) : 0)
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
63
#define VDPU_REG_WRITE_MVS_E(v) ((v) ? BIT(10) : 0)
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
64
#define VDPU_REG_SEQ_MBAFF_E(v) ((v) ? BIT(7) : 0)
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
65
#define VDPU_REG_PICORD_COUNT_E(v) ((v) ? BIT(6) : 0)
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
66
#define VDPU_REG_DEC_TIMEOUT_E(v) ((v) ? BIT(5) : 0)
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
67
#define VDPU_REG_DEC_CLK_GATE_E(v) ((v) ? BIT(4) : 0)
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
69
#define VDPU_REG_PRED_BC_TAP_0_0(v) (((v) << 22) & GENMASK(31, 22))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
70
#define VDPU_REG_PRED_BC_TAP_0_1(v) (((v) << 12) & GENMASK(21, 12))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
71
#define VDPU_REG_PRED_BC_TAP_0_2(v) (((v) << 2) & GENMASK(11, 2))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
73
#define VDPU_REG_REFBU_E(v) ((v) ? BIT(31) : 0)
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
75
#define VDPU_REG_PINIT_RLIST_F9(v) (((v) << 25) & GENMASK(29, 25))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
76
#define VDPU_REG_PINIT_RLIST_F8(v) (((v) << 20) & GENMASK(24, 20))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
77
#define VDPU_REG_PINIT_RLIST_F7(v) (((v) << 15) & GENMASK(19, 15))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
78
#define VDPU_REG_PINIT_RLIST_F6(v) (((v) << 10) & GENMASK(14, 10))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
79
#define VDPU_REG_PINIT_RLIST_F5(v) (((v) << 5) & GENMASK(9, 5))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
80
#define VDPU_REG_PINIT_RLIST_F4(v) (((v) << 0) & GENMASK(4, 0))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
82
#define VDPU_REG_PINIT_RLIST_F15(v) (((v) << 25) & GENMASK(29, 25))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
83
#define VDPU_REG_PINIT_RLIST_F14(v) (((v) << 20) & GENMASK(24, 20))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
84
#define VDPU_REG_PINIT_RLIST_F13(v) (((v) << 15) & GENMASK(19, 15))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
85
#define VDPU_REG_PINIT_RLIST_F12(v) (((v) << 10) & GENMASK(14, 10))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
86
#define VDPU_REG_PINIT_RLIST_F11(v) (((v) << 5) & GENMASK(9, 5))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
87
#define VDPU_REG_PINIT_RLIST_F10(v) (((v) << 0) & GENMASK(4, 0))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
89
#define VDPU_REG_REFER1_NBR(v) (((v) << 16) & GENMASK(31, 16))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
90
#define VDPU_REG_REFER0_NBR(v) (((v) << 0) & GENMASK(15, 0))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
92
#define VDPU_REG_REFER3_NBR(v) (((v) << 16) & GENMASK(31, 16))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
93
#define VDPU_REG_REFER2_NBR(v) (((v) << 0) & GENMASK(15, 0))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
95
#define VDPU_REG_REFER5_NBR(v) (((v) << 16) & GENMASK(31, 16))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
96
#define VDPU_REG_REFER4_NBR(v) (((v) << 0) & GENMASK(15, 0))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
98
#define VDPU_REG_REFER7_NBR(v) (((v) << 16) & GENMASK(31, 16))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_h264_dec.c
99
#define VDPU_REG_REFER6_NBR(v) (((v) << 0) & GENMASK(15, 0))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c
23
#define VDPU_REG_DEC_E(v) ((v) ? BIT(0) : 0)
drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c
25
#define VDPU_REG_DEC_ADV_PRE_DIS(v) ((v) ? BIT(11) : 0)
drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c
26
#define VDPU_REG_DEC_SCMD_DIS(v) ((v) ? BIT(10) : 0)
drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c
27
#define VDPU_REG_FILTERING_DIS(v) ((v) ? BIT(8) : 0)
drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c
28
#define VDPU_REG_DEC_LATENCY(v) (((v) << 1) & GENMASK(6, 1))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c
30
#define VDPU_REG_INIT_QP(v) (((v) << 25) & GENMASK(30, 25))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c
31
#define VDPU_REG_STREAM_LEN(v) (((v) << 0) & GENMASK(23, 0))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c
33
#define VDPU_REG_APF_THRESHOLD(v) (((v) << 17) & GENMASK(30, 17))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c
34
#define VDPU_REG_STARTMB_X(v) (((v) << 8) & GENMASK(16, 8))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c
35
#define VDPU_REG_STARTMB_Y(v) (((v) << 0) & GENMASK(7, 0))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c
37
#define VDPU_REG_DEC_MODE(v) (((v) << 0) & GENMASK(3, 0))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c
39
#define VDPU_REG_DEC_STRENDIAN_E(v) ((v) ? BIT(5) : 0)
drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c
40
#define VDPU_REG_DEC_STRSWAP32_E(v) ((v) ? BIT(4) : 0)
drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c
41
#define VDPU_REG_DEC_OUTSWAP32_E(v) ((v) ? BIT(3) : 0)
drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c
42
#define VDPU_REG_DEC_INSWAP32_E(v) ((v) ? BIT(2) : 0)
drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c
43
#define VDPU_REG_DEC_OUT_ENDIAN(v) ((v) ? BIT(1) : 0)
drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c
44
#define VDPU_REG_DEC_IN_ENDIAN(v) ((v) ? BIT(0) : 0)
drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c
46
#define VDPU_REG_DEC_DATA_DISC_E(v) ((v) ? BIT(22) : 0)
drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c
47
#define VDPU_REG_DEC_MAX_BURST(v) (((v) << 16) & GENMASK(20, 16))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c
48
#define VDPU_REG_DEC_AXI_WR_ID(v) (((v) << 8) & GENMASK(15, 8))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c
49
#define VDPU_REG_DEC_AXI_RD_ID(v) (((v) << 0) & GENMASK(7, 0))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c
51
#define VDPU_REG_RLC_MODE_E(v) ((v) ? BIT(20) : 0)
drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c
52
#define VDPU_REG_PIC_INTERLACE_E(v) ((v) ? BIT(17) : 0)
drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c
53
#define VDPU_REG_PIC_FIELDMODE_E(v) ((v) ? BIT(16) : 0)
drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c
54
#define VDPU_REG_PIC_B_E(v) ((v) ? BIT(15) : 0)
drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c
55
#define VDPU_REG_PIC_INTER_E(v) ((v) ? BIT(14) : 0)
drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c
56
#define VDPU_REG_PIC_TOPFIELD_E(v) ((v) ? BIT(13) : 0)
drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c
57
#define VDPU_REG_FWD_INTERLACE_E(v) ((v) ? BIT(12) : 0)
drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c
58
#define VDPU_REG_WRITE_MVS_E(v) ((v) ? BIT(10) : 0)
drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c
59
#define VDPU_REG_DEC_TIMEOUT_E(v) ((v) ? BIT(5) : 0)
drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c
60
#define VDPU_REG_DEC_CLK_GATE_E(v) ((v) ? BIT(4) : 0)
drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c
62
#define VDPU_REG_PIC_MB_WIDTH(v) (((v) << 23) & GENMASK(31, 23))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c
63
#define VDPU_REG_PIC_MB_HEIGHT_P(v) (((v) << 11) & GENMASK(18, 11))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c
64
#define VDPU_REG_ALT_SCAN_E(v) ((v) ? BIT(6) : 0)
drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c
65
#define VDPU_REG_TOPFIELDFIRST_E(v) ((v) ? BIT(5) : 0)
drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c
67
#define VDPU_REG_STRM_START_BIT(v) (((v) << 26) & GENMASK(31, 26))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c
68
#define VDPU_REG_QSCALE_TYPE(v) ((v) ? BIT(24) : 0)
drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c
69
#define VDPU_REG_CON_MV_E(v) ((v) ? BIT(4) : 0)
drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c
70
#define VDPU_REG_INTRA_DC_PREC(v) (((v) << 2) & GENMASK(3, 2))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c
71
#define VDPU_REG_INTRA_VLC_TAB(v) ((v) ? BIT(1) : 0)
drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c
72
#define VDPU_REG_FRAME_PRED_DCT(v) ((v) ? BIT(0) : 0)
drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c
74
#define VDPU_REG_ALT_SCAN_FLAG_E(v) ((v) ? BIT(19) : 0)
drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c
75
#define VDPU_REG_FCODE_FWD_HOR(v) (((v) << 15) & GENMASK(18, 15))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c
76
#define VDPU_REG_FCODE_FWD_VER(v) (((v) << 11) & GENMASK(14, 11))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c
77
#define VDPU_REG_FCODE_BWD_HOR(v) (((v) << 7) & GENMASK(10, 7))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c
78
#define VDPU_REG_FCODE_BWD_VER(v) (((v) << 3) & GENMASK(6, 3))
drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c
79
#define VDPU_REG_MV_ACCURACY_FWD(v) ((v) ? BIT(2) : 0)
drivers/media/platform/verisilicon/rockchip_vpu2_hw_mpeg2_dec.c
80
#define VDPU_REG_MV_ACCURACY_BWD(v) ((v) ? BIT(1) : 0)
drivers/media/radio/dsbr100.c
164
struct v4l2_capability *v)
drivers/media/radio/dsbr100.c
168
strscpy(v->driver, "dsbr100", sizeof(v->driver));
drivers/media/radio/dsbr100.c
169
strscpy(v->card, "D-Link R-100 USB FM Radio", sizeof(v->card));
drivers/media/radio/dsbr100.c
170
usb_make_path(radio->usbdev, v->bus_info, sizeof(v->bus_info));
drivers/media/radio/dsbr100.c
175
struct v4l2_tuner *v)
drivers/media/radio/dsbr100.c
179
if (v->index > 0)
drivers/media/radio/dsbr100.c
183
strscpy(v->name, "FM", sizeof(v->name));
drivers/media/radio/dsbr100.c
184
v->type = V4L2_TUNER_RADIO;
drivers/media/radio/dsbr100.c
185
v->rangelow = FREQ_MIN * FREQ_MUL;
drivers/media/radio/dsbr100.c
186
v->rangehigh = FREQ_MAX * FREQ_MUL;
drivers/media/radio/dsbr100.c
187
v->rxsubchans = radio->stereo ? V4L2_TUNER_SUB_STEREO :
drivers/media/radio/dsbr100.c
189
v->capability = V4L2_TUNER_CAP_LOW | V4L2_TUNER_CAP_STEREO;
drivers/media/radio/dsbr100.c
190
v->audmode = V4L2_TUNER_MODE_STEREO;
drivers/media/radio/dsbr100.c
191
v->signal = radio->stereo ? 0xffff : 0; /* We can't get the signal strength */
drivers/media/radio/dsbr100.c
196
const struct v4l2_tuner *v)
drivers/media/radio/dsbr100.c
198
return v->index ? -EINVAL : 0;
drivers/media/radio/radio-cadet.c
355
struct v4l2_capability *v)
drivers/media/radio/radio-cadet.c
357
strscpy(v->driver, "ADS Cadet", sizeof(v->driver));
drivers/media/radio/radio-cadet.c
358
strscpy(v->card, "ADS Cadet", sizeof(v->card));
drivers/media/radio/radio-cadet.c
359
strscpy(v->bus_info, "ISA:radio-cadet", sizeof(v->bus_info));
drivers/media/radio/radio-cadet.c
364
struct v4l2_tuner *v)
drivers/media/radio/radio-cadet.c
368
if (v->index)
drivers/media/radio/radio-cadet.c
370
v->type = V4L2_TUNER_RADIO;
drivers/media/radio/radio-cadet.c
371
strscpy(v->name, "Radio", sizeof(v->name));
drivers/media/radio/radio-cadet.c
372
v->capability = bands[0].capability | bands[1].capability;
drivers/media/radio/radio-cadet.c
373
v->rangelow = bands[0].rangelow; /* 520 kHz (start of AM band) */
drivers/media/radio/radio-cadet.c
374
v->rangehigh = bands[1].rangehigh; /* 108.0 MHz (end of FM band) */
drivers/media/radio/radio-cadet.c
376
v->rxsubchans = cadet_getstereo(dev);
drivers/media/radio/radio-cadet.c
382
v->rxsubchans |= V4L2_TUNER_SUB_RDS;
drivers/media/radio/radio-cadet.c
384
v->rangelow = 8320; /* 520 kHz */
drivers/media/radio/radio-cadet.c
385
v->rangehigh = 26400; /* 1650 kHz */
drivers/media/radio/radio-cadet.c
386
v->rxsubchans = V4L2_TUNER_SUB_MONO;
drivers/media/radio/radio-cadet.c
388
v->audmode = V4L2_TUNER_MODE_STEREO;
drivers/media/radio/radio-cadet.c
389
v->signal = dev->sigstrength; /* We might need to modify scaling of this */
drivers/media/radio/radio-cadet.c
394
const struct v4l2_tuner *v)
drivers/media/radio/radio-cadet.c
396
return v->index ? -EINVAL : 0;
drivers/media/radio/radio-isa.c
33
struct v4l2_capability *v)
drivers/media/radio/radio-isa.c
37
strscpy(v->driver, isa->drv->driver.driver.name, sizeof(v->driver));
drivers/media/radio/radio-isa.c
38
strscpy(v->card, isa->drv->card, sizeof(v->card));
drivers/media/radio/radio-isa.c
39
snprintf(v->bus_info, sizeof(v->bus_info), "ISA:%s", dev_name(isa->v4l2_dev.dev));
drivers/media/radio/radio-isa.c
44
struct v4l2_tuner *v)
drivers/media/radio/radio-isa.c
49
if (v->index > 0)
drivers/media/radio/radio-isa.c
52
strscpy(v->name, "FM", sizeof(v->name));
drivers/media/radio/radio-isa.c
53
v->type = V4L2_TUNER_RADIO;
drivers/media/radio/radio-isa.c
54
v->rangelow = FREQ_LOW;
drivers/media/radio/radio-isa.c
55
v->rangehigh = FREQ_HIGH;
drivers/media/radio/radio-isa.c
56
v->capability = V4L2_TUNER_CAP_LOW;
drivers/media/radio/radio-isa.c
58
v->capability |= V4L2_TUNER_CAP_STEREO;
drivers/media/radio/radio-isa.c
61
v->rxsubchans = ops->g_rxsubchans(isa);
drivers/media/radio/radio-isa.c
63
v->rxsubchans = V4L2_TUNER_SUB_MONO | V4L2_TUNER_SUB_STEREO;
drivers/media/radio/radio-isa.c
64
v->audmode = isa->stereo ? V4L2_TUNER_MODE_STEREO : V4L2_TUNER_MODE_MONO;
drivers/media/radio/radio-isa.c
66
v->signal = ops->g_signal(isa);
drivers/media/radio/radio-isa.c
68
v->signal = (v->rxsubchans & V4L2_TUNER_SUB_STEREO) ?
drivers/media/radio/radio-isa.c
74
const struct v4l2_tuner *v)
drivers/media/radio/radio-isa.c
79
if (v->index)
drivers/media/radio/radio-isa.c
82
isa->stereo = (v->audmode == V4L2_TUNER_MODE_STEREO);
drivers/media/radio/radio-keene.c
164
struct v4l2_capability *v)
drivers/media/radio/radio-keene.c
168
strscpy(v->driver, "radio-keene", sizeof(v->driver));
drivers/media/radio/radio-keene.c
169
strscpy(v->card, "Keene FM Transmitter", sizeof(v->card));
drivers/media/radio/radio-keene.c
170
usb_make_path(radio->usbdev, v->bus_info, sizeof(v->bus_info));
drivers/media/radio/radio-keene.c
175
struct v4l2_modulator *v)
drivers/media/radio/radio-keene.c
179
if (v->index > 0)
drivers/media/radio/radio-keene.c
182
strscpy(v->name, "FM", sizeof(v->name));
drivers/media/radio/radio-keene.c
183
v->rangelow = FREQ_MIN * FREQ_MUL;
drivers/media/radio/radio-keene.c
184
v->rangehigh = FREQ_MAX * FREQ_MUL;
drivers/media/radio/radio-keene.c
185
v->txsubchans = radio->stereo ? V4L2_TUNER_SUB_STEREO : V4L2_TUNER_SUB_MONO;
drivers/media/radio/radio-keene.c
186
v->capability = V4L2_TUNER_CAP_LOW | V4L2_TUNER_CAP_STEREO;
drivers/media/radio/radio-keene.c
191
const struct v4l2_modulator *v)
drivers/media/radio/radio-keene.c
195
if (v->index > 0)
drivers/media/radio/radio-keene.c
198
radio->stereo = (v->txsubchans == V4L2_TUNER_SUB_STEREO);
drivers/media/radio/radio-ma901.c
187
struct v4l2_capability *v)
drivers/media/radio/radio-ma901.c
191
strscpy(v->driver, "radio-ma901", sizeof(v->driver));
drivers/media/radio/radio-ma901.c
192
strscpy(v->card, "Masterkit MA901 USB FM Radio", sizeof(v->card));
drivers/media/radio/radio-ma901.c
193
usb_make_path(radio->usbdev, v->bus_info, sizeof(v->bus_info));
drivers/media/radio/radio-ma901.c
199
struct v4l2_tuner *v)
drivers/media/radio/radio-ma901.c
203
if (v->index > 0)
drivers/media/radio/radio-ma901.c
206
v->signal = 0;
drivers/media/radio/radio-ma901.c
214
strscpy(v->name, "FM", sizeof(v->name));
drivers/media/radio/radio-ma901.c
215
v->type = V4L2_TUNER_RADIO;
drivers/media/radio/radio-ma901.c
216
v->rangelow = FREQ_MIN * FREQ_MUL;
drivers/media/radio/radio-ma901.c
217
v->rangehigh = FREQ_MAX * FREQ_MUL;
drivers/media/radio/radio-ma901.c
218
v->capability = V4L2_TUNER_CAP_LOW | V4L2_TUNER_CAP_STEREO;
drivers/media/radio/radio-ma901.c
220
v->audmode = radio->stereo ?
drivers/media/radio/radio-ma901.c
227
const struct v4l2_tuner *v)
drivers/media/radio/radio-ma901.c
231
if (v->index > 0)
drivers/media/radio/radio-ma901.c
235
switch (v->audmode) {
drivers/media/radio/radio-miropcm20.c
200
struct v4l2_capability *v)
drivers/media/radio/radio-miropcm20.c
202
strscpy(v->driver, "Miro PCM20", sizeof(v->driver));
drivers/media/radio/radio-miropcm20.c
203
strscpy(v->card, "Miro PCM20", sizeof(v->card));
drivers/media/radio/radio-miropcm20.c
204
strscpy(v->bus_info, "ISA:radio-miropcm20", sizeof(v->bus_info));
drivers/media/radio/radio-miropcm20.c
223
struct v4l2_tuner *v)
drivers/media/radio/radio-miropcm20.c
229
if (v->index)
drivers/media/radio/radio-miropcm20.c
231
strscpy(v->name, "FM", sizeof(v->name));
drivers/media/radio/radio-miropcm20.c
232
v->type = V4L2_TUNER_RADIO;
drivers/media/radio/radio-miropcm20.c
233
v->rangelow = 87*16000;
drivers/media/radio/radio-miropcm20.c
234
v->rangehigh = 108*16000;
drivers/media/radio/radio-miropcm20.c
236
v->signal = (res & 0x80) ? 0 : 0xffff;
drivers/media/radio/radio-miropcm20.c
240
v->rxsubchans = (res & 0x40) ? V4L2_TUNER_SUB_MONO :
drivers/media/radio/radio-miropcm20.c
242
v->capability = V4L2_TUNER_CAP_LOW | V4L2_TUNER_CAP_STEREO |
drivers/media/radio/radio-miropcm20.c
244
v->audmode = dev->audmode;
drivers/media/radio/radio-miropcm20.c
247
v->rxsubchans |= V4L2_TUNER_SUB_RDS;
drivers/media/radio/radio-miropcm20.c
252
const struct v4l2_tuner *v)
drivers/media/radio/radio-miropcm20.c
256
if (v->index)
drivers/media/radio/radio-miropcm20.c
258
if (v->audmode > V4L2_TUNER_MODE_STEREO)
drivers/media/radio/radio-miropcm20.c
261
dev->audmode = v->audmode;
drivers/media/radio/radio-mr800.c
256
struct v4l2_capability *v)
drivers/media/radio/radio-mr800.c
260
strscpy(v->driver, "radio-mr800", sizeof(v->driver));
drivers/media/radio/radio-mr800.c
261
strscpy(v->card, "AverMedia MR 800 USB FM Radio", sizeof(v->card));
drivers/media/radio/radio-mr800.c
262
usb_make_path(radio->usbdev, v->bus_info, sizeof(v->bus_info));
drivers/media/radio/radio-mr800.c
268
struct v4l2_tuner *v)
drivers/media/radio/radio-mr800.c
274
if (v->index > 0)
drivers/media/radio/radio-mr800.c
277
v->signal = 0;
drivers/media/radio/radio-mr800.c
278
retval = amradio_get_stat(radio, &is_stereo, &v->signal);
drivers/media/radio/radio-mr800.c
282
strscpy(v->name, "FM", sizeof(v->name));
drivers/media/radio/radio-mr800.c
283
v->type = V4L2_TUNER_RADIO;
drivers/media/radio/radio-mr800.c
284
v->rangelow = FREQ_MIN * FREQ_MUL;
drivers/media/radio/radio-mr800.c
285
v->rangehigh = FREQ_MAX * FREQ_MUL;
drivers/media/radio/radio-mr800.c
286
v->capability = V4L2_TUNER_CAP_LOW | V4L2_TUNER_CAP_STEREO |
drivers/media/radio/radio-mr800.c
288
v->rxsubchans = is_stereo ? V4L2_TUNER_SUB_STEREO : V4L2_TUNER_SUB_MONO;
drivers/media/radio/radio-mr800.c
289
v->audmode = radio->stereo ?
drivers/media/radio/radio-mr800.c
296
const struct v4l2_tuner *v)
drivers/media/radio/radio-mr800.c
300
if (v->index > 0)
drivers/media/radio/radio-mr800.c
304
switch (v->audmode) {
drivers/media/radio/radio-raremono.c
180
struct v4l2_capability *v)
drivers/media/radio/radio-raremono.c
184
strscpy(v->driver, "radio-raremono", sizeof(v->driver));
drivers/media/radio/radio-raremono.c
185
strscpy(v->card, "Thanko's Raremono", sizeof(v->card));
drivers/media/radio/radio-raremono.c
186
usb_make_path(radio->usbdev, v->bus_info, sizeof(v->bus_info));
drivers/media/radio/radio-raremono.c
205
struct v4l2_tuner *v)
drivers/media/radio/radio-raremono.c
210
if (v->index > 0)
drivers/media/radio/radio-raremono.c
213
strscpy(v->name, "AM/FM/SW", sizeof(v->name));
drivers/media/radio/radio-raremono.c
214
v->capability = V4L2_TUNER_CAP_LOW | V4L2_TUNER_CAP_STEREO |
drivers/media/radio/radio-raremono.c
216
v->rangelow = AM_FREQ_RANGE_LOW * 16;
drivers/media/radio/radio-raremono.c
217
v->rangehigh = FM_FREQ_RANGE_HIGH * 16;
drivers/media/radio/radio-raremono.c
218
v->rxsubchans = V4L2_TUNER_SUB_STEREO | V4L2_TUNER_SUB_MONO;
drivers/media/radio/radio-raremono.c
219
v->audmode = (radio->curfreq < FM_FREQ_RANGE_LOW) ?
drivers/media/radio/radio-raremono.c
229
v->signal = ((radio->buffer[1] & 0xf) << 8 | radio->buffer[2]) << 4;
drivers/media/radio/radio-raremono.c
234
const struct v4l2_tuner *v)
drivers/media/radio/radio-raremono.c
236
return v->index ? -EINVAL : 0;
drivers/media/radio/radio-sf16fmi.c
131
struct v4l2_capability *v)
drivers/media/radio/radio-sf16fmi.c
133
strscpy(v->driver, "radio-sf16fmi", sizeof(v->driver));
drivers/media/radio/radio-sf16fmi.c
134
strscpy(v->card, "SF16-FMI/FMP/FMD radio", sizeof(v->card));
drivers/media/radio/radio-sf16fmi.c
135
strscpy(v->bus_info, "ISA:radio-sf16fmi", sizeof(v->bus_info));
drivers/media/radio/radio-sf16fmi.c
140
struct v4l2_tuner *v)
drivers/media/radio/radio-sf16fmi.c
144
if (v->index > 0)
drivers/media/radio/radio-sf16fmi.c
147
strscpy(v->name, "FM", sizeof(v->name));
drivers/media/radio/radio-sf16fmi.c
148
v->type = V4L2_TUNER_RADIO;
drivers/media/radio/radio-sf16fmi.c
149
v->rangelow = RSF16_MINFREQ;
drivers/media/radio/radio-sf16fmi.c
150
v->rangehigh = RSF16_MAXFREQ;
drivers/media/radio/radio-sf16fmi.c
151
v->rxsubchans = V4L2_TUNER_SUB_MONO | V4L2_TUNER_SUB_STEREO;
drivers/media/radio/radio-sf16fmi.c
152
v->capability = V4L2_TUNER_CAP_STEREO | V4L2_TUNER_CAP_LOW;
drivers/media/radio/radio-sf16fmi.c
153
v->audmode = V4L2_TUNER_MODE_STEREO;
drivers/media/radio/radio-sf16fmi.c
154
v->signal = fmi_getsigstr(fmi);
drivers/media/radio/radio-sf16fmi.c
159
const struct v4l2_tuner *v)
drivers/media/radio/radio-sf16fmi.c
161
return v->index ? -EINVAL : 0;
drivers/media/radio/radio-tea5764.c
276
struct v4l2_capability *v)
drivers/media/radio/radio-tea5764.c
281
strscpy(v->driver, dev->dev.driver->name, sizeof(v->driver));
drivers/media/radio/radio-tea5764.c
282
strscpy(v->card, dev->name, sizeof(v->card));
drivers/media/radio/radio-tea5764.c
283
snprintf(v->bus_info, sizeof(v->bus_info),
drivers/media/radio/radio-tea5764.c
289
struct v4l2_tuner *v)
drivers/media/radio/radio-tea5764.c
294
if (v->index > 0)
drivers/media/radio/radio-tea5764.c
297
strscpy(v->name, "FM", sizeof(v->name));
drivers/media/radio/radio-tea5764.c
298
v->type = V4L2_TUNER_RADIO;
drivers/media/radio/radio-tea5764.c
300
v->rangelow = FREQ_MIN * FREQ_MUL;
drivers/media/radio/radio-tea5764.c
301
v->rangehigh = FREQ_MAX * FREQ_MUL;
drivers/media/radio/radio-tea5764.c
302
v->capability = V4L2_TUNER_CAP_LOW | V4L2_TUNER_CAP_STEREO;
drivers/media/radio/radio-tea5764.c
304
v->rxsubchans = V4L2_TUNER_SUB_STEREO;
drivers/media/radio/radio-tea5764.c
306
v->rxsubchans = V4L2_TUNER_SUB_MONO;
drivers/media/radio/radio-tea5764.c
307
v->audmode = tea5764_get_audout_mode(radio);
drivers/media/radio/radio-tea5764.c
308
v->signal = TEA5764_TUNCHK_LEVEL(r->tunchk) * 0xffff / 0xf;
drivers/media/radio/radio-tea5764.c
309
v->afc = TEA5764_TUNCHK_IFCNT(r->tunchk);
drivers/media/radio/radio-tea5764.c
315
const struct v4l2_tuner *v)
drivers/media/radio/radio-tea5764.c
319
if (v->index > 0)
drivers/media/radio/radio-tea5764.c
322
tea5764_set_audout_mode(radio, v->audmode);
drivers/media/radio/radio-tea5777.c
255
struct v4l2_capability *v)
drivers/media/radio/radio-tea5777.c
259
strscpy(v->driver, tea->v4l2_dev->name, sizeof(v->driver));
drivers/media/radio/radio-tea5777.c
260
strscpy(v->card, tea->card, sizeof(v->card));
drivers/media/radio/radio-tea5777.c
261
strlcat(v->card, " TEA5777", sizeof(v->card));
drivers/media/radio/radio-tea5777.c
262
strscpy(v->bus_info, tea->bus_info, sizeof(v->bus_info));
drivers/media/radio/radio-tea5777.c
280
struct v4l2_tuner *v)
drivers/media/radio/radio-tea5777.c
285
if (v->index > 0)
drivers/media/radio/radio-tea5777.c
292
memset(v, 0, sizeof(*v));
drivers/media/radio/radio-tea5777.c
294
strscpy(v->name, "AM/FM", sizeof(v->name));
drivers/media/radio/radio-tea5777.c
296
strscpy(v->name, "FM", sizeof(v->name));
drivers/media/radio/radio-tea5777.c
297
v->type = V4L2_TUNER_RADIO;
drivers/media/radio/radio-tea5777.c
298
v->capability = V4L2_TUNER_CAP_LOW | V4L2_TUNER_CAP_STEREO |
drivers/media/radio/radio-tea5777.c
302
v->rangelow = tea->has_am ? bands[BAND_AM].rangelow :
drivers/media/radio/radio-tea5777.c
304
v->rangehigh = bands[BAND_FM].rangehigh;
drivers/media/radio/radio-tea5777.c
307
v->rxsubchans = V4L2_TUNER_SUB_STEREO;
drivers/media/radio/radio-tea5777.c
309
v->rxsubchans = V4L2_TUNER_SUB_MONO;
drivers/media/radio/radio-tea5777.c
310
v->audmode = tea->audmode;
drivers/media/radio/radio-tea5777.c
312
v->signal = (tea->read_reg & TEA5777_R_LEVEL_MASK) >>
drivers/media/radio/radio-tea5777.c
322
const struct v4l2_tuner *v)
drivers/media/radio/radio-tea5777.c
327
if (v->index)
drivers/media/radio/radio-tea5777.c
330
tea->audmode = v->audmode;
drivers/media/radio/radio-timb.c
32
struct v4l2_capability *v)
drivers/media/radio/radio-timb.c
34
strscpy(v->driver, DRIVER_NAME, sizeof(v->driver));
drivers/media/radio/radio-timb.c
35
strscpy(v->card, "Timberdale Radio", sizeof(v->card));
drivers/media/radio/radio-timb.c
36
snprintf(v->bus_info, sizeof(v->bus_info), "platform:"DRIVER_NAME);
drivers/media/radio/radio-timb.c
41
struct v4l2_tuner *v)
drivers/media/radio/radio-timb.c
44
return v4l2_subdev_call(tr->sd_tuner, tuner, g_tuner, v);
drivers/media/radio/radio-timb.c
48
const struct v4l2_tuner *v)
drivers/media/radio/radio-timb.c
51
return v4l2_subdev_call(tr->sd_tuner, tuner, s_tuner, v);
drivers/media/radio/radio-trust.c
140
int i, v;
drivers/media/radio/radio-trust.c
142
for (i = 0, v = 0; i < 100; i++)
drivers/media/radio/radio-trust.c
143
v |= inb(isa->io);
drivers/media/radio/radio-trust.c
144
return (v & 1) ? 0 : 0xffff;
drivers/media/radio/si4713/radio-usb-si4713.c
66
struct v4l2_capability *v)
drivers/media/radio/si4713/radio-usb-si4713.c
70
strscpy(v->driver, "radio-usb-si4713", sizeof(v->driver));
drivers/media/radio/si4713/radio-usb-si4713.c
71
strscpy(v->card, "Si4713 FM Transmitter", sizeof(v->card));
drivers/media/radio/si4713/radio-usb-si4713.c
72
usb_make_path(radio->usbdev, v->bus_info, sizeof(v->bus_info));
drivers/media/radio/si4713/si4713.c
76
#define set_bits(p, v, b, m) (((p) & ~(m)) | ((v) << (b)))
drivers/media/radio/tea575x.c
221
struct v4l2_capability *v)
drivers/media/radio/tea575x.c
225
strscpy(v->driver, tea->v4l2_dev->name, sizeof(v->driver));
drivers/media/radio/tea575x.c
226
strscpy(v->card, tea->card, sizeof(v->card));
drivers/media/radio/tea575x.c
227
strlcat(v->card, tea->tea5759 ? " TEA5759" : " TEA5757", sizeof(v->card));
drivers/media/radio/tea575x.c
228
strscpy(v->bus_info, tea->bus_info, sizeof(v->bus_info));
drivers/media/radio/tea575x.c
273
int snd_tea575x_g_tuner(struct snd_tea575x *tea, struct v4l2_tuner *v)
drivers/media/radio/tea575x.c
277
if (v->index > 0)
drivers/media/radio/tea575x.c
283
memset(v, 0, sizeof(*v));
drivers/media/radio/tea575x.c
284
strscpy(v->name, tea->has_am ? "FM/AM" : "FM", sizeof(v->name));
drivers/media/radio/tea575x.c
285
v->type = V4L2_TUNER_RADIO;
drivers/media/radio/tea575x.c
286
v->capability = band_fm.capability;
drivers/media/radio/tea575x.c
287
v->rangelow = tea->has_am ? bands[BAND_AM].rangelow : band_fm.rangelow;
drivers/media/radio/tea575x.c
288
v->rangehigh = band_fm.rangehigh;
drivers/media/radio/tea575x.c
289
v->rxsubchans = tea->stereo ? V4L2_TUNER_SUB_STEREO : V4L2_TUNER_SUB_MONO;
drivers/media/radio/tea575x.c
290
v->audmode = (tea->val & TEA575X_BIT_MONO) ?
drivers/media/radio/tea575x.c
292
v->signal = tea->tuned ? 0xffff : 0;
drivers/media/radio/tea575x.c
298
struct v4l2_tuner *v)
drivers/media/radio/tea575x.c
302
return snd_tea575x_g_tuner(tea, v);
drivers/media/radio/tea575x.c
306
const struct v4l2_tuner *v)
drivers/media/radio/tea575x.c
311
if (v->index)
drivers/media/radio/tea575x.c
314
if (v->audmode == V4L2_TUNER_MODE_MONO)
drivers/media/radio/tef6862.c
68
static int tef6862_g_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *v)
drivers/media/radio/tef6862.c
70
if (v->index > 0)
drivers/media/radio/tef6862.c
74
strscpy(v->name, "FM", sizeof(v->name));
drivers/media/radio/tef6862.c
75
v->type = V4L2_TUNER_RADIO;
drivers/media/radio/tef6862.c
76
v->rangelow = TEF6862_LO_FREQ;
drivers/media/radio/tef6862.c
77
v->rangehigh = TEF6862_HI_FREQ;
drivers/media/radio/tef6862.c
78
v->rxsubchans = V4L2_TUNER_SUB_MONO;
drivers/media/radio/tef6862.c
79
v->capability = V4L2_TUNER_CAP_LOW;
drivers/media/radio/tef6862.c
80
v->audmode = V4L2_TUNER_MODE_STEREO;
drivers/media/radio/tef6862.c
81
v->signal = tef6862_sigstr(v4l2_get_subdevdata(sd));
drivers/media/radio/tef6862.c
86
static int tef6862_s_tuner(struct v4l2_subdev *sd, const struct v4l2_tuner *v)
drivers/media/radio/tef6862.c
88
return v->index ? -EINVAL : 0;
drivers/media/rc/ir_toy.c
133
u16 v = be16_to_cpu(in[i]);
drivers/media/rc/ir_toy.c
135
if (v == 0xffff) {
drivers/media/rc/ir_toy.c
138
rawir.duration = v * UNIT_US;
drivers/media/rc/ir_toy.c
314
u16 v = DIV_ROUND_CLOSEST(txbuf[i], UNIT_US);
drivers/media/rc/ir_toy.c
316
if (!v)
drivers/media/rc/ir_toy.c
317
v = 1;
drivers/media/rc/ir_toy.c
318
buf[i] = cpu_to_be16(v);
drivers/media/rc/mtk-cir.c
55
#define MTK_IR_END(v, p) ((v) == MTK_MAX_SAMPLES && (p) == 0)
drivers/media/rc/ttusbir.c
111
unsigned i, v, b;
drivers/media/rc/ttusbir.c
115
v = buf[i] & 0xfe;
drivers/media/rc/ttusbir.c
116
switch (v) {
drivers/media/rc/ttusbir.c
131
if (v & 2) {
drivers/media/rc/ttusbir.c
132
b = ffz(v | 1);
drivers/media/rc/ttusbir.c
135
b = ffs(v) - 1;
drivers/media/test-drivers/vim2m.c
388
u8 y, y1, u, v;
drivers/media/test-drivers/vim2m.c
394
v = ((14456 * (*r++) - 12105 * (*g++) - 2351 * (*b++)
drivers/media/test-drivers/vim2m.c
403
*(*dst)++ = v;
drivers/media/tuners/e4000.c
295
static int e4000_g_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *v)
drivers/media/tuners/e4000.c
300
dev_dbg(&client->dev, "index=%d\n", v->index);
drivers/media/tuners/e4000.c
302
strscpy(v->name, "Elonics E4000", sizeof(v->name));
drivers/media/tuners/e4000.c
303
v->type = V4L2_TUNER_RF;
drivers/media/tuners/e4000.c
304
v->capability = V4L2_TUNER_CAP_1HZ | V4L2_TUNER_CAP_FREQ_BANDS;
drivers/media/tuners/e4000.c
305
v->rangelow = bands[0].rangelow;
drivers/media/tuners/e4000.c
306
v->rangehigh = bands[1].rangehigh;
drivers/media/tuners/e4000.c
310
static int e4000_s_tuner(struct v4l2_subdev *sd, const struct v4l2_tuner *v)
drivers/media/tuners/e4000.c
315
dev_dbg(&client->dev, "index=%d\n", v->index);
drivers/media/tuners/fc2580.c
388
static int fc2580_g_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *v)
drivers/media/tuners/fc2580.c
393
dev_dbg(&client->dev, "index=%d\n", v->index);
drivers/media/tuners/fc2580.c
395
strscpy(v->name, "FCI FC2580", sizeof(v->name));
drivers/media/tuners/fc2580.c
396
v->type = V4L2_TUNER_RF;
drivers/media/tuners/fc2580.c
397
v->capability = V4L2_TUNER_CAP_1HZ | V4L2_TUNER_CAP_FREQ_BANDS;
drivers/media/tuners/fc2580.c
398
v->rangelow = bands[0].rangelow;
drivers/media/tuners/fc2580.c
399
v->rangehigh = bands[0].rangehigh;
drivers/media/tuners/fc2580.c
403
static int fc2580_s_tuner(struct v4l2_subdev *sd, const struct v4l2_tuner *v)
drivers/media/tuners/fc2580.c
408
dev_dbg(&client->dev, "index=%d\n", v->index);
drivers/media/tuners/max2165.c
123
u8 v;
drivers/media/tuners/max2165.c
125
v = (osc / 2);
drivers/media/tuners/max2165.c
126
if (v == 2)
drivers/media/tuners/max2165.c
127
v = 0x7;
drivers/media/tuners/max2165.c
129
v -= 8;
drivers/media/tuners/max2165.c
131
max2165_mask_write_reg(priv, REG_PLL_CFG, 0x07, v);
drivers/media/tuners/max2165.c
81
u8 v;
drivers/media/tuners/max2165.c
84
ret = max2165_read_reg(priv, reg, &v);
drivers/media/tuners/max2165.c
87
v &= ~mask;
drivers/media/tuners/max2165.c
88
v |= data;
drivers/media/tuners/max2165.c
89
ret = max2165_write_reg(priv, reg, v);
drivers/media/tuners/msi001.c
292
static int msi001_g_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *v)
drivers/media/tuners/msi001.c
297
dev_dbg(&spi->dev, "index=%d\n", v->index);
drivers/media/tuners/msi001.c
299
strscpy(v->name, "Mirics MSi001", sizeof(v->name));
drivers/media/tuners/msi001.c
300
v->type = V4L2_TUNER_RF;
drivers/media/tuners/msi001.c
301
v->capability = V4L2_TUNER_CAP_1HZ | V4L2_TUNER_CAP_FREQ_BANDS;
drivers/media/tuners/msi001.c
302
v->rangelow = 49000000;
drivers/media/tuners/msi001.c
303
v->rangehigh = 960000000;
drivers/media/tuners/msi001.c
308
static int msi001_s_tuner(struct v4l2_subdev *sd, const struct v4l2_tuner *v)
drivers/media/tuners/msi001.c
313
dev_dbg(&spi->dev, "index=%d\n", v->index);
drivers/media/usb/airspy/airspy.c
462
struct v4l2_device *v = usb_get_intfdata(intf);
drivers/media/usb/airspy/airspy.c
463
struct airspy *s = container_of(v, struct airspy, v4l2_dev);
drivers/media/usb/airspy/airspy.c
687
const struct v4l2_tuner *v)
drivers/media/usb/airspy/airspy.c
691
if (v->index == 0)
drivers/media/usb/airspy/airspy.c
693
else if (v->index == 1)
drivers/media/usb/airspy/airspy.c
701
static int airspy_g_tuner(struct file *file, void *priv, struct v4l2_tuner *v)
drivers/media/usb/airspy/airspy.c
705
if (v->index == 0) {
drivers/media/usb/airspy/airspy.c
706
strscpy(v->name, "AirSpy ADC", sizeof(v->name));
drivers/media/usb/airspy/airspy.c
707
v->type = V4L2_TUNER_ADC;
drivers/media/usb/airspy/airspy.c
708
v->capability = V4L2_TUNER_CAP_1HZ | V4L2_TUNER_CAP_FREQ_BANDS;
drivers/media/usb/airspy/airspy.c
709
v->rangelow = bands[0].rangelow;
drivers/media/usb/airspy/airspy.c
710
v->rangehigh = bands[0].rangehigh;
drivers/media/usb/airspy/airspy.c
712
} else if (v->index == 1) {
drivers/media/usb/airspy/airspy.c
713
strscpy(v->name, "AirSpy RF", sizeof(v->name));
drivers/media/usb/airspy/airspy.c
714
v->type = V4L2_TUNER_RF;
drivers/media/usb/airspy/airspy.c
715
v->capability = V4L2_TUNER_CAP_1HZ | V4L2_TUNER_CAP_FREQ_BANDS;
drivers/media/usb/airspy/airspy.c
716
v->rangelow = bands_rf[0].rangelow;
drivers/media/usb/airspy/airspy.c
717
v->rangehigh = bands_rf[0].rangehigh;
drivers/media/usb/airspy/airspy.c
852
static void airspy_video_release(struct v4l2_device *v)
drivers/media/usb/airspy/airspy.c
854
struct airspy *s = container_of(v, struct airspy, v4l2_dev);
drivers/media/usb/dvb-usb-v2/dvb_usb.h
54
#define dvb_usb_dbg_usb_control_msg(udev, r, t, v, i, b, l) { \
drivers/media/usb/dvb-usb-v2/dvb_usb.h
61
"%s %*ph\n", __func__, t, r, v & 0xff, v >> 8, \
drivers/media/usb/dvb-usb/dw2102.c
70
int (*old_set_voltage)(struct dvb_frontend *f, enum fe_sec_voltage v);
drivers/media/usb/dvb-usb/vp7045.c
123
u8 v, br[2];
drivers/media/usb/dvb-usb/vp7045.c
125
v = offset + i;
drivers/media/usb/dvb-usb/vp7045.c
126
ret = vp7045_usb_op(d, GET_EE_VALUE, &v, 1, br, 2, 5);
drivers/media/usb/dvb-usb/vp7045.c
83
u8 obuf[2] = { 0 },v;
drivers/media/usb/dvb-usb/vp7045.c
86
vp7045_usb_op(d,TUNER_REG_READ,obuf,2,&v,1,30);
drivers/media/usb/dvb-usb/vp7045.c
88
return v;
drivers/media/usb/dvb-usb/vp7045.c
93
u8 v = onoff;
drivers/media/usb/dvb-usb/vp7045.c
94
return vp7045_usb_op(d,SET_TUNER_POWER,&v,1,NULL,0,150);
drivers/media/usb/em28xx/em28xx-video.c
286
static int em28xx_scaler_set(struct em28xx *dev, u16 h, u16 v)
drivers/media/usb/em28xx/em28xx-video.c
292
mode = (v ? 0x20 : 0x00) | (h ? 0x10 : 0x00);
drivers/media/usb/em28xx/em28xx-video.c
300
buf[0] = v;
drivers/media/usb/em28xx/em28xx-video.c
301
buf[1] = v >> 8;
drivers/media/usb/em28xx/em28xx-video.c
307
mode = (h || v) ? 0x30 : 0x00;
drivers/media/usb/gspca/nw80x.c
1637
static int swap_bits(int v)
drivers/media/usb/gspca/nw80x.c
1644
if (v & 1)
drivers/media/usb/gspca/nw80x.c
1646
v >>= 1;
drivers/media/usb/gspca/nw80x.c
1654
u8 v[2];
drivers/media/usb/gspca/nw80x.c
1663
v[0] = val << 3;
drivers/media/usb/gspca/nw80x.c
1664
v[1] = val >> 5;
drivers/media/usb/gspca/nw80x.c
1665
reg_w(gspca_dev, 0x101d, v, 2); /* SIF reg0/1 (AGC) */
drivers/media/usb/gspca/nw80x.c
1673
u8 v[2];
drivers/media/usb/gspca/nw80x.c
1677
v[0] = ((9 - val) << 3) | 0x01;
drivers/media/usb/gspca/nw80x.c
1678
reg_w(gspca_dev, 0x1019, v, 1);
drivers/media/usb/gspca/nw80x.c
1684
v[0] = val;
drivers/media/usb/gspca/nw80x.c
1685
v[1] = val >> 8;
drivers/media/usb/gspca/nw80x.c
1686
reg_w(gspca_dev, 0x101b, v, 2);
drivers/media/usb/gspca/ov519.c
1981
static unsigned char ov7670_abs_to_sm(unsigned char v)
drivers/media/usb/gspca/ov519.c
1983
if (v > 127)
drivers/media/usb/gspca/ov519.c
1984
return v & 0x7f;
drivers/media/usb/gspca/ov519.c
1985
return (128 - v) | 0x80;
drivers/media/usb/gspca/ov519.c
3907
u8 v;
drivers/media/usb/gspca/ov519.c
3923
u8 v;
drivers/media/usb/gspca/ov519.c
3929
v = 80;
drivers/media/usb/gspca/ov519.c
3932
v = 0x81;
drivers/media/usb/gspca/ov519.c
3935
v = 0x81;
drivers/media/usb/gspca/ov519.c
3937
i2c_w(sd, 0x11, v);
drivers/media/usb/gspca/ov519.c
4035
v = i2c_r(sd, OV7670_R32_HREF);
drivers/media/usb/gspca/ov519.c
4036
v = (v & 0xc0) | ((xend & 0x7) << 3) | (xstart & 0x07);
drivers/media/usb/gspca/ov519.c
4039
i2c_w(sd, OV7670_R32_HREF, v);
drivers/media/usb/gspca/ov519.c
4043
v = i2c_r(sd, OV7670_R03_VREF);
drivers/media/usb/gspca/ov519.c
4044
v = (v & 0xc0) | ((yend & 0x3) << 2) | (ystart & 0x03);
drivers/media/usb/gspca/ov519.c
4047
i2c_w(sd, OV7670_R03_VREF, v);
drivers/media/usb/gspca/pac7302.c
372
int i, v;
drivers/media/usb/gspca/pac7302.c
382
v = max[i];
drivers/media/usb/gspca/pac7302.c
383
v += (sd->brightness->val - (s32)sd->brightness->maximum)
drivers/media/usb/gspca/pac7302.c
385
v -= delta[i] * sd->contrast->val / (s32)sd->contrast->maximum;
drivers/media/usb/gspca/pac7302.c
386
if (v < 0)
drivers/media/usb/gspca/pac7302.c
387
v = 0;
drivers/media/usb/gspca/pac7302.c
388
else if (v > 0xff)
drivers/media/usb/gspca/pac7302.c
389
v = 0xff;
drivers/media/usb/gspca/pac7302.c
390
reg_w(gspca_dev, 0xa2 + i, v);
drivers/media/usb/gspca/pac7302.c
398
int i, v;
drivers/media/usb/gspca/pac7302.c
408
v = a[i] * sd->saturation->val / (s32)sd->saturation->maximum;
drivers/media/usb/gspca/pac7302.c
409
v += b[i];
drivers/media/usb/gspca/pac7302.c
410
reg_w(gspca_dev, 0x0f + 2 * i, (v >> 8) & 0x07);
drivers/media/usb/gspca/pac7302.c
411
reg_w(gspca_dev, 0x0f + 2 * i + 1, v);
drivers/media/usb/gspca/sonixj.c
1864
int i, v, colors;
drivers/media/usb/gspca/sonixj.c
1882
v = uv[i] * colors / COLORS_DEF;
drivers/media/usb/gspca/sonixj.c
1883
reg8a[i * 2] = v;
drivers/media/usb/gspca/sonixj.c
1884
reg8a[i * 2 + 1] = (v >> 8) & 0x0f;
drivers/media/usb/gspca/topro.c
1049
int v;
drivers/media/usb/gspca/topro.c
1055
v = gspca_dev->usb_buf[0];
drivers/media/usb/gspca/topro.c
1057
return v;
drivers/media/usb/gspca/topro.c
1060
v |= (gspca_dev->usb_buf[0] << 8);
drivers/media/usb/gspca/topro.c
1064
return v;
drivers/media/usb/gspca/vc032x.c
3384
u16 v;
drivers/media/usb/gspca/vc032x.c
3389
v = 613 + 12 * val;
drivers/media/usb/gspca/vc032x.c
3390
data = v >> 8;
drivers/media/usb/gspca/vc032x.c
3392
data = v;
drivers/media/usb/gspca/vc032x.c
3394
v = 1093 - 12 * val;
drivers/media/usb/gspca/vc032x.c
3395
data = v >> 8;
drivers/media/usb/gspca/vc032x.c
3397
data = v;
drivers/media/usb/gspca/vc032x.c
3399
v = 342 + 9 * val;
drivers/media/usb/gspca/vc032x.c
3400
data = v >> 8;
drivers/media/usb/gspca/vc032x.c
3402
data = v;
drivers/media/usb/gspca/vc032x.c
3404
v = 702 - 9 * val;
drivers/media/usb/gspca/vc032x.c
3405
data = v >> 8;
drivers/media/usb/gspca/vc032x.c
3407
data = v;
drivers/media/usb/gspca/w996Xcf.c
189
static void w9968cf_smbus_write_byte(struct sd *sd, u8 v)
drivers/media/usb/gspca/w996Xcf.c
195
sda = (v & 0x80) ? 2 : 0;
drivers/media/usb/gspca/w996Xcf.c
196
v <<= 1;
drivers/media/usb/gspca/w996Xcf.c
206
static void w9968cf_smbus_read_byte(struct sd *sd, u8 *v)
drivers/media/usb/gspca/w996Xcf.c
212
*v = 0;
drivers/media/usb/gspca/w996Xcf.c
214
*v <<= 1;
drivers/media/usb/gspca/w996Xcf.c
217
*v |= (w9968cf_read_sb(sd) & 0x0008) ? 1 : 0;
drivers/media/usb/hackrf/hackrf.c
1000
const struct v4l2_tuner *v)
drivers/media/usb/hackrf/hackrf.c
1005
dev_dbg(dev->dev, "index=%d\n", v->index);
drivers/media/usb/hackrf/hackrf.c
1007
if (v->index == 0)
drivers/media/usb/hackrf/hackrf.c
1009
else if (v->index == 1)
drivers/media/usb/hackrf/hackrf.c
1017
static int hackrf_g_tuner(struct file *file, void *priv, struct v4l2_tuner *v)
drivers/media/usb/hackrf/hackrf.c
1022
dev_dbg(dev->dev, "index=%d\n", v->index);
drivers/media/usb/hackrf/hackrf.c
1024
if (v->index == 0) {
drivers/media/usb/hackrf/hackrf.c
1025
strscpy(v->name, "HackRF ADC", sizeof(v->name));
drivers/media/usb/hackrf/hackrf.c
1026
v->type = V4L2_TUNER_SDR;
drivers/media/usb/hackrf/hackrf.c
1027
v->capability = V4L2_TUNER_CAP_1HZ | V4L2_TUNER_CAP_FREQ_BANDS;
drivers/media/usb/hackrf/hackrf.c
1028
v->rangelow = bands_adc_dac[0].rangelow;
drivers/media/usb/hackrf/hackrf.c
1029
v->rangehigh = bands_adc_dac[0].rangehigh;
drivers/media/usb/hackrf/hackrf.c
1031
} else if (v->index == 1) {
drivers/media/usb/hackrf/hackrf.c
1032
strscpy(v->name, "HackRF RF", sizeof(v->name));
drivers/media/usb/hackrf/hackrf.c
1033
v->type = V4L2_TUNER_RF;
drivers/media/usb/hackrf/hackrf.c
1034
v->capability = V4L2_TUNER_CAP_1HZ | V4L2_TUNER_CAP_FREQ_BANDS;
drivers/media/usb/hackrf/hackrf.c
1035
v->rangelow = bands_rx_tx[0].rangelow;
drivers/media/usb/hackrf/hackrf.c
1036
v->rangehigh = bands_rx_tx[0].rangehigh;
drivers/media/usb/hackrf/hackrf.c
1251
static void hackrf_video_release(struct v4l2_device *v)
drivers/media/usb/hackrf/hackrf.c
1253
struct hackrf_dev *dev = container_of(v, struct hackrf_dev, v4l2_dev);
drivers/media/usb/hackrf/hackrf.c
707
struct v4l2_device *v = usb_get_intfdata(intf);
drivers/media/usb/hackrf/hackrf.c
708
struct hackrf_dev *dev = container_of(v, struct hackrf_dev, v4l2_dev);
drivers/media/usb/msi2500/msi2500.c
1001
} else if (v->index == 1) {
drivers/media/usb/msi2500/msi2500.c
1002
ret = v4l2_subdev_call(dev->v4l2_subdev, tuner, g_tuner, v);
drivers/media/usb/msi2500/msi2500.c
1128
static void msi2500_video_release(struct v4l2_device *v)
drivers/media/usb/msi2500/msi2500.c
1130
struct msi2500_dev *dev = container_of(v, struct msi2500_dev, v4l2_dev);
drivers/media/usb/msi2500/msi2500.c
565
struct v4l2_device *v = usb_get_intfdata(intf);
drivers/media/usb/msi2500/msi2500.c
567
container_of(v, struct msi2500_dev, v4l2_dev);
drivers/media/usb/msi2500/msi2500.c
970
const struct v4l2_tuner *v)
drivers/media/usb/msi2500/msi2500.c
975
dev_dbg(dev->dev, "index=%d\n", v->index);
drivers/media/usb/msi2500/msi2500.c
977
if (v->index == 0)
drivers/media/usb/msi2500/msi2500.c
979
else if (v->index == 1)
drivers/media/usb/msi2500/msi2500.c
980
ret = v4l2_subdev_call(dev->v4l2_subdev, tuner, s_tuner, v);
drivers/media/usb/msi2500/msi2500.c
987
static int msi2500_g_tuner(struct file *file, void *priv, struct v4l2_tuner *v)
drivers/media/usb/msi2500/msi2500.c
992
dev_dbg(dev->dev, "index=%d\n", v->index);
drivers/media/usb/msi2500/msi2500.c
994
if (v->index == 0) {
drivers/media/usb/msi2500/msi2500.c
995
strscpy(v->name, "Mirics MSi2500", sizeof(v->name));
drivers/media/usb/msi2500/msi2500.c
996
v->type = V4L2_TUNER_ADC;
drivers/media/usb/msi2500/msi2500.c
997
v->capability = V4L2_TUNER_CAP_1HZ | V4L2_TUNER_CAP_FREQ_BANDS;
drivers/media/usb/msi2500/msi2500.c
998
v->rangelow = 1200000;
drivers/media/usb/msi2500/msi2500.c
999
v->rangehigh = 15000000;
drivers/media/usb/pvrusb2/pvrusb2-hdw.c
314
static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v);
drivers/media/usb/pvrusb2/pvrusb2-hdw.c
3528
enum pvr2_v4l_type index,int v)
drivers/media/usb/pvrusb2/pvrusb2-hdw.c
3531
case pvr2_v4l_type_video: hdw->v4l_minor_number_video = v;break;
drivers/media/usb/pvrusb2/pvrusb2-hdw.c
3532
case pvr2_v4l_type_vbi: hdw->v4l_minor_number_vbi = v;break;
drivers/media/usb/pvrusb2/pvrusb2-hdw.c
3533
case pvr2_v4l_type_radio: hdw->v4l_minor_number_radio = v;break;
drivers/media/usb/pvrusb2/pvrusb2-hdw.c
355
static int ctrl_channelfreq_set(struct pvr2_ctrl *cptr,int m,int v)
drivers/media/usb/pvrusb2/pvrusb2-hdw.c
360
hdw->freqTable[slotId-1] = v;
drivers/media/usb/pvrusb2/pvrusb2-hdw.c
383
static int ctrl_channelprog_set(struct pvr2_ctrl *cptr,int m,int v)
drivers/media/usb/pvrusb2/pvrusb2-hdw.c
386
if ((v >= 0) && (v <= FREQTABLE_SIZE)) {
drivers/media/usb/pvrusb2/pvrusb2-hdw.c
387
hdw->freqProgSlot = v;
drivers/media/usb/pvrusb2/pvrusb2-hdw.c
433
static int ctrl_freq_set(struct pvr2_ctrl *cptr,int m,int v)
drivers/media/usb/pvrusb2/pvrusb2-hdw.c
435
pvr2_hdw_set_cur_freq(cptr->hdw,v);
drivers/media/usb/pvrusb2/pvrusb2-hdw.c
5075
static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v)
drivers/media/usb/pvrusb2/pvrusb2-hdw.c
5077
if (hdw->input_val != v) {
drivers/media/usb/pvrusb2/pvrusb2-hdw.c
5078
hdw->input_val = v;
drivers/media/usb/pvrusb2/pvrusb2-hdw.c
659
static int ctrl_check_input(struct pvr2_ctrl *cptr,int v)
drivers/media/usb/pvrusb2/pvrusb2-hdw.c
661
if (v < 0 || v > PVR2_CVAL_INPUT_MAX)
drivers/media/usb/pvrusb2/pvrusb2-hdw.c
663
return ((1UL << v) & cptr->hdw->input_allowed_mask) != 0;
drivers/media/usb/pvrusb2/pvrusb2-hdw.c
666
static int ctrl_set_input(struct pvr2_ctrl *cptr,int m,int v)
drivers/media/usb/pvrusb2/pvrusb2-hdw.c
668
return pvr2_hdw_set_input(cptr->hdw,v);
drivers/media/usb/pvrusb2/pvrusb2-hdw.c
754
static int ctrl_cx2341x_set(struct pvr2_ctrl *cptr,int m,int v)
drivers/media/usb/pvrusb2/pvrusb2-hdw.c
765
c1.value = v;
drivers/media/usb/pvrusb2/pvrusb2-hdw.c
843
static int ctrl_stdavail_set(struct pvr2_ctrl *cptr,int m,int v)
drivers/media/usb/pvrusb2/pvrusb2-hdw.c
848
ns = (ns & ~m) | (v & m);
drivers/media/usb/pvrusb2/pvrusb2-hdw.c
881
static int ctrl_stdcur_set(struct pvr2_ctrl *cptr,int m,int v)
drivers/media/usb/pvrusb2/pvrusb2-hdw.c
886
ns = (ns & ~m) | (v & m);
drivers/media/usb/pvrusb2/pvrusb2-hdw.c
963
static int ctrl_set_##vname(struct pvr2_ctrl *cptr,int m,int v) \
drivers/media/usb/pvrusb2/pvrusb2-hdw.c
964
{cptr->hdw->vname##_val = v; cptr->hdw->vname##_dirty = !0; return 0;} \
drivers/media/usb/pwc/pwc-if.c
1172
struct v4l2_device *v = usb_get_intfdata(intf);
drivers/media/usb/pwc/pwc-if.c
1173
struct pwc_device *pdev = container_of(v, struct pwc_device, v4l2_dev);
drivers/media/usb/pwc/pwc-if.c
603
static void pwc_video_release(struct v4l2_device *v)
drivers/media/usb/pwc/pwc-if.c
605
struct pwc_device *pdev = container_of(v, struct pwc_device, v4l2_dev);
drivers/media/usb/uvc/uvc_v4l2.c
1120
struct uvc_xu_control_query32 v;
drivers/media/usb/uvc/uvc_v4l2.c
1122
if (copy_from_user(&v, up, sizeof(v)))
drivers/media/usb/uvc/uvc_v4l2.c
1126
.unit = v.unit,
drivers/media/usb/uvc/uvc_v4l2.c
1127
.selector = v.selector,
drivers/media/usb/uvc/uvc_v4l2.c
1128
.query = v.query,
drivers/media/usb/uvc/uvc_v4l2.c
1129
.size = v.size,
drivers/media/usb/uvc/uvc_v4l2.c
1130
.data = v.size ? compat_ptr(v.data) : NULL
drivers/media/v4l2-core/v4l2-fwnode.c
137
u32 v;
drivers/media/v4l2-core/v4l2-fwnode.c
211
if (!fwnode_property_read_u32(fwnode, "clock-lanes", &v)) {
drivers/media/v4l2-core/v4l2-fwnode.c
212
clock_lane = v;
drivers/media/v4l2-core/v4l2-fwnode.c
213
pr_debug("clock lane position %u\n", v);
drivers/media/v4l2-core/v4l2-fwnode.c
220
v);
drivers/media/v4l2-core/v4l2-fwnode.c
313
u32 v;
drivers/media/v4l2-core/v4l2-fwnode.c
318
if (!fwnode_property_read_u32(fwnode, "hsync-active", &v)) {
drivers/media/v4l2-core/v4l2-fwnode.c
321
flags |= v ? V4L2_MBUS_HSYNC_ACTIVE_HIGH :
drivers/media/v4l2-core/v4l2-fwnode.c
323
pr_debug("hsync-active %s\n", v ? "high" : "low");
drivers/media/v4l2-core/v4l2-fwnode.c
326
if (!fwnode_property_read_u32(fwnode, "vsync-active", &v)) {
drivers/media/v4l2-core/v4l2-fwnode.c
329
flags |= v ? V4L2_MBUS_VSYNC_ACTIVE_HIGH :
drivers/media/v4l2-core/v4l2-fwnode.c
331
pr_debug("vsync-active %s\n", v ? "high" : "low");
drivers/media/v4l2-core/v4l2-fwnode.c
334
if (!fwnode_property_read_u32(fwnode, "field-even-active", &v)) {
drivers/media/v4l2-core/v4l2-fwnode.c
337
flags |= v ? V4L2_MBUS_FIELD_EVEN_HIGH :
drivers/media/v4l2-core/v4l2-fwnode.c
339
pr_debug("field-even-active %s\n", v ? "high" : "low");
drivers/media/v4l2-core/v4l2-fwnode.c
342
if (!fwnode_property_read_u32(fwnode, "pclk-sample", &v)) {
drivers/media/v4l2-core/v4l2-fwnode.c
346
switch (v) {
drivers/media/v4l2-core/v4l2-fwnode.c
365
if (!fwnode_property_read_u32(fwnode, "data-active", &v)) {
drivers/media/v4l2-core/v4l2-fwnode.c
368
flags |= v ? V4L2_MBUS_DATA_ACTIVE_HIGH :
drivers/media/v4l2-core/v4l2-fwnode.c
370
pr_debug("data-active %s\n", v ? "high" : "low");
drivers/media/v4l2-core/v4l2-fwnode.c
382
if (!fwnode_property_read_u32(fwnode, "bus-width", &v)) {
drivers/media/v4l2-core/v4l2-fwnode.c
383
bus->bus_width = v;
drivers/media/v4l2-core/v4l2-fwnode.c
384
pr_debug("bus-width %u\n", v);
drivers/media/v4l2-core/v4l2-fwnode.c
387
if (!fwnode_property_read_u32(fwnode, "data-shift", &v)) {
drivers/media/v4l2-core/v4l2-fwnode.c
388
bus->data_shift = v;
drivers/media/v4l2-core/v4l2-fwnode.c
389
pr_debug("data-shift %u\n", v);
drivers/media/v4l2-core/v4l2-fwnode.c
392
if (!fwnode_property_read_u32(fwnode, "sync-on-green-active", &v)) {
drivers/media/v4l2-core/v4l2-fwnode.c
395
flags |= v ? V4L2_MBUS_VIDEO_SOG_ACTIVE_HIGH :
drivers/media/v4l2-core/v4l2-fwnode.c
397
pr_debug("sync-on-green-active %s\n", v ? "high" : "low");
drivers/media/v4l2-core/v4l2-fwnode.c
400
if (!fwnode_property_read_u32(fwnode, "data-enable-active", &v)) {
drivers/media/v4l2-core/v4l2-fwnode.c
403
flags |= v ? V4L2_MBUS_DATA_ENABLE_HIGH :
drivers/media/v4l2-core/v4l2-fwnode.c
405
pr_debug("data-enable-active %s\n", v ? "high" : "low");
drivers/media/v4l2-core/v4l2-fwnode.c
433
u32 v;
drivers/media/v4l2-core/v4l2-fwnode.c
435
if (!fwnode_property_read_u32(fwnode, "clock-inv", &v)) {
drivers/media/v4l2-core/v4l2-fwnode.c
436
bus->clock_inv = v;
drivers/media/v4l2-core/v4l2-fwnode.c
437
pr_debug("clock-inv %u\n", v);
drivers/media/v4l2-core/v4l2-fwnode.c
440
if (!fwnode_property_read_u32(fwnode, "strobe", &v)) {
drivers/media/v4l2-core/v4l2-fwnode.c
441
bus->strobe = v;
drivers/media/v4l2-core/v4l2-fwnode.c
442
pr_debug("strobe %u\n", v);
drivers/media/v4l2-core/v4l2-fwnode.c
445
if (!fwnode_property_read_u32(fwnode, "data-lanes", &v)) {
drivers/media/v4l2-core/v4l2-fwnode.c
446
bus->data_lane = v;
drivers/media/v4l2-core/v4l2-fwnode.c
447
pr_debug("data-lanes %u\n", v);
drivers/media/v4l2-core/v4l2-fwnode.c
450
if (!fwnode_property_read_u32(fwnode, "clock-lanes", &v)) {
drivers/media/v4l2-core/v4l2-fwnode.c
451
bus->clock_lane = v;
drivers/media/v4l2-core/v4l2-fwnode.c
452
pr_debug("clock-lanes %u\n", v);
drivers/media/v4l2-core/v4l2-vp9.c
1158
static int inv_recenter_nonneg(int v, int m)
drivers/media/v4l2-core/v4l2-vp9.c
1160
if (v > 2 * m)
drivers/media/v4l2-core/v4l2-vp9.c
1161
return v;
drivers/media/v4l2-core/v4l2-vp9.c
1163
if (v & 1)
drivers/media/v4l2-core/v4l2-vp9.c
1164
return m - ((v + 1) >> 1);
drivers/media/v4l2-core/v4l2-vp9.c
1166
return m + (v >> 1);
drivers/memory/omap-gpmc.c
2497
unsigned long cmd, void *v)
drivers/memory/renesas-rpc-if-regs.h
103
#define RPCIF_DMDMCR_DMCYC(v) ((((v) - 1) & 0x1F) << 0)
drivers/memory/renesas-rpc-if-regs.h
106
#define RPCIF_DRDRENR_HYPE(v) (((v) & 0x7) << 12)
drivers/memory/renesas-rpc-if-regs.h
112
#define RPCIF_SMDMCR_DMCYC(v) ((((v) - 1) & 0x1F) << 0)
drivers/memory/renesas-rpc-if-regs.h
115
#define RPCIF_SMDRENR_HYPE(v) (((v) & 0x7) << 12)
drivers/memory/renesas-rpc-if-regs.h
125
#define RPCIF_PHYCNT_OCTA(v) (((v) & 0x3) << 22)
drivers/memory/renesas-rpc-if-regs.h
130
#define RPCIF_PHYCNT_CKSEL(v) (((v) & 0x3) << 16) /* valid only for RZ/G2L */
drivers/memory/renesas-rpc-if-regs.h
131
#define RPCIF_PHYCNT_STRTIM(v) (((v) & 0x7) << 15 | ((v) & 0x8) << 24) /* valid for R-Car and RZ/G2{E,H,M,N} */
drivers/memory/renesas-rpc-if-regs.h
135
#define RPCIF_PHYCNT_PHYMEM(v) (((v) & 0x3) << 0)
drivers/memory/renesas-rpc-if-regs.h
139
#define RPCIF_PHYOFFSET1_DDRTMG(v) (((v) & 0x3) << 28)
drivers/memory/renesas-rpc-if-regs.h
142
#define RPCIF_PHYOFFSET2_OCTTMG(v) (((v) & 0x7) << 8)
drivers/memory/renesas-rpc-if-regs.h
35
#define RPCIF_DRCR_RBURST(v) ((((v) - 1) & 0x1F) << 16)
drivers/memory/renesas-rpc-if-regs.h
59
#define RPCIF_DRENR_ADE(v) (((v) & 0xF) << 8)
drivers/memory/renesas-rpc-if-regs.h
60
#define RPCIF_DRENR_OPDE(v) (((v) & 0xF) << 4)
drivers/memory/renesas-rpc-if-regs.h
89
#define RPCIF_SMENR_ADE(v) (((v) & 0xF) << 8)
drivers/memory/renesas-rpc-if-regs.h
90
#define RPCIF_SMENR_OPDE(v) (((v) & 0xF) << 4)
drivers/memory/renesas-rpc-if-regs.h
91
#define RPCIF_SMENR_SPIDE(v) (((v) & 0xF) << 0)
drivers/memory/tegra/tegra20-emc.c
302
u32 v;
drivers/memory/tegra/tegra20-emc.c
313
err = readl_relaxed_poll_timeout_atomic(emc->regs + EMC_INTSTATUS, v,
drivers/memory/tegra/tegra20-emc.c
314
v & EMC_CLKCHANGE_COMPLETE_INT,
drivers/memory/tegra/tegra30-emc.c
798
u32 v;
drivers/memory/tegra/tegra30-emc.c
800
err = readl_relaxed_poll_timeout_atomic(emc->regs + EMC_INTSTATUS, v,
drivers/memory/tegra/tegra30-emc.c
801
v & EMC_CLKCHANGE_COMPLETE_INT,
drivers/message/fusion/mptbase.c
200
static int mpt_summary_proc_show(struct seq_file *m, void *v);
drivers/message/fusion/mptbase.c
201
static int mpt_version_proc_show(struct seq_file *m, void *v);
drivers/message/fusion/mptbase.c
202
static int mpt_iocinfo_proc_show(struct seq_file *m, void *v);
drivers/message/fusion/mptbase.c
6641
static int mpt_summary_proc_show(struct seq_file *m, void *v)
drivers/message/fusion/mptbase.c
6656
static int mpt_version_proc_show(struct seq_file *m, void *v)
drivers/message/fusion/mptbase.c
6698
static int mpt_iocinfo_proc_show(struct seq_file *m, void *v)
drivers/mfd/da903x.c
265
uint8_t v[3];
drivers/mfd/da903x.c
269
v[0] = (chip->events_mask & 0xff);
drivers/mfd/da903x.c
270
v[1] = (chip->events_mask >> 8) & 0xff;
drivers/mfd/da903x.c
271
v[2] = (chip->events_mask >> 16) & 0xff;
drivers/mfd/da903x.c
273
return __da903x_writes(chip->client, DA9030_IRQ_MASK_A, 3, v);
drivers/mfd/da903x.c
278
uint8_t v[3];
drivers/mfd/da903x.c
282
v[0] = (chip->events_mask & 0xff);
drivers/mfd/da903x.c
283
v[1] = (chip->events_mask >> 8) & 0xff;
drivers/mfd/da903x.c
284
v[2] = (chip->events_mask >> 16) & 0xff;
drivers/mfd/da903x.c
286
return __da903x_writes(chip->client, DA9030_IRQ_MASK_A, 3, v);
drivers/mfd/da903x.c
291
uint8_t v[3] = {0, 0, 0};
drivers/mfd/da903x.c
294
ret = __da903x_reads(chip->client, DA9030_EVENT_A, 3, v);
drivers/mfd/da903x.c
298
*events = (v[2] << 16) | (v[1] << 8) | v[0];
drivers/mfd/da903x.c
342
uint8_t v[4];
drivers/mfd/da903x.c
346
v[0] = (chip->events_mask & 0xff);
drivers/mfd/da903x.c
347
v[1] = (chip->events_mask >> 8) & 0xff;
drivers/mfd/da903x.c
348
v[2] = (chip->events_mask >> 16) & 0xff;
drivers/mfd/da903x.c
349
v[3] = (chip->events_mask >> 24) & 0xff;
drivers/mfd/da903x.c
351
return __da903x_writes(chip->client, DA9034_IRQ_MASK_A, 4, v);
drivers/mfd/da903x.c
356
uint8_t v[4];
drivers/mfd/da903x.c
360
v[0] = (chip->events_mask & 0xff);
drivers/mfd/da903x.c
361
v[1] = (chip->events_mask >> 8) & 0xff;
drivers/mfd/da903x.c
362
v[2] = (chip->events_mask >> 16) & 0xff;
drivers/mfd/da903x.c
363
v[3] = (chip->events_mask >> 24) & 0xff;
drivers/mfd/da903x.c
365
return __da903x_writes(chip->client, DA9034_IRQ_MASK_A, 4, v);
drivers/mfd/da903x.c
370
uint8_t v[4] = {0, 0, 0, 0};
drivers/mfd/da903x.c
373
ret = __da903x_reads(chip->client, DA9034_EVENT_A, 4, v);
drivers/mfd/da903x.c
377
*events = (v[3] << 24) | (v[2] << 16) | (v[1] << 8) | v[0];
drivers/mfd/da903x.c
383
uint8_t v[2] = {0, 0};
drivers/mfd/da903x.c
386
ret = __da903x_reads(chip->client, DA9034_STATUS_A, 2, v);
drivers/mfd/da903x.c
390
*status = (v[1] << 8) | v[0];
drivers/mfd/intel-m10-bmc-spi.c
38
unsigned int v;
drivers/mfd/intel-m10-bmc-spi.c
49
ret = m10bmc_raw_read(ddata, M10BMC_N3000_LEGACY_BUILD_VER, &v);
drivers/mfd/intel-m10-bmc-spi.c
53
if (v != M10BMC_N3000_VER_LEGACY_INVALID) {
drivers/misc/bcm-vk/bcm_vk_tty.c
32
#define VK_BAR_CHAN(v, DIR, e) ((v)->DIR##_offset \
drivers/misc/bcm-vk/bcm_vk_tty.c
34
#define VK_BAR_CHAN_SIZE(v, DIR) VK_BAR_CHAN(v, DIR, size)
drivers/misc/bcm-vk/bcm_vk_tty.c
35
#define VK_BAR_CHAN_WR(v, DIR) VK_BAR_CHAN(v, DIR, wr)
drivers/misc/bcm-vk/bcm_vk_tty.c
36
#define VK_BAR_CHAN_RD(v, DIR) VK_BAR_CHAN(v, DIR, rd)
drivers/misc/bcm-vk/bcm_vk_tty.c
37
#define VK_BAR_CHAN_DATA(v, DIR, off) (VK_BAR_CHAN(v, DIR, data) + (off))
drivers/misc/c2port/c2port-duramar2150.c
31
u8 v;
drivers/misc/c2port/c2port-duramar2150.c
35
v = inb(DIR_PORT);
drivers/misc/c2port/c2port-duramar2150.c
39
outb(v | (C2D | C2CK), DIR_PORT);
drivers/misc/c2port/c2port-duramar2150.c
43
outb(v & ~(C2D | C2CK), DIR_PORT);
drivers/misc/c2port/c2port-duramar2150.c
50
u8 v;
drivers/misc/c2port/c2port-duramar2150.c
54
v = inb(DIR_PORT);
drivers/misc/c2port/c2port-duramar2150.c
57
outb(v & ~C2D, DIR_PORT);
drivers/misc/c2port/c2port-duramar2150.c
59
outb(v | C2D, DIR_PORT);
drivers/misc/c2port/c2port-duramar2150.c
71
u8 v;
drivers/misc/c2port/c2port-duramar2150.c
75
v = inb(DATA_PORT);
drivers/misc/c2port/c2port-duramar2150.c
78
outb(v | C2D, DATA_PORT);
drivers/misc/c2port/c2port-duramar2150.c
80
outb(v & ~C2D, DATA_PORT);
drivers/misc/c2port/c2port-duramar2150.c
87
u8 v;
drivers/misc/c2port/c2port-duramar2150.c
91
v = inb(DATA_PORT);
drivers/misc/c2port/c2port-duramar2150.c
94
outb(v | C2CK, DATA_PORT);
drivers/misc/c2port/c2port-duramar2150.c
96
outb(v & ~C2CK, DATA_PORT);
drivers/misc/ibmasm/heartbeat.c
32
static int panic_happened(struct notifier_block *n, unsigned long val, void *v)
drivers/misc/isl29003.c
356
int v = i2c_smbus_read_byte_data(client, i);
drivers/misc/isl29003.c
358
if (v < 0)
drivers/misc/isl29003.c
361
data->reg_cache[i] = v;
drivers/misc/lis3lv02d/lis3lv02d.c
139
int v;
drivers/misc/lis3lv02d/lis3lv02d.c
143
v = (int) ((hi << 8) | lo);
drivers/misc/lis3lv02d/lis3lv02d.c
145
return (s16) v >> lis3->shift_adj;
drivers/misc/lis3lv02d/lis3lv02d_i2c.c
52
static inline s32 lis3_i2c_read(struct lis3lv02d *lis3, int reg, u8 *v)
drivers/misc/lis3lv02d/lis3lv02d_i2c.c
55
*v = i2c_smbus_read_byte_data(c, reg);
drivers/misc/lis3lv02d/lis3lv02d_i2c.c
60
u8 *v)
drivers/misc/lis3lv02d/lis3lv02d_i2c.c
64
return i2c_smbus_read_i2c_block_data(c, reg, len, v);
drivers/misc/lis3lv02d/lis3lv02d_spi.c
25
static int lis3_spi_read(struct lis3lv02d *lis3, int reg, u8 *v)
drivers/misc/lis3lv02d/lis3lv02d_spi.c
32
*v = (u8) ret;
drivers/misc/lkdtm/bugs.c
100
atomic_t v = ATOMIC_INIT(0);
drivers/misc/lkdtm/bugs.c
101
stop_machine(panic_stop_irqoff_fn, &v, cpu_online_mask);
drivers/misc/lkdtm/bugs.c
81
atomic_t *v = arg;
drivers/misc/lkdtm/bugs.c
91
if (atomic_inc_return(v) == num_online_cpus())
drivers/misc/mei/hdcp/mei_hdcp.c
531
memcpy(rep_send_ack->v, verify_repeater_out.v,
drivers/misc/sgi-gru/gru_instructions.h
35
#define gru_ordered_store_ulong(p, v) \
drivers/misc/sgi-gru/gru_instructions.h
38
*(unsigned long *)p = v; \
drivers/misc/sgi-gru/gruprocfs.c
22
static void printstat_val(struct seq_file *s, atomic_long_t *v, char *id)
drivers/misc/sgi-gru/gruprocfs.c
24
unsigned long val = atomic_long_read(v);
drivers/misc/sgi-gru/grutables.h
385
#define TSID(a, v) (((a) - (v)->vm_start) / GRU_GSEG_PAGESIZE)
drivers/mmc/core/sdio_uart.c
944
static int sdio_uart_proc_show(struct seq_file *m, void *v)
drivers/mmc/host/atmel-mci.c
434
static int atmci_req_show(struct seq_file *s, void *v)
drivers/mmc/host/atmel-mci.c
522
static int atmci_regs_show(struct seq_file *s, void *v)
drivers/mmc/host/dw_mmc-k3.c
325
unsigned int v;
drivers/mmc/host/dw_mmc-k3.c
345
v = ror32(sample_flag, i);
drivers/mmc/host/dw_mmc-k3.c
346
len = ffs(~v) - 1;
drivers/mmc/host/dw_mmc-k3.c
353
interval = ffs(v >> len) - 1;
drivers/mmc/host/dw_mmc-rockchip.c
294
bool v, prev_v = 0, first_v;
drivers/mmc/host/dw_mmc-rockchip.c
322
v = !mmc_send_tuning(mmc, opcode, NULL);
drivers/mmc/host/dw_mmc-rockchip.c
325
first_v = v;
drivers/mmc/host/dw_mmc-rockchip.c
327
if ((!prev_v) && v) {
drivers/mmc/host/dw_mmc-rockchip.c
331
if (v) {
drivers/mmc/host/dw_mmc-rockchip.c
350
prev_v = v;
drivers/mmc/host/dw_mmc-rockchip.c
360
if ((range_count > 1) && first_v && v) {
drivers/mmc/host/dw_mmc.c
108
static int dw_mci_req_show(struct seq_file *s, void *v)
drivers/mmc/host/dw_mmc.c
149
static int dw_mci_regs_show(struct seq_file *s, void *v)
drivers/mmc/host/dw_mmc.h
353
#define _SBF(f, v) ((v) << (f))
drivers/mmc/host/dw_mmc.h
452
#define SDMMC_SET_THLD(v, x) (((v) & 0xFFF) << 16 | (x))
drivers/mmc/host/pxamci.c
120
unsigned int v;
drivers/mmc/host/pxamci.c
125
v = readl(host->base + MMC_STAT);
drivers/mmc/host/pxamci.c
126
if (!(v & STAT_CLK_EN))
drivers/mmc/host/pxamci.c
131
if (v & STAT_CLK_EN)
drivers/mmc/host/pxamci.c
278
u32 v;
drivers/mmc/host/pxamci.c
289
v = readl(host->base + MMC_RES) & 0xffff;
drivers/mmc/host/pxamci.c
293
cmd->resp[i] = v << 24 | w1 << 8 | w2 >> 8;
drivers/mmc/host/pxamci.c
294
v = w2;
drivers/mmc/host/sdhci-acpi.c
896
bool v = sdhci_acpi_flag(c, SDHCI_ACPI_SD_CD_OVERRIDE_LEVEL);
drivers/mmc/host/sdhci-acpi.c
901
err = mmc_gpiod_request_cd(host->mmc, NULL, 0, v, 0);
drivers/mmc/host/sdhci-esdhc-imx.c
1355
u32 v;
drivers/mmc/host/sdhci-esdhc-imx.c
1378
v = ESDHC_STROBE_DLL_CTRL_ENABLE |
drivers/mmc/host/sdhci-esdhc-imx.c
1381
writel(v, host->ioaddr + ESDHC_STROBE_DLL_CTRL);
drivers/mmc/host/sdhci-esdhc-imx.c
1384
ret = readl_poll_timeout(host->ioaddr + ESDHC_STROBE_DLL_STATUS, v,
drivers/mmc/host/sdhci-esdhc-imx.c
1385
((v & ESDHC_STROBE_DLL_STS_REF_LOCK) && (v & ESDHC_STROBE_DLL_STS_SLV_LOCK)), 1, 50);
drivers/mmc/host/sdhci-esdhc-imx.c
1388
"warning! HS400 strobe DLL status REF/SLV not lock in 50us, STROBE DLL status is %x!\n", v);
drivers/mmc/host/sdhci-esdhc-imx.c
1418
u32 v;
drivers/mmc/host/sdhci-esdhc-imx.c
1419
v = boarddata->delay_line <<
drivers/mmc/host/sdhci-esdhc-imx.c
1423
v <<= 1;
drivers/mmc/host/sdhci-esdhc-imx.c
1424
writel(v, host->ioaddr + ESDHC_DLL_CTRL);
drivers/mmc/host/sdhci-esdhc-imx.c
641
u32 v;
drivers/mmc/host/sdhci-esdhc-imx.c
642
v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
drivers/mmc/host/sdhci-esdhc-imx.c
643
v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK;
drivers/mmc/host/sdhci-esdhc-imx.c
644
writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
drivers/mmc/host/sdhci-esdhc-imx.c
744
u32 v = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS);
drivers/mmc/host/sdhci-esdhc-imx.c
746
v |= ESDHC_MIX_CTRL_SMPCLK_SEL;
drivers/mmc/host/sdhci-esdhc-imx.c
748
v &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
drivers/mmc/host/sdhci-esdhc-imx.c
751
v |= ESDHC_MIX_CTRL_EXE_TUNE;
drivers/mmc/host/sdhci-esdhc-imx.c
753
v &= ~ESDHC_MIX_CTRL_EXE_TUNE;
drivers/mmc/host/sdhci-esdhc-imx.c
755
writel(v, host->ioaddr + SDHCI_AUTO_CMD_STATUS);
drivers/mmc/host/sdhci-esdhc-imx.c
763
u32 v;
drivers/mmc/host/sdhci-esdhc-imx.c
764
v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
drivers/mmc/host/sdhci-esdhc-imx.c
765
v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK;
drivers/mmc/host/sdhci-esdhc-imx.c
766
writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
drivers/mmc/host/sdhci.c
4140
u16 v;
drivers/mmc/host/sdhci.c
4165
v = ver ? *ver : sdhci_readw(host, SDHCI_HOST_VERSION);
drivers/mmc/host/sdhci.c
4166
host->version = (v & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
drivers/mtd/chips/cfi_cmdset_0001.c
2673
void *v)
drivers/mtd/chips/cfi_cmdset_0002.c
3084
void *v)
drivers/mtd/devices/pmc551.c
118
#define PMC551_DRAM_BLK_SET_COL_MUX(x, v) (((x) & ~0x00007000) | (((v) & 0x7) << 12))
drivers/mtd/devices/pmc551.c
119
#define PMC551_DRAM_BLK_SET_ROW_MUX(x, v) (((x) & ~0x00000f00) | (((v) & 0xf) << 8))
drivers/mtd/maps/nettel.c
143
static int nettel_reboot_notifier(struct notifier_block *nb, unsigned long val, void *v)
drivers/mtd/mtdcore.c
2541
static int mtd_proc_show(struct seq_file *m, void *v)
drivers/mtd/nand/raw/gpmi-nand/bch-regs.h
108
#define BF_BCH_FLASH0LAYOUT1_DATAN_SIZE(v, x) \
drivers/mtd/nand/raw/gpmi-nand/bch-regs.h
110
? (((v) >> 2) & MX6Q_BM_BCH_FLASH0LAYOUT1_DATAN_SIZE) \
drivers/mtd/nand/raw/gpmi-nand/bch-regs.h
111
: ((v) & BM_BCH_FLASH0LAYOUT1_DATAN_SIZE) \
drivers/mtd/nand/raw/gpmi-nand/bch-regs.h
30
#define BF_BCH_FLASH0LAYOUT0_NBLOCKS(v) \
drivers/mtd/nand/raw/gpmi-nand/bch-regs.h
31
(((v) << BP_BCH_FLASH0LAYOUT0_NBLOCKS) & BM_BCH_FLASH0LAYOUT0_NBLOCKS)
drivers/mtd/nand/raw/gpmi-nand/bch-regs.h
35
#define BF_BCH_FLASH0LAYOUT0_META_SIZE(v) \
drivers/mtd/nand/raw/gpmi-nand/bch-regs.h
36
(((v) << BP_BCH_FLASH0LAYOUT0_META_SIZE)\
drivers/mtd/nand/raw/gpmi-nand/bch-regs.h
43
#define BF_BCH_FLASH0LAYOUT0_ECC0(v, x) \
drivers/mtd/nand/raw/gpmi-nand/bch-regs.h
45
? (((v) << MX6Q_BP_BCH_FLASH0LAYOUT0_ECC0) \
drivers/mtd/nand/raw/gpmi-nand/bch-regs.h
47
: (((v) << BP_BCH_FLASH0LAYOUT0_ECC0) \
drivers/mtd/nand/raw/gpmi-nand/bch-regs.h
54
#define BF_BCH_FLASH0LAYOUT0_GF(v, x) \
drivers/mtd/nand/raw/gpmi-nand/bch-regs.h
55
((GPMI_IS_MX6(x) && ((v) == 14)) \
drivers/mtd/nand/raw/gpmi-nand/bch-regs.h
66
#define BF_BCH_FLASH0LAYOUT0_DATA0_SIZE(v, x) \
drivers/mtd/nand/raw/gpmi-nand/bch-regs.h
68
? (((v) >> 2) & MX6Q_BM_BCH_FLASH0LAYOUT0_DATA0_SIZE) \
drivers/mtd/nand/raw/gpmi-nand/bch-regs.h
69
: ((v) & BM_BCH_FLASH0LAYOUT0_DATA0_SIZE) \
drivers/mtd/nand/raw/gpmi-nand/bch-regs.h
77
#define BF_BCH_FLASH0LAYOUT1_PAGE_SIZE(v) \
drivers/mtd/nand/raw/gpmi-nand/bch-regs.h
78
(((v) << BP_BCH_FLASH0LAYOUT1_PAGE_SIZE) \
drivers/mtd/nand/raw/gpmi-nand/bch-regs.h
85
#define BF_BCH_FLASH0LAYOUT1_ECCN(v, x) \
drivers/mtd/nand/raw/gpmi-nand/bch-regs.h
87
? (((v) << MX6Q_BP_BCH_FLASH0LAYOUT1_ECCN) \
drivers/mtd/nand/raw/gpmi-nand/bch-regs.h
89
: (((v) << BP_BCH_FLASH0LAYOUT1_ECCN) \
drivers/mtd/nand/raw/gpmi-nand/bch-regs.h
96
#define BF_BCH_FLASH0LAYOUT1_GF(v, x) \
drivers/mtd/nand/raw/gpmi-nand/bch-regs.h
97
((GPMI_IS_MX6(x) && ((v) == 14)) \
drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c
121
static int __gpmi_enable_clk(struct gpmi_nand_data *this, bool v)
drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c
132
if (v) {
drivers/mtd/nand/raw/gpmi-nand/gpmi-regs.h
103
#define BF_GPMI_CTRL1_WRN_DLY_SEL(v) \
drivers/mtd/nand/raw/gpmi-nand/gpmi-regs.h
104
(((v) << BP_GPMI_CTRL1_WRN_DLY_SEL) & BM_GPMI_CTRL1_WRN_DLY_SEL)
drivers/mtd/nand/raw/gpmi-nand/gpmi-regs.h
121
#define BF_GPMI_CTRL1_RDN_DELAY(v) \
drivers/mtd/nand/raw/gpmi-nand/gpmi-regs.h
122
(((v) << BP_GPMI_CTRL1_RDN_DELAY) & BM_GPMI_CTRL1_RDN_DELAY)
drivers/mtd/nand/raw/gpmi-nand/gpmi-regs.h
147
#define BF_GPMI_TIMING0_ADDRESS_SETUP(v) \
drivers/mtd/nand/raw/gpmi-nand/gpmi-regs.h
148
(((v) << BP_GPMI_TIMING0_ADDRESS_SETUP) & BM_GPMI_TIMING0_ADDRESS_SETUP)
drivers/mtd/nand/raw/gpmi-nand/gpmi-regs.h
152
#define BF_GPMI_TIMING0_DATA_HOLD(v) \
drivers/mtd/nand/raw/gpmi-nand/gpmi-regs.h
153
(((v) << BP_GPMI_TIMING0_DATA_HOLD) & BM_GPMI_TIMING0_DATA_HOLD)
drivers/mtd/nand/raw/gpmi-nand/gpmi-regs.h
157
#define BF_GPMI_TIMING0_DATA_SETUP(v) \
drivers/mtd/nand/raw/gpmi-nand/gpmi-regs.h
158
(((v) << BP_GPMI_TIMING0_DATA_SETUP) & BM_GPMI_TIMING0_DATA_SETUP)
drivers/mtd/nand/raw/gpmi-nand/gpmi-regs.h
163
#define BF_GPMI_TIMING1_BUSY_TIMEOUT(v) \
drivers/mtd/nand/raw/gpmi-nand/gpmi-regs.h
164
(((v) << BP_GPMI_TIMING1_BUSY_TIMEOUT) & BM_GPMI_TIMING1_BUSY_TIMEOUT)
drivers/mtd/nand/raw/gpmi-nand/gpmi-regs.h
173
#define MX28_BF_GPMI_STAT_READY_BUSY(v) \
drivers/mtd/nand/raw/gpmi-nand/gpmi-regs.h
174
(((v) << MX28_BP_GPMI_STAT_READY_BUSY) & MX28_BM_GPMI_STAT_READY_BUSY)
drivers/mtd/nand/raw/gpmi-nand/gpmi-regs.h
18
#define BF_GPMI_CTRL0_COMMAND_MODE(v) \
drivers/mtd/nand/raw/gpmi-nand/gpmi-regs.h
19
(((v) << BP_GPMI_CTRL0_COMMAND_MODE) & BM_GPMI_CTRL0_COMMAND_MODE)
drivers/mtd/nand/raw/gpmi-nand/gpmi-regs.h
37
#define BF_GPMI_CTRL0_LOCK_CS(v, x) 0x0
drivers/mtd/nand/raw/gpmi-nand/gpmi-regs.h
43
#define BF_GPMI_CTRL0_CS(v, x) (((v) << BP_GPMI_CTRL0_CS) & \
drivers/mtd/nand/raw/gpmi-nand/gpmi-regs.h
50
#define BF_GPMI_CTRL0_ADDRESS(v) \
drivers/mtd/nand/raw/gpmi-nand/gpmi-regs.h
51
(((v) << BP_GPMI_CTRL0_ADDRESS) & BM_GPMI_CTRL0_ADDRESS)
drivers/mtd/nand/raw/gpmi-nand/gpmi-regs.h
62
#define BF_GPMI_CTRL0_XFER_COUNT(v) \
drivers/mtd/nand/raw/gpmi-nand/gpmi-regs.h
63
(((v) << BP_GPMI_CTRL0_XFER_COUNT) & BM_GPMI_CTRL0_XFER_COUNT)
drivers/mtd/nand/raw/gpmi-nand/gpmi-regs.h
74
#define BF_GPMI_ECCCTRL_ECC_CMD(v) \
drivers/mtd/nand/raw/gpmi-nand/gpmi-regs.h
75
(((v) << BP_GPMI_ECCCTRL_ECC_CMD) & BM_GPMI_ECCCTRL_ECC_CMD)
drivers/mtd/nand/raw/gpmi-nand/gpmi-regs.h
85
#define BF_GPMI_ECCCTRL_BUFFER_MASK(v) \
drivers/mtd/nand/raw/gpmi-nand/gpmi-regs.h
86
(((v) << BP_GPMI_ECCCTRL_BUFFER_MASK) & BM_GPMI_ECCCTRL_BUFFER_MASK)
drivers/mtd/nand/raw/mpc5121_nfc.c
295
u8 v;
drivers/mtd/nand/raw/mpc5121_nfc.c
297
v = in_8(prv->csreg);
drivers/mtd/nand/raw/mpc5121_nfc.c
298
v |= 0x0F;
drivers/mtd/nand/raw/mpc5121_nfc.c
302
v &= ~(1 << chip);
drivers/mtd/nand/raw/mpc5121_nfc.c
306
out_8(prv->csreg, v);
drivers/mtd/nand/raw/mxic_nand.c
158
#define IDLY_CODE_VAL(x, v) ((v) << (((x) % 4) * 8))
drivers/mtd/tests/nandbiterrs.c
175
#define CBIT(v, n) ((v) & (1 << (n)))
drivers/mtd/tests/nandbiterrs.c
176
#define BCLR(v, n) ((v) = (v) & ~(1 << (n)))
drivers/mtd/tests/nandbiterrs.c
75
unsigned v = offset;
drivers/mtd/tests/nandbiterrs.c
77
v ^= 0x7f7edfd3;
drivers/mtd/tests/nandbiterrs.c
78
v = v ^ (v >> 3);
drivers/mtd/tests/nandbiterrs.c
79
v = v ^ (v >> 5);
drivers/mtd/tests/nandbiterrs.c
80
v = v ^ (v >> 13);
drivers/mtd/tests/nandbiterrs.c
81
c = v & 0xFF;
drivers/mtd/ubi/debug.c
492
static void *eraseblk_count_seq_next(struct seq_file *s, void *v, loff_t *pos)
drivers/mtd/ubi/debug.c
504
static void eraseblk_count_seq_stop(struct seq_file *s, void *v)
drivers/mtd/ubi/debug.h
214
#define ubi_dbg_fail_ff_bitflips(u, v) false
drivers/net/bonding/bond_debugfs.c
18
static int bond_debug_rlb_hash_show(struct seq_file *m, void *v)
drivers/net/bonding/bond_procfs.c
265
static int bond_info_seq_show(struct seq_file *seq, void *v)
drivers/net/bonding/bond_procfs.c
267
if (v == SEQ_START_TOKEN) {
drivers/net/bonding/bond_procfs.c
271
bond_info_show_slave(seq, v);
drivers/net/bonding/bond_procfs.c
31
static void *bond_info_seq_next(struct seq_file *seq, void *v, loff_t *pos)
drivers/net/bonding/bond_procfs.c
39
if (v == SEQ_START_TOKEN)
drivers/net/bonding/bond_procfs.c
45
if (slave == v)
drivers/net/bonding/bond_procfs.c
52
static void bond_info_seq_stop(struct seq_file *seq, void *v)
drivers/net/can/esd/esdacc.h
274
unsigned short offs, u32 v)
drivers/net/can/esd/esdacc.h
276
iowrite32be(v, core->addr + offs);
drivers/net/can/esd/esdacc.h
280
unsigned short offs, u32 v)
drivers/net/can/esd/esdacc.h
282
iowrite32(v, core->addr + offs);
drivers/net/can/esd/esdacc.h
288
u32 v = acc_read32(core, offs);
drivers/net/can/esd/esdacc.h
290
v |= mask;
drivers/net/can/esd/esdacc.h
291
acc_write32(core, offs, v);
drivers/net/can/esd/esdacc.h
297
u32 v = acc_read32(core, offs);
drivers/net/can/esd/esdacc.h
299
v &= ~mask;
drivers/net/can/esd/esdacc.h
300
acc_write32(core, offs, v);
drivers/net/can/esd/esdacc.h
316
unsigned short offs, u32 v)
drivers/net/can/esd/esdacc.h
318
iowrite32be(v, ov->addr + offs);
drivers/net/can/esd/esdacc.h
324
u32 v = acc_ov_read32(ov, offs);
drivers/net/can/esd/esdacc.h
326
v |= b;
drivers/net/can/esd/esdacc.h
327
acc_ov_write32(ov, offs, v);
drivers/net/can/esd/esdacc.h
333
u32 v = acc_ov_read32(ov, offs);
drivers/net/can/esd/esdacc.h
335
v &= ~b;
drivers/net/can/esd/esdacc.h
336
acc_ov_write32(ov, offs, v);
drivers/net/can/sja1000/peak_pcmcia.c
184
static void pcan_write_canreg(const struct sja1000_priv *priv, int port, u8 v)
drivers/net/can/sja1000/peak_pcmcia.c
191
switch (v) {
drivers/net/can/sja1000/peak_pcmcia.c
205
iowrite8(v, priv->reg_base + port);
drivers/net/can/sja1000/peak_pcmcia.c
219
static void pcan_write_reg(struct pcan_pccard *card, int port, u8 v)
drivers/net/can/sja1000/peak_pcmcia.c
223
if (card->ccr == v)
drivers/net/can/sja1000/peak_pcmcia.c
225
card->ccr = v;
drivers/net/can/sja1000/peak_pcmcia.c
228
iowrite8(v, card->ioport_addr + PCC_COMN_OFF + port);
drivers/net/can/sja1000/peak_pcmcia.c
262
static int pcan_write_eeprom(struct pcan_pccard *card, u16 addr, u8 v)
drivers/net/can/sja1000/peak_pcmcia.c
295
pcan_write_reg(card, PCC_SPI_DOR, v);
drivers/net/can/softing/softing_cs.c
165
static int softingcs_reset(struct platform_device *pdev, int v)
drivers/net/can/softing/softing_cs.c
169
dev_dbg(&pdev->dev, "pcmcia config [2] %02x\n", v ? 0 : 0x20);
drivers/net/can/softing/softing_cs.c
170
return pcmcia_write_config_byte(pcmcia, 2, v ? 0 : 0x20);
drivers/net/can/softing/softing_cs.c
173
static int softingcs_enable_irq(struct platform_device *pdev, int v)
drivers/net/can/softing/softing_cs.c
177
dev_dbg(&pdev->dev, "pcmcia config [0] %02x\n", v ? 0x60 : 0);
drivers/net/can/softing/softing_cs.c
178
return pcmcia_write_config_byte(pcmcia, 0, v ? 0x60 : 0);
drivers/net/can/softing/softing_cs.c
20
static int softingcs_reset(struct platform_device *pdev, int v);
drivers/net/can/softing/softing_cs.c
21
static int softingcs_enable_irq(struct platform_device *pdev, int v);
drivers/net/dsa/b53/b53_common.c
905
struct b53_vlan *v;
drivers/net/dsa/b53/b53_common.c
927
v = &dev->vlans[def_vid];
drivers/net/dsa/b53/b53_common.c
945
v = &dev->vlans[vid];
drivers/net/dsa/b53/b53_common.c
947
if (!v->members)
drivers/net/dsa/b53/b53_common.c
950
b53_set_vlan_entry(dev, vid, v);
drivers/net/dsa/b53/b53_mdio.c
45
u16 v;
drivers/net/dsa/b53/b53_mdio.c
51
v = (page << 8) | REG_MII_PAGE_ENABLE;
drivers/net/dsa/b53/b53_mdio.c
53
REG_MII_PAGE, v);
drivers/net/dsa/b53/b53_mdio.c
60
v = (reg << 8) | op;
drivers/net/dsa/b53/b53_mdio.c
61
ret = mdiobus_write_nested(bus, BRCM_PSEUDO_PHY_ADDR, REG_MII_ADDR, v);
drivers/net/dsa/b53/b53_mdio.c
67
v = mdiobus_read_nested(bus, BRCM_PSEUDO_PHY_ADDR,
drivers/net/dsa/b53/b53_mdio.c
69
if (!(v & (REG_MII_ADDR_WRITE | REG_MII_ADDR_READ)))
drivers/net/dsa/lantiq/lantiq_gswip.h
97
#define GSWIP_VERSION_REV(v) FIELD_GET(GSWIP_VERSION_REV_MASK, v)
drivers/net/dsa/lantiq/lantiq_gswip.h
98
#define GSWIP_VERSION_MOD(v) FIELD_GET(GSWIP_VERSION_MOD_MASK, v)
drivers/net/dsa/microchip/ksz_spi.c
119
u16 v;
drivers/net/dsa/microchip/ksz_spi.c
121
memcpy(&v, val, sizeof(v));
drivers/net/dsa/microchip/ksz_spi.c
122
put_unaligned_le16(v, val);
drivers/net/dsa/microchip/ksz_spi.c
125
u32 v;
drivers/net/dsa/microchip/ksz_spi.c
127
memcpy(&v, val, sizeof(v));
drivers/net/dsa/microchip/ksz_spi.c
128
put_unaligned_le32(v, val);
drivers/net/dsa/microchip/ksz_spi.c
84
u16 v = get_unaligned_le16(val);
drivers/net/dsa/microchip/ksz_spi.c
86
memcpy(val, &v, sizeof(v));
drivers/net/dsa/microchip/ksz_spi.c
88
u32 v = get_unaligned_le32(val);
drivers/net/dsa/microchip/ksz_spi.c
90
memcpy(val, &v, sizeof(v));
drivers/net/dsa/xrs700x/xrs700x_reg.h
208
#define XRS_VLAN(v) (XRS_SWITCH_VLAN_BASE + 0x2 * (v))
drivers/net/dsa/yt921x.c
226
u32 v;
drivers/net/dsa/yt921x.c
229
res = yt921x_reg_read(priv, reg, &v);
drivers/net/dsa/yt921x.c
233
u = v;
drivers/net/dsa/yt921x.c
236
if (u == v)
drivers/net/dsa/yt921x.c
296
u64 v;
drivers/net/dsa/yt921x.c
299
res = yt921x_reg64_read(priv, reg, &v);
drivers/net/dsa/yt921x.c
303
u = v;
drivers/net/dsa/yt921x.c
306
if (u == v)
drivers/net/ethernet/3com/3c509.c
1180
static void el3_set_msglevel(struct net_device *dev, u32 v)
drivers/net/ethernet/3com/3c509.c
1182
el3_debug = v;
drivers/net/ethernet/3com/3c574_cs.c
106
#define INT_MODULE_PARM(n, v) static int n = v; module_param(n, int, 0)
drivers/net/ethernet/3com/3c589_cs.c
152
#define INT_MODULE_PARM(n, v) static int n = v; module_param(n, int, 0)
drivers/net/ethernet/3com/3c59x.c
511
#define RAM_SIZE(v) BFEXT(v, 0, 3)
drivers/net/ethernet/3com/3c59x.c
512
#define RAM_WIDTH(v) BFEXT(v, 3, 1)
drivers/net/ethernet/3com/3c59x.c
513
#define RAM_SPEED(v) BFEXT(v, 4, 2)
drivers/net/ethernet/3com/3c59x.c
514
#define ROM_SIZE(v) BFEXT(v, 6, 2)
drivers/net/ethernet/3com/3c59x.c
515
#define RAM_SPLIT(v) BFEXT(v, 16, 2)
drivers/net/ethernet/3com/3c59x.c
516
#define XCVR(v) BFEXT(v, 20, 4)
drivers/net/ethernet/3com/3c59x.c
517
#define AUTOSELECT(v) BFEXT(v, 24, 1)
drivers/net/ethernet/8390/ax88796.c
594
static void ax_set_msglevel(struct net_device *dev, u32 v)
drivers/net/ethernet/8390/ax88796.c
598
ei_local->msg_enable = v;
drivers/net/ethernet/8390/etherh.c
617
static void etherh_set_msglevel(struct net_device *dev, u32 v)
drivers/net/ethernet/8390/etherh.c
621
ei_local->msg_enable = v;
drivers/net/ethernet/8390/ne2k-pci.c
671
static void ne2k_pci_set_msglevel(struct net_device *dev, u32 v)
drivers/net/ethernet/8390/ne2k-pci.c
675
ei_local->msg_enable = v;
drivers/net/ethernet/8390/pcnet_cs.c
77
#define INT_MODULE_PARM(n, v) static int n = v; module_param(n, int, 0)
drivers/net/ethernet/aeroflex/greth.c
82
#define GRETH_REGSAVE(a, v) (__raw_writel(cpu_to_be32(v), &(a)))
drivers/net/ethernet/aeroflex/greth.c
83
#define GRETH_REGORIN(a, v) (GRETH_REGSAVE(a, (GRETH_REGLOAD(a) | (v))))
drivers/net/ethernet/aeroflex/greth.c
84
#define GRETH_REGANDIN(a, v) (GRETH_REGSAVE(a, (GRETH_REGLOAD(a) & (v))))
drivers/net/ethernet/agere/et131x.c
796
static inline void add_10bit(u32 *v, int n)
drivers/net/ethernet/agere/et131x.c
798
*v = INDEX10(*v + n) | (*v & ET_DMA10_WRAP);
drivers/net/ethernet/agere/et131x.c
801
static inline void add_12bit(u32 *v, int n)
drivers/net/ethernet/agere/et131x.c
803
*v = INDEX12(*v + n) | (*v & ET_DMA12_WRAP);
drivers/net/ethernet/altera/altera_msgdmahw.h
105
#define MSGDMA_CSR_STAT_BUSY_GET(v) GET_BIT_VALUE(v, 0)
drivers/net/ethernet/altera/altera_msgdmahw.h
106
#define MSGDMA_CSR_STAT_DESC_BUF_EMPTY_GET(v) GET_BIT_VALUE(v, 1)
drivers/net/ethernet/altera/altera_msgdmahw.h
107
#define MSGDMA_CSR_STAT_DESC_BUF_FULL_GET(v) GET_BIT_VALUE(v, 2)
drivers/net/ethernet/altera/altera_msgdmahw.h
108
#define MSGDMA_CSR_STAT_RESP_BUF_EMPTY_GET(v) GET_BIT_VALUE(v, 3)
drivers/net/ethernet/altera/altera_msgdmahw.h
109
#define MSGDMA_CSR_STAT_RESP_BUF_FULL_GET(v) GET_BIT_VALUE(v, 4)
drivers/net/ethernet/altera/altera_msgdmahw.h
110
#define MSGDMA_CSR_STAT_STOPPED_GET(v) GET_BIT_VALUE(v, 5)
drivers/net/ethernet/altera/altera_msgdmahw.h
111
#define MSGDMA_CSR_STAT_RESETTING_GET(v) GET_BIT_VALUE(v, 6)
drivers/net/ethernet/altera/altera_msgdmahw.h
112
#define MSGDMA_CSR_STAT_STOPPED_ON_ERR_GET(v) GET_BIT_VALUE(v, 7)
drivers/net/ethernet/altera/altera_msgdmahw.h
113
#define MSGDMA_CSR_STAT_STOPPED_ON_EARLY_GET(v) GET_BIT_VALUE(v, 8)
drivers/net/ethernet/altera/altera_msgdmahw.h
114
#define MSGDMA_CSR_STAT_IRQ_GET(v) GET_BIT_VALUE(v, 9)
drivers/net/ethernet/altera/altera_msgdmahw.h
127
#define MSGDMA_CSR_WR_FILL_LEVEL_GET(v) (((v) & 0xffff0000) >> 16)
drivers/net/ethernet/altera/altera_msgdmahw.h
128
#define MSGDMA_CSR_RD_FILL_LEVEL_GET(v) ((v) & 0x0000ffff)
drivers/net/ethernet/altera/altera_msgdmahw.h
129
#define MSGDMA_CSR_RESP_FILL_LEVEL_GET(v) ((v) & 0x0000ffff)
drivers/net/ethernet/altera/altera_tse.h
100
#define MAC_CMDCFG_LOOP_ENA_GET(v) GET_BIT_VALUE(v, 15)
drivers/net/ethernet/altera/altera_tse.h
101
#define MAC_CMDCFG_TX_ADDR_SEL_GET(v) (((v) >> 16) & 0x7)
drivers/net/ethernet/altera/altera_tse.h
102
#define MAC_CMDCFG_MAGIC_ENA_GET(v) GET_BIT_VALUE(v, 19)
drivers/net/ethernet/altera/altera_tse.h
103
#define MAC_CMDCFG_SLEEP_GET(v) GET_BIT_VALUE(v, 20)
drivers/net/ethernet/altera/altera_tse.h
104
#define MAC_CMDCFG_WAKEUP_GET(v) GET_BIT_VALUE(v, 21)
drivers/net/ethernet/altera/altera_tse.h
105
#define MAC_CMDCFG_XOFF_GEN_GET(v) GET_BIT_VALUE(v, 22)
drivers/net/ethernet/altera/altera_tse.h
106
#define MAC_CMDCFG_CNTL_FRM_ENA_GET(v) GET_BIT_VALUE(v, 23)
drivers/net/ethernet/altera/altera_tse.h
107
#define MAC_CMDCFG_NO_LGTH_CHECK_GET(v) GET_BIT_VALUE(v, 24)
drivers/net/ethernet/altera/altera_tse.h
108
#define MAC_CMDCFG_ENA_10_GET(v) GET_BIT_VALUE(v, 25)
drivers/net/ethernet/altera/altera_tse.h
109
#define MAC_CMDCFG_RX_ERR_DISC_GET(v) GET_BIT_VALUE(v, 26)
drivers/net/ethernet/altera/altera_tse.h
110
#define MAC_CMDCFG_DISABLE_READ_TIMEOUT_GET(v) GET_BIT_VALUE(v, 27)
drivers/net/ethernet/altera/altera_tse.h
111
#define MAC_CMDCFG_CNT_RESET_GET(v) GET_BIT_VALUE(v, 31)
drivers/net/ethernet/altera/altera_tse.h
53
#define GET_BIT_VALUE(v, bit) (((v) >> (bit)) & 0x1)
drivers/net/ethernet/altera/altera_tse.h
73
#define MAC_CMDCFG_TX_ADDR_SEL(v) (((v) & 0x7) << 16)
drivers/net/ethernet/altera/altera_tse.h
85
#define MAC_CMDCFG_TX_ENA_GET(v) GET_BIT_VALUE(v, 0)
drivers/net/ethernet/altera/altera_tse.h
86
#define MAC_CMDCFG_RX_ENA_GET(v) GET_BIT_VALUE(v, 1)
drivers/net/ethernet/altera/altera_tse.h
87
#define MAC_CMDCFG_XON_GEN_GET(v) GET_BIT_VALUE(v, 2)
drivers/net/ethernet/altera/altera_tse.h
88
#define MAC_CMDCFG_ETH_SPEED_GET(v) GET_BIT_VALUE(v, 3)
drivers/net/ethernet/altera/altera_tse.h
89
#define MAC_CMDCFG_PROMIS_EN_GET(v) GET_BIT_VALUE(v, 4)
drivers/net/ethernet/altera/altera_tse.h
90
#define MAC_CMDCFG_PAD_EN_GET(v) GET_BIT_VALUE(v, 5)
drivers/net/ethernet/altera/altera_tse.h
91
#define MAC_CMDCFG_CRC_FWD_GET(v) GET_BIT_VALUE(v, 6)
drivers/net/ethernet/altera/altera_tse.h
92
#define MAC_CMDCFG_PAUSE_FWD_GET(v) GET_BIT_VALUE(v, 7)
drivers/net/ethernet/altera/altera_tse.h
93
#define MAC_CMDCFG_PAUSE_IGNORE_GET(v) GET_BIT_VALUE(v, 8)
drivers/net/ethernet/altera/altera_tse.h
94
#define MAC_CMDCFG_TX_ADDR_INS_GET(v) GET_BIT_VALUE(v, 9)
drivers/net/ethernet/altera/altera_tse.h
95
#define MAC_CMDCFG_HD_ENA_GET(v) GET_BIT_VALUE(v, 10)
drivers/net/ethernet/altera/altera_tse.h
96
#define MAC_CMDCFG_EXCESS_COL_GET(v) GET_BIT_VALUE(v, 11)
drivers/net/ethernet/altera/altera_tse.h
97
#define MAC_CMDCFG_LATE_COL_GET(v) GET_BIT_VALUE(v, 12)
drivers/net/ethernet/altera/altera_tse.h
98
#define MAC_CMDCFG_SW_RESET_GET(v) GET_BIT_VALUE(v, 13)
drivers/net/ethernet/altera/altera_tse.h
99
#define MAC_CMDCFG_MHASH_SEL_GET(v) GET_BIT_VALUE(v, 14)
drivers/net/ethernet/amd/nmclan_cs.c
389
#define INT_MODULE_PARM(n, v) static int n = v; module_param(n, int, 0)
drivers/net/ethernet/amd/pds_core/debugfs.c
33
static int identity_show(struct seq_file *seq, void *v)
drivers/net/ethernet/amd/pds_core/debugfs.c
75
static int viftype_show(struct seq_file *seq, void *v)
drivers/net/ethernet/apple/macmace.c
231
u8 v = bitrev8(addr[j<<4]);
drivers/net/ethernet/apple/macmace.c
232
checksum ^= v;
drivers/net/ethernet/apple/macmace.c
233
macaddr[j] = v;
drivers/net/ethernet/broadcom/bnge/bnge_netdev.h
374
__le32 v;
drivers/net/ethernet/broadcom/bnge/bnge_txrx.h
90
(!!((nqcmp)->v & cpu_to_le32(NQ_CN_V)) == !((raw_cons) & (bn)->cp_bit))
drivers/net/ethernet/broadcom/bnx2.c
4261
__be32 v = cpu_to_be32(BNX2_RD(bp, BNX2_NVM_READ));
drivers/net/ethernet/broadcom/bnx2.c
4262
memcpy(ret_val, &v, 4);
drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c
14232
u32 v;
drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c
14234
v = SHMEM2_RD(bp,
drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c
14237
v & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c
4164
static inline bool __atomic_add_ifless(atomic_t *v, int a, int u)
drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c
4168
c = atomic_read(v);
drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c
4173
old = atomic_cmpxchg((v), c, c + a);
drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c
4192
static inline bool __atomic_dec_ifmoe(atomic_t *v, int a, int u)
drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c
4196
c = atomic_read(v);
drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c
4201
old = atomic_cmpxchg((v), c, c - a);
drivers/net/ethernet/broadcom/bnxt/bnxt.h
675
__le32 v;
drivers/net/ethernet/broadcom/bnxt/bnxt.h
853
(!!((nqcmp)->v & cpu_to_le32(NQ_CN_V)) == !((raw_cons) & bp->cp_bit))
drivers/net/ethernet/broadcom/genet/bcmgenet.c
1171
#define BCMGENET_STATS64_ADD(stats, m, v) \
drivers/net/ethernet/broadcom/genet/bcmgenet.c
1174
u64_stats_add(&stats->m, v); \
drivers/net/ethernet/broadcom/tg3.c
15850
__be32 v;
drivers/net/ethernet/broadcom/tg3.c
15851
if (tg3_nvram_read_be32(tp, offset + i, &v))
drivers/net/ethernet/broadcom/tg3.c
15854
memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
drivers/net/ethernet/broadcom/tg3.c
15977
__be32 v;
drivers/net/ethernet/broadcom/tg3.c
15978
if (tg3_nvram_read_be32(tp, offset, &v))
drivers/net/ethernet/broadcom/tg3.c
15981
offset += sizeof(v);
drivers/net/ethernet/broadcom/tg3.c
15983
if (vlen > TG3_VER_SIZE - sizeof(v)) {
drivers/net/ethernet/broadcom/tg3.c
15984
memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
drivers/net/ethernet/broadcom/tg3.c
15988
memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
drivers/net/ethernet/broadcom/tg3.c
15989
vlen += sizeof(v);
drivers/net/ethernet/broadcom/tg3.c
3316
u32 v;
drivers/net/ethernet/broadcom/tg3.c
3317
int res = tg3_nvram_read(tp, offset, &v);
drivers/net/ethernet/broadcom/tg3.c
3319
*val = cpu_to_be32(v);
drivers/net/ethernet/cavium/liquidio/octeon_main.h
29
#define CVM_CAST64(v) ((long long)(v))
drivers/net/ethernet/cavium/liquidio/octeon_main.h
31
#define CVM_CAST64(v) ((long long)(long)(v))
drivers/net/ethernet/chelsio/cxgb/sge.c
77
#define V_CMD_LEN(v) (v)
drivers/net/ethernet/chelsio/cxgb/sge.c
78
#define G_CMD_LEN(v) ((v) & M_CMD_LEN)
drivers/net/ethernet/chelsio/cxgb/sge.c
79
#define V_CMD_GEN1(v) ((v) << 31)
drivers/net/ethernet/chelsio/cxgb/sge.c
80
#define V_CMD_GEN2(v) (v)
drivers/net/ethernet/chelsio/cxgb/sge.c
83
#define V_CMD_EOP(v) ((v) << 3)
drivers/net/ethernet/chelsio/cxgb/subr.c
569
u32 v;
drivers/net/ethernet/chelsio/cxgb/subr.c
585
pci_read_config_dword(adapter->pdev, A_PCICFG_VPD_DATA, &v);
drivers/net/ethernet/chelsio/cxgb/subr.c
586
*data = cpu_to_le32(v);
drivers/net/ethernet/chelsio/cxgb/suni1x10gexp_regs.h
524
#define mSUNI1x10GEXP_CLR_MSBITS_1(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_15)
drivers/net/ethernet/chelsio/cxgb/suni1x10gexp_regs.h
525
#define mSUNI1x10GEXP_CLR_MSBITS_2(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_14)
drivers/net/ethernet/chelsio/cxgb/suni1x10gexp_regs.h
526
#define mSUNI1x10GEXP_CLR_MSBITS_3(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_13)
drivers/net/ethernet/chelsio/cxgb/suni1x10gexp_regs.h
527
#define mSUNI1x10GEXP_CLR_MSBITS_4(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_12)
drivers/net/ethernet/chelsio/cxgb/suni1x10gexp_regs.h
528
#define mSUNI1x10GEXP_CLR_MSBITS_5(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_11)
drivers/net/ethernet/chelsio/cxgb/suni1x10gexp_regs.h
529
#define mSUNI1x10GEXP_CLR_MSBITS_6(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_10)
drivers/net/ethernet/chelsio/cxgb/suni1x10gexp_regs.h
530
#define mSUNI1x10GEXP_CLR_MSBITS_7(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_9)
drivers/net/ethernet/chelsio/cxgb/suni1x10gexp_regs.h
531
#define mSUNI1x10GEXP_CLR_MSBITS_8(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_8)
drivers/net/ethernet/chelsio/cxgb/suni1x10gexp_regs.h
532
#define mSUNI1x10GEXP_CLR_MSBITS_9(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_7)
drivers/net/ethernet/chelsio/cxgb/suni1x10gexp_regs.h
533
#define mSUNI1x10GEXP_CLR_MSBITS_10(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_6)
drivers/net/ethernet/chelsio/cxgb/suni1x10gexp_regs.h
534
#define mSUNI1x10GEXP_CLR_MSBITS_11(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_5)
drivers/net/ethernet/chelsio/cxgb/suni1x10gexp_regs.h
535
#define mSUNI1x10GEXP_CLR_MSBITS_12(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_4)
drivers/net/ethernet/chelsio/cxgb/suni1x10gexp_regs.h
536
#define mSUNI1x10GEXP_CLR_MSBITS_13(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_3)
drivers/net/ethernet/chelsio/cxgb/suni1x10gexp_regs.h
537
#define mSUNI1x10GEXP_CLR_MSBITS_14(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_2)
drivers/net/ethernet/chelsio/cxgb/suni1x10gexp_regs.h
538
#define mSUNI1x10GEXP_CLR_MSBITS_15(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_1)
drivers/net/ethernet/chelsio/cxgb/vsc7326.c
435
u32 v;
drivers/net/ethernet/chelsio/cxgb/vsc7326.c
438
vsc_read(mac->adapter, REG_ING_FFILT_UM_EN, &v);
drivers/net/ethernet/chelsio/cxgb/vsc7326.c
439
v |= 1 << 12;
drivers/net/ethernet/chelsio/cxgb/vsc7326.c
442
v &= ~(1 << (port + 16));
drivers/net/ethernet/chelsio/cxgb/vsc7326.c
444
v |= 1 << (port + 16);
drivers/net/ethernet/chelsio/cxgb/vsc7326.c
446
vsc_write(mac->adapter, REG_ING_FFILT_UM_EN, v);
drivers/net/ethernet/chelsio/cxgb/vsc7326.c
462
u32 v;
drivers/net/ethernet/chelsio/cxgb/vsc7326.c
472
vsc_read(mac->adapter, REG_MODE_CFG(port), &v);
drivers/net/ethernet/chelsio/cxgb/vsc7326.c
473
enable = v & 3; /* save tx/rx enables */
drivers/net/ethernet/chelsio/cxgb/vsc7326.c
474
v &= ~0xf;
drivers/net/ethernet/chelsio/cxgb/vsc7326.c
475
v |= 4; /* full duplex */
drivers/net/ethernet/chelsio/cxgb/vsc7326.c
477
v |= 8; /* GigE */
drivers/net/ethernet/chelsio/cxgb/vsc7326.c
478
enable |= v;
drivers/net/ethernet/chelsio/cxgb/vsc7326.c
479
vsc_write(mac->adapter, REG_MODE_CFG(port), v);
drivers/net/ethernet/chelsio/cxgb/vsc7326.c
482
v = 0x82;
drivers/net/ethernet/chelsio/cxgb/vsc7326.c
484
v = 0x84;
drivers/net/ethernet/chelsio/cxgb/vsc7326.c
486
v = 0x86;
drivers/net/ethernet/chelsio/cxgb/vsc7326.c
487
vsc_write(mac->adapter, REG_DEV_SETUP(port), v | 1); /* reset */
drivers/net/ethernet/chelsio/cxgb/vsc7326.c
488
vsc_write(mac->adapter, REG_DEV_SETUP(port), v);
drivers/net/ethernet/chelsio/cxgb/vsc7326.c
489
vsc_read(mac->adapter, REG_DBG(port), &v);
drivers/net/ethernet/chelsio/cxgb/vsc7326.c
490
v &= ~0xff00;
drivers/net/ethernet/chelsio/cxgb/vsc7326.c
492
v |= 0x400;
drivers/net/ethernet/chelsio/cxgb/vsc7326.c
494
v |= 0x2000;
drivers/net/ethernet/chelsio/cxgb/vsc7326.c
496
v |= 0xff00;
drivers/net/ethernet/chelsio/cxgb/vsc7326.c
497
vsc_write(mac->adapter, REG_DBG(port), v);
drivers/net/ethernet/chelsio/cxgb/vsc7326.c
515
vsc_read(mac->adapter, REG_PAUSE_CFG(port), &v);
drivers/net/ethernet/chelsio/cxgb/vsc7326.c
516
v &= 0xfff0ffff;
drivers/net/ethernet/chelsio/cxgb/vsc7326.c
517
v |= 0x20000; /* xon/xoff */
drivers/net/ethernet/chelsio/cxgb/vsc7326.c
519
v |= 0x40000;
drivers/net/ethernet/chelsio/cxgb/vsc7326.c
521
v |= 0x80000;
drivers/net/ethernet/chelsio/cxgb/vsc7326.c
523
v |= 0x10000;
drivers/net/ethernet/chelsio/cxgb/vsc7326.c
524
vsc_write(mac->adapter, REG_PAUSE_CFG(port), v);
drivers/net/ethernet/chelsio/cxgb/vsc7326.c
573
u32 v, lo;
drivers/net/ethernet/chelsio/cxgb/vsc7326.c
575
vsc_read(mac->adapter, addr, &v);
drivers/net/ethernet/chelsio/cxgb/vsc7326.c
577
*stat = *stat - lo + v;
drivers/net/ethernet/chelsio/cxgb/vsc7326.c
579
if (v == 0)
drivers/net/ethernet/chelsio/cxgb/vsc7326.c
582
if (v < lo)
drivers/net/ethernet/chelsio/cxgb3/ael1002.c
253
int v;
drivers/net/ethernet/chelsio/cxgb3/ael1002.c
259
v = ael_i2c_rd(phy, MODULE_DEV_ADDR, 3);
drivers/net/ethernet/chelsio/cxgb3/ael1002.c
260
if (v < 0)
drivers/net/ethernet/chelsio/cxgb3/ael1002.c
261
return v;
drivers/net/ethernet/chelsio/cxgb3/ael1002.c
263
if (v == 0x10)
drivers/net/ethernet/chelsio/cxgb3/ael1002.c
265
if (v == 0x20)
drivers/net/ethernet/chelsio/cxgb3/ael1002.c
267
if (v == 0x40)
drivers/net/ethernet/chelsio/cxgb3/ael1002.c
270
v = ael_i2c_rd(phy, MODULE_DEV_ADDR, 6);
drivers/net/ethernet/chelsio/cxgb3/ael1002.c
271
if (v < 0)
drivers/net/ethernet/chelsio/cxgb3/ael1002.c
272
return v;
drivers/net/ethernet/chelsio/cxgb3/ael1002.c
273
if (v != 4)
drivers/net/ethernet/chelsio/cxgb3/ael1002.c
276
v = ael_i2c_rd(phy, MODULE_DEV_ADDR, 10);
drivers/net/ethernet/chelsio/cxgb3/ael1002.c
277
if (v < 0)
drivers/net/ethernet/chelsio/cxgb3/ael1002.c
278
return v;
drivers/net/ethernet/chelsio/cxgb3/ael1002.c
280
if (v & 0x80) {
drivers/net/ethernet/chelsio/cxgb3/ael1002.c
281
v = ael_i2c_rd(phy, MODULE_DEV_ADDR, 0x12);
drivers/net/ethernet/chelsio/cxgb3/ael1002.c
282
if (v < 0)
drivers/net/ethernet/chelsio/cxgb3/ael1002.c
283
return v;
drivers/net/ethernet/chelsio/cxgb3/ael1002.c
284
return v > 10 ? phy_modtype_twinax_long : phy_modtype_twinax;
drivers/net/ethernet/chelsio/cxgb3/ael1002.c
363
int v;
drivers/net/ethernet/chelsio/cxgb3/ael1002.c
366
v = t3_mdio_read(phy, MDIO_MMD_PMAPMD, AEL2005_GPIO_CTRL, &stat);
drivers/net/ethernet/chelsio/cxgb3/ael1002.c
367
if (v)
drivers/net/ethernet/chelsio/cxgb3/ael1002.c
368
return v;
drivers/net/ethernet/chelsio/cxgb3/ael1002.c
606
int v;
drivers/net/ethernet/chelsio/cxgb3/ael1002.c
609
v = t3_mdio_read(phy, MDIO_MMD_PMAPMD, AEL2020_GPIO_STAT, &stat);
drivers/net/ethernet/chelsio/cxgb3/ael1002.c
610
if (v)
drivers/net/ethernet/chelsio/cxgb3/ael1002.c
611
return v;
drivers/net/ethernet/chelsio/cxgb3/aq100x.c
100
t3_mdio_read(phy, MDIO_MMD_PMAPMD, MDIO_STAT1, &v);
drivers/net/ethernet/chelsio/cxgb3/aq100x.c
108
unsigned int cause, v;
drivers/net/ethernet/chelsio/cxgb3/aq100x.c
115
t3_mdio_read(phy, MDIO_MMD_PMAPMD, MDIO_STAT1, &v);
drivers/net/ethernet/chelsio/cxgb3/aq100x.c
211
unsigned int v;
drivers/net/ethernet/chelsio/cxgb3/aq100x.c
214
err = t3_mdio_read(phy, MDIO_MMD_PMAPMD, AQ_LINK_STAT, &v);
drivers/net/ethernet/chelsio/cxgb3/aq100x.c
218
*link_ok = v & 1;
drivers/net/ethernet/chelsio/cxgb3/aq100x.c
223
err = t3_mdio_read(phy, MDIO_MMD_AN, AQ_ANEG_STAT, &v);
drivers/net/ethernet/chelsio/cxgb3/aq100x.c
228
switch (v & 0x6) {
drivers/net/ethernet/chelsio/cxgb3/aq100x.c
245
*duplex = v & 1 ? DUPLEX_FULL : DUPLEX_HALF;
drivers/net/ethernet/chelsio/cxgb3/aq100x.c
269
unsigned int v, v2, gpio, wait;
drivers/net/ethernet/chelsio/cxgb3/aq100x.c
292
err = t3_mdio_read(phy, MDIO_MMD_VEND1, MDIO_CTRL1, &v);
drivers/net/ethernet/chelsio/cxgb3/aq100x.c
293
if (err || v == 0xffff) {
drivers/net/ethernet/chelsio/cxgb3/aq100x.c
298
phy_addr, err, v);
drivers/net/ethernet/chelsio/cxgb3/aq100x.c
302
v &= AQ_RESET;
drivers/net/ethernet/chelsio/cxgb3/aq100x.c
303
if (v)
drivers/net/ethernet/chelsio/cxgb3/aq100x.c
305
} while (v && --wait);
drivers/net/ethernet/chelsio/cxgb3/aq100x.c
306
if (v) {
drivers/net/ethernet/chelsio/cxgb3/aq100x.c
308
phy_addr, v);
drivers/net/ethernet/chelsio/cxgb3/aq100x.c
319
t3_mdio_read(phy, MDIO_MMD_VEND1, AQ_FW_VERSION, &v);
drivers/net/ethernet/chelsio/cxgb3/aq100x.c
320
if (v != 101)
drivers/net/ethernet/chelsio/cxgb3/aq100x.c
322
phy_addr, v);
drivers/net/ethernet/chelsio/cxgb3/aq100x.c
328
err = t3_mdio_read(phy, MDIO_MMD_VEND1, MDIO_CTRL1, &v);
drivers/net/ethernet/chelsio/cxgb3/aq100x.c
331
if (v & AQ_LOWPOWER) {
drivers/net/ethernet/chelsio/cxgb3/aq100x.c
344
v = v2 = 0;
drivers/net/ethernet/chelsio/cxgb3/aq100x.c
345
t3_mdio_read(phy, MDIO_MMD_PHYXS, AQ_XAUI_RX_CFG, &v);
drivers/net/ethernet/chelsio/cxgb3/aq100x.c
347
if (v != 0x1b || v2 != 0x1b)
drivers/net/ethernet/chelsio/cxgb3/aq100x.c
350
phy_addr, v, v2);
drivers/net/ethernet/chelsio/cxgb3/aq100x.c
97
unsigned int v;
drivers/net/ethernet/chelsio/cxgb3/aq100x.c
99
t3_mdio_read(phy, MDIO_MMD_VEND1, AQ_IFLAG_GLOBAL, &v);
drivers/net/ethernet/chelsio/cxgb3/cxgb3_main.c
2722
unsigned int v, status, reset;
drivers/net/ethernet/chelsio/cxgb3/cxgb3_main.c
2773
v = (t3_read_reg(adapter, A_SG_RSPQ_FL_STATUS) >> S_FL0EMPTY) &
drivers/net/ethernet/chelsio/cxgb3/cxgb3_main.c
2776
while (v) {
drivers/net/ethernet/chelsio/cxgb3/cxgb3_main.c
2777
qs->fl[i].empty += (v & 1);
drivers/net/ethernet/chelsio/cxgb3/cxgb3_main.c
2781
v >>= 1;
drivers/net/ethernet/chelsio/cxgb3/cxgb3_main.c
802
unsigned int v, addr, bpt, cpt;
drivers/net/ethernet/chelsio/cxgb3/cxgb3_main.c
808
v = t3_read_reg(adap, A_TP_TM_PIO_DATA);
drivers/net/ethernet/chelsio/cxgb3/cxgb3_main.c
810
v >>= 16;
drivers/net/ethernet/chelsio/cxgb3/cxgb3_main.c
811
bpt = (v >> 8) & 0xff;
drivers/net/ethernet/chelsio/cxgb3/cxgb3_main.c
812
cpt = v & 0xff;
drivers/net/ethernet/chelsio/cxgb3/cxgb3_main.c
816
v = (adap->params.vpd.cclk * 1000) / cpt;
drivers/net/ethernet/chelsio/cxgb3/cxgb3_main.c
817
len = sprintf(buf, "%u Kbps\n", (v * bpt) / 125);
drivers/net/ethernet/chelsio/cxgb3/sge.c
2854
unsigned int v, status = t3_read_reg(adapter, A_SG_INT_CAUSE) &
drivers/net/ethernet/chelsio/cxgb3/sge.c
2868
v = t3_read_reg(adapter, A_SG_RSPQ_FL_STATUS);
drivers/net/ethernet/chelsio/cxgb3/sge.c
2872
"(0x%x)\n", (v >> S_RSPQ0DISABLED) & 0xff);
drivers/net/ethernet/chelsio/cxgb3/t3_hw.c
107
u32 v = t3_read_reg(adapter, addr) & ~mask;
drivers/net/ethernet/chelsio/cxgb3/t3_hw.c
109
t3_write_reg(adapter, addr, v | val);
drivers/net/ethernet/chelsio/cxgb3/t3_hw.c
2974
unsigned int v, tps, cpt, bpt, delta, mindelta = ~0;
drivers/net/ethernet/chelsio/cxgb3/t3_hw.c
2984
v = bpt * tps;
drivers/net/ethernet/chelsio/cxgb3/t3_hw.c
2985
delta = v >= kbps ? v - kbps : kbps - v;
drivers/net/ethernet/chelsio/cxgb3/t3_hw.c
2999
v = t3_read_reg(adap, A_TP_TM_PIO_DATA);
drivers/net/ethernet/chelsio/cxgb3/t3_hw.c
3001
v = (v & 0xffff) | (selected_cpt << 16) | (selected_bpt << 24);
drivers/net/ethernet/chelsio/cxgb3/t3_hw.c
3003
v = (v & 0xffff0000) | selected_cpt | (selected_bpt << 8);
drivers/net/ethernet/chelsio/cxgb3/t3_hw.c
3004
t3_write_reg(adap, A_TP_TM_PIO_DATA, v);
drivers/net/ethernet/chelsio/cxgb3/t3_hw.c
3066
unsigned int v, i;
drivers/net/ethernet/chelsio/cxgb3/t3_hw.c
3072
v = t3_read_reg(adapter, A_XGM_XAUI_IMP);
drivers/net/ethernet/chelsio/cxgb3/t3_hw.c
3073
if (!(v & (F_XGM_CALFAULT | F_CALBUSY))) {
drivers/net/ethernet/chelsio/cxgb3/t3_hw.c
3075
V_XAUIIMP(G_CALIMP(v) >> 2));
drivers/net/ethernet/chelsio/cxgb3/xgmac.c
269
u32 v = t3_read_reg(mac->adapter, reg);
drivers/net/ethernet/chelsio/cxgb3/xgmac.c
270
t3_write_reg(mac->adapter, reg, v);
drivers/net/ethernet/chelsio/cxgb3/xgmac.c
280
u32 v = t3_read_reg(mac->adapter, reg);
drivers/net/ethernet/chelsio/cxgb3/xgmac.c
281
t3_write_reg(mac->adapter, reg, v);
drivers/net/ethernet/chelsio/cxgb3/xgmac.c
349
unsigned int thres, v, reg;
drivers/net/ethernet/chelsio/cxgb3/xgmac.c
367
v = t3_read_reg(adap, A_XGM_RX_CFG + mac->offset);
drivers/net/ethernet/chelsio/cxgb3/xgmac.c
377
t3_write_reg(adap, A_XGM_RX_CFG + mac->offset, v);
drivers/net/ethernet/chelsio/cxgb3/xgmac.c
384
t3_write_reg(adap, A_XGM_RX_CFG + mac->offset, v);
drivers/net/ethernet/chelsio/cxgb3/xgmac.c
397
v = t3_read_reg(adap, A_XGM_RXFIFO_CFG + mac->offset);
drivers/net/ethernet/chelsio/cxgb3/xgmac.c
398
v &= ~V_RXFIFOPAUSELWM(M_RXFIFOPAUSELWM);
drivers/net/ethernet/chelsio/cxgb3/xgmac.c
399
v |= V_RXFIFOPAUSELWM(lwm / 8);
drivers/net/ethernet/chelsio/cxgb3/xgmac.c
400
if (G_RXFIFOPAUSEHWM(v))
drivers/net/ethernet/chelsio/cxgb3/xgmac.c
401
v = (v & ~V_RXFIFOPAUSEHWM(M_RXFIFOPAUSEHWM)) |
drivers/net/ethernet/chelsio/cxgb3/xgmac.c
404
t3_write_reg(adap, A_XGM_RXFIFO_CFG + mac->offset, v);
drivers/net/ethernet/chelsio/cxgb3/xgmac.c
607
u32 v, lo;
drivers/net/ethernet/chelsio/cxgb3/xgmac.c
621
v = RMON_READ(mac, A_XGM_RX_MAX_PKT_SIZE_ERR_CNT);
drivers/net/ethernet/chelsio/cxgb3/xgmac.c
623
v &= 0x7fffffff;
drivers/net/ethernet/chelsio/cxgb3/xgmac.c
624
mac->stats.rx_too_long += v;
drivers/net/ethernet/chelsio/cxgb3/xgmac.c
652
v = t3_read_reg(mac->adapter, A_TP_MIB_RDATA);
drivers/net/ethernet/chelsio/cxgb3/xgmac.c
654
mac->stats.rx_cong_drops += (u64) (v - lo);
drivers/net/ethernet/chelsio/cxgb4/clip_tbl.c
250
int clip_tbl_show(struct seq_file *seq, void *v)
drivers/net/ethernet/chelsio/cxgb4/clip_tbl.h
43
int clip_tbl_show(struct seq_file *seq, void *v);
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
1000
int fidx = (uintptr_t)v - 2;
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
1059
static void *devlog_next(struct seq_file *seq, void *v, loff_t *pos)
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
1067
static void devlog_stop(struct seq_file *seq, void *v)
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
1154
static int mboxlog_show(struct seq_file *seq, void *v)
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
1161
if (v == SEQ_START_TOKEN) {
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
1169
entry_idx = log->cursor + ((uintptr_t)v - 2);
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
1205
static void *mboxlog_next(struct seq_file *seq, void *v, loff_t *pos)
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
1211
static void mboxlog_stop(struct seq_file *seq, void *v)
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
123
static int cim_la_show(struct seq_file *seq, void *v, int idx)
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
1242
static int mbox_show(struct seq_file *seq, void *v)
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
125
if (v == SEQ_START_TOKEN)
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
129
const u32 *p = v;
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
1326
static int mps_trc_show(struct seq_file *seq, void *v)
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
140
static int cim_la_show_3in1(struct seq_file *seq, void *v, int idx)
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
142
if (v == SEQ_START_TOKEN) {
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
145
const u32 *p = v;
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
158
static int cim_la_show_t6(struct seq_file *seq, void *v, int idx)
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
160
if (v == SEQ_START_TOKEN) {
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
164
const u32 *p = v;
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
1672
static int mps_tcam_show(struct seq_file *seq, void *v)
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
1676
if (v == SEQ_START_TOKEN) {
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
1699
unsigned int idx = (uintptr_t)v - 2;
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
177
static int cim_la_show_pc_t6(struct seq_file *seq, void *v, int idx)
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
179
if (v == SEQ_START_TOKEN) {
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
182
const u32 *p = v;
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
1901
static void *mps_tcam_next(struct seq_file *seq, void *v, loff_t *pos)
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
1907
static void mps_tcam_stop(struct seq_file *seq, void *v)
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
1940
static int sensors_show(struct seq_file *seq, void *v)
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
1979
static int rss_show(struct seq_file *seq, void *v, int idx)
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
1981
u16 *entry = v;
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
2029
static int rss_config_show(struct seq_file *seq, void *v)
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
2181
static int rss_key_show(struct seq_file *seq, void *v)
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
2244
static int rss_pf_config_show(struct seq_file *seq, void *v, int idx)
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
2248
if (v == SEQ_START_TOKEN) {
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
2263
pfconf = v;
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
2326
static int rss_vf_config_show(struct seq_file *seq, void *v, int idx)
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
2328
if (v == SEQ_START_TOKEN) {
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
2333
struct rss_vf_conf *vfconf = v;
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
237
static int cim_pif_la_show(struct seq_file *seq, void *v, int idx)
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
2385
static int dcb_info_show(struct seq_file *seq, void *v)
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
2389
if (v == SEQ_START_TOKEN) {
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
239
const u32 *p = v;
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
2392
int port = (uintptr_t)v - 2;
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
241
if (v == SEQ_START_TOKEN) {
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
2530
static void dcb_info_stop(struct seq_file *seq, void *v)
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
2534
static void *dcb_info_next(struct seq_file *seq, void *v, loff_t *pos)
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
2570
static int resources_show(struct seq_file *seq, void *v)
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
2650
static int sge_qinfo_show(struct seq_file *seq, void *v)
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
2660
int i, j, n, r = (uintptr_t)v - 1;
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
2669
#define S3(fmt_spec, s, v) \
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
2673
seq_printf(seq, " %16" fmt_spec, v); \
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
2676
#define S(s, v) S3("s", s, v)
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
2677
#define T3(fmt_spec, s, v) S3(fmt_spec, s, tx[i].v)
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
2678
#define T(s, v) S3("u", s, tx[i].v)
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
2679
#define TL(s, v) T3("lu", s, v)
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
2680
#define R3(fmt_spec, s, v) S3(fmt_spec, s, rx[i].v)
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
2681
#define R(s, v) S3("u", s, rx[i].v)
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
2682
#define RL(s, v) R3("lu", s, v)
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
280
static int cim_ma_la_show(struct seq_file *seq, void *v, int idx)
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
282
const u32 *p = v;
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
284
if (v == SEQ_START_TOKEN) {
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
3214
static void sge_queue_stop(struct seq_file *seq, void *v)
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
3218
static void *sge_queue_next(struct seq_file *seq, void *v, loff_t *pos)
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
326
static int cim_qcfg_show(struct seq_file *seq, void *v)
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
3312
static int tid_info_show(struct seq_file *seq, void *v)
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
3465
static int meminfo_show(struct seq_file *seq, void *v)
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
3528
static int chcr_stats_show(struct seq_file *seq, void *v)
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
3729
static int tp_stats_show(struct seq_file *seq, void *v)
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
383
static int cimq_show(struct seq_file *seq, void *v, int idx)
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
385
const u32 *p = v;
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
454
static void field_desc_show(struct seq_file *seq, u64 v,
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
463
((unsigned long long)v >> p->start) & mask);
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
513
static int tp_la_show(struct seq_file *seq, void *v, int idx)
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
515
const u64 *p = v;
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
521
static int tp_la_show2(struct seq_file *seq, void *v, int idx)
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
523
const u64 *p = v;
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
533
static int tp_la_show3(struct seq_file *seq, void *v, int idx)
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
629
const u64 *p = v;
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
695
static int ulprx_la_show(struct seq_file *seq, void *v, int idx)
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
697
const u32 *p = v;
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
699
if (v == SEQ_START_TOKEN)
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
71
static void *seq_tab_next(struct seq_file *seq, void *v, loff_t *pos)
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
73
v = seq_tab_get_idx(seq->private, *pos + 1);
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
742
static int pm_stats_show(struct seq_file *seq, void *v)
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
75
return v;
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
78
static void seq_tab_stop(struct seq_file *seq, void *v)
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
82
static int seq_tab_show(struct seq_file *seq, void *v)
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
821
static int tx_rate_show(struct seq_file *seq, void *v)
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
853
static int cctrl_tbl_show(struct seq_file *seq, void *v)
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
86
return tb->show(seq, v, ((char *)v - tb->data) / tb->width);
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
903
static int clk_show(struct seq_file *seq, void *v)
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
98
int (*show)(struct seq_file *seq, void *v, int i))
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
993
static int devlog_show(struct seq_file *seq, void *v)
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
995
if (v == SEQ_START_TOKEN)
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.h
48
int (*show)(struct seq_file *seq, void *v, int idx);
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.h
62
int (*show)(struct seq_file *seq, void *v, int i));
drivers/net/ethernet/chelsio/cxgb4/cxgb4_ethtool.c
1191
static int eeprom_rd_phys(struct adapter *adap, unsigned int phys_addr, u32 *v)
drivers/net/ethernet/chelsio/cxgb4/cxgb4_ethtool.c
1196
vaddr = pci_read_vpd(adap->pdev, vaddr, sizeof(u32), v);
drivers/net/ethernet/chelsio/cxgb4/cxgb4_ethtool.c
1200
static int eeprom_wr_phys(struct adapter *adap, unsigned int phys_addr, u32 v)
drivers/net/ethernet/chelsio/cxgb4/cxgb4_ethtool.c
1205
vaddr = pci_write_vpd(adap->pdev, vaddr, sizeof(u32), &v);
drivers/net/ethernet/chelsio/cxgb4/cxgb4_ethtool.c
1737
unsigned int v = pi->rss_mode;
drivers/net/ethernet/chelsio/cxgb4/cxgb4_ethtool.c
1742
if (v & FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F)
drivers/net/ethernet/chelsio/cxgb4/cxgb4_ethtool.c
1745
else if (v & FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F)
drivers/net/ethernet/chelsio/cxgb4/cxgb4_ethtool.c
1749
if ((v & FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F) &&
drivers/net/ethernet/chelsio/cxgb4/cxgb4_ethtool.c
1750
(v & FW_RSS_VI_CONFIG_CMD_UDPEN_F))
drivers/net/ethernet/chelsio/cxgb4/cxgb4_ethtool.c
1753
else if (v & FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F)
drivers/net/ethernet/chelsio/cxgb4/cxgb4_ethtool.c
1759
if (v & FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F)
drivers/net/ethernet/chelsio/cxgb4/cxgb4_ethtool.c
1763
if (v & FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F)
drivers/net/ethernet/chelsio/cxgb4/cxgb4_ethtool.c
1766
else if (v & FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F)
drivers/net/ethernet/chelsio/cxgb4/cxgb4_ethtool.c
1770
if ((v & FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F) &&
drivers/net/ethernet/chelsio/cxgb4/cxgb4_ethtool.c
1771
(v & FW_RSS_VI_CONFIG_CMD_UDPEN_F))
drivers/net/ethernet/chelsio/cxgb4/cxgb4_ethtool.c
1774
else if (v & FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F)
drivers/net/ethernet/chelsio/cxgb4/cxgb4_ethtool.c
1780
if (v & FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F)
drivers/net/ethernet/chelsio/cxgb4/cxgb4_ethtool.c
340
int v;
drivers/net/ethernet/chelsio/cxgb4/cxgb4_ethtool.c
342
v = t4_read_reg(adap, SGE_STAT_CFG_A);
drivers/net/ethernet/chelsio/cxgb4/cxgb4_ethtool.c
343
if (STATSOURCE_T5_G(v) == 7) {
drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
1250
u32 v, new_idx;
drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
1255
v = FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) |
drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
1260
&v, &new_idx);
drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
4172
u32 v;
drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
4219
v = t4_read_reg(adap, TP_PIO_DATA_A);
drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
4220
t4_write_reg(adap, TP_PIO_DATA_A, v & ~CSUM_HAS_PSEUDO_HDR_F);
drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
4228
v = 0x84218421;
drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
4230
&v, 1, TP_TX_SCHED_HDR_A);
drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
4232
&v, 1, TP_TX_SCHED_FIFO_A);
drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
4234
&v, 1, TP_TX_SCHED_PCMD_A);
drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
4758
u32 v, port_vec;
drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
4925
v =
drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
4928
ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, &v, &port_vec);
drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
678
u32 v = t4_read_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A));
drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
680
if (v & PFSW_F) {
drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
682
t4_write_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A), v);
drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
6921
u32 v;
drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
6923
v = t4_read_reg(adapter, LE_DB_HASH_CONFIG_A);
drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
6925
adapter->tids.nhash = 1 << HASHTIDSIZE_G(v);
drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
6926
v = t4_read_reg(adapter, LE_DB_TID_HASHBASE_A);
drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
6927
adapter->tids.hash_base = v / 4;
drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
6929
adapter->tids.nhash = HASHTBLSIZE_G(v) << 3;
drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
6930
v = t4_read_reg(adapter,
drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
6932
adapter->tids.hash_base = v;
drivers/net/ethernet/chelsio/cxgb4/l2t.c
656
static void *l2t_seq_next(struct seq_file *seq, void *v, loff_t *pos)
drivers/net/ethernet/chelsio/cxgb4/l2t.c
658
v = l2t_get_idx(seq, *pos);
drivers/net/ethernet/chelsio/cxgb4/l2t.c
660
return v;
drivers/net/ethernet/chelsio/cxgb4/l2t.c
663
static void l2t_seq_stop(struct seq_file *seq, void *v)
drivers/net/ethernet/chelsio/cxgb4/l2t.c
692
static int l2t_seq_show(struct seq_file *seq, void *v)
drivers/net/ethernet/chelsio/cxgb4/l2t.c
694
if (v == SEQ_START_TOKEN)
drivers/net/ethernet/chelsio/cxgb4/l2t.c
700
struct l2t_entry *e = v;
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
10265
unsigned int i, v;
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
10269
v = t4_read_reg(adap, TP_PACE_TABLE_A);
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
10270
pace_vals[i] = dack_ticks_to_usec(adap, v);
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
10287
unsigned int v, addr, bpt, cpt;
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
10291
t4_tp_tm_pio_read(adap, &v, 1, addr, sleep_ok);
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
10293
v >>= 16;
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
10294
bpt = (v >> 8) & 0xff;
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
10295
cpt = v & 0xff;
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
10299
v = (adap->params.vpd.cclk * 1000) / cpt; /* ticks/s */
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
10300
*kbps = (v * bpt) / 125;
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
10305
t4_tp_tm_pio_read(adap, &v, 1, addr, sleep_ok);
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
10307
v >>= 16;
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
10308
v &= 0xffff;
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
10309
*ipg = (10000 * v) / core_ticks_per_usec(adap);
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
2732
unsigned int v = enable ? 0xc : 0;
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
2733
int ret = pci_write_vpd(adapter->pdev, EEPROM_STAT_ADDR, 4, &v);
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
2861
int v;
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
2874
v = t4_wr_mbox(adapter, adapter->mbox, &cmd, sizeof(cmd), &rpl);
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
2875
if (v != FW_SUCCESS)
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
2876
return v;
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
292
u32 v;
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
366
v = MBOWNER_G(t4_read_reg(adap, ctl_reg));
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
367
for (i = 0; v == MBOX_OWNER_NONE && i < 3; i++)
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
368
v = MBOWNER_G(t4_read_reg(adap, ctl_reg));
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
369
if (v != MBOX_OWNER_DRV) {
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
373
ret = (v == MBOX_OWNER_FW) ? -EBUSY : -ETIMEDOUT;
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
401
v = t4_read_reg(adap, ctl_reg);
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
402
if (MBOWNER_G(v) == MBOX_OWNER_DRV) {
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
403
if (!(v & MBMSGVALID_F)) {
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
4452
u32 v = 0, perr;
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
4489
v |= perr;
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
4496
v |= perr;
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
4506
v |= perr;
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
4512
v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A, sge_intr_info);
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
4514
v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A,
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
4528
if (v != 0)
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
4839
unsigned int addr, cnt_addr, v;
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
4857
v = t4_read_reg(adapter, addr) & MEM_INT_MASK;
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
4858
if (v & PERR_INT_CAUSE_F)
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
4861
if (v & ECC_CE_INT_CAUSE_F) {
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
4872
if (v & ECC_UE_INT_CAUSE_F)
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
4876
t4_write_reg(adapter, addr, v);
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
4877
if (v & (PERR_INT_CAUSE_F | ECC_UE_INT_CAUSE_F))
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
4886
u32 v, status = t4_read_reg(adap, MA_INT_CAUSE_A);
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
4899
v = t4_read_reg(adap, MA_INT_WRAP_STATUS_A);
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
4902
MEM_WRAP_CLIENT_NUM_G(v),
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
4903
MEM_WRAP_ADDRESS_G(v) << 4);
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
4947
u32 v, int_cause_reg;
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
4954
v = t4_read_reg(adap, int_cause_reg);
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
4956
v &= TXFIFO_PRTY_ERR_F | RXFIFO_PRTY_ERR_F;
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
4957
if (!v)
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
4960
if (v & TXFIFO_PRTY_ERR_F)
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
4963
if (v & RXFIFO_PRTY_ERR_F)
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
4966
t4_write_reg(adap, PORT_REG(port, XGMAC_PORT_INT_CAUSE_A), v);
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
5170
unsigned int v;
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
5172
v = FW_RSS_IND_TBL_CMD_IQ0_V(*rsp);
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
5175
v |= FW_RSS_IND_TBL_CMD_IQ1_V(*rsp);
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
5178
v |= FW_RSS_IND_TBL_CMD_IQ2_V(*rsp);
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
5182
*qp++ = cpu_to_be32(v);
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
5740
u32 v;
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
5746
v = t4_read_reg(adap, TP_MTU_TABLE_A);
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
5747
mtus[i] = MTUVALUE_G(v);
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
5749
mtu_log[i] = MTUWIDTH_G(v);
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
5893
u64 v = bytes256 * adap->params.vpd.cclk;
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
5895
return v * 62 + v / 2;
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
5909
u32 v;
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
5911
v = t4_read_reg(adap, TP_TX_TRATE_A);
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
5912
nic_rate[0] = chan_rate(adap, TNLRATE0_G(v));
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
5913
nic_rate[1] = chan_rate(adap, TNLRATE1_G(v));
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
5915
nic_rate[2] = chan_rate(adap, TNLRATE2_G(v));
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
5916
nic_rate[3] = chan_rate(adap, TNLRATE3_G(v));
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
5919
v = t4_read_reg(adap, TP_TX_ORATE_A);
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
5920
ofld_rate[0] = chan_rate(adap, OFDRATE0_G(v));
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
5921
ofld_rate[1] = chan_rate(adap, OFDRATE1_G(v));
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
5923
ofld_rate[2] = chan_rate(adap, OFDRATE2_G(v));
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
5924
ofld_rate[3] = chan_rate(adap, OFDRATE3_G(v));
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
6844
u32 v;
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
6876
v = be32_to_cpu(c.err_to_clearinit);
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
6877
master_mbox = FW_HELLO_CMD_MBMASTER_G(v);
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
6879
if (v & FW_HELLO_CMD_ERR_F)
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
6881
else if (v & FW_HELLO_CMD_INIT_F)
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
6898
if ((v & (FW_HELLO_CMD_ERR_F|FW_HELLO_CMD_INIT_F)) == 0 &&
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
9411
u32 param, val, v;
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
9415
v = t4_read_reg(adap, TP_TIMER_RESOLUTION_A);
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
9416
adap->params.tp.tre = TIMERRESOLUTION_G(v);
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
9417
adap->params.tp.dack_re = DELAYEDACKRESOLUTION_G(v);
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
9471
v = t4_read_reg(adap, TP_OUT_CONFIG_A);
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
9472
adap->params.tp.rx_pkt_encap = (v & CRXPKTENC_F) ? 1 : 0;
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
95
u32 v = t4_read_reg(adapter, addr) & ~mask;
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
9501
v = t4_read_reg(adap, LE_3_DB_HASH_MASK_GEN_IPV4_T6_A);
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
9502
adap->params.tp.hash_filter_mask = v;
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
9503
v = t4_read_reg(adap, LE_4_DB_HASH_MASK_GEN_IPV4_T6_A);
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
9504
adap->params.tp.hash_filter_mask |= ((u64)v << 32);
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
97
t4_write_reg(adapter, addr, v | val);
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
9745
unsigned int i, v;
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
9752
v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
9754
*base++ = CIMQBASE_G(v) * 256;
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
9755
*size++ = CIMQSIZE_G(v) * 256;
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
9756
*thres++ = QUEFULLTHRSH_G(v) * 8; /* 8-byte unit */
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
9761
v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
9763
*base++ = CIMQBASE_G(v) * 256;
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
9764
*size++ = CIMQSIZE_G(v) * 256;
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
9824
unsigned int addr, v, nwords;
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
9833
v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
9835
addr = CIMQBASE_G(v) * 64; /* muliple of 256 -> muliple of 4 */
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
9836
nwords = CIMQSIZE_G(v) * 64; /* same */
drivers/net/ethernet/chelsio/cxgb4vf/cxgb4vf_main.c
1095
u32 v, pktcnt_idx;
drivers/net/ethernet/chelsio/cxgb4vf/cxgb4vf_main.c
1099
v = FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) |
drivers/net/ethernet/chelsio/cxgb4vf/cxgb4vf_main.c
1103
err = t4vf_set_params(adapter, 1, &v, &pktcnt_idx);
drivers/net/ethernet/chelsio/cxgb4vf/cxgb4vf_main.c
1967
static int mboxlog_show(struct seq_file *seq, void *v)
drivers/net/ethernet/chelsio/cxgb4vf/cxgb4vf_main.c
1974
if (v == SEQ_START_TOKEN) {
drivers/net/ethernet/chelsio/cxgb4vf/cxgb4vf_main.c
1982
entry_idx = log->cursor + ((uintptr_t)v - 2);
drivers/net/ethernet/chelsio/cxgb4vf/cxgb4vf_main.c
2018
static void *mboxlog_next(struct seq_file *seq, void *v, loff_t *pos)
drivers/net/ethernet/chelsio/cxgb4vf/cxgb4vf_main.c
2024
static void mboxlog_stop(struct seq_file *seq, void *v)
drivers/net/ethernet/chelsio/cxgb4vf/cxgb4vf_main.c
2041
static int sge_qinfo_show(struct seq_file *seq, void *v)
drivers/net/ethernet/chelsio/cxgb4vf/cxgb4vf_main.c
2045
int qs, r = (uintptr_t)v - 1;
drivers/net/ethernet/chelsio/cxgb4vf/cxgb4vf_main.c
2050
#define S3(fmt_spec, s, v) \
drivers/net/ethernet/chelsio/cxgb4vf/cxgb4vf_main.c
2054
seq_printf(seq, " %16" fmt_spec, v); \
drivers/net/ethernet/chelsio/cxgb4vf/cxgb4vf_main.c
2057
#define S(s, v) S3("s", s, v)
drivers/net/ethernet/chelsio/cxgb4vf/cxgb4vf_main.c
2058
#define T(s, v) S3("u", s, txq[qs].v)
drivers/net/ethernet/chelsio/cxgb4vf/cxgb4vf_main.c
2059
#define R(s, v) S3("u", s, rxq[qs].v)
drivers/net/ethernet/chelsio/cxgb4vf/cxgb4vf_main.c
2151
static void sge_queue_stop(struct seq_file *seq, void *v)
drivers/net/ethernet/chelsio/cxgb4vf/cxgb4vf_main.c
2155
static void *sge_queue_next(struct seq_file *seq, void *v, loff_t *pos)
drivers/net/ethernet/chelsio/cxgb4vf/cxgb4vf_main.c
2177
static int sge_qstats_show(struct seq_file *seq, void *v)
drivers/net/ethernet/chelsio/cxgb4vf/cxgb4vf_main.c
2181
int qs, r = (uintptr_t)v - 1;
drivers/net/ethernet/chelsio/cxgb4vf/cxgb4vf_main.c
2186
#define S3(fmt, s, v) \
drivers/net/ethernet/chelsio/cxgb4vf/cxgb4vf_main.c
2190
seq_printf(seq, " %8" fmt, v); \
drivers/net/ethernet/chelsio/cxgb4vf/cxgb4vf_main.c
2193
#define S(s, v) S3("s", s, v)
drivers/net/ethernet/chelsio/cxgb4vf/cxgb4vf_main.c
2195
#define T3(fmt, s, v) S3(fmt, s, txq[qs].v)
drivers/net/ethernet/chelsio/cxgb4vf/cxgb4vf_main.c
2196
#define T(s, v) T3("lu", s, v)
drivers/net/ethernet/chelsio/cxgb4vf/cxgb4vf_main.c
2198
#define R3(fmt, s, v) S3(fmt, s, rxq[qs].v)
drivers/net/ethernet/chelsio/cxgb4vf/cxgb4vf_main.c
2199
#define R(s, v) R3("lu", s, v)
drivers/net/ethernet/chelsio/cxgb4vf/cxgb4vf_main.c
2280
static void sge_qstats_stop(struct seq_file *seq, void *v)
drivers/net/ethernet/chelsio/cxgb4vf/cxgb4vf_main.c
2284
static void *sge_qstats_next(struct seq_file *seq, void *v, loff_t *pos)
drivers/net/ethernet/chelsio/cxgb4vf/cxgb4vf_main.c
2304
static int resources_show(struct seq_file *seq, void *v)
drivers/net/ethernet/chelsio/cxgb4vf/cxgb4vf_main.c
2333
static int interfaces_show(struct seq_file *seq, void *v)
drivers/net/ethernet/chelsio/cxgb4vf/cxgb4vf_main.c
2335
if (v == SEQ_START_TOKEN) {
drivers/net/ethernet/chelsio/cxgb4vf/cxgb4vf_main.c
2339
int pidx = (uintptr_t)v - 2;
drivers/net/ethernet/chelsio/cxgb4vf/cxgb4vf_main.c
2363
static void *interfaces_next(struct seq_file *seq, void *v, loff_t *pos)
drivers/net/ethernet/chelsio/cxgb4vf/cxgb4vf_main.c
2369
static void interfaces_stop(struct seq_file *seq, void *v)
drivers/net/ethernet/chelsio/cxgb4vf/t4vf_hw.c
1000
if (v)
drivers/net/ethernet/chelsio/cxgb4vf/t4vf_hw.c
1001
return v;
drivers/net/ethernet/chelsio/cxgb4vf/t4vf_hw.c
1019
int v;
drivers/net/ethernet/chelsio/cxgb4vf/t4vf_hw.c
1030
v = t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), &rpl);
drivers/net/ethernet/chelsio/cxgb4vf/t4vf_hw.c
1031
if (v)
drivers/net/ethernet/chelsio/cxgb4vf/t4vf_hw.c
1032
return v;
drivers/net/ethernet/chelsio/cxgb4vf/t4vf_hw.c
1094
int v;
drivers/net/ethernet/chelsio/cxgb4vf/t4vf_hw.c
1106
v = t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), &rpl);
drivers/net/ethernet/chelsio/cxgb4vf/t4vf_hw.c
1107
if (v)
drivers/net/ethernet/chelsio/cxgb4vf/t4vf_hw.c
1108
return v;
drivers/net/ethernet/chelsio/cxgb4vf/t4vf_hw.c
1147
int v;
drivers/net/ethernet/chelsio/cxgb4vf/t4vf_hw.c
1155
v = t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), &rpl);
drivers/net/ethernet/chelsio/cxgb4vf/t4vf_hw.c
1156
if (v)
drivers/net/ethernet/chelsio/cxgb4vf/t4vf_hw.c
1157
return v;
drivers/net/ethernet/chelsio/cxgb4vf/t4vf_hw.c
1340
int v;
drivers/net/ethernet/chelsio/cxgb4vf/t4vf_hw.c
1354
v = t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), &rpl);
drivers/net/ethernet/chelsio/cxgb4vf/t4vf_hw.c
1355
if (v)
drivers/net/ethernet/chelsio/cxgb4vf/t4vf_hw.c
1356
return v;
drivers/net/ethernet/chelsio/cxgb4vf/t4vf_hw.c
137
u32 v, mbox_data;
drivers/net/ethernet/chelsio/cxgb4vf/t4vf_hw.c
210
v = MBOWNER_G(t4_read_reg(adapter, mbox_ctl));
drivers/net/ethernet/chelsio/cxgb4vf/t4vf_hw.c
211
for (i = 0; v == MBOX_OWNER_NONE && i < 3; i++)
drivers/net/ethernet/chelsio/cxgb4vf/t4vf_hw.c
212
v = MBOWNER_G(t4_read_reg(adapter, mbox_ctl));
drivers/net/ethernet/chelsio/cxgb4vf/t4vf_hw.c
213
if (v != MBOX_OWNER_DRV) {
drivers/net/ethernet/chelsio/cxgb4vf/t4vf_hw.c
217
ret = (v == MBOX_OWNER_FW) ? -EBUSY : -ETIMEDOUT;
drivers/net/ethernet/chelsio/cxgb4vf/t4vf_hw.c
263
v = t4_read_reg(adapter, mbox_ctl);
drivers/net/ethernet/chelsio/cxgb4vf/t4vf_hw.c
264
if (MBOWNER_G(v) == MBOX_OWNER_DRV) {
drivers/net/ethernet/chelsio/cxgb4vf/t4vf_hw.c
269
if ((v & MBMSGVALID_F) == 0) {
drivers/net/ethernet/chelsio/cxgb4vf/t4vf_hw.c
285
v = be64_to_cpu(cmd_rpl[0]);
drivers/net/ethernet/chelsio/cxgb4vf/t4vf_hw.c
304
return -FW_CMD_RETVAL_G(v);
drivers/net/ethernet/chelsio/cxgb4vf/t4vf_hw.c
851
int v;
drivers/net/ethernet/chelsio/cxgb4vf/t4vf_hw.c
867
v = t4vf_query_params(adapter, 7, params, vals);
drivers/net/ethernet/chelsio/cxgb4vf/t4vf_hw.c
868
if (v)
drivers/net/ethernet/chelsio/cxgb4vf/t4vf_hw.c
869
return v;
drivers/net/ethernet/chelsio/cxgb4vf/t4vf_hw.c
891
v = t4vf_query_params(adapter, 1, params, vals);
drivers/net/ethernet/chelsio/cxgb4vf/t4vf_hw.c
892
if (v != FW_SUCCESS) {
drivers/net/ethernet/chelsio/cxgb4vf/t4vf_hw.c
896
return v;
drivers/net/ethernet/chelsio/cxgb4vf/t4vf_hw.c
905
v = t4vf_query_params(adapter, 2, params, vals);
drivers/net/ethernet/chelsio/cxgb4vf/t4vf_hw.c
906
if (v)
drivers/net/ethernet/chelsio/cxgb4vf/t4vf_hw.c
907
return v;
drivers/net/ethernet/chelsio/cxgb4vf/t4vf_hw.c
924
v = t4vf_query_params(adapter, 2, params, vals);
drivers/net/ethernet/chelsio/cxgb4vf/t4vf_hw.c
925
if (v != FW_SUCCESS) {
drivers/net/ethernet/chelsio/cxgb4vf/t4vf_hw.c
929
return v;
drivers/net/ethernet/chelsio/cxgb4vf/t4vf_hw.c
970
int v;
drivers/net/ethernet/chelsio/cxgb4vf/t4vf_hw.c
974
v = t4vf_query_params(adapter, 1, params, vals);
drivers/net/ethernet/chelsio/cxgb4vf/t4vf_hw.c
975
if (v)
drivers/net/ethernet/chelsio/cxgb4vf/t4vf_hw.c
976
return v;
drivers/net/ethernet/chelsio/cxgb4vf/t4vf_hw.c
993
int v;
drivers/net/ethernet/chelsio/cxgb4vf/t4vf_hw.c
999
v = t4vf_query_params(adapter, 2, params, vals);
drivers/net/ethernet/chelsio/libcxgb/libcxgb_ppm.h
273
u32 v = val >> tformat->free_bits;
drivers/net/ethernet/chelsio/libcxgb/libcxgb_ppm.h
275
if (v) {
drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.h
722
#define DPAA2_PTP_SINGLE_CORRECTION_OFF(v) ((v) << 8)
drivers/net/ethernet/freescale/enetc/enetc.c
1079
struct enetc_int_vector *v = data;
drivers/net/ethernet/freescale/enetc/enetc.c
1085
enetc_wr_reg_hot(v->rbier, 0);
drivers/net/ethernet/freescale/enetc/enetc.c
1086
enetc_wr_reg_hot(v->ricr1, v->rx_ictt);
drivers/net/ethernet/freescale/enetc/enetc.c
1088
for_each_set_bit(i, &v->tx_rings_map, ENETC_MAX_NUM_TXQS)
drivers/net/ethernet/freescale/enetc/enetc.c
1089
enetc_wr_reg_hot(v->tbier_base + ENETC_BDR_OFF(i), 0);
drivers/net/ethernet/freescale/enetc/enetc.c
1093
napi_schedule(&v->napi);
drivers/net/ethernet/freescale/enetc/enetc.c
1103
struct enetc_int_vector *v =
drivers/net/ethernet/freescale/enetc/enetc.c
1105
struct enetc_ndev_priv *priv = netdev_priv(v->rx_ring.ndev);
drivers/net/ethernet/freescale/enetc/enetc.c
1107
v->rx_ictt = enetc_usecs_to_cycles(moder.usec, priv->sysclk_freq);
drivers/net/ethernet/freescale/enetc/enetc.c
1111
static void enetc_rx_net_dim(struct enetc_int_vector *v)
drivers/net/ethernet/freescale/enetc/enetc.c
1115
v->comp_cnt++;
drivers/net/ethernet/freescale/enetc/enetc.c
1117
if (!v->rx_napi_work)
drivers/net/ethernet/freescale/enetc/enetc.c
1120
dim_update_sample(v->comp_cnt,
drivers/net/ethernet/freescale/enetc/enetc.c
1121
v->rx_ring.stats.packets,
drivers/net/ethernet/freescale/enetc/enetc.c
1122
v->rx_ring.stats.bytes,
drivers/net/ethernet/freescale/enetc/enetc.c
1124
net_dim(&v->rx_dim, &dim_sample);
drivers/net/ethernet/freescale/enetc/enetc.c
2111
*v = container_of(napi, struct enetc_int_vector, napi);
drivers/net/ethernet/freescale/enetc/enetc.c
2112
struct enetc_bdr *rx_ring = &v->rx_ring;
drivers/net/ethernet/freescale/enetc/enetc.c
2120
for (i = 0; i < v->count_tx_rings; i++)
drivers/net/ethernet/freescale/enetc/enetc.c
2121
if (!enetc_clean_tx_ring(&v->tx_ring[i], budget))
drivers/net/ethernet/freescale/enetc/enetc.c
2133
v->rx_napi_work = true;
drivers/net/ethernet/freescale/enetc/enetc.c
2140
if (likely(v->rx_dim_en))
drivers/net/ethernet/freescale/enetc/enetc.c
2141
enetc_rx_net_dim(v);
drivers/net/ethernet/freescale/enetc/enetc.c
2143
v->rx_napi_work = false;
drivers/net/ethernet/freescale/enetc/enetc.c
2147
enetc_wr_reg_hot(v->rbier, ENETC_RBIER_RXTIE);
drivers/net/ethernet/freescale/enetc/enetc.c
2149
for_each_set_bit(i, &v->tx_rings_map, ENETC_MAX_NUM_TXQS)
drivers/net/ethernet/freescale/enetc/enetc.c
2150
enetc_wr_reg_hot(v->tbier_base + ENETC_BDR_OFF(i),
drivers/net/ethernet/freescale/enetc/enetc.c
2794
struct enetc_int_vector *v = priv->int_vector[i];
drivers/net/ethernet/freescale/enetc/enetc.c
2797
snprintf(v->name, sizeof(v->name), "%s-rxtx%d",
drivers/net/ethernet/freescale/enetc/enetc.c
2799
err = request_irq(irq, enetc_msix, IRQF_NO_AUTOEN, v->name, v);
drivers/net/ethernet/freescale/enetc/enetc.c
2805
v->tbier_base = hw->reg + ENETC_BDR(TX, 0, ENETC_TBIER);
drivers/net/ethernet/freescale/enetc/enetc.c
2806
v->rbier = hw->reg + ENETC_BDR(RX, i, ENETC_RBIER);
drivers/net/ethernet/freescale/enetc/enetc.c
2807
v->ricr1 = hw->reg + ENETC_BDR(RX, i, ENETC_RBICR1);
drivers/net/ethernet/freescale/enetc/enetc.c
2811
for (j = 0; j < v->count_tx_rings; j++) {
drivers/net/ethernet/freescale/enetc/enetc.c
2812
int idx = v->tx_ring[j].index;
drivers/net/ethernet/freescale/enetc/enetc.c
3463
struct enetc_int_vector *v;
drivers/net/ethernet/freescale/enetc/enetc.c
3467
v = kzalloc_flex(*v, tx_ring, v_tx_rings);
drivers/net/ethernet/freescale/enetc/enetc.c
3468
if (!v)
drivers/net/ethernet/freescale/enetc/enetc.c
3471
priv->int_vector[i] = v;
drivers/net/ethernet/freescale/enetc/enetc.c
3472
bdr = &v->rx_ring;
drivers/net/ethernet/freescale/enetc/enetc.c
3494
v->rx_ictt = 0x1;
drivers/net/ethernet/freescale/enetc/enetc.c
3495
v->rx_dim_en = true;
drivers/net/ethernet/freescale/enetc/enetc.c
3498
INIT_WORK(&v->rx_dim.work, enetc_rx_dim_work);
drivers/net/ethernet/freescale/enetc/enetc.c
3499
netif_napi_add(priv->ndev, &v->napi, enetc_poll);
drivers/net/ethernet/freescale/enetc/enetc.c
3500
v->count_tx_rings = v_tx_rings;
drivers/net/ethernet/freescale/enetc/enetc.c
3507
__set_bit(idx, &v->tx_rings_map);
drivers/net/ethernet/freescale/enetc/enetc.c
3508
bdr = &v->tx_ring[j];
drivers/net/ethernet/freescale/enetc/enetc.c
3521
kfree(v);
drivers/net/ethernet/freescale/enetc/enetc.c
3528
struct enetc_int_vector *v = priv->int_vector[i];
drivers/net/ethernet/freescale/enetc/enetc.c
3529
struct enetc_bdr *rx_ring = &v->rx_ring;
drivers/net/ethernet/freescale/enetc/enetc.c
3534
netif_napi_del(&v->napi);
drivers/net/ethernet/freescale/enetc/enetc.c
3535
cancel_work_sync(&v->rx_dim.work);
drivers/net/ethernet/freescale/enetc/enetc.c
3537
for (j = 0; j < v->count_tx_rings; j++) {
drivers/net/ethernet/freescale/enetc/enetc.c
3544
kfree(v);
drivers/net/ethernet/freescale/enetc/enetc_ethtool.c
850
struct enetc_int_vector *v = priv->int_vector[0];
drivers/net/ethernet/freescale/enetc/enetc_ethtool.c
854
ic->rx_coalesce_usecs = enetc_cycles_to_usecs(v->rx_ictt, clk_freq);
drivers/net/ethernet/freescale/enetc/enetc_ethtool.c
901
struct enetc_int_vector *v = priv->int_vector[i];
drivers/net/ethernet/freescale/enetc/enetc_ethtool.c
903
v->rx_ictt = rx_ictt;
drivers/net/ethernet/freescale/enetc/enetc_ethtool.c
904
v->rx_dim_en = !!(ic_mode & ENETC_IC_RX_ADAPTIVE);
drivers/net/ethernet/freescale/enetc/enetc_hw.h
286
#define ENETC_SET_SINGLE_STEP_OFFSET(v) (((v) & 0xff) << 8)
drivers/net/ethernet/freescale/enetc/ntmp_private.h
70
#define NTMP_TBLV_QACT(v, a) (FIELD_PREP(NTMP_TBL_VER, (v)) | \
drivers/net/ethernet/freescale/fec.h
317
#define RCMR_CMP_CFG(v, n) (((v) & 0x7) << (n << 2))
drivers/net/ethernet/freescale/fec_main.c
270
#define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
drivers/net/ethernet/freescale/fec_main.c
271
#define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
drivers/net/ethernet/freescale/fec_main.c
273
#define FEC_MMFR_DATA(v) (v & 0xffff)
drivers/net/ethernet/fujitsu/fmvj18x_cs.c
67
#define INT_MODULE_PARM(n, v) static int n = v; module_param(n, int, 0)
drivers/net/ethernet/fungible/funeth/funeth_main.c
49
u8 v[ADMIN_SQE_SIZE];
drivers/net/ethernet/fungible/funeth/funeth_main.c
85
u8 v[ADMIN_SQE_SIZE];
drivers/net/ethernet/hisilicon/hns/hns_enet.c
844
int budget, void *v)
drivers/net/ethernet/hisilicon/hns/hns_enet.c
881
((void (*)(struct hns_nic_ring_data *, struct sk_buff *))v)(
drivers/net/ethernet/hisilicon/hns/hns_enet.c
972
int budget, void *v)
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
861
#define calc_x(x, k, v) ((x) = ~(k) & (v))
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
862
#define calc_y(y, k, v) ((y) = (k) & (v))
drivers/net/ethernet/i825xx/82596.c
402
u32 v = (u32) (c) | (u32) (x);
drivers/net/ethernet/i825xx/82596.c
403
v = ((u32) (v) << 16) | ((u32) (v) >> 16);
drivers/net/ethernet/i825xx/82596.c
404
*(volatile u32 *) dev->base_addr = v;
drivers/net/ethernet/i825xx/82596.c
406
*(volatile u32 *) dev->base_addr = v;
drivers/net/ethernet/i825xx/lasi_82596.c
124
u32 v = (u32) (c) | (u32) (x);
drivers/net/ethernet/i825xx/lasi_82596.c
128
a = v >> 16;
drivers/net/ethernet/i825xx/lasi_82596.c
129
b = v & 0xffff;
drivers/net/ethernet/i825xx/lasi_82596.c
131
a = v & 0xffff;
drivers/net/ethernet/i825xx/lasi_82596.c
132
b = v >> 16;
drivers/net/ethernet/i825xx/lib82596.c
367
static inline dma_addr_t virt_to_dma(struct i596_private *lp, volatile void *v)
drivers/net/ethernet/i825xx/lib82596.c
369
return lp->dma_addr + ((unsigned long)v - (unsigned long)lp->dma);
drivers/net/ethernet/i825xx/sni_82596.c
56
u32 v = (u32) (c) | (u32) (x);
drivers/net/ethernet/i825xx/sni_82596.c
59
writew(v & 0xffff, lp->mpu_port);
drivers/net/ethernet/i825xx/sni_82596.c
62
writew(v >> 16, lp->mpu_port);
drivers/net/ethernet/i825xx/sni_82596.c
64
writel(v, lp->mpu_port);
drivers/net/ethernet/i825xx/sni_82596.c
67
writel(v, lp->mpu_port);
drivers/net/ethernet/intel/fm10k/fm10k_debugfs.c
21
void __always_unused *v,
drivers/net/ethernet/intel/fm10k/fm10k_debugfs.c
30
void __always_unused *v)
drivers/net/ethernet/intel/fm10k/fm10k_debugfs.c
43
static int fm10k_dbg_tx_desc_seq_show(struct seq_file *s, void *v)
drivers/net/ethernet/intel/fm10k/fm10k_debugfs.c
46
int i = *(loff_t *)v;
drivers/net/ethernet/intel/fm10k/fm10k_debugfs.c
70
static int fm10k_dbg_rx_desc_seq_show(struct seq_file *s, void *v)
drivers/net/ethernet/intel/fm10k/fm10k_debugfs.c
73
int i = *(loff_t *)v;
drivers/net/ethernet/intel/i40e/i40e_dcb_nl.c
951
int v, err;
drivers/net/ethernet/intel/i40e/i40e_dcb_nl.c
953
i40e_pf_for_each_vsi(pf, v, vsi)
drivers/net/ethernet/intel/i40e/i40e_debugfs.c
867
unsigned int v;
drivers/net/ethernet/intel/i40e/i40e_debugfs.c
871
cnt = sscanf(&cmd_buf[8], "%i %u", &vsi_seid, &v);
drivers/net/ethernet/intel/i40e/i40e_debugfs.c
885
vid = v;
drivers/net/ethernet/intel/i40e/i40e_main.c
10379
int v, ret;
drivers/net/ethernet/intel/i40e/i40e_main.c
10428
i40e_pf_for_each_vsi(pf, v, vsi) {
drivers/net/ethernet/intel/i40e/i40e_main.c
10438
v, ret);
drivers/net/ethernet/intel/i40e/i40e_main.c
10712
u32 v;
drivers/net/ethernet/intel/i40e/i40e_main.c
10725
i40e_pf_for_each_vsi(pf, v, vsi) {
drivers/net/ethernet/intel/i40e/i40e_main.c
10844
int v;
drivers/net/ethernet/intel/i40e/i40e_main.c
10983
i40e_pf_for_each_veb(pf, v, veb) {
drivers/net/ethernet/intel/i40e/i40e_main.c
14858
int v;
drivers/net/ethernet/intel/i40e/i40e_main.c
14865
v = i40e_veb_mem_alloc(pf);
drivers/net/ethernet/intel/i40e/i40e_main.c
14866
if (v < 0)
drivers/net/ethernet/intel/i40e/i40e_main.c
14868
pf->lan_veb = v;
drivers/net/ethernet/intel/i40e/i40e_main.c
2890
int v;
drivers/net/ethernet/intel/i40e/i40e_main.c
2901
i40e_pf_for_each_vsi(pf, v, vsi) {
drivers/net/ethernet/intel/i40e/i40e_main.c
5276
int v;
drivers/net/ethernet/intel/i40e/i40e_main.c
5278
i40e_pf_for_each_vsi(pf, v, vsi)
drivers/net/ethernet/intel/i40e/i40e_main.c
5289
int v;
drivers/net/ethernet/intel/i40e/i40e_main.c
5291
i40e_pf_for_each_vsi(pf, v, vsi)
drivers/net/ethernet/intel/i40e/i40e_main.c
5354
int v, ret = 0;
drivers/net/ethernet/intel/i40e/i40e_main.c
5356
i40e_pf_for_each_vsi(pf, v, vsi) {
drivers/net/ethernet/intel/i40e/i40e_main.c
6800
int v;
drivers/net/ethernet/intel/i40e/i40e_main.c
6807
i40e_pf_for_each_veb(pf, v, veb) {
drivers/net/ethernet/intel/i40e/i40e_main.c
6818
i40e_pf_for_each_vsi(pf, v, vsi) {
drivers/net/ethernet/intel/ice/ice_dcb_lib.c
747
int v, ret;
drivers/net/ethernet/intel/ice/ice_dcb_lib.c
750
ice_for_each_vsi(pf, v) {
drivers/net/ethernet/intel/ice/ice_dcb_lib.c
751
struct ice_vsi *vsi = pf->vsi[v];
drivers/net/ethernet/intel/ice/ice_lib.c
2080
int (*eth_fltr)(struct ice_vsi *v, u16 type, u16 flag,
drivers/net/ethernet/intel/ice/ice_main.c
125
u32 v;
drivers/net/ethernet/intel/ice/ice_main.c
127
ice_for_each_vsi(pf, v)
drivers/net/ethernet/intel/ice/ice_main.c
128
if (pf->vsi[v] && pf->vsi[v]->type == ICE_VSI_PF) {
drivers/net/ethernet/intel/ice/ice_main.c
129
vsi = pf->vsi[v];
drivers/net/ethernet/intel/ice/ice_main.c
491
int v;
drivers/net/ethernet/intel/ice/ice_main.c
498
ice_for_each_vsi(pf, v)
drivers/net/ethernet/intel/ice/ice_main.c
499
if (pf->vsi[v] && ice_vsi_fltr_changed(pf->vsi[v]) &&
drivers/net/ethernet/intel/ice/ice_main.c
500
ice_vsi_sync_fltr(pf->vsi[v])) {
drivers/net/ethernet/intel/ice/ice_main.c
515
int v;
drivers/net/ethernet/intel/ice/ice_main.c
517
ice_for_each_vsi(pf, v)
drivers/net/ethernet/intel/ice/ice_main.c
518
if (pf->vsi[v])
drivers/net/ethernet/intel/ice/ice_main.c
519
ice_dis_vsi(pf->vsi[v], locked);
drivers/net/ethernet/intel/ice/ice_main.c
5496
u32 v;
drivers/net/ethernet/intel/ice/ice_main.c
5507
ice_for_each_vsi(pf, v)
drivers/net/ethernet/intel/ice/ice_main.c
5508
if (pf->vsi[v])
drivers/net/ethernet/intel/ice/ice_main.c
5509
pf->vsi[v]->vsi_num = 0;
drivers/net/ethernet/intel/ice/ice_main.c
5527
int ret, v;
drivers/net/ethernet/intel/ice/ice_main.c
5540
ice_for_each_vsi(pf, v) {
drivers/net/ethernet/intel/ice/ice_main.c
5541
if (!pf->vsi[v])
drivers/net/ethernet/intel/ice/ice_main.c
5544
ret = ice_vsi_alloc_q_vectors(pf->vsi[v]);
drivers/net/ethernet/intel/ice/ice_main.c
5547
ice_vsi_map_rings_to_vectors(pf->vsi[v]);
drivers/net/ethernet/intel/ice/ice_main.c
5549
ice_vsi_set_napi_queues(pf->vsi[v]);
drivers/net/ethernet/intel/ice/ice_main.c
5563
while (v--)
drivers/net/ethernet/intel/ice/ice_main.c
5564
if (pf->vsi[v]) {
drivers/net/ethernet/intel/ice/ice_main.c
5566
ice_vsi_clear_napi_queues(pf->vsi[v]);
drivers/net/ethernet/intel/ice/ice_main.c
5568
ice_vsi_free_q_vectors(pf->vsi[v]);
drivers/net/ethernet/intel/ice/ice_main.c
5585
int disabled, v;
drivers/net/ethernet/intel/ice/ice_main.c
5632
ice_for_each_vsi(pf, v) {
drivers/net/ethernet/intel/ice/ice_main.c
5633
if (!pf->vsi[v])
drivers/net/ethernet/intel/ice/ice_main.c
5636
ice_vsi_clear_napi_queues(pf->vsi[v]);
drivers/net/ethernet/intel/ice/ice_main.c
5638
ice_vsi_free_q_vectors(pf->vsi[v]);
drivers/net/ethernet/intel/ice/ice_main.c
8225
int rem, v, err = 0;
drivers/net/ethernet/intel/ice/ice_main.c
8244
ice_for_each_vsi(pf, v) {
drivers/net/ethernet/intel/ice/ice_main.c
8245
if (!pf->vsi[v])
drivers/net/ethernet/intel/ice/ice_main.c
8247
err = ice_vsi_update_bridge_mode(pf->vsi[v], mode);
drivers/net/ethernet/intel/ice/ice_parser_rt.c
144
static u16 ice_bit_rev_u16(u16 v, int len)
drivers/net/ethernet/intel/ice/ice_parser_rt.c
146
return bitrev16(v) >> (BITS_PER_TYPE(v) - len);
drivers/net/ethernet/intel/ice/ice_parser_rt.c
149
static u32 ice_bit_rev_u32(u32 v, int len)
drivers/net/ethernet/intel/ice/ice_parser_rt.c
151
return bitrev32(v) >> (BITS_PER_TYPE(v) - len);
drivers/net/ethernet/intel/ice/ice_sriov.c
108
for (v = first; v <= last; v++) {
drivers/net/ethernet/intel/ice/ice_sriov.c
113
wr32(hw, GLINT_VECT2FUNC(v), reg);
drivers/net/ethernet/intel/ice/ice_sriov.c
233
int pf_based_first_msix, pf_based_last_msix, v;
drivers/net/ethernet/intel/ice/ice_sriov.c
260
for (v = pf_based_first_msix; v <= pf_based_last_msix; v++) {
drivers/net/ethernet/intel/ice/ice_sriov.c
263
wr32(hw, GLINT_VECT2FUNC(v), reg);
drivers/net/ethernet/intel/ice/ice_sriov.c
94
int first, last, v;
drivers/net/ethernet/intel/idpf/idpf_txrx.h
318
#define idpf_queue_assign(f, q, v) \
drivers/net/ethernet/intel/idpf/idpf_txrx.h
319
__assign_bit(__IDPF_Q_##f, (q)->flags, v)
drivers/net/ethernet/intel/ixgbevf/vf.h
169
#define IXGBE_WRITE_REG(h, r, v) ixgbe_write_reg(h, r, v)
drivers/net/ethernet/intel/ixgbevf/vf.h
180
#define IXGBE_WRITE_REG_ARRAY(h, r, o, v) ixgbe_write_reg_array(h, r, o, v)
drivers/net/ethernet/intel/libie/fwlog.c
383
static int libie_debugfs_module_show(struct seq_file *s, void *v)
drivers/net/ethernet/marvell/mv643xx_eth.c
1822
u32 v;
drivers/net/ethernet/marvell/mv643xx_eth.c
1824
v = 0;
drivers/net/ethernet/marvell/mv643xx_eth.c
1826
v |= 0x00000001;
drivers/net/ethernet/marvell/mv643xx_eth.c
1828
v |= 0x00000100;
drivers/net/ethernet/marvell/mv643xx_eth.c
1830
v |= 0x00010000;
drivers/net/ethernet/marvell/mv643xx_eth.c
1832
v |= 0x01000000;
drivers/net/ethernet/marvell/mv643xx_eth.c
1835
wrl(mp, off, v);
drivers/net/ethernet/marvell/mvneta.c
54
#define MVNETA_RXQ_NON_OCCUPIED(v) ((v) << 16)
drivers/net/ethernet/marvell/mvpp2/mvpp2.h
395
#define MVPP2_TXP_REFILL_PERIOD_MASK(v) ((v) << 20)
drivers/net/ethernet/marvell/mvpp2/mvpp2.h
401
#define MVPP2_TXQ_REFILL_PERIOD_MASK(v) ((v) << 20)
drivers/net/ethernet/marvell/mvpp2/mvpp2.h
465
#define MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(v) (((v) << 6) & \
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
1488
struct mvpp2_queue_vector *v = port->qvecs + i;
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
1490
if (v->type != MVPP2_QUEUE_VECTOR_SHARED)
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
1493
mvpp2_thread_write(port->priv, v->sw_thread_id,
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
1495
mvpp2_thread_write(port->priv, v->sw_thread_id,
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
5853
struct mvpp2_queue_vector *v = &port->qvecs[0];
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
5855
v->first_rxq = 0;
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
5856
v->nrxqs = port->nrxqs;
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
5857
v->type = MVPP2_QUEUE_VECTOR_SHARED;
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
5858
v->sw_thread_id = 0;
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
5859
v->sw_thread_mask = *cpumask_bits(cpu_online_mask);
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
5860
v->port = port;
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
5861
v->irq = irq_of_parse_and_map(port_node, 0);
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
5862
if (v->irq <= 0)
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
5864
netif_napi_add(port->dev, &v->napi, mvpp2_poll);
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
5875
struct mvpp2_queue_vector *v;
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
5890
v = port->qvecs + i;
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
5892
v->port = port;
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
5893
v->type = MVPP2_QUEUE_VECTOR_PRIVATE;
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
5894
v->sw_thread_id = i;
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
5895
v->sw_thread_mask = BIT(i);
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
5903
v->first_rxq = i;
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
5904
v->nrxqs = 1;
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
5907
v->first_rxq = 0;
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
5908
v->nrxqs = port->nrxqs;
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
5909
v->type = MVPP2_QUEUE_VECTOR_SHARED;
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
5916
v->irq = of_irq_get_byname(port_node, irqname);
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
5918
v->irq = fwnode_irq_get(port->fwnode, i);
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
5919
if (v->irq <= 0) {
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
5924
netif_napi_add(port->dev, &v->napi, mvpp2_poll);
drivers/net/ethernet/marvell/prestera/prestera_hw.c
549
u8 v; /* e.g. PRESTERA_IPV4 */
drivers/net/ethernet/marvell/prestera/prestera_pci.c
33
#define PRESTERA_FW_VER_MAJ(v) ((v) / PRESTERA_FW_VER_MAJ_MUL)
drivers/net/ethernet/marvell/prestera/prestera_pci.c
35
#define PRESTERA_FW_VER_MIN(v) \
drivers/net/ethernet/marvell/prestera/prestera_pci.c
36
(((v) - (PRESTERA_FW_VER_MAJ(v) * PRESTERA_FW_VER_MAJ_MUL)) / \
drivers/net/ethernet/marvell/prestera/prestera_pci.c
39
#define PRESTERA_FW_VER_PATCH(v) \
drivers/net/ethernet/marvell/prestera/prestera_pci.c
40
((v) - (PRESTERA_FW_VER_MAJ(v) * PRESTERA_FW_VER_MAJ_MUL) - \
drivers/net/ethernet/marvell/prestera/prestera_pci.c
41
(PRESTERA_FW_VER_MIN(v) * PRESTERA_FW_VER_MIN_MUL))
drivers/net/ethernet/marvell/prestera/prestera_router.c
100
key->addr.v = PRESTERA_IPV4;
drivers/net/ethernet/marvell/prestera/prestera_router.c
1054
if (nc->key.addr.v == PRESTERA_IPV4) {
drivers/net/ethernet/marvell/prestera/prestera_router.c
112
nk->addr.v = PRESTERA_IPV4;
drivers/net/ethernet/marvell/prestera/prestera_router.c
115
nk->addr.v = PRESTERA_IPV6;
drivers/net/ethernet/marvell/prestera/prestera_router.c
156
key->addr.v = PRESTERA_IPV4;
drivers/net/ethernet/marvell/prestera/prestera_router.c
286
if (addr->v == PRESTERA_IPV4)
drivers/net/ethernet/marvell/prestera/prestera_router.c
702
switch (fc->key.addr.v) {
drivers/net/ethernet/marvell/prestera/prestera_router.c
737
fc_key.prefix_len = PRESTERA_IP_ADDR_PLEN(n_cache->key.addr.v);
drivers/net/ethernet/marvell/prestera/prestera_router.c
748
fib_key.prefix_len = PRESTERA_IP_ADDR_PLEN(n_cache->key.addr.v);
drivers/net/ethernet/marvell/prestera/prestera_router.c
869
PRESTERA_IP_ADDR_PLEN(fc->key.addr.v)) {
drivers/net/ethernet/marvell/prestera/prestera_router_hw.h
33
} v;
drivers/net/ethernet/marvell/skge.c
1115
u16 v = 0;
drivers/net/ethernet/marvell/skge.c
1116
if (__xm_phy_read(hw, port, reg, &v))
drivers/net/ethernet/marvell/skge.c
1118
return v;
drivers/net/ethernet/marvell/skge.c
1939
u16 v = 0;
drivers/net/ethernet/marvell/skge.c
1940
if (__gm_phy_read(hw, port, reg, &v))
drivers/net/ethernet/marvell/skge.c
1942
return v;
drivers/net/ethernet/marvell/skge.c
3691
static int skge_debug_show(struct seq_file *seq, void *v)
drivers/net/ethernet/marvell/skge.h
2513
u32 v;
drivers/net/ethernet/marvell/skge.h
2514
v = skge_read16(hw, SK_XMAC_REG(port, reg));
drivers/net/ethernet/marvell/skge.h
2515
v |= (u32)skge_read16(hw, SK_XMAC_REG(port, reg+2)) << 16;
drivers/net/ethernet/marvell/skge.h
2516
return v;
drivers/net/ethernet/marvell/skge.h
2524
static inline void xm_write32(const struct skge_hw *hw, int port, int r, u32 v)
drivers/net/ethernet/marvell/skge.h
2526
skge_write16(hw, SK_XMAC_REG(port,r), v & 0xffff);
drivers/net/ethernet/marvell/skge.h
2527
skge_write16(hw, SK_XMAC_REG(port,r+2), v >> 16);
drivers/net/ethernet/marvell/skge.h
2530
static inline void xm_write16(const struct skge_hw *hw, int port, int r, u16 v)
drivers/net/ethernet/marvell/skge.h
2532
skge_write16(hw, SK_XMAC_REG(port,r), v);
drivers/net/ethernet/marvell/skge.h
2566
static inline void gma_write16(const struct skge_hw *hw, int port, int r, u16 v)
drivers/net/ethernet/marvell/skge.h
2568
skge_write16(hw, SK_GMAC_REG(port,r), v);
drivers/net/ethernet/marvell/sky2.c
207
u16 v = 0;
drivers/net/ethernet/marvell/sky2.c
208
__gm_phy_read(hw, port, reg, &v);
drivers/net/ethernet/marvell/sky2.c
209
return v;
drivers/net/ethernet/marvell/sky2.c
4384
static int sky2_debug_show(struct seq_file *seq, void *v)
drivers/net/ethernet/marvell/sky2.h
2395
static inline void gma_write16(const struct sky2_hw *hw, unsigned port, int r, u16 v)
drivers/net/ethernet/marvell/sky2.h
2397
sky2_write16(hw, SK_GMAC_REG(port,r), v);
drivers/net/ethernet/mellanox/mlx5/core/diag/fs_tracepoint.c
117
memcpy(src_ipv6.v.in6_u.u6_addr8,
drivers/net/ethernet/mellanox/mlx5/core/diag/fs_tracepoint.c
120
sizeof(src_ipv6.v));
drivers/net/ethernet/mellanox/mlx5/core/diag/fs_tracepoint.c
121
memcpy(dst_ipv6.v.in6_u.u6_addr8,
drivers/net/ethernet/mellanox/mlx5/core/diag/fs_tracepoint.c
124
sizeof(dst_ipv6.v));
drivers/net/ethernet/mellanox/mlx5/core/diag/fs_tracepoint.c
128
&src_ipv6.v);
drivers/net/ethernet/mellanox/mlx5/core/diag/fs_tracepoint.c
131
&dst_ipv6.v);
drivers/net/ethernet/mellanox/mlx5/core/diag/fs_tracepoint.c
167
.v = MLX5_GET(fte_match_set_misc, value, gre_key.nvgre.hi) << 8 |
drivers/net/ethernet/mellanox/mlx5/core/diag/fs_tracepoint.c
38
#define DECLARE_MASK_VAL(type, name) struct {type m; type v; } name
drivers/net/ethernet/mellanox/mlx5/core/diag/fs_tracepoint.c
42
.v = MLX5_GET(spec, val, fld)}
drivers/net/ethernet/mellanox/mlx5/core/diag/fs_tracepoint.c
46
.v = MLX5_GET_BE(type, spec, val, fld)}
drivers/net/ethernet/mellanox/mlx5/core/diag/fs_tracepoint.c
47
#define GET_MASKED_VAL(name) (name.m & name.v)
drivers/net/ethernet/mellanox/mlx5/core/diag/fs_tracepoint.c
51
name.v = MLX5_GET(type, val, fld), \
drivers/net/ethernet/mellanox/mlx5/core/diag/fs_tracepoint.c
52
name.m & name.v)
drivers/net/ethernet/mellanox/mlx5/core/diag/fs_tracepoint.c
55
trace_seq_printf(p, __stringify(name) "=" format " ", name.v); \
drivers/net/ethernet/mellanox/mlx5/core/diag/fs_tracepoint.c
60
(cast)&name.v);\
drivers/net/ethernet/mellanox/mlx5/core/diag/fs_tracepoint.c
71
.v = MLX5_GET(fte_match_set_lyr_2_4, value, smac_47_16) << 16 |
drivers/net/ethernet/mellanox/mlx5/core/diag/fs_tracepoint.c
76
.v = MLX5_GET(fte_match_set_lyr_2_4, value, dmac_47_16) << 16 |
drivers/net/ethernet/mellanox/mlx5/core/diag/fs_tracepoint.c
85
if ((ethertype.m == 0xffff && ethertype.v == ETH_P_IP) ||
drivers/net/ethernet/mellanox/mlx5/core/diag/fs_tracepoint.c
86
(ip_version.m == 0xf && ip_version.v == 4)) {
drivers/net/ethernet/mellanox/mlx5/core/diag/fs_tracepoint.c
94
PRINT_MASKED_VALP(src_ipv4, typeof(&src_ipv4.v), p,
drivers/net/ethernet/mellanox/mlx5/core/diag/fs_tracepoint.c
96
PRINT_MASKED_VALP(dst_ipv4, typeof(&dst_ipv4.v), p,
drivers/net/ethernet/mellanox/mlx5/core/diag/fs_tracepoint.c
98
} else if ((ethertype.m == 0xffff && ethertype.v == ETH_P_IPV6) ||
drivers/net/ethernet/mellanox/mlx5/core/diag/fs_tracepoint.c
99
(ip_version.m == 0xf && ip_version.v == 6)) {
drivers/net/ethernet/mellanox/mlx5/core/en_fs_ethtool.c
147
#define MLX5E_FTE_SET(header_p, fld, v) \
drivers/net/ethernet/mellanox/mlx5/core/en_fs_ethtool.c
148
MLX5_SET(fte_match_set_lyr_2_4, header_p, fld, v)
drivers/net/ethernet/mellanox/mlx5/core/esw/bridge_debugfs.c
10
static void mlx5_esw_bridge_debugfs_stop(struct seq_file *seq, void *v);
drivers/net/ethernet/mellanox/mlx5/core/esw/bridge_debugfs.c
11
static int mlx5_esw_bridge_debugfs_show(struct seq_file *seq, void *v);
drivers/net/ethernet/mellanox/mlx5/core/esw/bridge_debugfs.c
29
static void *mlx5_esw_bridge_debugfs_next(struct seq_file *seq, void *v, loff_t *pos)
drivers/net/ethernet/mellanox/mlx5/core/esw/bridge_debugfs.c
33
return seq_list_next(v == SEQ_START_TOKEN ? &bridge->fdb_list : v, &bridge->fdb_list, pos);
drivers/net/ethernet/mellanox/mlx5/core/esw/bridge_debugfs.c
36
static void mlx5_esw_bridge_debugfs_stop(struct seq_file *seq, void *v)
drivers/net/ethernet/mellanox/mlx5/core/esw/bridge_debugfs.c
41
static int mlx5_esw_bridge_debugfs_show(struct seq_file *seq, void *v)
drivers/net/ethernet/mellanox/mlx5/core/esw/bridge_debugfs.c
46
if (v == SEQ_START_TOKEN) {
drivers/net/ethernet/mellanox/mlx5/core/esw/bridge_debugfs.c
52
entry = list_entry(v, struct mlx5_esw_bridge_fdb_entry, list);
drivers/net/ethernet/mellanox/mlx5/core/esw/bridge_debugfs.c
9
static void *mlx5_esw_bridge_debugfs_next(struct seq_file *seq, void *v, loff_t *pos);
drivers/net/ethernet/mellanox/mlx5/core/fs_core.h
380
#define fs_get_obj(v, _node) {v = container_of((_node), typeof(*v), node); }
drivers/net/ethernet/mellanox/mlx5/core/lib/gid.c
121
#define MLX5_SET_RA(p, f, v) MLX5_SET(roce_addr_layout, p, f, v)
drivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c
54
#define _HWS_SET32(p, v, byte_off, bit_off, mask) \
drivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c
56
u32 _v = v; \
drivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c
66
#define HWS_SET32(p, v, byte_off, bit_off, mask) \
drivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c
71
_HWS_SET32(p, (v) >> _bit_off, byte_off, 0, (mask) >> _bit_off); \
drivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c
72
_HWS_SET32(p, (v) & second_dw_mask, (byte_off) + DW_SIZE, \
drivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c
75
_HWS_SET32(p, v, byte_off, (bit_off), (mask)); \
drivers/net/ethernet/mellanox/mlx5/core/steering/sws/dr_dbg.c
1110
dr_dump_next(struct seq_file *file, void *v, loff_t *pos)
drivers/net/ethernet/mellanox/mlx5/core/steering/sws/dr_dbg.c
1117
return seq_list_next(v, &dump_data->buff_list, pos);
drivers/net/ethernet/mellanox/mlx5/core/steering/sws/dr_dbg.c
1121
dr_dump_stop(struct seq_file *file, void *v)
drivers/net/ethernet/mellanox/mlx5/core/steering/sws/dr_dbg.c
1126
if (v && IS_ERR(v))
drivers/net/ethernet/mellanox/mlx5/core/steering/sws/dr_dbg.c
1129
if (!v) {
drivers/net/ethernet/mellanox/mlx5/core/steering/sws/dr_dbg.c
1141
dr_dump_show(struct seq_file *file, void *v)
drivers/net/ethernet/mellanox/mlx5/core/steering/sws/dr_dbg.c
1145
entry = list_entry(v, struct mlx5dr_dbg_dump_buff, node);
drivers/net/ethernet/mellanox/mlxsw/pci.c
1039
mlxsw_pci_cqe_owner_set(q->u.cq.v, elem, 1);
drivers/net/ethernet/mellanox/mlxsw/pci.c
1042
if (q->u.cq.v == MLXSW_PCI_CQE_V1)
drivers/net/ethernet/mellanox/mlxsw/pci.c
1045
else if (q->u.cq.v == MLXSW_PCI_CQE_V2)
drivers/net/ethernet/mellanox/mlxsw/pci.c
1089
return q->u.cq.v == MLXSW_PCI_CQE_V2 ? MLXSW_PCI_CQE2_COUNT :
drivers/net/ethernet/mellanox/mlxsw/pci.c
1095
return q->u.cq.v == MLXSW_PCI_CQE_V2 ? MLXSW_PCI_CQE2_SIZE :
drivers/net/ethernet/mellanox/mlxsw/pci.c
619
q->u.cq.v = mlxsw_pci->max_cqe_ver;
drivers/net/ethernet/mellanox/mlxsw/pci.c
621
if (q->u.cq.v == MLXSW_PCI_CQE_V2 &&
drivers/net/ethernet/mellanox/mlxsw/pci.c
624
q->u.cq.v = MLXSW_PCI_CQE_V1;
drivers/net/ethernet/mellanox/mlxsw/pci.c
829
owner_bit = mlxsw_pci_cqe_owner_get(q->u.cq.v, elem);
drivers/net/ethernet/mellanox/mlxsw/pci.c
843
owner_bit = mlxsw_pci_cqe_owner_get(q->u.cq.v, elem_info->elem);
drivers/net/ethernet/mellanox/mlxsw/pci.c
86
enum mlxsw_pci_cqe_v v;
drivers/net/ethernet/mellanox/mlxsw/pci.c
862
u8 sendq = mlxsw_pci_cqe_sr_get(q->u.cq.v, cqe);
drivers/net/ethernet/mellanox/mlxsw/pci.c
863
u8 dqn = mlxsw_pci_cqe_dqn_get(q->u.cq.v, cqe);
drivers/net/ethernet/mellanox/mlxsw/pci.c
876
wqe_counter, q->u.cq.v, cqe);
drivers/net/ethernet/mellanox/mlxsw/pci.c
920
u8 sendq = mlxsw_pci_cqe_sr_get(q->u.cq.v, cqe);
drivers/net/ethernet/mellanox/mlxsw/pci.c
921
u8 dqn = mlxsw_pci_cqe_dqn_get(q->u.cq.v, cqe);
drivers/net/ethernet/mellanox/mlxsw/pci.c
938
wqe_counter, q->u.cq.v, ncqe, budget);
drivers/net/ethernet/mellanox/mlxsw/pci_hw.h
116
static inline u32 mlxsw_pci_cqe_##name##_get(enum mlxsw_pci_cqe_v v, char *cqe) \
drivers/net/ethernet/mellanox/mlxsw/pci_hw.h
118
switch (v) { \
drivers/net/ethernet/mellanox/mlxsw/pci_hw.h
128
static inline void mlxsw_pci_cqe_##name##_set(enum mlxsw_pci_cqe_v v, \
drivers/net/ethernet/mellanox/mlxsw/pci_hw.h
131
switch (v) { \
drivers/net/ethernet/mellanox/mlxsw/reg.h
1594
MLXSW_ITEM32(reg, svfa, v, 0x00, 0, 1);
drivers/net/ethernet/mellanox/mlxsw/reg.h
2665
MLXSW_ITEM32(reg, pacl, v, 0x00, 24, 1);
drivers/net/ethernet/mellanox/mlxsw/reg.h
3154
MLXSW_ITEM32(reg, ptce2, v, 0x00, 31, 1);
drivers/net/ethernet/mellanox/mlxsw/reg.h
3412
MLXSW_ITEM32(reg, ptce3, v, 0x00, 31, 1);
drivers/net/ethernet/mellanox/mlxsw/reg.h
7322
MLXSW_ITEM32(reg, ratr, v, 0x00, 24, 1);
drivers/net/ethernet/mellanox/mlxsw/reg.h
8877
bool v, u16 erif)
drivers/net/ethernet/mellanox/mlxsw/reg.h
8879
mlxsw_reg_rigr2_erif_entry_v_set(payload, index, v);
drivers/net/ethernet/mellanox/mlxsw/reg.h
9031
MLXSW_ITEM32(reg, rmft2, v, 0x00, 31, 1);
drivers/net/ethernet/mellanox/mlxsw/reg.h
9141
mlxsw_reg_rmft2_common_pack(char *payload, bool v, u16 offset,
drivers/net/ethernet/mellanox/mlxsw/reg.h
9147
mlxsw_reg_rmft2_v_set(payload, v);
drivers/net/ethernet/mellanox/mlxsw/reg.h
9159
mlxsw_reg_rmft2_ipv4_pack(char *payload, bool v, u16 offset, u16 virtual_router,
drivers/net/ethernet/mellanox/mlxsw/reg.h
9164
mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router,
drivers/net/ethernet/mellanox/mlxsw/reg.h
9174
mlxsw_reg_rmft2_ipv6_pack(char *payload, bool v, u16 offset, u16 virtual_router,
drivers/net/ethernet/mellanox/mlxsw/reg.h
9180
mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router,
drivers/net/ethernet/meta/fbnic/fbnic.h
137
u32 v;
drivers/net/ethernet/meta/fbnic/fbnic.h
139
v = fbnic_rd32(fbd, reg);
drivers/net/ethernet/meta/fbnic/fbnic.h
140
v &= ~mask;
drivers/net/ethernet/meta/fbnic/fbnic.h
141
v |= val;
drivers/net/ethernet/meta/fbnic/fbnic.h
142
fbnic_wr32(fbd, reg, v);
drivers/net/ethernet/meta/fbnic/fbnic_debugfs.c
107
static int fbnic_dbg_twq_desc_seq_show(struct seq_file *s, void *v)
drivers/net/ethernet/meta/fbnic/fbnic_debugfs.c
132
static int fbnic_dbg_tcq_desc_seq_show(struct seq_file *s, void *v)
drivers/net/ethernet/meta/fbnic/fbnic_debugfs.c
181
static int fbnic_dbg_bdq_desc_seq_show(struct seq_file *s, void *v)
drivers/net/ethernet/meta/fbnic/fbnic_debugfs.c
254
static int fbnic_dbg_rcq_desc_seq_show(struct seq_file *s, void *v)
drivers/net/ethernet/meta/fbnic/fbnic_debugfs.c
286
int (*show)(struct seq_file *s, void *v);
drivers/net/ethernet/meta/fbnic/fbnic_debugfs.c
380
static int fbnic_dbg_mac_addr_show(struct seq_file *s, void *v)
drivers/net/ethernet/meta/fbnic/fbnic_debugfs.c
406
static int fbnic_dbg_tce_tcam_show(struct seq_file *s, void *v)
drivers/net/ethernet/meta/fbnic/fbnic_debugfs.c
440
static int fbnic_dbg_act_tcam_show(struct seq_file *s, void *v)
drivers/net/ethernet/meta/fbnic/fbnic_debugfs.c
500
static int fbnic_dbg_ip_src_show(struct seq_file *s, void *v)
drivers/net/ethernet/meta/fbnic/fbnic_debugfs.c
508
static int fbnic_dbg_ip_dst_show(struct seq_file *s, void *v)
drivers/net/ethernet/meta/fbnic/fbnic_debugfs.c
516
static int fbnic_dbg_ipo_src_show(struct seq_file *s, void *v)
drivers/net/ethernet/meta/fbnic/fbnic_debugfs.c
524
static int fbnic_dbg_ipo_dst_show(struct seq_file *s, void *v)
drivers/net/ethernet/meta/fbnic/fbnic_debugfs.c
563
static int fbnic_dbg_fw_mbx_show(struct seq_file *s, void *v)
drivers/net/ethernet/meta/fbnic/fbnic_debugfs.c
578
static int fbnic_dbg_fw_log_show(struct seq_file *s, void *v)
drivers/net/ethernet/meta/fbnic/fbnic_debugfs.c
605
static int fbnic_dbg_pcie_stats_show(struct seq_file *s, void *v)
drivers/net/ethernet/microchip/lan966x/lan966x_main.c
314
u8 v = val >> i & 0xff;
drivers/net/ethernet/microchip/lan966x/lan966x_main.c
319
ifh[p] |= v << ((pos + i) % 8);
drivers/net/ethernet/microchip/lan966x/lan966x_main.c
320
ifh[p - 1] |= v >> (8 - (pos + i) % 8);
drivers/net/ethernet/microchip/lan966x/lan966x_main.c
614
u8 v;
drivers/net/ethernet/microchip/lan966x/lan966x_main.c
621
v = ifh[IFH_LEN_BYTES - (j / 8) - 1];
drivers/net/ethernet/microchip/lan966x/lan966x_main.c
623
if (v & (1 << k))
drivers/net/ethernet/microchip/lan966x/lan966x_switchdev.c
535
const struct switchdev_obj_port_vlan *v = SWITCHDEV_OBJ_PORT_VLAN(obj);
drivers/net/ethernet/microchip/lan966x/lan966x_switchdev.c
539
lan966x_vlan_port_add_vlan(port, v->vid,
drivers/net/ethernet/microchip/lan966x/lan966x_switchdev.c
540
v->flags & BRIDGE_VLAN_INFO_PVID,
drivers/net/ethernet/microchip/lan966x/lan966x_switchdev.c
541
v->flags & BRIDGE_VLAN_INFO_UNTAGGED);
drivers/net/ethernet/microchip/lan966x/lan966x_switchdev.c
543
lan966x_vlan_cpu_add_vlan(lan966x, v->vid);
drivers/net/ethernet/microchip/lan966x/lan966x_switchdev.c
577
const struct switchdev_obj_port_vlan *v = SWITCHDEV_OBJ_PORT_VLAN(obj);
drivers/net/ethernet/microchip/lan966x/lan966x_switchdev.c
581
lan966x_vlan_port_del_vlan(port, v->vid);
drivers/net/ethernet/microchip/lan966x/lan966x_switchdev.c
583
lan966x_vlan_cpu_del_vlan(lan966x, v->vid);
drivers/net/ethernet/microchip/sparx5/sparx5_switchdev.c
436
const struct switchdev_obj_port_vlan *v)
drivers/net/ethernet/microchip/sparx5/sparx5_switchdev.c
447
dev->broadcast, v->vid);
drivers/net/ethernet/microchip/sparx5/sparx5_switchdev.c
454
return sparx5_vlan_vid_add(port, v->vid,
drivers/net/ethernet/microchip/sparx5/sparx5_switchdev.c
455
v->flags & BRIDGE_VLAN_INFO_PVID,
drivers/net/ethernet/microchip/sparx5/sparx5_switchdev.c
456
v->flags & BRIDGE_VLAN_INFO_UNTAGGED);
drivers/net/ethernet/microchip/sparx5/sparx5_switchdev.c
540
const struct switchdev_obj_port_mdb *v)
drivers/net/ethernet/microchip/sparx5/sparx5_switchdev.c
552
is_host = netif_is_bridge_master(v->obj.orig_dev);
drivers/net/ethernet/microchip/sparx5/sparx5_switchdev.c
560
vid = v->vid;
drivers/net/ethernet/microchip/sparx5/sparx5_switchdev.c
563
entry = sparx5_mdb_get_entry(spx5, v->addr, vid);
drivers/net/ethernet/microchip/sparx5/sparx5_switchdev.c
565
err = sparx5_alloc_mdb_entry(spx5, v->addr, vid, &entry);
drivers/net/ethernet/microchip/sparx5/sparx5_switchdev.c
574
if (is_new && ether_addr_is_ip_mcast(v->addr))
drivers/net/ethernet/microchip/sparx5/sparx5_switchdev.c
597
const struct switchdev_obj_port_mdb *v)
drivers/net/ethernet/microchip/sparx5/sparx5_switchdev.c
608
is_host = netif_is_bridge_master(v->obj.orig_dev);
drivers/net/ethernet/microchip/sparx5/sparx5_switchdev.c
613
vid = v->vid;
drivers/net/ethernet/microchip/sparx5/sparx5_switchdev.c
615
entry = sparx5_mdb_get_entry(spx5, v->addr, vid);
drivers/net/ethernet/microchip/sparx5/sparx5_switchdev.c
627
if (!port->is_mrouter || !ether_addr_is_ip_mcast(v->addr))
drivers/net/ethernet/mscc/ocelot_vcap.c
221
u32 i, v, m;
drivers/net/ethernet/mscc/ocelot_vcap.c
224
v = data[offset / ENTRY_WIDTH];
drivers/net/ethernet/mscc/ocelot_vcap.c
227
v |= m;
drivers/net/ethernet/mscc/ocelot_vcap.c
229
v &= ~m;
drivers/net/ethernet/mscc/ocelot_vcap.c
230
data[offset / ENTRY_WIDTH] = v;
drivers/net/ethernet/mscc/ocelot_vcap.c
236
u32 i, v, m, value = 0;
drivers/net/ethernet/mscc/ocelot_vcap.c
239
v = data[offset / ENTRY_WIDTH];
drivers/net/ethernet/mscc/ocelot_vcap.c
241
if (v & m)
drivers/net/ethernet/netronome/nfp/nfpcore/nfp_target.c
434
int v, ret;
drivers/net/ethernet/netronome/nfp/nfpcore/nfp_target.c
437
ret = nfp_decode_basic(addr, &v, cpp_tgt, mode, addr40, isld1, isld0);
drivers/net/ethernet/netronome/nfp/nfpcore/nfp_target.c
442
if (dest_island != -1 && dest_island != v)
drivers/net/ethernet/netronome/nfp/nfpcore/nfp_target.c
456
int i, v;
drivers/net/ethernet/netronome/nfp/nfpcore/nfp_target.c
459
for (v = 0; v < v_max; v++) {
drivers/net/ethernet/netronome/nfp/nfpcore/nfp_target.c
460
if (dest_island != (isld[i] | v))
drivers/net/ethernet/netronome/nfp/nfpcore/nfp_target.c
465
*addr |= ((u64)v << iid_lsb);
drivers/net/ethernet/nvidia/forcedeth.c
950
static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
drivers/net/ethernet/nvidia/forcedeth.c
953
& ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
drivers/net/ethernet/nvidia/forcedeth.c
956
static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c
115
struct ionic_vf *v;
drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c
122
v = &ionic->vfs[i];
drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c
124
if (v->stats_pa) {
drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c
127
dma_unmap_single(ionic->dev, v->stats_pa,
drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c
128
sizeof(v->stats), DMA_FROM_DEVICE);
drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c
129
v->stats_pa = 0;
drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c
148
struct ionic_vf *v;
drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c
161
v = &ionic->vfs[i];
drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c
162
v->stats_pa = dma_map_single(ionic->dev, &v->stats,
drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c
163
sizeof(v->stats), DMA_FROM_DEVICE);
drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c
164
if (dma_mapping_error(ionic->dev, v->stats_pa)) {
drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c
165
v->stats_pa = 0;
drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c
173
vfc.stats_pa = cpu_to_le64(v->stats_pa);
drivers/net/ethernet/pensando/ionic/ionic_debugfs.c
219
static int netdev_show(struct seq_file *seq, void *v)
drivers/net/ethernet/pensando/ionic/ionic_debugfs.c
229
static int lif_filters_show(struct seq_file *seq, void *v)
drivers/net/ethernet/pensando/ionic/ionic_debugfs.c
37
static int identity_show(struct seq_file *seq, void *v)
drivers/net/ethernet/pensando/ionic/ionic_debugfs.c
75
static int q_tail_show(struct seq_file *seq, void *v)
drivers/net/ethernet/pensando/ionic/ionic_debugfs.c
85
static int q_head_show(struct seq_file *seq, void *v)
drivers/net/ethernet/pensando/ionic/ionic_debugfs.c
95
static int cq_tail_show(struct seq_file *seq, void *v)
drivers/net/ethernet/pensando/ionic/ionic_lif.c
2617
struct ionic_vf *v;
drivers/net/ethernet/pensando/ionic/ionic_lif.c
2626
v = &ionic->vfs[i];
drivers/net/ethernet/pensando/ionic/ionic_lif.c
2628
if (v->stats_pa) {
drivers/net/ethernet/pensando/ionic/ionic_lif.c
2630
vfc.stats_pa = cpu_to_le64(v->stats_pa);
drivers/net/ethernet/pensando/ionic/ionic_lif.c
2635
if (!is_zero_ether_addr(v->macaddr)) {
drivers/net/ethernet/pensando/ionic/ionic_lif.c
2637
ether_addr_copy(vfc.macaddr, v->macaddr);
drivers/net/ethernet/pensando/ionic/ionic_lif.c
2642
if (v->vlanid) {
drivers/net/ethernet/pensando/ionic/ionic_lif.c
2644
vfc.vlanid = v->vlanid;
drivers/net/ethernet/pensando/ionic/ionic_lif.c
2649
if (v->maxrate) {
drivers/net/ethernet/pensando/ionic/ionic_lif.c
2651
vfc.maxrate = v->maxrate;
drivers/net/ethernet/pensando/ionic/ionic_lif.c
2656
if (v->spoofchk) {
drivers/net/ethernet/pensando/ionic/ionic_lif.c
2658
vfc.spoofchk = v->spoofchk;
drivers/net/ethernet/pensando/ionic/ionic_lif.c
2663
if (v->trusted) {
drivers/net/ethernet/pensando/ionic/ionic_lif.c
2665
vfc.trust = v->trusted;
drivers/net/ethernet/pensando/ionic/ionic_lif.c
2670
if (v->linkstate) {
drivers/net/ethernet/pensando/ionic/ionic_lif.c
2672
vfc.linkstate = v->linkstate;
drivers/net/ethernet/qlogic/netxen/netxen_nic.h
295
#define netxen_set_tx_vlan_tci(cmd_desc, v) \
drivers/net/ethernet/qlogic/netxen/netxen_nic.h
296
(cmd_desc)->vlan_TCI = cpu_to_le16(v);
drivers/net/ethernet/qlogic/netxen/netxen_nic.h
42
#define _major(v) (((v) >> 24) & 0xff)
drivers/net/ethernet/qlogic/netxen/netxen_nic.h
43
#define _minor(v) (((v) >> 16) & 0xff)
drivers/net/ethernet/qlogic/netxen/netxen_nic.h
44
#define _build(v) ((v) & 0xffff)
drivers/net/ethernet/qlogic/netxen/netxen_nic.h
51
#define NETXEN_DECODE_VERSION(v) \
drivers/net/ethernet/qlogic/netxen/netxen_nic.h
52
NETXEN_VERSION_CODE(((v) & 0xff), (((v) >> 8) & 0xff), ((v) >> 16))
drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c
971
int i, v, addr;
drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c
978
ret = netxen_rom_fast_read(adapter, addr, &v);
drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c
982
*ptr32 = cpu_to_le32(v);
drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c
988
ret = netxen_rom_fast_read(adapter, addr, &v);
drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c
991
local = cpu_to_le32(v);
drivers/net/ethernet/qlogic/netxen/netxen_nic_init.c
370
int v;
drivers/net/ethernet/qlogic/netxen/netxen_nic_init.c
371
ret = do_rom_fast_read(adapter, addridx, &v);
drivers/net/ethernet/qlogic/netxen/netxen_nic_init.c
374
*(__le32 *)bytes = cpu_to_le32(v);
drivers/net/ethernet/qlogic/qlcnic/qlcnic.h
46
#define _major(v) (((v) >> 24) & 0xff)
drivers/net/ethernet/qlogic/qlcnic/qlcnic.h
47
#define _minor(v) (((v) >> 16) & 0xff)
drivers/net/ethernet/qlogic/qlcnic/qlcnic.h
48
#define _build(v) ((v) & 0xffff)
drivers/net/ethernet/qlogic/qlcnic/qlcnic.h
55
#define QLCNIC_DECODE_VERSION(v) \
drivers/net/ethernet/qlogic/qlcnic/qlcnic.h
56
QLCNIC_VERSION_CODE(((v) & 0xff), (((v) >> 8) & 0xff), ((v) >> 16))
drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.h
27
#define QLC_83xx_FUNC_VAL(v, f) ((v) & (1 << (f * 4)))
drivers/net/ethernet/qlogic/qlcnic/qlcnic_init.c
343
int v;
drivers/net/ethernet/qlogic/qlcnic/qlcnic_init.c
344
ret = do_rom_fast_read(adapter, addridx, &v);
drivers/net/ethernet/qlogic/qlcnic/qlcnic_init.c
347
*(__le32 *)bytes = cpu_to_le32(v);
drivers/net/ethernet/qlogic/qlcnic/qlcnic_io.c
31
#define qlcnic_set_tx_vlan_tci(cmd_desc, v) \
drivers/net/ethernet/qlogic/qlcnic/qlcnic_io.c
32
(cmd_desc)->vlan_TCI = cpu_to_le16(v);
drivers/net/ethernet/qualcomm/ppe/ppe_debugfs.c
672
static int ppe_packet_counter_show(struct seq_file *seq, void *v)
drivers/net/ethernet/seeq/ether3.c
100
static inline void ether3_outb(int v, void __iomem *r)
drivers/net/ethernet/seeq/ether3.c
102
writeb(v, r);
drivers/net/ethernet/seeq/ether3.c
106
static inline void ether3_outw(int v, void __iomem *r)
drivers/net/ethernet/seeq/ether3.c
108
writew(v, r);
drivers/net/ethernet/seeq/sgiseeq.c
57
#define VIRT_TO_DMA(sp, v) ((sp)->srings_dma + \
drivers/net/ethernet/seeq/sgiseeq.c
58
(dma_addr_t)((unsigned long)(v) - \
drivers/net/ethernet/sfc/mae.c
1846
u64 v;
drivers/net/ethernet/sfc/mae.c
1848
v = ((u8 *)value)[value_size - i - 1];
drivers/net/ethernet/sfc/mae.c
1849
v <<= (bn % 32);
drivers/net/ethernet/sfc/mae.c
1850
row[wn] |= cpu_to_le32(v & 0xffffffff);
drivers/net/ethernet/sfc/mae.c
1852
row[wn + 1] |= cpu_to_le32(v >> 32);
drivers/net/ethernet/sfc/mae.c
1860
u8 v = value ? 1 : 0;
drivers/net/ethernet/sfc/mae.c
1864
return efx_mae_table_populate(field, row, row_bits, &v, 1);
drivers/net/ethernet/sfc/mae.c
1871
struct in6_addr v = {};
drivers/net/ethernet/sfc/mae.c
1875
v.s6_addr32[0] = value;
drivers/net/ethernet/sfc/mae.c
1876
return efx_mae_table_populate(field, row, row_bits, &v, sizeof(v));
drivers/net/ethernet/sfc/mae.c
1882
__be32 v = cpu_to_be32(value);
drivers/net/ethernet/sfc/mae.c
1888
return efx_mae_table_populate(field, row, row_bits, ((void *)&v) + 1,
drivers/net/ethernet/sfc/mae.c
1889
sizeof(v) - 1);
drivers/net/ethernet/sfc/tc.h
19
#define IS_ALL_ONES(v) (!(typeof (v))~(v))
drivers/net/ethernet/smsc/smc91c92_cs.c
262
#define set_bits(v, p) outw(inw(p)|(v), (p))
drivers/net/ethernet/smsc/smc91c92_cs.c
263
#define mask_bits(v, p) outw(inw(p)&(v), (p))
drivers/net/ethernet/smsc/smc91c92_cs.c
70
#define INT_MODULE_PARM(n, v) static int n = v; module_param(n, int, 0)
drivers/net/ethernet/smsc/smc91x.h
103
unsigned int v = val << 16;
drivers/net/ethernet/smsc/smc91x.h
104
v |= readl(ioaddr + (reg & ~2)) & 0xffff;
drivers/net/ethernet/smsc/smc91x.h
105
writel(v, ioaddr + (reg & ~2));
drivers/net/ethernet/smsc/smc91x.h
111
#define __SMC_outw(lp, v, a, r) \
drivers/net/ethernet/smsc/smc91x.h
112
_SMC_outw_align4((v), (a), (r), \
drivers/net/ethernet/smsc/smc91x.h
127
#define SMC_outb(v, a, r) writeb(v, (a) + (r))
drivers/net/ethernet/smsc/smc91x.h
128
#define SMC_outw(lp, v, a, r) writew(v, (a) + (r))
drivers/net/ethernet/smsc/smc91x.h
129
#define SMC_outl(v, a, r) writel(v, (a) + (r))
drivers/net/ethernet/smsc/smc91x.h
160
#define SMC_outw(lp, v, a, r) iowrite16be(v, (a) + (r))
drivers/net/ethernet/smsc/smc91x.h
182
#define SMC_outb(v, a, r) iowrite8(v, (a) + (r))
drivers/net/ethernet/smsc/smc91x.h
183
#define SMC_outw(lp, v, a, r) iowrite16(v, (a) + (r))
drivers/net/ethernet/smsc/smc91x.h
184
#define SMC_outl(v, a, r) iowrite32(v, (a) + (r))
drivers/net/ethernet/smsc/smc91x.h
77
#define SMC_outb(v, a, r) writeb(v, (a) + (r))
drivers/net/ethernet/smsc/smc91x.h
78
#define SMC_outw(lp, v, a, r) \
drivers/net/ethernet/smsc/smc91x.h
80
unsigned int __v = v, __smc_r = r; \
drivers/net/ethernet/smsc/smc91x.h
89
#define SMC_outl(v, a, r) writel(v, (a) + (r))
drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
308
u32 v;
drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
356
ret = readl_poll_timeout(priv->ioaddr + XGMAC_INT_STATUS, v,
drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
357
(v & XGMAC_INT_TSIS), 100, 10000);
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
379
u32 v;
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
381
v = readl(ioaddr + EMAC_TX_CTL1);
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
382
v |= EMAC_TX_DMA_START;
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
383
v |= EMAC_TX_DMA_EN;
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
384
writel(v, ioaddr + EMAC_TX_CTL1);
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
389
u32 v;
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
391
v = readl(ioaddr + EMAC_TX_CTL1);
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
392
v |= EMAC_TX_DMA_START;
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
393
v |= EMAC_TX_DMA_EN;
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
394
writel(v, ioaddr + EMAC_TX_CTL1);
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
400
u32 v;
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
402
v = readl(ioaddr + EMAC_TX_CTL1);
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
403
v &= ~EMAC_TX_DMA_EN;
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
404
writel(v, ioaddr + EMAC_TX_CTL1);
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
410
u32 v;
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
412
v = readl(ioaddr + EMAC_RX_CTL1);
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
413
v |= EMAC_RX_DMA_START;
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
414
v |= EMAC_RX_DMA_EN;
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
415
writel(v, ioaddr + EMAC_RX_CTL1);
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
421
u32 v;
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
423
v = readl(ioaddr + EMAC_RX_CTL1);
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
424
v &= ~EMAC_RX_DMA_EN;
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
425
writel(v, ioaddr + EMAC_RX_CTL1);
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
435
u32 v;
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
437
v = readl(ioaddr + EMAC_INT_STA);
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
440
v &= EMAC_INT_MSK_RX;
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
442
v &= EMAC_INT_MSK_TX;
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
444
if (v & EMAC_TX_INT) {
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
451
if (v & EMAC_TX_DMA_STOP_INT)
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
454
if (v & EMAC_TX_BUF_UA_INT)
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
457
if (v & EMAC_TX_TIMEOUT_INT)
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
460
if (v & EMAC_TX_UNDERFLOW_INT) {
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
465
if (v & EMAC_TX_EARLY_INT)
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
468
if (v & EMAC_RX_INT) {
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
475
if (v & EMAC_RX_BUF_UA_INT)
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
478
if (v & EMAC_RX_DMA_STOP_INT)
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
481
if (v & EMAC_RX_TIMEOUT_INT)
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
484
if (v & EMAC_RX_OVERFLOW_INT) {
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
489
if (v & EMAC_RX_EARLY_INT)
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
492
if (v & EMAC_RGMII_STA_INT)
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
495
writel(v, ioaddr + EMAC_INT_STA);
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
504
u32 v;
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
506
v = readl(ioaddr + EMAC_RX_CTL1);
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
508
v |= EMAC_RX_MD;
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
510
v &= ~EMAC_RX_MD;
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
511
v &= ~EMAC_RX_TH_MASK;
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
513
v |= EMAC_RX_TH_32;
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
515
v |= EMAC_RX_TH_64;
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
517
v |= EMAC_RX_TH_96;
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
519
v |= EMAC_RX_TH_128;
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
521
writel(v, ioaddr + EMAC_RX_CTL1);
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
528
u32 v;
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
530
v = readl(ioaddr + EMAC_TX_CTL1);
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
532
v |= EMAC_TX_MD;
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
538
v |= EMAC_TX_NEXT_FRM;
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
540
v &= ~EMAC_TX_MD;
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
541
v &= ~EMAC_TX_TH_MASK;
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
543
v |= EMAC_TX_TH_64;
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
545
v |= EMAC_TX_TH_128;
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
547
v |= EMAC_TX_TH_192;
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
549
v |= EMAC_TX_TH_256;
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
551
writel(v, ioaddr + EMAC_TX_CTL1);
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
607
u32 v;
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
609
v = (8 << EMAC_BURSTLEN_SHIFT); /* burst len */
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
610
writel(v, ioaddr + EMAC_BASIC_CTL1);
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
639
u32 v;
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
649
v = readl(ioaddr + EMAC_MACADDR_HI(reg_n));
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
650
v |= MAC_ADDR_TYPE_DST;
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
651
writel(v, ioaddr + EMAC_MACADDR_HI(reg_n));
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
669
u32 v;
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
671
v = readl(ioaddr + EMAC_RX_CTL0);
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
672
v |= EMAC_RX_DO_CRC;
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
673
writel(v, ioaddr + EMAC_RX_CTL0);
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
682
u32 v;
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
687
v = EMAC_FRM_FLT_CTL;
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
690
v = EMAC_FRM_FLT_RXALL;
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
692
v |= EMAC_FRM_FLT_MULTICAST;
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
709
v = EMAC_FRM_FLT_RXALL;
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
716
writel(v, ioaddr + EMAC_RX_FRM_FLT);
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
724
u32 v;
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
726
v = readl(ioaddr + EMAC_RX_CTL0);
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
728
v |= EMAC_RX_FLOW_CTL_EN;
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
730
v &= ~EMAC_RX_FLOW_CTL_EN;
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
731
writel(v, ioaddr + EMAC_RX_CTL0);
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
733
v = readl(ioaddr + EMAC_TX_FLOW_CTL);
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
735
v |= EMAC_TX_FLOW_CTL_EN;
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
737
v &= ~EMAC_TX_FLOW_CTL_EN;
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
738
writel(v, ioaddr + EMAC_TX_FLOW_CTL);
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
743
u32 v;
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
746
v = readl(priv->ioaddr + EMAC_BASIC_CTL1);
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
747
writel(v | 0x01, priv->ioaddr + EMAC_BASIC_CTL1);
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
752
err = readl_poll_timeout(priv->ioaddr + EMAC_BASIC_CTL1, v,
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
753
!(v & 0x01), 100, 100000);
drivers/net/ethernet/stmicro/stmmac/dwmac4.h
228
#define GMAC_CONFIG1_SPLM(v) FIELD_PREP(GENMASK(9, 8), v)
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
6453
static int stmmac_rings_status_show(struct seq_file *seq, void *v)
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
6500
static int stmmac_dma_cap_show(struct seq_file *seq, void *v)
drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
50
u32 v;
drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
52
if (readl_poll_timeout(reg, v, !(v & mask), 100, 10000))
drivers/net/ethernet/sun/niu.h
2587
#define MRVL88X2011_LED(n,v) ((v)<<((n)*4))
drivers/net/ethernet/sun/niu.h
2588
#define MRVL88X2011_LED_STAT(n,v) ((v)>>((n)*4))
drivers/net/ethernet/ti/am65-cpts.c
203
#define am65_cpts_write32(c, v, r) writel(v, &(c)->reg->r)
drivers/net/ethernet/ti/am65-cpts.c
582
u32 v;
drivers/net/ethernet/ti/am65-cpts.c
584
v = am65_cpts_read32(cpts, control);
drivers/net/ethernet/ti/am65-cpts.c
586
v |= BIT(AM65_CPTS_CONTROL_HW1_TS_PUSH_OFFSET + index);
drivers/net/ethernet/ti/am65-cpts.c
589
v &= ~BIT(AM65_CPTS_CONTROL_HW1_TS_PUSH_OFFSET + index);
drivers/net/ethernet/ti/am65-cpts.c
592
am65_cpts_write32(cpts, v, control);
drivers/net/ethernet/ti/cpts.c
277
u32 v;
drivers/net/ethernet/ti/cpts.c
284
v = cpts_read32(cpts, control);
drivers/net/ethernet/ti/cpts.c
286
v |= BIT(8 + index);
drivers/net/ethernet/ti/cpts.c
289
v &= ~BIT(8 + index);
drivers/net/ethernet/ti/cpts.c
292
cpts_write32(cpts, v, control);
drivers/net/ethernet/ti/cpts.c
33
#define cpts_write32(c, v, r) writel_relaxed(v, &c->reg->r)
drivers/net/ethernet/ti/davinci_cpdma.c
176
#define dma_reg_write(ctlr, ofs, v) writel(v, (ctlr)->dmaregs + (ofs))
drivers/net/ethernet/ti/davinci_cpdma.c
177
#define chan_write(chan, fld, v) writel(v, (chan)->fld)
drivers/net/ethernet/ti/davinci_cpdma.c
178
#define desc_write(desc, fld, v) writel((u32)(v), &(desc)->fld)
drivers/net/ethernet/ti/netcp_ethss.c
2195
u32 i, v;
drivers/net/ethernet/ti/netcp_ethss.c
2202
v = readl(GBE_REG_ADDR(slave, emac_regs, soft_reset));
drivers/net/ethernet/ti/netcp_ethss.c
2203
if ((v & SOFT_RESET_MASK) != SOFT_RESET)
drivers/net/ethernet/ti/netcp_xgbepcsr.c
29
#define VAL_SH(v, s) (v << s)
drivers/net/ethernet/wangxun/libwx/wx_type.h
275
#define WX_PSR_MAC_SWC_AD_H_AD(v) FIELD_PREP(U16_MAX, v)
drivers/net/ethernet/wangxun/libwx/wx_type.h
276
#define WX_PSR_MAC_SWC_AD_H_ADTYPE(v) FIELD_PREP(BIT(30), v)
drivers/net/ethernet/wangxun/libwx/wx_type.h
384
#define WX_MSCA_RA(v) FIELD_PREP(U16_MAX, v)
drivers/net/ethernet/wangxun/libwx/wx_type.h
385
#define WX_MSCA_PA(v) FIELD_PREP(GENMASK(20, 16), v)
drivers/net/ethernet/wangxun/libwx/wx_type.h
386
#define WX_MSCA_DA(v) FIELD_PREP(GENMASK(25, 21), v)
drivers/net/ethernet/wangxun/libwx/wx_type.h
388
#define WX_MSCC_CMD(v) FIELD_PREP(GENMASK(17, 16), v)
drivers/net/ethernet/wangxun/libwx/wx_type.h
399
#define WX_MDIO_CLK(v) FIELD_PREP(GENMASK(21, 19), v)
drivers/net/ethernet/wangxun/libwx/wx_vf.h
49
#define wx_conf_size(v, mwidth, uwidth) ({ \
drivers/net/ethernet/wangxun/libwx/wx_vf.h
50
typeof(v) _v = (v); \
drivers/net/ethernet/wangxun/libwx/wx_vf.h
53
#define wx_buf_len(v) wx_conf_size(v, 13, 7)
drivers/net/ethernet/wangxun/libwx/wx_vf.h
54
#define wx_hdr_sz(v) wx_conf_size(v, 10, 6)
drivers/net/ethernet/wangxun/libwx/wx_vf.h
55
#define wx_buf_sz(v) wx_conf_size(v, 14, 10)
drivers/net/ethernet/wangxun/libwx/wx_vf.h
56
#define wx_pkt_thresh(v) wx_conf_size(v, 4, 0)
drivers/net/ethernet/wangxun/txgbe/txgbe_type.h
120
#define TXGBE_RDB_FDIR_CTL_DROP_Q(v) FIELD_PREP(GENMASK(14, 8), v)
drivers/net/ethernet/wangxun/txgbe/txgbe_type.h
121
#define TXGBE_RDB_FDIR_CTL_HASH_BITS(v) FIELD_PREP(GENMASK(23, 20), v)
drivers/net/ethernet/wangxun/txgbe/txgbe_type.h
122
#define TXGBE_RDB_FDIR_CTL_MAX_LENGTH(v) FIELD_PREP(GENMASK(27, 24), v)
drivers/net/ethernet/wangxun/txgbe/txgbe_type.h
123
#define TXGBE_RDB_FDIR_CTL_FULL_THRESH(v) FIELD_PREP(GENMASK(31, 28), v)
drivers/net/ethernet/wangxun/txgbe/txgbe_type.h
132
#define TXGBE_RDB_FDIR_HASH_SIG_SW_INDEX(v) FIELD_PREP(GENMASK(31, 16), v)
drivers/net/ethernet/wangxun/txgbe/txgbe_type.h
136
#define TXGBE_RDB_FDIR_CMD_CMD(v) FIELD_PREP(GENMASK(1, 0), v)
drivers/net/ethernet/wangxun/txgbe/txgbe_type.h
142
#define TXGBE_RDB_FDIR_CMD_FLOW_TYPE(v) FIELD_PREP(GENMASK(6, 5), v)
drivers/net/ethernet/wangxun/txgbe/txgbe_type.h
146
#define TXGBE_RDB_FDIR_CMD_RX_QUEUE(v) FIELD_PREP(GENMASK(22, 16), v)
drivers/net/ethernet/wangxun/txgbe/txgbe_type.h
147
#define TXGBE_RDB_FDIR_CMD_VT_POOL(v) FIELD_PREP(GENMASK(29, 24), v)
drivers/net/ethernet/wangxun/txgbe/txgbe_type.h
162
#define TXGBE_RDB_FDIR_FLEX_CFG_OFST(v) FIELD_PREP(GENMASK(7, 3), v)
drivers/net/ethernet/xilinx/ll_temac.h
402
#define temac_iow(lp, o, v) ((lp)->temac_iow(lp, o, v))
drivers/net/ethernet/xircom/xirc2ps_cs.c
235
#define INT_MODULE_PARM(n, v) static int n = v; module_param(n, int, 0)
drivers/net/fddi/defxx.c
2935
unsigned long v;
drivers/net/fddi/defxx.c
2937
v = ALIGN(x, n); /* Where we want to be */
drivers/net/fddi/defxx.c
2939
skb_reserve(skb, v - x);
drivers/net/fddi/defza.c
107
static inline void fza_skb_align(struct sk_buff *skb, unsigned int v)
drivers/net/fddi/defza.c
112
y = ALIGN(x, v);
drivers/net/fjes/fjes_debugfs.c
26
static int fjes_dbg_status_show(struct seq_file *m, void *v)
drivers/net/hamradio/bpqether.c
374
static void *bpq_seq_next(struct seq_file *seq, void *v, loff_t *pos)
drivers/net/hamradio/bpqether.c
377
struct bpqdev *bpqdev = v;
drivers/net/hamradio/bpqether.c
381
if (v == SEQ_START_TOKEN)
drivers/net/hamradio/bpqether.c
390
static void bpq_seq_stop(struct seq_file *seq, void *v)
drivers/net/hamradio/bpqether.c
397
static int bpq_seq_show(struct seq_file *seq, void *v)
drivers/net/hamradio/bpqether.c
399
if (v == SEQ_START_TOKEN)
drivers/net/hamradio/bpqether.c
403
const struct bpqdev *bpqdev = v;
drivers/net/hamradio/scc.c
1998
static void *scc_net_seq_next(struct seq_file *seq, void *v, loff_t *pos)
drivers/net/hamradio/scc.c
2001
struct scc_channel *scc = v;
drivers/net/hamradio/scc.c
2004
for (k = (v == SEQ_START_TOKEN) ? 0 : (scc - SCC_Info)+1;
drivers/net/hamradio/scc.c
2012
static void scc_net_seq_stop(struct seq_file *seq, void *v)
drivers/net/hamradio/scc.c
2016
static int scc_net_seq_show(struct seq_file *seq, void *v)
drivers/net/hamradio/scc.c
2018
if (v == SEQ_START_TOKEN) {
drivers/net/hamradio/scc.c
2025
const struct scc_channel *scc = v;
drivers/net/hamradio/yam.c
786
static void *yam_seq_next(struct seq_file *seq, void *v, loff_t *pos)
drivers/net/hamradio/yam.c
792
static void yam_seq_stop(struct seq_file *seq, void *v)
drivers/net/hamradio/yam.c
796
static int yam_seq_show(struct seq_file *seq, void *v)
drivers/net/hamradio/yam.c
798
struct net_device *dev = v;
drivers/net/mdio/mdio-mux.c
188
int v;
drivers/net/mdio/mdio-mux.c
190
r = of_property_read_u32(child_bus_node, "reg", &v);
drivers/net/mdio/mdio-mux.c
203
cb->bus_number = v;
drivers/net/mdio/mdio-mux.c
215
cb->mii_bus->name, pb->parent_id, v);
drivers/net/pcs/pcs-xpcs-wx.c
14
#define TXGBE_TX_GEN_CTL2_TX0_WIDTH(v) FIELD_PREP(GENMASK(9, 8), v)
drivers/net/pcs/pcs-xpcs-wx.c
16
#define TXGBE_TX_RATE_CTL_TX0_RATE(v) FIELD_PREP(GENMASK(2, 0), v)
drivers/net/pcs/pcs-xpcs-wx.c
18
#define TXGBE_RX_GEN_CTL2_RX0_WIDTH(v) FIELD_PREP(GENMASK(9, 8), v)
drivers/net/pcs/pcs-xpcs-wx.c
22
#define TXGBE_RX_RATE_CTL_RX0_RATE(v) FIELD_PREP(GENMASK(1, 0), v)
drivers/net/pcs/pcs-xpcs-wx.c
26
#define TXGBE_RX_EQ_CTL0_VGA1_GAIN(v) FIELD_PREP(GENMASK(15, 12), v)
drivers/net/pcs/pcs-xpcs-wx.c
27
#define TXGBE_RX_EQ_CTL0_VGA2_GAIN(v) FIELD_PREP(GENMASK(11, 8), v)
drivers/net/pcs/pcs-xpcs-wx.c
28
#define TXGBE_RX_EQ_CTL0_CTLE_POLE(v) FIELD_PREP(GENMASK(7, 5), v)
drivers/net/pcs/pcs-xpcs-wx.c
29
#define TXGBE_RX_EQ_CTL0_CTLE_BOOST(v) FIELD_PREP(GENMASK(4, 0), v)
drivers/net/pcs/pcs-xpcs-wx.c
45
#define TXGBE_MISC_CTL0_RX_VREF(v) FIELD_PREP(GENMASK(12, 8), v)
drivers/net/phy/bcm54140.c
101
#define BCM54140_HWMON_TO_IN_3V3(v) ((v) * 4400 >> 12)
drivers/net/phy/bcm54140.c
102
#define BCM54140_HWMON_FROM_IN_3V3(v) DIV_ROUND_CLOSEST_ULL(((v) << 12), 4400)
drivers/net/phy/bcm54140.c
104
#define BCM54140_HWMON_TO_IN(ch, v) ((ch) ? BCM54140_HWMON_TO_IN_3V3(v) \
drivers/net/phy/bcm54140.c
105
: BCM54140_HWMON_TO_IN_1V0(v))
drivers/net/phy/bcm54140.c
106
#define BCM54140_HWMON_FROM_IN(ch, v) ((ch) ? BCM54140_HWMON_FROM_IN_3V3(v) \
drivers/net/phy/bcm54140.c
107
: BCM54140_HWMON_FROM_IN_1V0(v))
drivers/net/phy/bcm54140.c
83
#define BCM54140_HWMON_TO_TEMP(v) (413350L - (v) * 491)
drivers/net/phy/bcm54140.c
84
#define BCM54140_HWMON_FROM_TEMP(v) DIV_ROUND_CLOSEST_ULL(413350L - (v), 491)
drivers/net/phy/bcm54140.c
92
#define BCM54140_HWMON_TO_IN_1V0(v) ((v) * 2514 >> 11)
drivers/net/phy/bcm54140.c
93
#define BCM54140_HWMON_FROM_IN_1V0(v) DIV_ROUND_CLOSEST_ULL(((v) << 11), 2514)
drivers/net/phy/bcm7xxx.c
226
int v, ret;
drivers/net/phy/bcm7xxx.c
228
v = __phy_read(dev, location);
drivers/net/phy/bcm7xxx.c
229
if (v < 0)
drivers/net/phy/bcm7xxx.c
230
return v;
drivers/net/phy/bcm7xxx.c
232
v &= ~clr_mask;
drivers/net/phy/bcm7xxx.c
233
v |= set_mask;
drivers/net/phy/bcm7xxx.c
235
ret = __phy_write(dev, location, v);
drivers/net/phy/bcm7xxx.c
239
return v;
drivers/net/phy/microchip_rds_ptp.h
70
#define MCHP_RDS_PTP_TX_TS_CNT(v) (((v) & GENMASK(11, 8)) >> 8)
drivers/net/phy/microchip_rds_ptp.h
71
#define MCHP_RDS_PTP_RX_TS_CNT(v) ((v) & GENMASK(3, 0))
drivers/net/phy/sfp.c
635
unsigned int i, state, v;
drivers/net/phy/sfp.c
641
v = gpiod_get_value_cansleep(sfp->gpio[i]);
drivers/net/phy/sfp.c
642
if (v)
drivers/net/phy/sfp.c
869
u8 old, v;
drivers/net/phy/sfp.c
875
v = (old & ~mask) | (val & mask);
drivers/net/phy/sfp.c
876
if (v == old)
drivers/net/phy/sfp.c
877
return sizeof(v);
drivers/net/phy/sfp.c
879
return sfp_write(sfp, a2, addr, &v, sizeof(v));
drivers/net/ppp/bsd_comp.c
582
#define PUTBYTE(v) \
drivers/net/ppp/bsd_comp.c
587
*wptr++ = (unsigned char) (v); \
drivers/net/ppp/pppoe.c
1033
static int pppoe_seq_show(struct seq_file *seq, void *v)
drivers/net/ppp/pppoe.c
1038
if (v == SEQ_START_TOKEN) {
drivers/net/ppp/pppoe.c
1043
po = v;
drivers/net/ppp/pppoe.c
1080
static void *pppoe_seq_next(struct seq_file *seq, void *v, loff_t *pos)
drivers/net/ppp/pppoe.c
1086
if (v == SEQ_START_TOKEN) {
drivers/net/ppp/pppoe.c
1090
po = v;
drivers/net/ppp/pppoe.c
1109
static void pppoe_seq_stop(struct seq_file *seq, void *v)
drivers/net/slip/slip.c
1006
unsigned short v = 0;
drivers/net/slip/slip.c
1022
v = (v << 8) | s[i];
drivers/net/slip/slip.c
1026
c = 0x30 + ((v >> bits) & 0x3F);
drivers/net/slip/slip.c
1031
c = 0x30 + ((v << (6 - bits)) & 0x3F);
drivers/net/usb/asix_common.c
367
__le16 v;
drivers/net/usb/asix_common.c
368
int ret = asix_read_cmd(dev, AX_CMD_READ_RX_CTL, 0, 0, 2, &v, in_pm);
drivers/net/usb/asix_common.c
374
ret = le16_to_cpu(v);
drivers/net/usb/asix_common.c
394
__le16 v;
drivers/net/usb/asix_common.c
396
0, 0, 2, &v, in_pm);
drivers/net/usb/asix_common.c
404
return le16_to_cpu(v);
drivers/net/usb/pegasus.c
1007
static void pegasus_set_msglevel(struct net_device *dev, u32 v)
drivers/net/usb/pegasus.c
1010
pegasus->msg_enable = v;
drivers/net/usb/sr9800.c
222
__le16 v;
drivers/net/usb/sr9800.c
225
ret = sr_read_cmd(dev, SR_CMD_READ_RX_CTL, 0, 0, 2, &v);
drivers/net/usb/sr9800.c
232
ret = le16_to_cpu(v);
drivers/net/usb/sr9800.c
253
__le16 v;
drivers/net/usb/sr9800.c
256
ret = sr_read_cmd(dev, SR_CMD_READ_MEDIUM_STATUS, 0, 0, 2, &v);
drivers/net/usb/sr9800.c
263
return le16_to_cpu(v);
drivers/net/virtio_net.c
1685
typeof(vi) v = (vi); \
drivers/net/virtio_net.c
1688
if (v->curr_queue_pairs > nr_cpu_ids) { \
drivers/net/virtio_net.c
1689
qp = v->curr_queue_pairs - v->xdp_queue_pairs; \
drivers/net/virtio_net.c
1691
txq = netdev_get_tx_queue(v->dev, qp); \
drivers/net/virtio_net.c
1694
qp = cpu % v->curr_queue_pairs; \
drivers/net/virtio_net.c
1695
txq = netdev_get_tx_queue(v->dev, qp); \
drivers/net/virtio_net.c
1698
v->sq + qp; \
drivers/net/virtio_net.c
1703
typeof(vi) v = (vi); \
drivers/net/virtio_net.c
1705
txq = netdev_get_tx_queue(v->dev, (q) - v->sq); \
drivers/net/virtio_net.c
1706
if (v->curr_queue_pairs > nr_cpu_ids) \
drivers/net/virtio_net.c
4680
const __le64 *v;
drivers/net/virtio_net.c
4765
v = (const __le64 *)(base + desc[i].offset);
drivers/net/virtio_net.c
4766
ctx->data[offset] = le64_to_cpu(*v);
drivers/net/virtio_net.c
4788
const __le64 *v;
drivers/net/virtio_net.c
4894
v = (const __le64 *)(base + desc[i].offset);
drivers/net/virtio_net.c
4895
ctx->data[offset + i] = le64_to_cpu(*v);
drivers/net/virtio_net.c
6215
u16 v;
drivers/net/virtio_net.c
6218
struct virtio_net_config, status, &v) < 0)
drivers/net/virtio_net.c
6221
if (v & VIRTIO_NET_S_ANNOUNCE) {
drivers/net/virtio_net.c
6227
v &= VIRTIO_NET_S_LINK_UP;
drivers/net/virtio_net.c
6229
if (vi->status == v)
drivers/net/virtio_net.c
6232
vi->status = v;
drivers/net/virtio_net.c
7020
__le64 v;
drivers/net/virtio_net.c
7040
v = stats_cap->supported_stats_types[0];
drivers/net/virtio_net.c
7041
vi->device_stats_cap = le64_to_cpu(v);
drivers/net/vxlan/vxlan_multicast.c
104
struct vxlan_vni_node *v, *tmp;
drivers/net/vxlan/vxlan_multicast.c
111
list_for_each_entry_safe(v, tmp, &vg->vni_list, vlist) {
drivers/net/vxlan/vxlan_multicast.c
112
if (!vxlan_addr_multicast(&v->remote_ip))
drivers/net/vxlan/vxlan_multicast.c
116
&v->remote_ip,
drivers/net/vxlan/vxlan_multicast.c
182
struct vxlan_vni_node *v, *tmp, *vgood = NULL;
drivers/net/vxlan/vxlan_multicast.c
185
list_for_each_entry_safe(v, tmp, &vg->vni_list, vlist) {
drivers/net/vxlan/vxlan_multicast.c
186
if (!vxlan_addr_multicast(&v->remote_ip))
drivers/net/vxlan/vxlan_multicast.c
189
if (vxlan_addr_equal(&v->remote_ip,
drivers/net/vxlan/vxlan_multicast.c
192
ret = vxlan_igmp_join(vxlan, &v->remote_ip, 0);
drivers/net/vxlan/vxlan_multicast.c
197
vgood = v;
drivers/net/vxlan/vxlan_multicast.c
201
list_for_each_entry_safe(v, tmp, &vg->vni_list, vlist) {
drivers/net/vxlan/vxlan_multicast.c
202
if (!vxlan_addr_multicast(&v->remote_ip))
drivers/net/vxlan/vxlan_multicast.c
204
if (vxlan_addr_equal(&v->remote_ip,
drivers/net/vxlan/vxlan_multicast.c
207
vxlan_igmp_leave(vxlan, &v->remote_ip, 0);
drivers/net/vxlan/vxlan_multicast.c
208
if (v == vgood)
drivers/net/vxlan/vxlan_multicast.c
220
struct vxlan_vni_node *v, *tmp;
drivers/net/vxlan/vxlan_multicast.c
223
list_for_each_entry_safe(v, tmp, &vg->vni_list, vlist) {
drivers/net/vxlan/vxlan_multicast.c
224
if (vxlan_addr_multicast(&v->remote_ip) &&
drivers/net/vxlan/vxlan_multicast.c
225
!vxlan_group_used(vn, vxlan, v->vni, &v->remote_ip,
drivers/net/vxlan/vxlan_multicast.c
227
ret = vxlan_igmp_leave(vxlan, &v->remote_ip, 0);
drivers/net/vxlan/vxlan_vnifilter.c
100
struct vxlan_vni_node *v, *tmp;
drivers/net/vxlan/vxlan_vnifilter.c
107
list_for_each_entry_safe(v, tmp, &vg->vni_list, vlist) {
drivers/net/vxlan/vxlan_vnifilter.c
108
hlist_del_init_rcu(&v->hlist4.hlist);
drivers/net/vxlan/vxlan_vnifilter.c
110
hlist_del_init_rcu(&v->hlist6.hlist);
drivers/net/vxlan/vxlan_vnifilter.c
336
struct vxlan_vni_node *tmp, *v, *vbegin = NULL, *vend = NULL;
drivers/net/vxlan/vxlan_vnifilter.c
365
list_for_each_entry_safe(v, tmp, &vg->vni_list, vlist) {
drivers/net/vxlan/vxlan_vnifilter.c
371
vbegin = v;
drivers/net/vxlan/vxlan_vnifilter.c
372
vend = v;
drivers/net/vxlan/vxlan_vnifilter.c
375
if (!dump_stats && vnirange(vend, v) == 1 &&
drivers/net/vxlan/vxlan_vnifilter.c
376
vxlan_addr_equal(&v->remote_ip, &vend->remote_ip)) {
drivers/net/vxlan/vxlan_vnifilter.c
385
vbegin = v;
drivers/net/vxlan/vxlan_vnifilter.c
388
vend = v;
drivers/net/vxlan/vxlan_vnifilter.c
40
struct vxlan_vni_node *v,
drivers/net/vxlan/vxlan_vnifilter.c
49
if (!hlist_unhashed(&v->hlist4.hlist))
drivers/net/vxlan/vxlan_vnifilter.c
50
hlist_del_init_rcu(&v->hlist4.hlist);
drivers/net/vxlan/vxlan_vnifilter.c
52
if (!hlist_unhashed(&v->hlist6.hlist))
drivers/net/vxlan/vxlan_vnifilter.c
53
hlist_del_init_rcu(&v->hlist6.hlist);
drivers/net/vxlan/vxlan_vnifilter.c
60
if (vs && v) {
drivers/net/vxlan/vxlan_vnifilter.c
61
node = &v->hlist6;
drivers/net/vxlan/vxlan_vnifilter.c
62
hlist_add_head_rcu(&node->hlist, vni_head(vs, v->vni));
drivers/net/vxlan/vxlan_vnifilter.c
66
if (vs && v) {
drivers/net/vxlan/vxlan_vnifilter.c
67
node = &v->hlist4;
drivers/net/vxlan/vxlan_vnifilter.c
671
struct vxlan_vni_node *v)
drivers/net/vxlan/vxlan_vnifilter.c
679
if (be32_to_cpu(v->vni) < be32_to_cpu(vent->vni))
drivers/net/vxlan/vxlan_vnifilter.c
68
hlist_add_head_rcu(&node->hlist, vni_head(vs, v->vni));
drivers/net/vxlan/vxlan_vnifilter.c
684
list_add_rcu(&v->vlist, hpos);
drivers/net/vxlan/vxlan_vnifilter.c
689
struct vxlan_vni_node *v)
drivers/net/vxlan/vxlan_vnifilter.c
691
list_del_rcu(&v->vlist);
drivers/net/vxlan/vxlan_vnifilter.c
729
__be32 v = cpu_to_be32(vni);
drivers/net/vxlan/vxlan_vnifilter.c
733
if (vxlan_vnifilter_lookup(vxlan, v))
drivers/net/vxlan/vxlan_vnifilter.c
734
return vxlan_vni_update(vxlan, vg, v, group, &changed, extack);
drivers/net/vxlan/vxlan_vnifilter.c
736
err = vxlan_vni_in_use(vxlan->net, vxlan, &vxlan->cfg, v);
drivers/net/vxlan/vxlan_vnifilter.c
742
vninode = vxlan_vni_alloc(vxlan, v);
drivers/net/vxlan/vxlan_vnifilter.c
77
struct vxlan_vni_node *v, *tmp;
drivers/net/vxlan/vxlan_vnifilter.c
770
struct vxlan_vni_node *v;
drivers/net/vxlan/vxlan_vnifilter.c
772
v = container_of(rcu, struct vxlan_vni_node, rcu);
drivers/net/vxlan/vxlan_vnifilter.c
773
vxlan_vni_free(v);
drivers/net/vxlan/vxlan_vnifilter.c
781
__be32 v = cpu_to_be32(vni);
drivers/net/vxlan/vxlan_vnifilter.c
786
vninode = rhashtable_lookup_fast(&vg->vni_hash, &v,
drivers/net/vxlan/vxlan_vnifilter.c
820
int v, err = 0;
drivers/net/vxlan/vxlan_vnifilter.c
824
for (v = start_vni; v <= end_vni; v++) {
drivers/net/vxlan/vxlan_vnifilter.c
827
err = vxlan_vni_add(vxlan, vg, v, group, extack);
drivers/net/vxlan/vxlan_vnifilter.c
830
err = vxlan_vni_del(vxlan, vg, v, extack);
drivers/net/vxlan/vxlan_vnifilter.c
85
list_for_each_entry_safe(v, tmp, &vg->vni_list, vlist) {
drivers/net/vxlan/vxlan_vnifilter.c
88
node = &v->hlist6;
drivers/net/vxlan/vxlan_vnifilter.c
904
struct vxlan_vni_node *v, *tmp;
drivers/net/vxlan/vxlan_vnifilter.c
908
list_for_each_entry_safe(v, tmp, &vg->vni_list, vlist) {
drivers/net/vxlan/vxlan_vnifilter.c
909
rhashtable_remove_fast(&vg->vni_hash, &v->vnode,
drivers/net/vxlan/vxlan_vnifilter.c
91
node = &v->hlist4;
drivers/net/vxlan/vxlan_vnifilter.c
911
hlist_del_init_rcu(&v->hlist4.hlist);
drivers/net/vxlan/vxlan_vnifilter.c
913
hlist_del_init_rcu(&v->hlist6.hlist);
drivers/net/vxlan/vxlan_vnifilter.c
915
__vxlan_vni_del_list(vg, v);
drivers/net/vxlan/vxlan_vnifilter.c
916
vxlan_vnifilter_notify(vxlan, v, RTM_DELTUNNEL);
drivers/net/vxlan/vxlan_vnifilter.c
917
call_rcu(&v->rcu, vxlan_vni_node_rcu_free);
drivers/net/vxlan/vxlan_vnifilter.c
93
hlist_add_head_rcu(&node->hlist, vni_head(vs, v->vni));
drivers/net/wireguard/selftest/counter.c
24
#define T(n, v) do { \
drivers/net/wireguard/selftest/counter.c
26
if (counter_validate(counter, n) != (v)) { \
drivers/net/wireless/ath/ath10k/bmi.h
259
__le32 v = __cpu_to_le32(val); \
drivers/net/wireless/ath/ath10k/bmi.h
263
(u8 *)&v, sizeof(v)); \
drivers/net/wireless/ath/ath10k/wmi.c
3585
u32 v, tim_len;
drivers/net/wireless/ath/ath10k/wmi.c
3606
v = __le32_to_cpu(t);
drivers/net/wireless/ath/ath10k/wmi.c
3607
arvif->u.ap.tim_bitmap[i] = (v >> ((i % 4) * 8)) & 0xFF;
drivers/net/wireless/ath/ath11k/mac.c
2358
u16 he_tx_mcs = 0, v = 0;
drivers/net/wireless/ath/ath11k/mac.c
2514
v = le16_to_cpu(he_cap->he_mcs_nss_supp.rx_mcs_80p80);
drivers/net/wireless/ath/ath11k/mac.c
2515
v = ath11k_peer_assoc_h_he_limit(v, he_mcs_mask);
drivers/net/wireless/ath/ath11k/mac.c
2516
arg->peer_he_rx_mcs_set[WMI_HECAP_TXRX_MCS_NSS_IDX_80_80] = v;
drivers/net/wireless/ath/ath11k/mac.c
2518
v = le16_to_cpu(he_cap->he_mcs_nss_supp.tx_mcs_80p80);
drivers/net/wireless/ath/ath11k/mac.c
2519
arg->peer_he_tx_mcs_set[WMI_HECAP_TXRX_MCS_NSS_IDX_80_80] = v;
drivers/net/wireless/ath/ath11k/mac.c
2522
he_tx_mcs = v;
drivers/net/wireless/ath/ath11k/mac.c
2524
v = le16_to_cpu(he_cap->he_mcs_nss_supp.rx_mcs_160);
drivers/net/wireless/ath/ath11k/mac.c
2525
v = ath11k_peer_assoc_h_he_limit(v, he_mcs_mask);
drivers/net/wireless/ath/ath11k/mac.c
2526
arg->peer_he_rx_mcs_set[WMI_HECAP_TXRX_MCS_NSS_IDX_160] = v;
drivers/net/wireless/ath/ath11k/mac.c
2528
v = le16_to_cpu(he_cap->he_mcs_nss_supp.tx_mcs_160);
drivers/net/wireless/ath/ath11k/mac.c
2529
arg->peer_he_tx_mcs_set[WMI_HECAP_TXRX_MCS_NSS_IDX_160] = v;
drivers/net/wireless/ath/ath11k/mac.c
2533
he_tx_mcs = v;
drivers/net/wireless/ath/ath11k/mac.c
2537
v = le16_to_cpu(he_cap->he_mcs_nss_supp.rx_mcs_80);
drivers/net/wireless/ath/ath11k/mac.c
2538
v = ath11k_peer_assoc_h_he_limit(v, he_mcs_mask);
drivers/net/wireless/ath/ath11k/mac.c
2539
arg->peer_he_rx_mcs_set[WMI_HECAP_TXRX_MCS_NSS_IDX_80] = v;
drivers/net/wireless/ath/ath11k/mac.c
2541
v = le16_to_cpu(he_cap->he_mcs_nss_supp.tx_mcs_80);
drivers/net/wireless/ath/ath11k/mac.c
2542
arg->peer_he_tx_mcs_set[WMI_HECAP_TXRX_MCS_NSS_IDX_80] = v;
drivers/net/wireless/ath/ath11k/mac.c
2546
he_tx_mcs = v;
drivers/net/wireless/ath/ath11k/pci.c
257
u32 v;
drivers/net/wireless/ath/ath11k/pci.c
260
v = ath11k_pcic_read32(ab, offset);
drivers/net/wireless/ath/ath11k/pci.c
261
if ((v & mask) == value)
drivers/net/wireless/ath/ath11k/pci.c
265
ath11k_pcic_write32(ab, offset, (v & ~mask) | value);
drivers/net/wireless/ath/ath11k/pci.c
267
v = ath11k_pcic_read32(ab, offset);
drivers/net/wireless/ath/ath11k/pci.c
268
if ((v & mask) == value)
drivers/net/wireless/ath/ath11k/pci.c
275
offset, v & mask, value);
drivers/net/wireless/ath/ath12k/dp_htt.c
198
u32 v, succ_bytes = 0;
drivers/net/wireless/ath/ath12k/dp_htt.c
313
v = ath12k_he_ru_tones_to_nl80211_he_ru_alloc(tones);
drivers/net/wireless/ath/ath12k/dp_htt.c
314
peer->txrate.he_ru_alloc = v;
drivers/net/wireless/ath/ath12k/dp_htt.c
325
v = ath12k_mac_eht_ru_tones_to_nl80211_eht_ru_alloc(tones);
drivers/net/wireless/ath/ath12k/dp_htt.c
326
peer->txrate.eht_ru_alloc = v;
drivers/net/wireless/ath/ath12k/mac.c
2593
u16 he_tx_mcs = 0, v = 0;
drivers/net/wireless/ath/ath12k/mac.c
2751
v = le16_to_cpu(he_cap->he_mcs_nss_supp.rx_mcs_160);
drivers/net/wireless/ath/ath12k/mac.c
2752
v = ath12k_peer_assoc_h_he_limit(v, he_mcs_mask);
drivers/net/wireless/ath/ath12k/mac.c
2753
arg->peer_he_rx_mcs_set[WMI_HECAP_TXRX_MCS_NSS_IDX_160] = v;
drivers/net/wireless/ath/ath12k/mac.c
2755
v = le16_to_cpu(he_cap->he_mcs_nss_supp.tx_mcs_160);
drivers/net/wireless/ath/ath12k/mac.c
2756
arg->peer_he_tx_mcs_set[WMI_HECAP_TXRX_MCS_NSS_IDX_160] = v;
drivers/net/wireless/ath/ath12k/mac.c
2760
he_tx_mcs = v;
drivers/net/wireless/ath/ath12k/mac.c
2764
v = le16_to_cpu(he_cap->he_mcs_nss_supp.rx_mcs_80);
drivers/net/wireless/ath/ath12k/mac.c
2765
v = ath12k_peer_assoc_h_he_limit(v, he_mcs_mask);
drivers/net/wireless/ath/ath12k/mac.c
2766
arg->peer_he_rx_mcs_set[WMI_HECAP_TXRX_MCS_NSS_IDX_80] = v;
drivers/net/wireless/ath/ath12k/mac.c
2768
v = le16_to_cpu(he_cap->he_mcs_nss_supp.tx_mcs_80);
drivers/net/wireless/ath/ath12k/mac.c
2769
arg->peer_he_tx_mcs_set[WMI_HECAP_TXRX_MCS_NSS_IDX_80] = v;
drivers/net/wireless/ath/ath12k/mac.c
2773
he_tx_mcs = v;
drivers/net/wireless/ath/ath12k/pci.c
1414
memcpy_fromio(buf, ab->qmi.target_mem[i].v.ioaddr,
drivers/net/wireless/ath/ath12k/qmi.c
2500
if (mlo_chunk->v.addr)
drivers/net/wireless/ath/ath12k/qmi.c
2505
memset(mlo_chunk->v.addr, 0, mlo_chunk->size);
drivers/net/wireless/ath/ath12k/qmi.c
2530
if (fixed_mem && mlo_chunk->v.ioaddr) {
drivers/net/wireless/ath/ath12k/qmi.c
2531
iounmap(mlo_chunk->v.ioaddr);
drivers/net/wireless/ath/ath12k/qmi.c
2532
mlo_chunk->v.ioaddr = NULL;
drivers/net/wireless/ath/ath12k/qmi.c
2533
} else if (mlo_chunk->v.addr) {
drivers/net/wireless/ath/ath12k/qmi.c
2536
mlo_chunk->v.addr,
drivers/net/wireless/ath/ath12k/qmi.c
2538
mlo_chunk->v.addr = NULL;
drivers/net/wireless/ath/ath12k/qmi.c
2544
chunk->v.ioaddr = NULL;
drivers/net/wireless/ath/ath12k/qmi.c
2546
chunk->v.addr = NULL;
drivers/net/wireless/ath/ath12k/qmi.c
2563
ab->qmi.target_mem[i].v.ioaddr) {
drivers/net/wireless/ath/ath12k/qmi.c
2564
iounmap(ab->qmi.target_mem[i].v.ioaddr);
drivers/net/wireless/ath/ath12k/qmi.c
2565
ab->qmi.target_mem[i].v.ioaddr = NULL;
drivers/net/wireless/ath/ath12k/qmi.c
2567
if (!ab->qmi.target_mem[i].v.addr)
drivers/net/wireless/ath/ath12k/qmi.c
2571
ab->qmi.target_mem[i].v.addr,
drivers/net/wireless/ath/ath12k/qmi.c
2573
ab->qmi.target_mem[i].v.addr = NULL;
drivers/net/wireless/ath/ath12k/qmi.c
2590
if (chunk->v.addr) {
drivers/net/wireless/ath/ath12k/qmi.c
2597
chunk->v.addr, chunk->paddr);
drivers/net/wireless/ath/ath12k/qmi.c
2598
chunk->v.addr = NULL;
drivers/net/wireless/ath/ath12k/qmi.c
2601
chunk->v.addr = dma_alloc_coherent(ab->dev,
drivers/net/wireless/ath/ath12k/qmi.c
2605
if (!chunk->v.addr) {
drivers/net/wireless/ath/ath12k/qmi.c
2682
memset(mlo_chunk->v.addr, 0, mlo_chunk->size);
drivers/net/wireless/ath/ath12k/qmi.c
2686
chunk->v.addr = mlo_chunk->v.addr;
drivers/net/wireless/ath/ath12k/qmi.c
2694
chunk->v.addr = NULL;
drivers/net/wireless/ath/ath12k/qmi.c
2755
ab->qmi.target_mem[idx].v.ioaddr =
drivers/net/wireless/ath/ath12k/qmi.c
2758
if (!ab->qmi.target_mem[idx].v.ioaddr) {
drivers/net/wireless/ath/ath12k/qmi.c
2785
ab->qmi.target_mem[idx].v.ioaddr =
drivers/net/wireless/ath/ath12k/qmi.c
2788
if (!ab->qmi.target_mem[idx].v.ioaddr) {
drivers/net/wireless/ath/ath12k/qmi.c
2803
ab->qmi.target_mem[idx].v.ioaddr = NULL;
drivers/net/wireless/ath/ath12k/qmi.c
2827
ab->qmi.target_mem[idx].v.ioaddr =
drivers/net/wireless/ath/ath12k/qmi.c
2830
if (!ab->qmi.target_mem[idx].v.ioaddr) {
drivers/net/wireless/ath/ath12k/qmi.h
107
} v;
drivers/net/wireless/ath/ath12k/wmi.c
2177
__le32 v;
drivers/net/wireless/ath/ath12k/wmi.c
2422
v = cpu_to_le32(ATH12K_WMI_FLAG_MLO_LINK_ID_VALID);
drivers/net/wireless/ath/ath12k/wmi.c
2423
partner_info->flags |= v;
drivers/net/wireless/ath/ath5k/debug.c
181
unsigned int v;
drivers/net/wireless/ath/ath5k/debug.c
184
v = ath5k_hw_reg_read(ah, AR5K_BEACON);
drivers/net/wireless/ath/ath5k/debug.c
187
"AR5K_BEACON", v, v & AR5K_BEACON_PERIOD,
drivers/net/wireless/ath/ath5k/debug.c
188
(v & AR5K_BEACON_TIM) >> AR5K_BEACON_TIM_S);
drivers/net/wireless/ath/ath5k/debug.c
196
v = ath5k_hw_reg_read(ah, AR5K_TIMER0);
drivers/net/wireless/ath/ath5k/debug.c
198
"AR5K_TIMER0 (TBTT)", v, v);
drivers/net/wireless/ath/ath5k/debug.c
200
v = ath5k_hw_reg_read(ah, AR5K_TIMER1);
drivers/net/wireless/ath/ath5k/debug.c
202
"AR5K_TIMER1 (DMA)", v, v >> 3);
drivers/net/wireless/ath/ath5k/debug.c
204
v = ath5k_hw_reg_read(ah, AR5K_TIMER2);
drivers/net/wireless/ath/ath5k/debug.c
206
"AR5K_TIMER2 (SWBA)", v, v >> 3);
drivers/net/wireless/ath/ath5k/debug.c
208
v = ath5k_hw_reg_read(ah, AR5K_TIMER3);
drivers/net/wireless/ath/ath5k/debug.c
210
"AR5K_TIMER3 (ATIM)", v, v);
drivers/net/wireless/ath/ath5k/debug.c
365
unsigned int v;
drivers/net/wireless/ath/ath5k/debug.c
383
v = ath5k_hw_reg_read(ah, AR5K_DEFAULT_ANTENNA);
drivers/net/wireless/ath/ath5k/debug.c
385
"\nAR5K_DEFAULT_ANTENNA\t0x%08x\n", v);
drivers/net/wireless/ath/ath5k/debug.c
387
v = ath5k_hw_reg_read(ah, AR5K_STA_ID1);
drivers/net/wireless/ath/ath5k/debug.c
390
(v & AR5K_STA_ID1_DEFAULT_ANTENNA) != 0);
drivers/net/wireless/ath/ath5k/debug.c
393
(v & AR5K_STA_ID1_DESC_ANTENNA) != 0);
drivers/net/wireless/ath/ath5k/debug.c
396
(v & AR5K_STA_ID1_RTS_DEF_ANTENNA) != 0);
drivers/net/wireless/ath/ath5k/debug.c
399
(v & AR5K_STA_ID1_SELFGEN_DEF_ANT) != 0);
drivers/net/wireless/ath/ath5k/debug.c
401
v = ath5k_hw_reg_read(ah, AR5K_PHY_AGCCTL);
drivers/net/wireless/ath/ath5k/debug.c
404
(v & AR5K_PHY_AGCCTL_OFDM_DIV_DIS) != 0);
drivers/net/wireless/ath/ath5k/debug.c
406
v = ath5k_hw_reg_read(ah, AR5K_PHY_RESTART);
drivers/net/wireless/ath/ath5k/debug.c
409
(v & AR5K_PHY_RESTART_DIV_GC) >> AR5K_PHY_RESTART_DIV_GC_S);
drivers/net/wireless/ath/ath5k/debug.c
411
v = ath5k_hw_reg_read(ah, AR5K_PHY_FAST_ANT_DIV);
drivers/net/wireless/ath/ath5k/debug.c
414
(v & AR5K_PHY_FAST_ANT_DIV_EN) != 0);
drivers/net/wireless/ath/ath5k/debug.c
416
v = ath5k_hw_reg_read(ah, AR5K_PHY_ANT_SWITCH_TABLE_0);
drivers/net/wireless/ath/ath5k/debug.c
418
"\nAR5K_PHY_ANT_SWITCH_TABLE_0\t0x%08x\n", v);
drivers/net/wireless/ath/ath5k/debug.c
419
v = ath5k_hw_reg_read(ah, AR5K_PHY_ANT_SWITCH_TABLE_1);
drivers/net/wireless/ath/ath5k/debug.c
421
"AR5K_PHY_ANT_SWITCH_TABLE_1\t0x%08x\n", v);
drivers/net/wireless/ath/ath6kl/bmi.h
229
__le32 v; \
drivers/net/wireless/ath/ath6kl/bmi.h
232
v = cpu_to_le32(val); \
drivers/net/wireless/ath/ath6kl/bmi.h
233
ath6kl_bmi_write(ar, addr, (u8 *) &v, sizeof(v)); \
drivers/net/wireless/ath/ath6kl/target.h
133
#define SM(f, v) (((v) << f##_S) & f)
drivers/net/wireless/ath/ath6kl/target.h
134
#define MS(f, v) (((v) & f) >> f##_S)
drivers/net/wireless/ath/carl9170/cmd.c
105
4, (u8 *)&v,
drivers/net/wireless/ath/carl9170/cmd.c
110
if (v != echores) {
drivers/net/wireless/ath/carl9170/cmd.c
111
wiphy_info(ar->hw->wiphy, "wrong echo %x != %x", v, echores);
drivers/net/wireless/ath/carl9170/cmd.c
99
int carl9170_echo_test(struct ar9170 *ar, const u32 v)
drivers/net/wireless/ath/carl9170/cmd.h
153
#define carl9170_async_regwrite(r, v) do { \
drivers/net/wireless/ath/carl9170/cmd.h
157
__cmd->wreg.regs[__nreg].val = cpu_to_le32(v); \
drivers/net/wireless/ath/carl9170/cmd.h
49
int carl9170_echo_test(struct ar9170 *ar, u32 v);
drivers/net/wireless/ath/carl9170/cmd.h
87
#define carl9170_regwrite(r, v) do { \
drivers/net/wireless/ath/carl9170/cmd.h
89
__ar->cmd_buf[2 * __nreg + 2] = cpu_to_le32(v); \
drivers/net/wireless/ath/carl9170/mac.c
402
u32 v = 0;
drivers/net/wireless/ath/carl9170/mac.c
416
SET_VAL(AR9170_MAC_BCN_DTIM, v,
drivers/net/wireless/ath/carl9170/mac.c
422
v |= AR9170_MAC_BCN_IBSS_MODE;
drivers/net/wireless/ath/carl9170/mac.c
425
v |= AR9170_MAC_BCN_AP_MODE;
drivers/net/wireless/ath/carl9170/mac.c
434
SET_VAL(AR9170_MAC_BCN_DTIM, v,
drivers/net/wireless/ath/carl9170/mac.c
437
v |= AR9170_MAC_BCN_STA_PS |
drivers/net/wireless/ath/carl9170/mac.c
459
SET_VAL(AR9170_MAC_BCN_PERIOD, v, ar->global_beacon_int);
drivers/net/wireless/ath/carl9170/mac.c
465
carl9170_regwrite(AR9170_MAC_REG_BCN_PERIOD, v);
drivers/net/wireless/ath/wil6210/debugfs.c
100
v = (ring_id % 2 ? (v >> 16) : (v & 0xffff));
drivers/net/wireless/ath/wil6210/debugfs.c
101
seq_printf(s, " hwhead = %u\n", v);
drivers/net/wireless/ath/wil6210/debugfs.c
106
v = readl(x);
drivers/net/wireless/ath/wil6210/debugfs.c
107
seq_printf(s, "0x%08x = %d\n", v, v);
drivers/net/wireless/ath/wil6210/debugfs.c
198
u32 v;
drivers/net/wireless/ath/wil6210/debugfs.c
213
v = readl_relaxed(x);
drivers/net/wireless/ath/wil6210/debugfs.c
215
v = (sring_idx % 2 ? (v >> 16) : (v & 0xffff));
drivers/net/wireless/ath/wil6210/debugfs.c
216
seq_printf(s, " hwhead = %u\n", v);
drivers/net/wireless/ath/wil6210/debugfs.c
221
v = readl_relaxed(x);
drivers/net/wireless/ath/wil6210/debugfs.c
222
seq_printf(s, "0x%08x = %d\n", v, v);
drivers/net/wireless/ath/wil6210/debugfs.c
79
u32 v;
drivers/net/wireless/ath/wil6210/debugfs.c
98
v = readl_relaxed(x);
drivers/net/wireless/ath/wil6210/fw_inc.c
303
u32 v;
drivers/net/wireless/ath/wil6210/fw_inc.c
324
v = le32_to_cpu(d->value);
drivers/net/wireless/ath/wil6210/fw_inc.c
326
le32_to_cpu(d->addr), v, s);
drivers/net/wireless/ath/wil6210/fw_inc.c
327
wil_memset_toio_32(dst, v, s);
drivers/net/wireless/ath/wil6210/fw_inc.c
375
u32 v = le32_to_cpu(block[i].value);
drivers/net/wireless/ath/wil6210/fw_inc.c
382
y = (x & m) | (v & ~m);
drivers/net/wireless/ath/wil6210/fw_inc.c
385
le32_to_cpu(block[i].addr), y, x, v, m);
drivers/net/wireless/ath/wil6210/fw_inc.c
465
u32 v = le32_to_cpu(block[i].value);
drivers/net/wireless/ath/wil6210/fw_inc.c
468
i, a, v);
drivers/net/wireless/ath/wil6210/fw_inc.c
470
writel(v, gwa_val);
drivers/net/wireless/ath/wil6210/fw_inc.c
534
u32 v[ARRAY_SIZE(block->value)];
drivers/net/wireless/ath/wil6210/fw_inc.c
537
v[k] = le32_to_cpu(block[i].value[k]);
drivers/net/wireless/ath/wil6210/fw_inc.c
540
wil_hex_dump_fw(" val ", DUMP_PREFIX_NONE, 16, 4, v,
drivers/net/wireless/ath/wil6210/fw_inc.c
541
sizeof(v), false);
drivers/net/wireless/ath/wil6210/fw_inc.c
544
writel(v[k], gwa_val[k]);
drivers/net/wireless/ath/wil6210/txrx.c
1009
struct wil_ring *v = &wil->ring_rx;
drivers/net/wireless/ath/wil6210/txrx.c
1012
if (unlikely(!v->va)) {
drivers/net/wireless/ath/wil6210/txrx.c
1017
while ((*quota > 0) && (NULL != (skb = wil_vring_reap_rx(wil, v)))) {
drivers/net/wireless/ath/wil6210/txrx.c
1032
wil_rx_refill(wil, v->size);
drivers/net/wireless/ath/wil6210/txrx.c
1419
struct wil_ring *v = &wil->ring_tx[i];
drivers/net/wireless/ath/wil6210/txrx.c
1424
if (v->va && txdata->enabled) {
drivers/net/wireless/ath/wil6210/txrx.c
1425
return v;
drivers/net/wireless/ath/wil6210/txrx.c
1494
struct wil_ring *v;
drivers/net/wireless/ath/wil6210/txrx.c
1500
v = &wil->ring_tx[i];
drivers/net/wireless/ath/wil6210/txrx.c
1502
if (!v->va || !txdata->enabled)
drivers/net/wireless/ath/wil6210/txrx.c
1508
return v;
drivers/net/wireless/ath/wil6210/txrx.c
1553
struct wil_ring *v, *v2;
drivers/net/wireless/ath/wil6210/txrx.c
1563
v = &wil->ring_tx[i];
drivers/net/wireless/ath/wil6210/txrx.c
1565
if (!v->va || !txdata->enabled || txdata->mid != vif->mid)
drivers/net/wireless/ath/wil6210/txrx.c
1618
return v;
drivers/net/wireless/ath/wil6210/txrx.c
608
struct wil_ring *v = &wil->ring_rx;
drivers/net/wireless/ath/wil6210/txrx.c
614
for (; next_tail = wil_ring_next_tail(v),
drivers/net/wireless/ath/wil6210/txrx.c
615
(next_tail != v->swhead) && (count-- > 0);
drivers/net/wireless/ath/wil6210/txrx.c
616
v->swtail = next_tail) {
drivers/net/wireless/ath/wil6210/txrx.c
617
rc = wil_vring_alloc_skb(wil, v, v->swtail, headroom);
drivers/net/wireless/ath/wil6210/txrx.c
620
rc, v->swtail);
drivers/net/wireless/ath/wil6210/txrx.c
630
wil_w(wil, v->hwtail, v->swtail);
drivers/net/wireless/ath/wil6210/wil6210.h
1073
#define vif_to_wil(v) (v->wil)
drivers/net/wireless/ath/wil6210/wil6210.h
1074
#define vif_to_ndev(v) (v->ndev)
drivers/net/wireless/ath/wil6210/wil6210.h
1075
#define vif_to_wdev(v) (&v->wdev)
drivers/net/wireless/broadcom/b43/lo.c
132
u16 reg, v, padmix;
drivers/net/wireless/broadcom/b43/lo.c
135
v = 0x30;
drivers/net/wireless/broadcom/b43/lo.c
146
v = 0x10;
drivers/net/wireless/broadcom/b43/lo.c
150
v = 0x30;
drivers/net/wireless/broadcom/b43/lo.c
155
*value = v;
drivers/net/wireless/broadcom/b43/main.c
3467
u32 v, backup0, backup4;
drivers/net/wireless/broadcom/b43/main.c
3510
v = b43_read32(dev, B43_MMIO_MACCTL);
drivers/net/wireless/broadcom/b43/main.c
3511
v |= B43_MACCTL_GMODE;
drivers/net/wireless/broadcom/b43/main.c
3512
if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
drivers/net/wireless/broadcom/brcm80211/brcmfmac/bcmsdh.c
226
u32 v, bar0 = addr & SBSDIO_SBWINDOW_MASK;
drivers/net/wireless/broadcom/brcm80211/brcmfmac/bcmsdh.c
232
v = bar0 >> 8;
drivers/net/wireless/broadcom/brcm80211/brcmfmac/bcmsdh.c
234
for (i = 0 ; i < 3 && !err ; i++, v >>= 8)
drivers/net/wireless/broadcom/brcm80211/brcmfmac/bcmsdh.c
236
v & 0xff, &err);
drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.h
296
#define brcmf_sdiod_func0_wb(sdiodev, addr, v, ret) \
drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.h
297
sdio_f0_writeb((sdiodev)->func1, (v), (addr), (ret))
drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.h
303
#define brcmf_sdiod_writeb(sdiodev, addr, v, ret) \
drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.h
304
sdio_writeb((sdiodev)->func1, (v), (addr), (ret))
drivers/net/wireless/broadcom/brcm80211/brcmsmac/d11.h
658
#define PHY_TYPE(v) ((v & PV_PT_MASK) >> PV_PT_SHIFT)
drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c
1587
u16 v;
drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c
1592
v = SYNTHPU_DLY_LPPHY_US;
drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c
1594
v = SYNTHPU_DLY_NPHY_US;
drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c
1596
v = SYNTHPU_DLY_BPHY_US;
drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c
1598
brcms_b_write_shm(wlc_hw, M_SYNTHPU_DLY, v);
drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c
1927
bool v, clk, xtal;
drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c
1956
v = ((bcma_read32(wlc_hw->d11core,
drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c
1966
return v;
drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c
2910
brcms_b_write_objmem(struct brcms_hardware *wlc_hw, uint offset, u16 v,
drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c
2921
bcma_wflush16(core, objoff, v);
drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c
2937
void brcms_b_write_shm(struct brcms_hardware *wlc_hw, uint offset, u16 v)
drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c
2939
brcms_b_write_objmem(wlc_hw, offset, v, OBJADDR_SHM_SEL);
drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c
2952
u16 v;
drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c
2960
v = p[i] | (p[i + 1] << 8);
drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c
2961
brcms_b_write_objmem(wlc_hw, offset + i, v, sel);
drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c
2975
u16 v;
drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c
2983
v = brcms_b_read_objmem(wlc_hw, offset + i, sel);
drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c
2984
p[i] = v & 0xFF;
drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c
2985
p[i + 1] = (v >> 8) & 0xFF;
drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c
742
static void brcms_b_core_ioctl(struct brcms_hardware *wlc_hw, u32 m, u32 v)
drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c
747
bcma_awrite32(core, BCMA_IOCTL, ioctl | v);
drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.h
641
void brcms_b_write_shm(struct brcms_hardware *wlc_hw, uint offset, u16 v);
drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_int.h
1040
#define wlc_nphy_table_data_write(pi, w, v) \
drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_int.h
1041
wlc_phy_table_data_write((pi), (w), (v))
drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy_shim.c
100
brcms_b_write_shm(physhim->wlc_hw, offset, v);
drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy_shim.c
98
void wlapi_bmac_write_shm(struct phy_shim_info *physhim, uint offset, u16 v)
drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy_shim.h
143
void wlapi_bmac_write_shm(struct phy_shim_info *physhim, uint offset, u16 v);
drivers/net/wireless/broadcom/brcm80211/brcmsmac/types.h
259
#define bcma_wflush16(c, o, v) \
drivers/net/wireless/broadcom/brcm80211/brcmsmac/types.h
260
({ bcma_write16(c, o, v); (void)bcma_read16(c, o); })
drivers/net/wireless/broadcom/brcm80211/brcmsmac/types.h
262
#define bcma_wflush16(c, o, v) bcma_write16(c, o, v)
drivers/net/wireless/intel/ipw2x00/ipw2100.c
2177
#define IPW2100_HANDLER(v, f) { v, f, # v }
drivers/net/wireless/intel/ipw2x00/ipw2100.c
2184
#define IPW2100_HANDLER(v, f) { v, f }
drivers/net/wireless/intel/ipw2x00/ipw2100.c
3411
void *v;
drivers/net/wireless/intel/ipw2x00/ipw2100.c
3420
v = dma_alloc_coherent(&priv->pci_dev->dev,
drivers/net/wireless/intel/ipw2x00/ipw2100.c
3423
if (!v) {
drivers/net/wireless/intel/ipw2x00/ipw2100.c
3433
(struct ipw2100_cmd_header *)v;
drivers/net/wireless/intel/ipw2x00/ipw2100.c
4398
void *v;
drivers/net/wireless/intel/ipw2x00/ipw2100.c
4418
v = dma_alloc_coherent(&priv->pci_dev->dev,
drivers/net/wireless/intel/ipw2x00/ipw2100.c
4421
if (!v) {
drivers/net/wireless/intel/ipw2x00/ipw2100.c
4431
(struct ipw2100_data_header *)v;
drivers/net/wireless/intel/ipw2x00/ipw2200.c
2413
__le32 v = cpu_to_le32(phy_off);
drivers/net/wireless/intel/ipw2x00/ipw2200.c
2419
return ipw_send_cmd_pdu(priv, IPW_CMD_CARD_DISABLE, sizeof(v), &v);
drivers/net/wireless/intel/ipw2x00/libipw_crypto_tkip.c
160
static inline u16 Mk16_le(__le16 * v)
drivers/net/wireless/intel/ipw2x00/libipw_crypto_tkip.c
162
return le16_to_cpu(*v);
drivers/net/wireless/intel/ipw2x00/libipw_crypto_tkip.c
200
static inline u16 _S_(u16 v)
drivers/net/wireless/intel/ipw2x00/libipw_crypto_tkip.c
202
u16 t = Sbox[Hi8(v)];
drivers/net/wireless/intel/ipw2x00/libipw_crypto_tkip.c
203
return Sbox[Lo8(v)] ^ ((t << 8) | (t >> 8));
drivers/net/wireless/intel/ipw2x00/libipw_module.c
212
static int debug_level_proc_show(struct seq_file *m, void *v)
drivers/net/wireless/intel/iwlwifi/fw/debugfs.c
333
void *v, loff_t *pos)
drivers/net/wireless/intel/iwlwifi/fw/debugfs.c
335
struct iwl_dbgfs_fw_info_state *state = v;
drivers/net/wireless/intel/iwlwifi/fw/debugfs.c
349
void *v)
drivers/net/wireless/intel/iwlwifi/fw/debugfs.c
351
kfree(v);
drivers/net/wireless/intel/iwlwifi/fw/debugfs.c
370
static int iwl_dbgfs_fw_info_seq_show(struct seq_file *seq, void *v)
drivers/net/wireless/intel/iwlwifi/fw/debugfs.c
372
struct iwl_dbgfs_fw_info_state *state = v;
drivers/net/wireless/intel/iwlwifi/pcie/drv.c
575
#define SUBDEV_MASKED(v, m) .subdevice = (v) + _CHECK_MASK(m), \
drivers/net/wireless/intel/iwlwifi/pcie/gen1_2/trans.c
2759
void *v, loff_t *pos)
drivers/net/wireless/intel/iwlwifi/pcie/gen1_2/trans.c
2762
struct iwl_dbgfs_tx_queue_state *state = v;
drivers/net/wireless/intel/iwlwifi/pcie/gen1_2/trans.c
2772
static void iwl_dbgfs_tx_queue_seq_stop(struct seq_file *seq, void *v)
drivers/net/wireless/intel/iwlwifi/pcie/gen1_2/trans.c
2774
kfree(v);
drivers/net/wireless/intel/iwlwifi/pcie/gen1_2/trans.c
2777
static int iwl_dbgfs_tx_queue_seq_show(struct seq_file *seq, void *v)
drivers/net/wireless/intel/iwlwifi/pcie/gen1_2/trans.c
2780
struct iwl_dbgfs_tx_queue_state *state = v;
drivers/net/wireless/intel/iwlwifi/pcie/utils.h
16
u32 v;
drivers/net/wireless/intel/iwlwifi/pcie/utils.h
22
v = iwl_read32(trans, reg);
drivers/net/wireless/intel/iwlwifi/pcie/utils.h
23
v &= ~mask;
drivers/net/wireless/intel/iwlwifi/pcie/utils.h
24
v |= value;
drivers/net/wireless/intel/iwlwifi/pcie/utils.h
25
iwl_write32(trans, reg, v);
drivers/net/wireless/mediatek/mt76/mt7615/regs.h
227
#define MT_WF_PHY_PD_OFDM(_phy, v) ((v) << ((_phy) ? 16 : 20))
drivers/net/wireless/mediatek/mt76/mt7615/regs.h
240
#define MT_WF_PHY_PD_CCK(_phy, v) ((v) << ((_phy) ? 24 : 1))
drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.c
10
#define HE_PREP(f, m, v) le16_encode_bits(le32_get_bits(v, MT_CRXV_HE_##m),\
drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.c
12
#define EHT_PREP(f, m, v) le32_encode_bits(le32_get_bits(v, MT_CRXV_EHT_##m),\
drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.c
59
#define MU_PREP(f, v) le16_encode_bits(v, IEEE80211_RADIOTAP_HE_MU_##f)
drivers/net/wireless/mediatek/mt76/mt76_connac_mac.c
844
#define MU_PREP(f, v) le16_encode_bits(v, IEEE80211_RADIOTAP_HE_MU_##f)
drivers/net/wireless/mediatek/mt76/mt76_connac_mac.c
9
#define HE_PREP(f, m, v) le16_encode_bits(le32_get_bits(v, MT_CRXV_HE_##m),\
drivers/net/wireless/mediatek/mt7601u/trace.h
131
__field(int, o) __field(u16, v)
drivers/net/wireless/mediatek/mt7601u/trace.h
136
__entry->v = val;
drivers/net/wireless/mediatek/mt7601u/trace.h
138
TP_printk(DEV_PR_FMT "%04x=%04x", DEV_PR_ARG, __entry->o, __entry->v)
drivers/net/wireless/microchip/wilc1000/netdev.h
34
#define wilc_for_each_vif(w, v) \
drivers/net/wireless/microchip/wilc1000/netdev.h
36
list_for_each_entry_srcu(v, &_w->vif_list, list, \
drivers/net/wireless/realtek/rtlwifi/debug.c
115
static int rtl_debug_get_bb_page(struct seq_file *m, void *v)
drivers/net/wireless/realtek/rtlwifi/debug.c
157
static int rtl_debug_get_reg_rf(struct seq_file *m, void *v)
drivers/net/wireless/realtek/rtlwifi/debug.c
190
static int rtl_debug_get_cam_register(struct seq_file *m, void *v)
drivers/net/wireless/realtek/rtlwifi/debug.c
246
static int rtl_debug_get_btcoex(struct seq_file *m, void *v)
drivers/net/wireless/realtek/rtlwifi/debug.c
47
int (*cb_read)(struct seq_file *m, void *v);
drivers/net/wireless/realtek/rtlwifi/debug.c
55
static int rtl_debug_get_common(struct seq_file *m, void *v)
drivers/net/wireless/realtek/rtlwifi/debug.c
59
return debugfs_priv->cb_read(m, v);
drivers/net/wireless/realtek/rtlwifi/debug.c
74
static int rtl_debug_get_mac_page(struct seq_file *m, void *v)
drivers/net/wireless/realtek/rtw88/debug.c
1029
static int rtw_debugfs_get_fw_crash(struct seq_file *m, void *v)
drivers/net/wireless/realtek/rtw88/debug.c
1062
static int rtw_debugfs_get_force_lowest_basic_rate(struct seq_file *m, void *v)
drivers/net/wireless/realtek/rtw88/debug.c
107
static int rtw_debugfs_single_show(struct seq_file *m, void *v)
drivers/net/wireless/realtek/rtw88/debug.c
111
return debugfs_priv->cb_read(m, v);
drivers/net/wireless/realtek/rtw88/debug.c
1131
static int rtw_debugfs_get_dm_cap(struct seq_file *m, void *v)
drivers/net/wireless/realtek/rtw88/debug.c
167
static int rtw_debugfs_get_read_reg(struct seq_file *m, void *v)
drivers/net/wireless/realtek/rtw88/debug.c
192
static int rtw_debugfs_get_rf_read(struct seq_file *m, void *v)
drivers/net/wireless/realtek/rtw88/debug.c
21
int (*cb_read)(struct seq_file *m, void *v);
drivers/net/wireless/realtek/rtw88/debug.c
213
static int rtw_debugfs_get_fix_rate(struct seq_file *m, void *v)
drivers/net/wireless/realtek/rtw88/debug.c
281
static int rtw_debugfs_get_dump_cam(struct seq_file *m, void *v)
drivers/net/wireless/realtek/rtw88/debug.c
307
static int rtw_debugfs_get_rsvd_page(struct seq_file *m, void *v)
drivers/net/wireless/realtek/rtw88/debug.c
545
static int rtw_debug_get_mac_page(struct seq_file *m, void *v)
drivers/net/wireless/realtek/rtw88/debug.c
564
static int rtw_debug_get_bb_page(struct seq_file *m, void *v)
drivers/net/wireless/realtek/rtw88/debug.c
583
static int rtw_debugfs_get_rf_dump(struct seq_file *m, void *v)
drivers/net/wireless/realtek/rtw88/debug.c
691
static int rtw_debugfs_get_tx_pwr_tbl(struct seq_file *m, void *v)
drivers/net/wireless/realtek/rtw88/debug.c
778
static int rtw_debugfs_get_phy_info(struct seq_file *m, void *v)
drivers/net/wireless/realtek/rtw88/debug.c
922
static int rtw_debugfs_get_coex_info(struct seq_file *m, void *v)
drivers/net/wireless/realtek/rtw88/debug.c
956
static int rtw_debugfs_get_coex_enable(struct seq_file *m, void *v)
drivers/net/wireless/realtek/rtw88/debug.c
988
static int rtw_debugfs_get_edcca_enable(struct seq_file *m, void *v)
drivers/net/wireless/realtek/rtw88/reg.h
868
#define BIT_SET_RXPSF_PKTLENTHR(x, v) \
drivers/net/wireless/realtek/rtw88/reg.h
869
(BIT_CLEAR_RXPSF_PKTLENTHR(x) | BIT_RXPSF_PKTLENTHR(v))
drivers/net/wireless/realtek/rtw88/reg.h
890
#define BIT_SET_RXPSF_ERRTHR(x, v) \
drivers/net/wireless/realtek/rtw88/reg.h
891
(BIT_CLEAR_RXPSF_ERRTHR(x) | BIT_RXPSF_ERRTHR(v))
drivers/net/wireless/realtek/rtw88/rtw8822c.c
1402
u32 v, tmp_3f = 0;
drivers/net/wireless/realtek/rtw88/rtw8822c.c
1428
v = txgapk->rf3f_bp[band][gain][path];
drivers/net/wireless/realtek/rtw88/rtw8822c.c
1429
if (_rtw8822c_txgapk_gain_valid(rtwdev, v)) {
drivers/net/wireless/realtek/rtw88/rtw8822c.c
1657
u32 i, j, tmp = 0x20, tmp_3f, v;
drivers/net/wireless/realtek/rtw88/rtw8822c.c
1684
v = txgapk->rf3f_bp[band][j][path];
drivers/net/wireless/realtek/rtw88/rtw8822c.c
1685
if (_rtw8822c_txgapk_gain_valid(rtwdev, v))
drivers/net/wireless/realtek/rtw88/rtw8822c.c
1692
v = txgapk->rf3f_bp[band][i][path];
drivers/net/wireless/realtek/rtw88/rtw8822c.c
1693
if (_rtw8822c_txgapk_gain_valid(rtwdev, v)) {
drivers/net/wireless/realtek/rtw88/rtw8822c.c
1732
u32 rf18, v;
drivers/net/wireless/realtek/rtw88/rtw8822c.c
1764
v = rtw_read_rf(rtwdev, path,
drivers/net/wireless/realtek/rtw88/rtw8822c.c
1766
txgapk->rf3f_bp[band][gain][path] = v & BIT_DATA_L;
drivers/net/wireless/realtek/rtw89/acpi.c
530
static s16 rtw89_acpi_sar_normalize_hp_val(u8 v)
drivers/net/wireless/realtek/rtw89/acpi.c
539
(v << (TXPWR_FACTOR_OF_RTW89_ACPI_SAR - fct));
drivers/net/wireless/realtek/rtw89/acpi.c
544
static s16 rtw89_acpi_sar_normalize_rt_val(u8 v)
drivers/net/wireless/realtek/rtw89/acpi.c
551
res = v << (TXPWR_FACTOR_OF_RTW89_ACPI_SAR - fct);
drivers/net/wireless/realtek/rtw89/acpi.c
571
ent->v[subband][path] =
drivers/net/wireless/realtek/rtw89/acpi.c
572
rec->normalize(ptr->v[antidx][subband]);
drivers/net/wireless/realtek/rtw89/acpi.c
574
ent->v[subband][path] = MAX_VAL_OF_RTW89_ACPI_SAR;
drivers/net/wireless/realtek/rtw89/acpi.c
595
ent->v[subband][path] = rec->normalize(ptr->v[antidx][subband]);
drivers/net/wireless/realtek/rtw89/acpi.c
615
ent->v[subband][path] =
drivers/net/wireless/realtek/rtw89/acpi.c
616
rec->normalize(ptr->v[antidx][subband]);
drivers/net/wireless/realtek/rtw89/acpi.c
618
ent->v[subband][path] = MAX_VAL_OF_RTW89_ACPI_SAR;
drivers/net/wireless/realtek/rtw89/acpi.c
639
ent->v[subband][path] = rec->normalize(ptr->v[antidx][subband]);
drivers/net/wireless/realtek/rtw89/acpi.c
760
&ent->v[subband][path]);
drivers/net/wireless/realtek/rtw89/acpi.c
803
&ent->v[subband][path]);
drivers/net/wireless/realtek/rtw89/acpi.c
844
&ent->v[subband][path]);
drivers/net/wireless/realtek/rtw89/acpi.c
887
&ent->v[subband][path]);
drivers/net/wireless/realtek/rtw89/acpi.h
142
u8 v[RTW89_ACPI_SAR_ANT_NR_STD][RTW89_ACPI_SAR_SUBBAND_NR_LEGACY];
drivers/net/wireless/realtek/rtw89/acpi.h
146
u8 v[RTW89_ACPI_SAR_ANT_NR_STD][RTW89_ACPI_SAR_SUBBAND_NR_HAS_6GHZ];
drivers/net/wireless/realtek/rtw89/acpi.h
150
u8 v[RTW89_ACPI_SAR_ANT_NR_SML][RTW89_ACPI_SAR_SUBBAND_NR_LEGACY];
drivers/net/wireless/realtek/rtw89/acpi.h
154
u8 v[RTW89_ACPI_SAR_ANT_NR_SML][RTW89_ACPI_SAR_SUBBAND_NR_HAS_6GHZ];
drivers/net/wireless/realtek/rtw89/acpi.h
188
s16 (*normalize)(u8 v);
drivers/net/wireless/realtek/rtw89/coex.c
2226
struct rtw89_btc_fbtc_tdma *v;
drivers/net/wireless/realtek/rtw89/coex.c
2241
v = (struct rtw89_btc_fbtc_tdma *)&tlv->val[0];
drivers/net/wireless/realtek/rtw89/coex.c
2242
tlv->len = sizeof(*v);
drivers/net/wireless/realtek/rtw89/coex.c
2243
*v = dm->tdma;
drivers/net/wireless/realtek/rtw89/coex.c
2244
btc->policy_len += BTC_TLV_HDR_LEN + sizeof(*v);
drivers/net/wireless/realtek/rtw89/coex.c
2272
struct btc_fbtc_1slot *v = NULL;
drivers/net/wireless/realtek/rtw89/coex.c
2289
v = (struct btc_fbtc_1slot *)&tlv->val[0];
drivers/net/wireless/realtek/rtw89/coex.c
2291
tlv->len = sizeof(*v);
drivers/net/wireless/realtek/rtw89/coex.c
2293
v->fver = btc->ver->fcxslots;
drivers/net/wireless/realtek/rtw89/coex.c
2294
v->sid = i;
drivers/net/wireless/realtek/rtw89/coex.c
2295
v->slot = dm->slot.v1[i];
drivers/net/wireless/realtek/rtw89/coex.c
2303
btc->policy_len += BTC_TLV_HDR_LEN + sizeof(*v);
drivers/net/wireless/realtek/rtw89/core.h
4251
s8 v[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
drivers/net/wireless/realtek/rtw89/core.h
4258
s8 v[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
drivers/net/wireless/realtek/rtw89/core.h
4265
s8 v[RTW89_6G_BW_NUM][RTW89_NTX_NUM]
drivers/net/wireless/realtek/rtw89/core.h
4273
s8 v[RTW89_RU_NUM][RTW89_NTX_NUM]
drivers/net/wireless/realtek/rtw89/core.h
4279
s8 v[RTW89_RU_NUM][RTW89_NTX_NUM]
drivers/net/wireless/realtek/rtw89/core.h
4285
s8 v[RTW89_RU_NUM][RTW89_NTX_NUM]
drivers/net/wireless/realtek/rtw89/core.h
4292
u8 v[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM][RTW89_REGD_NUM];
drivers/net/wireless/realtek/rtw89/core.h
4297
u8 v[RTW89_BAND_NUM][RTW89_REGD_NUM];
drivers/net/wireless/realtek/rtw89/core.h
4961
s16 v[NUM_OF_RTW89_ACPI_SAR_SUBBAND][NUM_OF_RTW89_ACPI_SAR_RF_PATH];
drivers/net/wireless/realtek/rtw89/fw.c
10846
data->v[entry.bw][entry.nt][entry.rs][entry.bf][entry.regd]
drivers/net/wireless/realtek/rtw89/fw.c
10847
[entry.ch_idx] = entry.v;
drivers/net/wireless/realtek/rtw89/fw.c
10886
data->v[entry.bw][entry.nt][entry.rs][entry.bf][entry.regd]
drivers/net/wireless/realtek/rtw89/fw.c
10887
[entry.ch_idx] = entry.v;
drivers/net/wireless/realtek/rtw89/fw.c
10928
data->v[entry.bw][entry.nt][entry.rs][entry.bf][entry.regd]
drivers/net/wireless/realtek/rtw89/fw.c
10929
[entry.reg_6ghz_power][entry.ch_idx] = entry.v;
drivers/net/wireless/realtek/rtw89/fw.c
10964
data->v[entry.ru][entry.nt][entry.regd][entry.ch_idx] = entry.v;
drivers/net/wireless/realtek/rtw89/fw.c
10999
data->v[entry.ru][entry.nt][entry.regd][entry.ch_idx] = entry.v;
drivers/net/wireless/realtek/rtw89/fw.c
11036
data->v[entry.ru][entry.nt][entry.regd][entry.reg_6ghz_power]
drivers/net/wireless/realtek/rtw89/fw.c
11037
[entry.ch_idx] = entry.v;
drivers/net/wireless/realtek/rtw89/fw.c
11070
data->v[entry.band][entry.tx_shape_rs][entry.regd] = entry.v;
drivers/net/wireless/realtek/rtw89/fw.c
11101
data->v[entry.band][entry.regd] = entry.v;
drivers/net/wireless/realtek/rtw89/fw.c
11148
parms->rule_2ghz.lmt = &rfe_data->lmt_2ghz.v;
drivers/net/wireless/realtek/rtw89/fw.c
11153
parms->rule_5ghz.lmt = &rfe_data->lmt_5ghz.v;
drivers/net/wireless/realtek/rtw89/fw.c
11158
parms->rule_6ghz.lmt = &rfe_data->lmt_6ghz.v;
drivers/net/wireless/realtek/rtw89/fw.c
11163
parms->rule_da_2ghz.lmt = &rfe_data->da_lmt_2ghz.v;
drivers/net/wireless/realtek/rtw89/fw.c
11168
parms->rule_da_5ghz.lmt = &rfe_data->da_lmt_5ghz.v;
drivers/net/wireless/realtek/rtw89/fw.c
11173
parms->rule_da_6ghz.lmt = &rfe_data->da_lmt_6ghz.v;
drivers/net/wireless/realtek/rtw89/fw.c
11178
parms->rule_2ghz.lmt_ru = &rfe_data->lmt_ru_2ghz.v;
drivers/net/wireless/realtek/rtw89/fw.c
11183
parms->rule_5ghz.lmt_ru = &rfe_data->lmt_ru_5ghz.v;
drivers/net/wireless/realtek/rtw89/fw.c
11188
parms->rule_6ghz.lmt_ru = &rfe_data->lmt_ru_6ghz.v;
drivers/net/wireless/realtek/rtw89/fw.c
11193
parms->rule_da_2ghz.lmt_ru = &rfe_data->da_lmt_ru_2ghz.v;
drivers/net/wireless/realtek/rtw89/fw.c
11198
parms->rule_da_5ghz.lmt_ru = &rfe_data->da_lmt_ru_5ghz.v;
drivers/net/wireless/realtek/rtw89/fw.c
11203
parms->rule_da_6ghz.lmt_ru = &rfe_data->da_lmt_ru_6ghz.v;
drivers/net/wireless/realtek/rtw89/fw.c
11208
parms->tx_shape.lmt = &rfe_data->tx_shape_lmt.v;
drivers/net/wireless/realtek/rtw89/fw.c
11213
parms->tx_shape.lmt_ru = &rfe_data->tx_shape_lmt_ru.v;
drivers/net/wireless/realtek/rtw89/fw.c
321
key_sign_len = le16_to_cpu(section_content->key_sign_len.v) >> 2;
drivers/net/wireless/realtek/rtw89/fw.c
334
sb_sel_ver = get_unaligned_le32(§ion_content->sb_sel_ver.v);
drivers/net/wireless/realtek/rtw89/fw.h
5627
s8 v;
drivers/net/wireless/realtek/rtw89/fw.h
5638
s8 v;
drivers/net/wireless/realtek/rtw89/fw.h
5650
s8 v;
drivers/net/wireless/realtek/rtw89/fw.h
5659
s8 v;
drivers/net/wireless/realtek/rtw89/fw.h
5668
s8 v;
drivers/net/wireless/realtek/rtw89/fw.h
5678
s8 v;
drivers/net/wireless/realtek/rtw89/fw.h
5686
u8 v;
drivers/net/wireless/realtek/rtw89/fw.h
5693
u8 v;
drivers/net/wireless/realtek/rtw89/fw.h
697
__le32 v;
drivers/net/wireless/realtek/rtw89/fw.h
701
__le16 v;
drivers/net/wireless/realtek/rtw89/pci.c
1024
#define DEF_TXCHADDRS_TYPE3(gen, ch_idx, txch, v...) \
drivers/net/wireless/realtek/rtw89/pci.c
1027
.idx = R_##gen##_##txch##_TXBD_IDX ##v, \
drivers/net/wireless/realtek/rtw89/pci.c
1033
#define DEF_TXCHADDRS_TYPE3_GRP_BASE(gen, ch_idx, txch, grp, v...) \
drivers/net/wireless/realtek/rtw89/pci.c
1036
.idx = R_##gen##_##txch##_TXBD_IDX ##v, \
drivers/net/wireless/realtek/rtw89/pci.c
1042
#define DEF_TXCHADDRS_TYPE2(gen, ch_idx, txch, v...) \
drivers/net/wireless/realtek/rtw89/pci.c
1044
.num = R_##gen##_##txch##_TXBD_NUM ##v, \
drivers/net/wireless/realtek/rtw89/pci.c
1045
.idx = R_##gen##_##txch##_TXBD_IDX ##v, \
drivers/net/wireless/realtek/rtw89/pci.c
1047
.desa_l = R_##gen##_##txch##_TXBD_DESA_L ##v, \
drivers/net/wireless/realtek/rtw89/pci.c
1048
.desa_h = R_##gen##_##txch##_TXBD_DESA_H ##v, \
drivers/net/wireless/realtek/rtw89/pci.c
1051
#define DEF_TXCHADDRS_TYPE1(info, txch, v...) \
drivers/net/wireless/realtek/rtw89/pci.c
1053
.num = R_AX_##txch##_TXBD_NUM ##v, \
drivers/net/wireless/realtek/rtw89/pci.c
1054
.idx = R_AX_##txch##_TXBD_IDX ##v, \
drivers/net/wireless/realtek/rtw89/pci.c
1055
.bdram = R_AX_##txch##_BDRAM_CTRL ##v, \
drivers/net/wireless/realtek/rtw89/pci.c
1056
.desa_l = R_AX_##txch##_TXBD_DESA_L ##v, \
drivers/net/wireless/realtek/rtw89/pci.c
1057
.desa_h = R_AX_##txch##_TXBD_DESA_H ##v, \
drivers/net/wireless/realtek/rtw89/pci.c
1060
#define DEF_TXCHADDRS(info, txch, v...) \
drivers/net/wireless/realtek/rtw89/pci.c
1064
.bdram = R_AX_##txch##_BDRAM_CTRL ##v, \
drivers/net/wireless/realtek/rtw89/pci.c
1065
.desa_l = R_AX_##txch##_TXBD_DESA_L ##v, \
drivers/net/wireless/realtek/rtw89/pci.c
1066
.desa_h = R_AX_##txch##_TXBD_DESA_H ##v, \
drivers/net/wireless/realtek/rtw89/pci.c
1069
#define DEF_RXCHADDRS_TYPE3(gen, ch_idx, rxch, v...) \
drivers/net/wireless/realtek/rtw89/pci.c
1072
.idx = R_##gen##_##ch_idx##0_RXBD_IDX ##v, \
drivers/net/wireless/realtek/rtw89/pci.c
1077
#define DEF_RXCHADDRS_TYPE3_GRP_BASE(gen, ch_idx, rxch, grp, v...) \
drivers/net/wireless/realtek/rtw89/pci.c
1080
.idx = R_##gen##_##ch_idx##0_RXBD_IDX ##v, \
drivers/net/wireless/realtek/rtw89/pci.c
1085
#define DEF_RXCHADDRS(gen, ch_idx, rxch, v...) \
drivers/net/wireless/realtek/rtw89/pci.c
1087
.num = R_##gen##_##rxch##_RXBD_NUM ##v, \
drivers/net/wireless/realtek/rtw89/pci.c
1088
.idx = R_##gen##_##rxch##_RXBD_IDX ##v, \
drivers/net/wireless/realtek/rtw89/pci.c
1089
.desa_l = R_##gen##_##rxch##_RXBD_DESA_L ##v, \
drivers/net/wireless/realtek/rtw89/pci.c
1090
.desa_h = R_##gen##_##rxch##_RXBD_DESA_H ##v, \
drivers/net/wireless/realtek/rtw89/pci.h
1362
#define RTW89_PCI_SSID(v, d, ssv, ssd, cust) \
drivers/net/wireless/realtek/rtw89/pci.h
1363
.vendor = v, .device = d, .subsystem_vendor = ssv, .subsystem_device = ssd, \
drivers/net/wireless/realtek/rtw89/phy.c
3042
s8 v[4] = {};
drivers/net/wireless/realtek/rtw89/phy.c
3062
v[cur.idx % 4] =
drivers/net/wireless/realtek/rtw89/phy.c
3070
val = FIELD_PREP(GENMASK(7, 0), v[0]) |
drivers/net/wireless/realtek/rtw89/phy.c
3071
FIELD_PREP(GENMASK(15, 8), v[1]) |
drivers/net/wireless/realtek/rtw89/phy.c
3072
FIELD_PREP(GENMASK(23, 16), v[2]) |
drivers/net/wireless/realtek/rtw89/phy.c
3073
FIELD_PREP(GENMASK(31, 24), v[3]);
drivers/net/wireless/realtek/rtw89/phy.c
3093
s8 v[RTW89_RATE_OFFSET_NUM_AX] = {};
drivers/net/wireless/realtek/rtw89/phy.c
3099
v[desc.idx] = rtw89_phy_read_txpwr_byrate(rtwdev, band, 0, &desc);
drivers/net/wireless/realtek/rtw89/phy.c
3102
val = FIELD_PREP(GENMASK(3, 0), v[0]) |
drivers/net/wireless/realtek/rtw89/phy.c
3103
FIELD_PREP(GENMASK(7, 4), v[1]) |
drivers/net/wireless/realtek/rtw89/phy.c
3104
FIELD_PREP(GENMASK(11, 8), v[2]) |
drivers/net/wireless/realtek/rtw89/phy.c
3105
FIELD_PREP(GENMASK(15, 12), v[3]) |
drivers/net/wireless/realtek/rtw89/phy.c
3106
FIELD_PREP(GENMASK(19, 16), v[4]);
drivers/net/wireless/realtek/rtw89/phy_be.c
1012
v[pos] = rtw89_phy_read_txpwr_byrate(rtwdev, band, bw,
drivers/net/wireless/realtek/rtw89/phy_be.c
1018
val = u32_encode_bits(v[0], GENMASK(7, 0)) |
drivers/net/wireless/realtek/rtw89/phy_be.c
1019
u32_encode_bits(v[1], GENMASK(15, 8)) |
drivers/net/wireless/realtek/rtw89/phy_be.c
1020
u32_encode_bits(v[2], GENMASK(23, 16)) |
drivers/net/wireless/realtek/rtw89/phy_be.c
1021
u32_encode_bits(v[3], GENMASK(31, 24));
drivers/net/wireless/realtek/rtw89/phy_be.c
1055
s8 v[RTW89_RATE_OFFSET_NUM_BE] = {};
drivers/net/wireless/realtek/rtw89/phy_be.c
1062
v[desc.idx] = rtw89_phy_read_txpwr_byrate(rtwdev, band, 0, &desc);
drivers/net/wireless/realtek/rtw89/phy_be.c
1064
val = u32_encode_bits(v[RTW89_RATE_OFFSET_CCK], GENMASK(3, 0)) |
drivers/net/wireless/realtek/rtw89/phy_be.c
1065
u32_encode_bits(v[RTW89_RATE_OFFSET_OFDM], GENMASK(7, 4)) |
drivers/net/wireless/realtek/rtw89/phy_be.c
1066
u32_encode_bits(v[RTW89_RATE_OFFSET_HT], GENMASK(11, 8)) |
drivers/net/wireless/realtek/rtw89/phy_be.c
1067
u32_encode_bits(v[RTW89_RATE_OFFSET_VHT], GENMASK(15, 12)) |
drivers/net/wireless/realtek/rtw89/phy_be.c
1068
u32_encode_bits(v[RTW89_RATE_OFFSET_HE], GENMASK(19, 16)) |
drivers/net/wireless/realtek/rtw89/phy_be.c
1069
u32_encode_bits(v[RTW89_RATE_OFFSET_EHT], GENMASK(23, 20)) |
drivers/net/wireless/realtek/rtw89/phy_be.c
1070
u32_encode_bits(v[RTW89_RATE_OFFSET_DLRU_HE], GENMASK(27, 24)) |
drivers/net/wireless/realtek/rtw89/phy_be.c
1071
u32_encode_bits(v[RTW89_RATE_OFFSET_DLRU_EHT], GENMASK(31, 28));
drivers/net/wireless/realtek/rtw89/phy_be.c
999
s8 v[4];
drivers/net/wireless/realtek/rtw89/sar.c
117
return min(ent->v[subband_low][path], ent->v[subband_high][path]);
drivers/net/wireless/realtek/rtw89/sar.c
488
ent->v[k][RF_PATH_A], ent->v[k][RF_PATH_B]);
drivers/net/wireless/silabs/wfx/debug.c
151
static int wfx_rx_stats_show(struct seq_file *seq, void *v)
drivers/net/wireless/silabs/wfx/debug.c
181
static int wfx_tx_power_loop_show(struct seq_file *seq, void *v)
drivers/net/wireless/silabs/wfx/debug.c
61
static int wfx_counters_show(struct seq_file *seq, void *v)
drivers/net/wireless/st/cw1200/debug.c
291
static int cw1200_counters_show(struct seq_file *seq, void *v)
drivers/net/wireless/st/cw1200/debug.c
98
static int cw1200_status_show(struct seq_file *seq, void *v)
drivers/net/wireless/st/cw1200/sta.c
1079
u16 v;
drivers/net/wireless/st/cw1200/sta.c
1085
v = le16_to_cpu(*((__le16 *)(p + 2)));
drivers/net/wireless/st/cw1200/sta.c
1086
if (!v) /* non-zero means this is enabled */
drivers/net/wireless/st/cw1200/sta.c
1089
v = le16_to_cpu(*((__le16 *)(p + 4)));
drivers/net/wireless/st/cw1200/sta.c
1090
priv->conf_listen_interval = (v >> 7) & 0x1F;
drivers/net/wireless/zydas/zd1211rw/zd_chip.c
1309
u16 v[ARRAY_SIZE(a)];
drivers/net/wireless/zydas/zd1211rw/zd_chip.c
1317
r = zd_ioread16v_locked(chip, v, (const zd_addr_t *)a, ARRAY_SIZE(a));
drivers/net/wireless/zydas/zd1211rw/zd_chip.c
1326
ioreqs[1].value = v[1] & ~(LED1|LED2);
drivers/net/wireless/zydas/zd1211rw/zd_chip.c
1330
ioreqs[1].value = v[1] & ~other_led;
drivers/net/wireless/zydas/zd1211rw/zd_chip.c
1339
ioreqs[1].value = v[1] & ~other_led;
drivers/net/wireless/zydas/zd1211rw/zd_chip.c
1347
if (v[0] != ioreqs[0].value || v[1] != ioreqs[1].value) {
drivers/net/wireless/zydas/zd1211rw/zd_chip.c
433
u32 v;
drivers/net/wireless/zydas/zd1211rw/zd_chip.c
437
r = zd_ioread32_locked(chip, &v,
drivers/net/wireless/zydas/zd1211rw/zd_chip.c
441
v -= guard;
drivers/net/wireless/zydas/zd1211rw/zd_chip.c
443
values[i++] = v;
drivers/net/wireless/zydas/zd1211rw/zd_chip.c
444
values[i++] = v >> 8;
drivers/net/wireless/zydas/zd1211rw/zd_chip.c
445
values[i++] = v >> 16;
drivers/net/wireless/zydas/zd1211rw/zd_chip.c
446
values[i++] = v >> 24;
drivers/net/wireless/zydas/zd1211rw/zd_chip.c
450
values[i] = v >> (8*(i%3));
drivers/net/xen-netback/xenbus.c
161
static int xenvif_ctrl_show(struct seq_file *m, void *v)
drivers/net/xen-netback/xenbus.c
26
static int xenvif_read_io_ring(struct seq_file *m, void *v)
drivers/nfc/trf7970a.c
292
#define TRF7970A_REG_IO_CTRL_VRS(v) ((v) & 0x07)
drivers/nfc/trf7970a.c
337
#define TRF7970A_NFC_LOW_FIELD_LEVEL_RFDET(v) ((v) & 0x07)
drivers/nfc/trf7970a.c
340
#define TRF7970A_NFC_TARGET_LEVEL_RFDET(v) ((v) & 0x07)
drivers/ntb/ntb_transport.c
486
static int ntb_qp_debugfs_stats_show(struct seq_file *s, void *v)
drivers/nubus/nubus.c
84
unsigned long v = 0;
drivers/nubus/nubus.c
88
v <<= 8;
drivers/nubus/nubus.c
91
v |= *p++;
drivers/nubus/nubus.c
95
return v;
drivers/nubus/proc.c
108
static int nubus_proc_rsrc_show(struct seq_file *m, void *v)
drivers/nubus/proc.c
37
nubus_devices_proc_show(struct seq_file *m, void *v)
drivers/nvme/host/sysfs.c
527
unsigned int v;
drivers/nvme/host/sysfs.c
530
err = kstrtou32(buf, 10, &v);
drivers/nvme/host/sysfs.c
534
ctrl->opts->reconnect_delay = v;
drivers/nvmem/core.c
1709
u8 v, *p, *buf, *b, pbyte, pbits;
drivers/nvmem/core.c
1724
rc = nvmem_reg_read(nvmem, cell->offset, &v, 1);
drivers/nvmem/core.c
1727
*b++ |= GENMASK(bit_offset - 1, 0) & v;
drivers/nvmem/core.c
1744
cell->offset + cell->bytes - 1, &v, 1);
drivers/nvmem/core.c
1747
*p |= GENMASK(7, (nbits + bit_offset) % BITS_PER_BYTE) & v;
drivers/parisc/dino.c
176
u32 v = DINO_CFG_TOK(local_bus, devfn, where & ~3);
drivers/parisc/dino.c
185
__raw_writel(v, base_addr + DINO_PCI_ADDR);
drivers/parisc/dino.c
211
u32 v = DINO_CFG_TOK(local_bus, devfn, where & ~3);
drivers/parisc/dino.c
220
__raw_writel(v & 0xffffff00, base_addr + DINO_PCI_ADDR);
drivers/parisc/dino.c
224
__raw_writel(v, base_addr + DINO_PCI_ADDR);
drivers/parisc/dino.c
256
u##size v; \
drivers/parisc/dino.c
262
v = read##type(d->base_addr+DINO_IO_DATA+(addr&mask)); \
drivers/parisc/dino.c
264
return v; \
drivers/parport/parport_cs.c
64
#define INT_MODULE_PARM(n, v) static int n = v; module_param(n, int, 0)
drivers/parport/parport_pc.c
107
unsigned char v)
drivers/parport/parport_pc.c
117
new = (ectr & ~m) ^ v;
drivers/parport/parport_pc.c
122
pr_debug("frob_econtrol(%02x,%02x): %02x -> %02x\n", m, v, ectr, new);
drivers/parport/parport_pc.c
86
#define ECR_WRITE(p, v) frob_econtrol((p), 0xff, (v))
drivers/pci/controller/dwc/pcie-designware-debugfs.c
446
static int ltssm_status_show(struct seq_file *s, void *v)
drivers/pci/controller/pci-tegra.c
2494
static void *tegra_pcie_ports_seq_next(struct seq_file *s, void *v, loff_t *pos)
drivers/pci/controller/pci-tegra.c
2498
return seq_list_next(v, &pcie->ports, pos);
drivers/pci/controller/pci-tegra.c
2501
static void tegra_pcie_ports_seq_stop(struct seq_file *s, void *v)
drivers/pci/controller/pci-tegra.c
2505
static int tegra_pcie_ports_seq_show(struct seq_file *s, void *v)
drivers/pci/controller/pci-tegra.c
2511
port = list_entry(v, struct tegra_pcie_port, list);
drivers/pci/controller/pci-thunder-ecam.c
109
v = readl(addr);
drivers/pci/controller/pci-thunder-ecam.c
118
v |= node_bits;
drivers/pci/controller/pci-thunder-ecam.c
119
set_val(v, where, size, val);
drivers/pci/controller/pci-thunder-ecam.c
127
u32 v;
drivers/pci/controller/pci-thunder-ecam.c
138
v = readl(addr);
drivers/pci/controller/pci-thunder-ecam.c
141
cfg_type = (v >> 16) & 0x7f;
drivers/pci/controller/pci-thunder-ecam.c
18
static void set_val(u32 v, int where, int size, u32 *val)
drivers/pci/controller/pci-thunder-ecam.c
194
v = readl(addr);
drivers/pci/controller/pci-thunder-ecam.c
195
has_msix = (v & 0xff00) != 0;
drivers/pci/controller/pci-thunder-ecam.c
198
v |= 0xbc00; /* next capability is EA at 0xbc */
drivers/pci/controller/pci-thunder-ecam.c
199
set_val(v, where, size, val);
drivers/pci/controller/pci-thunder-ecam.c
207
v = readl(addr);
drivers/pci/controller/pci-thunder-ecam.c
208
if (v & 0xff00)
drivers/pci/controller/pci-thunder-ecam.c
209
pr_err("Bad MSI-X cap header: %08x\n", v);
drivers/pci/controller/pci-thunder-ecam.c
210
v |= 0xbc00; /* next capability is EA at 0xbc */
drivers/pci/controller/pci-thunder-ecam.c
211
set_val(v, where, size, val);
drivers/pci/controller/pci-thunder-ecam.c
216
v = 0x40014; /* EA last in chain, 4 entries */
drivers/pci/controller/pci-thunder-ecam.c
218
v = 0x30014; /* EA last in chain, 3 entries */
drivers/pci/controller/pci-thunder-ecam.c
22
pr_debug("set_val %04x: %08x\n", (unsigned int)(where & ~3), v);
drivers/pci/controller/pci-thunder-ecam.c
220
v = 0x20014; /* EA last in chain, 2 entries */
drivers/pci/controller/pci-thunder-ecam.c
222
v = 0x10014; /* EA last in chain, 1 entry */
drivers/pci/controller/pci-thunder-ecam.c
223
set_val(v, where, size, val);
drivers/pci/controller/pci-thunder-ecam.c
23
v >>= shift;
drivers/pci/controller/pci-thunder-ecam.c
25
v &= 0xff;
drivers/pci/controller/pci-thunder-ecam.c
263
v = readl(addr);
drivers/pci/controller/pci-thunder-ecam.c
264
if (v & 0xff00)
drivers/pci/controller/pci-thunder-ecam.c
265
pr_err("Bad PCIe cap header: %08x\n", v);
drivers/pci/controller/pci-thunder-ecam.c
266
v |= 0xbc00; /* next capability is EA at 0xbc */
drivers/pci/controller/pci-thunder-ecam.c
267
set_val(v, where, size, val);
drivers/pci/controller/pci-thunder-ecam.c
27
v &= 0xffff;
drivers/pci/controller/pci-thunder-ecam.c
272
v = 0x10014; /* EA last in chain, 1 entry */
drivers/pci/controller/pci-thunder-ecam.c
274
v = 0x00014; /* EA last in chain, no entries */
drivers/pci/controller/pci-thunder-ecam.c
275
set_val(v, where, size, val);
drivers/pci/controller/pci-thunder-ecam.c
28
*val = v;
drivers/pci/controller/pci-thunder-ecam.c
280
v = 0x0101; /* subordinate:secondary = 1:1 */
drivers/pci/controller/pci-thunder-ecam.c
282
v = 0x0202; /* subordinate:secondary = 2:2 */
drivers/pci/controller/pci-thunder-ecam.c
284
v = 0x0303; /* subordinate:secondary = 3:3 */
drivers/pci/controller/pci-thunder-ecam.c
286
v = 0x0404; /* subordinate:secondary = 4:4 */
drivers/pci/controller/pci-thunder-ecam.c
287
set_val(v, where, size, val);
drivers/pci/controller/pci-thunder-ecam.c
292
v = 0x80ff0564;
drivers/pci/controller/pci-thunder-ecam.c
293
set_val(v, where, size, val);
drivers/pci/controller/pci-thunder-ecam.c
297
v = 0x00000002; /* Base-L 64-bit */
drivers/pci/controller/pci-thunder-ecam.c
298
set_val(v, where, size, val);
drivers/pci/controller/pci-thunder-ecam.c
302
v = 0xfffffffe; /* MaxOffset-L 64-bit */
drivers/pci/controller/pci-thunder-ecam.c
303
set_val(v, where, size, val);
drivers/pci/controller/pci-thunder-ecam.c
307
v = 0x00008430; /* NIC Base-H */
drivers/pci/controller/pci-thunder-ecam.c
308
set_val(v, where, size, val);
drivers/pci/controller/pci-thunder-ecam.c
312
v = 0x0000000f; /* MaxOffset-H */
drivers/pci/controller/pci-thunder-ecam.c
313
set_val(v, where, size, val);
drivers/pci/controller/pci-thunder-ecam.c
35
u32 v;
drivers/pci/controller/pci-thunder-ecam.c
49
v = readl(addr);
drivers/pci/controller/pci-thunder-ecam.c
50
v &= ~0xf;
drivers/pci/controller/pci-thunder-ecam.c
51
v |= 2; /* EA entry-1. Base-L */
drivers/pci/controller/pci-thunder-ecam.c
52
set_val(v, where, size, val);
drivers/pci/controller/pci-thunder-ecam.c
68
v = ~barl_rb & ~3;
drivers/pci/controller/pci-thunder-ecam.c
69
v |= 0xc; /* EA entry-2. Offset-L */
drivers/pci/controller/pci-thunder-ecam.c
70
set_val(v, where, size, val);
drivers/pci/controller/pci-thunder-ecam.c
78
v = readl(addr); /* EA entry-3. Base-H */
drivers/pci/controller/pci-thunder-ecam.c
79
set_val(v, where, size, val);
drivers/pci/controller/pci-thunder-ecam.c
92
u32 v;
drivers/pci/controller/pcie-brcmstb.c
1847
unsigned long v, void *p)
drivers/pci/controller/pcie-brcmstb.c
1856
unsigned long v, void *p)
drivers/pci/controller/pcie-hisi-error.c
41
#define HISI_PCIE_PORT_ID(core, v) (((v) >> 1) + ((core) << 3))
drivers/pci/controller/pcie-hisi-error.c
42
#define HISI_PCIE_CORE_ID(v) ((v) >> 3)
drivers/pci/controller/pcie-hisi-error.c
43
#define HISI_PCIE_CORE_PORT_ID(v) (((v) & 7) << 1)
drivers/pci/pci.c
5743
u32 stat, v, o;
drivers/pci/pci.c
5749
v = ffs(mmrbc) - 10;
drivers/pci/pci.c
5758
if (v > FIELD_GET(PCI_X_STATUS_MAX_READ, stat))
drivers/pci/pci.c
5765
if (o != v) {
drivers/pci/pci.c
5766
if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
drivers/pci/pci.c
5770
cmd |= FIELD_PREP(PCI_X_CMD_MAX_READ, v);
drivers/pci/pci.c
5804
u16 v;
drivers/pci/pci.c
5827
v = FIELD_PREP(PCI_EXP_DEVCTL_READRQ, firstbit - 8);
drivers/pci/pci.c
5839
PCI_EXP_DEVCTL_READRQ, v);
drivers/pci/pci.c
5871
u16 v;
drivers/pci/pci.c
5877
v = ffs(mps) - 8;
drivers/pci/pci.c
5878
if (v > dev->pcie_mpss)
drivers/pci/pci.c
5880
v = FIELD_PREP(PCI_EXP_DEVCTL_PAYLOAD, v);
drivers/pci/pci.c
5883
PCI_EXP_DEVCTL_PAYLOAD, v);
drivers/pci/pci.c
6282
u32 v;
drivers/pci/pci.c
6288
return pci_bus_read_dev_vendor_id(pdev->bus, pdev->devfn, &v, 0);
drivers/pci/pci.c
711
u16 v, id;
drivers/pci/pci.c
713
pci_read_config_word(dev, pos + PCI_DVSEC_HEADER1, &v);
drivers/pci/pci.c
715
if (vendor == v && dvsec == id)
drivers/pci/probe.c
2339
u16 v;
drivers/pci/probe.c
2341
pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &v);
drivers/pci/probe.c
2343
return !!(v & PCI_EXP_DEVCTL_RELAX_EN);
drivers/pci/proc.c
354
static void *pci_seq_next(struct seq_file *m, void *v, loff_t *pos)
drivers/pci/proc.c
356
struct pci_dev *dev = v;
drivers/pci/proc.c
363
static void pci_seq_stop(struct seq_file *m, void *v)
drivers/pci/proc.c
365
if (v) {
drivers/pci/proc.c
366
struct pci_dev *dev = v;
drivers/pci/proc.c
371
static int show_device(struct seq_file *m, void *v)
drivers/pci/proc.c
373
const struct pci_dev *dev = v;
drivers/pcmcia/cistpl.c
44
#define SPEED_CVT(v) \
drivers/pcmcia/cistpl.c
45
(mantissa[(((v)>>3)&15)-1] * exponent[(v)&7] / 10)
drivers/pcmcia/cistpl.c
47
#define POWER_CVT(v) \
drivers/pcmcia/cistpl.c
48
(mantissa[((v)>>3)&15] * exponent[(v)&7] / 10)
drivers/pcmcia/cistpl.c
49
#define POWER_SCALE(v) (exponent[(v)&7])
drivers/pcmcia/cs.c
44
#define INT_MODULE_PARM(n, v) static int n = v; module_param(n, int, 0444)
drivers/pcmcia/db1xxx_ss.c
248
int v, p, ret;
drivers/pcmcia/db1xxx_ss.c
253
v = p = ret = 0;
drivers/pcmcia/db1xxx_ss.c
257
++v;
drivers/pcmcia/db1xxx_ss.c
260
++v;
drivers/pcmcia/db1xxx_ss.c
289
v = p = 0;
drivers/pcmcia/db1xxx_ss.c
295
cr_set |= ((v << 2) | p) << (sock->nr * 8);
drivers/pcmcia/i82365.c
292
#define flip(v,b,f) (v = ((f)<0) ? v : ((f) ? ((v)|(b)) : ((v)&(~b))))
drivers/pcmcia/rsrc_nonstatic.c
39
#define INT_MODULE_PARM(n, v) static int n = v; module_param(n, int, 0444)
drivers/pcmcia/soc_common.c
104
v / 10, v % 10, vout / 10, vout % 10);
drivers/pcmcia/soc_common.c
84
struct soc_pcmcia_regulator *r, int v)
drivers/pcmcia/soc_common.c
92
on = v != 0;
drivers/pcmcia/soc_common.c
97
ret = regulator_set_voltage(r->reg, v * 100000, v * 100000);
drivers/pcmcia/soc_common.h
47
struct soc_pcmcia_regulator *r, int v);
drivers/perf/arm-ni.c
712
for (int v = 0; v < cfg.num_components; v++) {
drivers/perf/arm-ni.c
713
reg = readl_relaxed(cfg.base + NI_CHILD_PTR(v));
drivers/perf/arm-ni.c
738
for (int v = 0; v < cfg.num_components; v++) {
drivers/perf/arm-ni.c
739
reg = readl_relaxed(cfg.base + NI_CHILD_PTR(v));
drivers/perf/arm_pmu.c
782
void *v)
drivers/perf/riscv_pmu_sbi.c
1243
void *v)
drivers/perf/starfive_starlink_pmu.c
447
unsigned long cmd, void *v)
drivers/phy/allwinner/phy-sun4i-usb.c
671
unsigned long val, void *v)
drivers/phy/allwinner/phy-sun4i-usb.c
675
struct power_supply *psy = v;
drivers/phy/microchip/lan966x_serdes.c
52
u32 v;
drivers/phy/microchip/lan966x_serdes.c
54
v = readl(mem + offset);
drivers/phy/microchip/lan966x_serdes.c
55
v = (v & ~mask) | (val & mask);
drivers/phy/microchip/lan966x_serdes.c
56
writel(v, mem + offset);
drivers/phy/qualcomm/phy-qcom-ipq806x-sata.c
24
#define __set(v, a, b) (((v) << (b)) & GENMASK(a, b))
drivers/phy/qualcomm/phy-qcom-m31-eusb2.c
59
#define M31_EUSB_PHY_INIT_CFG(o, b, v) \
drivers/phy/qualcomm/phy-qcom-m31-eusb2.c
63
.val = v, \
drivers/phy/qualcomm/phy-qcom-qmp-common.h
20
#define QMP_PHY_INIT_CFG(o, v) \
drivers/phy/qualcomm/phy-qcom-qmp-common.h
23
.val = v, \
drivers/phy/qualcomm/phy-qcom-qmp-common.h
28
#define QMP_PHY_INIT_CFG_LANE(o, v, l) \
drivers/phy/qualcomm/phy-qcom-qmp-common.h
31
.val = v, \
drivers/phy/qualcomm/phy-qcom-qmp-usb-legacy.c
56
#define QMP_PHY_INIT_CFG(o, v) \
drivers/phy/qualcomm/phy-qcom-qmp-usb-legacy.c
59
.val = v, \
drivers/phy/qualcomm/phy-qcom-qmp-usb-legacy.c
63
#define QMP_PHY_INIT_CFG_LANE(o, v, l) \
drivers/phy/qualcomm/phy-qcom-qmp-usb-legacy.c
66
.val = v, \
drivers/phy/qualcomm/phy-qcom-qusb2.c
110
#define QUSB2_PHY_INIT_CFG(o, v) \
drivers/phy/qualcomm/phy-qcom-qusb2.c
113
.val = v, \
drivers/phy/qualcomm/phy-qcom-qusb2.c
116
#define QUSB2_PHY_INIT_CFG_L(o, v) \
drivers/phy/qualcomm/phy-qcom-qusb2.c
119
.val = v, \
drivers/phy/qualcomm/phy-qcom-usb-hs-28nm.c
386
#define HSPHY_INIT_CFG(o, v, d) { .offset = o, .val = v, .delay = d, }
drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
1062
u32 v;
drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
1090
for (v = 0; v < 4; v++)
drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
1091
inno_write(inno, 0xef + v, phy_cfg->regs[v]);
drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
1101
ret = inno_poll(inno, 0xeb, v, v & RK3228_POST_PLL_LOCK_STATUS,
drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
1177
u32 v;
drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
1190
v = (cfg->postdiv / 2) - 1;
drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
1191
v &= RK3328_POST_PLL_POST_DIV_MASK;
drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
1192
inno_write(inno, 0xad, v);
drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
1200
for (v = 0; v < 14; v++)
drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
1201
inno_write(inno, 0xb5 + v, phy_cfg->regs[v]);
drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
1204
for (v = 0; v < 4; v++)
drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
1205
inno_update_bits(inno, 0xc8 + v, RK3328_ESD_DETECT_MASK,
drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
1210
v = clk_get_rate(inno->sysclk) / 100000;
drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
1211
inno_write(inno, 0xc5, RK3328_TERM_RESISTOR_CALIB_SPEED_14_8(v)
drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
1213
inno_write(inno, 0xc6, RK3328_TERM_RESISTOR_CALIB_SPEED_7_0(v));
drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
1228
for (v = 0; v < 3; v++)
drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
1229
inno_update_bits(inno, 0xc9 + v,
drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
1241
ret = inno_poll(inno, 0xaf, v, v & RK3328_POST_PLL_LOCK_STATUS,
drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
778
u32 v;
drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
821
ret = inno_poll(inno, 0xe8, v, v & RK3228_PRE_PLL_LOCK_STATUS,
drivers/phy/samsung/phy-exynos5-usbdrd.c
416
#define PHY_TUNING_ENTRY_PHY(o, m, v) { \
drivers/phy/samsung/phy-exynos5-usbdrd.c
419
.val = (v), \
drivers/phy/samsung/phy-exynos5-usbdrd.c
423
#define PHY_TUNING_ENTRY_PCS(o, m, v) { \
drivers/phy/samsung/phy-exynos5-usbdrd.c
426
.val = (v), \
drivers/phy/samsung/phy-exynos5-usbdrd.c
430
#define PHY_TUNING_ENTRY_PMA(o, m, v) { \
drivers/phy/samsung/phy-exynos5-usbdrd.c
433
.val = (v), \
drivers/phy/samsung/phy-exynosautov9-ufs.c
15
#define PHY_TRSV_REG_CFG_AUTOV9(o, v, d) \
drivers/phy/samsung/phy-exynosautov9-ufs.c
16
PHY_TRSV_REG_CFG_OFFSET(o, v, d, 0x50)
drivers/phy/samsung/phy-exynosautov920-ufs.c
18
#define PHY_TRSV_REG_CFG_AUTOV920(o, v, d) \
drivers/phy/samsung/phy-exynosautov920-ufs.c
19
PHY_TRSV_REG_CFG_OFFSET(o, v, d, PHY_EXYNOSAUTOV920_LANE_OFFSET)
drivers/phy/samsung/phy-gs101-ufs.c
26
#define PHY_TRSV_REG_CFG_GS101(o, v, d) \
drivers/phy/samsung/phy-gs101-ufs.c
27
PHY_TRSV_REG_CFG_OFFSET(o, v, d, PHY_GS101_LANE_OFFSET)
drivers/phy/samsung/phy-samsung-ufs.h
22
#define PHY_COMN_REG_CFG(o, v, d) { \
drivers/phy/samsung/phy-samsung-ufs.h
25
.val = (v), \
drivers/phy/samsung/phy-samsung-ufs.h
30
#define PHY_TRSV_REG_CFG_OFFSET(o, v, d, c) { \
drivers/phy/samsung/phy-samsung-ufs.h
33
.val = (v), \
drivers/phy/samsung/phy-samsung-ufs.h
38
#define PHY_TRSV_REG_CFG(o, v, d) \
drivers/phy/samsung/phy-samsung-ufs.h
39
PHY_TRSV_REG_CFG_OFFSET(o, v, d, PHY_TRSV_CH_OFFSET)
drivers/phy/tegra/xusb-tegra124.c
42
#define XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(x, v) (((v) & 0x7) << ((x) * 4))
drivers/phy/tegra/xusb-tegra210.c
54
#define XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(x, v) (((v) & 0x7) << ((x) * 5))
drivers/pinctrl/intel/pinctrl-baytrail.c
1696
u32 v;
drivers/pinctrl/intel/pinctrl-baytrail.c
1698
v = value & ~BYT_VAL_RESTORE_MASK;
drivers/pinctrl/intel/pinctrl-baytrail.c
1699
v |= vg->context.pads[i].val;
drivers/pinctrl/intel/pinctrl-baytrail.c
1700
if (v != value) {
drivers/pinctrl/intel/pinctrl-baytrail.c
1701
writel(v, reg);
drivers/pinctrl/intel/pinctrl-baytrail.c
1702
dev_dbg(dev, "restored pin %d VAL %#08x\n", i, v);
drivers/pinctrl/intel/pinctrl-intel.c
704
unsigned long v;
drivers/pinctrl/intel/pinctrl-intel.c
717
v = (value2 & PADCFG2_DEBOUNCE_MASK) >> PADCFG2_DEBOUNCE_SHIFT;
drivers/pinctrl/intel/pinctrl-intel.c
718
*arg = BIT(v) * DEBOUNCE_PERIOD_NSEC / NSEC_PER_USEC;
drivers/pinctrl/intel/pinctrl-intel.c
866
unsigned long v;
drivers/pinctrl/intel/pinctrl-intel.c
869
v = order_base_2(debounce * NSEC_PER_USEC / DEBOUNCE_PERIOD_NSEC);
drivers/pinctrl/intel/pinctrl-intel.c
870
if (v < 3 || v > 15)
drivers/pinctrl/intel/pinctrl-intel.c
873
v = 0;
drivers/pinctrl/intel/pinctrl-intel.c
887
value2 = (value2 & ~PADCFG2_DEBOUNCE_MASK) | (v << PADCFG2_DEBOUNCE_SHIFT);
drivers/pinctrl/intel/pinctrl-intel.c
888
if (v) {
drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
464
int v, v2;
drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
467
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PU, &v);
drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
475
if (v == MTK_ENABLE || v2 == MTK_ENABLE)
drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
507
int reg, err, v;
drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
511
err = mtk_hw_get_value(hw, desc, reg, &v);
drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
515
if (!v)
drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
536
int v, err;
drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
538
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PULLEN, &v);
drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
542
if (v == MTK_ENABLE)
drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
575
int err, v;
drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
577
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PULLEN, &v);
drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
581
if (v == MTK_DISABLE)
drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
584
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PULLSEL, &v);
drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
588
if (pullup ^ (v == MTK_PULLUP))
drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c
1506
int v;
drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c
1511
v = (pincfg[pin].flag & DRIVE_STRENGTH_MASK);
drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c
1512
if (!nval || !v)
drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c
1514
if (DSLO(v) == nval) {
drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c
1519
} else if (DSHI(v) == nval) {
drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c
1924
int v;
drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c
1926
v = pincfg[pin].flag & DRIVE_STRENGTH_MASK;
drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c
1928
if (DSLO(v) == nval)
drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c
1930
else if (DSHI(v) == nval)
drivers/pinctrl/pinctrl-mcp23s08_spi.c
146
u32 v;
drivers/pinctrl/pinctrl-mcp23s08_spi.c
150
ret = device_property_read_u32(dev, "microchip,spi-present-mask", &v);
drivers/pinctrl/pinctrl-mcp23s08_spi.c
152
ret = device_property_read_u32(dev, "mcp,spi-present-mask", &v);
drivers/pinctrl/pinctrl-mcp23s08_spi.c
158
spi_present_mask = v;
drivers/pinctrl/pinctrl-rockchip.c
47
#define WRITE_MASK_VAL(h, l, v) \
drivers/pinctrl/pinctrl-rockchip.c
48
(GENMASK(((h) + 16), ((l) + 16)) | (((v) << (l)) & GENMASK((h), (l))))
drivers/pinctrl/pinctrl-tps6594.c
66
#define FUNCTION(dev_name, fname, v) \
drivers/pinctrl/pinctrl-tps6594.c
71
.muxval = v, \
drivers/pinctrl/qcom/pinctrl-lpass-lpi.h
36
#define LPI_GPIO_DS_TO_VAL(v) (v / 2 - 1)
drivers/pinctrl/sophgo/pinctrl-cv18xx.c
319
u32 v = 0, m = 0;
drivers/pinctrl/sophgo/pinctrl-cv18xx.c
336
v &= ~PIN_IO_PULLDOWN;
drivers/pinctrl/sophgo/pinctrl-cv18xx.c
337
v |= FIELD_PREP(PIN_IO_PULLDOWN, arg);
drivers/pinctrl/sophgo/pinctrl-cv18xx.c
341
v &= ~PIN_IO_PULLUP;
drivers/pinctrl/sophgo/pinctrl-cv18xx.c
342
v |= FIELD_PREP(PIN_IO_PULLUP, arg);
drivers/pinctrl/sophgo/pinctrl-cv18xx.c
350
v &= ~PIN_IO_DRIVE;
drivers/pinctrl/sophgo/pinctrl-cv18xx.c
351
v |= FIELD_PREP(PIN_IO_DRIVE, ret);
drivers/pinctrl/sophgo/pinctrl-cv18xx.c
359
v &= ~PIN_IO_SCHMITT;
drivers/pinctrl/sophgo/pinctrl-cv18xx.c
360
v |= FIELD_PREP(PIN_IO_SCHMITT, ret);
drivers/pinctrl/sophgo/pinctrl-cv18xx.c
367
v &= ~PIN_IO_OUT_FAST_SLEW;
drivers/pinctrl/sophgo/pinctrl-cv18xx.c
368
v |= FIELD_PREP(PIN_IO_OUT_FAST_SLEW, arg);
drivers/pinctrl/sophgo/pinctrl-cv18xx.c
372
v &= ~PIN_IO_BUS_HOLD;
drivers/pinctrl/sophgo/pinctrl-cv18xx.c
373
v |= FIELD_PREP(PIN_IO_BUS_HOLD, arg);
drivers/pinctrl/sophgo/pinctrl-cv18xx.c
381
*value = v;
drivers/pinctrl/sophgo/pinctrl-sg2042-ops.c
197
u16 v = 0, m = 0;
drivers/pinctrl/sophgo/pinctrl-sg2042-ops.c
210
v &= ~PIN_IO_PULL_ONE_ENABLE;
drivers/pinctrl/sophgo/pinctrl-sg2042-ops.c
213
v &= ~PIN_IO_PULL_UP_MASK;
drivers/pinctrl/sophgo/pinctrl-sg2042-ops.c
219
v &= ~PIN_IO_PULL_ONE_MASK;
drivers/pinctrl/sophgo/pinctrl-sg2042-ops.c
220
v |= PIN_IO_PULL_DIR_DOWN;
drivers/pinctrl/sophgo/pinctrl-sg2042-ops.c
223
v |= PIN_IO_PULL_UP_DONW;
drivers/pinctrl/sophgo/pinctrl-sg2042-ops.c
229
v &= ~PIN_IO_PULL_ONE_MASK;
drivers/pinctrl/sophgo/pinctrl-sg2042-ops.c
230
v |= PIN_IO_PULL_DIR_UP;
drivers/pinctrl/sophgo/pinctrl-sg2042-ops.c
233
v |= PIN_IO_PULL_UP;
drivers/pinctrl/sophgo/pinctrl-sg2042-ops.c
238
v &= ~(PIN_IO_DRIVE | PIN_IO_OUTPUT_ENABLE);
drivers/pinctrl/sophgo/pinctrl-sg2042-ops.c
244
v |= PIN_IO_OUTPUT_ENABLE;
drivers/pinctrl/sophgo/pinctrl-sg2042-ops.c
245
v |= FIELD_PREP(PIN_IO_DRIVE, ret);
drivers/pinctrl/sophgo/pinctrl-sg2042-ops.c
250
v |= PIN_IO_SCHMITT_ENABLE;
drivers/pinctrl/sophgo/pinctrl-sg2042-ops.c
258
*value = v;
drivers/pinctrl/sophgo/pinctrl-sg2042-ops.c
72
u32 v = readl(reg);
drivers/pinctrl/sophgo/pinctrl-sg2042-ops.c
75
v &= ~(mask << 16);
drivers/pinctrl/sophgo/pinctrl-sg2042-ops.c
76
v |= value << 16;
drivers/pinctrl/sophgo/pinctrl-sg2042-ops.c
78
v &= ~mask;
drivers/pinctrl/sophgo/pinctrl-sg2042-ops.c
79
v |= value;
drivers/pinctrl/sophgo/pinctrl-sg2042-ops.c
82
writel(v, reg);
drivers/pinctrl/spacemit/pinctrl-k1.c
696
u32 v = 0, voltage = 0, arg, val;
drivers/pinctrl/spacemit/pinctrl-k1.c
708
v &= ~(PAD_PULL_EN | PAD_PULLDOWN | PAD_PULLUP);
drivers/pinctrl/spacemit/pinctrl-k1.c
709
v &= ~PAD_STRONG_PULL;
drivers/pinctrl/spacemit/pinctrl-k1.c
712
v &= ~(PAD_PULLUP | PAD_STRONG_PULL);
drivers/pinctrl/spacemit/pinctrl-k1.c
713
v |= (PAD_PULL_EN | PAD_PULLDOWN);
drivers/pinctrl/spacemit/pinctrl-k1.c
716
v &= ~PAD_PULLDOWN;
drivers/pinctrl/spacemit/pinctrl-k1.c
717
v |= (PAD_PULL_EN | PAD_PULLUP);
drivers/pinctrl/spacemit/pinctrl-k1.c
720
v |= PAD_STRONG_PULL;
drivers/pinctrl/spacemit/pinctrl-k1.c
727
v &= ~dconf->schmitt_mask;
drivers/pinctrl/spacemit/pinctrl-k1.c
728
v |= (arg << __ffs(dconf->schmitt_mask)) & dconf->schmitt_mask;
drivers/pinctrl/spacemit/pinctrl-k1.c
736
v |= PAD_SLEW_RATE_EN;
drivers/pinctrl/spacemit/pinctrl-k1.c
739
v &= ~PAD_SLEW_RATE_EN;
drivers/pinctrl/spacemit/pinctrl-k1.c
767
v &= ~dconf->drive_mask;
drivers/pinctrl/spacemit/pinctrl-k1.c
768
v |= (val << __ffs(dconf->drive_mask)) & dconf->drive_mask;
drivers/pinctrl/spacemit/pinctrl-k1.c
774
val = FIELD_GET(PAD_SLEW_RATE, v) + 2;
drivers/pinctrl/spacemit/pinctrl-k1.c
780
v &= ~PAD_SLEW_RATE;
drivers/pinctrl/spacemit/pinctrl-k1.c
782
v |= FIELD_PREP(PAD_SLEW_RATE, slew_rate);
drivers/pinctrl/spacemit/pinctrl-k1.c
786
*value = v;
drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c
168
static unsigned int starfive_pinmux_to_gpio(u32 v)
drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c
170
return v & (NR_GPIOS - 1);
drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c
173
static u32 starfive_pinmux_to_dout(u32 v)
drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c
175
return ((v & BIT(7)) << (31 - 7)) | ((v >> 24) & GENMASK(7, 0));
drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c
178
static u32 starfive_pinmux_to_doen(u32 v)
drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c
180
return ((v & BIT(6)) << (31 - 6)) | ((v >> 16) & GENMASK(7, 0));
drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c
183
static u32 starfive_pinmux_to_din(u32 v)
drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c
185
return (v >> 8) & GENMASK(7, 0);
drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c
576
u32 v;
drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c
578
ret = of_property_read_u32_index(child, "pins", i, &v);
drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c
581
pins[i] = v;
drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c
653
u32 v = pinmux[i];
drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c
654
unsigned int gpio = starfive_pinmux_to_gpio(v);
drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c
655
u32 dout = starfive_pinmux_to_dout(v);
drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c
656
u32 doen = starfive_pinmux_to_doen(v);
drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c
657
u32 din = starfive_pinmux_to_din(v);
drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c
309
u32 v = pinmux[i];
drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c
313
jh7110_pinmux_pin(v),
drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c
314
jh7110_pinmux_din(v),
drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c
315
jh7110_pinmux_dout(v),
drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c
316
jh7110_pinmux_doen(v),
drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c
317
jh7110_pinmux_function(v));
drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c
338
static u32 jh7110_padcfg_ds_from_mA(u32 v)
drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c
343
if (v <= jh7110_drive_strength_mA[i])
drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c
55
static unsigned int jh7110_pinmux_din(u32 v)
drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c
57
return (v & GENMASK(31, 24)) >> 24;
drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c
60
static u32 jh7110_pinmux_dout(u32 v)
drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c
62
return (v & GENMASK(23, 16)) >> 16;
drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c
65
static u32 jh7110_pinmux_doen(u32 v)
drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c
67
return (v & GENMASK(15, 10)) >> 10;
drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c
70
static u32 jh7110_pinmux_function(u32 v)
drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c
72
return (v & GENMASK(9, 8)) >> 8;
drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c
75
static unsigned int jh7110_pinmux_pin(u32 v)
drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c
77
return v & GENMASK(7, 0);
drivers/pinctrl/sunplus/sppctl.h
73
#define EGRP(n, v, p) { \
drivers/pinctrl/sunplus/sppctl.h
75
.gval = (v), \
drivers/pinctrl/visconti/pinctrl-common.h
53
#define VISCONTI_PIN_GROUP(group_name, off, msk, v) \
drivers/pinctrl/visconti/pinctrl-common.h
61
.val = v, \
drivers/platform/raspberrypi/vchiq-interface/vchiq_arm.c
942
vchiq_keepalive_thread_func(void *v)
drivers/platform/raspberrypi/vchiq-interface/vchiq_arm.c
944
struct vchiq_state *state = (struct vchiq_state *)v;
drivers/platform/raspberrypi/vchiq-interface/vchiq_core.c
2305
slot_handler_func(void *v)
drivers/platform/raspberrypi/vchiq-interface/vchiq_core.c
2307
struct vchiq_state *state = v;
drivers/platform/raspberrypi/vchiq-interface/vchiq_core.c
2343
recycle_func(void *v)
drivers/platform/raspberrypi/vchiq-interface/vchiq_core.c
2345
struct vchiq_state *state = v;
drivers/platform/raspberrypi/vchiq-interface/vchiq_core.c
2370
sync_func(void *v)
drivers/platform/raspberrypi/vchiq-interface/vchiq_core.c
2372
struct vchiq_state *state = v;
drivers/platform/raspberrypi/vchiq-mmal/mmal-common.h
63
u32 v;
drivers/platform/surface/surface_dtx.c
579
__u16 v;
drivers/platform/surface/surface_dtx.c
584
struct sdtx_base_info v;
drivers/platform/surface/surface_dtx.c
672
event.base.v.state = sdtx_translate_base_state(ddev, in->data[0]);
drivers/platform/surface/surface_dtx.c
673
event.base.v.base_id = SDTX_BASE_TYPE_SSH(in->data[1]);
drivers/platform/surface/surface_dtx.c
684
event.status.v = sdtx_translate_cancel_reason(ddev, in->data[0]);
drivers/platform/surface/surface_dtx.c
698
event.status.v = sdtx_translate_latch_status(ddev, in->data[0]);
drivers/platform/surface/surface_dtx.c
775
event.v = mode;
drivers/platform/surface/surface_dtx.c
809
event.v.state = sdtx_translate_base_state(ddev, info.state);
drivers/platform/surface/surface_dtx.c
810
event.v.base_id = SDTX_BASE_TYPE_SSH(info.base_id);
drivers/platform/surface/surface_dtx.c
844
event.v = mode;
drivers/platform/surface/surface_dtx.c
869
event.v = sdtx_translate_latch_status(ddev, status);
drivers/platform/x86/intel/pmc/core.h
206
#define GET_X2_COUNTER(v) ((v) >> 1)
drivers/platform/x86/intel/pmt/class.h
19
#define GET_BIR(v) ((v) & GENMASK(2, 0))
drivers/platform/x86/intel/pmt/class.h
20
#define GET_ADDRESS(v) ((v) & GENMASK(31, 3))
drivers/platform/x86/intel/pmt/crashlog.c
32
#define GET_ACCESS(v) ((v) & GENMASK(3, 0))
drivers/platform/x86/intel/pmt/crashlog.c
33
#define GET_TYPE(v) (((v) & GENMASK(7, 4)) >> 4)
drivers/platform/x86/intel/pmt/crashlog.c
34
#define GET_VERSION(v) (((v) & GENMASK(19, 16)) >> 16)
drivers/platform/x86/intel/pmt/crashlog.c
36
#define GET_SIZE(v) ((v) * sizeof(u32))
drivers/platform/x86/intel/pmt/telemetry.c
33
#define TELEM_ACCESS(v) ((v) & GENMASK(3, 0))
drivers/platform/x86/intel/pmt/telemetry.c
34
#define TELEM_TYPE(v) (((v) & GENMASK(7, 4)) >> 4)
drivers/platform/x86/intel/pmt/telemetry.c
36
#define TELEM_SIZE(v) (((v) & GENMASK(27, 12)) >> 10)
drivers/platform/x86/intel/pmt/telemetry.c
41
#define NUM_BYTES_QWORD(v) ((v) << 3)
drivers/platform/x86/intel/pmt/telemetry.c
42
#define SAMPLE_ID_OFFSET(v) ((v) << 3)
drivers/platform/x86/intel/pmt/telemetry.c
44
#define NUM_BYTES_DWORD(v) ((v) << 2)
drivers/platform/x86/intel/pmt/telemetry.c
45
#define SAMPLE_ID_OFFSET32(v) ((v) << 2)
drivers/platform/x86/intel/sdsi.c
79
#define DT_OFFSET(v) ((v) & GENMASK(31, 3))
drivers/platform/x86/intel/uncore-frequency/uncore-frequency-tpmi.c
155
unsigned int min, max, v;
drivers/platform/x86/intel/uncore-frequency/uncore-frequency-tpmi.c
170
&v, index);
drivers/platform/x86/intel/uncore-frequency/uncore-frequency-tpmi.c
171
if (v < min)
drivers/platform/x86/intel/uncore-frequency/uncore-frequency-tpmi.c
172
min = v;
drivers/platform/x86/intel/uncore-frequency/uncore-frequency-tpmi.c
173
if (v > max)
drivers/platform/x86/intel/uncore-frequency/uncore-frequency-tpmi.c
174
max = v;
drivers/platform/x86/lenovo/thinkpad_acpi.c
695
int v;
drivers/platform/x86/lenovo/thinkpad_acpi.c
698
if (!acpi_evalf(ecrd_handle, &v, NULL, "dd", i))
drivers/platform/x86/lenovo/thinkpad_acpi.c
700
*p = v;
drivers/platform/x86/lenovo/thinkpad_acpi.c
709
static int acpi_ec_write(int i, u8 v)
drivers/platform/x86/lenovo/thinkpad_acpi.c
712
if (!acpi_evalf(ecwr_handle, NULL, NULL, "vdd", i, v))
drivers/platform/x86/lenovo/thinkpad_acpi.c
715
if (ec_write(i, v) < 0)
drivers/platform/x86/lenovo/thinkpad_acpi.c
908
static int dispatch_proc_show(struct seq_file *m, void *v)
drivers/platform/x86/lenovo/thinkpad_acpi.c
9624
int ret, v;
drivers/platform/x86/lenovo/thinkpad_acpi.c
9630
ret = tpacpi_battery_get(what, battery, &v);
drivers/platform/x86/lenovo/thinkpad_acpi.c
9634
if (v == value)
drivers/platform/x86/lenovo/thinkpad_acpi.c
9639
ret = tpacpi_battery_get(what, battery, &v);
drivers/platform/x86/lenovo/thinkpad_acpi.c
9643
if (v == value)
drivers/platform/x86/sony-laptop.c
796
u64 v = *value;
drivers/platform/x86/sony-laptop.c
798
ret = sony_nc_buffer_call(handle, name, &v, result,
drivers/platform/x86/toshiba_acpi.c
1427
static int lcd_proc_show(struct seq_file *m, void *v)
drivers/platform/x86/toshiba_acpi.c
1530
static int video_proc_show(struct seq_file *m, void *v)
drivers/platform/x86/toshiba_acpi.c
1647
static int fan_proc_show(struct seq_file *m, void *v)
drivers/platform/x86/toshiba_acpi.c
1722
static int keys_proc_show(struct seq_file *m, void *v)
drivers/platform/x86/toshiba_acpi.c
1766
static int __maybe_unused version_proc_show(struct seq_file *m, void *v)
drivers/platform/x86/uv_sysfs.c
788
u64 v;
drivers/platform/x86/uv_sysfs.c
795
biosr = uv_bios_get_heapsize((u64)uv_master_nasid, (u64)sizeof(u64), &v);
drivers/platform/x86/uv_sysfs.c
799
uv_biosheap = vmalloc(v);
drivers/platform/x86/uv_sysfs.c
803
biosr = uv_bios_install_heap((u64)uv_master_nasid, v, (u64 *)uv_biosheap);
drivers/platform/x86/uv_sysfs.c
809
biosr = uv_bios_obj_count((u64)uv_master_nasid, sizeof(u64), &v);
drivers/platform/x86/uv_sysfs.c
814
uv_bios_obj_cnt = (int)v;
drivers/pmdomain/ti/omap_prm.c
526
u32 v, mode;
drivers/pmdomain/ti/omap_prm.c
535
v = prmd->pwrstctrl_saved;
drivers/pmdomain/ti/omap_prm.c
537
v = readl_relaxed(prmd->prm->base + prmd->pwrstctrl);
drivers/pmdomain/ti/omap_prm.c
544
writel_relaxed((v & ~PRM_POWERSTATE_MASK) | mode,
drivers/pmdomain/ti/omap_prm.c
549
v, !(v & PRM_ST_INTRANSITION), 1,
drivers/pmdomain/ti/omap_prm.c
570
u32 v;
drivers/pmdomain/ti/omap_prm.c
578
v = readl_relaxed(prmd->prm->base + prmd->pwrstctrl);
drivers/pmdomain/ti/omap_prm.c
579
prmd->pwrstctrl_saved = v;
drivers/pmdomain/ti/omap_prm.c
581
v &= ~PRM_POWERSTATE_MASK;
drivers/pmdomain/ti/omap_prm.c
582
v |= omap_prm_domain_find_lowest(prmd);
drivers/pmdomain/ti/omap_prm.c
585
v |= PRM_LOWPOWERSTATECHANGE;
drivers/pmdomain/ti/omap_prm.c
587
v &= ~PRM_LOGICRETSTATE;
drivers/pmdomain/ti/omap_prm.c
589
v |= PRM_LOGICRETSTATE;
drivers/pmdomain/ti/omap_prm.c
591
writel_relaxed(v, prmd->prm->base + prmd->pwrstctrl);
drivers/pmdomain/ti/omap_prm.c
595
v, !(v & PRM_ST_INTRANSITION), 1,
drivers/pmdomain/ti/omap_prm.c
755
u32 v;
drivers/pmdomain/ti/omap_prm.c
765
v = readl_relaxed(reset->prm->base + reset->prm->data->rstctrl);
drivers/pmdomain/ti/omap_prm.c
766
if (v & BIT(id))
drivers/pmdomain/ti/omap_prm.c
773
v = readl_relaxed(reset->prm->base + reset->prm->data->rstst);
drivers/pmdomain/ti/omap_prm.c
774
v >>= st_bit;
drivers/pmdomain/ti/omap_prm.c
775
v &= 1;
drivers/pmdomain/ti/omap_prm.c
777
return !v;
drivers/pmdomain/ti/omap_prm.c
784
u32 v;
drivers/pmdomain/ti/omap_prm.c
789
v = readl_relaxed(reset->prm->base + reset->prm->data->rstctrl);
drivers/pmdomain/ti/omap_prm.c
790
v |= 1 << id;
drivers/pmdomain/ti/omap_prm.c
791
writel_relaxed(v, reset->prm->base + reset->prm->data->rstctrl);
drivers/pmdomain/ti/omap_prm.c
801
u32 v;
drivers/pmdomain/ti/omap_prm.c
819
v = 1 << st_bit;
drivers/pmdomain/ti/omap_prm.c
820
writel_relaxed(v, reset->prm->base + reset->prm->data->rstst);
drivers/pmdomain/ti/omap_prm.c
828
v = readl_relaxed(reset->prm->base + reset->prm->data->rstctrl);
drivers/pmdomain/ti/omap_prm.c
829
v &= ~(1 << id);
drivers/pmdomain/ti/omap_prm.c
830
writel_relaxed(v, reset->prm->base + reset->prm->data->rstctrl);
drivers/pmdomain/ti/omap_prm.c
836
v, !(v & BIT(id)), 1,
drivers/pmdomain/ti/omap_prm.c
846
v, v & BIT(st_bit), 1,
drivers/pmdomain/ti/omap_prm.c
883
u32 v;
drivers/pmdomain/ti/omap_prm.c
933
v = readl_relaxed(reset->prm->base + reset->prm->data->rstctrl);
drivers/pmdomain/ti/omap_prm.c
934
if ((v & reset->mask) != reset->mask) {
drivers/pmdomain/ti/omap_prm.c
935
dev_dbg(&pdev->dev, "Asserting all resets: %08x\n", v);
drivers/pnp/pnpbios/proc.c
106
static int pnp_legacyres_proc_show(struct seq_file *m, void *v)
drivers/pnp/pnpbios/proc.c
123
static int pnp_devices_proc_show(struct seq_file *m, void *v)
drivers/pnp/pnpbios/proc.c
153
static int pnpbios_proc_show(struct seq_file *m, void *v)
drivers/pnp/pnpbios/proc.c
37
static int pnpconfig_proc_show(struct seq_file *m, void *v)
drivers/pnp/pnpbios/proc.c
50
static int escd_info_proc_show(struct seq_file *m, void *v)
drivers/pnp/pnpbios/proc.c
65
static int escd_proc_show(struct seq_file *m, void *v)
drivers/power/supply/axp20x_usb_power.c
210
unsigned int input, v;
drivers/power/supply/axp20x_usb_power.c
215
ret = regmap_read(power->regmap, AXP20X_VBUS_IPSOUT_MGMT, &v);
drivers/power/supply/axp20x_usb_power.c
219
val->intval = AXP20X_VBUS_VHOLD_uV(v);
drivers/power/supply/axp20x_usb_power.c
243
ret = regmap_field_read(power->curr_lim_fld, &v);
drivers/power/supply/axp20x_usb_power.c
247
if (v < power->axp_data->curr_lim_table_size)
drivers/power/supply/axp20x_usb_power.c
248
val->intval = power->axp_data->curr_lim_table[v];
drivers/power/supply/axp20x_usb_power.c
296
ret = regmap_field_read(power->vbus_valid_bit, &v);
drivers/power/supply/axp20x_usb_power.c
300
if (v == 0)
drivers/power/supply/axp20x_usb_power.c
322
unsigned int v;
drivers/power/supply/axp20x_usb_power.c
328
ret = regmap_read(power->regmap, AXP717_ON_INDICATE, &v);
drivers/power/supply/axp20x_usb_power.c
332
if (!(v & AXP717_PWR_STATUS_VBUS_GOOD))
drivers/power/supply/axp20x_usb_power.c
335
ret = regmap_read(power->regmap, AXP717_PMU_FAULT_VBUS, &v);
drivers/power/supply/axp20x_usb_power.c
339
v &= (AXP717_PMU_FAULT_VBUS | AXP717_PMU_FAULT_VSYS);
drivers/power/supply/axp20x_usb_power.c
340
if (v) {
drivers/power/supply/axp20x_usb_power.c
342
regmap_write(power->regmap, AXP717_PMU_FAULT_VBUS, v);
drivers/power/supply/axp20x_usb_power.c
347
ret = regmap_read(power->regmap, AXP717_INPUT_CUR_LIMIT_CTRL, &v);
drivers/power/supply/axp20x_usb_power.c
352
v &= AXP717_INPUT_CUR_LIMIT_MASK;
drivers/power/supply/axp20x_usb_power.c
353
val->intval = (v * 50000) + 100000;
drivers/power/supply/axp20x_usb_power.c
357
ret = regmap_read(power->regmap, AXP717_ON_INDICATE, &v);
drivers/power/supply/axp20x_usb_power.c
360
val->intval = !!(v & AXP717_PWR_STATUS_VBUS_GOOD);
drivers/power/supply/axp20x_usb_power.c
365
ret = regmap_read(power->regmap, AXP717_INPUT_VOL_LIMIT_CTRL, &v);
drivers/power/supply/axp20x_usb_power.c
370
v &= AXP717_INPUT_VOL_LIMIT_MASK;
drivers/power/supply/axp20x_usb_power.c
371
val->intval = (v * 80000) + 3880000;
drivers/power/supply/bq2415x_charger.c
808
unsigned long val, void *v)
drivers/power/supply/bq2415x_charger.c
812
struct power_supply *psy = v;
drivers/power/supply/bq24190_charger.c
1034
u8 v;
drivers/power/supply/bq24190_charger.c
1038
v = bdi->f_reg;
drivers/power/supply/bq24190_charger.c
1041
if (v & bdi->info->ntc_fault_mask) {
drivers/power/supply/bq24190_charger.c
1042
health = bdi->info->get_ntc_status(v);
drivers/power/supply/bq24190_charger.c
1043
} else if (v & BQ24190_REG_F_BAT_FAULT_MASK) {
drivers/power/supply/bq24190_charger.c
1045
} else if (v & BQ24190_REG_F_CHRG_FAULT_MASK) {
drivers/power/supply/bq24190_charger.c
1046
switch (v >> BQ24190_REG_F_CHRG_FAULT_SHIFT & 0x3) {
drivers/power/supply/bq24190_charger.c
1066
} else if (v & BQ24190_REG_F_BOOST_FAULT_MASK) {
drivers/power/supply/bq24190_charger.c
1142
u8 v;
drivers/power/supply/bq24190_charger.c
1147
BQ24190_REG_PCTCC_IPRECHG_SHIFT, &v);
drivers/power/supply/bq24190_charger.c
1151
curr = ++v * 128 * 1000;
drivers/power/supply/bq24190_charger.c
1155
BQ24190_REG_CCC_FORCE_20PCT_SHIFT, &v);
drivers/power/supply/bq24190_charger.c
1160
if (v)
drivers/power/supply/bq24190_charger.c
1171
u8 v;
drivers/power/supply/bq24190_charger.c
1176
BQ24190_REG_PCTCC_ITERM_SHIFT, &v);
drivers/power/supply/bq24190_charger.c
1180
val->intval = ++v * 128 * 1000;
drivers/power/supply/bq24190_charger.c
1187
u8 v;
drivers/power/supply/bq24190_charger.c
1199
BQ24190_REG_CCC_FORCE_20PCT_SHIFT, &v);
drivers/power/supply/bq24190_charger.c
1204
if (v)
drivers/power/supply/bq24190_charger.c
1214
u8 v;
drivers/power/supply/bq24190_charger.c
1219
BQ24190_REG_CCC_FORCE_20PCT_SHIFT, &v);
drivers/power/supply/bq24190_charger.c
1224
if (v)
drivers/power/supply/bq24190_charger.c
1568
u8 v;
drivers/power/supply/bq24190_charger.c
1572
v = bdi->f_reg;
drivers/power/supply/bq24190_charger.c
1575
if (v & BQ24190_REG_F_BAT_FAULT_MASK) {
drivers/power/supply/bq24190_charger.c
1578
v &= bdi->info->ntc_fault_mask;
drivers/power/supply/bq24190_charger.c
1580
health = v ? bdi->info->get_ntc_status(v) : POWER_SUPPLY_HEALTH_GOOD;
drivers/power/supply/bq24190_charger.c
1862
u8 v;
drivers/power/supply/bq24190_charger.c
1868
&v);
drivers/power/supply/bq24190_charger.c
1872
switch (v) {
drivers/power/supply/bq24190_charger.c
1878
dev_err(bdi->dev, "Error unknown model: 0x%02x\n", v);
drivers/power/supply/bq24190_charger.c
1887
u8 v;
drivers/power/supply/bq24190_charger.c
1893
&v);
drivers/power/supply/bq24190_charger.c
1897
switch (v) {
drivers/power/supply/bq24190_charger.c
1902
dev_err(bdi->dev, "Error unknown model: 0x%02x\n", v);
drivers/power/supply/bq24190_charger.c
1932
int v, idx;
drivers/power/supply/bq24190_charger.c
1941
if (device_property_read_u32(bdi->dev, s, &v) == 0) {
drivers/power/supply/bq24190_charger.c
1942
v /= 1000;
drivers/power/supply/bq24190_charger.c
1943
if (v >= BQ24190_REG_POC_SYS_MIN_MIN
drivers/power/supply/bq24190_charger.c
1944
&& v <= BQ24190_REG_POC_SYS_MIN_MAX)
drivers/power/supply/bq24190_charger.c
1945
bdi->sys_min = v;
drivers/power/supply/bq24190_charger.c
1947
dev_warn(bdi->dev, "invalid value for %s: %u\n", s, v);
drivers/power/supply/bq24190_charger.c
1951
v = info->precharge_current_ua / 1000;
drivers/power/supply/bq24190_charger.c
1952
if (v >= BQ24190_REG_PCTCC_IPRECHG_MIN
drivers/power/supply/bq24190_charger.c
1953
&& v <= BQ24190_REG_PCTCC_IPRECHG_MAX)
drivers/power/supply/bq24190_charger.c
1954
bdi->iprechg = v;
drivers/power/supply/bq24190_charger.c
1957
v);
drivers/power/supply/bq24190_charger.c
1959
v = info->charge_term_current_ua / 1000;
drivers/power/supply/bq24190_charger.c
1960
if (v >= BQ24190_REG_PCTCC_ITERM_MIN
drivers/power/supply/bq24190_charger.c
1961
&& v <= BQ24190_REG_PCTCC_ITERM_MAX)
drivers/power/supply/bq24190_charger.c
1962
bdi->iterm = v;
drivers/power/supply/bq24190_charger.c
1965
v);
drivers/power/supply/bq24190_charger.c
1968
v = info->constant_charge_current_max_ua;
drivers/power/supply/bq24190_charger.c
1969
if (v >= bq24190_ccc_ichg_values[0] && v <= bdi->ichg_max)
drivers/power/supply/bq24190_charger.c
1970
bdi->ichg = bdi->ichg_max = v;
drivers/power/supply/bq24190_charger.c
1972
v = info->constant_charge_voltage_max_uv;
drivers/power/supply/bq24190_charger.c
1973
if (v >= bq24190_cvc_vreg_values[0] && v <= bdi->vreg_max)
drivers/power/supply/bq24190_charger.c
1974
bdi->vreg = bdi->vreg_max = v;
drivers/power/supply/bq24190_charger.c
276
static u8 bq24190_find_idx(const int tbl[], int tbl_size, int v)
drivers/power/supply/bq24190_charger.c
281
if (v < tbl[i])
drivers/power/supply/bq24190_charger.c
309
u8 v;
drivers/power/supply/bq24190_charger.c
312
ret = bq24190_read(bdi, reg, &v);
drivers/power/supply/bq24190_charger.c
316
v &= mask;
drivers/power/supply/bq24190_charger.c
317
v >>= shift;
drivers/power/supply/bq24190_charger.c
318
*data = v;
drivers/power/supply/bq24190_charger.c
326
u8 v;
drivers/power/supply/bq24190_charger.c
329
ret = bq24190_read(bdi, reg, &v);
drivers/power/supply/bq24190_charger.c
333
v &= ~mask;
drivers/power/supply/bq24190_charger.c
334
v |= ((data << shift) & mask);
drivers/power/supply/bq24190_charger.c
336
return bq24190_write(bdi, reg, v);
drivers/power/supply/bq24190_charger.c
344
u8 v;
drivers/power/supply/bq24190_charger.c
347
ret = bq24190_read_mask(bdi, reg, mask, shift, &v);
drivers/power/supply/bq24190_charger.c
351
v = (v >= tbl_size) ? (tbl_size - 1) : v;
drivers/power/supply/bq24190_charger.c
352
*val = tbl[v];
drivers/power/supply/bq24190_charger.c
491
u8 v;
drivers/power/supply/bq24190_charger.c
501
ret = bq24190_read_mask(bdi, info->reg, info->mask, info->shift, &v);
drivers/power/supply/bq24190_charger.c
505
count = sysfs_emit(buf, "%hhx\n", v);
drivers/power/supply/bq24190_charger.c
519
u8 v;
drivers/power/supply/bq24190_charger.c
525
ret = kstrtou8(buf, 0, &v);
drivers/power/supply/bq24190_charger.c
533
ret = bq24190_write_mask(bdi, info->reg, info->mask, info->shift, v);
drivers/power/supply/bq24190_charger.c
752
u8 v;
drivers/power/supply/bq24190_charger.c
754
ret = bq24190_read(bdi, BQ24190_REG_CTTC, &v);
drivers/power/supply/bq24190_charger.c
758
bdi->watchdog = ((v & BQ24190_REG_CTTC_WATCHDOG_MASK) >>
drivers/power/supply/bq24190_charger.c
769
v &= ~BQ24190_REG_CTTC_WATCHDOG_MASK;
drivers/power/supply/bq24190_charger.c
771
ret = bq24190_write(bdi, BQ24190_REG_CTTC, v);
drivers/power/supply/bq24190_charger.c
776
v = bdi->sys_min / 100 - 30; // manual section 9.5.1.2, table 9
drivers/power/supply/bq24190_charger.c
780
v);
drivers/power/supply/bq24190_charger.c
786
v = bdi->iprechg / 128 - 1; // manual section 9.5.1.4, table 11
drivers/power/supply/bq24190_charger.c
790
v);
drivers/power/supply/bq24190_charger.c
796
v = bdi->iterm / 128 - 1; // manual section 9.5.1.4, table 11
drivers/power/supply/bq24190_charger.c
800
v);
drivers/power/supply/bq24190_charger.c
833
u8 v;
drivers/power/supply/bq24190_charger.c
861
&v);
drivers/power/supply/bq24190_charger.c
865
if (v == 0)
drivers/power/supply/bq24190_charger.c
879
u8 v;
drivers/power/supply/bq24190_charger.c
885
&v);
drivers/power/supply/bq24190_charger.c
890
if (!v) {
drivers/power/supply/bq24190_charger.c
896
&v);
drivers/power/supply/bq24190_charger.c
900
type = (v) ? POWER_SUPPLY_CHARGE_TYPE_TRICKLE :
drivers/power/supply/da9030_battery.c
452
char v[5];
drivers/power/supply/da9030_battery.c
455
v[0] = v[1] = charger->thresholds.vbat_low;
drivers/power/supply/da9030_battery.c
456
v[2] = charger->thresholds.tbat_high;
drivers/power/supply/da9030_battery.c
457
v[3] = charger->thresholds.tbat_restart;
drivers/power/supply/da9030_battery.c
458
v[4] = charger->thresholds.tbat_low;
drivers/power/supply/da9030_battery.c
460
ret = da903x_writes(charger->master, DA9030_VBATMON, 5, v);
drivers/power/supply/da9052-battery.c
220
u8 v[2] = {0, 0};
drivers/power/supply/da9052-battery.c
233
ret = da9052_group_read(bat->da9052, DA9052_STATUS_A_REG, 2, v);
drivers/power/supply/da9052-battery.c
237
bat_status = v[0];
drivers/power/supply/da9052-battery.c
238
chg_end = v[1];
drivers/power/supply/isp1704_charger.c
294
unsigned long val, void *v)
drivers/power/supply/rn5t618_power.c
158
unsigned int v;
drivers/power/supply/rn5t618_power.c
161
ret = regmap_read(info->rn5t618->regmap, RN5T618_CHGSTATE, &v);
drivers/power/supply/rn5t618_power.c
167
if (v & 0xc0) { /* USB or ADP plugged */
drivers/power/supply/rn5t618_power.c
168
val->intval = rn5t618_decode_status(v);
drivers/power/supply/rn5t618_power.c
178
unsigned int v;
drivers/power/supply/rn5t618_power.c
181
ret = regmap_read(info->rn5t618->regmap, RN5T618_CHGSTATE, &v);
drivers/power/supply/rn5t618_power.c
185
v &= CHG_STATE_MASK;
drivers/power/supply/rn5t618_power.c
186
if ((v == CHG_STATE_NO_BAT) || (v == CHG_STATE_NO_BAT2))
drivers/power/supply/rn5t618_power.c
228
unsigned int v;
drivers/power/supply/rn5t618_power.c
231
ret = regmap_read(info->rn5t618->regmap, RN5T618_SOC, &v);
drivers/power/supply/rn5t618_power.c
235
val->intval = v;
drivers/power/supply/rn5t618_power.c
718
unsigned int v;
drivers/power/supply/rn5t618_power.c
746
ret = regmap_read(info->rn5t618->regmap, RN5T618_CONTROL, &v);
drivers/power/supply/rn5t618_power.c
750
if (!(v & FG_ENABLE)) {
drivers/power/supply/rt9455_charger.c
255
static unsigned int rt9455_find_idx(const int tbl[], int tbl_size, int v)
drivers/power/supply/rt9455_charger.c
266
if (v <= tbl[i])
drivers/power/supply/rt9455_charger.c
276
unsigned int v;
drivers/power/supply/rt9455_charger.c
279
ret = regmap_field_read(info->regmap_fields[field], &v);
drivers/power/supply/rt9455_charger.c
283
v = (v >= tbl_size) ? (tbl_size - 1) : v;
drivers/power/supply/rt9455_charger.c
284
*val = tbl[v];
drivers/power/supply/rt9455_charger.c
301
unsigned int v;
drivers/power/supply/rt9455_charger.c
315
ret = regmap_field_read(info->regmap_fields[F_RST], &v);
drivers/power/supply/rt9455_charger.c
321
if (!v)
drivers/power/supply/rt9455_charger.c
356
unsigned int v, pwr_rdy;
drivers/power/supply/rt9455_charger.c
375
ret = regmap_field_read(info->regmap_fields[F_STAT], &v);
drivers/power/supply/rt9455_charger.c
381
switch (v) {
drivers/power/supply/rt9455_charger.c
409
unsigned int v;
drivers/power/supply/rt9455_charger.c
414
ret = regmap_read(info->regmap, RT9455_REG_IRQ1, &v);
drivers/power/supply/rt9455_charger.c
420
if (v & GET_MASK(F_TSDI)) {
drivers/power/supply/rt9455_charger.c
424
if (v & GET_MASK(F_VINOVPI)) {
drivers/power/supply/rt9455_charger.c
428
if (v & GET_MASK(F_BATAB)) {
drivers/power/supply/rt9455_charger.c
433
ret = regmap_read(info->regmap, RT9455_REG_IRQ2, &v);
drivers/power/supply/rt9455_charger.c
439
if (v & GET_MASK(F_CHBATOVI)) {
drivers/power/supply/rt9455_charger.c
443
if (v & GET_MASK(F_CH32MI)) {
drivers/power/supply/rt9455_charger.c
448
ret = regmap_read(info->regmap, RT9455_REG_IRQ3, &v);
drivers/power/supply/rt9455_charger.c
454
if (v & GET_MASK(F_BSTBUSOVI)) {
drivers/power/supply/rt9455_charger.c
458
if (v & GET_MASK(F_BSTOLI)) {
drivers/power/supply/rt9455_charger.c
462
if (v & GET_MASK(F_BSTLOWVI)) {
drivers/power/supply/rt9455_charger.c
466
if (v & GET_MASK(F_BST32SI)) {
drivers/power/supply/rt9455_charger.c
471
ret = regmap_field_read(info->regmap_fields[F_STAT], &v);
drivers/power/supply/rt9455_charger.c
477
if (v == RT9455_FAULT) {
drivers/power/supply/rt9455_charger.c
488
unsigned int v;
drivers/power/supply/rt9455_charger.c
491
ret = regmap_field_read(info->regmap_fields[F_BATAB], &v);
drivers/power/supply/rt9455_charger.c
501
val->intval = !v;
drivers/power/supply/rt9455_charger.c
509
unsigned int v;
drivers/power/supply/rt9455_charger.c
512
ret = regmap_field_read(info->regmap_fields[F_PWR_RDY], &v);
drivers/power/supply/rt9455_charger.c
518
val->intval = (int)v;
drivers/power/supply/smb347-charger.c
1007
if (v & 0x20) {
drivers/power/supply/smb347-charger.c
1009
ARRAY_SIZE(fcc_tbl[id]), v & 7);
drivers/power/supply/smb347-charger.c
1011
v >>= 3;
drivers/power/supply/smb347-charger.c
1013
ARRAY_SIZE(pcc_tbl[id]), v & 7);
drivers/power/supply/smb347-charger.c
1026
unsigned int v;
drivers/power/supply/smb347-charger.c
1031
ret = regmap_read(smb->regmap, STAT_A, &v);
drivers/power/supply/smb347-charger.c
1035
v &= STAT_A_FLOAT_VOLTAGE_MASK;
drivers/power/supply/smb347-charger.c
1036
if (v > 0x3d)
drivers/power/supply/smb347-charger.c
1037
v = 0x3d;
drivers/power/supply/smb347-charger.c
1039
intval = 3500000 + v * 20000;
drivers/power/supply/smb347-charger.c
994
unsigned int v;
drivers/power/supply/smb347-charger.c
999
ret = regmap_read(smb->regmap, STAT_B, &v);
drivers/power/supply/twl4030_charger.c
402
int v, curr;
drivers/power/supply/twl4030_charger.c
409
v = 0;
drivers/power/supply/twl4030_charger.c
412
v = res * 6843;
drivers/power/supply/twl4030_charger.c
415
dev_dbg(bci->dev, "v=%d cur=%d limit=%d target=%d\n", v, curr,
drivers/power/supply/twl4030_charger.c
418
if (v < USB_MIN_VOLT) {
drivers/powercap/intel_rapl_common.c
1934
#define RAPL_EVENT_ATTR_STR(_name, v, str) \
drivers/powercap/intel_rapl_common.c
1935
static struct perf_pmu_events_attr event_attr_##v = { \
drivers/ptp/ptp_ines.c
104
#define ines_write32(s, v, r) __raw_writel(v, (void __iomem *)&s->regs->r)
drivers/ptp/ptp_netc.c
129
#define netc_timer_wr(p, o, v) netc_write((p)->base + (o), v)
drivers/ptp/ptp_netc.c
62
#define FIPER_CTRL_SET_PW(i, v) (((v) & GENMASK(4, 0)) << 8 * (i))
drivers/pwm/core.c
2697
static void *pwm_seq_next(struct seq_file *s, void *v, loff_t *pos)
drivers/pwm/core.c
2709
static void pwm_seq_stop(struct seq_file *s, void *v)
drivers/pwm/core.c
2714
static int pwm_seq_show(struct seq_file *s, void *v)
drivers/pwm/core.c
2716
struct pwm_chip *chip = v;
drivers/pwm/pwm-omap-dmtimer.c
317
u32 v;
drivers/pwm/pwm-omap-dmtimer.c
388
if (!of_property_read_u32(pdev->dev.of_node, "ti,prescaler", &v))
drivers/pwm/pwm-omap-dmtimer.c
389
omap->pdata->set_prescaler(omap->dm_timer, v);
drivers/pwm/pwm-omap-dmtimer.c
392
if (!of_property_read_u32(pdev->dev.of_node, "ti,clock-source", &v))
drivers/pwm/pwm-omap-dmtimer.c
393
omap->pdata->set_source(omap->dm_timer, v);
drivers/ras/cec.c
447
static int array_show(struct seq_file *m, void *v)
drivers/ras/debugfs.c
22
static int trace_show(struct seq_file *m, void *v)
drivers/regulator/max8998.c
233
static inline void buck1_gpio_set(struct gpio_desc *gpio1, struct gpio_desc *gpio2, int v)
drivers/regulator/max8998.c
235
gpiod_set_value(gpio1, v & 0x1);
drivers/regulator/max8998.c
236
gpiod_set_value(gpio2, (v >> 1) & 0x1);
drivers/regulator/max8998.c
239
static inline void buck2_gpio_set(struct gpio_desc *gpio, int v)
drivers/regulator/max8998.c
241
gpiod_set_value(gpio, v & 0x1);
drivers/regulator/max8998.c
637
unsigned int v;
drivers/regulator/max8998.c
697
for (v = 0; v < ARRAY_SIZE(pdata->buck1_voltage); ++v) {
drivers/regulator/max8998.c
703
< pdata->buck1_voltage[v])
drivers/regulator/max8998.c
706
max8998->buck1_vol[v] = i;
drivers/regulator/max8998.c
708
MAX8998_REG_BUCK1_VOLTAGE1 + v, i);
drivers/regulator/max8998.c
716
for (v = 0; v < ARRAY_SIZE(pdata->buck2_voltage); ++v) {
drivers/regulator/max8998.c
722
< pdata->buck2_voltage[v])
drivers/regulator/max8998.c
725
max8998->buck2_vol[v] = i;
drivers/regulator/max8998.c
727
MAX8998_REG_BUCK2_VOLTAGE1 + v, i);
drivers/regulator/s2dos05-regulator.c
35
#define BUCK_DESC(_name, _id, _ops, m, s, v, e, em, t, a) { \
drivers/regulator/s2dos05-regulator.c
47
.vsel_reg = v, \
drivers/regulator/s2dos05-regulator.c
58
#define LDO_DESC(_name, _id, _ops, m, s, v, e, em, t, a) { \
drivers/regulator/s2dos05-regulator.c
70
.vsel_reg = v, \
drivers/regulator/twl6030-regulator.c
71
#define TWL6030_CFG_STATE_APP(v) (((v) & TWL6030_CFG_STATE_APP_MASK) >>\
drivers/remoteproc/remoteproc_debugfs.c
283
struct fw_rsc_vdev *v;
drivers/remoteproc/remoteproc_debugfs.c
326
v = rsc;
drivers/remoteproc/remoteproc_debugfs.c
329
seq_printf(seq, " ID %d\n", v->id);
drivers/remoteproc/remoteproc_debugfs.c
330
seq_printf(seq, " Notify ID %d\n", v->notifyid);
drivers/remoteproc/remoteproc_debugfs.c
331
seq_printf(seq, " Device features 0x%x\n", v->dfeatures);
drivers/remoteproc/remoteproc_debugfs.c
332
seq_printf(seq, " Guest features 0x%x\n", v->gfeatures);
drivers/remoteproc/remoteproc_debugfs.c
333
seq_printf(seq, " Config length 0x%x\n", v->config_len);
drivers/remoteproc/remoteproc_debugfs.c
334
seq_printf(seq, " Status 0x%x\n", v->status);
drivers/remoteproc/remoteproc_debugfs.c
335
seq_printf(seq, " Number of vrings %d\n", v->num_of_vrings);
drivers/remoteproc/remoteproc_debugfs.c
337
v->reserved[0], v->reserved[1]);
drivers/remoteproc/remoteproc_debugfs.c
339
for (j = 0; j < v->num_of_vrings; j++) {
drivers/remoteproc/remoteproc_debugfs.c
341
seq_printf(seq, " Device Address 0x%x\n", v->vring[j].da);
drivers/remoteproc/remoteproc_debugfs.c
342
seq_printf(seq, " Alignment %d\n", v->vring[j].align);
drivers/remoteproc/remoteproc_debugfs.c
343
seq_printf(seq, " Number of buffers %d\n", v->vring[j].num);
drivers/remoteproc/remoteproc_debugfs.c
344
seq_printf(seq, " Notify ID %d\n", v->vring[j].notifyid);
drivers/remoteproc/remoteproc_debugfs.c
346
v->vring[j].pa);
drivers/rtc/rtc-da9052.c
104
uint8_t v[3];
drivers/rtc/rtc-da9052.c
124
v[0] = rtc_tm->tm_hour;
drivers/rtc/rtc-da9052.c
125
v[1] = rtc_tm->tm_mday;
drivers/rtc/rtc-da9052.c
126
v[2] = rtc_tm->tm_mon;
drivers/rtc/rtc-da9052.c
128
ret = da9052_group_write(da9052, DA9052_ALARM_H_REG, 3, v);
drivers/rtc/rtc-da9052.c
157
uint8_t v[2][6];
drivers/rtc/rtc-da9052.c
161
ret = da9052_group_read(rtc->da9052, DA9052_COUNT_S_REG, 6, &v[0][0]);
drivers/rtc/rtc-da9052.c
169
DA9052_COUNT_S_REG, 6, &v[idx][0]);
drivers/rtc/rtc-da9052.c
175
if (memcmp(&v[0][0], &v[1][0], 6) == 0) {
drivers/rtc/rtc-da9052.c
176
rtc_tm->tm_year = (v[0][5] & DA9052_RTC_YEAR) + 100;
drivers/rtc/rtc-da9052.c
177
rtc_tm->tm_mon = (v[0][4] & DA9052_RTC_MONTH) - 1;
drivers/rtc/rtc-da9052.c
178
rtc_tm->tm_mday = v[0][3] & DA9052_RTC_DAY;
drivers/rtc/rtc-da9052.c
179
rtc_tm->tm_hour = v[0][2] & DA9052_RTC_HOUR;
drivers/rtc/rtc-da9052.c
180
rtc_tm->tm_min = v[0][1] & DA9052_RTC_MIN;
drivers/rtc/rtc-da9052.c
181
rtc_tm->tm_sec = v[0][0] & DA9052_RTC_SEC;
drivers/rtc/rtc-da9052.c
199
uint8_t v[6];
drivers/rtc/rtc-da9052.c
208
v[0] = tm->tm_sec;
drivers/rtc/rtc-da9052.c
209
v[1] = tm->tm_min;
drivers/rtc/rtc-da9052.c
210
v[2] = tm->tm_hour;
drivers/rtc/rtc-da9052.c
211
v[3] = tm->tm_mday;
drivers/rtc/rtc-da9052.c
212
v[4] = tm->tm_mon + 1;
drivers/rtc/rtc-da9052.c
213
v[5] = tm->tm_year - 100;
drivers/rtc/rtc-da9052.c
215
ret = da9052_group_write(rtc->da9052, DA9052_COUNT_S_REG, 6, v);
drivers/rtc/rtc-da9052.c
59
uint8_t v[2][5];
drivers/rtc/rtc-da9052.c
63
ret = da9052_group_read(rtc->da9052, DA9052_ALARM_MI_REG, 5, &v[0][0]);
drivers/rtc/rtc-da9052.c
71
DA9052_ALARM_MI_REG, 5, &v[idx][0]);
drivers/rtc/rtc-da9052.c
77
if (memcmp(&v[0][0], &v[1][0], 5) == 0) {
drivers/rtc/rtc-da9052.c
78
rtc_tm->tm_year = (v[0][4] & DA9052_RTC_YEAR) + 100;
drivers/rtc/rtc-da9052.c
79
rtc_tm->tm_mon = (v[0][3] & DA9052_RTC_MONTH) - 1;
drivers/rtc/rtc-da9052.c
80
rtc_tm->tm_mday = v[0][2] & DA9052_RTC_DAY;
drivers/rtc/rtc-da9052.c
81
rtc_tm->tm_hour = v[0][1] & DA9052_RTC_HOUR;
drivers/rtc/rtc-da9052.c
82
rtc_tm->tm_min = v[0][0] & DA9052_RTC_MIN;
drivers/rtc/rtc-da9055.c
128
uint8_t v[6];
drivers/rtc/rtc-da9055.c
142
ret = da9055_group_read(rtc->da9055, DA9055_REG_COUNT_S, 6, v);
drivers/rtc/rtc-da9055.c
149
rtc_tm->tm_year = (v[5] & DA9055_RTC_YEAR) + 100;
drivers/rtc/rtc-da9055.c
150
rtc_tm->tm_mon = (v[4] & DA9055_RTC_MONTH) - 1;
drivers/rtc/rtc-da9055.c
151
rtc_tm->tm_mday = v[3] & DA9055_RTC_DAY;
drivers/rtc/rtc-da9055.c
152
rtc_tm->tm_hour = v[2] & DA9055_RTC_HOUR;
drivers/rtc/rtc-da9055.c
153
rtc_tm->tm_min = v[1] & DA9055_RTC_MIN;
drivers/rtc/rtc-da9055.c
154
rtc_tm->tm_sec = v[0] & DA9055_RTC_SEC;
drivers/rtc/rtc-da9055.c
162
uint8_t v[6];
drivers/rtc/rtc-da9055.c
166
v[0] = tm->tm_sec;
drivers/rtc/rtc-da9055.c
167
v[1] = tm->tm_min;
drivers/rtc/rtc-da9055.c
168
v[2] = tm->tm_hour;
drivers/rtc/rtc-da9055.c
169
v[3] = tm->tm_mday;
drivers/rtc/rtc-da9055.c
170
v[4] = tm->tm_mon + 1;
drivers/rtc/rtc-da9055.c
171
v[5] = tm->tm_year - 100;
drivers/rtc/rtc-da9055.c
173
return da9055_group_write(rtc->da9055, DA9055_REG_COUNT_S, 6, v);
drivers/rtc/rtc-da9055.c
59
uint8_t v[5];
drivers/rtc/rtc-da9055.c
61
ret = da9055_group_read(da9055, DA9055_REG_ALARM_MI, 5, v);
drivers/rtc/rtc-da9055.c
67
rtc_tm->tm_year = (v[4] & DA9055_RTC_ALM_YEAR) + 100;
drivers/rtc/rtc-da9055.c
68
rtc_tm->tm_mon = (v[3] & DA9055_RTC_ALM_MONTH) - 1;
drivers/rtc/rtc-da9055.c
69
rtc_tm->tm_mday = v[2] & DA9055_RTC_ALM_DAY;
drivers/rtc/rtc-da9055.c
70
rtc_tm->tm_hour = v[1] & DA9055_RTC_ALM_HOUR;
drivers/rtc/rtc-da9055.c
71
rtc_tm->tm_min = v[0] & DA9055_RTC_ALM_MIN;
drivers/rtc/rtc-da9055.c
80
uint8_t v[2];
drivers/rtc/rtc-da9055.c
92
v[0] = rtc_tm->tm_hour;
drivers/rtc/rtc-da9055.c
93
v[1] = rtc_tm->tm_mday;
drivers/rtc/rtc-da9055.c
95
ret = da9055_group_write(da9055, DA9055_REG_ALARM_H, 2, v);
drivers/rtc/rtc-isl12026.c
326
u8 *v = val;
drivers/rtc/rtc-isl12026.c
354
memcpy(payload + 2, v + num_written, chunk_size);
drivers/rtc/rtc-moxart.c
188
unsigned char v;
drivers/rtc/rtc-moxart.c
192
v = moxart_rtc_read_register(dev, GPIO_RTC_SECONDS_R);
drivers/rtc/rtc-moxart.c
193
tm->tm_sec = (((v & 0x70) >> 4) * 10) + (v & 0x0F);
drivers/rtc/rtc-moxart.c
195
v = moxart_rtc_read_register(dev, GPIO_RTC_MINUTES_R);
drivers/rtc/rtc-moxart.c
196
tm->tm_min = (((v & 0x70) >> 4) * 10) + (v & 0x0F);
drivers/rtc/rtc-moxart.c
198
v = moxart_rtc_read_register(dev, GPIO_RTC_HOURS_R);
drivers/rtc/rtc-moxart.c
199
if (v & 0x80) { /* 12-hour mode */
drivers/rtc/rtc-moxart.c
200
tm->tm_hour = (((v & 0x10) >> 4) * 10) + (v & 0x0F);
drivers/rtc/rtc-moxart.c
201
if (v & 0x20) { /* PM mode */
drivers/rtc/rtc-moxart.c
207
tm->tm_hour = (((v & 0x30) >> 4) * 10) + (v & 0x0F);
drivers/rtc/rtc-moxart.c
210
v = moxart_rtc_read_register(dev, GPIO_RTC_DATE_R);
drivers/rtc/rtc-moxart.c
211
tm->tm_mday = (((v & 0x30) >> 4) * 10) + (v & 0x0F);
drivers/rtc/rtc-moxart.c
213
v = moxart_rtc_read_register(dev, GPIO_RTC_MONTH_R);
drivers/rtc/rtc-moxart.c
214
tm->tm_mon = (((v & 0x10) >> 4) * 10) + (v & 0x0F);
drivers/rtc/rtc-moxart.c
217
v = moxart_rtc_read_register(dev, GPIO_RTC_YEAR_R);
drivers/rtc/rtc-moxart.c
218
tm->tm_year = (((v & 0xF0) >> 4) * 10) + (v & 0x0F);
drivers/rtc/rtc-moxart.c
223
v = moxart_rtc_read_register(dev, GPIO_RTC_DAY_R);
drivers/rtc/rtc-moxart.c
224
tm->tm_wday = (v & 0x0f) - 1;
drivers/rtc/rtc-pcf8583.c
44
#define set_ctrl(x, v) get_ctrl(x) = v
drivers/s390/block/dasd.c
1011
static int dasd_stats_show(struct seq_file *m, void *v)
drivers/s390/block/dasd.c
1106
static int dasd_hosts_show(struct seq_file *m, void *v)
drivers/s390/block/dasd_proc.c
112
static void *dasd_devices_next(struct seq_file *m, void *v, loff_t *pos)
drivers/s390/block/dasd_proc.c
118
static void dasd_devices_stop(struct seq_file *m, void *v)
drivers/s390/block/dasd_proc.c
192
static int dasd_stats_proc_show(struct seq_file *m, void *v)
drivers/s390/block/dasd_proc.c
31
dasd_devices_show(struct seq_file *m, void *v)
drivers/s390/block/dasd_proc.c
37
device = dasd_device_from_devindex((unsigned long) v - 1);
drivers/s390/char/raw3270.c
1231
struct raw3270_view *v;
drivers/s390/char/raw3270.c
1254
v = list_entry(rp->view_list.next, struct raw3270_view, list);
drivers/s390/char/raw3270.c
1255
if (v->fn->release)
drivers/s390/char/raw3270.c
1256
v->fn->release(v);
drivers/s390/char/raw3270.c
1258
raw3270_del_view(v);
drivers/s390/char/sclp.h
366
struct gds_vector *v;
drivers/s390/char/sclp.h
368
for (v = start; (void *) v < end; v = (void *) v + v->length)
drivers/s390/char/sclp.h
369
if (v->gds_id == id)
drivers/s390/char/sclp.h
370
return v;
drivers/s390/char/sclp_ocf.c
45
struct gds_vector *v;
drivers/s390/char/sclp_ocf.c
50
v = sclp_find_gds_vector(evbuf + 1, (void *) evbuf + evbuf->length,
drivers/s390/char/sclp_ocf.c
52
if (!v)
drivers/s390/char/sclp_ocf.c
55
v = sclp_find_gds_vector(v + 1, (void *) v + v->length, 0x9f22);
drivers/s390/char/sclp_ocf.c
56
if (!v)
drivers/s390/char/sclp_ocf.c
59
sv = sclp_find_gds_subvector(v + 1, (void *) v + v->length, 0x81);
drivers/s390/char/sclp_tty.c
429
static inline void sclp_eval_textcmd(struct gds_vector *v)
drivers/s390/char/sclp_tty.c
434
end = (void *) v + v->length;
drivers/s390/char/sclp_tty.c
435
for (sv = (struct gds_subvector *) (v + 1);
drivers/s390/char/sclp_tty.c
442
static inline void sclp_eval_cpmsu(struct gds_vector *v)
drivers/s390/char/sclp_tty.c
446
end = (void *) v + v->length;
drivers/s390/char/sclp_tty.c
447
for (v = v + 1; (void *) v < end; v = (void *) v + v->length)
drivers/s390/char/sclp_tty.c
448
if (v->gds_id == GDS_ID_TEXTCMD)
drivers/s390/char/sclp_tty.c
449
sclp_eval_textcmd(v);
drivers/s390/char/sclp_tty.c
453
static inline void sclp_eval_mdsmu(struct gds_vector *v)
drivers/s390/char/sclp_tty.c
455
v = sclp_find_gds_vector(v + 1, (void *) v + v->length, GDS_ID_CPMSU);
drivers/s390/char/sclp_tty.c
456
if (v)
drivers/s390/char/sclp_tty.c
457
sclp_eval_cpmsu(v);
drivers/s390/char/sclp_tty.c
462
struct gds_vector *v;
drivers/s390/char/sclp_tty.c
464
v = sclp_find_gds_vector(evbuf + 1, (void *) evbuf + evbuf->length,
drivers/s390/char/sclp_tty.c
466
if (v)
drivers/s390/char/sclp_tty.c
467
sclp_eval_mdsmu(v);
drivers/s390/char/tape_proc.c
38
static int tape_proc_show(struct seq_file *m, void *v)
drivers/s390/char/tape_proc.c
45
n = (unsigned long) v - 1;
drivers/s390/char/tape_proc.c
90
static void *tape_proc_next(struct seq_file *m, void *v, loff_t *pos)
drivers/s390/char/tape_proc.c
96
static void tape_proc_stop(struct seq_file *m, void *v)
drivers/s390/cio/qdio_debug.c
179
static int ssqd_show(struct seq_file *m, void *v)
drivers/s390/cio/qdio_debug.c
216
static int qperf_show(struct seq_file *m, void *v)
drivers/s390/cio/qdio_debug.c
98
static int qstat_show(struct seq_file *m, void *v)
drivers/s390/net/qeth_core_main.c
733
static int qeth_debugfs_local_addr_show(struct seq_file *m, void *v)
drivers/sbus/char/uctrl.c
322
int i, v;
drivers/sbus/char/uctrl.c
336
v = driver->status.external_status;
drivers/sbus/char/uctrl.c
337
for (i = 0; v != 0; i++, v >>= 1) {
drivers/sbus/char/uctrl.c
338
if (v & 1) {
drivers/scsi/advansys.c
3167
ASC_DVC_VAR *v;
drivers/scsi/advansys.c
3172
v = &boardp->dvc_var.asc_dvc_var;
drivers/scsi/advansys.c
3183
v->err_code);
drivers/scsi/advansys.c
3187
" Total Command Pending: %d\n", v->cur_total_qng);
drivers/scsi/advansys.c
3197
(v->use_tagged_qng & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
drivers/scsi/advansys.c
3207
seq_printf(m, " %X:%u", i, v->cur_dvc_qng[i]);
drivers/scsi/advansys.c
3217
seq_printf(m, " %X:%u", i, v->max_dvc_qng[i]);
drivers/scsi/advansys.c
3242
(v->sdtr_done & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
drivers/scsi/advansys.c
3251
((v->init_sdtr & ADV_TID_TO_TIDMASK(i)) == 0)) {
drivers/scsi/advansys.c
3261
(boardp->sdtr_data[i] >> 4) & (v->max_sdtr_index -
drivers/scsi/advansys.c
3266
v->sdtr_period_tbl[syn_period_ix],
drivers/scsi/advansys.c
3267
250 / v->sdtr_period_tbl[syn_period_ix],
drivers/scsi/advansys.c
3269
v->sdtr_period_tbl[syn_period_ix]));
drivers/scsi/advansys.c
3275
if ((v->sdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
drivers/scsi/advansys.c
3297
ADV_DVC_VAR *v;
drivers/scsi/advansys.c
3309
v = &boardp->dvc_var.adv_dvc_var;
drivers/scsi/advansys.c
3311
iop_base = v->iop_base;
drivers/scsi/advansys.c
3312
chip_scsi_id = v->chip_scsi_id;
drivers/scsi/advansys.c
3320
v->iop_base,
drivers/scsi/advansys.c
3322
v->err_code);
drivers/scsi/aha1542.h
66
static inline void any2scsi(u8 *p, u32 v)
drivers/scsi/aha1542.h
68
p[0] = v >> 16;
drivers/scsi/aha1542.h
69
p[1] = v >> 8;
drivers/scsi/aha1542.h
70
p[2] = v;
drivers/scsi/aic7xxx/aic7xxx_93cx6.c
154
uint16_t v;
drivers/scsi/aic7xxx/aic7xxx_93cx6.c
187
v = 0;
drivers/scsi/aic7xxx/aic7xxx_93cx6.c
191
v <<= 1;
drivers/scsi/aic7xxx/aic7xxx_93cx6.c
193
v |= 1;
drivers/scsi/aic7xxx/aic7xxx_93cx6.c
198
buf[k - start_addr] = v;
drivers/scsi/aic7xxx/aic7xxx_93cx6.c
225
uint16_t v;
drivers/scsi/aic7xxx/aic7xxx_93cx6.c
264
v = buf[k - start_addr];
drivers/scsi/aic7xxx/aic7xxx_93cx6.c
266
if ((v & (1 << i)) != 0)
drivers/scsi/aic7xxx/aic7xxx_93cx6.c
272
if ((v & (1 << i)) != 0)
drivers/scsi/aic7xxx/aiclib.h
143
#define GETID(v, s) (unsigned)(((v) >> (s)) & 0xFFFF ?: PCI_ANY_ID)
drivers/scsi/aic94xx/aic94xx_hwi.c
1259
u32 v = asd_read_reg_dword(asd_ha, LmCONTROL(phy_id));
drivers/scsi/aic94xx/aic94xx_hwi.c
1261
v |= LEDPOL;
drivers/scsi/aic94xx/aic94xx_hwi.c
1263
v &= ~LEDPOL;
drivers/scsi/aic94xx/aic94xx_hwi.c
1264
asd_write_reg_dword(asd_ha, LmCONTROL(phy_id), v);
drivers/scsi/aic94xx/aic94xx_hwi.c
1280
u32 v;
drivers/scsi/aic94xx/aic94xx_hwi.c
1282
v = asd_read_reg_dword(asd_ha, GPIOOER);
drivers/scsi/aic94xx/aic94xx_hwi.c
1284
v |= (1 << phy_id);
drivers/scsi/aic94xx/aic94xx_hwi.c
1286
v &= ~(1 << phy_id);
drivers/scsi/aic94xx/aic94xx_hwi.c
1287
asd_write_reg_dword(asd_ha, GPIOOER, v);
drivers/scsi/aic94xx/aic94xx_hwi.c
1289
v = asd_read_reg_dword(asd_ha, GPIOCNFGR);
drivers/scsi/aic94xx/aic94xx_hwi.c
1291
v |= (1 << phy_id);
drivers/scsi/aic94xx/aic94xx_hwi.c
1293
v &= ~(1 << phy_id);
drivers/scsi/aic94xx/aic94xx_hwi.c
1294
asd_write_reg_dword(asd_ha, GPIOCNFGR, v);
drivers/scsi/aic94xx/aic94xx_hwi.c
145
u32 v;
drivers/scsi/aic94xx/aic94xx_hwi.c
148
err = pci_read_config_dword(pcidev, PCI_CONF_MBAR_KEY, &v);
drivers/scsi/aic94xx/aic94xx_hwi.c
154
if (v)
drivers/scsi/aic94xx/aic94xx_hwi.c
155
err = pci_write_config_dword(pcidev, PCI_CONF_MBAR_KEY, v);
drivers/scsi/aic94xx/aic94xx_hwi.c
606
u32 v;
drivers/scsi/aic94xx/aic94xx_hwi.c
612
err = pci_read_config_dword(asd_ha->pcidev, PCIC_HSTPCIX_CNTRL, &v);
drivers/scsi/aic94xx/aic94xx_hwi.c
619
v | SC_TMR_DIS);
drivers/scsi/aic94xx/aic94xx_sds.c
299
u32 v;
drivers/scsi/aic94xx/aic94xx_sds.c
305
err = pci_read_config_dword(pcidev, PCIC_INTRPT_STAT, &v);
drivers/scsi/aic94xx/aic94xx_sds.c
314
"is 0x%x\n", v);
drivers/scsi/aic94xx/aic94xx_sds.c
316
if (v)
drivers/scsi/aic94xx/aic94xx_sds.c
318
PCIC_INTRPT_STAT, v);
drivers/scsi/aic94xx/aic94xx_sds.c
597
u32 v;
drivers/scsi/aic94xx/aic94xx_sds.c
598
for (v = 0; v < ASD_FLASH_SIZE; v += FLASH_NEXT_ENTRY_OFFS) {
drivers/scsi/aic94xx/aic94xx_sds.c
599
asd_read_flash_seg(asd_ha, flash_dir, v,
drivers/scsi/aic94xx/aic94xx_sds.c
603
asd_ha->hw_prof.flash.dir_offs = v;
drivers/scsi/aic94xx/aic94xx_sds.c
604
asd_read_flash_seg(asd_ha, flash_dir, v,
drivers/scsi/arm/cumana_1.c
41
#define L(v) (((v)<<16)|((v) & 0x0000ffff))
drivers/scsi/arm/cumana_1.c
42
#define H(v) (((v)>>16)|((v) & 0xffff0000))
drivers/scsi/arm/cumana_1.c
58
unsigned long v;
drivers/scsi/arm/cumana_1.c
64
v=*laddr++; writew(L(v), dma); writew(H(v), dma);
drivers/scsi/arm/cumana_1.c
65
v=*laddr++; writew(L(v), dma); writew(H(v), dma);
drivers/scsi/arm/cumana_1.c
66
v=*laddr++; writew(L(v), dma); writew(H(v), dma);
drivers/scsi/arm/cumana_1.c
67
v=*laddr++; writew(L(v), dma); writew(H(v), dma);
drivers/scsi/arm/cumana_1.c
68
v=*laddr++; writew(L(v), dma); writew(H(v), dma);
drivers/scsi/arm/cumana_1.c
69
v=*laddr++; writew(L(v), dma); writew(H(v), dma);
drivers/scsi/arm/cumana_1.c
70
v=*laddr++; writew(L(v), dma); writew(H(v), dma);
drivers/scsi/arm/cumana_1.c
71
v=*laddr++; writew(L(v), dma); writew(H(v), dma);
drivers/scsi/atari_scsi.c
85
unsigned long v = val; \
drivers/scsi/atari_scsi.c
86
tt_scsi_dma.elt##_lo = v & 0xff; \
drivers/scsi/atari_scsi.c
87
v >>= 8; \
drivers/scsi/atari_scsi.c
88
tt_scsi_dma.elt##_lmd = v & 0xff; \
drivers/scsi/atari_scsi.c
89
v >>= 8; \
drivers/scsi/atari_scsi.c
90
tt_scsi_dma.elt##_hmd = v & 0xff; \
drivers/scsi/atari_scsi.c
91
v >>= 8; \
drivers/scsi/atari_scsi.c
92
tt_scsi_dma.elt##_hi = v & 0xff; \
drivers/scsi/csiostor/csio_hw.c
261
csio_hw_get_vpd_keyword_val(const struct t4_vpd_hdr *v, const char *kw)
drivers/scsi/csiostor/csio_hw.c
265
const uint8_t *buf = &v->id_tag;
drivers/scsi/csiostor/csio_hw.c
266
const uint8_t *vpdr_len = &v->vpdr_tag;
drivers/scsi/csiostor/csio_hw.c
307
const struct t4_vpd_hdr *v;
drivers/scsi/csiostor/csio_hw.c
3158
uint64_t v;
drivers/scsi/csiostor/csio_hw.c
3186
v = (uint64_t)csio_rd_reg32(hw, SGE_INT_CAUSE1_A) |
drivers/scsi/csiostor/csio_hw.c
3188
if (v) {
drivers/scsi/csiostor/csio_hw.c
3190
(unsigned long long)v);
drivers/scsi/csiostor/csio_hw.c
3191
csio_wr_reg32(hw, (uint32_t)(v & 0xFFFFFFFF),
drivers/scsi/csiostor/csio_hw.c
3193
csio_wr_reg32(hw, (uint32_t)(v >> 32), SGE_INT_CAUSE2_A);
drivers/scsi/csiostor/csio_hw.c
3196
v |= csio_handle_intr_status(hw, SGE_INT_CAUSE3_A, sge_intr_info);
drivers/scsi/csiostor/csio_hw.c
3199
v != 0)
drivers/scsi/csiostor/csio_hw.c
341
v = (const struct t4_vpd_hdr *)vpd;
drivers/scsi/csiostor/csio_hw.c
344
var = csio_hw_get_vpd_keyword_val(v, name); \
drivers/scsi/csiostor/csio_hw.c
3475
unsigned int addr, cnt_addr, v;
drivers/scsi/csiostor/csio_hw.c
3485
v = csio_rd_reg32(hw, addr) & MEM_INT_MASK;
drivers/scsi/csiostor/csio_hw.c
3486
if (v & PERR_INT_CAUSE_F)
drivers/scsi/csiostor/csio_hw.c
3488
if (v & ECC_CE_INT_CAUSE_F) {
drivers/scsi/csiostor/csio_hw.c
3495
if (v & ECC_UE_INT_CAUSE_F)
drivers/scsi/csiostor/csio_hw.c
3498
csio_wr_reg32(hw, v, addr);
drivers/scsi/csiostor/csio_hw.c
3499
if (v & (PERR_INT_CAUSE_F | ECC_UE_INT_CAUSE_F))
drivers/scsi/csiostor/csio_hw.c
3508
uint32_t v, status = csio_rd_reg32(hw, MA_INT_CAUSE_A);
drivers/scsi/csiostor/csio_hw.c
3514
v = csio_rd_reg32(hw, MA_INT_WRAP_STATUS_A);
drivers/scsi/csiostor/csio_hw.c
3517
MEM_WRAP_CLIENT_NUM_G(v), MEM_WRAP_ADDRESS_G(v) << 4);
drivers/scsi/csiostor/csio_hw.c
3561
uint32_t v = csio_rd_reg32(hw, T5_PORT_REG(port, MAC_PORT_INT_CAUSE_A));
drivers/scsi/csiostor/csio_hw.c
3563
v &= TXFIFO_PRTY_ERR_F | RXFIFO_PRTY_ERR_F;
drivers/scsi/csiostor/csio_hw.c
3564
if (!v)
drivers/scsi/csiostor/csio_hw.c
3567
if (v & TXFIFO_PRTY_ERR_F)
drivers/scsi/csiostor/csio_hw.c
3569
if (v & RXFIFO_PRTY_ERR_F)
drivers/scsi/csiostor/csio_hw.c
3571
csio_wr_reg32(hw, v, T5_PORT_REG(port, MAC_PORT_INT_CAUSE_A));
drivers/scsi/csiostor/csio_hw.c
365
memcpy(p->id, v->id_data, ID_LEN);
drivers/scsi/elx/libefc_sli/sli4.h
3000
#define GET_Q_CREATE_VERSION(v) \
drivers/scsi/elx/libefc_sli/sli4.h
3001
(((v) & SLI4_PARAM_QV_MASK) >> SLI4_PARAM_QV_SHIFT)
drivers/scsi/fcoe/fcoe_sysfs.c
406
unsigned long v;
drivers/scsi/fcoe/fcoe_sysfs.c
408
err = kstrtoul(buf, 10, &v);
drivers/scsi/fcoe/fcoe_sysfs.c
409
if (err || v > UINT_MAX)
drivers/scsi/fcoe/fcoe_sysfs.c
412
*var = v;
drivers/scsi/imm.c
647
unsigned char r, v;
drivers/scsi/imm.c
650
v = cmd->cmnd[0];
drivers/scsi/imm.c
651
bulk = ((v == READ_6) ||
drivers/scsi/imm.c
652
(v == READ_10) || (v == WRITE_6) || (v == WRITE_10));
drivers/scsi/ips.c
222
#define DEBUG_VAR(i, s, v...) if (ips_debug >= i) printk(KERN_NOTICE s "\n", v);
drivers/scsi/ips.c
226
#define DEBUG_VAR(i, s, v...)
drivers/scsi/megaraid.c
2043
proc_show_config(struct seq_file *m, void *v)
drivers/scsi/megaraid.c
2107
proc_show_stat(struct seq_file *m, void *v)
drivers/scsi/megaraid.c
2142
proc_show_mbox(struct seq_file *m, void *v)
drivers/scsi/megaraid.c
2169
proc_show_rebuild_rate(struct seq_file *m, void *v)
drivers/scsi/megaraid.c
2212
proc_show_battery(struct seq_file *m, void *v)
drivers/scsi/megaraid.c
2432
proc_show_pdrv_ch0(struct seq_file *m, void *v)
drivers/scsi/megaraid.c
2446
proc_show_pdrv_ch1(struct seq_file *m, void *v)
drivers/scsi/megaraid.c
2460
proc_show_pdrv_ch2(struct seq_file *m, void *v)
drivers/scsi/megaraid.c
2474
proc_show_pdrv_ch3(struct seq_file *m, void *v)
drivers/scsi/megaraid.c
2673
proc_show_rdrv_10(struct seq_file *m, void *v)
drivers/scsi/megaraid.c
2687
proc_show_rdrv_20(struct seq_file *m, void *v)
drivers/scsi/megaraid.c
2701
proc_show_rdrv_30(struct seq_file *m, void *v)
drivers/scsi/megaraid.c
2715
proc_show_rdrv_40(struct seq_file *m, void *v)
drivers/scsi/mesh.c
636
int v, tr;
drivers/scsi/mesh.c
652
v = (ms->clk_freq / 5000) * period;
drivers/scsi/mesh.c
653
if (v <= 250000) {
drivers/scsi/mesh.c
655
v = 0;
drivers/scsi/mesh.c
660
v = (v + 99999) / 100000 - 2;
drivers/scsi/mesh.c
661
if (v > 15)
drivers/scsi/mesh.c
662
v = 15; /* oops */
drivers/scsi/mesh.c
663
tr = ((ms->clk_freq / (v + 2)) + 199999) / 200000;
drivers/scsi/mesh.c
667
tp->sync_params = SYNC_PARAMS(offset, v);
drivers/scsi/mvme16x_scsi.c
113
volatile unsigned long v;
drivers/scsi/mvme16x_scsi.c
115
v = in_be32(0xfff4202c);
drivers/scsi/mvme16x_scsi.c
116
v &= ~0x10;
drivers/scsi/mvme16x_scsi.c
117
out_be32(0xfff4202c, v);
drivers/scsi/mvme16x_scsi.c
85
volatile unsigned long v;
drivers/scsi/mvme16x_scsi.c
88
v = in_be32(0xfff4202c);
drivers/scsi/mvme16x_scsi.c
89
v = (v & ~0xff) | 0x10 | 4;
drivers/scsi/mvme16x_scsi.c
90
out_be32(0xfff4202c, v);
drivers/scsi/mvsas/mv_94xx.c
168
phy_cfg_tmp.v = mvs_read_port_vsr_data(mvi, phy_id);
drivers/scsi/mvsas/mv_94xx.c
169
phy_cfg.v = 0;
drivers/scsi/mvsas/mv_94xx.c
200
mvs_write_port_vsr_data(mvi, phy_id, phy_cfg.v);
drivers/scsi/mvsas/mv_94xx.h
173
u32 v;
drivers/scsi/mvsas/mv_94xx.h
317
mv_ffc64(u64 v)
drivers/scsi/mvsas/mv_94xx.h
319
u64 x = ~v;
drivers/scsi/mvumi.c
913
void *virmem, *v;
drivers/scsi/mvumi.c
935
v = res_mgnt->virt_addr;
drivers/scsi/mvumi.c
939
v += offset;
drivers/scsi/mvumi.c
940
mhba->ib_list = v;
drivers/scsi/mvumi.c
943
v += sizeof(struct mvumi_dyn_list_entry) * mhba->max_io;
drivers/scsi/mvumi.c
945
mhba->ib_frame = v;
drivers/scsi/mvumi.c
948
v += mhba->ib_max_size * mhba->max_io;
drivers/scsi/mvumi.c
954
v += offset;
drivers/scsi/mvumi.c
955
mhba->ib_shadow = v;
drivers/scsi/mvumi.c
958
v += sizeof(u32)*2;
drivers/scsi/mvumi.c
963
v += offset;
drivers/scsi/mvumi.c
964
mhba->ob_shadow = v;
drivers/scsi/mvumi.c
967
v += 8;
drivers/scsi/mvumi.c
971
v += offset;
drivers/scsi/mvumi.c
972
mhba->ob_shadow = v;
drivers/scsi/mvumi.c
975
v += 4;
drivers/scsi/mvumi.c
981
v += offset;
drivers/scsi/mvumi.c
983
mhba->ob_list = v;
drivers/scsi/ncr53c8xx.c
793
int c, h, t, u, v;
drivers/scsi/ncr53c8xx.c
801
v = simple_strtoul(p, &ep, 0);
drivers/scsi/ncr53c8xx.c
810
t = (target == v) ? v : NO_TARGET;
drivers/scsi/ncr53c8xx.c
815
u = (lun == v) ? v : NO_LUN;
drivers/scsi/ncr53c8xx.c
821
return v;
drivers/scsi/ncr53c8xx.h
442
#define OUTL_DSP(v) \
drivers/scsi/ncr53c8xx.h
445
OUTL (nc_dsp, (v)); \
drivers/scsi/ppa.c
551
unsigned char r, v;
drivers/scsi/ppa.c
554
v = cmd->cmnd[0];
drivers/scsi/ppa.c
555
bulk = ((v == READ_6) ||
drivers/scsi/ppa.c
556
(v == READ_10) || (v == WRITE_6) || (v == WRITE_10));
drivers/scsi/qla2xxx/qla_edif.c
2781
qla28xx_sa_update_iocb_entry(scsi_qla_host_t *v, struct req_que *req,
drivers/scsi/qla2xxx/qla_edif.c
2791
sp = qla2x00_get_sp_from_handle(v, func, req, pkt);
drivers/scsi/qla2xxx/qla_edif.c
2794
ql_dbg(ql_dbg_edif, v, 0x3063,
drivers/scsi/qla2xxx/qla_inline.h
465
static void qla_atomic_dtz(atomic_t *v, int amount)
drivers/scsi/qla2xxx/qla_inline.h
469
c = atomic_read(v);
drivers/scsi/qla2xxx/qla_inline.h
475
old = atomic_cmpxchg((v), c, dec);
drivers/scsi/qla2xxx/qla_isr.c
2309
qla24xx_els_ct_entry(scsi_qla_host_t *v, struct req_que *req,
drivers/scsi/qla2xxx/qla_isr.c
2326
sp = qla2x00_get_sp_from_handle(v, func, req, pkt);
drivers/scsi/qla2xxx/qla_target.c
2841
uint32_t v;
drivers/scsi/qla2xxx/qla_target.c
2843
v = get_unaligned_be32(
drivers/scsi/qla2xxx/qla_target.c
2845
put_unaligned_le32(v,
drivers/scsi/qla2xxx/qla_tmpl.c
883
uint8_t v[] = { 0, 0, 0, 0, 0, 0 };
drivers/scsi/qla2xxx/qla_tmpl.c
887
v + 0, v + 1, v + 2, v + 3) != 4);
drivers/scsi/qla2xxx/qla_tmpl.c
890
v[3] << 24 | v[2] << 16 | v[1] << 8 | v[0]);
drivers/scsi/qla2xxx/qla_tmpl.c
891
tmp->driver_info[1] = cpu_to_le32(v[5] << 8 | v[4]);
drivers/scsi/qla4xxx/ql4_def.h
177
#define SET_BITVAL(o, n, v) { \
drivers/scsi/qla4xxx/ql4_def.h
179
n |= v; \
drivers/scsi/qla4xxx/ql4_def.h
181
n &= ~v; \
drivers/scsi/scsi_debug.c
7894
bool v;
drivers/scsi/scsi_debug.c
7896
if (kstrtobool(buf, &v))
drivers/scsi/scsi_debug.c
7899
sdebug_per_host_store = v;
drivers/scsi/scsi_debug.c
8058
bool v;
drivers/scsi/scsi_debug.c
8060
if (kstrtobool(buf, &v))
drivers/scsi/scsi_debug.c
8063
sdebug_no_rwlock = v;
drivers/scsi/scsi_debug.c
8274
bool v;
drivers/scsi/scsi_debug.c
8276
if (kstrtobool(buf, &v))
drivers/scsi/scsi_debug.c
8279
sdebug_random = v;
drivers/scsi/scsi_devinfo.c
598
static int devinfo_seq_show(struct seq_file *m, void *v)
drivers/scsi/scsi_devinfo.c
600
struct double_list *dl = v;
drivers/scsi/scsi_devinfo.c
637
static void *devinfo_seq_next(struct seq_file *m, void *v, loff_t *ppos)
drivers/scsi/scsi_devinfo.c
639
struct double_list *dl = v;
drivers/scsi/scsi_devinfo.c
660
static void devinfo_seq_stop(struct seq_file *m, void *v)
drivers/scsi/scsi_devinfo.c
662
kfree(v);
drivers/scsi/scsi_ioctl.c
235
struct scsi_idlun v = {
drivers/scsi/scsi_ioctl.c
242
if (copy_to_user(argp, &v, sizeof(struct scsi_idlun)))
drivers/scsi/scsi_proc.c
495
static void *scsi_seq_next(struct seq_file *sfile, void *v, loff_t *pos)
drivers/scsi/scsi_proc.c
499
return next_scsi_device(v);
drivers/scsi/scsi_proc.c
502
static void scsi_seq_stop(struct seq_file *sfile, void *v)
drivers/scsi/scsi_proc.c
504
put_device(v);
drivers/scsi/scsi_proc.c
89
static int proc_scsi_show(struct seq_file *m, void *v)
drivers/scsi/scsi_sysfs.c
1224
bool v;
drivers/scsi/scsi_sysfs.c
1226
if (kstrtobool(buf, &v))
drivers/scsi/scsi_sysfs.c
1229
ret = scsi_cdl_enable(to_scsi_device(dev), v);
drivers/scsi/sd.c
298
bool v;
drivers/scsi/sd.c
303
if (kstrtobool(buf, &v))
drivers/scsi/sd.c
306
sdp->manage_system_start_stop = v;
drivers/scsi/sd.c
329
bool v;
drivers/scsi/sd.c
334
if (kstrtobool(buf, &v))
drivers/scsi/sd.c
337
sdp->manage_runtime_start_stop = v;
drivers/scsi/sd.c
358
bool v;
drivers/scsi/sd.c
363
if (kstrtobool(buf, &v))
drivers/scsi/sd.c
366
sdp->manage_shutdown = v;
drivers/scsi/sd.c
387
bool v;
drivers/scsi/sd.c
392
if (kstrtobool(buf, &v))
drivers/scsi/sd.c
395
sdp->manage_restart = v;
drivers/scsi/sd.c
413
bool v;
drivers/scsi/sd.c
423
if (kstrtobool(buf, &v))
drivers/scsi/sd.c
426
sdp->allow_restart = v;
drivers/scsi/sg.c
2314
static int sg_proc_seq_show_int(struct seq_file *s, void *v);
drivers/scsi/sg.c
2338
static int sg_proc_seq_show_version(struct seq_file *s, void *v);
drivers/scsi/sg.c
2339
static int sg_proc_seq_show_devhdr(struct seq_file *s, void *v);
drivers/scsi/sg.c
2340
static int sg_proc_seq_show_dev(struct seq_file *s, void *v);
drivers/scsi/sg.c
2342
static void * dev_seq_next(struct seq_file *s, void *v, loff_t *pos);
drivers/scsi/sg.c
2343
static void dev_seq_stop(struct seq_file *s, void *v);
drivers/scsi/sg.c
2351
static int sg_proc_seq_show_devstrs(struct seq_file *s, void *v);
drivers/scsi/sg.c
2359
static int sg_proc_seq_show_debug(struct seq_file *s, void *v);
drivers/scsi/sg.c
2387
static int sg_proc_seq_show_int(struct seq_file *s, void *v)
drivers/scsi/sg.c
2439
static int sg_proc_seq_show_version(struct seq_file *s, void *v)
drivers/scsi/sg.c
2446
static int sg_proc_seq_show_devhdr(struct seq_file *s, void *v)
drivers/scsi/sg.c
2472
static void * dev_seq_next(struct seq_file *s, void *v, loff_t *pos)
drivers/scsi/sg.c
2480
static void dev_seq_stop(struct seq_file *s, void *v)
drivers/scsi/sg.c
2485
static int sg_proc_seq_show_dev(struct seq_file *s, void *v)
drivers/scsi/sg.c
2487
struct sg_proc_deviter * it = (struct sg_proc_deviter *) v;
drivers/scsi/sg.c
2511
static int sg_proc_seq_show_devstrs(struct seq_file *s, void *v)
drivers/scsi/sg.c
2513
struct sg_proc_deviter * it = (struct sg_proc_deviter *) v;
drivers/scsi/sg.c
2598
static int sg_proc_seq_show_debug(struct seq_file *s, void *v)
drivers/scsi/sg.c
2600
struct sg_proc_deviter * it = (struct sg_proc_deviter *) v;
drivers/scsi/sg.c
976
sg_scsi_id_t v;
drivers/scsi/sg.c
980
memset(&v, 0, sizeof(v));
drivers/scsi/sg.c
981
v.host_no = sdp->device->host->host_no;
drivers/scsi/sg.c
982
v.channel = sdp->device->channel;
drivers/scsi/sg.c
983
v.scsi_id = sdp->device->id;
drivers/scsi/sg.c
984
v.lun = sdp->device->lun;
drivers/scsi/sg.c
985
v.scsi_type = sdp->device->type;
drivers/scsi/sg.c
986
v.h_cmd_per_lun = sdp->device->host->cmd_per_lun;
drivers/scsi/sg.c
987
v.d_queue_depth = sdp->device->queue_depth;
drivers/scsi/sg.c
988
if (copy_to_user(p, &v, sizeof(sg_scsi_id_t)))
drivers/scsi/snic/snic_ctl.c
47
int v[4] = {0};
drivers/scsi/snic/snic_ctl.c
65
v[i] = v[i] * 10 + (c - '0');
drivers/scsi/snic/snic_ctl.c
70
if (v[i] > 0xff)
drivers/scsi/snic/snic_ctl.c
73
x |= (v[0] << 24) | v[1] << 16 | v[2] << 8 | v[3];
drivers/scsi/sym53c8xx_2/sym_glue.c
1055
#define GET_INT_ARG(ptr, len, v) \
drivers/scsi/sym53c8xx_2/sym_glue.c
1056
if (!(arg_len = get_int_arg(ptr, len, &(v)))) \
drivers/scsi/sym53c8xx_2/sym_hipd.c
4361
#define sym_printk(lvl, tp, cp, fmt, v...) do { \
drivers/scsi/sym53c8xx_2/sym_hipd.c
4363
scmd_printk(lvl, cp->cmd, fmt, ##v); \
drivers/scsi/sym53c8xx_2/sym_hipd.c
4365
starget_printk(lvl, tp->starget, fmt, ##v); \
drivers/scsi/sym53c8xx_2/sym_hipd.h
196
#define OUTB(np, r, v) OUTB_OFF(np, offsetof(struct sym_reg, r), (v))
drivers/scsi/sym53c8xx_2/sym_hipd.h
197
#define OUTW(np, r, v) OUTW_OFF(np, offsetof(struct sym_reg, r), (v))
drivers/scsi/sym53c8xx_2/sym_hipd.h
198
#define OUTL(np, r, v) OUTL_OFF(np, offsetof(struct sym_reg, r), (v))
drivers/scsi/sym53c8xx_2/sym_hipd.h
212
#define OUTL_DSP(np, v) \
drivers/scsi/sym53c8xx_2/sym_hipd.h
215
OUTL(np, nc_dsp, (v)); \
drivers/soc/fsl/dpio/qbman-portal.c
462
u8 *v = cmd;
drivers/soc/fsl/dpio/qbman-portal.c
466
*v = cmd_verb | p->mc.valid_bit;
drivers/soc/fsl/dpio/qbman-portal.c
468
*v = cmd_verb | p->mc.valid_bit;
drivers/soc/fsl/qbman/bman_ccsr.c
91
u32 v = bm_ccsr_in(REG_IP_REV_1);
drivers/soc/fsl/qbman/bman_ccsr.c
92
*id = (v >> 16);
drivers/soc/fsl/qbman/bman_ccsr.c
93
*major = (v >> 8) & 0xff;
drivers/soc/fsl/qbman/bman_ccsr.c
94
*minor = v & 0xff;
drivers/soc/fsl/qbman/qman.c
2639
static int _qm_mr_consume_and_match_verb(struct qm_portal *p, int v)
drivers/soc/fsl/qbman/qman.c
2647
if ((msg->verb & QM_MR_VERB_TYPE_MASK) == v)
drivers/soc/fsl/qbman/qman_ccsr.c
337
u32 v = qm_ccsr_in(REG_IP_REV_1);
drivers/soc/fsl/qbman/qman_ccsr.c
338
*id = (v >> 16);
drivers/soc/fsl/qbman/qman_ccsr.c
339
*major = (v >> 8) & 0xff;
drivers/soc/fsl/qbman/qman_ccsr.c
340
*minor = v & 0xff;
drivers/soc/fsl/qbman/qman_ccsr.c
94
#define MCR_get_rslt(v) (u8)((v) >> 24)
drivers/soc/fsl/qbman/qman_priv.h
246
#define QM_SDQCR_TOKEN_SET(v) (((v) & 0xff) << 16)
drivers/soc/fsl/qbman/qman_priv.h
247
#define QM_SDQCR_TOKEN_GET(v) (((v) >> 16) & 0xff)
drivers/soc/mediatek/mtk-svs.c
761
static int svs_enable_debug_show(struct seq_file *m, void *v)
drivers/soc/mediatek/mtk-svs.c
816
static int svs_status_debug_show(struct seq_file *m, void *v)
drivers/soc/qcom/ice.c
36
#define QCOM_ICE_HWKM_WRAPPED_KEY_SIZE(v) ((v) == QCOM_ICE_HWKM_V1 ? 68 : 100)
drivers/soc/qcom/ice.c
83
#define QCOM_ICE_HWKM_CRYPTO_BIST_DONE(v) (((v) == QCOM_ICE_HWKM_V1) ? BIT(14) : BIT(7))
drivers/soc/qcom/ice.c
84
#define QCOM_ICE_HWKM_BIST_DONE(v) (((v) == QCOM_ICE_HWKM_V1) ? BIT(16) : BIT(9))
drivers/soc/qcom/rpmh-rsc.c
853
unsigned long action, void *v)
drivers/soc/qcom/rpmh-rsc.c
935
unsigned long action, void *v)
drivers/soc/samsung/exynos-pmu.c
366
unsigned long action, void *v)
drivers/soc/samsung/exynos-pmu.c
389
unsigned long event, void *v)
drivers/soc/ti/knav_dma.c
147
u32 v = 0;
drivers/soc/ti/knav_dma.c
152
v |= DMA_TX_FILT_PSWORDS;
drivers/soc/ti/knav_dma.c
154
v |= DMA_TX_FILT_EINFO;
drivers/soc/ti/knav_dma.c
155
writel_relaxed(v, &chan->reg_chan->mode);
drivers/soc/ti/knav_dma.c
163
v = 0;
drivers/soc/ti/knav_dma.c
166
v |= CHAN_HAS_EPIB;
drivers/soc/ti/knav_dma.c
168
v |= CHAN_HAS_PSINFO;
drivers/soc/ti/knav_dma.c
170
v |= CHAN_ERR_RETRY;
drivers/soc/ti/knav_dma.c
171
v |= (cfg->u.rx.desc_type & DESC_TYPE_MASK) << DESC_TYPE_SHIFT;
drivers/soc/ti/knav_dma.c
173
v |= CHAN_PSINFO_AT_SOP;
drivers/soc/ti/knav_dma.c
174
v |= (cfg->u.rx.sop_offset & CHAN_SOP_OFF_MASK)
drivers/soc/ti/knav_dma.c
176
v |= cfg->u.rx.dst_q & CHAN_QNUM_MASK;
drivers/soc/ti/knav_dma.c
178
writel_relaxed(v, &chan->reg_rx_flow->control);
drivers/soc/ti/knav_dma.c
182
v = cfg->u.rx.fdq[0] << 16;
drivers/soc/ti/knav_dma.c
183
v |= cfg->u.rx.fdq[1] & CHAN_QNUM_MASK;
drivers/soc/ti/knav_dma.c
184
writel_relaxed(v, &chan->reg_rx_flow->fdq_sel[0]);
drivers/soc/ti/knav_dma.c
186
v = cfg->u.rx.fdq[2] << 16;
drivers/soc/ti/knav_dma.c
187
v |= cfg->u.rx.fdq[3] & CHAN_QNUM_MASK;
drivers/soc/ti/knav_dma.c
188
writel_relaxed(v, &chan->reg_rx_flow->fdq_sel[1]);
drivers/soc/ti/knav_dma.c
269
unsigned v;
drivers/soc/ti/knav_dma.c
273
v = dma->loopback ? DMA_LOOPBACK : 0;
drivers/soc/ti/knav_dma.c
274
writel_relaxed(v, &dma->reg_global->emulation_control);
drivers/soc/ti/knav_dma.c
276
v = readl_relaxed(&dma->reg_global->perf_control);
drivers/soc/ti/knav_dma.c
277
v |= ((dma->rx_timeout & DMA_RX_TIMEOUT_MASK) << DMA_RX_TIMEOUT_SHIFT);
drivers/soc/ti/knav_dma.c
278
writel_relaxed(v, &dma->reg_global->perf_control);
drivers/soc/ti/knav_dma.c
280
v = ((dma->tx_priority << DMA_TX_PRIO_SHIFT) |
drivers/soc/ti/knav_dma.c
283
writel_relaxed(v, &dma->reg_global->priority_control);
drivers/soc/ti/knav_dma.c
298
unsigned v;
drivers/soc/ti/knav_dma.c
301
v = ~DMA_ENABLE & REG_MASK;
drivers/soc/ti/knav_dma.c
304
writel_relaxed(v, &dma->reg_rx_chan[i].control);
drivers/soc/ti/knav_dma.c
307
writel_relaxed(v, &dma->reg_tx_chan[i].control);
drivers/soc/ti/knav_dma.c
350
static int knav_dma_debug_show(struct seq_file *s, void *v)
drivers/soc/ti/knav_qmss_queue.c
465
static int knav_queue_debug_show(struct seq_file *s, void *v)
drivers/spi/spi-altera-dfl.c
109
u64 v;
drivers/spi/spi-altera-dfl.c
111
v = readq(base + SPI_CORE_PARAMETER);
drivers/spi/spi-altera-dfl.c
114
if (FIELD_GET(CLK_POLARITY, v))
drivers/spi/spi-altera-dfl.c
116
if (FIELD_GET(CLK_PHASE, v))
drivers/spi/spi-altera-dfl.c
119
host->num_chipselect = FIELD_GET(NUM_CHIPSELECT, v);
drivers/spi/spi-altera-dfl.c
121
SPI_BPW_RANGE_MASK(1, FIELD_GET(DATA_WIDTH, v));
drivers/spi/spi-altera-dfl.c
54
u64 v;
drivers/spi/spi-altera-dfl.c
68
v = readq(base + INDIRECT_RD_DATA);
drivers/spi/spi-altera-dfl.c
70
*val = v & INDIRECT_DATA_MASK;
drivers/spi/spi-cavium.c
118
u64 v = readq(p->register_base + OCTEON_SPI_DAT0(p) + (8 * i));
drivers/spi/spi-cavium.c
119
*rx_buf++ = (u8)v;
drivers/spi/spi-cavium.c
90
u64 v = readq(p->register_base + OCTEON_SPI_DAT0(p) + (8 * i));
drivers/spi/spi-cavium.c
91
*rx_buf++ = (u8)v;
drivers/spi/spi-davinci.c
240
u32 v = ioread32(addr);
drivers/spi/spi-davinci.c
242
v |= bits;
drivers/spi/spi-davinci.c
243
iowrite32(v, addr);
drivers/spi/spi-davinci.c
248
u32 v = ioread32(addr);
drivers/spi/spi-davinci.c
250
v &= ~bits;
drivers/spi/spi-davinci.c
251
iowrite32(v, addr);
drivers/spi/spi-mxic.c
159
#define IDLY_CODE_VAL(x, v) ((v) << (((x) % 4) * 8))
drivers/spi/spi-pic32.c
192
__type v; \
drivers/spi/spi-pic32.c
195
v = read##__bwl(&pic32s->regs->buf); \
drivers/spi/spi-pic32.c
197
*(__type *)(pic32s->rx) = v; \
drivers/spi/spi-pic32.c
204
__type v; \
drivers/spi/spi-pic32.c
207
v = (__type)~0U; \
drivers/spi/spi-pic32.c
209
v = *(__type *)(pic32s->tx); \
drivers/spi/spi-pic32.c
210
write##__bwl(v, &pic32s->regs->buf); \
drivers/spi/spi-pic32.c
391
u32 buswidth, v;
drivers/spi/spi-pic32.c
421
v = readl(&pic32s->regs->ctrl);
drivers/spi/spi-pic32.c
422
v &= ~(CTRL_BPW_MASK << CTRL_BPW_SHIFT);
drivers/spi/spi-pic32.c
423
v |= buswidth << CTRL_BPW_SHIFT;
drivers/spi/spi-pic32.c
424
writel(v, &pic32s->regs->ctrl);
drivers/spi/spi-s3c64xx.c
113
#define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \
drivers/spi/spi-s3c64xx.c
115
#define TX_FIFO_LVL(v, sdd) (((v) & (sdd)->tx_fifomask) >> \
drivers/spi/spi-s3c64xx.c
117
#define RX_FIFO_LVL(v, sdd) (((v) & (sdd)->rx_fifomask) >> \
drivers/spi/spi-xtensa-xtfpga.c
54
u32 v, u8 bits, unsigned flags)
drivers/spi/spi-xtensa-xtfpga.c
58
xspi->data = (xspi->data << bits) | (v & GENMASK(bits - 1, 0));
drivers/ssb/driver_pcicore.c
586
u32 v;
drivers/ssb/driver_pcicore.c
589
v = (1 << 30); /* Start of Transaction */
drivers/ssb/driver_pcicore.c
590
v |= (1 << 28); /* Write Transaction */
drivers/ssb/driver_pcicore.c
591
v |= (1 << 17); /* Turnaround */
drivers/ssb/driver_pcicore.c
592
v |= (0x1F << 18);
drivers/ssb/driver_pcicore.c
593
v |= (phy << 4);
drivers/ssb/driver_pcicore.c
594
pcicore_write32(pc, mdio_data, v);
drivers/ssb/driver_pcicore.c
598
v = pcicore_read32(pc, mdio_control);
drivers/ssb/driver_pcicore.c
599
if (v & 0x100 /* Trans complete */)
drivers/ssb/driver_pcicore.c
611
u32 v;
drivers/ssb/driver_pcicore.c
614
v = 0x80; /* Enable Preamble Sequence */
drivers/ssb/driver_pcicore.c
615
v |= 0x2; /* MDIO Clock Divisor */
drivers/ssb/driver_pcicore.c
616
pcicore_write32(pc, mdio_control, v);
drivers/ssb/driver_pcicore.c
623
v = (1 << 30); /* Start of Transaction */
drivers/ssb/driver_pcicore.c
624
v |= (1 << 29); /* Read Transaction */
drivers/ssb/driver_pcicore.c
625
v |= (1 << 17); /* Turnaround */
drivers/ssb/driver_pcicore.c
627
v |= (u32)device << 22;
drivers/ssb/driver_pcicore.c
628
v |= (u32)address << 18;
drivers/ssb/driver_pcicore.c
629
pcicore_write32(pc, mdio_data, v);
drivers/ssb/driver_pcicore.c
633
v = pcicore_read32(pc, mdio_control);
drivers/ssb/driver_pcicore.c
634
if (v & 0x100 /* Trans complete */) {
drivers/ssb/driver_pcicore.c
651
u32 v;
drivers/ssb/driver_pcicore.c
654
v = 0x80; /* Enable Preamble Sequence */
drivers/ssb/driver_pcicore.c
655
v |= 0x2; /* MDIO Clock Divisor */
drivers/ssb/driver_pcicore.c
656
pcicore_write32(pc, mdio_control, v);
drivers/ssb/driver_pcicore.c
663
v = (1 << 30); /* Start of Transaction */
drivers/ssb/driver_pcicore.c
664
v |= (1 << 28); /* Write Transaction */
drivers/ssb/driver_pcicore.c
665
v |= (1 << 17); /* Turnaround */
drivers/ssb/driver_pcicore.c
667
v |= (u32)device << 22;
drivers/ssb/driver_pcicore.c
668
v |= (u32)address << 18;
drivers/ssb/driver_pcicore.c
669
v |= data;
drivers/ssb/driver_pcicore.c
670
pcicore_write32(pc, mdio_data, v);
drivers/ssb/driver_pcicore.c
674
v = pcicore_read32(pc, mdio_control);
drivers/ssb/driver_pcicore.c
675
if (v & 0x100 /* Trans complete */)
drivers/ssb/main.c
825
static u32 clkfactor_f6_resolve(u32 v)
drivers/ssb/main.c
828
switch (v) {
drivers/ssb/pci.c
330
u16 v;
drivers/ssb/pci.c
333
v = in[SPOFF(offset)];
drivers/ssb/pci.c
334
gain = (v & mask) >> shift;
drivers/staging/media/atomisp/pci/bits.h
85
#define _hrt_set_bits(w, b, n, v) \
drivers/staging/media/atomisp/pci/bits.h
86
(((w) & ~_hrt_mask(b, n)) | (((v) & _hrt_ones(n)) << (b)))
drivers/staging/media/atomisp/pci/bits.h
89
#define _hrt_set_bit(w, b, v) \
drivers/staging/media/atomisp/pci/bits.h
90
(((w) & (~(1 << (b)))) | (((v) & 1) << (b)))
drivers/staging/media/atomisp/pci/bits.h
91
#define _hrt_set_lower_half(w, v) \
drivers/staging/media/atomisp/pci/bits.h
92
_hrt_set_bits(w, 0, 16, v)
drivers/staging/media/atomisp/pci/bits.h
93
#define _hrt_set_upper_half(w, v) \
drivers/staging/media/atomisp/pci/bits.h
94
_hrt_set_bits(w, 16, 16, v)
drivers/staging/media/atomisp/pci/hive_isp_css_common/host/vmem.c
142
VMEM_ARRAY(v, 2 * ISP_NWAY); /* Need 2 vectors to work around vmem hss bug */
drivers/staging/media/atomisp/pci/hive_isp_css_common/host/vmem.c
145
ia_css_device_load(ISP_BAMEM_BASE[ID] + (unsigned long)from, &v[0][0], size);
drivers/staging/media/atomisp/pci/hive_isp_css_common/host/vmem.c
147
hrt_master_port_load(ISP_BAMEM_BASE[ID] + (unsigned long)from, &v[0][0], size);
drivers/staging/media/atomisp/pci/hive_isp_css_common/host/vmem.c
149
data = (hive_uedge *)v;
drivers/staging/media/atomisp/pci/hive_isp_css_common/host/vmem.c
167
VMEM_ARRAY(v, 2 * ISP_NWAY); /* Need 2 vectors to work around vmem hss bug */
drivers/staging/media/atomisp/pci/hive_isp_css_common/host/vmem.c
169
hive_uedge *data = (hive_uedge *)v;
drivers/staging/media/atomisp/pci/hive_isp_css_common/host/vmem.c
176
ia_css_device_store(ISP_BAMEM_BASE[ID] + (unsigned long)to, &v, size);
drivers/staging/media/atomisp/pci/hive_isp_css_common/host/vmem.c
179
hrt_master_port_store(ISP_BAMEM_BASE[ID] + (unsigned long)to, &v, size);
drivers/staging/media/atomisp/pci/ia_css_frame_public.h
61
struct ia_css_frame_plane v; /** V plane */
drivers/staging/media/atomisp/pci/runtime/debug/src/ia_css_debug.c
492
data + frame->planes.yuv.v.offset);
drivers/staging/media/atomisp/pci/runtime/frame/interface/ia_css_frame_comm.h
33
struct ia_css_frame_sp_plane v;
drivers/staging/media/atomisp/pci/runtime/frame/src/frame.c
551
frame_init_plane(&frame->planes.yuv.v, uv_width, uv_stride,
drivers/staging/media/atomisp/pci/runtime/frame/src/frame.c
558
frame_init_plane(&frame->planes.yuv.v, uv_width, uv_stride,
drivers/staging/media/atomisp/pci/sh_css_frac.h
26
static inline int sDIGIT_FITTING(int v, int a, int b)
drivers/staging/media/atomisp/pci/sh_css_frac.h
30
v >>= sSHIFT;
drivers/staging/media/atomisp/pci/sh_css_frac.h
32
v >>= fit_shift;
drivers/staging/media/atomisp/pci/sh_css_frac.h
34
return clamp_t(int, v, sISP_VAL_MIN, sISP_VAL_MAX);
drivers/staging/media/atomisp/pci/sh_css_frac.h
37
static inline unsigned int uDIGIT_FITTING(unsigned int v, int a, int b)
drivers/staging/media/atomisp/pci/sh_css_frac.h
41
v >>= uSHIFT;
drivers/staging/media/atomisp/pci/sh_css_frac.h
43
v >>= fit_shift;
drivers/staging/media/atomisp/pci/sh_css_frac.h
45
return clamp_t(unsigned int, v, uISP_VAL_MIN, uISP_VAL_MAX);
drivers/staging/media/atomisp/pci/sh_css_sp.c
482
sp_frame_out->planes.yuv.v.offset =
drivers/staging/media/atomisp/pci/sh_css_sp.c
483
frame_in->planes.yuv.v.offset;
drivers/staging/media/av7110/av7110_hw.c
916
u16 y, u, v;
drivers/staging/media/av7110/av7110_hw.c
921
v = 2048 + R * 8 - (y >> 5); /* Cb 0..4095 */
drivers/staging/media/av7110/av7110_hw.c
925
Cr = v / 16;
drivers/staging/media/deprecated/atmel/atmel-isc-regs.h
47
#define ISC_PFE_CFG1_COLMIN(v) ((v))
drivers/staging/media/deprecated/atmel/atmel-isc-regs.h
49
#define ISC_PFE_CFG1_COLMAX(v) ((v) << 16)
drivers/staging/media/deprecated/atmel/atmel-isc-regs.h
55
#define ISC_PFE_CFG2_ROWMIN(v) ((v))
drivers/staging/media/deprecated/atmel/atmel-isc-regs.h
57
#define ISC_PFE_CFG2_ROWMAX(v) ((v) << 16)
drivers/staging/media/deprecated/atmel/atmel-isc.h
38
#define to_isc_clk(v) container_of(v, struct isc_clk, hw)
drivers/staging/media/imx/imx-media-capture.c
51
#define to_capture_priv(v) container_of(v, struct capture_priv, vdev)
drivers/staging/media/imx/imx-media-csc-scaler.c
44
#define vdev_to_priv(v) container_of(v, struct ipu_csc_scaler_priv, vdev)
drivers/staging/media/ipu3/include/uapi/intel-ipu3.h
1914
__u32 v:13;
drivers/staging/media/ipu3/ipu3-abi.h
1388
struct imgu_abi_frame_sp_plane v;
drivers/staging/media/ipu3/ipu3-css.c
965
frame_sp->planes.yuv.v.offset = css_queue_vf->width_pad *
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
104
#define VE_DEC_MPEG_MP12HDR_TOP_FIELD_FIRST(v) \
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
105
((v) ? BIT(7) : 0)
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
106
#define VE_DEC_MPEG_MP12HDR_FRAME_PRED_FRAME_DCT(v) \
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
107
((v) ? BIT(6) : 0)
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
108
#define VE_DEC_MPEG_MP12HDR_CONCEALMENT_MOTION_VECTORS(v) \
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
109
((v) ? BIT(5) : 0)
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
110
#define VE_DEC_MPEG_MP12HDR_Q_SCALE_TYPE(v) \
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
111
((v) ? BIT(4) : 0)
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
112
#define VE_DEC_MPEG_MP12HDR_INTRA_VLC_FORMAT(v) \
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
113
((v) ? BIT(3) : 0)
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
114
#define VE_DEC_MPEG_MP12HDR_ALTERNATE_SCAN(v) \
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
115
((v) ? BIT(2) : 0)
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
116
#define VE_DEC_MPEG_MP12HDR_FULL_PEL_FORWARD_VECTOR(v) \
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
117
((v) ? BIT(1) : 0)
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
118
#define VE_DEC_MPEG_MP12HDR_FULL_PEL_BACKWARD_VECTOR(v) \
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
119
((v) ? BIT(0) : 0)
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
13
#define SHIFT_AND_MASK_BITS(v, h, l) \
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
14
(((unsigned long)(v) << (l)) & GENMASK(h, l))
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
250
#define VE_DEC_MPEG_IQMINPUT_WEIGHT(i, v) \
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
251
(SHIFT_AND_MASK_BITS(i, 13, 8) | SHIFT_AND_MASK_BITS(v, 7, 0))
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
260
#define VE_DEC_H265_DEC_NAL_HDR_NUH_TEMPORAL_ID_PLUS1(v) \
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
261
SHIFT_AND_MASK_BITS(v, 8, 6)
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
262
#define VE_DEC_H265_DEC_NAL_HDR_NAL_UNIT_TYPE(v) \
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
263
SHIFT_AND_MASK_BITS(v, 5, 0)
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
276
#define VE_DEC_H265_DEC_SPS_HDR_MAX_TRANSFORM_HIERARCHY_DEPTH_INTRA(v) \
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
277
SHIFT_AND_MASK_BITS(v, 22, 20)
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
278
#define VE_DEC_H265_DEC_SPS_HDR_MAX_TRANSFORM_HIERARCHY_DEPTH_INTER(v) \
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
279
SHIFT_AND_MASK_BITS(v, 19, 17)
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
280
#define VE_DEC_H265_DEC_SPS_HDR_LOG2_DIFF_MAX_MIN_TRANSFORM_BLOCK_SIZE(v) \
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
281
SHIFT_AND_MASK_BITS(v, 16, 15)
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
282
#define VE_DEC_H265_DEC_SPS_HDR_LOG2_MIN_TRANSFORM_BLOCK_SIZE_MINUS2(v) \
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
283
SHIFT_AND_MASK_BITS(v, 14, 13)
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
284
#define VE_DEC_H265_DEC_SPS_HDR_LOG2_DIFF_MAX_MIN_LUMA_CODING_BLOCK_SIZE(v) \
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
285
SHIFT_AND_MASK_BITS(v, 12, 11)
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
286
#define VE_DEC_H265_DEC_SPS_HDR_LOG2_MIN_LUMA_CODING_BLOCK_SIZE_MINUS3(v) \
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
287
SHIFT_AND_MASK_BITS(v, 10, 9)
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
288
#define VE_DEC_H265_DEC_SPS_HDR_BIT_DEPTH_CHROMA_MINUS8(v) \
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
289
SHIFT_AND_MASK_BITS(v, 8, 6)
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
290
#define VE_DEC_H265_DEC_SPS_HDR_BIT_DEPTH_LUMA_MINUS8(v) \
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
291
SHIFT_AND_MASK_BITS(v, 5, 3)
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
292
#define VE_DEC_H265_DEC_SPS_HDR_CHROMA_FORMAT_IDC(v) \
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
293
SHIFT_AND_MASK_BITS(v, 1, 0)
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
305
#define VE_DEC_H265_DEC_PCM_CTRL_LOG2_DIFF_MAX_MIN_PCM_LUMA_CODING_BLOCK_SIZE(v) \
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
306
SHIFT_AND_MASK_BITS(v, 11, 10)
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
307
#define VE_DEC_H265_DEC_PCM_CTRL_LOG2_MIN_PCM_LUMA_CODING_BLOCK_SIZE_MINUS3(v) \
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
308
SHIFT_AND_MASK_BITS(v, 9, 8)
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
309
#define VE_DEC_H265_DEC_PCM_CTRL_PCM_SAMPLE_BIT_DEPTH_CHROMA_MINUS1(v) \
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
310
SHIFT_AND_MASK_BITS(v, 7, 4)
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
311
#define VE_DEC_H265_DEC_PCM_CTRL_PCM_SAMPLE_BIT_DEPTH_LUMA_MINUS1(v) \
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
312
SHIFT_AND_MASK_BITS(v, 3, 0)
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
321
#define VE_DEC_H265_DEC_PPS_CTRL0_PPS_CR_QP_OFFSET(v) \
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
322
SHIFT_AND_MASK_BITS(v, 29, 24)
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
323
#define VE_DEC_H265_DEC_PPS_CTRL0_PPS_CB_QP_OFFSET(v) \
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
324
SHIFT_AND_MASK_BITS(v, 21, 16)
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
325
#define VE_DEC_H265_DEC_PPS_CTRL0_INIT_QP_MINUS26(v) \
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
326
SHIFT_AND_MASK_BITS(v, 14, 8)
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
327
#define VE_DEC_H265_DEC_PPS_CTRL0_DIFF_CU_QP_DELTA_DEPTH(v) \
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
328
SHIFT_AND_MASK_BITS(v, 5, 4)
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
340
#define VE_DEC_H265_DEC_PPS_CTRL1_LOG2_PARALLEL_MERGE_LEVEL_MINUS2(v) \
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
341
SHIFT_AND_MASK_BITS(v, 10, 8)
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
361
#define VE_DEC_H265_DEC_SLICE_HDR_INFO0_PICTURE_TYPE(v) \
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
362
SHIFT_AND_MASK_BITS(v, 29, 28)
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
363
#define VE_DEC_H265_DEC_SLICE_HDR_INFO0_FIVE_MINUS_MAX_NUM_MERGE_CAND(v) \
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
364
SHIFT_AND_MASK_BITS(v, 26, 24)
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
365
#define VE_DEC_H265_DEC_SLICE_HDR_INFO0_NUM_REF_IDX_L1_ACTIVE_MINUS1(v) \
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
366
SHIFT_AND_MASK_BITS(v, 23, 20)
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
367
#define VE_DEC_H265_DEC_SLICE_HDR_INFO0_NUM_REF_IDX_L0_ACTIVE_MINUS1(v) \
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
368
SHIFT_AND_MASK_BITS(v, 19, 16)
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
369
#define VE_DEC_H265_DEC_SLICE_HDR_INFO0_COLLOCATED_REF_IDX(v) \
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
370
SHIFT_AND_MASK_BITS(v, 15, 12)
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
371
#define VE_DEC_H265_DEC_SLICE_HDR_INFO0_COLOUR_PLANE_ID(v) \
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
372
SHIFT_AND_MASK_BITS(v, 5, 4)
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
373
#define VE_DEC_H265_DEC_SLICE_HDR_INFO0_SLICE_TYPE(v) \
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
374
SHIFT_AND_MASK_BITS(v, 3, 2)
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
382
#define VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_TC_OFFSET_DIV2(v) \
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
383
SHIFT_AND_MASK_BITS(v, 31, 28)
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
384
#define VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_BETA_OFFSET_DIV2(v) \
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
385
SHIFT_AND_MASK_BITS(v, 27, 24)
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
386
#define VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_CR_QP_OFFSET(v) \
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
387
SHIFT_AND_MASK_BITS(v, 20, 16)
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
388
#define VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_CB_QP_OFFSET(v) \
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
389
SHIFT_AND_MASK_BITS(v, 12, 8)
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
390
#define VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_QP_DELTA(v) \
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
391
SHIFT_AND_MASK_BITS(v, 6, 0)
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
395
#define VE_DEC_H265_DEC_SLICE_HDR_INFO2_NUM_ENTRY_POINT_OFFSETS(v) \
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
396
SHIFT_AND_MASK_BITS(v, 21, 8)
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
397
#define VE_DEC_H265_DEC_SLICE_HDR_INFO2_CHROMA_LOG2_WEIGHT_DENOM(v) \
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
398
SHIFT_AND_MASK_BITS(v, 6, 4)
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
399
#define VE_DEC_H265_DEC_SLICE_HDR_INFO2_LUMA_LOG2_WEIGHT_DENOM(v) \
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
400
SHIFT_AND_MASK_BITS(v, 2, 0)
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
508
#define VE_DEC_H265_10BIT_CONFIGURE_SECOND_OUT_FMT(v) \
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
509
SHIFT_AND_MASK_BITS(v, 24, 23)
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
511
#define VE_DEC_H265_10BIT_CONFIGURE_SECOND_2BIT_STRIDE(v) \
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
512
SHIFT_AND_MASK_BITS(v, 21, 11)
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
513
#define VE_DEC_H265_10BIT_CONFIGURE_FIRST_2BIT_STRIDE(v) \
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
514
SHIFT_AND_MASK_BITS(v, 10, 0)
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
621
#define VE_VP8_PPS_LAST_SHARPNESS_LEVEL(v) SHIFT_AND_MASK_BITS(v, 30, 28)
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
628
#define VE_VP8_PPS_TOKEN_PARTITION(v) SHIFT_AND_MASK_BITS(v, 21, 20)
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
631
#define VE_VP8_PPS_LOOP_FILTER_LEVEL(v) SHIFT_AND_MASK_BITS(v, 17, 12)
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
633
#define VE_VP8_PPS_SHARPNESS_LEVEL(v) SHIFT_AND_MASK_BITS(v, 10, 8)
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
644
#define VE_VP8_QP_INDEX_DELTA_UVAC(v) SHIFT_AND_MASK_BITS(v, 31, 27)
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
645
#define VE_VP8_QP_INDEX_DELTA_UVDC(v) SHIFT_AND_MASK_BITS(v, 26, 22)
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
646
#define VE_VP8_QP_INDEX_DELTA_Y2AC(v) SHIFT_AND_MASK_BITS(v, 21, 17)
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
647
#define VE_VP8_QP_INDEX_DELTA_Y2DC(v) SHIFT_AND_MASK_BITS(v, 16, 12)
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
648
#define VE_VP8_QP_INDEX_DELTA_Y1DC(v) SHIFT_AND_MASK_BITS(v, 11, 7)
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
649
#define VE_VP8_QP_INDEX_DELTA_BASE_QINDEX(v) SHIFT_AND_MASK_BITS(v, 6, 0)
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
677
#define VE_VP8_SEGMENT3(v) SHIFT_AND_MASK_BITS(v, 31, 24)
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
678
#define VE_VP8_SEGMENT2(v) SHIFT_AND_MASK_BITS(v, 23, 16)
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
679
#define VE_VP8_SEGMENT1(v) SHIFT_AND_MASK_BITS(v, 15, 8)
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
680
#define VE_VP8_SEGMENT0(v) SHIFT_AND_MASK_BITS(v, 7, 0)
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
685
#define VE_VP8_LF_DELTA3(v) SHIFT_AND_MASK_BITS(v, 30, 24)
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
686
#define VE_VP8_LF_DELTA2(v) SHIFT_AND_MASK_BITS(v, 22, 16)
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
687
#define VE_VP8_LF_DELTA1(v) SHIFT_AND_MASK_BITS(v, 14, 8)
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
688
#define VE_VP8_LF_DELTA0(v) SHIFT_AND_MASK_BITS(v, 6, 0)
drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h
104
#define SUN6I_ISP_MODE_INPUT_FMT(v) ((v) & GENMASK(2, 0))
drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h
105
#define SUN6I_ISP_MODE_INPUT_YUV_SEQ(v) (((v) << 3) & GENMASK(4, 3))
drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h
106
#define SUN6I_ISP_MODE_OTF_DPC(v) (((v) << 16) & BIT(16))
drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h
107
#define SUN6I_ISP_MODE_SHARP(v) (((v) << 17) & BIT(17))
drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h
108
#define SUN6I_ISP_MODE_HIST(v) (((v) << 20) & GENMASK(21, 20))
drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h
123
#define SUN6I_ISP_IN_CFG_STRIDE_DIV16(v) ((v) & GENMASK(10, 0))
drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h
133
#define SUN6I_ISP_AE_CFG_LOW_BRI_TH(v) ((v) & GENMASK(11, 0))
drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h
134
#define SUN6I_ISP_AE_CFG_HORZ_NUM(v) (((v) << 12) & GENMASK(15, 12))
drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h
135
#define SUN6I_ISP_AE_CFG_HIGH_BRI_TH(v) (((v) << 16) & GENMASK(27, 16))
drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h
136
#define SUN6I_ISP_AE_CFG_VERT_NUM(v) (((v) << 28) & GENMASK(31, 28))
drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h
139
#define SUN6I_ISP_AE_SIZE_WIDTH(v) ((v) & GENMASK(10, 0))
drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h
140
#define SUN6I_ISP_AE_SIZE_HEIGHT(v) (((v) << 16) & GENMASK(26, 16))
drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h
143
#define SUN6I_ISP_AE_POS_HORZ_START(v) ((v) & GENMASK(10, 0))
drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h
144
#define SUN6I_ISP_AE_POS_VERT_START(v) (((v) << 16) & GENMASK(26, 16))
drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h
149
#define SUN6I_ISP_OB_SIZE_WIDTH(v) ((v) & GENMASK(13, 0))
drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h
150
#define SUN6I_ISP_OB_SIZE_HEIGHT(v) (((v) << 16) & GENMASK(29, 16))
drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h
153
#define SUN6I_ISP_OB_VALID_WIDTH(v) ((v) & GENMASK(12, 0))
drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h
154
#define SUN6I_ISP_OB_VALID_HEIGHT(v) (((v) << 16) & GENMASK(28, 16))
drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h
157
#define SUN6I_ISP_OB_SRC0_VALID_START_HORZ(v) ((v) & GENMASK(11, 0))
drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h
158
#define SUN6I_ISP_OB_SRC0_VALID_START_VERT(v) (((v) << 16) & GENMASK(27, 16))
drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h
161
#define SUN6I_ISP_OB_SRC1_VALID_START_HORZ(v) ((v) & GENMASK(11, 0))
drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h
162
#define SUN6I_ISP_OB_SRC1_VALID_START_VERT(v) (((v) << 16) & GENMASK(27, 16))
drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h
165
#define SUN6I_ISP_OB_SPRITE_WIDTH(v) ((v) & GENMASK(12, 0))
drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h
166
#define SUN6I_ISP_OB_SPRITE_HEIGHT(v) (((v) << 16) & GENMASK(28, 16))
drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h
169
#define SUN6I_ISP_OB_SPRITE_START_HORZ(v) ((v) & GENMASK(11, 0))
drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h
170
#define SUN6I_ISP_OB_SPRITE_START_VERT(v) (((v) << 16) & GENMASK(27, 16))
drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h
180
#define SUN6I_ISP_BDNF_CFG_IN_DIS_MIN(v) ((v) & GENMASK(7, 0))
drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h
181
#define SUN6I_ISP_BDNF_CFG_IN_DIS_MAX(v) (((v) << 16) & GENMASK(23, 16))
drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h
184
#define SUN6I_ISP_BDNF_COEF_RB(i, v) (((v) << (4 * (i))) & \
drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h
188
#define SUN6I_ISP_BDNF_COEF_G(i, v) (((v) << (4 * (i))) & \
drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h
194
#define SUN6I_ISP_BAYER_OFFSET0_R(v) ((v) & GENMASK(12, 0))
drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h
195
#define SUN6I_ISP_BAYER_OFFSET0_GR(v) (((v) << 16) & GENMASK(28, 16))
drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h
198
#define SUN6I_ISP_BAYER_OFFSET1_GB(v) ((v) & GENMASK(12, 0))
drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h
199
#define SUN6I_ISP_BAYER_OFFSET1_B(v) (((v) << 16) & GENMASK(28, 16))
drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h
202
#define SUN6I_ISP_BAYER_GAIN0_R(v) ((v) & GENMASK(11, 0))
drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h
203
#define SUN6I_ISP_BAYER_GAIN0_GR(v) (((v) << 16) & GENMASK(27, 16))
drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h
206
#define SUN6I_ISP_BAYER_GAIN1_GB(v) ((v) & GENMASK(11, 0))
drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h
207
#define SUN6I_ISP_BAYER_GAIN1_B(v) (((v) << 16) & GENMASK(27, 16))
drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h
21
#define SUN6I_ISP_FE_CFG_SRC0_MODE(v) (((v) << 8) & GENMASK(9, 8))
drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h
212
#define SUN6I_ISP_WB_GAIN0_R(v) ((v) & GENMASK(11, 0))
drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h
213
#define SUN6I_ISP_WB_GAIN0_GR(v) (((v) << 16) & GENMASK(27, 16))
drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h
216
#define SUN6I_ISP_WB_GAIN1_GB(v) ((v) & GENMASK(11, 0))
drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h
217
#define SUN6I_ISP_WB_GAIN1_B(v) (((v) << 16) & GENMASK(27, 16))
drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h
22
#define SUN6I_ISP_FE_CFG_SRC1_MODE(v) (((v) << 16) & GENMASK(17, 16))
drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h
220
#define SUN6I_ISP_WB_CFG_CLIP(v) ((v) & GENMASK(11, 0))
drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h
225
#define SUN6I_ISP_MCH_SIZE_CFG_WIDTH(v) ((v) & GENMASK(12, 0))
drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h
226
#define SUN6I_ISP_MCH_SIZE_CFG_HEIGHT(v) (((v) << 16) & GENMASK(28, 16))
drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h
229
#define SUN6I_ISP_MCH_SCALE_CFG_X_RATIO(v) ((v) & GENMASK(11, 0))
drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h
230
#define SUN6I_ISP_MCH_SCALE_CFG_Y_RATIO(v) (((v) << 16) & GENMASK(27, 16))
drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h
231
#define SUN6I_ISP_MCH_SCALE_CFG_WEIGHT_SHIFT(v) (((v) << 28) & GENMASK(31, 28))
drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h
234
#define SUN6I_ISP_SCH_SIZE_CFG_WIDTH(v) ((v) & GENMASK(12, 0))
drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h
235
#define SUN6I_ISP_SCH_SIZE_CFG_HEIGHT(v) (((v) << 16) & GENMASK(28, 16))
drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h
238
#define SUN6I_ISP_SCH_SCALE_CFG_X_RATIO(v) ((v) & GENMASK(11, 0))
drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h
239
#define SUN6I_ISP_SCH_SCALE_CFG_Y_RATIO(v) (((v) << 16) & GENMASK(27, 16))
drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h
240
#define SUN6I_ISP_SCH_SCALE_CFG_WEIGHT_SHIFT(v) (((v) << 28) & GENMASK(31, 28))
drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h
245
#define SUN6I_ISP_MCH_CFG_OUTPUT_FMT(v) (((v) << 2) & GENMASK(4, 2))
drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h
248
#define SUN6I_ISP_MCH_CFG_STRIDE_Y_DIV4(v) (((v) << 8) & GENMASK(18, 8))
drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h
249
#define SUN6I_ISP_MCH_CFG_STRIDE_UV_DIV4(v) (((v) << 20) & GENMASK(30, 20))
drivers/staging/media/sunxi/sun6i-isp/sun6i_isp_reg.h
33
#define SUN6I_ISP_FE_CTRL_OUTPUT_SPEED_CTRL(v) (((v) << 16) & GENMASK(17, 16))
drivers/staging/rtl8723bs/hal/sdio_ops.c
640
void SdioLocalCmd52Write1Byte(struct adapter *adapter, u32 addr, u8 v)
drivers/staging/rtl8723bs/hal/sdio_ops.c
645
sd_cmd52_write(intfhdl, addr, 1, &v);
drivers/staging/rtl8723bs/hal/sdio_ops.c
648
static void sdio_local_cmd52_write4byte(struct adapter *adapter, u32 addr, u32 v)
drivers/staging/rtl8723bs/hal/sdio_ops.c
654
le_tmp = cpu_to_le32(v);
drivers/staging/rtl8723bs/include/sdio_ops.h
18
extern void SdioLocalCmd52Write1Byte(struct adapter *padapter, u32 addr, u8 v);
drivers/staging/rtl8723bs/include/sdio_ops_linux.h
23
void sd_write8(struct intf_hdl *pintfhdl, u32 addr, u8 v, s32 *err);
drivers/staging/rtl8723bs/include/sdio_ops_linux.h
24
void sd_write32(struct intf_hdl *pintfhdl, u32 addr, u32 v, s32 *err);
drivers/staging/rtl8723bs/os_dep/sdio_ops_linux.c
161
u8 v = 0;
drivers/staging/rtl8723bs/os_dep/sdio_ops_linux.c
170
return v;
drivers/staging/rtl8723bs/os_dep/sdio_ops_linux.c
177
v = sdio_readb(func, addr, err);
drivers/staging/rtl8723bs/os_dep/sdio_ops_linux.c
180
return v;
drivers/staging/rtl8723bs/os_dep/sdio_ops_linux.c
188
u32 v = 0;
drivers/staging/rtl8723bs/os_dep/sdio_ops_linux.c
197
return v;
drivers/staging/rtl8723bs/os_dep/sdio_ops_linux.c
204
v = sdio_readl(func, addr, err);
drivers/staging/rtl8723bs/os_dep/sdio_ops_linux.c
215
v = sdio_readl(func, addr, err);
drivers/staging/rtl8723bs/os_dep/sdio_ops_linux.c
233
return v;
drivers/staging/rtl8723bs/os_dep/sdio_ops_linux.c
236
void sd_write8(struct intf_hdl *pintfhdl, u32 addr, u8 v, s32 *err)
drivers/staging/rtl8723bs/os_dep/sdio_ops_linux.c
256
sdio_writeb(func, v, addr, err);
drivers/staging/rtl8723bs/os_dep/sdio_ops_linux.c
261
void sd_write32(struct intf_hdl *pintfhdl, u32 addr, u32 v, s32 *err)
drivers/staging/rtl8723bs/os_dep/sdio_ops_linux.c
281
sdio_writel(func, v, addr, err);
drivers/staging/rtl8723bs/os_dep/sdio_ops_linux.c
292
sdio_writel(func, v, addr, err);
drivers/target/sbp/sbp_target.h
19
#define ORB_NOTIFY(v) (((v) >> 31) & 0x01)
drivers/target/sbp/sbp_target.h
20
#define ORB_REQUEST_FORMAT(v) (((v) >> 29) & 0x03)
drivers/target/sbp/sbp_target.h
22
#define MANAGEMENT_ORB_FUNCTION(v) (((v) >> 16) & 0x0f)
drivers/target/sbp/sbp_target.h
34
#define LOGIN_ORB_EXCLUSIVE(v) (((v) >> 28) & 0x01)
drivers/target/sbp/sbp_target.h
35
#define LOGIN_ORB_RESERVED(v) (((v) >> 24) & 0x0f)
drivers/target/sbp/sbp_target.h
36
#define LOGIN_ORB_RECONNECT(v) (((v) >> 20) & 0x0f)
drivers/target/sbp/sbp_target.h
37
#define LOGIN_ORB_LUN(v) (((v) >> 0) & 0xffff)
drivers/target/sbp/sbp_target.h
38
#define LOGIN_ORB_PASSWORD_LENGTH(v) (((v) >> 16) & 0xffff)
drivers/target/sbp/sbp_target.h
39
#define LOGIN_ORB_RESPONSE_LENGTH(v) (((v) >> 0) & 0xffff)
drivers/target/sbp/sbp_target.h
41
#define RECONNECT_ORB_LOGIN_ID(v) (((v) >> 0) & 0xffff)
drivers/target/sbp/sbp_target.h
42
#define LOGOUT_ORB_LOGIN_ID(v) (((v) >> 0) & 0xffff)
drivers/target/sbp/sbp_target.h
44
#define CMDBLK_ORB_DIRECTION(v) (((v) >> 27) & 0x01)
drivers/target/sbp/sbp_target.h
45
#define CMDBLK_ORB_SPEED(v) (((v) >> 24) & 0x07)
drivers/target/sbp/sbp_target.h
46
#define CMDBLK_ORB_MAX_PAYLOAD(v) (((v) >> 20) & 0x0f)
drivers/target/sbp/sbp_target.h
47
#define CMDBLK_ORB_PG_TBL_PRESENT(v) (((v) >> 19) & 0x01)
drivers/target/sbp/sbp_target.h
48
#define CMDBLK_ORB_PG_SIZE(v) (((v) >> 16) & 0x07)
drivers/target/sbp/sbp_target.h
49
#define CMDBLK_ORB_DATA_SIZE(v) (((v) >> 0) & 0xffff)
drivers/target/sbp/sbp_target.h
51
#define STATUS_BLOCK_SRC(v) (((v) & 0x03) << 30)
drivers/target/sbp/sbp_target.h
52
#define STATUS_BLOCK_RESP(v) (((v) & 0x03) << 28)
drivers/target/sbp/sbp_target.h
53
#define STATUS_BLOCK_DEAD(v) (((v) ? 1 : 0) << 27)
drivers/target/sbp/sbp_target.h
54
#define STATUS_BLOCK_LEN(v) (((v) & 0x07) << 24)
drivers/target/sbp/sbp_target.h
55
#define STATUS_BLOCK_SBP_STATUS(v) (((v) & 0xff) << 16)
drivers/target/sbp/sbp_target.h
56
#define STATUS_BLOCK_ORB_OFFSET_HIGH(v) (((v) & 0xffff) << 0)
drivers/tee/amdtee/core.c
29
struct tee_ioctl_version_data v = {
drivers/tee/amdtee/core.c
34
*vers = v;
drivers/tee/optee/ffa_abi.c
905
struct tee_ioctl_version_data v = {
drivers/tee/optee/ffa_abi.c
912
*vers = v;
drivers/tee/optee/smc_abi.c
1221
struct tee_ioctl_version_data v = {
drivers/tee/optee/smc_abi.c
1229
v.gen_caps |= TEE_GEN_CAP_REG_MEM;
drivers/tee/optee/smc_abi.c
1231
v.gen_caps |= TEE_GEN_CAP_MEMREF_NULL;
drivers/tee/optee/smc_abi.c
1232
*vers = v;
drivers/tee/qcomtee/call.c
627
struct tee_ioctl_version_data v = {
drivers/tee/qcomtee/call.c
632
*vers = v;
drivers/tee/tee_core.c
1329
struct tee_ioctl_version_data v;
drivers/tee/tee_core.c
1330
struct match_dev_data match_data = { vers ? vers : &v, data, match };
drivers/tee/tstee/core.c
48
struct tee_ioctl_version_data v = {
drivers/tee/tstee/core.c
55
*vers = v;
drivers/thermal/intel/int340x_thermal/int3406_thermal.c
37
#define ACPI_TO_RAW(v, d) (d->raw_bd->props.max_brightness * v / 100)
drivers/thermal/intel/int340x_thermal/int3406_thermal.c
38
#define RAW_TO_ACPI(v, d) (v * 100 / d->raw_bd->props.max_brightness)
drivers/thermal/tegra/soctherm.c
1340
s32 v;
drivers/thermal/tegra/soctherm.c
1348
v = sign_extend32(state, ts->soc->bptt - 1);
drivers/thermal/tegra/soctherm.c
1349
v *= ts->soc->thresh_grain;
drivers/thermal/tegra/soctherm.c
1350
seq_printf(s, " %d: Up/Dn(%d /", level, v);
drivers/thermal/tegra/soctherm.c
1354
v = sign_extend32(state, ts->soc->bptt - 1);
drivers/thermal/tegra/soctherm.c
1355
v *= ts->soc->thresh_grain;
drivers/thermal/tegra/soctherm.c
1356
seq_printf(s, "%d ) ", v);
drivers/thermal/tegra/soctherm.c
1938
u32 v;
drivers/thermal/tegra/soctherm.c
1952
v = REG_SET_MASK(0, THROT_GLOBAL_ENB_MASK, 1);
drivers/thermal/tegra/soctherm.c
1954
ccroc_writel(ts, v, CCROC_GLOBAL_CFG);
drivers/thermal/tegra/soctherm.c
1956
v = ccroc_readl(ts, CCROC_SUPER_CCLKG_DIVIDER);
drivers/thermal/tegra/soctherm.c
1957
v = REG_SET_MASK(v, CDIVG_USE_THERM_CONTROLS_MASK, 1);
drivers/thermal/tegra/soctherm.c
1958
ccroc_writel(ts, v, CCROC_SUPER_CCLKG_DIVIDER);
drivers/thermal/tegra/soctherm.c
1960
writel(v, ts->regs + THROT_GLOBAL_CFG);
drivers/thermal/tegra/soctherm.c
1962
v = readl(ts->clk_regs + CAR_SUPER_CCLKG_DIVIDER);
drivers/thermal/tegra/soctherm.c
1963
v = REG_SET_MASK(v, CDIVG_USE_THERM_CONTROLS_MASK, 1);
drivers/thermal/tegra/soctherm.c
1964
writel(v, ts->clk_regs + CAR_SUPER_CCLKG_DIVIDER);
drivers/thermal/tegra/soctherm.c
1968
v = STATS_CTL_CLR_DN | STATS_CTL_EN_DN |
drivers/thermal/tegra/soctherm.c
1970
writel(v, ts->regs + THERMCTL_STATS_CTL);
drivers/thermal/tegra/soctherm.c
200
#define REG_SET_MASK(r, m, v) (((r) & ~(m)) | \
drivers/thermal/tegra/soctherm.c
201
(((v) & (m >> (ffs(m) - 1))) << (ffs(m) - 1)))
drivers/thermal/thermal_debugfs.c
299
static void *cdev_seq_next(struct seq_file *s, void *v, loff_t *pos)
drivers/thermal/thermal_debugfs.c
306
static void cdev_seq_stop(struct seq_file *s, void *v)
drivers/thermal/thermal_debugfs.c
313
static int cdev_tt_seq_show(struct seq_file *s, void *v)
drivers/thermal/thermal_debugfs.c
319
int i = *(loff_t *)v;
drivers/thermal/thermal_debugfs.c
349
static int cdev_dt_seq_show(struct seq_file *s, void *v)
drivers/thermal/thermal_debugfs.c
355
int i = *(loff_t *)v;
drivers/thermal/thermal_debugfs.c
771
static void *tze_seq_next(struct seq_file *s, void *v, loff_t *pos)
drivers/thermal/thermal_debugfs.c
776
return seq_list_next(v, &tz_dbg->tz_episodes, pos);
drivers/thermal/thermal_debugfs.c
779
static void tze_seq_stop(struct seq_file *s, void *v)
drivers/thermal/thermal_debugfs.c
786
static int tze_seq_show(struct seq_file *s, void *v)
drivers/thermal/thermal_debugfs.c
796
tze = list_entry((struct list_head *)v, struct tz_episode, node);
drivers/thermal/ti-soc-thermal/ti-bandgap.c
1189
unsigned long cmd, void *v)
drivers/thermal/ti-soc-thermal/ti-bandgap.c
41
unsigned long cmd, void *v);
drivers/thunderbolt/debugfs.c
157
u32 v[5];
drivers/thunderbolt/debugfs.c
186
ret = sscanf(token, "%i %i %i %i %i", &v[0], &v[1], &v[2], &v[3], &v[4]);
drivers/thunderbolt/debugfs.c
189
*offs = v[0];
drivers/thunderbolt/debugfs.c
190
*val = v[short_fmt_len - 1];
drivers/thunderbolt/debugfs.c
193
*offs = v[0];
drivers/thunderbolt/debugfs.c
194
*val = v[long_fmt_len - 1];
drivers/thunderbolt/nvm.c
299
const struct tb_nvm_vendor *v = &switch_nvm_vendors[i];
drivers/thunderbolt/nvm.c
301
if (v->vendor == sw->config.vendor_id) {
drivers/thunderbolt/nvm.c
302
vops = v->vops;
drivers/thunderbolt/nvm.c
316
const struct tb_nvm_vendor *v = &retimer_nvm_vendors[i];
drivers/thunderbolt/nvm.c
318
if (v->vendor == rt->vendor) {
drivers/thunderbolt/nvm.c
319
vops = v->vops;
drivers/tty/amiserial.c
1413
static int rs_proc_show(struct seq_file *m, void *v)
drivers/tty/hvc/hvc_xen.c
258
uint64_t v = 0;
drivers/tty/hvc/hvc_xen.c
281
r = hvm_get_parameter(HVM_PARAM_CONSOLE_EVTCHN, &v);
drivers/tty/hvc/hvc_xen.c
282
if (r < 0 || v == 0)
drivers/tty/hvc/hvc_xen.c
284
info->evtchn = v;
drivers/tty/hvc/hvc_xen.c
285
v = 0;
drivers/tty/hvc/hvc_xen.c
286
r = hvm_get_parameter(HVM_PARAM_CONSOLE_PFN, &v);
drivers/tty/hvc/hvc_xen.c
287
if (r < 0 || v == 0)
drivers/tty/hvc/hvc_xen.c
289
gfn = v;
drivers/tty/hvc/hvc_xen.c
374
uint64_t v = 0;
drivers/tty/hvc/hvc_xen.c
377
err = hvm_get_parameter(HVM_PARAM_CONSOLE_EVTCHN, &v);
drivers/tty/hvc/hvc_xen.c
378
if (!err && v)
drivers/tty/hvc/hvc_xen.c
379
info->evtchn = v;
drivers/tty/serial/8250/8250_platform.c
53
void serial8250_set_isa_configurator(serial8250_isa_config_fn v)
drivers/tty/serial/8250/8250_platform.c
55
serial8250_isa_config = v;
drivers/tty/serial/apbuart.h
54
#define UART_PUT_CHAR(port, v) (__raw_writel(v, APBBASE_DATA_P(port)))
drivers/tty/serial/apbuart.h
56
#define UART_PUT_STATUS(port, v)(__raw_writel(v, APBBASE_STATUS_P(port)))
drivers/tty/serial/apbuart.h
58
#define UART_PUT_CTRL(port, v) (__raw_writel(v, APBBASE_CTRL_P(port)))
drivers/tty/serial/apbuart.h
60
#define UART_PUT_SCAL(port, v) (__raw_writel(v, APBBASE_SCALAR_P(port)))
drivers/tty/serial/arc_uart.c
69
#define UART_REG_SET(u, r, v) writeb((v), RBASE(u, r))
drivers/tty/serial/arc_uart.c
72
#define UART_REG_OR(u, r, v) UART_REG_SET(u, r, UART_REG_GET(u, r) | (v))
drivers/tty/serial/arc_uart.c
73
#define UART_REG_CLR(u, r, v) UART_REG_SET(u, r, UART_REG_GET(u, r) & ~(v))
drivers/tty/serial/esp32_acm.c
48
static void esp32s3_acm_write(struct uart_port *port, unsigned long reg, u32 v)
drivers/tty/serial/esp32_acm.c
50
writel(v, port->membase + reg);
drivers/tty/serial/esp32_uart.c
144
static void esp32_uart_write(struct uart_port *port, unsigned long reg, u32 v)
drivers/tty/serial/esp32_uart.c
146
writel(v, port->membase + reg);
drivers/tty/serial/mcf.c
44
#define mcf_setppdtr(p, v) do { } while (0)
drivers/tty/serial/mxs-auart.c
64
#define AUART_CTRL0_RXTIMEOUT(v) (((v) & 0x7ff) << 16)
drivers/tty/serial/mxs-auart.c
65
#define AUART_CTRL0_XFER_COUNT(v) ((v) & 0xffff)
drivers/tty/serial/mxs-auart.c
67
#define AUART_CTRL1_XFER_COUNT(v) ((v) & 0xffff)
drivers/tty/serial/mxs-auart.c
84
#define AUART_LINECTRL_BAUD_DIVINT(v) (((v) & 0xffff) << 16)
drivers/tty/serial/mxs-auart.c
87
#define AUART_LINECTRL_BAUD_DIVFRAC(v) (((v) & 0x3f) << 8)
drivers/tty/serial/mxs-auart.c
90
#define AUART_LINECTRL_WLEN(v) ((((v) - 5) & 0x3) << 5)
drivers/tty/serial/sa1100.c
53
#define UART_PUT_UTCR0(sport,v) __raw_writel((v),(sport)->port.membase + UTCR0)
drivers/tty/serial/sa1100.c
54
#define UART_PUT_UTCR1(sport,v) __raw_writel((v),(sport)->port.membase + UTCR1)
drivers/tty/serial/sa1100.c
55
#define UART_PUT_UTCR2(sport,v) __raw_writel((v),(sport)->port.membase + UTCR2)
drivers/tty/serial/sa1100.c
56
#define UART_PUT_UTCR3(sport,v) __raw_writel((v),(sport)->port.membase + UTCR3)
drivers/tty/serial/sa1100.c
57
#define UART_PUT_UTSR0(sport,v) __raw_writel((v),(sport)->port.membase + UTSR0)
drivers/tty/serial/sa1100.c
58
#define UART_PUT_UTSR1(sport,v) __raw_writel((v),(sport)->port.membase + UTSR1)
drivers/tty/serial/sa1100.c
59
#define UART_PUT_CHAR(sport,v) __raw_writel((v),(sport)->port.membase + UTDR)
drivers/tty/serial/sccnxp.c
235
static void sccnxp_write(struct uart_port *port, u8 reg, u8 v)
drivers/tty/serial/sccnxp.c
239
writeb(v, port->membase + (reg << port->regshift));
drivers/tty/serial/sccnxp.c
249
static void sccnxp_port_write(struct uart_port *port, u8 reg, u8 v)
drivers/tty/serial/sccnxp.c
251
sccnxp_write(port, (port->line << 3) + reg, v);
drivers/tty/serial/serial_core.c
2048
static int uart_proc_show(struct seq_file *m, void *v)
drivers/tty/serial/sh-sci.c
1367
int v;
drivers/tty/serial/sh-sci.c
1370
v = sci->hscif_tot >> HSSCR_TOT_SHIFT;
drivers/tty/serial/sh-sci.c
1372
v = sci->rx_fifo_timeout;
drivers/tty/serial/sh-sci.c
1374
return sprintf(buf, "%d\n", v);
drivers/tty/serial/sifive.c
191
static void __ssp_early_writel(u32 v, u16 offs, struct uart_port *port)
drivers/tty/serial/sifive.c
193
writel_relaxed(v, port->membase + offs);
drivers/tty/serial/sifive.c
227
static void __ssp_writel(u32 v, u16 offs, struct sifive_serial_port *ssp)
drivers/tty/serial/sifive.c
229
__ssp_early_writel(v, offs, &ssp->port);
drivers/tty/serial/sifive.c
379
u32 v;
drivers/tty/serial/sifive.c
382
v = __ssp_readl(ssp, SIFIVE_SERIAL_RXDATA_OFFS);
drivers/tty/serial/sifive.c
387
*is_empty = (v & SIFIVE_SERIAL_RXDATA_EMPTY_MASK) >>
drivers/tty/serial/sifive.c
390
ch = (v & SIFIVE_SERIAL_RXDATA_DATA_MASK) >>
drivers/tty/serial/sifive.c
470
u32 v;
drivers/tty/serial/sifive.c
477
v = __ssp_readl(ssp, SIFIVE_SERIAL_TXCTRL_OFFS);
drivers/tty/serial/sifive.c
478
v &= ~SIFIVE_SERIAL_TXCTRL_NSTOP_MASK;
drivers/tty/serial/sifive.c
479
v |= (nstop - 1) << SIFIVE_SERIAL_TXCTRL_NSTOP_SHIFT;
drivers/tty/serial/sifive.c
480
__ssp_writel(v, SIFIVE_SERIAL_TXCTRL_OFFS, ssp);
drivers/tty/serial/sifive.c
641
u32 v, old_v;
drivers/tty/serial/sifive.c
673
v = __ssp_readl(ssp, SIFIVE_SERIAL_RXCTRL_OFFS);
drivers/tty/serial/sifive.c
674
old_v = v;
drivers/tty/serial/sifive.c
676
v &= SIFIVE_SERIAL_RXCTRL_RXEN_MASK;
drivers/tty/serial/sifive.c
678
v |= SIFIVE_SERIAL_RXCTRL_RXEN_MASK;
drivers/tty/serial/sifive.c
679
if (v != old_v)
drivers/tty/serial/sifive.c
680
__ssp_writel(v, SIFIVE_SERIAL_RXCTRL_OFFS, ssp);
drivers/tty/synclink_gt.c
1233
static int synclink_gt_proc_show(struct seq_file *m, void *v)
drivers/tty/tty_io.c
2631
struct serial_struct v;
drivers/tty/tty_io.c
2633
if (copy_from_user(&v, ss, sizeof(*ss)))
drivers/tty/tty_io.c
2636
return tty_set_serial(tty, &v);
drivers/tty/tty_io.c
2641
struct serial_struct v;
drivers/tty/tty_io.c
2644
memset(&v, 0, sizeof(v));
drivers/tty/tty_io.c
2647
err = tty->ops->get_serial(tty, &v);
drivers/tty/tty_io.c
2648
if (!err && copy_to_user(ss, &v, sizeof(v)))
drivers/tty/tty_io.c
2837
struct serial_struct v;
drivers/tty/tty_io.c
2842
memcpy(&v, &v32, offsetof(struct serial_struct32, iomem_base));
drivers/tty/tty_io.c
2843
v.iomem_base = compat_ptr(v32.iomem_base);
drivers/tty/tty_io.c
2844
v.iomem_reg_shift = v32.iomem_reg_shift;
drivers/tty/tty_io.c
2845
v.port_high = v32.port_high;
drivers/tty/tty_io.c
2846
v.iomap_base = 0;
drivers/tty/tty_io.c
2848
return tty_set_serial(tty, &v);
drivers/tty/tty_io.c
2855
struct serial_struct v;
drivers/tty/tty_io.c
2858
memset(&v, 0, sizeof(v));
drivers/tty/tty_io.c
2863
err = tty->ops->get_serial(tty, &v);
drivers/tty/tty_io.c
2865
memcpy(&v32, &v, offsetof(struct serial_struct32, iomem_base));
drivers/tty/tty_io.c
2866
v32.iomem_base = (unsigned long)v.iomem_base >> 32 ?
drivers/tty/tty_io.c
2867
0xfffffff : ptr_to_compat(v.iomem_base);
drivers/tty/tty_io.c
2868
v32.iomem_reg_shift = v.iomem_reg_shift;
drivers/tty/tty_io.c
2869
v32.port_high = v.port_high;
drivers/tty/tty_ioctl.c
363
struct termio v;
drivers/tty/tty_ioctl.c
365
if (copy_from_user(&v, termio, sizeof(struct termio)))
drivers/tty/tty_ioctl.c
368
termios->c_iflag = (0xffff0000 & termios->c_iflag) | v.c_iflag;
drivers/tty/tty_ioctl.c
369
termios->c_oflag = (0xffff0000 & termios->c_oflag) | v.c_oflag;
drivers/tty/tty_ioctl.c
370
termios->c_cflag = (0xffff0000 & termios->c_cflag) | v.c_cflag;
drivers/tty/tty_ioctl.c
371
termios->c_lflag = (0xffff0000 & termios->c_lflag) | v.c_lflag;
drivers/tty/tty_ioctl.c
372
termios->c_line = (0xffff0000 & termios->c_lflag) | v.c_line;
drivers/tty/tty_ioctl.c
373
memcpy(termios->c_cc, v.c_cc, NCC);
drivers/tty/tty_ioctl.c
383
struct termio v;
drivers/tty/tty_ioctl.c
384
memset(&v, 0, sizeof(struct termio));
drivers/tty/tty_ioctl.c
385
v.c_iflag = termios->c_iflag;
drivers/tty/tty_ioctl.c
386
v.c_oflag = termios->c_oflag;
drivers/tty/tty_ioctl.c
387
v.c_cflag = termios->c_cflag;
drivers/tty/tty_ioctl.c
388
v.c_lflag = termios->c_lflag;
drivers/tty/tty_ioctl.c
389
v.c_line = termios->c_line;
drivers/tty/tty_ioctl.c
390
memcpy(v.c_cc, termios->c_cc, NCC);
drivers/tty/tty_ioctl.c
391
return copy_to_user(termio, &v, sizeof(struct termio));
drivers/tty/tty_ldisc.c
192
static void *tty_ldiscs_seq_next(struct seq_file *m, void *v, loff_t *pos)
drivers/tty/tty_ldisc.c
198
static void tty_ldiscs_seq_stop(struct seq_file *m, void *v)
drivers/tty/tty_ldisc.c
202
static int tty_ldiscs_seq_show(struct seq_file *m, void *v)
drivers/tty/tty_ldisc.c
204
int i = *(loff_t *)v;
drivers/tty/vt/selection.c
189
struct tiocl_selection v;
drivers/tty/vt/selection.c
191
if (copy_from_user(&v, sel, sizeof(*sel)))
drivers/tty/vt/selection.c
198
switch (v.sel_mode) {
drivers/tty/vt/selection.c
207
return set_selection_kernel(&v, tty);
drivers/tty/vt/selection.c
338
static int vc_selection(struct vc_data *vc, struct tiocl_selection *v,
drivers/tty/vt/selection.c
345
if (v->sel_mode == TIOCL_SELCLEAR) {
drivers/tty/vt/selection.c
352
v->xs = umin(v->xs - 1, vc->vc_cols - 1);
drivers/tty/vt/selection.c
353
v->ys = umin(v->ys - 1, vc->vc_rows - 1);
drivers/tty/vt/selection.c
354
v->xe = umin(v->xe - 1, vc->vc_cols - 1);
drivers/tty/vt/selection.c
355
v->ye = umin(v->ye - 1, vc->vc_rows - 1);
drivers/tty/vt/selection.c
357
if (mouse_reporting() && (v->sel_mode & TIOCL_SELMOUSEREPORT)) {
drivers/tty/vt/selection.c
358
mouse_report(tty, v->sel_mode & TIOCL_SELBUTTONMASK, v->xs,
drivers/tty/vt/selection.c
359
v->ys);
drivers/tty/vt/selection.c
363
ps = v->ys * vc->vc_size_row + (v->xs << 1);
drivers/tty/vt/selection.c
364
pe = v->ye * vc->vc_size_row + (v->xe << 1);
drivers/tty/vt/selection.c
373
return vc_do_selection(vc, v->sel_mode, ps, pe);
drivers/tty/vt/selection.c
376
int set_selection_kernel(struct tiocl_selection *v, struct tty_struct *tty)
drivers/tty/vt/selection.c
380
return vc_selection(vc_cons[fg_console].d, v, tty);
drivers/tty/vt/vt_ioctl.c
664
struct vt_consize v;
drivers/tty/vt/vt_ioctl.c
667
if (copy_from_user(&v, cs, sizeof(struct vt_consize)))
drivers/tty/vt/vt_ioctl.c
671
if (!v.v_vlin)
drivers/tty/vt/vt_ioctl.c
672
v.v_vlin = vc->vc_scan_lines;
drivers/tty/vt/vt_ioctl.c
674
if (v.v_clin) {
drivers/tty/vt/vt_ioctl.c
675
int rows = v.v_vlin / v.v_clin;
drivers/tty/vt/vt_ioctl.c
676
if (v.v_rows != rows) {
drivers/tty/vt/vt_ioctl.c
677
if (v.v_rows) /* Parameters don't add up */
drivers/tty/vt/vt_ioctl.c
679
v.v_rows = rows;
drivers/tty/vt/vt_ioctl.c
683
if (v.v_vcol && v.v_ccol) {
drivers/tty/vt/vt_ioctl.c
684
int cols = v.v_vcol / v.v_ccol;
drivers/tty/vt/vt_ioctl.c
685
if (v.v_cols != cols) {
drivers/tty/vt/vt_ioctl.c
686
if (v.v_cols)
drivers/tty/vt/vt_ioctl.c
688
v.v_cols = cols;
drivers/tty/vt/vt_ioctl.c
692
if (v.v_clin > 32)
drivers/tty/vt/vt_ioctl.c
707
if (v.v_vlin)
drivers/tty/vt/vt_ioctl.c
708
vcp->vc_scan_lines = v.v_vlin;
drivers/tty/vt/vt_ioctl.c
709
if (v.v_clin)
drivers/tty/vt/vt_ioctl.c
710
vcp->vc_cell_height = v.v_clin;
drivers/tty/vt/vt_ioctl.c
711
ret = __vc_resize(vcp, v.v_cols, v.v_rows, true);
drivers/ufs/core/ufshcd.c
789
u32 v;
drivers/ufs/core/ufshcd.c
793
return read_poll_timeout(ufshcd_readl, v, (v & mask) == val,
drivers/ufs/host/ufs-exynos.c
49
#define UNIPRO_APB_CLK(v, x) (((v) & ~0xF) | ((x) & 0xF))
drivers/ufs/host/ufs-exynos.h
100
#define RX_OV_SLEEP_CNT(v) (((v) >> 6) & 0x1F)
drivers/ufs/host/ufs-exynos.h
102
#define RX_OV_STALL_CNT(v) (((v) >> 4) & 0xFF)
drivers/ufs/host/ufs-exynos.h
104
#define RX_BASE_NVAL_L(v) ((v) & 0xFF)
drivers/ufs/host/ufs-exynos.h
106
#define RX_BASE_NVAL_H(v) (((v) >> 8) & 0xFF)
drivers/ufs/host/ufs-exynos.h
108
#define RX_GRAN_NVAL_L(v) ((v) & 0xFF)
drivers/ufs/host/ufs-exynos.h
110
#define RX_GRAN_NVAL_H(v) (((v) >> 8) & 0x3)
drivers/ufs/host/ufs-exynos.h
55
#define TX_LINERESET_N(v) (((v) >> 10) & 0xFF)
drivers/ufs/host/ufs-exynos.h
57
#define TX_LINERESET_P(v) (((v) >> 12) & 0xFF)
drivers/ufs/host/ufs-exynos.h
60
#define TX_OV_SLEEP_CNT(v) (((v) >> 5) & 0x7F)
drivers/ufs/host/ufs-exynos.h
62
#define TX_HIGH_Z_CNT_H(v) (((v) >> 8) & 0xF)
drivers/ufs/host/ufs-exynos.h
64
#define TX_HIGH_Z_CNT_L(v) ((v) & 0xFF)
drivers/ufs/host/ufs-exynos.h
66
#define TX_BASE_NVAL_L(v) ((v) & 0xFF)
drivers/ufs/host/ufs-exynos.h
68
#define TX_BASE_NVAL_H(v) (((v) >> 8) & 0xFF)
drivers/ufs/host/ufs-exynos.h
70
#define TX_GRAN_NVAL_L(v) ((v) & 0xFF)
drivers/ufs/host/ufs-exynos.h
72
#define TX_GRAN_NVAL_H(v) (((v) >> 8) & 0x3)
drivers/ufs/host/ufs-exynos.h
93
#define RX_LINERESET(v) (((v) >> 12) & 0xFF)
drivers/ufs/host/ufshcd-dwc.c
19
const struct ufshcd_dme_attr_val *v, int n)
drivers/ufs/host/ufshcd-dwc.c
25
ret = ufshcd_dme_set_attr(hba, v[attr_node].attr_sel,
drivers/ufs/host/ufshcd-dwc.c
26
ATTR_SET_NOR, v[attr_node].mib_val, v[attr_node].peer);
drivers/ufs/host/ufshcd-dwc.h
70
const struct ufshcd_dme_attr_val *v, int n);
drivers/usb/chipidea/usbmisc_imx.c
100
#define MX7D_USB_VBUS_WAKEUP_SOURCE(v) (v << 0)
drivers/usb/chipidea/usbmisc_imx.c
107
#define MX7D_USBNC_USB_CTRL2_OPMODE(v) (v << 6)
drivers/usb/chipidea/usbmisc_imx.c
90
#define MX6SX_USB_VBUS_WAKEUP_SOURCE(v) (v << 8)
drivers/usb/dwc2/debugfs.c
126
static int state_show(struct seq_file *seq, void *v)
drivers/usb/dwc2/debugfs.c
183
static int fifo_show(struct seq_file *seq, void *v)
drivers/usb/dwc2/debugfs.c
225
static int ep_show(struct seq_file *seq, void *v)
drivers/usb/dwc2/debugfs.c
667
static int params_show(struct seq_file *seq, void *v)
drivers/usb/dwc2/debugfs.c
729
static int hw_params_show(struct seq_file *seq, void *v)
drivers/usb/dwc2/debugfs.c
764
static int dr_mode_show(struct seq_file *seq, void *v)
drivers/usb/fotg210/fotg210-hcd.c
341
__u32 v = hc32_to_cpu(fotg210, token);
drivers/usb/fotg210/fotg210-hcd.c
343
if (v & QTD_STS_ACTIVE)
drivers/usb/fotg210/fotg210-hcd.c
345
if (v & QTD_STS_HALT)
drivers/usb/fotg210/fotg210-hcd.c
347
if (!IS_SHORT_READ(v))
drivers/usb/gadget/function/f_midi2.c
154
#define to_ump_protocol(v) (((v) & 3) << 8)
drivers/usb/gadget/function/rndis.c
1099
static int rndis_proc_show(struct seq_file *m, void *v)
drivers/usb/gadget/function/rndis.c
587
params->resp_avail(params->v);
drivers/usb/gadget/function/rndis.c
629
params->resp_avail(params->v);
drivers/usb/gadget/function/rndis.c
673
params->resp_avail(params->v);
drivers/usb/gadget/function/rndis.c
700
params->resp_avail(params->v);
drivers/usb/gadget/function/rndis.c
722
params->resp_avail(params->v);
drivers/usb/gadget/function/rndis.c
749
params->resp_avail(params->v);
drivers/usb/gadget/function/rndis.c
880
struct rndis_params *rndis_register(void (*resp_avail)(void *v), void *v)
drivers/usb/gadget/function/rndis.c
924
params->v = v;
drivers/usb/gadget/function/rndis.h
174
void (*resp_avail)(void *v);
drivers/usb/gadget/function/rndis.h
175
void *v;
drivers/usb/gadget/function/rndis.h
182
struct rndis_params *rndis_register(void (*resp_avail)(void *v), void *v);
drivers/usb/gadget/udc/fsl_udc_core.c
100
out_be32(p, v);
drivers/usb/gadget/udc/fsl_udc_core.c
103
static void _fsl_writel_le(u32 v, unsigned __iomem *p)
drivers/usb/gadget/udc/fsl_udc_core.c
105
out_le32(p, v);
drivers/usb/gadget/udc/fsl_udc_core.c
109
static void (*_fsl_writel)(u32 v, unsigned __iomem *p);
drivers/usb/gadget/udc/fsl_udc_core.c
112
#define fsl_writel(v, p) (*_fsl_writel)((v), (p))
drivers/usb/gadget/udc/fsl_udc_core.c
2026
static int fsl_proc_read(struct seq_file *m, void *v)
drivers/usb/gadget/udc/fsl_udc_core.c
98
static void _fsl_writel_be(u32 v, unsigned __iomem *p)
drivers/usb/gadget/udc/goku_udc.c
1137
static int udc_proc_read(struct seq_file *m, void *v)
drivers/usb/gadget/udc/gr_udc.c
181
static int gr_dfs_show(struct seq_file *seq, void *v)
drivers/usb/gadget/udc/gr_udc.c
52
#define gr_write32(x, v) (iowrite32be((v), (x)))
drivers/usb/gadget/udc/m66592-udc.h
284
#define M66592_GET_DT_TYPE(v) (((v) & DT_TYPE) >> 8)
drivers/usb/host/ehci-dbg.c
358
__u32 v = hc32_to_cpu(ehci, token);
drivers/usb/host/ehci-dbg.c
360
if (v & QTD_STS_ACTIVE)
drivers/usb/host/ehci-dbg.c
362
if (v & QTD_STS_HALT)
drivers/usb/host/ehci-dbg.c
364
if (!IS_SHORT_READ(v))
drivers/usb/host/fhci-dbg.c
37
static int fhci_dfs_regs_show(struct seq_file *s, void *v)
drivers/usb/host/fhci-dbg.c
60
static int fhci_dfs_irq_stat_show(struct seq_file *s, void *v)
drivers/usb/host/isp116x.h
187
#define PTD_COUNT(v) (((v) << 0) & PTD_COUNT_MSK)
drivers/usb/host/isp116x.h
189
#define PTD_TOGGLE(v) (((v) << 10) & PTD_TOGGLE_MSK)
drivers/usb/host/isp116x.h
191
#define PTD_ACTIVE(v) (((v) << 11) & PTD_ACTIVE_MSK)
drivers/usb/host/isp116x.h
193
#define PTD_CC(v) (((v) << 12) & PTD_CC_MSK)
drivers/usb/host/isp116x.h
195
#define PTD_MPS(v) (((v) << 0) & PTD_MPS_MSK)
drivers/usb/host/isp116x.h
197
#define PTD_SPD(v) (((v) << 10) & PTD_SPD_MSK)
drivers/usb/host/isp116x.h
199
#define PTD_LAST(v) (((v) << 11) & PTD_LAST_MSK)
drivers/usb/host/isp116x.h
201
#define PTD_EP(v) (((v) << 12) & PTD_EP_MSK)
drivers/usb/host/isp116x.h
203
#define PTD_LEN(v) (((v) << 0) & PTD_LEN_MSK)
drivers/usb/host/isp116x.h
205
#define PTD_DIR(v) (((v) << 10) & PTD_DIR_MSK)
drivers/usb/host/isp116x.h
207
#define PTD_B5_5(v) (((v) << 13) & PTD_B5_5_MSK)
drivers/usb/host/isp116x.h
209
#define PTD_FA(v) (((v) << 0) & PTD_FA_MSK)
drivers/usb/host/isp116x.h
211
#define PTD_FMT(v) (((v) << 7) & PTD_FMT_MSK)
drivers/usb/host/ohci.h
586
#define ohci_writel(o,v,r) _ohci_writel(o,v,r)
drivers/usb/musb/tusb6010.h
188
#define TUSB_INT_CTRL_CONF_INT_RELCYC(v) (((v) & 0x7) << 18)
drivers/usb/musb/tusb6010.h
191
#define TUSB_GPIO_CONF_DMAREQ(v) (((v) & 0x3f) << 24)
drivers/usb/musb/tusb6010.h
192
#define TUSB_DMA_REQ_CONF_BURST_SIZE(v) (((v) & 3) << 26)
drivers/usb/musb/tusb6010.h
193
#define TUSB_DMA_REQ_CONF_DMA_REQ_EN(v) (((v) & 0x3f) << 20)
drivers/usb/musb/tusb6010.h
194
#define TUSB_DMA_REQ_CONF_DMA_REQ_ASSER(v) (((v) & 0xf) << 16)
drivers/usb/musb/tusb6010.h
197
#define TUSB_EP0_CONFIG_XFR_SIZE(v) ((v) & 0x7f)
drivers/usb/musb/tusb6010.h
199
#define TUSB_EP_CONFIG_XFR_SIZE(v) ((v) & 0x7fffffff)
drivers/usb/musb/tusb6010.h
205
#define TUSB_DIDR1_HI_CHIP_REV(v) (((v) >> 17) & 0xf)
drivers/usb/musb/tusb6010.h
45
#define TUSB_PHY_OTG_CTRL_PHYREF_CLKSEL(v) (((v) & 3) << 7)
drivers/usb/musb/tusb6010.h
69
# define TUSB_DEV_OTG_TIMER_VAL(v) ((v) & 0x07ffffff)
drivers/usb/musb/tusb6010.h
75
#define TUSB_PRCM_CONF_SYS_CLKSEL(v) (((v) & 3) << 16)
drivers/usb/musb/tusb6010.h
79
#define TUSB_PRCM_MNGMT_SRP_FIX_TIMER(v) (((v) & 0xf) << 25)
drivers/usb/musb/tusb6010.h
81
#define TUSB_PRCM_MNGMT_VBUS_VALID_TIMER(v) (((v) & 0xf) << 20)
drivers/usb/phy/phy-fsl-usb.c
84
static void _fsl_writel_be(u32 v, unsigned __iomem *p)
drivers/usb/phy/phy-fsl-usb.c
86
out_be32(p, v);
drivers/usb/phy/phy-fsl-usb.c
89
static void _fsl_writel_le(u32 v, unsigned __iomem *p)
drivers/usb/phy/phy-fsl-usb.c
91
out_le32(p, v);
drivers/usb/phy/phy-fsl-usb.c
95
static void (*_fsl_writel)(u32 v, unsigned __iomem *p);
drivers/usb/phy/phy-fsl-usb.c
98
#define fsl_writel(v, p) (*_fsl_writel)((v), (p))
drivers/usb/serial/belkin_sa.c
108
#define BSA_USB_CMD(c, v) usb_control_msg(serial->dev, usb_sndctrlpipe(serial->dev, 0), \
drivers/usb/serial/belkin_sa.c
110
(v), 0, NULL, 0, WDR_TIMEOUT)
drivers/usb/serial/ftdi_sio.c
1646
u8 v;
drivers/usb/serial/ftdi_sio.c
1649
if (kstrtou8(valbuf, 10, &v))
drivers/usb/serial/ftdi_sio.c
1652
priv->latency = v;
drivers/usb/serial/ftdi_sio.c
1668
unsigned int v;
drivers/usb/serial/ftdi_sio.c
1671
if (kstrtouint(valbuf, 0, &v) || v >= 0x200)
drivers/usb/serial/ftdi_sio.c
1674
dev_dbg(&port->dev, "%s: setting event char = 0x%03x\n", __func__, v);
drivers/usb/serial/ftdi_sio.c
1680
v, priv->channel,
drivers/usb/serial/io_ti.c
2626
unsigned int v = simple_strtoul(valbuf, NULL, 0);
drivers/usb/serial/io_ti.c
2628
dev_dbg(dev, "%s: setting uart_mode = %d\n", __func__, v);
drivers/usb/serial/io_ti.c
2630
if (v < 256)
drivers/usb/serial/io_ti.c
2631
edge_port->bUartMode = v;
drivers/usb/serial/io_ti.c
2633
dev_err(dev, "%s - uart_mode %d is invalid\n", __func__, v);
drivers/usb/serial/iuu_phoenix.c
1122
unsigned long v;
drivers/usb/serial/iuu_phoenix.c
1124
if (kstrtoul(buf, 10, &v)) {
drivers/usb/serial/iuu_phoenix.c
1130
dev_dbg(dev, "%s: setting vcc_mode = %ld\n", __func__, v);
drivers/usb/serial/iuu_phoenix.c
1132
if ((v != 3) && (v != 5)) {
drivers/usb/serial/iuu_phoenix.c
1133
dev_err(dev, "%s - vcc_mode %ld is invalid\n", __func__, v);
drivers/usb/serial/iuu_phoenix.c
1135
iuu_vcc_set(port, v);
drivers/usb/serial/iuu_phoenix.c
1136
priv->vcc = v;
drivers/usb/serial/qcserial.c
31
#define DEVICE_G1K(v, p) \
drivers/usb/serial/qcserial.c
32
USB_DEVICE(v, p), .driver_info = QCSERIAL_G1K
drivers/usb/serial/qcserial.c
33
#define DEVICE_SWI(v, p) \
drivers/usb/serial/qcserial.c
34
USB_DEVICE(v, p), .driver_info = QCSERIAL_SWI
drivers/usb/serial/qcserial.c
35
#define DEVICE_HWI(v, p) \
drivers/usb/serial/qcserial.c
36
USB_DEVICE(v, p), .driver_info = QCSERIAL_HWI
drivers/usb/serial/usb-serial.c
546
static int serial_proc_show(struct seq_file *m, void *v)
drivers/usb/typec/tcpm/fusb302.c
193
static int fusb302_debug_show(struct seq_file *s, void *v)
drivers/usb/typec/tcpm/tcpm.c
855
static int tcpm_debug_show(struct seq_file *s, void *v)
drivers/usb/typec/ucsi/debugfs.c
104
static int ucsi_vbus_volt_show(struct seq_file *m, void *v)
drivers/usb/typec/ucsi/debugfs.c
86
static int ucsi_peak_curr_show(struct seq_file *m, void *v)
drivers/usb/typec/ucsi/debugfs.c
95
static int ucsi_avg_curr_show(struct seq_file *m, void *v)
drivers/vdpa/pds/debugfs.c
175
static int identity_show(struct seq_file *seq, void *v)
drivers/vdpa/pds/debugfs.c
201
static int config_show(struct seq_file *seq, void *v)
drivers/vdpa/pds/debugfs.c
236
static int vq_show(struct seq_file *seq, void *v)
drivers/vhost/vdpa.c
1009
if (!v->in_batch)
drivers/vhost/vdpa.c
1012
r = iommu_map(v->domain, iova, pa, size,
drivers/vhost/vdpa.c
102
static struct vhost_vdpa_as *vhost_vdpa_alloc_as(struct vhost_vdpa *v, u32 asid)
drivers/vhost/vdpa.c
1027
static void vhost_vdpa_unmap(struct vhost_vdpa *v,
drivers/vhost/vdpa.c
1031
struct vdpa_device *vdpa = v->vdpa;
drivers/vhost/vdpa.c
1035
vhost_vdpa_iotlb_unmap(v, iotlb, iova, iova + size - 1, asid);
drivers/vhost/vdpa.c
1038
if (!v->in_batch)
drivers/vhost/vdpa.c
104
struct hlist_head *head = &v->as[asid % VHOST_VDPA_IOTLB_BUCKETS];
drivers/vhost/vdpa.c
1044
static int vhost_vdpa_va_map(struct vhost_vdpa *v,
drivers/vhost/vdpa.c
1048
struct vhost_dev *dev = &v->vdev;
drivers/vhost/vdpa.c
107
if (asid_to_as(v, asid))
drivers/vhost/vdpa.c
1075
ret = vhost_vdpa_map(v, iotlb, map_iova, map_size, uaddr,
drivers/vhost/vdpa.c
1088
vhost_vdpa_unmap(v, iotlb, iova, map_iova - iova);
drivers/vhost/vdpa.c
1095
static int vhost_vdpa_pa_map(struct vhost_vdpa *v,
drivers/vhost/vdpa.c
1099
struct vhost_dev *dev = &v->vdev;
drivers/vhost/vdpa.c
110
if (asid >= v->vdpa->nas)
drivers/vhost/vdpa.c
1160
ret = vhost_vdpa_map(v, iotlb, iova, csize,
drivers/vhost/vdpa.c
1190
ret = vhost_vdpa_map(v, iotlb, iova, PFN_PHYS(last_pfn - map_pfn + 1),
drivers/vhost/vdpa.c
1210
vhost_vdpa_unmap(v, iotlb, start, size);
drivers/vhost/vdpa.c
1220
static int vhost_vdpa_process_iotlb_update(struct vhost_vdpa *v,
drivers/vhost/vdpa.c
1224
struct vdpa_device *vdpa = v->vdpa;
drivers/vhost/vdpa.c
1226
if (msg->iova < v->range.first || !msg->size ||
drivers/vhost/vdpa.c
1228
msg->iova + msg->size - 1 > v->range.last)
drivers/vhost/vdpa.c
1236
return vhost_vdpa_va_map(v, iotlb, msg->iova, msg->size,
drivers/vhost/vdpa.c
1239
return vhost_vdpa_pa_map(v, iotlb, msg->iova, msg->size, msg->uaddr,
drivers/vhost/vdpa.c
124
static struct vhost_vdpa_as *vhost_vdpa_find_alloc_as(struct vhost_vdpa *v,
drivers/vhost/vdpa.c
1246
struct vhost_vdpa *v = container_of(dev, struct vhost_vdpa, vdev);
drivers/vhost/vdpa.c
1247
struct vdpa_device *vdpa = v->vdpa;
drivers/vhost/vdpa.c
1261
as = vhost_vdpa_find_alloc_as(v, asid);
drivers/vhost/vdpa.c
1263
dev_err(&v->dev, "can't find and alloc asid %d\n",
drivers/vhost/vdpa.c
127
struct vhost_vdpa_as *as = asid_to_as(v, asid);
drivers/vhost/vdpa.c
1270
iotlb = asid_to_iotlb(v, asid);
drivers/vhost/vdpa.c
1272
if ((v->in_batch && v->batch_asid != asid) || !iotlb) {
drivers/vhost/vdpa.c
1273
if (v->in_batch && v->batch_asid != asid) {
drivers/vhost/vdpa.c
1274
dev_info(&v->dev, "batch id %d asid %d\n",
drivers/vhost/vdpa.c
1275
v->batch_asid, asid);
drivers/vhost/vdpa.c
1278
dev_err(&v->dev, "no iotlb for asid %d\n", asid);
drivers/vhost/vdpa.c
1285
r = vhost_vdpa_process_iotlb_update(v, iotlb, msg);
drivers/vhost/vdpa.c
1288
vhost_vdpa_unmap(v, iotlb, msg->iova, msg->size);
drivers/vhost/vdpa.c
1291
v->batch_asid = asid;
drivers/vhost/vdpa.c
1292
v->in_batch = true;
drivers/vhost/vdpa.c
1295
if (v->in_batch && ops->set_map)
drivers/vhost/vdpa.c
1297
v->in_batch = false;
drivers/vhost/vdpa.c
1313
struct vhost_vdpa *v = file->private_data;
drivers/vhost/vdpa.c
1314
struct vhost_dev *dev = &v->vdev;
drivers/vhost/vdpa.c
1319
static int vhost_vdpa_alloc_domain(struct vhost_vdpa *v)
drivers/vhost/vdpa.c
132
return vhost_vdpa_alloc_as(v, asid);
drivers/vhost/vdpa.c
1321
struct vdpa_device *vdpa = v->vdpa;
drivers/vhost/vdpa.c
1332
dev_warn_once(&v->dev,
drivers/vhost/vdpa.c
1337
v->domain = iommu_paging_domain_alloc(dma_dev);
drivers/vhost/vdpa.c
1338
if (IS_ERR(v->domain)) {
drivers/vhost/vdpa.c
1339
ret = PTR_ERR(v->domain);
drivers/vhost/vdpa.c
1340
v->domain = NULL;
drivers/vhost/vdpa.c
1344
ret = iommu_attach_device(v->domain, dma_dev);
drivers/vhost/vdpa.c
135
static void vhost_vdpa_reset_map(struct vhost_vdpa *v, u32 asid)
drivers/vhost/vdpa.c
1351
iommu_domain_free(v->domain);
drivers/vhost/vdpa.c
1352
v->domain = NULL;
drivers/vhost/vdpa.c
1356
static void vhost_vdpa_free_domain(struct vhost_vdpa *v)
drivers/vhost/vdpa.c
1358
struct vdpa_device *vdpa = v->vdpa;
drivers/vhost/vdpa.c
1362
if (v->domain) {
drivers/vhost/vdpa.c
1363
iommu_detach_device(v->domain, dma_dev);
drivers/vhost/vdpa.c
1364
iommu_domain_free(v->domain);
drivers/vhost/vdpa.c
1367
v->domain = NULL;
drivers/vhost/vdpa.c
137
struct vdpa_device *vdpa = v->vdpa;
drivers/vhost/vdpa.c
1370
static void vhost_vdpa_set_iova_range(struct vhost_vdpa *v)
drivers/vhost/vdpa.c
1372
struct vdpa_iova_range *range = &v->range;
drivers/vhost/vdpa.c
1373
struct vdpa_device *vdpa = v->vdpa;
drivers/vhost/vdpa.c
1378
} else if (v->domain && v->domain->geometry.force_aperture) {
drivers/vhost/vdpa.c
1379
range->first = v->domain->geometry.aperture_start;
drivers/vhost/vdpa.c
1380
range->last = v->domain->geometry.aperture_end;
drivers/vhost/vdpa.c
1387
static void vhost_vdpa_cleanup(struct vhost_vdpa *v)
drivers/vhost/vdpa.c
1392
for (asid = 0; asid < v->vdpa->nas; asid++) {
drivers/vhost/vdpa.c
1393
as = asid_to_as(v, asid);
drivers/vhost/vdpa.c
1395
vhost_vdpa_remove_as(v, asid);
drivers/vhost/vdpa.c
1398
vhost_vdpa_free_domain(v);
drivers/vhost/vdpa.c
1399
vhost_dev_cleanup(&v->vdev);
drivers/vhost/vdpa.c
1400
kfree(v->vdev.vqs);
drivers/vhost/vdpa.c
1401
v->vdev.vqs = NULL;
drivers/vhost/vdpa.c
1406
struct vhost_vdpa *v;
drivers/vhost/vdpa.c
1412
v = container_of(inode->i_cdev, struct vhost_vdpa, cdev);
drivers/vhost/vdpa.c
1414
opened = atomic_cmpxchg(&v->opened, 0, 1);
drivers/vhost/vdpa.c
1418
nvqs = v->nvqs;
drivers/vhost/vdpa.c
1419
r = vhost_vdpa_reset(v);
drivers/vhost/vdpa.c
1429
dev = &v->vdev;
drivers/vhost/vdpa.c
1431
vqs[i] = &v->vqs[i];
drivers/vhost/vdpa.c
1438
r = vhost_vdpa_alloc_domain(v);
drivers/vhost/vdpa.c
144
static int vhost_vdpa_remove_as(struct vhost_vdpa *v, u32 asid)
drivers/vhost/vdpa.c
1442
vhost_vdpa_set_iova_range(v);
drivers/vhost/vdpa.c
1444
filep->private_data = v;
drivers/vhost/vdpa.c
1449
vhost_vdpa_cleanup(v);
drivers/vhost/vdpa.c
1451
atomic_dec(&v->opened);
drivers/vhost/vdpa.c
1455
static void vhost_vdpa_clean_irq(struct vhost_vdpa *v)
drivers/vhost/vdpa.c
1459
for (i = 0; i < v->nvqs; i++)
drivers/vhost/vdpa.c
146
struct vhost_vdpa_as *as = asid_to_as(v, asid);
drivers/vhost/vdpa.c
1460
vhost_vdpa_unsetup_vq_irq(v, i);
drivers/vhost/vdpa.c
1465
struct vhost_vdpa *v = filep->private_data;
drivers/vhost/vdpa.c
1466
struct vhost_dev *d = &v->vdev;
drivers/vhost/vdpa.c
1470
vhost_vdpa_clean_irq(v);
drivers/vhost/vdpa.c
1471
vhost_vdpa_reset(v);
drivers/vhost/vdpa.c
1472
vhost_dev_stop(&v->vdev);
drivers/vhost/vdpa.c
1473
vhost_vdpa_unbind_mm(v);
drivers/vhost/vdpa.c
1474
vhost_vdpa_config_put(v);
drivers/vhost/vdpa.c
1475
vhost_vdpa_cleanup(v);
drivers/vhost/vdpa.c
1478
atomic_dec(&v->opened);
drivers/vhost/vdpa.c
1479
complete(&v->completion);
drivers/vhost/vdpa.c
1487
struct vhost_vdpa *v = vmf->vma->vm_file->private_data;
drivers/vhost/vdpa.c
1488
struct vdpa_device *vdpa = v->vdpa;
drivers/vhost/vdpa.c
1505
struct vhost_vdpa *v = vma->vm_file->private_data;
drivers/vhost/vdpa.c
1506
struct vdpa_device *vdpa = v->vdpa;
drivers/vhost/vdpa.c
152
vhost_vdpa_iotlb_unmap(v, &as->iotlb, 0ULL, 0ULL - 1, asid);
drivers/vhost/vdpa.c
1553
struct vhost_vdpa *v =
drivers/vhost/vdpa.c
1556
ida_free(&vhost_vdpa_ida, v->minor);
drivers/vhost/vdpa.c
1557
kfree(v->vqs);
drivers/vhost/vdpa.c
1558
kfree(v);
drivers/vhost/vdpa.c
1564
struct vhost_vdpa *v;
drivers/vhost/vdpa.c
1575
v = kzalloc_obj(*v, GFP_KERNEL | __GFP_RETRY_MAYFAIL);
drivers/vhost/vdpa.c
1576
if (!v)
drivers/vhost/vdpa.c
1582
kfree(v);
drivers/vhost/vdpa.c
1586
atomic_set(&v->opened, 0);
drivers/vhost/vdpa.c
1587
v->minor = minor;
drivers/vhost/vdpa.c
1588
v->vdpa = vdpa;
drivers/vhost/vdpa.c
1589
v->nvqs = vdpa->nvqs;
drivers/vhost/vdpa.c
1590
v->virtio_id = ops->get_device_id(vdpa);
drivers/vhost/vdpa.c
1592
device_initialize(&v->dev);
drivers/vhost/vdpa.c
1593
v->dev.release = vhost_vdpa_release_dev;
drivers/vhost/vdpa.c
1594
v->dev.parent = &vdpa->dev;
drivers/vhost/vdpa.c
1595
v->dev.devt = MKDEV(MAJOR(vhost_vdpa_major), minor);
drivers/vhost/vdpa.c
1596
v->vqs = kmalloc_objs(struct vhost_virtqueue, v->nvqs);
drivers/vhost/vdpa.c
1597
if (!v->vqs) {
drivers/vhost/vdpa.c
160
vhost_vdpa_reset_map(v, asid);
drivers/vhost/vdpa.c
1602
r = dev_set_name(&v->dev, "vhost-vdpa-%u", minor);
drivers/vhost/vdpa.c
1606
cdev_init(&v->cdev, &vhost_vdpa_fops);
drivers/vhost/vdpa.c
1607
v->cdev.owner = THIS_MODULE;
drivers/vhost/vdpa.c
1609
r = cdev_device_add(&v->cdev, &v->dev);
drivers/vhost/vdpa.c
1613
init_completion(&v->completion);
drivers/vhost/vdpa.c
1614
vdpa_set_drvdata(vdpa, v);
drivers/vhost/vdpa.c
1617
INIT_HLIST_HEAD(&v->as[i]);
drivers/vhost/vdpa.c
1622
put_device(&v->dev);
drivers/vhost/vdpa.c
1628
struct vhost_vdpa *v = vdpa_get_drvdata(vdpa);
drivers/vhost/vdpa.c
1631
cdev_device_del(&v->cdev, &v->dev);
drivers/vhost/vdpa.c
1634
opened = atomic_cmpxchg(&v->opened, 0, 1);
drivers/vhost/vdpa.c
1637
wait_for_completion(&v->completion);
drivers/vhost/vdpa.c
1640
put_device(&v->dev);
drivers/vhost/vdpa.c
170
struct vhost_vdpa *v = container_of(vq->dev, struct vhost_vdpa, vdev);
drivers/vhost/vdpa.c
171
const struct vdpa_config_ops *ops = v->vdpa->config;
drivers/vhost/vdpa.c
173
ops->kick_vq(v->vdpa, vq - v->vqs);
drivers/vhost/vdpa.c
189
struct vhost_vdpa *v = private;
drivers/vhost/vdpa.c
190
struct eventfd_ctx *config_ctx = v->config_ctx;
drivers/vhost/vdpa.c
198
static void vhost_vdpa_setup_vq_irq(struct vhost_vdpa *v, u16 qid)
drivers/vhost/vdpa.c
200
struct vhost_virtqueue *vq = &v->vqs[qid];
drivers/vhost/vdpa.c
201
const struct vdpa_config_ops *ops = v->vdpa->config;
drivers/vhost/vdpa.c
202
struct vdpa_device *vdpa = v->vdpa;
drivers/vhost/vdpa.c
218
dev_info(&v->dev, "vq %u, irq bypass producer (eventfd %p) registration fails, ret = %d\n",
drivers/vhost/vdpa.c
222
static void vhost_vdpa_unsetup_vq_irq(struct vhost_vdpa *v, u16 qid)
drivers/vhost/vdpa.c
224
struct vhost_virtqueue *vq = &v->vqs[qid];
drivers/vhost/vdpa.c
229
static int _compat_vdpa_reset(struct vhost_vdpa *v)
drivers/vhost/vdpa.c
231
struct vdpa_device *vdpa = v->vdpa;
drivers/vhost/vdpa.c
234
v->suspended = false;
drivers/vhost/vdpa.c
236
if (v->vdev.vqs) {
drivers/vhost/vdpa.c
237
flags |= !vhost_backend_has_feature(v->vdev.vqs[0],
drivers/vhost/vdpa.c
245
static int vhost_vdpa_reset(struct vhost_vdpa *v)
drivers/vhost/vdpa.c
247
v->in_batch = 0;
drivers/vhost/vdpa.c
248
return _compat_vdpa_reset(v);
drivers/vhost/vdpa.c
251
static long vhost_vdpa_bind_mm(struct vhost_vdpa *v)
drivers/vhost/vdpa.c
253
struct vdpa_device *vdpa = v->vdpa;
drivers/vhost/vdpa.c
259
return ops->bind_mm(vdpa, v->vdev.mm);
drivers/vhost/vdpa.c
262
static void vhost_vdpa_unbind_mm(struct vhost_vdpa *v)
drivers/vhost/vdpa.c
264
struct vdpa_device *vdpa = v->vdpa;
drivers/vhost/vdpa.c
273
static long vhost_vdpa_get_device_id(struct vhost_vdpa *v, u8 __user *argp)
drivers/vhost/vdpa.c
275
struct vdpa_device *vdpa = v->vdpa;
drivers/vhost/vdpa.c
287
static long vhost_vdpa_get_status(struct vhost_vdpa *v, u8 __user *statusp)
drivers/vhost/vdpa.c
289
struct vdpa_device *vdpa = v->vdpa;
drivers/vhost/vdpa.c
301
static long vhost_vdpa_set_status(struct vhost_vdpa *v, u8 __user *statusp)
drivers/vhost/vdpa.c
303
struct vdpa_device *vdpa = v->vdpa;
drivers/vhost/vdpa.c
306
u32 nvqs = v->nvqs;
drivers/vhost/vdpa.c
324
vhost_vdpa_unsetup_vq_irq(v, i);
drivers/vhost/vdpa.c
327
ret = _compat_vdpa_reset(v);
drivers/vhost/vdpa.c
335
vhost_vdpa_setup_vq_irq(v, i);
drivers/vhost/vdpa.c
340
static int vhost_vdpa_config_validate(struct vhost_vdpa *v,
drivers/vhost/vdpa.c
343
struct vdpa_device *vdpa = v->vdpa;
drivers/vhost/vdpa.c
355
static long vhost_vdpa_get_config(struct vhost_vdpa *v,
drivers/vhost/vdpa.c
358
struct vdpa_device *vdpa = v->vdpa;
drivers/vhost/vdpa.c
365
if (vhost_vdpa_config_validate(v, &config))
drivers/vhost/vdpa.c
382
static long vhost_vdpa_set_config(struct vhost_vdpa *v,
drivers/vhost/vdpa.c
385
struct vdpa_device *vdpa = v->vdpa;
drivers/vhost/vdpa.c
392
if (vhost_vdpa_config_validate(v, &config))
drivers/vhost/vdpa.c
405
static bool vhost_vdpa_can_suspend(const struct vhost_vdpa *v)
drivers/vhost/vdpa.c
407
struct vdpa_device *vdpa = v->vdpa;
drivers/vhost/vdpa.c
413
static bool vhost_vdpa_can_resume(const struct vhost_vdpa *v)
drivers/vhost/vdpa.c
415
struct vdpa_device *vdpa = v->vdpa;
drivers/vhost/vdpa.c
421
static bool vhost_vdpa_has_desc_group(const struct vhost_vdpa *v)
drivers/vhost/vdpa.c
423
struct vdpa_device *vdpa = v->vdpa;
drivers/vhost/vdpa.c
429
static long vhost_vdpa_get_features(struct vhost_vdpa *v, u64 __user *featurep)
drivers/vhost/vdpa.c
431
struct vdpa_device *vdpa = v->vdpa;
drivers/vhost/vdpa.c
443
static u64 vhost_vdpa_get_backend_features(const struct vhost_vdpa *v)
drivers/vhost/vdpa.c
445
struct vdpa_device *vdpa = v->vdpa;
drivers/vhost/vdpa.c
454
static bool vhost_vdpa_has_persistent_map(const struct vhost_vdpa *v)
drivers/vhost/vdpa.c
456
struct vdpa_device *vdpa = v->vdpa;
drivers/vhost/vdpa.c
460
vhost_vdpa_get_backend_features(v) & BIT_ULL(VHOST_BACKEND_F_IOTLB_PERSIST);
drivers/vhost/vdpa.c
463
static long vhost_vdpa_set_features(struct vhost_vdpa *v, u64 __user *featurep)
drivers/vhost/vdpa.c
465
struct vdpa_device *vdpa = v->vdpa;
drivers/vhost/vdpa.c
467
struct vhost_dev *d = &v->vdev;
drivers/vhost/vdpa.c
498
static long vhost_vdpa_get_vring_num(struct vhost_vdpa *v, u16 __user *argp)
drivers/vhost/vdpa.c
500
struct vdpa_device *vdpa = v->vdpa;
drivers/vhost/vdpa.c
512
static void vhost_vdpa_config_put(struct vhost_vdpa *v)
drivers/vhost/vdpa.c
514
if (v->config_ctx) {
drivers/vhost/vdpa.c
515
eventfd_ctx_put(v->config_ctx);
drivers/vhost/vdpa.c
516
v->config_ctx = NULL;
drivers/vhost/vdpa.c
520
static long vhost_vdpa_set_config_call(struct vhost_vdpa *v, u32 __user *argp)
drivers/vhost/vdpa.c
527
cb.private = v;
drivers/vhost/vdpa.c
532
swap(ctx, v->config_ctx);
drivers/vhost/vdpa.c
537
if (IS_ERR(v->config_ctx)) {
drivers/vhost/vdpa.c
538
long ret = PTR_ERR(v->config_ctx);
drivers/vhost/vdpa.c
540
v->config_ctx = NULL;
drivers/vhost/vdpa.c
544
v->vdpa->config->set_config_cb(v->vdpa, &cb);
drivers/vhost/vdpa.c
549
static long vhost_vdpa_get_iova_range(struct vhost_vdpa *v, u32 __user *argp)
drivers/vhost/vdpa.c
552
.first = v->range.first,
drivers/vhost/vdpa.c
553
.last = v->range.last,
drivers/vhost/vdpa.c
561
static long vhost_vdpa_get_config_size(struct vhost_vdpa *v, u32 __user *argp)
drivers/vhost/vdpa.c
563
struct vdpa_device *vdpa = v->vdpa;
drivers/vhost/vdpa.c
575
static long vhost_vdpa_get_vqs_count(struct vhost_vdpa *v, u32 __user *argp)
drivers/vhost/vdpa.c
577
struct vdpa_device *vdpa = v->vdpa;
drivers/vhost/vdpa.c
590
static long vhost_vdpa_suspend(struct vhost_vdpa *v)
drivers/vhost/vdpa.c
592
struct vdpa_device *vdpa = v->vdpa;
drivers/vhost/vdpa.c
604
v->suspended = true;
drivers/vhost/vdpa.c
613
static long vhost_vdpa_resume(struct vhost_vdpa *v)
drivers/vhost/vdpa.c
615
struct vdpa_device *vdpa = v->vdpa;
drivers/vhost/vdpa.c
627
v->suspended = false;
drivers/vhost/vdpa.c
632
static long vhost_vdpa_vring_ioctl(struct vhost_vdpa *v, unsigned int cmd,
drivers/vhost/vdpa.c
635
struct vdpa_device *vdpa = v->vdpa;
drivers/vhost/vdpa.c
648
if (idx >= v->nvqs)
drivers/vhost/vdpa.c
651
idx = array_index_nospec(idx, v->nvqs);
drivers/vhost/vdpa.c
652
vq = &v->vqs[idx];
drivers/vhost/vdpa.c
671
if (!vhost_vdpa_has_desc_group(v))
drivers/vhost/vdpa.c
69
static void vhost_vdpa_iotlb_unmap(struct vhost_vdpa *v,
drivers/vhost/vdpa.c
699
r = ops->get_vq_state(v->vdpa, idx, &vq_state);
drivers/vhost/vdpa.c
716
vhost_vdpa_unsetup_vq_irq(v, idx);
drivers/vhost/vdpa.c
721
r = vhost_vring_ioctl(&v->vdev, cmd, argp);
drivers/vhost/vdpa.c
727
if ((ops->get_status(vdpa) & VIRTIO_CONFIG_S_DRIVER_OK) && !v->suspended)
drivers/vhost/vdpa.c
738
if ((ops->get_status(vdpa) & VIRTIO_CONFIG_S_DRIVER_OK) && !v->suspended)
drivers/vhost/vdpa.c
759
vhost_vdpa_setup_vq_irq(v, idx);
drivers/vhost/vdpa.c
779
struct vhost_vdpa *v = filep->private_data;
drivers/vhost/vdpa.c
780
struct vhost_dev *d = &v->vdev;
drivers/vhost/vdpa.c
797
!vhost_vdpa_can_suspend(v))
drivers/vhost/vdpa.c
80
static struct vhost_vdpa_as *asid_to_as(struct vhost_vdpa *v, u32 asid)
drivers/vhost/vdpa.c
800
!vhost_vdpa_can_resume(v))
drivers/vhost/vdpa.c
806
!vhost_vdpa_has_desc_group(v))
drivers/vhost/vdpa.c
809
!vhost_vdpa_has_persistent_map(v))
drivers/vhost/vdpa.c
811
vhost_set_backend_features(&v->vdev, features);
drivers/vhost/vdpa.c
819
r = vhost_vdpa_get_device_id(v, argp);
drivers/vhost/vdpa.c
82
struct hlist_head *head = &v->as[asid % VHOST_VDPA_IOTLB_BUCKETS];
drivers/vhost/vdpa.c
822
r = vhost_vdpa_get_status(v, argp);
drivers/vhost/vdpa.c
825
r = vhost_vdpa_set_status(v, argp);
drivers/vhost/vdpa.c
828
r = vhost_vdpa_get_config(v, argp);
drivers/vhost/vdpa.c
831
r = vhost_vdpa_set_config(v, argp);
drivers/vhost/vdpa.c
834
r = vhost_vdpa_get_features(v, argp);
drivers/vhost/vdpa.c
837
r = vhost_vdpa_set_features(v, argp);
drivers/vhost/vdpa.c
840
r = vhost_vdpa_get_vring_num(v, argp);
drivers/vhost/vdpa.c
843
if (copy_to_user(argp, &v->vdpa->ngroups,
drivers/vhost/vdpa.c
844
sizeof(v->vdpa->ngroups)))
drivers/vhost/vdpa.c
848
if (copy_to_user(argp, &v->vdpa->nas, sizeof(v->vdpa->nas)))
drivers/vhost/vdpa.c
856
r = vhost_vdpa_set_config_call(v, argp);
drivers/vhost/vdpa.c
860
if (vhost_vdpa_can_suspend(v))
drivers/vhost/vdpa.c
862
if (vhost_vdpa_can_resume(v))
drivers/vhost/vdpa.c
864
if (vhost_vdpa_has_desc_group(v))
drivers/vhost/vdpa.c
866
if (vhost_vdpa_has_persistent_map(v))
drivers/vhost/vdpa.c
868
features |= vhost_vdpa_get_backend_features(v);
drivers/vhost/vdpa.c
873
r = vhost_vdpa_get_iova_range(v, argp);
drivers/vhost/vdpa.c
876
r = vhost_vdpa_get_config_size(v, argp);
drivers/vhost/vdpa.c
879
r = vhost_vdpa_get_vqs_count(v, argp);
drivers/vhost/vdpa.c
882
r = vhost_vdpa_suspend(v);
drivers/vhost/vdpa.c
885
r = vhost_vdpa_resume(v);
drivers/vhost/vdpa.c
888
r = vhost_dev_ioctl(&v->vdev, cmd, argp);
drivers/vhost/vdpa.c
890
r = vhost_vdpa_vring_ioctl(v, cmd, argp);
drivers/vhost/vdpa.c
899
r = vhost_vdpa_bind_mm(v);
drivers/vhost/vdpa.c
908
static void vhost_vdpa_general_unmap(struct vhost_vdpa *v,
drivers/vhost/vdpa.c
911
struct vdpa_device *vdpa = v->vdpa;
drivers/vhost/vdpa.c
916
iommu_unmap(v->domain, map->start, map->size);
drivers/vhost/vdpa.c
92
static struct vhost_iotlb *asid_to_iotlb(struct vhost_vdpa *v, u32 asid)
drivers/vhost/vdpa.c
920
static void vhost_vdpa_pa_unmap(struct vhost_vdpa *v, struct vhost_iotlb *iotlb,
drivers/vhost/vdpa.c
923
struct vhost_dev *dev = &v->vdev;
drivers/vhost/vdpa.c
938
vhost_vdpa_general_unmap(v, map, asid);
drivers/vhost/vdpa.c
94
struct vhost_vdpa_as *as = asid_to_as(v, asid);
drivers/vhost/vdpa.c
943
static void vhost_vdpa_va_unmap(struct vhost_vdpa *v, struct vhost_iotlb *iotlb,
drivers/vhost/vdpa.c
953
vhost_vdpa_general_unmap(v, map, asid);
drivers/vhost/vdpa.c
958
static void vhost_vdpa_iotlb_unmap(struct vhost_vdpa *v,
drivers/vhost/vdpa.c
962
struct vdpa_device *vdpa = v->vdpa;
drivers/vhost/vdpa.c
965
return vhost_vdpa_va_unmap(v, iotlb, start, last, asid);
drivers/vhost/vdpa.c
967
return vhost_vdpa_pa_unmap(v, iotlb, start, last, asid);
drivers/vhost/vdpa.c
992
static int vhost_vdpa_map(struct vhost_vdpa *v, struct vhost_iotlb *iotlb,
drivers/vhost/vdpa.c
995
struct vhost_dev *dev = &v->vdev;
drivers/vhost/vdpa.c
996
struct vdpa_device *vdpa = v->vdpa;
drivers/vhost/vhost.c
3134
bool v;
drivers/vhost/vhost.c
3153
v = vq->signalled_used_valid;
drivers/vhost/vhost.c
3157
if (unlikely(!v))
drivers/vhost/vringh.c
600
__virtio16 v = 0;
drivers/vhost/vringh.c
601
int rc = get_user(v, (__force __virtio16 __user *)p);
drivers/vhost/vringh.c
602
*val = vringh16_to_cpu(vrh, v);
drivers/vhost/vringh.c
608
__virtio16 v = cpu_to_vringh16(vrh, val);
drivers/vhost/vringh.c
609
return put_user(v, (__force __virtio16 __user *)p);
drivers/video/backlight/hp680_bl.c
34
u16 v;
drivers/video/backlight/hp680_bl.c
43
v = inw(HD64461_GPBDR);
drivers/video/backlight/hp680_bl.c
44
v &= ~HD64461_GPBDR_LCDOFF;
drivers/video/backlight/hp680_bl.c
45
outw(v, HD64461_GPBDR);
drivers/video/backlight/hp680_bl.c
50
v = inw(HD64461_GPBDR);
drivers/video/backlight/hp680_bl.c
51
v |= HD64461_GPBDR_LCDOFF;
drivers/video/backlight/hp680_bl.c
52
outw(v, HD64461_GPBDR);
drivers/video/backlight/qcom-wled.c
234
__le16 v;
drivers/video/backlight/qcom-wled.c
236
v = cpu_to_le16(brightness & WLED3_SINK_REG_BRIGHT_MAX);
drivers/video/backlight/qcom-wled.c
241
&v, sizeof(v));
drivers/video/backlight/qcom-wled.c
253
__le16 v;
drivers/video/backlight/qcom-wled.c
259
v = cpu_to_le16(brightness & WLED3_SINK_REG_BRIGHT_MAX);
drivers/video/backlight/qcom-wled.c
264
&v, sizeof(v));
drivers/video/backlight/qcom-wled.c
276
__le16 v;
drivers/video/backlight/qcom-wled.c
282
v = cpu_to_le16(brightness & WLED5_SINK_REG_BRIGHT_MAX_15B);
drivers/video/backlight/qcom-wled.c
289
&v, sizeof(v));
drivers/video/backlight/rt4831-backlight.c
45
u8 v[2];
drivers/video/backlight/rt4831-backlight.c
49
v[0] = (brightness - 1) & RT4831_BLDIML_MASK;
drivers/video/backlight/rt4831-backlight.c
50
v[1] = ((brightness - 1) & RT4831_BLDIMH_MASK) >> RT4831_BLDIMH_SHIFT;
drivers/video/backlight/rt4831-backlight.c
52
ret = regmap_raw_write(priv->regmap, RT4831_REG_BLDIML, v, sizeof(v));
drivers/video/backlight/rt4831-backlight.c
65
u8 v[2];
drivers/video/backlight/rt4831-backlight.c
75
ret = regmap_raw_read(priv->regmap, RT4831_REG_BLDIML, v, sizeof(v));
drivers/video/backlight/rt4831-backlight.c
79
ret = (v[1] << RT4831_BLDIMH_SHIFT) + (v[0] & RT4831_BLDIML_MASK) + 1;
drivers/video/fbdev/68328fb.c
332
u32 v;
drivers/video/fbdev/68328fb.c
337
v = (red << info->var.red.offset) |
drivers/video/fbdev/68328fb.c
345
((u32 *) (info->pseudo_palette))[regno] = v;
drivers/video/fbdev/68328fb.c
349
((u32 *) (info->pseudo_palette))[regno] = v;
drivers/video/fbdev/amifb.c
543
#define up2(v) (((v) + 1) & -2)
drivers/video/fbdev/amifb.c
544
#define down2(v) ((v) & -2)
drivers/video/fbdev/amifb.c
545
#define div2(v) ((v)>>1)
drivers/video/fbdev/amifb.c
546
#define mod2(v) ((v) & 1)
drivers/video/fbdev/amifb.c
548
#define up4(v) (((v) + 3) & -4)
drivers/video/fbdev/amifb.c
549
#define down4(v) ((v) & -4)
drivers/video/fbdev/amifb.c
550
#define mul4(v) ((v) << 2)
drivers/video/fbdev/amifb.c
551
#define div4(v) ((v)>>2)
drivers/video/fbdev/amifb.c
552
#define mod4(v) ((v) & 3)
drivers/video/fbdev/amifb.c
554
#define up8(v) (((v) + 7) & -8)
drivers/video/fbdev/amifb.c
555
#define down8(v) ((v) & -8)
drivers/video/fbdev/amifb.c
556
#define div8(v) ((v)>>3)
drivers/video/fbdev/amifb.c
557
#define mod8(v) ((v) & 7)
drivers/video/fbdev/amifb.c
559
#define up16(v) (((v) + 15) & -16)
drivers/video/fbdev/amifb.c
560
#define down16(v) ((v) & -16)
drivers/video/fbdev/amifb.c
561
#define div16(v) ((v)>>4)
drivers/video/fbdev/amifb.c
562
#define mod16(v) ((v) & 15)
drivers/video/fbdev/amifb.c
564
#define up32(v) (((v) + 31) & -32)
drivers/video/fbdev/amifb.c
565
#define down32(v) ((v) & -32)
drivers/video/fbdev/amifb.c
566
#define div32(v) ((v)>>5)
drivers/video/fbdev/amifb.c
567
#define mod32(v) ((v) & 31)
drivers/video/fbdev/amifb.c
569
#define up64(v) (((v) + 63) & -64)
drivers/video/fbdev/amifb.c
570
#define down64(v) ((v) & -64)
drivers/video/fbdev/amifb.c
571
#define div64(v) ((v)>>6)
drivers/video/fbdev/amifb.c
572
#define mod64(v) ((v) & 63)
drivers/video/fbdev/amifb.c
574
#define upx(x, v) (((v) + (x) - 1) & -(x))
drivers/video/fbdev/amifb.c
575
#define downx(x, v) ((v) & -(x))
drivers/video/fbdev/amifb.c
576
#define modx(x, v) ((v) & ((x) - 1))
drivers/video/fbdev/atafb_iplan2p2.c
106
u32 pval[4], v, v1, mask;
drivers/video/fbdev/atafb_iplan2p2.c
133
v = *src32++;
drivers/video/fbdev/atafb_iplan2p2.c
134
v1 = v & mask;
drivers/video/fbdev/atafb_iplan2p2.c
136
pval[0] = (v ^ v1) << 8;
drivers/video/fbdev/atafb_iplan2p2.c
148
u32 pval[4], v, v1, mask;
drivers/video/fbdev/atafb_iplan2p2.c
175
v = *--src32;
drivers/video/fbdev/atafb_iplan2p2.c
176
v1 = v & mask;
drivers/video/fbdev/atafb_iplan2p2.c
178
pval[0] = (v ^ v1) >> 8;
drivers/video/fbdev/atafb_iplan2p4.c
106
u32 pval[4], v, v1, mask;
drivers/video/fbdev/atafb_iplan2p4.c
135
v = *src32++;
drivers/video/fbdev/atafb_iplan2p4.c
136
v1 = v & mask;
drivers/video/fbdev/atafb_iplan2p4.c
138
pval[0] = (v ^ v1) << 8;
drivers/video/fbdev/atafb_iplan2p4.c
139
v = *src32++;
drivers/video/fbdev/atafb_iplan2p4.c
140
v1 = v & mask;
drivers/video/fbdev/atafb_iplan2p4.c
142
pval[1] = (v ^ v1) << 8;
drivers/video/fbdev/atafb_iplan2p4.c
155
u32 pval[4], v, v1, mask;
drivers/video/fbdev/atafb_iplan2p4.c
184
v = *--src32;
drivers/video/fbdev/atafb_iplan2p4.c
185
v1 = v & mask;
drivers/video/fbdev/atafb_iplan2p4.c
187
pval[0] = (v ^ v1) >> 8;
drivers/video/fbdev/atafb_iplan2p4.c
188
v = *--src32;
drivers/video/fbdev/atafb_iplan2p4.c
189
v1 = v & mask;
drivers/video/fbdev/atafb_iplan2p4.c
191
pval[1] = (v ^ v1) >> 8;
drivers/video/fbdev/atafb_iplan2p8.c
113
u32 pval[4], v, v1, mask;
drivers/video/fbdev/atafb_iplan2p8.c
146
v = *src32++;
drivers/video/fbdev/atafb_iplan2p8.c
147
v1 = v & mask;
drivers/video/fbdev/atafb_iplan2p8.c
149
pval[0] = (v ^ v1) << 8;
drivers/video/fbdev/atafb_iplan2p8.c
150
v = *src32++;
drivers/video/fbdev/atafb_iplan2p8.c
151
v1 = v & mask;
drivers/video/fbdev/atafb_iplan2p8.c
153
pval[1] = (v ^ v1) << 8;
drivers/video/fbdev/atafb_iplan2p8.c
154
v = *src32++;
drivers/video/fbdev/atafb_iplan2p8.c
155
v1 = v & mask;
drivers/video/fbdev/atafb_iplan2p8.c
157
pval[2] = (v ^ v1) << 8;
drivers/video/fbdev/atafb_iplan2p8.c
158
v = *src32++;
drivers/video/fbdev/atafb_iplan2p8.c
159
v1 = v & mask;
drivers/video/fbdev/atafb_iplan2p8.c
161
pval[3] = (v ^ v1) << 8;
drivers/video/fbdev/atafb_iplan2p8.c
176
u32 pval[4], v, v1, mask;
drivers/video/fbdev/atafb_iplan2p8.c
209
v = *--src32;
drivers/video/fbdev/atafb_iplan2p8.c
210
v1 = v & mask;
drivers/video/fbdev/atafb_iplan2p8.c
212
pval[0] = (v ^ v1) >> 8;
drivers/video/fbdev/atafb_iplan2p8.c
213
v = *--src32;
drivers/video/fbdev/atafb_iplan2p8.c
214
v1 = v & mask;
drivers/video/fbdev/atafb_iplan2p8.c
216
pval[1] = (v ^ v1) >> 8;
drivers/video/fbdev/atafb_iplan2p8.c
217
v = *--src32;
drivers/video/fbdev/atafb_iplan2p8.c
218
v1 = v & mask;
drivers/video/fbdev/atafb_iplan2p8.c
220
pval[2] = (v ^ v1) >> 8;
drivers/video/fbdev/atafb_iplan2p8.c
221
v = *--src32;
drivers/video/fbdev/atafb_iplan2p8.c
222
v1 = v & mask;
drivers/video/fbdev/atafb_iplan2p8.c
224
pval[3] = (v ^ v1) >> 8;
drivers/video/fbdev/atafb_utils.h
377
u32 *s, *d, v;
drivers/video/fbdev/atafb_utils.h
382
v = (*s++ & mask) | (*d & ~mask);
drivers/video/fbdev/atafb_utils.h
383
*d++ = v;
drivers/video/fbdev/atafb_utils.h
385
v = (*s++ & mask) | (*d & ~mask);
drivers/video/fbdev/atafb_utils.h
386
*d++ = v;
drivers/video/fbdev/atafb_utils.h
389
v = (*s++ & mask) | (*d & ~mask);
drivers/video/fbdev/atafb_utils.h
390
*d++ = v;
drivers/video/fbdev/atafb_utils.h
391
v = (*s++ & mask) | (*d & ~mask);
drivers/video/fbdev/atafb_utils.h
392
*d++ = v;
drivers/video/fbdev/aty/aty128fb.c
496
#define BIOS_IN8(v) (readb(bios + (v)))
drivers/video/fbdev/aty/aty128fb.c
497
#define BIOS_IN16(v) (readb(bios + (v)) | \
drivers/video/fbdev/aty/aty128fb.c
498
(readb(bios + (v) + 1) << 8))
drivers/video/fbdev/aty/aty128fb.c
499
#define BIOS_IN32(v) (readb(bios + (v)) | \
drivers/video/fbdev/aty/aty128fb.c
500
(readb(bios + (v) + 1) << 8) | \
drivers/video/fbdev/aty/aty128fb.c
501
(readb(bios + (v) + 2) << 16) | \
drivers/video/fbdev/aty/aty128fb.c
502
(readb(bios + (v) + 3) << 24))
drivers/video/fbdev/aty/radeon_base.c
835
struct fb_var_screeninfo v;
drivers/video/fbdev/aty/radeon_base.c
839
if (radeon_match_mode(rinfo, &v, var))
drivers/video/fbdev/aty/radeon_base.c
842
switch (v.bits_per_pixel) {
drivers/video/fbdev/aty/radeon_base.c
844
v.bits_per_pixel = 8;
drivers/video/fbdev/aty/radeon_base.c
847
v.bits_per_pixel = 16;
drivers/video/fbdev/aty/radeon_base.c
850
v.bits_per_pixel = 32;
drivers/video/fbdev/aty/radeon_base.c
856
switch (var_to_depth(&v)) {
drivers/video/fbdev/aty/radeon_base.c
859
v.red.offset = v.green.offset = v.blue.offset = 0;
drivers/video/fbdev/aty/radeon_base.c
860
v.red.length = v.green.length = v.blue.length = 8;
drivers/video/fbdev/aty/radeon_base.c
861
v.transp.offset = v.transp.length = 0;
drivers/video/fbdev/aty/radeon_base.c
866
v.red.offset = 10;
drivers/video/fbdev/aty/radeon_base.c
867
v.green.offset = 5;
drivers/video/fbdev/aty/radeon_base.c
868
v.blue.offset = 0;
drivers/video/fbdev/aty/radeon_base.c
869
v.red.length = v.green.length = v.blue.length = 5;
drivers/video/fbdev/aty/radeon_base.c
870
v.transp.offset = v.transp.length = 0;
drivers/video/fbdev/aty/radeon_base.c
875
v.red.offset = 11;
drivers/video/fbdev/aty/radeon_base.c
876
v.green.offset = 5;
drivers/video/fbdev/aty/radeon_base.c
877
v.blue.offset = 0;
drivers/video/fbdev/aty/radeon_base.c
878
v.red.length = 5;
drivers/video/fbdev/aty/radeon_base.c
879
v.green.length = 6;
drivers/video/fbdev/aty/radeon_base.c
880
v.blue.length = 5;
drivers/video/fbdev/aty/radeon_base.c
881
v.transp.offset = v.transp.length = 0;
drivers/video/fbdev/aty/radeon_base.c
886
v.red.offset = 16;
drivers/video/fbdev/aty/radeon_base.c
887
v.green.offset = 8;
drivers/video/fbdev/aty/radeon_base.c
888
v.blue.offset = 0;
drivers/video/fbdev/aty/radeon_base.c
889
v.red.length = v.blue.length = v.green.length = 8;
drivers/video/fbdev/aty/radeon_base.c
890
v.transp.offset = v.transp.length = 0;
drivers/video/fbdev/aty/radeon_base.c
895
v.red.offset = 16;
drivers/video/fbdev/aty/radeon_base.c
896
v.green.offset = 8;
drivers/video/fbdev/aty/radeon_base.c
897
v.blue.offset = 0;
drivers/video/fbdev/aty/radeon_base.c
898
v.red.length = v.blue.length = v.green.length = 8;
drivers/video/fbdev/aty/radeon_base.c
899
v.transp.offset = 24;
drivers/video/fbdev/aty/radeon_base.c
900
v.transp.length = 8;
drivers/video/fbdev/aty/radeon_base.c
908
if (v.yres_virtual < v.yres)
drivers/video/fbdev/aty/radeon_base.c
909
v.yres_virtual = v.yres;
drivers/video/fbdev/aty/radeon_base.c
910
if (v.xres_virtual < v.xres)
drivers/video/fbdev/aty/radeon_base.c
911
v.xres_virtual = v.xres;
drivers/video/fbdev/aty/radeon_base.c
918
v.xres_virtual = v.xres_virtual & ~7ul;
drivers/video/fbdev/aty/radeon_base.c
920
pitch = ((v.xres_virtual * ((v.bits_per_pixel + 1) / 8) + 0x3f)
drivers/video/fbdev/aty/radeon_base.c
922
v.xres_virtual = (pitch << 6) / ((v.bits_per_pixel + 1) / 8);
drivers/video/fbdev/aty/radeon_base.c
925
if (((v.xres_virtual * v.yres_virtual * nom) / den) > rinfo->mapped_vram)
drivers/video/fbdev/aty/radeon_base.c
928
if (v.xres_virtual < v.xres)
drivers/video/fbdev/aty/radeon_base.c
929
v.xres = v.xres_virtual;
drivers/video/fbdev/aty/radeon_base.c
931
if (v.xoffset > v.xres_virtual - v.xres)
drivers/video/fbdev/aty/radeon_base.c
932
v.xoffset = v.xres_virtual - v.xres - 1;
drivers/video/fbdev/aty/radeon_base.c
934
if (v.yoffset > v.yres_virtual - v.yres)
drivers/video/fbdev/aty/radeon_base.c
935
v.yoffset = v.yres_virtual - v.yres - 1;
drivers/video/fbdev/aty/radeon_base.c
937
v.red.msb_right = v.green.msb_right = v.blue.msb_right =
drivers/video/fbdev/aty/radeon_base.c
938
v.transp.offset = v.transp.length =
drivers/video/fbdev/aty/radeon_base.c
939
v.transp.msb_right = 0;
drivers/video/fbdev/aty/radeon_base.c
941
memcpy(var, &v, sizeof(v));
drivers/video/fbdev/aty/radeonfb.h
428
#define BIOS_IN8(v) (readb(rinfo->bios_seg + (v)))
drivers/video/fbdev/aty/radeonfb.h
429
#define BIOS_IN16(v) (readb(rinfo->bios_seg + (v)) | \
drivers/video/fbdev/aty/radeonfb.h
430
(readb(rinfo->bios_seg + (v) + 1) << 8))
drivers/video/fbdev/aty/radeonfb.h
431
#define BIOS_IN32(v) (readb(rinfo->bios_seg + (v)) | \
drivers/video/fbdev/aty/radeonfb.h
432
(readb(rinfo->bios_seg + (v) + 1) << 8) | \
drivers/video/fbdev/aty/radeonfb.h
433
(readb(rinfo->bios_seg + (v) + 2) << 16) | \
drivers/video/fbdev/aty/radeonfb.h
434
(readb(rinfo->bios_seg + (v) + 3) << 24))
drivers/video/fbdev/cirrusfb.c
1287
u32 v;
drivers/video/fbdev/cirrusfb.c
1294
v = (red << info->var.red.offset) |
drivers/video/fbdev/cirrusfb.c
1298
cinfo->pseudo_palette[regno] = v;
drivers/video/fbdev/core/fb_notify.c
50
int fb_notifier_call_chain(unsigned long val, void *v)
drivers/video/fbdev/core/fb_notify.c
52
return blocking_notifier_call_chain(&fb_notifier_list, val, v);
drivers/video/fbdev/core/fb_procfs.c
16
static void fb_seq_stop(struct seq_file *m, void *v)
drivers/video/fbdev/core/fb_procfs.c
21
static void *fb_seq_next(struct seq_file *m, void *v, loff_t *pos)
drivers/video/fbdev/core/fb_procfs.c
28
static int fb_seq_show(struct seq_file *m, void *v)
drivers/video/fbdev/core/fb_procfs.c
30
int i = *(loff_t *)v;
drivers/video/fbdev/core/fbcon.h
224
#define FBCON_SWAP(i,r,v) ({ \
drivers/video/fbdev/core/fbcon.h
226
typeof(v) _v = (v); \
drivers/video/fbdev/core/fbsysfs.c
36
char v = 'p';
drivers/video/fbdev/core/fbsysfs.c
46
v = 'i';
drivers/video/fbdev/core/fbsysfs.c
48
v = 'd';
drivers/video/fbdev/core/fbsysfs.c
51
m, mode->xres, mode->yres, v, mode->refresh);
drivers/video/fbdev/core/modedb.c
22
#define name_matches(v, s, l) \
drivers/video/fbdev/core/modedb.c
23
((v).name && !strncmp((s), (v).name, (l)) && strlen((v).name) == (l))
drivers/video/fbdev/core/modedb.c
24
#define res_matches(v, x, y) \
drivers/video/fbdev/core/modedb.c
25
((v).xres == (x) && (v).yres == (y))
drivers/video/fbdev/cyber2000fb.c
557
#define ENCODE_BIT(v, b1, m, b2) ((((v) >> (b1)) & (m)) << (b2))
drivers/video/fbdev/fsl-diu-fb.c
1216
u32 v;
drivers/video/fbdev/fsl-diu-fb.c
1223
v = (red << info->var.red.offset) |
drivers/video/fbdev/fsl-diu-fb.c
1228
pal[regno] = v;
drivers/video/fbdev/geode/gx1fb_core.c
168
u32 v;
drivers/video/fbdev/geode/gx1fb_core.c
173
v = chan_to_field(red, &info->var.red);
drivers/video/fbdev/geode/gx1fb_core.c
174
v |= chan_to_field(green, &info->var.green);
drivers/video/fbdev/geode/gx1fb_core.c
175
v |= chan_to_field(blue, &info->var.blue);
drivers/video/fbdev/geode/gx1fb_core.c
177
pal[regno] = v;
drivers/video/fbdev/geode/gxfb_core.c
192
u32 v;
drivers/video/fbdev/geode/gxfb_core.c
197
v = chan_to_field(red, &info->var.red);
drivers/video/fbdev/geode/gxfb_core.c
198
v |= chan_to_field(green, &info->var.green);
drivers/video/fbdev/geode/gxfb_core.c
199
v |= chan_to_field(blue, &info->var.blue);
drivers/video/fbdev/geode/gxfb_core.c
201
pal[regno] = v;
drivers/video/fbdev/geode/lxfb_core.c
302
u32 v;
drivers/video/fbdev/geode/lxfb_core.c
307
v = chan_to_field(red, &info->var.red);
drivers/video/fbdev/geode/lxfb_core.c
308
v |= chan_to_field(green, &info->var.green);
drivers/video/fbdev/geode/lxfb_core.c
309
v |= chan_to_field(blue, &info->var.blue);
drivers/video/fbdev/geode/lxfb_core.c
311
pal[regno] = v;
drivers/video/fbdev/grvga.c
218
u32 v;
drivers/video/fbdev/grvga.c
223
v = (red << info->var.red.offset) |
drivers/video/fbdev/grvga.c
228
((u32 *) (info->pseudo_palette))[regno] = v;
drivers/video/fbdev/hitfb.c
188
unsigned short v;
drivers/video/fbdev/hitfb.c
191
v = hitfb_readw(HD64461_LDR1);
drivers/video/fbdev/hitfb.c
192
v &= ~HD64461_LDR1_DON;
drivers/video/fbdev/hitfb.c
193
hitfb_writew(v, HD64461_LDR1);
drivers/video/fbdev/hitfb.c
195
v = hitfb_readw(HD64461_LCDCCR);
drivers/video/fbdev/hitfb.c
196
v |= HD64461_LCDCCR_MOFF;
drivers/video/fbdev/hitfb.c
197
hitfb_writew(v, HD64461_LCDCCR);
drivers/video/fbdev/hitfb.c
199
v = hitfb_readw(HD64461_STBCR);
drivers/video/fbdev/hitfb.c
200
v |= HD64461_STBCR_SLCDST;
drivers/video/fbdev/hitfb.c
201
hitfb_writew(v, HD64461_STBCR);
drivers/video/fbdev/hitfb.c
203
v = hitfb_readw(HD64461_STBCR);
drivers/video/fbdev/hitfb.c
204
v &= ~HD64461_STBCR_SLCDST;
drivers/video/fbdev/hitfb.c
205
hitfb_writew(v, HD64461_STBCR);
drivers/video/fbdev/hitfb.c
207
v = hitfb_readw(HD64461_LCDCCR);
drivers/video/fbdev/hitfb.c
208
v &= ~(HD64461_LCDCCR_MOFF | HD64461_LCDCCR_STREQ);
drivers/video/fbdev/hitfb.c
209
hitfb_writew(v, HD64461_LCDCCR);
drivers/video/fbdev/hitfb.c
212
v = hitfb_readw(HD64461_LCDCCR);
drivers/video/fbdev/hitfb.c
213
} while(v&HD64461_LCDCCR_STBACK);
drivers/video/fbdev/hitfb.c
215
v = hitfb_readw(HD64461_LDR1);
drivers/video/fbdev/hitfb.c
216
v |= HD64461_LDR1_DON;
drivers/video/fbdev/hitfb.c
217
hitfb_writew(v, HD64461_LDR1);
drivers/video/fbdev/hitfb.c
447
u16 v;
drivers/video/fbdev/hitfb.c
450
v = hitfb_readw(HD64461_STBCR);
drivers/video/fbdev/hitfb.c
451
v |= HD64461_STBCR_SLCKE_IST;
drivers/video/fbdev/hitfb.c
452
hitfb_writew(v, HD64461_STBCR);
drivers/video/fbdev/hitfb.c
459
u16 v;
drivers/video/fbdev/hitfb.c
461
v = hitfb_readw(HD64461_STBCR);
drivers/video/fbdev/hitfb.c
462
v &= ~HD64461_STBCR_SLCKE_OST;
drivers/video/fbdev/hitfb.c
464
v = hitfb_readw(HD64461_STBCR);
drivers/video/fbdev/hitfb.c
465
v &= ~HD64461_STBCR_SLCKE_IST;
drivers/video/fbdev/hitfb.c
466
hitfb_writew(v, HD64461_STBCR);
drivers/video/fbdev/matrox/i2c-matroxfb.c
43
int v;
drivers/video/fbdev/matrox/i2c-matroxfb.c
46
v = matroxfb_DAC_in(minfo, DAC_XGENIODATA);
drivers/video/fbdev/matrox/i2c-matroxfb.c
48
return v;
drivers/video/fbdev/matrox/i2c-matroxfb.c
53
int v;
drivers/video/fbdev/matrox/i2c-matroxfb.c
56
v = (matroxfb_DAC_in(minfo, DAC_XGENIOCTRL) & mask) | val;
drivers/video/fbdev/matrox/i2c-matroxfb.c
57
matroxfb_DAC_out(minfo, DAC_XGENIOCTRL, v);
drivers/video/fbdev/metronomefb.c
177
unsigned char v;
drivers/video/fbdev/metronomefb.c
277
v = mem[wfm_idx++];
drivers/video/fbdev/metronomefb.c
278
if (v == wfm_hdr->swtb) {
drivers/video/fbdev/metronomefb.c
279
while (((v = mem[wfm_idx++]) != wfm_hdr->swtb) &&
drivers/video/fbdev/metronomefb.c
281
metromem[mem_idx++] = v;
drivers/video/fbdev/metronomefb.c
286
if (v == wfm_hdr->endb)
drivers/video/fbdev/metronomefb.c
291
metromem[mem_idx++] = v;
drivers/video/fbdev/mmp/hw/mmp_ctrl.h
194
#define SPU_DMA_PITCH_V(v) ((v)<<16)
drivers/video/fbdev/mmp/hw/mmp_ctrl.h
308
#define CFG_CKEY_V(v) ((v)<<8)
drivers/video/fbdev/mmp/hw/mmp_ctrl.h
310
#define CFG_ALPHA_V(v) (v)
drivers/video/fbdev/omap2/omapfb/displays/panel-tpo-td043mtea1.c
138
static int tpo_td043_write_mirror(struct spi_device *spi, bool h, bool v)
drivers/video/fbdev/omap2/omapfb/displays/panel-tpo-td043mtea1.c
144
if (v)
drivers/video/fbdev/omap2/omapfb/dss/core.c
133
static int omap_dss_pm_notif(struct notifier_block *b, unsigned long v, void *d)
drivers/video/fbdev/omap2/omapfb/dss/core.c
135
DSSDBG("pm notif %lu\n", v);
drivers/video/fbdev/omap2/omapfb/dss/core.c
137
switch (v) {
drivers/video/fbdev/omap2/omapfb/dss/dispc.c
1141
u32 v;
drivers/video/fbdev/omap2/omapfb/dss/dispc.c
1143
v = dispc_read_reg(DISPC_GLOBAL_BUFFER);
drivers/video/fbdev/omap2/omapfb/dss/dispc.c
1145
v = FLD_MOD(v, 4, 2, 0); /* GFX BUF top to WB */
drivers/video/fbdev/omap2/omapfb/dss/dispc.c
1146
v = FLD_MOD(v, 4, 5, 3); /* GFX BUF bottom to WB */
drivers/video/fbdev/omap2/omapfb/dss/dispc.c
1147
v = FLD_MOD(v, 0, 26, 24); /* WB BUF top to GFX */
drivers/video/fbdev/omap2/omapfb/dss/dispc.c
1148
v = FLD_MOD(v, 0, 29, 27); /* WB BUF bottom to GFX */
drivers/video/fbdev/omap2/omapfb/dss/dispc.c
1150
dispc_write_reg(DISPC_GLOBAL_BUFFER, v);
drivers/video/fbdev/omap2/omapfb/dss/dispc.c
649
u32 v;
drivers/video/fbdev/omap2/omapfb/dss/dispc.c
650
v = FLD_VAL(v_coef[i].hc0_vc00, 7, 0)
drivers/video/fbdev/omap2/omapfb/dss/dispc.c
653
dispc_ovl_write_firv_reg(plane, i, v);
drivers/video/fbdev/omap2/omapfb/dss/dispc.c
655
dispc_ovl_write_firv2_reg(plane, i, v);
drivers/video/fbdev/omap2/omapfb/dss/dsi.c
2211
u8 v;
drivers/video/fbdev/omap2/omapfb/dss/dsi.c
2220
v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
drivers/video/fbdev/omap2/omapfb/dss/dsi.c
2221
r |= v << (8 * i);
drivers/video/fbdev/omap2/omapfb/dss/dsi.c
2244
u8 v;
drivers/video/fbdev/omap2/omapfb/dss/dsi.c
2253
v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
drivers/video/fbdev/omap2/omapfb/dss/dsi.c
2254
r |= v << (8 * i);
drivers/video/fbdev/omap2/omapfb/dss/hdmi.h
267
u32 t = 0, v;
drivers/video/fbdev/omap2/omapfb/dss/hdmi.h
268
while (val != (v = REG_GET(base_addr, idx, b2, b1))) {
drivers/video/fbdev/omap2/omapfb/dss/hdmi.h
270
return v;
drivers/video/fbdev/omap2/omapfb/dss/hdmi.h
273
return v;
drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c
73
u32 v;
drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c
88
v = hdmi_read_reg(hdmi.phy.base, HDMI_TXPHY_PAD_CFG_CTRL);
drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c
89
v = FLD_MOD(v, 1, 15, 15); /* FORCE_RXDET_HIGH */
drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c
90
v = FLD_MOD(v, 0, 14, 7); /* RXDET_LINE */
drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c
91
hdmi_write_reg(hdmi.phy.base, HDMI_TXPHY_PAD_CFG_CTRL, v);
drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c
50
unsigned v;
drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c
65
v = DIV_ROUND_UP_ULL(ss_scl_high * sfr, 1000000);
drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c
67
(v >> 8) & 0xff, 7, 0);
drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c
69
v & 0xff, 7, 0);
drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c
72
v = DIV_ROUND_UP_ULL(ss_scl_low * sfr, 1000000);
drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c
74
(v >> 8) & 0xff, 7, 0);
drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c
76
v & 0xff, 7, 0);
drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c
79
v = DIV_ROUND_UP_ULL(fs_scl_high * sfr, 1000000);
drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c
81
(v >> 8) & 0xff, 7, 0);
drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c
83
v & 0xff, 7, 0);
drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c
86
v = DIV_ROUND_UP_ULL(fs_scl_low * sfr, 1000000);
drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c
88
(v >> 8) & 0xff, 7, 0);
drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c
90
v & 0xff, 7, 0);
drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c
93
v = DIV_ROUND_UP_ULL(sda_hold * sfr, 1000000);
drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c
94
REG_FLD_MOD(base, HDMI_CORE_I2CM_SDA_HOLD_ADDR, v & 0xff, 7, 0);
drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c
119
u32 v;
drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c
123
v = hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS_RAW);
drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c
124
if (v & HDMI_IRQ_VIDEO_FRAME_DONE)
drivers/video/fbdev/omap2/omapfb/dss/pll.c
229
u32 v = readl_relaxed(pll->base + PLL_STATUS);
drivers/video/fbdev/omap2/omapfb/dss/pll.c
230
v &= hsdiv_ack_mask;
drivers/video/fbdev/omap2/omapfb/dss/pll.c
231
if (v == hsdiv_ack_mask)
drivers/video/fbdev/pm2fb.c
150
static inline void pm2_WR(struct pm2fb_par *p, s32 off, u32 v)
drivers/video/fbdev/pm2fb.c
152
fb_writel(v, p->v_regs + off);
drivers/video/fbdev/pm2fb.c
169
static inline void pm2_RDAC_WR(struct pm2fb_par *p, s32 idx, u32 v)
drivers/video/fbdev/pm2fb.c
173
pm2_WR(p, PM2R_RD_INDEXED_DATA, v);
drivers/video/fbdev/pm2fb.c
177
static inline void pm2v_RDAC_WR(struct pm2fb_par *p, s32 idx, u32 v)
drivers/video/fbdev/pm2fb.c
181
pm2_WR(p, PM2VR_RD_INDEXED_DATA, v);
drivers/video/fbdev/pm2fb.c
935
u32 v;
drivers/video/fbdev/pm2fb.c
940
v = (red << info->var.red.offset) |
drivers/video/fbdev/pm2fb.c
951
par->palette[regno] = v;
drivers/video/fbdev/pm3fb.c
100
static inline void PM3_WRITE_REG(struct pm3_par *par, s32 off, u32 v)
drivers/video/fbdev/pm3fb.c
102
fb_writel(v, par->v_regs + off);
drivers/video/fbdev/pm3fb.c
111
static inline void PM3_WRITE_DAC_REG(struct pm3_par *par, unsigned r, u8 v)
drivers/video/fbdev/pm3fb.c
1115
u32 v;
drivers/video/fbdev/pm3fb.c
1120
v = (red << info->var.red.offset) |
drivers/video/fbdev/pm3fb.c
1130
((u32 *)(info->pseudo_palette))[regno] = v;
drivers/video/fbdev/pm3fb.c
117
PM3_WRITE_REG(par, PM3RD_IndexedData, v);
drivers/video/fbdev/pm3fb.c
183
static inline int pm3fb_shift_bpp(unsigned bpp, int v)
drivers/video/fbdev/pm3fb.c
187
return (v >> 4);
drivers/video/fbdev/pm3fb.c
189
return (v >> 3);
drivers/video/fbdev/pm3fb.c
191
return (v >> 2);
drivers/video/fbdev/pmag-ba-fb.c
80
static inline void dac_write(struct pmagbafb_par *par, unsigned int reg, u8 v)
drivers/video/fbdev/pmag-ba-fb.c
82
writeb(v, par->dac + reg / 4);
drivers/video/fbdev/pmagb-b-fb.c
69
static inline void sfb_write(struct pmagbbfb_par *par, unsigned int reg, u32 v)
drivers/video/fbdev/pmagb-b-fb.c
71
writel(v, par->sfb + reg / 4);
drivers/video/fbdev/pmagb-b-fb.c
79
static inline void dac_write(struct pmagbbfb_par *par, unsigned int reg, u8 v)
drivers/video/fbdev/pmagb-b-fb.c
81
writeb(v, par->dac + reg / 4);
drivers/video/fbdev/pmagb-b-fb.c
89
static inline void gp0_write(struct pmagbbfb_par *par, u32 v)
drivers/video/fbdev/pmagb-b-fb.c
91
writel(v, par->mmio + PMAGB_B_GP0);
drivers/video/fbdev/pxa168fb.c
388
struct fb_var_screeninfo *v = &info->var;
drivers/video/fbdev/pxa168fb.c
392
x = v->xres + v->right_margin + v->hsync_len + v->left_margin;
drivers/video/fbdev/pxa168fb.c
393
y = v->yres + v->lower_margin + v->vsync_len + v->upper_margin;
drivers/video/fbdev/pxa168fb.h
135
#define CFG_CKEY_V(v) ((v) << 8)
drivers/video/fbdev/pxa168fb.h
137
#define CFG_ALPHA_V(v) (v)
drivers/video/fbdev/pxa168fb.h
21
#define SPU_DMA_PITCH_V(v) ((v) << 16)
drivers/video/fbdev/pxafb.c
310
#define SET_PIXFMT(v, r, g, b, t) \
drivers/video/fbdev/pxafb.c
312
(v)->transp.offset = (t) ? (r) + (g) + (b) : 0; \
drivers/video/fbdev/pxafb.c
313
(v)->transp.length = (t) ? (t) : 0; \
drivers/video/fbdev/pxafb.c
314
(v)->blue.length = (b); (v)->blue.offset = 0; \
drivers/video/fbdev/pxafb.c
315
(v)->green.length = (g); (v)->green.offset = (b); \
drivers/video/fbdev/pxafb.c
316
(v)->red.length = (r); (v)->red.offset = (b) + (g); \
drivers/video/fbdev/riva/riva_hw.c
537
int done, g,v, p;
drivers/video/fbdev/riva/riva_hw.c
544
for (v=128; v >=32; v = v>> 1)
drivers/video/fbdev/riva/riva_hw.c
548
ainfo->vburst_size = v;
drivers/video/fbdev/s3c-fb.c
45
#define writel(v, r) do { \
drivers/video/fbdev/s3c-fb.c
46
pr_debug("%s: %08x => %p\n", __func__, (unsigned int)v, r); \
drivers/video/fbdev/s3c-fb.c
47
__raw_writel(v, r); \
drivers/video/fbdev/sis/sis_main.c
469
if(monitor->vmin > sisfb_ddcsmodes[i].v) monitor->vmin = sisfb_ddcsmodes[i].v;
drivers/video/fbdev/sis/sis_main.c
470
if(monitor->vmax < sisfb_ddcsmodes[i].v) monitor->vmax = sisfb_ddcsmodes[i].v;
drivers/video/fbdev/sis/sis_main.c
488
(refresh == sisfb_ddcfmodes[j].v)) {
drivers/video/fbdev/sis/sis_main.c
491
if(monitor->vmin > sisfb_ddcsmodes[j].v) monitor->vmin = sisfb_ddcsmodes[j].v;
drivers/video/fbdev/sis/sis_main.c
492
if(monitor->vmax < sisfb_ddcsmodes[j].v) monitor->vmax = sisfb_ddcsmodes[j].v;
drivers/video/fbdev/sis/sis_main.h
454
u16 v;
drivers/video/fbdev/sis/sis_main.h
475
u16 v;
drivers/video/fbdev/skeletonfb.c
396
u32 v;
drivers/video/fbdev/skeletonfb.c
401
v = (red << info->var.red.offset) |
drivers/video/fbdev/skeletonfb.c
406
((u32*)(info->pseudo_palette))[regno] = v;
drivers/video/fbdev/tridentfb.c
175
static inline void writemmr(struct tridentfb_par *par, u16 r, u32 v)
drivers/video/fbdev/tridentfb.c
177
fb_writel(v, par->io_virt + r);
drivers/video/fbdev/vfb.c
326
u32 v;
drivers/video/fbdev/vfb.c
331
v = (red << info->var.red.offset) |
drivers/video/fbdev/vfb.c
339
((u32 *) (info->pseudo_palette))[regno] = v;
drivers/video/fbdev/vfb.c
343
((u32 *) (info->pseudo_palette))[regno] = v;
drivers/video/fbdev/via/via-core.c
59
static inline void viafb_mmio_write(int reg, u32 v)
drivers/video/fbdev/via/via-core.c
61
iowrite32(v, global_dev.engine_mmio + reg);
drivers/video/fbdev/via/viafbdev.c
1110
static int viafb_dvp0_proc_show(struct seq_file *m, void *v)
drivers/video/fbdev/via/viafbdev.c
1184
static int viafb_dvp1_proc_show(struct seq_file *m, void *v)
drivers/video/fbdev/via/viafbdev.c
1248
static int viafb_dfph_proc_show(struct seq_file *m, void *v)
drivers/video/fbdev/via/viafbdev.c
1282
static int viafb_dfpl_proc_show(struct seq_file *m, void *v)
drivers/video/fbdev/via/viafbdev.c
1316
static int viafb_vt1636_proc_show(struct seq_file *m, void *v)
drivers/video/fbdev/via/viafbdev.c
1453
static int __maybe_unused viafb_sup_odev_proc_show(struct seq_file *m, void *v)
drivers/video/fbdev/via/viafbdev.c
1489
static int viafb_iga1_odev_proc_show(struct seq_file *m, void *v)
drivers/video/fbdev/via/viafbdev.c
1528
static int viafb_iga2_odev_proc_show(struct seq_file *m, void *v)
drivers/video/fbdev/xen-fbfront.c
217
u32 v;
drivers/video/fbdev/xen-fbfront.c
228
v = (red << info->var.red.offset) |
drivers/video/fbdev/xen-fbfront.c
236
((u32 *)info->pseudo_palette)[regno] = v;
drivers/virtio/virtio_pci_common.c
132
unsigned int i, v;
drivers/virtio/virtio_pci_common.c
164
v = vp_dev->msix_used_vectors;
drivers/virtio/virtio_pci_common.c
165
snprintf(vp_dev->msix_names[v], sizeof *vp_dev->msix_names,
drivers/virtio/virtio_pci_common.c
167
err = request_irq(pci_irq_vector(vp_dev->pci_dev, v),
drivers/virtio/virtio_pci_common.c
168
vp_config_changed, 0, vp_dev->msix_names[v],
drivers/virtio/virtio_pci_common.c
174
v = vp_dev->config_vector(vp_dev, v);
drivers/virtio/virtio_pci_common.c
176
if (v == VIRTIO_MSI_NO_VECTOR) {
drivers/virtio/virtio_pci_common.c
183
v = vp_dev->msix_used_vectors;
drivers/virtio/virtio_pci_common.c
184
snprintf(vp_dev->msix_names[v], sizeof *vp_dev->msix_names,
drivers/virtio/virtio_pci_common.c
186
err = request_irq(pci_irq_vector(vp_dev->pci_dev, v),
drivers/virtio/virtio_pci_common.c
187
vp_vring_interrupt, 0, vp_dev->msix_names[v],
drivers/virtio/virtio_pci_common.c
276
int v = info->msix_vector;
drivers/virtio/virtio_pci_common.c
277
if (v != VIRTIO_MSI_NO_VECTOR &&
drivers/virtio/virtio_pci_common.c
278
!vp_is_slow_path_vector(v)) {
drivers/virtio/virtio_pci_common.c
279
int irq = pci_irq_vector(vp_dev->pci_dev, v);
drivers/watchdog/octeon-wdt-main.c
177
int v;
drivers/watchdog/octeon-wdt-main.c
180
v = (value >> ((digits - d - 1) * 4)) & 0xf;
drivers/watchdog/octeon-wdt-main.c
181
if (v >= 10)
drivers/watchdog/octeon-wdt-main.c
182
prom_putchar('a' + v - 10);
drivers/watchdog/octeon-wdt-main.c
184
prom_putchar('0' + v);
drivers/watchdog/orion_wdt.c
48
#define WDT_A370_RATIO_MASK(v) ((v) << 16)
drivers/watchdog/pic32-dmt.c
108
u32 v;
drivers/watchdog/pic32-dmt.c
115
v = readl(rst_base);
drivers/watchdog/pic32-dmt.c
120
return v & RESETCON_DMT_TIMEOUT;
drivers/watchdog/pic32-dmt.c
75
u32 v;
drivers/watchdog/pic32-dmt.c
83
v = readl(dmt->regs + DMTSTAT_REG) & DMTSTAT_WINOPN;
drivers/watchdog/pic32-dmt.c
84
if (v == DMTSTAT_WINOPN)
drivers/watchdog/pic32-wdt.c
50
u32 v = readl(wdt->regs + WDTCON_REG);
drivers/watchdog/pic32-wdt.c
52
return (v >> WDTCON_RMPS_SHIFT) & WDTCON_RMPS_MASK;
drivers/watchdog/pic32-wdt.c
57
u32 v = readl(wdt->regs + WDTCON_REG);
drivers/watchdog/pic32-wdt.c
59
return (v >> WDTCON_RMCS_SHIFT) & WDTCON_RMCS_MASK;
drivers/watchdog/pic32-wdt.c
64
u32 v = readl(wdt->rst_base);
drivers/watchdog/pic32-wdt.c
68
return v & RESETCON_WDT_TIMEOUT;
drivers/watchdog/realtek_otto_wdt.c
135
u32 v;
drivers/watchdog/realtek_otto_wdt.c
151
v = ioread32(ctrl->base + OTTO_WDT_REG_CTRL);
drivers/watchdog/realtek_otto_wdt.c
153
v &= ~(OTTO_WDT_CTRL_PRESCALE | OTTO_WDT_CTRL_PHASE1 | OTTO_WDT_CTRL_PHASE2);
drivers/watchdog/realtek_otto_wdt.c
154
v |= FIELD_PREP(OTTO_WDT_CTRL_PHASE1, phase1_ticks - 1);
drivers/watchdog/realtek_otto_wdt.c
155
v |= FIELD_PREP(OTTO_WDT_CTRL_PHASE2, phase2_ticks - 1);
drivers/watchdog/realtek_otto_wdt.c
156
v |= FIELD_PREP(OTTO_WDT_CTRL_PRESCALE, prescale);
drivers/watchdog/realtek_otto_wdt.c
158
iowrite32(v, ctrl->base + OTTO_WDT_REG_CTRL);
drivers/watchdog/realtek_otto_wdt.c
184
u32 v;
drivers/watchdog/realtek_otto_wdt.c
201
v = FIELD_PREP(OTTO_WDT_CTRL_RST_MODE, reset_mode) | OTTO_WDT_CTRL_ENABLE;
drivers/watchdog/realtek_otto_wdt.c
202
iowrite32(v, ctrl->base + OTTO_WDT_REG_CTRL);
drivers/watchdog/realtek_otto_wdt.c
259
u32 v;
drivers/watchdog/realtek_otto_wdt.c
281
v = ioread32(ctrl->base + OTTO_WDT_REG_CTRL);
drivers/watchdog/realtek_otto_wdt.c
282
v &= ~OTTO_WDT_CTRL_RST_MODE;
drivers/watchdog/realtek_otto_wdt.c
283
v |= FIELD_PREP(OTTO_WDT_CTRL_RST_MODE, mode);
drivers/watchdog/realtek_otto_wdt.c
284
iowrite32(v, ctrl->base + OTTO_WDT_REG_CTRL);
drivers/watchdog/realtek_otto_wdt.c
77
u32 v;
drivers/watchdog/realtek_otto_wdt.c
79
v = ioread32(ctrl->base + OTTO_WDT_REG_CTRL);
drivers/watchdog/realtek_otto_wdt.c
80
v |= OTTO_WDT_CTRL_ENABLE;
drivers/watchdog/realtek_otto_wdt.c
81
iowrite32(v, ctrl->base + OTTO_WDT_REG_CTRL);
drivers/watchdog/realtek_otto_wdt.c
89
u32 v;
drivers/watchdog/realtek_otto_wdt.c
91
v = ioread32(ctrl->base + OTTO_WDT_REG_CTRL);
drivers/watchdog/realtek_otto_wdt.c
92
v &= ~OTTO_WDT_CTRL_ENABLE;
drivers/watchdog/realtek_otto_wdt.c
93
iowrite32(v, ctrl->base + OTTO_WDT_REG_CTRL);
drivers/xen/balloon.c
359
static int xen_memory_notifier(struct notifier_block *nb, unsigned long val, void *v)
drivers/xen/events/events_2l.c
272
struct vcpu_info *v;
drivers/xen/events/events_2l.c
280
v = per_cpu(xen_vcpu, i);
drivers/xen/events/events_2l.c
283
: v->evtchn_upcall_mask;
drivers/xen/events/events_2l.c
285
pending, v->evtchn_upcall_pending,
drivers/xen/events/events_2l.c
286
(int)(sizeof(v->evtchn_pending_sel)*2),
drivers/xen/events/events_2l.c
287
v->evtchn_pending_sel);
drivers/xen/events/events_2l.c
289
v = per_cpu(xen_vcpu, cpu);
drivers/xen/events/events_2l.c
334
sync_test_bit(word_idx, BM(&v->evtchn_pending_sel))
drivers/xen/time.c
156
area.addr.v = &per_cpu(xen_runstate, cpu);
drivers/xen/xen-scsiback.c
1016
struct ids_tuple *v)
drivers/xen/xen-scsiback.c
1023
entry = scsiback_chk_translation_entry(info, v);
drivers/xen/xen-scsiback.c
649
struct ids_tuple *v)
drivers/xen/xen-scsiback.c
657
if ((entry->v.chn == v->chn) &&
drivers/xen/xen-scsiback.c
658
(entry->v.tgt == v->tgt) &&
drivers/xen/xen-scsiback.c
659
(entry->v.lun == v->lun)) {
drivers/xen/xen-scsiback.c
78
struct ids_tuple v; /* translate from */
drivers/xen/xen-scsiback.c
904
struct vscsibk_info *info, struct ids_tuple *v)
drivers/xen/xen-scsiback.c
910
if ((entry->v.chn == v->chn) &&
drivers/xen/xen-scsiback.c
911
(entry->v.tgt == v->tgt) &&
drivers/xen/xen-scsiback.c
912
(entry->v.lun == v->lun))
drivers/xen/xen-scsiback.c
922
char *phy, struct ids_tuple *v)
drivers/xen/xen-scsiback.c
985
if (scsiback_chk_translation_entry(info, v)) {
drivers/xen/xen-scsiback.c
993
new->v = *v;
drivers/xen/xenbus/xenbus_probe.c
1007
err = hvm_get_parameter(HVM_PARAM_STORE_EVTCHN, &v);
drivers/xen/xenbus/xenbus_probe.c
1010
xen_store_evtchn = (int)v;
drivers/xen/xenbus/xenbus_probe.c
1011
if (!v && xen_initial_domain())
drivers/xen/xenbus/xenbus_probe.c
1032
err = hvm_get_parameter(HVM_PARAM_STORE_PFN, &v);
drivers/xen/xenbus/xenbus_probe.c
1045
if (!v) {
drivers/xen/xenbus/xenbus_probe.c
1049
if (v == ~0ULL) {
drivers/xen/xenbus/xenbus_probe.c
1054
if (v > ULONG_MAX) {
drivers/xen/xenbus/xenbus_probe.c
1056
__func__, v);
drivers/xen/xenbus/xenbus_probe.c
1061
xen_store_gfn = (unsigned long)v;
drivers/xen/xenbus/xenbus_probe.c
1067
__func__, v);
drivers/xen/xenbus/xenbus_probe.c
958
uint64_t v = 0;
drivers/xen/xenbus/xenbus_probe.c
960
err = hvm_get_parameter(HVM_PARAM_STORE_EVTCHN, &v);
drivers/xen/xenbus/xenbus_probe.c
961
if (!err && v)
drivers/xen/xenbus/xenbus_probe.c
962
xen_store_evtchn = v;
drivers/xen/xenbus/xenbus_probe.c
979
uint64_t v = 0;
drivers/xen/xenbus/xenbus_probe.c
981
err = hvm_get_parameter(HVM_PARAM_STORE_PFN, &v);
drivers/xen/xenbus/xenbus_probe.c
982
if (err || !v || !~v)
drivers/xen/xenbus/xenbus_probe.c
984
xen_store_gfn = (unsigned long)v;
drivers/xen/xenbus/xenbus_probe.c
993
uint64_t v = 0;
drivers/zorro/proc.c
69
static void * zorro_seq_next(struct seq_file *m, void *v, loff_t *pos)
drivers/zorro/proc.c
75
static void zorro_seq_stop(struct seq_file *m, void *v)
drivers/zorro/proc.c
79
static int zorro_seq_show(struct seq_file *m, void *v)
drivers/zorro/proc.c
81
unsigned int slot = *(loff_t *)v;
fs/adfs/dir_f.c
117
__le32 v = *ptr.ptr32++;
fs/adfs/dir_f.c
118
dircheck = le32_to_cpu(v) ^ ror13(dircheck);
fs/adfs/dir_f.c
44
#define ror13(v) ((v >> 13) | (v << 19))
fs/afs/proc.c
154
static int afs_proc_addr_prefs_show(struct seq_file *m, void *v)
fs/afs/proc.c
204
static int afs_proc_rootcell_show(struct seq_file *m, void *v)
fs/afs/proc.c
267
static int afs_proc_cell_volumes_show(struct seq_file *m, void *v)
fs/afs/proc.c
269
struct afs_volume *vol = hlist_entry(v, struct afs_volume, proc_link);
fs/afs/proc.c
272
if (v == SEQ_START_TOKEN) {
fs/afs/proc.c
294
static void *afs_proc_cell_volumes_next(struct seq_file *m, void *v,
fs/afs/proc.c
299
return seq_hlist_next_rcu(v, &cell->proc_volumes, _pos);
fs/afs/proc.c
302
static void afs_proc_cell_volumes_stop(struct seq_file *m, void *v)
fs/afs/proc.c
34
static int afs_proc_cells_show(struct seq_file *m, void *v)
fs/afs/proc.c
340
static int afs_proc_cell_vlservers_show(struct seq_file *m, void *v)
fs/afs/proc.c
349
if (v == SEQ_START_TOKEN) {
fs/afs/proc.c
356
entry = v;
fs/afs/proc.c
39
if (v == SEQ_START_TOKEN) {
fs/afs/proc.c
402
static void *afs_proc_cell_vlservers_next(struct seq_file *m, void *v,
fs/afs/proc.c
418
static void afs_proc_cell_vlservers_stop(struct seq_file *m, void *v)
fs/afs/proc.c
434
static int afs_proc_servers_show(struct seq_file *m, void *v)
fs/afs/proc.c
442
if (v == SEQ_START_TOKEN) {
fs/afs/proc.c
447
server = list_entry(v, struct afs_server, proc_link);
fs/afs/proc.c
45
cell = list_entry(v, struct afs_cell, proc_link);
fs/afs/proc.c
491
static void *afs_proc_servers_next(struct seq_file *m, void *v, loff_t *_pos)
fs/afs/proc.c
493
return seq_hlist_next_rcu(v, &afs_seq2net(m)->fs_proc, _pos);
fs/afs/proc.c
496
static void afs_proc_servers_stop(struct seq_file *m, void *v)
fs/afs/proc.c
513
static int afs_proc_sysname_show(struct seq_file *m, void *v)
fs/afs/proc.c
517
unsigned int i = (unsigned long)v - 1;
fs/afs/proc.c
538
static void *afs_proc_sysname_next(struct seq_file *m, void *v, loff_t *pos)
fs/afs/proc.c
549
static void afs_proc_sysname_stop(struct seq_file *m, void *v)
fs/afs/proc.c
658
static int afs_proc_stats_show(struct seq_file *m, void *v)
fs/afs/proc.c
66
static void *afs_proc_cells_next(struct seq_file *m, void *v, loff_t *pos)
fs/afs/proc.c
68
return seq_hlist_next_rcu(v, &afs_seq2net(m)->proc_cells, pos);
fs/afs/proc.c
71
static void afs_proc_cells_stop(struct seq_file *m, void *v)
fs/btrfs/accessors.h
25
#define le8_to_cpu(v) (v)
fs/btrfs/accessors.h
26
#define cpu_to_le8(v) (v)
fs/ceph/dir.c
100
int v = ceph_frag_compare(fpos_frag(l), fpos_frag(r));
fs/ceph/dir.c
101
if (v)
fs/ceph/dir.c
102
return v;
fs/ceph/inode.c
366
static u32 __ceph_choose_frag(struct ceph_inode_info *ci, u32 v,
fs/ceph/inode.c
379
WARN_ON(!ceph_frag_contains_value(t, v));
fs/ceph/inode.c
393
doutc(cl, "frag(%x) %x splits by %d (%d ways)\n", v, t,
fs/ceph/inode.c
397
if (ceph_frag_contains_value(n, v)) {
fs/ceph/inode.c
404
doutc(cl, "frag(%x) = %x\n", v, t);
fs/ceph/inode.c
409
u32 ceph_choose_frag(struct ceph_inode_info *ci, u32 v,
fs/ceph/inode.c
414
ret = __ceph_choose_frag(ci, v, pfrag, found);
fs/ceph/locks.c
19
u64 v = lock_secret ^ (u64)(unsigned long)addr;
fs/ceph/locks.c
25
v |= (1ULL << 63);
fs/ceph/locks.c
26
return v;
fs/ceph/super.h
773
extern u32 ceph_choose_frag(struct ceph_inode_info *ci, u32 v,
fs/dax.c
329
unsigned long v = xa_to_value(entry);
fs/dax.c
330
return xas_store(xas, xa_mk_value(v | DAX_LOCKED));
fs/dlm/dir.c
106
__be16 v;
fs/dlm/dir.c
112
memcpy(&v, b, sizeof(__be16));
fs/dlm/dir.c
113
namelen = be16_to_cpu(v);
fs/erofs/data.c
240
void *v;
fs/erofs/data.c
243
folio->private = u.v; /* valid only if file-backed folio is locked */
fs/erofs/data.c
253
int orig, v;
fs/erofs/data.c
258
v = dirty << EROFS_ONLINEFOLIO_DIRTY;
fs/erofs/data.c
259
v |= (orig - 1) | (!!err << EROFS_ONLINEFOLIO_EIO);
fs/erofs/data.c
260
} while (atomic_cmpxchg((atomic_t *)&folio->private, orig, v) != orig);
fs/erofs/data.c
262
if (v & (BIT(EROFS_ONLINEFOLIO_DIRTY) - 1))
fs/erofs/data.c
265
if (v & BIT(EROFS_ONLINEFOLIO_DIRTY))
fs/erofs/data.c
267
folio_end_read(folio, !(v & BIT(EROFS_ONLINEFOLIO_EIO)));
fs/erofs/zmap.c
66
const unsigned int v = get_unaligned_le32(in + pos / 8) >> (pos & 7);
fs/erofs/zmap.c
67
const unsigned int lo = v & ((1 << lobits) - 1);
fs/erofs/zmap.c
69
*type = (v >> lobits) & 3;
fs/eventpoll.c
859
struct epitems_head *v;
fs/eventpoll.c
860
v = container_of(head, struct epitems_head, epitems);
fs/eventpoll.c
861
if (!smp_load_acquire(&v->next))
fs/eventpoll.c
862
to_free = v;
fs/ext2/inode.c
120
static inline void add_chain(Indirect *p, struct buffer_head *bh, __le32 *v)
fs/ext2/inode.c
122
p->key = *(p->p = v);
fs/ext4/ext4.h
2968
int ext4_fc_info_show(struct seq_file *seq, void *v);
fs/ext4/extents_status.c
1789
int ext4_seq_es_shrinker_info_show(struct seq_file *seq, void *v)
fs/ext4/extents_status.c
1796
if (v != SEQ_START_TOKEN)
fs/ext4/extents_status.h
242
extern int ext4_seq_es_shrinker_info_show(struct seq_file *seq, void *v);
fs/ext4/fast_commit.c
2318
int ext4_fc_info_show(struct seq_file *seq, void *v)
fs/ext4/fast_commit.c
2324
if (v != SEQ_START_TOKEN)
fs/ext4/indirect.c
37
static inline void add_chain(Indirect *p, struct buffer_head *bh, __le32 *v)
fs/ext4/indirect.c
39
p->key = *(p->p = v);
fs/ext4/mballoc.c
3131
static void *ext4_mb_seq_groups_next(struct seq_file *seq, void *v, loff_t *pos)
fs/ext4/mballoc.c
3143
static int ext4_mb_seq_groups_show(struct seq_file *seq, void *v)
fs/ext4/mballoc.c
3146
ext4_group_t group = (ext4_group_t) ((unsigned long) v);
fs/ext4/mballoc.c
3196
static void ext4_mb_seq_groups_stop(struct seq_file *seq, void *v)
fs/ext4/mballoc.c
3321
static void *ext4_mb_seq_structs_summary_next(struct seq_file *seq, void *v, loff_t *pos)
fs/ext4/mballoc.c
3333
static int ext4_mb_seq_structs_summary_show(struct seq_file *seq, void *v)
fs/ext4/mballoc.c
3337
unsigned long position = ((unsigned long) v);
fs/ext4/mballoc.c
3370
static void ext4_mb_seq_structs_summary_stop(struct seq_file *seq, void *v)
fs/ext4/super.c
4591
unsigned v, max = (sbi->s_inode_size -
fs/ext4/super.c
4594
v = le16_to_cpu(es->s_want_extra_isize);
fs/ext4/super.c
4595
if (v > max) {
fs/ext4/super.c
4597
"bad s_want_extra_isize: %d", v);
fs/ext4/super.c
4600
if (sbi->s_want_extra_isize < v)
fs/ext4/super.c
4601
sbi->s_want_extra_isize = v;
fs/ext4/super.c
4603
v = le16_to_cpu(es->s_min_extra_isize);
fs/ext4/super.c
4604
if (v > max) {
fs/ext4/super.c
4606
"bad s_min_extra_isize: %d", v);
fs/ext4/super.c
4609
if (sbi->s_want_extra_isize < v)
fs/ext4/super.c
4610
sbi->s_want_extra_isize = v;
fs/f2fs/debug.c
440
static int stat_show(struct seq_file *s, void *v)
fs/f2fs/f2fs.h
2618
unsigned long v = (1UL << PAGE_PRIVATE_NOT_POINTER) | \
fs/f2fs/f2fs.h
2620
return (priv & v) == v; \
fs/f2fs/f2fs.h
2632
unsigned long v = (1UL << PAGE_PRIVATE_NOT_POINTER) | \
fs/f2fs/f2fs.h
2635
folio_attach_private(folio, (void *)v); \
fs/f2fs/f2fs.h
2637
v |= (unsigned long)folio->private; \
fs/f2fs/f2fs.h
2638
folio->private = (void *)v; \
fs/f2fs/f2fs.h
2652
unsigned long v = (unsigned long)folio->private; \
fs/f2fs/f2fs.h
2654
v &= ~(1UL << PAGE_PRIVATE_##flagname); \
fs/f2fs/f2fs.h
2655
if (v == (1UL << PAGE_PRIVATE_NOT_POINTER)) \
fs/f2fs/f2fs.h
2658
folio->private = (void *)v; \
fs/f2fs/node.h
78
#define nat_set_version(nat, v) ((nat)->ni.version = (v))
fs/filesystems.c
238
static int filesystems_proc_show(struct seq_file *m, void *v)
fs/fuse/file.c
420
u64 v = (unsigned long) id;
fs/fuse/file.c
421
u32 v0 = v;
fs/fuse/file.c
422
u32 v1 = v >> 32;
fs/hfs/bnode.c
162
__be16 v = cpu_to_be16(data);
fs/hfs/bnode.c
164
hfs_bnode_write(node, &v, off, 2);
fs/hfsplus/bnode.c
131
__be16 v = cpu_to_be16(data);
fs/hfsplus/bnode.c
133
hfs_bnode_write(node, &v, off, 2);
fs/hfsplus/unicode.c
364
int l, v, t;
fs/hfsplus/unicode.c
371
v = Hangul_VBase + (index % Hangul_NCount) / Hangul_TCount;
fs/hfsplus/unicode.c
375
result[1] = v;
fs/jbd2/journal.c
1118
static void *jbd2_seq_info_next(struct seq_file *seq, void *v, loff_t *pos)
fs/jbd2/journal.c
1124
static int jbd2_seq_info_show(struct seq_file *seq, void *v)
fs/jbd2/journal.c
1128
if (v != SEQ_START_TOKEN)
fs/jbd2/journal.c
1161
static void jbd2_seq_info_stop(struct seq_file *seq, void *v)
fs/jffs2/wbuf.c
861
uint8_t *v = invecs[invec].iov_base;
fs/jffs2/wbuf.c
863
wbuf_retlen = jffs2_fill_wbuf(c, v, vlen);
fs/jffs2/wbuf.c
873
v += wbuf_retlen;
fs/jffs2/wbuf.c
877
&wbuf_retlen, v);
fs/jffs2/wbuf.c
885
v += wbuf_retlen;
fs/jffs2/wbuf.c
888
wbuf_retlen = jffs2_fill_wbuf(c, v, vlen);
fs/jfs/jfs_debug.c
20
static int jfs_loglevel_proc_show(struct seq_file *m, void *v)
fs/jfs/jfs_debug.h
52
int jfs_txanchor_proc_show(struct seq_file *m, void *v);
fs/jfs/jfs_debug.h
95
int jfs_lmstats_proc_show(struct seq_file *m, void *v);
fs/jfs/jfs_debug.h
96
int jfs_txstats_proc_show(struct seq_file *m, void *v);
fs/jfs/jfs_debug.h
97
int jfs_mpstat_proc_show(struct seq_file *m, void *v);
fs/jfs/jfs_debug.h
98
int jfs_xtstat_proc_show(struct seq_file *m, void *v);
fs/jfs/jfs_logmgr.c
2474
int jfs_lmstats_proc_show(struct seq_file *m, void *v)
fs/jfs/jfs_metapage.c
939
int jfs_mpstat_proc_show(struct seq_file *m, void *v)
fs/jfs/jfs_txnmgr.c
2958
int jfs_txanchor_proc_show(struct seq_file *m, void *v)
fs/jfs/jfs_txnmgr.c
2995
int jfs_txstats_proc_show(struct seq_file *m, void *v)
fs/jfs/jfs_xtree.c
2917
int jfs_xtstat_proc_show(struct seq_file *m, void *v)
fs/kernfs/dir.c
467
int v;
fs/kernfs/dir.c
474
v = atomic_dec_return(&kn->active);
fs/kernfs/dir.c
475
if (likely(v != KN_DEACTIVATED_BIAS))
fs/kernfs/file.c
153
static void kernfs_seq_stop_active(struct seq_file *sf, void *v)
fs/kernfs/file.c
159
ops->seq_stop(sf, v);
fs/kernfs/file.c
187
static void *kernfs_seq_next(struct seq_file *sf, void *v, loff_t *ppos)
fs/kernfs/file.c
193
void *next = ops->seq_next(sf, v, ppos);
fs/kernfs/file.c
208
static void kernfs_seq_stop(struct seq_file *sf, void *v)
fs/kernfs/file.c
212
if (v != ERR_PTR(-ENODEV))
fs/kernfs/file.c
213
kernfs_seq_stop_active(sf, v);
fs/kernfs/file.c
217
static int kernfs_seq_show(struct seq_file *sf, void *v)
fs/kernfs/file.c
223
return of->kn->attr.ops->seq_show(sf, v);
fs/locks.c
2934
static int locks_show(struct seq_file *f, void *v)
fs/locks.c
2941
cur = hlist_entry(v, struct file_lock_core, flc_link);
fs/locks.c
3027
static void *locks_next(struct seq_file *f, void *v, loff_t *pos)
fs/locks.c
3032
return seq_hlist_next_percpu(v, &file_lock_list.hlist, &iter->li_cpu, pos);
fs/locks.c
3035
static void locks_stop(struct seq_file *f, void *v)
fs/minix/itree_common.c
12
static inline void add_chain(Indirect *p, struct buffer_head *bh, block_t *v)
fs/minix/itree_common.c
14
p->key = *(p->p = v);
fs/namei.c
310
static inline int __delayed_getname(struct delayed_filename *v,
fs/namei.c
313
v->__incomplete_filename = do_getname(string, flags, true);
fs/namei.c
314
return PTR_ERR_OR_ZERO(v->__incomplete_filename);
fs/namei.c
317
int delayed_getname(struct delayed_filename *v, const char __user *string)
fs/namei.c
319
return __delayed_getname(v, string, 0);
fs/namei.c
322
int delayed_getname_uflags(struct delayed_filename *v, const char __user *string,
fs/namei.c
326
return __delayed_getname(v, string, flags);
fs/namei.c
329
int putname_to_delayed(struct delayed_filename *v, struct filename *name)
fs/namei.c
332
v->__incomplete_filename = name;
fs/namei.c
336
v->__incomplete_filename = do_getname_kernel(name->name, true);
fs/namei.c
337
return PTR_ERR_OR_ZERO(v->__incomplete_filename);
fs/namei.c
340
void dismiss_delayed_filename(struct delayed_filename *v)
fs/namei.c
342
putname(no_free_ptr(v->__incomplete_filename));
fs/namei.c
345
struct filename *complete_getname(struct delayed_filename *v)
fs/namei.c
347
struct filename *res = no_free_ptr(v->__incomplete_filename);
fs/namespace.c
1544
static void *m_next(struct seq_file *m, void *v, loff_t *pos)
fs/namespace.c
1546
struct mount *mnt = v;
fs/namespace.c
1563
static void m_stop(struct seq_file *m, void *v)
fs/namespace.c
1568
static int m_show(struct seq_file *m, void *v)
fs/namespace.c
1571
struct mount *r = v;
fs/netfs/fscache_cache.c
380
static int fscache_caches_seq_show(struct seq_file *m, void *v)
fs/netfs/fscache_cache.c
384
if (v == &fscache_caches) {
fs/netfs/fscache_cache.c
392
cache = list_entry(v, struct fscache_cache, cache_link);
fs/netfs/fscache_cache.c
412
static void *fscache_caches_seq_next(struct seq_file *m, void *v, loff_t *_pos)
fs/netfs/fscache_cache.c
414
return seq_list_next(v, &fscache_caches, _pos);
fs/netfs/fscache_cache.c
417
static void fscache_caches_seq_stop(struct seq_file *m, void *v)
fs/netfs/fscache_cookie.c
1111
static int fscache_cookies_seq_show(struct seq_file *m, void *v)
fs/netfs/fscache_cookie.c
1117
if (v == &fscache_cookies) {
fs/netfs/fscache_cookie.c
1125
cookie = list_entry(v, struct fscache_cookie, proc_link);
fs/netfs/fscache_cookie.c
1166
static void *fscache_cookies_seq_next(struct seq_file *m, void *v, loff_t *_pos)
fs/netfs/fscache_cookie.c
1168
return seq_list_next(v, &fscache_cookies, _pos);
fs/netfs/fscache_cookie.c
1171
static void fscache_cookies_seq_stop(struct seq_file *m, void *v)
fs/netfs/fscache_volume.c
484
static int fscache_volumes_seq_show(struct seq_file *m, void *v)
fs/netfs/fscache_volume.c
488
if (v == &fscache_volumes) {
fs/netfs/fscache_volume.c
495
volume = list_entry(v, struct fscache_volume, proc_link);
fs/netfs/fscache_volume.c
515
static void *fscache_volumes_seq_next(struct seq_file *m, void *v, loff_t *_pos)
fs/netfs/fscache_volume.c
517
return seq_list_next(v, &fscache_volumes, _pos);
fs/netfs/fscache_volume.c
520
static void fscache_volumes_seq_stop(struct seq_file *m, void *v)
fs/netfs/internal.h
170
int netfs_stats_show(struct seq_file *m, void *v);
fs/netfs/main.c
55
static int netfs_requests_seq_show(struct seq_file *m, void *v)
fs/netfs/main.c
59
if (v == &netfs_io_requests) {
fs/netfs/main.c
67
rreq = list_entry(v, struct netfs_io_request, proc_link);
fs/netfs/main.c
88
static void *netfs_requests_seq_next(struct seq_file *m, void *v, loff_t *_pos)
fs/netfs/main.c
90
return seq_list_next(v, &netfs_io_requests, _pos);
fs/netfs/main.c
93
static void netfs_requests_seq_stop(struct seq_file *m, void *v)
fs/netfs/stats.c
52
int netfs_stats_show(struct seq_file *m, void *v)
fs/nfs/blocklayout/dev.c
297
struct pnfs_block_volume *v = &volumes[idx];
fs/nfs/blocklayout/dev.c
301
dev = bl_resolve_deviceid(server, v, gfp_mask);
fs/nfs/blocklayout/dev.c
322
bl_validate_designator(struct pnfs_block_volume *v)
fs/nfs/blocklayout/dev.c
324
switch (v->scsi.designator_type) {
fs/nfs/blocklayout/dev.c
326
if (v->scsi.code_set != PS_CODE_SET_BINARY)
fs/nfs/blocklayout/dev.c
329
if (v->scsi.designator_len != 8 &&
fs/nfs/blocklayout/dev.c
330
v->scsi.designator_len != 10 &&
fs/nfs/blocklayout/dev.c
331
v->scsi.designator_len != 16)
fs/nfs/blocklayout/dev.c
336
if (v->scsi.code_set != PS_CODE_SET_BINARY)
fs/nfs/blocklayout/dev.c
339
if (v->scsi.designator_len != 8 &&
fs/nfs/blocklayout/dev.c
340
v->scsi.designator_len != 16)
fs/nfs/blocklayout/dev.c
348
v->scsi.code_set,
fs/nfs/blocklayout/dev.c
349
v->scsi.designator_type,
fs/nfs/blocklayout/dev.c
350
v->scsi.designator_len);
fs/nfs/blocklayout/dev.c
355
v->scsi.code_set,
fs/nfs/blocklayout/dev.c
356
v->scsi.designator_type,
fs/nfs/blocklayout/dev.c
357
v->scsi.designator_len);
fs/nfs/blocklayout/dev.c
363
bl_open_path(struct pnfs_block_volume *v, const char *prefix)
fs/nfs/blocklayout/dev.c
369
prefix, v->scsi.designator_len, v->scsi.designator);
fs/nfs/blocklayout/dev.c
388
struct pnfs_block_volume *v = &volumes[idx];
fs/nfs/blocklayout/dev.c
394
if (!bl_validate_designator(v))
fs/nfs/blocklayout/dev.c
403
bdev_file = bl_open_path(v, "dm-uuid-mpath-0x");
fs/nfs/blocklayout/dev.c
405
bdev_file = bl_open_path(v, "wwn-0x");
fs/nfs/blocklayout/dev.c
407
bdev_file = bl_open_path(v, "nvme-eui.");
fs/nfs/blocklayout/dev.c
410
v->scsi.designator_len, v->scsi.designator);
fs/nfs/blocklayout/dev.c
418
d->pr_key = v->scsi.pr_key;
fs/nfs/blocklayout/dev.c
444
struct pnfs_block_volume *v = &volumes[idx];
fs/nfs/blocklayout/dev.c
447
ret = bl_parse_deviceid(server, d, volumes, v->slice.volume, gfp_mask);
fs/nfs/blocklayout/dev.c
451
d->disk_offset = v->slice.start;
fs/nfs/blocklayout/dev.c
452
d->len = v->slice.len;
fs/nfs/blocklayout/dev.c
460
struct pnfs_block_volume *v = &volumes[idx];
fs/nfs/blocklayout/dev.c
465
v->concat.volumes_count, gfp_mask);
fs/nfs/blocklayout/dev.c
469
for (i = 0; i < v->concat.volumes_count; i++) {
fs/nfs/blocklayout/dev.c
471
volumes, v->concat.volumes[i], gfp_mask);
fs/nfs/blocklayout/dev.c
489
struct pnfs_block_volume *v = &volumes[idx];
fs/nfs/blocklayout/dev.c
494
v->stripe.volumes_count, gfp_mask);
fs/nfs/blocklayout/dev.c
498
for (i = 0; i < v->stripe.volumes_count; i++) {
fs/nfs/blocklayout/dev.c
500
volumes, v->stripe.volumes[i], gfp_mask);
fs/nfs/blocklayout/dev.c
509
d->chunk_size = v->stripe.chunk_size;
fs/nfs/client.c
1296
static void *nfs_server_list_next(struct seq_file *p, void *v, loff_t *pos);
fs/nfs/client.c
1297
static void nfs_server_list_stop(struct seq_file *p, void *v);
fs/nfs/client.c
1298
static int nfs_server_list_show(struct seq_file *m, void *v);
fs/nfs/client.c
1308
static void *nfs_volume_list_next(struct seq_file *p, void *v, loff_t *pos);
fs/nfs/client.c
1309
static void nfs_volume_list_stop(struct seq_file *p, void *v);
fs/nfs/client.c
1310
static int nfs_volume_list_show(struct seq_file *m, void *v);
fs/nfs/client.c
1335
static void *nfs_server_list_next(struct seq_file *p, void *v, loff_t *pos)
fs/nfs/client.c
1339
return seq_list_next(v, &nn->nfs_client_list, pos);
fs/nfs/client.c
1345
static void nfs_server_list_stop(struct seq_file *p, void *v)
fs/nfs/client.c
1356
static int nfs_server_list_show(struct seq_file *m, void *v)
fs/nfs/client.c
1362
if (v == &nn->nfs_client_list) {
fs/nfs/client.c
1368
clp = list_entry(v, struct nfs_client, cl_share_link);
fs/nfs/client.c
1402
static void *nfs_volume_list_next(struct seq_file *p, void *v, loff_t *pos)
fs/nfs/client.c
1406
return seq_list_next(v, &nn->nfs_volume_list, pos);
fs/nfs/client.c
1412
static void nfs_volume_list_stop(struct seq_file *p, void *v)
fs/nfs/client.c
1423
static int nfs_volume_list_show(struct seq_file *m, void *v)
fs/nfs/client.c
1432
if (v == &nn->nfs_volume_list) {
fs/nfs/client.c
1438
server = list_entry(v, struct nfs_server, master_link);
fs/nfs/localio.c
474
unsigned long v, total;
fs/nfs/localio.c
478
v = 0;
fs/nfs/localio.c
483
while (total && v < hdr->page_array.npages) {
fs/nfs/localio.c
485
bvec_set_page(&iocb->bvec[v], *pagevec, len, base);
fs/nfs/localio.c
488
++v;
fs/nfs/localio.c
503
nfs_local_iters_setup_dio(iocb, rw, v, len, &local_dio) != 0) {
fs/nfs/localio.c
512
iov_iter_bvec(&iocb->iters[0], rw, iocb->bvec, v, len);
fs/nfs/nfstrace.h
1674
#define nfs_show_direct_req_flags(v) \
fs/nfs/nfstrace.h
1675
__print_flags(v, "|", \
fs/nfs/nfstrace.h
18
#define nfs_show_cache_validity(v) \
fs/nfs/nfstrace.h
19
__print_flags(v, "|", \
fs/nfs/nfstrace.h
38
#define nfs_show_nfsi_flags(v) \
fs/nfs/nfstrace.h
39
__print_flags(v, "|", \
fs/nfs/nfstrace.h
48
#define nfs_show_wb_flags(v) \
fs/nfs/nfstrace.h
49
__print_flags(v, "|", \
fs/nfsd/cache.h
89
int nfsd_reply_cache_stats_show(struct seq_file *m, void *v);
fs/nfsd/filecache.c
1384
int nfsd_file_cache_stats_show(struct seq_file *m, void *v)
fs/nfsd/filecache.h
87
int nfsd_file_cache_stats_show(struct seq_file *m, void *v);
fs/nfsd/nfs4state.c
2791
static int client_info_show(struct seq_file *m, void *v)
fs/nfsd/nfs4state.c
2861
static void *states_next(struct seq_file *s, void *v, loff_t *pos)
fs/nfsd/nfs4state.c
2874
static void states_stop(struct seq_file *s, void *v)
fs/nfsd/nfs4state.c
3069
static int states_show(struct seq_file *s, void *v)
fs/nfsd/nfs4state.c
3071
struct nfs4_stid *st = v;
fs/nfsd/nfscache.c
644
int nfsd_reply_cache_stats_show(struct seq_file *m, void *v)
fs/nfsd/nfsctl.c
177
static int export_features_show(struct seq_file *m, void *v)
fs/nfsd/stats.c
30
static int nfsd_show(struct seq_file *seq, void *v)
fs/nfsd/vfs.c
1117
unsigned long v, total;
fs/nfsd/vfs.c
1132
v = 0;
fs/nfsd/vfs.c
1134
while (total && v < rqstp->rq_maxpages &&
fs/nfsd/vfs.c
1137
bvec_set_page(&rqstp->rq_bvec[v], *rqstp->rq_next_page,
fs/nfsd/vfs.c
1142
++v;
fs/nfsd/vfs.c
1146
iov_iter_bvec(&iter, ITER_DEST, rqstp->rq_bvec, v,
fs/nfsd/vfs.c
1196
unsigned long v, total;
fs/nfsd/vfs.c
1221
v = 0;
fs/nfsd/vfs.c
1223
while (total && v < rqstp->rq_maxpages &&
fs/nfsd/vfs.c
1226
bvec_set_page(&rqstp->rq_bvec[v], *rqstp->rq_next_page,
fs/nfsd/vfs.c
1231
++v;
fs/nfsd/vfs.c
1236
iov_iter_bvec(&iter, ITER_DEST, rqstp->rq_bvec, v, *count - total);
fs/nfsd/xdr4.h
100
#define nfsd4_encode_sequenceid4(x, v) nfsd4_encode_uint32_t(x, v)
fs/nfsd/xdr4.h
101
#define nfsd4_encode_slotid4(x, v) nfsd4_encode_uint32_t(x, v)
fs/nfsd/xdr4.h
123
#define nfsd4_encode_changeid4(x, v) nfsd4_encode_uint64_t(x, v)
fs/nfsd/xdr4.h
124
#define nfsd4_encode_nfs_cookie4(x, v) nfsd4_encode_uint64_t(x, v)
fs/nfsd/xdr4.h
125
#define nfsd4_encode_length4(x, v) nfsd4_encode_uint64_t(x, v)
fs/nfsd/xdr4.h
126
#define nfsd4_encode_offset4(x, v) nfsd4_encode_uint64_t(x, v)
fs/nfsd/xdr4.h
300
} v;
fs/nfsd/xdr4.h
306
#define lk_new_open_seqid v.new.open_seqid
fs/nfsd/xdr4.h
307
#define lk_new_open_stateid v.new.open_stateid
fs/nfsd/xdr4.h
308
#define lk_new_lock_seqid v.new.lock_seqid
fs/nfsd/xdr4.h
309
#define lk_new_clientid v.new.clientid
fs/nfsd/xdr4.h
310
#define lk_new_owner v.new.owner
fs/nfsd/xdr4.h
311
#define lk_old_lock_stateid v.old.lock_stateid
fs/nfsd/xdr4.h
312
#define lk_old_lock_seqid v.old.lock_seqid
fs/nfsd/xdr4.h
93
#define nfsd4_encode_aceflag4(x, v) nfsd4_encode_uint32_t(x, v)
fs/nfsd/xdr4.h
94
#define nfsd4_encode_acemask4(x, v) nfsd4_encode_uint32_t(x, v)
fs/nfsd/xdr4.h
95
#define nfsd4_encode_acetype4(x, v) nfsd4_encode_uint32_t(x, v)
fs/nfsd/xdr4.h
96
#define nfsd4_encode_count4(x, v) nfsd4_encode_uint32_t(x, v)
fs/nfsd/xdr4.h
97
#define nfsd4_encode_mode4(x, v) nfsd4_encode_uint32_t(x, v)
fs/nfsd/xdr4.h
98
#define nfsd4_encode_nfs_lease4(x, v) nfsd4_encode_uint32_t(x, v)
fs/nfsd/xdr4.h
99
#define nfsd4_encode_qop4(x, v) nfsd4_encode_uint32_t(x, v)
fs/nls/nls_base.c
194
unsigned long u, v;
fs/nls/nls_base.c
211
v = get_utf16(*pwcs, endian);
fs/nls/nls_base.c
212
if ((v & SURROGATE_MASK) != SURROGATE_PAIR ||
fs/nls/nls_base.c
213
!(v & SURROGATE_LOW)) {
fs/nls/nls_base.c
218
+ (v & SURROGATE_BITS);
fs/ntfs3/bitmap.c
142
static struct rb_node *rb_lookup(struct rb_root *root, size_t v)
fs/ntfs3/bitmap.c
151
if (v < k->key) {
fs/ntfs3/bitmap.c
153
} else if (v > k->key) {
fs/ntfs3/lib/decompress_common.h
155
u16 v;
fs/ntfs3/lib/decompress_common.h
159
v = get_unaligned_le16(is->next);
fs/ntfs3/lib/decompress_common.h
161
return v;
fs/ntfs3/lib/decompress_common.h
168
u32 v;
fs/ntfs3/lib/decompress_common.h
172
v = get_unaligned_le32(is->next);
fs/ntfs3/lib/decompress_common.h
174
return v;
fs/ntfs3/lib/decompress_common.h
305
size_t v = repeat_byte(*(dst - 1));
fs/ntfs3/lib/decompress_common.h
308
put_unaligned(v, (size_t *)dst);
fs/ntfs3/lib/decompress_common.h
41
size_t v;
fs/ntfs3/lib/decompress_common.h
43
v = b;
fs/ntfs3/lib/decompress_common.h
44
v |= v << 8;
fs/ntfs3/lib/decompress_common.h
45
v |= v << 16;
fs/ntfs3/lib/decompress_common.h
46
v |= v << ((WORDBYTES == 8) ? 32 : 0);
fs/ntfs3/lib/decompress_common.h
47
return v;
fs/ntfs3/ntfs.h
641
__le64 *v = Add2Ptr(e, le16_to_cpu(e->size) - sizeof(__le64));
fs/ntfs3/ntfs.h
643
*v = vcn;
fs/ntfs3/ntfs.h
648
__le64 *v = Add2Ptr(e, le16_to_cpu(e->size) - sizeof(__le64));
fs/ntfs3/ntfs.h
650
*v = cpu_to_le64(vcn);
fs/ntfs3/ntfs.h
660
__le64 *v = Add2Ptr(e, le16_to_cpu(e->size) - sizeof(__le64));
fs/ntfs3/ntfs.h
662
return le64_to_cpu(*v);
fs/ntfs3/run.c
695
static inline void run_pack_s64(u8 *run_buf, u8 size, s64 v)
fs/ntfs3/run.c
697
const u8 *p = (u8 *)&v;
fs/ntfs3/run.c
727
static inline s64 run_unpack_s64(const u8 *run_buf, u8 size, s64 v)
fs/ntfs3/run.c
729
u8 *p = (u8 *)&v;
fs/ntfs3/run.c
756
return v;
fs/ntfs3/run.c
790
static inline void run_pack_s64(u8 *run_buf, u8 size, s64 v)
fs/ntfs3/run.c
792
const u8 *p = (u8 *)&v;
fs/ntfs3/run.c
823
static inline s64 run_unpack_s64(const u8 *run_buf, u8 size, s64 v)
fs/ntfs3/run.c
825
u8 *p = (u8 *)&v;
fs/ntfs3/run.c
853
return v;
fs/ocfs2/cluster/netdebug.c
109
static int nst_seq_show(struct seq_file *seq, void *v)
fs/ocfs2/cluster/netdebug.c
153
static void nst_seq_stop(struct seq_file *seq, void *v)
fs/ocfs2/cluster/netdebug.c
246
static void *sc_seq_next(struct seq_file *seq, void *v, loff_t *pos)
fs/ocfs2/cluster/netdebug.c
347
static int sc_seq_show(struct seq_file *seq, void *v)
fs/ocfs2/cluster/netdebug.c
367
static void sc_seq_stop(struct seq_file *seq, void *v)
fs/ocfs2/cluster/netdebug.c
94
static void *nst_seq_next(struct seq_file *seq, void *v, loff_t *pos)
fs/ocfs2/dlm/dlmdebug.c
533
static void lockres_seq_stop(struct seq_file *m, void *v)
fs/ocfs2/dlm/dlmdebug.c
537
static void *lockres_seq_next(struct seq_file *m, void *v, loff_t *pos)
fs/ocfs2/dlm/dlmdebug.c
542
static int lockres_seq_show(struct seq_file *s, void *v)
fs/ocfs2/dlm/dlmdebug.c
544
struct debug_lockres *dl = (struct debug_lockres *)v;
fs/ocfs2/dlmglue.c
3102
static void ocfs2_dlm_seq_stop(struct seq_file *m, void *v)
fs/ocfs2/dlmglue.c
3106
static void *ocfs2_dlm_seq_next(struct seq_file *m, void *v, loff_t *pos)
fs/ocfs2/dlmglue.c
3109
struct ocfs2_lock_res *iter = v;
fs/ocfs2/dlmglue.c
3137
static int ocfs2_dlm_seq_show(struct seq_file *m, void *v)
fs/ocfs2/dlmglue.c
3141
struct ocfs2_lock_res *lockres = v;
fs/openpromfs/inode.c
127
static void *property_next(struct seq_file *f, void *v, loff_t *pos)
fs/openpromfs/inode.c
133
static void property_stop(struct seq_file *f, void *v)
fs/openpromfs/inode.c
67
static int property_show(struct seq_file *f, void *v)
fs/orangefs/orangefs-bufmap.c
70
int v;
fs/orangefs/orangefs-bufmap.c
73
v = ++m->c;
fs/orangefs/orangefs-bufmap.c
74
if (v > 0)
fs/orangefs/orangefs-bufmap.c
76
if (unlikely(v == -1)) /* finished dying */
fs/orangefs/orangefs-debugfs.c
313
static void *help_next(struct seq_file *m, void *v, loff_t *pos)
fs/orangefs/orangefs-debugfs.c
327
static int help_show(struct seq_file *m, void *v)
fs/orangefs/orangefs-debugfs.c
331
seq_puts(m, v);
fs/proc/array.c
769
static int children_seq_show(struct seq_file *seq, void *v)
fs/proc/array.c
773
seq_printf(seq, "%d ", pid_nr_ns(v, proc_pid_ns(inode->i_sb)));
fs/proc/array.c
782
static void *children_seq_next(struct seq_file *seq, void *v, loff_t *pos)
fs/proc/array.c
786
pid = get_children_pid(file_inode(seq->file), v, *pos + 1);
fs/proc/array.c
787
put_pid(v);
fs/proc/array.c
793
static void children_seq_stop(struct seq_file *seq, void *v)
fs/proc/array.c
795
put_pid(v);
fs/proc/base.c
1501
static int sched_show(struct seq_file *m, void *v)
fs/proc/base.c
1551
static int sched_autogroup_show(struct seq_file *m, void *v)
fs/proc/base.c
1622
static int timens_offsets_show(struct seq_file *m, void *v)
fs/proc/base.c
1750
static int comm_show(struct seq_file *m, void *v)
fs/proc/base.c
2523
static void *timers_next(struct seq_file *m, void *v, loff_t *pos)
fs/proc/base.c
2527
return seq_hlist_next_rcu(v, &tp->task->signal->posix_timers, pos);
fs/proc/base.c
2530
static void timers_stop(struct seq_file *m, void *v)
fs/proc/base.c
2541
static int show_timer(struct seq_file *m, void *v)
fs/proc/base.c
2549
struct k_itimer *timer = hlist_entry((struct hlist_node *)v, struct k_itimer, list);
fs/proc/base.c
2643
static int timerslack_ns_show(struct seq_file *m, void *v)
fs/proc/base.c
527
static int lstats_show_proc(struct seq_file *m, void *v)
fs/proc/base.c
800
static int proc_single_show(struct seq_file *m, void *v)
fs/proc/bootconfig.c
15
static int boot_config_proc_show(struct seq_file *m, void *v)
fs/proc/cmdline.c
8
static int cmdline_proc_show(struct seq_file *m, void *v)
fs/proc/consoles.c
15
static int show_console_dev(struct seq_file *m, void *v)
fs/proc/consoles.c
30
struct console *con = v;
fs/proc/consoles.c
90
static void *c_next(struct seq_file *m, void *v, loff_t *pos)
fs/proc/consoles.c
92
struct console *con = v;
fs/proc/consoles.c
98
static void c_stop(struct seq_file *m, void *v)
fs/proc/devices.c
11
int i = *(loff_t *) v;
fs/proc/devices.c
36
static void *devinfo_next(struct seq_file *f, void *v, loff_t *pos)
fs/proc/devices.c
44
static void devinfo_stop(struct seq_file *f, void *v)
fs/proc/devices.c
9
static int devinfo_show(struct seq_file *f, void *v)
fs/proc/fd.c
23
static int seq_show(struct seq_file *m, void *v)
fs/proc/inode.c
161
static inline const char *hidepid2str(enum proc_hidepid v)
fs/proc/inode.c
163
switch (v) {
fs/proc/inode.c
169
WARN_ONCE(1, "bad hide_pid value: %d\n", v);
fs/proc/interrupts.c
17
static void *int_seq_next(struct seq_file *f, void *v, loff_t *pos)
fs/proc/interrupts.c
25
static void int_seq_stop(struct seq_file *f, void *v)
fs/proc/kcore.c
45
#define kc_vaddr_to_offset(v) ((v) - PAGE_OFFSET)
fs/proc/loadavg.c
14
static int loadavg_proc_show(struct seq_file *m, void *v)
fs/proc/meminfo.c
34
static int meminfo_proc_show(struct seq_file *m, void *v)
fs/proc/nommu.c
100
return rb_next((struct rb_node *) v);
fs/proc/nommu.c
92
static void nommu_region_list_stop(struct seq_file *m, void *v)
fs/proc/nommu.c
97
static void *nommu_region_list_next(struct seq_file *m, void *v, loff_t *pos)
fs/proc/proc_tty.c
110
static void *t_next(struct seq_file *m, void *v, loff_t *pos)
fs/proc/proc_tty.c
112
return seq_list_next(v, &tty_drivers, pos);
fs/proc/proc_tty.c
115
static void t_stop(struct seq_file *m, void *v)
fs/proc/proc_tty.c
67
static int show_tty_driver(struct seq_file *m, void *v)
fs/proc/proc_tty.c
69
struct tty_driver *p = list_entry(v, struct tty_driver, tty_drivers);
fs/proc/softirqs.c
11
static int show_softirqs(struct seq_file *p, void *v)
fs/proc/stat.c
82
static int show_stat(struct seq_file *p, void *v)
fs/proc/task_mmu.c
1370
static int show_smap(struct seq_file *m, void *v)
fs/proc/task_mmu.c
1372
struct vm_area_struct *vma = v;
fs/proc/task_mmu.c
1397
static int show_smaps_rollup(struct seq_file *m, void *v)
fs/proc/task_mmu.c
319
static void *m_next(struct seq_file *m, void *v, loff_t *ppos)
fs/proc/task_mmu.c
328
static void m_stop(struct seq_file *m, void *v)
fs/proc/task_mmu.c
3297
static int show_numa_map(struct seq_file *m, void *v)
fs/proc/task_mmu.c
3301
struct vm_area_struct *vma = v;
fs/proc/task_mmu.c
499
static int show_map(struct seq_file *m, void *v)
fs/proc/task_mmu.c
501
show_map_vma(m, v);
fs/proc/task_nommu.c
226
static void m_stop(struct seq_file *m, void *v)
fs/proc/uptime.c
12
static int uptime_proc_show(struct seq_file *m, void *v)
fs/proc/version.c
10
static int version_proc_show(struct seq_file *m, void *v)
fs/pstore/inode.c
103
static int pstore_ftrace_seq_show(struct seq_file *s, void *v)
fs/pstore/inode.c
106
struct pstore_ftrace_seq_data *data = v;
fs/pstore/inode.c
85
static void pstore_ftrace_seq_stop(struct seq_file *s, void *v)
fs/pstore/inode.c
87
kfree(v);
fs/pstore/inode.c
90
static void *pstore_ftrace_seq_next(struct seq_file *s, void *v, loff_t *pos)
fs/pstore/inode.c
93
struct pstore_ftrace_seq_data *data = v;
fs/resctrl/ctrlmondata.c
417
struct seq_file *s, void *v)
fs/resctrl/ctrlmondata.c
503
struct seq_file *s, void *v)
fs/resctrl/ctrlmondata.c
769
int resctrl_io_alloc_show(struct kernfs_open_file *of, struct seq_file *seq, void *v)
fs/resctrl/ctrlmondata.c
916
int resctrl_io_alloc_cbm_show(struct kernfs_open_file *of, struct seq_file *seq, void *v)
fs/resctrl/internal.h
297
struct seq_file *sf, void *v);
fs/resctrl/internal.h
350
struct seq_file *s, void *v);
fs/resctrl/internal.h
356
struct seq_file *s, void *v);
fs/resctrl/internal.h
421
int resctrl_mbm_assign_mode_show(struct kernfs_open_file *of, struct seq_file *s, void *v);
fs/resctrl/internal.h
429
int resctrl_num_mbm_cntrs_show(struct kernfs_open_file *of, struct seq_file *s, void *v);
fs/resctrl/internal.h
432
void *v);
fs/resctrl/internal.h
438
int event_filter_show(struct kernfs_open_file *of, struct seq_file *seq, void *v);
fs/resctrl/internal.h
444
struct seq_file *s, void *v);
fs/resctrl/internal.h
449
int mbm_L3_assignments_show(struct kernfs_open_file *of, struct seq_file *s, void *v);
fs/resctrl/internal.h
453
int resctrl_io_alloc_show(struct kernfs_open_file *of, struct seq_file *seq, void *v);
fs/resctrl/internal.h
464
void *v);
fs/resctrl/monitor.c
1046
int event_filter_show(struct kernfs_open_file *of, struct seq_file *seq, void *v)
fs/resctrl/monitor.c
1080
void *v)
fs/resctrl/monitor.c
1438
struct seq_file *s, void *v)
fs/resctrl/monitor.c
1541
struct seq_file *s, void *v)
fs/resctrl/monitor.c
1565
struct seq_file *s, void *v)
fs/resctrl/monitor.c
1606
int mbm_L3_assignments_show(struct kernfs_open_file *of, struct seq_file *s, void *v)
fs/resctrl/rdtgroup.c
1004
struct seq_file *seq, void *v)
fs/resctrl/rdtgroup.c
1014
struct seq_file *seq, void *v)
fs/resctrl/rdtgroup.c
1024
struct seq_file *seq, void *v)
fs/resctrl/rdtgroup.c
1048
struct seq_file *seq, void *v)
fs/resctrl/rdtgroup.c
1147
struct seq_file *seq, void *v)
fs/resctrl/rdtgroup.c
1157
struct seq_file *seq, void *v)
fs/resctrl/rdtgroup.c
1167
struct seq_file *seq, void *v)
fs/resctrl/rdtgroup.c
1185
struct seq_file *seq, void *v)
fs/resctrl/rdtgroup.c
1195
struct seq_file *seq, void *v)
fs/resctrl/rdtgroup.c
1205
struct seq_file *seq, void *v)
fs/resctrl/rdtgroup.c
1213
struct seq_file *seq, void *v)
fs/resctrl/rdtgroup.c
1257
struct seq_file *s, void *v)
fs/resctrl/rdtgroup.c
1287
struct seq_file *seq, void *v)
fs/resctrl/rdtgroup.c
1563
struct seq_file *s, void *v)
fs/resctrl/rdtgroup.c
1672
struct seq_file *seq, void *v)
fs/resctrl/rdtgroup.c
1682
struct seq_file *seq, void *v)
fs/resctrl/rdtgroup.c
351
struct seq_file *s, void *v)
fs/resctrl/rdtgroup.c
836
struct seq_file *s, void *v)
fs/resctrl/rdtgroup.c
852
struct seq_file *s, void *v)
fs/resctrl/rdtgroup.c
868
struct seq_file *s, void *v)
fs/resctrl/rdtgroup.c
970
struct seq_file *seq, void *v)
fs/resctrl/rdtgroup.c
995
struct seq_file *seq, void *v)
fs/seq_file.c
1003
struct hlist_node *seq_hlist_next(void *v, struct hlist_head *head,
fs/seq_file.c
1006
struct hlist_node *node = v;
fs/seq_file.c
1009
if (v == SEQ_START_TOKEN)
fs/seq_file.c
1073
struct hlist_node *seq_hlist_next_rcu(void *v,
fs/seq_file.c
1077
struct hlist_node *node = v;
fs/seq_file.c
1080
if (v == SEQ_START_TOKEN)
fs/seq_file.c
1120
seq_hlist_next_percpu(void *v, struct hlist_head __percpu *head,
fs/seq_file.c
1123
struct hlist_node *node = v;
fs/seq_file.c
563
static void *single_next(struct seq_file *p, void *v, loff_t *pos)
fs/seq_file.c
569
static void single_stop(struct seq_file *p, void *v)
fs/seq_file.c
744
unsigned long long v, unsigned int width)
fs/seq_file.c
757
if (v == 0)
fs/seq_file.c
760
len = (sizeof(v) * 8 - __builtin_clzll(v) + 3) / 4;
fs/seq_file.c
771
m->buf[m->count + i] = hex_asc[0xf & v];
fs/seq_file.c
772
v = v >> 4;
fs/seq_file.c
918
struct list_head *seq_list_next(void *v, struct list_head *head, loff_t *ppos)
fs/seq_file.c
922
lh = ((struct list_head *)v)->next;
fs/seq_file.c
949
struct list_head *seq_list_next_rcu(void *v, struct list_head *head,
fs/seq_file.c
954
lh = list_next_rcu((struct list_head *)v);
fs/smb/client/cifs_debug.c
1025
static int cifsFYI_proc_show(struct seq_file *m, void *v)
fs/smb/client/cifs_debug.c
1064
static int cifs_linux_ext_proc_show(struct seq_file *m, void *v)
fs/smb/client/cifs_debug.c
1095
static int cifs_lookup_cache_proc_show(struct seq_file *m, void *v)
fs/smb/client/cifs_debug.c
1126
static int traceSMB_proc_show(struct seq_file *m, void *v)
fs/smb/client/cifs_debug.c
1157
static int cifs_security_flags_proc_show(struct seq_file *m, void *v)
fs/smb/client/cifs_debug.c
1261
static int cifs_mount_params_proc_show(struct seq_file *m, void *v)
fs/smb/client/cifs_debug.c
221
static int cifs_debug_files_proc_show(struct seq_file *m, void *v)
fs/smb/client/cifs_debug.c
299
static int cifs_debug_dirs_proc_show(struct seq_file *m, void *v)
fs/smb/client/cifs_debug.c
391
static int cifs_debug_data_proc_show(struct seq_file *m, void *v)
fs/smb/client/cifs_debug.c
800
static int cifs_stats_proc_show(struct seq_file *m, void *v)
fs/smb/client/cifs_debug.c
904
static int name##_proc_show(struct seq_file *m, void *v) \
fs/smb/client/compress/lz77.c
36
static __always_inline void lz77_write8(u8 *ptr, u8 v)
fs/smb/client/compress/lz77.c
38
put_unaligned(v, ptr);
fs/smb/client/compress/lz77.c
41
static __always_inline void lz77_write16(u16 *ptr, u16 v)
fs/smb/client/compress/lz77.c
43
put_unaligned_le16(v, ptr);
fs/smb/client/compress/lz77.c
46
static __always_inline void lz77_write32(u32 *ptr, u32 v)
fs/smb/client/compress/lz77.c
48
put_unaligned_le32(v, ptr);
fs/smb/client/dfs.h
17
#define DFS_INTERLINK(v) \
fs/smb/client/dfs.h
18
(((v) & DFSREF_REFERRAL_SERVER) && !((v) & DFSREF_STORAGE_SERVER))
fs/smb/client/dfs_cache.c
156
static int dfscache_proc_show(struct seq_file *m, void *v)
fs/smb/client/reparse.c
1153
void *v;
fs/smb/client/reparse.c
1163
v = (void *)((u8 *)ea->ea_data + ea->ea_name_length + 1);
fs/smb/client/reparse.c
1166
fattr->cf_uid = wsl_make_kuid(cifs_sb, v);
fs/smb/client/reparse.c
1168
fattr->cf_gid = wsl_make_kgid(cifs_sb, v);
fs/smb/client/reparse.c
1171
if (S_DT(fattr->cf_mode) != S_DT(le32_to_cpu(*(__le32 *)v)))
fs/smb/client/reparse.c
1173
fattr->cf_mode = (umode_t)le32_to_cpu(*(__le32 *)v);
fs/smb/client/reparse.c
1175
fattr->cf_rdev = reparse_mkdev(v);
fs/smb/client/reparse.h
26
u64 v = le64_to_cpu(*(__le64 *)ptr);
fs/smb/client/reparse.h
28
return MKDEV(v & 0xffffffff, v >> 32);
fs/smb/client/smb2pdu.c
3218
struct kvec *v = &iov[i];
fs/smb/client/smb2pdu.c
3219
size_t len = v->iov_len;
fs/smb/client/smb2pdu.c
3221
(struct create_context *)v->iov_base;
fs/smb/server/connection.c
29
static int proc_show_clients(struct seq_file *m, void *v)
fs/smb/server/mgmt/user_session.c
200
static int show_proc_sessions(struct seq_file *m, void *v)
fs/smb/server/mgmt/user_session.c
81
static int show_proc_session(struct seq_file *m, void *v)
fs/smb/server/misc.h
51
int (*show)(struct seq_file *m, void *v),
fs/smb/server/misc.h
52
void *v);
fs/smb/server/proc.c
23
int (*show)(struct seq_file *m, void *v),
fs/smb/server/proc.c
24
void *v)
fs/smb/server/proc.c
27
show, v);
fs/smb/server/proc.c
57
static int proc_show_ksmbd_stats(struct seq_file *m, void *v)
fs/smb/server/server.c
57
int ksmbd_set_netbios_name(char *v)
fs/smb/server/server.c
59
return ___server_conf_set(SERVER_CONF_NETBIOS_NAME, v);
fs/smb/server/server.c
62
int ksmbd_set_server_string(char *v)
fs/smb/server/server.c
64
return ___server_conf_set(SERVER_CONF_SERVER_STRING, v);
fs/smb/server/server.c
67
int ksmbd_set_work_group(char *v)
fs/smb/server/server.c
69
return ___server_conf_set(SERVER_CONF_WORK_GROUP, v);
fs/smb/server/server.h
55
int ksmbd_set_netbios_name(char *v);
fs/smb/server/server.h
56
int ksmbd_set_server_string(char *v);
fs/smb/server/server.h
57
int ksmbd_set_work_group(char *v);
fs/smb/server/transport_rdma.c
1669
struct kvec *v = &vecs[nvecs];
fs/smb/server/transport_rdma.c
1672
v->iov_base = ((u8 *)iov[iov_idx].iov_base) + iov_ofs;
fs/smb/server/transport_rdma.c
1673
v->iov_len = min_t(size_t,
fs/smb/server/transport_rdma.c
1676
page_count = get_buf_page_count(v->iov_base, v->iov_len);
fs/smb/server/transport_rdma.c
1700
size_t fpofs = offset_in_page(v->iov_base);
fs/smb/server/transport_rdma.c
1701
size_t fplen = min_t(size_t, PAGE_SIZE - fpofs, v->iov_len);
fs/smb/server/transport_rdma.c
1702
size_t elen = min_t(size_t, v->iov_len - fplen, epages*PAGE_SIZE);
fs/smb/server/transport_rdma.c
1704
v->iov_len = fplen + elen;
fs/smb/server/transport_rdma.c
1705
page_count = get_buf_page_count(v->iov_base, v->iov_len);
fs/smb/server/transport_rdma.c
1717
possible_bytes -= v->iov_len;
fs/smb/server/transport_rdma.c
1718
bytes += v->iov_len;
fs/smb/server/transport_rdma.c
1720
iov_ofs += v->iov_len;
fs/smb/server/vfs_cache.c
142
long v = atomic_long_dec_return(&fd_limit);
fs/smb/server/vfs_cache.c
144
if (v >= 0)
fs/smb/server/vfs_cache.c
69
static int proc_show_files(struct seq_file *m, void *v)
fs/sysfs/file.c
46
static int sysfs_kf_seq_show(struct seq_file *sf, void *v)
fs/ufs/inode.c
105
struct buffer_head *bh, __fs64 *v,
fs/ufs/inode.c
113
to->key64 = *(__fs64 *)(to->p = v);
fs/ufs/inode.c
89
struct buffer_head *bh, __fs32 *v,
fs/ufs/inode.c
97
to->key32 = *(__fs32 *)(to->p = v);
fs/xfs/libxfs/xfs_bit.h
30
static inline int xfs_highbit32(uint32_t v)
fs/xfs/libxfs/xfs_bit.h
32
return fls(v) - 1;
fs/xfs/libxfs/xfs_bit.h
36
static inline int xfs_highbit64(uint64_t v)
fs/xfs/libxfs/xfs_bit.h
38
return fls64(v) - 1;
fs/xfs/libxfs/xfs_bit.h
42
static inline int xfs_lowbit32(uint32_t v)
fs/xfs/libxfs/xfs_bit.h
44
return ffs(v) - 1;
fs/xfs/libxfs/xfs_bit.h
48
static inline int xfs_lowbit64(uint64_t v)
fs/xfs/libxfs/xfs_bit.h
50
uint32_t w = (uint32_t)v;
fs/xfs/libxfs/xfs_bit.h
56
w = (uint32_t)(v >> 32);
fs/xfs/libxfs/xfs_format.h
508
#define XFS_AGF_GOOD_VERSION(v) ((v) == XFS_AGF_VERSION)
fs/xfs/libxfs/xfs_format.h
509
#define XFS_AGI_GOOD_VERSION(v) ((v) == XFS_AGI_VERSION)
fs/xfs/libxfs/xfs_trans_space.h
94
#define XFS_ATTRSET_SPACE_RES(mp, v) \
fs/xfs/libxfs/xfs_trans_space.h
95
(XFS_DAENTER_SPACE_RES(mp, XFS_ATTR_FORK) + XFS_B_TO_FSB(mp, v))
fs/xfs/libxfs/xfs_trans_space.h
96
#define XFS_DIOSTRAT_SPACE_RES(mp, v) \
fs/xfs/libxfs/xfs_trans_space.h
97
(XFS_EXTENTADD_SPACE_RES(mp, XFS_DATA_FORK) + (v))
fs/xfs/scrub/rtsummary.c
150
union xfs_suminfo_raw *v)
fs/xfs/scrub/rtsummary.c
153
be32_add_cpu(&v->rtg, 1);
fs/xfs/scrub/rtsummary.c
154
return be32_to_cpu(v->rtg);
fs/xfs/scrub/rtsummary.c
157
v->old += 1;
fs/xfs/scrub/rtsummary.c
158
return v->old;
fs/xfs/scrub/rtsummary.c
176
union xfs_suminfo_raw v;
fs/xfs/scrub/rtsummary.c
197
error = xfsum_load(sc, offs, &v);
fs/xfs/scrub/rtsummary.c
201
value = xchk_rtsum_inc(sc->mp, &v);
fs/xfs/scrub/rtsummary.c
205
return xfsum_store(sc, offs, v);
fs/xfs/scrub/scrub.c
831
const struct xfs_scrub_vec *v;
fs/xfs/scrub/scrub.c
836
for (v = vectors; v < stop_vec; v++) {
fs/xfs/scrub/scrub.c
837
if (v->sv_type == XFS_SCRUB_TYPE_BARRIER)
fs/xfs/scrub/scrub.c
844
switch (v->sv_ret) {
fs/xfs/scrub/scrub.c
858
if (v->sv_flags & failmask)
fs/xfs/scrub/scrub.c
906
struct xfs_scrub_vec *v;
fs/xfs/scrub/scrub.c
935
for (i = 0, v = vectors; i < head.svh_nr; i++, v++) {
fs/xfs/scrub/scrub.c
936
if (v->sv_reserved) {
fs/xfs/scrub/scrub.c
941
if (v->sv_type == XFS_SCRUB_TYPE_BARRIER &&
fs/xfs/scrub/scrub.c
942
(v->sv_flags & ~XFS_SCRUB_FLAGS_OUT)) {
fs/xfs/scrub/scrub.c
947
trace_xchk_scrubv_item(mp, &head, i, v);
fs/xfs/scrub/scrub.c
962
for (i = 0, v = vectors; i < head.svh_nr; i++, v++) {
fs/xfs/scrub/scrub.c
964
.sm_type = v->sv_type,
fs/xfs/scrub/scrub.c
965
.sm_flags = v->sv_flags,
fs/xfs/scrub/scrub.c
971
if (v->sv_type == XFS_SCRUB_TYPE_BARRIER) {
fs/xfs/scrub/scrub.c
972
v->sv_ret = xfs_scrubv_check_barrier(mp, vectors, v);
fs/xfs/scrub/scrub.c
973
if (v->sv_ret) {
fs/xfs/scrub/scrub.c
974
trace_xchk_scrubv_barrier_fail(mp, &head, i, v);
fs/xfs/scrub/scrub.c
981
v->sv_ret = xfs_scrub_metadata(file, &sm);
fs/xfs/scrub/scrub.c
982
v->sv_flags = sm.sm_flags;
fs/xfs/scrub/scrub.c
984
trace_xchk_scrubv_outcome(mp, &head, i, v);
fs/xfs/scrub/trace.h
266
unsigned int vec_nr, struct xfs_scrub_vec *v),
fs/xfs/scrub/trace.h
267
TP_ARGS(mp, vhead, vec_nr, v),
fs/xfs/scrub/trace.h
278
__entry->vec_type = v->sv_type;
fs/xfs/scrub/trace.h
279
__entry->vec_flags = v->sv_flags;
fs/xfs/scrub/trace.h
280
__entry->vec_ret = v->sv_ret;
fs/xfs/scrub/trace.h
292
unsigned int vec_nr, struct xfs_scrub_vec *v), \
fs/xfs/scrub/trace.h
293
TP_ARGS(mp, vhead, vec_nr, v))
fs/xfs/xfs_stats.c
128
static int xqm_proc_show(struct seq_file *m, void *v)
fs/xfs/xfs_stats.c
139
static int xqmstat_proc_show(struct seq_file *m, void *v)
fs/xfs/xfs_stats.h
175
#define XFS_STATS_INC(mp, v) \
fs/xfs/xfs_stats.h
177
per_cpu_ptr(xfsstats.xs_stats, current_cpu())->s.v++; \
fs/xfs/xfs_stats.h
178
per_cpu_ptr(mp->m_stats.xs_stats, current_cpu())->s.v++; \
fs/xfs/xfs_stats.h
181
#define XFS_STATS_DEC(mp, v) \
fs/xfs/xfs_stats.h
183
per_cpu_ptr(xfsstats.xs_stats, current_cpu())->s.v--; \
fs/xfs/xfs_stats.h
184
per_cpu_ptr(mp->m_stats.xs_stats, current_cpu())->s.v--; \
fs/xfs/xfs_stats.h
187
#define XFS_STATS_ADD(mp, v, inc) \
fs/xfs/xfs_stats.h
189
per_cpu_ptr(xfsstats.xs_stats, current_cpu())->s.v += (inc); \
fs/xfs/xfs_stats.h
190
per_cpu_ptr(mp->m_stats.xs_stats, current_cpu())->s.v += (inc); \
include/asm-generic/archrandom.h
10
static inline size_t __must_check arch_get_random_seed_longs(unsigned long *v, size_t max_longs)
include/asm-generic/archrandom.h
5
static inline size_t __must_check arch_get_random_longs(unsigned long *v, size_t max_longs)
include/asm-generic/atomic.h
130
#define arch_atomic_read(v) READ_ONCE((v)->counter)
include/asm-generic/atomic.h
131
#define arch_atomic_set(v, i) WRITE_ONCE(((v)->counter), (i))
include/asm-generic/atomic.h
20
static inline void generic_atomic_##op(int i, atomic_t *v) \
include/asm-generic/atomic.h
24
c = v->counter; \
include/asm-generic/atomic.h
25
while ((old = arch_cmpxchg(&v->counter, c, c c_op i)) != c) \
include/asm-generic/atomic.h
30
static inline int generic_atomic_##op##_return(int i, atomic_t *v) \
include/asm-generic/atomic.h
34
c = v->counter; \
include/asm-generic/atomic.h
35
while ((old = arch_cmpxchg(&v->counter, c, c c_op i)) != c) \
include/asm-generic/atomic.h
42
static inline int generic_atomic_fetch_##op(int i, atomic_t *v) \
include/asm-generic/atomic.h
46
c = v->counter; \
include/asm-generic/atomic.h
47
while ((old = arch_cmpxchg(&v->counter, c, c c_op i)) != c) \
include/asm-generic/atomic.h
58
static inline void generic_atomic_##op(int i, atomic_t *v) \
include/asm-generic/atomic.h
63
v->counter = v->counter c_op i; \
include/asm-generic/atomic.h
68
static inline int generic_atomic_##op##_return(int i, atomic_t *v) \
include/asm-generic/atomic.h
74
ret = (v->counter = v->counter c_op i); \
include/asm-generic/atomic.h
81
static inline int generic_atomic_fetch_##op(int i, atomic_t *v) \
include/asm-generic/atomic.h
87
ret = v->counter; \
include/asm-generic/atomic.h
88
v->counter = v->counter c_op i; \
include/asm-generic/atomic64.h
18
extern s64 generic_atomic64_read(const atomic64_t *v);
include/asm-generic/atomic64.h
19
extern void generic_atomic64_set(atomic64_t *v, s64 i);
include/asm-generic/atomic64.h
22
extern void generic_atomic64_##op(s64 a, atomic64_t *v);
include/asm-generic/atomic64.h
25
extern s64 generic_atomic64_##op##_return(s64 a, atomic64_t *v);
include/asm-generic/atomic64.h
28
extern s64 generic_atomic64_fetch_##op(s64 a, atomic64_t *v);
include/asm-generic/atomic64.h
47
extern s64 generic_atomic64_dec_if_positive(atomic64_t *v);
include/asm-generic/atomic64.h
48
extern s64 generic_atomic64_cmpxchg(atomic64_t *v, s64 o, s64 n);
include/asm-generic/atomic64.h
49
extern s64 generic_atomic64_xchg(atomic64_t *v, s64 new);
include/asm-generic/atomic64.h
50
extern s64 generic_atomic64_fetch_add_unless(atomic64_t *v, s64 a, s64 u);
include/asm-generic/barrier.h
139
#define __smp_store_release(p, v) \
include/asm-generic/barrier.h
143
WRITE_ONCE(*p, v); \
include/asm-generic/barrier.h
172
#define smp_store_release(p, v) do { kcsan_release(); __smp_store_release(p, v); } while (0)
include/asm-generic/barrier.h
194
#define smp_store_release(p, v) \
include/asm-generic/barrier.h
197
WRITE_ONCE(*p, v); \
include/asm-generic/barrier.h
219
#define virt_store_release(p, v) do { kcsan_release(); __smp_store_release(p, v); } while (0)
include/asm-generic/io.h
30
#define __io_ar(v) rmb()
include/asm-generic/io.h
32
#define __io_ar(v) barrier()
include/asm-generic/io.h
63
#define __io_par(v) __io_ar(v)
include/crypto/aria.h
309
static inline u32 rotl32(u32 v, u32 r)
include/crypto/aria.h
311
return ((v << r) | (v >> (32 - r)));
include/crypto/aria.h
314
static inline u32 rotr32(u32 v, u32 r)
include/crypto/aria.h
316
return ((v >> r) | (v << (32 - r)));
include/crypto/aria.h
319
static inline u32 bswap32(u32 v)
include/crypto/aria.h
321
return ((v << 24) ^
include/crypto/aria.h
322
(v >> 24) ^
include/crypto/aria.h
323
((v & 0x0000ff00) << 8) ^
include/crypto/aria.h
324
((v & 0x00ff0000) >> 8));
include/cxl/einj.h
20
int einj_cxl_available_error_type_show(struct seq_file *m, void *v);
include/cxl/einj.h
26
void *v)
include/drm/display/drm_hdcp.h
210
u8 v[HDCP_2_2_V_PRIME_HALF_LEN];
include/drm/intel/i915_hdcp_interface.h
526
u8 v[HDCP_2_2_V_PRIME_HALF_LEN];
include/kvm/arm_arch_timer.h
121
#define vcpu_timer(v) (&(v)->arch.timer_cpu)
include/kvm/arm_arch_timer.h
122
#define vcpu_get_timer(v,t) (&vcpu_timer(v)->timers[(t)])
include/kvm/arm_arch_timer.h
123
#define vcpu_vtimer(v) (&(v)->arch.timer_cpu.timers[TIMER_VTIMER])
include/kvm/arm_arch_timer.h
124
#define vcpu_ptimer(v) (&(v)->arch.timer_cpu.timers[TIMER_PTIMER])
include/kvm/arm_arch_timer.h
125
#define vcpu_hvtimer(v) (&(v)->arch.timer_cpu.timers[TIMER_HVTIMER])
include/kvm/arm_arch_timer.h
126
#define vcpu_hptimer(v) (&(v)->arch.timer_cpu.timers[TIMER_HPTIMER])
include/kvm/arm_pmu.h
104
#define kvm_arm_pmu_irq_initialized(v) (false)
include/kvm/arm_pmu.h
41
#define kvm_arm_pmu_irq_initialized(v) ((v)->arch.pmu.irq_num >= VGIC_NR_SGIS)
include/kvm/iodev.h
44
int l, void *v)
include/kvm/iodev.h
46
return dev->ops->read ? dev->ops->read(vcpu, dev, addr, l, v)
include/kvm/iodev.h
52
int l, const void *v)
include/kvm/iodev.h
54
return dev->ops->write ? dev->ops->write(vcpu, dev, addr, l, v)
include/linux/alloc_tag.h
139
struct alloc_tag_counters v = { 0, 0 };
include/linux/alloc_tag.h
145
v.bytes += counter->bytes;
include/linux/alloc_tag.h
146
v.calls += counter->calls;
include/linux/alloc_tag.h
149
return v;
include/linux/atomic.h
28
#define atomic_cond_read_acquire(v, c) smp_cond_load_acquire(&(v)->counter, (c))
include/linux/atomic.h
29
#define atomic_cond_read_relaxed(v, c) smp_cond_load_relaxed(&(v)->counter, (c))
include/linux/atomic.h
31
#define atomic64_cond_read_acquire(v, c) smp_cond_load_acquire(&(v)->counter, (c))
include/linux/atomic.h
32
#define atomic64_cond_read_relaxed(v, c) smp_cond_load_relaxed(&(v)->counter, (c))
include/linux/atomic/atomic-arch-fallback.h
1009
raw_atomic_inc_return(atomic_t *v)
include/linux/atomic/atomic-arch-fallback.h
1012
return arch_atomic_inc_return(v);
include/linux/atomic/atomic-arch-fallback.h
1016
ret = arch_atomic_inc_return_relaxed(v);
include/linux/atomic/atomic-arch-fallback.h
1020
return raw_atomic_add_return(1, v);
include/linux/atomic/atomic-arch-fallback.h
1035
raw_atomic_inc_return_acquire(atomic_t *v)
include/linux/atomic/atomic-arch-fallback.h
1038
return arch_atomic_inc_return_acquire(v);
include/linux/atomic/atomic-arch-fallback.h
1040
int ret = arch_atomic_inc_return_relaxed(v);
include/linux/atomic/atomic-arch-fallback.h
1044
return arch_atomic_inc_return(v);
include/linux/atomic/atomic-arch-fallback.h
1046
return raw_atomic_add_return_acquire(1, v);
include/linux/atomic/atomic-arch-fallback.h
1061
raw_atomic_inc_return_release(atomic_t *v)
include/linux/atomic/atomic-arch-fallback.h
1064
return arch_atomic_inc_return_release(v);
include/linux/atomic/atomic-arch-fallback.h
1067
return arch_atomic_inc_return_relaxed(v);
include/linux/atomic/atomic-arch-fallback.h
1069
return arch_atomic_inc_return(v);
include/linux/atomic/atomic-arch-fallback.h
1071
return raw_atomic_add_return_release(1, v);
include/linux/atomic/atomic-arch-fallback.h
1086
raw_atomic_inc_return_relaxed(atomic_t *v)
include/linux/atomic/atomic-arch-fallback.h
1089
return arch_atomic_inc_return_relaxed(v);
include/linux/atomic/atomic-arch-fallback.h
1091
return arch_atomic_inc_return(v);
include/linux/atomic/atomic-arch-fallback.h
1093
return raw_atomic_add_return_relaxed(1, v);
include/linux/atomic/atomic-arch-fallback.h
1108
raw_atomic_fetch_inc(atomic_t *v)
include/linux/atomic/atomic-arch-fallback.h
1111
return arch_atomic_fetch_inc(v);
include/linux/atomic/atomic-arch-fallback.h
1115
ret = arch_atomic_fetch_inc_relaxed(v);
include/linux/atomic/atomic-arch-fallback.h
1119
return raw_atomic_fetch_add(1, v);
include/linux/atomic/atomic-arch-fallback.h
1134
raw_atomic_fetch_inc_acquire(atomic_t *v)
include/linux/atomic/atomic-arch-fallback.h
1137
return arch_atomic_fetch_inc_acquire(v);
include/linux/atomic/atomic-arch-fallback.h
1139
int ret = arch_atomic_fetch_inc_relaxed(v);
include/linux/atomic/atomic-arch-fallback.h
1143
return arch_atomic_fetch_inc(v);
include/linux/atomic/atomic-arch-fallback.h
1145
return raw_atomic_fetch_add_acquire(1, v);
include/linux/atomic/atomic-arch-fallback.h
1160
raw_atomic_fetch_inc_release(atomic_t *v)
include/linux/atomic/atomic-arch-fallback.h
1163
return arch_atomic_fetch_inc_release(v);
include/linux/atomic/atomic-arch-fallback.h
1166
return arch_atomic_fetch_inc_relaxed(v);
include/linux/atomic/atomic-arch-fallback.h
1168
return arch_atomic_fetch_inc(v);
include/linux/atomic/atomic-arch-fallback.h
1170
return raw_atomic_fetch_add_release(1, v);
include/linux/atomic/atomic-arch-fallback.h
1185
raw_atomic_fetch_inc_relaxed(atomic_t *v)
include/linux/atomic/atomic-arch-fallback.h
1188
return arch_atomic_fetch_inc_relaxed(v);
include/linux/atomic/atomic-arch-fallback.h
1190
return arch_atomic_fetch_inc(v);
include/linux/atomic/atomic-arch-fallback.h
1192
return raw_atomic_fetch_add_relaxed(1, v);
include/linux/atomic/atomic-arch-fallback.h
1207
raw_atomic_dec(atomic_t *v)
include/linux/atomic/atomic-arch-fallback.h
1210
arch_atomic_dec(v);
include/linux/atomic/atomic-arch-fallback.h
1212
raw_atomic_sub(1, v);
include/linux/atomic/atomic-arch-fallback.h
1227
raw_atomic_dec_return(atomic_t *v)
include/linux/atomic/atomic-arch-fallback.h
1230
return arch_atomic_dec_return(v);
include/linux/atomic/atomic-arch-fallback.h
1234
ret = arch_atomic_dec_return_relaxed(v);
include/linux/atomic/atomic-arch-fallback.h
1238
return raw_atomic_sub_return(1, v);
include/linux/atomic/atomic-arch-fallback.h
1253
raw_atomic_dec_return_acquire(atomic_t *v)
include/linux/atomic/atomic-arch-fallback.h
1256
return arch_atomic_dec_return_acquire(v);
include/linux/atomic/atomic-arch-fallback.h
1258
int ret = arch_atomic_dec_return_relaxed(v);
include/linux/atomic/atomic-arch-fallback.h
1262
return arch_atomic_dec_return(v);
include/linux/atomic/atomic-arch-fallback.h
1264
return raw_atomic_sub_return_acquire(1, v);
include/linux/atomic/atomic-arch-fallback.h
1279
raw_atomic_dec_return_release(atomic_t *v)
include/linux/atomic/atomic-arch-fallback.h
1282
return arch_atomic_dec_return_release(v);
include/linux/atomic/atomic-arch-fallback.h
1285
return arch_atomic_dec_return_relaxed(v);
include/linux/atomic/atomic-arch-fallback.h
1287
return arch_atomic_dec_return(v);
include/linux/atomic/atomic-arch-fallback.h
1289
return raw_atomic_sub_return_release(1, v);
include/linux/atomic/atomic-arch-fallback.h
1304
raw_atomic_dec_return_relaxed(atomic_t *v)
include/linux/atomic/atomic-arch-fallback.h
1307
return arch_atomic_dec_return_relaxed(v);
include/linux/atomic/atomic-arch-fallback.h
1309
return arch_atomic_dec_return(v);
include/linux/atomic/atomic-arch-fallback.h
1311
return raw_atomic_sub_return_relaxed(1, v);
include/linux/atomic/atomic-arch-fallback.h
1326
raw_atomic_fetch_dec(atomic_t *v)
include/linux/atomic/atomic-arch-fallback.h
1329
return arch_atomic_fetch_dec(v);
include/linux/atomic/atomic-arch-fallback.h
1333
ret = arch_atomic_fetch_dec_relaxed(v);
include/linux/atomic/atomic-arch-fallback.h
1337
return raw_atomic_fetch_sub(1, v);
include/linux/atomic/atomic-arch-fallback.h
1352
raw_atomic_fetch_dec_acquire(atomic_t *v)
include/linux/atomic/atomic-arch-fallback.h
1355
return arch_atomic_fetch_dec_acquire(v);
include/linux/atomic/atomic-arch-fallback.h
1357
int ret = arch_atomic_fetch_dec_relaxed(v);
include/linux/atomic/atomic-arch-fallback.h
1361
return arch_atomic_fetch_dec(v);
include/linux/atomic/atomic-arch-fallback.h
1363
return raw_atomic_fetch_sub_acquire(1, v);
include/linux/atomic/atomic-arch-fallback.h
1378
raw_atomic_fetch_dec_release(atomic_t *v)
include/linux/atomic/atomic-arch-fallback.h
1381
return arch_atomic_fetch_dec_release(v);
include/linux/atomic/atomic-arch-fallback.h
1384
return arch_atomic_fetch_dec_relaxed(v);
include/linux/atomic/atomic-arch-fallback.h
1386
return arch_atomic_fetch_dec(v);
include/linux/atomic/atomic-arch-fallback.h
1388
return raw_atomic_fetch_sub_release(1, v);
include/linux/atomic/atomic-arch-fallback.h
1403
raw_atomic_fetch_dec_relaxed(atomic_t *v)
include/linux/atomic/atomic-arch-fallback.h
1406
return arch_atomic_fetch_dec_relaxed(v);
include/linux/atomic/atomic-arch-fallback.h
1408
return arch_atomic_fetch_dec(v);
include/linux/atomic/atomic-arch-fallback.h
1410
return raw_atomic_fetch_sub_relaxed(1, v);
include/linux/atomic/atomic-arch-fallback.h
1426
raw_atomic_and(int i, atomic_t *v)
include/linux/atomic/atomic-arch-fallback.h
1428
arch_atomic_and(i, v);
include/linux/atomic/atomic-arch-fallback.h
1443
raw_atomic_fetch_and(int i, atomic_t *v)
include/linux/atomic/atomic-arch-fallback.h
1446
return arch_atomic_fetch_and(i, v);
include/linux/atomic/atomic-arch-fallback.h
1450
ret = arch_atomic_fetch_and_relaxed(i, v);
include/linux/atomic/atomic-arch-fallback.h
1470
raw_atomic_fetch_and_acquire(int i, atomic_t *v)
include/linux/atomic/atomic-arch-fallback.h
1473
return arch_atomic_fetch_and_acquire(i, v);
include/linux/atomic/atomic-arch-fallback.h
1475
int ret = arch_atomic_fetch_and_relaxed(i, v);
include/linux/atomic/atomic-arch-fallback.h
1479
return arch_atomic_fetch_and(i, v);
include/linux/atomic/atomic-arch-fallback.h
1497
raw_atomic_fetch_and_release(int i, atomic_t *v)
include/linux/atomic/atomic-arch-fallback.h
1500
return arch_atomic_fetch_and_release(i, v);
include/linux/atomic/atomic-arch-fallback.h
1503
return arch_atomic_fetch_and_relaxed(i, v);
include/linux/atomic/atomic-arch-fallback.h
1505
return arch_atomic_fetch_and(i, v);
include/linux/atomic/atomic-arch-fallback.h
1523
raw_atomic_fetch_and_relaxed(int i, atomic_t *v)
include/linux/atomic/atomic-arch-fallback.h
1526
return arch_atomic_fetch_and_relaxed(i, v);
include/linux/atomic/atomic-arch-fallback.h
1528
return arch_atomic_fetch_and(i, v);
include/linux/atomic/atomic-arch-fallback.h
1546
raw_atomic_andnot(int i, atomic_t *v)
include/linux/atomic/atomic-arch-fallback.h
1549
arch_atomic_andnot(i, v);
include/linux/atomic/atomic-arch-fallback.h
1551
raw_atomic_and(~i, v);
include/linux/atomic/atomic-arch-fallback.h
1567
raw_atomic_fetch_andnot(int i, atomic_t *v)
include/linux/atomic/atomic-arch-fallback.h
1570
return arch_atomic_fetch_andnot(i, v);
include/linux/atomic/atomic-arch-fallback.h
1574
ret = arch_atomic_fetch_andnot_relaxed(i, v);
include/linux/atomic/atomic-arch-fallback.h
1578
return raw_atomic_fetch_and(~i, v);
include/linux/atomic/atomic-arch-fallback.h
1594
raw_atomic_fetch_andnot_acquire(int i, atomic_t *v)
include/linux/atomic/atomic-arch-fallback.h
1597
return arch_atomic_fetch_andnot_acquire(i, v);
include/linux/atomic/atomic-arch-fallback.h
1599
int ret = arch_atomic_fetch_andnot_relaxed(i, v);
include/linux/atomic/atomic-arch-fallback.h
1603
return arch_atomic_fetch_andnot(i, v);
include/linux/atomic/atomic-arch-fallback.h
1605
return raw_atomic_fetch_and_acquire(~i, v);
include/linux/atomic/atomic-arch-fallback.h
1621
raw_atomic_fetch_andnot_release(int i, atomic_t *v)
include/linux/atomic/atomic-arch-fallback.h
1624
return arch_atomic_fetch_andnot_release(i, v);
include/linux/atomic/atomic-arch-fallback.h
1627
return arch_atomic_fetch_andnot_relaxed(i, v);
include/linux/atomic/atomic-arch-fallback.h
1629
return arch_atomic_fetch_andnot(i, v);
include/linux/atomic/atomic-arch-fallback.h
1631
return raw_atomic_fetch_and_release(~i, v);
include/linux/atomic/atomic-arch-fallback.h
1647
raw_atomic_fetch_andnot_relaxed(int i, atomic_t *v)
include/linux/atomic/atomic-arch-fallback.h
1650
return arch_atomic_fetch_andnot_relaxed(i, v);
include/linux/atomic/atomic-arch-fallback.h
1652
return arch_atomic_fetch_andnot(i, v);
include/linux/atomic/atomic-arch-fallback.h
1654
return raw_atomic_fetch_and_relaxed(~i, v);
include/linux/atomic/atomic-arch-fallback.h
1670
raw_atomic_or(int i, atomic_t *v)
include/linux/atomic/atomic-arch-fallback.h
1672
arch_atomic_or(i, v);
include/linux/atomic/atomic-arch-fallback.h
1687
raw_atomic_fetch_or(int i, atomic_t *v)
include/linux/atomic/atomic-arch-fallback.h
1690
return arch_atomic_fetch_or(i, v);
include/linux/atomic/atomic-arch-fallback.h
1694
ret = arch_atomic_fetch_or_relaxed(i, v);
include/linux/atomic/atomic-arch-fallback.h
1714
raw_atomic_fetch_or_acquire(int i, atomic_t *v)
include/linux/atomic/atomic-arch-fallback.h
1717
return arch_atomic_fetch_or_acquire(i, v);
include/linux/atomic/atomic-arch-fallback.h
1719
int ret = arch_atomic_fetch_or_relaxed(i, v);
include/linux/atomic/atomic-arch-fallback.h
1723
return arch_atomic_fetch_or(i, v);
include/linux/atomic/atomic-arch-fallback.h
1741
raw_atomic_fetch_or_release(int i, atomic_t *v)
include/linux/atomic/atomic-arch-fallback.h
1744
return arch_atomic_fetch_or_release(i, v);
include/linux/atomic/atomic-arch-fallback.h
1747
return arch_atomic_fetch_or_relaxed(i, v);
include/linux/atomic/atomic-arch-fallback.h
1749
return arch_atomic_fetch_or(i, v);
include/linux/atomic/atomic-arch-fallback.h
1767
raw_atomic_fetch_or_relaxed(int i, atomic_t *v)
include/linux/atomic/atomic-arch-fallback.h
1770
return arch_atomic_fetch_or_relaxed(i, v);
include/linux/atomic/atomic-arch-fallback.h
1772
return arch_atomic_fetch_or(i, v);
include/linux/atomic/atomic-arch-fallback.h
1790
raw_atomic_xor(int i, atomic_t *v)
include/linux/atomic/atomic-arch-fallback.h
1792
arch_atomic_xor(i, v);
include/linux/atomic/atomic-arch-fallback.h
1807
raw_atomic_fetch_xor(int i, atomic_t *v)
include/linux/atomic/atomic-arch-fallback.h
1810
return arch_atomic_fetch_xor(i, v);
include/linux/atomic/atomic-arch-fallback.h
1814
ret = arch_atomic_fetch_xor_relaxed(i, v);
include/linux/atomic/atomic-arch-fallback.h
1834
raw_atomic_fetch_xor_acquire(int i, atomic_t *v)
include/linux/atomic/atomic-arch-fallback.h
1837
return arch_atomic_fetch_xor_acquire(i, v);
include/linux/atomic/atomic-arch-fallback.h
1839
int ret = arch_atomic_fetch_xor_relaxed(i, v);
include/linux/atomic/atomic-arch-fallback.h
1843
return arch_atomic_fetch_xor(i, v);
include/linux/atomic/atomic-arch-fallback.h
1861
raw_atomic_fetch_xor_release(int i, atomic_t *v)
include/linux/atomic/atomic-arch-fallback.h
1864
return arch_atomic_fetch_xor_release(i, v);
include/linux/atomic/atomic-arch-fallback.h
1867
return arch_atomic_fetch_xor_relaxed(i, v);
include/linux/atomic/atomic-arch-fallback.h
1869
return arch_atomic_fetch_xor(i, v);
include/linux/atomic/atomic-arch-fallback.h
1887
raw_atomic_fetch_xor_relaxed(int i, atomic_t *v)
include/linux/atomic/atomic-arch-fallback.h
1890
return arch_atomic_fetch_xor_relaxed(i, v);
include/linux/atomic/atomic-arch-fallback.h
1892
return arch_atomic_fetch_xor(i, v);
include/linux/atomic/atomic-arch-fallback.h
1910
raw_atomic_xchg(atomic_t *v, int new)
include/linux/atomic/atomic-arch-fallback.h
1913
return arch_atomic_xchg(v, new);
include/linux/atomic/atomic-arch-fallback.h
1917
ret = arch_atomic_xchg_relaxed(v, new);
include/linux/atomic/atomic-arch-fallback.h
1921
return raw_xchg(&v->counter, new);
include/linux/atomic/atomic-arch-fallback.h
1937
raw_atomic_xchg_acquire(atomic_t *v, int new)
include/linux/atomic/atomic-arch-fallback.h
1940
return arch_atomic_xchg_acquire(v, new);
include/linux/atomic/atomic-arch-fallback.h
1942
int ret = arch_atomic_xchg_relaxed(v, new);
include/linux/atomic/atomic-arch-fallback.h
1946
return arch_atomic_xchg(v, new);
include/linux/atomic/atomic-arch-fallback.h
1948
return raw_xchg_acquire(&v->counter, new);
include/linux/atomic/atomic-arch-fallback.h
1964
raw_atomic_xchg_release(atomic_t *v, int new)
include/linux/atomic/atomic-arch-fallback.h
1967
return arch_atomic_xchg_release(v, new);
include/linux/atomic/atomic-arch-fallback.h
1970
return arch_atomic_xchg_relaxed(v, new);
include/linux/atomic/atomic-arch-fallback.h
1972
return arch_atomic_xchg(v, new);
include/linux/atomic/atomic-arch-fallback.h
1974
return raw_xchg_release(&v->counter, new);
include/linux/atomic/atomic-arch-fallback.h
1990
raw_atomic_xchg_relaxed(atomic_t *v, int new)
include/linux/atomic/atomic-arch-fallback.h
1993
return arch_atomic_xchg_relaxed(v, new);
include/linux/atomic/atomic-arch-fallback.h
1995
return arch_atomic_xchg(v, new);
include/linux/atomic/atomic-arch-fallback.h
1997
return raw_xchg_relaxed(&v->counter, new);
include/linux/atomic/atomic-arch-fallback.h
2015
raw_atomic_cmpxchg(atomic_t *v, int old, int new)
include/linux/atomic/atomic-arch-fallback.h
2018
return arch_atomic_cmpxchg(v, old, new);
include/linux/atomic/atomic-arch-fallback.h
2022
ret = arch_atomic_cmpxchg_relaxed(v, old, new);
include/linux/atomic/atomic-arch-fallback.h
2026
return raw_cmpxchg(&v->counter, old, new);
include/linux/atomic/atomic-arch-fallback.h
2044
raw_atomic_cmpxchg_acquire(atomic_t *v, int old, int new)
include/linux/atomic/atomic-arch-fallback.h
2047
return arch_atomic_cmpxchg_acquire(v, old, new);
include/linux/atomic/atomic-arch-fallback.h
2049
int ret = arch_atomic_cmpxchg_relaxed(v, old, new);
include/linux/atomic/atomic-arch-fallback.h
2053
return arch_atomic_cmpxchg(v, old, new);
include/linux/atomic/atomic-arch-fallback.h
2055
return raw_cmpxchg_acquire(&v->counter, old, new);
include/linux/atomic/atomic-arch-fallback.h
2073
raw_atomic_cmpxchg_release(atomic_t *v, int old, int new)
include/linux/atomic/atomic-arch-fallback.h
2076
return arch_atomic_cmpxchg_release(v, old, new);
include/linux/atomic/atomic-arch-fallback.h
2079
return arch_atomic_cmpxchg_relaxed(v, old, new);
include/linux/atomic/atomic-arch-fallback.h
2081
return arch_atomic_cmpxchg(v, old, new);
include/linux/atomic/atomic-arch-fallback.h
2083
return raw_cmpxchg_release(&v->counter, old, new);
include/linux/atomic/atomic-arch-fallback.h
2101
raw_atomic_cmpxchg_relaxed(atomic_t *v, int old, int new)
include/linux/atomic/atomic-arch-fallback.h
2104
return arch_atomic_cmpxchg_relaxed(v, old, new);
include/linux/atomic/atomic-arch-fallback.h
2106
return arch_atomic_cmpxchg(v, old, new);
include/linux/atomic/atomic-arch-fallback.h
2108
return raw_cmpxchg_relaxed(&v->counter, old, new);
include/linux/atomic/atomic-arch-fallback.h
2127
raw_atomic_try_cmpxchg(atomic_t *v, int *old, int new)
include/linux/atomic/atomic-arch-fallback.h
2130
return arch_atomic_try_cmpxchg(v, old, new);
include/linux/atomic/atomic-arch-fallback.h
2134
ret = arch_atomic_try_cmpxchg_relaxed(v, old, new);
include/linux/atomic/atomic-arch-fallback.h
2139
r = raw_atomic_cmpxchg(v, o, new);
include/linux/atomic/atomic-arch-fallback.h
2161
raw_atomic_try_cmpxchg_acquire(atomic_t *v, int *old, int new)
include/linux/atomic/atomic-arch-fallback.h
2164
return arch_atomic_try_cmpxchg_acquire(v, old, new);
include/linux/atomic/atomic-arch-fallback.h
2166
bool ret = arch_atomic_try_cmpxchg_relaxed(v, old, new);
include/linux/atomic/atomic-arch-fallback.h
2170
return arch_atomic_try_cmpxchg(v, old, new);
include/linux/atomic/atomic-arch-fallback.h
2173
r = raw_atomic_cmpxchg_acquire(v, o, new);
include/linux/atomic/atomic-arch-fallback.h
2195
raw_atomic_try_cmpxchg_release(atomic_t *v, int *old, int new)
include/linux/atomic/atomic-arch-fallback.h
2198
return arch_atomic_try_cmpxchg_release(v, old, new);
include/linux/atomic/atomic-arch-fallback.h
2201
return arch_atomic_try_cmpxchg_relaxed(v, old, new);
include/linux/atomic/atomic-arch-fallback.h
2203
return arch_atomic_try_cmpxchg(v, old, new);
include/linux/atomic/atomic-arch-fallback.h
2206
r = raw_atomic_cmpxchg_release(v, o, new);
include/linux/atomic/atomic-arch-fallback.h
2228
raw_atomic_try_cmpxchg_relaxed(atomic_t *v, int *old, int new)
include/linux/atomic/atomic-arch-fallback.h
2231
return arch_atomic_try_cmpxchg_relaxed(v, old, new);
include/linux/atomic/atomic-arch-fallback.h
2233
return arch_atomic_try_cmpxchg(v, old, new);
include/linux/atomic/atomic-arch-fallback.h
2236
r = raw_atomic_cmpxchg_relaxed(v, o, new);
include/linux/atomic/atomic-arch-fallback.h
2255
raw_atomic_sub_and_test(int i, atomic_t *v)
include/linux/atomic/atomic-arch-fallback.h
2258
return arch_atomic_sub_and_test(i, v);
include/linux/atomic/atomic-arch-fallback.h
2260
return raw_atomic_sub_return(i, v) == 0;
include/linux/atomic/atomic-arch-fallback.h
2275
raw_atomic_dec_and_test(atomic_t *v)
include/linux/atomic/atomic-arch-fallback.h
2278
return arch_atomic_dec_and_test(v);
include/linux/atomic/atomic-arch-fallback.h
2280
return raw_atomic_dec_return(v) == 0;
include/linux/atomic/atomic-arch-fallback.h
2295
raw_atomic_inc_and_test(atomic_t *v)
include/linux/atomic/atomic-arch-fallback.h
2298
return arch_atomic_inc_and_test(v);
include/linux/atomic/atomic-arch-fallback.h
2300
return raw_atomic_inc_return(v) == 0;
include/linux/atomic/atomic-arch-fallback.h
2316
raw_atomic_add_negative(int i, atomic_t *v)
include/linux/atomic/atomic-arch-fallback.h
2319
return arch_atomic_add_negative(i, v);
include/linux/atomic/atomic-arch-fallback.h
2323
ret = arch_atomic_add_negative_relaxed(i, v);
include/linux/atomic/atomic-arch-fallback.h
2327
return raw_atomic_add_return(i, v) < 0;
include/linux/atomic/atomic-arch-fallback.h
2343
raw_atomic_add_negative_acquire(int i, atomic_t *v)
include/linux/atomic/atomic-arch-fallback.h
2346
return arch_atomic_add_negative_acquire(i, v);
include/linux/atomic/atomic-arch-fallback.h
2348
bool ret = arch_atomic_add_negative_relaxed(i, v);
include/linux/atomic/atomic-arch-fallback.h
2352
return arch_atomic_add_negative(i, v);
include/linux/atomic/atomic-arch-fallback.h
2354
return raw_atomic_add_return_acquire(i, v) < 0;
include/linux/atomic/atomic-arch-fallback.h
2370
raw_atomic_add_negative_release(int i, atomic_t *v)
include/linux/atomic/atomic-arch-fallback.h
2373
return arch_atomic_add_negative_release(i, v);
include/linux/atomic/atomic-arch-fallback.h
2376
return arch_atomic_add_negative_relaxed(i, v);
include/linux/atomic/atomic-arch-fallback.h
2378
return arch_atomic_add_negative(i, v);
include/linux/atomic/atomic-arch-fallback.h
2380
return raw_atomic_add_return_release(i, v) < 0;
include/linux/atomic/atomic-arch-fallback.h
2396
raw_atomic_add_negative_relaxed(int i, atomic_t *v)
include/linux/atomic/atomic-arch-fallback.h
2399
return arch_atomic_add_negative_relaxed(i, v);
include/linux/atomic/atomic-arch-fallback.h
2401
return arch_atomic_add_negative(i, v);
include/linux/atomic/atomic-arch-fallback.h
2403
return raw_atomic_add_return_relaxed(i, v) < 0;
include/linux/atomic/atomic-arch-fallback.h
2421
raw_atomic_fetch_add_unless(atomic_t *v, int a, int u)
include/linux/atomic/atomic-arch-fallback.h
2424
return arch_atomic_fetch_add_unless(v, a, u);
include/linux/atomic/atomic-arch-fallback.h
2426
int c = raw_atomic_read(v);
include/linux/atomic/atomic-arch-fallback.h
2431
} while (!raw_atomic_try_cmpxchg(v, &c, c + a));
include/linux/atomic/atomic-arch-fallback.h
2451
raw_atomic_add_unless(atomic_t *v, int a, int u)
include/linux/atomic/atomic-arch-fallback.h
2454
return arch_atomic_add_unless(v, a, u);
include/linux/atomic/atomic-arch-fallback.h
2456
return raw_atomic_fetch_add_unless(v, a, u) != u;
include/linux/atomic/atomic-arch-fallback.h
2472
raw_atomic_inc_not_zero(atomic_t *v)
include/linux/atomic/atomic-arch-fallback.h
2475
return arch_atomic_inc_not_zero(v);
include/linux/atomic/atomic-arch-fallback.h
2477
return raw_atomic_add_unless(v, 1, 0);
include/linux/atomic/atomic-arch-fallback.h
2493
raw_atomic_inc_unless_negative(atomic_t *v)
include/linux/atomic/atomic-arch-fallback.h
2496
return arch_atomic_inc_unless_negative(v);
include/linux/atomic/atomic-arch-fallback.h
2498
int c = raw_atomic_read(v);
include/linux/atomic/atomic-arch-fallback.h
2503
} while (!raw_atomic_try_cmpxchg(v, &c, c + 1));
include/linux/atomic/atomic-arch-fallback.h
2521
raw_atomic_dec_unless_positive(atomic_t *v)
include/linux/atomic/atomic-arch-fallback.h
2524
return arch_atomic_dec_unless_positive(v);
include/linux/atomic/atomic-arch-fallback.h
2526
int c = raw_atomic_read(v);
include/linux/atomic/atomic-arch-fallback.h
2531
} while (!raw_atomic_try_cmpxchg(v, &c, c - 1));
include/linux/atomic/atomic-arch-fallback.h
2549
raw_atomic_dec_if_positive(atomic_t *v)
include/linux/atomic/atomic-arch-fallback.h
2552
return arch_atomic_dec_if_positive(v);
include/linux/atomic/atomic-arch-fallback.h
2554
int dec, c = raw_atomic_read(v);
include/linux/atomic/atomic-arch-fallback.h
2560
} while (!raw_atomic_try_cmpxchg(v, &c, dec));
include/linux/atomic/atomic-arch-fallback.h
2581
raw_atomic64_read(const atomic64_t *v)
include/linux/atomic/atomic-arch-fallback.h
2583
return arch_atomic64_read(v);
include/linux/atomic/atomic-arch-fallback.h
2597
raw_atomic64_read_acquire(const atomic64_t *v)
include/linux/atomic/atomic-arch-fallback.h
2600
return arch_atomic64_read_acquire(v);
include/linux/atomic/atomic-arch-fallback.h
2605
ret = smp_load_acquire(&(v)->counter);
include/linux/atomic/atomic-arch-fallback.h
2607
ret = raw_atomic64_read(v);
include/linux/atomic/atomic-arch-fallback.h
2627
raw_atomic64_set(atomic64_t *v, s64 i)
include/linux/atomic/atomic-arch-fallback.h
2629
arch_atomic64_set(v, i);
include/linux/atomic/atomic-arch-fallback.h
2644
raw_atomic64_set_release(atomic64_t *v, s64 i)
include/linux/atomic/atomic-arch-fallback.h
2647
arch_atomic64_set_release(v, i);
include/linux/atomic/atomic-arch-fallback.h
2650
smp_store_release(&(v)->counter, i);
include/linux/atomic/atomic-arch-fallback.h
2653
raw_atomic64_set(v, i);
include/linux/atomic/atomic-arch-fallback.h
2670
raw_atomic64_add(s64 i, atomic64_t *v)
include/linux/atomic/atomic-arch-fallback.h
2672
arch_atomic64_add(i, v);
include/linux/atomic/atomic-arch-fallback.h
2687
raw_atomic64_add_return(s64 i, atomic64_t *v)
include/linux/atomic/atomic-arch-fallback.h
2690
return arch_atomic64_add_return(i, v);
include/linux/atomic/atomic-arch-fallback.h
2694
ret = arch_atomic64_add_return_relaxed(i, v);
include/linux/atomic/atomic-arch-fallback.h
2714
raw_atomic64_add_return_acquire(s64 i, atomic64_t *v)
include/linux/atomic/atomic-arch-fallback.h
2717
return arch_atomic64_add_return_acquire(i, v);
include/linux/atomic/atomic-arch-fallback.h
2719
s64 ret = arch_atomic64_add_return_relaxed(i, v);
include/linux/atomic/atomic-arch-fallback.h
2723
return arch_atomic64_add_return(i, v);
include/linux/atomic/atomic-arch-fallback.h
2741
raw_atomic64_add_return_release(s64 i, atomic64_t *v)
include/linux/atomic/atomic-arch-fallback.h
2744
return arch_atomic64_add_return_release(i, v);
include/linux/atomic/atomic-arch-fallback.h
2747
return arch_atomic64_add_return_relaxed(i, v);
include/linux/atomic/atomic-arch-fallback.h
2749
return arch_atomic64_add_return(i, v);
include/linux/atomic/atomic-arch-fallback.h
2767
raw_atomic64_add_return_relaxed(s64 i, atomic64_t *v)
include/linux/atomic/atomic-arch-fallback.h
2770
return arch_atomic64_add_return_relaxed(i, v);
include/linux/atomic/atomic-arch-fallback.h
2772
return arch_atomic64_add_return(i, v);
include/linux/atomic/atomic-arch-fallback.h
2790
raw_atomic64_fetch_add(s64 i, atomic64_t *v)
include/linux/atomic/atomic-arch-fallback.h
2793
return arch_atomic64_fetch_add(i, v);
include/linux/atomic/atomic-arch-fallback.h
2797
ret = arch_atomic64_fetch_add_relaxed(i, v);
include/linux/atomic/atomic-arch-fallback.h
2817
raw_atomic64_fetch_add_acquire(s64 i, atomic64_t *v)
include/linux/atomic/atomic-arch-fallback.h
2820
return arch_atomic64_fetch_add_acquire(i, v);
include/linux/atomic/atomic-arch-fallback.h
2822
s64 ret = arch_atomic64_fetch_add_relaxed(i, v);
include/linux/atomic/atomic-arch-fallback.h
2826
return arch_atomic64_fetch_add(i, v);
include/linux/atomic/atomic-arch-fallback.h
2844
raw_atomic64_fetch_add_release(s64 i, atomic64_t *v)
include/linux/atomic/atomic-arch-fallback.h
2847
return arch_atomic64_fetch_add_release(i, v);
include/linux/atomic/atomic-arch-fallback.h
2850
return arch_atomic64_fetch_add_relaxed(i, v);
include/linux/atomic/atomic-arch-fallback.h
2852
return arch_atomic64_fetch_add(i, v);
include/linux/atomic/atomic-arch-fallback.h
2870
raw_atomic64_fetch_add_relaxed(s64 i, atomic64_t *v)
include/linux/atomic/atomic-arch-fallback.h
2873
return arch_atomic64_fetch_add_relaxed(i, v);
include/linux/atomic/atomic-arch-fallback.h
2875
return arch_atomic64_fetch_add(i, v);
include/linux/atomic/atomic-arch-fallback.h
2893
raw_atomic64_sub(s64 i, atomic64_t *v)
include/linux/atomic/atomic-arch-fallback.h
2895
arch_atomic64_sub(i, v);
include/linux/atomic/atomic-arch-fallback.h
2910
raw_atomic64_sub_return(s64 i, atomic64_t *v)
include/linux/atomic/atomic-arch-fallback.h
2913
return arch_atomic64_sub_return(i, v);
include/linux/atomic/atomic-arch-fallback.h
2917
ret = arch_atomic64_sub_return_relaxed(i, v);
include/linux/atomic/atomic-arch-fallback.h
2937
raw_atomic64_sub_return_acquire(s64 i, atomic64_t *v)
include/linux/atomic/atomic-arch-fallback.h
2940
return arch_atomic64_sub_return_acquire(i, v);
include/linux/atomic/atomic-arch-fallback.h
2942
s64 ret = arch_atomic64_sub_return_relaxed(i, v);
include/linux/atomic/atomic-arch-fallback.h
2946
return arch_atomic64_sub_return(i, v);
include/linux/atomic/atomic-arch-fallback.h
2964
raw_atomic64_sub_return_release(s64 i, atomic64_t *v)
include/linux/atomic/atomic-arch-fallback.h
2967
return arch_atomic64_sub_return_release(i, v);
include/linux/atomic/atomic-arch-fallback.h
2970
return arch_atomic64_sub_return_relaxed(i, v);
include/linux/atomic/atomic-arch-fallback.h
2972
return arch_atomic64_sub_return(i, v);
include/linux/atomic/atomic-arch-fallback.h
2990
raw_atomic64_sub_return_relaxed(s64 i, atomic64_t *v)
include/linux/atomic/atomic-arch-fallback.h
2993
return arch_atomic64_sub_return_relaxed(i, v);
include/linux/atomic/atomic-arch-fallback.h
2995
return arch_atomic64_sub_return(i, v);
include/linux/atomic/atomic-arch-fallback.h
3013
raw_atomic64_fetch_sub(s64 i, atomic64_t *v)
include/linux/atomic/atomic-arch-fallback.h
3016
return arch_atomic64_fetch_sub(i, v);
include/linux/atomic/atomic-arch-fallback.h
3020
ret = arch_atomic64_fetch_sub_relaxed(i, v);
include/linux/atomic/atomic-arch-fallback.h
3040
raw_atomic64_fetch_sub_acquire(s64 i, atomic64_t *v)
include/linux/atomic/atomic-arch-fallback.h
3043
return arch_atomic64_fetch_sub_acquire(i, v);
include/linux/atomic/atomic-arch-fallback.h
3045
s64 ret = arch_atomic64_fetch_sub_relaxed(i, v);
include/linux/atomic/atomic-arch-fallback.h
3049
return arch_atomic64_fetch_sub(i, v);
include/linux/atomic/atomic-arch-fallback.h
3067
raw_atomic64_fetch_sub_release(s64 i, atomic64_t *v)
include/linux/atomic/atomic-arch-fallback.h
3070
return arch_atomic64_fetch_sub_release(i, v);
include/linux/atomic/atomic-arch-fallback.h
3073
return arch_atomic64_fetch_sub_relaxed(i, v);
include/linux/atomic/atomic-arch-fallback.h
3075
return arch_atomic64_fetch_sub(i, v);
include/linux/atomic/atomic-arch-fallback.h
3093
raw_atomic64_fetch_sub_relaxed(s64 i, atomic64_t *v)
include/linux/atomic/atomic-arch-fallback.h
3096
return arch_atomic64_fetch_sub_relaxed(i, v);
include/linux/atomic/atomic-arch-fallback.h
3098
return arch_atomic64_fetch_sub(i, v);
include/linux/atomic/atomic-arch-fallback.h
3115
raw_atomic64_inc(atomic64_t *v)
include/linux/atomic/atomic-arch-fallback.h
3118
arch_atomic64_inc(v);
include/linux/atomic/atomic-arch-fallback.h
3120
raw_atomic64_add(1, v);
include/linux/atomic/atomic-arch-fallback.h
3135
raw_atomic64_inc_return(atomic64_t *v)
include/linux/atomic/atomic-arch-fallback.h
3138
return arch_atomic64_inc_return(v);
include/linux/atomic/atomic-arch-fallback.h
3142
ret = arch_atomic64_inc_return_relaxed(v);
include/linux/atomic/atomic-arch-fallback.h
3146
return raw_atomic64_add_return(1, v);
include/linux/atomic/atomic-arch-fallback.h
3161
raw_atomic64_inc_return_acquire(atomic64_t *v)
include/linux/atomic/atomic-arch-fallback.h
3164
return arch_atomic64_inc_return_acquire(v);
include/linux/atomic/atomic-arch-fallback.h
3166
s64 ret = arch_atomic64_inc_return_relaxed(v);
include/linux/atomic/atomic-arch-fallback.h
3170
return arch_atomic64_inc_return(v);
include/linux/atomic/atomic-arch-fallback.h
3172
return raw_atomic64_add_return_acquire(1, v);
include/linux/atomic/atomic-arch-fallback.h
3187
raw_atomic64_inc_return_release(atomic64_t *v)
include/linux/atomic/atomic-arch-fallback.h
3190
return arch_atomic64_inc_return_release(v);
include/linux/atomic/atomic-arch-fallback.h
3193
return arch_atomic64_inc_return_relaxed(v);
include/linux/atomic/atomic-arch-fallback.h
3195
return arch_atomic64_inc_return(v);
include/linux/atomic/atomic-arch-fallback.h
3197
return raw_atomic64_add_return_release(1, v);
include/linux/atomic/atomic-arch-fallback.h
3212
raw_atomic64_inc_return_relaxed(atomic64_t *v)
include/linux/atomic/atomic-arch-fallback.h
3215
return arch_atomic64_inc_return_relaxed(v);
include/linux/atomic/atomic-arch-fallback.h
3217
return arch_atomic64_inc_return(v);
include/linux/atomic/atomic-arch-fallback.h
3219
return raw_atomic64_add_return_relaxed(1, v);
include/linux/atomic/atomic-arch-fallback.h
3234
raw_atomic64_fetch_inc(atomic64_t *v)
include/linux/atomic/atomic-arch-fallback.h
3237
return arch_atomic64_fetch_inc(v);
include/linux/atomic/atomic-arch-fallback.h
3241
ret = arch_atomic64_fetch_inc_relaxed(v);
include/linux/atomic/atomic-arch-fallback.h
3245
return raw_atomic64_fetch_add(1, v);
include/linux/atomic/atomic-arch-fallback.h
3260
raw_atomic64_fetch_inc_acquire(atomic64_t *v)
include/linux/atomic/atomic-arch-fallback.h
3263
return arch_atomic64_fetch_inc_acquire(v);
include/linux/atomic/atomic-arch-fallback.h
3265
s64 ret = arch_atomic64_fetch_inc_relaxed(v);
include/linux/atomic/atomic-arch-fallback.h
3269
return arch_atomic64_fetch_inc(v);
include/linux/atomic/atomic-arch-fallback.h
3271
return raw_atomic64_fetch_add_acquire(1, v);
include/linux/atomic/atomic-arch-fallback.h
3286
raw_atomic64_fetch_inc_release(atomic64_t *v)
include/linux/atomic/atomic-arch-fallback.h
3289
return arch_atomic64_fetch_inc_release(v);
include/linux/atomic/atomic-arch-fallback.h
3292
return arch_atomic64_fetch_inc_relaxed(v);
include/linux/atomic/atomic-arch-fallback.h
3294
return arch_atomic64_fetch_inc(v);
include/linux/atomic/atomic-arch-fallback.h
3296
return raw_atomic64_fetch_add_release(1, v);
include/linux/atomic/atomic-arch-fallback.h
3311
raw_atomic64_fetch_inc_relaxed(atomic64_t *v)
include/linux/atomic/atomic-arch-fallback.h
3314
return arch_atomic64_fetch_inc_relaxed(v);
include/linux/atomic/atomic-arch-fallback.h
3316
return arch_atomic64_fetch_inc(v);
include/linux/atomic/atomic-arch-fallback.h
3318
return raw_atomic64_fetch_add_relaxed(1, v);
include/linux/atomic/atomic-arch-fallback.h
3333
raw_atomic64_dec(atomic64_t *v)
include/linux/atomic/atomic-arch-fallback.h
3336
arch_atomic64_dec(v);
include/linux/atomic/atomic-arch-fallback.h
3338
raw_atomic64_sub(1, v);
include/linux/atomic/atomic-arch-fallback.h
3353
raw_atomic64_dec_return(atomic64_t *v)
include/linux/atomic/atomic-arch-fallback.h
3356
return arch_atomic64_dec_return(v);
include/linux/atomic/atomic-arch-fallback.h
3360
ret = arch_atomic64_dec_return_relaxed(v);
include/linux/atomic/atomic-arch-fallback.h
3364
return raw_atomic64_sub_return(1, v);
include/linux/atomic/atomic-arch-fallback.h
3379
raw_atomic64_dec_return_acquire(atomic64_t *v)
include/linux/atomic/atomic-arch-fallback.h
3382
return arch_atomic64_dec_return_acquire(v);
include/linux/atomic/atomic-arch-fallback.h
3384
s64 ret = arch_atomic64_dec_return_relaxed(v);
include/linux/atomic/atomic-arch-fallback.h
3388
return arch_atomic64_dec_return(v);
include/linux/atomic/atomic-arch-fallback.h
3390
return raw_atomic64_sub_return_acquire(1, v);
include/linux/atomic/atomic-arch-fallback.h
3405
raw_atomic64_dec_return_release(atomic64_t *v)
include/linux/atomic/atomic-arch-fallback.h
3408
return arch_atomic64_dec_return_release(v);
include/linux/atomic/atomic-arch-fallback.h
3411
return arch_atomic64_dec_return_relaxed(v);
include/linux/atomic/atomic-arch-fallback.h
3413
return arch_atomic64_dec_return(v);
include/linux/atomic/atomic-arch-fallback.h
3415
return raw_atomic64_sub_return_release(1, v);
include/linux/atomic/atomic-arch-fallback.h
3430
raw_atomic64_dec_return_relaxed(atomic64_t *v)
include/linux/atomic/atomic-arch-fallback.h
3433
return arch_atomic64_dec_return_relaxed(v);
include/linux/atomic/atomic-arch-fallback.h
3435
return arch_atomic64_dec_return(v);
include/linux/atomic/atomic-arch-fallback.h
3437
return raw_atomic64_sub_return_relaxed(1, v);
include/linux/atomic/atomic-arch-fallback.h
3452
raw_atomic64_fetch_dec(atomic64_t *v)
include/linux/atomic/atomic-arch-fallback.h
3455
return arch_atomic64_fetch_dec(v);
include/linux/atomic/atomic-arch-fallback.h
3459
ret = arch_atomic64_fetch_dec_relaxed(v);
include/linux/atomic/atomic-arch-fallback.h
3463
return raw_atomic64_fetch_sub(1, v);
include/linux/atomic/atomic-arch-fallback.h
3478
raw_atomic64_fetch_dec_acquire(atomic64_t *v)
include/linux/atomic/atomic-arch-fallback.h
3481
return arch_atomic64_fetch_dec_acquire(v);
include/linux/atomic/atomic-arch-fallback.h
3483
s64 ret = arch_atomic64_fetch_dec_relaxed(v);
include/linux/atomic/atomic-arch-fallback.h
3487
return arch_atomic64_fetch_dec(v);
include/linux/atomic/atomic-arch-fallback.h
3489
return raw_atomic64_fetch_sub_acquire(1, v);
include/linux/atomic/atomic-arch-fallback.h
3504
raw_atomic64_fetch_dec_release(atomic64_t *v)
include/linux/atomic/atomic-arch-fallback.h
3507
return arch_atomic64_fetch_dec_release(v);
include/linux/atomic/atomic-arch-fallback.h
3510
return arch_atomic64_fetch_dec_relaxed(v);
include/linux/atomic/atomic-arch-fallback.h
3512
return arch_atomic64_fetch_dec(v);
include/linux/atomic/atomic-arch-fallback.h
3514
return raw_atomic64_fetch_sub_release(1, v);
include/linux/atomic/atomic-arch-fallback.h
3529
raw_atomic64_fetch_dec_relaxed(atomic64_t *v)
include/linux/atomic/atomic-arch-fallback.h
3532
return arch_atomic64_fetch_dec_relaxed(v);
include/linux/atomic/atomic-arch-fallback.h
3534
return arch_atomic64_fetch_dec(v);
include/linux/atomic/atomic-arch-fallback.h
3536
return raw_atomic64_fetch_sub_relaxed(1, v);
include/linux/atomic/atomic-arch-fallback.h
3552
raw_atomic64_and(s64 i, atomic64_t *v)
include/linux/atomic/atomic-arch-fallback.h
3554
arch_atomic64_and(i, v);
include/linux/atomic/atomic-arch-fallback.h
3569
raw_atomic64_fetch_and(s64 i, atomic64_t *v)
include/linux/atomic/atomic-arch-fallback.h
3572
return arch_atomic64_fetch_and(i, v);
include/linux/atomic/atomic-arch-fallback.h
3576
ret = arch_atomic64_fetch_and_relaxed(i, v);
include/linux/atomic/atomic-arch-fallback.h
3596
raw_atomic64_fetch_and_acquire(s64 i, atomic64_t *v)
include/linux/atomic/atomic-arch-fallback.h
3599
return arch_atomic64_fetch_and_acquire(i, v);
include/linux/atomic/atomic-arch-fallback.h
3601
s64 ret = arch_atomic64_fetch_and_relaxed(i, v);
include/linux/atomic/atomic-arch-fallback.h
3605
return arch_atomic64_fetch_and(i, v);
include/linux/atomic/atomic-arch-fallback.h
3623
raw_atomic64_fetch_and_release(s64 i, atomic64_t *v)
include/linux/atomic/atomic-arch-fallback.h
3626
return arch_atomic64_fetch_and_release(i, v);
include/linux/atomic/atomic-arch-fallback.h
3629
return arch_atomic64_fetch_and_relaxed(i, v);
include/linux/atomic/atomic-arch-fallback.h
3631
return arch_atomic64_fetch_and(i, v);
include/linux/atomic/atomic-arch-fallback.h
3649
raw_atomic64_fetch_and_relaxed(s64 i, atomic64_t *v)
include/linux/atomic/atomic-arch-fallback.h
3652
return arch_atomic64_fetch_and_relaxed(i, v);
include/linux/atomic/atomic-arch-fallback.h
3654
return arch_atomic64_fetch_and(i, v);
include/linux/atomic/atomic-arch-fallback.h
3672
raw_atomic64_andnot(s64 i, atomic64_t *v)
include/linux/atomic/atomic-arch-fallback.h
3675
arch_atomic64_andnot(i, v);
include/linux/atomic/atomic-arch-fallback.h
3677
raw_atomic64_and(~i, v);
include/linux/atomic/atomic-arch-fallback.h
3693
raw_atomic64_fetch_andnot(s64 i, atomic64_t *v)
include/linux/atomic/atomic-arch-fallback.h
3696
return arch_atomic64_fetch_andnot(i, v);
include/linux/atomic/atomic-arch-fallback.h
3700
ret = arch_atomic64_fetch_andnot_relaxed(i, v);
include/linux/atomic/atomic-arch-fallback.h
3704
return raw_atomic64_fetch_and(~i, v);
include/linux/atomic/atomic-arch-fallback.h
3720
raw_atomic64_fetch_andnot_acquire(s64 i, atomic64_t *v)
include/linux/atomic/atomic-arch-fallback.h
3723
return arch_atomic64_fetch_andnot_acquire(i, v);
include/linux/atomic/atomic-arch-fallback.h
3725
s64 ret = arch_atomic64_fetch_andnot_relaxed(i, v);
include/linux/atomic/atomic-arch-fallback.h
3729
return arch_atomic64_fetch_andnot(i, v);
include/linux/atomic/atomic-arch-fallback.h
3731
return raw_atomic64_fetch_and_acquire(~i, v);
include/linux/atomic/atomic-arch-fallback.h
3747
raw_atomic64_fetch_andnot_release(s64 i, atomic64_t *v)
include/linux/atomic/atomic-arch-fallback.h
3750
return arch_atomic64_fetch_andnot_release(i, v);
include/linux/atomic/atomic-arch-fallback.h
3753
return arch_atomic64_fetch_andnot_relaxed(i, v);
include/linux/atomic/atomic-arch-fallback.h
3755
return arch_atomic64_fetch_andnot(i, v);
include/linux/atomic/atomic-arch-fallback.h
3757
return raw_atomic64_fetch_and_release(~i, v);
include/linux/atomic/atomic-arch-fallback.h
3773
raw_atomic64_fetch_andnot_relaxed(s64 i, atomic64_t *v)
include/linux/atomic/atomic-arch-fallback.h
3776
return arch_atomic64_fetch_andnot_relaxed(i, v);
include/linux/atomic/atomic-arch-fallback.h
3778
return arch_atomic64_fetch_andnot(i, v);
include/linux/atomic/atomic-arch-fallback.h
3780
return raw_atomic64_fetch_and_relaxed(~i, v);
include/linux/atomic/atomic-arch-fallback.h
3796
raw_atomic64_or(s64 i, atomic64_t *v)
include/linux/atomic/atomic-arch-fallback.h
3798
arch_atomic64_or(i, v);
include/linux/atomic/atomic-arch-fallback.h
3813
raw_atomic64_fetch_or(s64 i, atomic64_t *v)
include/linux/atomic/atomic-arch-fallback.h
3816
return arch_atomic64_fetch_or(i, v);
include/linux/atomic/atomic-arch-fallback.h
3820
ret = arch_atomic64_fetch_or_relaxed(i, v);
include/linux/atomic/atomic-arch-fallback.h
3840
raw_atomic64_fetch_or_acquire(s64 i, atomic64_t *v)
include/linux/atomic/atomic-arch-fallback.h
3843
return arch_atomic64_fetch_or_acquire(i, v);
include/linux/atomic/atomic-arch-fallback.h
3845
s64 ret = arch_atomic64_fetch_or_relaxed(i, v);
include/linux/atomic/atomic-arch-fallback.h
3849
return arch_atomic64_fetch_or(i, v);
include/linux/atomic/atomic-arch-fallback.h
3867
raw_atomic64_fetch_or_release(s64 i, atomic64_t *v)
include/linux/atomic/atomic-arch-fallback.h
3870
return arch_atomic64_fetch_or_release(i, v);
include/linux/atomic/atomic-arch-fallback.h
3873
return arch_atomic64_fetch_or_relaxed(i, v);
include/linux/atomic/atomic-arch-fallback.h
3875
return arch_atomic64_fetch_or(i, v);
include/linux/atomic/atomic-arch-fallback.h
3893
raw_atomic64_fetch_or_relaxed(s64 i, atomic64_t *v)
include/linux/atomic/atomic-arch-fallback.h
3896
return arch_atomic64_fetch_or_relaxed(i, v);
include/linux/atomic/atomic-arch-fallback.h
3898
return arch_atomic64_fetch_or(i, v);
include/linux/atomic/atomic-arch-fallback.h
3916
raw_atomic64_xor(s64 i, atomic64_t *v)
include/linux/atomic/atomic-arch-fallback.h
3918
arch_atomic64_xor(i, v);
include/linux/atomic/atomic-arch-fallback.h
3933
raw_atomic64_fetch_xor(s64 i, atomic64_t *v)
include/linux/atomic/atomic-arch-fallback.h
3936
return arch_atomic64_fetch_xor(i, v);
include/linux/atomic/atomic-arch-fallback.h
3940
ret = arch_atomic64_fetch_xor_relaxed(i, v);
include/linux/atomic/atomic-arch-fallback.h
3960
raw_atomic64_fetch_xor_acquire(s64 i, atomic64_t *v)
include/linux/atomic/atomic-arch-fallback.h
3963
return arch_atomic64_fetch_xor_acquire(i, v);
include/linux/atomic/atomic-arch-fallback.h
3965
s64 ret = arch_atomic64_fetch_xor_relaxed(i, v);
include/linux/atomic/atomic-arch-fallback.h
3969
return arch_atomic64_fetch_xor(i, v);
include/linux/atomic/atomic-arch-fallback.h
3987
raw_atomic64_fetch_xor_release(s64 i, atomic64_t *v)
include/linux/atomic/atomic-arch-fallback.h
3990
return arch_atomic64_fetch_xor_release(i, v);
include/linux/atomic/atomic-arch-fallback.h
3993
return arch_atomic64_fetch_xor_relaxed(i, v);
include/linux/atomic/atomic-arch-fallback.h
3995
return arch_atomic64_fetch_xor(i, v);
include/linux/atomic/atomic-arch-fallback.h
4013
raw_atomic64_fetch_xor_relaxed(s64 i, atomic64_t *v)
include/linux/atomic/atomic-arch-fallback.h
4016
return arch_atomic64_fetch_xor_relaxed(i, v);
include/linux/atomic/atomic-arch-fallback.h
4018
return arch_atomic64_fetch_xor(i, v);
include/linux/atomic/atomic-arch-fallback.h
4036
raw_atomic64_xchg(atomic64_t *v, s64 new)
include/linux/atomic/atomic-arch-fallback.h
4039
return arch_atomic64_xchg(v, new);
include/linux/atomic/atomic-arch-fallback.h
4043
ret = arch_atomic64_xchg_relaxed(v, new);
include/linux/atomic/atomic-arch-fallback.h
4047
return raw_xchg(&v->counter, new);
include/linux/atomic/atomic-arch-fallback.h
4063
raw_atomic64_xchg_acquire(atomic64_t *v, s64 new)
include/linux/atomic/atomic-arch-fallback.h
4066
return arch_atomic64_xchg_acquire(v, new);
include/linux/atomic/atomic-arch-fallback.h
4068
s64 ret = arch_atomic64_xchg_relaxed(v, new);
include/linux/atomic/atomic-arch-fallback.h
4072
return arch_atomic64_xchg(v, new);
include/linux/atomic/atomic-arch-fallback.h
4074
return raw_xchg_acquire(&v->counter, new);
include/linux/atomic/atomic-arch-fallback.h
4090
raw_atomic64_xchg_release(atomic64_t *v, s64 new)
include/linux/atomic/atomic-arch-fallback.h
4093
return arch_atomic64_xchg_release(v, new);
include/linux/atomic/atomic-arch-fallback.h
4096
return arch_atomic64_xchg_relaxed(v, new);
include/linux/atomic/atomic-arch-fallback.h
4098
return arch_atomic64_xchg(v, new);
include/linux/atomic/atomic-arch-fallback.h
4100
return raw_xchg_release(&v->counter, new);
include/linux/atomic/atomic-arch-fallback.h
4116
raw_atomic64_xchg_relaxed(atomic64_t *v, s64 new)
include/linux/atomic/atomic-arch-fallback.h
4119
return arch_atomic64_xchg_relaxed(v, new);
include/linux/atomic/atomic-arch-fallback.h
4121
return arch_atomic64_xchg(v, new);
include/linux/atomic/atomic-arch-fallback.h
4123
return raw_xchg_relaxed(&v->counter, new);
include/linux/atomic/atomic-arch-fallback.h
4141
raw_atomic64_cmpxchg(atomic64_t *v, s64 old, s64 new)
include/linux/atomic/atomic-arch-fallback.h
4144
return arch_atomic64_cmpxchg(v, old, new);
include/linux/atomic/atomic-arch-fallback.h
4148
ret = arch_atomic64_cmpxchg_relaxed(v, old, new);
include/linux/atomic/atomic-arch-fallback.h
4152
return raw_cmpxchg(&v->counter, old, new);
include/linux/atomic/atomic-arch-fallback.h
4170
raw_atomic64_cmpxchg_acquire(atomic64_t *v, s64 old, s64 new)
include/linux/atomic/atomic-arch-fallback.h
4173
return arch_atomic64_cmpxchg_acquire(v, old, new);
include/linux/atomic/atomic-arch-fallback.h
4175
s64 ret = arch_atomic64_cmpxchg_relaxed(v, old, new);
include/linux/atomic/atomic-arch-fallback.h
4179
return arch_atomic64_cmpxchg(v, old, new);
include/linux/atomic/atomic-arch-fallback.h
4181
return raw_cmpxchg_acquire(&v->counter, old, new);
include/linux/atomic/atomic-arch-fallback.h
4199
raw_atomic64_cmpxchg_release(atomic64_t *v, s64 old, s64 new)
include/linux/atomic/atomic-arch-fallback.h
4202
return arch_atomic64_cmpxchg_release(v, old, new);
include/linux/atomic/atomic-arch-fallback.h
4205
return arch_atomic64_cmpxchg_relaxed(v, old, new);
include/linux/atomic/atomic-arch-fallback.h
4207
return arch_atomic64_cmpxchg(v, old, new);
include/linux/atomic/atomic-arch-fallback.h
4209
return raw_cmpxchg_release(&v->counter, old, new);
include/linux/atomic/atomic-arch-fallback.h
4227
raw_atomic64_cmpxchg_relaxed(atomic64_t *v, s64 old, s64 new)
include/linux/atomic/atomic-arch-fallback.h
4230
return arch_atomic64_cmpxchg_relaxed(v, old, new);
include/linux/atomic/atomic-arch-fallback.h
4232
return arch_atomic64_cmpxchg(v, old, new);
include/linux/atomic/atomic-arch-fallback.h
4234
return raw_cmpxchg_relaxed(&v->counter, old, new);
include/linux/atomic/atomic-arch-fallback.h
4253
raw_atomic64_try_cmpxchg(atomic64_t *v, s64 *old, s64 new)
include/linux/atomic/atomic-arch-fallback.h
4256
return arch_atomic64_try_cmpxchg(v, old, new);
include/linux/atomic/atomic-arch-fallback.h
4260
ret = arch_atomic64_try_cmpxchg_relaxed(v, old, new);
include/linux/atomic/atomic-arch-fallback.h
4265
r = raw_atomic64_cmpxchg(v, o, new);
include/linux/atomic/atomic-arch-fallback.h
4287
raw_atomic64_try_cmpxchg_acquire(atomic64_t *v, s64 *old, s64 new)
include/linux/atomic/atomic-arch-fallback.h
4290
return arch_atomic64_try_cmpxchg_acquire(v, old, new);
include/linux/atomic/atomic-arch-fallback.h
4292
bool ret = arch_atomic64_try_cmpxchg_relaxed(v, old, new);
include/linux/atomic/atomic-arch-fallback.h
4296
return arch_atomic64_try_cmpxchg(v, old, new);
include/linux/atomic/atomic-arch-fallback.h
4299
r = raw_atomic64_cmpxchg_acquire(v, o, new);
include/linux/atomic/atomic-arch-fallback.h
4321
raw_atomic64_try_cmpxchg_release(atomic64_t *v, s64 *old, s64 new)
include/linux/atomic/atomic-arch-fallback.h
4324
return arch_atomic64_try_cmpxchg_release(v, old, new);
include/linux/atomic/atomic-arch-fallback.h
4327
return arch_atomic64_try_cmpxchg_relaxed(v, old, new);
include/linux/atomic/atomic-arch-fallback.h
4329
return arch_atomic64_try_cmpxchg(v, old, new);
include/linux/atomic/atomic-arch-fallback.h
4332
r = raw_atomic64_cmpxchg_release(v, o, new);
include/linux/atomic/atomic-arch-fallback.h
4354
raw_atomic64_try_cmpxchg_relaxed(atomic64_t *v, s64 *old, s64 new)
include/linux/atomic/atomic-arch-fallback.h
4357
return arch_atomic64_try_cmpxchg_relaxed(v, old, new);
include/linux/atomic/atomic-arch-fallback.h
4359
return arch_atomic64_try_cmpxchg(v, old, new);
include/linux/atomic/atomic-arch-fallback.h
4362
r = raw_atomic64_cmpxchg_relaxed(v, o, new);
include/linux/atomic/atomic-arch-fallback.h
4381
raw_atomic64_sub_and_test(s64 i, atomic64_t *v)
include/linux/atomic/atomic-arch-fallback.h
4384
return arch_atomic64_sub_and_test(i, v);
include/linux/atomic/atomic-arch-fallback.h
4386
return raw_atomic64_sub_return(i, v) == 0;
include/linux/atomic/atomic-arch-fallback.h
4401
raw_atomic64_dec_and_test(atomic64_t *v)
include/linux/atomic/atomic-arch-fallback.h
4404
return arch_atomic64_dec_and_test(v);
include/linux/atomic/atomic-arch-fallback.h
4406
return raw_atomic64_dec_return(v) == 0;
include/linux/atomic/atomic-arch-fallback.h
4421
raw_atomic64_inc_and_test(atomic64_t *v)
include/linux/atomic/atomic-arch-fallback.h
4424
return arch_atomic64_inc_and_test(v);
include/linux/atomic/atomic-arch-fallback.h
4426
return raw_atomic64_inc_return(v) == 0;
include/linux/atomic/atomic-arch-fallback.h
4442
raw_atomic64_add_negative(s64 i, atomic64_t *v)
include/linux/atomic/atomic-arch-fallback.h
4445
return arch_atomic64_add_negative(i, v);
include/linux/atomic/atomic-arch-fallback.h
4449
ret = arch_atomic64_add_negative_relaxed(i, v);
include/linux/atomic/atomic-arch-fallback.h
4453
return raw_atomic64_add_return(i, v) < 0;
include/linux/atomic/atomic-arch-fallback.h
4469
raw_atomic64_add_negative_acquire(s64 i, atomic64_t *v)
include/linux/atomic/atomic-arch-fallback.h
4472
return arch_atomic64_add_negative_acquire(i, v);
include/linux/atomic/atomic-arch-fallback.h
4474
bool ret = arch_atomic64_add_negative_relaxed(i, v);
include/linux/atomic/atomic-arch-fallback.h
4478
return arch_atomic64_add_negative(i, v);
include/linux/atomic/atomic-arch-fallback.h
4480
return raw_atomic64_add_return_acquire(i, v) < 0;
include/linux/atomic/atomic-arch-fallback.h
4496
raw_atomic64_add_negative_release(s64 i, atomic64_t *v)
include/linux/atomic/atomic-arch-fallback.h
4499
return arch_atomic64_add_negative_release(i, v);
include/linux/atomic/atomic-arch-fallback.h
4502
return arch_atomic64_add_negative_relaxed(i, v);
include/linux/atomic/atomic-arch-fallback.h
4504
return arch_atomic64_add_negative(i, v);
include/linux/atomic/atomic-arch-fallback.h
4506
return raw_atomic64_add_return_release(i, v) < 0;
include/linux/atomic/atomic-arch-fallback.h
4522
raw_atomic64_add_negative_relaxed(s64 i, atomic64_t *v)
include/linux/atomic/atomic-arch-fallback.h
4525
return arch_atomic64_add_negative_relaxed(i, v);
include/linux/atomic/atomic-arch-fallback.h
4527
return arch_atomic64_add_negative(i, v);
include/linux/atomic/atomic-arch-fallback.h
4529
return raw_atomic64_add_return_relaxed(i, v) < 0;
include/linux/atomic/atomic-arch-fallback.h
4547
raw_atomic64_fetch_add_unless(atomic64_t *v, s64 a, s64 u)
include/linux/atomic/atomic-arch-fallback.h
455
raw_atomic_read(const atomic_t *v)
include/linux/atomic/atomic-arch-fallback.h
4550
return arch_atomic64_fetch_add_unless(v, a, u);
include/linux/atomic/atomic-arch-fallback.h
4552
s64 c = raw_atomic64_read(v);
include/linux/atomic/atomic-arch-fallback.h
4557
} while (!raw_atomic64_try_cmpxchg(v, &c, c + a));
include/linux/atomic/atomic-arch-fallback.h
457
return arch_atomic_read(v);
include/linux/atomic/atomic-arch-fallback.h
4577
raw_atomic64_add_unless(atomic64_t *v, s64 a, s64 u)
include/linux/atomic/atomic-arch-fallback.h
4580
return arch_atomic64_add_unless(v, a, u);
include/linux/atomic/atomic-arch-fallback.h
4582
return raw_atomic64_fetch_add_unless(v, a, u) != u;
include/linux/atomic/atomic-arch-fallback.h
4598
raw_atomic64_inc_not_zero(atomic64_t *v)
include/linux/atomic/atomic-arch-fallback.h
4601
return arch_atomic64_inc_not_zero(v);
include/linux/atomic/atomic-arch-fallback.h
4603
return raw_atomic64_add_unless(v, 1, 0);
include/linux/atomic/atomic-arch-fallback.h
4619
raw_atomic64_inc_unless_negative(atomic64_t *v)
include/linux/atomic/atomic-arch-fallback.h
4622
return arch_atomic64_inc_unless_negative(v);
include/linux/atomic/atomic-arch-fallback.h
4624
s64 c = raw_atomic64_read(v);
include/linux/atomic/atomic-arch-fallback.h
4629
} while (!raw_atomic64_try_cmpxchg(v, &c, c + 1));
include/linux/atomic/atomic-arch-fallback.h
4647
raw_atomic64_dec_unless_positive(atomic64_t *v)
include/linux/atomic/atomic-arch-fallback.h
4650
return arch_atomic64_dec_unless_positive(v);
include/linux/atomic/atomic-arch-fallback.h
4652
s64 c = raw_atomic64_read(v);
include/linux/atomic/atomic-arch-fallback.h
4657
} while (!raw_atomic64_try_cmpxchg(v, &c, c - 1));
include/linux/atomic/atomic-arch-fallback.h
4675
raw_atomic64_dec_if_positive(atomic64_t *v)
include/linux/atomic/atomic-arch-fallback.h
4678
return arch_atomic64_dec_if_positive(v);
include/linux/atomic/atomic-arch-fallback.h
4680
s64 dec, c = raw_atomic64_read(v);
include/linux/atomic/atomic-arch-fallback.h
4686
} while (!raw_atomic64_try_cmpxchg(v, &c, dec));
include/linux/atomic/atomic-arch-fallback.h
471
raw_atomic_read_acquire(const atomic_t *v)
include/linux/atomic/atomic-arch-fallback.h
474
return arch_atomic_read_acquire(v);
include/linux/atomic/atomic-arch-fallback.h
479
ret = smp_load_acquire(&(v)->counter);
include/linux/atomic/atomic-arch-fallback.h
481
ret = raw_atomic_read(v);
include/linux/atomic/atomic-arch-fallback.h
501
raw_atomic_set(atomic_t *v, int i)
include/linux/atomic/atomic-arch-fallback.h
503
arch_atomic_set(v, i);
include/linux/atomic/atomic-arch-fallback.h
518
raw_atomic_set_release(atomic_t *v, int i)
include/linux/atomic/atomic-arch-fallback.h
521
arch_atomic_set_release(v, i);
include/linux/atomic/atomic-arch-fallback.h
524
smp_store_release(&(v)->counter, i);
include/linux/atomic/atomic-arch-fallback.h
527
raw_atomic_set(v, i);
include/linux/atomic/atomic-arch-fallback.h
544
raw_atomic_add(int i, atomic_t *v)
include/linux/atomic/atomic-arch-fallback.h
546
arch_atomic_add(i, v);
include/linux/atomic/atomic-arch-fallback.h
561
raw_atomic_add_return(int i, atomic_t *v)
include/linux/atomic/atomic-arch-fallback.h
564
return arch_atomic_add_return(i, v);
include/linux/atomic/atomic-arch-fallback.h
568
ret = arch_atomic_add_return_relaxed(i, v);
include/linux/atomic/atomic-arch-fallback.h
588
raw_atomic_add_return_acquire(int i, atomic_t *v)
include/linux/atomic/atomic-arch-fallback.h
591
return arch_atomic_add_return_acquire(i, v);
include/linux/atomic/atomic-arch-fallback.h
593
int ret = arch_atomic_add_return_relaxed(i, v);
include/linux/atomic/atomic-arch-fallback.h
597
return arch_atomic_add_return(i, v);
include/linux/atomic/atomic-arch-fallback.h
615
raw_atomic_add_return_release(int i, atomic_t *v)
include/linux/atomic/atomic-arch-fallback.h
618
return arch_atomic_add_return_release(i, v);
include/linux/atomic/atomic-arch-fallback.h
621
return arch_atomic_add_return_relaxed(i, v);
include/linux/atomic/atomic-arch-fallback.h
623
return arch_atomic_add_return(i, v);
include/linux/atomic/atomic-arch-fallback.h
641
raw_atomic_add_return_relaxed(int i, atomic_t *v)
include/linux/atomic/atomic-arch-fallback.h
644
return arch_atomic_add_return_relaxed(i, v);
include/linux/atomic/atomic-arch-fallback.h
646
return arch_atomic_add_return(i, v);
include/linux/atomic/atomic-arch-fallback.h
664
raw_atomic_fetch_add(int i, atomic_t *v)
include/linux/atomic/atomic-arch-fallback.h
667
return arch_atomic_fetch_add(i, v);
include/linux/atomic/atomic-arch-fallback.h
671
ret = arch_atomic_fetch_add_relaxed(i, v);
include/linux/atomic/atomic-arch-fallback.h
691
raw_atomic_fetch_add_acquire(int i, atomic_t *v)
include/linux/atomic/atomic-arch-fallback.h
694
return arch_atomic_fetch_add_acquire(i, v);
include/linux/atomic/atomic-arch-fallback.h
696
int ret = arch_atomic_fetch_add_relaxed(i, v);
include/linux/atomic/atomic-arch-fallback.h
700
return arch_atomic_fetch_add(i, v);
include/linux/atomic/atomic-arch-fallback.h
718
raw_atomic_fetch_add_release(int i, atomic_t *v)
include/linux/atomic/atomic-arch-fallback.h
721
return arch_atomic_fetch_add_release(i, v);
include/linux/atomic/atomic-arch-fallback.h
724
return arch_atomic_fetch_add_relaxed(i, v);
include/linux/atomic/atomic-arch-fallback.h
726
return arch_atomic_fetch_add(i, v);
include/linux/atomic/atomic-arch-fallback.h
744
raw_atomic_fetch_add_relaxed(int i, atomic_t *v)
include/linux/atomic/atomic-arch-fallback.h
747
return arch_atomic_fetch_add_relaxed(i, v);
include/linux/atomic/atomic-arch-fallback.h
749
return arch_atomic_fetch_add(i, v);
include/linux/atomic/atomic-arch-fallback.h
767
raw_atomic_sub(int i, atomic_t *v)
include/linux/atomic/atomic-arch-fallback.h
769
arch_atomic_sub(i, v);
include/linux/atomic/atomic-arch-fallback.h
784
raw_atomic_sub_return(int i, atomic_t *v)
include/linux/atomic/atomic-arch-fallback.h
787
return arch_atomic_sub_return(i, v);
include/linux/atomic/atomic-arch-fallback.h
791
ret = arch_atomic_sub_return_relaxed(i, v);
include/linux/atomic/atomic-arch-fallback.h
811
raw_atomic_sub_return_acquire(int i, atomic_t *v)
include/linux/atomic/atomic-arch-fallback.h
814
return arch_atomic_sub_return_acquire(i, v);
include/linux/atomic/atomic-arch-fallback.h
816
int ret = arch_atomic_sub_return_relaxed(i, v);
include/linux/atomic/atomic-arch-fallback.h
820
return arch_atomic_sub_return(i, v);
include/linux/atomic/atomic-arch-fallback.h
838
raw_atomic_sub_return_release(int i, atomic_t *v)
include/linux/atomic/atomic-arch-fallback.h
841
return arch_atomic_sub_return_release(i, v);
include/linux/atomic/atomic-arch-fallback.h
844
return arch_atomic_sub_return_relaxed(i, v);
include/linux/atomic/atomic-arch-fallback.h
846
return arch_atomic_sub_return(i, v);
include/linux/atomic/atomic-arch-fallback.h
864
raw_atomic_sub_return_relaxed(int i, atomic_t *v)
include/linux/atomic/atomic-arch-fallback.h
867
return arch_atomic_sub_return_relaxed(i, v);
include/linux/atomic/atomic-arch-fallback.h
869
return arch_atomic_sub_return(i, v);
include/linux/atomic/atomic-arch-fallback.h
887
raw_atomic_fetch_sub(int i, atomic_t *v)
include/linux/atomic/atomic-arch-fallback.h
890
return arch_atomic_fetch_sub(i, v);
include/linux/atomic/atomic-arch-fallback.h
894
ret = arch_atomic_fetch_sub_relaxed(i, v);
include/linux/atomic/atomic-arch-fallback.h
914
raw_atomic_fetch_sub_acquire(int i, atomic_t *v)
include/linux/atomic/atomic-arch-fallback.h
917
return arch_atomic_fetch_sub_acquire(i, v);
include/linux/atomic/atomic-arch-fallback.h
919
int ret = arch_atomic_fetch_sub_relaxed(i, v);
include/linux/atomic/atomic-arch-fallback.h
923
return arch_atomic_fetch_sub(i, v);
include/linux/atomic/atomic-arch-fallback.h
941
raw_atomic_fetch_sub_release(int i, atomic_t *v)
include/linux/atomic/atomic-arch-fallback.h
944
return arch_atomic_fetch_sub_release(i, v);
include/linux/atomic/atomic-arch-fallback.h
947
return arch_atomic_fetch_sub_relaxed(i, v);
include/linux/atomic/atomic-arch-fallback.h
949
return arch_atomic_fetch_sub(i, v);
include/linux/atomic/atomic-arch-fallback.h
967
raw_atomic_fetch_sub_relaxed(int i, atomic_t *v)
include/linux/atomic/atomic-arch-fallback.h
970
return arch_atomic_fetch_sub_relaxed(i, v);
include/linux/atomic/atomic-arch-fallback.h
972
return arch_atomic_fetch_sub(i, v);
include/linux/atomic/atomic-arch-fallback.h
989
raw_atomic_inc(atomic_t *v)
include/linux/atomic/atomic-arch-fallback.h
992
arch_atomic_inc(v);
include/linux/atomic/atomic-arch-fallback.h
994
raw_atomic_add(1, v);
include/linux/atomic/atomic-instrumented.h
1006
atomic_fetch_or_relaxed(int i, atomic_t *v)
include/linux/atomic/atomic-instrumented.h
1008
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
1009
return raw_atomic_fetch_or_relaxed(i, v);
include/linux/atomic/atomic-instrumented.h
102
atomic_add(int i, atomic_t *v)
include/linux/atomic/atomic-instrumented.h
1024
atomic_xor(int i, atomic_t *v)
include/linux/atomic/atomic-instrumented.h
1026
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
1027
raw_atomic_xor(i, v);
include/linux/atomic/atomic-instrumented.h
104
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
1042
atomic_fetch_xor(int i, atomic_t *v)
include/linux/atomic/atomic-instrumented.h
1045
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
1046
return raw_atomic_fetch_xor(i, v);
include/linux/atomic/atomic-instrumented.h
105
raw_atomic_add(i, v);
include/linux/atomic/atomic-instrumented.h
1061
atomic_fetch_xor_acquire(int i, atomic_t *v)
include/linux/atomic/atomic-instrumented.h
1063
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
1064
return raw_atomic_fetch_xor_acquire(i, v);
include/linux/atomic/atomic-instrumented.h
1079
atomic_fetch_xor_release(int i, atomic_t *v)
include/linux/atomic/atomic-instrumented.h
1082
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
1083
return raw_atomic_fetch_xor_release(i, v);
include/linux/atomic/atomic-instrumented.h
1098
atomic_fetch_xor_relaxed(int i, atomic_t *v)
include/linux/atomic/atomic-instrumented.h
1100
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
1101
return raw_atomic_fetch_xor_relaxed(i, v);
include/linux/atomic/atomic-instrumented.h
1116
atomic_xchg(atomic_t *v, int new)
include/linux/atomic/atomic-instrumented.h
1119
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
1120
return raw_atomic_xchg(v, new);
include/linux/atomic/atomic-instrumented.h
1135
atomic_xchg_acquire(atomic_t *v, int new)
include/linux/atomic/atomic-instrumented.h
1137
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
1138
return raw_atomic_xchg_acquire(v, new);
include/linux/atomic/atomic-instrumented.h
1153
atomic_xchg_release(atomic_t *v, int new)
include/linux/atomic/atomic-instrumented.h
1156
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
1157
return raw_atomic_xchg_release(v, new);
include/linux/atomic/atomic-instrumented.h
1172
atomic_xchg_relaxed(atomic_t *v, int new)
include/linux/atomic/atomic-instrumented.h
1174
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
1175
return raw_atomic_xchg_relaxed(v, new);
include/linux/atomic/atomic-instrumented.h
1192
atomic_cmpxchg(atomic_t *v, int old, int new)
include/linux/atomic/atomic-instrumented.h
1195
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
1196
return raw_atomic_cmpxchg(v, old, new);
include/linux/atomic/atomic-instrumented.h
120
atomic_add_return(int i, atomic_t *v)
include/linux/atomic/atomic-instrumented.h
1213
atomic_cmpxchg_acquire(atomic_t *v, int old, int new)
include/linux/atomic/atomic-instrumented.h
1215
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
1216
return raw_atomic_cmpxchg_acquire(v, old, new);
include/linux/atomic/atomic-instrumented.h
123
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
1233
atomic_cmpxchg_release(atomic_t *v, int old, int new)
include/linux/atomic/atomic-instrumented.h
1236
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
1237
return raw_atomic_cmpxchg_release(v, old, new);
include/linux/atomic/atomic-instrumented.h
124
return raw_atomic_add_return(i, v);
include/linux/atomic/atomic-instrumented.h
1254
atomic_cmpxchg_relaxed(atomic_t *v, int old, int new)
include/linux/atomic/atomic-instrumented.h
1256
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
1257
return raw_atomic_cmpxchg_relaxed(v, old, new);
include/linux/atomic/atomic-instrumented.h
1275
atomic_try_cmpxchg(atomic_t *v, int *old, int new)
include/linux/atomic/atomic-instrumented.h
1278
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
1280
return raw_atomic_try_cmpxchg(v, old, new);
include/linux/atomic/atomic-instrumented.h
1298
atomic_try_cmpxchg_acquire(atomic_t *v, int *old, int new)
include/linux/atomic/atomic-instrumented.h
1300
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
1302
return raw_atomic_try_cmpxchg_acquire(v, old, new);
include/linux/atomic/atomic-instrumented.h
1320
atomic_try_cmpxchg_release(atomic_t *v, int *old, int new)
include/linux/atomic/atomic-instrumented.h
1323
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
1325
return raw_atomic_try_cmpxchg_release(v, old, new);
include/linux/atomic/atomic-instrumented.h
1343
atomic_try_cmpxchg_relaxed(atomic_t *v, int *old, int new)
include/linux/atomic/atomic-instrumented.h
1345
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
1347
return raw_atomic_try_cmpxchg_relaxed(v, old, new);
include/linux/atomic/atomic-instrumented.h
1362
atomic_sub_and_test(int i, atomic_t *v)
include/linux/atomic/atomic-instrumented.h
1365
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
1366
return raw_atomic_sub_and_test(i, v);
include/linux/atomic/atomic-instrumented.h
1380
atomic_dec_and_test(atomic_t *v)
include/linux/atomic/atomic-instrumented.h
1383
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
1384
return raw_atomic_dec_and_test(v);
include/linux/atomic/atomic-instrumented.h
139
atomic_add_return_acquire(int i, atomic_t *v)
include/linux/atomic/atomic-instrumented.h
1398
atomic_inc_and_test(atomic_t *v)
include/linux/atomic/atomic-instrumented.h
1401
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
1402
return raw_atomic_inc_and_test(v);
include/linux/atomic/atomic-instrumented.h
141
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
1417
atomic_add_negative(int i, atomic_t *v)
include/linux/atomic/atomic-instrumented.h
142
return raw_atomic_add_return_acquire(i, v);
include/linux/atomic/atomic-instrumented.h
1420
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
1421
return raw_atomic_add_negative(i, v);
include/linux/atomic/atomic-instrumented.h
1436
atomic_add_negative_acquire(int i, atomic_t *v)
include/linux/atomic/atomic-instrumented.h
1438
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
1439
return raw_atomic_add_negative_acquire(i, v);
include/linux/atomic/atomic-instrumented.h
1454
atomic_add_negative_release(int i, atomic_t *v)
include/linux/atomic/atomic-instrumented.h
1457
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
1458
return raw_atomic_add_negative_release(i, v);
include/linux/atomic/atomic-instrumented.h
1473
atomic_add_negative_relaxed(int i, atomic_t *v)
include/linux/atomic/atomic-instrumented.h
1475
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
1476
return raw_atomic_add_negative_relaxed(i, v);
include/linux/atomic/atomic-instrumented.h
1493
atomic_fetch_add_unless(atomic_t *v, int a, int u)
include/linux/atomic/atomic-instrumented.h
1496
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
1497
return raw_atomic_fetch_add_unless(v, a, u);
include/linux/atomic/atomic-instrumented.h
1514
atomic_add_unless(atomic_t *v, int a, int u)
include/linux/atomic/atomic-instrumented.h
1517
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
1518
return raw_atomic_add_unless(v, a, u);
include/linux/atomic/atomic-instrumented.h
1533
atomic_inc_not_zero(atomic_t *v)
include/linux/atomic/atomic-instrumented.h
1536
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
1537
return raw_atomic_inc_not_zero(v);
include/linux/atomic/atomic-instrumented.h
1552
atomic_inc_unless_negative(atomic_t *v)
include/linux/atomic/atomic-instrumented.h
1555
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
1556
return raw_atomic_inc_unless_negative(v);
include/linux/atomic/atomic-instrumented.h
157
atomic_add_return_release(int i, atomic_t *v)
include/linux/atomic/atomic-instrumented.h
1571
atomic_dec_unless_positive(atomic_t *v)
include/linux/atomic/atomic-instrumented.h
1574
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
1575
return raw_atomic_dec_unless_positive(v);
include/linux/atomic/atomic-instrumented.h
1590
atomic_dec_if_positive(atomic_t *v)
include/linux/atomic/atomic-instrumented.h
1593
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
1594
return raw_atomic_dec_if_positive(v);
include/linux/atomic/atomic-instrumented.h
160
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
1608
atomic64_read(const atomic64_t *v)
include/linux/atomic/atomic-instrumented.h
161
return raw_atomic_add_return_release(i, v);
include/linux/atomic/atomic-instrumented.h
1610
instrument_atomic_read(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
1611
return raw_atomic64_read(v);
include/linux/atomic/atomic-instrumented.h
1625
atomic64_read_acquire(const atomic64_t *v)
include/linux/atomic/atomic-instrumented.h
1627
instrument_atomic_read(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
1628
return raw_atomic64_read_acquire(v);
include/linux/atomic/atomic-instrumented.h
1643
atomic64_set(atomic64_t *v, s64 i)
include/linux/atomic/atomic-instrumented.h
1645
instrument_atomic_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
1646
raw_atomic64_set(v, i);
include/linux/atomic/atomic-instrumented.h
1661
atomic64_set_release(atomic64_t *v, s64 i)
include/linux/atomic/atomic-instrumented.h
1664
instrument_atomic_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
1665
raw_atomic64_set_release(v, i);
include/linux/atomic/atomic-instrumented.h
1680
atomic64_add(s64 i, atomic64_t *v)
include/linux/atomic/atomic-instrumented.h
1682
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
1683
raw_atomic64_add(i, v);
include/linux/atomic/atomic-instrumented.h
1698
atomic64_add_return(s64 i, atomic64_t *v)
include/linux/atomic/atomic-instrumented.h
1701
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
1702
return raw_atomic64_add_return(i, v);
include/linux/atomic/atomic-instrumented.h
1717
atomic64_add_return_acquire(s64 i, atomic64_t *v)
include/linux/atomic/atomic-instrumented.h
1719
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
1720
return raw_atomic64_add_return_acquire(i, v);
include/linux/atomic/atomic-instrumented.h
1735
atomic64_add_return_release(s64 i, atomic64_t *v)
include/linux/atomic/atomic-instrumented.h
1738
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
1739
return raw_atomic64_add_return_release(i, v);
include/linux/atomic/atomic-instrumented.h
1754
atomic64_add_return_relaxed(s64 i, atomic64_t *v)
include/linux/atomic/atomic-instrumented.h
1756
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
1757
return raw_atomic64_add_return_relaxed(i, v);
include/linux/atomic/atomic-instrumented.h
176
atomic_add_return_relaxed(int i, atomic_t *v)
include/linux/atomic/atomic-instrumented.h
1772
atomic64_fetch_add(s64 i, atomic64_t *v)
include/linux/atomic/atomic-instrumented.h
1775
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
1776
return raw_atomic64_fetch_add(i, v);
include/linux/atomic/atomic-instrumented.h
178
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
179
return raw_atomic_add_return_relaxed(i, v);
include/linux/atomic/atomic-instrumented.h
1791
atomic64_fetch_add_acquire(s64 i, atomic64_t *v)
include/linux/atomic/atomic-instrumented.h
1793
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
1794
return raw_atomic64_fetch_add_acquire(i, v);
include/linux/atomic/atomic-instrumented.h
1809
atomic64_fetch_add_release(s64 i, atomic64_t *v)
include/linux/atomic/atomic-instrumented.h
1812
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
1813
return raw_atomic64_fetch_add_release(i, v);
include/linux/atomic/atomic-instrumented.h
1828
atomic64_fetch_add_relaxed(s64 i, atomic64_t *v)
include/linux/atomic/atomic-instrumented.h
1830
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
1831
return raw_atomic64_fetch_add_relaxed(i, v);
include/linux/atomic/atomic-instrumented.h
1846
atomic64_sub(s64 i, atomic64_t *v)
include/linux/atomic/atomic-instrumented.h
1848
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
1849
raw_atomic64_sub(i, v);
include/linux/atomic/atomic-instrumented.h
1864
atomic64_sub_return(s64 i, atomic64_t *v)
include/linux/atomic/atomic-instrumented.h
1867
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
1868
return raw_atomic64_sub_return(i, v);
include/linux/atomic/atomic-instrumented.h
1883
atomic64_sub_return_acquire(s64 i, atomic64_t *v)
include/linux/atomic/atomic-instrumented.h
1885
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
1886
return raw_atomic64_sub_return_acquire(i, v);
include/linux/atomic/atomic-instrumented.h
1901
atomic64_sub_return_release(s64 i, atomic64_t *v)
include/linux/atomic/atomic-instrumented.h
1904
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
1905
return raw_atomic64_sub_return_release(i, v);
include/linux/atomic/atomic-instrumented.h
1920
atomic64_sub_return_relaxed(s64 i, atomic64_t *v)
include/linux/atomic/atomic-instrumented.h
1922
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
1923
return raw_atomic64_sub_return_relaxed(i, v);
include/linux/atomic/atomic-instrumented.h
1938
atomic64_fetch_sub(s64 i, atomic64_t *v)
include/linux/atomic/atomic-instrumented.h
194
atomic_fetch_add(int i, atomic_t *v)
include/linux/atomic/atomic-instrumented.h
1941
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
1942
return raw_atomic64_fetch_sub(i, v);
include/linux/atomic/atomic-instrumented.h
1957
atomic64_fetch_sub_acquire(s64 i, atomic64_t *v)
include/linux/atomic/atomic-instrumented.h
1959
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
1960
return raw_atomic64_fetch_sub_acquire(i, v);
include/linux/atomic/atomic-instrumented.h
197
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
1975
atomic64_fetch_sub_release(s64 i, atomic64_t *v)
include/linux/atomic/atomic-instrumented.h
1978
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
1979
return raw_atomic64_fetch_sub_release(i, v);
include/linux/atomic/atomic-instrumented.h
198
return raw_atomic_fetch_add(i, v);
include/linux/atomic/atomic-instrumented.h
1994
atomic64_fetch_sub_relaxed(s64 i, atomic64_t *v)
include/linux/atomic/atomic-instrumented.h
1996
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
1997
return raw_atomic64_fetch_sub_relaxed(i, v);
include/linux/atomic/atomic-instrumented.h
2011
atomic64_inc(atomic64_t *v)
include/linux/atomic/atomic-instrumented.h
2013
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
2014
raw_atomic64_inc(v);
include/linux/atomic/atomic-instrumented.h
2028
atomic64_inc_return(atomic64_t *v)
include/linux/atomic/atomic-instrumented.h
2031
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
2032
return raw_atomic64_inc_return(v);
include/linux/atomic/atomic-instrumented.h
2046
atomic64_inc_return_acquire(atomic64_t *v)
include/linux/atomic/atomic-instrumented.h
2048
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
2049
return raw_atomic64_inc_return_acquire(v);
include/linux/atomic/atomic-instrumented.h
2063
atomic64_inc_return_release(atomic64_t *v)
include/linux/atomic/atomic-instrumented.h
2066
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
2067
return raw_atomic64_inc_return_release(v);
include/linux/atomic/atomic-instrumented.h
2081
atomic64_inc_return_relaxed(atomic64_t *v)
include/linux/atomic/atomic-instrumented.h
2083
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
2084
return raw_atomic64_inc_return_relaxed(v);
include/linux/atomic/atomic-instrumented.h
2098
atomic64_fetch_inc(atomic64_t *v)
include/linux/atomic/atomic-instrumented.h
2101
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
2102
return raw_atomic64_fetch_inc(v);
include/linux/atomic/atomic-instrumented.h
2116
atomic64_fetch_inc_acquire(atomic64_t *v)
include/linux/atomic/atomic-instrumented.h
2118
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
2119
return raw_atomic64_fetch_inc_acquire(v);
include/linux/atomic/atomic-instrumented.h
213
atomic_fetch_add_acquire(int i, atomic_t *v)
include/linux/atomic/atomic-instrumented.h
2133
atomic64_fetch_inc_release(atomic64_t *v)
include/linux/atomic/atomic-instrumented.h
2136
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
2137
return raw_atomic64_fetch_inc_release(v);
include/linux/atomic/atomic-instrumented.h
215
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
2151
atomic64_fetch_inc_relaxed(atomic64_t *v)
include/linux/atomic/atomic-instrumented.h
2153
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
2154
return raw_atomic64_fetch_inc_relaxed(v);
include/linux/atomic/atomic-instrumented.h
216
return raw_atomic_fetch_add_acquire(i, v);
include/linux/atomic/atomic-instrumented.h
2168
atomic64_dec(atomic64_t *v)
include/linux/atomic/atomic-instrumented.h
2170
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
2171
raw_atomic64_dec(v);
include/linux/atomic/atomic-instrumented.h
2185
atomic64_dec_return(atomic64_t *v)
include/linux/atomic/atomic-instrumented.h
2188
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
2189
return raw_atomic64_dec_return(v);
include/linux/atomic/atomic-instrumented.h
2203
atomic64_dec_return_acquire(atomic64_t *v)
include/linux/atomic/atomic-instrumented.h
2205
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
2206
return raw_atomic64_dec_return_acquire(v);
include/linux/atomic/atomic-instrumented.h
2220
atomic64_dec_return_release(atomic64_t *v)
include/linux/atomic/atomic-instrumented.h
2223
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
2224
return raw_atomic64_dec_return_release(v);
include/linux/atomic/atomic-instrumented.h
2238
atomic64_dec_return_relaxed(atomic64_t *v)
include/linux/atomic/atomic-instrumented.h
2240
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
2241
return raw_atomic64_dec_return_relaxed(v);
include/linux/atomic/atomic-instrumented.h
2255
atomic64_fetch_dec(atomic64_t *v)
include/linux/atomic/atomic-instrumented.h
2258
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
2259
return raw_atomic64_fetch_dec(v);
include/linux/atomic/atomic-instrumented.h
2273
atomic64_fetch_dec_acquire(atomic64_t *v)
include/linux/atomic/atomic-instrumented.h
2275
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
2276
return raw_atomic64_fetch_dec_acquire(v);
include/linux/atomic/atomic-instrumented.h
2290
atomic64_fetch_dec_release(atomic64_t *v)
include/linux/atomic/atomic-instrumented.h
2293
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
2294
return raw_atomic64_fetch_dec_release(v);
include/linux/atomic/atomic-instrumented.h
2308
atomic64_fetch_dec_relaxed(atomic64_t *v)
include/linux/atomic/atomic-instrumented.h
231
atomic_fetch_add_release(int i, atomic_t *v)
include/linux/atomic/atomic-instrumented.h
2310
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
2311
return raw_atomic64_fetch_dec_relaxed(v);
include/linux/atomic/atomic-instrumented.h
2326
atomic64_and(s64 i, atomic64_t *v)
include/linux/atomic/atomic-instrumented.h
2328
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
2329
raw_atomic64_and(i, v);
include/linux/atomic/atomic-instrumented.h
234
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
2344
atomic64_fetch_and(s64 i, atomic64_t *v)
include/linux/atomic/atomic-instrumented.h
2347
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
2348
return raw_atomic64_fetch_and(i, v);
include/linux/atomic/atomic-instrumented.h
235
return raw_atomic_fetch_add_release(i, v);
include/linux/atomic/atomic-instrumented.h
2363
atomic64_fetch_and_acquire(s64 i, atomic64_t *v)
include/linux/atomic/atomic-instrumented.h
2365
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
2366
return raw_atomic64_fetch_and_acquire(i, v);
include/linux/atomic/atomic-instrumented.h
2381
atomic64_fetch_and_release(s64 i, atomic64_t *v)
include/linux/atomic/atomic-instrumented.h
2384
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
2385
return raw_atomic64_fetch_and_release(i, v);
include/linux/atomic/atomic-instrumented.h
2400
atomic64_fetch_and_relaxed(s64 i, atomic64_t *v)
include/linux/atomic/atomic-instrumented.h
2402
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
2403
return raw_atomic64_fetch_and_relaxed(i, v);
include/linux/atomic/atomic-instrumented.h
2418
atomic64_andnot(s64 i, atomic64_t *v)
include/linux/atomic/atomic-instrumented.h
2420
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
2421
raw_atomic64_andnot(i, v);
include/linux/atomic/atomic-instrumented.h
2436
atomic64_fetch_andnot(s64 i, atomic64_t *v)
include/linux/atomic/atomic-instrumented.h
2439
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
2440
return raw_atomic64_fetch_andnot(i, v);
include/linux/atomic/atomic-instrumented.h
2455
atomic64_fetch_andnot_acquire(s64 i, atomic64_t *v)
include/linux/atomic/atomic-instrumented.h
2457
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
2458
return raw_atomic64_fetch_andnot_acquire(i, v);
include/linux/atomic/atomic-instrumented.h
2473
atomic64_fetch_andnot_release(s64 i, atomic64_t *v)
include/linux/atomic/atomic-instrumented.h
2476
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
2477
return raw_atomic64_fetch_andnot_release(i, v);
include/linux/atomic/atomic-instrumented.h
2492
atomic64_fetch_andnot_relaxed(s64 i, atomic64_t *v)
include/linux/atomic/atomic-instrumented.h
2494
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
2495
return raw_atomic64_fetch_andnot_relaxed(i, v);
include/linux/atomic/atomic-instrumented.h
250
atomic_fetch_add_relaxed(int i, atomic_t *v)
include/linux/atomic/atomic-instrumented.h
2510
atomic64_or(s64 i, atomic64_t *v)
include/linux/atomic/atomic-instrumented.h
2512
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
2513
raw_atomic64_or(i, v);
include/linux/atomic/atomic-instrumented.h
252
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
2528
atomic64_fetch_or(s64 i, atomic64_t *v)
include/linux/atomic/atomic-instrumented.h
253
return raw_atomic_fetch_add_relaxed(i, v);
include/linux/atomic/atomic-instrumented.h
2531
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
2532
return raw_atomic64_fetch_or(i, v);
include/linux/atomic/atomic-instrumented.h
2547
atomic64_fetch_or_acquire(s64 i, atomic64_t *v)
include/linux/atomic/atomic-instrumented.h
2549
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
2550
return raw_atomic64_fetch_or_acquire(i, v);
include/linux/atomic/atomic-instrumented.h
2565
atomic64_fetch_or_release(s64 i, atomic64_t *v)
include/linux/atomic/atomic-instrumented.h
2568
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
2569
return raw_atomic64_fetch_or_release(i, v);
include/linux/atomic/atomic-instrumented.h
2584
atomic64_fetch_or_relaxed(s64 i, atomic64_t *v)
include/linux/atomic/atomic-instrumented.h
2586
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
2587
return raw_atomic64_fetch_or_relaxed(i, v);
include/linux/atomic/atomic-instrumented.h
2602
atomic64_xor(s64 i, atomic64_t *v)
include/linux/atomic/atomic-instrumented.h
2604
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
2605
raw_atomic64_xor(i, v);
include/linux/atomic/atomic-instrumented.h
2620
atomic64_fetch_xor(s64 i, atomic64_t *v)
include/linux/atomic/atomic-instrumented.h
2623
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
2624
return raw_atomic64_fetch_xor(i, v);
include/linux/atomic/atomic-instrumented.h
2639
atomic64_fetch_xor_acquire(s64 i, atomic64_t *v)
include/linux/atomic/atomic-instrumented.h
2641
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
2642
return raw_atomic64_fetch_xor_acquire(i, v);
include/linux/atomic/atomic-instrumented.h
2657
atomic64_fetch_xor_release(s64 i, atomic64_t *v)
include/linux/atomic/atomic-instrumented.h
2660
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
2661
return raw_atomic64_fetch_xor_release(i, v);
include/linux/atomic/atomic-instrumented.h
2676
atomic64_fetch_xor_relaxed(s64 i, atomic64_t *v)
include/linux/atomic/atomic-instrumented.h
2678
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
2679
return raw_atomic64_fetch_xor_relaxed(i, v);
include/linux/atomic/atomic-instrumented.h
268
atomic_sub(int i, atomic_t *v)
include/linux/atomic/atomic-instrumented.h
2694
atomic64_xchg(atomic64_t *v, s64 new)
include/linux/atomic/atomic-instrumented.h
2697
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
2698
return raw_atomic64_xchg(v, new);
include/linux/atomic/atomic-instrumented.h
270
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
271
raw_atomic_sub(i, v);
include/linux/atomic/atomic-instrumented.h
2713
atomic64_xchg_acquire(atomic64_t *v, s64 new)
include/linux/atomic/atomic-instrumented.h
2715
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
2716
return raw_atomic64_xchg_acquire(v, new);
include/linux/atomic/atomic-instrumented.h
2731
atomic64_xchg_release(atomic64_t *v, s64 new)
include/linux/atomic/atomic-instrumented.h
2734
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
2735
return raw_atomic64_xchg_release(v, new);
include/linux/atomic/atomic-instrumented.h
2750
atomic64_xchg_relaxed(atomic64_t *v, s64 new)
include/linux/atomic/atomic-instrumented.h
2752
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
2753
return raw_atomic64_xchg_relaxed(v, new);
include/linux/atomic/atomic-instrumented.h
2770
atomic64_cmpxchg(atomic64_t *v, s64 old, s64 new)
include/linux/atomic/atomic-instrumented.h
2773
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
2774
return raw_atomic64_cmpxchg(v, old, new);
include/linux/atomic/atomic-instrumented.h
2791
atomic64_cmpxchg_acquire(atomic64_t *v, s64 old, s64 new)
include/linux/atomic/atomic-instrumented.h
2793
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
2794
return raw_atomic64_cmpxchg_acquire(v, old, new);
include/linux/atomic/atomic-instrumented.h
2811
atomic64_cmpxchg_release(atomic64_t *v, s64 old, s64 new)
include/linux/atomic/atomic-instrumented.h
2814
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
2815
return raw_atomic64_cmpxchg_release(v, old, new);
include/linux/atomic/atomic-instrumented.h
2832
atomic64_cmpxchg_relaxed(atomic64_t *v, s64 old, s64 new)
include/linux/atomic/atomic-instrumented.h
2834
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
2835
return raw_atomic64_cmpxchg_relaxed(v, old, new);
include/linux/atomic/atomic-instrumented.h
2853
atomic64_try_cmpxchg(atomic64_t *v, s64 *old, s64 new)
include/linux/atomic/atomic-instrumented.h
2856
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
2858
return raw_atomic64_try_cmpxchg(v, old, new);
include/linux/atomic/atomic-instrumented.h
286
atomic_sub_return(int i, atomic_t *v)
include/linux/atomic/atomic-instrumented.h
2876
atomic64_try_cmpxchg_acquire(atomic64_t *v, s64 *old, s64 new)
include/linux/atomic/atomic-instrumented.h
2878
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
2880
return raw_atomic64_try_cmpxchg_acquire(v, old, new);
include/linux/atomic/atomic-instrumented.h
289
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
2898
atomic64_try_cmpxchg_release(atomic64_t *v, s64 *old, s64 new)
include/linux/atomic/atomic-instrumented.h
290
return raw_atomic_sub_return(i, v);
include/linux/atomic/atomic-instrumented.h
2901
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
2903
return raw_atomic64_try_cmpxchg_release(v, old, new);
include/linux/atomic/atomic-instrumented.h
2921
atomic64_try_cmpxchg_relaxed(atomic64_t *v, s64 *old, s64 new)
include/linux/atomic/atomic-instrumented.h
2923
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
2925
return raw_atomic64_try_cmpxchg_relaxed(v, old, new);
include/linux/atomic/atomic-instrumented.h
2940
atomic64_sub_and_test(s64 i, atomic64_t *v)
include/linux/atomic/atomic-instrumented.h
2943
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
2944
return raw_atomic64_sub_and_test(i, v);
include/linux/atomic/atomic-instrumented.h
2958
atomic64_dec_and_test(atomic64_t *v)
include/linux/atomic/atomic-instrumented.h
2961
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
2962
return raw_atomic64_dec_and_test(v);
include/linux/atomic/atomic-instrumented.h
2976
atomic64_inc_and_test(atomic64_t *v)
include/linux/atomic/atomic-instrumented.h
2979
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
2980
return raw_atomic64_inc_and_test(v);
include/linux/atomic/atomic-instrumented.h
2995
atomic64_add_negative(s64 i, atomic64_t *v)
include/linux/atomic/atomic-instrumented.h
2998
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
2999
return raw_atomic64_add_negative(i, v);
include/linux/atomic/atomic-instrumented.h
30
atomic_read(const atomic_t *v)
include/linux/atomic/atomic-instrumented.h
3014
atomic64_add_negative_acquire(s64 i, atomic64_t *v)
include/linux/atomic/atomic-instrumented.h
3016
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
3017
return raw_atomic64_add_negative_acquire(i, v);
include/linux/atomic/atomic-instrumented.h
3032
atomic64_add_negative_release(s64 i, atomic64_t *v)
include/linux/atomic/atomic-instrumented.h
3035
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
3036
return raw_atomic64_add_negative_release(i, v);
include/linux/atomic/atomic-instrumented.h
305
atomic_sub_return_acquire(int i, atomic_t *v)
include/linux/atomic/atomic-instrumented.h
3051
atomic64_add_negative_relaxed(s64 i, atomic64_t *v)
include/linux/atomic/atomic-instrumented.h
3053
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
3054
return raw_atomic64_add_negative_relaxed(i, v);
include/linux/atomic/atomic-instrumented.h
307
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
3071
atomic64_fetch_add_unless(atomic64_t *v, s64 a, s64 u)
include/linux/atomic/atomic-instrumented.h
3074
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
3075
return raw_atomic64_fetch_add_unless(v, a, u);
include/linux/atomic/atomic-instrumented.h
308
return raw_atomic_sub_return_acquire(i, v);
include/linux/atomic/atomic-instrumented.h
3092
atomic64_add_unless(atomic64_t *v, s64 a, s64 u)
include/linux/atomic/atomic-instrumented.h
3095
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
3096
return raw_atomic64_add_unless(v, a, u);
include/linux/atomic/atomic-instrumented.h
3111
atomic64_inc_not_zero(atomic64_t *v)
include/linux/atomic/atomic-instrumented.h
3114
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
3115
return raw_atomic64_inc_not_zero(v);
include/linux/atomic/atomic-instrumented.h
3130
atomic64_inc_unless_negative(atomic64_t *v)
include/linux/atomic/atomic-instrumented.h
3133
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
3134
return raw_atomic64_inc_unless_negative(v);
include/linux/atomic/atomic-instrumented.h
3149
atomic64_dec_unless_positive(atomic64_t *v)
include/linux/atomic/atomic-instrumented.h
3152
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
3153
return raw_atomic64_dec_unless_positive(v);
include/linux/atomic/atomic-instrumented.h
3168
atomic64_dec_if_positive(atomic64_t *v)
include/linux/atomic/atomic-instrumented.h
3171
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
3172
return raw_atomic64_dec_if_positive(v);
include/linux/atomic/atomic-instrumented.h
3186
atomic_long_read(const atomic_long_t *v)
include/linux/atomic/atomic-instrumented.h
3188
instrument_atomic_read(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
3189
return raw_atomic_long_read(v);
include/linux/atomic/atomic-instrumented.h
32
instrument_atomic_read(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
3203
atomic_long_read_acquire(const atomic_long_t *v)
include/linux/atomic/atomic-instrumented.h
3205
instrument_atomic_read(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
3206
return raw_atomic_long_read_acquire(v);
include/linux/atomic/atomic-instrumented.h
3221
atomic_long_set(atomic_long_t *v, long i)
include/linux/atomic/atomic-instrumented.h
3223
instrument_atomic_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
3224
raw_atomic_long_set(v, i);
include/linux/atomic/atomic-instrumented.h
323
atomic_sub_return_release(int i, atomic_t *v)
include/linux/atomic/atomic-instrumented.h
3239
atomic_long_set_release(atomic_long_t *v, long i)
include/linux/atomic/atomic-instrumented.h
3242
instrument_atomic_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
3243
raw_atomic_long_set_release(v, i);
include/linux/atomic/atomic-instrumented.h
3258
atomic_long_add(long i, atomic_long_t *v)
include/linux/atomic/atomic-instrumented.h
326
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
3260
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
3261
raw_atomic_long_add(i, v);
include/linux/atomic/atomic-instrumented.h
327
return raw_atomic_sub_return_release(i, v);
include/linux/atomic/atomic-instrumented.h
3276
atomic_long_add_return(long i, atomic_long_t *v)
include/linux/atomic/atomic-instrumented.h
3279
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
3280
return raw_atomic_long_add_return(i, v);
include/linux/atomic/atomic-instrumented.h
3295
atomic_long_add_return_acquire(long i, atomic_long_t *v)
include/linux/atomic/atomic-instrumented.h
3297
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
3298
return raw_atomic_long_add_return_acquire(i, v);
include/linux/atomic/atomic-instrumented.h
33
return raw_atomic_read(v);
include/linux/atomic/atomic-instrumented.h
3313
atomic_long_add_return_release(long i, atomic_long_t *v)
include/linux/atomic/atomic-instrumented.h
3316
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
3317
return raw_atomic_long_add_return_release(i, v);
include/linux/atomic/atomic-instrumented.h
3332
atomic_long_add_return_relaxed(long i, atomic_long_t *v)
include/linux/atomic/atomic-instrumented.h
3334
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
3335
return raw_atomic_long_add_return_relaxed(i, v);
include/linux/atomic/atomic-instrumented.h
3350
atomic_long_fetch_add(long i, atomic_long_t *v)
include/linux/atomic/atomic-instrumented.h
3353
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
3354
return raw_atomic_long_fetch_add(i, v);
include/linux/atomic/atomic-instrumented.h
3369
atomic_long_fetch_add_acquire(long i, atomic_long_t *v)
include/linux/atomic/atomic-instrumented.h
3371
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
3372
return raw_atomic_long_fetch_add_acquire(i, v);
include/linux/atomic/atomic-instrumented.h
3387
atomic_long_fetch_add_release(long i, atomic_long_t *v)
include/linux/atomic/atomic-instrumented.h
3390
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
3391
return raw_atomic_long_fetch_add_release(i, v);
include/linux/atomic/atomic-instrumented.h
3406
atomic_long_fetch_add_relaxed(long i, atomic_long_t *v)
include/linux/atomic/atomic-instrumented.h
3408
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
3409
return raw_atomic_long_fetch_add_relaxed(i, v);
include/linux/atomic/atomic-instrumented.h
342
atomic_sub_return_relaxed(int i, atomic_t *v)
include/linux/atomic/atomic-instrumented.h
3424
atomic_long_sub(long i, atomic_long_t *v)
include/linux/atomic/atomic-instrumented.h
3426
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
3427
raw_atomic_long_sub(i, v);
include/linux/atomic/atomic-instrumented.h
344
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
3442
atomic_long_sub_return(long i, atomic_long_t *v)
include/linux/atomic/atomic-instrumented.h
3445
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
3446
return raw_atomic_long_sub_return(i, v);
include/linux/atomic/atomic-instrumented.h
345
return raw_atomic_sub_return_relaxed(i, v);
include/linux/atomic/atomic-instrumented.h
3461
atomic_long_sub_return_acquire(long i, atomic_long_t *v)
include/linux/atomic/atomic-instrumented.h
3463
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
3464
return raw_atomic_long_sub_return_acquire(i, v);
include/linux/atomic/atomic-instrumented.h
3479
atomic_long_sub_return_release(long i, atomic_long_t *v)
include/linux/atomic/atomic-instrumented.h
3482
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
3483
return raw_atomic_long_sub_return_release(i, v);
include/linux/atomic/atomic-instrumented.h
3498
atomic_long_sub_return_relaxed(long i, atomic_long_t *v)
include/linux/atomic/atomic-instrumented.h
3500
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
3501
return raw_atomic_long_sub_return_relaxed(i, v);
include/linux/atomic/atomic-instrumented.h
3516
atomic_long_fetch_sub(long i, atomic_long_t *v)
include/linux/atomic/atomic-instrumented.h
3519
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
3520
return raw_atomic_long_fetch_sub(i, v);
include/linux/atomic/atomic-instrumented.h
3535
atomic_long_fetch_sub_acquire(long i, atomic_long_t *v)
include/linux/atomic/atomic-instrumented.h
3537
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
3538
return raw_atomic_long_fetch_sub_acquire(i, v);
include/linux/atomic/atomic-instrumented.h
3553
atomic_long_fetch_sub_release(long i, atomic_long_t *v)
include/linux/atomic/atomic-instrumented.h
3556
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
3557
return raw_atomic_long_fetch_sub_release(i, v);
include/linux/atomic/atomic-instrumented.h
3572
atomic_long_fetch_sub_relaxed(long i, atomic_long_t *v)
include/linux/atomic/atomic-instrumented.h
3574
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
3575
return raw_atomic_long_fetch_sub_relaxed(i, v);
include/linux/atomic/atomic-instrumented.h
3589
atomic_long_inc(atomic_long_t *v)
include/linux/atomic/atomic-instrumented.h
3591
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
3592
raw_atomic_long_inc(v);
include/linux/atomic/atomic-instrumented.h
360
atomic_fetch_sub(int i, atomic_t *v)
include/linux/atomic/atomic-instrumented.h
3606
atomic_long_inc_return(atomic_long_t *v)
include/linux/atomic/atomic-instrumented.h
3609
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
3610
return raw_atomic_long_inc_return(v);
include/linux/atomic/atomic-instrumented.h
3624
atomic_long_inc_return_acquire(atomic_long_t *v)
include/linux/atomic/atomic-instrumented.h
3626
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
3627
return raw_atomic_long_inc_return_acquire(v);
include/linux/atomic/atomic-instrumented.h
363
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
364
return raw_atomic_fetch_sub(i, v);
include/linux/atomic/atomic-instrumented.h
3641
atomic_long_inc_return_release(atomic_long_t *v)
include/linux/atomic/atomic-instrumented.h
3644
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
3645
return raw_atomic_long_inc_return_release(v);
include/linux/atomic/atomic-instrumented.h
3659
atomic_long_inc_return_relaxed(atomic_long_t *v)
include/linux/atomic/atomic-instrumented.h
3661
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
3662
return raw_atomic_long_inc_return_relaxed(v);
include/linux/atomic/atomic-instrumented.h
3676
atomic_long_fetch_inc(atomic_long_t *v)
include/linux/atomic/atomic-instrumented.h
3679
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
3680
return raw_atomic_long_fetch_inc(v);
include/linux/atomic/atomic-instrumented.h
3694
atomic_long_fetch_inc_acquire(atomic_long_t *v)
include/linux/atomic/atomic-instrumented.h
3696
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
3697
return raw_atomic_long_fetch_inc_acquire(v);
include/linux/atomic/atomic-instrumented.h
3711
atomic_long_fetch_inc_release(atomic_long_t *v)
include/linux/atomic/atomic-instrumented.h
3714
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
3715
return raw_atomic_long_fetch_inc_release(v);
include/linux/atomic/atomic-instrumented.h
3729
atomic_long_fetch_inc_relaxed(atomic_long_t *v)
include/linux/atomic/atomic-instrumented.h
3731
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
3732
return raw_atomic_long_fetch_inc_relaxed(v);
include/linux/atomic/atomic-instrumented.h
3746
atomic_long_dec(atomic_long_t *v)
include/linux/atomic/atomic-instrumented.h
3748
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
3749
raw_atomic_long_dec(v);
include/linux/atomic/atomic-instrumented.h
3763
atomic_long_dec_return(atomic_long_t *v)
include/linux/atomic/atomic-instrumented.h
3766
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
3767
return raw_atomic_long_dec_return(v);
include/linux/atomic/atomic-instrumented.h
3781
atomic_long_dec_return_acquire(atomic_long_t *v)
include/linux/atomic/atomic-instrumented.h
3783
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
3784
return raw_atomic_long_dec_return_acquire(v);
include/linux/atomic/atomic-instrumented.h
379
atomic_fetch_sub_acquire(int i, atomic_t *v)
include/linux/atomic/atomic-instrumented.h
3798
atomic_long_dec_return_release(atomic_long_t *v)
include/linux/atomic/atomic-instrumented.h
3801
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
3802
return raw_atomic_long_dec_return_release(v);
include/linux/atomic/atomic-instrumented.h
381
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
3816
atomic_long_dec_return_relaxed(atomic_long_t *v)
include/linux/atomic/atomic-instrumented.h
3818
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
3819
return raw_atomic_long_dec_return_relaxed(v);
include/linux/atomic/atomic-instrumented.h
382
return raw_atomic_fetch_sub_acquire(i, v);
include/linux/atomic/atomic-instrumented.h
3833
atomic_long_fetch_dec(atomic_long_t *v)
include/linux/atomic/atomic-instrumented.h
3836
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
3837
return raw_atomic_long_fetch_dec(v);
include/linux/atomic/atomic-instrumented.h
3851
atomic_long_fetch_dec_acquire(atomic_long_t *v)
include/linux/atomic/atomic-instrumented.h
3853
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
3854
return raw_atomic_long_fetch_dec_acquire(v);
include/linux/atomic/atomic-instrumented.h
3868
atomic_long_fetch_dec_release(atomic_long_t *v)
include/linux/atomic/atomic-instrumented.h
3871
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
3872
return raw_atomic_long_fetch_dec_release(v);
include/linux/atomic/atomic-instrumented.h
3886
atomic_long_fetch_dec_relaxed(atomic_long_t *v)
include/linux/atomic/atomic-instrumented.h
3888
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
3889
return raw_atomic_long_fetch_dec_relaxed(v);
include/linux/atomic/atomic-instrumented.h
3904
atomic_long_and(long i, atomic_long_t *v)
include/linux/atomic/atomic-instrumented.h
3906
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
3907
raw_atomic_long_and(i, v);
include/linux/atomic/atomic-instrumented.h
3922
atomic_long_fetch_and(long i, atomic_long_t *v)
include/linux/atomic/atomic-instrumented.h
3925
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
3926
return raw_atomic_long_fetch_and(i, v);
include/linux/atomic/atomic-instrumented.h
3941
atomic_long_fetch_and_acquire(long i, atomic_long_t *v)
include/linux/atomic/atomic-instrumented.h
3943
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
3944
return raw_atomic_long_fetch_and_acquire(i, v);
include/linux/atomic/atomic-instrumented.h
3959
atomic_long_fetch_and_release(long i, atomic_long_t *v)
include/linux/atomic/atomic-instrumented.h
3962
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
3963
return raw_atomic_long_fetch_and_release(i, v);
include/linux/atomic/atomic-instrumented.h
397
atomic_fetch_sub_release(int i, atomic_t *v)
include/linux/atomic/atomic-instrumented.h
3978
atomic_long_fetch_and_relaxed(long i, atomic_long_t *v)
include/linux/atomic/atomic-instrumented.h
3980
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
3981
return raw_atomic_long_fetch_and_relaxed(i, v);
include/linux/atomic/atomic-instrumented.h
3996
atomic_long_andnot(long i, atomic_long_t *v)
include/linux/atomic/atomic-instrumented.h
3998
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
3999
raw_atomic_long_andnot(i, v);
include/linux/atomic/atomic-instrumented.h
400
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
401
return raw_atomic_fetch_sub_release(i, v);
include/linux/atomic/atomic-instrumented.h
4014
atomic_long_fetch_andnot(long i, atomic_long_t *v)
include/linux/atomic/atomic-instrumented.h
4017
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
4018
return raw_atomic_long_fetch_andnot(i, v);
include/linux/atomic/atomic-instrumented.h
4033
atomic_long_fetch_andnot_acquire(long i, atomic_long_t *v)
include/linux/atomic/atomic-instrumented.h
4035
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
4036
return raw_atomic_long_fetch_andnot_acquire(i, v);
include/linux/atomic/atomic-instrumented.h
4051
atomic_long_fetch_andnot_release(long i, atomic_long_t *v)
include/linux/atomic/atomic-instrumented.h
4054
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
4055
return raw_atomic_long_fetch_andnot_release(i, v);
include/linux/atomic/atomic-instrumented.h
4070
atomic_long_fetch_andnot_relaxed(long i, atomic_long_t *v)
include/linux/atomic/atomic-instrumented.h
4072
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
4073
return raw_atomic_long_fetch_andnot_relaxed(i, v);
include/linux/atomic/atomic-instrumented.h
4088
atomic_long_or(long i, atomic_long_t *v)
include/linux/atomic/atomic-instrumented.h
4090
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
4091
raw_atomic_long_or(i, v);
include/linux/atomic/atomic-instrumented.h
4106
atomic_long_fetch_or(long i, atomic_long_t *v)
include/linux/atomic/atomic-instrumented.h
4109
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
4110
return raw_atomic_long_fetch_or(i, v);
include/linux/atomic/atomic-instrumented.h
4125
atomic_long_fetch_or_acquire(long i, atomic_long_t *v)
include/linux/atomic/atomic-instrumented.h
4127
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
4128
return raw_atomic_long_fetch_or_acquire(i, v);
include/linux/atomic/atomic-instrumented.h
4143
atomic_long_fetch_or_release(long i, atomic_long_t *v)
include/linux/atomic/atomic-instrumented.h
4146
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
4147
return raw_atomic_long_fetch_or_release(i, v);
include/linux/atomic/atomic-instrumented.h
416
atomic_fetch_sub_relaxed(int i, atomic_t *v)
include/linux/atomic/atomic-instrumented.h
4162
atomic_long_fetch_or_relaxed(long i, atomic_long_t *v)
include/linux/atomic/atomic-instrumented.h
4164
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
4165
return raw_atomic_long_fetch_or_relaxed(i, v);
include/linux/atomic/atomic-instrumented.h
418
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
4180
atomic_long_xor(long i, atomic_long_t *v)
include/linux/atomic/atomic-instrumented.h
4182
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
4183
raw_atomic_long_xor(i, v);
include/linux/atomic/atomic-instrumented.h
419
return raw_atomic_fetch_sub_relaxed(i, v);
include/linux/atomic/atomic-instrumented.h
4198
atomic_long_fetch_xor(long i, atomic_long_t *v)
include/linux/atomic/atomic-instrumented.h
4201
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
4202
return raw_atomic_long_fetch_xor(i, v);
include/linux/atomic/atomic-instrumented.h
4217
atomic_long_fetch_xor_acquire(long i, atomic_long_t *v)
include/linux/atomic/atomic-instrumented.h
4219
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
4220
return raw_atomic_long_fetch_xor_acquire(i, v);
include/linux/atomic/atomic-instrumented.h
4235
atomic_long_fetch_xor_release(long i, atomic_long_t *v)
include/linux/atomic/atomic-instrumented.h
4238
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
4239
return raw_atomic_long_fetch_xor_release(i, v);
include/linux/atomic/atomic-instrumented.h
4254
atomic_long_fetch_xor_relaxed(long i, atomic_long_t *v)
include/linux/atomic/atomic-instrumented.h
4256
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
4257
return raw_atomic_long_fetch_xor_relaxed(i, v);
include/linux/atomic/atomic-instrumented.h
4272
atomic_long_xchg(atomic_long_t *v, long new)
include/linux/atomic/atomic-instrumented.h
4275
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
4276
return raw_atomic_long_xchg(v, new);
include/linux/atomic/atomic-instrumented.h
4291
atomic_long_xchg_acquire(atomic_long_t *v, long new)
include/linux/atomic/atomic-instrumented.h
4293
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
4294
return raw_atomic_long_xchg_acquire(v, new);
include/linux/atomic/atomic-instrumented.h
4309
atomic_long_xchg_release(atomic_long_t *v, long new)
include/linux/atomic/atomic-instrumented.h
4312
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
4313
return raw_atomic_long_xchg_release(v, new);
include/linux/atomic/atomic-instrumented.h
4328
atomic_long_xchg_relaxed(atomic_long_t *v, long new)
include/linux/atomic/atomic-instrumented.h
433
atomic_inc(atomic_t *v)
include/linux/atomic/atomic-instrumented.h
4330
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
4331
return raw_atomic_long_xchg_relaxed(v, new);
include/linux/atomic/atomic-instrumented.h
4348
atomic_long_cmpxchg(atomic_long_t *v, long old, long new)
include/linux/atomic/atomic-instrumented.h
435
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
4351
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
4352
return raw_atomic_long_cmpxchg(v, old, new);
include/linux/atomic/atomic-instrumented.h
436
raw_atomic_inc(v);
include/linux/atomic/atomic-instrumented.h
4369
atomic_long_cmpxchg_acquire(atomic_long_t *v, long old, long new)
include/linux/atomic/atomic-instrumented.h
4371
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
4372
return raw_atomic_long_cmpxchg_acquire(v, old, new);
include/linux/atomic/atomic-instrumented.h
4389
atomic_long_cmpxchg_release(atomic_long_t *v, long old, long new)
include/linux/atomic/atomic-instrumented.h
4392
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
4393
return raw_atomic_long_cmpxchg_release(v, old, new);
include/linux/atomic/atomic-instrumented.h
4410
atomic_long_cmpxchg_relaxed(atomic_long_t *v, long old, long new)
include/linux/atomic/atomic-instrumented.h
4412
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
4413
return raw_atomic_long_cmpxchg_relaxed(v, old, new);
include/linux/atomic/atomic-instrumented.h
4431
atomic_long_try_cmpxchg(atomic_long_t *v, long *old, long new)
include/linux/atomic/atomic-instrumented.h
4434
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
4436
return raw_atomic_long_try_cmpxchg(v, old, new);
include/linux/atomic/atomic-instrumented.h
4454
atomic_long_try_cmpxchg_acquire(atomic_long_t *v, long *old, long new)
include/linux/atomic/atomic-instrumented.h
4456
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
4458
return raw_atomic_long_try_cmpxchg_acquire(v, old, new);
include/linux/atomic/atomic-instrumented.h
4476
atomic_long_try_cmpxchg_release(atomic_long_t *v, long *old, long new)
include/linux/atomic/atomic-instrumented.h
4479
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
4481
return raw_atomic_long_try_cmpxchg_release(v, old, new);
include/linux/atomic/atomic-instrumented.h
4499
atomic_long_try_cmpxchg_relaxed(atomic_long_t *v, long *old, long new)
include/linux/atomic/atomic-instrumented.h
450
atomic_inc_return(atomic_t *v)
include/linux/atomic/atomic-instrumented.h
4501
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
4503
return raw_atomic_long_try_cmpxchg_relaxed(v, old, new);
include/linux/atomic/atomic-instrumented.h
4518
atomic_long_sub_and_test(long i, atomic_long_t *v)
include/linux/atomic/atomic-instrumented.h
4521
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
4522
return raw_atomic_long_sub_and_test(i, v);
include/linux/atomic/atomic-instrumented.h
453
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
4536
atomic_long_dec_and_test(atomic_long_t *v)
include/linux/atomic/atomic-instrumented.h
4539
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
454
return raw_atomic_inc_return(v);
include/linux/atomic/atomic-instrumented.h
4540
return raw_atomic_long_dec_and_test(v);
include/linux/atomic/atomic-instrumented.h
4554
atomic_long_inc_and_test(atomic_long_t *v)
include/linux/atomic/atomic-instrumented.h
4557
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
4558
return raw_atomic_long_inc_and_test(v);
include/linux/atomic/atomic-instrumented.h
4573
atomic_long_add_negative(long i, atomic_long_t *v)
include/linux/atomic/atomic-instrumented.h
4576
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
4577
return raw_atomic_long_add_negative(i, v);
include/linux/atomic/atomic-instrumented.h
4592
atomic_long_add_negative_acquire(long i, atomic_long_t *v)
include/linux/atomic/atomic-instrumented.h
4594
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
4595
return raw_atomic_long_add_negative_acquire(i, v);
include/linux/atomic/atomic-instrumented.h
4610
atomic_long_add_negative_release(long i, atomic_long_t *v)
include/linux/atomic/atomic-instrumented.h
4613
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
4614
return raw_atomic_long_add_negative_release(i, v);
include/linux/atomic/atomic-instrumented.h
4629
atomic_long_add_negative_relaxed(long i, atomic_long_t *v)
include/linux/atomic/atomic-instrumented.h
4631
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
4632
return raw_atomic_long_add_negative_relaxed(i, v);
include/linux/atomic/atomic-instrumented.h
4649
atomic_long_fetch_add_unless(atomic_long_t *v, long a, long u)
include/linux/atomic/atomic-instrumented.h
4652
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
4653
return raw_atomic_long_fetch_add_unless(v, a, u);
include/linux/atomic/atomic-instrumented.h
4670
atomic_long_add_unless(atomic_long_t *v, long a, long u)
include/linux/atomic/atomic-instrumented.h
4673
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
4674
return raw_atomic_long_add_unless(v, a, u);
include/linux/atomic/atomic-instrumented.h
468
atomic_inc_return_acquire(atomic_t *v)
include/linux/atomic/atomic-instrumented.h
4689
atomic_long_inc_not_zero(atomic_long_t *v)
include/linux/atomic/atomic-instrumented.h
4692
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
4693
return raw_atomic_long_inc_not_zero(v);
include/linux/atomic/atomic-instrumented.h
47
atomic_read_acquire(const atomic_t *v)
include/linux/atomic/atomic-instrumented.h
470
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
4708
atomic_long_inc_unless_negative(atomic_long_t *v)
include/linux/atomic/atomic-instrumented.h
471
return raw_atomic_inc_return_acquire(v);
include/linux/atomic/atomic-instrumented.h
4711
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
4712
return raw_atomic_long_inc_unless_negative(v);
include/linux/atomic/atomic-instrumented.h
4727
atomic_long_dec_unless_positive(atomic_long_t *v)
include/linux/atomic/atomic-instrumented.h
4730
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
4731
return raw_atomic_long_dec_unless_positive(v);
include/linux/atomic/atomic-instrumented.h
4746
atomic_long_dec_if_positive(atomic_long_t *v)
include/linux/atomic/atomic-instrumented.h
4749
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
4750
return raw_atomic_long_dec_if_positive(v);
include/linux/atomic/atomic-instrumented.h
485
atomic_inc_return_release(atomic_t *v)
include/linux/atomic/atomic-instrumented.h
488
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
489
return raw_atomic_inc_return_release(v);
include/linux/atomic/atomic-instrumented.h
49
instrument_atomic_read(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
50
return raw_atomic_read_acquire(v);
include/linux/atomic/atomic-instrumented.h
503
atomic_inc_return_relaxed(atomic_t *v)
include/linux/atomic/atomic-instrumented.h
505
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
506
return raw_atomic_inc_return_relaxed(v);
include/linux/atomic/atomic-instrumented.h
520
atomic_fetch_inc(atomic_t *v)
include/linux/atomic/atomic-instrumented.h
523
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
524
return raw_atomic_fetch_inc(v);
include/linux/atomic/atomic-instrumented.h
538
atomic_fetch_inc_acquire(atomic_t *v)
include/linux/atomic/atomic-instrumented.h
540
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
541
return raw_atomic_fetch_inc_acquire(v);
include/linux/atomic/atomic-instrumented.h
555
atomic_fetch_inc_release(atomic_t *v)
include/linux/atomic/atomic-instrumented.h
558
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
559
return raw_atomic_fetch_inc_release(v);
include/linux/atomic/atomic-instrumented.h
573
atomic_fetch_inc_relaxed(atomic_t *v)
include/linux/atomic/atomic-instrumented.h
575
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
576
return raw_atomic_fetch_inc_relaxed(v);
include/linux/atomic/atomic-instrumented.h
590
atomic_dec(atomic_t *v)
include/linux/atomic/atomic-instrumented.h
592
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
593
raw_atomic_dec(v);
include/linux/atomic/atomic-instrumented.h
607
atomic_dec_return(atomic_t *v)
include/linux/atomic/atomic-instrumented.h
610
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
611
return raw_atomic_dec_return(v);
include/linux/atomic/atomic-instrumented.h
625
atomic_dec_return_acquire(atomic_t *v)
include/linux/atomic/atomic-instrumented.h
627
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
628
return raw_atomic_dec_return_acquire(v);
include/linux/atomic/atomic-instrumented.h
642
atomic_dec_return_release(atomic_t *v)
include/linux/atomic/atomic-instrumented.h
645
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
646
return raw_atomic_dec_return_release(v);
include/linux/atomic/atomic-instrumented.h
65
atomic_set(atomic_t *v, int i)
include/linux/atomic/atomic-instrumented.h
660
atomic_dec_return_relaxed(atomic_t *v)
include/linux/atomic/atomic-instrumented.h
662
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
663
return raw_atomic_dec_return_relaxed(v);
include/linux/atomic/atomic-instrumented.h
67
instrument_atomic_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
677
atomic_fetch_dec(atomic_t *v)
include/linux/atomic/atomic-instrumented.h
68
raw_atomic_set(v, i);
include/linux/atomic/atomic-instrumented.h
680
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
681
return raw_atomic_fetch_dec(v);
include/linux/atomic/atomic-instrumented.h
695
atomic_fetch_dec_acquire(atomic_t *v)
include/linux/atomic/atomic-instrumented.h
697
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
698
return raw_atomic_fetch_dec_acquire(v);
include/linux/atomic/atomic-instrumented.h
712
atomic_fetch_dec_release(atomic_t *v)
include/linux/atomic/atomic-instrumented.h
715
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
716
return raw_atomic_fetch_dec_release(v);
include/linux/atomic/atomic-instrumented.h
730
atomic_fetch_dec_relaxed(atomic_t *v)
include/linux/atomic/atomic-instrumented.h
732
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
733
return raw_atomic_fetch_dec_relaxed(v);
include/linux/atomic/atomic-instrumented.h
748
atomic_and(int i, atomic_t *v)
include/linux/atomic/atomic-instrumented.h
750
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
751
raw_atomic_and(i, v);
include/linux/atomic/atomic-instrumented.h
766
atomic_fetch_and(int i, atomic_t *v)
include/linux/atomic/atomic-instrumented.h
769
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
770
return raw_atomic_fetch_and(i, v);
include/linux/atomic/atomic-instrumented.h
785
atomic_fetch_and_acquire(int i, atomic_t *v)
include/linux/atomic/atomic-instrumented.h
787
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
788
return raw_atomic_fetch_and_acquire(i, v);
include/linux/atomic/atomic-instrumented.h
803
atomic_fetch_and_release(int i, atomic_t *v)
include/linux/atomic/atomic-instrumented.h
806
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
807
return raw_atomic_fetch_and_release(i, v);
include/linux/atomic/atomic-instrumented.h
822
atomic_fetch_and_relaxed(int i, atomic_t *v)
include/linux/atomic/atomic-instrumented.h
824
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
825
return raw_atomic_fetch_and_relaxed(i, v);
include/linux/atomic/atomic-instrumented.h
83
atomic_set_release(atomic_t *v, int i)
include/linux/atomic/atomic-instrumented.h
840
atomic_andnot(int i, atomic_t *v)
include/linux/atomic/atomic-instrumented.h
842
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
843
raw_atomic_andnot(i, v);
include/linux/atomic/atomic-instrumented.h
858
atomic_fetch_andnot(int i, atomic_t *v)
include/linux/atomic/atomic-instrumented.h
86
instrument_atomic_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
861
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
862
return raw_atomic_fetch_andnot(i, v);
include/linux/atomic/atomic-instrumented.h
87
raw_atomic_set_release(v, i);
include/linux/atomic/atomic-instrumented.h
877
atomic_fetch_andnot_acquire(int i, atomic_t *v)
include/linux/atomic/atomic-instrumented.h
879
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
880
return raw_atomic_fetch_andnot_acquire(i, v);
include/linux/atomic/atomic-instrumented.h
895
atomic_fetch_andnot_release(int i, atomic_t *v)
include/linux/atomic/atomic-instrumented.h
898
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
899
return raw_atomic_fetch_andnot_release(i, v);
include/linux/atomic/atomic-instrumented.h
914
atomic_fetch_andnot_relaxed(int i, atomic_t *v)
include/linux/atomic/atomic-instrumented.h
916
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
917
return raw_atomic_fetch_andnot_relaxed(i, v);
include/linux/atomic/atomic-instrumented.h
932
atomic_or(int i, atomic_t *v)
include/linux/atomic/atomic-instrumented.h
934
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
935
raw_atomic_or(i, v);
include/linux/atomic/atomic-instrumented.h
950
atomic_fetch_or(int i, atomic_t *v)
include/linux/atomic/atomic-instrumented.h
953
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
954
return raw_atomic_fetch_or(i, v);
include/linux/atomic/atomic-instrumented.h
969
atomic_fetch_or_acquire(int i, atomic_t *v)
include/linux/atomic/atomic-instrumented.h
971
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
972
return raw_atomic_fetch_or_acquire(i, v);
include/linux/atomic/atomic-instrumented.h
987
atomic_fetch_or_release(int i, atomic_t *v)
include/linux/atomic/atomic-instrumented.h
990
instrument_atomic_read_write(v, sizeof(*v));
include/linux/atomic/atomic-instrumented.h
991
return raw_atomic_fetch_or_release(i, v);
include/linux/atomic/atomic-long.h
100
raw_atomic64_set_release(v, i);
include/linux/atomic/atomic-long.h
1003
raw_atomic_long_fetch_andnot_acquire(long i, atomic_long_t *v)
include/linux/atomic/atomic-long.h
1006
return raw_atomic64_fetch_andnot_acquire(i, v);
include/linux/atomic/atomic-long.h
1008
return raw_atomic_fetch_andnot_acquire(i, v);
include/linux/atomic/atomic-long.h
102
raw_atomic_set_release(v, i);
include/linux/atomic/atomic-long.h
1024
raw_atomic_long_fetch_andnot_release(long i, atomic_long_t *v)
include/linux/atomic/atomic-long.h
1027
return raw_atomic64_fetch_andnot_release(i, v);
include/linux/atomic/atomic-long.h
1029
return raw_atomic_fetch_andnot_release(i, v);
include/linux/atomic/atomic-long.h
1045
raw_atomic_long_fetch_andnot_relaxed(long i, atomic_long_t *v)
include/linux/atomic/atomic-long.h
1048
return raw_atomic64_fetch_andnot_relaxed(i, v);
include/linux/atomic/atomic-long.h
1050
return raw_atomic_fetch_andnot_relaxed(i, v);
include/linux/atomic/atomic-long.h
1066
raw_atomic_long_or(long i, atomic_long_t *v)
include/linux/atomic/atomic-long.h
1069
raw_atomic64_or(i, v);
include/linux/atomic/atomic-long.h
1071
raw_atomic_or(i, v);
include/linux/atomic/atomic-long.h
1087
raw_atomic_long_fetch_or(long i, atomic_long_t *v)
include/linux/atomic/atomic-long.h
1090
return raw_atomic64_fetch_or(i, v);
include/linux/atomic/atomic-long.h
1092
return raw_atomic_fetch_or(i, v);
include/linux/atomic/atomic-long.h
1108
raw_atomic_long_fetch_or_acquire(long i, atomic_long_t *v)
include/linux/atomic/atomic-long.h
1111
return raw_atomic64_fetch_or_acquire(i, v);
include/linux/atomic/atomic-long.h
1113
return raw_atomic_fetch_or_acquire(i, v);
include/linux/atomic/atomic-long.h
1129
raw_atomic_long_fetch_or_release(long i, atomic_long_t *v)
include/linux/atomic/atomic-long.h
1132
return raw_atomic64_fetch_or_release(i, v);
include/linux/atomic/atomic-long.h
1134
return raw_atomic_fetch_or_release(i, v);
include/linux/atomic/atomic-long.h
1150
raw_atomic_long_fetch_or_relaxed(long i, atomic_long_t *v)
include/linux/atomic/atomic-long.h
1153
return raw_atomic64_fetch_or_relaxed(i, v);
include/linux/atomic/atomic-long.h
1155
return raw_atomic_fetch_or_relaxed(i, v);
include/linux/atomic/atomic-long.h
1171
raw_atomic_long_xor(long i, atomic_long_t *v)
include/linux/atomic/atomic-long.h
1174
raw_atomic64_xor(i, v);
include/linux/atomic/atomic-long.h
1176
raw_atomic_xor(i, v);
include/linux/atomic/atomic-long.h
118
raw_atomic_long_add(long i, atomic_long_t *v)
include/linux/atomic/atomic-long.h
1192
raw_atomic_long_fetch_xor(long i, atomic_long_t *v)
include/linux/atomic/atomic-long.h
1195
return raw_atomic64_fetch_xor(i, v);
include/linux/atomic/atomic-long.h
1197
return raw_atomic_fetch_xor(i, v);
include/linux/atomic/atomic-long.h
121
raw_atomic64_add(i, v);
include/linux/atomic/atomic-long.h
1213
raw_atomic_long_fetch_xor_acquire(long i, atomic_long_t *v)
include/linux/atomic/atomic-long.h
1216
return raw_atomic64_fetch_xor_acquire(i, v);
include/linux/atomic/atomic-long.h
1218
return raw_atomic_fetch_xor_acquire(i, v);
include/linux/atomic/atomic-long.h
123
raw_atomic_add(i, v);
include/linux/atomic/atomic-long.h
1234
raw_atomic_long_fetch_xor_release(long i, atomic_long_t *v)
include/linux/atomic/atomic-long.h
1237
return raw_atomic64_fetch_xor_release(i, v);
include/linux/atomic/atomic-long.h
1239
return raw_atomic_fetch_xor_release(i, v);
include/linux/atomic/atomic-long.h
1255
raw_atomic_long_fetch_xor_relaxed(long i, atomic_long_t *v)
include/linux/atomic/atomic-long.h
1258
return raw_atomic64_fetch_xor_relaxed(i, v);
include/linux/atomic/atomic-long.h
1260
return raw_atomic_fetch_xor_relaxed(i, v);
include/linux/atomic/atomic-long.h
1276
raw_atomic_long_xchg(atomic_long_t *v, long new)
include/linux/atomic/atomic-long.h
1279
return raw_atomic64_xchg(v, new);
include/linux/atomic/atomic-long.h
1281
return raw_atomic_xchg(v, new);
include/linux/atomic/atomic-long.h
1297
raw_atomic_long_xchg_acquire(atomic_long_t *v, long new)
include/linux/atomic/atomic-long.h
1300
return raw_atomic64_xchg_acquire(v, new);
include/linux/atomic/atomic-long.h
1302
return raw_atomic_xchg_acquire(v, new);
include/linux/atomic/atomic-long.h
1318
raw_atomic_long_xchg_release(atomic_long_t *v, long new)
include/linux/atomic/atomic-long.h
1321
return raw_atomic64_xchg_release(v, new);
include/linux/atomic/atomic-long.h
1323
return raw_atomic_xchg_release(v, new);
include/linux/atomic/atomic-long.h
1339
raw_atomic_long_xchg_relaxed(atomic_long_t *v, long new)
include/linux/atomic/atomic-long.h
1342
return raw_atomic64_xchg_relaxed(v, new);
include/linux/atomic/atomic-long.h
1344
return raw_atomic_xchg_relaxed(v, new);
include/linux/atomic/atomic-long.h
1362
raw_atomic_long_cmpxchg(atomic_long_t *v, long old, long new)
include/linux/atomic/atomic-long.h
1365
return raw_atomic64_cmpxchg(v, old, new);
include/linux/atomic/atomic-long.h
1367
return raw_atomic_cmpxchg(v, old, new);
include/linux/atomic/atomic-long.h
1385
raw_atomic_long_cmpxchg_acquire(atomic_long_t *v, long old, long new)
include/linux/atomic/atomic-long.h
1388
return raw_atomic64_cmpxchg_acquire(v, old, new);
include/linux/atomic/atomic-long.h
139
raw_atomic_long_add_return(long i, atomic_long_t *v)
include/linux/atomic/atomic-long.h
1390
return raw_atomic_cmpxchg_acquire(v, old, new);
include/linux/atomic/atomic-long.h
1408
raw_atomic_long_cmpxchg_release(atomic_long_t *v, long old, long new)
include/linux/atomic/atomic-long.h
1411
return raw_atomic64_cmpxchg_release(v, old, new);
include/linux/atomic/atomic-long.h
1413
return raw_atomic_cmpxchg_release(v, old, new);
include/linux/atomic/atomic-long.h
142
return raw_atomic64_add_return(i, v);
include/linux/atomic/atomic-long.h
1431
raw_atomic_long_cmpxchg_relaxed(atomic_long_t *v, long old, long new)
include/linux/atomic/atomic-long.h
1434
return raw_atomic64_cmpxchg_relaxed(v, old, new);
include/linux/atomic/atomic-long.h
1436
return raw_atomic_cmpxchg_relaxed(v, old, new);
include/linux/atomic/atomic-long.h
144
return raw_atomic_add_return(i, v);
include/linux/atomic/atomic-long.h
1455
raw_atomic_long_try_cmpxchg(atomic_long_t *v, long *old, long new)
include/linux/atomic/atomic-long.h
1458
return raw_atomic64_try_cmpxchg(v, (s64 *)old, new);
include/linux/atomic/atomic-long.h
1460
return raw_atomic_try_cmpxchg(v, (int *)old, new);
include/linux/atomic/atomic-long.h
1479
raw_atomic_long_try_cmpxchg_acquire(atomic_long_t *v, long *old, long new)
include/linux/atomic/atomic-long.h
1482
return raw_atomic64_try_cmpxchg_acquire(v, (s64 *)old, new);
include/linux/atomic/atomic-long.h
1484
return raw_atomic_try_cmpxchg_acquire(v, (int *)old, new);
include/linux/atomic/atomic-long.h
1503
raw_atomic_long_try_cmpxchg_release(atomic_long_t *v, long *old, long new)
include/linux/atomic/atomic-long.h
1506
return raw_atomic64_try_cmpxchg_release(v, (s64 *)old, new);
include/linux/atomic/atomic-long.h
1508
return raw_atomic_try_cmpxchg_release(v, (int *)old, new);
include/linux/atomic/atomic-long.h
1527
raw_atomic_long_try_cmpxchg_relaxed(atomic_long_t *v, long *old, long new)
include/linux/atomic/atomic-long.h
1530
return raw_atomic64_try_cmpxchg_relaxed(v, (s64 *)old, new);
include/linux/atomic/atomic-long.h
1532
return raw_atomic_try_cmpxchg_relaxed(v, (int *)old, new);
include/linux/atomic/atomic-long.h
1548
raw_atomic_long_sub_and_test(long i, atomic_long_t *v)
include/linux/atomic/atomic-long.h
1551
return raw_atomic64_sub_and_test(i, v);
include/linux/atomic/atomic-long.h
1553
return raw_atomic_sub_and_test(i, v);
include/linux/atomic/atomic-long.h
1568
raw_atomic_long_dec_and_test(atomic_long_t *v)
include/linux/atomic/atomic-long.h
1571
return raw_atomic64_dec_and_test(v);
include/linux/atomic/atomic-long.h
1573
return raw_atomic_dec_and_test(v);
include/linux/atomic/atomic-long.h
1588
raw_atomic_long_inc_and_test(atomic_long_t *v)
include/linux/atomic/atomic-long.h
1591
return raw_atomic64_inc_and_test(v);
include/linux/atomic/atomic-long.h
1593
return raw_atomic_inc_and_test(v);
include/linux/atomic/atomic-long.h
160
raw_atomic_long_add_return_acquire(long i, atomic_long_t *v)
include/linux/atomic/atomic-long.h
1609
raw_atomic_long_add_negative(long i, atomic_long_t *v)
include/linux/atomic/atomic-long.h
1612
return raw_atomic64_add_negative(i, v);
include/linux/atomic/atomic-long.h
1614
return raw_atomic_add_negative(i, v);
include/linux/atomic/atomic-long.h
163
return raw_atomic64_add_return_acquire(i, v);
include/linux/atomic/atomic-long.h
1630
raw_atomic_long_add_negative_acquire(long i, atomic_long_t *v)
include/linux/atomic/atomic-long.h
1633
return raw_atomic64_add_negative_acquire(i, v);
include/linux/atomic/atomic-long.h
1635
return raw_atomic_add_negative_acquire(i, v);
include/linux/atomic/atomic-long.h
165
return raw_atomic_add_return_acquire(i, v);
include/linux/atomic/atomic-long.h
1651
raw_atomic_long_add_negative_release(long i, atomic_long_t *v)
include/linux/atomic/atomic-long.h
1654
return raw_atomic64_add_negative_release(i, v);
include/linux/atomic/atomic-long.h
1656
return raw_atomic_add_negative_release(i, v);
include/linux/atomic/atomic-long.h
1672
raw_atomic_long_add_negative_relaxed(long i, atomic_long_t *v)
include/linux/atomic/atomic-long.h
1675
return raw_atomic64_add_negative_relaxed(i, v);
include/linux/atomic/atomic-long.h
1677
return raw_atomic_add_negative_relaxed(i, v);
include/linux/atomic/atomic-long.h
1695
raw_atomic_long_fetch_add_unless(atomic_long_t *v, long a, long u)
include/linux/atomic/atomic-long.h
1698
return raw_atomic64_fetch_add_unless(v, a, u);
include/linux/atomic/atomic-long.h
1700
return raw_atomic_fetch_add_unless(v, a, u);
include/linux/atomic/atomic-long.h
1718
raw_atomic_long_add_unless(atomic_long_t *v, long a, long u)
include/linux/atomic/atomic-long.h
1721
return raw_atomic64_add_unless(v, a, u);
include/linux/atomic/atomic-long.h
1723
return raw_atomic_add_unless(v, a, u);
include/linux/atomic/atomic-long.h
1739
raw_atomic_long_inc_not_zero(atomic_long_t *v)
include/linux/atomic/atomic-long.h
1742
return raw_atomic64_inc_not_zero(v);
include/linux/atomic/atomic-long.h
1744
return raw_atomic_inc_not_zero(v);
include/linux/atomic/atomic-long.h
1760
raw_atomic_long_inc_unless_negative(atomic_long_t *v)
include/linux/atomic/atomic-long.h
1763
return raw_atomic64_inc_unless_negative(v);
include/linux/atomic/atomic-long.h
1765
return raw_atomic_inc_unless_negative(v);
include/linux/atomic/atomic-long.h
1781
raw_atomic_long_dec_unless_positive(atomic_long_t *v)
include/linux/atomic/atomic-long.h
1784
return raw_atomic64_dec_unless_positive(v);
include/linux/atomic/atomic-long.h
1786
return raw_atomic_dec_unless_positive(v);
include/linux/atomic/atomic-long.h
1802
raw_atomic_long_dec_if_positive(atomic_long_t *v)
include/linux/atomic/atomic-long.h
1805
return raw_atomic64_dec_if_positive(v);
include/linux/atomic/atomic-long.h
1807
return raw_atomic_dec_if_positive(v);
include/linux/atomic/atomic-long.h
181
raw_atomic_long_add_return_release(long i, atomic_long_t *v)
include/linux/atomic/atomic-long.h
184
return raw_atomic64_add_return_release(i, v);
include/linux/atomic/atomic-long.h
186
return raw_atomic_add_return_release(i, v);
include/linux/atomic/atomic-long.h
202
raw_atomic_long_add_return_relaxed(long i, atomic_long_t *v)
include/linux/atomic/atomic-long.h
205
return raw_atomic64_add_return_relaxed(i, v);
include/linux/atomic/atomic-long.h
207
return raw_atomic_add_return_relaxed(i, v);
include/linux/atomic/atomic-long.h
223
raw_atomic_long_fetch_add(long i, atomic_long_t *v)
include/linux/atomic/atomic-long.h
226
return raw_atomic64_fetch_add(i, v);
include/linux/atomic/atomic-long.h
228
return raw_atomic_fetch_add(i, v);
include/linux/atomic/atomic-long.h
244
raw_atomic_long_fetch_add_acquire(long i, atomic_long_t *v)
include/linux/atomic/atomic-long.h
247
return raw_atomic64_fetch_add_acquire(i, v);
include/linux/atomic/atomic-long.h
249
return raw_atomic_fetch_add_acquire(i, v);
include/linux/atomic/atomic-long.h
265
raw_atomic_long_fetch_add_release(long i, atomic_long_t *v)
include/linux/atomic/atomic-long.h
268
return raw_atomic64_fetch_add_release(i, v);
include/linux/atomic/atomic-long.h
270
return raw_atomic_fetch_add_release(i, v);
include/linux/atomic/atomic-long.h
286
raw_atomic_long_fetch_add_relaxed(long i, atomic_long_t *v)
include/linux/atomic/atomic-long.h
289
return raw_atomic64_fetch_add_relaxed(i, v);
include/linux/atomic/atomic-long.h
291
return raw_atomic_fetch_add_relaxed(i, v);
include/linux/atomic/atomic-long.h
307
raw_atomic_long_sub(long i, atomic_long_t *v)
include/linux/atomic/atomic-long.h
310
raw_atomic64_sub(i, v);
include/linux/atomic/atomic-long.h
312
raw_atomic_sub(i, v);
include/linux/atomic/atomic-long.h
328
raw_atomic_long_sub_return(long i, atomic_long_t *v)
include/linux/atomic/atomic-long.h
331
return raw_atomic64_sub_return(i, v);
include/linux/atomic/atomic-long.h
333
return raw_atomic_sub_return(i, v);
include/linux/atomic/atomic-long.h
349
raw_atomic_long_sub_return_acquire(long i, atomic_long_t *v)
include/linux/atomic/atomic-long.h
35
raw_atomic_long_read(const atomic_long_t *v)
include/linux/atomic/atomic-long.h
352
return raw_atomic64_sub_return_acquire(i, v);
include/linux/atomic/atomic-long.h
354
return raw_atomic_sub_return_acquire(i, v);
include/linux/atomic/atomic-long.h
370
raw_atomic_long_sub_return_release(long i, atomic_long_t *v)
include/linux/atomic/atomic-long.h
373
return raw_atomic64_sub_return_release(i, v);
include/linux/atomic/atomic-long.h
375
return raw_atomic_sub_return_release(i, v);
include/linux/atomic/atomic-long.h
38
return raw_atomic64_read(v);
include/linux/atomic/atomic-long.h
391
raw_atomic_long_sub_return_relaxed(long i, atomic_long_t *v)
include/linux/atomic/atomic-long.h
394
return raw_atomic64_sub_return_relaxed(i, v);
include/linux/atomic/atomic-long.h
396
return raw_atomic_sub_return_relaxed(i, v);
include/linux/atomic/atomic-long.h
40
return raw_atomic_read(v);
include/linux/atomic/atomic-long.h
412
raw_atomic_long_fetch_sub(long i, atomic_long_t *v)
include/linux/atomic/atomic-long.h
415
return raw_atomic64_fetch_sub(i, v);
include/linux/atomic/atomic-long.h
417
return raw_atomic_fetch_sub(i, v);
include/linux/atomic/atomic-long.h
433
raw_atomic_long_fetch_sub_acquire(long i, atomic_long_t *v)
include/linux/atomic/atomic-long.h
436
return raw_atomic64_fetch_sub_acquire(i, v);
include/linux/atomic/atomic-long.h
438
return raw_atomic_fetch_sub_acquire(i, v);
include/linux/atomic/atomic-long.h
454
raw_atomic_long_fetch_sub_release(long i, atomic_long_t *v)
include/linux/atomic/atomic-long.h
457
return raw_atomic64_fetch_sub_release(i, v);
include/linux/atomic/atomic-long.h
459
return raw_atomic_fetch_sub_release(i, v);
include/linux/atomic/atomic-long.h
475
raw_atomic_long_fetch_sub_relaxed(long i, atomic_long_t *v)
include/linux/atomic/atomic-long.h
478
return raw_atomic64_fetch_sub_relaxed(i, v);
include/linux/atomic/atomic-long.h
480
return raw_atomic_fetch_sub_relaxed(i, v);
include/linux/atomic/atomic-long.h
495
raw_atomic_long_inc(atomic_long_t *v)
include/linux/atomic/atomic-long.h
498
raw_atomic64_inc(v);
include/linux/atomic/atomic-long.h
500
raw_atomic_inc(v);
include/linux/atomic/atomic-long.h
515
raw_atomic_long_inc_return(atomic_long_t *v)
include/linux/atomic/atomic-long.h
518
return raw_atomic64_inc_return(v);
include/linux/atomic/atomic-long.h
520
return raw_atomic_inc_return(v);
include/linux/atomic/atomic-long.h
535
raw_atomic_long_inc_return_acquire(atomic_long_t *v)
include/linux/atomic/atomic-long.h
538
return raw_atomic64_inc_return_acquire(v);
include/linux/atomic/atomic-long.h
540
return raw_atomic_inc_return_acquire(v);
include/linux/atomic/atomic-long.h
55
raw_atomic_long_read_acquire(const atomic_long_t *v)
include/linux/atomic/atomic-long.h
555
raw_atomic_long_inc_return_release(atomic_long_t *v)
include/linux/atomic/atomic-long.h
558
return raw_atomic64_inc_return_release(v);
include/linux/atomic/atomic-long.h
560
return raw_atomic_inc_return_release(v);
include/linux/atomic/atomic-long.h
575
raw_atomic_long_inc_return_relaxed(atomic_long_t *v)
include/linux/atomic/atomic-long.h
578
return raw_atomic64_inc_return_relaxed(v);
include/linux/atomic/atomic-long.h
58
return raw_atomic64_read_acquire(v);
include/linux/atomic/atomic-long.h
580
return raw_atomic_inc_return_relaxed(v);
include/linux/atomic/atomic-long.h
595
raw_atomic_long_fetch_inc(atomic_long_t *v)
include/linux/atomic/atomic-long.h
598
return raw_atomic64_fetch_inc(v);
include/linux/atomic/atomic-long.h
60
return raw_atomic_read_acquire(v);
include/linux/atomic/atomic-long.h
600
return raw_atomic_fetch_inc(v);
include/linux/atomic/atomic-long.h
615
raw_atomic_long_fetch_inc_acquire(atomic_long_t *v)
include/linux/atomic/atomic-long.h
618
return raw_atomic64_fetch_inc_acquire(v);
include/linux/atomic/atomic-long.h
620
return raw_atomic_fetch_inc_acquire(v);
include/linux/atomic/atomic-long.h
635
raw_atomic_long_fetch_inc_release(atomic_long_t *v)
include/linux/atomic/atomic-long.h
638
return raw_atomic64_fetch_inc_release(v);
include/linux/atomic/atomic-long.h
640
return raw_atomic_fetch_inc_release(v);
include/linux/atomic/atomic-long.h
655
raw_atomic_long_fetch_inc_relaxed(atomic_long_t *v)
include/linux/atomic/atomic-long.h
658
return raw_atomic64_fetch_inc_relaxed(v);
include/linux/atomic/atomic-long.h
660
return raw_atomic_fetch_inc_relaxed(v);
include/linux/atomic/atomic-long.h
675
raw_atomic_long_dec(atomic_long_t *v)
include/linux/atomic/atomic-long.h
678
raw_atomic64_dec(v);
include/linux/atomic/atomic-long.h
680
raw_atomic_dec(v);
include/linux/atomic/atomic-long.h
695
raw_atomic_long_dec_return(atomic_long_t *v)
include/linux/atomic/atomic-long.h
698
return raw_atomic64_dec_return(v);
include/linux/atomic/atomic-long.h
700
return raw_atomic_dec_return(v);
include/linux/atomic/atomic-long.h
715
raw_atomic_long_dec_return_acquire(atomic_long_t *v)
include/linux/atomic/atomic-long.h
718
return raw_atomic64_dec_return_acquire(v);
include/linux/atomic/atomic-long.h
720
return raw_atomic_dec_return_acquire(v);
include/linux/atomic/atomic-long.h
735
raw_atomic_long_dec_return_release(atomic_long_t *v)
include/linux/atomic/atomic-long.h
738
return raw_atomic64_dec_return_release(v);
include/linux/atomic/atomic-long.h
740
return raw_atomic_dec_return_release(v);
include/linux/atomic/atomic-long.h
755
raw_atomic_long_dec_return_relaxed(atomic_long_t *v)
include/linux/atomic/atomic-long.h
758
return raw_atomic64_dec_return_relaxed(v);
include/linux/atomic/atomic-long.h
76
raw_atomic_long_set(atomic_long_t *v, long i)
include/linux/atomic/atomic-long.h
760
return raw_atomic_dec_return_relaxed(v);
include/linux/atomic/atomic-long.h
775
raw_atomic_long_fetch_dec(atomic_long_t *v)
include/linux/atomic/atomic-long.h
778
return raw_atomic64_fetch_dec(v);
include/linux/atomic/atomic-long.h
780
return raw_atomic_fetch_dec(v);
include/linux/atomic/atomic-long.h
79
raw_atomic64_set(v, i);
include/linux/atomic/atomic-long.h
795
raw_atomic_long_fetch_dec_acquire(atomic_long_t *v)
include/linux/atomic/atomic-long.h
798
return raw_atomic64_fetch_dec_acquire(v);
include/linux/atomic/atomic-long.h
800
return raw_atomic_fetch_dec_acquire(v);
include/linux/atomic/atomic-long.h
81
raw_atomic_set(v, i);
include/linux/atomic/atomic-long.h
815
raw_atomic_long_fetch_dec_release(atomic_long_t *v)
include/linux/atomic/atomic-long.h
818
return raw_atomic64_fetch_dec_release(v);
include/linux/atomic/atomic-long.h
820
return raw_atomic_fetch_dec_release(v);
include/linux/atomic/atomic-long.h
835
raw_atomic_long_fetch_dec_relaxed(atomic_long_t *v)
include/linux/atomic/atomic-long.h
838
return raw_atomic64_fetch_dec_relaxed(v);
include/linux/atomic/atomic-long.h
840
return raw_atomic_fetch_dec_relaxed(v);
include/linux/atomic/atomic-long.h
856
raw_atomic_long_and(long i, atomic_long_t *v)
include/linux/atomic/atomic-long.h
859
raw_atomic64_and(i, v);
include/linux/atomic/atomic-long.h
861
raw_atomic_and(i, v);
include/linux/atomic/atomic-long.h
877
raw_atomic_long_fetch_and(long i, atomic_long_t *v)
include/linux/atomic/atomic-long.h
880
return raw_atomic64_fetch_and(i, v);
include/linux/atomic/atomic-long.h
882
return raw_atomic_fetch_and(i, v);
include/linux/atomic/atomic-long.h
898
raw_atomic_long_fetch_and_acquire(long i, atomic_long_t *v)
include/linux/atomic/atomic-long.h
901
return raw_atomic64_fetch_and_acquire(i, v);
include/linux/atomic/atomic-long.h
903
return raw_atomic_fetch_and_acquire(i, v);
include/linux/atomic/atomic-long.h
919
raw_atomic_long_fetch_and_release(long i, atomic_long_t *v)
include/linux/atomic/atomic-long.h
922
return raw_atomic64_fetch_and_release(i, v);
include/linux/atomic/atomic-long.h
924
return raw_atomic_fetch_and_release(i, v);
include/linux/atomic/atomic-long.h
940
raw_atomic_long_fetch_and_relaxed(long i, atomic_long_t *v)
include/linux/atomic/atomic-long.h
943
return raw_atomic64_fetch_and_relaxed(i, v);
include/linux/atomic/atomic-long.h
945
return raw_atomic_fetch_and_relaxed(i, v);
include/linux/atomic/atomic-long.h
961
raw_atomic_long_andnot(long i, atomic_long_t *v)
include/linux/atomic/atomic-long.h
964
raw_atomic64_andnot(i, v);
include/linux/atomic/atomic-long.h
966
raw_atomic_andnot(i, v);
include/linux/atomic/atomic-long.h
97
raw_atomic_long_set_release(atomic_long_t *v, long i)
include/linux/atomic/atomic-long.h
982
raw_atomic_long_fetch_andnot(long i, atomic_long_t *v)
include/linux/atomic/atomic-long.h
985
return raw_atomic64_fetch_andnot(i, v);
include/linux/atomic/atomic-long.h
987
return raw_atomic_fetch_andnot(i, v);
include/linux/bitfield.h
214
static __always_inline __##type __must_check type##_encode_bits(base v, base field) \
include/linux/bitfield.h
216
if (__builtin_constant_p(v) && (v & ~field_mask(field))) \
include/linux/bitfield.h
218
return to((v & field_mask(field)) * field_multiplier(field)); \
include/linux/bitfield.h
230
static __always_inline base __must_check type##_get_bits(__##type v, base field) \
include/linux/bitfield.h
232
return (from(v) & field)/field_multiplier(field); \
include/linux/bnge/hsi.h
773
__le16 v;
include/linux/bnge/hsi.h
797
__le32 v;
include/linux/bnxt/hsi.h
769
__le16 v;
include/linux/bnxt/hsi.h
793
__le32 v;
include/linux/bug.h
94
static inline __must_check bool check_data_corruption(bool v) { return v; }
include/linux/ccp.h
35
#define CCP_VERSION(v, r) ((unsigned int)((v << CCP_VSIZE) \
include/linux/ceph/ceph_frag.h
22
static inline __u32 ceph_frag_make(__u32 b, __u32 v)
include/linux/ceph/ceph_frag.h
25
(v & (0xffffffu << (24-b)) & 0xffffffu);
include/linux/ceph/ceph_frag.h
44
static inline bool ceph_frag_contains_value(__u32 f, __u32 v)
include/linux/ceph/ceph_frag.h
46
return (v & ceph_frag_mask(f)) == ceph_frag_value(f);
include/linux/ceph/decode.h
21
u64 v = get_unaligned_le64(*p);
include/linux/ceph/decode.h
23
return v;
include/linux/ceph/decode.h
253
static inline void ceph_encode_64(void **p, u64 v)
include/linux/ceph/decode.h
255
put_unaligned_le64(v, (__le64 *)*p);
include/linux/ceph/decode.h
258
static inline void ceph_encode_32(void **p, u32 v)
include/linux/ceph/decode.h
260
put_unaligned_le32(v, (__le32 *)*p);
include/linux/ceph/decode.h
263
static inline void ceph_encode_16(void **p, u16 v)
include/linux/ceph/decode.h
265
put_unaligned_le16(v, (__le16 *)*p);
include/linux/ceph/decode.h
268
static inline void ceph_encode_8(void **p, u8 v)
include/linux/ceph/decode.h
27
u32 v = get_unaligned_le32(*p);
include/linux/ceph/decode.h
270
*(u8 *)*p = v;
include/linux/ceph/decode.h
29
return v;
include/linux/ceph/decode.h
33
u16 v = get_unaligned_le16(*p);
include/linux/ceph/decode.h
336
static inline int ceph_start_decoding(void **p, void *end, u8 v,
include/linux/ceph/decode.h
345
if (v < struct_compat) {
include/linux/ceph/decode.h
347
*struct_v, struct_compat, v, name);
include/linux/ceph/decode.h
35
return v;
include/linux/ceph/decode.h
365
#define ceph_encode_64_safe(p, end, v, bad) \
include/linux/ceph/decode.h
368
ceph_encode_64(p, v); \
include/linux/ceph/decode.h
370
#define ceph_encode_32_safe(p, end, v, bad) \
include/linux/ceph/decode.h
373
ceph_encode_32(p, v); \
include/linux/ceph/decode.h
375
#define ceph_encode_16_safe(p, end, v, bad) \
include/linux/ceph/decode.h
378
ceph_encode_16(p, v); \
include/linux/ceph/decode.h
380
#define ceph_encode_8_safe(p, end, v, bad) \
include/linux/ceph/decode.h
383
ceph_encode_8(p, v); \
include/linux/ceph/decode.h
39
u8 v = *(u8 *)*p;
include/linux/ceph/decode.h
41
return v;
include/linux/ceph/decode.h
63
#define ceph_decode_64_safe(p, end, v, bad) \
include/linux/ceph/decode.h
66
v = ceph_decode_64(p); \
include/linux/ceph/decode.h
68
#define ceph_decode_32_safe(p, end, v, bad) \
include/linux/ceph/decode.h
71
v = ceph_decode_32(p); \
include/linux/ceph/decode.h
73
#define ceph_decode_16_safe(p, end, v, bad) \
include/linux/ceph/decode.h
76
v = ceph_decode_16(p); \
include/linux/ceph/decode.h
78
#define ceph_decode_8_safe(p, end, v, bad) \
include/linux/ceph/decode.h
81
v = ceph_decode_8(p); \
include/linux/ceph/pagelist.h
30
static inline int ceph_pagelist_encode_64(struct ceph_pagelist *pl, u64 v)
include/linux/ceph/pagelist.h
32
__le64 ev = cpu_to_le64(v);
include/linux/ceph/pagelist.h
35
static inline int ceph_pagelist_encode_32(struct ceph_pagelist *pl, u32 v)
include/linux/ceph/pagelist.h
37
__le32 ev = cpu_to_le32(v);
include/linux/ceph/pagelist.h
40
static inline int ceph_pagelist_encode_16(struct ceph_pagelist *pl, u16 v)
include/linux/ceph/pagelist.h
42
__le16 ev = cpu_to_le16(v);
include/linux/ceph/pagelist.h
45
static inline int ceph_pagelist_encode_8(struct ceph_pagelist *pl, u8 v)
include/linux/ceph/pagelist.h
47
return ceph_pagelist_append(pl, &v, 1);
include/linux/cgroup-defs.h
733
int (*seq_show)(struct seq_file *sf, void *v);
include/linux/cgroup-defs.h
737
void *(*seq_next)(struct seq_file *sf, void *v, loff_t *ppos);
include/linux/cgroup-defs.h
738
void (*seq_stop)(struct seq_file *sf, void *v);
include/linux/cgroup.h
148
int cgroup_parse_float(const char *input, unsigned dec_shift, s64 *v);
include/linux/closure.h
171
void closure_sub(struct closure *cl, int v);
include/linux/compat.h
42
#define __SC_DELOUSE(t,v) ((__force t)(unsigned long)(v))
include/linux/compat.h
452
compat_sigset_t v;
include/linux/compat.h
454
case 4: v.sig[7] = (set->sig[3] >> 32); v.sig[6] = set->sig[3];
include/linux/compat.h
456
case 3: v.sig[5] = (set->sig[2] >> 32); v.sig[4] = set->sig[2];
include/linux/compat.h
458
case 2: v.sig[3] = (set->sig[1] >> 32); v.sig[2] = set->sig[1];
include/linux/compat.h
460
case 1: v.sig[1] = (set->sig[0] >> 32); v.sig[0] = set->sig[0];
include/linux/compat.h
462
return copy_to_user(compat, &v, size) ? -EFAULT : 0;
include/linux/cpu.h
214
extern bool cpu_attack_vector_mitigated(enum cpu_attack_vectors v);
include/linux/cpu.h
225
static inline bool cpu_attack_vector_mitigated(enum cpu_attack_vectors v)
include/linux/crush/mapper.h
32
void crush_init_workspace(const struct crush_map *map, void *v);
include/linux/dma-mapping.h
599
#define dma_get_sgtable(d, t, v, h, s) dma_get_sgtable_attrs(d, t, v, h, s, 0)
include/linux/dma-mapping.h
600
#define dma_mmap_coherent(d, v, c, h, s) dma_mmap_attrs(d, v, c, h, s, 0)
include/linux/dsa/brcm.h
13
#define BRCM_TAG_GET_PORT(v) ((v) >> 8)
include/linux/dsa/brcm.h
14
#define BRCM_TAG_GET_QUEUE(v) ((v) & 0xff)
include/linux/fb.h
158
extern int fb_notifier_call_chain(unsigned long val, void *v);
include/linux/fb.h
170
static inline int fb_notifier_call_chain(unsigned long val, void *v)
include/linux/filter.h
578
#define __BPF_MAP_0(m, v, ...) v
include/linux/filter.h
579
#define __BPF_MAP_1(m, v, t, a, ...) m(t, a)
include/linux/filter.h
580
#define __BPF_MAP_2(m, v, t, a, ...) m(t, a), __BPF_MAP_1(m, v, __VA_ARGS__)
include/linux/filter.h
581
#define __BPF_MAP_3(m, v, t, a, ...) m(t, a), __BPF_MAP_2(m, v, __VA_ARGS__)
include/linux/filter.h
582
#define __BPF_MAP_4(m, v, t, a, ...) m(t, a), __BPF_MAP_3(m, v, __VA_ARGS__)
include/linux/filter.h
583
#define __BPF_MAP_5(m, v, t, a, ...) m(t, a), __BPF_MAP_4(m, v, __VA_ARGS__)
include/linux/fixp-arith.h
81
#define fixp_cos32(v) fixp_sin32((v) + 90)
include/linux/fixp-arith.h
89
#define fixp_sin16(v) (fixp_sin32(v) >> 16)
include/linux/fixp-arith.h
90
#define fixp_cos16(v) (fixp_cos32(v) >> 16)
include/linux/fs.h
2534
int delayed_getname_uflags(struct delayed_filename *v, const char __user *, int);
include/linux/fsi.h
48
#define FSI_DEVICE_VERSIONED(t, v) \
include/linux/fsi.h
49
.engine_type = (t), .version = (v),
include/linux/greybus.h
43
#define GREYBUS_DEVICE(v, p) \
include/linux/greybus.h
45
.vendor = (v), \
include/linux/hfs_common.h
279
__be16 v;
include/linux/ieee80211.h
123
#define SM64(f, v) ((((u64)v) << f##_S) & f)
include/linux/ieee80211.h
2777
u8 v;
include/linux/ieee802154.h
69
#define IEEE802154_FC_SET_TYPE(v, x) do { \
include/linux/ieee802154.h
70
v = (((v) & ~IEEE802154_FC_TYPE_MASK) | \
include/linux/instrumented.h
110
static __always_inline void instrument_atomic_read_write(const volatile void *v, size_t size)
include/linux/instrumented.h
112
kasan_check_write(v, size);
include/linux/instrumented.h
113
kcsan_check_atomic_read_write(v, size);
include/linux/instrumented.h
114
instrument_atomic_check_alignment(v, size);
include/linux/instrumented.h
25
static __always_inline void instrument_read(const volatile void *v, size_t size)
include/linux/instrumented.h
27
kasan_check_read(v, size);
include/linux/instrumented.h
28
kcsan_check_read(v, size);
include/linux/instrumented.h
39
static __always_inline void instrument_write(const volatile void *v, size_t size)
include/linux/instrumented.h
41
kasan_check_write(v, size);
include/linux/instrumented.h
42
kcsan_check_write(v, size);
include/linux/instrumented.h
53
static __always_inline void instrument_read_write(const volatile void *v, size_t size)
include/linux/instrumented.h
55
kasan_check_write(v, size);
include/linux/instrumented.h
56
kcsan_check_read_write(v, size);
include/linux/instrumented.h
59
static __always_inline void instrument_atomic_check_alignment(const volatile void *v, size_t size)
include/linux/instrumented.h
67
WARN_ON_ONCE((unsigned long)v & mask);
include/linux/instrumented.h
80
static __always_inline void instrument_atomic_read(const volatile void *v, size_t size)
include/linux/instrumented.h
82
kasan_check_read(v, size);
include/linux/instrumented.h
83
kcsan_check_atomic_read(v, size);
include/linux/instrumented.h
84
instrument_atomic_check_alignment(v, size);
include/linux/instrumented.h
95
static __always_inline void instrument_atomic_write(const volatile void *v, size_t size)
include/linux/instrumented.h
97
kasan_check_write(v, size);
include/linux/instrumented.h
98
kcsan_check_atomic_write(v, size);
include/linux/instrumented.h
99
instrument_atomic_check_alignment(v, size);
include/linux/interrupt.h
865
int show_interrupts(struct seq_file *p, void *v);
include/linux/ipmi_smi.h
239
#define ipmi_version_major(v) ((v)->ipmi_version & 0xf)
include/linux/ipmi_smi.h
240
#define ipmi_version_minor(v) ((v)->ipmi_version >> 4)
include/linux/jump_label.h
288
int v;
include/linux/jump_label.h
295
v = atomic_read(&key->enabled);
include/linux/jump_label.h
297
if (v < 0 || (v + 1) < 0)
include/linux/jump_label.h
299
} while (!likely(atomic_try_cmpxchg(&key->enabled, &v, v + 1)));
include/linux/kernfs.h
295
int (*seq_show)(struct seq_file *sf, void *v);
include/linux/kernfs.h
298
void *(*seq_next)(struct seq_file *sf, void *v, loff_t *ppos);
include/linux/kernfs.h
299
void (*seq_stop)(struct seq_file *sf, void *v);
include/linux/kho/abi/kexec_handover.h
113
typeof(val) v = val; \
include/linux/kho/abi/kexec_handover.h
114
typecheck(typeof((dest).ptr), v); \
include/linux/kho/abi/kexec_handover.h
115
(dest).phys = virt_to_phys(v); \
include/linux/kvm_host.h
1335
#define __kvm_get_guest(kvm, gfn, offset, v) \
include/linux/kvm_host.h
1338
typeof(v) __user *__uaddr = (typeof(__uaddr))(__addr + offset); \
include/linux/kvm_host.h
1342
__ret = get_user(v, __uaddr); \
include/linux/kvm_host.h
1346
#define kvm_get_guest(kvm, gpa, v) \
include/linux/kvm_host.h
1352
offset_in_page(__gpa), v); \
include/linux/kvm_host.h
1355
#define __kvm_put_guest(kvm, gfn, offset, v) \
include/linux/kvm_host.h
1358
typeof(v) __user *__uaddr = (typeof(__uaddr))(__addr + offset); \
include/linux/kvm_host.h
1362
__ret = put_user(v, __uaddr); \
include/linux/kvm_host.h
1368
#define kvm_put_guest(kvm, gpa, v) \
include/linux/kvm_host.h
1374
offset_in_page(__gpa), v); \
include/linux/libgcc.h
34
long long notrace __muldi3(long long u, long long v);
include/linux/memory.h
135
static inline int memory_notify(enum memory_block_state state, void *v)
include/linux/memory.h
159
extern int memory_notify(enum memory_block_state state, void *v);
include/linux/mlx5/device.h
106
#define __MLX5_SET64(typ, p, fld, v) do { \
include/linux/mlx5/device.h
108
*((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \
include/linux/mlx5/device.h
111
#define MLX5_SET64(typ, p, fld, v) do { \
include/linux/mlx5/device.h
113
__MLX5_SET64(typ, p, fld, v); \
include/linux/mlx5/device.h
116
#define MLX5_ARRAY_SET64(typ, p, fld, idx, v) do { \
include/linux/mlx5/device.h
118
__MLX5_SET64(typ, p, fld[idx], v); \
include/linux/mlx5/device.h
133
#define MLX5_SET16(typ, p, fld, v) do { \
include/linux/mlx5/device.h
134
u16 _v = v; \
include/linux/mlx5/device.h
74
#define MLX5_SET(typ, p, fld, v) do { \
include/linux/mlx5/device.h
75
u32 _v = v; \
include/linux/mlx5/device.h
83
#define MLX5_ARRAY_SET(typ, p, fld, idx, v) do { \
include/linux/mlx5/device.h
85
MLX5_SET(typ, p, fld[idx], v); \
include/linux/mlx5/fs.h
41
#define MLX5_SET_CFG(p, f, v) MLX5_SET(create_flow_group_in, p, f, v)
include/linux/mm_types.h
697
typedef struct { unsigned long v; } freeptr_t;
include/linux/mpi.h
68
int mpi_cmp_ui(MPI u, ulong v);
include/linux/mpi.h
69
int mpi_cmp(MPI u, MPI v);
include/linux/mpi.h
82
int mpi_add(MPI w, MPI u, MPI v);
include/linux/mpi.h
83
int mpi_sub(MPI w, MPI u, MPI v);
include/linux/mpi.h
84
int mpi_addm(MPI w, MPI u, MPI v, MPI m);
include/linux/mpi.h
85
int mpi_subm(MPI w, MPI u, MPI v, MPI m);
include/linux/mpi.h
88
int mpi_mul(MPI w, MPI u, MPI v);
include/linux/mpi.h
89
int mpi_mulm(MPI w, MPI u, MPI v, MPI m);
include/linux/mroute_base.h
271
void vif_device_init(struct vif_device *v,
include/linux/mroute_base.h
318
static inline void vif_device_init(struct vif_device *v,
include/linux/mroute_base.h
400
void *mr_vif_seq_next(struct seq_file *seq, void *v, loff_t *pos);
include/linux/mroute_base.h
414
void *mr_mfc_seq_next(struct seq_file *seq, void *v,
include/linux/mroute_base.h
431
static inline void mr_mfc_seq_stop(struct seq_file *seq, void *v)
include/linux/mroute_base.h
449
void *v, loff_t *pos)
include/linux/mroute_base.h
465
static inline void *mr_mfc_seq_next(struct seq_file *seq, void *v,
include/linux/mroute_base.h
477
static inline void mr_mfc_seq_stop(struct seq_file *seq, void *v)
include/linux/mtd/onenand.h
164
#define ONENAND_SET_SYS_CFG1(v, this) \
include/linux/mtd/onenand.h
165
(this->write_word(v, this->base + ONENAND_REG_SYS_CFG1))
include/linux/node.h
149
extern int node_notify(unsigned long val, void *v);
include/linux/node.h
164
static inline int node_notify(unsigned long val, void *v)
include/linux/notifier.h
170
unsigned long val, void *v);
include/linux/notifier.h
172
unsigned long val, void *v);
include/linux/notifier.h
174
unsigned long val, void *v);
include/linux/notifier.h
176
unsigned long val, void *v);
include/linux/notifier.h
179
unsigned long val_up, unsigned long val_down, void *v);
include/linux/notifier.h
181
unsigned long val_up, unsigned long val_down, void *v);
include/linux/overflow.h
212
typeof(T) v = 0; \
include/linux/overflow.h
213
check_add_overflow((x), v, &v); \
include/linux/page_ref.h
101
__page_ref_set(page, v);
include/linux/page_ref.h
104
static inline void folio_set_count(struct folio *folio, int v)
include/linux/page_ref.h
106
set_page_count(&folio->page, v);
include/linux/page_ref.h
29
extern void __page_ref_set(struct page *page, int v);
include/linux/page_ref.h
30
extern void __page_ref_mod(struct page *page, int v);
include/linux/page_ref.h
31
extern void __page_ref_mod_and_test(struct page *page, int v, int ret);
include/linux/page_ref.h
32
extern void __page_ref_mod_and_return(struct page *page, int v, int ret);
include/linux/page_ref.h
33
extern void __page_ref_mod_unless(struct page *page, int v, int u);
include/linux/page_ref.h
34
extern void __page_ref_freeze(struct page *page, int v, int ret);
include/linux/page_ref.h
35
extern void __page_ref_unfreeze(struct page *page, int v);
include/linux/page_ref.h
41
static inline void __page_ref_set(struct page *page, int v)
include/linux/page_ref.h
44
static inline void __page_ref_mod(struct page *page, int v)
include/linux/page_ref.h
47
static inline void __page_ref_mod_and_test(struct page *page, int v, int ret)
include/linux/page_ref.h
50
static inline void __page_ref_mod_and_return(struct page *page, int v, int ret)
include/linux/page_ref.h
53
static inline void __page_ref_mod_unless(struct page *page, int v, int u)
include/linux/page_ref.h
56
static inline void __page_ref_freeze(struct page *page, int v, int ret)
include/linux/page_ref.h
59
static inline void __page_ref_unfreeze(struct page *page, int v)
include/linux/page_ref.h
97
static inline void set_page_count(struct page *page, int v)
include/linux/page_ref.h
99
atomic_set(&page->_refcount, v);
include/linux/parport.h
518
#define parport_frob_control(p,m,v) parport_pc_frob_control(p,m,v)
include/linux/parport.h
532
#define parport_frob_control(p,m,v) (p)->ops->frob_control(p,m,v)
include/linux/platform_data/cros_ec_commands.h
3256
int32_t v; /* In nV */
include/linux/poll.h
117
#define __MAP(v, from, to) \
include/linux/poll.h
118
(from < to ? (v & from) * (to/from) : (v & from) / (from/to))
include/linux/poll.h
122
__u16 v = (__force __u16)val;
include/linux/poll.h
123
#define M(X) __MAP(v, (__force __u16)EPOLL##X, POLL##X)
include/linux/raspberrypi/vchiq_core.h
70
#define DEBUG_VALUE(d, v) \
include/linux/raspberrypi/vchiq_core.h
71
do { debug_ptr[DEBUG_ ## d] = (v); dsb(sy); } while (0)
include/linux/raspberrypi/vchiq_core.h
79
#define DEBUG_VALUE(d, v)
include/linux/rcupdate.h
1041
#define RCU_INIT_POINTER(p, v) \
include/linux/rcupdate.h
1044
WRITE_ONCE(p, RCU_INITIALIZER(v)); \
include/linux/rcupdate.h
1054
#define RCU_POINTER_INITIALIZER(p, v) \
include/linux/rcupdate.h
1055
.p = RCU_INITIALIZER(v)
include/linux/rcupdate.h
537
#define RCU_INITIALIZER(v) (typeof(*(v)) __force __rcu *)(v)
include/linux/rcupdate.h
570
#define rcu_assign_pointer(p, v) \
include/linux/rcupdate.h
572
uintptr_t _r_a_p__v = (uintptr_t)(v); \
include/linux/rcupdate.h
575
if (__builtin_constant_p(v) && (_r_a_p__v) == (uintptr_t)NULL) \
include/linux/regset.h
37
static inline int membuf_write(struct membuf *s, const void *v, size_t size)
include/linux/regset.h
42
memcpy(s->p, v, size);
include/linux/regset.h
62
#define membuf_store(s, v) \
include/linux/regset.h
66
typeof(v) __v = (v); \
include/linux/selection.h
20
int set_selection_kernel(struct tiocl_selection *v, struct tty_struct *tty);
include/linux/seq_file.h
138
unsigned long long v, unsigned int width);
include/linux/seq_file.h
303
extern struct list_head *seq_list_next(void *v, struct list_head *head,
include/linux/seq_file.h
308
extern struct list_head *seq_list_next_rcu(void *v, struct list_head *head, loff_t *ppos);
include/linux/seq_file.h
318
extern struct hlist_node *seq_hlist_next(void *v, struct hlist_head *head,
include/linux/seq_file.h
325
extern struct hlist_node *seq_hlist_next_rcu(void *v,
include/linux/seq_file.h
33
void (*stop) (struct seq_file *m, void *v);
include/linux/seq_file.h
332
extern struct hlist_node *seq_hlist_next_percpu(void *v, struct hlist_head __percpu *head, int *cpu, loff_t *pos);
include/linux/seq_file.h
34
void * (*next) (struct seq_file *m, void *v, loff_t *pos);
include/linux/seq_file.h
35
int (*show) (struct seq_file *m, void *v);
include/linux/serial_8250.h
211
void serial8250_set_isa_configurator(void (*v)(int port, struct uart_port *up,
include/linux/soc/qcom/apr.h
122
#define APR_SVC_MAJOR_VERSION(v) ((v >> 16) & 0xFF)
include/linux/soc/qcom/apr.h
123
#define APR_SVC_MINOR_VERSION(v) (v & 0xFF)
include/linux/soc/ti/omap1-io.h
15
extern void omap_writeb(u8 v, u32 pa);
include/linux/soc/ti/omap1-io.h
16
extern void omap_writew(u16 v, u32 pa);
include/linux/soc/ti/omap1-io.h
17
extern void omap_writel(u32 v, u32 pa);
include/linux/soc/ti/omap1-io.h
22
static inline void omap_writeb(u8 v, u32 pa) { }
include/linux/soc/ti/omap1-io.h
23
static inline void omap_writew(u16 v, u32 pa) { }
include/linux/soc/ti/omap1-io.h
24
static inline void omap_writel(u32 v, u32 pa) { }
include/linux/spi/mxs-spi.h
58
#define BF_SSP_TIMING_CLOCK_DIVIDE(v) \
include/linux/spi/mxs-spi.h
59
(((v) << 8) & BM_SSP_TIMING_CLOCK_DIVIDE)
include/linux/spi/mxs-spi.h
62
#define BF_SSP_TIMING_CLOCK_RATE(v) \
include/linux/spi/mxs-spi.h
63
(((v) << 0) & BM_SSP_TIMING_CLOCK_RATE)
include/linux/spi/mxs-spi.h
86
#define BF_SSP_CTRL1_WORD_LENGTH(v) \
include/linux/spi/mxs-spi.h
87
(((v) << 4) & BM_SSP_CTRL1_WORD_LENGTH)
include/linux/spi/mxs-spi.h
93
#define BF_SSP_CTRL1_SSP_MODE(v) \
include/linux/spi/mxs-spi.h
94
(((v) << 0) & BM_SSP_CTRL1_SSP_MODE)
include/linux/ssbi.h
19
u8 v;
include/linux/ssbi.h
21
ret = ssbi_read(context, reg, &v, 1);
include/linux/ssbi.h
23
*val = v;
include/linux/ssbi.h
31
u8 v = val;
include/linux/ssbi.h
32
return ssbi_write(context, reg, &v, 1);
include/linux/statfs.h
49
static inline __kernel_fsid_t u64_to_fsid(u64 v)
include/linux/statfs.h
51
return (__kernel_fsid_t){.val = {(u32)v, (u32)(v>>32)}};
include/linux/stdarg.h
6
#define va_start(v, l) __builtin_va_start(v, l)
include/linux/stdarg.h
7
#define va_end(v) __builtin_va_end(v)
include/linux/stdarg.h
8
#define va_arg(v, T) __builtin_va_arg(v, T)
include/linux/string.h
235
static inline void *memset_l(unsigned long *p, unsigned long v,
include/linux/string.h
239
return memset32((uint32_t *)p, v, n);
include/linux/string.h
241
return memset64((uint64_t *)p, v, n);
include/linux/string.h
244
static inline void *memset_p(void **p, void *v, __kernel_size_t n)
include/linux/string.h
247
return memset32((uint32_t *)p, (uintptr_t)v, n);
include/linux/string.h
249
return memset64((uint64_t *)p, (uintptr_t)v, n);
include/linux/string.h
512
#define memset_after(obj, v, member) \
include/linux/string.h
515
typeof(v) __val = (v); \
include/linux/string.h
530
#define memset_startat(obj, v, member) \
include/linux/string.h
533
typeof(v) __val = (v); \
include/linux/string_choices.h
20
static inline const char *str_assert_deassert(bool v)
include/linux/string_choices.h
22
return v ? "assert" : "deassert";
include/linux/string_choices.h
24
#define str_deassert_assert(v) str_assert_deassert(!(v))
include/linux/string_choices.h
26
static inline const char *str_enable_disable(bool v)
include/linux/string_choices.h
28
return v ? "enable" : "disable";
include/linux/string_choices.h
30
#define str_disable_enable(v) str_enable_disable(!(v))
include/linux/string_choices.h
32
static inline const char *str_enabled_disabled(bool v)
include/linux/string_choices.h
34
return v ? "enabled" : "disabled";
include/linux/string_choices.h
36
#define str_disabled_enabled(v) str_enabled_disabled(!(v))
include/linux/string_choices.h
38
static inline const char *str_hi_lo(bool v)
include/linux/string_choices.h
40
return v ? "hi" : "lo";
include/linux/string_choices.h
42
#define str_lo_hi(v) str_hi_lo(!(v))
include/linux/string_choices.h
44
static inline const char *str_high_low(bool v)
include/linux/string_choices.h
46
return v ? "high" : "low";
include/linux/string_choices.h
48
#define str_low_high(v) str_high_low(!(v))
include/linux/string_choices.h
50
static inline const char *str_input_output(bool v)
include/linux/string_choices.h
52
return v ? "input" : "output";
include/linux/string_choices.h
54
#define str_output_input(v) str_input_output(!(v))
include/linux/string_choices.h
56
static inline const char *str_on_off(bool v)
include/linux/string_choices.h
58
return v ? "on" : "off";
include/linux/string_choices.h
60
#define str_off_on(v) str_on_off(!(v))
include/linux/string_choices.h
62
static inline const char *str_read_write(bool v)
include/linux/string_choices.h
64
return v ? "read" : "write";
include/linux/string_choices.h
66
#define str_write_read(v) str_read_write(!(v))
include/linux/string_choices.h
68
static inline const char *str_true_false(bool v)
include/linux/string_choices.h
70
return v ? "true" : "false";
include/linux/string_choices.h
72
#define str_false_true(v) str_true_false(!(v))
include/linux/string_choices.h
74
static inline const char *str_up_down(bool v)
include/linux/string_choices.h
76
return v ? "up" : "down";
include/linux/string_choices.h
78
#define str_down_up(v) str_up_down(!(v))
include/linux/string_choices.h
80
static inline const char *str_yes_no(bool v)
include/linux/string_choices.h
82
return v ? "yes" : "no";
include/linux/string_choices.h
84
#define str_no_yes(v) str_yes_no(!(v))
include/linux/syscalls.h
127
#define __TYPE_AS(t, v) __same_type((__force t)0, v)
include/linux/torture.h
105
bool torture_init_begin(char *ttype, int v);
include/linux/u64_stats_sync.h
102
local64_sub(val, &p->v);
include/linux/u64_stats_sync.h
107
local64_inc(&p->v);
include/linux/u64_stats_sync.h
129
u64 v;
include/linux/u64_stats_sync.h
134
return p->v;
include/linux/u64_stats_sync.h
145
p->v = val;
include/linux/u64_stats_sync.h
150
p->v += val;
include/linux/u64_stats_sync.h
155
p->v -= val;
include/linux/u64_stats_sync.h
160
p->v++;
include/linux/u64_stats_sync.h
74
local64_t v;
include/linux/u64_stats_sync.h
79
return local64_read(&p->v);
include/linux/u64_stats_sync.h
92
local64_set(&p->v, val);
include/linux/u64_stats_sync.h
97
local64_add(val, &p->v);
include/linux/usb/gadget.h
901
static inline void usb_free_descriptors(struct usb_descriptor_header **v)
include/linux/usb/gadget.h
903
kfree(v);
include/linux/user_namespace.h
151
long inc_rlimit_ucounts(struct ucounts *ucounts, enum rlimit_type type, long v);
include/linux/user_namespace.h
152
bool dec_rlimit_ucounts(struct ucounts *ucounts, enum rlimit_type type, long v);
include/linux/user_namespace.h
201
extern int proc_setgroups_show(struct seq_file *m, void *v);
include/linux/virtio_config.h
631
__virtio16 v;
include/linux/virtio_config.h
634
v = cpu_to_virtio16(vdev, val);
include/linux/virtio_config.h
635
vdev->config->set(vdev, offset, &v, sizeof(v));
include/linux/virtio_config.h
651
__virtio32 v;
include/linux/virtio_config.h
654
v = cpu_to_virtio32(vdev, val);
include/linux/virtio_config.h
655
vdev->config->set(vdev, offset, &v, sizeof(v));
include/linux/virtio_config.h
670
__virtio64 v;
include/linux/virtio_config.h
673
v = cpu_to_virtio64(vdev, val);
include/linux/virtio_config.h
674
vdev->config->set(vdev, offset, &v, sizeof(v));
include/linux/virtio_ring.h
50
#define virtio_store_mb(weak_barriers, p, v) \
include/linux/virtio_ring.h
53
virt_store_mb(*p, v); \
include/linux/virtio_ring.h
55
WRITE_ONCE(*p, v); \
include/linux/vmw_vmci_defs.h
397
#define VMCI_VERSION_MAJOR(v) ((u32) (v) >> VMCI_VERSION_SHIFT_WIDTH)
include/linux/vmw_vmci_defs.h
398
#define VMCI_VERSION_MINOR(v) ((u16) (v))
include/linux/win_minmax.h
14
u32 v; /* value measured */
include/linux/win_minmax.h
24
return m->s[0].v;
include/linux/win_minmax.h
29
struct minmax_sample val = { .t = t, .v = meas };
include/linux/win_minmax.h
32
return m->s[0].v;
include/linux/xarray.h
149
static inline void *xa_mk_internal(unsigned long v)
include/linux/xarray.h
151
return (void *)((v << 2) | 2);
include/linux/xarray.h
58
static inline void *xa_mk_value(unsigned long v)
include/linux/xarray.h
60
WARN_ON((long)v < 0);
include/linux/xarray.h
61
return (void *)((v << 1) | 1);
include/media/drv-intf/tea575x.h
62
int snd_tea575x_g_tuner(struct snd_tea575x *tea, struct v4l2_tuner *v);
include/net/addrconf.h
330
int inet6addr_notifier_call_chain(unsigned long val, void *v);
include/net/addrconf.h
334
int inet6addr_validator_notifier_call_chain(unsigned long val, void *v);
include/net/dcbevent.h
20
int call_dcbevent_notifiers(unsigned long val, void *v);
include/net/dcbevent.h
33
static inline int call_dcbevent_notifiers(unsigned long val, void *v)
include/net/netevent.h
37
int call_netevent_notifiers(unsigned long val, void *v);
include/net/netfilter/nf_conntrack.h
379
#define NF_CT_STAT_ADD_ATOMIC(net, count, v) this_cpu_add((net)->ct.stat->count, (v))
include/net/netfilter/nf_tables.h
1355
const struct nft_verdict *v);
include/net/ping.h
75
void *ping_seq_next(struct seq_file *seq, void *v, loff_t *pos);
include/net/ping.h
76
void ping_seq_stop(struct seq_file *seq, void *v);
include/net/raw.h
71
void *raw_seq_next(struct seq_file *seq, void *v, loff_t *pos);
include/net/raw.h
72
void raw_seq_stop(struct seq_file *seq, void *v);
include/net/red.h
159
static inline void red_set_vars(struct red_vars *v)
include/net/red.h
165
v->qavg = 0;
include/net/red.h
167
v->qcount = -1;
include/net/red.h
267
static inline int red_is_idling(const struct red_vars *v)
include/net/red.h
269
return v->qidlestart != 0;
include/net/red.h
272
static inline void red_start_of_idle_period(struct red_vars *v)
include/net/red.h
274
v->qidlestart = ktime_get();
include/net/red.h
277
static inline void red_end_of_idle_period(struct red_vars *v)
include/net/red.h
279
v->qidlestart = 0;
include/net/red.h
282
static inline void red_restart(struct red_vars *v)
include/net/red.h
284
red_end_of_idle_period(v);
include/net/red.h
285
v->qavg = 0;
include/net/red.h
286
v->qcount = -1;
include/net/red.h
290
const struct red_vars *v)
include/net/red.h
292
s64 delta = ktime_us_delta(ktime_get(), v->qidlestart);
include/net/red.h
319
return v->qavg >> shift;
include/net/red.h
328
us_idle = (v->qavg * (u64)us_idle) >> p->Scell_log;
include/net/red.h
330
if (us_idle < (v->qavg >> 1))
include/net/red.h
331
return v->qavg - us_idle;
include/net/red.h
333
return v->qavg >> 1;
include/net/red.h
338
const struct red_vars *v,
include/net/red.h
350
return v->qavg + (backlog - (v->qavg >> p->Wlog));
include/net/red.h
354
const struct red_vars *v,
include/net/red.h
357
if (!red_is_idling(v))
include/net/red.h
358
return red_calc_qavg_no_idle_time(p, v, backlog);
include/net/red.h
360
return red_calc_qavg_from_idle_time(p, v);
include/net/red.h
370
const struct red_vars *v,
include/net/red.h
389
return !(((qavg - p->qth_min) >> p->Wlog) * v->qcount < v->qR);
include/net/red.h
415
struct red_vars *v,
include/net/red.h
420
v->qcount = -1;
include/net/red.h
424
if (++v->qcount) {
include/net/red.h
425
if (red_mark_probability(p, v, qavg)) {
include/net/red.h
426
v->qcount = 0;
include/net/red.h
427
v->qR = red_random(p);
include/net/red.h
431
v->qR = red_random(p);
include/net/red.h
436
v->qcount = -1;
include/net/red.h
444
static inline void red_adaptative_algo(struct red_parms *p, struct red_vars *v)
include/net/red.h
449
qavg = v->qavg;
include/net/red.h
450
if (red_is_idling(v))
include/net/red.h
451
qavg = red_calc_qavg_from_idle_time(p, v);
include/net/sctp/sctp.h
427
for (pos.v = (u8 *)(chunk + 1);\
include/net/sctp/sctp.h
428
(pos.v + offsetof(struct sctp_paramhdr, length) + sizeof(pos.p->length) <=\
include/net/sctp/sctp.h
430
pos.v <= (void *)chunk + end - ntohs(pos.p->length) &&\
include/net/sctp/sctp.h
432
pos.v += SCTP_PAD4(ntohs(pos.p->length)))
include/net/sctp/structs.h
350
void *v;
include/net/sctp/structs.h
578
__u8 *v;
include/net/sock.h
2162
u32 v = get_random_u32();
include/net/sock.h
2164
return v ?: 1;
include/net/sock.h
2713
int v = waitall ? len : min_t(int, READ_ONCE(sk->sk_rcvlowat), len);
include/net/sock.h
2715
return v ?: 1;
include/net/tcp.h
2355
void *tcp_seq_next(struct seq_file *seq, void *v, loff_t *pos);
include/net/tcp.h
2356
void tcp_seq_stop(struct seq_file *seq, void *v);
include/net/udp.h
575
void *udp_seq_next(struct seq_file *seq, void *v, loff_t *pos);
include/net/udp.h
576
void udp_seq_stop(struct seq_file *seq, void *v);
include/net/xfrm.h
2190
m->v = m->m = 0;
include/net/xfrm.h
2192
return m->v & m->m;
include/net/xfrm.h
2199
if (m->m | m->v)
include/net/xfrm.h
2208
return (m->v & m->m) | (mark & ~m->m);
include/rdma/ib_verbs.h
5024
u64 v = (u64)lqpn * rqpn;
include/rdma/ib_verbs.h
5026
v ^= v >> 20;
include/rdma/ib_verbs.h
5027
v ^= v >> 40;
include/rdma/ib_verbs.h
5029
return (u32)(v & IB_GRH_FLOWLABEL_MASK);
include/rdma/rdmavt_qp.h
1000
void (*cb)(struct rvt_qp *qp, u64 v));
include/rdma/rdmavt_qp.h
1003
u64 v,
include/rdma/rdmavt_qp.h
1004
void (*cb)(struct rvt_qp *qp, u64 v));
include/rdma/rdmavt_qp.h
907
void (*cb)(struct rvt_qp *qp, u64 v);
include/rdma/rdmavt_qp.h
909
u64 v;
include/rdma/rdmavt_qp.h
999
u64 v,
include/scsi/fc/fc_fip.h
55
#define FIP_VER_ENCAPS(v) ((v) << FIP_VER_SHIFT)
include/scsi/fc/fc_fip.h
56
#define FIP_VER_DECAPS(v) ((v) >> FIP_VER_SHIFT)
include/scsi/fc_frame.h
31
static inline void hton24(u8 *p, u32 v)
include/scsi/fc_frame.h
33
p[0] = (v >> 16) & 0xff;
include/scsi/fc_frame.h
34
p[1] = (v >> 8) & 0xff;
include/scsi/fc_frame.h
35
p[2] = v & 0xff;
include/scsi/iscsi_proto.h
58
#define hton24(p, v) { \
include/scsi/iscsi_proto.h
59
p[0] = (((v) >> 16) & 0xFF); \
include/scsi/iscsi_proto.h
60
p[1] = (((v) >> 8) & 0xFF); \
include/scsi/iscsi_proto.h
61
p[2] = ((v) & 0xFF); \
include/scsi/scsi_transport_fc.h
257
#define vport_to_shost(v) \
include/scsi/scsi_transport_fc.h
258
(v->shost)
include/scsi/scsi_transport_fc.h
259
#define vport_to_shost_channel(v) \
include/scsi/scsi_transport_fc.h
260
(v->channel)
include/scsi/scsi_transport_fc.h
261
#define vport_to_parent(v) \
include/scsi/scsi_transport_fc.h
262
(v->dev.parent)
include/soc/arc/arc_aux.h
14
#define write_aux_reg(r, v) __builtin_arc_sr((unsigned int)(v), r)
include/soc/arc/arc_aux.h
27
static inline void write_aux_reg(u32 r, u32 v)
include/soc/fsl/qman.h
272
#define qm_fqid_set(p, v) ((p)->fqid = cpu_to_be32((v) & QM_FQID_MASK))
include/soc/fsl/qman.h
857
#define QM_MCR_NP_RA1_NRA(v) (((v) >> 14) & 0x3) /* FQD::NRA */
include/soc/fsl/qman.h
858
#define QM_MCR_NP_RA2_IT(v) (((v) >> 14) & 0x1) /* FQD::IT */
include/soc/fsl/qman.h
859
#define QM_MCR_NP_OD1_NOD(v) (((v) >> 14) & 0x3) /* FQD::NOD */
include/soc/fsl/qman.h
860
#define QM_MCR_NP_OD3_NPC(v) (((v) >> 14) & 0x3) /* FQD::NPC */
include/soc/tegra/tegra-cbb.h
24
int (*debugfs_show)(struct tegra_cbb *cbb, struct seq_file *s, void *v);
include/sound/emu10k1.h
64
#define REG_VAL_GET(r, v) ((v & REG_MASK(r)) >> REG_SHIFT(r))
include/sound/emu10k1.h
65
#define REG_VAL_PUT(r, v) ((v) << REG_SHIFT(r))
include/sound/pcm.h
1068
int snd_interval_refine(struct snd_interval *i, const struct snd_interval *v);
include/sound/pcm_params.h
100
unsigned int v;
include/sound/pcm_params.h
101
v = mask->bits[MASK_OFS(val)] & MASK_BIT(val);
include/sound/pcm_params.h
103
mask->bits[MASK_OFS(val)] = v;
include/sound/pcm_params.h
107
const struct snd_mask *v)
include/sound/pcm_params.h
111
mask->bits[i] &= v->bits[i];
include/sound/pcm_params.h
115
const struct snd_mask *v)
include/sound/pcm_params.h
117
return ! memcmp(mask, v, SNDRV_MASK_SIZE * sizeof(u_int32_t));
include/sound/pcm_params.h
121
const struct snd_mask *v)
include/sound/pcm_params.h
123
*mask = *v;
include/sound/pcm_params.h
154
const struct snd_mask *v)
include/sound/pcm_params.h
158
snd_mask_intersect(mask, v);
include/sound/pcm_params.h
261
unsigned int v;
include/sound/pcm_params.h
262
v = i->max;
include/sound/pcm_params.h
264
v--;
include/sound/pcm_params.h
265
return v;
include/sound/soundfont.h
25
struct soundfont_voice_info v; /* All the soundfont parameters */
include/sound/soundfont.h
35
struct soundfont_sample_info v;
include/target/target_core_base.h
1022
static inline void atomic_inc_mb(atomic_t *v)
include/target/target_core_base.h
1025
atomic_inc(v);
include/target/target_core_base.h
1029
static inline void atomic_dec_mb(atomic_t *v)
include/target/target_core_base.h
1032
atomic_dec(v);
include/trace/events/page_ref.h
101
TP_ARGS(page, v, ret)
include/trace/events/page_ref.h
106
TP_PROTO(struct page *page, int v, int ret),
include/trace/events/page_ref.h
108
TP_ARGS(page, v, ret)
include/trace/events/page_ref.h
113
TP_PROTO(struct page *page, int v, int ret),
include/trace/events/page_ref.h
115
TP_ARGS(page, v, ret)
include/trace/events/page_ref.h
120
TP_PROTO(struct page *page, int v, int ret),
include/trace/events/page_ref.h
122
TP_ARGS(page, v, ret)
include/trace/events/page_ref.h
127
TP_PROTO(struct page *page, int v),
include/trace/events/page_ref.h
129
TP_ARGS(page, v)
include/trace/events/page_ref.h
15
TP_PROTO(struct page *page, int v),
include/trace/events/page_ref.h
17
TP_ARGS(page, v),
include/trace/events/page_ref.h
36
__entry->val = v;
include/trace/events/page_ref.h
49
TP_PROTO(struct page *page, int v),
include/trace/events/page_ref.h
51
TP_ARGS(page, v)
include/trace/events/page_ref.h
56
TP_PROTO(struct page *page, int v),
include/trace/events/page_ref.h
58
TP_ARGS(page, v)
include/trace/events/page_ref.h
63
TP_PROTO(struct page *page, int v, int ret),
include/trace/events/page_ref.h
65
TP_ARGS(page, v, ret),
include/trace/events/page_ref.h
85
__entry->val = v;
include/trace/events/page_ref.h
99
TP_PROTO(struct page *page, int v, int ret),
include/uapi/drm/drm_fourcc.h
1057
#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(v) \
include/uapi/drm/drm_fourcc.h
1058
DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 0, 0, 0, (v))
include/uapi/drm/drm_fourcc.h
1139
#define DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(v) \
include/uapi/drm/drm_fourcc.h
1140
fourcc_mod_broadcom_code(2, v)
include/uapi/drm/drm_fourcc.h
1141
#define DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(v) \
include/uapi/drm/drm_fourcc.h
1142
fourcc_mod_broadcom_code(3, v)
include/uapi/drm/drm_fourcc.h
1143
#define DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(v) \
include/uapi/drm/drm_fourcc.h
1144
fourcc_mod_broadcom_code(4, v)
include/uapi/drm/drm_fourcc.h
1145
#define DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(v) \
include/uapi/drm/drm_fourcc.h
1146
fourcc_mod_broadcom_code(5, v)
include/uapi/drm/exynos_drm.h
225
struct drm_exynos_ipp_limit_val v;
include/uapi/linux/coff.h
53
#define COFF_LONG(v) COFF_LONG_L(v)
include/uapi/linux/coff.h
54
#define COFF_SHORT(v) COFF_SHORT_L(v)
include/uapi/linux/firewire-cdev.h
862
#define FW_CDEV_ISO_PAYLOAD_LENGTH(v) (v)
include/uapi/linux/firewire-cdev.h
866
#define FW_CDEV_ISO_TAG(v) ((v) << 18)
include/uapi/linux/firewire-cdev.h
867
#define FW_CDEV_ISO_SY(v) ((v) << 20)
include/uapi/linux/firewire-cdev.h
868
#define FW_CDEV_ISO_HEADER_LENGTH(v) ((v) << 24)
include/uapi/linux/keyboard.h
45
#define K(t,v) (((t)<<8)|(v))
include/uapi/linux/msdos_fs.h
22
#define CF_LE_W(v) le16_to_cpu(v)
include/uapi/linux/msdos_fs.h
23
#define CF_LE_L(v) le32_to_cpu(v)
include/uapi/linux/msdos_fs.h
24
#define CT_LE_W(v) cpu_to_le16(v)
include/uapi/linux/msdos_fs.h
25
#define CT_LE_L(v) cpu_to_le32(v)
include/uapi/linux/pkt_cls.h
765
#define TCF_EM_REL_VALID(v) (((v) & TCF_EM_REL_MASK) != TCF_EM_REL_MASK)
include/uapi/linux/ppp-comp.h
56
#define BSD_MAKE_OPT(v, n) (((v) << 5) | (n))
include/uapi/linux/rkisp1-config.h
149
#define RKISP1_CIF_ISP_DPCC_LINE_THRESH_G(v) ((v) << 0)
include/uapi/linux/rkisp1-config.h
150
#define RKISP1_CIF_ISP_DPCC_LINE_THRESH_RB(v) ((v) << 8)
include/uapi/linux/rkisp1-config.h
151
#define RKISP1_CIF_ISP_DPCC_LINE_MAD_FAC_G(v) ((v) << 0)
include/uapi/linux/rkisp1-config.h
152
#define RKISP1_CIF_ISP_DPCC_LINE_MAD_FAC_RB(v) ((v) << 8)
include/uapi/linux/rkisp1-config.h
153
#define RKISP1_CIF_ISP_DPCC_PG_FAC_G(v) ((v) << 0)
include/uapi/linux/rkisp1-config.h
154
#define RKISP1_CIF_ISP_DPCC_PG_FAC_RB(v) ((v) << 8)
include/uapi/linux/rkisp1-config.h
155
#define RKISP1_CIF_ISP_DPCC_RND_THRESH_G(v) ((v) << 0)
include/uapi/linux/rkisp1-config.h
156
#define RKISP1_CIF_ISP_DPCC_RND_THRESH_RB(v) ((v) << 8)
include/uapi/linux/rkisp1-config.h
157
#define RKISP1_CIF_ISP_DPCC_RG_FAC_G(v) ((v) << 0)
include/uapi/linux/rkisp1-config.h
158
#define RKISP1_CIF_ISP_DPCC_RG_FAC_RB(v) ((v) << 8)
include/uapi/linux/rkisp1-config.h
160
#define RKISP1_CIF_ISP_DPCC_RO_LIMITS_n_G(n, v) ((v) << ((n) * 4))
include/uapi/linux/rkisp1-config.h
161
#define RKISP1_CIF_ISP_DPCC_RO_LIMITS_n_RB(n, v) ((v) << ((n) * 4 + 2))
include/uapi/linux/rkisp1-config.h
163
#define RKISP1_CIF_ISP_DPCC_RND_OFFS_n_G(n, v) ((v) << ((n) * 4))
include/uapi/linux/rkisp1-config.h
164
#define RKISP1_CIF_ISP_DPCC_RND_OFFS_n_RB(n, v) ((v) << ((n) * 4 + 2))
include/uapi/linux/xfrm.h
340
__u32 v; /* value */
include/uapi/sound/fcp.h
70
#define FCP_HWDEP_VERSION_MAJOR(v) (((v) >> 16) & 0xFF)
include/uapi/sound/fcp.h
71
#define FCP_HWDEP_VERSION_MINOR(v) (((v) >> 8) & 0xFF)
include/uapi/sound/fcp.h
72
#define FCP_HWDEP_VERSION_SUBMINOR(v) ((v) & 0xFF)
include/uapi/sound/scarlett2.h
24
#define SCARLETT2_HWDEP_VERSION_MAJOR(v) (((v) >> 16) & 0xFF)
include/uapi/sound/scarlett2.h
25
#define SCARLETT2_HWDEP_VERSION_MINOR(v) (((v) >> 8) & 0xFF)
include/uapi/sound/scarlett2.h
26
#define SCARLETT2_HWDEP_VERSION_SUBMINOR(v) ((v) & 0xFF)
include/ufs/ufshci.h
315
#define UIC_GET_ATTR_ID(v) (((v) >> 16) & 0xFFFF)
include/video/gbe.h
83
#define GET(v, msb, lsb) \
include/video/gbe.h
84
( ((u32)(v) & MASK(msb,lsb)) >> (lsb) )
include/video/gbe.h
85
#define SET(v, f, msb, lsb) \
include/video/gbe.h
86
( (v) = ((v)&~MASK(msb,lsb)) | (( (u32)(f)<<(lsb) ) & MASK(msb,lsb)) )
include/video/gbe.h
88
#define GET_GBE_FIELD(reg, field, v) \
include/video/gbe.h
89
GET((v), GBE_##reg##_##field##_MSB, GBE_##reg##_##field##_LSB)
include/video/gbe.h
90
#define SET_GBE_FIELD(reg, field, v, f) \
include/video/gbe.h
91
SET((v), (f), GBE_##reg##_##field##_MSB, GBE_##reg##_##field##_LSB)
include/video/tgafb.h
228
TGA_WRITE_REG(struct tga_par *par, u32 v, u32 r)
include/video/tgafb.h
230
writel(v, par->tga_regs_base +r);
include/video/tgafb.h
240
BT485_WRITE(struct tga_par *par, u8 v, u8 r)
include/video/tgafb.h
243
TGA_WRITE_REG(par, v | (r << 8), TGA_RAMDAC_REG);
include/video/tgafb.h
256
BT463_WRITE(struct tga_par *par, u32 m, u16 a, u8 v)
include/video/tgafb.h
260
TGA_WRITE_REG(par, m << 10 | v, TGA_RAMDAC_REG);
include/video/tgafb.h
273
BT459_WRITE(struct tga_par *par, u32 m, u16 a, u8 v)
include/video/tgafb.h
277
TGA_WRITE_REG(par, v, TGA_RAMDAC_REG);
include/video/vga.h
169
#define VGA_OUT16VAL(v, r) (((v) << 8) | (r))
include/xen/arm/page.h
79
#define virt_to_gfn(v) \
include/xen/arm/page.h
81
WARN_ON_ONCE(!virt_addr_valid(v)); \
include/xen/arm/page.h
82
pfn_to_gfn(virt_to_phys(v) >> XEN_PAGE_SHIFT); \
include/xen/arm/page.h
86
#define percpu_to_gfn(v) \
include/xen/arm/page.h
87
(pfn_to_gfn(per_cpu_ptr_to_phys(v) >> XEN_PAGE_SHIFT))
include/xen/interface/vcpu.h
113
struct vcpu_runstate_info *v;
include/xen/interface/vcpu.h
200
struct pvclock_vcpu_time_info *v;
io_uring/net.c
1425
struct bio_vec v = mp_bvec_iter_bvec(from->bvec, bi);
io_uring/net.c
1427
copied += v.bv_len;
io_uring/net.c
1428
truesize += PAGE_ALIGN(v.bv_len + v.bv_offset);
io_uring/net.c
1429
__skb_fill_page_desc_noacc(shinfo, frag++, v.bv_page,
io_uring/net.c
1430
v.bv_offset, v.bv_len);
io_uring/net.c
1431
bvec_iter_advance_single(from->bvec, &bi, v.bv_len);
io_uring/poll.c
243
int v;
io_uring/poll.c
249
v = atomic_read(&req->poll_refs);
io_uring/poll.c
251
if (unlikely(v != 1)) {
io_uring/poll.c
253
if (WARN_ON_ONCE(!(v & IO_POLL_REF_MASK)))
io_uring/poll.c
255
if (v & IO_POLL_CANCEL_FLAG)
io_uring/poll.c
262
if ((v & IO_POLL_REF_MASK) != 1)
io_uring/poll.c
265
if (v & IO_POLL_RETRY_FLAG) {
io_uring/poll.c
273
v &= ~IO_POLL_RETRY_FLAG;
io_uring/poll.c
275
v &= IO_POLL_REF_MASK;
io_uring/poll.c
311
if ((req->cqe.res & (POLLHUP | POLLRDHUP)) && v != 1)
io_uring/poll.c
312
v--;
io_uring/poll.c
330
} while (atomic_sub_return(v, &req->poll_refs) & IO_POLL_REF_MASK);
io_uring/poll.c
75
int v;
io_uring/poll.c
82
v = atomic_fetch_or(IO_POLL_RETRY_FLAG, &req->poll_refs);
io_uring/poll.c
83
if (v & IO_POLL_REF_MASK)
ipc/compat.c
41
struct compat_ipc64_perm v;
ipc/compat.c
42
if (copy_from_user(&v, from, sizeof(v)))
ipc/compat.c
44
to->uid = v.uid;
ipc/compat.c
45
to->gid = v.gid;
ipc/compat.c
46
to->mode = v.mode;
ipc/compat.c
53
struct compat_ipc_perm v;
ipc/compat.c
54
if (copy_from_user(&v, from, sizeof(v)))
ipc/compat.c
56
to->uid = v.uid;
ipc/compat.c
57
to->gid = v.gid;
ipc/compat.c
58
to->mode = v.mode;
ipc/mqueue.c
1465
struct compat_mq_attr v;
ipc/mqueue.c
1467
if (copy_from_user(&v, uattr, sizeof(*uattr)))
ipc/mqueue.c
1471
attr->mq_flags = v.mq_flags;
ipc/mqueue.c
1472
attr->mq_maxmsg = v.mq_maxmsg;
ipc/mqueue.c
1473
attr->mq_msgsize = v.mq_msgsize;
ipc/mqueue.c
1474
attr->mq_curmsgs = v.mq_curmsgs;
ipc/mqueue.c
1481
struct compat_mq_attr v;
ipc/mqueue.c
1483
memset(&v, 0, sizeof(v));
ipc/mqueue.c
1484
v.mq_flags = attr->mq_flags;
ipc/mqueue.c
1485
v.mq_maxmsg = attr->mq_maxmsg;
ipc/mqueue.c
1486
v.mq_msgsize = attr->mq_msgsize;
ipc/mqueue.c
1487
v.mq_curmsgs = attr->mq_curmsgs;
ipc/mqueue.c
1488
if (copy_to_user(uattr, &v, sizeof(*uattr)))
ipc/msg.c
701
struct compat_msqid64_ds v;
ipc/msg.c
702
memset(&v, 0, sizeof(v));
ipc/msg.c
703
to_compat_ipc64_perm(&v.msg_perm, &in->msg_perm);
ipc/msg.c
704
v.msg_stime = lower_32_bits(in->msg_stime);
ipc/msg.c
705
v.msg_stime_high = upper_32_bits(in->msg_stime);
ipc/msg.c
706
v.msg_rtime = lower_32_bits(in->msg_rtime);
ipc/msg.c
707
v.msg_rtime_high = upper_32_bits(in->msg_rtime);
ipc/msg.c
708
v.msg_ctime = lower_32_bits(in->msg_ctime);
ipc/msg.c
709
v.msg_ctime_high = upper_32_bits(in->msg_ctime);
ipc/msg.c
710
v.msg_cbytes = in->msg_cbytes;
ipc/msg.c
711
v.msg_qnum = in->msg_qnum;
ipc/msg.c
712
v.msg_qbytes = in->msg_qbytes;
ipc/msg.c
713
v.msg_lspid = in->msg_lspid;
ipc/msg.c
714
v.msg_lrpid = in->msg_lrpid;
ipc/msg.c
715
return copy_to_user(buf, &v, sizeof(v));
ipc/msg.c
717
struct compat_msqid_ds v;
ipc/msg.c
718
memset(&v, 0, sizeof(v));
ipc/msg.c
719
to_compat_ipc_perm(&v.msg_perm, &in->msg_perm);
ipc/msg.c
720
v.msg_stime = in->msg_stime;
ipc/msg.c
721
v.msg_rtime = in->msg_rtime;
ipc/msg.c
722
v.msg_ctime = in->msg_ctime;
ipc/msg.c
723
v.msg_cbytes = in->msg_cbytes;
ipc/msg.c
724
v.msg_qnum = in->msg_qnum;
ipc/msg.c
725
v.msg_qbytes = in->msg_qbytes;
ipc/msg.c
726
v.msg_lspid = in->msg_lspid;
ipc/msg.c
727
v.msg_lrpid = in->msg_lrpid;
ipc/msg.c
728
return copy_to_user(buf, &v, sizeof(v));
ipc/sem.c
1754
struct compat_semid64_ds v;
ipc/sem.c
1755
memset(&v, 0, sizeof(v));
ipc/sem.c
1756
to_compat_ipc64_perm(&v.sem_perm, &in->sem_perm);
ipc/sem.c
1757
v.sem_otime = lower_32_bits(in->sem_otime);
ipc/sem.c
1758
v.sem_otime_high = upper_32_bits(in->sem_otime);
ipc/sem.c
1759
v.sem_ctime = lower_32_bits(in->sem_ctime);
ipc/sem.c
1760
v.sem_ctime_high = upper_32_bits(in->sem_ctime);
ipc/sem.c
1761
v.sem_nsems = in->sem_nsems;
ipc/sem.c
1762
return copy_to_user(buf, &v, sizeof(v));
ipc/sem.c
1764
struct compat_semid_ds v;
ipc/sem.c
1765
memset(&v, 0, sizeof(v));
ipc/sem.c
1766
to_compat_ipc_perm(&v.sem_perm, &in->sem_perm);
ipc/sem.c
1767
v.sem_otime = in->sem_otime;
ipc/sem.c
1768
v.sem_ctime = in->sem_ctime;
ipc/sem.c
1769
v.sem_nsems = in->sem_nsems;
ipc/sem.c
1770
return copy_to_user(buf, &v, sizeof(v));
ipc/shm.c
1394
struct compat_shmid64_ds v;
ipc/shm.c
1395
memset(&v, 0, sizeof(v));
ipc/shm.c
1396
to_compat_ipc64_perm(&v.shm_perm, &in->shm_perm);
ipc/shm.c
1397
v.shm_atime = lower_32_bits(in->shm_atime);
ipc/shm.c
1398
v.shm_atime_high = upper_32_bits(in->shm_atime);
ipc/shm.c
1399
v.shm_dtime = lower_32_bits(in->shm_dtime);
ipc/shm.c
1400
v.shm_dtime_high = upper_32_bits(in->shm_dtime);
ipc/shm.c
1401
v.shm_ctime = lower_32_bits(in->shm_ctime);
ipc/shm.c
1402
v.shm_ctime_high = upper_32_bits(in->shm_ctime);
ipc/shm.c
1403
v.shm_segsz = in->shm_segsz;
ipc/shm.c
1404
v.shm_nattch = in->shm_nattch;
ipc/shm.c
1405
v.shm_cpid = in->shm_cpid;
ipc/shm.c
1406
v.shm_lpid = in->shm_lpid;
ipc/shm.c
1407
return copy_to_user(buf, &v, sizeof(v));
ipc/shm.c
1409
struct compat_shmid_ds v;
ipc/shm.c
1410
memset(&v, 0, sizeof(v));
ipc/shm.c
1411
to_compat_ipc_perm(&v.shm_perm, &in->shm_perm);
ipc/shm.c
1412
v.shm_perm.key = in->shm_perm.key;
ipc/shm.c
1413
v.shm_atime = in->shm_atime;
ipc/shm.c
1414
v.shm_dtime = in->shm_dtime;
ipc/shm.c
1415
v.shm_ctime = in->shm_ctime;
ipc/shm.c
1416
v.shm_segsz = in->shm_segsz;
ipc/shm.c
1417
v.shm_nattch = in->shm_nattch;
ipc/shm.c
1418
v.shm_cpid = in->shm_cpid;
ipc/shm.c
1419
v.shm_lpid = in->shm_lpid;
ipc/shm.c
1420
return copy_to_user(buf, &v, sizeof(v));
kernel/bpf/arraymap.c
628
static void *bpf_array_map_seq_next(struct seq_file *seq, void *v, loff_t *pos)
kernel/bpf/arraymap.c
647
static int __bpf_array_map_seq_show(struct seq_file *seq, void *v)
kernel/bpf/arraymap.c
660
prog = bpf_iter_get_info(&meta, v == NULL);
kernel/bpf/arraymap.c
666
if (v) {
kernel/bpf/arraymap.c
670
ctx.value = v;
kernel/bpf/arraymap.c
672
pptr = (void __percpu *)(uintptr_t)v;
kernel/bpf/arraymap.c
687
static int bpf_array_map_seq_show(struct seq_file *seq, void *v)
kernel/bpf/arraymap.c
689
return __bpf_array_map_seq_show(seq, v);
kernel/bpf/arraymap.c
692
static void bpf_array_map_seq_stop(struct seq_file *seq, void *v)
kernel/bpf/arraymap.c
694
if (!v)
kernel/bpf/btf.c
2001
struct resolve_vertex *v;
kernel/bpf/btf.c
2012
v = &env->stack[env->top_stack++];
kernel/bpf/btf.c
2013
v->t = t;
kernel/bpf/btf.c
2014
v->type_id = type_id;
kernel/bpf/btf.c
2015
v->next_member = 0;
kernel/bpf/btf.c
2258
const struct resolve_vertex *v)
kernel/bpf/btf.c
2260
btf_verifier_log_basic(env, v->t, "Unsupported resolve");
kernel/bpf/btf.c
2755
const struct resolve_vertex *v)
kernel/bpf/btf.c
2757
const struct btf_type *t = v->t;
kernel/bpf/btf.c
2764
btf_verifier_log_type(env, v->t, "Invalid type_id");
kernel/bpf/btf.c
2786
btf_verifier_log_type(env, v->t, "Invalid type_id");
kernel/bpf/btf.c
2797
const struct resolve_vertex *v)
kernel/bpf/btf.c
2800
const struct btf_type *t = v->t;
kernel/bpf/btf.c
2806
btf_verifier_log_type(env, v->t, "Invalid type_id");
kernel/bpf/btf.c
2833
btf_verifier_log_type(env, v->t, "Invalid type_id");
kernel/bpf/btf.c
2843
const struct resolve_vertex *v)
kernel/bpf/btf.c
2846
const struct btf_type *t = v->t;
kernel/bpf/btf.c
2852
btf_verifier_log_type(env, v->t, "Invalid type_id");
kernel/bpf/btf.c
2889
btf_verifier_log_type(env, v->t, "Invalid type_id");
kernel/bpf/btf.c
3087
const struct resolve_vertex *v)
kernel/bpf/btf.c
3089
const struct btf_array *array = btf_type_array(v->t);
kernel/bpf/btf.c
3100
btf_verifier_log_type(env, v->t, "Invalid index");
kernel/bpf/btf.c
3111
btf_verifier_log_type(env, v->t, "Invalid index");
kernel/bpf/btf.c
3120
btf_verifier_log_type(env, v->t,
kernel/bpf/btf.c
3131
btf_verifier_log_type(env, v->t, "Invalid elem");
kernel/bpf/btf.c
3136
btf_verifier_log_type(env, v->t, "Invalid array of int");
kernel/bpf/btf.c
3141
btf_verifier_log_type(env, v->t,
kernel/bpf/btf.c
3362
const struct resolve_vertex *v)
kernel/bpf/btf.c
3372
if (v->next_member) {
kernel/bpf/btf.c
3377
last_member = btf_type_member(v->t) + v->next_member - 1;
kernel/bpf/btf.c
3385
if (btf_type_kflag(v->t))
kernel/bpf/btf.c
3386
err = btf_type_ops(last_member_type)->check_kflag_member(env, v->t,
kernel/bpf/btf.c
3390
err = btf_type_ops(last_member_type)->check_member(env, v->t,
kernel/bpf/btf.c
3397
for_each_member_from(i, v->next_member, v->t, member) {
kernel/bpf/btf.c
3404
btf_verifier_log_member(env, v->t, member,
kernel/bpf/btf.c
3415
if (btf_type_kflag(v->t))
kernel/bpf/btf.c
3416
err = btf_type_ops(member_type)->check_kflag_member(env, v->t,
kernel/bpf/btf.c
3420
err = btf_type_ops(member_type)->check_member(env, v->t,
kernel/bpf/btf.c
450
const struct resolve_vertex *v);
kernel/bpf/btf.c
4509
int v;
kernel/bpf/btf.c
4515
v = *(int *)safe_data;
kernel/bpf/btf.c
4518
if (v != enums[i].val)
kernel/bpf/btf.c
4530
btf_show_type_value(show, "%d", v);
kernel/bpf/btf.c
4532
btf_show_type_value(show, "%u", v);
kernel/bpf/btf.c
4612
s64 v;
kernel/bpf/btf.c
4618
v = *(u64 *)safe_data;
kernel/bpf/btf.c
4621
if (v != btf_enum64_value(enums + i))
kernel/bpf/btf.c
4633
btf_show_type_value(show, "%lld", v);
kernel/bpf/btf.c
4635
btf_show_type_value(show, "%llu", v);
kernel/bpf/btf.c
4761
const struct resolve_vertex *v)
kernel/bpf/btf.c
4763
const struct btf_type *t = v->t;
kernel/bpf/btf.c
4922
const struct resolve_vertex *v)
kernel/bpf/btf.c
4929
for_each_vsi_from(i, v->next_member, v->t, vsi) {
kernel/bpf/btf.c
4934
btf_verifier_log_vsi(env, v->t, vsi,
kernel/bpf/btf.c
4947
btf_verifier_log_vsi(env, v->t, vsi, "Invalid type");
kernel/bpf/btf.c
4952
btf_verifier_log_vsi(env, v->t, vsi, "Invalid size");
kernel/bpf/btf.c
5114
const struct resolve_vertex *v)
kernel/bpf/btf.c
5117
const struct btf_type *t = v->t;
kernel/bpf/btf.c
5125
btf_verifier_log_type(env, v->t, "Invalid type_id");
kernel/bpf/btf.c
5136
btf_verifier_log_type(env, v->t, "Invalid component_idx");
kernel/bpf/btf.c
5149
btf_verifier_log_type(env, v->t, "Invalid component_idx");
kernel/bpf/btf.c
5433
const struct resolve_vertex *v;
kernel/bpf/btf.c
5438
while (!err && (v = env_stack_peak(env))) {
kernel/bpf/btf.c
5439
env->log_type_id = v->type_id;
kernel/bpf/btf.c
5440
err = btf_type_ops(v->t)->resolve(env, v);
kernel/bpf/cgroup_iter.c
104
static void *cgroup_iter_seq_next(struct seq_file *seq, void *v, loff_t *pos)
kernel/bpf/cgroup_iter.c
106
struct cgroup_subsys_state *curr = (struct cgroup_subsys_state *)v;
kernel/bpf/cgroup_iter.c
152
static int cgroup_iter_seq_show(struct seq_file *seq, void *v)
kernel/bpf/cgroup_iter.c
154
return __cgroup_iter_seq_show(seq, (struct cgroup_subsys_state *)v,
kernel/bpf/cgroup_iter.c
91
static void cgroup_iter_seq_stop(struct seq_file *seq, void *v)
kernel/bpf/cgroup_iter.c
98
if (!v) {
kernel/bpf/dmabuf_iter.c
40
static void *dmabuf_iter_seq_next(struct seq_file *seq, void *v, loff_t *pos)
kernel/bpf/dmabuf_iter.c
42
struct dma_buf *dmabuf = v;
kernel/bpf/dmabuf_iter.c
54
static int __dmabuf_seq_show(struct seq_file *seq, void *v, bool in_stop)
kernel/bpf/dmabuf_iter.c
61
.dmabuf = v,
kernel/bpf/dmabuf_iter.c
71
static int dmabuf_iter_seq_show(struct seq_file *seq, void *v)
kernel/bpf/dmabuf_iter.c
73
return __dmabuf_seq_show(seq, v, false);
kernel/bpf/dmabuf_iter.c
76
static void dmabuf_iter_seq_stop(struct seq_file *seq, void *v)
kernel/bpf/dmabuf_iter.c
78
struct dma_buf *dmabuf = v;
kernel/bpf/hashtab.c
2153
static void *bpf_hash_map_seq_next(struct seq_file *seq, void *v, loff_t *pos)
kernel/bpf/hashtab.c
2159
return bpf_hash_map_seq_find_next(info, v);
kernel/bpf/hashtab.c
2200
static int bpf_hash_map_seq_show(struct seq_file *seq, void *v)
kernel/bpf/hashtab.c
2202
return __bpf_hash_map_seq_show(seq, v);
kernel/bpf/hashtab.c
2205
static void bpf_hash_map_seq_stop(struct seq_file *seq, void *v)
kernel/bpf/hashtab.c
2207
if (!v)
kernel/bpf/inode.c
213
static void *map_seq_next(struct seq_file *m, void *v, loff_t *pos)
kernel/bpf/inode.c
223
if (unlikely(v == SEQ_START_TOKEN))
kernel/bpf/inode.c
245
static void map_seq_stop(struct seq_file *m, void *v)
kernel/bpf/inode.c
249
static int map_seq_show(struct seq_file *m, void *v)
kernel/bpf/inode.c
254
if (unlikely(v == SEQ_START_TOKEN)) {
kernel/bpf/kmem_cache_iter.c
152
static void kmem_cache_iter_seq_stop(struct seq_file *seq, void *v)
kernel/bpf/kmem_cache_iter.c
157
.s = v,
kernel/bpf/kmem_cache_iter.c
170
static void *kmem_cache_iter_seq_next(struct seq_file *seq, void *v, loff_t *pos)
kernel/bpf/kmem_cache_iter.c
179
static int kmem_cache_iter_seq_show(struct seq_file *seq, void *v)
kernel/bpf/kmem_cache_iter.c
184
.s = v,
kernel/bpf/link_iter.c
27
static void *bpf_link_seq_next(struct seq_file *seq, void *v, loff_t *pos)
kernel/bpf/link_iter.c
33
bpf_link_put((struct bpf_link *)v);
kernel/bpf/link_iter.c
44
static int __bpf_link_seq_show(struct seq_file *seq, void *v, bool in_stop)
kernel/bpf/link_iter.c
52
ctx.link = v;
kernel/bpf/link_iter.c
61
static int bpf_link_seq_show(struct seq_file *seq, void *v)
kernel/bpf/link_iter.c
63
return __bpf_link_seq_show(seq, v, false);
kernel/bpf/link_iter.c
66
static void bpf_link_seq_stop(struct seq_file *seq, void *v)
kernel/bpf/link_iter.c
68
if (!v)
kernel/bpf/link_iter.c
69
(void)__bpf_link_seq_show(seq, v, true);
kernel/bpf/link_iter.c
71
bpf_link_put((struct bpf_link *)v);
kernel/bpf/map_iter.c
27
static void *bpf_map_seq_next(struct seq_file *seq, void *v, loff_t *pos)
kernel/bpf/map_iter.c
33
bpf_map_put((struct bpf_map *)v);
kernel/bpf/map_iter.c
44
static int __bpf_map_seq_show(struct seq_file *seq, void *v, bool in_stop)
kernel/bpf/map_iter.c
52
ctx.map = v;
kernel/bpf/map_iter.c
61
static int bpf_map_seq_show(struct seq_file *seq, void *v)
kernel/bpf/map_iter.c
63
return __bpf_map_seq_show(seq, v, false);
kernel/bpf/map_iter.c
66
static void bpf_map_seq_stop(struct seq_file *seq, void *v)
kernel/bpf/map_iter.c
68
if (!v)
kernel/bpf/map_iter.c
69
(void)__bpf_map_seq_show(seq, v, true);
kernel/bpf/map_iter.c
71
bpf_map_put((struct bpf_map *)v);
kernel/bpf/prog_iter.c
27
static void *bpf_prog_seq_next(struct seq_file *seq, void *v, loff_t *pos)
kernel/bpf/prog_iter.c
33
bpf_prog_put((struct bpf_prog *)v);
kernel/bpf/prog_iter.c
44
static int __bpf_prog_seq_show(struct seq_file *seq, void *v, bool in_stop)
kernel/bpf/prog_iter.c
52
ctx.prog = v;
kernel/bpf/prog_iter.c
61
static int bpf_prog_seq_show(struct seq_file *seq, void *v)
kernel/bpf/prog_iter.c
63
return __bpf_prog_seq_show(seq, v, false);
kernel/bpf/prog_iter.c
66
static void bpf_prog_seq_stop(struct seq_file *seq, void *v)
kernel/bpf/prog_iter.c
68
if (!v)
kernel/bpf/prog_iter.c
69
(void)__bpf_prog_seq_show(seq, v, true);
kernel/bpf/prog_iter.c
71
bpf_prog_put((struct bpf_prog *)v);
kernel/bpf/rqspinlock.c
308
#define res_smp_cond_load_acquire(v, c) smp_cond_load_acquire(v, c)
kernel/bpf/rqspinlock.c
311
#define res_atomic_cond_read_acquire(v, c) res_smp_cond_load_acquire(&(v)->counter, (c))
kernel/bpf/task_iter.c
153
static void *task_seq_next(struct seq_file *seq, void *v, loff_t *pos)
kernel/bpf/task_iter.c
160
put_task_struct((struct task_struct *)v);
kernel/bpf/task_iter.c
192
static int task_seq_show(struct seq_file *seq, void *v)
kernel/bpf/task_iter.c
194
return __task_seq_show(seq, v, false);
kernel/bpf/task_iter.c
197
static void task_seq_stop(struct seq_file *seq, void *v)
kernel/bpf/task_iter.c
199
if (!v)
kernel/bpf/task_iter.c
200
(void)__task_seq_show(seq, v, true);
kernel/bpf/task_iter.c
202
put_task_struct((struct task_struct *)v);
kernel/bpf/task_iter.c
322
static void *task_file_seq_next(struct seq_file *seq, void *v, loff_t *pos)
kernel/bpf/task_iter.c
328
fput((struct file *)v);
kernel/bpf/task_iter.c
363
static int task_file_seq_show(struct seq_file *seq, void *v)
kernel/bpf/task_iter.c
365
return __task_file_seq_show(seq, v, false);
kernel/bpf/task_iter.c
368
static void task_file_seq_stop(struct seq_file *seq, void *v)
kernel/bpf/task_iter.c
372
if (!v) {
kernel/bpf/task_iter.c
373
(void)__task_file_seq_show(seq, v, true);
kernel/bpf/task_iter.c
375
fput((struct file *)v);
kernel/bpf/task_iter.c
589
static void *task_vma_seq_next(struct seq_file *seq, void *v, loff_t *pos)
kernel/bpf/task_iter.c
624
static int task_vma_seq_show(struct seq_file *seq, void *v)
kernel/bpf/task_iter.c
629
static void task_vma_seq_stop(struct seq_file *seq, void *v)
kernel/bpf/task_iter.c
633
if (!v) {
kernel/bpf/tnum.c
104
u64 v, mu;
kernel/bpf/tnum.c
106
v = a.value | b.value;
kernel/bpf/tnum.c
108
return TNUM(v, mu & ~v);
kernel/bpf/tnum.c
113
u64 v, mu;
kernel/bpf/tnum.c
115
v = a.value ^ b.value;
kernel/bpf/tnum.c
117
return TNUM(v & ~mu, mu);
kernel/bpf/tnum.c
176
u64 v, mu;
kernel/bpf/tnum.c
178
v = a.value | b.value;
kernel/bpf/tnum.c
180
return TNUM(v & ~mu, mu);
kernel/bpf/tnum.c
190
u64 v = a.value & b.value;
kernel/bpf/tnum.c
193
return TNUM(v & ~mu, mu);
kernel/bpf/tnum.c
289
u64 tmax, j, p, q, r, s, v, u, w, res;
kernel/bpf/tnum.c
311
v = r | s;
kernel/bpf/tnum.c
312
res = v;
kernel/bpf/tnum.c
319
v = r | s;
kernel/bpf/tnum.c
321
u = v + (1ULL << k);
kernel/bpf/tnum.c
94
u64 alpha, beta, v;
kernel/bpf/tnum.c
98
v = a.value & b.value;
kernel/bpf/tnum.c
99
return TNUM(v, alpha & beta & ~v);
kernel/cgroup/cgroup-internal.h
293
int proc_cgroupstats_show(struct seq_file *m, void *v);
kernel/cgroup/cgroup-v1.c
458
static void cgroup_pidlist_stop(struct seq_file *s, void *v)
kernel/cgroup/cgroup-v1.c
470
static void *cgroup_pidlist_next(struct seq_file *s, void *v, loff_t *pos)
kernel/cgroup/cgroup-v1.c
475
pid_t *p = v;
kernel/cgroup/cgroup-v1.c
491
static int cgroup_pidlist_show(struct seq_file *s, void *v)
kernel/cgroup/cgroup-v1.c
493
seq_printf(s, "%d\n", *(int *)v);
kernel/cgroup/cgroup-v1.c
582
static int cgroup_release_agent_show(struct seq_file *seq, void *v)
kernel/cgroup/cgroup-v1.c
593
static int cgroup_sane_behavior_show(struct seq_file *seq, void *v)
kernel/cgroup/cgroup-v1.c
677
int proc_cgroupstats_show(struct seq_file *m, void *v)
kernel/cgroup/cgroup.c
3153
static int cgroup_controllers_show(struct seq_file *seq, void *v)
kernel/cgroup/cgroup.c
3162
static int cgroup_subtree_control_show(struct seq_file *seq, void *v)
kernel/cgroup/cgroup.c
3693
static int cgroup_type_show(struct seq_file *seq, void *v)
kernel/cgroup/cgroup.c
3731
static int cgroup_max_descendants_show(struct seq_file *seq, void *v)
kernel/cgroup/cgroup.c
3774
static int cgroup_max_depth_show(struct seq_file *seq, void *v)
kernel/cgroup/cgroup.c
3817
static int cgroup_events_show(struct seq_file *seq, void *v)
kernel/cgroup/cgroup.c
3827
static int cgroup_stat_show(struct seq_file *seq, void *v)
kernel/cgroup/cgroup.c
3867
static int cgroup_core_local_stat_show(struct seq_file *seq, void *v)
kernel/cgroup/cgroup.c
3950
static int cpu_stat_show(struct seq_file *seq, void *v)
kernel/cgroup/cgroup.c
3961
static int cpu_local_stat_show(struct seq_file *seq, void *v)
kernel/cgroup/cgroup.c
3973
static int cgroup_io_pressure_show(struct seq_file *seq, void *v)
kernel/cgroup/cgroup.c
3980
static int cgroup_memory_pressure_show(struct seq_file *seq, void *v)
kernel/cgroup/cgroup.c
3987
static int cgroup_cpu_pressure_show(struct seq_file *seq, void *v)
kernel/cgroup/cgroup.c
4051
static int cgroup_irq_pressure_show(struct seq_file *seq, void *v)
kernel/cgroup/cgroup.c
4067
static int cgroup_pressure_show(struct seq_file *seq, void *v)
kernel/cgroup/cgroup.c
4146
static int cgroup_freeze_show(struct seq_file *seq, void *v)
kernel/cgroup/cgroup.c
4324
unsigned long long v;
kernel/cgroup/cgroup.c
4325
ret = kstrtoull(buf, 0, &v);
kernel/cgroup/cgroup.c
4327
ret = cft->write_u64(css, cft, v);
kernel/cgroup/cgroup.c
4329
long long v;
kernel/cgroup/cgroup.c
4330
ret = kstrtoll(buf, 0, &v);
kernel/cgroup/cgroup.c
4332
ret = cft->write_s64(css, cft, v);
kernel/cgroup/cgroup.c
4355
static void *cgroup_seqfile_next(struct seq_file *seq, void *v, loff_t *ppos)
kernel/cgroup/cgroup.c
4357
return seq_cft(seq)->seq_next(seq, v, ppos);
kernel/cgroup/cgroup.c
4360
static void cgroup_seqfile_stop(struct seq_file *seq, void *v)
kernel/cgroup/cgroup.c
4363
seq_cft(seq)->seq_stop(seq, v);
kernel/cgroup/cgroup.c
5238
static void *cgroup_procs_next(struct seq_file *s, void *v, loff_t *pos)
kernel/cgroup/cgroup.c
5292
static int cgroup_procs_show(struct seq_file *s, void *v)
kernel/cgroup/cgroup.c
5294
seq_printf(s, "%d\n", task_pid_vnr(v));
kernel/cgroup/cgroup.c
7362
u64 v = 1;
kernel/cgroup/cgroup.c
7364
v *= 10;
kernel/cgroup/cgroup.c
7365
return v;
kernel/cgroup/cgroup.c
7382
int cgroup_parse_float(const char *input, unsigned dec_shift, s64 *v)
kernel/cgroup/cgroup.c
7398
*v = whole * power_of_ten(dec_shift) + frac;
kernel/cgroup/cpuset-internal.h
308
int cpuset_common_seq_show(struct seq_file *sf, void *v);
kernel/cgroup/cpuset.c
3260
int cpuset_common_seq_show(struct seq_file *sf, void *v)
kernel/cgroup/cpuset.c
3301
static int cpuset_partition_show(struct seq_file *seq, void *v)
kernel/cgroup/debug.c
110
static int cgroup_css_links_read(struct seq_file *seq, void *v)
kernel/cgroup/debug.c
199
static int cgroup_subsys_states_read(struct seq_file *seq, void *v)
kernel/cgroup/debug.c
251
static int cgroup_masks_read(struct seq_file *seq, void *v)
kernel/cgroup/debug.c
40
static int current_css_set_read(struct seq_file *seq, void *v)
kernel/cgroup/debug.c
85
static int current_css_set_cg_links_read(struct seq_file *seq, void *v)
kernel/cgroup/dmem.c
697
static int dmem_cgroup_region_capacity_show(struct seq_file *sf, void *v)
kernel/cgroup/dmem.c
787
static int dmemcg_limit_show(struct seq_file *sf, void *v,
kernel/cgroup/dmem.c
811
static int dmem_cgroup_region_current_show(struct seq_file *sf, void *v)
kernel/cgroup/dmem.c
813
return dmemcg_limit_show(sf, v, get_resource_current);
kernel/cgroup/dmem.c
816
static int dmem_cgroup_region_min_show(struct seq_file *sf, void *v)
kernel/cgroup/dmem.c
818
return dmemcg_limit_show(sf, v, get_resource_min);
kernel/cgroup/dmem.c
827
static int dmem_cgroup_region_low_show(struct seq_file *sf, void *v)
kernel/cgroup/dmem.c
829
return dmemcg_limit_show(sf, v, get_resource_low);
kernel/cgroup/dmem.c
838
static int dmem_cgroup_region_max_show(struct seq_file *sf, void *v)
kernel/cgroup/dmem.c
840
return dmemcg_limit_show(sf, v, get_resource_max);
kernel/cgroup/legacy_freezer.c
280
static int freezer_read(struct seq_file *m, void *v)
kernel/cgroup/misc.c
216
static int misc_cg_max_show(struct seq_file *sf, void *v)
kernel/cgroup/misc.c
305
static int misc_cg_current_show(struct seq_file *sf, void *v)
kernel/cgroup/misc.c
328
static int misc_cg_peak_show(struct seq_file *sf, void *v)
kernel/cgroup/misc.c
353
static int misc_cg_capacity_show(struct seq_file *sf, void *v)
kernel/cgroup/misc.c
384
static int misc_events_show(struct seq_file *sf, void *v)
kernel/cgroup/misc.c
389
static int misc_events_local_show(struct seq_file *sf, void *v)
kernel/cgroup/pids.c
331
static int pids_max_show(struct seq_file *sf, void *v)
kernel/cgroup/pids.c
378
static int pids_events_show(struct seq_file *sf, void *v)
kernel/cgroup/pids.c
384
static int pids_events_local_show(struct seq_file *sf, void *v)
kernel/cgroup/rdma.c
526
static int rdmacg_resource_read(struct seq_file *sf, void *v)
kernel/compat.c
253
compat_sigset_t v;
kernel/compat.c
254
if (copy_from_user(&v, compat, sizeof(compat_sigset_t)))
kernel/compat.c
257
case 4: set->sig[3] = v.sig[6] | (((long)v.sig[7]) << 32 );
kernel/compat.c
259
case 3: set->sig[2] = v.sig[4] | (((long)v.sig[5]) << 32 );
kernel/compat.c
261
case 2: set->sig[1] = v.sig[2] | (((long)v.sig[3]) << 32 );
kernel/compat.c
263
case 1: set->sig[0] = v.sig[0] | (((long)v.sig[1]) << 32 );
kernel/cpu.c
3204
bool cpu_attack_vector_mitigated(enum cpu_attack_vectors v)
kernel/cpu.c
3206
if (v < NR_CPU_ATTACK_VECTORS)
kernel/cpu.c
3207
return attack_vectors[v];
kernel/cpu.c
3209
WARN_ONCE(1, "Invalid attack vector %d\n", v);
kernel/dma.c
118
static int proc_dma_show(struct seq_file *m, void *v)
kernel/dma.c
131
static int proc_dma_show(struct seq_file *m, void *v)
kernel/dma/debug.c
564
static int dump_show(struct seq_file *seq, void *v)
kernel/events/core.c
15213
perf_reboot(struct notifier_block *notifier, unsigned long val, void *v)
kernel/events/uprobes.c
52
#define uprobes_mmap_hash(v) (&uprobes_mmap_mutex[((unsigned long)(v)) % UPROBES_HASH_SZ])
kernel/exec_domain.c
24
static int execdomains_proc_show(struct seq_file *m, void *v)
kernel/fail_function.c
189
static void fei_seq_stop(struct seq_file *m, void *v)
kernel/fail_function.c
194
static void *fei_seq_next(struct seq_file *m, void *v, loff_t *pos)
kernel/fail_function.c
196
return seq_list_next(v, &fei_attr_list, pos);
kernel/fail_function.c
199
static int fei_seq_show(struct seq_file *m, void *v)
kernel/fail_function.c
201
struct fei_attr *attr = list_entry(v, struct fei_attr, list);
kernel/futex/futex.h
436
extern int futex_unqueue_multiple(struct futex_vector *v, int count);
kernel/futex/waitwake.c
374
int futex_unqueue_multiple(struct futex_vector *v, int count)
kernel/futex/waitwake.c
379
if (!futex_unqueue(&v[i].q))
kernel/gcov/base.c
63
size_t store_gcov_u32(void *buffer, size_t off, u32 v)
kernel/gcov/base.c
69
*data = v;
kernel/gcov/base.c
87
size_t store_gcov_u64(void *buffer, size_t off, u64 v)
kernel/gcov/base.c
94
data[0] = (v & 0xffffffffUL);
kernel/gcov/base.c
95
data[1] = (v >> 32);
kernel/gcov/gcov.h
63
size_t store_gcov_u32(void *buffer, size_t off, u32 v);
kernel/gcov/gcov.h
64
size_t store_gcov_u64(void *buffer, size_t off, u64 v);
kernel/irq/proc.c
103
static int irq_affinity_proc_show(struct seq_file *m, void *v)
kernel/irq/proc.c
108
static int irq_affinity_list_proc_show(struct seq_file *m, void *v)
kernel/irq/proc.c
217
static int irq_effective_aff_proc_show(struct seq_file *m, void *v)
kernel/irq/proc.c
222
static int irq_effective_aff_list_proc_show(struct seq_file *m, void *v)
kernel/irq/proc.c
228
static int default_affinity_show(struct seq_file *m, void *v)
kernel/irq/proc.c
278
static int irq_node_proc_show(struct seq_file *m, void *v)
kernel/irq/proc.c
287
static int irq_spurious_proc_show(struct seq_file *m, void *v)
kernel/irq/proc.c
453
int show_interrupts(struct seq_file *p, void *v)
kernel/irq/proc.c
458
int i = *(loff_t *) v, j;
kernel/irq/proc.c
84
static int irq_affinity_hint_proc_show(struct seq_file *m, void *v)
kernel/jump_label.c
129
int v;
kernel/jump_label.c
141
v = atomic_read(&key->enabled);
kernel/jump_label.c
143
if (v <= 0 || v == INT_MAX)
kernel/jump_label.c
145
} while (!likely(atomic_try_cmpxchg(&key->enabled, &v, v + 1)));
kernel/jump_label.c
255
int v;
kernel/jump_label.c
268
v = atomic_read(&key->enabled);
kernel/jump_label.c
276
WARN_ON_ONCE(v < 0);
kernel/jump_label.c
282
if (WARN_ON_ONCE(v == 0))
kernel/jump_label.c
285
if (v <= 1)
kernel/jump_label.c
287
} while (!likely(atomic_try_cmpxchg(&key->enabled, &v, v - 1)));
kernel/kcmp.c
39
static long kptr_obfuscate(long v, int type)
kernel/kcmp.c
41
return (v ^ cookies[type][0]) * cookies[type][1];
kernel/kcsan/core.c
1181
void __tsan_atomic##bits##_store(u##bits *ptr, u##bits v, int memorder); \
kernel/kcsan/core.c
1182
void __tsan_atomic##bits##_store(u##bits *ptr, u##bits v, int memorder) \
kernel/kcsan/core.c
1189
__atomic_store_n(ptr, v, memorder); \
kernel/kcsan/core.c
1194
u##bits __tsan_atomic##bits##_##op(u##bits *ptr, u##bits v, int memorder); \
kernel/kcsan/core.c
1195
u##bits __tsan_atomic##bits##_##op(u##bits *ptr, u##bits v, int memorder) \
kernel/kcsan/core.c
1203
return __atomic_##op##suffix(ptr, v, memorder); \
kernel/kcsan/debugfs.c
191
static int show_info(struct seq_file *file, void *v)
kernel/kcsan/kcsan_test.c
317
static noinline void sink_value(long v) { WRITE_ONCE(test_sink, v); }
kernel/kcsan/kcsan_test.c
496
long v = 0; \
kernel/kcsan/kcsan_test.c
499
while (v++ < 100) { \
kernel/kcsan/kcsan_test.c
514
__atomic_compare_exchange_n(flag, &v, 1, 0, __ATOMIC_ACQUIRE, __ATOMIC_RELAXED),
kernel/kcsan/kcsan_test.c
517
__atomic_compare_exchange_n(flag, &v, 1, 0, __ATOMIC_RELAXED, __ATOMIC_RELAXED),
kernel/kprobes.c
2842
static void *kprobe_seq_next(struct seq_file *f, void *v, loff_t *pos)
kernel/kprobes.c
2850
static void kprobe_seq_stop(struct seq_file *f, void *v)
kernel/kprobes.c
2855
static int show_kprobe_addr(struct seq_file *pi, void *v)
kernel/kprobes.c
2860
unsigned int i = *(loff_t *) v;
kernel/kprobes.c
2895
static void *kprobe_blacklist_seq_next(struct seq_file *m, void *v, loff_t *pos)
kernel/kprobes.c
2897
return seq_list_next(v, &kprobe_blacklist, pos);
kernel/kprobes.c
2900
static int kprobe_blacklist_seq_show(struct seq_file *m, void *v)
kernel/kprobes.c
2903
list_entry(v, struct kprobe_blacklist_entry, list);
kernel/kprobes.c
2918
static void kprobe_blacklist_seq_stop(struct seq_file *f, void *v)
kernel/latencytop.c
242
static int lstats_show(struct seq_file *m, void *v)
kernel/liveupdate/kexec_handover_debugfs.c
105
static int scratch_len_show(struct seq_file *m, void *v)
kernel/liveupdate/kexec_handover_debugfs.c
96
static int scratch_phys_show(struct seq_file *m, void *v)
kernel/locking/lockdep_proc.c
139
static void *lc_next(struct seq_file *m, void *v, loff_t *pos)
kernel/locking/lockdep_proc.c
145
static void lc_stop(struct seq_file *m, void *v)
kernel/locking/lockdep_proc.c
149
static int lc_show(struct seq_file *m, void *v)
kernel/locking/lockdep_proc.c
151
struct lock_chain *chain = v;
kernel/locking/lockdep_proc.c
162
if (v == SEQ_START_TOKEN) {
kernel/locking/lockdep_proc.c
231
static int lockdep_stats_show(struct seq_file *m, void *v)
kernel/locking/lockdep_proc.c
38
static void *l_next(struct seq_file *m, void *v, loff_t *pos)
kernel/locking/lockdep_proc.c
40
struct lock_class *class = v;
kernel/locking/lockdep_proc.c
56
static void l_stop(struct seq_file *m, void *v)
kernel/locking/lockdep_proc.c
614
static void *ls_next(struct seq_file *m, void *v, loff_t *pos)
kernel/locking/lockdep_proc.c
620
static void ls_stop(struct seq_file *m, void *v)
kernel/locking/lockdep_proc.c
624
static int ls_show(struct seq_file *m, void *v)
kernel/locking/lockdep_proc.c
626
if (v == SEQ_START_TOKEN)
kernel/locking/lockdep_proc.c
629
seq_stats(m, v);
kernel/locking/lockdep_proc.c
77
static int l_show(struct seq_file *m, void *v)
kernel/locking/lockdep_proc.c
79
struct lock_class *class = v;
kernel/locking/lockdep_proc.c
84
if (v == lock_classes)
kernel/locking/qspinlock_stat.h
134
#define pv_wait(p, v) __pv_wait(p, v)
kernel/notifier.c
116
void *v)
kernel/notifier.c
120
ret = notifier_call_chain(nl, val_up, v, -1, &nr);
kernel/notifier.c
122
notifier_call_chain(nl, val_down, v, nr-1, NULL);
kernel/notifier.c
218
unsigned long val, void *v)
kernel/notifier.c
223
ret = notifier_call_chain(&nh->head, val, v, -1, NULL);
kernel/notifier.c
334
unsigned long val_up, unsigned long val_down, void *v)
kernel/notifier.c
345
ret = notifier_call_chain_robust(&nh->head, val_up, val_down, v);
kernel/notifier.c
369
unsigned long val, void *v)
kernel/notifier.c
380
ret = notifier_call_chain(&nh->head, val, v, -1, NULL);
kernel/notifier.c
427
unsigned long val_up, unsigned long val_down, void *v)
kernel/notifier.c
429
return notifier_call_chain_robust(&nh->head, val_up, val_down, v);
kernel/notifier.c
451
unsigned long val, void *v)
kernel/notifier.c
453
return notifier_call_chain(&nh->head, val, v, -1, NULL);
kernel/notifier.c
540
unsigned long val, void *v)
kernel/notifier.c
546
ret = notifier_call_chain(&nh->head, val, v, -1, NULL);
kernel/notifier.c
66
unsigned long val, void *v,
kernel/notifier.c
85
ret = nb->notifier_call(nb, val, v);
kernel/params.c
396
bool v;
kernel/params.c
399
boolkp.arg = &v;
kernel/params.c
403
*(int *)kp->arg = v;
kernel/printk/index.c
116
static void pi_stop(struct seq_file *p, void *v) { }
kernel/printk/index.c
43
static void *pi_next(struct seq_file *s, void *v, loff_t *pos)
kernel/printk/index.c
73
static int pi_show(struct seq_file *s, void *v)
kernel/printk/index.c
75
const struct pi_entry *entry = v;
kernel/printk/index.c
80
if (v == SEQ_START_TOKEN) {
kernel/printk/printk.c
498
#define LOG_LEVEL(v) ((v) & 0x07)
kernel/printk/printk.c
499
#define LOG_FACILITY(v) ((v) >> 3 & 0xff)
kernel/rcu/rcu.h
689
int rcu_stall_notifier_call_chain(unsigned long val, void *v);
kernel/rcu/rcu.h
691
static inline int rcu_stall_notifier_call_chain(unsigned long val, void *v) { return NOTIFY_DONE; }
kernel/rcu/rcu_segcblist.c
110
static void rcu_segcblist_set_seglen(struct rcu_segcblist *rsclp, int seg, long v)
kernel/rcu/rcu_segcblist.c
112
WRITE_ONCE(rsclp->seglen[seg], v);
kernel/rcu/rcu_segcblist.c
116
static void rcu_segcblist_add_seglen(struct rcu_segcblist *rsclp, int seg, long v)
kernel/rcu/rcu_segcblist.c
118
WRITE_ONCE(rsclp->seglen[seg], rsclp->seglen[seg] + v);
kernel/rcu/rcu_segcblist.c
210
void rcu_segcblist_add_len(struct rcu_segcblist *rsclp, long v)
kernel/rcu/rcu_segcblist.c
214
atomic_long_add(v, &rsclp->len);
kernel/rcu/rcu_segcblist.c
218
WRITE_ONCE(rsclp->len, rsclp->len + v);
kernel/rcu/rcu_segcblist.c
82
static void rcu_segcblist_set_len(struct rcu_segcblist *rsclp, long v)
kernel/rcu/rcu_segcblist.c
85
atomic_long_set(&rsclp->len, v);
kernel/rcu/rcu_segcblist.c
87
WRITE_ONCE(rsclp->len, v);
kernel/rcu/rcu_segcblist.h
120
void rcu_segcblist_add_len(struct rcu_segcblist *rsclp, long v);
kernel/rcu/rcutorture.c
3012
static int rcu_torture_stall_nf(struct notifier_block *nb, unsigned long v, void *ptr)
kernel/rcu/rcutorture.c
3014
pr_info("%s: v=%lu, duration=%lu.\n", __func__, v, (unsigned long)ptr);
kernel/rcu/tree_stall.h
1180
int rcu_stall_notifier_call_chain(unsigned long val, void *v)
kernel/rcu/tree_stall.h
1182
return atomic_notifier_call_chain(&rcu_cpu_stall_notifier_list, val, v);
kernel/resource.c
111
static void *r_next(struct seq_file *m, void *v, loff_t *pos)
kernel/resource.c
113
struct resource *p = v;
kernel/resource.c
120
static void r_stop(struct seq_file *m, void *v)
kernel/resource.c
126
static int r_show(struct seq_file *m, void *v)
kernel/resource.c
129
struct resource *r = v, *p;
kernel/sched/core.c
10167
static int cpu_max_show(struct seq_file *sf, void *v)
kernel/sched/core.c
7278
#define fetch_and_set(x, v) ({ int _x = (x); (x) = (v); _x; })
kernel/sched/core.c
9455
static int cpu_uclamp_min_show(struct seq_file *sf, void *v)
kernel/sched/core.c
9461
static int cpu_uclamp_max_show(struct seq_file *sf, void *v)
kernel/sched/core.c
9690
static int cpu_cfs_stat_show(struct seq_file *sf, void *v)
kernel/sched/core.c
9730
static int cpu_cfs_local_stat_show(struct seq_file *sf, void *v)
kernel/sched/cpuacct.c
262
static int cpuacct_stats_show(struct seq_file *sf, void *v)
kernel/sched/debug.c
1143
static int sched_debug_show(struct seq_file *m, void *v)
kernel/sched/debug.c
1145
int cpu = (unsigned long)(v - 2);
kernel/sched/debug.c
193
static int sched_scaling_show(struct seq_file *m, void *v)
kernel/sched/debug.c
238
static int sched_dynamic_show(struct seq_file *m, void *v)
kernel/sched/debug.c
396
static size_t sched_server_show_common(struct seq_file *m, void *v, enum dl_param param,
kernel/sched/debug.c
426
static int sched_fair_server_runtime_show(struct seq_file *m, void *v)
kernel/sched/debug.c
431
return sched_server_show_common(m, v, DL_RUNTIME, &rq->fair_server);
kernel/sched/debug.c
459
static int sched_ext_server_runtime_show(struct seq_file *m, void *v)
kernel/sched/debug.c
464
return sched_server_show_common(m, v, DL_RUNTIME, &rq->ext_server);
kernel/sched/debug.c
492
static int sched_fair_server_period_show(struct seq_file *m, void *v)
kernel/sched/debug.c
497
return sched_server_show_common(m, v, DL_PERIOD, &rq->fair_server);
kernel/sched/debug.c
525
static int sched_ext_server_period_show(struct seq_file *m, void *v)
kernel/sched/debug.c
530
return sched_server_show_common(m, v, DL_PERIOD, &rq->ext_server);
kernel/sched/debug.c
59
static int sched_feat_show(struct seq_file *m, void *v)
kernel/sched/debug.c
641
static int sd_flags_show(struct seq_file *m, void *v)
kernel/sched/ext.c
5837
s32 cpu, v;
kernel/sched/ext.c
5844
WRITE_ONCE(v, SCX_ENQ_WAKEUP | SCX_DEQ_SLEEP | SCX_KICK_PREEMPT |
kernel/sched/psi.c
1507
static int psi_io_show(struct seq_file *m, void *v)
kernel/sched/psi.c
1512
static int psi_memory_show(struct seq_file *m, void *v)
kernel/sched/psi.c
1517
static int psi_cpu_show(struct seq_file *m, void *v)
kernel/sched/psi.c
1641
static int psi_irq_show(struct seq_file *m, void *v)
kernel/sched/rt.c
2159
static inline bool rto_start_trylock(atomic_t *v)
kernel/sched/rt.c
2161
return !atomic_cmpxchg_acquire(v, 0, 1);
kernel/sched/rt.c
2164
static inline void rto_start_unlock(atomic_t *v)
kernel/sched/rt.c
2166
atomic_set_release(v, 0);
kernel/sched/sched.h
239
#define cap_scale(v, s) ((v)*(s) >> SCHED_CAPACITY_SHIFT)
kernel/sched/stats.c
109
static int show_schedstat(struct seq_file *seq, void *v)
kernel/sched/stats.c
113
if (v == (void *)1) {
kernel/sched/stats.c
120
cpu = (unsigned long)(v - 2);
kernel/sys.c
1333
unsigned v;
kernel/sys.c
1343
v = LINUX_VERSION_PATCHLEVEL + 60;
kernel/sys.c
1345
copy = scnprintf(buf, copy, "2.6.%u%s", v, rest);
kernel/sysctl.c
209
static void proc_skip_char(char **buf, size_t *size, const char v)
kernel/sysctl.c
212
if (**buf != v)
kernel/time/itimer.c
103
struct __kernel_old_itimerval v;
kernel/time/itimer.c
105
v.it_interval.tv_sec = i->it_interval.tv_sec;
kernel/time/itimer.c
106
v.it_interval.tv_usec = i->it_interval.tv_nsec / NSEC_PER_USEC;
kernel/time/itimer.c
107
v.it_value.tv_sec = i->it_value.tv_sec;
kernel/time/itimer.c
108
v.it_value.tv_usec = i->it_value.tv_nsec / NSEC_PER_USEC;
kernel/time/itimer.c
109
return copy_to_user(o, &v, sizeof(struct __kernel_old_itimerval)) ? -EFAULT : 0;
kernel/time/itimer.c
274
struct itimerspec64 v = {};
kernel/time/itimer.c
278
do_setitimer(i, &v, NULL);
kernel/time/itimer.c
334
struct __kernel_old_itimerval v;
kernel/time/itimer.c
336
if (copy_from_user(&v, i, sizeof(struct __kernel_old_itimerval)))
kernel/time/itimer.c
340
if (!timeval_valid(&v.it_value) ||
kernel/time/itimer.c
341
!timeval_valid(&v.it_interval))
kernel/time/itimer.c
344
o->it_interval.tv_sec = v.it_interval.tv_sec;
kernel/time/itimer.c
345
o->it_interval.tv_nsec = v.it_interval.tv_usec * NSEC_PER_USEC;
kernel/time/itimer.c
346
o->it_value.tv_sec = v.it_value.tv_sec;
kernel/time/itimer.c
347
o->it_value.tv_nsec = v.it_value.tv_usec * NSEC_PER_USEC;
kernel/time/test_udelay.c
67
static int udelay_test_show(struct seq_file *s, void *v)
kernel/time/timer_list.c
286
static int timer_list_show(struct seq_file *m, void *v)
kernel/time/timer_list.c
288
struct timer_list_iter *iter = v;
kernel/time/timer_list.c
333
static void *timer_list_next(struct seq_file *file, void *v, loff_t *offset)
kernel/time/timer_list.c
340
static void timer_list_stop(struct seq_file *seq, void *v)
kernel/torture.c
816
bool torture_init_begin(char *ttype, int v)
kernel/torture.c
827
verbose = v;
kernel/trace/ftrace.c
4215
t_next(struct seq_file *m, void *v, loff_t *pos)
kernel/trace/ftrace.c
4462
static int t_show(struct seq_file *m, void *v)
kernel/trace/ftrace.c
456
function_stat_next(void *v, int idx)
kernel/trace/ftrace.c
458
struct ftrace_profile *rec = v;
kernel/trace/ftrace.c
534
static int function_stat_show(struct seq_file *m, void *v)
kernel/trace/ftrace.c
537
struct ftrace_profile *rec = v;
kernel/trace/ftrace.c
7100
g_next(struct seq_file *m, void *v, loff_t *pos)
kernel/trace/ftrace.c
7133
static int g_show(struct seq_file *m, void *v)
kernel/trace/ftrace.c
7135
struct ftrace_func_entry *entry = v;
kernel/trace/ftrace.c
8731
static void *fpid_next(struct seq_file *m, void *v, loff_t *pos)
kernel/trace/ftrace.c
8736
if (v == FTRACE_NO_PIDS) {
kernel/trace/ftrace.c
8740
return trace_pid_next(pid_list, v, pos);
kernel/trace/ftrace.c
8750
static int fpid_show(struct seq_file *m, void *v)
kernel/trace/ftrace.c
8752
if (v == FTRACE_NO_PIDS) {
kernel/trace/ftrace.c
8757
return trace_pid_show(m, v);
kernel/trace/ftrace.c
8784
static void *fnpid_next(struct seq_file *m, void *v, loff_t *pos)
kernel/trace/ftrace.c
8789
if (v == FTRACE_NO_PIDS) {
kernel/trace/ftrace.c
8793
return trace_pid_next(pid_list, v, pos);
kernel/trace/ring_buffer.c
2171
static void *rbm_next(struct seq_file *m, void *v, loff_t *pos)
kernel/trace/ring_buffer.c
2178
static int rbm_show(struct seq_file *m, void *v)
kernel/trace/ring_buffer.c
2182
unsigned long val = (unsigned long)v;
kernel/trace/trace.c
3162
static void *s_next(struct seq_file *m, void *v, loff_t *pos)
kernel/trace/trace.c
3807
static int s_show(struct seq_file *m, void *v)
kernel/trace/trace.c
3809
struct trace_iterator *iter = v;
kernel/trace/trace.c
4198
t_next(struct seq_file *m, void *v, loff_t *pos)
kernel/trace/trace.c
4201
struct tracer *t = v;
kernel/trace/trace.c
4231
static int t_show(struct seq_file *m, void *v)
kernel/trace/trace.c
4233
struct tracer *t = v;
kernel/trace/trace.c
4420
static int tracing_trace_options_show(struct seq_file *m, void *v)
kernel/trace/trace.c
5033
static void *eval_map_next(struct seq_file *m, void *v, loff_t *pos)
kernel/trace/trace.c
5035
union trace_eval_map_item *ptr = v;
kernel/trace/trace.c
5054
union trace_eval_map_item *v;
kernel/trace/trace.c
5059
v = trace_eval_maps;
kernel/trace/trace.c
5060
if (v)
kernel/trace/trace.c
5061
v++;
kernel/trace/trace.c
5063
while (v && l < *pos) {
kernel/trace/trace.c
5064
v = eval_map_next(m, v, &l);
kernel/trace/trace.c
5067
return v;
kernel/trace/trace.c
5070
static void eval_map_stop(struct seq_file *m, void *v)
kernel/trace/trace.c
5075
static int eval_map_show(struct seq_file *m, void *v)
kernel/trace/trace.c
5077
union trace_eval_map_item *ptr = v;
kernel/trace/trace.c
6346
static void *l_next(struct seq_file *m, void *v, loff_t *pos)
kernel/trace/trace.c
6399
static int l_show(struct seq_file *m, void *v)
kernel/trace/trace.c
6402
struct trace_mod_entry *entry = v;
kernel/trace/trace.c
6404
if (v == LAST_BOOT_HEADER) {
kernel/trace/trace.c
7009
static int tracing_clock_show(struct seq_file *m, void *v)
kernel/trace/trace.c
7107
static int tracing_time_stamp_mode_show(struct seq_file *m, void *v)
kernel/trace/trace.c
7712
static void *tracing_err_log_seq_next(struct seq_file *m, void *v, loff_t *pos)
kernel/trace/trace.c
7716
return seq_list_next(v, &tr->err_log, pos);
kernel/trace/trace.c
7719
static void tracing_err_log_seq_stop(struct seq_file *m, void *v)
kernel/trace/trace.c
7735
static int tracing_err_log_seq_show(struct seq_file *m, void *v)
kernel/trace/trace.c
7737
struct tracing_log_err *err = v;
kernel/trace/trace.h
793
void *trace_pid_next(struct trace_pid_list *pid_list, void *v, loff_t *pos);
kernel/trace/trace.h
795
int trace_pid_show(struct seq_file *m, void *v);
kernel/trace/trace_boot.c
30
unsigned long v = 0;
kernel/trace/trace_boot.c
45
if (kstrtoul(p, 10, &v))
kernel/trace/trace_boot.c
47
if (v)
kernel/trace/trace_boot.c
61
v = memparse(p, NULL);
kernel/trace/trace_boot.c
62
if (v < PAGE_SIZE)
kernel/trace/trace_boot.c
64
if (tracing_resize_ring_buffer(tr, v, RING_BUFFER_ALL_CPUS) < 0)
kernel/trace/trace_branch.c
291
static int annotate_branch_stat_show(struct seq_file *m, void *v)
kernel/trace/trace_branch.c
293
struct ftrace_likely_data *p = v;
kernel/trace/trace_branch.c
317
annotated_branch_stat_next(void *v, int idx)
kernel/trace/trace_branch.c
319
struct ftrace_likely_data *p = v;
kernel/trace/trace_branch.c
407
all_branch_stat_next(void *v, int idx)
kernel/trace/trace_branch.c
409
struct ftrace_branch_data *p = v;
kernel/trace/trace_branch.c
419
static int all_branch_stat_show(struct seq_file *m, void *v)
kernel/trace/trace_branch.c
421
struct ftrace_branch_data *p = v;
kernel/trace/trace_dynevent.c
170
void *dyn_event_seq_next(struct seq_file *m, void *v, loff_t *pos)
kernel/trace/trace_dynevent.c
172
return seq_list_next(v, &dyn_event_list, pos);
kernel/trace/trace_dynevent.c
175
void dyn_event_seq_stop(struct seq_file *m, void *v)
kernel/trace/trace_dynevent.c
180
static int dyn_event_seq_show(struct seq_file *m, void *v)
kernel/trace/trace_dynevent.c
182
struct dyn_event *ev = v;
kernel/trace/trace_dynevent.h
100
void dyn_event_seq_stop(struct seq_file *m, void *v);
kernel/trace/trace_dynevent.h
99
void *dyn_event_seq_next(struct seq_file *m, void *v, loff_t *pos);
kernel/trace/trace_events.c
1557
t_next(struct seq_file *m, void *v, loff_t *pos)
kernel/trace/trace_events.c
1559
struct trace_event_file *file = v;
kernel/trace/trace_events.c
1610
s_next(struct seq_file *m, void *v, loff_t *pos)
kernel/trace/trace_events.c
1612
struct set_event_iter *iter = v;
kernel/trace/trace_events.c
1669
static int t_show(struct seq_file *m, void *v)
kernel/trace/trace_events.c
1671
struct trace_event_file *file = v;
kernel/trace/trace_events.c
1707
static int t_show_filters(struct seq_file *m, void *v)
kernel/trace/trace_events.c
1709
struct trace_event_file *file = v;
kernel/trace/trace_events.c
1736
static int t_show_triggers(struct seq_file *m, void *v)
kernel/trace/trace_events.c
1738
struct trace_event_file *file = v;
kernel/trace/trace_events.c
1763
static int s_show(struct seq_file *m, void *v)
kernel/trace/trace_events.c
1765
struct set_event_iter *iter = v;
kernel/trace/trace_events.c
1787
static int s_show(struct seq_file *m, void *v)
kernel/trace/trace_events.c
1789
struct set_event_iter *iter = v;
kernel/trace/trace_events.c
1795
static void s_stop(struct seq_file *m, void *v)
kernel/trace/trace_events.c
1797
kfree(v);
kernel/trace/trace_events.c
1802
__next(struct seq_file *m, void *v, loff_t *pos, int type)
kernel/trace/trace_events.c
1812
return trace_pid_next(pid_list, v, pos);
kernel/trace/trace_events.c
1816
p_next(struct seq_file *m, void *v, loff_t *pos)
kernel/trace/trace_events.c
1818
return __next(m, v, pos, TRACE_PIDS);
kernel/trace/trace_events.c
1822
np_next(struct seq_file *m, void *v, loff_t *pos)
kernel/trace/trace_events.c
1824
return __next(m, v, pos, TRACE_NO_PIDS);
kernel/trace/trace_events.c
2047
static void *f_next(struct seq_file *m, void *v, loff_t *pos)
kernel/trace/trace_events.c
2053
struct list_head *node = v;
kernel/trace/trace_events.c
2057
switch ((unsigned long)v) {
kernel/trace/trace_events.c
2080
static int f_show(struct seq_file *m, void *v)
kernel/trace/trace_events.c
2087
switch ((unsigned long)v) {
kernel/trace/trace_events.c
2104
field = list_entry(v, struct ftrace_event_field, link);
kernel/trace/trace_events_hist.c
5749
static int hist_show(struct seq_file *m, void *v)
kernel/trace/trace_events_hist.c
6102
static int hist_debug_show(struct seq_file *m, void *v)
kernel/trace/trace_events_synth.c
2274
static int synth_events_seq_show(struct seq_file *m, void *v)
kernel/trace/trace_events_synth.c
2276
struct dyn_event *ev = v;
kernel/trace/trace_events_trigger.c
296
static int trigger_show(struct seq_file *m, void *v)
kernel/trace/trace_events_trigger.c
301
if (v == SHOW_AVAILABLE_TRIGGERS) {
kernel/trace/trace_events_trigger.c
312
data = list_entry(v, struct event_trigger_data, list);
kernel/trace/trace_hwlat.c
614
static void *s_mode_next(struct seq_file *s, void *v, loff_t *pos)
kernel/trace/trace_hwlat.c
624
static int s_mode_show(struct seq_file *s, void *v)
kernel/trace/trace_hwlat.c
626
loff_t *pos = v;
kernel/trace/trace_hwlat.c
640
static void s_mode_stop(struct seq_file *s, void *v)
kernel/trace/trace_kprobe.c
1317
static int probes_seq_show(struct seq_file *m, void *v)
kernel/trace/trace_kprobe.c
1319
struct dyn_event *ev = v;
kernel/trace/trace_kprobe.c
1374
static int probes_profile_seq_show(struct seq_file *m, void *v)
kernel/trace/trace_kprobe.c
1376
struct dyn_event *ev = v;
kernel/trace/trace_osnoise.c
2141
static void *s_options_next(struct seq_file *s, void *v, loff_t *pos)
kernel/trace/trace_osnoise.c
2151
static int s_options_show(struct seq_file *s, void *v)
kernel/trace/trace_osnoise.c
2153
loff_t *pos = v;
kernel/trace/trace_osnoise.c
2176
static void s_options_stop(struct seq_file *s, void *v)
kernel/trace/trace_output.c
564
#define MARK(v, s) {.val = v, .sym = s}
kernel/trace/trace_pid.c
145
int trace_pid_show(struct seq_file *m, void *v)
kernel/trace/trace_pid.c
147
unsigned long pid = (unsigned long)v - 1;
kernel/trace/trace_pid.c
91
void *trace_pid_next(struct trace_pid_list *pid_list, void *v, loff_t *pos)
kernel/trace/trace_pid.c
93
long pid = (unsigned long)v;
kernel/trace/trace_printk.c
123
find_next_mod_format(int start_index, void *v, const char **fmt, loff_t *pos)
kernel/trace/trace_printk.c
136
if (!v || start_index == *pos) {
kernel/trace/trace_printk.c
153
mod_fmt = container_of(v, typeof(*mod_fmt), fmt);
kernel/trace/trace_printk.c
180
find_next_mod_format(int start_index, void *v, const char **fmt, loff_t *pos)
kernel/trace/trace_printk.c
265
static const char **find_next(void *v, loff_t *pos)
kernel/trace/trace_printk.c
267
const char **fmt = v;
kernel/trace/trace_printk.c
295
return find_next_mod_format(start_index, v, fmt, pos);
kernel/trace/trace_printk.c
305
static void *t_next(struct seq_file *m, void * v, loff_t *pos)
kernel/trace/trace_printk.c
308
return find_next(v, pos);
kernel/trace/trace_printk.c
311
static int t_show(struct seq_file *m, void *v)
kernel/trace/trace_printk.c
313
const char **fmt = v;
kernel/trace/trace_recursion_record.c
141
static void *recursed_function_seq_next(struct seq_file *m, void *v, loff_t *pos)
kernel/trace/trace_recursion_record.c
152
static void recursed_function_seq_stop(struct seq_file *m, void *v)
kernel/trace/trace_recursion_record.c
158
static int recursed_function_seq_show(struct seq_file *m, void *v)
kernel/trace/trace_recursion_record.c
160
struct recursed_functions *record = v;
kernel/trace/trace_sched_switch.c
461
static void *saved_tgids_next(struct seq_file *m, void *v, loff_t *pos)
kernel/trace/trace_sched_switch.c
475
static void saved_tgids_stop(struct seq_file *m, void *v)
kernel/trace/trace_sched_switch.c
479
static int saved_tgids_show(struct seq_file *m, void *v)
kernel/trace/trace_sched_switch.c
481
int *entry = (int *)v;
kernel/trace/trace_sched_switch.c
518
static void *saved_cmdlines_next(struct seq_file *m, void *v, loff_t *pos)
kernel/trace/trace_sched_switch.c
520
unsigned int *ptr = v;
kernel/trace/trace_sched_switch.c
540
void *v;
kernel/trace/trace_sched_switch.c
546
v = &savedcmd->map_cmdline_to_pid[0];
kernel/trace/trace_sched_switch.c
548
v = saved_cmdlines_next(m, v, &l);
kernel/trace/trace_sched_switch.c
549
if (!v)
kernel/trace/trace_sched_switch.c
553
return v;
kernel/trace/trace_sched_switch.c
556
static void saved_cmdlines_stop(struct seq_file *m, void *v)
kernel/trace/trace_sched_switch.c
562
static int saved_cmdlines_show(struct seq_file *m, void *v)
kernel/trace/trace_sched_switch.c
565
unsigned int *pid = v;
kernel/trace/trace_stack.c
388
t_next(struct seq_file *m, void *v, loff_t *pos)
kernel/trace/trace_stack.c
435
static int t_show(struct seq_file *m, void *v)
kernel/trace/trace_stack.c
440
if (v == SEQ_START_TOKEN) {
kernel/trace/trace_stack.c
452
i = *(long *)v;
kernel/trace/trace_stat.c
211
static int stat_seq_show(struct seq_file *s, void *v)
kernel/trace/trace_stat.c
214
struct stat_node *l = container_of(v, struct stat_node, node);
kernel/trace/trace_stat.c
216
if (v == SEQ_START_TOKEN)
kernel/trace/trace_uprobe.c
771
static int probes_seq_show(struct seq_file *m, void *v)
kernel/trace/trace_uprobe.c
773
struct dyn_event *ev = v;
kernel/trace/trace_uprobe.c
822
static int probes_profile_seq_show(struct seq_file *m, void *v)
kernel/trace/trace_uprobe.c
824
struct dyn_event *ev = v;
kernel/ucount.c
202
static inline bool atomic_long_inc_below(atomic_long_t *v, long u)
kernel/ucount.c
204
long c = atomic_long_read(v);
kernel/ucount.c
209
} while (!atomic_long_try_cmpxchg(v, &c, c+1));
kernel/ucount.c
247
long inc_rlimit_ucounts(struct ucounts *ucounts, enum rlimit_type type, long v)
kernel/ucount.c
254
long new = atomic_long_add_return(v, &iter->rlimit[type]);
kernel/ucount.c
264
bool dec_rlimit_ucounts(struct ucounts *ucounts, enum rlimit_type type, long v)
kernel/ucount.c
269
long dec = atomic_long_sub_return(v, &iter->rlimit[type]);
kernel/user_namespace.c
1214
int proc_setgroups_show(struct seq_file *seq, void *v)
kernel/user_namespace.c
613
static int uid_m_show(struct seq_file *seq, void *v)
kernel/user_namespace.c
616
struct uid_gid_extent *extent = v;
kernel/user_namespace.c
634
static int gid_m_show(struct seq_file *seq, void *v)
kernel/user_namespace.c
637
struct uid_gid_extent *extent = v;
kernel/user_namespace.c
655
static int projid_m_show(struct seq_file *seq, void *v)
kernel/user_namespace.c
658
struct uid_gid_extent *extent = v;
kernel/user_namespace.c
713
static void *m_next(struct seq_file *seq, void *v, loff_t *pos)
kernel/user_namespace.c
719
static void m_stop(struct seq_file *seq, void *v)
kernel/workqueue.c
7331
int v, ret = -ENOMEM;
kernel/workqueue.c
7333
if (sscanf(buf, "%d", &v) != 1)
kernel/workqueue.c
7339
attrs->affn_strict = (bool)v;
kernel/workqueue.c
899
static unsigned long shift_and_mask(unsigned long v, u32 shift, u32 bits)
kernel/workqueue.c
901
return (v >> shift) & ((1U << bits) - 1);
lib/842/842_decompress.c
133
u64 v;
lib/842/842_decompress.c
139
ret = next_bits(p, &v, n * 8);
lib/842/842_decompress.c
145
put_unaligned(cpu_to_be16((u16)v), (__be16 *)p->out);
lib/842/842_decompress.c
148
put_unaligned(cpu_to_be32((u32)v), (__be32 *)p->out);
lib/842/842_decompress.c
151
put_unaligned(cpu_to_be64((u64)v), (__be64 *)p->out);
lib/atomic64.c
104
s64 generic_atomic64_fetch_##op(s64 a, atomic64_t *v) \
lib/atomic64.c
107
arch_spinlock_t *lock = lock_addr(v); \
lib/atomic64.c
112
val = v->counter; \
lib/atomic64.c
113
v->counter c_op a; \
lib/atomic64.c
141
s64 generic_atomic64_dec_if_positive(atomic64_t *v)
lib/atomic64.c
144
arch_spinlock_t *lock = lock_addr(v);
lib/atomic64.c
149
val = v->counter - 1;
lib/atomic64.c
151
v->counter = val;
lib/atomic64.c
158
s64 generic_atomic64_cmpxchg(atomic64_t *v, s64 o, s64 n)
lib/atomic64.c
161
arch_spinlock_t *lock = lock_addr(v);
lib/atomic64.c
166
val = v->counter;
lib/atomic64.c
168
v->counter = n;
lib/atomic64.c
175
s64 generic_atomic64_xchg(atomic64_t *v, s64 new)
lib/atomic64.c
178
arch_spinlock_t *lock = lock_addr(v);
lib/atomic64.c
183
val = v->counter;
lib/atomic64.c
184
v->counter = new;
lib/atomic64.c
191
s64 generic_atomic64_fetch_add_unless(atomic64_t *v, s64 a, s64 u)
lib/atomic64.c
194
arch_spinlock_t *lock = lock_addr(v);
lib/atomic64.c
199
val = v->counter;
lib/atomic64.c
201
v->counter += a;
lib/atomic64.c
36
static inline arch_spinlock_t *lock_addr(const atomic64_t *v)
lib/atomic64.c
38
unsigned long addr = (unsigned long) v;
lib/atomic64.c
45
s64 generic_atomic64_read(const atomic64_t *v)
lib/atomic64.c
48
arch_spinlock_t *lock = lock_addr(v);
lib/atomic64.c
53
val = v->counter;
lib/atomic64.c
60
void generic_atomic64_set(atomic64_t *v, s64 i)
lib/atomic64.c
63
arch_spinlock_t *lock = lock_addr(v);
lib/atomic64.c
67
v->counter = i;
lib/atomic64.c
74
void generic_atomic64_##op(s64 a, atomic64_t *v) \
lib/atomic64.c
77
arch_spinlock_t *lock = lock_addr(v); \
lib/atomic64.c
81
v->counter c_op a; \
lib/atomic64.c
88
s64 generic_atomic64_##op##_return(s64 a, atomic64_t *v) \
lib/atomic64.c
91
arch_spinlock_t *lock = lock_addr(v); \
lib/atomic64.c
96
val = (v->counter c_op a); \
lib/atomic64_test.c
111
atomic_t v;
lib/atomic64_test.c
146
#define INIT(c) do { atomic64_set(&v, c); r = c; } while (0)
lib/atomic64_test.c
157
atomic64_t v = ATOMIC64_INIT(v0);
lib/atomic64_test.c
159
BUG_ON(v.counter != r);
lib/atomic64_test.c
161
atomic64_set(&v, v1);
lib/atomic64_test.c
163
BUG_ON(v.counter != r);
lib/atomic64_test.c
164
BUG_ON(atomic64_read(&v) != r);
lib/atomic64_test.c
191
atomic64_inc(&v);
lib/atomic64_test.c
193
BUG_ON(v.counter != r);
lib/atomic64_test.c
196
atomic64_dec(&v);
lib/atomic64_test.c
198
BUG_ON(v.counter != r);
lib/atomic64_test.c
207
BUG_ON(atomic64_add_unless(&v, one, v0));
lib/atomic64_test.c
208
BUG_ON(v.counter != r);
lib/atomic64_test.c
211
BUG_ON(!atomic64_add_unless(&v, one, v1));
lib/atomic64_test.c
213
BUG_ON(v.counter != r);
lib/atomic64_test.c
216
BUG_ON(atomic64_dec_if_positive(&v) != (onestwos - 1));
lib/atomic64_test.c
218
BUG_ON(v.counter != r);
lib/atomic64_test.c
22
atomic##bit##_set(&v, v0); \
lib/atomic64_test.c
221
BUG_ON(atomic64_dec_if_positive(&v) != -one);
lib/atomic64_test.c
222
BUG_ON(v.counter != r);
lib/atomic64_test.c
225
BUG_ON(atomic64_dec_if_positive(&v) != (-one - one));
lib/atomic64_test.c
226
BUG_ON(v.counter != r);
lib/atomic64_test.c
229
BUG_ON(!atomic64_inc_not_zero(&v));
lib/atomic64_test.c
231
BUG_ON(v.counter != r);
lib/atomic64_test.c
234
BUG_ON(atomic64_inc_not_zero(&v));
lib/atomic64_test.c
235
BUG_ON(v.counter != r);
lib/atomic64_test.c
238
BUG_ON(!atomic64_inc_not_zero(&v));
lib/atomic64_test.c
24
atomic##bit##_##op(val, &v); \
lib/atomic64_test.c
240
BUG_ON(v.counter != r);
lib/atomic64_test.c
244
r_int = atomic64_inc_not_zero(&v);
lib/atomic64_test.c
26
WARN(atomic##bit##_read(&v) != r, "%Lx != %Lx\n", \
lib/atomic64_test.c
27
(unsigned long long)atomic##bit##_read(&v), \
lib/atomic64_test.c
46
atomic##bit##_set(&v, v0); \
lib/atomic64_test.c
49
BUG_ON(atomic##bit##_##op(val, &v) != r); \
lib/atomic64_test.c
50
BUG_ON(atomic##bit##_read(&v) != r); \
lib/atomic64_test.c
55
atomic##bit##_set(&v, v0); \
lib/atomic64_test.c
58
BUG_ON(atomic##bit##_##op(val, &v) != v0); \
lib/atomic64_test.c
59
BUG_ON(atomic##bit##_read(&v) != r); \
lib/atomic64_test.c
74
atomic##bit##_set(&v, init); \
lib/atomic64_test.c
75
BUG_ON(atomic##bit##_##op(&v, ##args) != ret); \
lib/atomic64_test.c
76
BUG_ON(atomic##bit##_read(&v) != expect); \
lib/base64.c
31
#define INIT_1(v, ch_62, ch_63) \
lib/base64.c
32
[v] = (v) >= 'A' && (v) <= 'Z' ? (v) - 'A' \
lib/base64.c
33
: (v) >= 'a' && (v) <= 'z' ? (v) - 'a' + 26 \
lib/base64.c
34
: (v) >= '0' && (v) <= '9' ? (v) - '0' + 52 \
lib/base64.c
35
: (v) == (ch_62) ? 62 : (v) == (ch_63) ? 63 : -1
lib/base64.c
42
#define INIT_2(v, ...) INIT_1(v, __VA_ARGS__), INIT_1((v) + 1, __VA_ARGS__)
lib/base64.c
43
#define INIT_4(v, ...) INIT_2(v, __VA_ARGS__), INIT_2((v) + 2, __VA_ARGS__)
lib/base64.c
44
#define INIT_8(v, ...) INIT_4(v, __VA_ARGS__), INIT_4((v) + 4, __VA_ARGS__)
lib/base64.c
45
#define INIT_16(v, ...) INIT_8(v, __VA_ARGS__), INIT_8((v) + 8, __VA_ARGS__)
lib/base64.c
46
#define INIT_32(v, ...) INIT_16(v, __VA_ARGS__), INIT_16((v) + 16, __VA_ARGS__)
lib/bch.c
289
static inline int modulo(struct bch_control *bch, unsigned int v)
lib/bch.c
292
while (v >= n) {
lib/bch.c
293
v -= n;
lib/bch.c
294
v = (v & n) + (v >> GF_M(bch));
lib/bch.c
296
return v;
lib/bch.c
302
static inline int mod_s(struct bch_control *bch, unsigned int v)
lib/bch.c
305
return (v < n) ? v : v-n;
lib/bch.c
594
unsigned int u, v, r;
lib/bch.c
611
v = u;
lib/bch.c
612
while (v) {
lib/bch.c
613
i = deg(v);
lib/bch.c
615
v ^= (1 << i);
lib/bootconfig.c
564
char *p, *v = *__v;
lib/bootconfig.c
567
if (*v == '"' || *v == '\'') {
lib/bootconfig.c
568
quotes = *v;
lib/bootconfig.c
569
v++;
lib/bootconfig.c
571
p = v - 1;
lib/bootconfig.c
590
v = strim(v);
lib/bootconfig.c
601
*__v = v;
lib/bootconfig.c
696
static int __init xbc_parse_kv(char **k, char *v, int op)
lib/bootconfig.c
707
v = skip_spaces_until_newline(v);
lib/bootconfig.c
709
if (*v == '#') {
lib/bootconfig.c
710
next = skip_comment(v);
lib/bootconfig.c
711
*v = '\0';
lib/bootconfig.c
714
c = __xbc_parse_value(&v, &next);
lib/bootconfig.c
722
return xbc_parse_error("Value is redefined", v);
lib/bootconfig.c
726
if (xbc_init_node(child, v, XBC_VALUE) < 0)
lib/bootconfig.c
727
return xbc_parse_error("Failed to override value", v);
lib/bootconfig.c
735
if (!xbc_add_head_sibling(v, XBC_VALUE))
lib/closure.c
206
unsigned old, new, v = atomic_read(&cl->remaining);
lib/closure.c
208
old = v;
lib/closure.c
213
} while ((v = atomic_cmpxchg(&cl->remaining, old, new)) != old);
lib/closure.c
59
void closure_sub(struct closure *cl, int v)
lib/closure.c
61
closure_put_after_sub(cl, atomic_sub_return_release(v, &cl->remaining));
lib/crc/tests/crc_kunit.c
114
static u64 generate_random_initial_crc(const struct crc_variant *v)
lib/crc/tests/crc_kunit.c
120
return crc_mask(v); /* All 1 bits */
lib/crc/tests/crc_kunit.c
122
return rand64() & crc_mask(v);
lib/crc/tests/crc_kunit.c
149
const struct crc_variant *v;
lib/crc/tests/crc_kunit.c
163
const struct crc_variant *v = state->v;
lib/crc/tests/crc_kunit.c
165
u64 actual_crc = v->func(state->initial_crc,
lib/crc/tests/crc_kunit.c
177
const struct crc_variant *v)
lib/crc/tests/crc_kunit.c
180
.v = v,
lib/crc/tests/crc_kunit.c
181
.initial_crc = generate_random_initial_crc(v),
lib/crc/tests/crc_kunit.c
186
v, state.initial_crc,
lib/crc/tests/crc_kunit.c
194
static void crc_test(struct kunit *test, const struct crc_variant *v)
lib/crc/tests/crc_kunit.c
202
init_crc = generate_random_initial_crc(v);
lib/crc/tests/crc_kunit.c
223
expected_crc = crc_ref(v, init_crc, &test_buffer[offset], len);
lib/crc/tests/crc_kunit.c
224
actual_crc = v->func(init_crc, &test_buffer[offset], len);
lib/crc/tests/crc_kunit.c
230
crc_interrupt_context_test(test, v);
lib/crc/tests/crc_kunit.c
60
static u64 crc_mask(const struct crc_variant *v)
lib/crc/tests/crc_kunit.c
62
return (u64)-1 >> (64 - v->bits);
lib/crc/tests/crc_kunit.c
66
static u64 crc_ref(const struct crc_variant *v,
lib/crc/tests/crc_kunit.c
73
if (v->le) {
lib/crc/tests/crc_kunit.c
75
crc = (crc >> 1) ^ ((crc & 1) ? v->poly : 0);
lib/crc/tests/crc_kunit.c
78
(v->bits - 1);
lib/crc/tests/crc_kunit.c
79
if (crc & (1ULL << (v->bits - 1)))
lib/crc/tests/crc_kunit.c
80
crc = ((crc << 1) ^ v->poly) &
lib/crc/tests/crc_kunit.c
81
crc_mask(v);
lib/crypto/aescfb.c
45
const u8 *v = iv;
lib/crypto/aescfb.c
48
aescfb_encrypt_block(key, ks, v);
lib/crypto/aescfb.c
50
v = dst;
lib/crypto/blake2b.c
46
u64 v[16];
lib/crypto/blake2b.c
56
memcpy(v, ctx->h, 64);
lib/crypto/blake2b.c
57
v[ 8] = BLAKE2B_IV0;
lib/crypto/blake2b.c
58
v[ 9] = BLAKE2B_IV1;
lib/crypto/blake2b.c
59
v[10] = BLAKE2B_IV2;
lib/crypto/blake2b.c
60
v[11] = BLAKE2B_IV3;
lib/crypto/blake2b.c
61
v[12] = BLAKE2B_IV4 ^ ctx->t[0];
lib/crypto/blake2b.c
62
v[13] = BLAKE2B_IV5 ^ ctx->t[1];
lib/crypto/blake2b.c
63
v[14] = BLAKE2B_IV6 ^ ctx->f[0];
lib/crypto/blake2b.c
64
v[15] = BLAKE2B_IV7 ^ ctx->f[1];
lib/crypto/blake2b.c
87
G(r, 0, v[0], v[4], v[8], v[12]);
lib/crypto/blake2b.c
88
G(r, 1, v[1], v[5], v[9], v[13]);
lib/crypto/blake2b.c
89
G(r, 2, v[2], v[6], v[10], v[14]);
lib/crypto/blake2b.c
90
G(r, 3, v[3], v[7], v[11], v[15]);
lib/crypto/blake2b.c
91
G(r, 4, v[0], v[5], v[10], v[15]);
lib/crypto/blake2b.c
92
G(r, 5, v[1], v[6], v[11], v[12]);
lib/crypto/blake2b.c
93
G(r, 6, v[2], v[7], v[8], v[13]);
lib/crypto/blake2b.c
94
G(r, 7, v[3], v[4], v[9], v[14]);
lib/crypto/blake2b.c
99
ctx->h[i] ^= v[i] ^ v[i + 8];
lib/crypto/blake2s.c
44
u32 v[16];
lib/crypto/blake2s.c
54
memcpy(v, ctx->h, 32);
lib/crypto/blake2s.c
55
v[ 8] = BLAKE2S_IV0;
lib/crypto/blake2s.c
56
v[ 9] = BLAKE2S_IV1;
lib/crypto/blake2s.c
57
v[10] = BLAKE2S_IV2;
lib/crypto/blake2s.c
58
v[11] = BLAKE2S_IV3;
lib/crypto/blake2s.c
59
v[12] = BLAKE2S_IV4 ^ ctx->t[0];
lib/crypto/blake2s.c
60
v[13] = BLAKE2S_IV5 ^ ctx->t[1];
lib/crypto/blake2s.c
61
v[14] = BLAKE2S_IV6 ^ ctx->f[0];
lib/crypto/blake2s.c
62
v[15] = BLAKE2S_IV7 ^ ctx->f[1];
lib/crypto/blake2s.c
81
G(r, 0, v[0], v[4], v[8], v[12]);
lib/crypto/blake2s.c
82
G(r, 1, v[1], v[5], v[9], v[13]);
lib/crypto/blake2s.c
83
G(r, 2, v[2], v[6], v[10], v[14]);
lib/crypto/blake2s.c
84
G(r, 3, v[3], v[7], v[11], v[15]);
lib/crypto/blake2s.c
85
G(r, 4, v[0], v[5], v[10], v[15]);
lib/crypto/blake2s.c
86
G(r, 5, v[1], v[6], v[11], v[12]);
lib/crypto/blake2s.c
87
G(r, 6, v[2], v[7], v[8], v[13]);
lib/crypto/blake2s.c
88
G(r, 7, v[3], v[4], v[9], v[14]);
lib/crypto/blake2s.c
93
ctx->h[i] ^= v[i] ^ v[i + 8];
lib/crypto/curve25519-fiat32.c
167
fe_freeze(h, f->v);
lib/crypto/curve25519-fiat32.c
223
h->v[0] = 1;
lib/crypto/curve25519-fiat32.c
23
typedef struct fe { u32 v[10]; } fe;
lib/crypto/curve25519-fiat32.c
266
fe_add_impl(h->v, f->v, g->v);
lib/crypto/curve25519-fiat32.c
28
typedef struct fe_loose { u32 v[10]; } fe_loose;
lib/crypto/curve25519-fiat32.c
309
fe_sub_impl(h->v, f->v, g->v);
lib/crypto/curve25519-fiat32.c
430
fe_mul_impl(h->v, f->v, g->v);
lib/crypto/curve25519-fiat32.c
435
fe_mul_impl(h->v, f->v, g->v);
lib/crypto/curve25519-fiat32.c
441
fe_mul_impl(h->v, f->v, g->v);
lib/crypto/curve25519-fiat32.c
55
fe_frombytes_impl(h->v, s);
lib/crypto/curve25519-fiat32.c
552
fe_sqr_impl(h->v, f->v);
lib/crypto/curve25519-fiat32.c
557
fe_sqr_impl(h->v, f->v);
lib/crypto/curve25519-fiat32.c
627
u32 x = f->v[i] ^ g->v[i];
lib/crypto/curve25519-fiat32.c
629
f->v[i] ^= x;
lib/crypto/curve25519-fiat32.c
630
g->v[i] ^= x;
lib/crypto/curve25519-fiat32.c
753
fe_mul_121666_impl(h->v, f->v);
lib/crypto/mldsa.c
292
u32 v = get_unaligned_le32(t1_encoded);
lib/crypto/mldsa.c
294
out->x[j + 0] = ((v >> 0) & 0x3ff) << D;
lib/crypto/mldsa.c
295
out->x[j + 1] = ((v >> 10) & 0x3ff) << D;
lib/crypto/mldsa.c
296
out->x[j + 2] = ((v >> 20) & 0x3ff) << D;
lib/crypto/mldsa.c
297
out->x[j + 3] = ((v >> 30) | (t1_encoded[4] << 2)) << D;
lib/crypto/mldsa.c
322
u64 v = get_unaligned_le64(sig);
lib/crypto/mldsa.c
324
z[i].x[j + 0] = (v >> 0) & 0x3ffff;
lib/crypto/mldsa.c
325
z[i].x[j + 1] = (v >> 18) & 0x3ffff;
lib/crypto/mldsa.c
326
z[i].x[j + 2] = (v >> 36) & 0x3ffff;
lib/crypto/mldsa.c
327
z[i].x[j + 3] = (v >> 54) | (sig[8] << 10);
lib/crypto/mldsa.c
332
u64 v = get_unaligned_le64(sig);
lib/crypto/mldsa.c
334
z[i].x[j + 0] = (v >> 0) & 0xfffff;
lib/crypto/mldsa.c
335
z[i].x[j + 1] = (v >> 20) & 0xfffff;
lib/crypto/mldsa.c
336
z[i].x[j + 2] = (v >> 40) & 0xfffff;
lib/crypto/mldsa.c
338
(v >> 60) |
lib/crypto/mldsa.c
514
u32 v = (w1->x[j + 0] << 0) | (w1->x[j + 1] << 6) |
lib/crypto/mldsa.c
516
out[pos++] = v >> 0;
lib/crypto/mldsa.c
517
out[pos++] = v >> 8;
lib/crypto/mldsa.c
518
out[pos++] = v >> 16;
lib/crypto/mpi/longlong.h
1000
#define umul_ppmm(w1, w0, u, v) \
lib/crypto/mpi/longlong.h
1005
"r" ((USItype)(v)))
lib/crypto/mpi/longlong.h
1058
#define umul_ppmm(w1, w0, u, v) \
lib/crypto/mpi/longlong.h
1102
"r" ((USItype)(v)) \
lib/crypto/mpi/longlong.h
1241
#define __umulsidi3(u, v) \
lib/crypto/mpi/longlong.h
1243
umul_ppmm(__hi, __lo, u, v); \
lib/crypto/mpi/longlong.h
1270
#define umul_ppmm(w1, w0, u, v) \
lib/crypto/mpi/longlong.h
1274
UWtype __u = (u), __v = (v); \
lib/crypto/mpi/longlong.h
1297
#define smul_ppmm(w1, w0, u, v) \
lib/crypto/mpi/longlong.h
1300
UWtype __m0 = (u), __m1 = (v); \
lib/crypto/mpi/longlong.h
232
#define umul_ppmm(w1, w0, u, v) \
lib/crypto/mpi/longlong.h
239
"r" ((USItype)(v))); \
lib/crypto/mpi/longlong.h
241
#define smul_ppmm(w1, w0, u, v) \
lib/crypto/mpi/longlong.h
248
"r" ((SItype)(v))); \
lib/crypto/mpi/longlong.h
250
#define __umulsidi3(u, v) \
lib/crypto/mpi/longlong.h
255
"r" ((USItype)(v))); \
lib/crypto/mpi/longlong.h
320
#define umul_ppmm(wh, wl, u, v) \
lib/crypto/mpi/longlong.h
328
"*f" ((USItype)(v))); \
lib/crypto/mpi/longlong.h
415
#define umul_ppmm(w1, w0, u, v) \
lib/crypto/mpi/longlong.h
420
"rm" ((USItype)(v)))
lib/crypto/mpi/longlong.h
470
#define umul_ppmm(w1, w0, u, v) \
lib/crypto/mpi/longlong.h
477
"dI" ((USItype)(v))); \
lib/crypto/mpi/longlong.h
479
#define __umulsidi3(u, v) \
lib/crypto/mpi/longlong.h
484
"dI" ((USItype)(v))); \
lib/crypto/mpi/longlong.h
534
#define umul_ppmm(w1, w0, u, v) \
lib/crypto/mpi/longlong.h
539
"dmi" ((USItype)(v)))
lib/crypto/mpi/longlong.h
613
#define umul_ppmm(wh, wl, u, v) \
lib/crypto/mpi/longlong.h
618
__asm__ ("mulu.d %0,%1,%2" : "=r" (__x.__ll) : "r" (u), "r" (v)); \
lib/crypto/mpi/longlong.h
642
#define umul_ppmm(w1, w0, u, v) \
lib/crypto/mpi/longlong.h
644
UDItype __ll = (UDItype)(u) * (v); \
lib/crypto/mpi/longlong.h
661
#define umul_ppmm(w1, w0, u, v) \
lib/crypto/mpi/longlong.h
666
"d" ((UDItype)(v))); \
lib/crypto/mpi/longlong.h
670
"d" ((UDItype)(v))); \
lib/crypto/mpi/longlong.h
673
#define umul_ppmm(w1, w0, u, v) \
lib/crypto/mpi/longlong.h
676
__ll_UTItype __ll = (__ll_UTItype)(u) * (v); \
lib/crypto/mpi/longlong.h
689
#define umul_ppmm(w1, w0, u, v) \
lib/crypto/mpi/longlong.h
696
"g" ((USItype)(v))); \
lib/crypto/mpi/longlong.h
698
#define __umulsidi3(u, v) \
lib/crypto/mpi/longlong.h
703
"g" ((USItype)(v))); \
lib/crypto/mpi/longlong.h
858
#define umul_ppmm(w1, w0, u, v) \
lib/crypto/mpi/longlong.h
866
"g" ((USItype)(v))); \
lib/crypto/mpi/longlong.h
933
#define umul_ppmm(w1, w0, u, v) \
lib/crypto/mpi/longlong.h
941
"r" ((USItype)(v)) \
lib/crypto/mpi/longlong.h
975
#define umul_ppmm(w1, w0, u, v) \
lib/crypto/mpi/longlong.h
980
"r" ((USItype)(v)))
lib/crypto/mpi/mpi-add.c
108
int mpi_addm(MPI w, MPI u, MPI v, MPI m)
lib/crypto/mpi/mpi-add.c
110
return mpi_add(w, u, v) ?:
lib/crypto/mpi/mpi-add.c
115
int mpi_subm(MPI w, MPI u, MPI v, MPI m)
lib/crypto/mpi/mpi-add.c
117
return mpi_sub(w, u, v) ?:
lib/crypto/mpi/mpi-add.c
18
int mpi_add(MPI w, MPI u, MPI v)
lib/crypto/mpi/mpi-add.c
25
if (u->nlimbs < v->nlimbs) { /* Swap U and V. */
lib/crypto/mpi/mpi-add.c
26
usize = v->nlimbs;
lib/crypto/mpi/mpi-add.c
27
usign = v->sign;
lib/crypto/mpi/mpi-add.c
35
up = v->d;
lib/crypto/mpi/mpi-add.c
40
vsize = v->nlimbs;
lib/crypto/mpi/mpi-add.c
41
vsign = v->sign;
lib/crypto/mpi/mpi-add.c
48
vp = v->d;
lib/crypto/mpi/mpi-add.c
91
int mpi_sub(MPI w, MPI u, MPI v)
lib/crypto/mpi/mpi-add.c
96
vv = mpi_copy(v);
lib/crypto/mpi/mpi-cmp.c
25
int mpi_cmp_ui(MPI u, unsigned long v)
lib/crypto/mpi/mpi-cmp.c
27
mpi_limb_t limb = v;
lib/crypto/mpi/mpi-cmp.c
31
if (v == 0)
lib/crypto/mpi/mpi-cmp.c
50
int mpi_cmp(MPI u, MPI v)
lib/crypto/mpi/mpi-cmp.c
56
mpi_normalize(v);
lib/crypto/mpi/mpi-cmp.c
58
vsize = v->nlimbs;
lib/crypto/mpi/mpi-cmp.c
59
if (!u->sign && v->sign)
lib/crypto/mpi/mpi-cmp.c
61
if (u->sign && !v->sign)
lib/crypto/mpi/mpi-cmp.c
63
if (usize != vsize && !u->sign && !v->sign)
lib/crypto/mpi/mpi-cmp.c
65
if (usize != vsize && u->sign && v->sign)
lib/crypto/mpi/mpi-cmp.c
69
cmp = mpihelp_cmp(u->d, v->d, usize);
lib/crypto/mpi/mpi-mul.c
106
int mpi_mulm(MPI w, MPI u, MPI v, MPI m)
lib/crypto/mpi/mpi-mul.c
108
return mpi_mul(w, u, v) ?:
lib/crypto/mpi/mpi-mul.c
18
int mpi_mul(MPI w, MPI u, MPI v)
lib/crypto/mpi/mpi-mul.c
28
if (u->nlimbs < v->nlimbs) {
lib/crypto/mpi/mpi-mul.c
30
usize = v->nlimbs;
lib/crypto/mpi/mpi-mul.c
31
usign = v->sign;
lib/crypto/mpi/mpi-mul.c
32
up = v->d;
lib/crypto/mpi/mpi-mul.c
40
vsize = v->nlimbs;
lib/crypto/mpi/mpi-mul.c
41
vsign = v->sign;
lib/crypto/mpi/mpi-mul.c
42
vp = v->d;
lib/debugobjects.c
1152
static int debug_stats_show(struct seq_file *m, void *v)
lib/earlycpio.c
102
*chp++ = v;
lib/earlycpio.c
65
unsigned int ch[C_NFIELDS], *chp, v;
lib/earlycpio.c
83
v = 0;
lib/earlycpio.c
85
v <<= 4;
lib/earlycpio.c
90
v += x;
lib/earlycpio.c
96
v += x + 10;
lib/error-inject.c
171
static void ei_seq_stop(struct seq_file *m, void *v)
lib/error-inject.c
176
static void *ei_seq_next(struct seq_file *m, void *v, loff_t *pos)
lib/error-inject.c
178
return seq_list_next(v, &error_injection_list, pos);
lib/error-inject.c
197
static int ei_seq_show(struct seq_file *m, void *v)
lib/error-inject.c
199
struct ei_entry *ent = list_entry(v, struct ei_entry, list);
lib/fault-inject.c
77
#define atomic_dec_not_zero(v) atomic_add_unless((v), -1, 0)
lib/generic-radix-tree.c
26
struct genradix_root *v = READ_ONCE(radix->root);
lib/generic-radix-tree.c
35
struct genradix_root *r = v, *new_root;
lib/generic-radix-tree.c
53
if ((v = cmpxchg_release(&radix->root, r, new_root)) == r) {
lib/generic-radix-tree.c
54
v = new_root;
lib/group_cpus.c
265
unsigned int v, cpus_per_grp, extra_grps;
lib/group_cpus.c
270
for (v = 0; v < nv->ngroups; v++, *curgrp += 1) {
lib/idr.c
570
unsigned long v = xa_to_value(bitmap);
lib/idr.c
573
if (!(v & (1UL << bit)))
lib/idr.c
575
v &= ~(1UL << bit);
lib/idr.c
576
if (!v)
lib/idr.c
578
xas_store(&xas, xa_mk_value(v));
lib/inflate.c
145
} v;
lib/inflate.c
233
#define NEXTBYTE() ({ int v = get_byte(); if (v < 0) goto underrun; (uch)v; })
lib/inflate.c
355
unsigned v[N_MAX]; /* values in order of bit length */
lib/inflate.c
358
unsigned *c, *v, *x;
lib/inflate.c
369
v = stk->v;
lib/inflate.c
437
v[x[j]++] = i;
lib/inflate.c
445
p = v; /* grab values in bit order */
lib/inflate.c
499
*(t = &(q->v.t)) = (struct huft *)NULL;
lib/inflate.c
509
r.v.t = q; /* pointer to this table */
lib/inflate.c
519
if (p >= v + n)
lib/inflate.c
524
r.v.n = (ush)(*p); /* simple code is just the value */
lib/inflate.c
530
r.v.n = d[*p++ - s];
lib/inflate.c
581
q = (--p)->v.t;
lib/inflate.c
625
} while ((e = (t = t->v.t + ((unsigned)b & mask_bits[e]))->e) > 16);
lib/inflate.c
629
slide[w++] = (uch)t->v.n;
lib/inflate.c
645
n = t->v.n + ((unsigned)b & mask_bits[e]);
lib/inflate.c
657
} while ((e = (t = t->v.t + ((unsigned)b & mask_bits[e]))->e) > 16);
lib/inflate.c
660
d = w - t->v.n - ((unsigned)b & mask_bits[e]);
lib/inflate.c
920
j = td->v.n;
lib/iov_iter.c
341
size_t v = n + offset;
lib/iov_iter.c
350
if (n <= v && v <= PAGE_SIZE)
lib/iov_iter.c
354
v += (page - head) << PAGE_SHIFT;
lib/iov_iter.c
356
if (WARN_ON(n > v || v > page_size(head)))
lib/iov_iter.c
871
unsigned long v = 0;
lib/iov_iter.c
885
if (v) // if not the first one
lib/iov_iter.c
886
res |= base | v; // this start | previous end
lib/iov_iter.c
887
v = base + iov->iov_len;
lib/kunit/debugfs.c
112
static int debugfs_print_run(struct seq_file *seq, void *v)
lib/kunit/debugfs.c
64
static int debugfs_print_results(struct seq_file *seq, void *v)
lib/lzo/lzo1x_compress.c
185
u64 v;
lib/lzo/lzo1x_compress.c
186
v = get_unaligned((const u64 *) (ip + m_len)) ^
lib/lzo/lzo1x_compress.c
188
if (unlikely(v == 0)) {
lib/lzo/lzo1x_compress.c
191
v = get_unaligned((const u64 *) (ip + m_len)) ^
lib/lzo/lzo1x_compress.c
195
} while (v == 0);
lib/lzo/lzo1x_compress.c
198
m_len += (unsigned) __builtin_ctzll(v) / 8;
lib/lzo/lzo1x_compress.c
200
m_len += (unsigned) __builtin_clzll(v) / 8;
lib/lzo/lzo1x_compress.c
205
u32 v;
lib/lzo/lzo1x_compress.c
206
v = get_unaligned((const u32 *) (ip + m_len)) ^
lib/lzo/lzo1x_compress.c
208
if (unlikely(v == 0)) {
lib/lzo/lzo1x_compress.c
211
v = get_unaligned((const u32 *) (ip + m_len)) ^
lib/lzo/lzo1x_compress.c
213
if (v != 0)
lib/lzo/lzo1x_compress.c
216
v = get_unaligned((const u32 *) (ip + m_len)) ^
lib/lzo/lzo1x_compress.c
220
} while (v == 0);
lib/lzo/lzo1x_compress.c
223
m_len += (unsigned) __builtin_ctz(v) / 8;
lib/lzo/lzo1x_compress.c
225
m_len += (unsigned) __builtin_clz(v) / 8;
lib/muldi3.c
16
#define umul_ppmm(w1, w0, u, v) \
lib/muldi3.c
23
__vl = __ll_lowpart(v); \
lib/muldi3.c
24
__vh = __ll_highpart(v); \
lib/muldi3.c
42
#define __umulsidi3(u, v) ({ \
lib/muldi3.c
44
umul_ppmm(__w.s.high, __w.s.low, u, v); \
lib/muldi3.c
49
long long notrace __muldi3(long long u, long long v)
lib/muldi3.c
52
const DWunion vv = {.ll = v};
lib/oid_registry.c
108
const unsigned char *v = data;
lib/oid_registry.c
111
if (datasize < 3 || v[0] != ASN1_OID || v[1] != datasize - 2)
lib/oid_registry.c
132
const unsigned char *v = data, *end = v + datasize;
lib/oid_registry.c
138
if (v >= end)
lib/oid_registry.c
141
n = *v++;
lib/oid_registry.c
148
while (v < end) {
lib/oid_registry.c
149
n = *v++;
lib/oid_registry.c
155
if (v >= end)
lib/oid_registry.c
157
n = *v++;
lib/raid6/mktables.c
109
v = 1;
lib/raid6/mktables.c
115
exptbl[i + j] = v;
lib/raid6/mktables.c
116
printf("0x%02x,%c", v, (j == 7) ? '\n' : ' ');
lib/raid6/mktables.c
117
v = gfmul(v, 2);
lib/raid6/mktables.c
118
if (v == 1)
lib/raid6/mktables.c
119
v = 0; /* For entry 255, not a real entry */
lib/raid6/mktables.c
133
v = 255;
lib/raid6/mktables.c
136
v = k;
lib/raid6/mktables.c
139
printf("0x%02x,%c", v, (j == 7) ? '\n' : ' ');
lib/raid6/mktables.c
153
invtbl[i + j] = v = gfpow(i + j, 254);
lib/raid6/mktables.c
154
printf("0x%02x,%c", v, (j == 7) ? '\n' : ' ');
lib/raid6/mktables.c
23
uint8_t v = 0;
lib/raid6/mktables.c
27
v ^= a;
lib/raid6/mktables.c
32
return v;
lib/raid6/mktables.c
37
uint8_t v = 1;
lib/raid6/mktables.c
45
v = gfmul(v, a);
lib/raid6/mktables.c
50
return v;
lib/raid6/mktables.c
56
uint8_t v;
lib/reed_solomon/test_rslib.c
32
__param(int, v, V_PROGRESS, "Verbosity level");
lib/reed_solomon/test_rslib.c
326
if (v >= V_PROGRESS)
lib/reed_solomon/test_rslib.c
333
if (v >= V_CSUMMARY) {
lib/reed_solomon/test_rslib.c
343
if (retval && v >= V_PROGRESS)
lib/reed_solomon/test_rslib.c
356
if (v >= V_PROGRESS)
lib/reed_solomon/test_rslib.c
414
if (v >= V_PROGRESS)
lib/reed_solomon/test_rslib.c
427
if (v >= V_CSUMMARY) {
lib/reed_solomon/test_rslib.c
436
if (stat.noncw && v >= V_PROGRESS)
lib/reed_solomon/test_rslib.c
470
if (v >= V_PROGRESS) {
lib/ref_tracker.c
369
static int ref_tracker_debugfs_show(struct seq_file *f, void *v)
lib/stackdepot.c
853
static int stats_show(struct seq_file *seq, void *v)
lib/string.c
556
void *memset16(uint16_t *s, uint16_t v, size_t count)
lib/string.c
561
*xs++ = v;
lib/string.c
578
void *memset32(uint32_t *s, uint32_t v, size_t count)
lib/string.c
583
*xs++ = v;
lib/string.c
600
void *memset64(uint64_t *s, uint64_t v, size_t count)
lib/string.c
605
*xs++ = v;
lib/tests/bitfield_kunit.c
100
tp##_encode_bits(v, mask) != v << __ffs64(mask));\
lib/tests/bitfield_kunit.c
11
#define CHECK_ENC_GET_U(tp, v, field, res) do { \
lib/tests/bitfield_kunit.c
15
_res = u##tp##_encode_bits(v, field); \
lib/tests/bitfield_kunit.c
17
"u" #tp "_encode_bits(" #v ", " #field ") is 0x%llx != " #res "\n", \
lib/tests/bitfield_kunit.c
20
u##tp##_get_bits(_res, field) != v); \
lib/tests/bitfield_kunit.c
24
#define CHECK_ENC_GET_LE(tp, v, field, res) do { \
lib/tests/bitfield_kunit.c
28
_res = le##tp##_encode_bits(v, field); \
lib/tests/bitfield_kunit.c
31
"le" #tp "_encode_bits(" #v ", " #field ") is 0x%llx != 0x%llx",\
lib/tests/bitfield_kunit.c
35
le##tp##_get_bits(_res, field) != v);\
lib/tests/bitfield_kunit.c
39
#define CHECK_ENC_GET_BE(tp, v, field, res) do { \
lib/tests/bitfield_kunit.c
43
_res = be##tp##_encode_bits(v, field); \
lib/tests/bitfield_kunit.c
46
"be" #tp "_encode_bits(" #v ", " #field ") is 0x%llx != 0x%llx", \
lib/tests/bitfield_kunit.c
50
be##tp##_get_bits(_res, field) != v);\
lib/tests/bitfield_kunit.c
54
#define CHECK_ENC_GET(tp, v, field, res) do { \
lib/tests/bitfield_kunit.c
55
CHECK_ENC_GET_U(tp, v, field, res); \
lib/tests/bitfield_kunit.c
56
CHECK_ENC_GET_LE(tp, v, field, res); \
lib/tests/bitfield_kunit.c
57
CHECK_ENC_GET_BE(tp, v, field, res); \
lib/tests/bitfield_kunit.c
96
u64 v; \
lib/tests/bitfield_kunit.c
98
for (v = 0; v < 1 << hweight32(mask); v++) \
lib/tests/memcpy_kunit.c
31
#define check(instance, v) do { \
lib/tests/memcpy_kunit.c
34
KUNIT_ASSERT_EQ_MSG(test, instance.data[i], v, \
lib/tests/memcpy_kunit.c
36
__LINE__, #instance, v, i, instance.data[i]); \
lib/tests/overflow_kunit.c
810
#define TEST_OVERFLOWS_TYPE(__t1, __t2, v, of) do { \
lib/tests/overflow_kunit.c
811
__t1 t1 = (v); \
lib/tests/string_kunit.c
23
u16 v, *p;
lib/tests/string_kunit.c
30
memset(p, 0xa1, 256 * 2 * sizeof(v));
lib/tests/string_kunit.c
33
v = p[k];
lib/tests/string_kunit.c
35
KUNIT_ASSERT_EQ_MSG(test, v, 0xa1a1,
lib/tests/string_kunit.c
38
KUNIT_ASSERT_EQ_MSG(test, v, 0xb1b2,
lib/tests/string_kunit.c
41
KUNIT_ASSERT_EQ_MSG(test, v, 0xa1a1,
lib/tests/string_kunit.c
52
u32 v, *p;
lib/tests/string_kunit.c
59
memset(p, 0xa1, 256 * 2 * sizeof(v));
lib/tests/string_kunit.c
62
v = p[k];
lib/tests/string_kunit.c
64
KUNIT_ASSERT_EQ_MSG(test, v, 0xa1a1a1a1,
lib/tests/string_kunit.c
67
KUNIT_ASSERT_EQ_MSG(test, v, 0xb1b2b3b4,
lib/tests/string_kunit.c
70
KUNIT_ASSERT_EQ_MSG(test, v, 0xa1a1a1a1,
lib/tests/string_kunit.c
81
u64 v, *p;
lib/tests/string_kunit.c
88
memset(p, 0xa1, 256 * 2 * sizeof(v));
lib/tests/string_kunit.c
91
v = p[k];
lib/tests/string_kunit.c
93
KUNIT_ASSERT_EQ_MSG(test, v, 0xa1a1a1a1a1a1a1a1ULL,
lib/tests/string_kunit.c
96
KUNIT_ASSERT_EQ_MSG(test, v, 0xb1b2b3b4b5b6b7b8ULL,
lib/tests/string_kunit.c
99
KUNIT_ASSERT_EQ_MSG(test, v, 0xa1a1a1a1a1a1a1a1ULL,
lib/win_minmax.c
63
return m->s[0].v;
lib/win_minmax.c
69
struct minmax_sample val = { .t = t, .v = meas };
lib/win_minmax.c
71
if (unlikely(val.v >= m->s[0].v) || /* found new max? */
lib/win_minmax.c
75
if (unlikely(val.v >= m->s[1].v))
lib/win_minmax.c
77
else if (unlikely(val.v >= m->s[2].v))
lib/win_minmax.c
87
struct minmax_sample val = { .t = t, .v = meas };
lib/win_minmax.c
89
if (unlikely(val.v <= m->s[0].v) || /* found new min? */
lib/win_minmax.c
93
if (unlikely(val.v <= m->s[1].v))
lib/win_minmax.c
95
else if (unlikely(val.v <= m->s[2].v))
lib/zlib_deflate/deftree.c
323
int v = s->heap[k];
lib/zlib_deflate/deftree.c
332
if (smaller(tree, v, s->heap[j], s->depth)) break;
lib/zlib_deflate/deftree.c
340
s->heap[k] = v;
lib/zstd/decompress/zstd_decompress.c
1796
#define CHECK_DBOUNDS(p,v) { \
lib/zstd/decompress/zstd_decompress.c
1797
RETURN_ERROR_IF(!ZSTD_dParam_withinBounds(p, v), parameter_outOfBound, ""); \
mm/backing-dev.c
110
static int bdi_debug_stats_show(struct seq_file *m, void *v)
mm/backing-dev.c
193
static int cgwb_debug_stats_show(struct seq_file *m, void *v)
mm/debug_page_ref.c
10
trace_page_ref_set(page, v);
mm/debug_page_ref.c
15
void __page_ref_mod(struct page *page, int v)
mm/debug_page_ref.c
17
trace_page_ref_mod(page, v);
mm/debug_page_ref.c
22
void __page_ref_mod_and_test(struct page *page, int v, int ret)
mm/debug_page_ref.c
24
trace_page_ref_mod_and_test(page, v, ret);
mm/debug_page_ref.c
29
void __page_ref_mod_and_return(struct page *page, int v, int ret)
mm/debug_page_ref.c
31
trace_page_ref_mod_and_return(page, v, ret);
mm/debug_page_ref.c
36
void __page_ref_mod_unless(struct page *page, int v, int u)
mm/debug_page_ref.c
38
trace_page_ref_mod_unless(page, v, u);
mm/debug_page_ref.c
43
void __page_ref_freeze(struct page *page, int v, int ret)
mm/debug_page_ref.c
45
trace_page_ref_freeze(page, v, ret);
mm/debug_page_ref.c
50
void __page_ref_unfreeze(struct page *page, int v)
mm/debug_page_ref.c
52
trace_page_ref_unfreeze(page, v);
mm/debug_page_ref.c
8
void __page_ref_set(struct page *page, int v)
mm/dmapool_test.c
14
void *v;
mm/dmapool_test.c
46
p[i].v = dma_pool_alloc(pool, GFP_KERNEL,
mm/dmapool_test.c
48
if (!p[i].v)
mm/dmapool_test.c
53
dma_pool_free(pool, p[i].v, p[i].dma);
mm/dmapool_test.c
59
dma_pool_free(pool, p[i].v, p[i].dma);
mm/hugetlb_cgroup.c
541
static int hugetlb_cgroup_read_u64_max(struct seq_file *seq, void *v)
mm/hugetlb_cgroup.c
693
static int hugetlb_events_show(struct seq_file *seq, void *v)
mm/hugetlb_cgroup.c
698
static int hugetlb_events_local_show(struct seq_file *seq, void *v)
mm/interval_tree.c
13
static inline unsigned long vma_start_pgoff(struct vm_area_struct *v)
mm/interval_tree.c
15
return v->vm_pgoff;
mm/interval_tree.c
18
static inline unsigned long vma_last_pgoff(struct vm_area_struct *v)
mm/interval_tree.c
20
return v->vm_pgoff + vma_pages(v) - 1;
mm/kfence/core.c
745
static int stats_show(struct seq_file *seq, void *v)
mm/kfence/core.c
769
static void stop_object(struct seq_file *seq, void *v)
mm/kfence/core.c
773
static void *next_object(struct seq_file *seq, void *v, loff_t *pos)
mm/kfence/core.c
781
static int show_object(struct seq_file *seq, void *v)
mm/kfence/core.c
783
struct kfence_metadata *meta = &kfence_metadata[(long)v - 1];
mm/kmemleak.c
1971
static void *kmemleak_seq_next(struct seq_file *seq, void *v, loff_t *pos)
mm/kmemleak.c
1973
struct kmemleak_object *prev_obj = v;
mm/kmemleak.c
1993
static void kmemleak_seq_stop(struct seq_file *seq, void *v)
mm/kmemleak.c
1995
if (!IS_ERR(v)) {
mm/kmemleak.c
2002
if (v)
mm/kmemleak.c
2003
put_object(v);
mm/kmemleak.c
2010
static int kmemleak_seq_show(struct seq_file *seq, void *v)
mm/kmemleak.c
2012
struct kmemleak_object *object = v;
mm/memcontrol-v1.c
1620
__always_unused void *v)
mm/memcontrol-v1.c
1800
static int memcg_numa_stat_show(struct seq_file *m, void *v)
mm/memcontrol-v1.c
1990
static int mem_cgroup_oom_control_read(struct seq_file *sf, void *v)
mm/memcontrol-v1.h
28
int memory_stat_show(struct seq_file *m, void *v);
mm/memcontrol.c
4025
long delta, delta_cpu, v;
mm/memcontrol.c
4039
v = READ_ONCE(ac->cstat[i]);
mm/memcontrol.c
4040
if (v != ac->cstat_prev[i]) {
mm/memcontrol.c
4041
delta_cpu = v - ac->cstat_prev[i];
mm/memcontrol.c
4043
ac->cstat_prev[i] = v;
mm/memcontrol.c
4255
static int peak_show(struct seq_file *sf, void *v, struct page_counter *pc)
mm/memcontrol.c
4270
static int memory_peak_show(struct seq_file *sf, void *v)
mm/memcontrol.c
4274
return peak_show(sf, v, &memcg->memory);
mm/memcontrol.c
4338
static int memory_min_show(struct seq_file *m, void *v)
mm/memcontrol.c
4361
static int memory_low_show(struct seq_file *m, void *v)
mm/memcontrol.c
4384
static int memory_high_show(struct seq_file *m, void *v)
mm/memcontrol.c
4436
static int memory_max_show(struct seq_file *m, void *v)
mm/memcontrol.c
4511
static int memory_events_show(struct seq_file *m, void *v)
mm/memcontrol.c
4519
static int memory_events_local_show(struct seq_file *m, void *v)
mm/memcontrol.c
4527
int memory_stat_show(struct seq_file *m, void *v)
mm/memcontrol.c
4550
static int memory_numa_stat_show(struct seq_file *m, void *v)
mm/memcontrol.c
4580
static int memory_oom_group_show(struct seq_file *m, void *v)
mm/memcontrol.c
5334
static int swap_peak_show(struct seq_file *sf, void *v)
mm/memcontrol.c
5338
return peak_show(sf, v, &memcg->swap);
mm/memcontrol.c
5350
static int swap_high_show(struct seq_file *m, void *v)
mm/memcontrol.c
5373
static int swap_max_show(struct seq_file *m, void *v)
mm/memcontrol.c
5396
static int swap_events_show(struct seq_file *m, void *v)
mm/memcontrol.c
5564
static int zswap_max_show(struct seq_file *m, void *v)
mm/memcontrol.c
5587
static int zswap_writeback_show(struct seq_file *m, void *v)
mm/page_owner.c
878
static void *stack_next(struct seq_file *m, void *v, loff_t *ppos)
mm/page_owner.c
880
struct stack *stack = v;
mm/page_owner.c
892
static int stack_print(struct seq_file *m, void *v)
mm/page_owner.c
895
struct stack *stack = v;
mm/page_owner.c
925
static void stack_stop(struct seq_file *m, void *v)
mm/percpu-stats.c
134
static int percpu_stats_show(struct seq_file *m, void *v)
mm/percpu.c
2466
int group, v;
mm/percpu.c
2469
v = ai->nr_groups;
mm/percpu.c
2470
while (v /= 10)
mm/percpu.c
2473
v = num_possible_cpus();
mm/percpu.c
2474
while (v /= 10)
mm/ptdump.c
193
static int check_wx_show(struct seq_file *m, void *v)
mm/shrinker_debug.c
47
static int shrinker_debugfs_count_show(struct seq_file *m, void *v)
mm/slub.c
386
void stat_add(const struct kmem_cache *s, enum stat_item si, int v)
mm/slub.c
389
raw_cpu_add(s->cpu_stats->stat[si], v);
mm/slub.c
510
return (freeptr_t){.v = encoded};
mm/slub.c
519
decoded = (void *)(ptr.v ^ s->random ^ swab(ptr_addr));
mm/slub.c
521
decoded = (void *)ptr.v;
mm/slub.c
9607
static int slab_debugfs_show(struct seq_file *seq, void *v)
mm/slub.c
9673
static void slab_debugfs_stop(struct seq_file *seq, void *v)
mm/slub.c
9677
static void *slab_debugfs_next(struct seq_file *seq, void *v, loff_t *ppos)
mm/swap_state.c
53
#define SWAP_RA_HITS(v) ((v) & SWAP_RA_HITS_MASK)
mm/swap_state.c
54
#define SWAP_RA_WIN(v) (((v) & SWAP_RA_WIN_MASK) >> SWAP_RA_WIN_SHIFT)
mm/swap_state.c
55
#define SWAP_RA_ADDR(v) ((v) & PAGE_MASK)
mm/swapfile.c
2946
static void *swap_next(struct seq_file *swap, void *v, loff_t *pos)
mm/swapfile.c
2948
struct swap_info_struct *si = v;
mm/swapfile.c
2951
if (v == SEQ_START_TOKEN)
mm/swapfile.c
2966
static void swap_stop(struct seq_file *swap, void *v)
mm/swapfile.c
2971
static int swap_show(struct seq_file *swap, void *v)
mm/swapfile.c
2973
struct swap_info_struct *si = v;
mm/vmalloc.c
5182
static void show_numa_info(struct seq_file *m, struct vm_struct *v,
mm/vmalloc.c
5186
unsigned int step = 1U << vm_area_page_order(v);
mm/vmalloc.c
5193
for (nr = 0; nr < v->nr_pages; nr += step)
mm/vmalloc.c
5194
counters[page_to_nid(v->pages[nr])] += step;
mm/vmalloc.c
5220
struct vm_struct *v;
mm/vmalloc.c
5238
v = va->vm;
mm/vmalloc.c
5239
if (v->flags & VM_UNINITIALIZED)
mm/vmalloc.c
5246
v->addr, v->addr + v->size, v->size);
mm/vmalloc.c
5248
if (v->caller)
mm/vmalloc.c
5249
seq_printf(m, " %pS", v->caller);
mm/vmalloc.c
5251
if (v->nr_pages)
mm/vmalloc.c
5252
seq_printf(m, " pages=%d", v->nr_pages);
mm/vmalloc.c
5254
if (v->phys_addr)
mm/vmalloc.c
5255
seq_printf(m, " phys=%pa", &v->phys_addr);
mm/vmalloc.c
5257
if (v->flags & VM_IOREMAP)
mm/vmalloc.c
5260
if (v->flags & VM_SPARSE)
mm/vmalloc.c
5263
if (v->flags & VM_ALLOC)
mm/vmalloc.c
5266
if (v->flags & VM_MAP)
mm/vmalloc.c
5269
if (v->flags & VM_USERMAP)
mm/vmalloc.c
5272
if (v->flags & VM_DMA_COHERENT)
mm/vmalloc.c
5275
if (is_vmalloc_addr(v->pages))
mm/vmalloc.c
5279
show_numa_info(m, v, counters);
mm/vmscan.c
5326
static void lru_gen_seq_stop(struct seq_file *m, void *v)
mm/vmscan.c
5328
if (!IS_ERR_OR_NULL(v))
mm/vmscan.c
5329
mem_cgroup_iter_break(NULL, lruvec_memcg(v));
mm/vmscan.c
5335
static void *lru_gen_seq_next(struct seq_file *m, void *v, loff_t *pos)
mm/vmscan.c
5337
int nid = lruvec_pgdat(v)->node_id;
mm/vmscan.c
5338
struct mem_cgroup *memcg = lruvec_memcg(v);
mm/vmscan.c
5409
static int lru_gen_seq_show(struct seq_file *m, void *v)
mm/vmscan.c
5413
struct lruvec *lruvec = v;
mm/vmstat.c
1880
unsigned long *v;
mm/vmstat.c
1888
v = kmalloc_array(NR_VMSTAT_ITEMS, sizeof(unsigned long), GFP_KERNEL);
mm/vmstat.c
1889
m->private = v;
mm/vmstat.c
1890
if (!v)
mm/vmstat.c
1893
v[i] = global_zone_page_state(i);
mm/vmstat.c
1894
v += NR_VM_ZONE_STAT_ITEMS;
mm/vmstat.c
1898
v[i] = global_numa_event_state(i);
mm/vmstat.c
1899
v += NR_VM_NUMA_EVENT_ITEMS;
mm/vmstat.c
1903
v[i] = global_node_page_state_pages(i);
mm/vmstat.c
1905
v[i] /= HPAGE_PMD_NR;
mm/vmstat.c
1907
v += NR_VM_NODE_STAT_ITEMS;
mm/vmstat.c
1909
global_dirty_limits(v + NR_DIRTY_BG_THRESHOLD,
mm/vmstat.c
1910
v + NR_DIRTY_THRESHOLD);
mm/vmstat.c
1911
v[NR_MEMMAP_PAGES] = atomic_long_read(&nr_memmap_pages);
mm/vmstat.c
1912
v[NR_MEMMAP_BOOT_PAGES] = atomic_long_read(&nr_memmap_boot_pages);
mm/vmstat.c
1913
v += NR_VM_STAT_ITEMS;
mm/vmstat.c
1916
all_vm_events(v);
mm/vmstat.c
1917
v[PGPGIN] /= 2; /* sectors -> kbytes */
mm/vmstat.c
1918
v[PGPGOUT] /= 2;
mm/vmstat.c
439
s8 v, t;
mm/vmstat.c
444
v = __this_cpu_inc_return(*p);
mm/vmstat.c
446
if (unlikely(v > t)) {
mm/vmstat.c
449
zone_page_state_add(v + overstep, zone, item);
mm/vmstat.c
460
s8 v, t;
mm/vmstat.c
467
v = __this_cpu_inc_return(*p);
mm/vmstat.c
469
if (unlikely(v > t)) {
mm/vmstat.c
472
node_page_state_add(v + overstep, pgdat, item);
mm/vmstat.c
495
s8 v, t;
mm/vmstat.c
500
v = __this_cpu_dec_return(*p);
mm/vmstat.c
502
if (unlikely(v < - t)) {
mm/vmstat.c
505
zone_page_state_add(v - overstep, zone, item);
mm/vmstat.c
516
s8 v, t;
mm/vmstat.c
523
v = __this_cpu_dec_return(*p);
mm/vmstat.c
525
if (unlikely(v < - t)) {
mm/vmstat.c
528
node_page_state_add(v - overstep, pgdat, item);
mm/vmstat.c
813
int v;
mm/vmstat.c
815
v = this_cpu_xchg(pzstats->vm_stat_diff[i], 0);
mm/vmstat.c
816
if (v) {
mm/vmstat.c
818
atomic_long_add(v, &zone->vm_stat[i]);
mm/vmstat.c
819
global_zone_diff[i] += v;
mm/vmstat.c
869
int v;
mm/vmstat.c
871
v = this_cpu_xchg(p->vm_node_stat_diff[i], 0);
mm/vmstat.c
872
if (v) {
mm/vmstat.c
873
atomic_long_add(v, &pgdat->vm_stat[i]);
mm/vmstat.c
874
global_node_diff[i] += v;
mm/vmstat.c
904
int v;
mm/vmstat.c
906
v = pzstats->vm_stat_diff[i];
mm/vmstat.c
908
atomic_long_add(v, &zone->vm_stat[i]);
mm/vmstat.c
909
global_zone_diff[i] += v;
mm/vmstat.c
915
unsigned long v;
mm/vmstat.c
917
v = pzstats->vm_numa_event[i];
mm/vmstat.c
919
zone_numa_event_add(v, zone, i);
mm/vmstat.c
932
int v;
mm/vmstat.c
934
v = p->vm_node_stat_diff[i];
mm/vmstat.c
936
atomic_long_add(v, &pgdat->vm_stat[i]);
mm/vmstat.c
937
global_node_diff[i] += v;
mm/vmstat.c
950
unsigned long v;
mm/vmstat.c
955
v = pzstats->vm_stat_diff[i];
mm/vmstat.c
957
zone_page_state_add(v, zone, i);
mm/vmstat.c
964
v = pzstats->vm_numa_event[i];
mm/vmstat.c
966
zone_numa_event_add(v, zone, i);
mm/zsmalloc.c
517
static int zs_stats_size_show(struct seq_file *s, void *v)
net/802/mrp.c
218
u8 *v = (u8 *)value;
net/802/mrp.c
223
while (len > 0 && !++v[--len])
net/8021q/vlanproc.c
190
static void *vlan_seq_next(struct seq_file *seq, void *v, loff_t *pos)
net/8021q/vlanproc.c
196
static void vlan_seq_stop(struct seq_file *seq, void *v)
net/8021q/vlanproc.c
202
static int vlan_seq_show(struct seq_file *seq, void *v)
net/8021q/vlanproc.c
207
if (v == SEQ_START_TOKEN) {
net/8021q/vlanproc.c
218
const struct net_device *vlandev = v;
net/8021q/vlanproc.c
36
static int vlan_seq_show(struct seq_file *seq, void *v);
net/8021q/vlanproc.c
38
static void *vlan_seq_next(struct seq_file *seq, void *v, loff_t *pos);
net/8021q/vlanproc.c
40
static int vlandev_seq_show(struct seq_file *seq, void *v);
net/9p/trans_fd.c
216
static int p9_fd_read(struct p9_client *client, void *v, int len)
net/9p/trans_fd.c
232
ret = kernel_read(ts->rd, v, len, &pos);
net/9p/trans_fd.c
384
static int p9_fd_write(struct p9_client *client, void *v, int len)
net/9p/trans_fd.c
398
ret = kernel_write(ts->wr, v, len, &ts->wr->f_pos);
net/9p/trans_virtio.c
446
__le32 v = cpu_to_le32(n);
net/9p/trans_virtio.c
447
memcpy(&req->tc.sdata[req->tc.size - 4], &v, 4);
net/9p/trans_virtio.c
465
__le32 v = cpu_to_le32(n);
net/9p/trans_virtio.c
466
memcpy(&req->tc.sdata[req->tc.size - 4], &v, 4);
net/9p/trans_xen.c
393
char *versions, *v;
net/9p/trans_xen.c
399
for (v = versions; *v; v++) {
net/9p/trans_xen.c
400
if (simple_strtoul(v, &v, 10) == 1) {
net/9p/trans_xen.c
401
v = NULL;
net/9p/trans_xen.c
405
if (v) {
net/appletalk/aarp.c
950
static void *aarp_seq_next(struct seq_file *seq, void *v, loff_t *pos)
net/appletalk/aarp.c
952
struct aarp_entry *entry = v;
net/appletalk/aarp.c
958
if (v == SEQ_START_TOKEN)
net/appletalk/aarp.c
973
static void aarp_seq_stop(struct seq_file *seq, void *v)
net/appletalk/aarp.c
988
static int aarp_seq_show(struct seq_file *seq, void *v)
net/appletalk/aarp.c
991
struct aarp_entry *entry = v;
net/appletalk/aarp.c
994
if (v == SEQ_START_TOKEN)
net/appletalk/atalk_proc.c
102
if (v == SEQ_START_TOKEN) {
net/appletalk/atalk_proc.c
108
r = v;
net/appletalk/atalk_proc.c
114
static void atalk_seq_route_stop(struct seq_file *seq, void *v)
net/appletalk/atalk_proc.c
120
static int atalk_seq_route_show(struct seq_file *seq, void *v)
net/appletalk/atalk_proc.c
124
if (v == SEQ_START_TOKEN) {
net/appletalk/atalk_proc.c
136
rt = v;
net/appletalk/atalk_proc.c
152
static void *atalk_seq_socket_next(struct seq_file *seq, void *v, loff_t *pos)
net/appletalk/atalk_proc.c
154
return seq_hlist_next(v, &atalk_sockets, pos);
net/appletalk/atalk_proc.c
157
static void atalk_seq_socket_stop(struct seq_file *seq, void *v)
net/appletalk/atalk_proc.c
163
static int atalk_seq_socket_show(struct seq_file *seq, void *v)
net/appletalk/atalk_proc.c
168
if (v == SEQ_START_TOKEN) {
net/appletalk/atalk_proc.c
174
s = sk_entry(v);
net/appletalk/atalk_proc.c
36
static void *atalk_seq_interface_next(struct seq_file *seq, void *v, loff_t *pos)
net/appletalk/atalk_proc.c
41
if (v == SEQ_START_TOKEN) {
net/appletalk/atalk_proc.c
47
i = v;
net/appletalk/atalk_proc.c
53
static void atalk_seq_interface_stop(struct seq_file *seq, void *v)
net/appletalk/atalk_proc.c
59
static int atalk_seq_interface_show(struct seq_file *seq, void *v)
net/appletalk/atalk_proc.c
63
if (v == SEQ_START_TOKEN) {
net/appletalk/atalk_proc.c
69
iface = v;
net/appletalk/atalk_proc.c
97
static void *atalk_seq_route_next(struct seq_file *seq, void *v, loff_t *pos)
net/atm/br2684.c
774
static void *br2684_seq_next(struct seq_file *seq, void *v, loff_t * pos)
net/atm/br2684.c
776
return seq_list_next(v, &br2684_devs, pos);
net/atm/br2684.c
779
static void br2684_seq_stop(struct seq_file *seq, void *v)
net/atm/br2684.c
785
static int br2684_seq_show(struct seq_file *seq, void *v)
net/atm/br2684.c
787
const struct br2684_dev *brdev = list_entry(v, struct br2684_dev,
net/atm/clip.c
874
static int clip_seq_show(struct seq_file *seq, void *v)
net/atm/clip.c
879
if (v == SEQ_START_TOKEN) {
net/atm/clip.c
884
struct neighbour *n = v;
net/atm/lec.c
877
void *v = NULL;
net/atm/lec.c
881
v = lec_tbl_walk(state, &priv->lec_arp_tables[p], l);
net/atm/lec.c
882
if (v)
net/atm/lec.c
886
return v;
net/atm/lec.c
897
void *v = NULL;
net/atm/lec.c
901
v = lec_tbl_walk(state, lec_misc_tables[q], l);
net/atm/lec.c
902
if (v)
net/atm/lec.c
906
return v;
net/atm/lec.c
928
void *v;
net/atm/lec.c
931
v = (dev && netdev_priv(dev)) ?
net/atm/lec.c
933
if (!v && dev) {
net/atm/lec.c
938
return v;
net/atm/lec.c
943
void *v = NULL;
net/atm/lec.c
946
v = lec_itf_walk(state, &l);
net/atm/lec.c
947
if (v)
net/atm/lec.c
950
return v;
net/atm/lec.c
968
static void lec_seq_stop(struct seq_file *seq, void *v)
net/atm/lec.c
980
static void *lec_seq_next(struct seq_file *seq, void *v, loff_t *pos)
net/atm/lec.c
988
static int lec_seq_show(struct seq_file *seq, void *v)
net/atm/lec.c
995
if (v == SEQ_START_TOKEN)
net/atm/mpoa_proc.c
117
static void *mpc_next(struct seq_file *m, void *v, loff_t *pos)
net/atm/mpoa_proc.c
119
struct mpoa_client *p = v;
net/atm/mpoa_proc.c
121
return v == SEQ_START_TOKEN ? mpcs : p->next;
net/atm/mpoa_proc.c
124
static void mpc_stop(struct seq_file *m, void *v)
net/atm/mpoa_proc.c
131
static int mpc_show(struct seq_file *m, void *v)
net/atm/mpoa_proc.c
133
struct mpoa_client *mpc = v;
net/atm/mpoa_proc.c
140
if (v == SEQ_START_TOKEN) {
net/atm/proc.c
128
static void vcc_seq_stop(struct seq_file *seq, void *v)
net/atm/proc.c
134
static void *vcc_seq_next(struct seq_file *seq, void *v, loff_t *pos)
net/atm/proc.c
136
v = vcc_walk(seq, 1);
net/atm/proc.c
138
return v;
net/atm/proc.c
224
static int atm_dev_seq_show(struct seq_file *seq, void *v)
net/atm/proc.c
230
if (v == &atm_devs)
net/atm/proc.c
233
struct atm_dev *dev = list_entry(v, struct atm_dev, dev_list);
net/atm/proc.c
247
static int pvc_seq_show(struct seq_file *seq, void *v)
net/atm/proc.c
252
if (v == SEQ_START_TOKEN)
net/atm/proc.c
270
static int vcc_seq_show(struct seq_file *seq, void *v)
net/atm/proc.c
272
if (v == SEQ_START_TOKEN) {
net/atm/proc.c
292
static int svc_seq_show(struct seq_file *seq, void *v)
net/atm/proc.c
297
if (v == SEQ_START_TOKEN)
net/atm/resources.c
411
void atm_dev_seq_stop(struct seq_file *seq, void *v)
net/atm/resources.c
416
void *atm_dev_seq_next(struct seq_file *seq, void *v, loff_t *pos)
net/atm/resources.c
418
return seq_list_next(v, &atm_devs, pos);
net/atm/resources.h
26
void atm_dev_seq_stop(struct seq_file *seq, void *v);
net/atm/resources.h
27
void *atm_dev_seq_next(struct seq_file *seq, void *v, loff_t *pos);
net/ax25/af_ax25.c
1939
static void *ax25_info_next(struct seq_file *seq, void *v, loff_t *pos)
net/ax25/af_ax25.c
1941
return seq_hlist_next(v, &ax25_list, pos);
net/ax25/af_ax25.c
1944
static void ax25_info_stop(struct seq_file *seq, void *v)
net/ax25/af_ax25.c
1950
static int ax25_info_show(struct seq_file *seq, void *v)
net/ax25/af_ax25.c
1952
ax25_cb *ax25 = hlist_entry(v, struct ax25_cb, ax25_node);
net/ax25/ax25_route.c
276
static void *ax25_rt_seq_next(struct seq_file *seq, void *v, loff_t *pos)
net/ax25/ax25_route.c
279
return (v == SEQ_START_TOKEN) ? ax25_route_list :
net/ax25/ax25_route.c
280
((struct ax25_route *) v)->next;
net/ax25/ax25_route.c
283
static void ax25_rt_seq_stop(struct seq_file *seq, void *v)
net/ax25/ax25_route.c
289
static int ax25_rt_seq_show(struct seq_file *seq, void *v)
net/ax25/ax25_route.c
293
if (v == SEQ_START_TOKEN)
net/ax25/ax25_route.c
296
struct ax25_route *ax25_rt = v;
net/ax25/ax25_uid.c
153
static void *ax25_uid_seq_next(struct seq_file *seq, void *v, loff_t *pos)
net/ax25/ax25_uid.c
155
return seq_hlist_next(v, &ax25_uid_list, pos);
net/ax25/ax25_uid.c
158
static void ax25_uid_seq_stop(struct seq_file *seq, void *v)
net/ax25/ax25_uid.c
164
static int ax25_uid_seq_show(struct seq_file *seq, void *v)
net/ax25/ax25_uid.c
168
if (v == SEQ_START_TOKEN)
net/ax25/ax25_uid.c
173
pt = hlist_entry(v, struct ax25_uid_assoc, uid_node);
net/batman-adv/main.h
286
#define batadv_atomic_dec_not_zero(v) atomic_add_unless((v), -1, 0)
net/batman-adv/translation-table.c
294
unsigned short vid, int v)
net/batman-adv/translation-table.c
302
atomic_add(v, &vlan->tt.num_entries);
net/batman-adv/translation-table.c
339
unsigned short vid, int v)
net/batman-adv/translation-table.c
347
if (atomic_add_return(v, &vlan->tt.num_entries) == 0) {
net/bluetooth/af_bluetooth.c
787
static void *bt_seq_next(struct seq_file *seq, void *v, loff_t *pos)
net/bluetooth/af_bluetooth.c
791
return seq_hlist_next(v, &l->head, pos);
net/bluetooth/af_bluetooth.c
794
static void bt_seq_stop(struct seq_file *seq, void *v)
net/bluetooth/af_bluetooth.c
802
static int bt_seq_show(struct seq_file *seq, void *v)
net/bluetooth/af_bluetooth.c
806
if (v == SEQ_START_TOKEN) {
net/bluetooth/af_bluetooth.c
811
l->custom_seq_show(seq, v);
net/bluetooth/af_bluetooth.c
816
struct sock *sk = sk_entry(v);
net/bluetooth/af_bluetooth.c
831
l->custom_seq_show(seq, v);
net/bluetooth/cmtp/capi.c
491
static int cmtp_proc_show(struct seq_file *m, void *v)
net/bluetooth/smp.c
210
const u8 v[32], const u8 x[16], u8 z, u8 res[16])
net/bluetooth/smp.c
216
SMP_DBG("v %32phN", v);
net/bluetooth/smp.c
220
memcpy(m + 1, v, 32);
net/bluetooth/smp.c
313
static int smp_g2(struct crypto_shash *tfm_cmac, const u8 u[32], const u8 v[32],
net/bluetooth/smp.c
320
SMP_DBG("v %32phN", v);
net/bluetooth/smp.c
324
memcpy(m + 16, v, 32);
net/bluetooth/smp.c
3575
const u8 v[32] = {
net/bluetooth/smp.c
3590
err = smp_f4(tfm_cmac, u, v, x, z, res);
net/bluetooth/smp.c
3677
const u8 v[32] = {
net/bluetooth/smp.c
3692
err = smp_g2(tfm_cmac, u, v, x, y, &val);
net/bridge/br_arp_nd_proxy.c
508
struct net_bridge_vlan *v;
net/bridge/br_arp_nd_proxy.c
510
v = br_vlan_find(vg, vid);
net/bridge/br_arp_nd_proxy.c
511
if (!v)
net/bridge/br_arp_nd_proxy.c
513
return !!(v->priv_flags & BR_VLFLAG_NEIGH_SUPPRESS_ENABLED);
net/bridge/br_fdb.c
1318
struct net_bridge_vlan *v;
net/bridge/br_fdb.c
1368
v = br_vlan_find(vg, vid);
net/bridge/br_fdb.c
1369
if (!v || !br_vlan_should_use(v)) {
net/bridge/br_fdb.c
1387
list_for_each_entry(v, &vg->vlan_list, vlist) {
net/bridge/br_fdb.c
1388
if (!br_vlan_should_use(v))
net/bridge/br_fdb.c
1390
err = __br_fdb_add(ndm, br, p, addr, nlh_flags, v->vid,
net/bridge/br_fdb.c
1458
struct net_bridge_vlan *v;
net/bridge/br_fdb.c
1465
list_for_each_entry(v, &vg->vlan_list, vlist) {
net/bridge/br_fdb.c
1466
if (!br_vlan_should_use(v))
net/bridge/br_fdb.c
1468
err &= __br_fdb_delete(br, p, addr, v->vid, notified);
net/bridge/br_fdb.c
340
const struct net_bridge_vlan *v;
net/bridge/br_fdb.c
356
v = br_vlan_find(vg, vid);
net/bridge/br_fdb.c
359
(!vid || (v && br_vlan_should_use(v)))) {
net/bridge/br_fdb.c
461
struct net_bridge_vlan *v;
net/bridge/br_fdb.c
494
list_for_each_entry(v, &vg->vlan_list, vlist)
net/bridge/br_fdb.c
495
fdb_add_local(br, p, newaddr, v->vid);
net/bridge/br_fdb.c
505
struct net_bridge_vlan *v;
net/bridge/br_fdb.c
526
list_for_each_entry(v, &vg->vlan_list, vlist) {
net/bridge/br_fdb.c
527
if (!br_vlan_should_use(v))
net/bridge/br_fdb.c
529
f = br_fdb_find(br, br->dev->dev_addr, v->vid);
net/bridge/br_fdb.c
533
fdb_add_local(br, NULL, newaddr, v->vid);
net/bridge/br_fdb.c
589
struct net_bridge_vlan *v;
net/bridge/br_fdb.c
603
list_for_each_entry(v, &vg->vlan_list, vlist)
net/bridge/br_fdb.c
604
br_fdb_find_delete_local(br, p, dev->dev_addr, v->vid);
net/bridge/br_fdb.c
624
struct net_bridge_vlan *v;
net/bridge/br_fdb.c
639
list_for_each_entry(v, &vg->vlan_list, vlist) {
net/bridge/br_fdb.c
640
if (!br_vlan_should_use(v))
net/bridge/br_fdb.c
643
err = br_fdb_add_local(br, p, dev->dev_addr, v->vid);
net/bridge/br_mdb.c
1301
struct net_bridge_vlan *v;
net/bridge/br_mdb.c
1342
list_for_each_entry(v, &vg->vlan_list, vlist) {
net/bridge/br_mdb.c
1343
cfg.entry->vid = v->vid;
net/bridge/br_mdb.c
1344
cfg.group.vid = v->vid;
net/bridge/br_mdb.c
1403
struct net_bridge_vlan *v;
net/bridge/br_mdb.c
1420
list_for_each_entry(v, &vg->vlan_list, vlist) {
net/bridge/br_mdb.c
1421
cfg.entry->vid = v->vid;
net/bridge/br_mdb.c
1422
cfg.group.vid = v->vid;
net/bridge/br_mdb.c
713
struct net_bridge_vlan *v;
net/bridge/br_mdb.c
725
v = br_vlan_find(br_vlan_group(br), entry->vid);
net/bridge/br_mdb.c
726
if (!v) {
net/bridge/br_mdb.c
730
if (br_multicast_ctx_vlan_global_disabled(&v->br_mcast_ctx)) {
net/bridge/br_mdb.c
734
brmctx = &v->br_mcast_ctx;
net/bridge/br_mdb.c
90
struct net_bridge_vlan *v;
net/bridge/br_mdb.c
92
v = br_vlan_find(nbp_vlan_group(p), vid);
net/bridge/br_mdb.c
93
if (!v)
net/bridge/br_mdb.c
95
pmctx = &v->port_mcast_ctx;
net/bridge/br_mst.c
107
struct net_bridge_vlan *v;
net/bridge/br_mst.c
125
list_for_each_entry_rcu(v, &vg->vlan_list, vlist) {
net/bridge/br_mst.c
126
if (v->brvlan->msti != msti)
net/bridge/br_mst.c
129
br_mst_vlan_set_state(vg, v, state);
net/bridge/br_mst.c
140
struct net_bridge_vlan *v;
net/bridge/br_mst.c
142
list_for_each_entry(v, &vg->vlan_list, vlist) {
net/bridge/br_mst.c
147
if (v != pv && v->brvlan->msti == msti) {
net/bridge/br_mst.c
148
br_mst_vlan_set_state(vg, pv, v->state);
net/bridge/br_mst.c
192
void br_mst_vlan_init_state(struct net_bridge_vlan *v)
net/bridge/br_mst.c
195
v->msti = 0;
net/bridge/br_mst.c
197
if (br_vlan_is_master(v))
net/bridge/br_mst.c
198
v->state = BR_STATE_FORWARDING;
net/bridge/br_mst.c
200
v->state = v->port->state;
net/bridge/br_mst.c
245
const struct net_bridge_vlan *v;
net/bridge/br_mst.c
251
list_for_each_entry_rcu(v, &vg->vlan_list, vlist) {
net/bridge/br_mst.c
252
if (test_bit(v->brvlan->msti, seen))
net/bridge/br_mst.c
262
__set_bit(v->brvlan->msti, seen);
net/bridge/br_mst.c
272
const struct net_bridge_vlan *v;
net/bridge/br_mst.c
276
list_for_each_entry(v, &vg->vlan_list, vlist) {
net/bridge/br_mst.c
277
if (test_bit(v->brvlan->msti, seen))
net/bridge/br_mst.c
282
nla_put_u16(skb, IFLA_BRIDGE_MST_ENTRY_MSTI, v->brvlan->msti) ||
net/bridge/br_mst.c
283
nla_put_u8(skb, IFLA_BRIDGE_MST_ENTRY_STATE, v->state)) {
net/bridge/br_mst.c
289
__set_bit(v->brvlan->msti, seen);
net/bridge/br_mst.c
34
const struct net_bridge_vlan *v;
net/bridge/br_mst.c
48
list_for_each_entry(v, &vg->vlan_list, vlist) {
net/bridge/br_mst.c
49
if (v->msti == msti)
net/bridge/br_mst.c
50
__set_bit(v->vid, vids);
net/bridge/br_mst.c
61
const struct net_bridge_vlan *v;
net/bridge/br_mst.c
71
list_for_each_entry(v, &vg->vlan_list, vlist) {
net/bridge/br_mst.c
72
if (v->brvlan->msti == msti) {
net/bridge/br_mst.c
73
*state = v->state;
net/bridge/br_mst.c
83
struct net_bridge_vlan *v,
net/bridge/br_mst.c
86
if (br_vlan_get_state(v) == state)
net/bridge/br_mst.c
89
if (v->vid == vg->pvid)
net/bridge/br_mst.c
92
br_vlan_set_state(v, state);
net/bridge/br_multicast.c
4273
void br_multicast_update_vlan_mcast_ctx(struct net_bridge_vlan *v, u8 state)
net/bridge/br_multicast.c
4278
if (!br_vlan_should_use(v))
net/bridge/br_multicast.c
4281
if (br_vlan_is_master(v))
net/bridge/br_multicast.c
4284
br = v->port->br;
net/bridge/br_multicast.c
4290
br_multicast_enable_port_ctx(&v->port_mcast_ctx);
net/bridge/br_multicast.c
4580
int br_multicast_set_vlan_router(struct net_bridge_vlan *v, u8 mcast_router)
net/bridge/br_multicast.c
4584
if (br_vlan_is_master(v))
net/bridge/br_multicast.c
4585
err = br_multicast_set_router(&v->br_mcast_ctx, mcast_router);
net/bridge/br_multicast.c
4587
err = br_multicast_set_port_router(&v->port_mcast_ctx,
net/bridge/br_netlink.c
1770
struct net_bridge_vlan *v;
net/bridge/br_netlink.c
1791
list_for_each_entry(v, &vg->vlan_list, vlist)
net/bridge/br_netlink.c
1808
struct net_bridge_vlan *v;
net/bridge/br_netlink.c
1837
list_for_each_entry(v, &vg->vlan_list, vlist) {
net/bridge/br_netlink.c
1844
vxi.vid = v->vid;
net/bridge/br_netlink.c
1845
vxi.flags = v->flags;
net/bridge/br_netlink.c
1846
if (v->vid == pvid)
net/bridge/br_netlink.c
1848
br_vlan_get_stats(v, &stats);
net/bridge/br_netlink.c
26
struct net_bridge_vlan *v;
net/bridge/br_netlink.c
36
list_for_each_entry_rcu(v, &vg->vlan_list, vlist) {
net/bridge/br_netlink.c
365
struct net_bridge_vlan *v;
net/bridge/br_netlink.c
375
list_for_each_entry_rcu(v, &vg->vlan_list, vlist) {
net/bridge/br_netlink.c
377
if (!br_vlan_should_use(v))
net/bridge/br_netlink.c
379
if (v->vid == pvid)
net/bridge/br_netlink.c
382
if (v->flags & BRIDGE_VLAN_INFO_UNTAGGED)
net/bridge/br_netlink.c
387
} else if ((v->vid - vid_range_end) == 1 &&
net/bridge/br_netlink.c
389
vid_range_end = v->vid;
net/bridge/br_netlink.c
39
if (!br_vlan_should_use(v))
net/bridge/br_netlink.c
400
vid_range_start = v->vid;
net/bridge/br_netlink.c
401
vid_range_end = v->vid;
net/bridge/br_netlink.c
41
if (v->vid == pvid)
net/bridge/br_netlink.c
421
struct net_bridge_vlan *v;
net/bridge/br_netlink.c
425
list_for_each_entry_rcu(v, &vg->vlan_list, vlist) {
net/bridge/br_netlink.c
426
if (!br_vlan_should_use(v))
net/bridge/br_netlink.c
429
vinfo.vid = v->vid;
net/bridge/br_netlink.c
431
if (v->vid == pvid)
net/bridge/br_netlink.c
434
if (v->flags & BRIDGE_VLAN_INFO_UNTAGGED)
net/bridge/br_netlink.c
44
if (v->flags & BRIDGE_VLAN_INFO_UNTAGGED)
net/bridge/br_netlink.c
49
} else if ((v->vid - vid_range_end) == 1 &&
net/bridge/br_netlink.c
51
vid_range_end = v->vid;
net/bridge/br_netlink.c
60
vid_range_start = v->vid;
net/bridge/br_netlink.c
61
vid_range_end = v->vid;
net/bridge/br_netlink.c
757
int v, v_change_start = 0;
net/bridge/br_netlink.c
764
for (v = (*vinfo_last)->vid; v <= vinfo_curr->vid; v++) {
net/bridge/br_netlink.c
767
tmp_vinfo.vid = v;
net/bridge/br_netlink.c
775
v_change_start = v;
net/bridge/br_netlink.c
781
v - 1, rtm_cmd);
net/bridge/br_netlink.c
789
v - 1, rtm_cmd);
net/bridge/br_netlink_tunnel.c
153
struct net_bridge_vlan *v;
net/bridge/br_netlink_tunnel.c
157
list_for_each_entry_rcu(v, &vg->vlan_list, vlist) {
net/bridge/br_netlink_tunnel.c
159
if (!br_vlan_should_use(v))
net/bridge/br_netlink_tunnel.c
162
if (!v->tinfo.tunnel_dst)
net/bridge/br_netlink_tunnel.c
167
} else if ((v->vid - vtend->vid) == 1 &&
net/bridge/br_netlink_tunnel.c
168
vlan_tunid_inrange(v, vtend)) {
net/bridge/br_netlink_tunnel.c
169
vtend = v;
net/bridge/br_netlink_tunnel.c
177
vtbegin = v;
net/bridge/br_netlink_tunnel.c
178
vtend = v;
net/bridge/br_netlink_tunnel.c
263
struct net_bridge_vlan *v;
net/bridge/br_netlink_tunnel.c
269
v = br_vlan_find(vg, v_curr);
net/bridge/br_netlink_tunnel.c
274
if (v && curr_change && br_vlan_can_enter_range(v, *v_end)) {
net/bridge/br_netlink_tunnel.c
275
*v_end = v;
net/bridge/br_netlink_tunnel.c
282
*v_start = curr_change ? v : NULL;
net/bridge/br_netlink_tunnel.c
300
int t, v;
net/bridge/br_netlink_tunnel.c
308
for (v = tinfo_last->vid; v <= tinfo_curr->vid; v++) {
net/bridge/br_netlink_tunnel.c
311
err = br_vlan_tunnel_info(p, cmd, v, t, &curr_change);
net/bridge/br_netlink_tunnel.c
318
__vlan_tunnel_handle_range(p, &v_start, &v_end, v,
net/bridge/br_netlink_tunnel.c
40
struct net_bridge_vlan *v, *vtbegin = NULL, *vtend = NULL;
net/bridge/br_netlink_tunnel.c
44
list_for_each_entry_rcu(v, &vg->vlan_list, vlist) {
net/bridge/br_netlink_tunnel.c
46
if (!br_vlan_should_use(v) || !v->tinfo.tunnel_id)
net/bridge/br_netlink_tunnel.c
51
} else if ((v->vid - vtend->vid) == 1 &&
net/bridge/br_netlink_tunnel.c
52
vlan_tunid_inrange(v, vtend)) {
net/bridge/br_netlink_tunnel.c
53
vtend = v;
net/bridge/br_netlink_tunnel.c
62
vtbegin = v;
net/bridge/br_netlink_tunnel.c
63
vtend = v;
net/bridge/br_private.h
1065
void br_multicast_update_vlan_mcast_ctx(struct net_bridge_vlan *v, u8 state);
net/bridge/br_private.h
1542
static inline void br_multicast_update_vlan_mcast_ctx(struct net_bridge_vlan *v,
net/bridge/br_private.h
1611
void br_vlan_get_stats(const struct net_bridge_vlan *v,
net/bridge/br_private.h
1685
static inline u16 br_vlan_flags(const struct net_bridge_vlan *v, u16 pvid)
net/bridge/br_private.h
1687
return v->vid == pvid ? v->flags | BRIDGE_VLAN_INFO_PVID : v->flags;
net/bridge/br_private.h
1834
static inline void br_vlan_get_stats(const struct net_bridge_vlan *v,
net/bridge/br_private.h
1878
static inline u16 br_vlan_flags(const struct net_bridge_vlan *v, u16 pvid)
net/bridge/br_private.h
1889
bool br_vlan_opts_fill(struct sk_buff *skb, const struct net_bridge_vlan *v,
net/bridge/br_private.h
1910
static inline u8 br_vlan_get_state(const struct net_bridge_vlan *v)
net/bridge/br_private.h
1912
return READ_ONCE(v->state);
net/bridge/br_private.h
1915
static inline void br_vlan_set_state(struct net_bridge_vlan *v, u8 state)
net/bridge/br_private.h
1917
WRITE_ONCE(v->state, state);
net/bridge/br_private.h
1918
br_multicast_update_vlan_mcast_ctx(v, state);
net/bridge/br_private.h
1959
int br_mst_vlan_set_msti(struct net_bridge_vlan *v, u16 msti);
net/bridge/br_private.h
1960
void br_mst_vlan_init_state(struct net_bridge_vlan *v);
net/bridge/br_private.h
657
static inline bool br_vlan_is_master(const struct net_bridge_vlan *v)
net/bridge/br_private.h
659
return v->flags & BRIDGE_VLAN_INFO_MASTER;
net/bridge/br_private.h
663
static inline bool br_vlan_is_brentry(const struct net_bridge_vlan *v)
net/bridge/br_private.h
665
return v->flags & BRIDGE_VLAN_INFO_BRENTRY;
net/bridge/br_private.h
669
static inline bool br_vlan_should_use(const struct net_bridge_vlan *v)
net/bridge/br_private.h
671
if (br_vlan_is_master(v)) {
net/bridge/br_private.h
672
if (br_vlan_is_brentry(v))
net/bridge/br_private.h
733
static inline u8 br_vlan_multicast_router(const struct net_bridge_vlan *v)
net/bridge/br_private.h
738
if (!br_vlan_is_master(v))
net/bridge/br_private.h
739
mcast_router = v->port_mcast_ctx.multicast_router;
net/bridge/br_private.h
741
mcast_router = v->br_mcast_ctx.multicast_router;
net/bridge/br_private.h
988
int br_multicast_set_vlan_router(struct net_bridge_vlan *v, u8 mcast_router);
net/bridge/br_switchdev.c
182
struct switchdev_obj_port_vlan v = {
net/bridge/br_switchdev.c
190
return switchdev_port_obj_add(dev, &v.obj, extack);
net/bridge/br_switchdev.c
195
struct switchdev_obj_port_vlan v = {
net/bridge/br_switchdev.c
201
return switchdev_port_obj_del(dev, &v.obj);
net/bridge/br_switchdev.c
366
struct net_bridge_vlan *v;
net/bridge/br_switchdev.c
376
list_for_each_entry(v, &vg->vlan_list, vlist) {
net/bridge/br_switchdev.c
377
if (v->msti) {
net/bridge/br_switchdev.c
379
attr.u.vlan_msti.vid = v->vid;
net/bridge/br_switchdev.c
380
attr.u.vlan_msti.msti = v->msti;
net/bridge/br_switchdev.c
420
struct net_bridge_vlan *v;
net/bridge/br_switchdev.c
429
list_for_each_entry(v, &vg->vlan_list, vlist) {
net/bridge/br_switchdev.c
433
.flags = br_vlan_flags(v, pvid),
net/bridge/br_switchdev.c
434
.vid = v->vid,
net/bridge/br_switchdev.c
437
if (!br_vlan_should_use(v))
net/bridge/br_sysfs_if.c
176
static int store_flush(struct net_bridge_port *p, unsigned long v)
net/bridge/br_sysfs_if.c
189
unsigned long v)
net/bridge/br_sysfs_if.c
191
if (v & BR_GROUPFWD_MACPAUSE)
net/bridge/br_sysfs_if.c
193
p->group_fwd_mask = v;
net/bridge/br_sysfs_if.c
251
unsigned long v)
net/bridge/br_sysfs_if.c
253
return br_multicast_set_port_router(&p->multicast_ctx, v);
net/bridge/br_sysfs_if.c
52
static int store_##_name(struct net_bridge_port *p, unsigned long v) \
net/bridge/br_sysfs_if.c
54
return store_flag(p, v, _mask); \
net/bridge/br_sysfs_if.c
59
static int store_flag(struct net_bridge_port *p, unsigned long v,
net/bridge/br_sysfs_if.c
66
if (v)
net/bridge/br_vlan.c
100
__vlan_flags_update(v, flags, true);
net/bridge/br_vlan.c
104
struct net_bridge_vlan *v, u16 flags,
net/bridge/br_vlan.c
1062
struct net_bridge_vlan *v;
net/bridge/br_vlan.c
1067
v = br_vlan_lookup(&vg->vlan_hash, vid);
net/bridge/br_vlan.c
1068
if (v && br_vlan_should_use(v) &&
net/bridge/br_vlan.c
1069
(v->flags & BRIDGE_VLAN_INFO_UNTAGGED))
net/bridge/br_vlan.c
112
err = br_switchdev_port_vlan_add(dev, v->vid, flags, false, extack);
net/bridge/br_vlan.c
114
return vlan_vid_add(dev, br->vlan_proto, v->vid);
net/bridge/br_vlan.c
115
v->priv_flags |= BR_VLFLAG_ADDED_BY_SWITCHDEV;
net/bridge/br_vlan.c
119
static void __vlan_add_list(struct net_bridge_vlan *v)
net/bridge/br_vlan.c
125
if (br_vlan_is_master(v))
net/bridge/br_vlan.c
126
vg = br_vlan_group(v->br);
net/bridge/br_vlan.c
128
vg = nbp_vlan_group(v->port);
net/bridge/br_vlan.c
133
if (v->vid >= vent->vid)
net/bridge/br_vlan.c
1357
struct net_bridge_vlan *v;
net/bridge/br_vlan.c
136
list_add_rcu(&v->vlist, hpos);
net/bridge/br_vlan.c
1361
v = br_vlan_find(nbp_vlan_group(port), vid);
net/bridge/br_vlan.c
1362
if (!v)
net/bridge/br_vlan.c
1367
return __vlan_del(v);
net/bridge/br_vlan.c
1383
void br_vlan_get_stats(const struct net_bridge_vlan *v,
net/bridge/br_vlan.c
139
static void __vlan_del_list(struct net_bridge_vlan *v)
net/bridge/br_vlan.c
1394
cpu_stats = per_cpu_ptr(v->stats, i);
net/bridge/br_vlan.c
141
list_del_rcu(&v->vlist);
net/bridge/br_vlan.c
145
const struct net_bridge_vlan *v)
net/bridge/br_vlan.c
1479
struct net_bridge_vlan *v;
net/bridge/br_vlan.c
1485
v = br_vlan_find(vg, path->bridge.vlan_id);
net/bridge/br_vlan.c
1486
if (!v || !br_vlan_should_use(v))
net/bridge/br_vlan.c
1489
if (!(v->flags & BRIDGE_VLAN_INFO_UNTAGGED))
net/bridge/br_vlan.c
1494
else if (v->priv_flags & BR_VLFLAG_ADDED_BY_SWITCHDEV)
net/bridge/br_vlan.c
1506
struct net_bridge_vlan *v;
net/bridge/br_vlan.c
1518
v = br_vlan_find(vg, vid);
net/bridge/br_vlan.c
1519
if (!v)
net/bridge/br_vlan.c
152
err = br_switchdev_port_vlan_del(dev, v->vid);
net/bridge/br_vlan.c
1523
p_vinfo->flags = v->flags;
net/bridge/br_vlan.c
153
if (!(v->priv_flags & BR_VLFLAG_ADDED_BY_SWITCHDEV))
net/bridge/br_vlan.c
1534
struct net_bridge_vlan *v;
net/bridge/br_vlan.c
154
vlan_vid_del(dev, br->vlan_proto, v->vid);
net/bridge/br_vlan.c
1545
v = br_vlan_find(vg, vid);
net/bridge/br_vlan.c
1546
if (!v)
net/bridge/br_vlan.c
1550
p_vinfo->flags = v->flags;
net/bridge/br_vlan.c
1819
const struct net_bridge_vlan *v)
net/bridge/br_vlan.c
1828
br_vlan_get_stats(v, &stats);
net/bridge/br_vlan.c
189
struct net_bridge_vlan *v;
net/bridge/br_vlan.c
191
v = container_of(rcu, struct net_bridge_vlan, rcu);
net/bridge/br_vlan.c
1913
struct net_bridge_vlan *v = NULL;
net/bridge/br_vlan.c
192
WARN_ON(!br_vlan_is_master(v));
net/bridge/br_vlan.c
193
free_percpu(v->stats);
net/bridge/br_vlan.c
194
v->stats = NULL;
net/bridge/br_vlan.c
195
kfree(v);
net/bridge/br_vlan.c
1951
v = br_vlan_find(vg, vid);
net/bridge/br_vlan.c
1952
if (!v || !br_vlan_should_use(v))
net/bridge/br_vlan.c
1955
flags = v->flags;
net/bridge/br_vlan.c
1956
if (br_get_pvid(vg) == v->vid)
net/bridge/br_vlan.c
1965
if (!br_vlan_fill_vids(skb, vid, vid_range, v, p, flags, false))
net/bridge/br_vlan.c
1992
struct net_bridge_vlan *v, *range_start = NULL, *range_end = NULL;
net/bridge/br_vlan.c
2037
list_for_each_entry_rcu(v, &vg->vlan_list, vlist) {
net/bridge/br_vlan.c
2038
if (!dump_global && !br_vlan_should_use(v))
net/bridge/br_vlan.c
2046
range_start = v;
net/bridge/br_vlan.c
2047
range_end = v;
net/bridge/br_vlan.c
2052
if (br_vlan_global_opts_can_enter_range(v, range_end))
net/bridge/br_vlan.c
2063
range_start = v;
net/bridge/br_vlan.c
2064
} else if (dump_stats || v->vid == pvid ||
net/bridge/br_vlan.c
2065
!br_vlan_can_enter_range(v, range_end)) {
net/bridge/br_vlan.c
2077
range_start = v;
net/bridge/br_vlan.c
2080
range_end = v;
net/bridge/br_vlan.c
218
struct net_bridge_vlan *v;
net/bridge/br_vlan.c
220
v = container_of(rcu, struct net_bridge_vlan, rcu);
net/bridge/br_vlan.c
221
WARN_ON(br_vlan_is_master(v));
net/bridge/br_vlan.c
223
if (v->priv_flags & BR_VLFLAG_PER_PORT_STATS)
net/bridge/br_vlan.c
224
free_percpu(v->stats);
net/bridge/br_vlan.c
225
v->stats = NULL;
net/bridge/br_vlan.c
226
kfree(v);
net/bridge/br_vlan.c
229
static void br_vlan_init_state(struct net_bridge_vlan *v)
net/bridge/br_vlan.c
233
if (br_vlan_is_master(v))
net/bridge/br_vlan.c
234
br = v->br;
net/bridge/br_vlan.c
236
br = v->port->br;
net/bridge/br_vlan.c
239
br_mst_vlan_init_state(v);
net/bridge/br_vlan.c
243
v->state = BR_STATE_FORWARDING;
net/bridge/br_vlan.c
244
v->msti = 0;
net/bridge/br_vlan.c
258
static int __vlan_add(struct net_bridge_vlan *v, u16 flags,
net/bridge/br_vlan.c
268
if (br_vlan_is_master(v)) {
net/bridge/br_vlan.c
269
br = v->br;
net/bridge/br_vlan.c
273
p = v->port;
net/bridge/br_vlan.c
284
err = __vlan_vid_add(dev, br, v, flags, extack);
net/bridge/br_vlan.c
292
err = br_vlan_add(br, v->vid,
net/bridge/br_vlan.c
299
br_vlan_notify(br, NULL, v->vid, 0,
net/bridge/br_vlan.c
303
masterv = br_vlan_get_master(br, v->vid, extack);
net/bridge/br_vlan.c
308
v->brvlan = masterv;
net/bridge/br_vlan.c
310
v->stats =
net/bridge/br_vlan.c
312
if (!v->stats) {
net/bridge/br_vlan.c
316
v->priv_flags |= BR_VLFLAG_PER_PORT_STATS;
net/bridge/br_vlan.c
318
v->stats = masterv->stats;
net/bridge/br_vlan.c
320
br_multicast_port_ctx_init(p, v, &v->port_mcast_ctx);
net/bridge/br_vlan.c
322
if (br_vlan_should_use(v)) {
net/bridge/br_vlan.c
323
err = br_switchdev_port_vlan_add(dev, v->vid, flags,
net/bridge/br_vlan.c
328
br_multicast_ctx_init(br, v, &v->br_mcast_ctx);
net/bridge/br_vlan.c
329
v->priv_flags |= BR_VLFLAG_GLOBAL_MCAST_ENABLED;
net/bridge/br_vlan.c
333
if (br_vlan_should_use(v)) {
net/bridge/br_vlan.c
335
err = br_fdb_add_local(br, p, dev->dev_addr, v->vid);
net/bridge/br_vlan.c
345
br_vlan_init_state(v);
net/bridge/br_vlan.c
347
err = rhashtable_lookup_insert_fast(&vg->vlan_hash, &v->vnode,
net/bridge/br_vlan.c
352
__vlan_add_list(v);
net/bridge/br_vlan.c
353
__vlan_flags_commit(v, flags);
net/bridge/br_vlan.c
354
br_multicast_toggle_one_vlan(v, true);
net/bridge/br_vlan.c
357
nbp_vlan_set_vlan_dev_state(p, v->vid);
net/bridge/br_vlan.c
362
if (br_vlan_should_use(v)) {
net/bridge/br_vlan.c
363
br_fdb_find_delete_local(br, p, dev->dev_addr, v->vid);
net/bridge/br_vlan.c
369
__vlan_vid_del(dev, br, v);
net/bridge/br_vlan.c
371
if (v->stats && masterv->stats != v->stats)
net/bridge/br_vlan.c
372
free_percpu(v->stats);
net/bridge/br_vlan.c
373
v->stats = NULL;
net/bridge/br_vlan.c
376
v->brvlan = NULL;
net/bridge/br_vlan.c
379
br_switchdev_port_vlan_del(dev, v->vid);
net/bridge/br_vlan.c
38
const struct net_bridge_vlan *v)
net/bridge/br_vlan.c
385
static int __vlan_del(struct net_bridge_vlan *v)
net/bridge/br_vlan.c
387
struct net_bridge_vlan *masterv = v;
net/bridge/br_vlan.c
392
if (br_vlan_is_master(v)) {
net/bridge/br_vlan.c
393
vg = br_vlan_group(v->br);
net/bridge/br_vlan.c
395
p = v->port;
net/bridge/br_vlan.c
396
vg = nbp_vlan_group(v->port);
net/bridge/br_vlan.c
397
masterv = v->brvlan;
net/bridge/br_vlan.c
40
if (vg->pvid == v->vid)
net/bridge/br_vlan.c
400
__vlan_delete_pvid(vg, v->vid);
net/bridge/br_vlan.c
402
err = __vlan_vid_del(p->dev, p->br, v);
net/bridge/br_vlan.c
406
err = br_switchdev_port_vlan_del(v->br->dev, v->vid);
net/bridge/br_vlan.c
412
if (br_vlan_should_use(v)) {
net/bridge/br_vlan.c
413
v->flags &= ~BRIDGE_VLAN_INFO_BRENTRY;
net/bridge/br_vlan.c
417
if (masterv != v) {
net/bridge/br_vlan.c
418
vlan_tunnel_info_del(vg, v);
net/bridge/br_vlan.c
419
rhashtable_remove_fast(&vg->vlan_hash, &v->vnode,
net/bridge/br_vlan.c
421
__vlan_del_list(v);
net/bridge/br_vlan.c
422
nbp_vlan_set_vlan_dev_state(p, v->vid);
net/bridge/br_vlan.c
423
br_multicast_toggle_one_vlan(v, false);
net/bridge/br_vlan.c
424
br_multicast_port_ctx_deinit(&v->port_mcast_ctx);
net/bridge/br_vlan.c
425
call_rcu(&v->rcu, nbp_vlan_rcu_free);
net/bridge/br_vlan.c
44
br_vlan_set_pvid_state(vg, v->state);
net/bridge/br_vlan.c
45
vg->pvid = v->vid;
net/bridge/br_vlan.c
481
struct net_bridge_vlan *v;
net/bridge/br_vlan.c
493
v = br_vlan_find(vg, vid);
net/bridge/br_vlan.c
499
if (!v || !br_vlan_should_use(v)) {
net/bridge/br_vlan.c
508
stats = this_cpu_ptr(v->stats);
net/bridge/br_vlan.c
522
if (v->flags & BRIDGE_VLAN_INFO_UNTAGGED &&
net/bridge/br_vlan.c
527
br_handle_egress_vlan_tunnel(skb, v)) {
net/bridge/br_vlan.c
543
struct net_bridge_vlan *v;
net/bridge/br_vlan.c
61
static bool __vlan_flags_update(struct net_bridge_vlan *v, u16 flags,
net/bridge/br_vlan.c
616
v = br_vlan_find(vg, *vid);
net/bridge/br_vlan.c
617
if (!v || !br_vlan_should_use(v))
net/bridge/br_vlan.c
621
*state = br_vlan_get_state(v);
net/bridge/br_vlan.c
627
stats = this_cpu_ptr(v->stats);
net/bridge/br_vlan.c
634
*vlan = v;
net/bridge/br_vlan.c
664
const struct net_bridge_vlan *v;
net/bridge/br_vlan.c
67
if (br_vlan_is_master(v))
net/bridge/br_vlan.c
672
v = br_vlan_find(vg, vid);
net/bridge/br_vlan.c
673
if (v && br_vlan_should_use(v) &&
net/bridge/br_vlan.c
674
br_vlan_state_allowed(br_vlan_get_state(v), false))
net/bridge/br_vlan.c
68
vg = br_vlan_group(v->br);
net/bridge/br_vlan.c
685
struct net_bridge_vlan *v;
net/bridge/br_vlan.c
70
vg = nbp_vlan_group(v->port);
net/bridge/br_vlan.c
707
v = br_vlan_find(vg, *vid);
net/bridge/br_vlan.c
708
if (v && br_vlan_state_allowed(br_vlan_get_state(v), true))
net/bridge/br_vlan.c
73
change = !!(flags & BRIDGE_VLAN_INFO_PVID) == !!(vg->pvid != v->vid) ||
net/bridge/br_vlan.c
74
((flags ^ v->flags) & BRIDGE_VLAN_INFO_UNTAGGED);
net/bridge/br_vlan.c
80
__vlan_add_pvid(vg, v);
net/bridge/br_vlan.c
82
__vlan_delete_pvid(vg, v->vid);
net/bridge/br_vlan.c
822
struct net_bridge_vlan *v;
net/bridge/br_vlan.c
827
v = br_vlan_find(vg, vid);
net/bridge/br_vlan.c
828
if (!v || !br_vlan_is_brentry(v))
net/bridge/br_vlan.c
834
vlan_tunnel_info_del(vg, v);
net/bridge/br_vlan.c
836
return __vlan_del(v);
net/bridge/br_vlan.c
85
v->flags |= BRIDGE_VLAN_INFO_UNTAGGED;
net/bridge/br_vlan.c
87
v->flags &= ~BRIDGE_VLAN_INFO_UNTAGGED;
net/bridge/br_vlan.c
93
static bool __vlan_flags_would_change(struct net_bridge_vlan *v, u16 flags)
net/bridge/br_vlan.c
95
return __vlan_flags_update(v, flags, false);
net/bridge/br_vlan.c
98
static void __vlan_flags_commit(struct net_bridge_vlan *v, u16 flags)
net/bridge/br_vlan_options.c
110
struct net_bridge_vlan *v,
net/bridge/br_vlan_options.c
12
static bool __vlan_tun_put(struct sk_buff *skb, const struct net_bridge_vlan *v)
net/bridge/br_vlan_options.c
124
if (br_vlan_is_brentry(v))
net/bridge/br_vlan_options.c
125
br = v->br;
net/bridge/br_vlan_options.c
127
br = v->port->br;
net/bridge/br_vlan_options.c
139
if (v->state == state)
net/bridge/br_vlan_options.c
14
__be32 tid = tunnel_id_to_key32(v->tinfo.tunnel_id);
net/bridge/br_vlan_options.c
142
if (v->vid == br_get_pvid(vg))
net/bridge/br_vlan_options.c
145
br_vlan_set_state(v, state);
net/bridge/br_vlan_options.c
157
struct net_bridge_vlan *v,
net/bridge/br_vlan_options.c
17
if (!v->tinfo.tunnel_dst)
net/bridge/br_vlan_options.c
201
tun_id += v->vid - vinfo->vid;
net/bridge/br_vlan_options.c
210
return br_vlan_tunnel_info(p, cmd, v->vid, tun_id, changed);
net/bridge/br_vlan_options.c
216
struct net_bridge_vlan *v,
net/bridge/br_vlan_options.c
227
err = br_vlan_modify_state(vg, v, state, changed, extack);
net/bridge/br_vlan_options.c
232
err = br_vlan_modify_tunnel(p, v, tb, changed, extack);
net/bridge/br_vlan_options.c
242
err = br_multicast_set_vlan_router(v, val);
net/bridge/br_vlan_options.c
254
if (br_multicast_port_ctx_vlan_disabled(&v->port_mcast_ctx)) {
net/bridge/br_vlan_options.c
260
br_multicast_ngroups_set_max(&v->port_mcast_ctx, val);
net/bridge/br_vlan_options.c
266
bool enabled = v->priv_flags & BR_VLFLAG_NEIGH_SUPPRESS_ENABLED;
net/bridge/br_vlan_options.c
275
v->priv_flags ^= BR_VLFLAG_NEIGH_SUPPRESS_ENABLED;
net/bridge/br_vlan_options.c
290
struct net_bridge_vlan *v, *curr_start = NULL, *curr_end = NULL;
net/bridge/br_vlan_options.c
313
v = br_vlan_find(vg, vid);
net/bridge/br_vlan_options.c
314
if (!v || !br_vlan_should_use(v)) {
net/bridge/br_vlan_options.c
320
err = br_vlan_process_one_opts(br, p, vg, v, tb, &changed,
net/bridge/br_vlan_options.c
328
curr_start = v;
net/bridge/br_vlan_options.c
329
curr_end = v;
net/bridge/br_vlan_options.c
333
if (v->vid == pvid ||
net/bridge/br_vlan_options.c
334
!br_vlan_can_enter_range(v, curr_end)) {
net/bridge/br_vlan_options.c
337
curr_start = v;
net/bridge/br_vlan_options.c
339
curr_end = v;
net/bridge/br_vlan_options.c
463
static size_t rtnl_vlan_global_opts_nlmsg_size(const struct net_bridge_vlan *v)
net/bridge/br_vlan_options.c
483
+ br_rports_size(&v->br_mcast_ctx) /* BRIDGE_VLANDB_GOPTS_MCAST_ROUTER_PORTS */
net/bridge/br_vlan_options.c
492
struct net_bridge_vlan *v;
net/bridge/br_vlan_options.c
502
v = br_vlan_find(br_vlan_group(br), vid);
net/bridge/br_vlan_options.c
503
if (!v)
net/bridge/br_vlan_options.c
506
skb = nlmsg_new(rtnl_vlan_global_opts_nlmsg_size(v), GFP_KERNEL);
net/bridge/br_vlan_options.c
519
if (!br_vlan_global_opts_fill(skb, vid, vid_range, v))
net/bridge/br_vlan_options.c
533
struct net_bridge_vlan *v,
net/bridge/br_vlan_options.c
546
if (br_multicast_toggle_global_vlan(v, !!mc_snooping))
net/bridge/br_vlan_options.c
553
err = br_multicast_set_igmp_version(&v->br_mcast_ctx, ver);
net/bridge/br_vlan_options.c
562
v->br_mcast_ctx.multicast_last_member_count = cnt;
net/bridge/br_vlan_options.c
569
v->br_mcast_ctx.multicast_startup_query_count = cnt;
net/bridge/br_vlan_options.c
576
v->br_mcast_ctx.multicast_last_member_interval = clock_t_to_jiffies(val);
net/bridge/br_vlan_options.c
583
v->br_mcast_ctx.multicast_membership_interval = clock_t_to_jiffies(val);
net/bridge/br_vlan_options.c
590
v->br_mcast_ctx.multicast_querier_interval = clock_t_to_jiffies(val);
net/bridge/br_vlan_options.c
597
br_multicast_set_query_intvl(&v->br_mcast_ctx, val);
net/bridge/br_vlan_options.c
604
v->br_mcast_ctx.multicast_query_response_interval = clock_t_to_jiffies(val);
net/bridge/br_vlan_options.c
611
br_multicast_set_startup_query_intvl(&v->br_mcast_ctx, val);
net/bridge/br_vlan_options.c
618
err = br_multicast_set_querier(&v->br_mcast_ctx, val);
net/bridge/br_vlan_options.c
628
err = br_multicast_set_mld_version(&v->br_mcast_ctx, ver);
net/bridge/br_vlan_options.c
639
err = br_mst_vlan_set_msti(v, msti);
net/bridge/br_vlan_options.c
671
struct net_bridge_vlan *v, *curr_start = NULL, *curr_end = NULL;
net/bridge/br_vlan_options.c
71
bool br_vlan_opts_fill(struct sk_buff *skb, const struct net_bridge_vlan *v,
net/bridge/br_vlan_options.c
719
v = br_vlan_find(vg, vid);
net/bridge/br_vlan_options.c
720
if (!v) {
net/bridge/br_vlan_options.c
726
err = br_vlan_process_global_one_opts(br, vg, v, tb, &changed,
net/bridge/br_vlan_options.c
734
curr_start = v;
net/bridge/br_vlan_options.c
735
curr_end = v;
net/bridge/br_vlan_options.c
739
if (!br_vlan_global_opts_can_enter_range(v, curr_end)) {
net/bridge/br_vlan_options.c
74
if (nla_put_u8(skb, BRIDGE_VLANDB_ENTRY_STATE, br_vlan_get_state(v)) ||
net/bridge/br_vlan_options.c
742
curr_start = v;
net/bridge/br_vlan_options.c
744
curr_end = v;
net/bridge/br_vlan_options.c
75
!__vlan_tun_put(skb, v) ||
net/bridge/br_vlan_options.c
77
!!(v->priv_flags & BR_VLFLAG_NEIGH_SUPPRESS_ENABLED)))
net/bridge/br_vlan_options.c
82
br_vlan_multicast_router(v)))
net/bridge/br_vlan_options.c
84
if (p && !br_multicast_port_ctx_vlan_disabled(&v->port_mcast_ctx) &&
net/bridge/br_vlan_options.c
86
br_multicast_ngroups_get(&v->port_mcast_ctx)) ||
net/bridge/br_vlan_options.c
88
br_multicast_ngroups_get_max(&v->port_mcast_ctx))))
net/bridge/br_vlan_tunnel.c
120
struct net_bridge_vlan *v;
net/bridge/br_vlan_tunnel.c
125
v = br_vlan_find(vg, vid);
net/bridge/br_vlan_tunnel.c
126
if (!v)
net/bridge/br_vlan_tunnel.c
129
vlan_tunnel_info_del(vg, v);
net/bridge/netfilter/ebtables.c
62
int v = *(compat_int_t *)src;
net/bridge/netfilter/ebtables.c
64
if (v >= 0)
net/bridge/netfilter/ebtables.c
65
v += xt_compat_calc_jump(NFPROTO_BRIDGE, v);
net/bridge/netfilter/ebtables.c
66
memcpy(dst, &v, sizeof(v));
net/can/bcm.c
208
static int bcm_proc_show(struct seq_file *m, void *v)
net/can/proc.c
216
static int can_stats_proc_show(struct seq_file *m, void *v)
net/can/proc.c
281
static int can_reset_stats_proc_show(struct seq_file *m, void *v)
net/can/proc.c
314
static int can_rcvlist_proc_show(struct seq_file *m, void *v)
net/can/proc.c
370
static int can_rcvlist_sff_proc_show(struct seq_file *m, void *v)
net/can/proc.c
403
static int can_rcvlist_eff_proc_show(struct seq_file *m, void *v)
net/ceph/crush/mapper.c
851
void crush_init_workspace(const struct crush_map *map, void *v)
net/ceph/crush/mapper.c
853
struct crush_work *w = v;
net/ceph/crush/mapper.c
864
v += sizeof(struct crush_work);
net/ceph/crush/mapper.c
865
w->work = v;
net/ceph/crush/mapper.c
866
v += map->max_buckets * sizeof(struct crush_work_bucket *);
net/ceph/crush/mapper.c
871
w->work[b] = v;
net/ceph/crush/mapper.c
874
v += sizeof(struct crush_work_bucket);
net/ceph/crush/mapper.c
879
w->work[b]->perm = v;
net/ceph/crush/mapper.c
880
v += map->buckets[b]->size * sizeof(__u32);
net/ceph/crush/mapper.c
882
BUG_ON(v - (void *)w != map->working_size);
net/ceph/osdmap.c
1282
const char *prefix, u8 *v)
net/ceph/osdmap.c
1323
*v = struct_v;
net/core/bpf_sk_storage.c
774
static void *bpf_sk_storage_map_seq_next(struct seq_file *seq, void *v,
net/core/bpf_sk_storage.c
781
return bpf_sk_storage_map_seq_find_next(seq->private, v);
net/core/bpf_sk_storage.c
821
static int bpf_sk_storage_map_seq_show(struct seq_file *seq, void *v)
net/core/bpf_sk_storage.c
823
return __bpf_sk_storage_map_seq_show(seq, v);
net/core/bpf_sk_storage.c
826
static void bpf_sk_storage_map_seq_stop(struct seq_file *seq, void *v)
net/core/bpf_sk_storage.c
829
if (!v)
net/core/bpf_sk_storage.c
830
(void)__bpf_sk_storage_map_seq_show(seq, v);
net/core/dev.c
11261
void __percpu *v;
net/core/dev.c
11275
v = dev->lstats = netdev_alloc_pcpu_stats(struct pcpu_lstats);
net/core/dev.c
11278
v = dev->tstats = netdev_alloc_pcpu_stats(struct pcpu_sw_netstats);
net/core/dev.c
11281
v = dev->dstats = netdev_alloc_pcpu_stats(struct pcpu_dstats);
net/core/dev.c
11287
return v ? 0 : -ENOMEM;
net/core/filter.c
7371
offsetof(struct minmax_sample, v));
net/core/neighbour.c
3263
void *v;
net/core/neighbour.c
3265
v = state->neigh_sub_iter(state, n, pos ? pos : &fakep);
net/core/neighbour.c
3266
if (!v)
net/core/neighbour.c
3269
return v;
net/core/neighbour.c
3308
void *v = state->neigh_sub_iter(state, n, pos);
net/core/neighbour.c
3310
if (v)
net/core/neighbour.c
3443
void *neigh_seq_next(struct seq_file *seq, void *v, loff_t *pos)
net/core/neighbour.c
3448
if (v == SEQ_START_TOKEN) {
net/core/neighbour.c
3455
rc = neigh_get_next(seq, v, NULL);
net/core/neighbour.c
3462
rc = pneigh_get_next(seq, v, NULL);
net/core/neighbour.c
3470
void neigh_seq_stop(struct seq_file *seq, void *v)
net/core/neighbour.c
3501
static void *neigh_stat_seq_next(struct seq_file *seq, void *v, loff_t *pos)
net/core/neighbour.c
3516
static void neigh_stat_seq_stop(struct seq_file *seq, void *v)
net/core/neighbour.c
3521
static int neigh_stat_seq_show(struct seq_file *seq, void *v)
net/core/neighbour.c
3524
struct neigh_statistics *st = v;
net/core/neighbour.c
3526
if (v == SEQ_START_TOKEN) {
net/core/net-procfs.c
113
static void *softnet_seq_next(struct seq_file *seq, void *v, loff_t *pos)
net/core/net-procfs.c
119
static void softnet_seq_stop(struct seq_file *seq, void *v)
net/core/net-procfs.c
123
static int softnet_seq_show(struct seq_file *seq, void *v)
net/core/net-procfs.c
125
struct softnet_data *sd = v;
net/core/net-procfs.c
229
static void *ptype_seq_next(struct seq_file *seq, void *v, loff_t *pos)
net/core/net-procfs.c
239
if (v == SEQ_START_TOKEN)
net/core/net-procfs.c
242
pt = v;
net/core/net-procfs.c
287
static void ptype_seq_stop(struct seq_file *seq, void *v)
net/core/net-procfs.c
293
static int ptype_seq_show(struct seq_file *seq, void *v)
net/core/net-procfs.c
296
struct packet_type *pt = v;
net/core/net-procfs.c
299
if (v == SEQ_START_TOKEN) {
net/core/net-procfs.c
32
static void *dev_seq_next(struct seq_file *seq, void *v, loff_t *pos)
net/core/net-procfs.c
367
static int dev_mc_seq_show(struct seq_file *seq, void *v)
net/core/net-procfs.c
370
struct net_device *dev = v;
net/core/net-procfs.c
372
if (v == SEQ_START_TOKEN)
net/core/net-procfs.c
38
static void dev_seq_stop(struct seq_file *seq, void *v)
net/core/net-procfs.c
72
static int dev_seq_show(struct seq_file *seq, void *v)
net/core/net-procfs.c
74
if (v == SEQ_START_TOKEN)
net/core/net-procfs.c
81
dev_seq_printf_stats(seq, v);
net/core/netclassid_cgroup.c
71
static int update_classid_sock(const void *v, struct file *file, unsigned int n)
net/core/netclassid_cgroup.c
73
struct update_classid_context *ctx = (void *)v;
net/core/netevent.c
59
int call_netevent_notifiers(unsigned long val, void *v)
net/core/netevent.c
61
return atomic_notifier_call_chain(&netevent_notif_chain, val, v);
net/core/netprio_cgroup.c
183
static int read_priomap(struct seq_file *sf, void *v)
net/core/netprio_cgroup.c
219
static int update_netprio(const void *v, struct file *file, unsigned n)
net/core/netprio_cgroup.c
225
(unsigned long)v);
net/core/netprio_cgroup.c
235
void *v = (void *)(unsigned long)css->id;
net/core/netprio_cgroup.c
238
iterate_fd(p->files, 0, update_netprio, v);
net/core/pktgen.c
1885
static int pktgen_thread_show(struct seq_file *seq, void *v)
net/core/pktgen.c
513
static int pgctrl_show(struct seq_file *seq, void *v)
net/core/pktgen.c
566
static int pktgen_if_show(struct seq_file *seq, void *v)
net/core/sock.c
1740
} v;
net/core/sock.c
1750
memset(&v, 0, sizeof(v));
net/core/sock.c
1754
v.val = sock_flag(sk, SOCK_DBG);
net/core/sock.c
1758
v.val = sock_flag(sk, SOCK_LOCALROUTE);
net/core/sock.c
1762
v.val = sock_flag(sk, SOCK_BROADCAST);
net/core/sock.c
1766
v.val = READ_ONCE(sk->sk_sndbuf);
net/core/sock.c
1770
v.val = READ_ONCE(sk->sk_rcvbuf);
net/core/sock.c
1774
v.val = sk->sk_reuse;
net/core/sock.c
1778
v.val = sk->sk_reuseport;
net/core/sock.c
1782
v.val = sock_flag(sk, SOCK_KEEPOPEN);
net/core/sock.c
1786
v.val = sk->sk_type;
net/core/sock.c
1790
v.val = sk->sk_protocol;
net/core/sock.c
1794
v.val = sk->sk_family;
net/core/sock.c
1798
v.val = -sock_error(sk);
net/core/sock.c
1799
if (v.val == 0)
net/core/sock.c
1800
v.val = xchg(&sk->sk_err_soft, 0);
net/core/sock.c
1804
v.val = sock_flag(sk, SOCK_URGINLINE);
net/core/sock.c
1808
v.val = sk->sk_no_check_tx;
net/core/sock.c
1812
v.val = READ_ONCE(sk->sk_priority);
net/core/sock.c
1816
lv = sizeof(v.ling);
net/core/sock.c
1817
v.ling.l_onoff = sock_flag(sk, SOCK_LINGER);
net/core/sock.c
1818
v.ling.l_linger = READ_ONCE(sk->sk_lingertime) / HZ;
net/core/sock.c
1825
v.val = sock_flag(sk, SOCK_RCVTSTAMP) &&
net/core/sock.c
1831
v.val = sock_flag(sk, SOCK_RCVTSTAMPNS) && !sock_flag(sk, SOCK_TSTAMP_NEW);
net/core/sock.c
1835
v.val = sock_flag(sk, SOCK_RCVTSTAMP) && sock_flag(sk, SOCK_TSTAMP_NEW);
net/core/sock.c
1839
v.val = sock_flag(sk, SOCK_RCVTSTAMPNS) && sock_flag(sk, SOCK_TSTAMP_NEW);
net/core/sock.c
1844
lv = sizeof(v.timestamping);
net/core/sock.c
1850
v.timestamping.flags = READ_ONCE(sk->sk_tsflags);
net/core/sock.c
1851
v.timestamping.bind_phc = READ_ONCE(sk->sk_bind_phc);
net/core/sock.c
1857
lv = sock_get_timeout(READ_ONCE(sk->sk_rcvtimeo), &v,
net/core/sock.c
1863
lv = sock_get_timeout(READ_ONCE(sk->sk_sndtimeo), &v,
net/core/sock.c
1868
v.val = READ_ONCE(sk->sk_rcvlowat);
net/core/sock.c
1872
v.val = 1;
net/core/sock.c
1879
v.val = sk->sk_scm_credentials;
net/core/sock.c
1886
v.val = sk->sk_scm_pidfd;
net/core/sock.c
1893
v.val = sk->sk_scm_rights;
net/core/sock.c
1994
v.val = sk->sk_state == TCP_LISTEN;
net/core/sock.c
2001
v.val = sk->sk_scm_security;
net/core/sock.c
2009
v.val = READ_ONCE(sk->sk_mark);
net/core/sock.c
2013
v.val = sock_flag(sk, SOCK_RCVMARK);
net/core/sock.c
2017
v.val = sock_flag(sk, SOCK_RCVPRIORITY);
net/core/sock.c
2021
v.val = sock_flag(sk, SOCK_RXQ_OVFL);
net/core/sock.c
2025
v.val = sock_flag(sk, SOCK_WIFI_STATUS);
net/core/sock.c
2032
v.val = READ_ONCE(sk->sk_peek_off);
net/core/sock.c
2035
v.val = sock_flag(sk, SOCK_NOFCS);
net/core/sock.c
2049
v.val = sock_flag(sk, SOCK_FILTER_LOCKED);
net/core/sock.c
2053
v.val = bpf_tell_extensions();
net/core/sock.c
2057
v.val = sock_flag(sk, SOCK_SELECT_ERR_QUEUE);
net/core/sock.c
2062
v.val = READ_ONCE(sk->sk_ll_usec);
net/core/sock.c
2065
v.val = READ_ONCE(sk->sk_prefer_busy_poll);
net/core/sock.c
2071
if (sizeof(v.ulval) != sizeof(v.val) && len >= sizeof(v.ulval)) {
net/core/sock.c
2072
lv = sizeof(v.ulval);
net/core/sock.c
2073
v.ulval = READ_ONCE(sk->sk_max_pacing_rate);
net/core/sock.c
2076
v.val = min_t(unsigned long, ~0U,
net/core/sock.c
2082
v.val = READ_ONCE(sk->sk_incoming_cpu);
net/core/sock.c
2100
v.val = READ_ONCE(sk->sk_napi_id);
net/core/sock.c
2103
if (!napi_id_valid(v.val))
net/core/sock.c
2104
v.val = 0;
net/core/sock.c
2113
v.val64 = sock_gen_cookie(sk);
net/core/sock.c
2117
v.val = sock_flag(sk, SOCK_ZEROCOPY);
net/core/sock.c
2121
lv = sizeof(v.txtime);
net/core/sock.c
2122
v.txtime.clockid = sk->sk_clockid;
net/core/sock.c
2123
v.txtime.flags |= sk->sk_txtime_deadline_mode ?
net/core/sock.c
2125
v.txtime.flags |= sk->sk_txtime_report_errors ?
net/core/sock.c
2130
v.val = READ_ONCE(sk->sk_bound_dev_if);
net/core/sock.c
2137
v.val64 = sock_net(sk)->net_cookie;
net/core/sock.c
2141
v.val = sk->sk_userlocks & SOCK_BUF_LOCK_MASK;
net/core/sock.c
2145
v.val = READ_ONCE(sk->sk_reserved_mem);
net/core/sock.c
2153
v.val = READ_ONCE(sk->sk_txrehash);
net/core/sock.c
2165
if (copy_to_sockptr(optval, &v, len))
net/core/sock.c
4291
static void *proto_seq_next(struct seq_file *seq, void *v, loff_t *pos)
net/core/sock.c
4293
return seq_list_next(v, &proto_list, pos);
net/core/sock.c
4296
static void proto_seq_stop(struct seq_file *seq, void *v)
net/core/sock.c
4350
static int proto_seq_show(struct seq_file *seq, void *v)
net/core/sock.c
4352
if (v == &proto_list)
net/core/sock.c
4364
proto_seq_printf(seq, list_entry(v, struct proto, node));
net/core/sock_map.c
1359
static void *sock_hash_seq_next(struct seq_file *seq, void *v, loff_t *pos)
net/core/sock_map.c
1365
return sock_hash_seq_find_next(info, v);
net/core/sock_map.c
1368
static int sock_hash_seq_show(struct seq_file *seq, void *v)
net/core/sock_map.c
1373
struct bpf_shtab_elem *elem = v;
net/core/sock_map.c
1392
static void sock_hash_seq_stop(struct seq_file *seq, void *v)
net/core/sock_map.c
1395
if (!v)
net/core/sock_map.c
745
static void *sock_map_seq_next(struct seq_file *seq, void *v, loff_t *pos)
net/core/sock_map.c
756
static int sock_map_seq_show(struct seq_file *seq, void *v)
net/core/sock_map.c
765
prog = bpf_iter_get_info(&meta, !v);
net/core/sock_map.c
771
if (v) {
net/core/sock_map.c
779
static void sock_map_seq_stop(struct seq_file *seq, void *v)
net/core/sock_map.c
782
if (!v)
net/dcb/dcbevent.c
27
int call_dcbevent_notifiers(unsigned long val, void *v)
net/dcb/dcbevent.c
29
return atomic_notifier_call_chain(&dcbevent_notif_chain, val, v);
net/dsa/dsa.c
1489
struct dsa_vlan *v, *n;
net/dsa/dsa.c
1520
list_for_each_entry_safe(v, n, &dp->vlans, list) {
net/dsa/dsa.c
1523
v->vid, dp->index);
net/dsa/dsa.c
1524
list_del(&v->list);
net/dsa/dsa.c
1525
kfree(v);
net/dsa/port.c
33
static int dsa_port_notify(const struct dsa_port *dp, unsigned long e, void *v)
net/dsa/port.c
35
return dsa_tree_notify(dp->ds->dst, e, v);
net/dsa/switch.c
1084
int dsa_tree_notify(struct dsa_switch_tree *dst, unsigned long e, void *v)
net/dsa/switch.c
1089
err = raw_notifier_call_chain(nh, e, v);
net/dsa/switch.c
1106
int dsa_broadcast(unsigned long e, void *v)
net/dsa/switch.c
1112
err = dsa_tree_notify(dst, e, v);
net/dsa/switch.c
679
struct dsa_vlan *v;
net/dsa/switch.c
681
list_for_each_entry(v, vlan_list, list)
net/dsa/switch.c
682
if (v->vid == vlan->vid)
net/dsa/switch.c
683
return v;
net/dsa/switch.c
694
struct dsa_vlan *v;
net/dsa/switch.c
715
v = dsa_vlan_find(&dp->vlans, vlan);
net/dsa/switch.c
716
if (v) {
net/dsa/switch.c
717
refcount_inc(&v->refcount);
net/dsa/switch.c
718
trace_dsa_vlan_add_bump(dp, vlan, &v->refcount);
net/dsa/switch.c
722
v = kzalloc_obj(*v);
net/dsa/switch.c
723
if (!v) {
net/dsa/switch.c
731
kfree(v);
net/dsa/switch.c
735
v->vid = vlan->vid;
net/dsa/switch.c
736
refcount_set(&v->refcount, 1);
net/dsa/switch.c
737
list_add_tail(&v->list, &dp->vlans);
net/dsa/switch.c
750
struct dsa_vlan *v;
net/dsa/switch.c
763
v = dsa_vlan_find(&dp->vlans, vlan);
net/dsa/switch.c
764
if (!v) {
net/dsa/switch.c
770
if (!refcount_dec_and_test(&v->refcount)) {
net/dsa/switch.c
771
trace_dsa_vlan_del_drop(dp, vlan, &v->refcount);
net/dsa/switch.c
778
refcount_set(&v->refcount, 1);
net/dsa/switch.c
782
list_del(&v->list);
net/dsa/switch.c
783
kfree(v);
net/dsa/switch.h
117
int dsa_tree_notify(struct dsa_switch_tree *dst, unsigned long e, void *v);
net/dsa/switch.h
118
int dsa_broadcast(unsigned long e, void *v);
net/dsa/tag_8021q.c
133
struct dsa_tag_8021q_vlan *v;
net/dsa/tag_8021q.c
135
list_for_each_entry(v, &ctx->vlans, list)
net/dsa/tag_8021q.c
136
if (v->vid == vid && v->port == port)
net/dsa/tag_8021q.c
137
return v;
net/dsa/tag_8021q.c
147
struct dsa_tag_8021q_vlan *v;
net/dsa/tag_8021q.c
155
v = dsa_tag_8021q_vlan_find(ctx, port, vid);
net/dsa/tag_8021q.c
156
if (v) {
net/dsa/tag_8021q.c
157
refcount_inc(&v->refcount);
net/dsa/tag_8021q.c
161
v = kzalloc_obj(*v);
net/dsa/tag_8021q.c
162
if (!v)
net/dsa/tag_8021q.c
167
kfree(v);
net/dsa/tag_8021q.c
171
v->vid = vid;
net/dsa/tag_8021q.c
172
v->port = port;
net/dsa/tag_8021q.c
173
refcount_set(&v->refcount, 1);
net/dsa/tag_8021q.c
174
list_add_tail(&v->list, &ctx->vlans);
net/dsa/tag_8021q.c
183
struct dsa_tag_8021q_vlan *v;
net/dsa/tag_8021q.c
191
v = dsa_tag_8021q_vlan_find(ctx, port, vid);
net/dsa/tag_8021q.c
192
if (!v)
net/dsa/tag_8021q.c
195
if (!refcount_dec_and_test(&v->refcount))
net/dsa/tag_8021q.c
200
refcount_set(&v->refcount, 1);
net/dsa/tag_8021q.c
204
list_del(&v->list);
net/dsa/tag_8021q.c
205
kfree(v);
net/dsa/tag_8021q.c
449
struct dsa_tag_8021q_vlan *v, *n;
net/dsa/tag_8021q.c
453
list_for_each_entry_safe(v, n, &ctx->vlans, list) {
net/dsa/tag_8021q.c
454
list_del(&v->list);
net/dsa/tag_8021q.c
455
kfree(v);
net/dsa/user.c
178
struct dsa_vlan *v;
net/dsa/user.c
1802
struct dsa_vlan *v;
net/dsa/user.c
1826
v = kzalloc_obj(*v);
net/dsa/user.c
1827
if (!v) {
net/dsa/user.c
1834
v->vid = vid;
net/dsa/user.c
1835
list_add_tail(&v->list, &dp->user_vlans);
net/dsa/user.c
187
list_for_each_entry(v, &dp->user_vlans, list) {
net/dsa/user.c
1875
struct dsa_vlan *v;
net/dsa/user.c
188
err = cb(arg, v->vid);
net/dsa/user.c
1892
v = dsa_vlan_find(&dp->user_vlans, &vlan);
net/dsa/user.c
1893
if (!v) {
net/dsa/user.c
1898
list_del(&v->list);
net/dsa/user.c
1899
kfree(v);
net/ipv4/af_inet.c
1678
u64 v;
net/ipv4/af_inet.c
1685
v = *(((u64 *)bhptr) + offt);
net/ipv4/af_inet.c
1688
return v;
net/ipv4/arp.c
1464
static int arp_seq_show(struct seq_file *seq, void *v)
net/ipv4/arp.c
1466
if (v == SEQ_START_TOKEN) {
net/ipv4/arp.c
1473
arp_format_pneigh_entry(seq, v);
net/ipv4/arp.c
1475
arp_format_neigh_entry(seq, v);
net/ipv4/fib_trie.c
2610
static int fib_triestat_seq_show(struct seq_file *seq, void *v)
net/ipv4/fib_trie.c
2681
static void *fib_trie_seq_next(struct seq_file *seq, void *v, loff_t *pos)
net/ipv4/fib_trie.c
2721
static void fib_trie_seq_stop(struct seq_file *seq, void *v)
net/ipv4/fib_trie.c
2771
static int fib_trie_seq_show(struct seq_file *seq, void *v)
net/ipv4/fib_trie.c
2774
struct key_vector *n = v;
net/ipv4/fib_trie.c
2889
static void *fib_route_seq_next(struct seq_file *seq, void *v, loff_t *pos)
net/ipv4/fib_trie.c
2898
if ((v == SEQ_START_TOKEN) || key)
net/ipv4/fib_trie.c
2911
static void fib_route_seq_stop(struct seq_file *seq, void *v)
net/ipv4/fib_trie.c
2941
static int fib_route_seq_show(struct seq_file *seq, void *v)
net/ipv4/fib_trie.c
2946
struct key_vector *l = v;
net/ipv4/fib_trie.c
2949
if (v == SEQ_START_TOKEN) {
net/ipv4/igmp.c
2918
static void *igmp_mc_seq_next(struct seq_file *seq, void *v, loff_t *pos)
net/ipv4/igmp.c
2921
if (v == SEQ_START_TOKEN)
net/ipv4/igmp.c
2924
im = igmp_mc_get_next(seq, v);
net/ipv4/igmp.c
2929
static void igmp_mc_seq_stop(struct seq_file *seq, void *v)
net/ipv4/igmp.c
2939
static int igmp_mc_seq_show(struct seq_file *seq, void *v)
net/ipv4/igmp.c
2941
if (v == SEQ_START_TOKEN)
net/ipv4/igmp.c
2945
struct ip_mc_list *im = v;
net/ipv4/igmp.c
3061
static void *igmp_mcf_seq_next(struct seq_file *seq, void *v, loff_t *pos)
net/ipv4/igmp.c
3064
if (v == SEQ_START_TOKEN)
net/ipv4/igmp.c
3067
psf = igmp_mcf_get_next(seq, v);
net/ipv4/igmp.c
3072
static void igmp_mcf_seq_stop(struct seq_file *seq, void *v)
net/ipv4/igmp.c
3085
static int igmp_mcf_seq_show(struct seq_file *seq, void *v)
net/ipv4/igmp.c
3087
struct ip_sf_list *psf = v;
net/ipv4/igmp.c
3090
if (v == SEQ_START_TOKEN) {
net/ipv4/ipcomp.c
103
u32 mark = x->mark.v & x->mark.m;
net/ipv4/ipconfig.c
1328
static int pnp_seq_show(struct seq_file *seq, void *v)
net/ipv4/ipconfig.c
1386
static int ntp_servers_show(struct seq_file *seq, void *v)
net/ipv4/ipconfig.c
1679
char *v;
net/ipv4/ipconfig.c
1682
v = strchr(client_id, ',');
net/ipv4/ipconfig.c
1683
if (!v)
net/ipv4/ipconfig.c
1685
*v = 0;
net/ipv4/ipconfig.c
1688
strscpy(dhcp_client_identifier + 1, v + 1,
net/ipv4/ipconfig.c
1690
*v = ',';
net/ipv4/ipmr.c
1769
struct vif_device *v;
net/ipv4/ipmr.c
1776
v = &mrt->vif_table[0];
net/ipv4/ipmr.c
1777
for (ct = 0; ct < mrt->maxvif; ct++, v++) {
net/ipv4/ipmr.c
1778
if (rcu_access_pointer(v->dev) == dev)
net/ipv4/ipmr.c
3081
static void ipmr_vif_seq_stop(struct seq_file *seq, void *v)
net/ipv4/ipmr.c
3087
static int ipmr_vif_seq_show(struct seq_file *seq, void *v)
net/ipv4/ipmr.c
3092
if (v == SEQ_START_TOKEN) {
net/ipv4/ipmr.c
3096
const struct vif_device *vif = v;
net/ipv4/ipmr.c
3131
static int ipmr_mfc_seq_show(struct seq_file *seq, void *v)
net/ipv4/ipmr.c
3135
if (v == SEQ_START_TOKEN) {
net/ipv4/ipmr.c
3139
const struct mfc_cache *mfc = v;
net/ipv4/ipmr.c
459
static struct net_device *ipmr_new_tunnel(struct net *net, struct vifctl *v)
net/ipv4/ipmr.c
469
p.iph.daddr = v->vifc_rmt_addr.s_addr;
net/ipv4/ipmr.c
470
p.iph.saddr = v->vifc_lcl_addr.s_addr;
net/ipv4/ipmr.c
474
sprintf(p.name, "dvmrp%d", v->vifc_vifi);
net/ipv4/ipmr.c
671
struct vif_device *v;
net/ipv4/ipmr.c
678
v = &mrt->vif_table[vifi];
net/ipv4/ipmr.c
680
dev = rtnl_dereference(v->dev);
net/ipv4/ipmr.c
685
call_ipmr_vif_entry_notifiers(net, FIB_EVENT_VIF_DEL, v, dev,
net/ipv4/ipmr.c
687
RCU_INIT_POINTER(v->dev, NULL);
net/ipv4/ipmr.c
716
if (v->flags & (VIFF_TUNNEL | VIFF_REGISTER) && !notify)
net/ipv4/ipmr.c
719
netdev_put(dev, &v->dev_tracker);
net/ipv4/ipmr.c
833
struct vif_device *v = &mrt->vif_table[vifi];
net/ipv4/ipmr.c
900
vif_device_init(v, dev, vifc->vifc_rate_limit,
net/ipv4/ipmr.c
907
memcpy(v->dev_parent_id.id, ppid.id, ppid.id_len);
net/ipv4/ipmr.c
908
v->dev_parent_id.id_len = ppid.id_len;
net/ipv4/ipmr.c
910
v->dev_parent_id.id_len = 0;
net/ipv4/ipmr.c
913
v->local = vifc->vifc_lcl_addr.s_addr;
net/ipv4/ipmr.c
914
v->remote = vifc->vifc_rmt_addr.s_addr;
net/ipv4/ipmr.c
918
rcu_assign_pointer(v->dev, dev);
net/ipv4/ipmr.c
919
netdev_tracker_alloc(dev, &v->dev_tracker, GFP_ATOMIC);
net/ipv4/ipmr.c
920
if (v->flags & VIFF_REGISTER) {
net/ipv4/ipmr.c
927
call_ipmr_vif_entry_notifiers(net, FIB_EVENT_VIF_ADD, v, dev,
net/ipv4/ipmr_base.c
128
void *mr_vif_seq_next(struct seq_file *seq, void *v, loff_t *pos)
net/ipv4/ipmr_base.c
135
if (v == SEQ_START_TOKEN)
net/ipv4/ipmr_base.c
16
RCU_INIT_POINTER(v->dev, NULL);
net/ipv4/ipmr_base.c
17
v->bytes_in = 0;
net/ipv4/ipmr_base.c
172
void *mr_mfc_seq_next(struct seq_file *seq, void *v,
net/ipv4/ipmr_base.c
178
struct mr_mfc *c = v;
net/ipv4/ipmr_base.c
18
v->bytes_out = 0;
net/ipv4/ipmr_base.c
182
if (v == SEQ_START_TOKEN)
net/ipv4/ipmr_base.c
19
v->pkt_in = 0;
net/ipv4/ipmr_base.c
20
v->pkt_out = 0;
net/ipv4/ipmr_base.c
21
v->rate_limit = rate_limit;
net/ipv4/ipmr_base.c
22
v->flags = flags;
net/ipv4/ipmr_base.c
23
v->threshold = threshold;
net/ipv4/ipmr_base.c
24
if (v->flags & get_iflink_mask)
net/ipv4/ipmr_base.c
25
v->link = dev_get_iflink(dev);
net/ipv4/ipmr_base.c
27
v->link = dev->ifindex;
net/ipv4/ipmr_base.c
410
struct vif_device *v = &mrt->vif_table[0];
net/ipv4/ipmr_base.c
417
for (vifi = 0; vifi < mrt->maxvif; vifi++, v++) {
net/ipv4/ipmr_base.c
418
vif_dev = rcu_dereference(v->dev);
net/ipv4/ipmr_base.c
423
FIB_EVENT_VIF_ADD, v,
net/ipv4/ipmr_base.c
9
void vif_device_init(struct vif_device *v,
net/ipv4/netfilter/arp_tables.c
237
int v;
net/ipv4/netfilter/arp_tables.c
239
v = ((struct xt_standard_target *)t)->verdict;
net/ipv4/netfilter/arp_tables.c
240
if (v < 0) {
net/ipv4/netfilter/arp_tables.c
242
if (v != XT_RETURN) {
net/ipv4/netfilter/arp_tables.c
243
verdict = (unsigned int)(-v) - 1;
net/ipv4/netfilter/arp_tables.c
255
if (table_base + v
net/ipv4/netfilter/arp_tables.c
264
e = get_entry(table_base, v);
net/ipv4/netfilter/arp_tables.c
720
int v = *(compat_int_t *)src;
net/ipv4/netfilter/arp_tables.c
722
if (v > 0)
net/ipv4/netfilter/arp_tables.c
723
v += xt_compat_calc_jump(NFPROTO_ARP, v);
net/ipv4/netfilter/arp_tables.c
724
memcpy(dst, &v, sizeof(v));
net/ipv4/netfilter/ip_tables.c
311
int v;
net/ipv4/netfilter/ip_tables.c
313
v = ((struct xt_standard_target *)t)->verdict;
net/ipv4/netfilter/ip_tables.c
314
if (v < 0) {
net/ipv4/netfilter/ip_tables.c
316
if (v != XT_RETURN) {
net/ipv4/netfilter/ip_tables.c
317
verdict = (unsigned int)(-v) - 1;
net/ipv4/netfilter/ip_tables.c
329
if (table_base + v != ipt_next_entry(e) &&
net/ipv4/netfilter/ip_tables.c
338
e = get_entry(table_base, v);
net/ipv4/netfilter/ip_tables.c
873
int v = *(compat_int_t *)src;
net/ipv4/netfilter/ip_tables.c
875
if (v > 0)
net/ipv4/netfilter/ip_tables.c
876
v += xt_compat_calc_jump(AF_INET, v);
net/ipv4/netfilter/ip_tables.c
877
memcpy(dst, &v, sizeof(v));
net/ipv4/ping.c
1083
void *ping_seq_next(struct seq_file *seq, void *v, loff_t *pos)
net/ipv4/ping.c
1087
if (v == SEQ_START_TOKEN)
net/ipv4/ping.c
1090
sk = ping_get_next(seq, v);
net/ipv4/ping.c
1097
void ping_seq_stop(struct seq_file *seq, void *v)
net/ipv4/ping.c
1125
static int ping_v4_seq_show(struct seq_file *seq, void *v)
net/ipv4/ping.c
1128
if (v == SEQ_START_TOKEN)
net/ipv4/ping.c
1135
ping_v4_format_sock(v, seq, state->bucket);
net/ipv4/proc.c
385
static int snmp_seq_show_ipstats(struct seq_file *seq, void *v)
net/ipv4/proc.c
412
static int snmp_seq_show_tcp_udp(struct seq_file *seq, void *v)
net/ipv4/proc.c
467
static int snmp_seq_show(struct seq_file *seq, void *v)
net/ipv4/proc.c
469
snmp_seq_show_ipstats(seq, v);
net/ipv4/proc.c
474
snmp_seq_show_tcp_udp(seq, v);
net/ipv4/proc.c
482
static int netstat_seq_show(struct seq_file *seq, void *v)
net/ipv4/proc.c
52
static int sockstat_seq_show(struct seq_file *seq, void *v)
net/ipv4/raw.c
1013
void *raw_seq_next(struct seq_file *seq, void *v, loff_t *pos)
net/ipv4/raw.c
1017
if (v == SEQ_START_TOKEN)
net/ipv4/raw.c
1020
sk = raw_get_next(seq, v);
net/ipv4/raw.c
1026
void raw_seq_stop(struct seq_file *seq, void *v)
net/ipv4/raw.c
1054
static int raw_seq_show(struct seq_file *seq, void *v)
net/ipv4/raw.c
1056
if (v == SEQ_START_TOKEN)
net/ipv4/raw.c
1061
raw_sock_seq_show(seq, v, raw_seq_private(seq)->bucket);
net/ipv4/route.c
207
static void *rt_cache_seq_next(struct seq_file *seq, void *v, loff_t *pos)
net/ipv4/route.c
213
static void rt_cache_seq_stop(struct seq_file *seq, void *v)
net/ipv4/route.c
217
static int rt_cache_seq_show(struct seq_file *seq, void *v)
net/ipv4/route.c
219
if (v == SEQ_START_TOKEN)
net/ipv4/route.c
250
static void *rt_cpu_seq_next(struct seq_file *seq, void *v, loff_t *pos)
net/ipv4/route.c
265
static void rt_cpu_seq_stop(struct seq_file *seq, void *v)
net/ipv4/route.c
270
static int rt_cpu_seq_show(struct seq_file *seq, void *v)
net/ipv4/route.c
272
struct rt_cache_stat *st = v;
net/ipv4/route.c
274
if (v == SEQ_START_TOKEN) {
net/ipv4/route.c
313
static int rt_acct_proc_show(struct seq_file *m, void *v)
net/ipv4/tcp_cdg.c
105
static const u16 v[] = {
net/ipv4/tcp_cdg.c
124
u32 y = v[i & -(msb & 1)] + U32_C(1);
net/ipv4/tcp_cubic.c
178
static const u8 v[] = {
net/ipv4/tcp_cubic.c
192
return ((u32)v[(u32)a] + 35) >> 6;
net/ipv4/tcp_cubic.c
198
x = ((u32)(((u32)v[shift] + 10) << b)) >> 6;
net/ipv4/tcp_ipv4.c
2771
void *tcp_seq_next(struct seq_file *seq, void *v, loff_t *pos)
net/ipv4/tcp_ipv4.c
2776
if (v == SEQ_START_TOKEN) {
net/ipv4/tcp_ipv4.c
2783
rc = listening_get_next(seq, v);
net/ipv4/tcp_ipv4.c
2792
rc = established_get_next(seq, v);
net/ipv4/tcp_ipv4.c
2802
void tcp_seq_stop(struct seq_file *seq, void *v)
net/ipv4/tcp_ipv4.c
2809
if (v != SEQ_START_TOKEN)
net/ipv4/tcp_ipv4.c
2813
if (v)
net/ipv4/tcp_ipv4.c
2931
static int tcp4_seq_show(struct seq_file *seq, void *v)
net/ipv4/tcp_ipv4.c
2934
struct sock *sk = v;
net/ipv4/tcp_ipv4.c
2937
if (v == SEQ_START_TOKEN) {
net/ipv4/tcp_ipv4.c
2946
get_timewait4_sock(v, seq, st->num);
net/ipv4/tcp_ipv4.c
2948
get_openreq4(v, seq, st->num);
net/ipv4/tcp_ipv4.c
2950
get_tcp4_sock(v, seq, st->num);
net/ipv4/tcp_ipv4.c
3264
static void *bpf_iter_tcp_seq_next(struct seq_file *seq, void *v, loff_t *pos)
net/ipv4/tcp_ipv4.c
3296
static int bpf_iter_tcp_seq_show(struct seq_file *seq, void *v)
net/ipv4/tcp_ipv4.c
3300
struct sock *sk = v;
net/ipv4/tcp_ipv4.c
3304
if (v == SEQ_START_TOKEN)
net/ipv4/tcp_ipv4.c
3318
const struct request_sock *req = v;
net/ipv4/tcp_ipv4.c
3328
ret = tcp_prog_seq_show(prog, &meta, v, uid);
net/ipv4/tcp_ipv4.c
3337
static void bpf_iter_tcp_seq_stop(struct seq_file *seq, void *v)
net/ipv4/tcp_ipv4.c
3343
if (!v) {
net/ipv4/tcp_ipv4.c
3347
(void)tcp_prog_seq_show(prog, &meta, v, 0);
net/ipv4/udp.c
3399
void *udp_seq_next(struct seq_file *seq, void *v, loff_t *pos)
net/ipv4/udp.c
3403
if (v == SEQ_START_TOKEN)
net/ipv4/udp.c
3406
sk = udp_get_next(seq, v);
net/ipv4/udp.c
3413
void udp_seq_stop(struct seq_file *seq, void *v)
net/ipv4/udp.c
3447
int udp4_seq_show(struct seq_file *seq, void *v)
net/ipv4/udp.c
3450
if (v == SEQ_START_TOKEN)
net/ipv4/udp.c
3457
udp4_format_sock(v, seq, state->bucket);
net/ipv4/udp.c
3617
static void *bpf_iter_udp_seq_next(struct seq_file *seq, void *v, loff_t *pos)
net/ipv4/udp.c
3665
static int bpf_iter_udp_seq_show(struct seq_file *seq, void *v)
net/ipv4/udp.c
3670
struct sock *sk = v;
net/ipv4/udp.c
3674
if (v == SEQ_START_TOKEN)
net/ipv4/udp.c
3687
ret = udp_prog_seq_show(prog, &meta, v, uid, state->bucket);
net/ipv4/udp.c
3711
static void bpf_iter_udp_seq_stop(struct seq_file *seq, void *v)
net/ipv4/udp.c
3717
if (!v) {
net/ipv4/udp.c
3721
(void)udp_prog_seq_show(prog, &meta, v, 0, 0);
net/ipv4/udp_impl.h
26
int udp4_seq_show(struct seq_file *seq, void *v);
net/ipv6/addrconf.c
4472
static void *if6_seq_next(struct seq_file *seq, void *v, loff_t *pos)
net/ipv6/addrconf.c
4476
ifa = if6_get_next(seq, v);
net/ipv6/addrconf.c
4481
static void if6_seq_stop(struct seq_file *seq, void *v)
net/ipv6/addrconf.c
4487
static int if6_seq_show(struct seq_file *seq, void *v)
net/ipv6/addrconf.c
4489
struct inet6_ifaddr *ifp = (struct inet6_ifaddr *)v;
net/ipv6/addrconf_core.c
107
int inet6addr_notifier_call_chain(unsigned long val, void *v)
net/ipv6/addrconf_core.c
109
return atomic_notifier_call_chain(&inet6addr_chain, val, v);
net/ipv6/addrconf_core.c
126
int inet6addr_validator_notifier_call_chain(unsigned long val, void *v)
net/ipv6/addrconf_core.c
128
return blocking_notifier_call_chain(&inet6addr_validator_chain, val, v);
net/ipv6/anycast.c
590
static void *ac6_seq_next(struct seq_file *seq, void *v, loff_t *pos)
net/ipv6/anycast.c
592
struct ifacaddr6 *im = ac6_get_next(seq, v);
net/ipv6/anycast.c
598
static void ac6_seq_stop(struct seq_file *seq, void *v)
net/ipv6/anycast.c
604
static int ac6_seq_show(struct seq_file *seq, void *v)
net/ipv6/anycast.c
606
struct ifacaddr6 *im = (struct ifacaddr6 *)v;
net/ipv6/ila/ila_xlat.c
42
u32 *v = (u32 *)loc.v32;
net/ipv6/ila/ila_xlat.c
45
return jhash_2words(v[0], v[1], hashrnd);
net/ipv6/ip6_fib.c
2608
static int ipv6_route_native_seq_show(struct seq_file *seq, void *v)
net/ipv6/ip6_fib.c
2610
struct fib6_info *rt = v;
net/ipv6/ip6_fib.c
2708
static void *ipv6_route_seq_next(struct seq_file *seq, void *v, loff_t *pos)
net/ipv6/ip6_fib.c
2716
if (!v)
net/ipv6/ip6_fib.c
2719
n = rcu_dereference(((struct fib6_info *)v)->fib6_next);
net/ipv6/ip6_fib.c
2770
static void ipv6_route_native_seq_stop(struct seq_file *seq, void *v)
net/ipv6/ip6_fib.c
2785
void *v)
net/ipv6/ip6_fib.c
2790
ctx.rt = v;
net/ipv6/ip6_fib.c
2794
static int ipv6_route_seq_show(struct seq_file *seq, void *v)
net/ipv6/ip6_fib.c
2804
return ipv6_route_native_seq_show(seq, v);
net/ipv6/ip6_fib.c
2806
ret = ipv6_route_prog_seq_show(prog, &meta, v);
net/ipv6/ip6_fib.c
2812
static void ipv6_route_seq_stop(struct seq_file *seq, void *v)
net/ipv6/ip6_fib.c
2817
if (!v) {
net/ipv6/ip6_fib.c
2821
(void)ipv6_route_prog_seq_show(prog, &meta, v);
net/ipv6/ip6_fib.c
2824
ipv6_route_native_seq_stop(seq, v);
net/ipv6/ip6_fib.c
2827
static int ipv6_route_seq_show(struct seq_file *seq, void *v)
net/ipv6/ip6_fib.c
2829
return ipv6_route_native_seq_show(seq, v);
net/ipv6/ip6_fib.c
2832
static void ipv6_route_seq_stop(struct seq_file *seq, void *v)
net/ipv6/ip6_fib.c
2834
ipv6_route_native_seq_stop(seq, v);
net/ipv6/ip6_flowlabel.c
812
static void *ip6fl_seq_next(struct seq_file *seq, void *v, loff_t *pos)
net/ipv6/ip6_flowlabel.c
816
if (v == SEQ_START_TOKEN)
net/ipv6/ip6_flowlabel.c
819
fl = ip6fl_get_next(seq, v);
net/ipv6/ip6_flowlabel.c
824
static void ip6fl_seq_stop(struct seq_file *seq, void *v)
net/ipv6/ip6_flowlabel.c
830
static int ip6fl_seq_show(struct seq_file *seq, void *v)
net/ipv6/ip6_flowlabel.c
833
if (v == SEQ_START_TOKEN) {
net/ipv6/ip6_flowlabel.c
836
struct ip6_flowlabel *fl = v;
net/ipv6/ip6mr.c
1264
struct vif_device *v;
net/ipv6/ip6mr.c
1271
v = &mrt->vif_table[0];
net/ipv6/ip6mr.c
1272
for (ct = 0; ct < mrt->maxvif; ct++, v++) {
net/ipv6/ip6mr.c
1273
if (rcu_access_pointer(v->dev) == dev)
net/ipv6/ip6mr.c
1777
int v;
net/ipv6/ip6mr.c
1779
if (optlen != sizeof(v))
net/ipv6/ip6mr.c
1781
if (copy_from_sockptr(&v, optval, sizeof(v)))
net/ipv6/ip6mr.c
1783
mrt->mroute_do_assert = v;
net/ipv6/ip6mr.c
1791
int v;
net/ipv6/ip6mr.c
1793
if (optlen != sizeof(v))
net/ipv6/ip6mr.c
1795
if (copy_from_sockptr(&v, optval, sizeof(v)))
net/ipv6/ip6mr.c
1798
do_wrmifwhole = (v == MRT6MSG_WRMIFWHOLE);
net/ipv6/ip6mr.c
1799
v = !!v;
net/ipv6/ip6mr.c
1802
if (v != mrt->mroute_do_pim) {
net/ipv6/ip6mr.c
1803
mrt->mroute_do_pim = v;
net/ipv6/ip6mr.c
1804
mrt->mroute_do_assert = v;
net/ipv6/ip6mr.c
1815
u32 v;
net/ipv6/ip6mr.c
1819
if (copy_from_sockptr(&v, optval, sizeof(v)))
net/ipv6/ip6mr.c
1822
if (v != RT_TABLE_DEFAULT && v >= 100000000)
net/ipv6/ip6mr.c
1829
mrt = ip6mr_new_table(net, v);
net/ipv6/ip6mr.c
1833
raw6_sk(sk)->ip6mr_table = v;
net/ipv6/ip6mr.c
442
static void ip6mr_vif_seq_stop(struct seq_file *seq, void *v)
net/ipv6/ip6mr.c
448
static int ip6mr_vif_seq_show(struct seq_file *seq, void *v)
net/ipv6/ip6mr.c
453
if (v == SEQ_START_TOKEN) {
net/ipv6/ip6mr.c
457
const struct vif_device *vif = v;
net/ipv6/ip6mr.c
493
static int ipmr_mfc_seq_show(struct seq_file *seq, void *v)
net/ipv6/ip6mr.c
497
if (v == SEQ_START_TOKEN) {
net/ipv6/ip6mr.c
503
const struct mfc6_cache *mfc = v;
net/ipv6/ip6mr.c
720
struct vif_device *v;
net/ipv6/ip6mr.c
727
v = &mrt->vif_table[vifi];
net/ipv6/ip6mr.c
729
dev = rtnl_dereference(v->dev);
net/ipv6/ip6mr.c
734
FIB_EVENT_VIF_DEL, v, dev,
net/ipv6/ip6mr.c
737
RCU_INIT_POINTER(v->dev, NULL);
net/ipv6/ip6mr.c
767
if ((v->flags & MIFF_REGISTER) && !notify)
net/ipv6/ip6mr.c
770
netdev_put(dev, &v->dev_tracker);
net/ipv6/ip6mr.c
884
struct vif_device *v = &mrt->vif_table[vifi];
net/ipv6/ip6mr.c
936
vif_device_init(v, dev, vifc->vifc_rate_limit, vifc->vifc_threshold,
net/ipv6/ip6mr.c
942
rcu_assign_pointer(v->dev, dev);
net/ipv6/ip6mr.c
943
netdev_tracker_alloc(dev, &v->dev_tracker, GFP_ATOMIC);
net/ipv6/ip6mr.c
945
if (v->flags & MIFF_REGISTER)
net/ipv6/ip6mr.c
952
v, dev, vifi, mrt->id);
net/ipv6/ipcomp6.c
119
u32 mark = x->mark.m & x->mark.v;
net/ipv6/mcast.c
2962
static void *igmp6_mc_seq_next(struct seq_file *seq, void *v, loff_t *pos)
net/ipv6/mcast.c
2964
struct ifmcaddr6 *im = igmp6_mc_get_next(seq, v);
net/ipv6/mcast.c
2970
static void igmp6_mc_seq_stop(struct seq_file *seq, void *v)
net/ipv6/mcast.c
2981
static int igmp6_mc_seq_show(struct seq_file *seq, void *v)
net/ipv6/mcast.c
2983
struct ifmcaddr6 *im = (struct ifmcaddr6 *)v;
net/ipv6/mcast.c
3080
static void *igmp6_mcf_seq_next(struct seq_file *seq, void *v, loff_t *pos)
net/ipv6/mcast.c
3083
if (v == SEQ_START_TOKEN)
net/ipv6/mcast.c
3086
psf = igmp6_mcf_get_next(seq, v);
net/ipv6/mcast.c
3091
static void igmp6_mcf_seq_stop(struct seq_file *seq, void *v)
net/ipv6/mcast.c
3105
static int igmp6_mcf_seq_show(struct seq_file *seq, void *v)
net/ipv6/mcast.c
3107
struct ip6_sf_list *psf = (struct ip6_sf_list *)v;
net/ipv6/mcast.c
3110
if (v == SEQ_START_TOKEN) {
net/ipv6/netfilter/ip6_tables.c
334
int v;
net/ipv6/netfilter/ip6_tables.c
336
v = ((struct xt_standard_target *)t)->verdict;
net/ipv6/netfilter/ip6_tables.c
337
if (v < 0) {
net/ipv6/netfilter/ip6_tables.c
339
if (v != XT_RETURN) {
net/ipv6/netfilter/ip6_tables.c
340
verdict = (unsigned int)(-v) - 1;
net/ipv6/netfilter/ip6_tables.c
350
if (table_base + v != ip6t_next_entry(e) &&
net/ipv6/netfilter/ip6_tables.c
359
e = get_entry(table_base, v);
net/ipv6/netfilter/ip6_tables.c
889
int v = *(compat_int_t *)src;
net/ipv6/netfilter/ip6_tables.c
891
if (v > 0)
net/ipv6/netfilter/ip6_tables.c
892
v += xt_compat_calc_jump(AF_INET6, v);
net/ipv6/netfilter/ip6_tables.c
893
memcpy(dst, &v, sizeof(v));
net/ipv6/ping.c
233
static int ping_v6_seq_show(struct seq_file *seq, void *v)
net/ipv6/ping.c
235
if (v == SEQ_START_TOKEN) {
net/ipv6/ping.c
239
struct inet_sock *inet = inet_sk((struct sock *)v);
net/ipv6/ping.c
242
ip6_dgram_sock_seq_show(seq, v, srcp, destp, bucket);
net/ipv6/proc.c
216
static int snmp6_seq_show(struct seq_file *seq, void *v)
net/ipv6/proc.c
237
static int snmp6_dev_seq_show(struct seq_file *seq, void *v)
net/ipv6/proc.c
34
static int sockstat6_seq_show(struct seq_file *seq, void *v)
net/ipv6/raw.c
1224
static int raw6_seq_show(struct seq_file *seq, void *v)
net/ipv6/raw.c
1226
if (v == SEQ_START_TOKEN) {
net/ipv6/raw.c
1229
struct sock *sp = v;
net/ipv6/raw.c
1231
ip6_dgram_sock_seq_show(seq, v, srcp, 0,
net/ipv6/route.c
6500
static int rt6_stats_seq_show(struct seq_file *seq, void *v)
net/ipv6/tcp_ipv6.c
2227
static int tcp6_seq_show(struct seq_file *seq, void *v)
net/ipv6/tcp_ipv6.c
2230
struct sock *sk = v;
net/ipv6/tcp_ipv6.c
2232
if (v == SEQ_START_TOKEN) {
net/ipv6/tcp_ipv6.c
2244
get_timewait6_sock(seq, v, st->num);
net/ipv6/tcp_ipv6.c
2246
get_openreq6(seq, v, st->num);
net/ipv6/tcp_ipv6.c
2248
get_tcp6_sock(seq, v, st->num);
net/ipv6/udp.c
1860
int udp6_seq_show(struct seq_file *seq, void *v)
net/ipv6/udp.c
1862
if (v == SEQ_START_TOKEN) {
net/ipv6/udp.c
1866
const struct inet_sock *inet = inet_sk((const struct sock *)v);
net/ipv6/udp.c
1869
__ip6_dgram_sock_seq_show(seq, v, srcp, destp,
net/ipv6/udp.c
1870
udp_rqueue_get(v), bucket);
net/ipv6/udp_impl.h
30
int udp6_seq_show(struct seq_file *seq, void *v);
net/kcm/kcmproc.c
220
static int kcm_seq_show(struct seq_file *seq, void *v)
net/kcm/kcmproc.c
225
if (v == SEQ_START_TOKEN) {
net/kcm/kcmproc.c
229
kcm_format_mux(v, mux_state->idx, seq);
net/kcm/kcmproc.c
242
static int kcm_stats_seq_show(struct seq_file *seq, void *v)
net/kcm/kcmproc.c
49
static void *kcm_seq_next(struct seq_file *seq, void *v, loff_t *pos)
net/kcm/kcmproc.c
53
if (v == SEQ_START_TOKEN)
net/kcm/kcmproc.c
56
p = kcm_get_next(v);
net/kcm/kcmproc.c
72
static void kcm_seq_stop(struct seq_file *seq, void *v)
net/key/af_key.c
3800
static int pfkey_seq_show(struct seq_file *f, void *v)
net/key/af_key.c
3802
struct sock *s = sk_entry(v);
net/key/af_key.c
3804
if (v == SEQ_START_TOKEN)
net/key/af_key.c
3828
static void *pfkey_seq_next(struct seq_file *f, void *v, loff_t *ppos)
net/key/af_key.c
3833
return seq_hlist_next_rcu(v, &net_pfkey->table, ppos);
net/key/af_key.c
3836
static void pfkey_seq_stop(struct seq_file *f, void *v)
net/l2tp/l2tp_debugfs.c
103
static void l2tp_dfs_seq_stop(struct seq_file *p, void *v)
net/l2tp/l2tp_debugfs.c
105
struct l2tp_dfs_seq_data *pd = v;
net/l2tp/l2tp_debugfs.c
123
static void l2tp_dfs_seq_tunnel_show(struct seq_file *m, void *v)
net/l2tp/l2tp_debugfs.c
125
struct l2tp_tunnel *tunnel = v;
net/l2tp/l2tp_debugfs.c
176
static void l2tp_dfs_seq_session_show(struct seq_file *m, void *v)
net/l2tp/l2tp_debugfs.c
178
struct l2tp_session *session = v;
net/l2tp/l2tp_debugfs.c
230
static int l2tp_dfs_seq_show(struct seq_file *m, void *v)
net/l2tp/l2tp_debugfs.c
232
struct l2tp_dfs_seq_data *pd = v;
net/l2tp/l2tp_debugfs.c
235
if (v == SEQ_START_TOKEN) {
net/l2tp/l2tp_debugfs.c
97
static void *l2tp_dfs_seq_next(struct seq_file *m, void *v, loff_t *pos)
net/l2tp/l2tp_ppp.c
1462
static void *pppol2tp_seq_next(struct seq_file *m, void *v, loff_t *pos)
net/l2tp/l2tp_ppp.c
1468
static void pppol2tp_seq_stop(struct seq_file *p, void *v)
net/l2tp/l2tp_ppp.c
1470
struct pppol2tp_seq_data *pd = v;
net/l2tp/l2tp_ppp.c
1488
static void pppol2tp_seq_tunnel_show(struct seq_file *m, void *v)
net/l2tp/l2tp_ppp.c
1490
struct l2tp_tunnel *tunnel = v;
net/l2tp/l2tp_ppp.c
1506
static void pppol2tp_seq_session_show(struct seq_file *m, void *v)
net/l2tp/l2tp_ppp.c
1508
struct l2tp_session *session = v;
net/l2tp/l2tp_ppp.c
1563
static int pppol2tp_seq_show(struct seq_file *m, void *v)
net/l2tp/l2tp_ppp.c
1565
struct pppol2tp_seq_data *pd = v;
net/l2tp/l2tp_ppp.c
1568
if (v == SEQ_START_TOKEN) {
net/llc/llc_proc.c
114
static void llc_seq_stop(struct seq_file *seq, void *v)
net/llc/llc_proc.c
116
if (v && v != SEQ_START_TOKEN) {
net/llc/llc_proc.c
117
struct sock *sk = v;
net/llc/llc_proc.c
126
static int llc_seq_socket_show(struct seq_file *seq, void *v)
net/llc/llc_proc.c
131
if (v == SEQ_START_TOKEN) {
net/llc/llc_proc.c
136
sk = v;
net/llc/llc_proc.c
175
static int llc_seq_core_show(struct seq_file *seq, void *v)
net/llc/llc_proc.c
180
if (v == SEQ_START_TOKEN) {
net/llc/llc_proc.c
186
sk = v;
net/llc/llc_proc.c
80
static void *llc_seq_next(struct seq_file *seq, void *v, loff_t *pos)
net/llc/llc_proc.c
87
if (v == SEQ_START_TOKEN) {
net/llc/llc_proc.c
91
sk = v;
net/mac80211/debugfs_sta.c
983
u16 v = le16_to_cpu(nss->f); \
net/mac80211/debugfs_sta.c
984
p += scnprintf(p, buf_sz + buf - p, n ": %#.4x\n", v); \
net/mac80211/debugfs_sta.c
986
switch ((v >> _i) & 0x3) { \
net/mac80211/fils_aead.c
106
memcpy(out, v, AES_BLOCK_SIZE);
net/mac80211/fils_aead.c
111
v[8] &= 0x7f;
net/mac80211/fils_aead.c
112
v[12] &= 0x7f;
net/mac80211/fils_aead.c
134
skcipher_request_set_crypt(req, src, dst, plain_len, v);
net/mac80211/fils_aead.c
26
size_t num_elem, const u8 *addr[], size_t len[], u8 *v)
net/mac80211/fils_aead.c
60
crypto_shash_finup(desc, d, AES_BLOCK_SIZE, v);
net/mac80211/fils_aead.c
71
u8 v[AES_BLOCK_SIZE];
net/mac80211/fils_aead.c
93
res = aes_s2v(tfm, num_elem, addr, len, v);
net/mac80211/tests/s1g_tim.c
114
static void tim_push(u8 **p, u8 v)
net/mac80211/tests/s1g_tim.c
116
*(*p)++ = v;
net/mac80211/tests/s1g_tim.c
20
static void byte_to_bitstr(u8 v, char *out)
net/mac80211/tests/s1g_tim.c
23
*out++ = (v & BIT(b)) ? '1' : '0';
net/mptcp/protocol.c
3879
static int mptcp_ioctl_outq(const struct mptcp_sock *msk, u64 v)
net/mptcp/protocol.c
3890
delta = msk->write_seq - v;
net/netfilter/ipvs/ip_vs_app.c
542
static void *ip_vs_app_seq_next(struct seq_file *seq, void *v, loff_t *pos)
net/netfilter/ipvs/ip_vs_app.c
550
if (v == SEQ_START_TOKEN)
net/netfilter/ipvs/ip_vs_app.c
553
inc = v;
net/netfilter/ipvs/ip_vs_app.c
569
static void ip_vs_app_seq_stop(struct seq_file *seq, void *v)
net/netfilter/ipvs/ip_vs_app.c
574
static int ip_vs_app_seq_show(struct seq_file *seq, void *v)
net/netfilter/ipvs/ip_vs_app.c
576
if (v == SEQ_START_TOKEN)
net/netfilter/ipvs/ip_vs_app.c
579
const struct ip_vs_app *inc = v;
net/netfilter/ipvs/ip_vs_conn.c
1095
static void *ip_vs_conn_seq_next(struct seq_file *seq, void *v, loff_t *pos)
net/netfilter/ipvs/ip_vs_conn.c
1097
struct ip_vs_conn *cp = v;
net/netfilter/ipvs/ip_vs_conn.c
1102
if (v == SEQ_START_TOKEN)
net/netfilter/ipvs/ip_vs_conn.c
1118
static void ip_vs_conn_seq_stop(struct seq_file *seq, void *v)
net/netfilter/ipvs/ip_vs_conn.c
1124
static int ip_vs_conn_seq_show(struct seq_file *seq, void *v)
net/netfilter/ipvs/ip_vs_conn.c
1127
if (v == SEQ_START_TOKEN)
net/netfilter/ipvs/ip_vs_conn.c
1131
const struct ip_vs_conn *cp = v;
net/netfilter/ipvs/ip_vs_conn.c
1201
static int ip_vs_conn_sync_seq_show(struct seq_file *seq, void *v)
net/netfilter/ipvs/ip_vs_conn.c
1205
if (v == SEQ_START_TOKEN)
net/netfilter/ipvs/ip_vs_conn.c
1209
const struct ip_vs_conn *cp = v;
net/netfilter/ipvs/ip_vs_core.c
1708
int v;
net/netfilter/ipvs/ip_vs_core.c
1713
if (!ip_vs_try_to_schedule(ipvs, AF_INET, skb, pd, &v, &cp, &ciph))
net/netfilter/ipvs/ip_vs_core.c
1714
return v;
net/netfilter/ipvs/ip_vs_core.c
1862
int v;
net/netfilter/ipvs/ip_vs_core.c
1867
if (!ip_vs_try_to_schedule(ipvs, AF_INET6, skb, pd, &v, &cp, &ciph))
net/netfilter/ipvs/ip_vs_core.c
1868
return v;
net/netfilter/ipvs/ip_vs_core.c
2048
int v;
net/netfilter/ipvs/ip_vs_core.c
2050
if (!ip_vs_try_to_schedule(ipvs, af, skb, pd, &v, &cp, &iph))
net/netfilter/ipvs/ip_vs_core.c
2051
return v;
net/netfilter/ipvs/ip_vs_ctl.c
2340
static void *ip_vs_info_seq_next(struct seq_file *seq, void *v, loff_t *pos)
net/netfilter/ipvs/ip_vs_ctl.c
2347
if (v == SEQ_START_TOKEN)
net/netfilter/ipvs/ip_vs_ctl.c
2350
svc = v;
net/netfilter/ipvs/ip_vs_ctl.c
2388
static void ip_vs_info_seq_stop(struct seq_file *seq, void *v)
net/netfilter/ipvs/ip_vs_ctl.c
2395
static int ip_vs_info_seq_show(struct seq_file *seq, void *v)
net/netfilter/ipvs/ip_vs_ctl.c
2397
if (v == SEQ_START_TOKEN) {
net/netfilter/ipvs/ip_vs_ctl.c
2408
const struct ip_vs_service *svc = v;
net/netfilter/ipvs/ip_vs_ctl.c
2481
static int ip_vs_stats_show(struct seq_file *seq, void *v)
net/netfilter/ipvs/ip_vs_ctl.c
2513
static int ip_vs_stats_percpu_show(struct seq_file *seq, void *v)
net/netfilter/ipvs/ip_vs_mh.c
100
return hsiphash(&v, sizeof(v), key);
net/netfilter/ipvs/ip_vs_mh.c
91
unsigned int v;
net/netfilter/ipvs/ip_vs_mh.c
99
v = (offset + ntohs(port) + ntohl(addr_fold));
net/netfilter/nf_conntrack_expect.c
639
static void *exp_seq_next(struct seq_file *seq, void *v, loff_t *pos)
net/netfilter/nf_conntrack_expect.c
642
return ct_expect_get_next(seq, v);
net/netfilter/nf_conntrack_expect.c
645
static void exp_seq_stop(struct seq_file *seq, void *v)
net/netfilter/nf_conntrack_expect.c
651
static int exp_seq_show(struct seq_file *s, void *v)
net/netfilter/nf_conntrack_expect.c
656
struct hlist_node *n = v;
net/netfilter/nf_conntrack_h323_asn1.c
152
unsigned int v;
net/netfilter/nf_conntrack_h323_asn1.c
154
v = *bs->cur++;
net/netfilter/nf_conntrack_h323_asn1.c
156
if (v & 0x80) {
net/netfilter/nf_conntrack_h323_asn1.c
157
v &= 0x3f;
net/netfilter/nf_conntrack_h323_asn1.c
158
v <<= 8;
net/netfilter/nf_conntrack_h323_asn1.c
159
v += *bs->cur++;
net/netfilter/nf_conntrack_h323_asn1.c
162
return v;
net/netfilter/nf_conntrack_h323_asn1.c
190
unsigned int v, l;
net/netfilter/nf_conntrack_h323_asn1.c
192
v = (*bs->cur) & (0xffU >> bs->bit);
net/netfilter/nf_conntrack_h323_asn1.c
196
v >>= 8 - l;
net/netfilter/nf_conntrack_h323_asn1.c
203
v <<= 8;
net/netfilter/nf_conntrack_h323_asn1.c
204
v += *(++bs->cur);
net/netfilter/nf_conntrack_h323_asn1.c
205
v >>= 16 - l;
net/netfilter/nf_conntrack_h323_asn1.c
209
return v;
net/netfilter/nf_conntrack_h323_asn1.c
215
unsigned int v, l, shift, bytes;
net/netfilter/nf_conntrack_h323_asn1.c
223
v = (unsigned int)(*bs->cur) << (bs->bit + 24);
net/netfilter/nf_conntrack_h323_asn1.c
226
v = (unsigned int)(*bs->cur++) << (bs->bit + 24);
net/netfilter/nf_conntrack_h323_asn1.c
229
for (bytes = l >> 3, shift = 24, v = 0; bytes;
net/netfilter/nf_conntrack_h323_asn1.c
231
v |= (unsigned int)(*bs->cur++) << shift;
net/netfilter/nf_conntrack_h323_asn1.c
234
v |= (unsigned int)(*bs->cur) << shift;
net/netfilter/nf_conntrack_h323_asn1.c
235
v <<= bs->bit;
net/netfilter/nf_conntrack_h323_asn1.c
237
v <<= bs->bit;
net/netfilter/nf_conntrack_h323_asn1.c
238
v |= (*bs->cur) >> (8 - bs->bit);
net/netfilter/nf_conntrack_h323_asn1.c
244
v &= 0xffffffff << (32 - b);
net/netfilter/nf_conntrack_h323_asn1.c
246
return v;
net/netfilter/nf_conntrack_h323_asn1.c
254
unsigned int v = 0;
net/netfilter/nf_conntrack_h323_asn1.c
258
v |= *bs->cur++;
net/netfilter/nf_conntrack_h323_asn1.c
259
v <<= 8;
net/netfilter/nf_conntrack_h323_asn1.c
262
v |= *bs->cur++;
net/netfilter/nf_conntrack_h323_asn1.c
263
v <<= 8;
net/netfilter/nf_conntrack_h323_asn1.c
266
v |= *bs->cur++;
net/netfilter/nf_conntrack_h323_asn1.c
267
v <<= 8;
net/netfilter/nf_conntrack_h323_asn1.c
270
v |= *bs->cur++;
net/netfilter/nf_conntrack_h323_asn1.c
273
return v;
net/netfilter/nf_conntrack_h323_asn1.c
338
unsigned int v = get_uint(bs, len) + f->lb;
net/netfilter/nf_conntrack_h323_asn1.c
339
PRINT(" = %u", v);
net/netfilter/nf_conntrack_h323_asn1.c
340
*((unsigned int *)(base + f->offset)) = v;
net/netfilter/nf_conntrack_labels.c
61
int v;
net/netfilter/nf_conntrack_labels.c
68
v = atomic_inc_return_relaxed(&net->ct.labels_used);
net/netfilter/nf_conntrack_labels.c
69
WARN_ON_ONCE(v <= 0);
net/netfilter/nf_conntrack_labels.c
77
int v = atomic_dec_return_relaxed(&net->ct.labels_used);
net/netfilter/nf_conntrack_labels.c
79
WARN_ON_ONCE(v < 0);
net/netfilter/nf_conntrack_standalone.c
171
static void *ct_seq_next(struct seq_file *s, void *v, loff_t *pos)
net/netfilter/nf_conntrack_standalone.c
180
static void ct_seq_stop(struct seq_file *s, void *v)
net/netfilter/nf_conntrack_standalone.c
304
static int ct_seq_show(struct seq_file *s, void *v)
net/netfilter/nf_conntrack_standalone.c
306
struct nf_conntrack_tuple_hash *hash = v;
net/netfilter/nf_conntrack_standalone.c
420
static void *ct_cpu_seq_next(struct seq_file *seq, void *v, loff_t *pos)
net/netfilter/nf_conntrack_standalone.c
435
static void ct_cpu_seq_stop(struct seq_file *seq, void *v)
net/netfilter/nf_conntrack_standalone.c
439
static int ct_cpu_seq_show(struct seq_file *seq, void *v)
net/netfilter/nf_conntrack_standalone.c
442
const struct ip_conntrack_stat *st = v;
net/netfilter/nf_conntrack_standalone.c
445
if (v == SEQ_START_TOKEN) {
net/netfilter/nf_flow_table_procfs.c
24
static void *nf_flow_table_cpu_seq_next(struct seq_file *seq, void *v, loff_t *pos)
net/netfilter/nf_flow_table_procfs.c
39
static void nf_flow_table_cpu_seq_stop(struct seq_file *seq, void *v)
net/netfilter/nf_flow_table_procfs.c
43
static int nf_flow_table_cpu_seq_show(struct seq_file *seq, void *v)
net/netfilter/nf_flow_table_procfs.c
45
const struct nf_flow_table_stat *st = v;
net/netfilter/nf_flow_table_procfs.c
47
if (v == SEQ_START_TOKEN) {
net/netfilter/nf_log.c
360
static void *seq_next(struct seq_file *s, void *v, loff_t *pos)
net/netfilter/nf_log.c
372
static void seq_stop(struct seq_file *s, void *v)
net/netfilter/nf_log.c
377
static int seq_show(struct seq_file *s, void *v)
net/netfilter/nf_log.c
379
loff_t *pos = v;
net/netfilter/nf_synproxy_core.c
259
static void *synproxy_cpu_seq_next(struct seq_file *seq, void *v, loff_t *pos)
net/netfilter/nf_synproxy_core.c
274
static void synproxy_cpu_seq_stop(struct seq_file *seq, void *v)
net/netfilter/nf_synproxy_core.c
279
static int synproxy_cpu_seq_show(struct seq_file *seq, void *v)
net/netfilter/nf_synproxy_core.c
281
struct synproxy_stats *stats = v;
net/netfilter/nf_synproxy_core.c
283
if (v == SEQ_START_TOKEN) {
net/netfilter/nf_tables_api.c
11731
int nft_verdict_dump(struct sk_buff *skb, int type, const struct nft_verdict *v)
net/netfilter/nf_tables_api.c
11739
if (nla_put_be32(skb, NFTA_VERDICT_CODE, htonl(v->code)))
net/netfilter/nf_tables_api.c
11742
switch (v->code) {
net/netfilter/nf_tables_api.c
11746
v->chain->name))
net/netfilter/nf_tables_trace.c
313
unsigned int v;
net/netfilter/nf_tables_trace.c
319
v = verdict->code & NF_VERDICT_MASK;
net/netfilter/nf_tables_trace.c
320
if (v == NF_STOLEN)
net/netfilter/nfnetlink.c
676
u8 v;
net/netfilter/nfnetlink.c
698
v = READ_ONCE(nf_ctnetlink_has_listener);
net/netfilter/nfnetlink.c
699
if ((v & group_bit) == 0) {
net/netfilter/nfnetlink.c
700
v |= group_bit;
net/netfilter/nfnetlink.c
703
WRITE_ONCE(nf_ctnetlink_has_listener, v);
net/netfilter/nfnetlink.c
757
u8 v = READ_ONCE(nf_ctnetlink_has_listener);
net/netfilter/nfnetlink.c
759
v &= ~group_bit;
net/netfilter/nfnetlink.c
762
WRITE_ONCE(nf_ctnetlink_has_listener, v);
net/netfilter/nfnetlink_log.c
1079
static void *seq_next(struct seq_file *s, void *v, loff_t *pos)
net/netfilter/nfnetlink_log.c
1082
return get_next(seq_file_net(s), s->private, v);
net/netfilter/nfnetlink_log.c
1085
static void seq_stop(struct seq_file *s, void *v)
net/netfilter/nfnetlink_log.c
1091
static int seq_show(struct seq_file *s, void *v)
net/netfilter/nfnetlink_log.c
1093
const struct nfulnl_instance *inst = v;
net/netfilter/nfnetlink_queue.c
1772
static void *seq_next(struct seq_file *s, void *v, loff_t *pos)
net/netfilter/nfnetlink_queue.c
1775
return get_next(s, v);
net/netfilter/nfnetlink_queue.c
1778
static void seq_stop(struct seq_file *s, void *v)
net/netfilter/nfnetlink_queue.c
1784
static int seq_show(struct seq_file *s, void *v)
net/netfilter/nfnetlink_queue.c
1786
const struct nfqnl_instance *inst = v;
net/netfilter/nft_set_pipapo.c
1002
int i, v;
net/netfilter/nft_set_pipapo.c
1005
v = k[group / (BITS_PER_BYTE / f->bb)];
net/netfilter/nft_set_pipapo.c
1006
v &= GENMASK(BITS_PER_BYTE - bit_offset - 1, 0);
net/netfilter/nft_set_pipapo.c
1007
v >>= (BITS_PER_BYTE - bit_offset) - f->bb;
net/netfilter/nft_set_pipapo.c
1014
pipapo_bucket_set(f, rule, group, v);
net/netfilter/nft_set_pipapo.c
1024
if ((i & ~mask) == (v & ~mask))
net/netfilter/nft_set_pipapo.c
784
int v)
net/netfilter/nft_set_pipapo.c
790
pos += f->bsize * v;
net/netfilter/nft_set_pipapo.h
199
u8 v;
net/netfilter/nft_set_pipapo.h
201
v = *data >> 4;
net/netfilter/nft_set_pipapo.h
202
__bitmap_and(dst, dst, lt + v * f->bsize,
net/netfilter/nft_set_pipapo.h
206
v = *data & 0x0f;
net/netfilter/nft_set_pipapo.h
207
__bitmap_and(dst, dst, lt + v * f->bsize,
net/netfilter/nft_set_pipapo_avx2.c
45
#define NFT_PIPAPO_AVX2_BUCKET_LOAD4(reg, lt, group, v, bsize) \
net/netfilter/nft_set_pipapo_avx2.c
48
(v)) * (bsize)])
net/netfilter/nft_set_pipapo_avx2.c
49
#define NFT_PIPAPO_AVX2_BUCKET_LOAD8(reg, lt, group, v, bsize) \
net/netfilter/nft_set_pipapo_avx2.c
52
(v)) * (bsize)])
net/netfilter/x_tables.c
1556
static void *xt_table_seq_next(struct seq_file *seq, void *v, loff_t *pos)
net/netfilter/x_tables.c
1564
return seq_list_next(v, &xt_net->tables[af], pos);
net/netfilter/x_tables.c
1567
static void xt_table_seq_stop(struct seq_file *seq, void *v)
net/netfilter/x_tables.c
1574
static int xt_table_seq_show(struct seq_file *seq, void *v)
net/netfilter/x_tables.c
1576
struct xt_table *table = list_entry(v, struct xt_table, list);
net/netfilter/x_tables.c
1606
static void *xt_mttg_seq_next(struct seq_file *seq, void *v, loff_t *ppos,
net/netfilter/x_tables.c
1660
static void xt_mttg_seq_stop(struct seq_file *seq, void *v)
net/netfilter/x_tables.c
1680
static void *xt_match_seq_next(struct seq_file *seq, void *v, loff_t *ppos)
net/netfilter/x_tables.c
1682
return xt_mttg_seq_next(seq, v, ppos, false);
net/netfilter/x_tables.c
1685
static int xt_match_seq_show(struct seq_file *seq, void *v)
net/netfilter/x_tables.c
1714
static void *xt_target_seq_next(struct seq_file *seq, void *v, loff_t *ppos)
net/netfilter/x_tables.c
1716
return xt_mttg_seq_next(seq, v, ppos, true);
net/netfilter/x_tables.c
1719
static int xt_target_seq_show(struct seq_file *seq, void *v)
net/netfilter/x_tables.c
650
int v = -verdict - 1;
net/netfilter/x_tables.c
655
switch (v) {
net/netfilter/xt_hashlimit.c
1072
static void *dl_seq_next(struct seq_file *s, void *v, loff_t *pos)
net/netfilter/xt_hashlimit.c
1075
unsigned int *bucket = v;
net/netfilter/xt_hashlimit.c
1079
kfree(v);
net/netfilter/xt_hashlimit.c
1085
static void dl_seq_stop(struct seq_file *s, void *v)
net/netfilter/xt_hashlimit.c
1089
unsigned int *bucket = v;
net/netfilter/xt_hashlimit.c
1172
static int dl_seq_show_v2(struct seq_file *s, void *v)
net/netfilter/xt_hashlimit.c
1175
unsigned int *bucket = (unsigned int *)v;
net/netfilter/xt_hashlimit.c
1186
static int dl_seq_show_v1(struct seq_file *s, void *v)
net/netfilter/xt_hashlimit.c
1189
unsigned int *bucket = v;
net/netfilter/xt_hashlimit.c
1200
static int dl_seq_show(struct seq_file *s, void *v)
net/netfilter/xt_hashlimit.c
1203
unsigned int *bucket = v;
net/netfilter/xt_recent.c
496
static void *recent_seq_next(struct seq_file *seq, void *v, loff_t *pos)
net/netfilter/xt_recent.c
500
const struct recent_entry *e = v;
net/netfilter/xt_recent.c
512
static void recent_seq_stop(struct seq_file *s, void *v)
net/netfilter/xt_recent.c
518
static int recent_seq_show(struct seq_file *seq, void *v)
net/netfilter/xt_recent.c
520
const struct recent_entry *e = v;
net/netfilter/xt_time.c
78
unsigned int v, w;
net/netfilter/xt_time.c
81
div_u64_rem(time, SECONDS_PER_DAY, &v);
net/netfilter/xt_time.c
82
r->second = v % 60;
net/netfilter/xt_time.c
83
w = v / 60;
net/netfilter/xt_time.c
86
return v;
net/netlink/af_netlink.c
2676
static void *netlink_seq_next(struct seq_file *seq, void *v, loff_t *pos)
net/netlink/af_netlink.c
2682
static void netlink_native_seq_stop(struct seq_file *seq, void *v)
net/netlink/af_netlink.c
2693
static int netlink_native_seq_show(struct seq_file *seq, void *v)
net/netlink/af_netlink.c
2695
if (v == SEQ_START_TOKEN) {
net/netlink/af_netlink.c
2700
struct sock *s = v;
net/netlink/af_netlink.c
2730
void *v)
net/netlink/af_netlink.c
2736
ctx.sk = nlk_sk((struct sock *)v);
net/netlink/af_netlink.c
2740
static int netlink_seq_show(struct seq_file *seq, void *v)
net/netlink/af_netlink.c
2748
return netlink_native_seq_show(seq, v);
net/netlink/af_netlink.c
2750
if (v != SEQ_START_TOKEN)
net/netlink/af_netlink.c
2751
return netlink_prog_seq_show(prog, &meta, v);
net/netlink/af_netlink.c
2756
static void netlink_seq_stop(struct seq_file *seq, void *v)
net/netlink/af_netlink.c
2761
if (!v) {
net/netlink/af_netlink.c
2765
(void)netlink_prog_seq_show(prog, &meta, v);
net/netlink/af_netlink.c
2768
netlink_native_seq_stop(seq, v);
net/netlink/af_netlink.c
2771
static int netlink_seq_show(struct seq_file *seq, void *v)
net/netlink/af_netlink.c
2773
return netlink_native_seq_show(seq, v);
net/netlink/af_netlink.c
2776
static void netlink_seq_stop(struct seq_file *seq, void *v)
net/netlink/af_netlink.c
2778
netlink_native_seq_stop(seq, v);
net/netrom/af_netrom.c
1272
static void *nr_info_next(struct seq_file *seq, void *v, loff_t *pos)
net/netrom/af_netrom.c
1274
return seq_hlist_next(v, &nr_list, pos);
net/netrom/af_netrom.c
1277
static void nr_info_stop(struct seq_file *seq, void *v)
net/netrom/af_netrom.c
1283
static int nr_info_show(struct seq_file *seq, void *v)
net/netrom/af_netrom.c
1285
struct sock *s = sk_entry(v);
net/netrom/af_netrom.c
1291
if (v == SEQ_START_TOKEN)
net/netrom/nr_route.c
857
static void *nr_node_next(struct seq_file *seq, void *v, loff_t *pos)
net/netrom/nr_route.c
859
return seq_hlist_next(v, &nr_node_list, pos);
net/netrom/nr_route.c
862
static void nr_node_stop(struct seq_file *seq, void *v)
net/netrom/nr_route.c
868
static int nr_node_show(struct seq_file *seq, void *v)
net/netrom/nr_route.c
873
if (v == SEQ_START_TOKEN)
net/netrom/nr_route.c
877
struct nr_node *nr_node = hlist_entry(v, struct nr_node,
net/netrom/nr_route.c
914
static void *nr_neigh_next(struct seq_file *seq, void *v, loff_t *pos)
net/netrom/nr_route.c
916
return seq_hlist_next(v, &nr_neigh_list, pos);
net/netrom/nr_route.c
919
static void nr_neigh_stop(struct seq_file *seq, void *v)
net/netrom/nr_route.c
925
static int nr_neigh_show(struct seq_file *seq, void *v)
net/netrom/nr_route.c
930
if (v == SEQ_START_TOKEN)
net/netrom/nr_route.c
935
nr_neigh = hlist_entry(v, struct nr_neigh, neigh_node);
net/packet/af_packet.c
4702
static void *packet_seq_next(struct seq_file *seq, void *v, loff_t *pos)
net/packet/af_packet.c
4705
return seq_hlist_next_rcu(v, &net->packet.sklist, pos);
net/packet/af_packet.c
4708
static void packet_seq_stop(struct seq_file *seq, void *v)
net/packet/af_packet.c
4714
static int packet_seq_show(struct seq_file *seq, void *v)
net/packet/af_packet.c
4716
if (v == SEQ_START_TOKEN)
net/packet/af_packet.c
4721
struct sock *s = sk_entry(v);
net/phonet/socket.c
554
static void *pn_sock_seq_next(struct seq_file *seq, void *v, loff_t *pos)
net/phonet/socket.c
558
if (v == SEQ_START_TOKEN)
net/phonet/socket.c
561
sk = pn_sock_get_next(seq, v);
net/phonet/socket.c
566
static void pn_sock_seq_stop(struct seq_file *seq, void *v)
net/phonet/socket.c
572
static int pn_sock_seq_show(struct seq_file *seq, void *v)
net/phonet/socket.c
575
if (v == SEQ_START_TOKEN)
net/phonet/socket.c
579
struct sock *sk = v;
net/phonet/socket.c
729
static void *pn_res_seq_next(struct seq_file *seq, void *v, loff_t *pos)
net/phonet/socket.c
733
if (v == SEQ_START_TOKEN)
net/phonet/socket.c
736
sk = pn_res_get_next(seq, v);
net/phonet/socket.c
741
static void pn_res_seq_stop(struct seq_file *seq, void *v)
net/phonet/socket.c
747
static int pn_res_seq_show(struct seq_file *seq, void *v)
net/phonet/socket.c
750
if (v == SEQ_START_TOKEN) {
net/phonet/socket.c
753
struct sock __rcu **psk = v;
net/rds/ib.h
227
#define IB_GET_SEND_CREDITS(v) ((v) & 0xffff)
net/rds/ib.h
228
#define IB_GET_POST_CREDITS(v) ((v) >> 16)
net/rds/ib.h
229
#define IB_SET_SEND_CREDITS(v) ((v) & 0xffff)
net/rds/ib.h
230
#define IB_SET_POST_CREDITS(v) ((v) << 16)
net/rds/rds.h
25
#define RDS_PROTOCOL_MAJOR(v) ((v) >> 8)
net/rds/rds.h
26
#define RDS_PROTOCOL_MINOR(v) ((v) & 255)
net/rose/af_rose.c
1447
static void *rose_info_next(struct seq_file *seq, void *v, loff_t *pos)
net/rose/af_rose.c
1449
return seq_hlist_next(v, &rose_list, pos);
net/rose/af_rose.c
1452
static void rose_info_stop(struct seq_file *seq, void *v)
net/rose/af_rose.c
1458
static int rose_info_show(struct seq_file *seq, void *v)
net/rose/af_rose.c
1462
if (v == SEQ_START_TOKEN)
net/rose/af_rose.c
1467
struct sock *s = sk_entry(v);
net/rose/rose_route.c
1113
static void *rose_node_next(struct seq_file *seq, void *v, loff_t *pos)
net/rose/rose_route.c
1117
return (v == SEQ_START_TOKEN) ? rose_node_list
net/rose/rose_route.c
1118
: ((struct rose_node *)v)->next;
net/rose/rose_route.c
1121
static void rose_node_stop(struct seq_file *seq, void *v)
net/rose/rose_route.c
1127
static int rose_node_show(struct seq_file *seq, void *v)
net/rose/rose_route.c
1132
if (v == SEQ_START_TOKEN)
net/rose/rose_route.c
1135
const struct rose_node *rose_node = v;
net/rose/rose_route.c
1172
static void *rose_neigh_next(struct seq_file *seq, void *v, loff_t *pos)
net/rose/rose_route.c
1176
return (v == SEQ_START_TOKEN) ? rose_neigh_list
net/rose/rose_route.c
1177
: ((struct rose_neigh *)v)->next;
net/rose/rose_route.c
1180
static void rose_neigh_stop(struct seq_file *seq, void *v)
net/rose/rose_route.c
1186
static int rose_neigh_show(struct seq_file *seq, void *v)
net/rose/rose_route.c
1191
if (v == SEQ_START_TOKEN)
net/rose/rose_route.c
1195
struct rose_neigh *rose_neigh = v;
net/rose/rose_route.c
1243
static void *rose_route_next(struct seq_file *seq, void *v, loff_t *pos)
net/rose/rose_route.c
1247
return (v == SEQ_START_TOKEN) ? rose_route_list
net/rose/rose_route.c
1248
: ((struct rose_route *)v)->next;
net/rose/rose_route.c
1251
static void rose_route_stop(struct seq_file *seq, void *v)
net/rose/rose_route.c
1257
static int rose_route_show(struct seq_file *seq, void *v)
net/rose/rose_route.c
1261
if (v == SEQ_START_TOKEN)
net/rose/rose_route.c
1265
struct rose_route *rose_route = v;
net/rxrpc/ar-internal.h
1497
int rxrpc_stats_show(struct seq_file *seq, void *v);
net/rxrpc/io_thread.c
127
char v;
net/rxrpc/io_thread.c
132
if (skb_copy_bits(skb, sizeof(struct rxrpc_wire_header), &v, 1) >= 0) {
net/rxrpc/io_thread.c
133
if (v == 0)
net/rxrpc/proc.c
128
static void *rxrpc_connection_seq_next(struct seq_file *seq, void *v,
net/rxrpc/proc.c
133
return seq_list_next(v, &rxnet->conn_proc_list, pos);
net/rxrpc/proc.c
136
static void rxrpc_connection_seq_stop(struct seq_file *seq, void *v)
net/rxrpc/proc.c
144
static int rxrpc_connection_seq_show(struct seq_file *seq, void *v)
net/rxrpc/proc.c
151
if (v == &rxnet->conn_proc_list) {
net/rxrpc/proc.c
161
conn = list_entry(v, struct rxrpc_connection, proc_link);
net/rxrpc/proc.c
215
static void *rxrpc_bundle_seq_next(struct seq_file *seq, void *v,
net/rxrpc/proc.c
220
return seq_list_next(v, &rxnet->bundle_proc_list, pos);
net/rxrpc/proc.c
223
static void rxrpc_bundle_seq_stop(struct seq_file *seq, void *v)
net/rxrpc/proc.c
231
static int rxrpc_bundle_seq_show(struct seq_file *seq, void *v)
net/rxrpc/proc.c
237
if (v == &rxnet->bundle_proc_list) {
net/rxrpc/proc.c
247
bundle = list_entry(v, struct rxrpc_bundle, proc_link);
net/rxrpc/proc.c
282
static int rxrpc_peer_seq_show(struct seq_file *seq, void *v)
net/rxrpc/proc.c
288
if (v == SEQ_START_TOKEN) {
net/rxrpc/proc.c
295
peer = list_entry(v, struct rxrpc_peer, hash_link);
net/rxrpc/proc.c
352
static void *rxrpc_peer_seq_next(struct seq_file *seq, void *v, loff_t *_pos)
net/rxrpc/proc.c
364
p = seq_hlist_next_rcu(v, &rxnet->peer_hash[bucket], _pos);
net/rxrpc/proc.c
388
static void rxrpc_peer_seq_stop(struct seq_file *seq, void *v)
net/rxrpc/proc.c
40
static void *rxrpc_call_seq_next(struct seq_file *seq, void *v, loff_t *pos)
net/rxrpc/proc.c
405
static int rxrpc_local_seq_show(struct seq_file *seq, void *v)
net/rxrpc/proc.c
410
if (v == SEQ_START_TOKEN) {
net/rxrpc/proc.c
417
local = hlist_entry(v, struct rxrpc_local, link);
net/rxrpc/proc.c
44
return seq_list_next_rcu(v, &rxnet->calls, pos);
net/rxrpc/proc.c
449
static void *rxrpc_local_seq_next(struct seq_file *seq, void *v, loff_t *_pos)
net/rxrpc/proc.c
456
return seq_hlist_next_rcu(v, &rxnet->local_endpoints, _pos);
net/rxrpc/proc.c
459
static void rxrpc_local_seq_stop(struct seq_file *seq, void *v)
net/rxrpc/proc.c
47
static void rxrpc_call_seq_stop(struct seq_file *seq, void *v)
net/rxrpc/proc.c
475
int rxrpc_stats_show(struct seq_file *seq, void *v)
net/rxrpc/proc.c
53
static int rxrpc_call_seq_show(struct seq_file *seq, void *v)
net/rxrpc/proc.c
63
if (v == &rxnet->calls) {
net/rxrpc/proc.c
72
call = list_entry(v, struct rxrpc_call, link);
net/sched/act_vlan.c
100
tcf_action_inc_drop_qstats(&v->common);
net/sched/act_vlan.c
126
struct tcf_vlan *v;
net/sched/act_vlan.c
234
v = to_vlan(*a);
net/sched/act_vlan.c
256
spin_lock_bh(&v->tcf_lock);
net/sched/act_vlan.c
258
p = rcu_replace_pointer(v->vlan_p, p, lockdep_is_held(&v->tcf_lock));
net/sched/act_vlan.c
259
spin_unlock_bh(&v->tcf_lock);
net/sched/act_vlan.c
26
struct tcf_vlan *v = to_vlan(a);
net/sched/act_vlan.c
277
struct tcf_vlan *v = to_vlan(a);
net/sched/act_vlan.c
280
p = rcu_dereference_protected(v->vlan_p, 1);
net/sched/act_vlan.c
289
struct tcf_vlan *v = to_vlan(a);
net/sched/act_vlan.c
292
.index = v->tcf_index,
net/sched/act_vlan.c
293
.refcnt = refcount_read(&v->tcf_refcnt) - ref,
net/sched/act_vlan.c
294
.bindcnt = atomic_read(&v->tcf_bindcnt) - bind,
net/sched/act_vlan.c
299
p = rcu_dereference(v->vlan_p);
net/sched/act_vlan.c
31
tcf_lastuse_update(&v->tcf_tm);
net/sched/act_vlan.c
32
tcf_action_update_bstats(&v->common, skb);
net/sched/act_vlan.c
323
tcf_tm_dump(&t, &v->tcf_tm);
net/sched/act_vlan.c
339
struct tcf_vlan *v = to_vlan(a);
net/sched/act_vlan.c
340
struct tcf_t *tm = &v->tcf_tm;
net/sched/act_vlan.c
40
p = rcu_dereference_bh(v->vlan_p);
net/sched/em_meta.c
100
struct tcf_pkt_info *info, struct meta_value *v, \
net/sched/em_meta.c
706
static void meta_var_destroy(struct meta_value *v)
net/sched/em_meta.c
708
kfree((void *) v->val);
net/sched/em_meta.c
711
static void meta_var_apply_extras(struct meta_value *v,
net/sched/em_meta.c
714
int shift = v->hdr.shift;
net/sched/em_meta.c
720
static int meta_var_dump(struct sk_buff *skb, struct meta_value *v, int tlv)
net/sched/em_meta.c
722
if (v->val && v->len &&
net/sched/em_meta.c
723
nla_put(skb, tlv, v->len, (void *) v->val))
net/sched/em_meta.c
762
static void meta_int_apply_extras(struct meta_value *v,
net/sched/em_meta.c
765
if (v->hdr.shift)
net/sched/em_meta.c
766
dst->value >>= v->hdr.shift;
net/sched/em_meta.c
768
if (v->val)
net/sched/em_meta.c
769
dst->value &= v->val;
net/sched/em_meta.c
772
static int meta_int_dump(struct sk_buff *skb, struct meta_value *v, int tlv)
net/sched/em_meta.c
774
if (v->len == sizeof(unsigned long)) {
net/sched/em_meta.c
775
if (nla_put(skb, tlv, sizeof(unsigned long), &v->val))
net/sched/em_meta.c
777
} else if (v->len == sizeof(u32)) {
net/sched/em_meta.c
778
if (nla_put_u32(skb, tlv, v->val))
net/sched/em_meta.c
816
static inline const struct meta_type_ops *meta_type_ops(struct meta_value *v)
net/sched/em_meta.c
818
return &__meta_type_ops[meta_type(v)];
net/sched/em_meta.c
826
struct meta_value *v, struct meta_obj *dst)
net/sched/em_meta.c
830
if (meta_id(v) == TCF_META_ID_VALUE) {
net/sched/em_meta.c
831
dst->value = v->val;
net/sched/em_meta.c
832
dst->len = v->len;
net/sched/em_meta.c
836
meta_ops(v)->get(skb, info, v, dst, &err);
net/sched/em_meta.c
840
if (meta_type_ops(v)->apply_extras)
net/sched/em_meta.c
841
meta_type_ops(v)->apply_extras(v, dst);
net/sched/em_meta.c
89
static inline int meta_id(struct meta_value *v)
net/sched/em_meta.c
91
return TCF_META_ID(v->hdr.kind);
net/sched/em_meta.c
94
static inline int meta_type(struct meta_value *v)
net/sched/em_meta.c
96
return TCF_META_TYPE(v->hdr.kind);
net/sched/ematch.c
264
void *v = kmemdup(data, data_len, GFP_KERNEL);
net/sched/ematch.c
265
if (v == NULL) {
net/sched/ematch.c
269
em->data = (unsigned long) v;
net/sched/sch_api.c
2440
static int psched_show(struct seq_file *seq, void *v)
net/sctp/bind_addr.c
236
retval.v = NULL;
net/sctp/bind_addr.c
240
retval.v = kmalloc(len, gfp);
net/sctp/bind_addr.c
241
if (!retval.v)
net/sctp/bind_addr.c
249
memcpy(addrparms.v, &rawaddr, len);
net/sctp/bind_addr.c
250
addrparms.v += len;
net/sctp/inqueue.c
210
chunk->subh.v = NULL; /* Subheader is no longer valid. */
net/sctp/objcnt.c
62
static int sctp_objcnt_seq_show(struct seq_file *seq, void *v)
net/sctp/objcnt.c
66
i = (int)*(loff_t *)v;
net/sctp/objcnt.c
79
static void sctp_objcnt_seq_stop(struct seq_file *seq, void *v)
net/sctp/objcnt.c
83
static void *sctp_objcnt_seq_next(struct seq_file *seq, void *v, loff_t *pos)
net/sctp/proc.c
146
static void sctp_eps_seq_stop(struct seq_file *seq, void *v)
net/sctp/proc.c
151
static void *sctp_eps_seq_next(struct seq_file *seq, void *v, loff_t *pos)
net/sctp/proc.c
161
static int sctp_eps_seq_show(struct seq_file *seq, void *v)
net/sctp/proc.c
166
int hash = *(loff_t *)v;
net/sctp/proc.c
212
static void sctp_transport_seq_stop(struct seq_file *seq, void *v)
net/sctp/proc.c
216
if (v && v != SEQ_START_TOKEN) {
net/sctp/proc.c
217
struct sctp_transport *transport = v;
net/sctp/proc.c
225
static void *sctp_transport_seq_next(struct seq_file *seq, void *v, loff_t *pos)
net/sctp/proc.c
229
if (v && v != SEQ_START_TOKEN) {
net/sctp/proc.c
230
struct sctp_transport *transport = v;
net/sctp/proc.c
241
static int sctp_assocs_seq_show(struct seq_file *seq, void *v)
net/sctp/proc.c
248
if (v == SEQ_START_TOKEN) {
net/sctp/proc.c
257
transport = (struct sctp_transport *)v;
net/sctp/proc.c
300
static int sctp_remaddr_seq_show(struct seq_file *seq, void *v)
net/sctp/proc.c
305
if (v == SEQ_START_TOKEN) {
net/sctp/proc.c
311
transport = (struct sctp_transport *)v;
net/sctp/proc.c
58
static int sctp_snmp_seq_show(struct seq_file *seq, void *v)
net/sctp/sm_make_chunk.c
1975
param.v, len, 0);
net/sctp/sm_make_chunk.c
2116
param.v);
net/sctp/sm_make_chunk.c
2291
if (param.v != (void *)chunk->chunk_end)
net/sctp/sm_make_chunk.c
2633
addr_param = param.v + sizeof(struct sctp_addip_param);
net/sctp/sm_make_chunk.c
2793
retval->param_hdr.v =
net/sctp/sm_make_chunk.c
317
retval->param_hdr.v =
net/sctp/sm_make_chunk.c
318
sctp_addto_chunk(retval, addrs_len, addrs.v);
net/sctp/sm_make_chunk.c
3188
if (param.v != (addip + 1))
net/sctp/sm_make_chunk.c
3195
if (param.v != (addip + 1))
net/sctp/sm_make_chunk.c
3226
if (param.v != chunk->chunk_end)
net/sctp/sm_make_chunk.c
3609
retval->param_hdr.v = (u8 *)(reconf + 1);
net/sctp/sm_make_chunk.c
367
kfree(addrs.v);
net/sctp/sm_make_chunk.c
404
addrs.v, addrs_len);
net/sctp/sm_make_chunk.c
484
retval->param_hdr.v = sctp_addto_chunk(retval, addrs_len, addrs.v);
net/sctp/sm_make_chunk.c
521
kfree(addrs.v);
net/sctp/sm_statefuns.c
1557
chunk->param_hdr.v = skb_pull(chunk->skb, sizeof(struct sctp_inithdr));
net/sctp/sm_statefuns.c
409
chunk->param_hdr.v = skb_pull(chunk->skb, sizeof(struct sctp_inithdr));
net/sctp/sm_statefuns.c
599
chunk->param_hdr.v = skb_pull(chunk->skb, sizeof(struct sctp_inithdr));
net/sctp/socket.c
2835
struct sctp_assoc_value *v = (struct sctp_assoc_value *)params;
net/sctp/socket.c
2844
p.sack_assoc_id = v->assoc_id;
net/sctp/socket.c
2845
p.sack_delay = v->assoc_value;
net/sctp/socket.c
2846
p.sack_freq = v->assoc_value ? 0 : 1;
net/sctp/stream.c
499
struct sctp_strreset_tsnreq *req = param.v;
net/sctp/stream.c
503
return param.v;
net/sctp/stream.c
521
struct sctp_strreset_outreq *outreq = param.v;
net/sctp/stream.c
610
struct sctp_strreset_inreq *inreq = param.v;
net/sctp/stream.c
688
struct sctp_strreset_tsnreq *tsnreq = param.v;
net/sctp/stream.c
784
struct sctp_strreset_addstrm *addstrm = param.v;
net/sctp/stream.c
854
struct sctp_strreset_addstrm *addstrm = param.v;
net/sctp/stream.c
920
struct sctp_strreset_resp *resp = param.v;
net/sunrpc/auth_gss/gss_rpc_xdr.c
11
static int gssx_enc_bool(struct xdr_stream *xdr, int v)
net/sunrpc/auth_gss/gss_rpc_xdr.c
18
*p = v ? xdr_one : xdr_zero;
net/sunrpc/auth_gss/gss_rpc_xdr.c
22
static int gssx_dec_bool(struct xdr_stream *xdr, u32 *v)
net/sunrpc/auth_gss/gss_rpc_xdr.c
29
*v = be32_to_cpu(*p);
net/sunrpc/debugfs.c
177
xprt_info_show(struct seq_file *f, void *v)
net/sunrpc/debugfs.c
20
tasks_show(struct seq_file *f, void *v)
net/sunrpc/debugfs.c
23
struct rpc_task *task = v;
net/sunrpc/debugfs.c
57
tasks_next(struct seq_file *f, void *v, loff_t *pos)
net/sunrpc/debugfs.c
60
struct rpc_task *task = v;
net/sunrpc/debugfs.c
72
tasks_stop(struct seq_file *f, void *v)
net/sunrpc/rpc_pipe.c
1076
rpc_dummy_info_show(struct seq_file *m, void *v)
net/sunrpc/rpc_pipe.c
398
rpc_show_info(struct seq_file *m, void *v)
net/sunrpc/stats.c
37
static int rpc_proc_show(struct seq_file *seq, void *v) {
net/tipc/monitor.c
155
static void map_set(u64 *up_map, int i, unsigned int v)
net/tipc/monitor.c
158
*up_map |= ((u64)v << i);
net/tls/tls_proc.c
32
static int tls_statistics_seq_show(struct seq_file *seq, void *v)
net/unix/af_unix.c
3513
static void *unix_seq_next(struct seq_file *seq, void *v, loff_t *pos)
net/unix/af_unix.c
3517
if (v == SEQ_START_TOKEN)
net/unix/af_unix.c
3520
return unix_get_next(seq, v, pos);
net/unix/af_unix.c
3523
static void unix_seq_stop(struct seq_file *seq, void *v)
net/unix/af_unix.c
3525
struct sock *sk = v;
net/unix/af_unix.c
3531
static int unix_seq_show(struct seq_file *seq, void *v)
net/unix/af_unix.c
3534
if (v == SEQ_START_TOKEN)
net/unix/af_unix.c
3538
struct sock *s = v;
net/unix/af_unix.c
3706
static void *bpf_iter_unix_seq_next(struct seq_file *seq, void *v, loff_t *pos)
net/unix/af_unix.c
3728
static int bpf_iter_unix_seq_show(struct seq_file *seq, void *v)
net/unix/af_unix.c
3732
struct sock *sk = v;
net/unix/af_unix.c
3737
if (v == SEQ_START_TOKEN)
net/unix/af_unix.c
3750
ret = unix_prog_seq_show(prog, &meta, v, uid);
net/unix/af_unix.c
3756
static void bpf_iter_unix_seq_stop(struct seq_file *seq, void *v)
net/unix/af_unix.c
3762
if (!v) {
net/unix/af_unix.c
3766
(void)unix_prog_seq_show(prog, &meta, v, 0);
net/vmw_vsock/af_vsock.c
2094
} v;
net/vmw_vsock/af_vsock.c
2096
int lv = sizeof(v.val64);
net/vmw_vsock/af_vsock.c
2105
memset(&v, 0, sizeof(v));
net/vmw_vsock/af_vsock.c
2109
v.val64 = vsk->buffer_size;
net/vmw_vsock/af_vsock.c
2113
v.val64 = vsk->buffer_max_size;
net/vmw_vsock/af_vsock.c
2117
v.val64 = vsk->buffer_min_size;
net/vmw_vsock/af_vsock.c
2122
lv = sock_get_timeout(vsk->connect_timeout, &v,
net/vmw_vsock/af_vsock.c
2134
if (copy_to_user(optval, &v, len))
net/wireless/nl80211.c
8253
struct net_device *v;
net/wireless/nl80211.c
8259
v = dev_get_by_index(genl_info_net(info), nla_get_u32(vlanattr));
net/wireless/nl80211.c
8260
if (!v)
net/wireless/nl80211.c
8263
if (!v->ieee80211_ptr || v->ieee80211_ptr->wiphy != &rdev->wiphy) {
net/wireless/nl80211.c
8268
if (v->ieee80211_ptr->iftype != NL80211_IFTYPE_AP_VLAN &&
net/wireless/nl80211.c
8269
v->ieee80211_ptr->iftype != NL80211_IFTYPE_AP &&
net/wireless/nl80211.c
8270
v->ieee80211_ptr->iftype != NL80211_IFTYPE_P2P_GO) {
net/wireless/nl80211.c
8275
if (!netif_running(v)) {
net/wireless/nl80211.c
8280
return v;
net/wireless/nl80211.c
8282
dev_put(v);
net/wireless/wext-proc.c
107
static void *wireless_dev_seq_next(struct seq_file *seq, void *v, loff_t *pos)
net/wireless/wext-proc.c
113
return v == SEQ_START_TOKEN ?
net/wireless/wext-proc.c
114
first_net_device(net) : next_net_device(v);
net/wireless/wext-proc.c
117
static void wireless_dev_seq_stop(struct seq_file *seq, void *v)
net/wireless/wext-proc.c
75
static int wireless_dev_seq_show(struct seq_file *seq, void *v)
net/wireless/wext-proc.c
79
if (v == SEQ_START_TOKEN)
net/wireless/wext-proc.c
86
wireless_seq_printf_stats(seq, v);
net/x25/x25_proc.c
119
static void *x25_seq_forward_next(struct seq_file *seq, void *v, loff_t *pos)
net/x25/x25_proc.c
121
return seq_list_next(v, &x25_forward_list, pos);
net/x25/x25_proc.c
124
static void x25_seq_forward_stop(struct seq_file *seq, void *v)
net/x25/x25_proc.c
130
static int x25_seq_forward_show(struct seq_file *seq, void *v)
net/x25/x25_proc.c
132
struct x25_forward *f = list_entry(v, struct x25_forward, node);
net/x25/x25_proc.c
134
if (v == &x25_forward_list) {
net/x25/x25_proc.c
139
f = v;
net/x25/x25_proc.c
32
static void *x25_seq_route_next(struct seq_file *seq, void *v, loff_t *pos)
net/x25/x25_proc.c
34
return seq_list_next(v, &x25_route_list, pos);
net/x25/x25_proc.c
37
static void x25_seq_route_stop(struct seq_file *seq, void *v)
net/x25/x25_proc.c
43
static int x25_seq_route_show(struct seq_file *seq, void *v)
net/x25/x25_proc.c
45
struct x25_route *rt = list_entry(v, struct x25_route, node);
net/x25/x25_proc.c
47
if (v == &x25_route_list) {
net/x25/x25_proc.c
52
rt = v;
net/x25/x25_proc.c
67
static void *x25_seq_socket_next(struct seq_file *seq, void *v, loff_t *pos)
net/x25/x25_proc.c
69
return seq_hlist_next(v, &x25_list, pos);
net/x25/x25_proc.c
72
static void x25_seq_socket_stop(struct seq_file *seq, void *v)
net/x25/x25_proc.c
78
static int x25_seq_socket_show(struct seq_file *seq, void *v)
net/x25/x25_proc.c
84
if (v == SEQ_START_TOKEN) {
net/x25/x25_proc.c
90
s = sk_entry(v);
net/xfrm/xfrm_policy.c
1014
struct xfrm_pol_inexact_node *v,
net/xfrm/xfrm_policy.c
1026
while ((rnode = rb_first(&v->root)) != NULL) {
net/xfrm/xfrm_policy.c
1028
rb_erase(&node->node, &v->root);
net/xfrm/xfrm_policy.c
1033
hlist_for_each_entry(tmp, &v->hhead, bydst) {
net/xfrm/xfrm_policy.c
1489
return mark->v == pol->mark.v && mark->m == pol->mark.m;
net/xfrm/xfrm_policy.c
1585
policy->mark.v &= policy->mark.m;
net/xfrm/xfrm_policy.c
1980
(fl->flowi_mark & pol->mark.m) != pol->mark.v ||
net/xfrm/xfrm_policy.c
2260
if ((READ_ONCE(sk->sk_mark) & pol->mark.m) != pol->mark.v ||
net/xfrm/xfrm_policy.c
2732
if (xfrm[i]->props.smark.v || xfrm[i]->props.smark.m)
net/xfrm/xfrm_policy.c
2919
skb->mark = pol->mark.v;
net/xfrm/xfrm_policy.c
2955
skb->mark = pol->mark.v;
net/xfrm/xfrm_proc.c
50
static int xfrm_statistics_seq_show(struct seq_file *seq, void *v)
net/xfrm/xfrm_state.c
1165
if ((mark & x->mark.m) != x->mark.v)
net/xfrm/xfrm_state.c
1191
if ((mark & x->mark.m) != x->mark.v)
net/xfrm/xfrm_state.c
1220
if ((mark & x->mark.m) != x->mark.v)
net/xfrm/xfrm_state.c
1264
if ((mark & x->mark.m) != x->mark.v)
net/xfrm/xfrm_state.c
1279
u32 mark = x->mark.v & x->mark.m;
net/xfrm/xfrm_state.c
1362
u32 mark = pol->mark.v & pol->mark.m;
net/xfrm/xfrm_state.c
1384
(mark & x->mark.m) == x->mark.v &&
net/xfrm/xfrm_state.c
1401
(mark & x->mark.m) == x->mark.v &&
net/xfrm/xfrm_state.c
1442
(mark & x->mark.m) == x->mark.v &&
net/xfrm/xfrm_state.c
1477
(mark & x->mark.m) == x->mark.v &&
net/xfrm/xfrm_state.c
1658
(mark & x->mark.m) == x->mark.v &&
net/xfrm/xfrm_state.c
1723
x->mark.v &= x->mark.m;
net/xfrm/xfrm_state.c
1771
u32 mark = xnew->mark.v & xnew->mark.m;
net/xfrm/xfrm_state.c
1781
(mark & x->mark.m) == x->mark.v &&
net/xfrm/xfrm_state.c
1810
u32 mark = m->v & m->m;
net/xfrm/xfrm_state.c
1819
(mark & x->mark.m) != x->mark.v ||
net/xfrm/xfrm_state.c
1861
x->mark.v = m->v;
net/xfrm/xfrm_state.c
1893
u32 mark = x->mark.v & x->mark.m;
net/xfrm/xfrm_state.c
2252
if (x->props.smark.m || x->props.smark.v || x->if_id) {
net/xfrm/xfrm_state.c
2255
if (x->props.smark.m || x->props.smark.v)
net/xfrm/xfrm_state.c
2409
const struct xfrm_state *v = p;
net/xfrm/xfrm_state.c
2411
switch (v->props.mode) {
net/xfrm/xfrm_state.c
2413
if (v->id.proto != IPPROTO_AH)
net/xfrm/xfrm_state.c
2439
const struct xfrm_tmpl *v = p;
net/xfrm/xfrm_state.c
2441
switch (v->mode) {
net/xfrm/xfrm_state.c
2509
(mark & x->mark.m) == x->mark.v &&
net/xfrm/xfrm_user.c
1327
if (m->v | m->m) {
net/xfrm/xfrm_user.c
1328
ret = nla_put_u32(skb, XFRMA_SET_MARK, m->v);
net/xfrm/xfrm_user.c
3042
xp->mark.v = x->mark.v = mark.v;
net/xfrm/xfrm_user.c
3688
if (x->props.smark.v | x->props.smark.m) {
net/xfrm/xfrm_user.c
3689
l += nla_total_size(sizeof(x->props.smark.v));
net/xfrm/xfrm_user.c
884
m->v = nla_get_u32(attrs[XFRMA_SET_MARK]);
net/xfrm/xfrm_user.c
888
m->v = m->m = 0;
rust/helpers/atomic.c
1001
return atomic64_fetch_add_unless(v, a, u);
rust/helpers/atomic.c
1005
rust_helper_atomic64_add_unless(atomic64_t *v, s64 a, s64 u)
rust/helpers/atomic.c
1007
return atomic64_add_unless(v, a, u);
rust/helpers/atomic.c
101
return atomic_sub_return(i, v);
rust/helpers/atomic.c
1011
rust_helper_atomic64_inc_not_zero(atomic64_t *v)
rust/helpers/atomic.c
1013
return atomic64_inc_not_zero(v);
rust/helpers/atomic.c
1017
rust_helper_atomic64_inc_unless_negative(atomic64_t *v)
rust/helpers/atomic.c
1019
return atomic64_inc_unless_negative(v);
rust/helpers/atomic.c
1023
rust_helper_atomic64_dec_unless_positive(atomic64_t *v)
rust/helpers/atomic.c
1025
return atomic64_dec_unless_positive(v);
rust/helpers/atomic.c
1029
rust_helper_atomic64_dec_if_positive(atomic64_t *v)
rust/helpers/atomic.c
1031
return atomic64_dec_if_positive(v);
rust/helpers/atomic.c
105
rust_helper_atomic_sub_return_acquire(int i, atomic_t *v)
rust/helpers/atomic.c
107
return atomic_sub_return_acquire(i, v);
rust/helpers/atomic.c
111
rust_helper_atomic_sub_return_release(int i, atomic_t *v)
rust/helpers/atomic.c
113
return atomic_sub_return_release(i, v);
rust/helpers/atomic.c
117
rust_helper_atomic_sub_return_relaxed(int i, atomic_t *v)
rust/helpers/atomic.c
119
return atomic_sub_return_relaxed(i, v);
rust/helpers/atomic.c
123
rust_helper_atomic_fetch_sub(int i, atomic_t *v)
rust/helpers/atomic.c
125
return atomic_fetch_sub(i, v);
rust/helpers/atomic.c
129
rust_helper_atomic_fetch_sub_acquire(int i, atomic_t *v)
rust/helpers/atomic.c
131
return atomic_fetch_sub_acquire(i, v);
rust/helpers/atomic.c
135
rust_helper_atomic_fetch_sub_release(int i, atomic_t *v)
rust/helpers/atomic.c
137
return atomic_fetch_sub_release(i, v);
rust/helpers/atomic.c
141
rust_helper_atomic_fetch_sub_relaxed(int i, atomic_t *v)
rust/helpers/atomic.c
143
return atomic_fetch_sub_relaxed(i, v);
rust/helpers/atomic.c
147
rust_helper_atomic_inc(atomic_t *v)
rust/helpers/atomic.c
149
atomic_inc(v);
rust/helpers/atomic.c
15
rust_helper_atomic_read(const atomic_t *v)
rust/helpers/atomic.c
153
rust_helper_atomic_inc_return(atomic_t *v)
rust/helpers/atomic.c
155
return atomic_inc_return(v);
rust/helpers/atomic.c
159
rust_helper_atomic_inc_return_acquire(atomic_t *v)
rust/helpers/atomic.c
161
return atomic_inc_return_acquire(v);
rust/helpers/atomic.c
165
rust_helper_atomic_inc_return_release(atomic_t *v)
rust/helpers/atomic.c
167
return atomic_inc_return_release(v);
rust/helpers/atomic.c
17
return atomic_read(v);
rust/helpers/atomic.c
171
rust_helper_atomic_inc_return_relaxed(atomic_t *v)
rust/helpers/atomic.c
173
return atomic_inc_return_relaxed(v);
rust/helpers/atomic.c
177
rust_helper_atomic_fetch_inc(atomic_t *v)
rust/helpers/atomic.c
179
return atomic_fetch_inc(v);
rust/helpers/atomic.c
183
rust_helper_atomic_fetch_inc_acquire(atomic_t *v)
rust/helpers/atomic.c
185
return atomic_fetch_inc_acquire(v);
rust/helpers/atomic.c
189
rust_helper_atomic_fetch_inc_release(atomic_t *v)
rust/helpers/atomic.c
191
return atomic_fetch_inc_release(v);
rust/helpers/atomic.c
195
rust_helper_atomic_fetch_inc_relaxed(atomic_t *v)
rust/helpers/atomic.c
197
return atomic_fetch_inc_relaxed(v);
rust/helpers/atomic.c
201
rust_helper_atomic_dec(atomic_t *v)
rust/helpers/atomic.c
203
atomic_dec(v);
rust/helpers/atomic.c
207
rust_helper_atomic_dec_return(atomic_t *v)
rust/helpers/atomic.c
209
return atomic_dec_return(v);
rust/helpers/atomic.c
21
rust_helper_atomic_read_acquire(const atomic_t *v)
rust/helpers/atomic.c
213
rust_helper_atomic_dec_return_acquire(atomic_t *v)
rust/helpers/atomic.c
215
return atomic_dec_return_acquire(v);
rust/helpers/atomic.c
219
rust_helper_atomic_dec_return_release(atomic_t *v)
rust/helpers/atomic.c
221
return atomic_dec_return_release(v);
rust/helpers/atomic.c
225
rust_helper_atomic_dec_return_relaxed(atomic_t *v)
rust/helpers/atomic.c
227
return atomic_dec_return_relaxed(v);
rust/helpers/atomic.c
23
return atomic_read_acquire(v);
rust/helpers/atomic.c
231
rust_helper_atomic_fetch_dec(atomic_t *v)
rust/helpers/atomic.c
233
return atomic_fetch_dec(v);
rust/helpers/atomic.c
237
rust_helper_atomic_fetch_dec_acquire(atomic_t *v)
rust/helpers/atomic.c
239
return atomic_fetch_dec_acquire(v);
rust/helpers/atomic.c
243
rust_helper_atomic_fetch_dec_release(atomic_t *v)
rust/helpers/atomic.c
245
return atomic_fetch_dec_release(v);
rust/helpers/atomic.c
249
rust_helper_atomic_fetch_dec_relaxed(atomic_t *v)
rust/helpers/atomic.c
251
return atomic_fetch_dec_relaxed(v);
rust/helpers/atomic.c
255
rust_helper_atomic_and(int i, atomic_t *v)
rust/helpers/atomic.c
257
atomic_and(i, v);
rust/helpers/atomic.c
261
rust_helper_atomic_fetch_and(int i, atomic_t *v)
rust/helpers/atomic.c
263
return atomic_fetch_and(i, v);
rust/helpers/atomic.c
267
rust_helper_atomic_fetch_and_acquire(int i, atomic_t *v)
rust/helpers/atomic.c
269
return atomic_fetch_and_acquire(i, v);
rust/helpers/atomic.c
27
rust_helper_atomic_set(atomic_t *v, int i)
rust/helpers/atomic.c
273
rust_helper_atomic_fetch_and_release(int i, atomic_t *v)
rust/helpers/atomic.c
275
return atomic_fetch_and_release(i, v);
rust/helpers/atomic.c
279
rust_helper_atomic_fetch_and_relaxed(int i, atomic_t *v)
rust/helpers/atomic.c
281
return atomic_fetch_and_relaxed(i, v);
rust/helpers/atomic.c
285
rust_helper_atomic_andnot(int i, atomic_t *v)
rust/helpers/atomic.c
287
atomic_andnot(i, v);
rust/helpers/atomic.c
29
atomic_set(v, i);
rust/helpers/atomic.c
291
rust_helper_atomic_fetch_andnot(int i, atomic_t *v)
rust/helpers/atomic.c
293
return atomic_fetch_andnot(i, v);
rust/helpers/atomic.c
297
rust_helper_atomic_fetch_andnot_acquire(int i, atomic_t *v)
rust/helpers/atomic.c
299
return atomic_fetch_andnot_acquire(i, v);
rust/helpers/atomic.c
303
rust_helper_atomic_fetch_andnot_release(int i, atomic_t *v)
rust/helpers/atomic.c
305
return atomic_fetch_andnot_release(i, v);
rust/helpers/atomic.c
309
rust_helper_atomic_fetch_andnot_relaxed(int i, atomic_t *v)
rust/helpers/atomic.c
311
return atomic_fetch_andnot_relaxed(i, v);
rust/helpers/atomic.c
315
rust_helper_atomic_or(int i, atomic_t *v)
rust/helpers/atomic.c
317
atomic_or(i, v);
rust/helpers/atomic.c
321
rust_helper_atomic_fetch_or(int i, atomic_t *v)
rust/helpers/atomic.c
323
return atomic_fetch_or(i, v);
rust/helpers/atomic.c
327
rust_helper_atomic_fetch_or_acquire(int i, atomic_t *v)
rust/helpers/atomic.c
329
return atomic_fetch_or_acquire(i, v);
rust/helpers/atomic.c
33
rust_helper_atomic_set_release(atomic_t *v, int i)
rust/helpers/atomic.c
333
rust_helper_atomic_fetch_or_release(int i, atomic_t *v)
rust/helpers/atomic.c
335
return atomic_fetch_or_release(i, v);
rust/helpers/atomic.c
339
rust_helper_atomic_fetch_or_relaxed(int i, atomic_t *v)
rust/helpers/atomic.c
341
return atomic_fetch_or_relaxed(i, v);
rust/helpers/atomic.c
345
rust_helper_atomic_xor(int i, atomic_t *v)
rust/helpers/atomic.c
347
atomic_xor(i, v);
rust/helpers/atomic.c
35
atomic_set_release(v, i);
rust/helpers/atomic.c
351
rust_helper_atomic_fetch_xor(int i, atomic_t *v)
rust/helpers/atomic.c
353
return atomic_fetch_xor(i, v);
rust/helpers/atomic.c
357
rust_helper_atomic_fetch_xor_acquire(int i, atomic_t *v)
rust/helpers/atomic.c
359
return atomic_fetch_xor_acquire(i, v);
rust/helpers/atomic.c
363
rust_helper_atomic_fetch_xor_release(int i, atomic_t *v)
rust/helpers/atomic.c
365
return atomic_fetch_xor_release(i, v);
rust/helpers/atomic.c
369
rust_helper_atomic_fetch_xor_relaxed(int i, atomic_t *v)
rust/helpers/atomic.c
371
return atomic_fetch_xor_relaxed(i, v);
rust/helpers/atomic.c
375
rust_helper_atomic_xchg(atomic_t *v, int new)
rust/helpers/atomic.c
377
return atomic_xchg(v, new);
rust/helpers/atomic.c
381
rust_helper_atomic_xchg_acquire(atomic_t *v, int new)
rust/helpers/atomic.c
383
return atomic_xchg_acquire(v, new);
rust/helpers/atomic.c
387
rust_helper_atomic_xchg_release(atomic_t *v, int new)
rust/helpers/atomic.c
389
return atomic_xchg_release(v, new);
rust/helpers/atomic.c
39
rust_helper_atomic_add(int i, atomic_t *v)
rust/helpers/atomic.c
393
rust_helper_atomic_xchg_relaxed(atomic_t *v, int new)
rust/helpers/atomic.c
395
return atomic_xchg_relaxed(v, new);
rust/helpers/atomic.c
399
rust_helper_atomic_cmpxchg(atomic_t *v, int old, int new)
rust/helpers/atomic.c
401
return atomic_cmpxchg(v, old, new);
rust/helpers/atomic.c
405
rust_helper_atomic_cmpxchg_acquire(atomic_t *v, int old, int new)
rust/helpers/atomic.c
407
return atomic_cmpxchg_acquire(v, old, new);
rust/helpers/atomic.c
41
atomic_add(i, v);
rust/helpers/atomic.c
411
rust_helper_atomic_cmpxchg_release(atomic_t *v, int old, int new)
rust/helpers/atomic.c
413
return atomic_cmpxchg_release(v, old, new);
rust/helpers/atomic.c
417
rust_helper_atomic_cmpxchg_relaxed(atomic_t *v, int old, int new)
rust/helpers/atomic.c
419
return atomic_cmpxchg_relaxed(v, old, new);
rust/helpers/atomic.c
423
rust_helper_atomic_try_cmpxchg(atomic_t *v, int *old, int new)
rust/helpers/atomic.c
425
return atomic_try_cmpxchg(v, old, new);
rust/helpers/atomic.c
429
rust_helper_atomic_try_cmpxchg_acquire(atomic_t *v, int *old, int new)
rust/helpers/atomic.c
431
return atomic_try_cmpxchg_acquire(v, old, new);
rust/helpers/atomic.c
435
rust_helper_atomic_try_cmpxchg_release(atomic_t *v, int *old, int new)
rust/helpers/atomic.c
437
return atomic_try_cmpxchg_release(v, old, new);
rust/helpers/atomic.c
441
rust_helper_atomic_try_cmpxchg_relaxed(atomic_t *v, int *old, int new)
rust/helpers/atomic.c
443
return atomic_try_cmpxchg_relaxed(v, old, new);
rust/helpers/atomic.c
447
rust_helper_atomic_sub_and_test(int i, atomic_t *v)
rust/helpers/atomic.c
449
return atomic_sub_and_test(i, v);
rust/helpers/atomic.c
45
rust_helper_atomic_add_return(int i, atomic_t *v)
rust/helpers/atomic.c
453
rust_helper_atomic_dec_and_test(atomic_t *v)
rust/helpers/atomic.c
455
return atomic_dec_and_test(v);
rust/helpers/atomic.c
459
rust_helper_atomic_inc_and_test(atomic_t *v)
rust/helpers/atomic.c
461
return atomic_inc_and_test(v);
rust/helpers/atomic.c
465
rust_helper_atomic_add_negative(int i, atomic_t *v)
rust/helpers/atomic.c
467
return atomic_add_negative(i, v);
rust/helpers/atomic.c
47
return atomic_add_return(i, v);
rust/helpers/atomic.c
471
rust_helper_atomic_add_negative_acquire(int i, atomic_t *v)
rust/helpers/atomic.c
473
return atomic_add_negative_acquire(i, v);
rust/helpers/atomic.c
477
rust_helper_atomic_add_negative_release(int i, atomic_t *v)
rust/helpers/atomic.c
479
return atomic_add_negative_release(i, v);
rust/helpers/atomic.c
483
rust_helper_atomic_add_negative_relaxed(int i, atomic_t *v)
rust/helpers/atomic.c
485
return atomic_add_negative_relaxed(i, v);
rust/helpers/atomic.c
489
rust_helper_atomic_fetch_add_unless(atomic_t *v, int a, int u)
rust/helpers/atomic.c
491
return atomic_fetch_add_unless(v, a, u);
rust/helpers/atomic.c
495
rust_helper_atomic_add_unless(atomic_t *v, int a, int u)
rust/helpers/atomic.c
497
return atomic_add_unless(v, a, u);
rust/helpers/atomic.c
501
rust_helper_atomic_inc_not_zero(atomic_t *v)
rust/helpers/atomic.c
503
return atomic_inc_not_zero(v);
rust/helpers/atomic.c
507
rust_helper_atomic_inc_unless_negative(atomic_t *v)
rust/helpers/atomic.c
509
return atomic_inc_unless_negative(v);
rust/helpers/atomic.c
51
rust_helper_atomic_add_return_acquire(int i, atomic_t *v)
rust/helpers/atomic.c
513
rust_helper_atomic_dec_unless_positive(atomic_t *v)
rust/helpers/atomic.c
515
return atomic_dec_unless_positive(v);
rust/helpers/atomic.c
519
rust_helper_atomic_dec_if_positive(atomic_t *v)
rust/helpers/atomic.c
521
return atomic_dec_if_positive(v);
rust/helpers/atomic.c
525
rust_helper_atomic64_read(const atomic64_t *v)
rust/helpers/atomic.c
527
return atomic64_read(v);
rust/helpers/atomic.c
53
return atomic_add_return_acquire(i, v);
rust/helpers/atomic.c
531
rust_helper_atomic64_read_acquire(const atomic64_t *v)
rust/helpers/atomic.c
533
return atomic64_read_acquire(v);
rust/helpers/atomic.c
537
rust_helper_atomic64_set(atomic64_t *v, s64 i)
rust/helpers/atomic.c
539
atomic64_set(v, i);
rust/helpers/atomic.c
543
rust_helper_atomic64_set_release(atomic64_t *v, s64 i)
rust/helpers/atomic.c
545
atomic64_set_release(v, i);
rust/helpers/atomic.c
549
rust_helper_atomic64_add(s64 i, atomic64_t *v)
rust/helpers/atomic.c
551
atomic64_add(i, v);
rust/helpers/atomic.c
555
rust_helper_atomic64_add_return(s64 i, atomic64_t *v)
rust/helpers/atomic.c
557
return atomic64_add_return(i, v);
rust/helpers/atomic.c
561
rust_helper_atomic64_add_return_acquire(s64 i, atomic64_t *v)
rust/helpers/atomic.c
563
return atomic64_add_return_acquire(i, v);
rust/helpers/atomic.c
567
rust_helper_atomic64_add_return_release(s64 i, atomic64_t *v)
rust/helpers/atomic.c
569
return atomic64_add_return_release(i, v);
rust/helpers/atomic.c
57
rust_helper_atomic_add_return_release(int i, atomic_t *v)
rust/helpers/atomic.c
573
rust_helper_atomic64_add_return_relaxed(s64 i, atomic64_t *v)
rust/helpers/atomic.c
575
return atomic64_add_return_relaxed(i, v);
rust/helpers/atomic.c
579
rust_helper_atomic64_fetch_add(s64 i, atomic64_t *v)
rust/helpers/atomic.c
581
return atomic64_fetch_add(i, v);
rust/helpers/atomic.c
585
rust_helper_atomic64_fetch_add_acquire(s64 i, atomic64_t *v)
rust/helpers/atomic.c
587
return atomic64_fetch_add_acquire(i, v);
rust/helpers/atomic.c
59
return atomic_add_return_release(i, v);
rust/helpers/atomic.c
591
rust_helper_atomic64_fetch_add_release(s64 i, atomic64_t *v)
rust/helpers/atomic.c
593
return atomic64_fetch_add_release(i, v);
rust/helpers/atomic.c
597
rust_helper_atomic64_fetch_add_relaxed(s64 i, atomic64_t *v)
rust/helpers/atomic.c
599
return atomic64_fetch_add_relaxed(i, v);
rust/helpers/atomic.c
603
rust_helper_atomic64_sub(s64 i, atomic64_t *v)
rust/helpers/atomic.c
605
atomic64_sub(i, v);
rust/helpers/atomic.c
609
rust_helper_atomic64_sub_return(s64 i, atomic64_t *v)
rust/helpers/atomic.c
611
return atomic64_sub_return(i, v);
rust/helpers/atomic.c
615
rust_helper_atomic64_sub_return_acquire(s64 i, atomic64_t *v)
rust/helpers/atomic.c
617
return atomic64_sub_return_acquire(i, v);
rust/helpers/atomic.c
621
rust_helper_atomic64_sub_return_release(s64 i, atomic64_t *v)
rust/helpers/atomic.c
623
return atomic64_sub_return_release(i, v);
rust/helpers/atomic.c
627
rust_helper_atomic64_sub_return_relaxed(s64 i, atomic64_t *v)
rust/helpers/atomic.c
629
return atomic64_sub_return_relaxed(i, v);
rust/helpers/atomic.c
63
rust_helper_atomic_add_return_relaxed(int i, atomic_t *v)
rust/helpers/atomic.c
633
rust_helper_atomic64_fetch_sub(s64 i, atomic64_t *v)
rust/helpers/atomic.c
635
return atomic64_fetch_sub(i, v);
rust/helpers/atomic.c
639
rust_helper_atomic64_fetch_sub_acquire(s64 i, atomic64_t *v)
rust/helpers/atomic.c
641
return atomic64_fetch_sub_acquire(i, v);
rust/helpers/atomic.c
645
rust_helper_atomic64_fetch_sub_release(s64 i, atomic64_t *v)
rust/helpers/atomic.c
647
return atomic64_fetch_sub_release(i, v);
rust/helpers/atomic.c
65
return atomic_add_return_relaxed(i, v);
rust/helpers/atomic.c
651
rust_helper_atomic64_fetch_sub_relaxed(s64 i, atomic64_t *v)
rust/helpers/atomic.c
653
return atomic64_fetch_sub_relaxed(i, v);
rust/helpers/atomic.c
657
rust_helper_atomic64_inc(atomic64_t *v)
rust/helpers/atomic.c
659
atomic64_inc(v);
rust/helpers/atomic.c
663
rust_helper_atomic64_inc_return(atomic64_t *v)
rust/helpers/atomic.c
665
return atomic64_inc_return(v);
rust/helpers/atomic.c
669
rust_helper_atomic64_inc_return_acquire(atomic64_t *v)
rust/helpers/atomic.c
671
return atomic64_inc_return_acquire(v);
rust/helpers/atomic.c
675
rust_helper_atomic64_inc_return_release(atomic64_t *v)
rust/helpers/atomic.c
677
return atomic64_inc_return_release(v);
rust/helpers/atomic.c
681
rust_helper_atomic64_inc_return_relaxed(atomic64_t *v)
rust/helpers/atomic.c
683
return atomic64_inc_return_relaxed(v);
rust/helpers/atomic.c
687
rust_helper_atomic64_fetch_inc(atomic64_t *v)
rust/helpers/atomic.c
689
return atomic64_fetch_inc(v);
rust/helpers/atomic.c
69
rust_helper_atomic_fetch_add(int i, atomic_t *v)
rust/helpers/atomic.c
693
rust_helper_atomic64_fetch_inc_acquire(atomic64_t *v)
rust/helpers/atomic.c
695
return atomic64_fetch_inc_acquire(v);
rust/helpers/atomic.c
699
rust_helper_atomic64_fetch_inc_release(atomic64_t *v)
rust/helpers/atomic.c
701
return atomic64_fetch_inc_release(v);
rust/helpers/atomic.c
705
rust_helper_atomic64_fetch_inc_relaxed(atomic64_t *v)
rust/helpers/atomic.c
707
return atomic64_fetch_inc_relaxed(v);
rust/helpers/atomic.c
71
return atomic_fetch_add(i, v);
rust/helpers/atomic.c
711
rust_helper_atomic64_dec(atomic64_t *v)
rust/helpers/atomic.c
713
atomic64_dec(v);
rust/helpers/atomic.c
717
rust_helper_atomic64_dec_return(atomic64_t *v)
rust/helpers/atomic.c
719
return atomic64_dec_return(v);
rust/helpers/atomic.c
723
rust_helper_atomic64_dec_return_acquire(atomic64_t *v)
rust/helpers/atomic.c
725
return atomic64_dec_return_acquire(v);
rust/helpers/atomic.c
729
rust_helper_atomic64_dec_return_release(atomic64_t *v)
rust/helpers/atomic.c
731
return atomic64_dec_return_release(v);
rust/helpers/atomic.c
735
rust_helper_atomic64_dec_return_relaxed(atomic64_t *v)
rust/helpers/atomic.c
737
return atomic64_dec_return_relaxed(v);
rust/helpers/atomic.c
741
rust_helper_atomic64_fetch_dec(atomic64_t *v)
rust/helpers/atomic.c
743
return atomic64_fetch_dec(v);
rust/helpers/atomic.c
747
rust_helper_atomic64_fetch_dec_acquire(atomic64_t *v)
rust/helpers/atomic.c
749
return atomic64_fetch_dec_acquire(v);
rust/helpers/atomic.c
75
rust_helper_atomic_fetch_add_acquire(int i, atomic_t *v)
rust/helpers/atomic.c
753
rust_helper_atomic64_fetch_dec_release(atomic64_t *v)
rust/helpers/atomic.c
755
return atomic64_fetch_dec_release(v);
rust/helpers/atomic.c
759
rust_helper_atomic64_fetch_dec_relaxed(atomic64_t *v)
rust/helpers/atomic.c
761
return atomic64_fetch_dec_relaxed(v);
rust/helpers/atomic.c
765
rust_helper_atomic64_and(s64 i, atomic64_t *v)
rust/helpers/atomic.c
767
atomic64_and(i, v);
rust/helpers/atomic.c
77
return atomic_fetch_add_acquire(i, v);
rust/helpers/atomic.c
771
rust_helper_atomic64_fetch_and(s64 i, atomic64_t *v)
rust/helpers/atomic.c
773
return atomic64_fetch_and(i, v);
rust/helpers/atomic.c
777
rust_helper_atomic64_fetch_and_acquire(s64 i, atomic64_t *v)
rust/helpers/atomic.c
779
return atomic64_fetch_and_acquire(i, v);
rust/helpers/atomic.c
783
rust_helper_atomic64_fetch_and_release(s64 i, atomic64_t *v)
rust/helpers/atomic.c
785
return atomic64_fetch_and_release(i, v);
rust/helpers/atomic.c
789
rust_helper_atomic64_fetch_and_relaxed(s64 i, atomic64_t *v)
rust/helpers/atomic.c
791
return atomic64_fetch_and_relaxed(i, v);
rust/helpers/atomic.c
795
rust_helper_atomic64_andnot(s64 i, atomic64_t *v)
rust/helpers/atomic.c
797
atomic64_andnot(i, v);
rust/helpers/atomic.c
801
rust_helper_atomic64_fetch_andnot(s64 i, atomic64_t *v)
rust/helpers/atomic.c
803
return atomic64_fetch_andnot(i, v);
rust/helpers/atomic.c
807
rust_helper_atomic64_fetch_andnot_acquire(s64 i, atomic64_t *v)
rust/helpers/atomic.c
809
return atomic64_fetch_andnot_acquire(i, v);
rust/helpers/atomic.c
81
rust_helper_atomic_fetch_add_release(int i, atomic_t *v)
rust/helpers/atomic.c
813
rust_helper_atomic64_fetch_andnot_release(s64 i, atomic64_t *v)
rust/helpers/atomic.c
815
return atomic64_fetch_andnot_release(i, v);
rust/helpers/atomic.c
819
rust_helper_atomic64_fetch_andnot_relaxed(s64 i, atomic64_t *v)
rust/helpers/atomic.c
821
return atomic64_fetch_andnot_relaxed(i, v);
rust/helpers/atomic.c
825
rust_helper_atomic64_or(s64 i, atomic64_t *v)
rust/helpers/atomic.c
827
atomic64_or(i, v);
rust/helpers/atomic.c
83
return atomic_fetch_add_release(i, v);
rust/helpers/atomic.c
831
rust_helper_atomic64_fetch_or(s64 i, atomic64_t *v)
rust/helpers/atomic.c
833
return atomic64_fetch_or(i, v);
rust/helpers/atomic.c
837
rust_helper_atomic64_fetch_or_acquire(s64 i, atomic64_t *v)
rust/helpers/atomic.c
839
return atomic64_fetch_or_acquire(i, v);
rust/helpers/atomic.c
843
rust_helper_atomic64_fetch_or_release(s64 i, atomic64_t *v)
rust/helpers/atomic.c
845
return atomic64_fetch_or_release(i, v);
rust/helpers/atomic.c
849
rust_helper_atomic64_fetch_or_relaxed(s64 i, atomic64_t *v)
rust/helpers/atomic.c
851
return atomic64_fetch_or_relaxed(i, v);
rust/helpers/atomic.c
855
rust_helper_atomic64_xor(s64 i, atomic64_t *v)
rust/helpers/atomic.c
857
atomic64_xor(i, v);
rust/helpers/atomic.c
861
rust_helper_atomic64_fetch_xor(s64 i, atomic64_t *v)
rust/helpers/atomic.c
863
return atomic64_fetch_xor(i, v);
rust/helpers/atomic.c
867
rust_helper_atomic64_fetch_xor_acquire(s64 i, atomic64_t *v)
rust/helpers/atomic.c
869
return atomic64_fetch_xor_acquire(i, v);
rust/helpers/atomic.c
87
rust_helper_atomic_fetch_add_relaxed(int i, atomic_t *v)
rust/helpers/atomic.c
873
rust_helper_atomic64_fetch_xor_release(s64 i, atomic64_t *v)
rust/helpers/atomic.c
875
return atomic64_fetch_xor_release(i, v);
rust/helpers/atomic.c
879
rust_helper_atomic64_fetch_xor_relaxed(s64 i, atomic64_t *v)
rust/helpers/atomic.c
881
return atomic64_fetch_xor_relaxed(i, v);
rust/helpers/atomic.c
885
rust_helper_atomic64_xchg(atomic64_t *v, s64 new)
rust/helpers/atomic.c
887
return atomic64_xchg(v, new);
rust/helpers/atomic.c
89
return atomic_fetch_add_relaxed(i, v);
rust/helpers/atomic.c
891
rust_helper_atomic64_xchg_acquire(atomic64_t *v, s64 new)
rust/helpers/atomic.c
893
return atomic64_xchg_acquire(v, new);
rust/helpers/atomic.c
897
rust_helper_atomic64_xchg_release(atomic64_t *v, s64 new)
rust/helpers/atomic.c
899
return atomic64_xchg_release(v, new);
rust/helpers/atomic.c
903
rust_helper_atomic64_xchg_relaxed(atomic64_t *v, s64 new)
rust/helpers/atomic.c
905
return atomic64_xchg_relaxed(v, new);
rust/helpers/atomic.c
909
rust_helper_atomic64_cmpxchg(atomic64_t *v, s64 old, s64 new)
rust/helpers/atomic.c
911
return atomic64_cmpxchg(v, old, new);
rust/helpers/atomic.c
915
rust_helper_atomic64_cmpxchg_acquire(atomic64_t *v, s64 old, s64 new)
rust/helpers/atomic.c
917
return atomic64_cmpxchg_acquire(v, old, new);
rust/helpers/atomic.c
921
rust_helper_atomic64_cmpxchg_release(atomic64_t *v, s64 old, s64 new)
rust/helpers/atomic.c
923
return atomic64_cmpxchg_release(v, old, new);
rust/helpers/atomic.c
927
rust_helper_atomic64_cmpxchg_relaxed(atomic64_t *v, s64 old, s64 new)
rust/helpers/atomic.c
929
return atomic64_cmpxchg_relaxed(v, old, new);
rust/helpers/atomic.c
93
rust_helper_atomic_sub(int i, atomic_t *v)
rust/helpers/atomic.c
933
rust_helper_atomic64_try_cmpxchg(atomic64_t *v, s64 *old, s64 new)
rust/helpers/atomic.c
935
return atomic64_try_cmpxchg(v, old, new);
rust/helpers/atomic.c
939
rust_helper_atomic64_try_cmpxchg_acquire(atomic64_t *v, s64 *old, s64 new)
rust/helpers/atomic.c
941
return atomic64_try_cmpxchg_acquire(v, old, new);
rust/helpers/atomic.c
945
rust_helper_atomic64_try_cmpxchg_release(atomic64_t *v, s64 *old, s64 new)
rust/helpers/atomic.c
947
return atomic64_try_cmpxchg_release(v, old, new);
rust/helpers/atomic.c
95
atomic_sub(i, v);
rust/helpers/atomic.c
951
rust_helper_atomic64_try_cmpxchg_relaxed(atomic64_t *v, s64 *old, s64 new)
rust/helpers/atomic.c
953
return atomic64_try_cmpxchg_relaxed(v, old, new);
rust/helpers/atomic.c
957
rust_helper_atomic64_sub_and_test(s64 i, atomic64_t *v)
rust/helpers/atomic.c
959
return atomic64_sub_and_test(i, v);
rust/helpers/atomic.c
963
rust_helper_atomic64_dec_and_test(atomic64_t *v)
rust/helpers/atomic.c
965
return atomic64_dec_and_test(v);
rust/helpers/atomic.c
969
rust_helper_atomic64_inc_and_test(atomic64_t *v)
rust/helpers/atomic.c
971
return atomic64_inc_and_test(v);
rust/helpers/atomic.c
975
rust_helper_atomic64_add_negative(s64 i, atomic64_t *v)
rust/helpers/atomic.c
977
return atomic64_add_negative(i, v);
rust/helpers/atomic.c
981
rust_helper_atomic64_add_negative_acquire(s64 i, atomic64_t *v)
rust/helpers/atomic.c
983
return atomic64_add_negative_acquire(i, v);
rust/helpers/atomic.c
987
rust_helper_atomic64_add_negative_release(s64 i, atomic64_t *v)
rust/helpers/atomic.c
989
return atomic64_add_negative_release(i, v);
rust/helpers/atomic.c
99
rust_helper_atomic_sub_return(int i, atomic_t *v)
rust/helpers/atomic.c
993
rust_helper_atomic64_add_negative_relaxed(s64 i, atomic64_t *v)
rust/helpers/atomic.c
995
return atomic64_add_negative_relaxed(i, v);
rust/helpers/atomic.c
999
rust_helper_atomic64_fetch_add_unless(atomic64_t *v, s64 a, s64 u)
samples/bpf/lathist_kern.c
40
static unsigned int log2(unsigned int v)
samples/bpf/lathist_kern.c
45
r = (v > 0xFFFF) << 4; v >>= r;
samples/bpf/lathist_kern.c
46
shift = (v > 0xFF) << 3; v >>= shift; r |= shift;
samples/bpf/lathist_kern.c
47
shift = (v > 0xF) << 2; v >>= shift; r |= shift;
samples/bpf/lathist_kern.c
48
shift = (v > 0x3) << 1; v >>= shift; r |= shift;
samples/bpf/lathist_kern.c
49
r |= (v >> 1);
samples/bpf/lathist_kern.c
54
static unsigned int log2l(unsigned long v)
samples/bpf/lathist_kern.c
56
unsigned int hi = v >> 32;
samples/bpf/lathist_kern.c
61
return log2(v);
samples/bpf/lwt_len_hist.bpf.c
24
static unsigned int log2(unsigned int v)
samples/bpf/lwt_len_hist.bpf.c
29
r = (v > 0xFFFF) << 4; v >>= r;
samples/bpf/lwt_len_hist.bpf.c
30
shift = (v > 0xFF) << 3; v >>= shift; r |= shift;
samples/bpf/lwt_len_hist.bpf.c
31
shift = (v > 0xF) << 2; v >>= shift; r |= shift;
samples/bpf/lwt_len_hist.bpf.c
32
shift = (v > 0x3) << 1; v >>= shift; r |= shift;
samples/bpf/lwt_len_hist.bpf.c
33
r |= (v >> 1);
samples/bpf/lwt_len_hist.bpf.c
37
static unsigned int log2l(unsigned long v)
samples/bpf/lwt_len_hist.bpf.c
39
unsigned int hi = v >> 32;
samples/bpf/lwt_len_hist.bpf.c
43
return log2(v);
samples/bpf/spintest.bpf.c
39
long v = PT_REGS_IP(ctx), *val; \
samples/bpf/spintest.bpf.c
41
val = bpf_map_lookup_elem(&my_map, &v); \
samples/bpf/spintest.bpf.c
42
bpf_map_update_elem(&my_map, &v, &v, BPF_ANY); \
samples/bpf/spintest.bpf.c
43
bpf_map_update_elem(&my_map2, &v, &v, BPF_ANY); \
samples/bpf/spintest.bpf.c
44
bpf_map_delete_elem(&my_map2, &v); \
samples/bpf/tracex4.bpf.c
45
struct pair v = {
samples/bpf/tracex4.bpf.c
50
bpf_map_update_elem(&my_map, &ptr, &v, BPF_ANY);
samples/bpf/tracex4_user.c
32
struct pair v;
samples/bpf/tracex4_user.c
38
bpf_map_lookup_elem(fd, &next_key, &v);
samples/bpf/tracex4_user.c
40
if (val - v.val < 1000000000ll)
samples/bpf/tracex4_user.c
44
next_key, (val - v.val) / 1000000000ll, v.ip);
samples/livepatch/livepatch-sample.c
33
static int livepatch_cmdline_proc_show(struct seq_file *m, void *v)
scripts/dtc/livetree.c
390
const fdt32_t *v, *val_end = (const fdt32_t *)p->val.val + p->val.len / 4;
scripts/dtc/livetree.c
396
for (v = (const void *)p->val.val; v < val_end; v++) {
scripts/dtc/livetree.c
397
if (*v == value)
scripts/kconfig/preprocess.c
245
struct variable *v;
scripts/kconfig/preprocess.c
247
list_for_each_entry(v, &variable_list, node) {
scripts/kconfig/preprocess.c
248
if (!strcmp(name, v->name))
scripts/kconfig/preprocess.c
249
return v;
scripts/kconfig/preprocess.c
257
struct variable *v;
scripts/kconfig/preprocess.c
260
v = variable_lookup(name);
scripts/kconfig/preprocess.c
261
if (!v)
scripts/kconfig/preprocess.c
264
if (argc == 0 && v->exp_count)
scripts/kconfig/preprocess.c
268
if (v->exp_count > 1000)
scripts/kconfig/preprocess.c
271
v->exp_count++;
scripts/kconfig/preprocess.c
273
if (v->flavor == VAR_RECURSIVE)
scripts/kconfig/preprocess.c
274
res = expand_string_with_args(v->value, argc, argv);
scripts/kconfig/preprocess.c
276
res = xstrdup(v->value);
scripts/kconfig/preprocess.c
278
v->exp_count--;
scripts/kconfig/preprocess.c
286
struct variable *v;
scripts/kconfig/preprocess.c
290
v = variable_lookup(name);
scripts/kconfig/preprocess.c
291
if (v) {
scripts/kconfig/preprocess.c
294
flavor = v->flavor;
scripts/kconfig/preprocess.c
297
free(v->value);
scripts/kconfig/preprocess.c
304
v = xmalloc(sizeof(*v));
scripts/kconfig/preprocess.c
305
v->name = xstrdup(name);
scripts/kconfig/preprocess.c
306
v->exp_count = 0;
scripts/kconfig/preprocess.c
307
list_add_tail(&v->node, &variable_list);
scripts/kconfig/preprocess.c
310
v->flavor = flavor;
scripts/kconfig/preprocess.c
318
v->value = xrealloc(v->value,
scripts/kconfig/preprocess.c
319
strlen(v->value) + strlen(new_value) + 2);
scripts/kconfig/preprocess.c
320
strcat(v->value, " ");
scripts/kconfig/preprocess.c
321
strcat(v->value, new_value);
scripts/kconfig/preprocess.c
324
v->value = new_value;
scripts/kconfig/preprocess.c
328
static void variable_del(struct variable *v)
scripts/kconfig/preprocess.c
330
list_del(&v->node);
scripts/kconfig/preprocess.c
331
free(v->name);
scripts/kconfig/preprocess.c
332
free(v->value);
scripts/kconfig/preprocess.c
333
free(v);
scripts/kconfig/preprocess.c
338
struct variable *v, *tmp;
scripts/kconfig/preprocess.c
340
list_for_each_entry_safe(v, tmp, &variable_list, node)
scripts/kconfig/preprocess.c
341
variable_del(v);
scripts/kconfig/qconf.cc
1824
ConfigMainWindow* v;
scripts/kconfig/qconf.cc
1850
v = new ConfigMainWindow();
scripts/kconfig/qconf.cc
1854
v->show();
scripts/kconfig/qconf.cc
1858
delete v;
scripts/sign-file.c
69
static int pem_pw_cb(char *buf, int len, int w, void *v)
scripts/unifdef.c
746
static Linetype op_strict(int *p, int v, Linetype at, Linetype bt) {
scripts/unifdef.c
748
return (*p = v, v ? LT_TRUE : LT_FALSE);
security/apparmor/apparmorfs.c
1083
static int aa_sfs_seq_show(struct seq_file *seq, void *v)
security/apparmor/apparmorfs.c
1092
seq_printf(seq, "%s\n", str_yes_no(fs_file->v.boolean));
security/apparmor/apparmorfs.c
1095
seq_printf(seq, "%s\n", fs_file->v.string);
security/apparmor/apparmorfs.c
1098
seq_printf(seq, "%#08lx\n", fs_file->v.u64);
security/apparmor/apparmorfs.c
1162
static int seq_profile_name_show(struct seq_file *seq, void *v)
security/apparmor/apparmorfs.c
1173
static int seq_profile_mode_show(struct seq_file *seq, void *v)
security/apparmor/apparmorfs.c
1184
static int seq_profile_attach_show(struct seq_file *seq, void *v)
security/apparmor/apparmorfs.c
1200
static int seq_profile_hash_show(struct seq_file *seq, void *v)
security/apparmor/apparmorfs.c
1242
static int seq_ns_stacked_show(struct seq_file *seq, void *v)
security/apparmor/apparmorfs.c
1253
static int seq_ns_nsstacked_show(struct seq_file *seq, void *v)
security/apparmor/apparmorfs.c
1276
static int seq_ns_level_show(struct seq_file *seq, void *v)
security/apparmor/apparmorfs.c
1287
static int seq_ns_name_show(struct seq_file *seq, void *v)
security/apparmor/apparmorfs.c
1296
static int seq_ns_compress_min_show(struct seq_file *seq, void *v)
security/apparmor/apparmorfs.c
1302
static int seq_ns_compress_max_show(struct seq_file *seq, void *v)
security/apparmor/apparmorfs.c
1361
static int seq_rawdata_abi_show(struct seq_file *seq, void *v)
security/apparmor/apparmorfs.c
1370
static int seq_rawdata_revision_show(struct seq_file *seq, void *v)
security/apparmor/apparmorfs.c
1379
static int seq_rawdata_hash_show(struct seq_file *seq, void *v)
security/apparmor/apparmorfs.c
1393
static int seq_rawdata_compressed_size_show(struct seq_file *seq, void *v)
security/apparmor/apparmorfs.c
2558
for (fs_file = fs_dir->v.files; fs_file && fs_file->name; ++fs_file) {
security/apparmor/apparmorfs.c
2596
for (fs_file = fs_dir->v.files; fs_file && fs_file->name; ++fs_file) {
security/apparmor/include/apparmorfs.h
36
} v;
security/apparmor/include/apparmorfs.h
44
.v_type = AA_SFS_TYPE_BOOLEAN, .v.boolean = (_value), \
security/apparmor/include/apparmorfs.h
48
.v_type = AA_SFS_TYPE_STRING, .v.string = (_value), \
security/apparmor/include/apparmorfs.h
52
.v_type = AA_SFS_TYPE_U64, .v.u64 = (_value), \
security/apparmor/include/apparmorfs.h
58
{ .name = (_name), .v_type = AA_SFS_TYPE_DIR, .v.files = (_value) }
security/device_cgroup.c
277
static int devcgroup_seq_show(struct seq_file *m, void *v)
security/integrity/ima/ima.h
286
int ima_measurements_show(struct seq_file *m, void *v);
security/integrity/ima/ima.h
425
void *ima_policy_next(struct seq_file *m, void *v, loff_t *pos);
security/integrity/ima/ima.h
426
void ima_policy_stop(struct seq_file *m, void *v);
security/integrity/ima/ima.h
427
int ima_policy_show(struct seq_file *m, void *v);
security/integrity/ima/ima_fs.c
109
static void ima_measurements_stop(struct seq_file *m, void *v)
security/integrity/ima/ima_fs.c
127
int ima_measurements_show(struct seq_file *m, void *v)
security/integrity/ima/ima_fs.c
130
struct ima_queue_entry *qe = v;
security/integrity/ima/ima_fs.c
226
static int ima_ascii_measurements_show(struct seq_file *m, void *v)
security/integrity/ima/ima_fs.c
229
struct ima_queue_entry *qe = v;
security/integrity/ima/ima_fs.c
94
static void *ima_measurements_next(struct seq_file *m, void *v, loff_t *pos)
security/integrity/ima/ima_fs.c
96
struct ima_queue_entry *qe = v;
security/integrity/ima/ima_policy.c
2055
void *ima_policy_next(struct seq_file *m, void *v, loff_t *pos)
security/integrity/ima/ima_policy.c
2057
struct ima_rule_entry *entry = v;
security/integrity/ima/ima_policy.c
2068
void ima_policy_stop(struct seq_file *m, void *v)
security/integrity/ima/ima_policy.c
2112
int ima_policy_show(struct seq_file *m, void *v)
security/integrity/ima/ima_policy.c
2114
struct ima_rule_entry *entry = v;
security/keys/proc.c
135
static void *proc_keys_next(struct seq_file *p, void *v, loff_t *_pos)
security/keys/proc.c
139
n = key_serial_next(p, v);
security/keys/proc.c
147
static void proc_keys_stop(struct seq_file *p, void *v)
security/keys/proc.c
153
static int proc_keys_show(struct seq_file *m, void *v)
security/keys/proc.c
155
struct rb_node *_p = v;
security/keys/proc.c
17
static void *proc_keys_next(struct seq_file *p, void *v, loff_t *_pos);
security/keys/proc.c
18
static void proc_keys_stop(struct seq_file *p, void *v);
security/keys/proc.c
19
static int proc_keys_show(struct seq_file *m, void *v);
security/keys/proc.c
29
static void *proc_key_users_next(struct seq_file *p, void *v, loff_t *_pos);
security/keys/proc.c
291
static void *proc_key_users_next(struct seq_file *p, void *v, loff_t *_pos)
security/keys/proc.c
294
return key_user_next(seq_user_ns(p), (struct rb_node *)v);
security/keys/proc.c
297
static void proc_key_users_stop(struct seq_file *p, void *v)
security/keys/proc.c
30
static void proc_key_users_stop(struct seq_file *p, void *v);
security/keys/proc.c
303
static int proc_key_users_show(struct seq_file *m, void *v)
security/keys/proc.c
305
struct rb_node *_p = v;
security/keys/proc.c
31
static int proc_key_users_show(struct seq_file *m, void *v);
security/keys/trusted-keys/trusted_tpm2.c
139
const u8 *v = value;
security/keys/trusted-keys/trusted_tpm2.c
145
ctx->parent |= v[i];
security/selinux/include/hash.h
23
u32 v = input; \
security/selinux/include/hash.h
24
v *= c1; \
security/selinux/include/hash.h
25
v = (v << r1) | (v >> (32 - r1)); \
security/selinux/include/hash.h
26
v *= c2; \
security/selinux/include/hash.h
27
hash ^= v; \
security/selinux/selinuxfs.c
1558
static void *sel_avc_stats_seq_next(struct seq_file *seq, void *v, loff_t *pos)
security/selinux/selinuxfs.c
1563
static int sel_avc_stats_seq_show(struct seq_file *seq, void *v)
security/selinux/selinuxfs.c
1565
struct avc_cache_stats *st = v;
security/selinux/selinuxfs.c
1567
if (v == SEQ_START_TOKEN) {
security/selinux/selinuxfs.c
1581
static void sel_avc_stats_seq_stop(struct seq_file *seq, void *v)
security/selinux/ss/policydb.c
2206
newc->v.sclass = le32_to_cpu(buf[0]);
security/selinux/ss/policydb.c
2215
(!c->v.sclass || !newc->v.sclass ||
security/selinux/ss/policydb.c
2216
newc->v.sclass == c->v.sclass)) {
security/selinux/ss/policydb.c
2340
c->v.behavior = le32_to_cpu(buf[0]);
security/selinux/ss/policydb.c
2342
if (c->v.behavior == SECURITY_FS_USE_MNTPOINT)
security/selinux/ss/policydb.c
2344
if (c->v.behavior > SECURITY_FS_USE_MAX)
security/selinux/ss/policydb.c
3374
buf[0] = cpu_to_le32(c->v.behavior);
security/selinux/ss/policydb.c
3483
buf[0] = cpu_to_le32(c->v.sclass);
security/selinux/ss/policydb.c
430
int v;
security/selinux/ss/policydb.c
432
v = ft1->ttype - ft2->ttype;
security/selinux/ss/policydb.c
433
if (v)
security/selinux/ss/policydb.c
434
return v;
security/selinux/ss/policydb.c
436
v = ft1->tclass - ft2->tclass;
security/selinux/ss/policydb.c
437
if (v)
security/selinux/ss/policydb.c
438
return v;
security/selinux/ss/policydb.c
465
int v;
security/selinux/ss/policydb.c
467
v = key1->source_type - key2->source_type;
security/selinux/ss/policydb.c
468
if (v)
security/selinux/ss/policydb.c
469
return v;
security/selinux/ss/policydb.c
471
v = key1->target_type - key2->target_type;
security/selinux/ss/policydb.c
472
if (v)
security/selinux/ss/policydb.c
473
return v;
security/selinux/ss/policydb.c
475
v = key1->target_class - key2->target_class;
security/selinux/ss/policydb.c
477
return v;
security/selinux/ss/policydb.c
502
int v;
security/selinux/ss/policydb.c
504
v = key1->role - key2->role;
security/selinux/ss/policydb.c
505
if (v)
security/selinux/ss/policydb.c
506
return v;
security/selinux/ss/policydb.c
508
v = key1->type - key2->type;
security/selinux/ss/policydb.c
509
if (v)
security/selinux/ss/policydb.c
510
return v;
security/selinux/ss/policydb.h
200
} v;
security/selinux/ss/services.c
2921
if (!c->v.sclass || sclass == c->v.sclass) {
security/selinux/ss/services.c
3017
sbsec->behavior = c->v.behavior;
security/smack/smackfs.c
1054
static void *net4addr_seq_next(struct seq_file *s, void *v, loff_t *pos)
security/smack/smackfs.c
1056
return smk_seq_next(s, v, pos, &smk_net4addr_list);
security/smack/smackfs.c
1062
static int net4addr_seq_show(struct seq_file *s, void *v)
security/smack/smackfs.c
1064
struct list_head *list = v;
security/smack/smackfs.c
1318
static void *net6addr_seq_next(struct seq_file *s, void *v, loff_t *pos)
security/smack/smackfs.c
1320
return smk_seq_next(s, v, pos, &smk_net6addr_list);
security/smack/smackfs.c
1326
static int net6addr_seq_show(struct seq_file *s, void *v)
security/smack/smackfs.c
1328
struct list_head *list = v;
security/smack/smackfs.c
1884
static void *onlycap_seq_next(struct seq_file *s, void *v, loff_t *pos)
security/smack/smackfs.c
1886
return smk_seq_next(s, v, pos, &smack_onlycap_list);
security/smack/smackfs.c
1889
static int onlycap_seq_show(struct seq_file *s, void *v)
security/smack/smackfs.c
1891
struct list_head *list = v;
security/smack/smackfs.c
2224
static void *load_self_seq_next(struct seq_file *s, void *v, loff_t *pos)
security/smack/smackfs.c
2228
return smk_seq_next(s, v, pos, &tsp->smk_rules);
security/smack/smackfs.c
2231
static int load_self_seq_show(struct seq_file *s, void *v)
security/smack/smackfs.c
2233
struct list_head *list = v;
security/smack/smackfs.c
2361
static int load2_seq_show(struct seq_file *s, void *v)
security/smack/smackfs.c
2363
struct list_head *list = v;
security/smack/smackfs.c
2433
static void *load_self2_seq_next(struct seq_file *s, void *v, loff_t *pos)
security/smack/smackfs.c
2437
return smk_seq_next(s, v, pos, &tsp->smk_rules);
security/smack/smackfs.c
2440
static int load_self2_seq_show(struct seq_file *s, void *v)
security/smack/smackfs.c
2442
struct list_head *list = v;
security/smack/smackfs.c
2704
static void *relabel_self_seq_next(struct seq_file *s, void *v, loff_t *pos)
security/smack/smackfs.c
2708
return smk_seq_next(s, v, pos, &tsp->smk_relabel);
security/smack/smackfs.c
2711
static int relabel_self_seq_show(struct seq_file *s, void *v)
security/smack/smackfs.c
2713
struct list_head *list = v;
security/smack/smackfs.c
550
static void *smk_seq_next(struct seq_file *s, void *v, loff_t *pos,
security/smack/smackfs.c
553
struct list_head *list = v;
security/smack/smackfs.c
561
static void smk_seq_stop(struct seq_file *s, void *v)
security/smack/smackfs.c
598
static void *load2_seq_next(struct seq_file *s, void *v, loff_t *pos)
security/smack/smackfs.c
600
return smk_seq_next(s, v, pos, &smack_known_list);
security/smack/smackfs.c
603
static int load_seq_show(struct seq_file *s, void *v)
security/smack/smackfs.c
605
struct list_head *list = v;
security/smack/smackfs.c
759
static void *cipso_seq_next(struct seq_file *s, void *v, loff_t *pos)
security/smack/smackfs.c
761
return smk_seq_next(s, v, pos, &smack_known_list);
security/smack/smackfs.c
768
static int cipso_seq_show(struct seq_file *s, void *v)
security/smack/smackfs.c
770
struct list_head *list = v;
security/smack/smackfs.c
979
static int cipso2_seq_show(struct seq_file *s, void *v)
security/smack/smackfs.c
981
struct list_head *list = v;
security/tomoyo/util.c
277
unsigned long v;
security/tomoyo/util.c
286
type = tomoyo_parse_ulong(&v, &data);
security/tomoyo/util.c
289
ptr->values[0] = v;
security/tomoyo/util.c
292
ptr->values[1] = v;
security/tomoyo/util.c
298
type = tomoyo_parse_ulong(&v, &data);
security/tomoyo/util.c
299
if (type == TOMOYO_VALUE_TYPE_INVALID || *data || ptr->values[0] > v)
security/tomoyo/util.c
301
ptr->values[1] = v;
sound/aoa/codecs/onyx.c
210
u8 v, n;
sound/aoa/codecs/onyx.c
216
onyx_read_register(onyx, ONYX_REG_ADC_CONTROL, &v);
sound/aoa/codecs/onyx.c
217
n = v;
sound/aoa/codecs/onyx.c
223
return n != v;
sound/aoa/codecs/onyx.c
247
s8 v;
sound/aoa/codecs/onyx.c
250
onyx_read_register(onyx, ONYX_REG_ADC_CONTROL, &v);
sound/aoa/codecs/onyx.c
252
ucontrol->value.enumerated.item[0] = !!(v&ONYX_ADC_INPUT_MIC);
sound/aoa/codecs/onyx.c
259
s8 v;
sound/aoa/codecs/onyx.c
262
onyx_read_register(onyx, ONYX_REG_ADC_CONTROL, &v);
sound/aoa/codecs/onyx.c
263
v &= ~ONYX_ADC_INPUT_MIC;
sound/aoa/codecs/onyx.c
265
v |= ONYX_ADC_INPUT_MIC;
sound/aoa/codecs/onyx.c
266
onyx_write_register(onyx, ONYX_REG_ADC_CONTROL, v);
sound/aoa/codecs/onyx.c
320
u8 v = 0, c = 0;
sound/aoa/codecs/onyx.c
327
onyx_read_register(onyx, ONYX_REG_DAC_CONTROL, &v);
sound/aoa/codecs/onyx.c
328
c = v;
sound/aoa/codecs/onyx.c
336
return !err ? (v != c) : err;
sound/aoa/codecs/onyx.c
376
u8 v = 0, c = 0;
sound/aoa/codecs/onyx.c
389
onyx_read_register(onyx, address, &v);
sound/aoa/codecs/onyx.c
390
c = v;
sound/aoa/codecs/onyx.c
396
return !err ? (v != c) : err;
sound/aoa/codecs/onyx.c
474
u8 v;
sound/aoa/codecs/onyx.c
477
onyx_read_register(onyx, ONYX_REG_DIG_INFO1, &v);
sound/aoa/codecs/onyx.c
478
ucontrol->value.iec958.status[0] = v & 0x3e;
sound/aoa/codecs/onyx.c
480
onyx_read_register(onyx, ONYX_REG_DIG_INFO2, &v);
sound/aoa/codecs/onyx.c
481
ucontrol->value.iec958.status[1] = v;
sound/aoa/codecs/onyx.c
483
onyx_read_register(onyx, ONYX_REG_DIG_INFO3, &v);
sound/aoa/codecs/onyx.c
484
ucontrol->value.iec958.status[3] = v & 0x3f;
sound/aoa/codecs/onyx.c
486
onyx_read_register(onyx, ONYX_REG_DIG_INFO4, &v);
sound/aoa/codecs/onyx.c
487
ucontrol->value.iec958.status[4] = v & 0x0f;
sound/aoa/codecs/onyx.c
496
u8 v;
sound/aoa/codecs/onyx.c
499
onyx_read_register(onyx, ONYX_REG_DIG_INFO1, &v);
sound/aoa/codecs/onyx.c
500
v = (v & ~0x3e) | (ucontrol->value.iec958.status[0] & 0x3e);
sound/aoa/codecs/onyx.c
501
onyx_write_register(onyx, ONYX_REG_DIG_INFO1, v);
sound/aoa/codecs/onyx.c
503
v = ucontrol->value.iec958.status[1];
sound/aoa/codecs/onyx.c
504
onyx_write_register(onyx, ONYX_REG_DIG_INFO2, v);
sound/aoa/codecs/onyx.c
506
onyx_read_register(onyx, ONYX_REG_DIG_INFO3, &v);
sound/aoa/codecs/onyx.c
507
v = (v & ~0x3f) | (ucontrol->value.iec958.status[3] & 0x3f);
sound/aoa/codecs/onyx.c
508
onyx_write_register(onyx, ONYX_REG_DIG_INFO3, v);
sound/aoa/codecs/onyx.c
510
onyx_read_register(onyx, ONYX_REG_DIG_INFO4, &v);
sound/aoa/codecs/onyx.c
511
v = (v & ~0x0f) | (ucontrol->value.iec958.status[4] & 0x0f);
sound/aoa/codecs/onyx.c
512
onyx_write_register(onyx, ONYX_REG_DIG_INFO4, v);
sound/aoa/codecs/onyx.c
653
u8 v;
sound/aoa/codecs/onyx.c
658
onyx_read_register(onyx, ONYX_REG_DIG_INFO4, &v);
sound/aoa/codecs/onyx.c
659
spdif_enabled = !!(v & ONYX_SPDIF_ENABLE);
sound/aoa/codecs/onyx.c
660
onyx_read_register(onyx, ONYX_REG_DAC_CONTROL, &v);
sound/aoa/codecs/onyx.c
662
(v & (ONYX_MUTE_RIGHT|ONYX_MUTE_LEFT))
sound/aoa/codecs/onyx.c
677
u8 v;
sound/aoa/codecs/onyx.c
68
s32 v;
sound/aoa/codecs/onyx.c
685
onyx_read_register(onyx, ONYX_REG_DAC_CONTROL, &v);
sound/aoa/codecs/onyx.c
688
v | ONYX_MUTE_RIGHT | ONYX_MUTE_LEFT))
sound/aoa/codecs/onyx.c
705
onyx_read_register(cii->codec_data, ONYX_REG_DIG_INFO4, &v);
sound/aoa/codecs/onyx.c
708
v & ~ONYX_SPDIF_ENABLE))
sound/aoa/codecs/onyx.c
74
v = i2c_smbus_read_byte_data(onyx->i2c, reg);
sound/aoa/codecs/onyx.c
75
if (v < 0) {
sound/aoa/codecs/onyx.c
767
u8 v;
sound/aoa/codecs/onyx.c
770
if (onyx_read_register(onyx, ONYX_REG_CONTROL, &v))
sound/aoa/codecs/onyx.c
772
onyx_write_register(onyx, ONYX_REG_CONTROL, v | ONYX_ADPSV | ONYX_DAPSV);
sound/aoa/codecs/onyx.c
780
u8 v;
sound/aoa/codecs/onyx.c
79
*value = (u8)v;
sound/aoa/codecs/onyx.c
793
if (onyx_read_register(onyx, ONYX_REG_CONTROL, &v))
sound/aoa/codecs/onyx.c
795
onyx_write_register(onyx, ONYX_REG_CONTROL, v & ~(ONYX_ADPSV | ONYX_DAPSV));
sound/aoa/codecs/onyx.c
826
u8 v;
sound/aoa/codecs/onyx.c
928
onyx_read_register(onyx, ONYX_REG_DIG_INFO4, &v);
sound/aoa/codecs/onyx.c
929
v |= ONYX_SPDIF_ENABLE;
sound/aoa/codecs/onyx.c
930
onyx_write_register(onyx, ONYX_REG_DIG_INFO4, v);
sound/aoa/core/gpio-feature.c
127
#define SWITCH_GPIO(name, v, on) \
sound/aoa/core/gpio-feature.c
128
(((v)&~1) | ((on)? \
sound/aoa/core/gpio-feature.c
135
int v; \
sound/aoa/core/gpio-feature.c
142
v = pmac_call_feature(PMAC_FTR_READ_GPIO, NULL, \
sound/aoa/core/gpio-feature.c
147
v = SWITCH_GPIO(name##_mute, v, !on); \
sound/aoa/core/gpio-feature.c
150
name##_mute_gpio, v); \
sound/aoa/core/gpio-feature.c
168
int v;
sound/aoa/core/gpio-feature.c
174
v = pmac_call_feature(PMAC_FTR_READ_GPIO, NULL,
sound/aoa/core/gpio-feature.c
176
v = SWITCH_GPIO(hw_reset, v, on);
sound/aoa/core/gpio-feature.c
178
hw_reset_gpio, v);
sound/aoa/core/gpio-feature.c
222
int v;
sound/aoa/core/gpio-feature.c
226
v = pmac_call_feature(PMAC_FTR_READ_GPIO, NULL, gpio, 0);
sound/aoa/core/gpio-feature.c
227
v |= 0x80; /* enable dual edge */
sound/aoa/core/gpio-feature.c
228
pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, gpio, v);
sound/aoa/core/gpio-pmf.c
16
struct pmf_args args = { .count = 1, .u[0].v = !on }; \
sound/aoa/core/gpio-pmf.c
39
struct pmf_args args = { .count = 1, .u[0].v = !!on };
sound/aoa/fabrics/layout.c
733
int v;
sound/aoa/fabrics/layout.c
737
v = ldev->gpio.methods->get_detect(&ldev->gpio,
sound/aoa/fabrics/layout.c
741
v = ldev->gpio.methods->get_detect(&ldev->gpio,
sound/aoa/fabrics/layout.c
747
ucontrol->value.integer.value[0] = v;
sound/aoa/fabrics/layout.c
855
int v, update;
sound/aoa/fabrics/layout.c
861
v = ldev->gpio.methods->get_detect(&ldev->gpio, AOA_NOTIFY_HEADPHONE);
sound/aoa/fabrics/layout.c
865
ldev->gpio.methods->set_speakers(&ldev->gpio, !v);
sound/aoa/fabrics/layout.c
866
ldev->gpio.methods->set_headphone(&ldev->gpio, v);
sound/aoa/fabrics/layout.c
870
v = ldev->gpio.methods->get_detect(&ldev->gpio, AOA_NOTIFY_LINE_OUT);
sound/aoa/fabrics/layout.c
874
ldev->gpio.methods->set_speakers(&ldev->gpio, !v);
sound/aoa/fabrics/layout.c
876
ldev->gpio.methods->set_lineout(&ldev->gpio, v);
sound/aoa/soundbus/i2sbus/pcm.c
103
v = *ti;
sound/aoa/soundbus/i2sbus/pcm.c
105
&& cii->codec->usable(cii, ti, &v)) {
sound/aoa/soundbus/i2sbus/pcm.c
107
formats &= v.formats;
sound/aoa/soundbus/i2sbus/pcm.c
108
rates &= v.rates;
sound/aoa/soundbus/i2sbus/pcm.c
110
formats = v.formats;
sound/aoa/soundbus/i2sbus/pcm.c
111
rates = v.rates;
sound/aoa/soundbus/i2sbus/pcm.c
81
struct transfer_info v;
sound/arm/aaci.c
109
u32 v;
sound/arm/aaci.c
130
v = readl(aaci->base + AACI_SLFR);
sound/arm/aaci.c
131
} while ((v & SLFR_1TXB) && --timeout);
sound/arm/aaci.c
133
if (v & SLFR_1TXB) {
sound/arm/aaci.c
146
v = readl(aaci->base + AACI_SLFR) & (SLFR_1RXV|SLFR_2RXV);
sound/arm/aaci.c
147
} while ((v != (SLFR_1RXV|SLFR_2RXV)) && --timeout);
sound/arm/aaci.c
149
if (v != (SLFR_1RXV|SLFR_2RXV)) {
sound/arm/aaci.c
155
v = readl(aaci->base + AACI_SL1RX) >> 12;
sound/arm/aaci.c
156
if (v == reg) {
sound/arm/aaci.c
157
v = readl(aaci->base + AACI_SL2RX) >> 4;
sound/arm/aaci.c
166
v, reg);
sound/arm/aaci.c
167
v = ~0;
sound/arm/aaci.c
170
return v;
sound/arm/aaci.c
39
u32 v, maincr = aaci->maincr | MAINCR_SCRA(ac97->num);
sound/arm/aaci.c
44
v = readl(aaci->base + AACI_SLFR);
sound/arm/aaci.c
45
if (v & SLFR_2RXV)
sound/arm/aaci.c
47
if (v & SLFR_1RXV)
sound/arm/aaci.c
71
u32 v;
sound/arm/aaci.c
94
v = readl(aaci->base + AACI_SLFR);
sound/arm/aaci.c
95
} while ((v & (SLFR_1TXB|SLFR_2TXB)) && --timeout);
sound/arm/aaci.c
97
if (v & (SLFR_1TXB|SLFR_2TXB))
sound/core/oss/io.c
81
struct snd_pcm_plugin_channel *v;
sound/core/oss/io.c
82
err = snd_pcm_plugin_client_channels(plugin, frames, &v);
sound/core/oss/io.c
85
*channels = v;
sound/core/oss/io.c
87
for (channel = 0; channel < plugin->src_format.channels; ++channel, ++v)
sound/core/oss/io.c
88
v->wanted = 1;
sound/core/oss/pcm_oss.c
380
int v;
sound/core/oss/pcm_oss.c
434
v = snd_pcm_hw_param_last(pcm, params, var, dir);
sound/core/oss/pcm_oss.c
436
v = snd_pcm_hw_param_first(pcm, params, var, dir);
sound/core/oss/pcm_oss.c
437
return v;
sound/core/oss/pcm_plugin.c
548
struct snd_pcm_plugin_channel *v;
sound/core/oss/pcm_plugin.c
562
v = plugin->buf_channels;
sound/core/oss/pcm_plugin.c
563
*channels = v;
sound/core/oss/pcm_plugin.c
571
for (channel = 0; channel < nchannels; channel++, v++) {
sound/core/oss/pcm_plugin.c
572
v->frames = count;
sound/core/oss/pcm_plugin.c
573
v->enabled = 1;
sound/core/oss/pcm_plugin.c
574
v->wanted = (stream == SNDRV_PCM_STREAM_CAPTURE);
sound/core/oss/pcm_plugin.c
575
v->area.addr = buf;
sound/core/oss/pcm_plugin.c
576
v->area.first = channel * width;
sound/core/oss/pcm_plugin.c
577
v->area.step = nchannels * width;
sound/core/pcm.c
150
#define FORMAT(v) [SNDRV_PCM_FORMAT_##v] = #v
sound/core/pcm.c
224
#define STATE(v) [SNDRV_PCM_STATE_##v] = #v
sound/core/pcm.c
225
#define STREAM(v) [SNDRV_PCM_STREAM_##v] = #v
sound/core/pcm.c
226
#define READY(v) [SNDRV_PCM_READY_##v] = #v
sound/core/pcm.c
227
#define XRUN(v) [SNDRV_PCM_XRUN_##v] = #v
sound/core/pcm.c
228
#define SILENCE(v) [SNDRV_PCM_SILENCE_##v] = #v
sound/core/pcm.c
229
#define TSTAMP(v) [SNDRV_PCM_TSTAMP_##v] = #v
sound/core/pcm.c
230
#define ACCESS(v) [SNDRV_PCM_ACCESS_##v] = #v
sound/core/pcm.c
231
#define START(v) [SNDRV_PCM_START_##v] = #v
sound/core/pcm.c
232
#define SUBFORMAT(v) [SNDRV_PCM_SUBFORMAT_##v] = #v
sound/core/pcm_lib.c
626
int snd_interval_refine(struct snd_interval *i, const struct snd_interval *v)
sound/core/pcm_lib.c
631
if (i->min < v->min) {
sound/core/pcm_lib.c
632
i->min = v->min;
sound/core/pcm_lib.c
633
i->openmin = v->openmin;
sound/core/pcm_lib.c
635
} else if (i->min == v->min && !i->openmin && v->openmin) {
sound/core/pcm_lib.c
639
if (i->max > v->max) {
sound/core/pcm_lib.c
640
i->max = v->max;
sound/core/pcm_lib.c
641
i->openmax = v->openmax;
sound/core/pcm_lib.c
643
} else if (i->max == v->max && !i->openmax && v->openmax) {
sound/core/pcm_lib.c
647
if (!i->integer && v->integer) {
sound/core/pcm_native.c
676
const int *v;
sound/core/pcm_native.c
681
for (v = vars; *v != -1; v++) {
sound/core/pcm_native.c
684
if (hw_is_mask(*v))
sound/core/pcm_native.c
685
old_mask = *hw_param_mask(params, *v);
sound/core/pcm_native.c
688
if (hw_is_interval(*v))
sound/core/pcm_native.c
689
old_interval = *hw_param_interval(params, *v);
sound/core/pcm_native.c
691
if (*v != SNDRV_PCM_HW_PARAM_BUFFER_SIZE)
sound/core/pcm_native.c
692
changed = snd_pcm_hw_param_first(pcm, params, *v, NULL);
sound/core/pcm_native.c
694
changed = snd_pcm_hw_param_last(pcm, params, *v, NULL);
sound/core/pcm_native.c
701
if (hw_is_mask(*v)) {
sound/core/pcm_native.c
702
trace_hw_mask_param(pcm, *v, 0, &old_mask,
sound/core/pcm_native.c
703
hw_param_mask(params, *v));
sound/core/pcm_native.c
705
if (hw_is_interval(*v)) {
sound/core/pcm_native.c
706
trace_hw_interval_param(pcm, *v, 0, &old_interval,
sound/core/pcm_native.c
707
hw_param_interval(params, *v));
sound/core/seq/oss/seq_oss_event.c
177
if (q->v.chn >= 32)
sound/core/seq/oss/seq_oss_event.c
179
switch (q->v.cmd) {
sound/core/seq/oss/seq_oss_event.c
181
return note_on_event(dp, q->v.dev, q->v.chn, q->v.note, q->v.parm, ev);
sound/core/seq/oss/seq_oss_event.c
184
return note_off_event(dp, q->v.dev, q->v.chn, q->v.note, q->v.parm, ev);
sound/core/seq/oss/seq_oss_event.c
187
return set_note_event(dp, q->v.dev, SNDRV_SEQ_EVENT_KEYPRESS,
sound/core/seq/oss/seq_oss_event.c
188
q->v.chn, q->v.note, q->v.parm, ev);
sound/core/seq/oss/seq_oss_event.h
83
struct evrec_voice v;
sound/core/seq/oss/seq_oss_midi.c
516
ossev.v.cmd = MIDI_NOTEON; break;
sound/core/seq/oss/seq_oss_midi.c
518
ossev.v.cmd = MIDI_NOTEOFF; break;
sound/core/seq/oss/seq_oss_midi.c
520
ossev.v.cmd = MIDI_KEY_PRESSURE; break;
sound/core/seq/oss/seq_oss_midi.c
533
ossev.v.dev = dev;
sound/core/seq/oss/seq_oss_midi.c
539
ossev.v.code = EV_CHN_VOICE;
sound/core/seq/oss/seq_oss_midi.c
540
ossev.v.note = ev->data.note.note;
sound/core/seq/oss/seq_oss_midi.c
541
ossev.v.parm = ev->data.note.velocity;
sound/core/seq/oss/seq_oss_midi.c
542
ossev.v.chn = ev->data.note.channel;
sound/core/seq/seq_prioq.c
299
struct prioq_match_arg *v = arg;
sound/core/seq/seq_prioq.c
301
if (cell->event.source.client == v->client ||
sound/core/seq/seq_prioq.c
302
cell->event.dest.client == v->client)
sound/core/seq/seq_prioq.c
304
if (!v->timestamp)
sound/core/seq/seq_prioq.c
335
struct prioq_remove_match_arg *v = arg;
sound/core/seq/seq_prioq.c
337
struct snd_seq_remove_events *info = v->info;
sound/core/seq/seq_prioq.c
340
if (ev->source.client != v->client)
sound/core/seq/seq_ump_convert.c
442
u16 v;
sound/core/seq/seq_ump_convert.c
490
v = downscale_32_to_14bit(midi2->pb.data);
sound/core/seq/seq_ump_convert.c
491
midi1->pb.data_msb = v >> 7;
sound/core/seq/seq_ump_convert.c
492
midi1->pb.data_lsb = v & 0x7f;
sound/core/ump_convert.c
107
u16 v;
sound/core/ump_convert.c
144
v = downscale_32_to_14bit(midi2->pb.data);
sound/core/ump_convert.c
145
buf[1] = v & 0x7f;
sound/core/ump_convert.c
146
buf[2] = v >> 7;
sound/core/ump_convert.c
158
v = downscale_32_to_14bit(midi2->rpn.data);
sound/core/ump_convert.c
159
buf[8] = v >> 7;
sound/core/ump_convert.c
162
buf[11] = v & 0x7f;
sound/firewire/oxfw/oxfw.c
100
v = info->vendor_name;
sound/firewire/oxfw/oxfw.c
104
v = vendor;
sound/firewire/oxfw/oxfw.c
114
v, m, firmware >> 20, firmware & 0xffff,
sound/firewire/oxfw/oxfw.c
71
const char *d, *v, *m;
sound/hda/codecs/analog.c
1000
.v.func = ad1884_fixup_amp_override,
sound/hda/codecs/analog.c
1004
.v.func = ad1884_fixup_hp_eapd,
sound/hda/codecs/analog.c
1010
.v.verbs = ad1884_dmic_init_verbs,
sound/hda/codecs/analog.c
1014
.v.func = ad1884_fixup_thinkpad,
sound/hda/codecs/analog.c
1020
.v.verbs = ad1884_dmic_init_verbs,
sound/hda/codecs/analog.c
260
.v.func = ad_fixup_inv_jack_detect,
sound/hda/codecs/analog.c
264
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/analog.c
272
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/analog.c
282
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/analog.c
295
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/analog.c
308
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/analog.c
317
.v.func = ad1986a_fixup_eapd,
sound/hda/codecs/analog.c
321
.v.func = ad1986a_fixup_eapd_mix_in,
sound/hda/codecs/analog.c
325
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/analog.c
562
.v.func = ad1981_fixup_amp_override,
sound/hda/codecs/analog.c
566
.v.func = ad1981_fixup_hp_eapd,
sound/hda/codecs/analog.c
843
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/cirrus/cs420x.c
474
.v.pins = mbp53_pincfgs,
sound/hda/codecs/cirrus/cs420x.c
480
.v.pins = mbp55_pincfgs,
sound/hda/codecs/cirrus/cs420x.c
486
.v.pins = imac27_pincfgs,
sound/hda/codecs/cirrus/cs420x.c
492
.v.func = cs420x_fixup_gpio_13,
sound/hda/codecs/cirrus/cs420x.c
496
.v.func = cs420x_fixup_gpio_23,
sound/hda/codecs/cirrus/cs420x.c
500
.v.pins = mbp101_pincfgs,
sound/hda/codecs/cirrus/cs420x.c
506
.v.verbs = (const struct hda_verb[]) {
sound/hda/codecs/cirrus/cs420x.c
517
.v.pins = mba42_pincfgs,
sound/hda/codecs/cirrus/cs420x.c
673
.v.pins = mba6_pincfgs,
sound/hda/codecs/cirrus/cs420x.c
679
.v.func = cs4208_fixup_spdif_switch,
sound/hda/codecs/cirrus/cs420x.c
685
.v.func = cs4208_fixup_macmini,
sound/hda/codecs/cirrus/cs420x.c
691
.v.func = cs4208_fixup_gpio0,
sound/hda/codecs/cirrus/cs420x.c
695
.v.func = cs4208_fixup_mac,
sound/hda/codecs/cirrus/cs421x.c
233
.v.pins = cdb4210_pincfgs,
sound/hda/codecs/cirrus/cs421x.c
239
.v.func = cs421x_fixup_sense_b,
sound/hda/codecs/cirrus/cs421x.c
243
.v.pins = stumpy_pincfgs,
sound/hda/codecs/cirrus/cs8409-tables.c
639
.v.pins = cs8409_cs42l42_pincfgs,
sound/hda/codecs/cirrus/cs8409-tables.c
645
.v.pins = cs8409_cs42l42_pincfgs,
sound/hda/codecs/cirrus/cs8409-tables.c
651
.v.pins = cs8409_cs42l42_pincfgs,
sound/hda/codecs/cirrus/cs8409-tables.c
657
.v.pins = cs8409_cs42l42_pincfgs,
sound/hda/codecs/cirrus/cs8409-tables.c
663
.v.pins = cs8409_cs42l42_pincfgs,
sound/hda/codecs/cirrus/cs8409-tables.c
669
.v.func = cs8409_cs42l42_fixups,
sound/hda/codecs/cirrus/cs8409-tables.c
673
.v.pins = dolphin_pincfgs,
sound/hda/codecs/cirrus/cs8409-tables.c
679
.v.func = dolphin_fixups,
sound/hda/codecs/cirrus/cs8409-tables.c
683
.v.pins = cs8409_cs42l42_pincfgs_no_dmic,
sound/hda/codecs/cirrus/cs8409-tables.c
689
.v.pins = cs8409_cdb35l56_four_pincfgs,
sound/hda/codecs/cirrus/cs8409-tables.c
695
.v.func = cs8409_cdb35l56_four_autodet_fixup,
sound/hda/codecs/conexant.c
1002
.v.func = cxt_fixup_headset_mic,
sound/hda/codecs/conexant.c
1006
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/conexant.c
1015
.v.pins = cxt_pincfg_sws_js201d,
sound/hda/codecs/conexant.c
1019
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/conexant.c
1026
.v.func = cxt_fixup_hp_a_u,
sound/hda/codecs/conexant.c
1030
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/conexant.c
851
.v.pins = cxt_pincfg_lenovo_x200,
sound/hda/codecs/conexant.c
855
.v.pins = cxt_pincfg_lenovo_tp410,
sound/hda/codecs/conexant.c
863
.v.pins = cxt_pincfg_lemote,
sound/hda/codecs/conexant.c
867
.v.pins = cxt_pincfg_lemote,
sound/hda/codecs/conexant.c
871
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/conexant.c
880
.v.func = cxt_fixup_stereo_dmic,
sound/hda/codecs/conexant.c
884
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/conexant.c
892
.v.func = cxt5066_increase_mic_boost,
sound/hda/codecs/conexant.c
898
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/conexant.c
905
.v.func = cxt_fixup_headphone_mic,
sound/hda/codecs/conexant.c
909
.v.verbs = (const struct hda_verb[]) {
sound/hda/codecs/conexant.c
918
.v.func = cxt_fixup_stereo_dmic,
sound/hda/codecs/conexant.c
924
.v.func = hda_fixup_thinkpad_acpi,
sound/hda/codecs/conexant.c
928
.v.func = hda_fixup_ideapad_acpi,
sound/hda/codecs/conexant.c
934
.v.func = cxt_fixup_olpc_xo,
sound/hda/codecs/conexant.c
938
.v.func = cxt_fixup_cap_mix_amp,
sound/hda/codecs/conexant.c
942
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/conexant.c
951
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/conexant.c
960
.v.func = cxt_fixup_cap_mix_amp_5047,
sound/hda/codecs/conexant.c
964
.v.func = cxt_fixup_mute_led_eapd,
sound/hda/codecs/conexant.c
968
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/conexant.c
978
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/conexant.c
986
.v.func = cxt_fixup_hp_gate_mic_jack,
sound/hda/codecs/conexant.c
990
.v.func = cxt_fixup_mute_led_gpio,
sound/hda/codecs/conexant.c
994
.v.func = cxt_fixup_update_pinctl,
sound/hda/codecs/conexant.c
998
.v.func = cxt_fixup_hp_zbook_mute_led,
sound/hda/codecs/realtek/alc260.c
108
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc260.c
115
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc260.c
122
.v.verbs = (const struct hda_verb[]) {
sound/hda/codecs/realtek/alc260.c
130
.v.func = alc_fixup_gpio1,
sound/hda/codecs/realtek/alc260.c
134
.v.func = alc260_fixup_gpio1_toggle,
sound/hda/codecs/realtek/alc260.c
140
.v.verbs = (const struct hda_verb[]) {
sound/hda/codecs/realtek/alc260.c
150
.v.func = alc260_fixup_gpio1_toggle,
sound/hda/codecs/realtek/alc260.c
156
.v.func = alc260_fixup_kn1,
sound/hda/codecs/realtek/alc260.c
160
.v.func = alc260_fixup_fsc_s7020,
sound/hda/codecs/realtek/alc260.c
164
.v.func = alc260_fixup_fsc_s7020_jwse,
sound/hda/codecs/realtek/alc260.c
170
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc262.c
35
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc262.c
44
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc262.c
53
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc262.c
60
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc262.c
67
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc262.c
76
.v.verbs = (const struct hda_verb[]) {
sound/hda/codecs/realtek/alc262.c
84
.v.verbs = (const struct hda_verb[]) {
sound/hda/codecs/realtek/alc262.c
92
.v.func = alc_fixup_inv_dmic,
sound/hda/codecs/realtek/alc262.c
96
.v.func = alc_fixup_no_depop_delay,
sound/hda/codecs/realtek/alc268.c
57
.v.func = alc_fixup_inv_dmic,
sound/hda/codecs/realtek/alc268.c
61
.v.verbs = (const struct hda_verb[]) {
sound/hda/codecs/realtek/alc268.c
68
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
4166
.v.func = alc_fixup_gpio2,
sound/hda/codecs/realtek/alc269.c
4170
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
4177
.v.func = alc275_fixup_gpio4_off,
sound/hda/codecs/realtek/alc269.c
4183
.v.verbs = (const struct hda_verb[]) {
sound/hda/codecs/realtek/alc269.c
4192
.v.func = alc_fixup_sku_ignore,
sound/hda/codecs/realtek/alc269.c
4196
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
4203
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
4212
.v.verbs = (const struct hda_verb[]) {
sound/hda/codecs/realtek/alc269.c
4226
.v.verbs = (const struct hda_verb[]) {
sound/hda/codecs/realtek/alc269.c
4233
.v.func = alc269_fixup_hweq,
sound/hda/codecs/realtek/alc269.c
4239
.v.func = alc_fixup_disable_aamix,
sound/hda/codecs/realtek/alc269.c
4245
.v.func = alc271_fixup_dmic,
sound/hda/codecs/realtek/alc269.c
4249
.v.func = alc269_fixup_pcm_44k,
sound/hda/codecs/realtek/alc269.c
4255
.v.func = alc269_fixup_stereo_dmic,
sound/hda/codecs/realtek/alc269.c
4259
.v.func = alc_fixup_headset_mic,
sound/hda/codecs/realtek/alc269.c
4263
.v.func = alc269_fixup_quanta_mute,
sound/hda/codecs/realtek/alc269.c
4267
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
4277
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
4284
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
4291
.v.func = alc269_fixup_pincfg_no_hp_to_lineout,
sound/hda/codecs/realtek/alc269.c
4295
.v.func = alc269_fixup_pincfg_U7x7_headset_mic,
sound/hda/codecs/realtek/alc269.c
4299
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
4309
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
4318
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
4326
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
4336
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
4346
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
4356
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
4366
.v.func = alc269_fixup_hp_mute_led,
sound/hda/codecs/realtek/alc269.c
4370
.v.func = alc269_fixup_hp_mute_led_mic1,
sound/hda/codecs/realtek/alc269.c
4374
.v.func = alc269_fixup_hp_mute_led_mic2,
sound/hda/codecs/realtek/alc269.c
4378
.v.func = alc269_fixup_hp_mute_led_mic3,
sound/hda/codecs/realtek/alc269.c
4384
.v.func = alc269_fixup_hp_gpio_led,
sound/hda/codecs/realtek/alc269.c
4388
.v.func = alc269_fixup_hp_gpio_mic1_led,
sound/hda/codecs/realtek/alc269.c
4392
.v.func = alc269_fixup_hp_line1_mic1_led,
sound/hda/codecs/realtek/alc269.c
4396
.v.func = alc_fixup_inv_dmic,
sound/hda/codecs/realtek/alc269.c
4400
.v.func = alc_fixup_no_shutup,
sound/hda/codecs/realtek/alc269.c
4404
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
4414
.v.func = alc269_fixup_limit_int_mic_boost,
sound/hda/codecs/realtek/alc269.c
4420
.v.func = alc269_fixup_pincfg_no_hp_to_lineout,
sound/hda/codecs/realtek/alc269.c
4426
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
4436
.v.func = alc269_fixup_limit_int_mic_boost,
sound/hda/codecs/realtek/alc269.c
4442
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
4453
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
4462
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
4472
.v.func = alc_fixup_headset_mode,
sound/hda/codecs/realtek/alc269.c
4478
.v.func = alc_fixup_headset_mode_no_hp_mic,
sound/hda/codecs/realtek/alc269.c
4482
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
4491
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
4500
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
4518
.v.func = alc298_fixup_huawei_mbx_stereo,
sound/hda/codecs/realtek/alc269.c
4524
.v.func = alc269_fixup_x101_headset_mic,
sound/hda/codecs/realtek/alc269.c
4528
.v.verbs = (const struct hda_verb[]) {
sound/hda/codecs/realtek/alc269.c
4539
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
4548
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
4558
.v.func = alc271_hp_gate_mic_jack,
sound/hda/codecs/realtek/alc269.c
4564
.v.func = alc269_fixup_limit_int_mic_boost,
sound/hda/codecs/realtek/alc269.c
4570
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
4583
.v.func = alc269_fixup_limit_int_mic_boost,
sound/hda/codecs/realtek/alc269.c
4589
.v.func = alc269_fixup_limit_int_mic_boost,
sound/hda/codecs/realtek/alc269.c
4595
.v.verbs = (const struct hda_verb[]) {
sound/hda/codecs/realtek/alc269.c
4606
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
4615
.v.func = alc269_fixup_limit_int_mic_boost,
sound/hda/codecs/realtek/alc269.c
4621
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
4630
.v.func = alc283_fixup_chromebook,
sound/hda/codecs/realtek/alc269.c
4634
.v.func = alc283_fixup_sense_combo_jack,
sound/hda/codecs/realtek/alc269.c
4640
.v.func = alc282_fixup_asus_tx300,
sound/hda/codecs/realtek/alc269.c
4644
.v.verbs = (const struct hda_verb[]) {
sound/hda/codecs/realtek/alc269.c
4654
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
4663
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
4672
.v.func = alc290_fixup_mono_speakers,
sound/hda/codecs/realtek/alc269.c
4676
.v.func = alc290_fixup_mono_speakers,
sound/hda/codecs/realtek/alc269.c
4682
.v.func = alc_fixup_thinkpad_acpi,
sound/hda/codecs/realtek/alc269.c
4688
.v.func = alc_fixup_ideapad_acpi,
sound/hda/codecs/realtek/alc269.c
4694
.v.func = alc_fixup_inv_dmic,
sound/hda/codecs/realtek/alc269.c
4700
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
4709
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
4718
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
4728
.v.func = alc269_fixup_limit_int_mic_boost,
sound/hda/codecs/realtek/alc269.c
4734
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
4743
.v.func = alc_fixup_headset_mode_alc255,
sound/hda/codecs/realtek/alc269.c
4749
.v.func = alc_fixup_headset_mode_alc255_no_hp_mic,
sound/hda/codecs/realtek/alc269.c
4753
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
4763
.v.func = alc_fixup_tpt440_dock,
sound/hda/codecs/realtek/alc269.c
4769
.v.func = alc_fixup_disable_aamix,
sound/hda/codecs/realtek/alc269.c
4775
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
4782
.v.func = alc_fixup_micmute_led,
sound/hda/codecs/realtek/alc269.c
4786
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
4802
.v.func = alc269vb_fixup_aspire_e1_coef,
sound/hda/codecs/realtek/alc269.c
4806
.v.func = alc280_fixup_hp_gpio4,
sound/hda/codecs/realtek/alc269.c
4810
.v.func = alc286_fixup_hp_gpio_led,
sound/hda/codecs/realtek/alc269.c
4814
.v.func = alc280_fixup_hp_gpio2_mic_hotkey,
sound/hda/codecs/realtek/alc269.c
4818
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
4829
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
4839
.v.func = alc280_fixup_hp_9480m,
sound/hda/codecs/realtek/alc269.c
4843
.v.func = alc245_fixup_hp_x360_amp,
sound/hda/codecs/realtek/alc269.c
4849
.v.func = alc_fixup_headset_mode_dell_alc288,
sound/hda/codecs/realtek/alc269.c
4855
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
4865
.v.func = alc_fixup_disable_aamix,
sound/hda/codecs/realtek/alc269.c
4871
.v.func = alc_fixup_dell_xps13,
sound/hda/codecs/realtek/alc269.c
4877
.v.func = alc_fixup_disable_aamix,
sound/hda/codecs/realtek/alc269.c
4883
.v.func = alc_fixup_disable_aamix,
sound/hda/codecs/realtek/alc269.c
4889
.v.func = alc_fixup_dell_xps13,
sound/hda/codecs/realtek/alc269.c
4895
.v.func = alc_fixup_micmute_led,
sound/hda/codecs/realtek/alc269.c
4902
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
4911
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
4921
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
4930
.v.verbs = (const struct hda_verb[]) {
sound/hda/codecs/realtek/alc269.c
4941
.v.func = alc_fixup_disable_aamix,
sound/hda/codecs/realtek/alc269.c
4947
.v.func = alc233_fixup_lenovo_line2_mic_hotkey,
sound/hda/codecs/realtek/alc269.c
4951
.v.func = alc233_fixup_lenovo_low_en_micmute_led,
sound/hda/codecs/realtek/alc269.c
4955
.v.func = alc_fixup_inv_dmic,
sound/hda/codecs/realtek/alc269.c
4961
.v.func = alc269_fixup_limit_int_mic_boost
sound/hda/codecs/realtek/alc269.c
4965
.v.func = alc_fixup_disable_aamix,
sound/hda/codecs/realtek/alc269.c
4971
.v.func = alc_fixup_disable_mic_vref,
sound/hda/codecs/realtek/alc269.c
4977
.v.verbs = (const struct hda_verb[]) {
sound/hda/codecs/realtek/alc269.c
4988
.v.func = alc_fixup_disable_aamix,
sound/hda/codecs/realtek/alc269.c
4994
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
5001
.v.func = alc_fixup_tpt440_dock,
sound/hda/codecs/realtek/alc269.c
5007
.v.func = alc298_fixup_speaker_volume,
sound/hda/codecs/realtek/alc269.c
5013
.v.func = alc298_fixup_speaker_volume,
sound/hda/codecs/realtek/alc269.c
5017
.v.func = alc295_fixup_disable_dac3,
sound/hda/codecs/realtek/alc269.c
5021
.v.func = alc285_fixup_speaker2_to_dac1,
sound/hda/codecs/realtek/alc269.c
5027
.v.func = alc285_fixup_speaker2_to_dac1,
sound/hda/codecs/realtek/alc269.c
5033
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
5043
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
5052
.v.func = alc285_fixup_speaker2_to_dac1,
sound/hda/codecs/realtek/alc269.c
5058
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
5068
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
5077
.v.func = alc_fixup_auto_mute_via_amp,
sound/hda/codecs/realtek/alc269.c
5083
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
5093
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
5103
.v.func = alc_fixup_headset_mode,
sound/hda/codecs/realtek/alc269.c
5107
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
5118
.v.func = alc_fixup_gpio4,
sound/hda/codecs/realtek/alc269.c
5122
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
5131
.v.verbs = (const struct hda_verb[]) {
sound/hda/codecs/realtek/alc269.c
5142
.v.func = alc233_alc662_fixup_lenovo_dual_codecs,
sound/hda/codecs/realtek/alc269.c
5148
.v.verbs = (const struct hda_verb[]) {
sound/hda/codecs/realtek/alc269.c
5158
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
5170
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
5182
.v.func = alc225_fixup_s3_pop_noise,
sound/hda/codecs/realtek/alc269.c
5188
.v.verbs = (const struct hda_verb[]) {
sound/hda/codecs/realtek/alc269.c
5203
.v.func = alc274_fixup_bind_dacs,
sound/hda/codecs/realtek/alc269.c
5209
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
5218
.v.func = alc_fixup_tpt470_dock,
sound/hda/codecs/realtek/alc269.c
5224
.v.func = alc_fixup_tpt470_dacs,
sound/hda/codecs/realtek/alc269.c
5230
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
5239
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
5248
.v.func = alc295_fixup_hp_top_speakers,
sound/hda/codecs/realtek/alc269.c
5254
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
5263
.v.func = alc285_fixup_invalidate_dacs,
sound/hda/codecs/realtek/alc269.c
5269
.v.func = alc_fixup_auto_mute_via_amp,
sound/hda/codecs/realtek/alc269.c
5273
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
5282
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
5292
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
5301
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
5310
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
5319
.v.verbs = (const struct hda_verb[]) {
sound/hda/codecs/realtek/alc269.c
5332
.v.func = alc295_fixup_chromebook,
sound/hda/codecs/realtek/alc269.c
5338
.v.func = alc_fixup_headset_jack,
sound/hda/codecs/realtek/alc269.c
5342
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
5351
.v.verbs = (const struct hda_verb[]) {
sound/hda/codecs/realtek/alc269.c
5362
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
5372
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
5382
.v.func = alc_fixup_auto_mute_via_amp,
sound/hda/codecs/realtek/alc269.c
5388
.v.func = alc_fixup_disable_mic_vref,
sound/hda/codecs/realtek/alc269.c
5394
.v.verbs = (const struct hda_verb[]) {
sound/hda/codecs/realtek/alc269.c
5404
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
5413
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
5422
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
5429
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
5436
.v.func = cs35l41_fixup_i2c_two,
sound/hda/codecs/realtek/alc269.c
5442
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
5452
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
5461
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
5470
.v.func = alc285_fixup_speaker2_to_dac1,
sound/hda/codecs/realtek/alc269.c
5476
.v.func = alc285_fixup_speaker2_to_dac1,
sound/hda/codecs/realtek/alc269.c
5482
.v.func = alc285_fixup_speaker2_to_dac1,
sound/hda/codecs/realtek/alc269.c
5489
.v.func = alc_fixup_gpio4,
sound/hda/codecs/realtek/alc269.c
5495
.v.func = cs35l41_fixup_i2c_two,
sound/hda/codecs/realtek/alc269.c
5501
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
5512
.v.verbs = (const struct hda_verb[]) {
sound/hda/codecs/realtek/alc269.c
5532
.v.func = alc285_fixup_speaker2_to_dac1,
sound/hda/codecs/realtek/alc269.c
5536
.v.func = alc285_fixup_thinkpad_x1_gen7,
sound/hda/codecs/realtek/alc269.c
5542
.v.func = alc_fixup_headset_jack,
sound/hda/codecs/realtek/alc269.c
5548
.v.verbs = (const struct hda_verb[]) {
sound/hda/codecs/realtek/alc269.c
5559
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
5570
.v.verbs = (const struct hda_verb[]) {
sound/hda/codecs/realtek/alc269.c
5582
.v.func = alc294_fixup_gx502_hp,
sound/hda/codecs/realtek/alc269.c
5586
.v.func = tas2781_fixup_tias_i2c,
sound/hda/codecs/realtek/alc269.c
5592
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
5603
.v.verbs = (const struct hda_verb[]) {
sound/hda/codecs/realtek/alc269.c
5617
.v.func = alc294_fixup_gu502_hp,
sound/hda/codecs/realtek/alc269.c
5621
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
5630
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
5641
.v.verbs = (const struct hda_verb[]) {
sound/hda/codecs/realtek/alc269.c
5654
.v.func = alc285_fixup_hp_gpio_led,
sound/hda/codecs/realtek/alc269.c
5658
.v.func = alc285_fixup_hp_mute_led,
sound/hda/codecs/realtek/alc269.c
5662
.v.func = alc285_fixup_hp_spectre_x360_mute_led,
sound/hda/codecs/realtek/alc269.c
5666
.v.func = alc245_fixup_hp_envy_x360_mute_led,
sound/hda/codecs/realtek/alc269.c
5670
.v.func = alc285_fixup_hp_beep,
sound/hda/codecs/realtek/alc269.c
5676
.v.func = alc236_fixup_hp_mute_led_coefbit2,
sound/hda/codecs/realtek/alc269.c
5680
.v.func = alc236_fixup_hp_gpio_led,
sound/hda/codecs/realtek/alc269.c
5684
.v.func = alc236_fixup_hp_mute_led,
sound/hda/codecs/realtek/alc269.c
5688
.v.func = alc236_fixup_hp_mute_led_micmute_vref,
sound/hda/codecs/realtek/alc269.c
5692
.v.func = alc236_fixup_hp_mute_led_micmute_gpio,
sound/hda/codecs/realtek/alc269.c
5696
.v.func = alc_fixup_inv_dmic,
sound/hda/codecs/realtek/alc269.c
5702
.v.func = alc295_fixup_hp_mute_led_coefbit11,
sound/hda/codecs/realtek/alc269.c
5706
.v.func = alc298_fixup_samsung_amp,
sound/hda/codecs/realtek/alc269.c
5712
.v.func = alc298_fixup_samsung_amp_v2_2_amps
sound/hda/codecs/realtek/alc269.c
5716
.v.func = alc298_fixup_samsung_amp_v2_4_amps
sound/hda/codecs/realtek/alc269.c
5720
.v.func = alc298_fixup_lg_gram_style_14
sound/hda/codecs/realtek/alc269.c
5724
.v.verbs = (const struct hda_verb[]) {
sound/hda/codecs/realtek/alc269.c
5731
.v.verbs = (const struct hda_verb[]) {
sound/hda/codecs/realtek/alc269.c
5739
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
5748
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
5759
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
5768
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
5777
.v.func = alc289_fixup_asus_ga401,
sound/hda/codecs/realtek/alc269.c
5783
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
5790
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
5799
.v.func = alc285_fixup_hp_gpio_amp_init,
sound/hda/codecs/realtek/alc269.c
5805
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
5822
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
5840
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
5858
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
5876
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
5888
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
5897
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
5906
.v.verbs = (const struct hda_verb[]) {
sound/hda/codecs/realtek/alc269.c
5916
.v.verbs = (const struct hda_verb[]) {
sound/hda/codecs/realtek/alc269.c
5924
.v.func = alc274_fixup_hp_headset_mic,
sound/hda/codecs/realtek/alc269.c
5930
.v.func = alc274_fixup_hp_envy_gpio,
sound/hda/codecs/realtek/alc269.c
5934
.v.verbs = (const struct hda_verb[]) {
sound/hda/codecs/realtek/alc269.c
5954
.v.verbs = (const struct hda_verb[]) {
sound/hda/codecs/realtek/alc269.c
5965
.v.func = alc_fixup_headset_jack,
sound/hda/codecs/realtek/alc269.c
5971
.v.func = alc287_fixup_hp_gpio_led,
sound/hda/codecs/realtek/alc269.c
5975
.v.func = alc274_fixup_hp_headset_mic,
sound/hda/codecs/realtek/alc269.c
5979
.v.func = alc_fixup_no_int_mic,
sound/hda/codecs/realtek/alc269.c
5985
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
5995
.v.func = alc269_fixup_limit_int_mic_boost,
sound/hda/codecs/realtek/alc269.c
6001
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
6011
.v.func = alc285_fixup_ideapad_s740_coef,
sound/hda/codecs/realtek/alc269.c
6017
.v.func = alc269_fixup_limit_int_mic_boost,
sound/hda/codecs/realtek/alc269.c
6023
.v.func = alc295_fixup_asus_dacs,
sound/hda/codecs/realtek/alc269.c
6027
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
6047
.v.func = alc285_fixup_hp_spectre_x360,
sound/hda/codecs/realtek/alc269.c
6051
.v.func = alc285_fixup_hp_spectre_x360_eb1
sound/hda/codecs/realtek/alc269.c
6055
.v.func = alc285_fixup_hp_spectre_x360_df1
sound/hda/codecs/realtek/alc269.c
6059
.v.func = alc285_fixup_hp_envy_x360,
sound/hda/codecs/realtek/alc269.c
6065
.v.func = alc285_fixup_ideapad_s740_coef,
sound/hda/codecs/realtek/alc269.c
6071
.v.func = alc_fixup_no_shutup,
sound/hda/codecs/realtek/alc269.c
6077
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
6086
.v.func = alc269_fixup_limit_int_mic_boost,
sound/hda/codecs/realtek/alc269.c
6092
.v.func = alc285_fixup_ideapad_s740_coef,
sound/hda/codecs/realtek/alc269.c
6098
.v.func = alc287_fixup_legion_15imhg05_speakers,
sound/hda/codecs/realtek/alc269.c
6105
.v.verbs = (const struct hda_verb[]) {
sound/hda/codecs/realtek/alc269.c
6144
.v.func = alc287_fixup_legion_15imhg05_speakers,
sound/hda/codecs/realtek/alc269.c
6150
.v.verbs = (const struct hda_verb[]) {
sound/hda/codecs/realtek/alc269.c
6189
.v.func = alc298_fixup_lenovo_c940_duet7,
sound/hda/codecs/realtek/alc269.c
6193
.v.func = alc287_fixup_lenovo_yoga_book_9i,
sound/hda/codecs/realtek/alc269.c
6197
.v.verbs = (const struct hda_verb[]) {
sound/hda/codecs/realtek/alc269.c
6219
.v.func = alc256_fixup_set_coef_defaults,
sound/hda/codecs/realtek/alc269.c
6223
.v.func = alc245_fixup_hp_gpio_led,
sound/hda/codecs/realtek/alc269.c
6227
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
6236
.v.func = alc233_fixup_no_audio_jack,
sound/hda/codecs/realtek/alc269.c
6240
.v.func = alc256_fixup_mic_no_presence_and_resume,
sound/hda/codecs/realtek/alc269.c
6246
.v.func = alc287_fixup_legion_16achg6_speakers,
sound/hda/codecs/realtek/alc269.c
6250
.v.func = cs35l41_fixup_i2c_two,
sound/hda/codecs/realtek/alc269.c
6254
.v.func = cs35l41_fixup_i2c_two,
sound/hda/codecs/realtek/alc269.c
6260
.v.func = cs35l41_fixup_i2c_four,
sound/hda/codecs/realtek/alc269.c
6264
.v.func = cs35l41_fixup_spi_two,
sound/hda/codecs/realtek/alc269.c
6268
.v.func = cs35l41_fixup_spi_one,
sound/hda/codecs/realtek/alc269.c
6272
.v.func = cs35l41_fixup_spi_two,
sound/hda/codecs/realtek/alc269.c
6278
.v.func = cs35l41_fixup_spi_four,
sound/hda/codecs/realtek/alc269.c
6282
.v.func = cs35l41_fixup_spi_four,
sound/hda/codecs/realtek/alc269.c
6288
.v.verbs = (const struct hda_verb[]) {
sound/hda/codecs/realtek/alc269.c
6298
.v.func = alc_fixup_dell4_mic_no_presence_quiet,
sound/hda/codecs/realtek/alc269.c
6304
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
6313
.v.func = alc287_fixup_legion_16ithg6_speakers,
sound/hda/codecs/realtek/alc269.c
6317
.v.verbs = (const struct hda_verb[]) {
sound/hda/codecs/realtek/alc269.c
6379
.v.func = alc287_fixup_yoga9_14iap7_bass_spk_pin,
sound/hda/codecs/realtek/alc269.c
6385
.v.func = alc287_fixup_yoga9_14iap7_bass_spk_pin,
sound/hda/codecs/realtek/alc269.c
6391
.v.func = alc295_fixup_dell_inspiron_top_speakers,
sound/hda/codecs/realtek/alc269.c
6397
.v.func = alc1220_fixup_gb_dual_codecs,
sound/hda/codecs/realtek/alc269.c
6403
.v.func = cs35l41_fixup_i2c_two,
sound/hda/codecs/realtek/alc269.c
6409
.v.func = tas2781_fixup_tias_i2c,
sound/hda/codecs/realtek/alc269.c
6415
.v.func = tas2781_fixup_spi,
sound/hda/codecs/realtek/alc269.c
6421
.v.func = tas2781_fixup_txnw_i2c,
sound/hda/codecs/realtek/alc269.c
6427
.v.func = tas2781_fixup_txnw_i2c,
sound/hda/codecs/realtek/alc269.c
6433
.v.func = yoga7_14arb7_fixup_i2c,
sound/hda/codecs/realtek/alc269.c
6439
.v.func = alc245_fixup_hp_mute_led_coefbit,
sound/hda/codecs/realtek/alc269.c
6443
.v.func = alc245_fixup_hp_mute_led_v1_coefbit,
sound/hda/codecs/realtek/alc269.c
6447
.v.func = alc245_fixup_hp_mute_led_v2_coefbit,
sound/hda/codecs/realtek/alc269.c
6451
.v.func = alc245_fixup_hp_mute_led_coefbit,
sound/hda/codecs/realtek/alc269.c
6457
.v.func = alc287_fixup_bind_dacs,
sound/hda/codecs/realtek/alc269.c
6463
.v.func = alc287_fixup_bind_dacs,
sound/hda/codecs/realtek/alc269.c
6469
.v.func = alc2xx_fixup_headset_mic,
sound/hda/codecs/realtek/alc269.c
6473
.v.func = cs35l41_fixup_spi_two,
sound/hda/codecs/realtek/alc269.c
6479
.v.func = cs35l41_fixup_i2c_two,
sound/hda/codecs/realtek/alc269.c
6483
.v.func = alc256_fixup_acer_sfg16_micmute_led,
sound/hda/codecs/realtek/alc269.c
6487
.v.func = alc256_decrease_headphone_amp_val,
sound/hda/codecs/realtek/alc269.c
6491
.v.func = alc245_fixup_hp_spectre_x360_eu0xxx,
sound/hda/codecs/realtek/alc269.c
6495
.v.func = alc245_fixup_hp_spectre_x360_16_aa0xxx,
sound/hda/codecs/realtek/alc269.c
6499
.v.func = alc245_fixup_hp_zbook_firefly_g12a,
sound/hda/codecs/realtek/alc269.c
6503
.v.func = alc285_fixup_asus_ga403u,
sound/hda/codecs/realtek/alc269.c
6507
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
6517
.v.func = alc285_fixup_speaker2_to_dac1,
sound/hda/codecs/realtek/alc269.c
6523
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
6531
.v.func = alc285_fixup_speaker2_to_dac1,
sound/hda/codecs/realtek/alc269.c
6537
.v.func = alc287_fixup_lenovo_thinkpad_with_alc1318,
sound/hda/codecs/realtek/alc269.c
6543
.v.func = alc256_fixup_chromebook,
sound/hda/codecs/realtek/alc269.c
6549
.v.func = alc269_fixup_limit_int_mic_boost,
sound/hda/codecs/realtek/alc269.c
6555
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
6565
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
6572
.v.func = alc233_fixup_starlabs_starfighter,
sound/hda/codecs/realtek/alc269.c
6576
.v.func = alc294_fixup_bass_speaker_15,
sound/hda/codecs/realtek/alc269.c
6580
.v.func = alc283_fixup_dell_hp_resume,
sound/hda/codecs/realtek/alc269.c
6584
.v.func = cs35l41_fixup_spi_two,
sound/hda/codecs/realtek/alc269.c
6590
.v.func = alc274_fixup_hp_aio_bind_dacs,
sound/hda/codecs/realtek/alc269.c
6594
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
6604
.v.func = alc285_fixup_speaker2_to_dac1,
sound/hda/codecs/realtek/alc269.c
6608
.v.func = alc269_fixup_limit_int_mic_boost,
sound/hda/codecs/realtek/alc269.c
6614
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
6622
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc269.c
6632
.v.func = alc245_tas2781_spi_hp_fixup_muteled,
sound/hda/codecs/realtek/alc269.c
6636
.v.func = alc245_tas2781_i2c_hp_fixup_muteled,
sound/hda/codecs/realtek/alc269.c
6640
.v.func = alc288_fixup_surface_swap_dacs,
sound/hda/codecs/realtek/alc269.c
6644
.v.func = alc233_fixup_lenovo_gpio2_mic_hotkey,
sound/hda/codecs/realtek/alc269.c
6649
.v.func = alc285_fixup_thinkpad_x1_gen7,
sound/hda/codecs/realtek/alc269.c
6653
.v.func = alc285_fixup_hp_coef_micmute_led,
sound/hda/codecs/realtek/alc269.c
6659
.v.func = alc245_fixup_hp_mute_led_coefbit,
sound/hda/codecs/realtek/alc269.c
6665
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc662.c
321
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc662.c
328
.v.func = alc662_fixup_led_gpio1,
sound/hda/codecs/realtek/alc662.c
332
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc662.c
341
.v.func = alc272_fixup_mario,
sound/hda/codecs/realtek/alc662.c
345
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc662.c
364
.v.verbs = (const struct hda_verb[]) {
sound/hda/codecs/realtek/alc662.c
371
.v.func = alc_fixup_sku_ignore,
sound/hda/codecs/realtek/alc662.c
375
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc662.c
384
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc662.c
396
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc662.c
408
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc662.c
421
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc662.c
434
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc662.c
447
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc662.c
460
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc662.c
474
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc662.c
488
.v.func = alc_fixup_no_jack_detect,
sound/hda/codecs/realtek/alc662.c
492
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc662.c
499
.v.func = alc_fixup_inv_dmic,
sound/hda/codecs/realtek/alc662.c
503
.v.func = alc_fixup_dell_xps13,
sound/hda/codecs/realtek/alc662.c
509
.v.func = alc_fixup_disable_aamix,
sound/hda/codecs/realtek/alc662.c
515
.v.func = alc_fixup_auto_mute_via_amp,
sound/hda/codecs/realtek/alc662.c
521
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc662.c
531
.v.func = alc_fixup_headset_mode_alc662,
sound/hda/codecs/realtek/alc662.c
535
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc662.c
545
.v.func = alc_fixup_headset_mode_alc668,
sound/hda/codecs/realtek/alc662.c
549
.v.func = alc_fixup_bass_chmap,
sound/hda/codecs/realtek/alc662.c
555
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc662.c
564
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc662.c
573
.v.func = alc_fixup_bass_chmap,
sound/hda/codecs/realtek/alc662.c
577
.v.func = alc_fixup_auto_mute_via_amp,
sound/hda/codecs/realtek/alc662.c
583
.v.func = alc_fixup_headset_mode_alc668,
sound/hda/codecs/realtek/alc662.c
588
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc662.c
599
.v.verbs = (const struct hda_verb[]) {
sound/hda/codecs/realtek/alc662.c
607
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc662.c
616
.v.func = alc_fixup_headset_mode,
sound/hda/codecs/realtek/alc662.c
620
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc662.c
630
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc662.c
637
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc662.c
645
.v.func = alc662_fixup_usi_headset_mic,
sound/hda/codecs/realtek/alc662.c
649
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc662.c
659
.v.func = alc233_alc662_fixup_lenovo_dual_codecs,
sound/hda/codecs/realtek/alc662.c
663
.v.func = alc662_fixup_aspire_ethos_hp,
sound/hda/codecs/realtek/alc662.c
667
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc662.c
678
.v.func = alc671_fixup_hp_headset_mic2,
sound/hda/codecs/realtek/alc662.c
682
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc662.c
691
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc662.c
701
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc662.c
710
.v.func = alc_fixup_headset_mic,
sound/hda/codecs/realtek/alc662.c
716
.v.verbs = (const struct hda_verb[]) {
sound/hda/codecs/realtek/alc662.c
724
.v.func = alc897_fixup_lenovo_headset_mic,
sound/hda/codecs/realtek/alc662.c
728
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc662.c
737
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc662.c
744
.v.func = alc897_fixup_lenovo_headset_mode,
sound/hda/codecs/realtek/alc662.c
748
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc662.c
757
.v.verbs = (const struct hda_verb[]) {
sound/hda/codecs/realtek/alc662.c
764
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc861.c
46
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc861.c
54
.v.func = alc861_fixup_asus_amp_vref_0f,
sound/hda/codecs/realtek/alc861.c
58
.v.func = alc_fixup_no_jack_detect,
sound/hda/codecs/realtek/alc861.c
62
.v.func = alc861_fixup_asus_amp_vref_0f,
sound/hda/codecs/realtek/alc861.c
68
.v.verbs = (const struct hda_verb[]) {
sound/hda/codecs/realtek/alc861vd.c
48
.v.func = alc660vd_fixup_asus_gpio1,
sound/hda/codecs/realtek/alc861vd.c
52
.v.func = alc861vd_fixup_dallas,
sound/hda/codecs/realtek/alc880.c
103
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc880.c
113
.v.verbs = (const struct hda_verb[]) {
sound/hda/codecs/realtek/alc880.c
122
.v.verbs = (const struct hda_verb[]) {
sound/hda/codecs/realtek/alc880.c
133
.v.func = alc880_fixup_vol_knob,
sound/hda/codecs/realtek/alc880.c
138
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc880.c
158
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc880.c
178
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc880.c
187
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc880.c
198
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc880.c
216
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc880.c
236
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc880.c
254
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc880.c
263
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc880.c
272
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc880.c
290
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc880.c
299
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc880.c
308
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc880.c
326
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc880.c
335
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc880.c
344
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc880.c
67
.v.func = alc_fixup_gpio1,
sound/hda/codecs/realtek/alc880.c
71
.v.func = alc_fixup_gpio2,
sound/hda/codecs/realtek/alc880.c
75
.v.verbs = (const struct hda_verb[]) {
sound/hda/codecs/realtek/alc880.c
85
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc880.c
95
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc882.c
267
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc882.c
276
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc882.c
284
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc882.c
291
.v.func = alc_fixup_sku_ignore,
sound/hda/codecs/realtek/alc882.c
295
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc882.c
302
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc882.c
309
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc882.c
318
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc882.c
325
.v.verbs = (const struct hda_verb[]) {
sound/hda/codecs/realtek/alc882.c
333
.v.verbs = (const struct hda_verb[]) {
sound/hda/codecs/realtek/alc882.c
342
.v.verbs = (const struct hda_verb[]) {
sound/hda/codecs/realtek/alc882.c
351
.v.verbs = (const struct hda_verb[]) {
sound/hda/codecs/realtek/alc882.c
360
.v.verbs = (const struct hda_verb[]) {
sound/hda/codecs/realtek/alc882.c
369
.v.func = alc_fixup_gpio1,
sound/hda/codecs/realtek/alc882.c
373
.v.func = alc_fixup_gpio2,
sound/hda/codecs/realtek/alc882.c
377
.v.func = alc_fixup_gpio3,
sound/hda/codecs/realtek/alc882.c
381
.v.func = alc_fixup_gpio1,
sound/hda/codecs/realtek/alc882.c
387
.v.func = alc889_fixup_coef,
sound/hda/codecs/realtek/alc882.c
391
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc882.c
401
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc882.c
412
.v.verbs = (const struct hda_verb[]) {
sound/hda/codecs/realtek/alc882.c
446
.v.func = alc885_fixup_macpro_gpio,
sound/hda/codecs/realtek/alc882.c
450
.v.func = alc889_fixup_dac_route,
sound/hda/codecs/realtek/alc882.c
454
.v.func = alc889_fixup_mbp_vref,
sound/hda/codecs/realtek/alc882.c
460
.v.func = alc889_fixup_imac91_vref,
sound/hda/codecs/realtek/alc882.c
466
.v.func = alc889_fixup_mba11_vref,
sound/hda/codecs/realtek/alc882.c
472
.v.func = alc889_fixup_mba21_vref,
sound/hda/codecs/realtek/alc882.c
478
.v.func = alc889_fixup_mba11_vref,
sound/hda/codecs/realtek/alc882.c
484
.v.func = alc889_fixup_mbp_vref,
sound/hda/codecs/realtek/alc882.c
490
.v.func = alc_fixup_inv_dmic,
sound/hda/codecs/realtek/alc882.c
494
.v.func = alc882_fixup_no_primary_hp,
sound/hda/codecs/realtek/alc882.c
498
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc882.c
507
.v.func = alc_fixup_bass_chmap,
sound/hda/codecs/realtek/alc882.c
511
.v.func = alc1220_fixup_gb_dual_codecs,
sound/hda/codecs/realtek/alc882.c
515
.v.func = alc1220_fixup_gb_x570,
sound/hda/codecs/realtek/alc882.c
519
.v.func = alc1220_fixup_clevo_p950,
sound/hda/codecs/realtek/alc882.c
523
.v.func = alc1220_fixup_clevo_pb51ed,
sound/hda/codecs/realtek/alc882.c
527
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc882.c
536
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc882.c
544
.v.func = alc887_fixup_asus_jack,
sound/hda/codecs/realtek/alc882.c
550
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/realtek/alc882.c
558
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/side-codecs/cirrus_scodec_test.c
196
unsigned int v;
sound/hda/codecs/side-codecs/cirrus_scodec_test.c
202
for (i = 0, v = 0; i < num_spk_id_refs; ) {
sound/hda/codecs/side-codecs/cirrus_scodec_test.c
203
cirrus_scodec_test_set_gpio_ref_arg(&refs[i++], v++);
sound/hda/codecs/side-codecs/cirrus_scodec_test.c
215
v -= param->gpios_per_amp;
sound/hda/codecs/side-codecs/cirrus_scodec_test.c
222
for (v = 0; v < (1 << param->gpios_per_amp); ++v) {
sound/hda/codecs/side-codecs/cirrus_scodec_test.c
225
v << (param->gpios_per_amp * (i / param->num_amps_sharing));
sound/hda/codecs/side-codecs/cirrus_scodec_test.c
228
KUNIT_EXPECT_EQ_MSG(test, ret, v,
sound/hda/codecs/sigmatel.c
1373
.v.pins = ref9200_pin_configs,
sound/hda/codecs/sigmatel.c
1377
.v.pins = oqo9200_pin_configs,
sound/hda/codecs/sigmatel.c
1383
.v.pins = dell9200_d21_pin_configs,
sound/hda/codecs/sigmatel.c
1387
.v.pins = dell9200_d22_pin_configs,
sound/hda/codecs/sigmatel.c
1391
.v.pins = dell9200_d23_pin_configs,
sound/hda/codecs/sigmatel.c
1395
.v.pins = dell9200_m21_pin_configs,
sound/hda/codecs/sigmatel.c
1399
.v.pins = dell9200_m22_pin_configs,
sound/hda/codecs/sigmatel.c
1403
.v.pins = dell9200_m23_pin_configs,
sound/hda/codecs/sigmatel.c
1407
.v.pins = dell9200_m24_pin_configs,
sound/hda/codecs/sigmatel.c
1411
.v.pins = dell9200_m25_pin_configs,
sound/hda/codecs/sigmatel.c
1415
.v.pins = dell9200_m26_pin_configs,
sound/hda/codecs/sigmatel.c
1419
.v.pins = dell9200_m27_pin_configs,
sound/hda/codecs/sigmatel.c
1423
.v.pins = gateway9200_m4_pin_configs,
sound/hda/codecs/sigmatel.c
1429
.v.pins = gateway9200_m4_2_pin_configs,
sound/hda/codecs/sigmatel.c
1435
.v.func = stac9200_fixup_panasonic,
sound/hda/codecs/sigmatel.c
1439
.v.verbs = (const struct hda_verb[]) {
sound/hda/codecs/sigmatel.c
1642
.v.pins = ref925x_pin_configs,
sound/hda/codecs/sigmatel.c
1646
.v.pins = stac925xM1_pin_configs,
sound/hda/codecs/sigmatel.c
1650
.v.pins = stac925xM1_2_pin_configs,
sound/hda/codecs/sigmatel.c
1654
.v.pins = stac925xM2_pin_configs,
sound/hda/codecs/sigmatel.c
1658
.v.pins = stac925xM2_2_pin_configs,
sound/hda/codecs/sigmatel.c
1662
.v.pins = stac925xM3_pin_configs,
sound/hda/codecs/sigmatel.c
1666
.v.pins = stac925xM5_pin_configs,
sound/hda/codecs/sigmatel.c
1670
.v.pins = stac925xM6_pin_configs,
sound/hda/codecs/sigmatel.c
1891
.v.func = stac92hd73xx_fixup_ref,
sound/hda/codecs/sigmatel.c
1895
.v.func = stac92hd73xx_fixup_dell_m6_amic,
sound/hda/codecs/sigmatel.c
1899
.v.func = stac92hd73xx_fixup_dell_m6_dmic,
sound/hda/codecs/sigmatel.c
1903
.v.func = stac92hd73xx_fixup_dell_m6_both,
sound/hda/codecs/sigmatel.c
1907
.v.func = stac92hd73xx_fixup_dell_eq,
sound/hda/codecs/sigmatel.c
1911
.v.func = stac92hd73xx_fixup_alienware_m17x,
sound/hda/codecs/sigmatel.c
1915
.v.func = stac92hd73xx_disable_automute,
sound/hda/codecs/sigmatel.c
1919
.v.pins = intel_dg45id_pin_configs,
sound/hda/codecs/sigmatel.c
1923
.v.func = stac92hd73xx_fixup_no_jd,
sound/hda/codecs/sigmatel.c
1927
.v.pins = stac92hd89xx_hp_front_jack_pin_configs,
sound/hda/codecs/sigmatel.c
1931
.v.pins = stac92hd89xx_hp_z1_g2_right_mic_jack_pin_configs,
sound/hda/codecs/sigmatel.c
1935
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/sigmatel.c
2642
.v.pins = ref92hd83xxx_pin_configs,
sound/hda/codecs/sigmatel.c
2646
.v.pins = ref92hd83xxx_pin_configs,
sound/hda/codecs/sigmatel.c
2650
.v.pins = dell_s14_pin_configs,
sound/hda/codecs/sigmatel.c
2654
.v.pins = dell_vostro_3500_pin_configs,
sound/hda/codecs/sigmatel.c
2658
.v.pins = hp_cNB11_intquad_pin_configs,
sound/hda/codecs/sigmatel.c
2664
.v.func = stac92hd83xxx_fixup_hp,
sound/hda/codecs/sigmatel.c
2668
.v.pins = hp_dv7_4000_pin_configs,
sound/hda/codecs/sigmatel.c
2674
.v.func = stac92hd83xxx_fixup_hp_zephyr,
sound/hda/codecs/sigmatel.c
2680
.v.func = stac92hd83xxx_fixup_hp_led,
sound/hda/codecs/sigmatel.c
2686
.v.func = stac92hd83xxx_fixup_hp_inv_led,
sound/hda/codecs/sigmatel.c
2692
.v.func = stac92hd83xxx_fixup_hp_mic_led,
sound/hda/codecs/sigmatel.c
2698
.v.func = stac92hd83xxx_fixup_hp_led_gpio10,
sound/hda/codecs/sigmatel.c
2704
.v.func = stac92hd83xxx_fixup_headset_jack,
sound/hda/codecs/sigmatel.c
2708
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/sigmatel.c
2715
.v.verbs = hp_bnb13_eq_verbs,
sound/hda/codecs/sigmatel.c
2721
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/sigmatel.c
2728
.v.func = hp_envy_ts_fixup_dac_bind,
sound/hda/codecs/sigmatel.c
2734
.v.func = stac92hd83xxx_fixup_gpio10_eapd,
sound/hda/codecs/sigmatel.c
3182
.v.func = stac92hd71bxx_fixup_ref,
sound/hda/codecs/sigmatel.c
3186
.v.pins = dell_m4_1_pin_configs,
sound/hda/codecs/sigmatel.c
3190
.v.pins = dell_m4_2_pin_configs,
sound/hda/codecs/sigmatel.c
3194
.v.pins = dell_m4_3_pin_configs,
sound/hda/codecs/sigmatel.c
3198
.v.func = stac92hd71bxx_fixup_hp_m4,
sound/hda/codecs/sigmatel.c
3204
.v.func = stac92hd71bxx_fixup_hp_dv4,
sound/hda/codecs/sigmatel.c
3210
.v.func = stac92hd71bxx_fixup_hp_dv5,
sound/hda/codecs/sigmatel.c
3216
.v.func = stac92hd71bxx_fixup_hp_hdx,
sound/hda/codecs/sigmatel.c
3222
.v.func = stac92hd71bxx_fixup_hp,
sound/hda/codecs/sigmatel.c
3548
.v.pins = ref922x_pin_configs,
sound/hda/codecs/sigmatel.c
3552
.v.pins = d945gtp3_pin_configs,
sound/hda/codecs/sigmatel.c
3556
.v.pins = d945gtp5_pin_configs,
sound/hda/codecs/sigmatel.c
3560
.v.func = stac922x_fixup_intel_mac_auto,
sound/hda/codecs/sigmatel.c
3564
.v.pins = intel_mac_v1_pin_configs,
sound/hda/codecs/sigmatel.c
3570
.v.pins = intel_mac_v2_pin_configs,
sound/hda/codecs/sigmatel.c
3576
.v.pins = intel_mac_v3_pin_configs,
sound/hda/codecs/sigmatel.c
3582
.v.pins = intel_mac_v4_pin_configs,
sound/hda/codecs/sigmatel.c
3588
.v.pins = intel_mac_v5_pin_configs,
sound/hda/codecs/sigmatel.c
3594
.v.func = stac922x_fixup_intel_mac_gpio,
sound/hda/codecs/sigmatel.c
3598
.v.pins = ecs202_pin_configs,
sound/hda/codecs/sigmatel.c
3602
.v.pins = dell_922x_d81_pin_configs,
sound/hda/codecs/sigmatel.c
3606
.v.pins = dell_922x_d82_pin_configs,
sound/hda/codecs/sigmatel.c
3610
.v.pins = dell_922x_m81_pin_configs,
sound/hda/codecs/sigmatel.c
3614
.v.pins = dell_922x_m82_pin_configs,
sound/hda/codecs/sigmatel.c
3877
.v.func = stac927x_fixup_ref_no_jd,
sound/hda/codecs/sigmatel.c
3883
.v.func = stac927x_fixup_ref,
sound/hda/codecs/sigmatel.c
3887
.v.pins = d965_3st_pin_configs,
sound/hda/codecs/sigmatel.c
3893
.v.pins = d965_5st_pin_configs,
sound/hda/codecs/sigmatel.c
3899
.v.verbs = d965_core_init,
sound/hda/codecs/sigmatel.c
3903
.v.pins = d965_5st_no_fp_pin_configs,
sound/hda/codecs/sigmatel.c
3907
.v.pins = nemo_pin_configs,
sound/hda/codecs/sigmatel.c
3911
.v.pins = dell_3st_pin_configs,
sound/hda/codecs/sigmatel.c
3917
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/sigmatel.c
3929
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/sigmatel.c
3939
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/sigmatel.c
3949
.v.func = stac927x_fixup_dell_dmic,
sound/hda/codecs/sigmatel.c
3953
.v.func = stac927x_fixup_volknob,
sound/hda/codecs/sigmatel.c
4151
.v.func = stac9205_fixup_ref,
sound/hda/codecs/sigmatel.c
4155
.v.pins = dell_9205_m42_pin_configs,
sound/hda/codecs/sigmatel.c
4159
.v.func = stac9205_fixup_dell_m43,
sound/hda/codecs/sigmatel.c
4163
.v.pins = dell_9205_m44_pin_configs,
sound/hda/codecs/sigmatel.c
4167
.v.func = stac9205_fixup_eapd,
sound/hda/codecs/sigmatel.c
4245
.v.func = stac92hd95_fixup_hp_led,
sound/hda/codecs/sigmatel.c
4249
.v.verbs = (const struct hda_verb[]) {
sound/hda/codecs/sigmatel.c
4935
.v.pins = stac9872_vaio_pin_configs,
sound/hda/codecs/via.c
296
int ch, v;
sound/hda/codecs/via.c
303
v = snd_hda_codec_amp_read(codec, p->nid, ch, p->dir,
sound/hda/codecs/via.c
305
if (!(v & HDA_AMP_MUTE) && v > 0)
sound/hda/codecs/via.c
916
.v.func = via_fixup_intmic_boost,
sound/hda/codecs/via.c
920
.v.pins = (const struct hda_pintbl[]) {
sound/hda/codecs/via.c
929
.v.func = via_fixup_power_save,
sound/hda/common/auto_parser.c
785
const struct hda_verb **v;
sound/hda/common/auto_parser.c
786
v = snd_array_new(&codec->verbs);
sound/hda/common/auto_parser.c
787
if (!v)
sound/hda/common/auto_parser.c
789
*v = list;
sound/hda/common/auto_parser.c
800
const struct hda_verb **v;
sound/hda/common/auto_parser.c
803
snd_array_for_each(&codec->verbs, i, v)
sound/hda/common/auto_parser.c
804
snd_hda_sequence_write(codec, *v);
sound/hda/common/auto_parser.c
842
if (action != HDA_FIXUP_ACT_PRE_PROBE || !fix->v.pins)
sound/hda/common/auto_parser.c
846
snd_hda_apply_pincfgs(codec, fix->v.pins);
sound/hda/common/auto_parser.c
849
if (action != HDA_FIXUP_ACT_PROBE || !fix->v.verbs)
sound/hda/common/auto_parser.c
853
snd_hda_add_verbs(codec, fix->v.verbs);
sound/hda/common/auto_parser.c
856
if (!fix->v.func)
sound/hda/common/auto_parser.c
860
fix->v.func(codec, fix, action);
sound/hda/common/auto_parser.c
863
if (action != HDA_FIXUP_ACT_PROBE || !fix->v.pins)
sound/hda/common/auto_parser.c
867
set_pin_targets(codec, fix->v.pins);
sound/hda/common/codec.c
3451
int ch, v;
sound/hda/common/codec.c
3464
v = snd_hda_codec_amp_read(codec, p->nid, ch, p->dir,
sound/hda/common/codec.c
3466
if (!(v & HDA_AMP_MUTE) && v > 0) {
sound/hda/common/hda_local.h
294
} v;
sound/hda/common/sysfs.c
216
const struct hda_verb *v;
sound/hda/common/sysfs.c
220
snd_array_for_each(&codec->init_verbs, i, v) {
sound/hda/common/sysfs.c
222
v->nid, v->verb, v->param);
sound/hda/common/sysfs.c
229
struct hda_verb *v;
sound/hda/common/sysfs.c
237
v = snd_array_new(&codec->init_verbs);
sound/hda/common/sysfs.c
238
if (!v)
sound/hda/common/sysfs.c
240
v->nid = nid;
sound/hda/common/sysfs.c
241
v->verb = verb;
sound/hda/common/sysfs.c
242
v->param = param;
sound/hda/controllers/tegra.c
106
u32 v;
sound/hda/controllers/tegra.c
109
v = readl(hda->regs + HDA_IPFS_CONFIG);
sound/hda/controllers/tegra.c
110
v |= HDA_IPFS_EN_FPCI;
sound/hda/controllers/tegra.c
111
writel(v, hda->regs + HDA_IPFS_CONFIG);
sound/hda/controllers/tegra.c
114
v = readl(hda->regs + HDA_CFG_CMD);
sound/hda/controllers/tegra.c
115
v &= ~HDA_DISABLE_INTR;
sound/hda/controllers/tegra.c
116
v |= HDA_ENABLE_MEM_SPACE | HDA_ENABLE_IO_SPACE |
sound/hda/controllers/tegra.c
118
writel(v, hda->regs + HDA_CFG_CMD);
sound/hda/controllers/tegra.c
124
v = readl(hda->regs + HDA_IPFS_INTR_MASK);
sound/hda/controllers/tegra.c
125
v |= HDA_IPFS_EN_INTR;
sound/hda/controllers/tegra.c
126
writel(v, hda->regs + HDA_IPFS_INTR_MASK);
sound/hda/core/bus.c
243
unsigned int v;
sound/hda/core/bus.c
245
v = readl(aligned_addr);
sound/hda/core/bus.c
246
return (v >> shift) & mask;
sound/hda/core/bus.c
256
unsigned int v;
sound/hda/core/bus.c
258
v = readl(aligned_addr);
sound/hda/core/bus.c
259
v &= ~(mask << shift);
sound/hda/core/bus.c
260
v |= val << shift;
sound/hda/core/bus.c
261
writel(v, aligned_addr);
sound/hda/core/regmap.c
69
const unsigned int *v;
sound/hda/core/regmap.c
72
snd_array_for_each(&codec->vendor_verbs, i, v) {
sound/hda/core/regmap.c
73
if (verb == *v)
sound/isa/sb/emu8000_patch.c
152
truesize = sp->v.size;
sound/isa/sb/emu8000_patch.c
153
if (sp->v.mode_flags & (SNDRV_SFNT_SAMPLE_BIDIR_LOOP|SNDRV_SFNT_SAMPLE_REVERSE_LOOP))
sound/isa/sb/emu8000_patch.c
154
truesize += sp->v.loopend - sp->v.loopstart;
sound/isa/sb/emu8000_patch.c
155
if (sp->v.mode_flags & SNDRV_SFNT_SAMPLE_NO_BLANK)
sound/isa/sb/emu8000_patch.c
164
if (sp->v.mode_flags & SNDRV_SFNT_SAMPLE_8BITS) {
sound/isa/sb/emu8000_patch.c
165
if (!access_ok(data, sp->v.size))
sound/isa/sb/emu8000_patch.c
168
if (!access_ok(data, sp->v.size * 2))
sound/isa/sb/emu8000_patch.c
177
sp->v.truesize = truesize * 2; /* in bytes */
sound/isa/sb/emu8000_patch.c
200
for (i = 0; i < sp->v.size; i++) {
sound/isa/sb/emu8000_patch.c
203
s = read_word(data, offset, sp->v.mode_flags);
sound/isa/sb/emu8000_patch.c
212
if (i == sp->v.loopend &&
sound/isa/sb/emu8000_patch.c
213
(sp->v.mode_flags & (SNDRV_SFNT_SAMPLE_BIDIR_LOOP|SNDRV_SFNT_SAMPLE_REVERSE_LOOP)))
sound/isa/sb/emu8000_patch.c
215
int looplen = sp->v.loopend - sp->v.loopstart;
sound/isa/sb/emu8000_patch.c
220
s = read_word(data, offset - k, sp->v.mode_flags);
sound/isa/sb/emu8000_patch.c
223
if (sp->v.mode_flags & SNDRV_SFNT_SAMPLE_BIDIR_LOOP) {
sound/isa/sb/emu8000_patch.c
224
sp->v.loopend += looplen;
sound/isa/sb/emu8000_patch.c
226
sp->v.loopstart += looplen;
sound/isa/sb/emu8000_patch.c
227
sp->v.loopend += looplen;
sound/isa/sb/emu8000_patch.c
229
sp->v.end += looplen;
sound/isa/sb/emu8000_patch.c
234
if (sp->v.mode_flags & SNDRV_SFNT_SAMPLE_NO_BLANK) {
sound/isa/sb/emu8000_patch.c
238
if (sp->v.mode_flags & SNDRV_SFNT_SAMPLE_SINGLESHOT) {
sound/isa/sb/emu8000_patch.c
239
sp->v.loopstart = sp->v.end + BLANK_LOOP_START;
sound/isa/sb/emu8000_patch.c
240
sp->v.loopend = sp->v.end + BLANK_LOOP_END;
sound/isa/sb/emu8000_patch.c
245
sp->v.start += dram_start;
sound/isa/sb/emu8000_patch.c
246
sp->v.end += dram_start;
sound/isa/sb/emu8000_patch.c
247
sp->v.loopstart += dram_start;
sound/isa/sb/emu8000_patch.c
248
sp->v.loopend += dram_start;
sound/isa/sb/sb8_main.c
32
#define SB8_DEN(v) ((SB8_CLOCK + (v) / 2) / (v))
sound/isa/sb/sb8_main.c
33
#define SB8_RATE(v) (SB8_CLOCK / SB8_DEN(v))
sound/oss/dmasound/dmasound_atari.c
1001
#define GAIN_VOXWARE_TO_DB(v) \
sound/oss/dmasound/dmasound_atari.c
1002
(((v) < 0) ? -80 : ((v) > 100) ? 0 : ((v) * 4) / 5 - 80)
sound/oss/dmasound/dmasound_atari.c
1003
#define GAIN_DB_TO_VOXWARE(v) ((((v) + 80) * 5 + 1) / 4)
sound/oss/dmasound/dmasound_atari.c
1154
#define VOLUME_VOXWARE_TO_ATT(v) \
sound/oss/dmasound/dmasound_atari.c
1155
((v) < 0 ? 15 : (v) > 100 ? 0 : 15 - (v) * 3 / 20)
sound/oss/dmasound/dmasound_atari.c
1156
#define VOLUME_ATT_TO_VOXWARE(v) (100 - (v) * 20 / 3)
sound/oss/dmasound/dmasound_atari.c
1339
#define RECLEVEL_VOXWARE_TO_GAIN(v) \
sound/oss/dmasound/dmasound_atari.c
1340
((v) < 0 ? 0 : (v) > 100 ? 15 : (v) * 3 / 20)
sound/oss/dmasound/dmasound_atari.c
1341
#define RECLEVEL_GAIN_TO_VOXWARE(v) (((v) * 20 + 2) / 3)
sound/oss/dmasound/dmasound_atari.c
873
#define TONE_VOXWARE_TO_DB(v) \
sound/oss/dmasound/dmasound_atari.c
874
(((v) < 0) ? -12 : ((v) > 100) ? 12 : ((v) - 50) * 6 / 25)
sound/oss/dmasound/dmasound_atari.c
875
#define TONE_DB_TO_VOXWARE(v) (((v) * 25 + ((v) > 0 ? 5 : -5)) / 6 + 50)
sound/oss/dmasound/dmasound_atari.c
985
#define VOLUME_VOXWARE_TO_DB(v) \
sound/oss/dmasound/dmasound_atari.c
986
(((v) < 0) ? -40 : ((v) > 100) ? 0 : ((v) * 2) / 5 - 40)
sound/oss/dmasound/dmasound_atari.c
987
#define VOLUME_DB_TO_VOXWARE(v) ((((v) + 40) * 5 + 1) / 2)
sound/oss/dmasound/dmasound_paula.c
423
#define VOLUME_VOXWARE_TO_AMI(v) \
sound/oss/dmasound/dmasound_paula.c
424
(((v) < 0) ? 0 : ((v) > 100) ? 64 : ((v) * 64)/100)
sound/oss/dmasound/dmasound_paula.c
425
#define VOLUME_AMI_TO_VOXWARE(v) ((v)*100/64)
sound/parisc/harmony.c
101
harmony_write(struct snd_harmony *h, unsigned r, unsigned long v)
sound/parisc/harmony.c
103
__raw_writel(v, h->iobase + r);
sound/pci/ac97/ac97_codec.c
767
int v;
sound/pci/ac97/ac97_codec.c
768
v = new & (IEC958_AES0_CON_EMPHASIS_5015|IEC958_AES0_CON_NOT_COPYRIGHT) ? 0 : AC97_CXR_COPYRGT;
sound/pci/ac97/ac97_codec.c
769
v |= new & IEC958_AES0_NONAUDIO ? AC97_CXR_SPDIF_AC3 : AC97_CXR_SPDIF_PCM;
sound/pci/ac97/ac97_codec.c
772
v);
sound/pci/asihpi/hpi_version.h
27
#define HPI_VER_MAJOR(v) ((int)(v >> 16))
sound/pci/asihpi/hpi_version.h
29
#define HPI_VER_MINOR(v) ((int)((v >> 8) & 0xFF))
sound/pci/asihpi/hpi_version.h
31
#define HPI_VER_RELEASE(v) ((int)(v & 0xFF))
sound/pci/au88x0/au88x0.h
232
static int vortex_alsafmt_aspfmt(snd_pcm_format_t alsafmt, vortex_t *v);
sound/pci/au88x0/au88x0.h
264
static void vortex_Vort3D_enable(vortex_t * v);
sound/pci/au88x0/au88x0.h
265
static void vortex_Vort3D_disable(vortex_t * v);
sound/pci/au88x0/au88x0.h
267
static void vortex_Vort3D_InitializeSource(a3dsrc_t *a, int en, vortex_t *v);
sound/pci/au88x0/au88x0_a3d.c
475
static void a3dsrc_ZeroStateA3D(a3dsrc_t *a, vortex_t *v)
sound/pci/au88x0/au88x0_a3d.c
480
dev_err(v->card->dev,
sound/pci/au88x0/au88x0_a3d.c
542
static void vortex_A3dSourceHw_Initialize(vortex_t * v, int source, int slice)
sound/pci/au88x0/au88x0_a3d.c
544
a3dsrc_t *a3dsrc = &(v->a3d[source + (slice * 4)]);
sound/pci/au88x0/au88x0_a3d.c
547
a3dsrc->vortex = (void *)v;
sound/pci/au88x0/au88x0_a3d.c
555
static int Vort3DRend_Initialize(vortex_t * v, unsigned short mode)
sound/pci/au88x0/au88x0_a3d.c
557
v->xt_mode = mode; /* this_14 */
sound/pci/au88x0/au88x0_a3d.c
559
vortex_XtalkHw_init(v);
sound/pci/au88x0/au88x0_a3d.c
560
vortex_XtalkHw_SetGainsAllChan(v);
sound/pci/au88x0/au88x0_a3d.c
561
switch (v->xt_mode) {
sound/pci/au88x0/au88x0_a3d.c
563
vortex_XtalkHw_ProgramXtalkNarrow(v);
sound/pci/au88x0/au88x0_a3d.c
566
vortex_XtalkHw_ProgramXtalkWide(v);
sound/pci/au88x0/au88x0_a3d.c
570
vortex_XtalkHw_ProgramPipe(v);
sound/pci/au88x0/au88x0_a3d.c
573
vortex_XtalkHw_ProgramDiamondXtalk(v);
sound/pci/au88x0/au88x0_a3d.c
576
vortex_XtalkHw_SetSampleRate(v, 0x11);
sound/pci/au88x0/au88x0_a3d.c
577
vortex_XtalkHw_Enable(v);
sound/pci/au88x0/au88x0_a3d.c
586
static void vortex_Vort3D_enable(vortex_t *v)
sound/pci/au88x0/au88x0_a3d.c
590
Vort3DRend_Initialize(v, XT_HEADPHONE);
sound/pci/au88x0/au88x0_a3d.c
592
vortex_A3dSourceHw_Initialize(v, i % 4, i >> 2);
sound/pci/au88x0/au88x0_a3d.c
593
a3dsrc_ZeroStateA3D(&v->a3d[0], v);
sound/pci/au88x0/au88x0_a3d.c
596
vortex_a3d_register_controls(v);
sound/pci/au88x0/au88x0_a3d.c
599
static void vortex_Vort3D_disable(vortex_t * v)
sound/pci/au88x0/au88x0_a3d.c
601
vortex_XtalkHw_Disable(v);
sound/pci/au88x0/au88x0_a3d.c
602
vortex_a3d_unregister_controls(v);
sound/pci/au88x0/au88x0_a3d.c
606
static void vortex_Vort3D_connect(vortex_t * v, int en)
sound/pci/au88x0/au88x0_a3d.c
617
v->mixxtlk[0] =
sound/pci/au88x0/au88x0_a3d.c
618
vortex_adb_checkinout(v, v->fixed_res, en, VORTEX_RESOURCE_MIXIN);
sound/pci/au88x0/au88x0_a3d.c
619
if (v->mixxtlk[0] < 0) {
sound/pci/au88x0/au88x0_a3d.c
620
dev_warn(v->card->dev,
sound/pci/au88x0/au88x0_a3d.c
624
v->mixxtlk[1] =
sound/pci/au88x0/au88x0_a3d.c
625
vortex_adb_checkinout(v, v->fixed_res, en, VORTEX_RESOURCE_MIXIN);
sound/pci/au88x0/au88x0_a3d.c
626
if (v->mixxtlk[1] < 0) {
sound/pci/au88x0/au88x0_a3d.c
627
dev_warn(v->card->dev,
sound/pci/au88x0/au88x0_a3d.c
636
vortex_route(v, en, 0x11, ADB_A3DOUT(i * 2), ADB_XTALKIN(i));
sound/pci/au88x0/au88x0_a3d.c
637
vortex_route(v, en, 0x11, ADB_A3DOUT(i * 2) + 1, ADB_XTALKIN(5 + i));
sound/pci/au88x0/au88x0_a3d.c
640
vortex_route(v, en, 0x11, ADB_XTALKOUT(0), ADB_EQIN(2));
sound/pci/au88x0/au88x0_a3d.c
641
vortex_route(v, en, 0x11, ADB_XTALKOUT(1), ADB_EQIN(3));
sound/pci/au88x0/au88x0_a3d.c
644
vortex_route(v, en, 0x11, ADB_XTALKOUT(0), ADB_MIXIN(v->mixxtlk[0]));
sound/pci/au88x0/au88x0_a3d.c
645
vortex_route(v, en, 0x11, ADB_XTALKOUT(1), ADB_MIXIN(v->mixxtlk[1]));
sound/pci/au88x0/au88x0_a3d.c
646
vortex_connection_mixin_mix(v, en, v->mixxtlk[0], v->mixplayb[0], 0);
sound/pci/au88x0/au88x0_a3d.c
647
vortex_connection_mixin_mix(v, en, v->mixxtlk[1], v->mixplayb[1], 0);
sound/pci/au88x0/au88x0_a3d.c
648
vortex_mix_setinputvolumebyte(v, v->mixplayb[0], v->mixxtlk[0],
sound/pci/au88x0/au88x0_a3d.c
650
vortex_mix_setinputvolumebyte(v, v->mixplayb[1], v->mixxtlk[1],
sound/pci/au88x0/au88x0_a3d.c
652
if (VORTEX_IS_QUAD(v)) {
sound/pci/au88x0/au88x0_a3d.c
653
vortex_connection_mixin_mix(v, en, v->mixxtlk[0],
sound/pci/au88x0/au88x0_a3d.c
654
v->mixplayb[2], 0);
sound/pci/au88x0/au88x0_a3d.c
655
vortex_connection_mixin_mix(v, en, v->mixxtlk[1],
sound/pci/au88x0/au88x0_a3d.c
656
v->mixplayb[3], 0);
sound/pci/au88x0/au88x0_a3d.c
657
vortex_mix_setinputvolumebyte(v, v->mixplayb[2],
sound/pci/au88x0/au88x0_a3d.c
658
v->mixxtlk[0],
sound/pci/au88x0/au88x0_a3d.c
660
vortex_mix_setinputvolumebyte(v, v->mixplayb[3],
sound/pci/au88x0/au88x0_a3d.c
661
v->mixxtlk[1],
sound/pci/au88x0/au88x0_a3d.c
668
static void vortex_Vort3D_InitializeSource(a3dsrc_t *a, int en, vortex_t *v)
sound/pci/au88x0/au88x0_a3d.c
671
dev_warn(v->card->dev,
sound/pci/au88x0/au88x0_core.c
2768
static int vortex_alsafmt_aspfmt(snd_pcm_format_t alsafmt, vortex_t *v)
sound/pci/au88x0/au88x0_core.c
2796
dev_err(v->card->dev,
sound/pci/cmipci.c
1926
unsigned char v;
sound/pci/cmipci.c
1929
v = inb(s->iobase + CM_REG_SB16_DATA);
sound/pci/cmipci.c
1930
return v;
sound/pci/cmipci.c
2704
int i, v;
sound/pci/cmipci.c
2710
v = inb(cm->iobase + i);
sound/pci/cmipci.c
2713
snd_iprintf(buffer, " %02x", v);
sound/pci/cs5535audio/cs5535audio_olpc.c
102
v->value.integer.value[0] = i ? 0 : 1;
sound/pci/cs5535audio/cs5535audio_olpc.c
106
static int olpc_mic_put(struct snd_kcontrol *kctl, struct snd_ctl_elem_value *v)
sound/pci/cs5535audio/cs5535audio_olpc.c
110
olpc_mic_bias(cs5535au->ac97, v->value.integer.value[0]);
sound/pci/cs5535audio/cs5535audio_olpc.c
71
static int olpc_dc_get(struct snd_kcontrol *kctl, struct snd_ctl_elem_value *v)
sound/pci/cs5535audio/cs5535audio_olpc.c
73
v->value.integer.value[0] = gpio_get_value(OLPC_GPIO_MIC_AC);
sound/pci/cs5535audio/cs5535audio_olpc.c
77
static int olpc_dc_put(struct snd_kcontrol *kctl, struct snd_ctl_elem_value *v)
sound/pci/cs5535audio/cs5535audio_olpc.c
81
olpc_analog_input(cs5535au->ac97, v->value.integer.value[0]);
sound/pci/cs5535audio/cs5535audio_olpc.c
95
static int olpc_mic_get(struct snd_kcontrol *kctl, struct snd_ctl_elem_value *v)
sound/pci/emu10k1/emu10k1_patch.c
108
sp->v.truesize = blocksize;
sound/pci/emu10k1/emu10k1_patch.c
41
if (sp->v.mode_flags & (SNDRV_SFNT_SAMPLE_BIDIR_LOOP | SNDRV_SFNT_SAMPLE_REVERSE_LOOP)) {
sound/pci/emu10k1/emu10k1_patch.c
45
sp->v.sample);
sound/pci/emu10k1/emu10k1_patch.c
48
if (sp->v.mode_flags & SNDRV_SFNT_SAMPLE_8BITS) {
sound/pci/emu10k1/emu10k1_patch.c
51
xor = (sp->v.mode_flags & SNDRV_SFNT_SAMPLE_UNSIGNED) ? 0 : 0x80808080;
sound/pci/emu10k1/emu10k1_patch.c
55
xor = (sp->v.mode_flags & SNDRV_SFNT_SAMPLE_UNSIGNED) ? 0x80008000 : 0;
sound/pci/emu10k1/emu10k1_patch.c
59
truesize = sp->v.size + BLANK_HEAD_SIZE;
sound/pci/emu10k1/emu10k1_patch.c
60
if (sp->v.mode_flags & SNDRV_SFNT_SAMPLE_NO_BLANK) {
sound/pci/emu10k1/emu10k1_patch.c
63
if (sp->v.mode_flags & SNDRV_SFNT_SAMPLE_SINGLESHOT) {
sound/pci/emu10k1/emu10k1_patch.c
64
sp->v.loopstart = sp->v.end + BLANK_LOOP_START;
sound/pci/emu10k1/emu10k1_patch.c
65
sp->v.loopend = sp->v.end + BLANK_LOOP_END;
sound/pci/emu10k1/emu10k1_patch.c
69
loop_start = sp->v.loopstart;
sound/pci/emu10k1/emu10k1_patch.c
70
loop_end = sp->v.loopend;
sound/pci/emu10k1/emu10k1_patch.c
74
data_end = sp->v.end;
sound/pci/emu10k1/emu10k1_patch.c
77
sp->v.start += BLANK_HEAD_SIZE;
sound/pci/emu10k1/emu10k1_patch.c
78
sp->v.end += BLANK_HEAD_SIZE;
sound/pci/emu10k1/emu10k1_patch.c
79
sp->v.loopstart += BLANK_HEAD_SIZE;
sound/pci/emu10k1/emu10k1_patch.c
80
sp->v.loopend += BLANK_HEAD_SIZE;
sound/pci/emu10k1/emu10k1_patch.c
90
while (sp->v.loopend < 64) {
sound/pci/emu10k1/emu10k1_patch.c
92
sp->v.loopstart += loop_size;
sound/pci/emu10k1/emu10k1_patch.c
93
sp->v.loopend += loop_size;
sound/pci/emu10k1/emu10k1_patch.c
94
sp->v.end += loop_size;
sound/pci/emu10k1/emufx.c
1153
#define HR_VAL(v) ((v) * 0x80000000LL / 100 - 1)
sound/pci/es1938.c
288
unsigned char v;
sound/pci/es1938.c
290
v = inb(SLSB_REG(chip, READSTATUS));
sound/pci/es1938.c
291
if (!(v & 0x80)) {
sound/pci/es1938.c
297
"snd_es1938_write_cmd timeout (0x02%x/0x02%x)\n", cmd, v);
sound/pci/es1938.c
306
unsigned char v;
sound/pci/es1938.c
308
v = inb(SLSB_REG(chip, STATUS));
sound/pci/es1938.c
309
if (v & 0x80)
sound/pci/es1938.c
312
dev_err(chip->card->dev, "get_byte timeout: status 0x02%x\n", v);
sound/pci/korg1212/korg1212.c
290
} v;
sound/pci/korg1212/korg1212.c
297
} v;
sound/pci/korg1212/korg1212.c
886
sensVals.l.v.leftChanId = SET_SENS_LEFTCHANID;
sound/pci/korg1212/korg1212.c
887
sensVals.r.v.rightChanId = SET_SENS_RIGHTCHANID;
sound/pci/korg1212/korg1212.c
888
sensVals.l.v.leftChanVal = korg1212->leftADCInSens;
sound/pci/korg1212/korg1212.c
889
sensVals.r.v.rightChanVal = korg1212->rightADCInSens;
sound/pci/rme9652/hdspm.c
1194
static inline void snd_hdspm_enable_in(struct hdspm * hdspm, int i, int v)
sound/pci/rme9652/hdspm.c
1196
hdspm_write(hdspm, HDSPM_inputEnableBase + (4 * i), v);
sound/pci/rme9652/hdspm.c
1199
static inline void snd_hdspm_enable_out(struct hdspm * hdspm, int i, int v)
sound/pci/rme9652/hdspm.c
1201
hdspm_write(hdspm, HDSPM_outputEnableBase + (4 * i), v);
sound/soc/au1x/ac97c.c
126
unsigned short v)
sound/soc/au1x/ac97c.c
142
WR(ctx, AC97_CMDRESP, CMD_WRITE | CMD_IDX(r) | CMD_SET_DATA(v));
sound/soc/au1x/ac97c.c
152
pr_debug("AC97WR %04x %04x %d\n", r, v, retry);
sound/soc/au1x/ac97c.c
77
static inline void WR(struct au1xpsc_audio_data *ctx, int reg, unsigned long v)
sound/soc/au1x/ac97c.c
79
__raw_writel(v, ctx->mmio + reg);
sound/soc/au1x/i2sc.c
186
unsigned long v;
sound/soc/au1x/i2sc.c
188
v = msbits_to_reg(params->msbits);
sound/soc/au1x/i2sc.c
189
if (!v)
sound/soc/au1x/i2sc.c
193
ctx->cfg |= v;
sound/soc/au1x/i2sc.c
75
static inline void WR(struct au1xpsc_audio_data *ctx, int reg, unsigned long v)
sound/soc/au1x/i2sc.c
77
__raw_writel(v, ctx->mmio + reg);
sound/soc/bcm/bcm2835-i2s.c
100
#define BCM2835_I2S_TX(v) ((v) << 8)
sound/soc/bcm/bcm2835-i2s.c
101
#define BCM2835_I2S_RX(v) (v)
sound/soc/bcm/bcm2835-i2s.c
69
#define BCM2835_I2S_RXTHR(v) ((v) << 7)
sound/soc/bcm/bcm2835-i2s.c
70
#define BCM2835_I2S_TXTHR(v) ((v) << 5)
sound/soc/bcm/bcm2835-i2s.c
86
#define BCM2835_I2S_FLEN(v) ((v) << 10)
sound/soc/bcm/bcm2835-i2s.c
87
#define BCM2835_I2S_FSLEN(v) (v)
sound/soc/bcm/bcm2835-i2s.c
91
#define BCM2835_I2S_CHPOS(v) ((v) << 4)
sound/soc/bcm/bcm2835-i2s.c
92
#define BCM2835_I2S_CHWID(v) (v)
sound/soc/bcm/bcm2835-i2s.c
93
#define BCM2835_I2S_CH1(v) ((v) << 16)
sound/soc/bcm/bcm2835-i2s.c
94
#define BCM2835_I2S_CH2(v) (v)
sound/soc/bcm/bcm2835-i2s.c
95
#define BCM2835_I2S_CH1_POS(v) BCM2835_I2S_CH1(BCM2835_I2S_CHPOS(v))
sound/soc/bcm/bcm2835-i2s.c
96
#define BCM2835_I2S_CH2_POS(v) BCM2835_I2S_CH2(BCM2835_I2S_CHPOS(v))
sound/soc/bcm/bcm2835-i2s.c
98
#define BCM2835_I2S_TX_PANIC(v) ((v) << 24)
sound/soc/bcm/bcm2835-i2s.c
99
#define BCM2835_I2S_RX_PANIC(v) ((v) << 16)
sound/soc/codecs/cs42xx8.h
101
#define CS42XX8_FUNCMOD_xC_FM(x, v) ((x) ? CS42XX8_FUNCMOD_DAC_FM(v) : CS42XX8_FUNCMOD_ADC_FM(v))
sound/soc/codecs/cs42xx8.h
95
#define CS42XX8_FUNCMOD_DAC_FM(v) ((v) << CS42XX8_FUNCMOD_DAC_FM_SHIFT)
sound/soc/codecs/cs42xx8.h
99
#define CS42XX8_FUNCMOD_ADC_FM(v) ((v) << CS42XX8_FUNCMOD_ADC_FM_SHIFT)
sound/soc/codecs/cs43130.c
756
(clk_gen->v.denominator & CS43130_SP_M_LSB_DATA_MASK) >>
sound/soc/codecs/cs43130.c
759
(clk_gen->v.denominator & CS43130_SP_M_MSB_DATA_MASK) >>
sound/soc/codecs/cs43130.c
762
(clk_gen->v.numerator & CS43130_SP_N_LSB_DATA_MASK) >>
sound/soc/codecs/cs43130.c
765
(clk_gen->v.numerator & CS43130_SP_N_MSB_DATA_MASK) >>
sound/soc/codecs/cs43130.c
770
(clk_gen->v.denominator & CS43130_SP_M_LSB_DATA_MASK) >>
sound/soc/codecs/cs43130.c
773
(clk_gen->v.denominator & CS43130_SP_M_MSB_DATA_MASK) >>
sound/soc/codecs/cs43130.c
776
(clk_gen->v.numerator & CS43130_SP_N_LSB_DATA_MASK) >>
sound/soc/codecs/cs43130.c
779
(clk_gen->v.numerator & CS43130_SP_N_MSB_DATA_MASK) >>
sound/soc/codecs/cs43130.h
379
struct u16_fract v;
sound/soc/codecs/cs43130.h
384
{ 22579200, 32000, .v = { 10, 441, }, },
sound/soc/codecs/cs43130.h
385
{ 22579200, 44100, .v = { 1, 32, }, },
sound/soc/codecs/cs43130.h
386
{ 22579200, 48000, .v = { 5, 147, }, },
sound/soc/codecs/cs43130.h
387
{ 22579200, 88200, .v = { 1, 16, }, },
sound/soc/codecs/cs43130.h
388
{ 22579200, 96000, .v = { 10, 147, }, },
sound/soc/codecs/cs43130.h
389
{ 22579200, 176400, .v = { 1, 8, }, },
sound/soc/codecs/cs43130.h
390
{ 22579200, 192000, .v = { 20, 147, }, },
sound/soc/codecs/cs43130.h
391
{ 22579200, 352800, .v = { 1, 4, }, },
sound/soc/codecs/cs43130.h
392
{ 22579200, 384000, .v = { 40, 147, }, },
sound/soc/codecs/cs43130.h
393
{ 24576000, 32000, .v = { 1, 48, }, },
sound/soc/codecs/cs43130.h
394
{ 24576000, 44100, .v = { 147, 5120, }, },
sound/soc/codecs/cs43130.h
395
{ 24576000, 48000, .v = { 1, 32, }, },
sound/soc/codecs/cs43130.h
396
{ 24576000, 88200, .v = { 147, 2560, }, },
sound/soc/codecs/cs43130.h
397
{ 24576000, 96000, .v = { 1, 16, }, },
sound/soc/codecs/cs43130.h
398
{ 24576000, 176400, .v = { 147, 1280, }, },
sound/soc/codecs/cs43130.h
399
{ 24576000, 192000, .v = { 1, 8, }, },
sound/soc/codecs/cs43130.h
400
{ 24576000, 352800, .v = { 147, 640, }, },
sound/soc/codecs/cs43130.h
401
{ 24576000, 384000, .v = { 1, 4, }, },
sound/soc/codecs/cs43130.h
406
{ 22579200, 32000, .v = { 20, 441, }, },
sound/soc/codecs/cs43130.h
407
{ 22579200, 44100, .v = { 1, 16, }, },
sound/soc/codecs/cs43130.h
408
{ 22579200, 48000, .v = { 10, 147, }, },
sound/soc/codecs/cs43130.h
409
{ 22579200, 88200, .v = { 1, 8, }, },
sound/soc/codecs/cs43130.h
410
{ 22579200, 96000, .v = { 20, 147, }, },
sound/soc/codecs/cs43130.h
411
{ 22579200, 176400, .v = { 1, 4, }, },
sound/soc/codecs/cs43130.h
412
{ 22579200, 192000, .v = { 40, 147, }, },
sound/soc/codecs/cs43130.h
413
{ 22579200, 352800, .v = { 1, 2, }, },
sound/soc/codecs/cs43130.h
414
{ 22579200, 384000, .v = { 80, 147, }, },
sound/soc/codecs/cs43130.h
415
{ 24576000, 32000, .v = { 1, 24, }, },
sound/soc/codecs/cs43130.h
416
{ 24576000, 44100, .v = { 147, 2560, }, },
sound/soc/codecs/cs43130.h
417
{ 24576000, 48000, .v = { 1, 16, }, },
sound/soc/codecs/cs43130.h
418
{ 24576000, 88200, .v = { 147, 1280, }, },
sound/soc/codecs/cs43130.h
419
{ 24576000, 96000, .v = { 1, 8, }, },
sound/soc/codecs/cs43130.h
420
{ 24576000, 176400, .v = { 147, 640, }, },
sound/soc/codecs/cs43130.h
421
{ 24576000, 192000, .v = { 1, 4, }, },
sound/soc/codecs/cs43130.h
422
{ 24576000, 352800, .v = { 147, 320, }, },
sound/soc/codecs/cs43130.h
423
{ 24576000, 384000, .v = { 1, 2, }, },
sound/soc/codecs/cs43130.h
428
{ 22579200, 32000, .v = { 100, 147, }, },
sound/soc/codecs/cs43130.h
429
{ 22579200, 44100, .v = { 3, 32, }, },
sound/soc/codecs/cs43130.h
430
{ 22579200, 48000, .v = { 5, 49, }, },
sound/soc/codecs/cs43130.h
431
{ 22579200, 88200, .v = { 3, 16, }, },
sound/soc/codecs/cs43130.h
432
{ 22579200, 96000, .v = { 10, 49, }, },
sound/soc/codecs/cs43130.h
433
{ 22579200, 176400, .v = { 3, 8, }, },
sound/soc/codecs/cs43130.h
434
{ 22579200, 192000, .v = { 20, 49, }, },
sound/soc/codecs/cs43130.h
435
{ 22579200, 352800, .v = { 3, 4, }, },
sound/soc/codecs/cs43130.h
436
{ 22579200, 384000, .v = { 40, 49, }, },
sound/soc/codecs/cs43130.h
437
{ 24576000, 32000, .v = { 1, 16, }, },
sound/soc/codecs/cs43130.h
438
{ 24576000, 44100, .v = { 441, 5120, }, },
sound/soc/codecs/cs43130.h
439
{ 24576000, 48000, .v = { 3, 32, }, },
sound/soc/codecs/cs43130.h
440
{ 24576000, 88200, .v = { 441, 2560, }, },
sound/soc/codecs/cs43130.h
441
{ 24576000, 96000, .v = { 3, 16, }, },
sound/soc/codecs/cs43130.h
442
{ 24576000, 176400, .v = { 441, 1280, }, },
sound/soc/codecs/cs43130.h
443
{ 24576000, 192000, .v = { 3, 8, }, },
sound/soc/codecs/cs43130.h
444
{ 24576000, 352800, .v = { 441, 640, }, },
sound/soc/codecs/cs43130.h
445
{ 24576000, 384000, .v = { 3, 4, }, },
sound/soc/codecs/cs43130.h
450
{ 22579200, 32000, .v = { 40, 441, }, },
sound/soc/codecs/cs43130.h
451
{ 22579200, 44100, .v = { 1, 8, }, },
sound/soc/codecs/cs43130.h
452
{ 22579200, 48000, .v = { 20, 147, }, },
sound/soc/codecs/cs43130.h
453
{ 22579200, 88200, .v = { 1, 4, }, },
sound/soc/codecs/cs43130.h
454
{ 22579200, 96000, .v = { 40, 147, }, },
sound/soc/codecs/cs43130.h
455
{ 22579200, 176400, .v = { 1, 2, }, },
sound/soc/codecs/cs43130.h
456
{ 22579200, 192000, .v = { 80, 147, }, },
sound/soc/codecs/cs43130.h
457
{ 22579200, 352800, .v = { 1, 1, }, },
sound/soc/codecs/cs43130.h
458
{ 24576000, 32000, .v = { 1, 12, }, },
sound/soc/codecs/cs43130.h
459
{ 24576000, 44100, .v = { 147, 1280, }, },
sound/soc/codecs/cs43130.h
460
{ 24576000, 48000, .v = { 1, 8, }, },
sound/soc/codecs/cs43130.h
461
{ 24576000, 88200, .v = { 147, 640, }, },
sound/soc/codecs/cs43130.h
462
{ 24576000, 96000, .v = { 1, 4, }, },
sound/soc/codecs/cs43130.h
463
{ 24576000, 176400, .v = { 147, 320, }, },
sound/soc/codecs/cs43130.h
464
{ 24576000, 192000, .v = { 1, 2, }, },
sound/soc/codecs/cs43130.h
465
{ 24576000, 352800, .v = { 147, 160, }, },
sound/soc/codecs/cs43130.h
466
{ 24576000, 384000, .v = { 1, 1, }, },
sound/soc/codecs/cs47l24.c
64
unsigned int v;
sound/soc/codecs/cs47l24.c
67
ret = regmap_read(arizona->regmap, ARIZONA_SYSTEM_CLOCK_1, &v);
sound/soc/codecs/cs47l24.c
73
v = (v & ARIZONA_SYSCLK_FREQ_MASK) >> ARIZONA_SYSCLK_FREQ_SHIFT;
sound/soc/codecs/cs47l24.c
75
wm_adsp2_set_dspclk(w, v);
sound/soc/codecs/msm8916-wcd-analog.c
109
#define MICB_VOLTAGE_REGVAL(v) (((v - MICB_MIN_VAL)/MICB_STEP_SIZE) << 3)
sound/soc/codecs/mt6359-accdet.c
330
static unsigned int check_button(struct mt6359_accdet *priv, unsigned int v)
sound/soc/codecs/mt6359-accdet.c
333
if (v < priv->data->four_key.down &&
sound/soc/codecs/mt6359-accdet.c
334
v >= priv->data->four_key.up)
sound/soc/codecs/mt6359-accdet.c
336
if (v < priv->data->four_key.up &&
sound/soc/codecs/mt6359-accdet.c
337
v >= priv->data->four_key.voice)
sound/soc/codecs/mt6359-accdet.c
339
if (v < priv->data->four_key.voice &&
sound/soc/codecs/mt6359-accdet.c
340
v >= priv->data->four_key.mid)
sound/soc/codecs/mt6359-accdet.c
342
if (v < priv->data->four_key.mid)
sound/soc/codecs/mt6359-accdet.c
345
if (v < priv->data->three_key.down &&
sound/soc/codecs/mt6359-accdet.c
346
v >= priv->data->three_key.up)
sound/soc/codecs/mt6359-accdet.c
348
if (v < priv->data->three_key.up &&
sound/soc/codecs/mt6359-accdet.c
349
v >= priv->data->three_key.mid)
sound/soc/codecs/mt6359-accdet.c
351
if (v < priv->data->three_key.mid)
sound/soc/codecs/rt5677.c
4718
static int rt5677_update_gpio_bits(struct rt5677_priv *rt5677, unsigned offset, int m, int v)
sound/soc/codecs/rt5677.c
4724
return regmap_update_bits(rt5677->regmap, reg, m << shift, v << shift);
sound/soc/codecs/rt5677.c
4744
int v = RT5677_GPIOx_DIR_OUT | level;
sound/soc/codecs/rt5677.c
4746
return rt5677_update_gpio_bits(rt5677, offset, m, v);
sound/soc/codecs/rt5677.c
4765
int v = RT5677_GPIOx_DIR_IN;
sound/soc/codecs/rt5677.c
4767
return rt5677_update_gpio_bits(rt5677, offset, m, v);
sound/soc/codecs/tas5805m.c
176
uint8_t v[4];
sound/soc/codecs/tas5805m.c
181
v[3 - i] = x;
sound/soc/codecs/tas5805m.c
185
regmap_bulk_write(rm, offset, v, ARRAY_SIZE(v));
sound/soc/codecs/tas5805m.c
241
static inline int volume_is_valid(int v)
sound/soc/codecs/tas5805m.c
243
return (v >= TAS5805M_VOLUME_MIN) && (v <= TAS5805M_VOLUME_MAX);
sound/soc/codecs/tlv320adcx140.c
673
bool v = value->value.integer.value[0] ? true : false;
sound/soc/codecs/tlv320adcx140.c
675
if (adcx140->phase_calib_on != v) {
sound/soc/codecs/tlv320adcx140.c
676
adcx140->phase_calib_on = v;
sound/soc/codecs/tscs42xx.h
115
#define RV(v, b) ((v)<<(b))
sound/soc/codecs/wcd939x.c
67
#define WCD_VOUT_CTL_TO_MICB(v) (1000 + (v) * 50)
sound/soc/codecs/wm5102.c
624
unsigned int v = 0;
sound/soc/codecs/wm5102.c
629
ret = regmap_read(arizona->regmap, ARIZONA_SYSTEM_CLOCK_1, &v);
sound/soc/codecs/wm5102.c
636
v = (v & ARIZONA_SYSCLK_FREQ_MASK) >> ARIZONA_SYSCLK_FREQ_SHIFT;
sound/soc/codecs/wm5102.c
638
if (v >= 3) {
sound/soc/codecs/wm5102.c
647
wm_adsp2_set_dspclk(w, v);
sound/soc/codecs/wm5110.c
200
unsigned int v;
sound/soc/codecs/wm5110.c
203
ret = regmap_read(arizona->regmap, ARIZONA_SYSTEM_CLOCK_1, &v);
sound/soc/codecs/wm5110.c
209
v = (v & ARIZONA_SYSCLK_FREQ_MASK) >> ARIZONA_SYSCLK_FREQ_SHIFT;
sound/soc/codecs/wm5110.c
211
wm_adsp2_set_dspclk(w, v);
sound/soc/fsl/fsl_asrc.h
125
#define ASRCNCR_ANCi(i, v, b) ((v << ASRCNCR_ANCi_SHIFT(i, b)) & ASRCNCR_ANCi_MASK(i, b))
sound/soc/fsl/fsl_asrc.h
140
#define ASRCFG_POSTMOD(i, v) ((v) << ASRCFG_POSTMODi_SHIFT(i))
sound/soc/fsl/fsl_asrc.h
148
#define ASRCFG_PREMOD(i, v) ((v) << ASRCFG_PREMODi_SHIFT(i))
sound/soc/fsl/fsl_asrc.h
159
#define ASRCSR_AOCS(i, v) ((v) << ASRCSR_AOCSi_SHIFT(i))
sound/soc/fsl/fsl_asrc.h
162
#define ASRCSR_AICS(i, v) ((v) << ASRCSR_AICSi_SHIFT(i))
sound/soc/fsl/fsl_asrc.h
168
#define ASRCDRi_AICP(i, v) ((v) << ASRCDRi_AICPi_SHIFT(i))
sound/soc/fsl/fsl_asrc.h
171
#define ASRCDRi_AICD(i, v) ((v) << ASRCDRi_AICDi_SHIFT(i))
sound/soc/fsl/fsl_asrc.h
174
#define ASRCDRi_AOCP(i, v) ((v) << ASRCDRi_AOCPi_SHIFT(i))
sound/soc/fsl/fsl_asrc.h
177
#define ASRCDRi_AOCD(i, v) ((v) << ASRCDRi_AOCDi_SHIFT(i))
sound/soc/fsl/fsl_asrc.h
237
#define ASRMCRi_OUTFIFO_THRESHOLD(v) (((v) << ASRMCRi_OUTFIFO_THRESHOLD_SHIFT) & ASRMCRi_OUTFIFO_THRESHOLD_MASK)
sound/soc/fsl/fsl_asrc.h
247
#define ASRMCRi_INFIFO_THRESHOLD(v) (((v) << ASRMCRi_INFIFO_THRESHOLD_SHIFT) & ASRMCRi_INFIFO_THRESHOLD_MASK)
sound/soc/fsl/fsl_asrc.h
260
#define ASRFSTi_OUTPUT_FIFO_FILL(v) \
sound/soc/fsl/fsl_asrc.h
261
(((v) & ASRFSTi_OUTPUT_FIFO_MASK) >> ASRFSTi_OUTPUT_FIFO_SHIFT)
sound/soc/fsl/fsl_asrc.h
273
#define ASRMCR1i_IWD(v) ((v) << ASRMCR1i_IWD_SHIFT)
sound/soc/fsl/fsl_asrc.h
287
#define ASRMCR1i_OW16(v) ((v) << ASRMCR1i_OW16_SHIFT)
sound/soc/fsl/fsl_easrc.h
100
#define EASRC_CC_FIFO_WTMK(v) (((v) << EASRC_CC_FIFO_WTMK_SHIFT) \
sound/soc/fsl/fsl_easrc.h
106
#define EASRC_CC_SAMPLE_POS(v) (((v) << EASRC_CC_SAMPLE_POS_SHIFT) \
sound/soc/fsl/fsl_easrc.h
115
#define EASRC_CC_BPS(v) (((v) << EASRC_CC_BPS_SHIFT) \
sound/soc/fsl/fsl_easrc.h
127
#define EASRC_CC_CHEN(v) (((v) << EASRC_CC_CHEN_SHIFT) \
sound/soc/fsl/fsl_easrc.h
141
#define EASRC_CCE1_PF_EXP(v) (((v) << EASRC_CCE1_PF_EXP_SHIFT) \
sound/soc/fsl/fsl_easrc.h
165
#define EASRC_CCE1_RS_INIT(v) (((v) << EASRC_CCE1_RS_INIT_SHIFT) \
sound/soc/fsl/fsl_easrc.h
171
#define EASRC_CCE1_PF_INIT(v) (((v) << EASRC_CCE1_PF_INIT_SHIFT) \
sound/soc/fsl/fsl_easrc.h
179
#define EASRC_CCE2_ST2_TAPS(v) (((v) << EASRC_CCE2_ST2_TAPS_SHIFT) \
sound/soc/fsl/fsl_easrc.h
185
#define EASRC_CCE2_ST1_TAPS(v) (((v) << EASRC_CCE2_ST1_TAPS_SHIFT) \
sound/soc/fsl/fsl_easrc.h
193
#define EASRC_CIA_ITER(v) (((v) << EASRC_CIA_ITER_SHIFT) \
sound/soc/fsl/fsl_easrc.h
199
#define EASRC_CIA_GRLEN(v) (((v) << EASRC_CIA_GRLEN_SHIFT) \
sound/soc/fsl/fsl_easrc.h
205
#define EASRC_CIA_ACCLEN(v) (((v) << EASRC_CIA_ACCLEN_SHIFT) \
sound/soc/fsl/fsl_easrc.h
213
#define EASRC_DPCS0R0_MAXCH(v) (((v) << EASRC_DPCS0R0_MAXCH_SHIFT) \
sound/soc/fsl/fsl_easrc.h
219
#define EASRC_DPCS0R0_MINCH(v) (((v) << EASRC_DPCS0R0_MINCH_SHIFT) \
sound/soc/fsl/fsl_easrc.h
225
#define EASRC_DPCS0R0_NUMCH(v) (((v) << EASRC_DPCS0R0_NUMCH_SHIFT) \
sound/soc/fsl/fsl_easrc.h
231
#define EASRC_DPCS0R0_CTXNUM(v) (((v) << EASRC_DPCS0R0_CTXNUM_SHIFT) \
sound/soc/fsl/fsl_easrc.h
242
#define EASRC_DPCS0R1_ST1_EXP(v) (((v) << EASRC_DPCS0R1_ST1_EXP_SHIFT) \
sound/soc/fsl/fsl_easrc.h
250
#define EASRC_DPCS0R2_ST1_MA(v) (((v) << EASRC_DPCS0R2_ST1_MA_SHIFT) \
sound/soc/fsl/fsl_easrc.h
256
#define EASRC_DPCS0R2_ST1_SA(v) (((v) << EASRC_DPCS0R2_ST1_SA_SHIFT) \
sound/soc/fsl/fsl_easrc.h
264
#define EASRC_DPCS0R3_ST2_MA(v) (((v) << EASRC_DPCS0R3_ST2_MA_SHIFT) \
sound/soc/fsl/fsl_easrc.h
270
#define EASRC_DPCS0R3_ST2_SA(v) (((v) << EASRC_DPCS0R3_ST2_SA_SHIFT) \
sound/soc/fsl/fsl_easrc.h
281
#define EASRC_COC_FIFO_WTMK(v) (((v) << EASRC_COC_FIFO_WTMK_SHIFT) \
sound/soc/fsl/fsl_easrc.h
287
#define EASRC_COC_SAMPLE_POS(v) (((v) << EASRC_COC_SAMPLE_POS_SHIFT) \
sound/soc/fsl/fsl_easrc.h
296
#define EASRC_COC_BPS(v) (((v) << EASRC_COC_BPS_SHIFT) \
sound/soc/fsl/fsl_easrc.h
319
#define EASRC_COA_ITER(v) (((v) << EASRC_COA_ITER_SHIFT) \
sound/soc/fsl/fsl_easrc.h
325
#define EASRC_COA_GRLEN(v) (((v) << EASRC_COA_GRLEN_SHIFT) \
sound/soc/fsl/fsl_easrc.h
331
#define EASRC_COA_ACCLEN(v) (((v) << EASRC_COA_ACCLEN_SHIFT) \
sound/soc/fsl/fsl_easrc.h
342
#define EASRC_SFS_NSGI(v) (((v) << EASRC_SFS_NSGI_SHIFT) \
sound/soc/fsl/fsl_easrc.h
351
#define EASRC_SFS_NSGO(v) (((v) << EASRC_SFS_NSGO_SHIFT) \
sound/soc/fsl/fsl_easrc.h
357
#define EASRC_RRL_RS_RL(v) ((v) << EASRC_RRL_RS_RL_SHIFT)
sound/soc/fsl/fsl_easrc.h
367
#define EASRC_RRH_RS_RH(v) (((v) << EASRC_RRH_RS_RH_SHIFT) \
sound/soc/fsl/fsl_easrc.h
373
#define EASRC_RSUC_RS_RM(v) ((v) << EASRC_RSUC_RS_RM_SHIFT)
sound/soc/fsl/fsl_easrc.h
380
#define EASRC_RRUR_RRR(v) (((v) << EASRC_RRUR_RRR_SHIFT) \
sound/soc/fsl/fsl_easrc.h
386
#define EASRC_RCTCL_RS_CL(v) ((v) << EASRC_RCTCL_RS_CL_SHIFT)
sound/soc/fsl/fsl_easrc.h
391
#define EASRC_RCTCH_RS_CH(v) ((v) << EASRC_RCTCH_RS_CH_SHIFT)
sound/soc/fsl/fsl_easrc.h
396
#define EASRC_PCF_CD(v) ((v) << EASRC_PCF_CD_SHIFT)
sound/soc/fsl/fsl_easrc.h
401
#define EASRC_CRCM_RS_CWD(v) ((v) << EASRC_CRCM_RS_CWD_SHIFT)
sound/soc/fsl/fsl_easrc.h
408
#define EASRC_CRCC_RS_CA(v) (((v) << EASRC_CRCC_RS_CA_SHIFT) \
sound/soc/fsl/fsl_easrc.h
414
#define EASRC_CRCC_RS_TAPS(v) (((v) << EASRC_CRCC_RS_TAPS_SHIFT) \
sound/soc/fsl/fsl_easrc.h
425
#define EASRC_IRQC_RSDM(v) (((v) << EASRC_IRQC_RSDM_SHIFT) \
sound/soc/fsl/fsl_easrc.h
431
#define EASRC_IRQC_OERM(v) (((v) << EASRC_IRQC_OERM_SHIFT) \
sound/soc/fsl/fsl_easrc.h
437
#define EASRC_IRQC_IOM(v) (((v) << EASRC_IRQC_IOM_SHIFT) \
sound/soc/fsl/fsl_easrc.h
445
#define EASRC_IRQF_RSD(v) (((v) << EASRC_IRQF_RSD_SHIFT) \
sound/soc/fsl/fsl_easrc.h
451
#define EASRC_IRQF_OER(v) (((v) << EASRC_IRQF_OER_SHIFT) \
sound/soc/fsl/fsl_easrc.h
457
#define EASRC_IRQF_IFO(v) (((v) << EASRC_IRQF_IFO_SHIFT) \
sound/soc/fsl/fsl_easrc.h
463
#define EASRC_CSx_CSx(v) ((v) << EASRC_CSx_CSx_SHIFT)
sound/soc/fsl/fsl_easrc.h
470
#define EASRC_DBGC_DMS(v) (((v) << EASRC_DBGC_DMS_SHIFT) \
sound/soc/fsl/fsl_easrc.h
476
#define EASRC_DBGS_DS(v) ((v) << EASRC_DBGS_DS_SHIFT)
sound/soc/fsl/fsl_esai.h
120
#define ESAI_xFCR_xWA(v) (((8 - ((v) >> 2)) << ESAI_xFCR_xWA_SHIFT) & ESAI_xFCR_xWA_MASK)
sound/soc/fsl/fsl_esai.h
124
#define ESAI_xFCR_xFWM(v) ((((v) - 1) << ESAI_xFCR_xFWM_SHIFT) & ESAI_xFCR_xFWM_MASK)
sound/soc/fsl/fsl_esai.h
300
#define ESAI_xCCR_xFP(v) ((((v) - 1) << ESAI_xCCR_xFP_SHIFT) & ESAI_xCCR_xFP_MASK)
sound/soc/fsl/fsl_esai.h
304
#define ESAI_xCCR_xDC(v) ((((v) - 1) << ESAI_xCCR_xDC_SHIFT) & ESAI_xCCR_xDC_MASK)
sound/soc/fsl/fsl_esai.h
312
#define ESAI_xCCR_xPM(v) ((((v) - 1) << ESAI_xCCR_xPM_SHIFT) & ESAI_xCCR_xPM_MASK)
sound/soc/fsl/fsl_esai.h
318
#define ESAI_xSMA_xS(v) ((v) & ESAI_xSMA_xS_MASK)
sound/soc/fsl/fsl_esai.h
322
#define ESAI_xSMB_xS(v) (((v) >> ESAI_xSMA_xS_WIDTH) & ESAI_xSMB_xS_MASK)
sound/soc/fsl/fsl_esai.h
328
#define ESAI_PRRC_PDC(v) ((v) & ESAI_PRRC_PDC_MASK)
sound/soc/fsl/fsl_esai.h
334
#define ESAI_PCRC_PC(v) ((v) & ESAI_PCRC_PC_MASK)
sound/soc/fsl/fsl_micfil.h
159
#define MICFIL_OUTGAIN_CHX_SHIFT(v) (4 * (v))
sound/soc/fsl/fsl_xcvr.h
271
#define FSL_XCVR_PLL_PDIVx(v, i) ((v & 0x7) << (4 * i))
sound/soc/mxs/mxs-saif.h
20
#define BF_SAIF_CTRL_BITCLK_MULT_RATE(v) \
sound/soc/mxs/mxs-saif.h
21
(((v) << 27) & BM_SAIF_CTRL_BITCLK_MULT_RATE)
sound/soc/mxs/mxs-saif.h
30
#define BF_SAIF_CTRL_DMAWAIT_COUNT(v) \
sound/soc/mxs/mxs-saif.h
31
(((v) << 16) & BM_SAIF_CTRL_DMAWAIT_COUNT)
sound/soc/mxs/mxs-saif.h
34
#define BF_SAIF_CTRL_CHANNEL_NUM_SELECT(v) \
sound/soc/mxs/mxs-saif.h
35
(((v) << 14) & BM_SAIF_CTRL_CHANNEL_NUM_SELECT)
sound/soc/mxs/mxs-saif.h
44
#define BF_SAIF_CTRL_WORD_LENGTH(v) \
sound/soc/mxs/mxs-saif.h
45
(((v) << 4) & BM_SAIF_CTRL_WORD_LENGTH)
sound/soc/mxs/mxs-saif.h
55
#define BF_SAIF_STAT_RSRVD2(v) \
sound/soc/mxs/mxs-saif.h
56
(((v) << 17) & BM_SAIF_STAT_RSRVD2)
sound/soc/mxs/mxs-saif.h
60
#define BF_SAIF_STAT_RSRVD1(v) \
sound/soc/mxs/mxs-saif.h
61
(((v) << 7) & BM_SAIF_STAT_RSRVD1)
sound/soc/mxs/mxs-saif.h
68
#define BF_SAIF_STAT_RSRVD0(v) \
sound/soc/mxs/mxs-saif.h
69
(((v) << 1) & BM_SAIF_STAT_RSRVD0)
sound/soc/mxs/mxs-saif.h
75
#define BF_SAIF_DATA_PCM_RIGHT(v) \
sound/soc/mxs/mxs-saif.h
76
(((v) << 16) & BM_SAIF_DATA_PCM_RIGHT)
sound/soc/mxs/mxs-saif.h
79
#define BF_SAIF_DATA_PCM_LEFT(v) \
sound/soc/mxs/mxs-saif.h
80
(((v) << 0) & BM_SAIF_DATA_PCM_LEFT)
sound/soc/mxs/mxs-saif.h
85
#define BF_SAIF_VERSION_MAJOR(v) \
sound/soc/mxs/mxs-saif.h
86
(((v) << 24) & BM_SAIF_VERSION_MAJOR)
sound/soc/mxs/mxs-saif.h
89
#define BF_SAIF_VERSION_MINOR(v) \
sound/soc/mxs/mxs-saif.h
90
(((v) << 16) & BM_SAIF_VERSION_MINOR)
sound/soc/mxs/mxs-saif.h
93
#define BF_SAIF_VERSION_STEP(v) \
sound/soc/mxs/mxs-saif.h
94
(((v) << 0) & BM_SAIF_VERSION_STEP)
sound/soc/qcom/lpass-apq8016.c
126
const struct lpass_variant *v = drvdata->variant;
sound/soc/qcom/lpass-apq8016.c
131
v->rdma_channels);
sound/soc/qcom/lpass-apq8016.c
133
if (chan >= v->rdma_channels)
sound/soc/qcom/lpass-apq8016.c
137
v->wrdma_channel_start +
sound/soc/qcom/lpass-apq8016.c
138
v->wrdma_channels,
sound/soc/qcom/lpass-apq8016.c
139
v->wrdma_channel_start);
sound/soc/qcom/lpass-apq8016.c
141
if (chan >= v->wrdma_channel_start + v->wrdma_channels)
sound/soc/qcom/lpass-cdc-dma.c
41
const struct lpass_variant *v = drvdata->variant;
sound/soc/qcom/lpass-cdc-dma.c
51
*id = pcm_data->dma_ch - v->rxtx_wrdma_channel_start;
sound/soc/qcom/lpass-cdc-dma.c
55
*id = pcm_data->dma_ch - v->va_wrdma_channel_start;
sound/soc/qcom/lpass-cpu.c
47
const struct lpass_variant *v = drvdata->variant;
sound/soc/qcom/lpass-cpu.c
49
i2sctl->loopback = devm_regmap_field_alloc(dev, map, v->loopback);
sound/soc/qcom/lpass-cpu.c
491
const struct lpass_variant *v = drvdata->variant;
sound/soc/qcom/lpass-cpu.c
494
for (i = 0; i < v->i2s_ports; ++i)
sound/soc/qcom/lpass-cpu.c
495
if (reg == LPAIF_I2SCTL_REG(v, i))
sound/soc/qcom/lpass-cpu.c
498
for (i = 0; i < v->irq_ports; ++i) {
sound/soc/qcom/lpass-cpu.c
499
if (reg == LPAIF_IRQEN_REG(v, i))
sound/soc/qcom/lpass-cpu.c
50
i2sctl->spken = devm_regmap_field_alloc(dev, map, v->spken);
sound/soc/qcom/lpass-cpu.c
501
if (reg == LPAIF_IRQCLEAR_REG(v, i))
sound/soc/qcom/lpass-cpu.c
505
for (i = 0; i < v->rdma_channels; ++i) {
sound/soc/qcom/lpass-cpu.c
506
if (reg == LPAIF_RDMACTL_REG(v, i))
sound/soc/qcom/lpass-cpu.c
508
if (reg == LPAIF_RDMABASE_REG(v, i))
sound/soc/qcom/lpass-cpu.c
51
i2sctl->spkmode = devm_regmap_field_alloc(dev, map, v->spkmode);
sound/soc/qcom/lpass-cpu.c
510
if (reg == LPAIF_RDMABUFF_REG(v, i))
sound/soc/qcom/lpass-cpu.c
512
if (reg == LPAIF_RDMAPER_REG(v, i))
sound/soc/qcom/lpass-cpu.c
516
for (i = 0; i < v->wrdma_channels; ++i) {
sound/soc/qcom/lpass-cpu.c
517
if (reg == LPAIF_WRDMACTL_REG(v, i + v->wrdma_channel_start))
sound/soc/qcom/lpass-cpu.c
519
if (reg == LPAIF_WRDMABASE_REG(v, i + v->wrdma_channel_start))
sound/soc/qcom/lpass-cpu.c
52
i2sctl->spkmono = devm_regmap_field_alloc(dev, map, v->spkmono);
sound/soc/qcom/lpass-cpu.c
521
if (reg == LPAIF_WRDMABUFF_REG(v, i + v->wrdma_channel_start))
sound/soc/qcom/lpass-cpu.c
523
if (reg == LPAIF_WRDMAPER_REG(v, i + v->wrdma_channel_start))
sound/soc/qcom/lpass-cpu.c
53
i2sctl->micen = devm_regmap_field_alloc(dev, map, v->micen);
sound/soc/qcom/lpass-cpu.c
533
const struct lpass_variant *v = drvdata->variant;
sound/soc/qcom/lpass-cpu.c
536
for (i = 0; i < v->i2s_ports; ++i)
sound/soc/qcom/lpass-cpu.c
537
if (reg == LPAIF_I2SCTL_REG(v, i))
sound/soc/qcom/lpass-cpu.c
54
i2sctl->micmode = devm_regmap_field_alloc(dev, map, v->micmode);
sound/soc/qcom/lpass-cpu.c
540
for (i = 0; i < v->irq_ports; ++i) {
sound/soc/qcom/lpass-cpu.c
541
if (reg == LPAIF_IRQCLEAR_REG(v, i))
sound/soc/qcom/lpass-cpu.c
543
if (reg == LPAIF_IRQEN_REG(v, i))
sound/soc/qcom/lpass-cpu.c
545
if (reg == LPAIF_IRQSTAT_REG(v, i))
sound/soc/qcom/lpass-cpu.c
549
for (i = 0; i < v->rdma_channels; ++i) {
sound/soc/qcom/lpass-cpu.c
55
i2sctl->micmono = devm_regmap_field_alloc(dev, map, v->micmono);
sound/soc/qcom/lpass-cpu.c
550
if (reg == LPAIF_RDMACTL_REG(v, i))
sound/soc/qcom/lpass-cpu.c
552
if (reg == LPAIF_RDMABASE_REG(v, i))
sound/soc/qcom/lpass-cpu.c
554
if (reg == LPAIF_RDMABUFF_REG(v, i))
sound/soc/qcom/lpass-cpu.c
556
if (reg == LPAIF_RDMACURR_REG(v, i))
sound/soc/qcom/lpass-cpu.c
558
if (reg == LPAIF_RDMAPER_REG(v, i))
sound/soc/qcom/lpass-cpu.c
56
i2sctl->wssrc = devm_regmap_field_alloc(dev, map, v->wssrc);
sound/soc/qcom/lpass-cpu.c
562
for (i = 0; i < v->wrdma_channels; ++i) {
sound/soc/qcom/lpass-cpu.c
563
if (reg == LPAIF_WRDMACTL_REG(v, i + v->wrdma_channel_start))
sound/soc/qcom/lpass-cpu.c
565
if (reg == LPAIF_WRDMABASE_REG(v, i + v->wrdma_channel_start))
sound/soc/qcom/lpass-cpu.c
567
if (reg == LPAIF_WRDMABUFF_REG(v, i + v->wrdma_channel_start))
sound/soc/qcom/lpass-cpu.c
569
if (reg == LPAIF_WRDMACURR_REG(v, i + v->wrdma_channel_start))
sound/soc/qcom/lpass-cpu.c
57
i2sctl->bitwidth = devm_regmap_field_alloc(dev, map, v->bitwidth);
sound/soc/qcom/lpass-cpu.c
571
if (reg == LPAIF_WRDMAPER_REG(v, i + v->wrdma_channel_start))
sound/soc/qcom/lpass-cpu.c
581
const struct lpass_variant *v = drvdata->variant;
sound/soc/qcom/lpass-cpu.c
584
for (i = 0; i < v->irq_ports; ++i) {
sound/soc/qcom/lpass-cpu.c
585
if (reg == LPAIF_IRQCLEAR_REG(v, i))
sound/soc/qcom/lpass-cpu.c
587
if (reg == LPAIF_IRQSTAT_REG(v, i))
sound/soc/qcom/lpass-cpu.c
591
for (i = 0; i < v->rdma_channels; ++i)
sound/soc/qcom/lpass-cpu.c
592
if (reg == LPAIF_RDMACURR_REG(v, i))
sound/soc/qcom/lpass-cpu.c
595
for (i = 0; i < v->wrdma_channels; ++i)
sound/soc/qcom/lpass-cpu.c
596
if (reg == LPAIF_WRDMACURR_REG(v, i + v->wrdma_channel_start))
sound/soc/qcom/lpass-cpu.c
616
const struct lpass_variant *v = drvdata->variant;
sound/soc/qcom/lpass-cpu.c
633
QCOM_REGMAP_FIELD_ALLOC(dev, map, v->soft_reset, tx_ctl->soft_reset);
sound/soc/qcom/lpass-cpu.c
634
QCOM_REGMAP_FIELD_ALLOC(dev, map, v->force_reset, tx_ctl->force_reset);
sound/soc/qcom/lpass-cpu.c
637
QCOM_REGMAP_FIELD_ALLOC(dev, map, v->legacy_en, legacy_en);
sound/soc/qcom/lpass-cpu.c
644
QCOM_REGMAP_FIELD_ALLOC(dev, map, v->replace_vbit, vbit_ctl->replace_vbit);
sound/soc/qcom/lpass-cpu.c
645
QCOM_REGMAP_FIELD_ALLOC(dev, map, v->vbit_stream, vbit_ctl->vbit_stream);
sound/soc/qcom/lpass-cpu.c
649
QCOM_REGMAP_FIELD_ALLOC(dev, map, v->calc_en, tx_parity);
sound/soc/qcom/lpass-cpu.c
656
rval = devm_regmap_field_bulk_alloc(dev, map, &meta_ctl->mute, &v->mute, 7);
sound/soc/qcom/lpass-cpu.c
665
rval = devm_regmap_field_bulk_alloc(dev, map, &sstream_ctl->sstream_en, &v->sstream_en, 9);
sound/soc/qcom/lpass-cpu.c
672
QCOM_REGMAP_FIELD_ALLOC(dev, map, v->msb_bits, ch_msb);
sound/soc/qcom/lpass-cpu.c
675
QCOM_REGMAP_FIELD_ALLOC(dev, map, v->lsb_bits, ch_lsb);
sound/soc/qcom/lpass-cpu.c
682
QCOM_REGMAP_FIELD_ALLOC(dev, map, v->use_hw_chs, tx_dmactl->use_hw_chs);
sound/soc/qcom/lpass-cpu.c
683
QCOM_REGMAP_FIELD_ALLOC(dev, map, v->use_hw_usr, tx_dmactl->use_hw_usr);
sound/soc/qcom/lpass-cpu.c
684
QCOM_REGMAP_FIELD_ALLOC(dev, map, v->hw_chs_sel, tx_dmactl->hw_chs_sel);
sound/soc/qcom/lpass-cpu.c
685
QCOM_REGMAP_FIELD_ALLOC(dev, map, v->hw_usr_sel, tx_dmactl->hw_usr_sel);
sound/soc/qcom/lpass-cpu.c
694
const struct lpass_variant *v = drvdata->variant;
sound/soc/qcom/lpass-cpu.c
697
if (reg == LPASS_HDMI_TX_CTL_ADDR(v))
sound/soc/qcom/lpass-cpu.c
699
if (reg == LPASS_HDMI_TX_LEGACY_ADDR(v))
sound/soc/qcom/lpass-cpu.c
701
if (reg == LPASS_HDMI_TX_VBIT_CTL_ADDR(v))
sound/soc/qcom/lpass-cpu.c
703
if (reg == LPASS_HDMI_TX_PARITY_ADDR(v))
sound/soc/qcom/lpass-cpu.c
705
if (reg == LPASS_HDMI_TX_DP_ADDR(v))
sound/soc/qcom/lpass-cpu.c
707
if (reg == LPASS_HDMI_TX_SSTREAM_ADDR(v))
sound/soc/qcom/lpass-cpu.c
709
if (reg == LPASS_HDMITX_APP_IRQEN_REG(v))
sound/soc/qcom/lpass-cpu.c
711
if (reg == LPASS_HDMITX_APP_IRQCLEAR_REG(v))
sound/soc/qcom/lpass-cpu.c
714
for (i = 0; i < v->hdmi_rdma_channels; i++) {
sound/soc/qcom/lpass-cpu.c
715
if (reg == LPASS_HDMI_TX_CH_LSB_ADDR(v, i))
sound/soc/qcom/lpass-cpu.c
717
if (reg == LPASS_HDMI_TX_CH_MSB_ADDR(v, i))
sound/soc/qcom/lpass-cpu.c
719
if (reg == LPASS_HDMI_TX_DMA_ADDR(v, i))
sound/soc/qcom/lpass-cpu.c
723
for (i = 0; i < v->hdmi_rdma_channels; ++i) {
sound/soc/qcom/lpass-cpu.c
724
if (reg == LPAIF_HDMI_RDMACTL_REG(v, i))
sound/soc/qcom/lpass-cpu.c
726
if (reg == LPAIF_HDMI_RDMABASE_REG(v, i))
sound/soc/qcom/lpass-cpu.c
728
if (reg == LPAIF_HDMI_RDMABUFF_REG(v, i))
sound/soc/qcom/lpass-cpu.c
730
if (reg == LPAIF_HDMI_RDMAPER_REG(v, i))
sound/soc/qcom/lpass-cpu.c
739
const struct lpass_variant *v = drvdata->variant;
sound/soc/qcom/lpass-cpu.c
742
if (reg == LPASS_HDMI_TX_CTL_ADDR(v))
sound/soc/qcom/lpass-cpu.c
744
if (reg == LPASS_HDMI_TX_LEGACY_ADDR(v))
sound/soc/qcom/lpass-cpu.c
746
if (reg == LPASS_HDMI_TX_VBIT_CTL_ADDR(v))
sound/soc/qcom/lpass-cpu.c
749
for (i = 0; i < v->hdmi_rdma_channels; i++) {
sound/soc/qcom/lpass-cpu.c
750
if (reg == LPASS_HDMI_TX_CH_LSB_ADDR(v, i))
sound/soc/qcom/lpass-cpu.c
752
if (reg == LPASS_HDMI_TX_CH_MSB_ADDR(v, i))
sound/soc/qcom/lpass-cpu.c
754
if (reg == LPASS_HDMI_TX_DMA_ADDR(v, i))
sound/soc/qcom/lpass-cpu.c
758
if (reg == LPASS_HDMI_TX_PARITY_ADDR(v))
sound/soc/qcom/lpass-cpu.c
760
if (reg == LPASS_HDMI_TX_DP_ADDR(v))
sound/soc/qcom/lpass-cpu.c
762
if (reg == LPASS_HDMI_TX_SSTREAM_ADDR(v))
sound/soc/qcom/lpass-cpu.c
764
if (reg == LPASS_HDMITX_APP_IRQEN_REG(v))
sound/soc/qcom/lpass-cpu.c
766
if (reg == LPASS_HDMITX_APP_IRQSTAT_REG(v))
sound/soc/qcom/lpass-cpu.c
769
for (i = 0; i < v->hdmi_rdma_channels; ++i) {
sound/soc/qcom/lpass-cpu.c
770
if (reg == LPAIF_HDMI_RDMACTL_REG(v, i))
sound/soc/qcom/lpass-cpu.c
772
if (reg == LPAIF_HDMI_RDMABASE_REG(v, i))
sound/soc/qcom/lpass-cpu.c
774
if (reg == LPAIF_HDMI_RDMABUFF_REG(v, i))
sound/soc/qcom/lpass-cpu.c
776
if (reg == LPAIF_HDMI_RDMAPER_REG(v, i))
sound/soc/qcom/lpass-cpu.c
778
if (reg == LPAIF_HDMI_RDMACURR_REG(v, i))
sound/soc/qcom/lpass-cpu.c
788
const struct lpass_variant *v = drvdata->variant;
sound/soc/qcom/lpass-cpu.c
791
if (reg == LPASS_HDMITX_APP_IRQSTAT_REG(v))
sound/soc/qcom/lpass-cpu.c
793
if (reg == LPASS_HDMI_TX_LEGACY_ADDR(v))
sound/soc/qcom/lpass-cpu.c
795
if (reg == LPASS_HDMI_TX_VBIT_CTL_ADDR(v))
sound/soc/qcom/lpass-cpu.c
797
if (reg == LPASS_HDMI_TX_PARITY_ADDR(v))
sound/soc/qcom/lpass-cpu.c
800
for (i = 0; i < v->hdmi_rdma_channels; ++i) {
sound/soc/qcom/lpass-cpu.c
801
if (reg == LPAIF_HDMI_RDMACURR_REG(v, i))
sound/soc/qcom/lpass-cpu.c
803
if (reg == LPASS_HDMI_TX_DMA_ADDR(v, i))
sound/soc/qcom/lpass-cpu.c
805
if (reg == LPASS_HDMI_TX_CH_LSB_ADDR(v, i))
sound/soc/qcom/lpass-cpu.c
807
if (reg == LPASS_HDMI_TX_CH_MSB_ADDR(v, i))
sound/soc/qcom/lpass-cpu.c
827
const struct lpass_variant *v = drvdata->variant;
sound/soc/qcom/lpass-cpu.c
830
for (i = 0; i < v->rxtx_irq_ports; ++i) {
sound/soc/qcom/lpass-cpu.c
831
if (reg == LPAIF_RXTX_IRQCLEAR_REG(v, i))
sound/soc/qcom/lpass-cpu.c
833
if (reg == LPAIF_RXTX_IRQEN_REG(v, i))
sound/soc/qcom/lpass-cpu.c
835
if (reg == LPAIF_RXTX_IRQSTAT_REG(v, i))
sound/soc/qcom/lpass-cpu.c
839
for (i = 0; i < v->rxtx_rdma_channels; ++i) {
sound/soc/qcom/lpass-cpu.c
840
if (reg == LPAIF_CDC_RXTX_RDMACTL_REG(v, i, LPASS_CDC_DMA_RX0))
sound/soc/qcom/lpass-cpu.c
842
if (reg == LPAIF_CDC_RXTX_RDMABASE_REG(v, i, LPASS_CDC_DMA_RX0))
sound/soc/qcom/lpass-cpu.c
844
if (reg == LPAIF_CDC_RXTX_RDMABUFF_REG(v, i, LPASS_CDC_DMA_RX0))
sound/soc/qcom/lpass-cpu.c
847
if (reg == LPAIF_CDC_RXTX_RDMACURR_REG(v, i, LPASS_CDC_DMA_RX0))
sound/soc/qcom/lpass-cpu.c
850
if (reg == LPAIF_CDC_RXTX_RDMAPER_REG(v, i, LPASS_CDC_DMA_RX0))
sound/soc/qcom/lpass-cpu.c
852
if (reg == LPAIF_CDC_RXTX_RDMA_INTF_REG(v, i, LPASS_CDC_DMA_RX0))
sound/soc/qcom/lpass-cpu.c
856
for (i = 0; i < v->rxtx_wrdma_channels; ++i) {
sound/soc/qcom/lpass-cpu.c
857
if (reg == LPAIF_CDC_RXTX_WRDMACTL_REG(v, i + v->rxtx_wrdma_channel_start,
sound/soc/qcom/lpass-cpu.c
860
if (reg == LPAIF_CDC_RXTX_WRDMABASE_REG(v, i + v->rxtx_wrdma_channel_start,
sound/soc/qcom/lpass-cpu.c
863
if (reg == LPAIF_CDC_RXTX_WRDMABUFF_REG(v, i + v->rxtx_wrdma_channel_start,
sound/soc/qcom/lpass-cpu.c
867
if (reg == LPAIF_CDC_RXTX_WRDMACURR_REG(v, i, LPASS_CDC_DMA_RX0))
sound/soc/qcom/lpass-cpu.c
870
if (reg == LPAIF_CDC_RXTX_WRDMAPER_REG(v, i + v->rxtx_wrdma_channel_start,
sound/soc/qcom/lpass-cpu.c
873
if (reg == LPAIF_CDC_RXTX_WRDMA_INTF_REG(v, i + v->rxtx_wrdma_channel_start,
sound/soc/qcom/lpass-cpu.c
893
const struct lpass_variant *v = drvdata->variant;
sound/soc/qcom/lpass-cpu.c
896
for (i = 0; i < v->rxtx_irq_ports; ++i) {
sound/soc/qcom/lpass-cpu.c
897
if (reg == LPAIF_RXTX_IRQCLEAR_REG(v, i))
sound/soc/qcom/lpass-cpu.c
899
if (reg == LPAIF_RXTX_IRQSTAT_REG(v, i))
sound/soc/qcom/lpass-cpu.c
903
for (i = 0; i < v->rxtx_rdma_channels; ++i)
sound/soc/qcom/lpass-cpu.c
904
if (reg == LPAIF_CDC_RXTX_RDMACURR_REG(v, i, LPASS_CDC_DMA_RX0))
sound/soc/qcom/lpass-cpu.c
907
for (i = 0; i < v->rxtx_wrdma_channels; ++i)
sound/soc/qcom/lpass-cpu.c
908
if (reg == LPAIF_CDC_RXTX_WRDMACURR_REG(v, i + v->rxtx_wrdma_channel_start,
sound/soc/qcom/lpass-cpu.c
918
const struct lpass_variant *v = drvdata->variant;
sound/soc/qcom/lpass-cpu.c
921
for (i = 0; i < v->va_irq_ports; ++i) {
sound/soc/qcom/lpass-cpu.c
922
if (reg == LPAIF_VA_IRQCLEAR_REG(v, i))
sound/soc/qcom/lpass-cpu.c
924
if (reg == LPAIF_VA_IRQEN_REG(v, i))
sound/soc/qcom/lpass-cpu.c
926
if (reg == LPAIF_VA_IRQSTAT_REG(v, i))
sound/soc/qcom/lpass-cpu.c
930
for (i = 0; i < v->va_wrdma_channels; ++i) {
sound/soc/qcom/lpass-cpu.c
931
if (reg == LPAIF_CDC_VA_WRDMACTL_REG(v, i + v->va_wrdma_channel_start,
sound/soc/qcom/lpass-cpu.c
934
if (reg == LPAIF_CDC_VA_WRDMABASE_REG(v, i + v->va_wrdma_channel_start,
sound/soc/qcom/lpass-cpu.c
937
if (reg == LPAIF_CDC_VA_WRDMABUFF_REG(v, i + v->va_wrdma_channel_start,
sound/soc/qcom/lpass-cpu.c
941
if (reg == LPAIF_CDC_VA_WRDMACURR_REG(v, i + v->va_wrdma_channel_start,
sound/soc/qcom/lpass-cpu.c
945
if (reg == LPAIF_CDC_VA_WRDMAPER_REG(v, i + v->va_wrdma_channel_start,
sound/soc/qcom/lpass-cpu.c
948
if (reg == LPAIF_CDC_VA_WRDMA_INTF_REG(v, i + v->va_wrdma_channel_start,
sound/soc/qcom/lpass-cpu.c
968
const struct lpass_variant *v = drvdata->variant;
sound/soc/qcom/lpass-cpu.c
971
for (i = 0; i < v->va_irq_ports; ++i) {
sound/soc/qcom/lpass-cpu.c
972
if (reg == LPAIF_VA_IRQCLEAR_REG(v, i))
sound/soc/qcom/lpass-cpu.c
974
if (reg == LPAIF_VA_IRQSTAT_REG(v, i))
sound/soc/qcom/lpass-cpu.c
978
for (i = 0; i < v->va_wrdma_channels; ++i) {
sound/soc/qcom/lpass-cpu.c
979
if (reg == LPAIF_CDC_VA_WRDMACURR_REG(v, i + v->va_wrdma_channel_start,
sound/soc/qcom/lpass-hdmi.h
47
#define LPASS_HDMI_TX_CTL_ADDR(v) (v->hdmi_tx_ctl_addr)
sound/soc/qcom/lpass-hdmi.h
48
#define LPASS_HDMI_TX_LEGACY_ADDR(v) (v->hdmi_legacy_addr)
sound/soc/qcom/lpass-hdmi.h
49
#define LPASS_HDMI_TX_VBIT_CTL_ADDR(v) (v->hdmi_vbit_addr)
sound/soc/qcom/lpass-hdmi.h
50
#define LPASS_HDMI_TX_PARITY_ADDR(v) (v->hdmi_parity_addr)
sound/soc/qcom/lpass-hdmi.h
51
#define LPASS_HDMI_TX_DP_ADDR(v) (v->hdmi_DP_addr)
sound/soc/qcom/lpass-hdmi.h
52
#define LPASS_HDMI_TX_SSTREAM_ADDR(v) (v->hdmi_sstream_addr)
sound/soc/qcom/lpass-hdmi.h
54
#define LPASS_HDMI_TX_CH_LSB_ADDR(v, port) \
sound/soc/qcom/lpass-hdmi.h
55
(v->hdmi_ch_lsb_addr + v->ch_stride * (port))
sound/soc/qcom/lpass-hdmi.h
56
#define LPASS_HDMI_TX_CH_MSB_ADDR(v, port) \
sound/soc/qcom/lpass-hdmi.h
57
(v->hdmi_ch_msb_addr + v->ch_stride * (port))
sound/soc/qcom/lpass-hdmi.h
58
#define LPASS_HDMI_TX_DMA_ADDR(v, port) \
sound/soc/qcom/lpass-hdmi.h
59
(v->hdmi_dmactl_addr + v->hdmi_dma_stride * (port))
sound/soc/qcom/lpass-lpaif-reg.h
11
#define LPAIF_I2SCTL_REG_ADDR(v, addr, port) \
sound/soc/qcom/lpass-lpaif-reg.h
112
#define LPAIF_HDMI_RDMA_REG_ADDR(v, addr, chan) \
sound/soc/qcom/lpass-lpaif-reg.h
113
(v->hdmi_rdma_reg_base + (addr) + v->hdmi_rdma_reg_stride * (chan))
sound/soc/qcom/lpass-lpaif-reg.h
117
#define LPAIF_HDMI_RDMACTL_REG(v, chan) LPAIF_HDMI_RDMA_REG_ADDR(v, 0x00, (chan))
sound/soc/qcom/lpass-lpaif-reg.h
118
#define LPAIF_HDMI_RDMABASE_REG(v, chan) LPAIF_HDMI_RDMA_REG_ADDR(v, 0x04, (chan))
sound/soc/qcom/lpass-lpaif-reg.h
119
#define LPAIF_HDMI_RDMABUFF_REG(v, chan) LPAIF_HDMI_RDMA_REG_ADDR(v, 0x08, (chan))
sound/soc/qcom/lpass-lpaif-reg.h
12
(v->i2sctrl_reg_base + (addr) + v->i2sctrl_reg_stride * (port))
sound/soc/qcom/lpass-lpaif-reg.h
120
#define LPAIF_HDMI_RDMACURR_REG(v, chan) LPAIF_HDMI_RDMA_REG_ADDR(v, 0x0C, (chan))
sound/soc/qcom/lpass-lpaif-reg.h
121
#define LPAIF_HDMI_RDMAPER_REG(v, chan) LPAIF_HDMI_RDMA_REG_ADDR(v, 0x10, (chan))
sound/soc/qcom/lpass-lpaif-reg.h
122
#define LPAIF_HDMI_RDMAPERCNT_REG(v, chan) LPAIF_HDMI_RDMA_REG_ADDR(v, 0x14, (chan))
sound/soc/qcom/lpass-lpaif-reg.h
124
#define LPAIF_RDMA_REG_ADDR(v, addr, chan) \
sound/soc/qcom/lpass-lpaif-reg.h
125
(v->rdma_reg_base + (addr) + v->rdma_reg_stride * (chan))
sound/soc/qcom/lpass-lpaif-reg.h
129
#define LPAIF_RDMACTL_REG(v, chan) LPAIF_RDMA_REG_ADDR(v, 0x00, (chan))
sound/soc/qcom/lpass-lpaif-reg.h
130
#define LPAIF_RDMABASE_REG(v, chan) LPAIF_RDMA_REG_ADDR(v, 0x04, (chan))
sound/soc/qcom/lpass-lpaif-reg.h
131
#define LPAIF_RDMABUFF_REG(v, chan) LPAIF_RDMA_REG_ADDR(v, 0x08, (chan))
sound/soc/qcom/lpass-lpaif-reg.h
132
#define LPAIF_RDMACURR_REG(v, chan) LPAIF_RDMA_REG_ADDR(v, 0x0C, (chan))
sound/soc/qcom/lpass-lpaif-reg.h
133
#define LPAIF_RDMAPER_REG(v, chan) LPAIF_RDMA_REG_ADDR(v, 0x10, (chan))
sound/soc/qcom/lpass-lpaif-reg.h
134
#define LPAIF_RDMAPERCNT_REG(v, chan) LPAIF_RDMA_REG_ADDR(v, 0x14, (chan))
sound/soc/qcom/lpass-lpaif-reg.h
136
#define LPAIF_WRDMA_REG_ADDR(v, addr, chan) \
sound/soc/qcom/lpass-lpaif-reg.h
137
(v->wrdma_reg_base + (addr) + \
sound/soc/qcom/lpass-lpaif-reg.h
138
v->wrdma_reg_stride * (chan - v->wrdma_channel_start))
sound/soc/qcom/lpass-lpaif-reg.h
14
#define LPAIF_I2SCTL_REG(v, port) LPAIF_I2SCTL_REG_ADDR(v, 0x0, (port))
sound/soc/qcom/lpass-lpaif-reg.h
140
#define LPAIF_WRDMACTL_REG(v, chan) LPAIF_WRDMA_REG_ADDR(v, 0x00, (chan))
sound/soc/qcom/lpass-lpaif-reg.h
141
#define LPAIF_WRDMABASE_REG(v, chan) LPAIF_WRDMA_REG_ADDR(v, 0x04, (chan))
sound/soc/qcom/lpass-lpaif-reg.h
142
#define LPAIF_WRDMABUFF_REG(v, chan) LPAIF_WRDMA_REG_ADDR(v, 0x08, (chan))
sound/soc/qcom/lpass-lpaif-reg.h
143
#define LPAIF_WRDMACURR_REG(v, chan) LPAIF_WRDMA_REG_ADDR(v, 0x0C, (chan))
sound/soc/qcom/lpass-lpaif-reg.h
144
#define LPAIF_WRDMAPER_REG(v, chan) LPAIF_WRDMA_REG_ADDR(v, 0x10, (chan))
sound/soc/qcom/lpass-lpaif-reg.h
145
#define LPAIF_WRDMAPERCNT_REG(v, chan) LPAIF_WRDMA_REG_ADDR(v, 0x14, (chan))
sound/soc/qcom/lpass-lpaif-reg.h
147
#define LPAIF_INTFDMA_REG(v, chan, reg, dai_id) \
sound/soc/qcom/lpass-lpaif-reg.h
149
LPAIF_HDMI_RDMA##reg##_REG(v, chan) : \
sound/soc/qcom/lpass-lpaif-reg.h
150
LPAIF_RDMA##reg##_REG(v, chan))
sound/soc/qcom/lpass-lpaif-reg.h
152
#define __LPAIF_DMA_REG(v, chan, dir, reg, dai_id) \
sound/soc/qcom/lpass-lpaif-reg.h
154
(LPAIF_INTFDMA_REG(v, chan, reg, dai_id)) : \
sound/soc/qcom/lpass-lpaif-reg.h
155
LPAIF_WRDMA##reg##_REG(v, chan))
sound/soc/qcom/lpass-lpaif-reg.h
157
#define LPAIF_DMACTL_REG(v, chan, dir, dai_id) \
sound/soc/qcom/lpass-lpaif-reg.h
159
__LPAIF_CDC_DMA_REG(v, chan, dir, CTL, dai_id) : \
sound/soc/qcom/lpass-lpaif-reg.h
160
__LPAIF_DMA_REG(v, chan, dir, CTL, dai_id))
sound/soc/qcom/lpass-lpaif-reg.h
161
#define LPAIF_DMABASE_REG(v, chan, dir, dai_id) \
sound/soc/qcom/lpass-lpaif-reg.h
163
__LPAIF_CDC_DMA_REG(v, chan, dir, BASE, dai_id) : \
sound/soc/qcom/lpass-lpaif-reg.h
164
__LPAIF_DMA_REG(v, chan, dir, BASE, dai_id))
sound/soc/qcom/lpass-lpaif-reg.h
165
#define LPAIF_DMABUFF_REG(v, chan, dir, dai_id) \
sound/soc/qcom/lpass-lpaif-reg.h
167
__LPAIF_CDC_DMA_REG(v, chan, dir, BUFF, dai_id) : \
sound/soc/qcom/lpass-lpaif-reg.h
168
__LPAIF_DMA_REG(v, chan, dir, BUFF, dai_id))
sound/soc/qcom/lpass-lpaif-reg.h
169
#define LPAIF_DMACURR_REG(v, chan, dir, dai_id) \
sound/soc/qcom/lpass-lpaif-reg.h
171
__LPAIF_CDC_DMA_REG(v, chan, dir, CURR, dai_id) : \
sound/soc/qcom/lpass-lpaif-reg.h
172
__LPAIF_DMA_REG(v, chan, dir, CURR, dai_id))
sound/soc/qcom/lpass-lpaif-reg.h
173
#define LPAIF_DMAPER_REG(v, chan, dir, dai_id) \
sound/soc/qcom/lpass-lpaif-reg.h
175
__LPAIF_CDC_DMA_REG(v, chan, dir, PER, dai_id) : \
sound/soc/qcom/lpass-lpaif-reg.h
176
__LPAIF_DMA_REG(v, chan, dir, PER, dai_id))
sound/soc/qcom/lpass-lpaif-reg.h
177
#define LPAIF_DMAPERCNT_REG(v, chan, dir, dai_id) \
sound/soc/qcom/lpass-lpaif-reg.h
179
__LPAIF_CDC_DMA_REG(v, chan, dir, PERCNT, dai_id) : \
sound/soc/qcom/lpass-lpaif-reg.h
180
__LPAIF_DMA_REG(v, chan, dir, PERCNT, dai_id))
sound/soc/qcom/lpass-lpaif-reg.h
182
#define LPAIF_CDC_RDMA_REG_ADDR(v, addr, chan, dai_id) \
sound/soc/qcom/lpass-lpaif-reg.h
184
(v->rxtx_rdma_reg_base + (addr) + v->rxtx_rdma_reg_stride * (chan)) : \
sound/soc/qcom/lpass-lpaif-reg.h
185
(v->va_rdma_reg_base + (addr) + v->va_rdma_reg_stride * (chan)))
sound/soc/qcom/lpass-lpaif-reg.h
187
#define LPAIF_CDC_RXTX_RDMACTL_REG(v, chan, dai_id) \
sound/soc/qcom/lpass-lpaif-reg.h
188
LPAIF_CDC_RDMA_REG_ADDR(v, 0x00, (chan), dai_id)
sound/soc/qcom/lpass-lpaif-reg.h
189
#define LPAIF_CDC_RXTX_RDMABASE_REG(v, chan, dai_id) \
sound/soc/qcom/lpass-lpaif-reg.h
190
LPAIF_CDC_RDMA_REG_ADDR(v, 0x04, (chan), dai_id)
sound/soc/qcom/lpass-lpaif-reg.h
191
#define LPAIF_CDC_RXTX_RDMABUFF_REG(v, chan, dai_id) \
sound/soc/qcom/lpass-lpaif-reg.h
192
LPAIF_CDC_RDMA_REG_ADDR(v, 0x08, (chan), dai_id)
sound/soc/qcom/lpass-lpaif-reg.h
193
#define LPAIF_CDC_RXTX_RDMACURR_REG(v, chan, dai_id) \
sound/soc/qcom/lpass-lpaif-reg.h
194
LPAIF_CDC_RDMA_REG_ADDR(v, 0x0C, (chan), dai_id)
sound/soc/qcom/lpass-lpaif-reg.h
195
#define LPAIF_CDC_RXTX_RDMAPER_REG(v, chan, dai_id) \
sound/soc/qcom/lpass-lpaif-reg.h
196
LPAIF_CDC_RDMA_REG_ADDR(v, 0x10, (chan), dai_id)
sound/soc/qcom/lpass-lpaif-reg.h
197
#define LPAIF_CDC_RXTX_RDMA_INTF_REG(v, chan, dai_id) \
sound/soc/qcom/lpass-lpaif-reg.h
198
LPAIF_CDC_RDMA_REG_ADDR(v, 0x50, (chan), dai_id)
sound/soc/qcom/lpass-lpaif-reg.h
200
#define LPAIF_CDC_VA_RDMACTL_REG(v, chan, dai_id) LPAIF_CDC_RDMA_REG_ADDR(v, 0x00, (chan), dai_id)
sound/soc/qcom/lpass-lpaif-reg.h
201
#define LPAIF_CDC_VA_RDMABASE_REG(v, chan, dai_id) LPAIF_CDC_RDMA_REG_ADDR(v, 0x04, (chan), dai_id)
sound/soc/qcom/lpass-lpaif-reg.h
202
#define LPAIF_CDC_VA_RDMABUFF_REG(v, chan, dai_id) LPAIF_CDC_RDMA_REG_ADDR(v, 0x08, (chan), dai_id)
sound/soc/qcom/lpass-lpaif-reg.h
203
#define LPAIF_CDC_VA_RDMACURR_REG(v, chan, dai_id) LPAIF_CDC_RDMA_REG_ADDR(v, 0x0C, (chan), dai_id)
sound/soc/qcom/lpass-lpaif-reg.h
204
#define LPAIF_CDC_VA_RDMAPER_REG(v, chan, dai_id) LPAIF_CDC_RDMA_REG_ADDR(v, 0x10, (chan), dai_id)
sound/soc/qcom/lpass-lpaif-reg.h
205
#define LPAIF_CDC_VA_RDMA_INTF_REG(v, chan, dai_id) \
sound/soc/qcom/lpass-lpaif-reg.h
206
LPAIF_CDC_RDMA_REG_ADDR(v, 0x50, (chan), dai_id)
sound/soc/qcom/lpass-lpaif-reg.h
208
#define LPAIF_CDC_WRDMA_REG_ADDR(v, addr, chan, dai_id) \
sound/soc/qcom/lpass-lpaif-reg.h
210
(v->rxtx_wrdma_reg_base + (addr) + \
sound/soc/qcom/lpass-lpaif-reg.h
211
v->rxtx_wrdma_reg_stride * (chan - v->rxtx_wrdma_channel_start)) : \
sound/soc/qcom/lpass-lpaif-reg.h
212
(v->va_wrdma_reg_base + (addr) + \
sound/soc/qcom/lpass-lpaif-reg.h
213
v->va_wrdma_reg_stride * (chan - v->va_wrdma_channel_start)))
sound/soc/qcom/lpass-lpaif-reg.h
215
#define LPAIF_CDC_RXTX_WRDMACTL_REG(v, chan, dai_id) \
sound/soc/qcom/lpass-lpaif-reg.h
216
LPAIF_CDC_WRDMA_REG_ADDR(v, 0x00, (chan), dai_id)
sound/soc/qcom/lpass-lpaif-reg.h
217
#define LPAIF_CDC_RXTX_WRDMABASE_REG(v, chan, dai_id) \
sound/soc/qcom/lpass-lpaif-reg.h
218
LPAIF_CDC_WRDMA_REG_ADDR(v, 0x04, (chan), dai_id)
sound/soc/qcom/lpass-lpaif-reg.h
219
#define LPAIF_CDC_RXTX_WRDMABUFF_REG(v, chan, dai_id) \
sound/soc/qcom/lpass-lpaif-reg.h
220
LPAIF_CDC_WRDMA_REG_ADDR(v, 0x08, (chan), dai_id)
sound/soc/qcom/lpass-lpaif-reg.h
221
#define LPAIF_CDC_RXTX_WRDMACURR_REG(v, chan, dai_id) \
sound/soc/qcom/lpass-lpaif-reg.h
222
LPAIF_CDC_WRDMA_REG_ADDR(v, 0x0C, (chan), dai_id)
sound/soc/qcom/lpass-lpaif-reg.h
223
#define LPAIF_CDC_RXTX_WRDMAPER_REG(v, chan, dai_id) \
sound/soc/qcom/lpass-lpaif-reg.h
224
LPAIF_CDC_WRDMA_REG_ADDR(v, 0x10, (chan), dai_id)
sound/soc/qcom/lpass-lpaif-reg.h
225
#define LPAIF_CDC_RXTX_WRDMA_INTF_REG(v, chan, dai_id) \
sound/soc/qcom/lpass-lpaif-reg.h
226
LPAIF_CDC_WRDMA_REG_ADDR(v, 0x50, (chan), dai_id)
sound/soc/qcom/lpass-lpaif-reg.h
228
#define LPAIF_CDC_VA_WRDMACTL_REG(v, chan, dai_id) \
sound/soc/qcom/lpass-lpaif-reg.h
229
LPAIF_CDC_WRDMA_REG_ADDR(v, 0x00, (chan), dai_id)
sound/soc/qcom/lpass-lpaif-reg.h
230
#define LPAIF_CDC_VA_WRDMABASE_REG(v, chan, dai_id) \
sound/soc/qcom/lpass-lpaif-reg.h
231
LPAIF_CDC_WRDMA_REG_ADDR(v, 0x04, (chan), dai_id)
sound/soc/qcom/lpass-lpaif-reg.h
232
#define LPAIF_CDC_VA_WRDMABUFF_REG(v, chan, dai_id) \
sound/soc/qcom/lpass-lpaif-reg.h
233
LPAIF_CDC_WRDMA_REG_ADDR(v, 0x08, (chan), dai_id)
sound/soc/qcom/lpass-lpaif-reg.h
234
#define LPAIF_CDC_VA_WRDMACURR_REG(v, chan, dai_id) \
sound/soc/qcom/lpass-lpaif-reg.h
235
LPAIF_CDC_WRDMA_REG_ADDR(v, 0x0C, (chan), dai_id)
sound/soc/qcom/lpass-lpaif-reg.h
236
#define LPAIF_CDC_VA_WRDMAPER_REG(v, chan, dai_id) \
sound/soc/qcom/lpass-lpaif-reg.h
237
LPAIF_CDC_WRDMA_REG_ADDR(v, 0x10, (chan), dai_id)
sound/soc/qcom/lpass-lpaif-reg.h
238
#define LPAIF_CDC_VA_WRDMA_INTF_REG(v, chan, dai_id) \
sound/soc/qcom/lpass-lpaif-reg.h
239
LPAIF_CDC_WRDMA_REG_ADDR(v, 0x50, (chan), dai_id)
sound/soc/qcom/lpass-lpaif-reg.h
241
#define __LPAIF_CDC_RDDMA_REG(v, chan, dir, reg, dai_id) \
sound/soc/qcom/lpass-lpaif-reg.h
242
(is_rxtx_cdc_dma_port(dai_id) ? LPAIF_CDC_RXTX_RDMA##reg##_REG(v, chan, dai_id) : \
sound/soc/qcom/lpass-lpaif-reg.h
243
LPAIF_CDC_VA_RDMA##reg##_REG(v, chan, dai_id))
sound/soc/qcom/lpass-lpaif-reg.h
245
#define __LPAIF_CDC_WRDMA_REG(v, chan, dir, reg, dai_id) \
sound/soc/qcom/lpass-lpaif-reg.h
246
(is_rxtx_cdc_dma_port(dai_id) ? LPAIF_CDC_RXTX_WRDMA##reg##_REG(v, chan, dai_id) : \
sound/soc/qcom/lpass-lpaif-reg.h
247
LPAIF_CDC_VA_WRDMA##reg##_REG(v, chan, dai_id))
sound/soc/qcom/lpass-lpaif-reg.h
249
#define __LPAIF_CDC_DMA_REG(v, chan, dir, reg, dai_id) \
sound/soc/qcom/lpass-lpaif-reg.h
251
__LPAIF_CDC_RDDMA_REG(v, chan, dir, reg, dai_id) : \
sound/soc/qcom/lpass-lpaif-reg.h
252
__LPAIF_CDC_WRDMA_REG(v, chan, dir, reg, dai_id))
sound/soc/qcom/lpass-lpaif-reg.h
254
#define LPAIF_CDC_INTF_REG(v, chan, dir, dai_id) \
sound/soc/qcom/lpass-lpaif-reg.h
256
LPAIF_CDC_RDMA_INTF_REG(v, chan, dai_id) : \
sound/soc/qcom/lpass-lpaif-reg.h
257
LPAIF_CDC_WRDMA_INTF_REG(v, chan, dai_id))
sound/soc/qcom/lpass-lpaif-reg.h
259
#define LPAIF_INTF_REG(v, chan, dir, dai_id) \
sound/soc/qcom/lpass-lpaif-reg.h
261
LPAIF_CDC_INTF_REG(v, chan, dir, dai_id) : \
sound/soc/qcom/lpass-lpaif-reg.h
262
LPAIF_DMACTL_REG(v, chan, dir, dai_id))
sound/soc/qcom/lpass-lpaif-reg.h
68
#define LPAIF_IRQ_REG_ADDR(v, addr, port) \
sound/soc/qcom/lpass-lpaif-reg.h
69
(v->irq_reg_base + (addr) + v->irq_reg_stride * (port))
sound/soc/qcom/lpass-lpaif-reg.h
73
#define LPAIF_IRQEN_REG(v, port) LPAIF_IRQ_REG_ADDR(v, 0x0, (port))
sound/soc/qcom/lpass-lpaif-reg.h
74
#define LPAIF_IRQSTAT_REG(v, port) LPAIF_IRQ_REG_ADDR(v, 0x4, (port))
sound/soc/qcom/lpass-lpaif-reg.h
75
#define LPAIF_IRQCLEAR_REG(v, port) LPAIF_IRQ_REG_ADDR(v, 0xC, (port))
sound/soc/qcom/lpass-lpaif-reg.h
78
#define LPAIF_RXTX_IRQ_REG_ADDR(v, addr, port) \
sound/soc/qcom/lpass-lpaif-reg.h
79
(v->rxtx_irq_reg_base + (addr) + v->rxtx_irq_reg_stride * (port))
sound/soc/qcom/lpass-lpaif-reg.h
81
#define LPAIF_RXTX_IRQEN_REG(v, port) LPAIF_RXTX_IRQ_REG_ADDR(v, 0x0, port)
sound/soc/qcom/lpass-lpaif-reg.h
82
#define LPAIF_RXTX_IRQSTAT_REG(v, port) LPAIF_RXTX_IRQ_REG_ADDR(v, 0x4, port)
sound/soc/qcom/lpass-lpaif-reg.h
83
#define LPAIF_RXTX_IRQCLEAR_REG(v, port) LPAIF_RXTX_IRQ_REG_ADDR(v, 0xC, port)
sound/soc/qcom/lpass-lpaif-reg.h
86
#define LPAIF_VA_IRQ_REG_ADDR(v, addr, port) \
sound/soc/qcom/lpass-lpaif-reg.h
87
(v->va_irq_reg_base + (addr) + v->va_irq_reg_stride * (port))
sound/soc/qcom/lpass-lpaif-reg.h
89
#define LPAIF_VA_IRQEN_REG(v, port) LPAIF_VA_IRQ_REG_ADDR(v, 0x0, port)
sound/soc/qcom/lpass-lpaif-reg.h
90
#define LPAIF_VA_IRQSTAT_REG(v, port) LPAIF_VA_IRQ_REG_ADDR(v, 0x4, port)
sound/soc/qcom/lpass-lpaif-reg.h
91
#define LPAIF_VA_IRQCLEAR_REG(v, port) LPAIF_VA_IRQ_REG_ADDR(v, 0xC, port)
sound/soc/qcom/lpass-lpaif-reg.h
93
#define LPASS_HDMITX_APP_IRQ_REG_ADDR(v, addr) \
sound/soc/qcom/lpass-lpaif-reg.h
94
((v->hdmi_irq_reg_base) + (addr))
sound/soc/qcom/lpass-lpaif-reg.h
96
#define LPASS_HDMITX_APP_IRQEN_REG(v) LPASS_HDMITX_APP_IRQ_REG_ADDR(v, 0x4)
sound/soc/qcom/lpass-lpaif-reg.h
97
#define LPASS_HDMITX_APP_IRQSTAT_REG(v) LPASS_HDMITX_APP_IRQ_REG_ADDR(v, 0x8)
sound/soc/qcom/lpass-lpaif-reg.h
98
#define LPASS_HDMITX_APP_IRQCLEAR_REG(v) LPASS_HDMITX_APP_IRQ_REG_ADDR(v, 0xC)
sound/soc/qcom/lpass-platform.c
1023
const struct lpass_variant *v = drvdata->variant;
sound/soc/qcom/lpass-platform.c
1028
LPAIF_IRQSTAT_REG(v, LPAIF_IRQ_PORT_HOST), &irqs);
sound/soc/qcom/lpass-platform.c
104
const struct lpass_variant *v = drvdata->variant;
sound/soc/qcom/lpass-platform.c
1051
const struct lpass_variant *v = drvdata->variant;
sound/soc/qcom/lpass-platform.c
1056
LPASS_HDMITX_APP_IRQSTAT_REG(v), &irqs);
sound/soc/qcom/lpass-platform.c
1081
const struct lpass_variant *v = drvdata->variant;
sound/soc/qcom/lpass-platform.c
1087
LPAIF_RXTX_IRQSTAT_REG(v, LPAIF_IRQ_PORT_HOST), &irqs);
sound/soc/qcom/lpass-platform.c
1106
const struct lpass_variant *v = drvdata->variant;
sound/soc/qcom/lpass-platform.c
1112
LPAIF_VA_IRQSTAT_REG(v, LPAIF_IRQ_PORT_HOST), &irqs);
sound/soc/qcom/lpass-platform.c
120
&v->rxtx_rdma_intf, LPASS_CDC_DMA_REGISTER_FIELDS_MAX);
sound/soc/qcom/lpass-platform.c
125
&v->rxtx_wrdma_intf, LPASS_CDC_DMA_REGISTER_FIELDS_MAX);
sound/soc/qcom/lpass-platform.c
1281
const struct lpass_variant *v = drvdata->variant;
sound/soc/qcom/lpass-platform.c
1290
LPAIF_IRQEN_REG(v, LPAIF_IRQ_PORT_HOST), 0);
sound/soc/qcom/lpass-platform.c
1314
LPAIF_RXTX_IRQEN_REG(v, LPAIF_IRQ_PORT_HOST), 0x0);
sound/soc/qcom/lpass-platform.c
132
const struct lpass_variant *v = drvdata->variant;
sound/soc/qcom/lpass-platform.c
1320
LPAIF_VA_IRQEN_REG(v, LPAIF_IRQ_PORT_HOST), 0x0);
sound/soc/qcom/lpass-platform.c
1376
LPASS_HDMITX_APP_IRQEN_REG(v), 0);
sound/soc/qcom/lpass-platform.c
141
&v->va_wrdma_intf, LPASS_CDC_DMA_REGISTER_FIELDS_MAX);
sound/soc/qcom/lpass-platform.c
149
const struct lpass_variant *v = drvdata->variant;
sound/soc/qcom/lpass-platform.c
167
&v->rdma_intf, 6);
sound/soc/qcom/lpass-platform.c
172
&v->wrdma_intf, 6);
sound/soc/qcom/lpass-platform.c
179
const struct lpass_variant *v = drvdata->variant;
sound/soc/qcom/lpass-platform.c
189
&v->hdmi_rdma_bursten, 8);
sound/soc/qcom/lpass-platform.c
199
const struct lpass_variant *v = drvdata->variant;
sound/soc/qcom/lpass-platform.c
212
if (v->alloc_dma_channel)
sound/soc/qcom/lpass-platform.c
213
dma_ch = v->alloc_dma_channel(drvdata, dir, dai_id);
sound/soc/qcom/lpass-platform.c
248
ret = regmap_write(map, LPAIF_DMACTL_REG(v, dma_ch, dir, data->i2s_port), 0);
sound/soc/qcom/lpass-platform.c
290
const struct lpass_variant *v = drvdata->variant;
sound/soc/qcom/lpass-platform.c
314
if (v->free_dma_channel)
sound/soc/qcom/lpass-platform.c
315
v->free_dma_channel(drvdata, data->dma_ch, dai_id);
sound/soc/qcom/lpass-platform.c
361
const struct lpass_variant *v = drvdata->variant;
sound/soc/qcom/lpass-platform.c
369
id = pcm_data->dma_ch - v->wrdma_channel_start;
sound/soc/qcom/lpass-platform.c
378
id = pcm_data->dma_ch - v->rxtx_wrdma_channel_start;
sound/soc/qcom/lpass-platform.c
381
id = pcm_data->dma_ch - v->va_wrdma_channel_start;
sound/soc/qcom/lpass-platform.c
424
const struct lpass_variant *v = drvdata->variant;
sound/soc/qcom/lpass-platform.c
431
int ret, dma_port = pcm_data->i2s_port + v->dmactl_audif_start;
sound/soc/qcom/lpass-platform.c
577
const struct lpass_variant *v = drvdata->variant;
sound/soc/qcom/lpass-platform.c
587
reg = LPAIF_DMACTL_REG(v, pcm_data->dma_ch, substream->stream, dai_id);
sound/soc/qcom/lpass-platform.c
605
const struct lpass_variant *v = drvdata->variant;
sound/soc/qcom/lpass-platform.c
617
ret = regmap_write(map, LPAIF_DMABASE_REG(v, ch, dir, dai_id),
sound/soc/qcom/lpass-platform.c
625
ret = regmap_write(map, LPAIF_DMABUFF_REG(v, ch, dir, dai_id),
sound/soc/qcom/lpass-platform.c
633
ret = regmap_write(map, LPAIF_DMAPER_REG(v, ch, dir, dai_id),
sound/soc/qcom/lpass-platform.c
668
const struct lpass_variant *v = drvdata->variant;
sound/soc/qcom/lpass-platform.c
701
reg_irqclr = LPASS_HDMITX_APP_IRQCLEAR_REG(v);
sound/soc/qcom/lpass-platform.c
707
reg_irqen = LPASS_HDMITX_APP_IRQEN_REG(v);
sound/soc/qcom/lpass-platform.c
722
reg_irqclr = LPAIF_IRQCLEAR_REG(v, LPAIF_IRQ_PORT_HOST);
sound/soc/qcom/lpass-platform.c
726
reg_irqen = LPAIF_IRQEN_REG(v, LPAIF_IRQ_PORT_HOST);
sound/soc/qcom/lpass-platform.c
738
reg_irqclr = LPAIF_RXTX_IRQCLEAR_REG(v, LPAIF_IRQ_PORT_HOST);
sound/soc/qcom/lpass-platform.c
741
reg_irqen = LPAIF_RXTX_IRQEN_REG(v, LPAIF_IRQ_PORT_HOST);
sound/soc/qcom/lpass-platform.c
752
reg_irqclr = LPAIF_VA_IRQCLEAR_REG(v, LPAIF_IRQ_PORT_HOST);
sound/soc/qcom/lpass-platform.c
755
reg_irqen = LPAIF_VA_IRQEN_REG(v, LPAIF_IRQ_PORT_HOST);
sound/soc/qcom/lpass-platform.c
794
reg_irqen = LPASS_HDMITX_APP_IRQEN_REG(v);
sound/soc/qcom/lpass-platform.c
806
reg_irqen = LPAIF_IRQEN_REG(v, LPAIF_IRQ_PORT_HOST);
sound/soc/qcom/lpass-platform.c
819
reg_irqclr = LPAIF_RXTX_IRQCLEAR_REG(v, LPAIF_IRQ_PORT_HOST);
sound/soc/qcom/lpass-platform.c
822
reg_irqen = LPAIF_RXTX_IRQEN_REG(v, LPAIF_IRQ_PORT_HOST);
sound/soc/qcom/lpass-platform.c
834
reg_irqclr = LPAIF_VA_IRQCLEAR_REG(v, LPAIF_IRQ_PORT_HOST);
sound/soc/qcom/lpass-platform.c
837
reg_irqen = LPAIF_VA_IRQEN_REG(v, LPAIF_IRQ_PORT_HOST);
sound/soc/qcom/lpass-platform.c
867
const struct lpass_variant *v = drvdata->variant;
sound/soc/qcom/lpass-platform.c
877
LPAIF_DMABASE_REG(v, ch, dir, dai_id), &base_addr);
sound/soc/qcom/lpass-platform.c
885
LPAIF_DMACURR_REG(v, ch, dir, dai_id), &curr_addr);
sound/soc/qcom/lpass-platform.c
931
const struct lpass_variant *v = drvdata->variant;
sound/soc/qcom/lpass-platform.c
942
reg = LPASS_HDMITX_APP_IRQCLEAR_REG(v);
sound/soc/qcom/lpass-platform.c
953
reg = LPAIF_IRQCLEAR_REG(v, LPAIF_IRQ_PORT_HOST);
sound/soc/qcom/lpass-platform.c
959
reg = LPAIF_RXTX_IRQCLEAR_REG(v, LPAIF_IRQ_PORT_HOST);
sound/soc/qcom/lpass-platform.c
964
reg = LPAIF_VA_IRQCLEAR_REG(v, LPAIF_IRQ_PORT_HOST);
sound/soc/qcom/lpass-sc7180.c
100
v->wrdma_channel_start +
sound/soc/qcom/lpass-sc7180.c
101
v->wrdma_channels,
sound/soc/qcom/lpass-sc7180.c
102
v->wrdma_channel_start);
sound/soc/qcom/lpass-sc7180.c
104
if (chan >= v->wrdma_channel_start + v->wrdma_channels)
sound/soc/qcom/lpass-sc7180.c
79
const struct lpass_variant *v = drvdata->variant;
sound/soc/qcom/lpass-sc7180.c
85
v->hdmi_rdma_channels);
sound/soc/qcom/lpass-sc7180.c
87
if (chan >= v->hdmi_rdma_channels)
sound/soc/qcom/lpass-sc7180.c
94
v->rdma_channels);
sound/soc/qcom/lpass-sc7180.c
96
if (chan >= v->rdma_channels)
sound/soc/qcom/lpass-sc7280.c
113
const struct lpass_variant *v = drvdata->variant;
sound/soc/qcom/lpass-sc7280.c
120
v->rdma_channels);
sound/soc/qcom/lpass-sc7280.c
122
if (chan >= v->rdma_channels)
sound/soc/qcom/lpass-sc7280.c
126
v->wrdma_channel_start +
sound/soc/qcom/lpass-sc7280.c
127
v->wrdma_channels,
sound/soc/qcom/lpass-sc7280.c
128
v->wrdma_channel_start);
sound/soc/qcom/lpass-sc7280.c
130
if (chan >= v->wrdma_channel_start + v->wrdma_channels)
sound/soc/qcom/lpass-sc7280.c
137
v->hdmi_rdma_channels);
sound/soc/qcom/lpass-sc7280.c
138
if (chan >= v->hdmi_rdma_channels)
sound/soc/qcom/lpass-sc7280.c
144
v->rxtx_rdma_channels);
sound/soc/qcom/lpass-sc7280.c
145
if (chan >= v->rxtx_rdma_channels)
sound/soc/qcom/lpass-sc7280.c
150
v->rxtx_wrdma_channel_start +
sound/soc/qcom/lpass-sc7280.c
151
v->rxtx_wrdma_channels,
sound/soc/qcom/lpass-sc7280.c
152
v->rxtx_wrdma_channel_start);
sound/soc/qcom/lpass-sc7280.c
153
if (chan >= v->rxtx_wrdma_channel_start + v->rxtx_wrdma_channels)
sound/soc/qcom/lpass-sc7280.c
159
v->va_wrdma_channel_start +
sound/soc/qcom/lpass-sc7280.c
160
v->va_wrdma_channels,
sound/soc/qcom/lpass-sc7280.c
161
v->va_wrdma_channel_start);
sound/soc/qcom/lpass-sc7280.c
162
if (chan >= v->va_wrdma_channel_start + v->va_wrdma_channels)
sound/soc/qcom/qdsp6/q6core.c
117
struct avcs_cmdrsp_get_version *v;
sound/soc/qcom/qdsp6/q6core.c
119
v = data->payload;
sound/soc/qcom/qdsp6/q6core.c
122
struct_size(v, svc_api_info,
sound/soc/qcom/qdsp6/q6core.c
123
v->num_services),
sound/soc/renesas/hac.c
100
unsigned short *v)
sound/soc/renesas/hac.c
106
*v = 0;
sound/soc/renesas/hac.c
121
*v = ((HACREG(HACCSDR) & CSDR_MASK) >> CSDR_SHIFT);
sound/soc/renesas/rcar/debugfs.c
17
static int rsnd_debugfs_show(struct seq_file *m, void *v)
sound/soc/renesas/rcar/ssi.c
61
#define CKDV(v) (v << 4) /* Serial Clock Division Ratio */
sound/soc/rockchip/rockchip_i2s_tdm.h
21
#define I2S_TXCR_PATH(x, v) ((v) << I2S_TXCR_PATH_SHIFT(x))
sound/soc/rockchip/rockchip_i2s_tdm.h
290
#define HIWORD_UPDATE(v, h, l) (FIELD_PREP_WM16_CONST(GENMASK((h), (l)), (v)))
sound/soc/rockchip/rockchip_i2s_tdm.h
58
#define I2S_RXCR_PATH(x, v) ((v) << I2S_RXCR_PATH_SHIFT(x))
sound/soc/rockchip/rockchip_pdm.h
58
#define PDM_PATH(x, v) ((v) << PDM_PATH_SHIFT(x))
sound/soc/rockchip/rockchip_sai.h
113
#define SAI_DMACR_RDL_V(v) ((((v) & SAI_DMACR_RDL_MASK) >> 16) + 1)
sound/soc/rockchip/rockchip_sai.h
118
#define SAI_DMACR_TDL_V(v) (((v) & SAI_DMACR_TDL_MASK) >> 0)
sound/soc/rockchip/rockchip_sai.h
147
#define SAI_RX_PATH(x, v) ((v) << SAI_RX_PATH_SHIFT(x))
sound/soc/rockchip/rockchip_sai.h
150
#define SAI_TX_PATH(x, v) ((v) << SAI_TX_PATH_SHIFT(x))
sound/soc/rockchip/rockchip_sai.h
20
#define SAI_XCR_CSR_V(v) ((((v) & SAI_XCR_CSR_MASK) >> 20) + 1)
sound/soc/rockchip/rockchip_sai.h
34
#define SAI_XCR_SBW_V(v) ((((v) & SAI_XCR_SBW_MASK) >> 5) + 1)
sound/soc/rockchip/rockchip_sai.h
46
#define SAI_FSCR_FW_V(v) ((((v) & SAI_FSCR_FW_MASK) >> 0) + 1)
sound/soc/soc-core.c
166
static int dai_list_show(struct seq_file *m, void *v)
sound/soc/soc-core.c
183
static int component_list_show(struct seq_file *m, void *v)
sound/soc/sof/compress.c
170
struct sof_ipc_fw_version *v = &ready->version;
sound/soc/sof/compress.c
177
if (v->abi_version < SOF_ABI_VER(3, 22, 0)) {
sound/soc/sof/compress.c
180
SOF_ABI_VERSION_MAJOR(v->abi_version),
sound/soc/sof/compress.c
181
SOF_ABI_VERSION_MINOR(v->abi_version),
sound/soc/sof/compress.c
182
SOF_ABI_VERSION_PATCH(v->abi_version));
sound/soc/sof/intel/hda-dsp.c
229
#define MASK_IS_EQUAL(v, m, field) ({ \
sound/soc/sof/intel/hda-dsp.c
231
((v) & _m) == _m; \
sound/soc/sof/ipc3-dtrace.c
431
struct sof_ipc_fw_version *v = &ready->version;
sound/soc/sof/ipc3-dtrace.c
447
if (v->abi_version >= SOF_ABI_VER(3, 7, 0)) {
sound/soc/sof/ipc3-dtrace.c
600
struct sof_ipc_fw_version *v = &ready->version;
sound/soc/sof/ipc3-dtrace.c
616
if (v->abi_version >= SOF_ABI_VER(3, 20, 0)) {
sound/soc/sof/ipc3-loader.c
17
const struct sof_ext_man_fw_version *v =
sound/soc/sof/ipc3-loader.c
20
memcpy(&sdev->fw_ready.version, &v->version, sizeof(v->version));
sound/soc/sof/ipc3-loader.c
21
sdev->fw_ready.flags = v->flags;
sound/soc/sof/ipc3-pcm.c
111
if (v->abi_version < SOF_ABI_VER(3, 10, 0))
sound/soc/sof/ipc3-pcm.c
46
struct sof_ipc_fw_version *v = &sdev->fw_ready.version;
sound/soc/sof/ipc3-topology.c
1466
struct sof_ipc_fw_version *v = &ready->version;
sound/soc/sof/ipc3-topology.c
1520
if (SOF_ABI_VER(v->major, v->minor, v->micro) < SOF_ABI_VER(3, 0, 1))
sound/soc/sof/ipc3-topology.c
2144
struct sof_ipc_fw_version *v = &sdev->fw_ready.version;
sound/soc/sof/ipc3-topology.c
2173
if (v->abi_version < SOF_ABI_VER(3, 18, 0) &&
sound/soc/sof/ipc3-topology.c
2286
struct sof_ipc_fw_version *v = &sdev->fw_ready.version;
sound/soc/sof/ipc3-topology.c
2301
if (v->abi_version < SOF_ABI_VER(3, 19, 0) &&
sound/soc/sof/ipc3-topology.c
2364
if (v->abi_version < SOF_ABI_VER(3, 19, 0)) {
sound/soc/sof/ipc3-topology.c
2417
struct sof_ipc_fw_version *v = &sdev->fw_ready.version;
sound/soc/sof/ipc3-topology.c
2429
SOF_FW_VER(v->major, v->minor, v->micro) < SOF_FW_VER(2, 2, 0)) {
sound/soc/sof/ipc3-topology.c
2458
struct sof_ipc_fw_version *v = &sdev->fw_ready.version;
sound/soc/sof/ipc3-topology.c
2482
if (!verify && (dyn_widgets || SOF_FW_VER(v->major, v->minor, v->micro) >=
sound/soc/sof/ipc3.c
777
struct sof_ipc_fw_version *v = &ready->version;
sound/soc/sof/ipc3.c
780
"Firmware info: version %d:%d:%d-%s\n", v->major, v->minor,
sound/soc/sof/ipc3.c
781
v->micro, v->tag);
sound/soc/sof/ipc3.c
784
SOF_ABI_VERSION_MAJOR(v->abi_version),
sound/soc/sof/ipc3.c
785
SOF_ABI_VERSION_MINOR(v->abi_version),
sound/soc/sof/ipc3.c
786
SOF_ABI_VERSION_PATCH(v->abi_version),
sound/soc/sof/ipc3.c
789
if (SOF_ABI_VERSION_INCOMPATIBLE(SOF_ABI_VERSION, v->abi_version)) {
sound/soc/sof/ipc3.c
795
SOF_ABI_VERSION_MINOR(v->abi_version) > SOF_ABI_MINOR) {
sound/soc/sof/ipc3.c
806
v->build, v->date, v->time,
sound/soc/sof/ipc3.c
812
memcpy(&sdev->fw_version, v, sizeof(*v));
sound/soc/sof/sof-audio.h
251
u32 v;
sound/soc/sof/topology.c
107
*val = (u16)tuples[j].value.v;
sound/soc/sof/topology.c
1204
return tuples[i].value.v;
sound/soc/sof/topology.c
593
tuples[*num_copied_tuples].value.v =
sound/soc/sof/topology.c
98
*val = tuples[j].value.v;
sound/soc/sunxi/sun4i-spdif.c
117
#define SUN4I_SPDIF_TXCHSTA0_CLK(v) ((v) << 28)
sound/soc/sunxi/sun4i-spdif.c
118
#define SUN4I_SPDIF_TXCHSTA0_SAMFREQ(v) ((v) << 24)
sound/soc/sunxi/sun4i-spdif.c
120
#define SUN4I_SPDIF_TXCHSTA0_CHNUM(v) ((v) << 20)
sound/soc/sunxi/sun4i-spdif.c
122
#define SUN4I_SPDIF_TXCHSTA0_SRCNUM(v) ((v) << 16)
sound/soc/sunxi/sun4i-spdif.c
123
#define SUN4I_SPDIF_TXCHSTA0_CATACOD(v) ((v) << 8)
sound/soc/sunxi/sun4i-spdif.c
124
#define SUN4I_SPDIF_TXCHSTA0_MODE(v) ((v) << 6)
sound/soc/sunxi/sun4i-spdif.c
125
#define SUN4I_SPDIF_TXCHSTA0_EMPHASIS(v) ((v) << 3)
sound/soc/sunxi/sun4i-spdif.c
131
#define SUN4I_SPDIF_TXCHSTA1_CGMSA(v) ((v) << 8)
sound/soc/sunxi/sun4i-spdif.c
132
#define SUN4I_SPDIF_TXCHSTA1_ORISAMFREQ(v) ((v) << 4)
sound/soc/sunxi/sun4i-spdif.c
134
#define SUN4I_SPDIF_TXCHSTA1_SAMWORDLEN(v) ((v) << 1)
sound/soc/sunxi/sun4i-spdif.c
138
#define SUN4I_SPDIF_RXCHSTA0_CLK(v) ((v) << 28)
sound/soc/sunxi/sun4i-spdif.c
139
#define SUN4I_SPDIF_RXCHSTA0_SAMFREQ(v) ((v) << 24)
sound/soc/sunxi/sun4i-spdif.c
140
#define SUN4I_SPDIF_RXCHSTA0_CHNUM(v) ((v) << 20)
sound/soc/sunxi/sun4i-spdif.c
141
#define SUN4I_SPDIF_RXCHSTA0_SRCNUM(v) ((v) << 16)
sound/soc/sunxi/sun4i-spdif.c
142
#define SUN4I_SPDIF_RXCHSTA0_CATACOD(v) ((v) << 8)
sound/soc/sunxi/sun4i-spdif.c
143
#define SUN4I_SPDIF_RXCHSTA0_MODE(v) ((v) << 6)
sound/soc/sunxi/sun4i-spdif.c
144
#define SUN4I_SPDIF_RXCHSTA0_EMPHASIS(v) ((v) << 3)
sound/soc/sunxi/sun4i-spdif.c
150
#define SUN4I_SPDIF_RXCHSTA1_CGMSA(v) ((v) << 8)
sound/soc/sunxi/sun4i-spdif.c
151
#define SUN4I_SPDIF_RXCHSTA1_ORISAMFREQ(v) ((v) << 4)
sound/soc/sunxi/sun4i-spdif.c
152
#define SUN4I_SPDIF_RXCHSTA1_SAMWORDLEN(v) ((v) << 1)
sound/soc/sunxi/sun4i-spdif.c
30
#define SUN4I_SPDIF_CTL_MCLKDIV(v) ((v) << 4) /* v even */
sound/soc/sunxi/sun4i-spdif.c
39
#define SUN4I_SPDIF_TXCFG_TXRATIO(v) ((v) << 4)
sound/soc/sunxi/sun4i-spdif.c
62
#define SUN4I_SPDIF_FCTL_TXTL(v) ((v) << 8)
sound/soc/sunxi/sun4i-spdif.c
64
#define SUN4I_SPDIF_FCTL_RXTL(v) ((v) << 3)
sound/soc/sunxi/sun4i-spdif.c
67
#define SUN4I_SPDIF_FCTL_RXOM(v) ((v) << 0)
sound/soc/sunxi/sun4i-spdif.c
74
#define SUN50I_H6_SPDIF_FCTL_TXTL(v) ((v) << 12)
sound/soc/sunxi/sun4i-spdif.c
76
#define SUN50I_H6_SPDIF_FCTL_RXTL(v) ((v) << 4)
sound/soc/sunxi/sun4i-spdif.c
79
#define SUN50I_H6_SPDIF_FCTL_RXOM(v) ((v) << 0)
sound/soc/sunxi/sun50i-dmic.c
21
#define SUN50I_DMIC_EN_CTL_CHAN(v) ((v) << 0)
sound/soc/sunxi/sun50i-dmic.c
24
#define SUN50I_DMIC_SR_SAMPLE_RATE(v) ((v) << 0)
sound/soc/sunxi/sun50i-dmic.c
43
#define SUN50I_DMIC_CH_NUM_N(v) ((v) << 0)
sound/soc/ti/davinci-i2s.c
63
#define DAVINCI_MCBSP_SPCR_RINTM(v) ((v) << 4)
sound/soc/ti/davinci-i2s.c
64
#define DAVINCI_MCBSP_SPCR_RJUST(v) ((v) << 13)
sound/soc/ti/davinci-i2s.c
68
#define DAVINCI_MCBSP_SPCR_XINTM(v) ((v) << 20)
sound/soc/ti/davinci-i2s.c
73
#define DAVINCI_MCBSP_RCR_RWDLEN1(v) ((v) << 5)
sound/soc/ti/davinci-i2s.c
74
#define DAVINCI_MCBSP_RCR_RFRLEN1(v) ((v) << 8)
sound/soc/ti/davinci-i2s.c
75
#define DAVINCI_MCBSP_RCR_RDATDLY(v) ((v) << 16)
sound/soc/ti/davinci-i2s.c
77
#define DAVINCI_MCBSP_RCR_RWDLEN2(v) ((v) << 21)
sound/soc/ti/davinci-i2s.c
78
#define DAVINCI_MCBSP_RCR_RFRLEN2(v) ((v) << 24)
sound/soc/ti/davinci-i2s.c
81
#define DAVINCI_MCBSP_XCR_XWDLEN1(v) ((v) << 5)
sound/soc/ti/davinci-i2s.c
82
#define DAVINCI_MCBSP_XCR_XFRLEN1(v) ((v) << 8)
sound/soc/ti/davinci-i2s.c
83
#define DAVINCI_MCBSP_XCR_XDATDLY(v) ((v) << 16)
sound/soc/ti/davinci-i2s.c
85
#define DAVINCI_MCBSP_XCR_XWDLEN2(v) ((v) << 21)
sound/soc/ti/davinci-i2s.c
86
#define DAVINCI_MCBSP_XCR_XFRLEN2(v) ((v) << 24)
sound/soc/ti/davinci-i2s.c
89
#define DAVINCI_MCBSP_SRGR_FWID(v) ((v) << 8)
sound/soc/ti/davinci-i2s.c
90
#define DAVINCI_MCBSP_SRGR_FPER(v) ((v) << 16)
sound/soc/uniphier/aio-core.c
1017
u32 v;
sound/soc/uniphier/aio-core.c
1020
v = CDA2D_STRT0_STOP_START;
sound/soc/uniphier/aio-core.c
1022
v = CDA2D_STRT0_STOP_STOP;
sound/soc/uniphier/aio-core.c
1025
v | BIT(sub->swm->och.map));
sound/soc/uniphier/aio-core.c
1031
u32 v;
sound/soc/uniphier/aio-core.c
1036
v = CDA2D_CHMXAMODE_ENDIAN_3210 |
sound/soc/uniphier/aio-core.c
1041
regmap_write(r, CDA2D_CHMXSRCAMODE(sub->swm->ch.map), v);
sound/soc/uniphier/aio-core.c
1043
regmap_write(r, CDA2D_CHMXDSTAMODE(sub->swm->ch.map), v);
sound/soc/uniphier/aio-core.c
111
u32 v;
sound/soc/uniphier/aio-core.c
137
v = A2APLLCTR1_APLLX_36MHZ;
sound/soc/uniphier/aio-core.c
140
v = A2APLLCTR1_APLLX_33MHZ;
sound/soc/uniphier/aio-core.c
149
v << shift);
sound/soc/uniphier/aio-core.c
334
u32 v;
sound/soc/uniphier/aio-core.c
339
v = OPORTMXCTR1_FSSEL_8;
sound/soc/uniphier/aio-core.c
342
v = OPORTMXCTR1_FSSEL_11_025;
sound/soc/uniphier/aio-core.c
345
v = OPORTMXCTR1_FSSEL_12;
sound/soc/uniphier/aio-core.c
348
v = OPORTMXCTR1_FSSEL_16;
sound/soc/uniphier/aio-core.c
351
v = OPORTMXCTR1_FSSEL_22_05;
sound/soc/uniphier/aio-core.c
354
v = OPORTMXCTR1_FSSEL_24;
sound/soc/uniphier/aio-core.c
357
v = OPORTMXCTR1_FSSEL_32;
sound/soc/uniphier/aio-core.c
360
v = OPORTMXCTR1_FSSEL_44_1;
sound/soc/uniphier/aio-core.c
363
v = OPORTMXCTR1_FSSEL_48;
sound/soc/uniphier/aio-core.c
366
v = OPORTMXCTR1_FSSEL_88_2;
sound/soc/uniphier/aio-core.c
369
v = OPORTMXCTR1_FSSEL_96;
sound/soc/uniphier/aio-core.c
372
v = OPORTMXCTR1_FSSEL_176_4;
sound/soc/uniphier/aio-core.c
375
v = OPORTMXCTR1_FSSEL_192;
sound/soc/uniphier/aio-core.c
383
OPORTMXCTR1_FSSEL_MASK, v);
sound/soc/uniphier/aio-core.c
387
v = IPORTMXCTR1_FSSEL_8;
sound/soc/uniphier/aio-core.c
390
v = IPORTMXCTR1_FSSEL_11_025;
sound/soc/uniphier/aio-core.c
393
v = IPORTMXCTR1_FSSEL_12;
sound/soc/uniphier/aio-core.c
396
v = IPORTMXCTR1_FSSEL_16;
sound/soc/uniphier/aio-core.c
399
v = IPORTMXCTR1_FSSEL_22_05;
sound/soc/uniphier/aio-core.c
402
v = IPORTMXCTR1_FSSEL_24;
sound/soc/uniphier/aio-core.c
405
v = IPORTMXCTR1_FSSEL_32;
sound/soc/uniphier/aio-core.c
408
v = IPORTMXCTR1_FSSEL_44_1;
sound/soc/uniphier/aio-core.c
411
v = IPORTMXCTR1_FSSEL_48;
sound/soc/uniphier/aio-core.c
414
v = IPORTMXCTR1_FSSEL_88_2;
sound/soc/uniphier/aio-core.c
417
v = IPORTMXCTR1_FSSEL_96;
sound/soc/uniphier/aio-core.c
420
v = IPORTMXCTR1_FSSEL_176_4;
sound/soc/uniphier/aio-core.c
423
v = IPORTMXCTR1_FSSEL_192;
sound/soc/uniphier/aio-core.c
431
IPORTMXCTR1_FSSEL_MASK, v);
sound/soc/uniphier/aio-core.c
453
u32 v;
sound/soc/uniphier/aio-core.c
458
v = OPORTMXCTR1_I2SLRSEL_LEFT;
sound/soc/uniphier/aio-core.c
461
v = OPORTMXCTR1_I2SLRSEL_RIGHT;
sound/soc/uniphier/aio-core.c
464
v = OPORTMXCTR1_I2SLRSEL_I2S;
sound/soc/uniphier/aio-core.c
472
v |= OPORTMXCTR1_OUTBITSEL_24;
sound/soc/uniphier/aio-core.c
475
OPORTMXCTR1_OUTBITSEL_MASK, v);
sound/soc/uniphier/aio-core.c
479
v = IPORTMXCTR1_LRSEL_LEFT;
sound/soc/uniphier/aio-core.c
482
v = IPORTMXCTR1_LRSEL_RIGHT;
sound/soc/uniphier/aio-core.c
485
v = IPORTMXCTR1_LRSEL_I2S;
sound/soc/uniphier/aio-core.c
493
v |= IPORTMXCTR1_OUTBITSEL_24 |
sound/soc/uniphier/aio-core.c
498
IPORTMXCTR1_CHSEL_MASK, v);
sound/soc/uniphier/aio-core.c
529
u32 v;
sound/soc/uniphier/aio-core.c
544
v = v_pll[sub->aio->pll_out] |
sound/soc/uniphier/aio-core.c
552
v |= OPORTMXCTR2_EXTLSIFSSEL_36;
sound/soc/uniphier/aio-core.c
555
v |= OPORTMXCTR2_EXTLSIFSSEL_24;
sound/soc/uniphier/aio-core.c
559
v = OPORTMXCTR2_ACLKSEL_A2PLL |
sound/soc/uniphier/aio-core.c
569
v = v_pll[sub->aio->pll_out] |
sound/soc/uniphier/aio-core.c
577
v |= OPORTMXCTR2_EXTLSIFSSEL_36;
sound/soc/uniphier/aio-core.c
580
v |= OPORTMXCTR2_EXTLSIFSSEL_24;
sound/soc/uniphier/aio-core.c
584
v = OPORTMXCTR2_ACLKSEL_A1 |
sound/soc/uniphier/aio-core.c
589
regmap_write(r, OPORTMXCTR2(sub->swm->oport.map), v);
sound/soc/uniphier/aio-core.c
591
v = IPORTMXCTR2_ACLKSEL_A1 |
sound/soc/uniphier/aio-core.c
595
regmap_write(r, IPORTMXCTR2(sub->swm->iport.map), v);
sound/soc/uniphier/aio-core.c
618
u32 v;
sound/soc/uniphier/aio-core.c
648
v = OPORTMXCTR3_SRCSEL_STREAM |
sound/soc/uniphier/aio-core.c
651
v = OPORTMXCTR3_SRCSEL_PCM |
sound/soc/uniphier/aio-core.c
654
v |= OPORTMXCTR3_IECTHUR_IECOUT |
sound/soc/uniphier/aio-core.c
657
regmap_write(r, OPORTMXCTR3(sub->swm->oport.map), v);
sound/soc/uniphier/aio-core.c
726
u32 v;
sound/soc/uniphier/aio-core.c
728
regmap_read(r, OPORTMXTYVOLGAINSTATUS(sub->swm->oport.map, 0), &v);
sound/soc/uniphier/aio-core.c
730
return FIELD_GET(OPORTMXTYVOLGAINSTATUS_CUR_MASK, v);
sound/soc/uniphier/aio-core.c
789
u32 memfmt, v;
sound/soc/uniphier/aio-core.c
793
v = PBOUTMXCTR0_ENDIAN_0123 |
sound/soc/uniphier/aio-core.c
809
v = PBOUTMXCTR0_ENDIAN_3210 | memfmt;
sound/soc/uniphier/aio-core.c
812
regmap_write(r, PBOUTMXCTR0(sub->swm->oif.map), v);
sound/soc/uniphier/aio-core.c
929
u32 v;
sound/soc/uniphier/aio-core.c
947
v = OPORTMXRATE_I_ACLKSEL_APLLA1 |
sound/soc/uniphier/aio-core.c
952
v = OPORTMXRATE_I_ACLKSEL_APLLA2 |
sound/soc/uniphier/aio-core.c
957
v = OPORTMXRATE_I_ACLKSEL_APLLA1 |
sound/soc/uniphier/aio-core.c
965
v | OPORTMXRATE_I_ACLKSRC_APLL |
sound/sparc/dbri.c
215
#define CS4215_LO(v) v /* Left Output Attenuation 0x3f: -94.5 dB */
sound/sparc/dbri.c
220
#define CS4215_RO(v) v /* Right Output Attenuation 0x3f: -94.5 dB */
sound/sparc/dbri.c
225
#define CS4215_LG(v) v /* Left Gain Setting 0xf: 22.5 dB */
sound/sparc/dbri.c
232
#define CS4215_RG(v) v /* Right Gain Setting 0xf: 22.5 dB */
sound/sparc/dbri.c
233
#define CS4215_MA(v) (v<<4) /* Monitor Path Attenuation 0xf: mute */
sound/sparc/dbri.c
380
#define D_PIPE(v) ((v)<<0) /* Pipe No.: 0-15 long, 16-21 short */
sound/sparc/dbri.c
396
#define D_SDP_MODE(v) ((v)&(7<<13))
sound/sparc/dbri.c
411
#define D_DTS_PRVIN(v) ((v)<<10) /* Previous In Pipe */
sound/sparc/dbri.c
412
#define D_DTS_PRVOUT(v) ((v)<<5) /* Previous Out Pipe */
sound/sparc/dbri.c
415
#define D_TS_LEN(v) ((v)<<24) /* Number of bits in this time slot */
sound/sparc/dbri.c
416
#define D_TS_CYCLE(v) ((v)<<14) /* Bit Count at start of TS */
sound/sparc/dbri.c
422
#define D_TS_MON(v) ((v)<<5) /* Monitor Pipe */
sound/sparc/dbri.c
423
#define D_TS_NEXT(v) ((v)<<0) /* Pipe no.: 0-15 long, 16-21 short */
sound/sparc/dbri.c
426
#define D_CHI_CHICM(v) ((v)<<16) /* Clock mode */
sound/sparc/dbri.c
432
#define D_CHI_BPF(v) ((v)<<0) /* Bits per Frame */
sound/sparc/dbri.c
445
#define D_NT_RLB(v) ((v)<<5) /* Remote Loopback */
sound/sparc/dbri.c
446
#define D_NT_LLB(v) ((v)<<2) /* Local Loopback */
sound/sparc/dbri.c
451
#define D_CDEC_CK(v) ((v)<<24) /* Clock Select */
sound/sparc/dbri.c
452
#define D_CDEC_FED(v) ((v)<<12) /* FSCOD Falling Edge Delay */
sound/sparc/dbri.c
453
#define D_CDEC_RED(v) ((v)<<0) /* FSCOD Rising Edge Delay */
sound/sparc/dbri.c
456
#define D_TEST_RAM(v) ((v)<<16) /* RAM Pointer */
sound/sparc/dbri.c
457
#define D_TEST_SIZE(v) ((v)<<11) /* */
sound/sparc/dbri.c
497
#define D_INTR_GETCHAN(v) (((v) >> 24) & 0x3f)
sound/sparc/dbri.c
498
#define D_INTR_GETCODE(v) (((v) >> 20) & 0xf)
sound/sparc/dbri.c
499
#define D_INTR_GETCMD(v) (((v) >> 16) & 0xf)
sound/sparc/dbri.c
500
#define D_INTR_GETVAL(v) ((v) & 0xffff)
sound/sparc/dbri.c
501
#define D_INTR_GETRVAL(v) ((v) & 0xfffff)
sound/sparc/dbri.c
539
#define DBRI_TD_CNT(v) ((v) << 16) /* Number of valid bytes in the buffer */
sound/sparc/dbri.c
543
#define DBRI_TD_FCNT(v) (v) /* Flag Count */
sound/sparc/dbri.c
547
#define DBRI_TD_STATUS(v) ((v) & 0xff) /* Transmit status */
sound/sparc/dbri.c
556
#define DBRI_RD_BCNT(v) (v) /* Buffer size */
sound/sparc/dbri.c
561
#define DBRI_RD_STATUS(v) ((v) & 0xff) /* Receive status */
sound/sparc/dbri.c
562
#define DBRI_RD_CNT(v) (((v) >> 16) & 0x1fff) /* Valid bytes in the buffer */
sound/synth/emux/emux_effect.c
203
origp = (unsigned char *)&vp->zone->v.parm + offset;
sound/synth/emux/emux_synth.c
518
#define LO_BYTE(v) ((v) & 0xff)
sound/synth/emux/emux_synth.c
519
#define HI_BYTE(v) (((v) >> 8) & 0xff)
sound/synth/emux/emux_synth.c
532
vp->reg = vp->zone->v;
sound/synth/emux/emux_synth.c
70
if (zp && zp->v.exclusiveClass)
sound/synth/emux/emux_synth.c
71
exclusive_note_off(emu, port, zp->v.exclusiveClass);
sound/synth/emux/soundfont.c
1002
smp->v.dummy = 0;
sound/synth/emux/soundfont.c
1003
smp->v.truesize = 0;
sound/synth/emux/soundfont.c
1004
smp->v.sf_id = sf->id;
sound/synth/emux/soundfont.c
1016
if (smp->v.size > 0) {
sound/synth/emux/soundfont.c
1029
sflist->mem_used += smp->v.truesize;
sound/synth/emux/soundfont.c
1031
zone->v.sample = sample_id; /* the last sample */
sound/synth/emux/soundfont.c
1032
zone->v.rate_offset = calc_rate_offset(patch.base_freq);
sound/synth/emux/soundfont.c
1034
zone->v.root = note / 100;
sound/synth/emux/soundfont.c
1035
zone->v.tune = -(note % 100);
sound/synth/emux/soundfont.c
1036
zone->v.low = (freq_to_note(patch.low_note) + 99) / 100;
sound/synth/emux/soundfont.c
1037
zone->v.high = freq_to_note(patch.high_note) / 100;
sound/synth/emux/soundfont.c
1039
zone->v.pan = (patch.panning + 128) / 2;
sound/synth/emux/soundfont.c
1043
(int)patch.base_freq, zone->v.rate_offset,
sound/synth/emux/soundfont.c
1044
zone->v.root, zone->v.tune, zone->v.low, zone->v.high);
sound/synth/emux/soundfont.c
1068
zone->v.parm.volatkhld =
sound/synth/emux/soundfont.c
1071
zone->v.parm.voldcysus = (calc_gus_sustain(patch.env_offset[2]) << 8) |
sound/synth/emux/soundfont.c
1073
zone->v.parm.volrelease = 0x8000 | snd_sf_calc_parm_decay(release);
sound/synth/emux/soundfont.c
1074
zone->v.attenuation = calc_gus_attenuation(patch.env_offset[0]);
sound/synth/emux/soundfont.c
1078
zone->v.parm.volatkhld,
sound/synth/emux/soundfont.c
1079
zone->v.parm.voldcysus,
sound/synth/emux/soundfont.c
1080
zone->v.parm.volrelease,
sound/synth/emux/soundfont.c
1081
zone->v.attenuation);
sound/synth/emux/soundfont.c
1087
zone->v.parm.volrelease = 0x807f;
sound/synth/emux/soundfont.c
1093
zone->v.parm.tremfrq = ((patch.tremolo_depth / 2) << 8) | rate;
sound/synth/emux/soundfont.c
1098
zone->v.parm.fm2frq2 = ((patch.vibrato_depth / 6) << 8) | rate;
sound/synth/emux/soundfont.c
1103
if (!(smp->v.mode_flags & SNDRV_SFNT_SAMPLE_SINGLESHOT))
sound/synth/emux/soundfont.c
1104
zone->v.mode = SNDRV_SFNT_MODE_LOOPING;
sound/synth/emux/soundfont.c
1106
zone->v.mode = 0;
sound/synth/emux/soundfont.c
1113
zone->v.sf_id = sf->id;
sound/synth/emux/soundfont.c
1115
zone->sample = set_sample(sf, &zone->v);
sound/synth/emux/soundfont.c
1155
cur->sample = set_sample(sf, &cur->v);
sound/synth/emux/soundfont.c
1175
zone = search_first_zone(sflist, cur->bank, cur->instr, cur->v.low);
sound/synth/emux/soundfont.c
1176
if (zone && zone->v.sf_id != cur->v.sf_id) {
sound/synth/emux/soundfont.c
1191
index = get_index(cur->bank, cur->instr, cur->v.low);
sound/synth/emux/soundfont.c
1208
index = get_index(zp->bank, zp->instr, zp->v.low);
sound/synth/emux/soundfont.c
1290
if (*notep >= zp->v.low && *notep <= zp->v.high &&
sound/synth/emux/soundfont.c
1291
vel >= zp->v.vellow && vel <= zp->v.velhigh) {
sound/synth/emux/soundfont.c
1294
int key = zp->v.fixkey;
sound/synth/emux/soundfont.c
1295
preset = zp->v.start;
sound/synth/emux/soundfont.c
1296
bank = zp->v.end;
sound/synth/emux/soundfont.c
1476
sflist->mem_used -= sp->v.truesize;
sound/synth/emux/soundfont.c
318
init_voice_info(&zp->v);
sound/synth/emux/soundfont.c
398
zp->v.low == map.map_key &&
sound/synth/emux/soundfont.c
399
zp->v.start == map.src_instr &&
sound/synth/emux/soundfont.c
400
zp->v.end == map.src_bank &&
sound/synth/emux/soundfont.c
401
zp->v.fixkey == map.src_key) {
sound/synth/emux/soundfont.c
424
zp->v.low = map.map_key;
sound/synth/emux/soundfont.c
425
zp->v.high = map.map_key;
sound/synth/emux/soundfont.c
427
zp->v.start = map.src_instr;
sound/synth/emux/soundfont.c
428
zp->v.end = map.src_bank;
sound/synth/emux/soundfont.c
429
zp->v.fixkey = map.src_key;
sound/synth/emux/soundfont.c
430
zp->v.sf_id = sf->id;
sound/synth/emux/soundfont.c
532
if (copy_from_user(&tmpzone.v, data, sizeof(tmpzone.v))) {
sound/synth/emux/soundfont.c
536
data += sizeof(tmpzone.v);
sound/synth/emux/soundfont.c
537
count -= sizeof(tmpzone.v);
sound/synth/emux/soundfont.c
542
tmpzone.v.sf_id = sf->id;
sound/synth/emux/soundfont.c
543
if (tmpzone.v.mode & SNDRV_SFNT_MODE_INIT_PARM)
sound/synth/emux/soundfont.c
544
init_voice_parm(&tmpzone.v.parm);
sound/synth/emux/soundfont.c
554
zone->v = tmpzone.v;
sound/synth/emux/soundfont.c
557
zone->sample = set_sample(sf, &zone->v);
sound/synth/emux/soundfont.c
625
avp->start += sample->v.start;
sound/synth/emux/soundfont.c
626
avp->end += sample->v.end;
sound/synth/emux/soundfont.c
627
avp->loopstart += sample->v.loopstart;
sound/synth/emux/soundfont.c
628
avp->loopend += sample->v.loopend;
sound/synth/emux/soundfont.c
631
avp->sample_mode = sample->v.mode_flags;
sound/synth/emux/soundfont.c
646
if (p->v.sample == sample_id)
sound/synth/emux/soundfont.c
729
sp->v = sample_info;
sound/synth/emux/soundfont.c
730
sp->v.sf_id = sf->id;
sound/synth/emux/soundfont.c
731
sp->v.dummy = 0;
sound/synth/emux/soundfont.c
732
sp->v.truesize = 0;
sound/synth/emux/soundfont.c
737
if (sp->v.size > 0) {
sound/synth/emux/soundfont.c
746
sflist->mem_used += sp->v.truesize;
sound/synth/emux/soundfont.c
787
int v;
sound/synth/emux/soundfont.c
797
v = (log_tbl[s + 1] * low + log_tbl[s] * (0x100 - low)) >> 8;
sound/synth/emux/soundfont.c
798
v -= offset;
sound/synth/emux/soundfont.c
799
v = (v * ratio) >> 16;
sound/synth/emux/soundfont.c
800
v += (24 - bit) * ratio;
sound/synth/emux/soundfont.c
801
return v;
sound/synth/emux/soundfont.c
967
smp->v.sample = sample_id;
sound/synth/emux/soundfont.c
968
smp->v.start = 0;
sound/synth/emux/soundfont.c
969
smp->v.end = patch.len;
sound/synth/emux/soundfont.c
970
smp->v.loopstart = patch.loop_start;
sound/synth/emux/soundfont.c
971
smp->v.loopend = patch.loop_end;
sound/synth/emux/soundfont.c
972
smp->v.size = patch.len;
sound/synth/emux/soundfont.c
974
if (validate_sample_info(&smp->v) < 0) {
sound/synth/emux/soundfont.c
980
smp->v.mode_flags = 0;
sound/synth/emux/soundfont.c
982
smp->v.mode_flags |= SNDRV_SFNT_SAMPLE_8BITS;
sound/synth/emux/soundfont.c
984
smp->v.mode_flags |= SNDRV_SFNT_SAMPLE_UNSIGNED;
sound/synth/emux/soundfont.c
985
smp->v.mode_flags |= SNDRV_SFNT_SAMPLE_NO_BLANK;
sound/synth/emux/soundfont.c
987
smp->v.mode_flags |= SNDRV_SFNT_SAMPLE_SINGLESHOT;
sound/synth/emux/soundfont.c
989
smp->v.mode_flags |= SNDRV_SFNT_SAMPLE_BIDIR_LOOP;
sound/synth/emux/soundfont.c
991
smp->v.mode_flags |= SNDRV_SFNT_SAMPLE_REVERSE_LOOP;
sound/synth/emux/soundfont.c
995
smp->v.size /= 2;
sound/synth/emux/soundfont.c
996
smp->v.end /= 2;
sound/synth/emux/soundfont.c
997
smp->v.loopstart /= 2;
sound/synth/emux/soundfont.c
998
smp->v.loopend /= 2;
sound/usb/caiaq/control.c
107
cdev->control_state[i] = v;
sound/usb/caiaq/control.c
114
cdev->ep8_out_buf[1] = v;
sound/usb/caiaq/control.c
139
if (v)
sound/usb/caiaq/control.c
89
int v = ucontrol->value.integer.value[0];
sound/usb/mixer_quirks.c
3130
u32 v;
sound/usb/mixer_quirks.c
3138
v = value & SND_BBFPRO_MIXER_VAL_MASK;
sound/usb/mixer_quirks.c
3139
usb_idx = idx | (v & 0x3) << 14;
sound/usb/mixer_quirks.c
3140
usb_val = (v >> 2) & 0xffff;
sound/usb/mixer_scarlett2.c
3181
static uint8_t scarlett2_decode_muteable(uint8_t v)
sound/usb/mixer_scarlett2.c
3183
return (v ^ (v >> 1)) & 1;
sound/usb/usx2y/us122l.c
85
static void pt_info_set(struct usb_device *dev, u8 v)
sound/usb/usx2y/us122l.c
89
v, 0, NULL, 0, 1000, GFP_NOIO);
sound/usb/validate.c
108
switch (v->protocol) {
sound/usb/validate.c
111
if (v->type == UAC1_EXTENSION_UNIT)
sound/usb/validate.c
126
if (v->type == UAC2_EXTENSION_UNIT_V2)
sound/usb/validate.c
141
if (v->type == UAC3_EXTENSION_UNIT) {
sound/usb/validate.c
168
const struct usb_desc_validator *v)
sound/usb/validate.c
176
switch (v->protocol) {
sound/usb/validate.c
18
bool (*func)(const void *p, const struct usb_desc_validator *v);
sound/usb/validate.c
192
const struct usb_desc_validator *v)
sound/usb/validate.c
203
const struct usb_desc_validator *v)
sound/usb/validate.c
214
const struct usb_desc_validator *v)
sound/usb/validate.c
225
const struct usb_desc_validator *v)
sound/usb/validate.c
236
const struct usb_desc_validator *v)
sound/usb/validate.c
26
const struct usb_desc_validator *v)
sound/usb/validate.c
321
const struct usb_desc_validator *v)
sound/usb/validate.c
326
for (; v->type; v++) {
sound/usb/validate.c
327
if (v->type == hdr[2] &&
sound/usb/validate.c
328
(v->protocol == UAC_VERSION_ALL ||
sound/usb/validate.c
329
v->protocol == protocol)) {
sound/usb/validate.c
330
if (v->func)
sound/usb/validate.c
331
return v->func(hdr, v);
sound/usb/validate.c
333
return hdr[0] >= v->size;
sound/usb/validate.c
36
const struct usb_desc_validator *v)
sound/usb/validate.c
48
switch (v->protocol) {
sound/usb/validate.c
70
const struct usb_desc_validator *v)
sound/usb/validate.c
81
switch (v->protocol) {
sound/usb/validate.c
94
if (v->type == UAC2_PROCESSING_UNIT_V2)
tools/arch/arm64/include/asm/barrier.h
27
#define smp_store_release(p, v) \
tools/arch/arm64/include/asm/barrier.h
30
{ .__val = (v) }; \
tools/arch/arm64/include/asm/cputype.h
280
#define MIDR_REV_RANGE(m, v, r_min, r_max) MIDR_RANGE(m, v, r_min, v, r_max)
tools/arch/arm64/include/asm/cputype.h
281
#define MIDR_REV(m, v, r) MIDR_RANGE(m, v, r, v, r)
tools/arch/arm64/include/asm/sysreg.h
1110
#define __mrs_s(v, r) \
tools/arch/arm64/include/asm/sysreg.h
1112
" mrs_s " v ", " __stringify(r) "\n" \
tools/arch/arm64/include/asm/sysreg.h
1115
#define __msr_s(r, v) \
tools/arch/arm64/include/asm/sysreg.h
1117
" msr_s " __stringify(r) ", " v "\n" \
tools/arch/arm64/include/asm/sysreg.h
1134
#define write_sysreg(v, r) do { \
tools/arch/arm64/include/asm/sysreg.h
1135
u64 __val = (u64)(v); \
tools/arch/arm64/include/asm/sysreg.h
1155
#define write_sysreg_s(v, r) do { \
tools/arch/arm64/include/asm/sysreg.h
1156
u64 __val = (u64)(v); \
tools/arch/powerpc/include/asm/barrier.h
33
#define smp_store_release(p, v) \
tools/arch/powerpc/include/asm/barrier.h
36
WRITE_ONCE(*p, v); \
tools/arch/riscv/include/asm/barrier.h
26
#define smp_store_release(p, v) \
tools/arch/riscv/include/asm/barrier.h
29
WRITE_ONCE(*p, v); \
tools/arch/s390/include/asm/barrier.h
31
#define smp_store_release(p, v) \
tools/arch/s390/include/asm/barrier.h
34
WRITE_ONCE(*p, v); \
tools/arch/sparc/include/asm/barrier_64.h
43
#define smp_store_release(p, v) \
tools/arch/sparc/include/asm/barrier_64.h
46
WRITE_ONCE(*p, v); \
tools/arch/x86/include/asm/atomic.h
27
static inline int atomic_read(const atomic_t *v)
tools/arch/x86/include/asm/atomic.h
29
return READ_ONCE((v)->counter);
tools/arch/x86/include/asm/atomic.h
39
static inline void atomic_set(atomic_t *v, int i)
tools/arch/x86/include/asm/atomic.h
41
v->counter = i;
tools/arch/x86/include/asm/atomic.h
50
static inline void atomic_inc(atomic_t *v)
tools/arch/x86/include/asm/atomic.h
53
: "+m" (v->counter));
tools/arch/x86/include/asm/atomic.h
64
static inline int atomic_dec_and_test(atomic_t *v)
tools/arch/x86/include/asm/atomic.h
66
GEN_UNARY_RMWcc(LOCK_PREFIX "decl", v->counter, "%0", "e");
tools/arch/x86/include/asm/atomic.h
69
static __always_inline int atomic_cmpxchg(atomic_t *v, int old, int new)
tools/arch/x86/include/asm/atomic.h
71
return cmpxchg(&v->counter, old, new);
tools/arch/x86/include/asm/barrier.h
33
#define smp_store_release(p, v) \
tools/arch/x86/include/asm/barrier.h
36
WRITE_ONCE(*p, v); \
tools/arch/x86/include/asm/insn.h
26
static inline void insn_field_set(struct insn_field *p, insn_value_t v,
tools/arch/x86/include/asm/insn.h
29
p->value = v;
tools/arch/x86/include/asm/insn.h
34
insn_byte_t v)
tools/arch/x86/include/asm/insn.h
36
p->bytes[n] = v;
tools/arch/x86/include/asm/insn.h
52
static inline void insn_field_set(struct insn_field *p, insn_value_t v,
tools/arch/x86/include/asm/insn.h
55
p->value = v;
tools/arch/x86/include/asm/insn.h
56
p->little = __cpu_to_le32(v);
tools/arch/x86/include/asm/insn.h
61
insn_byte_t v)
tools/arch/x86/include/asm/insn.h
63
p->bytes[n] = v;
tools/arch/x86/include/asm/io.h
48
#define writeb_relaxed(v, a) __writeb(v, a)
tools/arch/x86/include/asm/io.h
49
#define writew_relaxed(v, a) __writew(v, a)
tools/arch/x86/include/asm/io.h
50
#define writel_relaxed(v, a) __writel(v, a)
tools/arch/x86/include/asm/io.h
63
#define writeq_relaxed(v, a) __writeq(v, a)
tools/arch/x86/lib/insn.c
25
__typeof__(t) v; \
tools/arch/x86/lib/insn.c
27
case 4: v = le32_to_cpu(r); break; \
tools/arch/x86/lib/insn.c
28
case 2: v = le16_to_cpu(r); break; \
tools/arch/x86/lib/insn.c
29
case 1: v = r; break; \
tools/arch/x86/lib/insn.c
33
v; \
tools/bpf/bpftool/btf.c
137
__u32 v = *(__u32 *)(t + 1);
tools/bpf/bpftool/btf.c
140
enc = btf_int_enc_str(BTF_INT_ENCODING(v));
tools/bpf/bpftool/btf.c
144
jsonw_uint_field(w, "bits_offset", BTF_INT_OFFSET(v));
tools/bpf/bpftool/btf.c
145
jsonw_uint_field(w, "nr_bits", BTF_INT_BITS(v));
tools/bpf/bpftool/btf.c
149
t->size, BTF_INT_OFFSET(v), BTF_INT_BITS(v),
tools/bpf/bpftool/btf.c
226
const struct btf_enum *v = (const void *)(t + 1);
tools/bpf/bpftool/btf.c
241
for (i = 0; i < vlen; i++, v++) {
tools/bpf/bpftool/btf.c
242
const char *name = btf_str(btf, v->name_off);
tools/bpf/bpftool/btf.c
248
jsonw_int_field(w, "val", v->val);
tools/bpf/bpftool/btf.c
250
jsonw_uint_field(w, "val", v->val);
tools/bpf/bpftool/btf.c
254
printf("\n\t'%s' val=%d", name, v->val);
tools/bpf/bpftool/btf.c
256
printf("\n\t'%s' val=%u", name, (__u32)v->val);
tools/bpf/bpftool/btf.c
264
const struct btf_enum64 *v = btf_enum64(t);
tools/bpf/bpftool/btf.c
279
for (i = 0; i < vlen; i++, v++) {
tools/bpf/bpftool/btf.c
280
const char *name = btf_str(btf, v->name_off);
tools/bpf/bpftool/btf.c
281
__u64 val = ((__u64)v->val_hi32 << 32) | v->val_lo32;
tools/bpf/bpftool/btf.c
355
const struct btf_var *v = (const void *)(t + 1);
tools/bpf/bpftool/btf.c
358
linkage = btf_var_linkage_str(v->linkage);
tools/bpf/bpftool/btf.c
369
const struct btf_var_secinfo *v = (const void *)(t + 1);
tools/bpf/bpftool/btf.c
382
for (i = 0; i < vlen; i++, v++) {
tools/bpf/bpftool/btf.c
385
jsonw_uint_field(w, "type_id", v->type);
tools/bpf/bpftool/btf.c
386
jsonw_uint_field(w, "offset", v->offset);
tools/bpf/bpftool/btf.c
387
jsonw_uint_field(w, "size", v->size);
tools/bpf/bpftool/btf.c
391
v->type, v->offset, v->size);
tools/bpf/bpftool/btf.c
393
if (v->type < btf__type_cnt(btf)) {
tools/bpf/bpftool/btf.c
394
vt = btf__type_by_id(btf, v->type);
tools/bpf/bpftool/gen.c
319
const struct btf_type *v)
tools/bpf/bpftool/gen.c
321
return btf_is_ptr(v) && btf_is_func_proto(btf__type_by_id(btf, v->type));
tools/include/asm-generic/atomic-gcc.h
24
static inline int atomic_read(const atomic_t *v)
tools/include/asm-generic/atomic-gcc.h
26
return READ_ONCE((v)->counter);
tools/include/asm-generic/atomic-gcc.h
36
static inline void atomic_set(atomic_t *v, int i)
tools/include/asm-generic/atomic-gcc.h
38
v->counter = i;
tools/include/asm-generic/atomic-gcc.h
47
static inline void atomic_inc(atomic_t *v)
tools/include/asm-generic/atomic-gcc.h
49
__sync_add_and_fetch(&v->counter, 1);
tools/include/asm-generic/atomic-gcc.h
60
static inline int atomic_dec_and_test(atomic_t *v)
tools/include/asm-generic/atomic-gcc.h
62
return __sync_sub_and_fetch(&v->counter, 1) == 0;
tools/include/asm-generic/atomic-gcc.h
68
static inline int atomic_cmpxchg(atomic_t *v, int oldval, int newval)
tools/include/asm-generic/atomic-gcc.h
70
return cmpxchg(&(v)->counter, oldval, newval);
tools/include/asm-generic/io.h
23
#define __io_ar(v) rmb()
tools/include/asm-generic/io.h
25
#define __io_ar(v) barrier()
tools/include/asm-generic/io.h
56
#define __io_par(v) __io_ar(v)
tools/include/asm/barrier.h
51
# define smp_store_release(p, v) \
tools/include/asm/barrier.h
54
WRITE_ONCE(*p, v); \
tools/include/linux/atomic.h
25
static inline bool atomic_inc_unless_negative(atomic_t *v)
tools/include/linux/atomic.h
27
int c = atomic_read(v);
tools/include/linux/atomic.h
32
} while (!atomic_try_cmpxchg(v, &c, c + 1));
tools/include/linux/atomic.h
7
void atomic_long_set(atomic_long_t *v, long i);
tools/include/linux/bitfield.h
146
static __always_inline __##type type##_encode_bits(base v, base field) \
tools/include/linux/bitfield.h
148
if (__builtin_constant_p(v) && (v & ~field_mask(field))) \
tools/include/linux/bitfield.h
150
return to((v & field_mask(field)) * field_multiplier(field)); \
tools/include/linux/bitfield.h
162
static __always_inline base type##_get_bits(__##type v, base field) \
tools/include/linux/bitfield.h
164
return (from(v) & field)/field_multiplier(field); \
tools/include/linux/rcu.h
22
#define rcu_assign_pointer(p, v) do { (p) = (v); } while (0)
tools/include/linux/rcu.h
23
#define RCU_INIT_POINTER(p, v) do { (p) = (v); } while (0)
tools/include/nolibc/errno.h
16
#define SET_ERRNO(v) do { errno = (v); } while (0)
tools/include/nolibc/errno.h
19
#define SET_ERRNO(v) do { } while (0)
tools/include/nolibc/stdarg.h
11
#define va_start(v, l) __builtin_va_start(v, l)
tools/include/nolibc/stdarg.h
12
#define va_end(v) __builtin_va_end(v)
tools/include/nolibc/stdarg.h
13
#define va_arg(v, l) __builtin_va_arg(v, l)
tools/include/nolibc/stdio.h
305
unsigned long long v;
tools/include/nolibc/stdio.h
332
v = va_arg(args, unsigned long);
tools/include/nolibc/stdio.h
335
v = va_arg(args, unsigned long long);
tools/include/nolibc/stdio.h
337
v = va_arg(args, unsigned long);
tools/include/nolibc/stdio.h
339
v = va_arg(args, unsigned int);
tools/include/nolibc/stdio.h
344
v = (long long)(int)v;
tools/include/nolibc/stdio.h
346
v = (long long)(long)v;
tools/include/nolibc/stdio.h
351
out[0] = v;
tools/include/nolibc/stdio.h
355
i64toa_r(v, out);
tools/include/nolibc/stdio.h
358
u64toa_r(v, out);
tools/include/nolibc/stdio.h
365
u64toh_r(v, out);
tools/include/uapi/linux/pkt_cls.h
529
#define TCF_EM_REL_VALID(v) (((v) & TCF_EM_REL_MASK) != TCF_EM_REL_MASK)
tools/lib/bpf/btf.c
2503
struct btf_enum *v;
tools/lib/bpf/btf.c
2524
v = btf_add_type_mem(btf, sz);
tools/lib/bpf/btf.c
2525
if (!v)
tools/lib/bpf/btf.c
2532
v->name_off = name_off;
tools/lib/bpf/btf.c
2533
v->val = value;
tools/lib/bpf/btf.c
2579
struct btf_enum64 *v;
tools/lib/bpf/btf.c
2599
v = btf_add_type_mem(btf, sz);
tools/lib/bpf/btf.c
2600
if (!v)
tools/lib/bpf/btf.c
2607
v->name_off = name_off;
tools/lib/bpf/btf.c
2608
v->val_lo32 = (__u32)value;
tools/lib/bpf/btf.c
2609
v->val_hi32 = value >> 32;
tools/lib/bpf/btf.c
2872
struct btf_var *v;
tools/lib/bpf/btf.c
2901
v = btf_var(t);
tools/lib/bpf/btf.c
2902
v->linkage = linkage;
tools/lib/bpf/btf.c
2961
struct btf_var_secinfo *v;
tools/lib/bpf/btf.c
2979
v = btf_add_type_mem(btf, sz);
tools/lib/bpf/btf.c
2980
if (!v)
tools/lib/bpf/btf.c
2983
v->type = var_type_id;
tools/lib/bpf/btf.c
2984
v->offset = offset;
tools/lib/bpf/btf.c
2985
v->size = byte_sz;
tools/lib/bpf/btf.c
347
struct btf_var_secinfo *v;
tools/lib/bpf/btf.c
407
for (i = 0, v = btf_var_secinfos(t); i < vlen; i++, v++) {
tools/lib/bpf/btf.c
408
v->type = bswap_32(v->type);
tools/lib/bpf/btf.c
409
v->offset = bswap_32(v->offset);
tools/lib/bpf/btf.c
410
v->size = bswap_32(v->size);
tools/lib/bpf/btf_dump.c
1069
const struct btf_enum *v = btf_enum(t);
tools/lib/bpf/btf_dump.c
1076
for (i = 0; i < vlen; i++, v++) {
tools/lib/bpf/btf_dump.c
1077
name = btf_name_of(d, v->name_off);
tools/lib/bpf/btf_dump.c
1082
btf_dump_printf(d, fmt_str, pfx(lvl + 1), name, dup_cnt, v->val);
tools/lib/bpf/btf_dump.c
1085
btf_dump_printf(d, fmt_str, pfx(lvl + 1), name, v->val);
tools/lib/bpf/btf_dump.c
1094
const struct btf_enum64 *v = btf_enum64(t);
tools/lib/bpf/btf_dump.c
1102
for (i = 0; i < vlen; i++, v++) {
tools/lib/bpf/btf_dump.c
1103
name = btf_name_of(d, v->name_off);
tools/lib/bpf/btf_dump.c
1105
val = btf_enum64_value(v);
tools/lib/bpf/btf_dump.c
2010
const struct btf_type *v,
tools/lib/bpf/btf_dump.c
2014
enum btf_func_linkage linkage = btf_var(v)->linkage;
tools/lib/bpf/btf_dump.c
2036
type_id = v->type;
tools/lib/bpf/btf_dump.c
2039
btf_dump_printf(d, " %s = ", btf_name_of(d, v->name_off));
tools/lib/bpf/btf_dump.c
368
const struct btf_var_secinfo *v = btf_var_secinfos(t);
tools/lib/bpf/btf_dump.c
370
for (j = 0; j < vlen; j++, v++)
tools/lib/bpf/btf_dump.c
371
d->type_states[v->type].referenced = 1;
tools/lib/bpf/libbpf.c
2177
static bool is_kcfg_value_in_range(const struct extern_desc *ext, __u64 v)
tools/lib/bpf/libbpf.c
2197
return v + (1ULL << (bit_sz - 1)) < (1ULL << bit_sz);
tools/lib/bpf/libbpf.c
2199
return (v >> bit_sz) == 0;
tools/lib/bpf/libbpf.c
3175
const struct btf_var_secinfo *v = btf_var_secinfos(t);
tools/lib/bpf/libbpf.c
3189
for (j = 0; j < vlen; j++, v++, m++) {
tools/lib/bpf/libbpf.c
3191
m->offset = v->offset * 8;
tools/lib/bpf/libbpf.c
3192
m->type = v->type;
tools/lib/bpf/libbpf.c
3194
vt = (void *)btf__type_by_id(btf, v->type);
tools/lib/bpf/libbpf_internal.h
729
static inline __u32 ror32(__u32 v, int bits)
tools/lib/bpf/libbpf_internal.h
731
return (v >> bits) | (v << (32 - bits));
tools/lib/subcmd/parse-options.h
114
#define check_vtype(v, type) ( BUILD_BUG_ON_ZERO(!__builtin_types_compatible_p(typeof(v), type)) + v )
tools/lib/subcmd/parse-options.h
120
#define OPT_BIT(s, l, v, h, b) { .type = OPTION_BIT, .short_name = (s), .long_name = (l), .value = check_vtype(v, int *), .help = (h), .defval = (b) }
tools/lib/subcmd/parse-options.h
121
#define OPT_BOOLEAN(s, l, v, h) { .type = OPTION_BOOLEAN, .short_name = (s), .long_name = (l), .value = check_vtype(v, bool *), .help = (h) }
tools/lib/subcmd/parse-options.h
122
#define OPT_BOOLEAN_FLAG(s, l, v, h, f) { .type = OPTION_BOOLEAN, .short_name = (s), .long_name = (l), .value = check_vtype(v, bool *), .help = (h), .flags = (f) }
tools/lib/subcmd/parse-options.h
123
#define OPT_BOOLEAN_SET(s, l, v, os, h) \
tools/lib/subcmd/parse-options.h
125
.value = check_vtype(v, bool *), .help = (h), \
tools/lib/subcmd/parse-options.h
127
#define OPT_INCR(s, l, v, h) { .type = OPTION_INCR, .short_name = (s), .long_name = (l), .value = check_vtype(v, int *), .help = (h) }
tools/lib/subcmd/parse-options.h
128
#define OPT_SET_UINT(s, l, v, h, i) { .type = OPTION_SET_UINT, .short_name = (s), .long_name = (l), .value = check_vtype(v, unsigned int *), .help = (h), .defval = (i) }
tools/lib/subcmd/parse-options.h
129
#define OPT_SET_PTR(s, l, v, h, p) { .type = OPTION_SET_PTR, .short_name = (s), .long_name = (l), .value = (v), .help = (h), .defval = (p) }
tools/lib/subcmd/parse-options.h
130
#define OPT_INTEGER(s, l, v, h) { .type = OPTION_INTEGER, .short_name = (s), .long_name = (l), .value = check_vtype(v, int *), .help = (h) }
tools/lib/subcmd/parse-options.h
131
#define OPT_UINTEGER(s, l, v, h) { .type = OPTION_UINTEGER, .short_name = (s), .long_name = (l), .value = check_vtype(v, unsigned int *), .help = (h) }
tools/lib/subcmd/parse-options.h
132
#define OPT_UINTEGER_OPTARG(s, l, v, d, h) { .type = OPTION_UINTEGER, .short_name = (s), .long_name = (l), .value = check_vtype(v, unsigned int *), .help = (h), .flags = PARSE_OPT_OPTARG, .defval = (intptr_t)(d) }
tools/lib/subcmd/parse-options.h
133
#define OPT_LONG(s, l, v, h) { .type = OPTION_LONG, .short_name = (s), .long_name = (l), .value = check_vtype(v, long *), .help = (h) }
tools/lib/subcmd/parse-options.h
134
#define OPT_ULONG(s, l, v, h) { .type = OPTION_ULONG, .short_name = (s), .long_name = (l), .value = check_vtype(v, unsigned long *), .help = (h) }
tools/lib/subcmd/parse-options.h
135
#define OPT_U64(s, l, v, h) { .type = OPTION_U64, .short_name = (s), .long_name = (l), .value = check_vtype(v, u64 *), .help = (h) }
tools/lib/subcmd/parse-options.h
136
#define OPT_STRING(s, l, v, a, h) { .type = OPTION_STRING, .short_name = (s), .long_name = (l), .value = check_vtype(v, const char **), .argh = (a), .help = (h) }
tools/lib/subcmd/parse-options.h
137
#define OPT_STRING_OPTARG(s, l, v, a, h, d) \
tools/lib/subcmd/parse-options.h
139
.value = check_vtype(v, const char **), .argh =(a), .help = (h), \
tools/lib/subcmd/parse-options.h
141
#define OPT_STRING_OPTARG_SET(s, l, v, os, a, h, d) \
tools/lib/subcmd/parse-options.h
143
.value = check_vtype(v, const char **), .argh = (a), .help = (h), \
tools/lib/subcmd/parse-options.h
146
#define OPT_STRING_NOEMPTY(s, l, v, a, h) { .type = OPTION_STRING, .short_name = (s), .long_name = (l), .value = check_vtype(v, const char **), .argh = (a), .help = (h), .flags = PARSE_OPT_NOEMPTY}
tools/lib/subcmd/parse-options.h
147
#define OPT_DATE(s, l, v, h) \
tools/lib/subcmd/parse-options.h
148
{ .type = OPTION_CALLBACK, .short_name = (s), .long_name = (l), .value = (v), .argh = "time", .help = (h), .callback = parse_opt_approxidate_cb }
tools/lib/subcmd/parse-options.h
149
#define OPT_CALLBACK(s, l, v, a, h, f) \
tools/lib/subcmd/parse-options.h
150
{ .type = OPTION_CALLBACK, .short_name = (s), .long_name = (l), .value = (v), .argh = (a), .help = (h), .callback = (f) }
tools/lib/subcmd/parse-options.h
151
#define OPT_CALLBACK_SET(s, l, v, os, a, h, f) \
tools/lib/subcmd/parse-options.h
152
{ .type = OPTION_CALLBACK, .short_name = (s), .long_name = (l), .value = (v), .argh = (a), .help = (h), .callback = (f), .set = check_vtype(os, bool *)}
tools/lib/subcmd/parse-options.h
153
#define OPT_CALLBACK_NOOPT(s, l, v, a, h, f) \
tools/lib/subcmd/parse-options.h
154
{ .type = OPTION_CALLBACK, .short_name = (s), .long_name = (l), .value = (v), .argh = (a), .help = (h), .callback = (f), .flags = PARSE_OPT_NOARG }
tools/lib/subcmd/parse-options.h
155
#define OPT_CALLBACK_DEFAULT(s, l, v, a, h, f, d) \
tools/lib/subcmd/parse-options.h
156
{ .type = OPTION_CALLBACK, .short_name = (s), .long_name = (l), .value = (v), .argh = (a), .help = (h), .callback = (f), .defval = (intptr_t)d, .flags = PARSE_OPT_LASTARG_DEFAULT }
tools/lib/subcmd/parse-options.h
157
#define OPT_CALLBACK_DEFAULT_NOOPT(s, l, v, a, h, f, d) \
tools/lib/subcmd/parse-options.h
159
.value = (v), .arg = (a), .help = (h), .callback = (f), .defval = (intptr_t)d,\
tools/lib/subcmd/parse-options.h
161
#define OPT_CALLBACK_OPTARG(s, l, v, d, a, h, f) \
tools/lib/subcmd/parse-options.h
163
.value = (v), .argh = (a), .help = (h), .callback = (f), \
tools/perf/arch/arm/util/cs-etm.c
568
enum cs_etm_version v = cs_etm_get_version(cs_etm_pmu, cpu);
tools/perf/arch/arm/util/cs-etm.c
570
ete += v == CS_ETE;
tools/perf/arch/arm/util/cs-etm.c
571
etmv4 += v == CS_ETMV4;
tools/perf/arch/arm/util/cs-etm.c
572
etmv3 += v == CS_ETMV3;
tools/perf/tests/parse-metric.c
24
struct value *v = values;
tools/perf/tests/parse-metric.c
26
while (v->event) {
tools/perf/tests/parse-metric.c
27
if (!strcmp(name, v->event))
tools/perf/tests/parse-metric.c
28
return v->val;
tools/perf/tests/parse-metric.c
29
v++;
tools/perf/tests/pmu-events.c
767
double v;
tools/perf/tests/pmu-events.c
770
v = strtod(str, &end_ptr);
tools/perf/tests/pmu-events.c
771
(void)v; // We're not interested in this value, only if it is valid
tools/perf/tests/shell/coresight/memcpy_thread/memcpy_thread.c
48
long long v;
tools/perf/tests/shell/coresight/memcpy_thread/memcpy_thread.c
55
v = atoll(argv[1]);
tools/perf/tests/shell/coresight/memcpy_thread/memcpy_thread.c
56
if ((v < 1) || (v > (1024 * 1024))) {
tools/perf/tests/shell/coresight/memcpy_thread/memcpy_thread.c
60
size = v;
tools/perf/tests/shell/coresight/memcpy_thread/memcpy_thread.c
66
v = atoll(argv[3]);
tools/perf/tests/shell/coresight/memcpy_thread/memcpy_thread.c
67
if ((v < 1) || (v > 40000000000ll)) {
tools/perf/tests/shell/coresight/memcpy_thread/memcpy_thread.c
71
len = v * 100;
tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h
126
#define SPE_OP_PKT_OTHER_SUBCLASS_OTHER(v) (((v) & GENMASK_ULL(7, 3)) == 0x0)
tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h
127
#define SPE_OP_PKT_OTHER_SUBCLASS_SVE(v) (((v) & (BIT(7) | BIT(3) | BIT(0))) == 0x8)
tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h
128
#define SPE_OP_PKT_OTHER_SUBCLASS_SME(v) (((v) & (BIT(7) | BIT(3) | BIT(0))) == 0x88)
tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h
140
#define SPE_OP_PKG_SME_ETS(v) (128 << (FIELD_GET(GENMASK_ULL(6, 4), (v)) << 1 | \
tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h
141
(FIELD_GET(BIT(2), (v)))))
tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h
143
#define SPE_OP_PKT_LDST_SUBCLASS_GP_REG(v) (((v) & GENMASK_ULL(7, 1)) == 0x0)
tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h
144
#define SPE_OP_PKT_LDST_SUBCLASS_SIMD_FP(v) (((v) & GENMASK_ULL(7, 1)) == 0x4)
tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h
145
#define SPE_OP_PKT_LDST_SUBCLASS_UNSPEC_REG(v) (((v) & GENMASK_ULL(7, 1)) == 0x10)
tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h
146
#define SPE_OP_PKT_LDST_SUBCLASS_NV_SYSREG(v) (((v) & GENMASK_ULL(7, 1)) == 0x30)
tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h
147
#define SPE_OP_PKT_LDST_SUBCLASS_MTE_TAG(v) (((v) & GENMASK_ULL(7, 1)) == 0x14)
tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h
148
#define SPE_OP_PKT_LDST_SUBCLASS_MEMCPY(v) (((v) & GENMASK_ULL(7, 1)) == 0x20)
tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h
149
#define SPE_OP_PKT_LDST_SUBCLASS_MEMSET(v) (((v) & GENMASK_ULL(7, 0)) == 0x25)
tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h
151
#define SPE_OP_PKT_LDST_SUBCLASS_EXTENDED(v) (((v) & (GENMASK_ULL(7, 5) | BIT(1))) == 0x2)
tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h
158
#define SPE_OP_PKT_LDST_SUBCLASS_SVE_SME_REG(v) (((v) & (BIT(3) | BIT(1))) == 0x8)
tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h
168
#define SPE_OP_PKG_SVE_EVL(v) (32 << (((v) & GENMASK_ULL(6, 4)) >> 4))
tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h
172
#define SPE_OP_PKT_LDST_SUBCLASS_GCS(v) (((v) & (GENMASK_ULL(7, 3) | BIT(1))) == 0x40)
tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h
177
#define SPE_OP_PKT_CR_BL(v) (FIELD_GET(SPE_OP_PKT_CR_MASK, (v)) == 1)
tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h
178
#define SPE_OP_PKT_CR_RET(v) (FIELD_GET(SPE_OP_PKT_CR_MASK, (v)) == 2)
tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h
179
#define SPE_OP_PKT_CR_NON_BL_RET(v) (FIELD_GET(SPE_OP_PKT_CR_MASK, (v)) == 3)
tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h
73
#define SPE_ADDR_PKT_ADDR_GET_BYTES_0_6(v) ((v) & GENMASK_ULL(55, 0))
tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h
74
#define SPE_ADDR_PKT_ADDR_GET_BYTE_6(v) (((v) & GENMASK_ULL(55, 48)) >> 48)
tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h
76
#define SPE_ADDR_PKT_GET_NS(v) (((v) & BIT_ULL(63)) >> 63)
tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h
77
#define SPE_ADDR_PKT_GET_EL(v) (((v) & GENMASK_ULL(62, 61)) >> 61)
tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h
78
#define SPE_ADDR_PKT_GET_CH(v) (((v) & BIT_ULL(62)) >> 62)
tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h
79
#define SPE_ADDR_PKT_GET_PAT(v) (((v) & GENMASK_ULL(59, 56)) >> 56)
tools/perf/util/blake2s.c
106
ctx->h[i] ^= v[i] ^ v[i + 8];
tools/perf/util/blake2s.c
13
static inline u32 ror32(u32 v, int n)
tools/perf/util/blake2s.c
15
return (v >> n) | (v << (32 - n));
tools/perf/util/blake2s.c
53
u32 v[16];
tools/perf/util/blake2s.c
60
memcpy(v, ctx->h, 32);
tools/perf/util/blake2s.c
61
v[ 8] = BLAKE2S_IV0;
tools/perf/util/blake2s.c
62
v[ 9] = BLAKE2S_IV1;
tools/perf/util/blake2s.c
63
v[10] = BLAKE2S_IV2;
tools/perf/util/blake2s.c
64
v[11] = BLAKE2S_IV3;
tools/perf/util/blake2s.c
65
v[12] = BLAKE2S_IV4 ^ ctx->t[0];
tools/perf/util/blake2s.c
66
v[13] = BLAKE2S_IV5 ^ ctx->t[1];
tools/perf/util/blake2s.c
67
v[14] = BLAKE2S_IV6 ^ ctx->f[0];
tools/perf/util/blake2s.c
68
v[15] = BLAKE2S_IV7 ^ ctx->f[1];
tools/perf/util/blake2s.c
82
G(r, 0, v[0], v[ 4], v[ 8], v[12]); \
tools/perf/util/blake2s.c
83
G(r, 1, v[1], v[ 5], v[ 9], v[13]); \
tools/perf/util/blake2s.c
84
G(r, 2, v[2], v[ 6], v[10], v[14]); \
tools/perf/util/blake2s.c
85
G(r, 3, v[3], v[ 7], v[11], v[15]); \
tools/perf/util/blake2s.c
86
G(r, 4, v[0], v[ 5], v[10], v[15]); \
tools/perf/util/blake2s.c
87
G(r, 5, v[1], v[ 6], v[11], v[12]); \
tools/perf/util/blake2s.c
88
G(r, 6, v[2], v[ 7], v[ 8], v[13]); \
tools/perf/util/blake2s.c
89
G(r, 7, v[3], v[ 4], v[ 9], v[14]); \
tools/perf/util/callchain.c
1397
u64 cycles, v = 0;
tools/perf/util/callchain.c
1407
v = iter_count / from_count;
tools/perf/util/callchain.c
1408
if (v) {
tools/perf/util/callchain.c
1410
v, bf + printed, bfsize - printed);
tools/perf/util/config.c
558
const char *v = getenv(k);
tools/perf/util/config.c
559
return v ? perf_config_bool(k, v) : def;
tools/perf/util/evsel.c
1996
struct sample_read_value *v;
tools/perf/util/evsel.c
2010
v = (void *)data;
tools/perf/util/evsel.c
2011
sample_read_group__for_each(v, nr, read_format) {
tools/perf/util/evsel.c
2014
counter = evlist__id2evsel(leader->evlist, v->id);
tools/perf/util/evsel.c
2019
lost = v->lost;
tools/perf/util/evsel.c
2021
evsel__set_count(counter, cpu_map_idx, thread, v->value, ena, run, lost);
tools/perf/util/header.c
1279
#define _W(v) \
tools/perf/util/header.c
1280
ret = do_write(ff, &c->v, sizeof(u32)); \
tools/perf/util/header.c
1290
#define _W(v) \
tools/perf/util/header.c
1291
ret = do_write_string(ff, (const char *) c->v); \
tools/perf/util/header.c
1497
#define _W(v) \
tools/perf/util/header.c
1498
ret = do_write(ff, &n->v, sizeof(n->v)); \
tools/perf/util/header.c
3123
#define _R(v) \
tools/perf/util/header.c
3124
if (do_read_u32(ff, &c->v)) \
tools/perf/util/header.c
3133
#define _R(v) \
tools/perf/util/header.c
3134
c->v = do_read_string(ff); \
tools/perf/util/header.c
3135
if (!c->v) \
tools/perf/util/header.c
3205
#define _R(v) \
tools/perf/util/header.c
3206
if (do_read_u64(ff, &n.v)) \
tools/perf/util/intel-pt.c
324
struct intel_pt_vmcs_info *v;
tools/perf/util/intel-pt.c
328
v = rb_entry(parent, struct intel_pt_vmcs_info, rb_node);
tools/perf/util/intel-pt.c
330
if (v->vmcs == vmcs)
tools/perf/util/intel-pt.c
331
return v;
tools/perf/util/intel-pt.c
333
if (vmcs < v->vmcs)
tools/perf/util/intel-pt.c
339
v = zalloc(sizeof(*v));
tools/perf/util/intel-pt.c
340
if (v) {
tools/perf/util/intel-pt.c
341
v->vmcs = vmcs;
tools/perf/util/intel-pt.c
342
v->tsc_offset = dflt_tsc_offset;
tools/perf/util/intel-pt.c
343
v->reliable = dflt_tsc_offset;
tools/perf/util/intel-pt.c
345
rb_link_node(&v->rb_node, parent, p);
tools/perf/util/intel-pt.c
346
rb_insert_color(&v->rb_node, rb_root);
tools/perf/util/intel-pt.c
349
return v;
tools/perf/util/intel-pt.c
365
struct intel_pt_vmcs_info *v;
tools/perf/util/intel-pt.c
370
v = rb_entry(n, struct intel_pt_vmcs_info, rb_node);
tools/perf/util/intel-pt.c
372
rb_erase(&v->rb_node, &pt->vmcs_info);
tools/perf/util/intel-pt.c
373
free(v);
tools/perf/util/parse-sublevel-options.c
14
int v = 1;
tools/perf/util/parse-sublevel-options.c
38
v = atoi(vstr);
tools/perf/util/parse-sublevel-options.c
40
*opt->value_ptr = v;
tools/perf/util/pmu.c
1404
void perf_pmu__format_pack(unsigned long *format, __u64 value, __u64 *v,
tools/perf/util/pmu.c
1415
*v |= (1llu << fbit);
tools/perf/util/pmu.c
1417
*v &= ~(1llu << fbit);
tools/perf/util/pmu.h
282
void perf_pmu__format_pack(unsigned long *format, __u64 value, __u64 *v,
tools/perf/util/sample.h
57
static inline struct sample_read_value *next_sample_read_value(struct sample_read_value *v, u64 read_format)
tools/perf/util/sample.h
59
return (void *)v + sample_read_value_size(read_format);
tools/perf/util/sample.h
62
#define sample_read_group__for_each(v, nr, rf) \
tools/perf/util/sample.h
63
for (int __i = 0; __i < (int)nr; v = next_sample_read_value(v, rf), __i++)
tools/perf/util/scripting-engines/trace-event-python.c
681
struct sample_read_value *v = sample->read.group.values;
tools/perf/util/scripting-engines/trace-event-python.c
684
sample_read_group__for_each(v, sample->read.group.nr, read_format) {
tools/perf/util/scripting-engines/trace-event-python.c
685
PyObject *t = get_sample_value_as_tuple(v, read_format);
tools/perf/util/session.c
1255
struct sample_read_value *v,
tools/perf/util/session.c
1259
struct perf_sample_id *sid = evlist__id2sid(evlist, v->id);
tools/perf/util/session.c
1268
sample->id = v->id;
tools/perf/util/session.c
1269
sample->period = v->value - *storage;
tools/perf/util/session.c
1270
*storage = v->value;
tools/perf/util/session.c
1298
struct sample_read_value *v = sample->read.group.values;
tools/perf/util/session.c
1301
return deliver_sample_value(evlist, tool, event, sample, v, machine,
tools/perf/util/session.c
1304
sample_read_group__for_each(v, sample->read.group.nr, read_format) {
tools/perf/util/session.c
1305
ret = deliver_sample_value(evlist, tool, event, sample, v,
tools/perf/util/synthetic-events.c
1597
struct sample_read_value *v = sample->read.group.values;
tools/perf/util/synthetic-events.c
1599
sample_read_group__for_each(v, sample->read.group.nr, read_format) {
tools/perf/util/synthetic-events.c
1601
memcpy(array, v, sz);
tools/perf/util/units.c
60
double v = convert_unit_double((double)value, unit);
tools/perf/util/units.c
62
return (unsigned long)v;
tools/perf/util/util.c
361
size_t hex_width(u64 v)
tools/perf/util/util.c
365
while ((v >>= 4))
tools/perf/util/util.h
102
(const void *)(v)) : \
tools/perf/util/util.h
44
size_t hex_width(u64 v);
tools/perf/util/util.h
95
#define realloc_array_as_needed(a, n, x, v) ({ \
tools/power/cpupower/utils/helpers/bitmask.c
71
static void _setbit(struct bitmask *bmp, unsigned int n, unsigned int v)
tools/power/cpupower/utils/helpers/bitmask.c
74
if (v)
tools/power/x86/turbostat/turbostat.c
4662
unsigned int v;
tools/power/x86/turbostat/turbostat.c
4665
status = read_perf_counter_info(path, parse_format, &v);
tools/power/x86/turbostat/turbostat.c
4667
v = -1;
tools/power/x86/turbostat/turbostat.c
4669
return v;
tools/power/x86/turbostat/turbostat.c
6758
static void msr_record_handler(union sigval v)
tools/power/x86/turbostat/turbostat.c
6760
UNUSED(v);
tools/sched_ext/include/scx/common.bpf.h
699
static inline u32 log2_u32(u32 v)
tools/sched_ext/include/scx/common.bpf.h
704
r = (v > 0xFFFF) << 4; v >>= r;
tools/sched_ext/include/scx/common.bpf.h
705
shift = (v > 0xFF) << 3; v >>= shift; r |= shift;
tools/sched_ext/include/scx/common.bpf.h
706
shift = (v > 0xF) << 2; v >>= shift; r |= shift;
tools/sched_ext/include/scx/common.bpf.h
707
shift = (v > 0x3) << 1; v >>= shift; r |= shift;
tools/sched_ext/include/scx/common.bpf.h
708
r |= (v >> 1);
tools/sched_ext/include/scx/common.bpf.h
716
static inline u32 log2_u64(u64 v)
tools/sched_ext/include/scx/common.bpf.h
718
u32 hi = v >> 32;
tools/sched_ext/include/scx/common.bpf.h
722
return log2_u32(v) + 1;
tools/sched_ext/include/scx/compat.h
25
static inline bool __COMPAT_read_enum(const char *type, const char *name, u64 *v)
tools/sched_ext/include/scx/compat.h
48
*v = e[i].val;
tools/sched_ext/include/scx/compat.h
59
*v = btf_enum64_value(&e[i]);
tools/sched_ext/scx_flatcg.c
152
double v;
tools/sched_ext/scx_flatcg.c
156
v = strtod(optarg, NULL);
tools/sched_ext/scx_flatcg.c
157
skel->rodata->cgrp_slice_ns = v * 1000;
tools/sched_ext/scx_flatcg.c
160
v = strtod(optarg, NULL);
tools/sched_ext/scx_flatcg.c
161
intv_ts.tv_sec = v;
tools/sched_ext/scx_flatcg.c
162
intv_ts.tv_nsec = (v - (float)intv_ts.tv_sec) * 1000000000;
tools/sched_ext/scx_flatcg.c
78
__u64 v;
tools/sched_ext/scx_flatcg.c
84
v = strtoull(tok, &endp, 0);
tools/sched_ext/scx_flatcg.c
90
sum += v;
tools/sched_ext/scx_flatcg.c
92
idle = v;
tools/testing/memblock/mmzone.c
18
void atomic_long_set(atomic_long_t *v, long i)
tools/testing/selftests/alsa/conf.c
196
const char *path_string, *regex_string, *v;
tools/testing/selftests/alsa/conf.c
212
v = sysfs_get(sysfs_root, path_string);
tools/testing/selftests/alsa/conf.c
213
if (!v)
tools/testing/selftests/alsa/conf.c
217
ret = regexec(&re, v, 1, match, 0);
tools/testing/selftests/alsa/pcm-test.c
85
long v;
tools/testing/selftests/alsa/pcm-test.c
90
v = strtol(id, &end, 10);
tools/testing/selftests/alsa/pcm-test.c
93
return v;
tools/testing/selftests/arm64/fp/fp-ptrace.c
889
static void fpsimd_to_sve(__uint128_t *v, char *z, int vl)
tools/testing/selftests/arm64/fp/fp-ptrace.c
900
*p = arm64_cpu_to_le128(v[i]);
tools/testing/selftests/bpf/benchs/bench_lpm_trie_map.c
209
__u32 *v = &vals[i];
tools/testing/selftests/bpf/benchs/bench_lpm_trie_map.c
213
*v = 1;
tools/testing/selftests/bpf/bpf_util.h
65
struct { type v; /* padding */ } __bpf_percpu_val_align \
tools/testing/selftests/bpf/bpf_util.h
67
#define bpf_percpu(name, cpu) name[(cpu)].v
tools/testing/selftests/bpf/btf_helpers.c
142
const struct btf_enum *v = btf_enum(t);
tools/testing/selftests/bpf/btf_helpers.c
148
for (i = 0; i < vlen; i++, v++) {
tools/testing/selftests/bpf/btf_helpers.c
150
btf_str(btf, v->name_off), v->val);
tools/testing/selftests/bpf/btf_helpers.c
155
const struct btf_enum64 *v = btf_enum64(t);
tools/testing/selftests/bpf/btf_helpers.c
162
for (i = 0; i < vlen; i++, v++) {
tools/testing/selftests/bpf/btf_helpers.c
164
btf_str(btf, v->name_off),
tools/testing/selftests/bpf/btf_helpers.c
165
((__u64)v->val_hi32 << 32) | v->val_lo32);
tools/testing/selftests/bpf/btf_helpers.c
190
const struct btf_var_secinfo *v = btf_var_secinfos(t);
tools/testing/selftests/bpf/btf_helpers.c
193
for (i = 0; i < vlen; i++, v++) {
tools/testing/selftests/bpf/btf_helpers.c
195
v->type, v->offset, v->size);
tools/testing/selftests/bpf/map_tests/htab_map_batch_ops.c
18
value *v = NULL;
tools/testing/selftests/bpf/map_tests/htab_map_batch_ops.c
26
v = (value *)values;
tools/testing/selftests/bpf/map_tests/htab_map_batch_ops.c
32
bpf_percpu(v[i], j) = i + 2 + j;
tools/testing/selftests/bpf/map_tests/htab_map_batch_ops.c
45
value *v = NULL;
tools/testing/selftests/bpf/map_tests/htab_map_batch_ops.c
49
v = (value *)values;
tools/testing/selftests/bpf/map_tests/htab_map_batch_ops.c
56
CHECK(keys[i] + 1 + j != bpf_percpu(v[i], j),
tools/testing/selftests/bpf/map_tests/htab_map_batch_ops.c
59
i, j, keys[i], bpf_percpu(v[i], j));
tools/testing/selftests/bpf/prog_tests/btf.c
5351
struct pprint_mapv *v = mapv;
tools/testing/selftests/bpf/prog_tests/btf.c
5354
v->ui32 = i + cpu;
tools/testing/selftests/bpf/prog_tests/btf.c
5355
v->si32 = -i;
tools/testing/selftests/bpf/prog_tests/btf.c
5356
v->unused_bits2a = 3;
tools/testing/selftests/bpf/prog_tests/btf.c
5357
v->bits28 = i;
tools/testing/selftests/bpf/prog_tests/btf.c
5358
v->unused_bits2b = 3;
tools/testing/selftests/bpf/prog_tests/btf.c
5359
v->ui64 = i;
tools/testing/selftests/bpf/prog_tests/btf.c
5360
v->aenum = i & 0x03;
tools/testing/selftests/bpf/prog_tests/btf.c
5361
v->ui32b = 4;
tools/testing/selftests/bpf/prog_tests/btf.c
5362
v->bits2c = 1;
tools/testing/selftests/bpf/prog_tests/btf.c
5363
v->si8_4[0][0] = (cpu + i) & 0xff;
tools/testing/selftests/bpf/prog_tests/btf.c
5364
v->si8_4[0][1] = (cpu + i + 1) & 0xff;
tools/testing/selftests/bpf/prog_tests/btf.c
5365
v->si8_4[1][0] = (cpu + i + 2) & 0xff;
tools/testing/selftests/bpf/prog_tests/btf.c
5366
v->si8_4[1][1] = (cpu + i + 3) & 0xff;
tools/testing/selftests/bpf/prog_tests/btf.c
5367
v = (void *)v + rounded_value_size;
tools/testing/selftests/bpf/prog_tests/btf.c
5373
struct pprint_mapv_int128 *v = mapv;
tools/testing/selftests/bpf/prog_tests/btf.c
5376
v->si128a = i;
tools/testing/selftests/bpf/prog_tests/btf.c
5377
v->si128b = -i;
tools/testing/selftests/bpf/prog_tests/btf.c
5378
v->bits3 = i & 0x07;
tools/testing/selftests/bpf/prog_tests/btf.c
5379
v->bits80 = (((unsigned __int128)1) << 64) + i;
tools/testing/selftests/bpf/prog_tests/btf.c
5380
v->ui128 = (((unsigned __int128)2) << 64) + i;
tools/testing/selftests/bpf/prog_tests/btf.c
5381
v = (void *)v + rounded_value_size;
tools/testing/selftests/bpf/prog_tests/btf.c
5395
struct pprint_mapv *v = mapv;
tools/testing/selftests/bpf/prog_tests/btf.c
5403
v->ui32, v->si32,
tools/testing/selftests/bpf/prog_tests/btf.c
5404
v->unused_bits2a,
tools/testing/selftests/bpf/prog_tests/btf.c
5405
v->bits28,
tools/testing/selftests/bpf/prog_tests/btf.c
5406
v->unused_bits2b,
tools/testing/selftests/bpf/prog_tests/btf.c
5407
(__u64)v->ui64,
tools/testing/selftests/bpf/prog_tests/btf.c
5408
v->ui8a[0], v->ui8a[1],
tools/testing/selftests/bpf/prog_tests/btf.c
5409
v->ui8a[2], v->ui8a[3],
tools/testing/selftests/bpf/prog_tests/btf.c
5410
v->ui8a[4], v->ui8a[5],
tools/testing/selftests/bpf/prog_tests/btf.c
5411
v->ui8a[6], v->ui8a[7],
tools/testing/selftests/bpf/prog_tests/btf.c
5412
pprint_enum_str[v->aenum],
tools/testing/selftests/bpf/prog_tests/btf.c
5413
v->ui32b,
tools/testing/selftests/bpf/prog_tests/btf.c
5414
v->bits2c,
tools/testing/selftests/bpf/prog_tests/btf.c
5415
v->si8_4[0][0], v->si8_4[0][1],
tools/testing/selftests/bpf/prog_tests/btf.c
5416
v->si8_4[1][0], v->si8_4[1][1]);
tools/testing/selftests/bpf/prog_tests/btf.c
5421
struct pprint_mapv_int128 *v = mapv;
tools/testing/selftests/bpf/prog_tests/btf.c
5428
(uint64_t)v->si128a,
tools/testing/selftests/bpf/prog_tests/btf.c
5429
(uint64_t)v->si128b,
tools/testing/selftests/bpf/prog_tests/btf.c
5430
(uint64_t)v->bits3,
tools/testing/selftests/bpf/prog_tests/btf.c
5431
(uint64_t)(v->bits80 >> 64),
tools/testing/selftests/bpf/prog_tests/btf.c
5432
(uint64_t)v->bits80,
tools/testing/selftests/bpf/prog_tests/btf.c
5433
(uint64_t)(v->ui128 >> 64),
tools/testing/selftests/bpf/prog_tests/btf.c
5434
(uint64_t)v->ui128);
tools/testing/selftests/bpf/prog_tests/btf_write.c
13
const struct btf_enum *v;
tools/testing/selftests/bpf/prog_tests/btf_write.c
168
v = btf_enum(t) + 0;
tools/testing/selftests/bpf/prog_tests/btf_write.c
169
ASSERT_STREQ(btf__str_by_offset(btf, v->name_off), "v1", "v1_name");
tools/testing/selftests/bpf/prog_tests/btf_write.c
170
ASSERT_EQ(v->val, 1, "v1_val");
tools/testing/selftests/bpf/prog_tests/btf_write.c
171
v = btf_enum(t) + 1;
tools/testing/selftests/bpf/prog_tests/btf_write.c
172
ASSERT_STREQ(btf__str_by_offset(btf, v->name_off), "v2", "v2_name");
tools/testing/selftests/bpf/prog_tests/btf_write.c
173
ASSERT_EQ(v->val, 2, "v2_val");
tools/testing/selftests/bpf/prog_tests/fs_kfuncs.c
20
int v[32];
tools/testing/selftests/bpf/prog_tests/fs_kfuncs.c
57
err = getxattr(testfile, name, v, sizeof(v));
tools/testing/selftests/bpf/prog_tests/hashmap.c
107
long oldv, v = 256 + i;
tools/testing/selftests/bpf/prog_tests/hashmap.c
109
err = hashmap__add(map, k, v);
tools/testing/selftests/bpf/prog_tests/hashmap.c
115
err = hashmap__update(map, k, v, &oldk, &oldv);
tools/testing/selftests/bpf/prog_tests/hashmap.c
117
err = hashmap__set(map, k, v, &oldk, &oldv);
tools/testing/selftests/bpf/prog_tests/hashmap.c
121
k, v, err))
tools/testing/selftests/bpf/prog_tests/hashmap.c
126
if (CHECK(oldv != v, "elem_val",
tools/testing/selftests/bpf/prog_tests/hashmap.c
142
long v = entry->value;
tools/testing/selftests/bpf/prog_tests/hashmap.c
145
if (CHECK(v - k != 256, "elem_check",
tools/testing/selftests/bpf/prog_tests/hashmap.c
146
"invalid updated k/v pair: %ld = %ld\n", k, v))
tools/testing/selftests/bpf/prog_tests/hashmap.c
165
long oldv, v;
tools/testing/selftests/bpf/prog_tests/hashmap.c
168
v = entry->value;
tools/testing/selftests/bpf/prog_tests/hashmap.c
174
"failed to delete k/v %ld = %ld\n", k, v))
tools/testing/selftests/bpf/prog_tests/hashmap.c
176
if (CHECK(oldk != k || oldv != v, "check_old",
tools/testing/selftests/bpf/prog_tests/hashmap.c
178
k, v, oldk, oldv))
tools/testing/selftests/bpf/prog_tests/hashmap.c
199
long oldv, v;
tools/testing/selftests/bpf/prog_tests/hashmap.c
202
v = entry->value;
tools/testing/selftests/bpf/prog_tests/hashmap.c
208
"failed to delete k/v %ld = %ld\n", k, v))
tools/testing/selftests/bpf/prog_tests/hashmap.c
210
if (CHECK(oldk != k || oldv != v, "elem_check",
tools/testing/selftests/bpf/prog_tests/hashmap.c
212
k, v, oldk, oldv))
tools/testing/selftests/bpf/prog_tests/hashmap.c
215
"unexpectedly deleted k/v %ld = %ld\n", k, v))
tools/testing/selftests/bpf/prog_tests/hashmap.c
57
long oldv, v = 1024 + i;
tools/testing/selftests/bpf/prog_tests/hashmap.c
59
err = hashmap__update(map, k, v, &oldk, &oldv);
tools/testing/selftests/bpf/prog_tests/hashmap.c
65
err = hashmap__add(map, k, v);
tools/testing/selftests/bpf/prog_tests/hashmap.c
67
err = hashmap__set(map, k, v, &oldk, &oldv);
tools/testing/selftests/bpf/prog_tests/hashmap.c
73
if (CHECK(err, "elem_add", "failed to add k/v %ld = %ld: %d\n", k, v, err))
tools/testing/selftests/bpf/prog_tests/hashmap.c
79
if (CHECK(oldv != v, "elem_val", "found value is wrong: %ld\n", oldv))
tools/testing/selftests/bpf/prog_tests/hashmap.c
94
long v = entry->value;
tools/testing/selftests/bpf/prog_tests/hashmap.c
97
if (CHECK(v - k != 1024, "check_kv",
tools/testing/selftests/bpf/prog_tests/hashmap.c
98
"invalid k/v pair: %ld = %ld\n", k, v))
tools/testing/selftests/bpf/prog_tests/map_init.c
16
map_value_t v; /* padding */
tools/testing/selftests/bpf/prog_tests/percpu_alloc.c
128
u32 count, v;
tools/testing/selftests/bpf/prog_tests/percpu_alloc.c
285
v = *(u32 *) (values_row + roundup(value_sz, 8) * j);
tools/testing/selftests/bpf/prog_tests/percpu_alloc.c
286
if (!ASSERT_EQ(v, j != cpu ? 0 : value,
tools/testing/selftests/bpf/prog_tests/select_reuseport.c
171
static int write_int_sysctl(const char *sysctl, int v)
tools/testing/selftests/bpf/prog_tests/select_reuseport.c
180
size = snprintf(buf, sizeof(buf), "%d", v);
tools/testing/selftests/bpf/prog_tests/send_signal.c
15
static void sigusr1_siginfo_handler(int s, siginfo_t *i, void *v)
tools/testing/selftests/bpf/prog_tests/sockmap_helpers.h
8
#define u32(v) ((u32){(v)})
tools/testing/selftests/bpf/prog_tests/sockmap_helpers.h
9
#define u64(v) ((u64){(v)})
tools/testing/selftests/bpf/progs/bpf_cubic.c
217
static const __u8 v[] = {
tools/testing/selftests/bpf/progs/bpf_cubic.c
238
return ((__u32)v[(__u32)a] + 35) >> 6;
tools/testing/selftests/bpf/progs/bpf_cubic.c
249
x = ((__u32)(((__u32)v[shift] + 10) << b)) >> 6;
tools/testing/selftests/bpf/progs/btf_dump_test_case_syntax.c
246
struct_in_array_t *v;
tools/testing/selftests/bpf/progs/cb_refs.c
53
struct map_value *v;
tools/testing/selftests/bpf/progs/cb_refs.c
55
v = bpf_map_lookup_elem(&array_map, &(int){0});
tools/testing/selftests/bpf/progs/cb_refs.c
56
if (!v)
tools/testing/selftests/bpf/progs/cb_refs.c
61
p = bpf_kptr_xchg(&v->ptr, p);
tools/testing/selftests/bpf/progs/cgrp_kfunc_common.h
44
struct __cgrps_kfunc_map_value local, *v;
tools/testing/selftests/bpf/progs/cgrp_kfunc_common.h
58
v = bpf_map_lookup_elem(&__cgrps_kfunc_map, &id);
tools/testing/selftests/bpf/progs/cgrp_kfunc_common.h
59
if (!v) {
tools/testing/selftests/bpf/progs/cgrp_kfunc_common.h
70
old = bpf_kptr_xchg(&v->cgrp, acquired);
tools/testing/selftests/bpf/progs/cgrp_kfunc_failure.c
141
struct __cgrps_kfunc_map_value *v;
tools/testing/selftests/bpf/progs/cgrp_kfunc_failure.c
143
v = insert_lookup_cgrp(cgrp);
tools/testing/selftests/bpf/progs/cgrp_kfunc_failure.c
144
if (!v)
tools/testing/selftests/bpf/progs/cgrp_kfunc_failure.c
147
kptr = bpf_kptr_xchg(&v->cgrp, NULL);
tools/testing/selftests/bpf/progs/cgrp_kfunc_failure.c
161
struct __cgrps_kfunc_map_value *v;
tools/testing/selftests/bpf/progs/cgrp_kfunc_failure.c
163
v = insert_lookup_cgrp(cgrp);
tools/testing/selftests/bpf/progs/cgrp_kfunc_failure.c
164
if (!v)
tools/testing/selftests/bpf/progs/cgrp_kfunc_failure.c
168
kptr = v->cgrp;
tools/testing/selftests/bpf/progs/cgrp_kfunc_failure.c
181
struct __cgrps_kfunc_map_value *v;
tools/testing/selftests/bpf/progs/cgrp_kfunc_failure.c
183
v = insert_lookup_cgrp(cgrp);
tools/testing/selftests/bpf/progs/cgrp_kfunc_failure.c
184
if (!v)
tools/testing/selftests/bpf/progs/cgrp_kfunc_failure.c
188
bpf_cgroup_release(v->cgrp);
tools/testing/selftests/bpf/progs/cgrp_kfunc_failure.c
209
struct __cgrps_kfunc_map_value local, *v;
tools/testing/selftests/bpf/progs/cgrp_kfunc_failure.c
223
v = bpf_map_lookup_elem(&__cgrps_kfunc_map, &id);
tools/testing/selftests/bpf/progs/cgrp_kfunc_failure.c
224
if (!v)
tools/testing/selftests/bpf/progs/cgrp_kfunc_failure.c
231
old = bpf_kptr_xchg(&v->cgrp, acquired);
tools/testing/selftests/bpf/progs/cgrp_kfunc_failure.c
36
struct __cgrps_kfunc_map_value *v;
tools/testing/selftests/bpf/progs/cgrp_kfunc_failure.c
38
v = insert_lookup_cgrp(cgrp);
tools/testing/selftests/bpf/progs/cgrp_kfunc_failure.c
39
if (!v)
tools/testing/selftests/bpf/progs/cgrp_kfunc_failure.c
43
acquired = bpf_cgroup_acquire(v->cgrp);
tools/testing/selftests/bpf/progs/cgrp_kfunc_success.c
111
struct __cgrps_kfunc_map_value *v;
tools/testing/selftests/bpf/progs/cgrp_kfunc_success.c
123
v = cgrps_kfunc_map_value_lookup(cgrp);
tools/testing/selftests/bpf/progs/cgrp_kfunc_success.c
124
if (!v) {
tools/testing/selftests/bpf/progs/cgrp_kfunc_success.c
130
kptr = v->cgrp;
tools/testing/selftests/bpf/progs/cgrp_kfunc_success.c
68
struct __cgrps_kfunc_map_value *v;
tools/testing/selftests/bpf/progs/cgrp_kfunc_success.c
80
v = cgrps_kfunc_map_value_lookup(cgrp);
tools/testing/selftests/bpf/progs/cgrp_kfunc_success.c
81
if (!v) {
tools/testing/selftests/bpf/progs/cgrp_kfunc_success.c
86
kptr = v->cgrp;
tools/testing/selftests/bpf/progs/cgrp_kfunc_success.c
96
kptr = bpf_kptr_xchg(&v->cgrp, NULL);
tools/testing/selftests/bpf/progs/core_kern.c
26
static __noinline int randmap(int v, const struct net_device *dev)
tools/testing/selftests/bpf/progs/core_kern.c
37
*val = bpf_get_prandom_u32() + v + dev->mtu;
tools/testing/selftests/bpf/progs/cpumask_common.h
102
struct __cpumask_map_value local, *v;
tools/testing/selftests/bpf/progs/cpumask_common.h
114
v = bpf_map_lookup_elem(&__cpumask_map, &key);
tools/testing/selftests/bpf/progs/cpumask_common.h
115
if (!v) {
tools/testing/selftests/bpf/progs/cpumask_common.h
120
old = bpf_kptr_xchg(&v->cpumask, mask);
tools/testing/selftests/bpf/progs/cpumask_failure.c
100
if (!v)
tools/testing/selftests/bpf/progs/cpumask_failure.c
103
cpumask = bpf_kptr_xchg(&v->cpumask, NULL);
tools/testing/selftests/bpf/progs/cpumask_failure.c
90
struct __cpumask_map_value *v;
tools/testing/selftests/bpf/progs/cpumask_failure.c
99
v = cpumask_map_value_lookup();
tools/testing/selftests/bpf/progs/cpumask_success.c
477
struct __cpumask_map_value *v;
tools/testing/selftests/bpf/progs/cpumask_success.c
488
v = cpumask_map_value_lookup();
tools/testing/selftests/bpf/progs/cpumask_success.c
489
if (!v) {
tools/testing/selftests/bpf/progs/cpumask_success.c
494
cpumask = bpf_kptr_xchg(&v->cpumask, NULL);
tools/testing/selftests/bpf/progs/crypto_bench.c
58
struct __crypto_ctx_value *v;
tools/testing/selftests/bpf/progs/crypto_bench.c
62
v = crypto_ctx_value_lookup();
tools/testing/selftests/bpf/progs/crypto_bench.c
63
if (!v) {
tools/testing/selftests/bpf/progs/crypto_bench.c
68
ctx = v->ctx;
tools/testing/selftests/bpf/progs/crypto_bench.c
87
struct __crypto_ctx_value *v;
tools/testing/selftests/bpf/progs/crypto_bench.c
90
v = crypto_ctx_value_lookup();
tools/testing/selftests/bpf/progs/crypto_bench.c
91
if (!v)
tools/testing/selftests/bpf/progs/crypto_bench.c
94
ctx = v->ctx;
tools/testing/selftests/bpf/progs/crypto_common.h
39
struct __crypto_ctx_value local, *v;
tools/testing/selftests/bpf/progs/crypto_common.h
51
v = bpf_map_lookup_elem(&__crypto_ctx_map, &key);
tools/testing/selftests/bpf/progs/crypto_common.h
52
if (!v) {
tools/testing/selftests/bpf/progs/crypto_common.h
57
old = bpf_kptr_xchg(&v->ctx, ctx);
tools/testing/selftests/bpf/progs/crypto_sanity.c
100
v = crypto_ctx_value_lookup();
tools/testing/selftests/bpf/progs/crypto_sanity.c
101
if (!v) {
tools/testing/selftests/bpf/progs/crypto_sanity.c
106
ctx = v->ctx;
tools/testing/selftests/bpf/progs/crypto_sanity.c
135
struct __crypto_ctx_value *v;
tools/testing/selftests/bpf/progs/crypto_sanity.c
147
v = crypto_ctx_value_lookup();
tools/testing/selftests/bpf/progs/crypto_sanity.c
148
if (!v) {
tools/testing/selftests/bpf/progs/crypto_sanity.c
153
ctx = v->ctx;
tools/testing/selftests/bpf/progs/crypto_sanity.c
88
struct __crypto_ctx_value *v;
tools/testing/selftests/bpf/progs/for_each_hash_map_elem.c
34
__u64 v;
tools/testing/selftests/bpf/progs/for_each_hash_map_elem.c
38
v = *val;
tools/testing/selftests/bpf/progs/for_each_hash_map_elem.c
39
if (skb->len == 10000 && k == 10 && v == 10)
tools/testing/selftests/bpf/progs/iters.c
101
while ((v = bpf_iter_num_next(&it))) {
tools/testing/selftests/bpf/progs/iters.c
102
bpf_printk("ITER_BASIC: E1 VAL: v=%d", *v);
tools/testing/selftests/bpf/progs/iters.c
114
int *v;
tools/testing/selftests/bpf/progs/iters.c
119
while ((v = bpf_iter_num_next(&it))) {
tools/testing/selftests/bpf/progs/iters.c
120
bpf_printk("ITER_BASIC: E1 VAL: v=%d", *v);
tools/testing/selftests/bpf/progs/iters.c
132
int *v;
tools/testing/selftests/bpf/progs/iters.c
137
for (v = bpf_iter_num_next(&it); v; v = bpf_iter_num_next(&it)) {
tools/testing/selftests/bpf/progs/iters.c
138
bpf_printk("ITER_BASIC: E2 VAL: v=%d", *v);
tools/testing/selftests/bpf/progs/iters.c
149
int *v;
tools/testing/selftests/bpf/progs/iters.c
153
bpf_for_each(num, v, 5, 10) {
tools/testing/selftests/bpf/progs/iters.c
154
bpf_printk("ITER_BASIC: E2 VAL: v=%d", *v);
tools/testing/selftests/bpf/progs/iters.c
180
int *v, i;
tools/testing/selftests/bpf/progs/iters.c
187
v = bpf_iter_num_next(&it);
tools/testing/selftests/bpf/progs/iters.c
188
bpf_printk("ITER_BASIC: E3 VAL: i=%d v=%d", i, v ? *v : -1);
tools/testing/selftests/bpf/progs/iters.c
200
int *v;
tools/testing/selftests/bpf/progs/iters.c
205
v = bpf_iter_num_next(&it);
tools/testing/selftests/bpf/progs/iters.c
206
bpf_printk("ITER_BASIC: E4 VAL: v=%d", v ? *v : -1);
tools/testing/selftests/bpf/progs/iters.c
207
v = bpf_iter_num_next(&it);
tools/testing/selftests/bpf/progs/iters.c
208
bpf_printk("ITER_BASIC: E4 VAL: v=%d", v ? *v : -1);
tools/testing/selftests/bpf/progs/iters.c
209
v = bpf_iter_num_next(&it);
tools/testing/selftests/bpf/progs/iters.c
210
bpf_printk("ITER_BASIC: E4 VAL: v=%d", v ? *v : -1);
tools/testing/selftests/bpf/progs/iters.c
211
v = bpf_iter_num_next(&it);
tools/testing/selftests/bpf/progs/iters.c
212
bpf_printk("ITER_BASIC: E4 VAL: v=%d\n", v ? *v : -1);
tools/testing/selftests/bpf/progs/iters.c
223
int *v, i;
tools/testing/selftests/bpf/progs/iters.c
228
while ((v = bpf_iter_num_next(&it))) {
tools/testing/selftests/bpf/progs/iters.c
229
bpf_printk("ITER_BASIC: E1 VAL: v=%d", *v);
tools/testing/selftests/bpf/progs/iters.c
234
for (v = bpf_iter_num_next(&it); v; v = bpf_iter_num_next(&it)) {
tools/testing/selftests/bpf/progs/iters.c
235
bpf_printk("ITER_BASIC: E2 VAL: v=%d", *v);
tools/testing/selftests/bpf/progs/iters.c
242
v = bpf_iter_num_next(&it);
tools/testing/selftests/bpf/progs/iters.c
243
bpf_printk("ITER_BASIC: E3 VAL: i=%d v=%d", i, v ? *v : -1);
tools/testing/selftests/bpf/progs/iters.c
248
v = bpf_iter_num_next(&it);
tools/testing/selftests/bpf/progs/iters.c
249
bpf_printk("ITER_BASIC: E4 VAL: v=%d", v ? *v : -1);
tools/testing/selftests/bpf/progs/iters.c
250
v = bpf_iter_num_next(&it);
tools/testing/selftests/bpf/progs/iters.c
251
bpf_printk("ITER_BASIC: E4 VAL: v=%d", v ? *v : -1);
tools/testing/selftests/bpf/progs/iters.c
252
v = bpf_iter_num_next(&it);
tools/testing/selftests/bpf/progs/iters.c
253
bpf_printk("ITER_BASIC: E4 VAL: v=%d", v ? *v : -1);
tools/testing/selftests/bpf/progs/iters.c
254
v = bpf_iter_num_next(&it);
tools/testing/selftests/bpf/progs/iters.c
255
bpf_printk("ITER_BASIC: E4 VAL: v=%d\n", v ? *v : -1);
tools/testing/selftests/bpf/progs/iters.c
266
int *v, i = 0, sum = 0;
tools/testing/selftests/bpf/progs/iters.c
271
while ((v = bpf_iter_num_next(&it))) {
tools/testing/selftests/bpf/progs/iters.c
272
bpf_printk("ITER_SIMPLE: i=%d v=%d", i, *v);
tools/testing/selftests/bpf/progs/iters.c
273
sum += *v;
tools/testing/selftests/bpf/progs/iters.c
291
int *v, sum = 0;
tools/testing/selftests/bpf/progs/iters.c
300
while ((v = bpf_iter_num_next(&it))) {
tools/testing/selftests/bpf/progs/iters.c
319
bpf_printk("ITER_OBFUSCATE_COUNTER: i=%d v=%d x=%d", i, *v, x);
tools/testing/selftests/bpf/progs/iters.c
335
int *v, *elem = NULL;
tools/testing/selftests/bpf/progs/iters.c
34
int *v, i = zero; /* obscure initial value of i */
tools/testing/selftests/bpf/progs/iters.c
342
while ((v = bpf_iter_num_next(&it))) {
tools/testing/selftests/bpf/progs/iters.c
343
bpf_printk("ITER_SEARCH_LOOP: v=%d", *v);
tools/testing/selftests/bpf/progs/iters.c
345
if (*v == 2) {
tools/testing/selftests/bpf/progs/iters.c
347
elem = v;
tools/testing/selftests/bpf/progs/iters.c
39
while ((v = bpf_iter_num_next(&it))) {
tools/testing/selftests/bpf/progs/iters.c
96
int *v;
tools/testing/selftests/bpf/progs/iters_num.c
185
int cnt = 0, *v;
tools/testing/selftests/bpf/progs/iters_num.c
188
while ((v = bpf_iter_num_next(&it))) {
tools/testing/selftests/bpf/progs/iters_num.c
205
int cnt = 0, *v, i;
tools/testing/selftests/bpf/progs/iters_num.c
209
v = bpf_iter_num_next(&it);
tools/testing/selftests/bpf/progs/iters_num.c
210
if (v)
tools/testing/selftests/bpf/progs/iters_num.c
227
int cnt = 0, *v, i;
tools/testing/selftests/bpf/progs/iters_num.c
231
v = bpf_iter_num_next(&it);
tools/testing/selftests/bpf/progs/iters_num.c
232
if (v)
tools/testing/selftests/bpf/progs/iters_testmod_seq.c
100
while ((v = bpf_iter_testmod_seq_next(&it))) {
tools/testing/selftests/bpf/progs/iters_testmod_seq.c
101
sum += *v;
tools/testing/selftests/bpf/progs/iters_testmod_seq.c
114
s64 sum = 0, *v;
tools/testing/selftests/bpf/progs/iters_testmod_seq.c
118
while ((v = bpf_iter_testmod_seq_next(&it))) {
tools/testing/selftests/bpf/progs/iters_testmod_seq.c
119
sum += *v;
tools/testing/selftests/bpf/progs/iters_testmod_seq.c
96
s64 sum = 0, *v;
tools/testing/selftests/bpf/progs/jit_probe_mem.c
21
p = bpf_kptr_xchg(&v, p);
tools/testing/selftests/bpf/progs/jit_probe_mem.c
26
p = v;
tools/testing/selftests/bpf/progs/jit_probe_mem.c
8
static struct prog_test_ref_kfunc __kptr *v;
tools/testing/selftests/bpf/progs/linked_list.c
296
struct map_value *v;
tools/testing/selftests/bpf/progs/linked_list.c
298
v = bpf_map_lookup_elem(&array_map, &(int){0});
tools/testing/selftests/bpf/progs/linked_list.c
299
if (!v)
tools/testing/selftests/bpf/progs/linked_list.c
301
return test_list_push_pop(&v->lock, &v->head);
tools/testing/selftests/bpf/progs/linked_list.c
307
struct map_value *v;
tools/testing/selftests/bpf/progs/linked_list.c
313
v = bpf_map_lookup_elem(map, &(int){0});
tools/testing/selftests/bpf/progs/linked_list.c
314
if (!v)
tools/testing/selftests/bpf/progs/linked_list.c
316
return test_list_push_pop(&v->lock, &v->head);
tools/testing/selftests/bpf/progs/linked_list.c
354
struct map_value *v;
tools/testing/selftests/bpf/progs/linked_list.c
356
v = bpf_map_lookup_elem(&array_map, &(int){0});
tools/testing/selftests/bpf/progs/linked_list.c
357
if (!v)
tools/testing/selftests/bpf/progs/linked_list.c
359
return test_list_push_pop_multiple(&v->lock, &v->head);
tools/testing/selftests/bpf/progs/linked_list.c
365
struct map_value *v;
tools/testing/selftests/bpf/progs/linked_list.c
371
v = bpf_map_lookup_elem(map, &(int){0});
tools/testing/selftests/bpf/progs/linked_list.c
372
if (!v)
tools/testing/selftests/bpf/progs/linked_list.c
374
return test_list_push_pop_multiple(&v->lock, &v->head);
tools/testing/selftests/bpf/progs/linked_list.c
391
struct map_value *v;
tools/testing/selftests/bpf/progs/linked_list.c
393
v = bpf_map_lookup_elem(&array_map, &(int){0});
tools/testing/selftests/bpf/progs/linked_list.c
394
if (!v)
tools/testing/selftests/bpf/progs/linked_list.c
396
return test_list_in_list(&v->lock, &v->head);
tools/testing/selftests/bpf/progs/linked_list.c
402
struct map_value *v;
tools/testing/selftests/bpf/progs/linked_list.c
408
v = bpf_map_lookup_elem(map, &(int){0});
tools/testing/selftests/bpf/progs/linked_list.c
409
if (!v)
tools/testing/selftests/bpf/progs/linked_list.c
411
return test_list_in_list(&v->lock, &v->head);
tools/testing/selftests/bpf/progs/linked_list_fail.c
108
CHECK(kptr_map, op, &f1->lock, &v->head); \
tools/testing/selftests/bpf/progs/linked_list_fail.c
11
struct map_value *v, *v2, *iv, *iv2; \
tools/testing/selftests/bpf/progs/linked_list_fail.c
113
CHECK(global_map, op, &glock, &v->head); \
tools/testing/selftests/bpf/progs/linked_list_fail.c
116
CHECK(map_map, op, &v->lock, &v2->head); \
tools/testing/selftests/bpf/progs/linked_list_fail.c
117
CHECK(map_kptr, op, &v->lock, &f2->head); \
tools/testing/selftests/bpf/progs/linked_list_fail.c
118
CHECK(map_global, op, &v->lock, &ghead); \
tools/testing/selftests/bpf/progs/linked_list_fail.c
119
CHECK(map_inner_map, op, &v->lock, &iv->head); \
tools/testing/selftests/bpf/progs/linked_list_fail.c
124
CHECK(inner_map_map, op, &iv->lock, &v->head);
tools/testing/selftests/bpf/progs/linked_list_fail.c
145
CHECK(kptr_map, op, &f1->lock, &v->head, &f->node2); \
tools/testing/selftests/bpf/progs/linked_list_fail.c
150
CHECK(global_map, op, &glock, &v->head, &f->node2); \
tools/testing/selftests/bpf/progs/linked_list_fail.c
153
CHECK(map_map, op, &v->lock, &v2->head, &f->node2); \
tools/testing/selftests/bpf/progs/linked_list_fail.c
154
CHECK(map_kptr, op, &v->lock, &f2->head, &b->node); \
tools/testing/selftests/bpf/progs/linked_list_fail.c
155
CHECK(map_global, op, &v->lock, &ghead, &f->node2); \
tools/testing/selftests/bpf/progs/linked_list_fail.c
156
CHECK(map_inner_map, op, &v->lock, &iv->head, &f->node2); \
tools/testing/selftests/bpf/progs/linked_list_fail.c
161
CHECK(inner_map_map, op, &iv->lock, &v->head, &f->node2);
tools/testing/selftests/bpf/progs/linked_list_fail.c
19
v = bpf_map_lookup_elem(&array_map, &(int){ 0 }); \
tools/testing/selftests/bpf/progs/linked_list_fail.c
20
if (!v) \
tools/testing/selftests/bpf/progs/linked_list_fail.c
63
CHECK(map, pop_front, &v->head);
tools/testing/selftests/bpf/progs/linked_list_fail.c
64
CHECK(map, pop_back, &v->head);
tools/testing/selftests/bpf/progs/linked_list_fail.c
86
CHECK(map, push_front, &v->head, &f->node2);
tools/testing/selftests/bpf/progs/linked_list_fail.c
87
CHECK(map, push_back, &v->head, &f->node2);
tools/testing/selftests/bpf/progs/lru_bug.c
23
struct map_value v = {};
tools/testing/selftests/bpf/progs/lru_bug.c
26
bpf_map_update_elem(&lru_map, &(int){0}, &v, 0);
tools/testing/selftests/bpf/progs/lru_bug.c
33
struct map_value val = {}, *v;
tools/testing/selftests/bpf/progs/lru_bug.c
37
v = bpf_map_lookup_elem(&lru_map, &(int){0});
tools/testing/selftests/bpf/progs/lru_bug.c
38
if (!v)
tools/testing/selftests/bpf/progs/lru_bug.c
42
v->ptr = current;
tools/testing/selftests/bpf/progs/lru_bug.c
45
result = !v->ptr;
tools/testing/selftests/bpf/progs/map_kptr.c
124
static void test_kptr_unref(struct map_value *v)
tools/testing/selftests/bpf/progs/map_kptr.c
128
p = v->unref_ptr;
tools/testing/selftests/bpf/progs/map_kptr.c
130
WRITE_ONCE(v->unref_ptr, p);
tools/testing/selftests/bpf/progs/map_kptr.c
136
WRITE_ONCE(v->unref_ptr, p);
tools/testing/selftests/bpf/progs/map_kptr.c
138
WRITE_ONCE(v->unref_ptr, NULL);
tools/testing/selftests/bpf/progs/map_kptr.c
141
static void test_kptr_ref(struct map_value *v)
tools/testing/selftests/bpf/progs/map_kptr.c
145
p = v->ref_ptr;
tools/testing/selftests/bpf/progs/map_kptr.c
147
WRITE_ONCE(v->unref_ptr, p);
tools/testing/selftests/bpf/progs/map_kptr.c
159
p = bpf_kptr_xchg(&v->ref_ptr, NULL);
tools/testing/selftests/bpf/progs/map_kptr.c
172
WRITE_ONCE(v->unref_ptr, p);
tools/testing/selftests/bpf/progs/map_kptr.c
179
p = bpf_kptr_xchg(&v->ref_ptr, p);
tools/testing/selftests/bpf/progs/map_kptr.c
189
static void test_kptr(struct map_value *v)
tools/testing/selftests/bpf/progs/map_kptr.c
191
test_kptr_unref(v);
tools/testing/selftests/bpf/progs/map_kptr.c
192
test_kptr_ref(v);
tools/testing/selftests/bpf/progs/map_kptr.c
198
struct map_value *v;
tools/testing/selftests/bpf/progs/map_kptr.c
202
v = bpf_map_lookup_elem(&map, &key); \
tools/testing/selftests/bpf/progs/map_kptr.c
203
if (!v) \
tools/testing/selftests/bpf/progs/map_kptr.c
205
test_kptr(v)
tools/testing/selftests/bpf/progs/map_kptr.c
221
struct map_value *v;
tools/testing/selftests/bpf/progs/map_kptr.c
223
v = bpf_cgrp_storage_get(&cgrp_ls_map, cgrp, NULL, BPF_LOCAL_STORAGE_GET_F_CREATE);
tools/testing/selftests/bpf/progs/map_kptr.c
224
if (v)
tools/testing/selftests/bpf/progs/map_kptr.c
225
test_kptr(v);
tools/testing/selftests/bpf/progs/map_kptr.c
233
struct map_value *v;
tools/testing/selftests/bpf/progs/map_kptr.c
238
v = bpf_task_storage_get(&task_ls_map, task, NULL, BPF_LOCAL_STORAGE_GET_F_CREATE);
tools/testing/selftests/bpf/progs/map_kptr.c
239
if (v)
tools/testing/selftests/bpf/progs/map_kptr.c
240
test_kptr(v);
tools/testing/selftests/bpf/progs/map_kptr.c
247
struct map_value *v;
tools/testing/selftests/bpf/progs/map_kptr.c
249
v = bpf_inode_storage_get(&inode_ls_map, inode, NULL, BPF_LOCAL_STORAGE_GET_F_CREATE);
tools/testing/selftests/bpf/progs/map_kptr.c
250
if (v)
tools/testing/selftests/bpf/progs/map_kptr.c
251
test_kptr(v);
tools/testing/selftests/bpf/progs/map_kptr.c
258
struct map_value *v;
tools/testing/selftests/bpf/progs/map_kptr.c
264
v = bpf_sk_storage_get(&sk_ls_map, sk, NULL, BPF_LOCAL_STORAGE_GET_F_CREATE);
tools/testing/selftests/bpf/progs/map_kptr.c
265
if (v)
tools/testing/selftests/bpf/progs/map_kptr.c
266
test_kptr(v);
tools/testing/selftests/bpf/progs/map_kptr.c
273
struct map_value *v;
tools/testing/selftests/bpf/progs/map_kptr.c
281
v = bpf_map_lookup_elem(map, &key); \
tools/testing/selftests/bpf/progs/map_kptr.c
282
if (!v) \
tools/testing/selftests/bpf/progs/map_kptr.c
284
test_kptr(v)
tools/testing/selftests/bpf/progs/map_kptr.c
306
int test_map_kptr_ref_pre(struct map_value *v)
tools/testing/selftests/bpf/progs/map_kptr.c
323
p = bpf_kptr_xchg(&v->ref_ptr, p);
tools/testing/selftests/bpf/progs/map_kptr.c
331
p = bpf_kptr_xchg(&v->ref_ptr, NULL);
tools/testing/selftests/bpf/progs/map_kptr.c
343
p = bpf_kptr_xchg(&v->ref_ptr, p);
tools/testing/selftests/bpf/progs/map_kptr.c
360
int test_map_kptr_ref_post(struct map_value *v)
tools/testing/selftests/bpf/progs/map_kptr.c
364
p_st = v->ref_ptr;
tools/testing/selftests/bpf/progs/map_kptr.c
368
p = bpf_kptr_xchg(&v->ref_ptr, NULL);
tools/testing/selftests/bpf/progs/map_kptr.c
376
p = bpf_kptr_xchg(&v->ref_ptr, p);
tools/testing/selftests/bpf/progs/map_kptr.c
388
v = bpf_map_lookup_elem(&map, &key); \
tools/testing/selftests/bpf/progs/map_kptr.c
389
if (!v) \
tools/testing/selftests/bpf/progs/map_kptr.c
391
ret = test_map_kptr_ref_pre(v); \
tools/testing/selftests/bpf/progs/map_kptr.c
396
v = bpf_map_lookup_percpu_elem(&map, &key, 0); \
tools/testing/selftests/bpf/progs/map_kptr.c
397
if (!v) \
tools/testing/selftests/bpf/progs/map_kptr.c
399
ret = test_map_kptr_ref_pre(v); \
tools/testing/selftests/bpf/progs/map_kptr.c
406
struct map_value *v, val = {};
tools/testing/selftests/bpf/progs/map_kptr.c
434
v = bpf_map_lookup_elem(&map, &key); \
tools/testing/selftests/bpf/progs/map_kptr.c
435
if (!v) \
tools/testing/selftests/bpf/progs/map_kptr.c
437
ret = test_map_kptr_ref_post(v); \
tools/testing/selftests/bpf/progs/map_kptr.c
442
v = bpf_map_lookup_percpu_elem(&map, &key, 0); \
tools/testing/selftests/bpf/progs/map_kptr.c
443
if (!v) \
tools/testing/selftests/bpf/progs/map_kptr.c
445
ret = test_map_kptr_ref_post(v); \
tools/testing/selftests/bpf/progs/map_kptr.c
452
struct map_value *v;
tools/testing/selftests/bpf/progs/map_kptr.c
512
struct map_value *v;
tools/testing/selftests/bpf/progs/map_kptr.c
517
v = bpf_task_storage_get(&task_ls_map, current, NULL, 0);
tools/testing/selftests/bpf/progs/map_kptr.c
518
if (v)
tools/testing/selftests/bpf/progs/map_kptr.c
520
v = bpf_task_storage_get(&task_ls_map, current, NULL, BPF_LOCAL_STORAGE_GET_F_CREATE);
tools/testing/selftests/bpf/progs/map_kptr.c
521
if (!v)
tools/testing/selftests/bpf/progs/map_kptr.c
523
return test_map_kptr_ref_pre(v);
tools/testing/selftests/bpf/progs/map_kptr.c
530
struct map_value *v;
tools/testing/selftests/bpf/progs/map_kptr.c
535
v = bpf_task_storage_get(&task_ls_map, current, NULL, 0);
tools/testing/selftests/bpf/progs/map_kptr.c
536
if (!v)
tools/testing/selftests/bpf/progs/map_kptr.c
538
return test_map_kptr_ref_post(v);
tools/testing/selftests/bpf/progs/map_kptr.c
545
struct map_value *v;
tools/testing/selftests/bpf/progs/map_kptr.c
550
v = bpf_task_storage_get(&task_ls_map, current, NULL, 0);
tools/testing/selftests/bpf/progs/map_kptr.c
551
if (!v)
tools/testing/selftests/bpf/progs/map_kptr.c
553
if (!v->ref_ptr)
tools/testing/selftests/bpf/progs/map_kptr_fail.c
100
if (!v)
tools/testing/selftests/bpf/progs/map_kptr_fail.c
103
return *(u64 *)((void *)v + 1);
tools/testing/selftests/bpf/progs/map_kptr_fail.c
111
struct map_value *v;
tools/testing/selftests/bpf/progs/map_kptr_fail.c
114
v = bpf_map_lookup_elem(&array_map, &key);
tools/testing/selftests/bpf/progs/map_kptr_fail.c
115
if (!v)
tools/testing/selftests/bpf/progs/map_kptr_fail.c
118
unref_ptr = v->unref_ptr;
tools/testing/selftests/bpf/progs/map_kptr_fail.c
125
v->unref_ptr = unref_ptr;
tools/testing/selftests/bpf/progs/map_kptr_fail.c
135
struct map_value *v;
tools/testing/selftests/bpf/progs/map_kptr_fail.c
138
v = bpf_map_lookup_elem(&array_map, &key);
tools/testing/selftests/bpf/progs/map_kptr_fail.c
139
if (!v)
tools/testing/selftests/bpf/progs/map_kptr_fail.c
142
unref_ptr = v->unref_ptr;
tools/testing/selftests/bpf/progs/map_kptr_fail.c
146
v->unref_ptr = unref_ptr;
tools/testing/selftests/bpf/progs/map_kptr_fail.c
155
struct map_value *v;
tools/testing/selftests/bpf/progs/map_kptr_fail.c
158
v = bpf_map_lookup_elem(&array_map, &key);
tools/testing/selftests/bpf/progs/map_kptr_fail.c
159
if (!v)
tools/testing/selftests/bpf/progs/map_kptr_fail.c
162
bpf_this_cpu_ptr(v->unref_ptr);
tools/testing/selftests/bpf/progs/map_kptr_fail.c
171
struct map_value *v;
tools/testing/selftests/bpf/progs/map_kptr_fail.c
174
v = bpf_map_lookup_elem(&array_map, &key);
tools/testing/selftests/bpf/progs/map_kptr_fail.c
175
if (!v)
tools/testing/selftests/bpf/progs/map_kptr_fail.c
178
p = v->unref_ptr;
tools/testing/selftests/bpf/progs/map_kptr_fail.c
189
struct map_value *v;
tools/testing/selftests/bpf/progs/map_kptr_fail.c
192
v = bpf_map_lookup_elem(&array_map, &key);
tools/testing/selftests/bpf/progs/map_kptr_fail.c
193
if (!v)
tools/testing/selftests/bpf/progs/map_kptr_fail.c
196
unref_ptr = v->unref_ptr;
tools/testing/selftests/bpf/progs/map_kptr_fail.c
208
struct map_value *v;
tools/testing/selftests/bpf/progs/map_kptr_fail.c
211
v = bpf_map_lookup_elem(&array_map, &key);
tools/testing/selftests/bpf/progs/map_kptr_fail.c
212
if (!v)
tools/testing/selftests/bpf/progs/map_kptr_fail.c
215
bpf_kptr_xchg(&v->unref_ptr, NULL);
tools/testing/selftests/bpf/progs/map_kptr_fail.c
223
struct map_value *v;
tools/testing/selftests/bpf/progs/map_kptr_fail.c
226
v = bpf_map_lookup_elem(&array_map, &key);
tools/testing/selftests/bpf/progs/map_kptr_fail.c
227
if (!v)
tools/testing/selftests/bpf/progs/map_kptr_fail.c
230
bpf_this_cpu_ptr(v->ref_ptr);
tools/testing/selftests/bpf/progs/map_kptr_fail.c
239
struct map_value *v;
tools/testing/selftests/bpf/progs/map_kptr_fail.c
242
v = bpf_map_lookup_elem(&array_map, &key);
tools/testing/selftests/bpf/progs/map_kptr_fail.c
243
if (!v)
tools/testing/selftests/bpf/progs/map_kptr_fail.c
246
p = v->ref_ptr;
tools/testing/selftests/bpf/progs/map_kptr_fail.c
250
*(struct prog_test_ref_kfunc * volatile *)&v->ref_ptr = p;
tools/testing/selftests/bpf/progs/map_kptr_fail.c
259
struct map_value *v;
tools/testing/selftests/bpf/progs/map_kptr_fail.c
262
v = bpf_map_lookup_elem(&array_map, &key);
tools/testing/selftests/bpf/progs/map_kptr_fail.c
263
if (!v)
tools/testing/selftests/bpf/progs/map_kptr_fail.c
266
p = v->ref_ptr;
tools/testing/selftests/bpf/progs/map_kptr_fail.c
269
bpf_kptr_xchg(&v->ref_ptr, p);
tools/testing/selftests/bpf/progs/map_kptr_fail.c
27
struct map_value *v;
tools/testing/selftests/bpf/progs/map_kptr_fail.c
279
struct map_value *v;
tools/testing/selftests/bpf/progs/map_kptr_fail.c
282
v = bpf_map_lookup_elem(&array_map, &key);
tools/testing/selftests/bpf/progs/map_kptr_fail.c
283
if (!v)
tools/testing/selftests/bpf/progs/map_kptr_fail.c
289
bpf_kptr_xchg(&v->ref_memb_ptr, ref_ptr);
tools/testing/selftests/bpf/progs/map_kptr_fail.c
298
struct map_value *v;
tools/testing/selftests/bpf/progs/map_kptr_fail.c
30
v = bpf_map_lookup_elem(&array_map, &key);
tools/testing/selftests/bpf/progs/map_kptr_fail.c
301
v = bpf_map_lookup_elem(&array_map, &key);
tools/testing/selftests/bpf/progs/map_kptr_fail.c
302
if (!v)
tools/testing/selftests/bpf/progs/map_kptr_fail.c
308
bpf_kptr_xchg(&v->ref_memb_ptr, &ref_ptr->memb);
tools/testing/selftests/bpf/progs/map_kptr_fail.c
31
if (!v)
tools/testing/selftests/bpf/progs/map_kptr_fail.c
316
struct map_value *v;
tools/testing/selftests/bpf/progs/map_kptr_fail.c
319
v = bpf_map_lookup_elem(&array_map, &key);
tools/testing/selftests/bpf/progs/map_kptr_fail.c
320
if (!v)
tools/testing/selftests/bpf/progs/map_kptr_fail.c
323
bpf_get_current_comm(v, sizeof(v->buf) + 1);
tools/testing/selftests/bpf/progs/map_kptr_fail.c
337
struct map_value *v;
tools/testing/selftests/bpf/progs/map_kptr_fail.c
34
*(u32 *)&v->unref_ptr = 0;
tools/testing/selftests/bpf/progs/map_kptr_fail.c
340
v = bpf_map_lookup_elem(&array_map, &key);
tools/testing/selftests/bpf/progs/map_kptr_fail.c
341
if (!v)
tools/testing/selftests/bpf/progs/map_kptr_fail.c
344
return write_func((void *)v + 5);
tools/testing/selftests/bpf/progs/map_kptr_fail.c
352
struct map_value *v;
tools/testing/selftests/bpf/progs/map_kptr_fail.c
355
v = bpf_map_lookup_elem(&array_map, &key);
tools/testing/selftests/bpf/progs/map_kptr_fail.c
356
if (!v)
tools/testing/selftests/bpf/progs/map_kptr_fail.c
362
bpf_kptr_xchg(&v->ref_ptr, p);
tools/testing/selftests/bpf/progs/map_kptr_fail.c
371
struct map_value *v;
tools/testing/selftests/bpf/progs/map_kptr_fail.c
374
v = bpf_map_lookup_elem(&array_map, &key);
tools/testing/selftests/bpf/progs/map_kptr_fail.c
375
if (!v)
tools/testing/selftests/bpf/progs/map_kptr_fail.c
381
p = bpf_kptr_xchg(&v->ref_ptr, p);
tools/testing/selftests/bpf/progs/map_kptr_fail.c
42
struct map_value *v;
tools/testing/selftests/bpf/progs/map_kptr_fail.c
45
v = bpf_map_lookup_elem(&array_map, &key);
tools/testing/selftests/bpf/progs/map_kptr_fail.c
46
if (!v)
tools/testing/selftests/bpf/progs/map_kptr_fail.c
52
*(u64 *)((void *)v + id) = 0;
tools/testing/selftests/bpf/progs/map_kptr_fail.c
61
struct map_value *v;
tools/testing/selftests/bpf/progs/map_kptr_fail.c
64
v = bpf_map_lookup_elem(&array_map, &key);
tools/testing/selftests/bpf/progs/map_kptr_fail.c
65
if (!v)
tools/testing/selftests/bpf/progs/map_kptr_fail.c
71
bpf_kptr_xchg((void *)v + id, NULL);
tools/testing/selftests/bpf/progs/map_kptr_fail.c
80
struct map_value *v;
tools/testing/selftests/bpf/progs/map_kptr_fail.c
83
v = bpf_map_lookup_elem(&array_map, &key);
tools/testing/selftests/bpf/progs/map_kptr_fail.c
84
if (!v)
tools/testing/selftests/bpf/progs/map_kptr_fail.c
87
*(void **)((void *)v + 7) = NULL;
tools/testing/selftests/bpf/progs/map_kptr_fail.c
96
struct map_value *v;
tools/testing/selftests/bpf/progs/map_kptr_fail.c
99
v = bpf_map_lookup_elem(&array_map, &key);
tools/testing/selftests/bpf/progs/map_kptr_race.c
100
v = bpf_map_lookup_percpu_elem(&race_percpu_hash_map, &key, i);
tools/testing/selftests/bpf/progs/map_kptr_race.c
101
if (!v)
tools/testing/selftests/bpf/progs/map_kptr_race.c
103
arr[i] = v;
tools/testing/selftests/bpf/progs/map_kptr_race.c
109
v = arr[i];
tools/testing/selftests/bpf/progs/map_kptr_race.c
110
err = fill_percpu_kptr(v);
tools/testing/selftests/bpf/progs/map_kptr_race.c
122
struct map_value *v;
tools/testing/selftests/bpf/progs/map_kptr_race.c
130
v = bpf_sk_storage_get(&race_sk_ls_map, sk, NULL,
tools/testing/selftests/bpf/progs/map_kptr_race.c
132
if (!v)
tools/testing/selftests/bpf/progs/map_kptr_race.c
138
old = bpf_kptr_xchg(&v->ref_ptr, p);
tools/testing/selftests/bpf/progs/map_kptr_race.c
147
old = bpf_kptr_xchg(&v->ref_ptr, p);
tools/testing/selftests/bpf/progs/map_kptr_race.c
46
struct map_value *v;
tools/testing/selftests/bpf/progs/map_kptr_race.c
52
v = bpf_map_lookup_elem(&race_hash_map, &key);
tools/testing/selftests/bpf/progs/map_kptr_race.c
53
if (!v)
tools/testing/selftests/bpf/progs/map_kptr_race.c
59
old = bpf_kptr_xchg(&v->ref_ptr, p);
tools/testing/selftests/bpf/progs/map_kptr_race.c
68
old = bpf_kptr_xchg(&v->ref_ptr, p);
tools/testing/selftests/bpf/progs/map_kptr_race.c
75
static int fill_percpu_kptr(struct map_value *v)
tools/testing/selftests/bpf/progs/map_kptr_race.c
82
old = bpf_kptr_xchg(&v->ref_ptr, p);
tools/testing/selftests/bpf/progs/map_kptr_race.c
91
struct map_value *v, *arr[16] = {};
tools/testing/selftests/bpf/progs/mem_rdonly_untrusted.c
100
v = 1;
tools/testing/selftests/bpf/progs/mem_rdonly_untrusted.c
101
p = bpf_rdonly_cast(&v, 0);
tools/testing/selftests/bpf/progs/mem_rdonly_untrusted.c
111
long v, *p;
tools/testing/selftests/bpf/progs/mem_rdonly_untrusted.c
113
v = 1;
tools/testing/selftests/bpf/progs/mem_rdonly_untrusted.c
114
p = bpf_rdonly_cast(&v, 0);
tools/testing/selftests/bpf/progs/mem_rdonly_untrusted.c
58
int v, *p;
tools/testing/selftests/bpf/progs/mem_rdonly_untrusted.c
60
v = 1;
tools/testing/selftests/bpf/progs/mem_rdonly_untrusted.c
61
p = bpf_rdonly_cast(&v, 0);
tools/testing/selftests/bpf/progs/mem_rdonly_untrusted.c
85
int v, *p;
tools/testing/selftests/bpf/progs/mem_rdonly_untrusted.c
87
v = 1;
tools/testing/selftests/bpf/progs/mem_rdonly_untrusted.c
88
p = bpf_rdonly_cast(&v, 0);
tools/testing/selftests/bpf/progs/mem_rdonly_untrusted.c
98
int v, *p;
tools/testing/selftests/bpf/progs/percpu_alloc_array.c
100
cpu0_field_d = v->d;
tools/testing/selftests/bpf/progs/percpu_alloc_array.c
101
sum_field_c += v->c;
tools/testing/selftests/bpf/progs/percpu_alloc_array.c
134
struct val_t *v;
tools/testing/selftests/bpf/progs/percpu_alloc_array.c
158
v = bpf_this_cpu_ptr(p);
tools/testing/selftests/bpf/progs/percpu_alloc_array.c
159
v->c = 3;
tools/testing/selftests/bpf/progs/percpu_alloc_array.c
160
v = bpf_this_cpu_ptr(p);
tools/testing/selftests/bpf/progs/percpu_alloc_array.c
161
v->c = 0;
tools/testing/selftests/bpf/progs/percpu_alloc_array.c
163
v = bpf_per_cpu_ptr(p, 0);
tools/testing/selftests/bpf/progs/percpu_alloc_array.c
164
if (!v)
tools/testing/selftests/bpf/progs/percpu_alloc_array.c
166
v->c = 1;
tools/testing/selftests/bpf/progs/percpu_alloc_array.c
167
v->d = 2;
tools/testing/selftests/bpf/progs/percpu_alloc_array.c
175
v = bpf_per_cpu_ptr(p, i);
tools/testing/selftests/bpf/progs/percpu_alloc_array.c
176
if (v) {
tools/testing/selftests/bpf/progs/percpu_alloc_array.c
178
cpu0_field_d = v->d;
tools/testing/selftests/bpf/progs/percpu_alloc_array.c
179
sum_field_c += v->c;
tools/testing/selftests/bpf/progs/percpu_alloc_array.c
52
struct val_t *v;
tools/testing/selftests/bpf/progs/percpu_alloc_array.c
64
v = bpf_per_cpu_ptr(p, 0);
tools/testing/selftests/bpf/progs/percpu_alloc_array.c
65
if (!v)
tools/testing/selftests/bpf/progs/percpu_alloc_array.c
67
v->c = 1;
tools/testing/selftests/bpf/progs/percpu_alloc_array.c
68
v->d = 2;
tools/testing/selftests/bpf/progs/percpu_alloc_array.c
82
struct val_t *v;
tools/testing/selftests/bpf/progs/percpu_alloc_array.c
97
v = bpf_per_cpu_ptr(p, i);
tools/testing/selftests/bpf/progs/percpu_alloc_array.c
98
if (v) {
tools/testing/selftests/bpf/progs/percpu_alloc_cgrp_local_storage.c
101
cpu0_field_d = v->d;
tools/testing/selftests/bpf/progs/percpu_alloc_cgrp_local_storage.c
102
sum_field_c += v->c;
tools/testing/selftests/bpf/progs/percpu_alloc_cgrp_local_storage.c
52
struct val_t *v;
tools/testing/selftests/bpf/progs/percpu_alloc_cgrp_local_storage.c
64
v = bpf_per_cpu_ptr(p, 0);
tools/testing/selftests/bpf/progs/percpu_alloc_cgrp_local_storage.c
65
if (!v)
tools/testing/selftests/bpf/progs/percpu_alloc_cgrp_local_storage.c
67
v->c = 1;
tools/testing/selftests/bpf/progs/percpu_alloc_cgrp_local_storage.c
68
v->d = 2;
tools/testing/selftests/bpf/progs/percpu_alloc_cgrp_local_storage.c
81
struct val_t *v;
tools/testing/selftests/bpf/progs/percpu_alloc_cgrp_local_storage.c
98
v = bpf_per_cpu_ptr(p, i);
tools/testing/selftests/bpf/progs/percpu_alloc_cgrp_local_storage.c
99
if (v) {
tools/testing/selftests/bpf/progs/percpu_alloc_fail.c
107
v = bpf_this_cpu_ptr(p);
tools/testing/selftests/bpf/progs/percpu_alloc_fail.c
108
ret = v->b;
tools/testing/selftests/bpf/progs/percpu_alloc_fail.c
91
struct val_t *v;
tools/testing/selftests/bpf/progs/refcounted_kptr.c
615
struct map_value *v;
tools/testing/selftests/bpf/progs/refcounted_kptr.c
618
v = bpf_map_lookup_elem(&percpu_hash, &key);
tools/testing/selftests/bpf/progs/refcounted_kptr.c
619
if (!v)
tools/testing/selftests/bpf/progs/refcounted_kptr.c
622
return __insert_in_list(&head, &lock, &v->node);
tools/testing/selftests/bpf/progs/task_kfunc_common.h
44
struct __tasks_kfunc_map_value local, *v;
tools/testing/selftests/bpf/progs/task_kfunc_common.h
58
v = bpf_map_lookup_elem(&__tasks_kfunc_map, &pid);
tools/testing/selftests/bpf/progs/task_kfunc_common.h
59
if (!v) {
tools/testing/selftests/bpf/progs/task_kfunc_common.h
68
old = bpf_kptr_xchg(&v->task, acquired);
tools/testing/selftests/bpf/progs/task_kfunc_failure.c
136
struct __tasks_kfunc_map_value *v;
tools/testing/selftests/bpf/progs/task_kfunc_failure.c
138
v = insert_lookup_task(task);
tools/testing/selftests/bpf/progs/task_kfunc_failure.c
139
if (!v)
tools/testing/selftests/bpf/progs/task_kfunc_failure.c
142
kptr = bpf_kptr_xchg(&v->task, NULL);
tools/testing/selftests/bpf/progs/task_kfunc_failure.c
168
struct __tasks_kfunc_map_value *v;
tools/testing/selftests/bpf/progs/task_kfunc_failure.c
170
v = insert_lookup_task(task);
tools/testing/selftests/bpf/progs/task_kfunc_failure.c
171
if (!v)
tools/testing/selftests/bpf/progs/task_kfunc_failure.c
175
bpf_task_release(v->task);
tools/testing/selftests/bpf/progs/task_kfunc_failure.c
196
struct __tasks_kfunc_map_value local, *v;
tools/testing/selftests/bpf/progs/task_kfunc_failure.c
210
v = bpf_map_lookup_elem(&__tasks_kfunc_map, &pid);
tools/testing/selftests/bpf/progs/task_kfunc_failure.c
211
if (!v)
tools/testing/selftests/bpf/progs/task_kfunc_failure.c
218
old = bpf_kptr_xchg(&v->task, acquired);
tools/testing/selftests/bpf/progs/task_kfunc_failure.c
320
struct __tasks_kfunc_map_value *v;
tools/testing/selftests/bpf/progs/task_kfunc_failure.c
325
v = tasks_kfunc_map_value_lookup(task);
tools/testing/selftests/bpf/progs/task_kfunc_failure.c
326
if (!v)
tools/testing/selftests/bpf/progs/task_kfunc_failure.c
330
local = v->task;
tools/testing/selftests/bpf/progs/task_kfunc_failure.c
35
struct __tasks_kfunc_map_value *v;
tools/testing/selftests/bpf/progs/task_kfunc_failure.c
37
v = insert_lookup_task(task);
tools/testing/selftests/bpf/progs/task_kfunc_failure.c
38
if (!v)
tools/testing/selftests/bpf/progs/task_kfunc_failure.c
42
acquired = bpf_task_acquire(v->task);
tools/testing/selftests/bpf/progs/task_kfunc_success.c
147
struct __tasks_kfunc_map_value *v, *local;
tools/testing/selftests/bpf/progs/task_kfunc_success.c
160
v = tasks_kfunc_map_value_lookup(task);
tools/testing/selftests/bpf/progs/task_kfunc_success.c
161
if (!v) {
tools/testing/selftests/bpf/progs/task_kfunc_success.c
166
kptr = bpf_kptr_xchg(&v->task, NULL);
tools/testing/selftests/bpf/progs/task_kfunc_success.c
231
struct __tasks_kfunc_map_value *v;
tools/testing/selftests/bpf/progs/task_kfunc_success.c
243
v = tasks_kfunc_map_value_lookup(task);
tools/testing/selftests/bpf/progs/task_kfunc_success.c
244
if (!v) {
tools/testing/selftests/bpf/progs/task_kfunc_success.c
250
kptr = v->task;
tools/testing/selftests/bpf/progs/test_global_func15.c
10
*v = bpf_get_prandom_u32();
tools/testing/selftests/bpf/progs/test_global_func15.c
19
unsigned int v = 1;
tools/testing/selftests/bpf/progs/test_global_func15.c
21
foo(&v);
tools/testing/selftests/bpf/progs/test_global_func15.c
23
return v;
tools/testing/selftests/bpf/progs/test_global_func15.c
7
__noinline int foo(unsigned int *v)
tools/testing/selftests/bpf/progs/test_global_func15.c
9
if (v)
tools/testing/selftests/bpf/progs/test_global_func_args.c
28
save_value(index, s->v);
tools/testing/selftests/bpf/progs/test_global_func_args.c
29
return ++s->v;
tools/testing/selftests/bpf/progs/test_global_func_args.c
40
save_value(index, s->v);
tools/testing/selftests/bpf/progs/test_global_func_args.c
41
return ++s->v;
tools/testing/selftests/bpf/progs/test_global_func_args.c
63
const int v = foo(index++, 0);
tools/testing/selftests/bpf/progs/test_global_func_args.c
65
save_value(index++, v);
tools/testing/selftests/bpf/progs/test_global_func_args.c
69
struct S s = { .v = 100 };
tools/testing/selftests/bpf/progs/test_global_func_args.c
72
save_value(index++, s.v);
tools/testing/selftests/bpf/progs/test_global_func_args.c
76
global_variable.v = 42;
tools/testing/selftests/bpf/progs/test_global_func_args.c
78
save_value(index++, global_variable.v);
tools/testing/selftests/bpf/progs/test_global_func_args.c
8
int v;
tools/testing/selftests/bpf/progs/test_global_func_args.c
82
struct S v, *p = &v;
tools/testing/selftests/bpf/progs/test_spin_lock_fail.c
115
CHECK(kptr_mapval, &f1->lock, &v->lock);
tools/testing/selftests/bpf/progs/test_spin_lock_fail.c
120
CHECK(global_mapval, &lockA, &v->lock);
tools/testing/selftests/bpf/progs/test_spin_lock_fail.c
143
CHECK(mapval_kptr, &v->lock, &f1->lock);
tools/testing/selftests/bpf/progs/test_spin_lock_fail.c
144
CHECK(mapval_global, &v->lock, &lockB);
tools/testing/selftests/bpf/progs/test_spin_lock_fail.c
145
CHECK(mapval_innermapval, &v->lock, &iv->lock);
tools/testing/selftests/bpf/progs/test_spin_lock_fail.c
200
CHECK(innermapval_mapval, &iv->lock, &v->lock);
tools/testing/selftests/bpf/progs/test_spin_lock_fail.c
87
struct foo *f1, *f2, *v, *iv; \
tools/testing/selftests/bpf/progs/test_spin_lock_fail.c
97
v = bpf_map_lookup_elem(&array_map, &key); \
tools/testing/selftests/bpf/progs/test_spin_lock_fail.c
98
if (!v) \
tools/testing/selftests/bpf/progs/test_subprogs.c
22
static __noinline int sub5(int v);
tools/testing/selftests/bpf/progs/test_subprogs.c
45
static __noinline int sub5(int v)
tools/testing/selftests/bpf/progs/test_subprogs.c
47
return sub1(v) - 1; /* compensates sub1()'s + 1 */
tools/testing/selftests/bpf/progs/test_tcpbpf_kern.c
102
v = 0xff;
tools/testing/selftests/bpf/progs/test_tcpbpf_kern.c
103
rv = bpf_setsockopt(skops, SOL_IPV6, IPV6_TCLASS, &v,
tools/testing/selftests/bpf/progs/test_tcpbpf_kern.c
104
sizeof(v));
tools/testing/selftests/bpf/progs/test_tcpbpf_kern.c
106
v = bpf_getsockopt(skops, IPPROTO_TCP, TCP_SAVED_SYN,
tools/testing/selftests/bpf/progs/test_tcpbpf_kern.c
109
if (!v) {
tools/testing/selftests/bpf/progs/test_tcpbpf_kern.c
113
v = thdr->syn;
tools/testing/selftests/bpf/progs/test_tcpbpf_kern.c
115
global.tcp_saved_syn = v;
tools/testing/selftests/bpf/progs/test_tcpbpf_kern.c
143
v = bpf_setsockopt(skops, IPPROTO_TCP, TCP_SAVE_SYN,
tools/testing/selftests/bpf/progs/test_tcpbpf_kern.c
146
global.tcp_save_syn = v;
tools/testing/selftests/bpf/progs/test_tcpbpf_kern.c
40
int v = 0;
tools/testing/selftests/bpf/progs/timer_lockup.c
33
static int timer_cb1(void *map, int *k, struct elem *v)
tools/testing/selftests/bpf/progs/timer_lockup.c
45
static int timer_cb2(void *map, int *k, struct elem *v)
tools/testing/selftests/bpf/progs/uptr_failure.c
100
bpf_obj_drop(v);
tools/testing/selftests/bpf/progs/uptr_failure.c
22
struct value_type *v;
tools/testing/selftests/bpf/progs/uptr_failure.c
25
v = bpf_task_storage_get(&datamap, task, 0,
tools/testing/selftests/bpf/progs/uptr_failure.c
27
if (!v)
tools/testing/selftests/bpf/progs/uptr_failure.c
30
v->udata = NULL;
tools/testing/selftests/bpf/progs/uptr_failure.c
39
struct value_type *v;
tools/testing/selftests/bpf/progs/uptr_failure.c
42
v = bpf_task_storage_get(&datamap, task, 0,
tools/testing/selftests/bpf/progs/uptr_failure.c
44
if (!v)
tools/testing/selftests/bpf/progs/uptr_failure.c
47
v->nested.udata = NULL;
tools/testing/selftests/bpf/progs/uptr_failure.c
56
struct value_type *v;
tools/testing/selftests/bpf/progs/uptr_failure.c
59
v = bpf_task_storage_get(&datamap, task, 0,
tools/testing/selftests/bpf/progs/uptr_failure.c
61
if (!v)
tools/testing/selftests/bpf/progs/uptr_failure.c
64
v->udata->result = 0;
tools/testing/selftests/bpf/progs/uptr_failure.c
74
struct value_type *v;
tools/testing/selftests/bpf/progs/uptr_failure.c
77
v = bpf_task_storage_get(&datamap, task, 0,
tools/testing/selftests/bpf/progs/uptr_failure.c
79
if (!v)
tools/testing/selftests/bpf/progs/uptr_failure.c
82
bpf_kptr_xchg(&v->udata, NULL);
tools/testing/selftests/bpf/progs/uptr_failure.c
91
struct value_type *v;
tools/testing/selftests/bpf/progs/uptr_failure.c
93
v = bpf_obj_new(typeof(*v));
tools/testing/selftests/bpf/progs/uptr_failure.c
94
if (!v)
tools/testing/selftests/bpf/progs/uptr_failure.c
97
if (v->udata)
tools/testing/selftests/bpf/progs/uptr_failure.c
98
v->udata->result = 0;
tools/testing/selftests/bpf/progs/verifier_iterating_callbacks.c
559
int *v, sum = 0;
tools/testing/selftests/bpf/progs/verifier_iterating_callbacks.c
563
while ((v = bpf_iter_num_next(&it))) {
tools/testing/selftests/bpf/progs/verifier_iterating_callbacks.c
576
int *v, sum = 0;
tools/testing/selftests/bpf/progs/verifier_iterating_callbacks.c
580
while ((v = bpf_iter_num_next(&it))) {
tools/testing/selftests/bpf/progs/verifier_iterating_callbacks.c
595
int *v, sum = 0;
tools/testing/selftests/bpf/progs/verifier_iterating_callbacks.c
599
while ((v = bpf_iter_num_next(&it))) {
tools/testing/selftests/drivers/net/hw/iou-zcrx.c
74
#define ALIGN_UP(v, align) (((v) + (align) - 1) & ~((align) - 1))
tools/testing/selftests/filesystems/epoll/epoll_wakeup_test.c
3172
uint64_t v;
tools/testing/selftests/filesystems/epoll/epoll_wakeup_test.c
3202
ret = read(e.data.fd, &v, sizeof(v));
tools/testing/selftests/filesystems/epoll/epoll_wakeup_test.c
3204
assert(ret == sizeof(v));
tools/testing/selftests/filesystems/epoll/epoll_wakeup_test.c
3257
uint64_t v = 1, ms;
tools/testing/selftests/filesystems/epoll/epoll_wakeup_test.c
3277
ret = write(ctx.evfd[n], &v, sizeof(v));
tools/testing/selftests/filesystems/epoll/epoll_wakeup_test.c
3278
ASSERT_EQ(ret, sizeof(v));
tools/testing/selftests/kselftest_harness.h
1073
struct __fixture_variant_metadata *v;
tools/testing/selftests/kselftest_harness.h
1078
v = f->variant;
tools/testing/selftests/kselftest_harness.h
1090
v ? v->name : "",
tools/testing/selftests/kselftest_harness.h
1093
v = v ? v->next : NULL;
tools/testing/selftests/kselftest_harness.h
1095
} while (v || t);
tools/testing/selftests/kselftest_harness.h
1150
struct __fixture_variant_metadata *v,
tools/testing/selftests/kselftest_harness.h
1172
if (!strcmp(v->name, optarg))
tools/testing/selftests/kselftest_harness.h
1178
vlen = strlen(v->name);
tools/testing/selftests/kselftest_harness.h
1183
!strncmp(v->name, &optarg[flen + 1], vlen) &&
tools/testing/selftests/kselftest_harness.h
1258
struct __fixture_variant_metadata *v;
tools/testing/selftests/kselftest_harness.h
1272
for (v = f->variant ?: &no_variant; v; v = v->next) {
tools/testing/selftests/kselftest_harness.h
1276
if (test_enabled(argc, argv, f, v, t))
tools/testing/selftests/kselftest_harness.h
1292
for (v = f->variant ?: &no_variant; v; v = v->next) {
tools/testing/selftests/kselftest_harness.h
1294
if (!test_enabled(argc, argv, f, v, t))
tools/testing/selftests/kselftest_harness.h
1298
__run_test(f, v, t);
tools/testing/selftests/kvm/arm64/debug-exceptions.c
38
#define PC(v) ((uint64_t)&(v))
tools/testing/selftests/kvm/arm64/get-reg-list.c
31
#define FEAT(id, f, v) \
tools/testing/selftests/kvm/arm64/get-reg-list.c
34
.feat_min = id ## _ ## f ## _ ## v
tools/testing/selftests/kvm/arm64/get-reg-list.c
36
#define REG_FEAT(r, id, f, v) \
tools/testing/selftests/kvm/arm64/get-reg-list.c
39
FEAT(id, f, v) \
tools/testing/selftests/kvm/arm64/sea_to_user.c
121
static void sigbus_signal_handler(int sig, siginfo_t *si, void *v)
tools/testing/selftests/kvm/arm64/vgic_init.c
101
close(v->gic_fd);
tools/testing/selftests/kvm/arm64/vgic_init.c
102
kvm_vm_free(v->vm);
tools/testing/selftests/kvm/arm64/vgic_init.c
143
static void subtest_dist_rdist(struct vm_gic *v)
tools/testing/selftests/kvm/arm64/vgic_init.c
150
rdist = VGIC_DEV_IS_V3(v->gic_dev_type) ? gic_v3_redist_region
tools/testing/selftests/kvm/arm64/vgic_init.c
152
dist = VGIC_DEV_IS_V3(v->gic_dev_type) ? gic_v3_dist_region
tools/testing/selftests/kvm/arm64/vgic_init.c
156
kvm_has_device_attr(v->gic_fd, KVM_DEV_ARM_VGIC_GRP_ADDR, dist.attr);
tools/testing/selftests/kvm/arm64/vgic_init.c
158
kvm_has_device_attr(v->gic_fd, KVM_DEV_ARM_VGIC_GRP_ADDR, rdist.attr);
tools/testing/selftests/kvm/arm64/vgic_init.c
161
ret = __kvm_has_device_attr(v->gic_fd, KVM_DEV_ARM_VGIC_GRP_ADDR, -1);
tools/testing/selftests/kvm/arm64/vgic_init.c
166
ret = __kvm_device_attr_set(v->gic_fd, KVM_DEV_ARM_VGIC_GRP_ADDR,
tools/testing/selftests/kvm/arm64/vgic_init.c
171
ret = __kvm_device_attr_set(v->gic_fd, KVM_DEV_ARM_VGIC_GRP_ADDR,
tools/testing/selftests/kvm/arm64/vgic_init.c
177
ret = __kvm_device_attr_set(v->gic_fd, KVM_DEV_ARM_VGIC_GRP_ADDR,
tools/testing/selftests/kvm/arm64/vgic_init.c
181
ret = __kvm_device_attr_set(v->gic_fd, KVM_DEV_ARM_VGIC_GRP_ADDR,
tools/testing/selftests/kvm/arm64/vgic_init.c
187
ret = __kvm_device_attr_set(v->gic_fd, KVM_DEV_ARM_VGIC_GRP_ADDR,
tools/testing/selftests/kvm/arm64/vgic_init.c
194
kvm_device_attr_set(v->gic_fd, KVM_DEV_ARM_VGIC_GRP_ADDR,
tools/testing/selftests/kvm/arm64/vgic_init.c
199
ret = __kvm_device_attr_set(v->gic_fd, KVM_DEV_ARM_VGIC_GRP_ADDR,
tools/testing/selftests/kvm/arm64/vgic_init.c
203
ret = __kvm_has_device_attr(v->gic_fd, KVM_DEV_ARM_VGIC_GRP_ADDR,
tools/testing/selftests/kvm/arm64/vgic_init.c
208
ret = __kvm_device_attr_set(v->gic_fd, KVM_DEV_ARM_VGIC_GRP_ADDR,
tools/testing/selftests/kvm/arm64/vgic_init.c
219
kvm_device_attr_set(v->gic_fd, KVM_DEV_ARM_VGIC_GRP_ADDR,
tools/testing/selftests/kvm/arm64/vgic_init.c
224
static void subtest_v3_redist_regions(struct vm_gic *v)
tools/testing/selftests/kvm/arm64/vgic_init.c
229
ret = __kvm_has_device_attr(v->gic_fd, KVM_DEV_ARM_VGIC_GRP_ADDR,
tools/testing/selftests/kvm/arm64/vgic_init.c
234
ret = __kvm_device_attr_set(v->gic_fd, KVM_DEV_ARM_VGIC_GRP_ADDR,
tools/testing/selftests/kvm/arm64/vgic_init.c
239
ret = __kvm_device_attr_set(v->gic_fd, KVM_DEV_ARM_VGIC_GRP_ADDR,
tools/testing/selftests/kvm/arm64/vgic_init.c
244
ret = __kvm_device_attr_set(v->gic_fd, KVM_DEV_ARM_VGIC_GRP_ADDR,
tools/testing/selftests/kvm/arm64/vgic_init.c
250
ret = __kvm_device_attr_set(v->gic_fd, KVM_DEV_ARM_VGIC_GRP_ADDR,
tools/testing/selftests/kvm/arm64/vgic_init.c
255
kvm_device_attr_set(v->gic_fd, KVM_DEV_ARM_VGIC_GRP_ADDR,
tools/testing/selftests/kvm/arm64/vgic_init.c
259
ret = __kvm_device_attr_set(v->gic_fd, KVM_DEV_ARM_VGIC_GRP_ADDR,
tools/testing/selftests/kvm/arm64/vgic_init.c
264
ret = __kvm_device_attr_set(v->gic_fd, KVM_DEV_ARM_VGIC_GRP_ADDR,
tools/testing/selftests/kvm/arm64/vgic_init.c
270
ret = __kvm_device_attr_set(v->gic_fd, KVM_DEV_ARM_VGIC_GRP_ADDR,
tools/testing/selftests/kvm/arm64/vgic_init.c
275
kvm_device_attr_set(v->gic_fd, KVM_DEV_ARM_VGIC_GRP_ADDR,
tools/testing/selftests/kvm/arm64/vgic_init.c
279
ret = __kvm_device_attr_set(v->gic_fd, KVM_DEV_ARM_VGIC_GRP_ADDR,
tools/testing/selftests/kvm/arm64/vgic_init.c
286
ret = __kvm_device_attr_set(v->gic_fd, KVM_DEV_ARM_VGIC_GRP_ADDR,
tools/testing/selftests/kvm/arm64/vgic_init.c
292
ret = __kvm_device_attr_set(v->gic_fd, KVM_DEV_ARM_VGIC_GRP_ADDR,
tools/testing/selftests/kvm/arm64/vgic_init.c
306
ret = __kvm_device_attr_get(v->gic_fd, KVM_DEV_ARM_VGIC_GRP_ADDR,
tools/testing/selftests/kvm/arm64/vgic_init.c
312
ret = __kvm_device_attr_get(v->gic_fd, KVM_DEV_ARM_VGIC_GRP_ADDR,
tools/testing/selftests/kvm/arm64/vgic_init.c
317
ret = __kvm_device_attr_get(v->gic_fd, KVM_DEV_ARM_VGIC_GRP_ADDR,
tools/testing/selftests/kvm/arm64/vgic_init.c
322
kvm_device_attr_set(v->gic_fd, KVM_DEV_ARM_VGIC_GRP_ADDR,
tools/testing/selftests/kvm/arm64/vgic_init.c
326
ret = __kvm_device_attr_set(v->gic_fd, KVM_DEV_ARM_VGIC_GRP_ADDR,
tools/testing/selftests/kvm/arm64/vgic_init.c
338
struct vm_gic v;
tools/testing/selftests/kvm/arm64/vgic_init.c
341
v = vm_gic_create_with_vcpus(gic_dev_type, 1, vcpus);
tools/testing/selftests/kvm/arm64/vgic_init.c
343
subtest_dist_rdist(&v);
tools/testing/selftests/kvm/arm64/vgic_init.c
347
vcpus[i] = vm_vcpu_add(v.vm, i, guest_code);
tools/testing/selftests/kvm/arm64/vgic_init.c
352
vm_gic_destroy(&v);
tools/testing/selftests/kvm/arm64/vgic_init.c
359
struct vm_gic v;
tools/testing/selftests/kvm/arm64/vgic_init.c
362
v = vm_gic_create_with_vcpus(gic_dev_type, NR_VCPUS, vcpus);
tools/testing/selftests/kvm/arm64/vgic_init.c
364
subtest_dist_rdist(&v);
tools/testing/selftests/kvm/arm64/vgic_init.c
369
vm_gic_destroy(&v);
tools/testing/selftests/kvm/arm64/vgic_init.c
380
struct vm_gic v;
tools/testing/selftests/kvm/arm64/vgic_init.c
384
v = vm_gic_create_barebones(KVM_DEV_TYPE_ARM_VGIC_V2);
tools/testing/selftests/kvm/arm64/vgic_init.c
385
subtest_dist_rdist(&v);
tools/testing/selftests/kvm/arm64/vgic_init.c
387
ret = __kvm_has_device_attr(v.gic_fd, KVM_DEV_ARM_VGIC_GRP_CPU_REGS,
tools/testing/selftests/kvm/arm64/vgic_init.c
392
ret = __kvm_device_attr_get(v.gic_fd, KVM_DEV_ARM_VGIC_GRP_CPU_REGS,
tools/testing/selftests/kvm/arm64/vgic_init.c
397
ret = __kvm_device_attr_set(v.gic_fd, KVM_DEV_ARM_VGIC_GRP_CPU_REGS,
tools/testing/selftests/kvm/arm64/vgic_init.c
403
vm_gic_destroy(&v);
tools/testing/selftests/kvm/arm64/vgic_init.c
410
struct vm_gic v;
tools/testing/selftests/kvm/arm64/vgic_init.c
414
v = vm_gic_create_with_vcpus(KVM_DEV_TYPE_ARM_VGIC_V3, NR_VCPUS, vcpus);
tools/testing/selftests/kvm/arm64/vgic_init.c
415
subtest_v3_redist_regions(&v);
tools/testing/selftests/kvm/arm64/vgic_init.c
416
kvm_device_attr_set(v.gic_fd, KVM_DEV_ARM_VGIC_GRP_CTRL,
tools/testing/selftests/kvm/arm64/vgic_init.c
421
vm_gic_destroy(&v);
tools/testing/selftests/kvm/arm64/vgic_init.c
425
v = vm_gic_create_with_vcpus(KVM_DEV_TYPE_ARM_VGIC_V3, NR_VCPUS, vcpus);
tools/testing/selftests/kvm/arm64/vgic_init.c
426
subtest_v3_redist_regions(&v);
tools/testing/selftests/kvm/arm64/vgic_init.c
429
kvm_device_attr_set(v.gic_fd, KVM_DEV_ARM_VGIC_GRP_ADDR,
tools/testing/selftests/kvm/arm64/vgic_init.c
435
vm_gic_destroy(&v);
tools/testing/selftests/kvm/arm64/vgic_init.c
439
v = vm_gic_create_with_vcpus(KVM_DEV_TYPE_ARM_VGIC_V3, NR_VCPUS, vcpus);
tools/testing/selftests/kvm/arm64/vgic_init.c
440
subtest_v3_redist_regions(&v);
tools/testing/selftests/kvm/arm64/vgic_init.c
442
ret = __kvm_device_attr_set(v.gic_fd, KVM_DEV_ARM_VGIC_GRP_ADDR,
tools/testing/selftests/kvm/arm64/vgic_init.c
448
kvm_device_attr_set(v.gic_fd, KVM_DEV_ARM_VGIC_GRP_ADDR,
tools/testing/selftests/kvm/arm64/vgic_init.c
451
kvm_device_attr_set(v.gic_fd, KVM_DEV_ARM_VGIC_GRP_CTRL,
tools/testing/selftests/kvm/arm64/vgic_init.c
457
vm_gic_destroy(&v);
tools/testing/selftests/kvm/arm64/vgic_init.c
462
struct vm_gic v;
tools/testing/selftests/kvm/arm64/vgic_init.c
466
v.vm = vm_create(NR_VCPUS);
tools/testing/selftests/kvm/arm64/vgic_init.c
467
(void)vm_vcpu_add(v.vm, 0, guest_code);
tools/testing/selftests/kvm/arm64/vgic_init.c
469
v.gic_fd = kvm_create_device(v.vm, KVM_DEV_TYPE_ARM_VGIC_V3);
tools/testing/selftests/kvm/arm64/vgic_init.c
471
(void)vm_vcpu_add(v.vm, 3, guest_code);
tools/testing/selftests/kvm/arm64/vgic_init.c
473
v3_redist_reg_get_errno(v.gic_fd, 1, GICR_TYPER, EINVAL,
tools/testing/selftests/kvm/arm64/vgic_init.c
476
(void)vm_vcpu_add(v.vm, 1, guest_code);
tools/testing/selftests/kvm/arm64/vgic_init.c
478
v3_redist_reg_get_errno(v.gic_fd, 1, GICR_TYPER, EBUSY,
tools/testing/selftests/kvm/arm64/vgic_init.c
481
(void)vm_vcpu_add(v.vm, 2, guest_code);
tools/testing/selftests/kvm/arm64/vgic_init.c
483
kvm_device_attr_set(v.gic_fd, KVM_DEV_ARM_VGIC_GRP_CTRL,
tools/testing/selftests/kvm/arm64/vgic_init.c
487
v3_redist_reg_get(v.gic_fd, i, GICR_TYPER, i * 0x100,
tools/testing/selftests/kvm/arm64/vgic_init.c
492
kvm_device_attr_set(v.gic_fd, KVM_DEV_ARM_VGIC_GRP_ADDR,
tools/testing/selftests/kvm/arm64/vgic_init.c
496
v3_redist_reg_get(v.gic_fd, 0, GICR_TYPER, 0x0, "read typer of rdist #0");
tools/testing/selftests/kvm/arm64/vgic_init.c
497
v3_redist_reg_get(v.gic_fd, 3, GICR_TYPER, 0x310, "read typer of rdist #1");
tools/testing/selftests/kvm/arm64/vgic_init.c
500
ret = __kvm_device_attr_set(v.gic_fd, KVM_DEV_ARM_VGIC_GRP_ADDR,
tools/testing/selftests/kvm/arm64/vgic_init.c
504
v3_redist_reg_get(v.gic_fd, 1, GICR_TYPER, 0x100,
tools/testing/selftests/kvm/arm64/vgic_init.c
506
v3_redist_reg_get(v.gic_fd, 2, GICR_TYPER, 0x200,
tools/testing/selftests/kvm/arm64/vgic_init.c
510
kvm_device_attr_set(v.gic_fd, KVM_DEV_ARM_VGIC_GRP_ADDR,
tools/testing/selftests/kvm/arm64/vgic_init.c
513
v3_redist_reg_get(v.gic_fd, 1, GICR_TYPER, 0x100, "read typer of rdist #1");
tools/testing/selftests/kvm/arm64/vgic_init.c
514
v3_redist_reg_get(v.gic_fd, 2, GICR_TYPER, 0x210,
tools/testing/selftests/kvm/arm64/vgic_init.c
517
vm_gic_destroy(&v);
tools/testing/selftests/kvm/arm64/vgic_init.c
523
struct vm_gic v;
tools/testing/selftests/kvm/arm64/vgic_init.c
526
v.vm = vm_create(nr_vcpus);
tools/testing/selftests/kvm/arm64/vgic_init.c
528
vm_vcpu_add(v.vm, vcpuids[i], guest_code);
tools/testing/selftests/kvm/arm64/vgic_init.c
530
v.gic_fd = kvm_create_device(v.vm, KVM_DEV_TYPE_ARM_VGIC_V3);
tools/testing/selftests/kvm/arm64/vgic_init.c
532
return v;
tools/testing/selftests/kvm/arm64/vgic_init.c
548
struct vm_gic v;
tools/testing/selftests/kvm/arm64/vgic_init.c
551
v = vm_gic_v3_create_with_vcpuids(ARRAY_SIZE(vcpuids), vcpuids);
tools/testing/selftests/kvm/arm64/vgic_init.c
553
kvm_device_attr_set(v.gic_fd, KVM_DEV_ARM_VGIC_GRP_CTRL,
tools/testing/selftests/kvm/arm64/vgic_init.c
557
kvm_device_attr_set(v.gic_fd, KVM_DEV_ARM_VGIC_GRP_ADDR,
tools/testing/selftests/kvm/arm64/vgic_init.c
561
kvm_device_attr_set(v.gic_fd, KVM_DEV_ARM_VGIC_GRP_ADDR,
tools/testing/selftests/kvm/arm64/vgic_init.c
565
kvm_device_attr_set(v.gic_fd, KVM_DEV_ARM_VGIC_GRP_ADDR,
tools/testing/selftests/kvm/arm64/vgic_init.c
568
v3_redist_reg_get(v.gic_fd, 0, GICR_TYPER, 0x000, "read typer of rdist #0");
tools/testing/selftests/kvm/arm64/vgic_init.c
569
v3_redist_reg_get(v.gic_fd, 1, GICR_TYPER, 0x100, "read typer of rdist #1");
tools/testing/selftests/kvm/arm64/vgic_init.c
570
v3_redist_reg_get(v.gic_fd, 2, GICR_TYPER, 0x200, "read typer of rdist #2");
tools/testing/selftests/kvm/arm64/vgic_init.c
571
v3_redist_reg_get(v.gic_fd, 3, GICR_TYPER, 0x310, "read typer of rdist #3");
tools/testing/selftests/kvm/arm64/vgic_init.c
572
v3_redist_reg_get(v.gic_fd, 5, GICR_TYPER, 0x500, "read typer of rdist #5");
tools/testing/selftests/kvm/arm64/vgic_init.c
573
v3_redist_reg_get(v.gic_fd, 4, GICR_TYPER, 0x410, "read typer of rdist #4");
tools/testing/selftests/kvm/arm64/vgic_init.c
575
vm_gic_destroy(&v);
tools/testing/selftests/kvm/arm64/vgic_init.c
582
struct vm_gic v;
tools/testing/selftests/kvm/arm64/vgic_init.c
585
v = vm_gic_v3_create_with_vcpuids(ARRAY_SIZE(vcpuids), vcpuids);
tools/testing/selftests/kvm/arm64/vgic_init.c
587
kvm_device_attr_set(v.gic_fd, KVM_DEV_ARM_VGIC_GRP_CTRL,
tools/testing/selftests/kvm/arm64/vgic_init.c
591
kvm_device_attr_set(v.gic_fd, KVM_DEV_ARM_VGIC_GRP_ADDR,
tools/testing/selftests/kvm/arm64/vgic_init.c
594
v3_redist_reg_get(v.gic_fd, 0, GICR_TYPER, 0x000, "read typer of rdist #0");
tools/testing/selftests/kvm/arm64/vgic_init.c
595
v3_redist_reg_get(v.gic_fd, 3, GICR_TYPER, 0x300, "read typer of rdist #1");
tools/testing/selftests/kvm/arm64/vgic_init.c
596
v3_redist_reg_get(v.gic_fd, 5, GICR_TYPER, 0x500, "read typer of rdist #2");
tools/testing/selftests/kvm/arm64/vgic_init.c
597
v3_redist_reg_get(v.gic_fd, 1, GICR_TYPER, 0x100, "read typer of rdist #3");
tools/testing/selftests/kvm/arm64/vgic_init.c
598
v3_redist_reg_get(v.gic_fd, 2, GICR_TYPER, 0x210, "read typer of rdist #3");
tools/testing/selftests/kvm/arm64/vgic_init.c
600
vm_gic_destroy(&v);
tools/testing/selftests/kvm/arm64/vgic_init.c
607
struct vm_gic v;
tools/testing/selftests/kvm/arm64/vgic_init.c
611
v = vm_gic_create_with_vcpus(KVM_DEV_TYPE_ARM_VGIC_V3, 1, vcpus);
tools/testing/selftests/kvm/arm64/vgic_init.c
615
kvm_device_attr_set(v.gic_fd, KVM_DEV_ARM_VGIC_GRP_ADDR,
tools/testing/selftests/kvm/arm64/vgic_init.c
619
kvm_device_attr_set(v.gic_fd, KVM_DEV_ARM_VGIC_GRP_ADDR,
tools/testing/selftests/kvm/arm64/vgic_init.c
624
vcpus[i] = vm_vcpu_add(v.vm, i, guest_code);
tools/testing/selftests/kvm/arm64/vgic_init.c
626
kvm_device_attr_set(v.gic_fd, KVM_DEV_ARM_VGIC_GRP_CTRL,
tools/testing/selftests/kvm/arm64/vgic_init.c
634
vm_gic_destroy(&v);
tools/testing/selftests/kvm/arm64/vgic_init.c
640
struct vm_gic v;
tools/testing/selftests/kvm/arm64/vgic_init.c
644
v = vm_gic_create_with_vcpus(KVM_DEV_TYPE_ARM_VGIC_V3, NR_VCPUS, vcpus);
tools/testing/selftests/kvm/arm64/vgic_init.c
645
its_fd = kvm_create_device(v.vm, KVM_DEV_TYPE_ARM_VGIC_ITS);
tools/testing/selftests/kvm/arm64/vgic_init.c
676
vm_gic_destroy(&v);
tools/testing/selftests/kvm/arm64/vgic_init.c
723
struct vm_gic v;
tools/testing/selftests/kvm/arm64/vgic_init.c
727
v.vm = vm_create_with_vcpus(NR_VCPUS, guest_code, vcpus);
tools/testing/selftests/kvm/arm64/vgic_init.c
730
ret = __kvm_test_create_device(v.vm, 0);
tools/testing/selftests/kvm/arm64/vgic_init.c
734
ret = __kvm_test_create_device(v.vm, gic_dev_type);
tools/testing/selftests/kvm/arm64/vgic_init.c
737
v.gic_fd = kvm_create_device(v.vm, gic_dev_type);
tools/testing/selftests/kvm/arm64/vgic_init.c
739
ret = __kvm_create_device(v.vm, gic_dev_type);
tools/testing/selftests/kvm/arm64/vgic_init.c
746
if (!__kvm_test_create_device(v.vm, other)) {
tools/testing/selftests/kvm/arm64/vgic_init.c
747
ret = __kvm_create_device(v.vm, other);
tools/testing/selftests/kvm/arm64/vgic_init.c
752
vm_gic_destroy(&v);
tools/testing/selftests/kvm/arm64/vgic_init.c
78
struct vm_gic v;
tools/testing/selftests/kvm/arm64/vgic_init.c
80
v.gic_dev_type = gic_dev_type;
tools/testing/selftests/kvm/arm64/vgic_init.c
81
v.vm = vm_create_with_vcpus(nr_vcpus, guest_code, vcpus);
tools/testing/selftests/kvm/arm64/vgic_init.c
82
v.gic_fd = kvm_create_device(v.vm, gic_dev_type);
tools/testing/selftests/kvm/arm64/vgic_init.c
84
return v;
tools/testing/selftests/kvm/arm64/vgic_init.c
89
struct vm_gic v;
tools/testing/selftests/kvm/arm64/vgic_init.c
91
v.gic_dev_type = gic_dev_type;
tools/testing/selftests/kvm/arm64/vgic_init.c
92
v.vm = vm_create_barebones();
tools/testing/selftests/kvm/arm64/vgic_init.c
93
v.gic_fd = kvm_create_device(v.vm, gic_dev_type);
tools/testing/selftests/kvm/arm64/vgic_init.c
95
return v;
tools/testing/selftests/kvm/arm64/vgic_init.c
99
static void vm_gic_destroy(struct vm_gic *v)
tools/testing/selftests/kvm/include/arm64/processor.h
165
#define VECTOR_IS_SYNC(v) ((v) == VECTOR_SYNC_CURRENT_SP0 || \
tools/testing/selftests/kvm/include/arm64/processor.h
166
(v) == VECTOR_SYNC_CURRENT || \
tools/testing/selftests/kvm/include/arm64/processor.h
167
(v) == VECTOR_SYNC_LOWER_64 || \
tools/testing/selftests/kvm/include/arm64/processor.h
168
(v) == VECTOR_SYNC_LOWER_32)
tools/testing/selftests/kvm/include/arm64/processor.h
199
#define __iormb(v) \
tools/testing/selftests/kvm/include/arm64/processor.h
213
: "=r" (tmp) : "r" ((unsigned long)(v)) \
tools/testing/selftests/kvm/include/arm64/processor.h
241
#define writel_relaxed(v,c) ((void)__raw_writel((__force u32)cpu_to_le32(v),(c)))
tools/testing/selftests/kvm/include/arm64/processor.h
243
#define writeq_relaxed(v,c) ((void)__raw_writeq((__force u64)cpu_to_le64(v),(c)))
tools/testing/selftests/kvm/include/arm64/processor.h
246
#define writel(v,c) ({ __iowmb(); writel_relaxed((v),(c));})
tools/testing/selftests/kvm/include/arm64/processor.h
248
#define writeq(v,c) ({ __iowmb(); writeq_relaxed((v),(c));})
tools/testing/selftests/kvm/include/arm64/spinlock.h
7
int v;
tools/testing/selftests/kvm/include/kvm_util.h
1284
static inline uint64_t vm_page_align(struct kvm_vm *vm, uint64_t v)
tools/testing/selftests/kvm/include/kvm_util.h
1286
return (v + vm->page_size - 1) & ~(vm->page_size - 1);
tools/testing/selftests/kvm/include/loongarch/processor.h
142
#define csr_write(v, csr) \
tools/testing/selftests/kvm/include/loongarch/processor.h
144
register unsigned long __v = v; \
tools/testing/selftests/kvm/include/x86/apic.h
75
#define APIC_VECTOR_TO_BIT_NUMBER(v) ((unsigned int)(v) % 32)
tools/testing/selftests/kvm/include/x86/apic.h
76
#define APIC_VECTOR_TO_REG_OFFSET(v) ((unsigned int)(v) / 32 * 0x10)
tools/testing/selftests/kvm/include/x86/processor.h
1164
uint64_t r, v = val; \
tools/testing/selftests/kvm/include/x86/processor.h
1166
TEST_ASSERT_MSR(_vcpu_set_msr(vcpu, msr, v) == 1, \
tools/testing/selftests/kvm/include/x86/processor.h
1167
"KVM_SET_MSRS failed on %s, value = 0x%lx", msr, #msr, v); \
tools/testing/selftests/kvm/include/x86/processor.h
1171
TEST_ASSERT_MSR(r == v, "Set %s to '0x%lx', got back '0x%lx'", msr, #msr, v, r);\
tools/testing/selftests/kvm/include/x86/processor.h
1253
#define KVM_ASM_SAFE_OUTPUTS(v, ec) [vector] "=qm"(v), [error_code] "=rm"(ec)
tools/testing/selftests/kvm/lib/arm64/spinlock.c
20
: "r" (&lock->v)
tools/testing/selftests/kvm/lib/arm64/spinlock.c
26
asm volatile("stlr wzr, [%0]\n" : : "r" (&lock->v) : "memory");
tools/testing/selftests/kvm/lib/guest_sprintf.c
6
#define APPEND_BUFFER_SAFE(str, end, v) \
tools/testing/selftests/kvm/lib/guest_sprintf.c
9
*str++ = (v); \
tools/testing/selftests/kvm/lib/x86/processor.c
33
#define VEC_STR(v) case v##_VECTOR: return "#" #v
tools/testing/selftests/kvm/riscv/ebreak_test.c
11
#define LABEL_ADDRESS(v) ((uint64_t)&(v))
tools/testing/selftests/kvm/riscv/get-reg-list.c
1159
KVM_ISA_EXT_SUBLIST_CONFIG(v, V);
tools/testing/selftests/kvm/s390/memop.c
218
#define GADDR_V(v) ._gaddr_v = 1, .gaddr_v = ((uintptr_t)v)
tools/testing/selftests/kvm/x86/debug_regs.c
70
#define CAST_TO_RIP(v) ((unsigned long long)&(v))
tools/testing/selftests/kvm/x86/fastops_test.c
113
uint8_t v, ex_v; \
tools/testing/selftests/kvm/x86/fastops_test.c
116
v = guest_execute_fastop_div(KVM_ASM_SAFE_FEP, insn, a, d, rm, flags); \
tools/testing/selftests/kvm/x86/fastops_test.c
118
GUEST_ASSERT_EQ(v, ex_v); \
tools/testing/selftests/kvm/x86/fastops_test.c
119
__GUEST_ASSERT(v == ex_v, \
tools/testing/selftests/kvm/x86/fastops_test.c
121
ex_v, insn, (uint64_t)_a, (uint64_t)_d, (uint64_t)rm, v); \
tools/testing/selftests/kvm/x86/fastops_test.c
126
__GUEST_ASSERT(v || ex_v || (flags == ex_flags), \
tools/testing/selftests/kvm/x86/pmu_counters_test.c
590
uint8_t v, j;
tools/testing/selftests/kvm/x86/pmu_counters_test.c
648
for (v = 0; v <= max_pmu_version; v++) {
tools/testing/selftests/kvm/x86/pmu_counters_test.c
654
v, perf_caps[i]);
tools/testing/selftests/kvm/x86/pmu_counters_test.c
665
test_arch_events(v, perf_caps[i], j, unavailable_masks[k]);
tools/testing/selftests/kvm/x86/pmu_counters_test.c
669
v, perf_caps[i]);
tools/testing/selftests/kvm/x86/pmu_counters_test.c
671
test_gp_counters(v, perf_caps[i], j);
tools/testing/selftests/kvm/x86/pmu_counters_test.c
674
v, perf_caps[i]);
tools/testing/selftests/kvm/x86/pmu_counters_test.c
677
test_fixed_counters(v, perf_caps[i], j, k);
tools/testing/selftests/kvm/x86/pmu_event_filter_test.c
432
: [v]"+m"(val) :: "eax");
tools/testing/selftests/kvm/x86/pmu_event_filter_test.c
80
uint64_t v = rdmsr(msr) ^ bits_to_flip;
tools/testing/selftests/kvm/x86/pmu_event_filter_test.c
82
wrmsr(msr, v);
tools/testing/selftests/kvm/x86/pmu_event_filter_test.c
83
if (rdmsr(msr) != v)
tools/testing/selftests/kvm/x86/pmu_event_filter_test.c
86
v ^= bits_to_flip;
tools/testing/selftests/kvm/x86/pmu_event_filter_test.c
87
wrmsr(msr, v);
tools/testing/selftests/kvm/x86/pmu_event_filter_test.c
88
if (rdmsr(msr) != v)
tools/testing/selftests/livepatch/test_modules/test_klp_atomic_replace.c
15
static int livepatch_meminfo_proc_show(struct seq_file *m, void *v)
tools/testing/selftests/livepatch/test_modules/test_klp_livepatch.c
11
static int livepatch_cmdline_proc_show(struct seq_file *m, void *v)
tools/testing/selftests/mm/thuge-gen.c
56
int ilog2(unsigned long v)
tools/testing/selftests/mm/thuge-gen.c
59
while ((1UL << l) < v)
tools/testing/selftests/mm/uffd-unit-tests.c
535
uint8_t v = *(uint8_t *)(p + (i * gopts->page_size) + j);
tools/testing/selftests/mm/uffd-unit-tests.c
536
if (v != expected_byte)
tools/testing/selftests/net/icmp_rfc4884.c
592
const FIXTURE_VARIANT(rfc4884) *v)
tools/testing/selftests/net/icmp_rfc4884.c
620
if (cmsg->cmsg_level != v->info.level ||
tools/testing/selftests/net/icmp_rfc4884.c
621
cmsg->cmsg_type != v->info.opt1) {
tools/testing/selftests/net/icmp_rfc4884.c
630
expected_invalid = v->bad_csum || v->bad_len;
tools/testing/selftests/net/icmp_rfc4884.c
637
(v->with_ext && v->payload_len >= v->info.min_payload) ?
tools/testing/selftests/net/icmp_rfc4884.c
638
v->payload_len : 0;
tools/testing/selftests/net/icmp_rfc4884.c
649
const typeof(variant) v = variant;
tools/testing/selftests/net/icmp_rfc4884.c
656
dgram = socket(v->info.domain, SOCK_DGRAM, 0);
tools/testing/selftests/net/icmp_rfc4884.c
659
err = bind_and_setsockopt(dgram, &v->info);
tools/testing/selftests/net/icmp_rfc4884.c
662
raw = socket(v->info.domain, SOCK_RAW, v->info.proto);
tools/testing/selftests/net/icmp_rfc4884.c
665
len = v->info.build_func(pkt, sizeof(pkt), v->with_ext, v->payload_len,
tools/testing/selftests/net/icmp_rfc4884.c
666
v->bad_csum, v->bad_len, v->smaller_len);
tools/testing/selftests/net/icmp_rfc4884.c
669
set_addr(&addr, v->info.domain, 0);
tools/testing/selftests/net/icmp_rfc4884.c
673
check_rfc4884_offset(_metadata, dgram, v);
tools/testing/selftests/net/netfilter/audit_logread.c
111
v = strtok(NULL, " ");
tools/testing/selftests/net/netfilter/audit_logread.c
121
*strchrnul(v, ':') = '\0';
tools/testing/selftests/net/netfilter/audit_logread.c
123
printf("%s%s=%s", sep, k, v);
tools/testing/selftests/net/netfilter/audit_logread.c
99
char *k, *v;
tools/testing/selftests/net/tcp_port_share.c
137
const typeof(variant) v = variant;
tools/testing/selftests/net/tcp_port_share.c
142
ln = socket(v->domain, SOCK_STREAM, 0);
tools/testing/selftests/net/tcp_port_share.c
146
make_inet_addr(v->domain, v->dst_ip, DST_PORT, &addr);
tools/testing/selftests/net/tcp_port_share.c
151
c1 = socket(v->domain, SOCK_STREAM, 0);
tools/testing/selftests/net/tcp_port_share.c
155
make_inet_addr(v->domain, v->src1_ip, 0, &addr);
tools/testing/selftests/net/tcp_port_share.c
158
make_inet_addr(v->domain, v->dst_ip, DST_PORT, &addr);
tools/testing/selftests/net/tcp_port_share.c
163
pb = socket(v->domain, SOCK_STREAM, 0);
tools/testing/selftests/net/tcp_port_share.c
167
make_inet_addr(v->domain, v->bind_ip, SRC_PORT, &addr);
tools/testing/selftests/net/tcp_port_share.c
171
c2 = socket(v->domain, SOCK_STREAM, 0);
tools/testing/selftests/net/tcp_port_share.c
175
make_inet_addr(v->domain, v->src2_ip, 0, &addr);
tools/testing/selftests/net/tcp_port_share.c
178
make_inet_addr(v->domain, v->dst_ip, DST_PORT, &addr);
tools/testing/selftests/net/tcp_port_share.c
199
const typeof(variant) v = variant;
tools/testing/selftests/net/tcp_port_share.c
204
ln = socket(v->domain, SOCK_STREAM, 0);
tools/testing/selftests/net/tcp_port_share.c
208
make_inet_addr(v->domain, v->dst_ip, DST_PORT, &addr);
tools/testing/selftests/net/tcp_port_share.c
213
c1 = socket(v->domain, SOCK_STREAM, 0);
tools/testing/selftests/net/tcp_port_share.c
217
make_inet_addr(v->domain, v->src1_ip, 0, &addr);
tools/testing/selftests/net/tcp_port_share.c
220
make_inet_addr(v->domain, v->dst_ip, DST_PORT, &addr);
tools/testing/selftests/net/tcp_port_share.c
228
make_inet_addr(v->domain, v->bind_ip, SRC_PORT, &addr);
tools/testing/selftests/net/tcp_port_share.c
232
pb = socket(v->domain, SOCK_STREAM, 0);
tools/testing/selftests/net/tcp_port_share.c
236
make_inet_addr(v->domain, v->bind_ip, SRC_PORT, &addr);
tools/testing/selftests/net/tcp_port_share.c
242
c2 = socket(v->domain, SOCK_STREAM, 0);
tools/testing/selftests/net/tcp_port_share.c
246
make_inet_addr(v->domain, v->src2_ip, 0, &addr);
tools/testing/selftests/net/tcp_port_share.c
249
make_inet_addr(v->domain, v->dst_ip, DST_PORT, &addr);
tools/testing/selftests/powerpc/benchmarks/null_syscall.c
70
unsigned long v;
tools/testing/selftests/powerpc/benchmarks/null_syscall.c
87
v = strtoull(p + 1, &end, 0);
tools/testing/selftests/powerpc/benchmarks/null_syscall.c
89
timebase_frequency = v;
tools/testing/selftests/powerpc/include/reg.h
15
#define mtspr(rn, v) asm volatile("mtspr " _str(rn) ",%0" : \
tools/testing/selftests/powerpc/include/reg.h
16
: "r" ((unsigned long)(v)) \
tools/testing/selftests/powerpc/include/reg.h
71
#define set_amr(v) asm volatile("isync;" \
tools/testing/selftests/powerpc/include/reg.h
74
: "r" ((unsigned long)(v)) \
tools/testing/selftests/powerpc/security/entry_flush.c
25
struct perf_event_read v;
tools/testing/selftests/powerpc/security/entry_flush.c
79
FAIL_IF(read(fd, &v, sizeof(v)) != sizeof(v));
tools/testing/selftests/powerpc/security/entry_flush.c
81
if (entry_flush && v.l1d_misses >= l1d_misses_expected)
tools/testing/selftests/powerpc/security/entry_flush.c
83
else if (!entry_flush && v.l1d_misses < (l1d_misses_expected / 2))
tools/testing/selftests/powerpc/security/entry_flush.c
86
l1d_misses_total += v.l1d_misses;
tools/testing/selftests/powerpc/security/rfi_flush.c
25
struct perf_event_read v;
tools/testing/selftests/powerpc/security/rfi_flush.c
80
FAIL_IF(read(fd, &v, sizeof(v)) != sizeof(v));
tools/testing/selftests/powerpc/security/rfi_flush.c
82
if (rfi_flush && v.l1d_misses >= l1d_misses_expected)
tools/testing/selftests/powerpc/security/rfi_flush.c
84
else if (!rfi_flush && v.l1d_misses < (l1d_misses_expected / 2))
tools/testing/selftests/powerpc/security/rfi_flush.c
87
l1d_misses_total += v.l1d_misses;
tools/testing/selftests/powerpc/security/uaccess_flush.c
100
l1d_misses_total += v.l1d_misses;
tools/testing/selftests/powerpc/security/uaccess_flush.c
26
struct perf_event_read v;
tools/testing/selftests/powerpc/security/uaccess_flush.c
93
FAIL_IF(read(fd, &v, sizeof(v)) != sizeof(v));
tools/testing/selftests/powerpc/security/uaccess_flush.c
95
if (uaccess_flush && v.l1d_misses >= l1d_misses_expected)
tools/testing/selftests/powerpc/security/uaccess_flush.c
97
else if (!uaccess_flush && v.l1d_misses < (l1d_misses_expected / 2))
tools/testing/selftests/rseq/basic_percpu_ops_test.c
107
assert(lock->c[cpu].v == 1);
tools/testing/selftests/rseq/basic_percpu_ops_test.c
112
rseq_smp_store_release(&lock->c[cpu].v, 0);
tools/testing/selftests/rseq/basic_percpu_ops_test.c
52
intptr_t v;
tools/testing/selftests/rseq/basic_percpu_ops_test.c
92
&lock->c[cpu].v, 0, 1, cpu);
tools/testing/selftests/rseq/param_test.c
360
intptr_t v;
tools/testing/selftests/rseq/param_test.c
453
&lock->c[cpu].v,
tools/testing/selftests/rseq/param_test.c
469
assert(lock->c[cpu].v == 1);
tools/testing/selftests/rseq/param_test.c
474
rseq_smp_store_release(&lock->c[cpu].v, 0);
tools/testing/selftests/rseq/rseq-arm-bits.h
122
[v] "m" (*v),
tools/testing/selftests/rseq/rseq-arm-bits.h
14
int RSEQ_TEMPLATE_IDENTIFIER(rseq_cmpeqv_storev)(intptr_t *v, intptr_t expect, intptr_t newv, int cpu)
tools/testing/selftests/rseq/rseq-arm-bits.h
154
int RSEQ_TEMPLATE_IDENTIFIER(rseq_addv)(intptr_t *v, intptr_t count, int cpu)
tools/testing/selftests/rseq/rseq-arm-bits.h
183
[v] "m" (*v),
tools/testing/selftests/rseq/rseq-arm-bits.h
207
int RSEQ_TEMPLATE_IDENTIFIER(rseq_cmpeqv_cmpeqv_storev)(intptr_t *v, intptr_t expect,
tools/testing/selftests/rseq/rseq-arm-bits.h
257
[v] "m" (*v),
tools/testing/selftests/rseq/rseq-arm-bits.h
297
int RSEQ_TEMPLATE_IDENTIFIER(rseq_cmpeqv_trystorev_storev)(intptr_t *v, intptr_t expect,
tools/testing/selftests/rseq/rseq-arm-bits.h
345
[v] "m" (*v),
tools/testing/selftests/rseq/rseq-arm-bits.h
377
int RSEQ_TEMPLATE_IDENTIFIER(rseq_cmpeqv_trymemcpy_storev)(intptr_t *v, intptr_t expect,
tools/testing/selftests/rseq/rseq-arm-bits.h
465
[v] "m" (*v),
tools/testing/selftests/rseq/rseq-arm-bits.h
50
[v] "m" (*v),
tools/testing/selftests/rseq/rseq-arm-bits.h
81
int RSEQ_TEMPLATE_IDENTIFIER(rseq_cmpnev_storeoffp_load)(intptr_t *v, intptr_t expectnot,
tools/testing/selftests/rseq/rseq-arm.h
76
#define rseq_smp_store_release(p, v) \
tools/testing/selftests/rseq/rseq-arm.h
79
RSEQ_WRITE_ONCE(*(p), v); \
tools/testing/selftests/rseq/rseq-arm64-bits.h
103
[v] "Qo" (*v),
tools/testing/selftests/rseq/rseq-arm64-bits.h
134
int RSEQ_TEMPLATE_IDENTIFIER(rseq_addv)(intptr_t *v, intptr_t count, int cpu)
tools/testing/selftests/rseq/rseq-arm64-bits.h
149
RSEQ_ASM_OP_R_LOAD(v)
tools/testing/selftests/rseq/rseq-arm64-bits.h
15
int RSEQ_TEMPLATE_IDENTIFIER(rseq_cmpeqv_storev)(intptr_t *v, intptr_t expect, intptr_t newv, int cpu)
tools/testing/selftests/rseq/rseq-arm64-bits.h
151
RSEQ_ASM_OP_R_FINAL_STORE(v, 3)
tools/testing/selftests/rseq/rseq-arm64-bits.h
158
[v] "Qo" (*v),
tools/testing/selftests/rseq/rseq-arm64-bits.h
181
int RSEQ_TEMPLATE_IDENTIFIER(rseq_cmpeqv_cmpeqv_storev)(intptr_t *v, intptr_t expect,
tools/testing/selftests/rseq/rseq-arm64-bits.h
198
RSEQ_ASM_OP_CMPEQ(v, expect, %l[cmpfail])
tools/testing/selftests/rseq/rseq-arm64-bits.h
204
RSEQ_ASM_OP_CMPEQ(v, expect, %l[error2])
tools/testing/selftests/rseq/rseq-arm64-bits.h
207
RSEQ_ASM_OP_FINAL_STORE(newv, v, 3)
tools/testing/selftests/rseq/rseq-arm64-bits.h
214
[v] "Qo" (*v),
tools/testing/selftests/rseq/rseq-arm64-bits.h
255
int RSEQ_TEMPLATE_IDENTIFIER(rseq_cmpeqv_trystorev_storev)(intptr_t *v, intptr_t expect,
tools/testing/selftests/rseq/rseq-arm64-bits.h
271
RSEQ_ASM_OP_CMPEQ(v, expect, %l[cmpfail])
tools/testing/selftests/rseq/rseq-arm64-bits.h
275
RSEQ_ASM_OP_CMPEQ(v, expect, %l[error2])
tools/testing/selftests/rseq/rseq-arm64-bits.h
280
RSEQ_ASM_OP_FINAL_STORE_RELEASE(newv, v, 3)
tools/testing/selftests/rseq/rseq-arm64-bits.h
282
RSEQ_ASM_OP_FINAL_STORE(newv, v, 3)
tools/testing/selftests/rseq/rseq-arm64-bits.h
29
RSEQ_ASM_OP_CMPEQ(v, expect, %l[cmpfail])
tools/testing/selftests/rseq/rseq-arm64-bits.h
291
[v] "Qo" (*v),
tools/testing/selftests/rseq/rseq-arm64-bits.h
322
int RSEQ_TEMPLATE_IDENTIFIER(rseq_cmpeqv_trymemcpy_storev)(intptr_t *v, intptr_t expect,
tools/testing/selftests/rseq/rseq-arm64-bits.h
33
RSEQ_ASM_OP_CMPEQ(v, expect, %l[error2])
tools/testing/selftests/rseq/rseq-arm64-bits.h
338
RSEQ_ASM_OP_CMPEQ(v, expect, %l[cmpfail])
tools/testing/selftests/rseq/rseq-arm64-bits.h
342
RSEQ_ASM_OP_CMPEQ(v, expect, %l[error2])
tools/testing/selftests/rseq/rseq-arm64-bits.h
347
RSEQ_ASM_OP_FINAL_STORE_RELEASE(newv, v, 3)
tools/testing/selftests/rseq/rseq-arm64-bits.h
349
RSEQ_ASM_OP_FINAL_STORE(newv, v, 3)
tools/testing/selftests/rseq/rseq-arm64-bits.h
35
RSEQ_ASM_OP_FINAL_STORE(newv, v, 3)
tools/testing/selftests/rseq/rseq-arm64-bits.h
358
[v] "Qo" (*v),
tools/testing/selftests/rseq/rseq-arm64-bits.h
42
[v] "Qo" (*v),
tools/testing/selftests/rseq/rseq-arm64-bits.h
72
int RSEQ_TEMPLATE_IDENTIFIER(rseq_cmpnev_storeoffp_load)(intptr_t *v, intptr_t expectnot,
tools/testing/selftests/rseq/rseq-arm64-bits.h
87
RSEQ_ASM_OP_CMPNE(v, expectnot, %l[cmpfail])
tools/testing/selftests/rseq/rseq-arm64-bits.h
91
RSEQ_ASM_OP_CMPNE(v, expectnot, %l[error2])
tools/testing/selftests/rseq/rseq-arm64-bits.h
93
RSEQ_ASM_OP_R_LOAD(v)
tools/testing/selftests/rseq/rseq-arm64-bits.h
96
RSEQ_ASM_OP_R_FINAL_STORE(v, 3)
tools/testing/selftests/rseq/rseq-arm64.h
58
#define rseq_smp_store_release(p, v) \
tools/testing/selftests/rseq/rseq-arm64.h
61
{ .__val = (rseq_unqual_scalar_typeof(*(p))) (v) }; \
tools/testing/selftests/rseq/rseq-mips-bits.h
113
[v] "m" (*v),
tools/testing/selftests/rseq/rseq-mips-bits.h
14
int RSEQ_TEMPLATE_IDENTIFIER(rseq_cmpeqv_storev)(intptr_t *v, intptr_t expect, intptr_t newv, int cpu)
tools/testing/selftests/rseq/rseq-mips-bits.h
140
int RSEQ_TEMPLATE_IDENTIFIER(rseq_addv)(intptr_t *v, intptr_t count, int cpu)
tools/testing/selftests/rseq/rseq-mips-bits.h
169
[v] "m" (*v),
tools/testing/selftests/rseq/rseq-mips-bits.h
190
int RSEQ_TEMPLATE_IDENTIFIER(rseq_cmpeqv_cmpeqv_storev)(intptr_t *v, intptr_t expect,
tools/testing/selftests/rseq/rseq-mips-bits.h
236
[v] "m" (*v),
tools/testing/selftests/rseq/rseq-mips-bits.h
270
int RSEQ_TEMPLATE_IDENTIFIER(rseq_cmpeqv_trystorev_storev)(intptr_t *v, intptr_t expect,
tools/testing/selftests/rseq/rseq-mips-bits.h
316
[v] "m" (*v),
tools/testing/selftests/rseq/rseq-mips-bits.h
342
int RSEQ_TEMPLATE_IDENTIFIER(rseq_cmpeqv_trymemcpy_storev)(intptr_t *v, intptr_t expect,
tools/testing/selftests/rseq/rseq-mips-bits.h
427
[v] "m" (*v),
tools/testing/selftests/rseq/rseq-mips-bits.h
48
[v] "m" (*v),
tools/testing/selftests/rseq/rseq-mips-bits.h
74
int RSEQ_TEMPLATE_IDENTIFIER(rseq_cmpnev_storeoffp_load)(intptr_t *v, intptr_t expectnot,
tools/testing/selftests/rseq/rseq-mips.h
55
#define rseq_smp_store_release(p, v) \
tools/testing/selftests/rseq/rseq-mips.h
58
RSEQ_WRITE_ONCE(*(p), v); \
tools/testing/selftests/rseq/rseq-or1k-bits.h
120
int RSEQ_TEMPLATE_IDENTIFIER(rseq_addv)(intptr_t *v, intptr_t count, int cpu)
tools/testing/selftests/rseq/rseq-or1k-bits.h
134
RSEQ_ASM_OP_R_LOAD(v)
tools/testing/selftests/rseq/rseq-or1k-bits.h
136
RSEQ_ASM_OP_R_FINAL_STORE(v, 3)
tools/testing/selftests/rseq/rseq-or1k-bits.h
143
[v] "m" (*v),
tools/testing/selftests/rseq/rseq-or1k-bits.h
164
int RSEQ_TEMPLATE_IDENTIFIER(rseq_cmpeqv_cmpeqv_storev)(intptr_t *v, intptr_t expect,
tools/testing/selftests/rseq/rseq-or1k-bits.h
180
RSEQ_ASM_OP_CMPEQ(v, expect, "%l[cmpfail]")
tools/testing/selftests/rseq/rseq-or1k-bits.h
186
RSEQ_ASM_OP_CMPEQ(v, expect, "%l[error2]")
tools/testing/selftests/rseq/rseq-or1k-bits.h
189
RSEQ_ASM_OP_FINAL_STORE(v, newv, 3)
tools/testing/selftests/rseq/rseq-or1k-bits.h
196
[v] "m" (*v),
tools/testing/selftests/rseq/rseq-or1k-bits.h
23
RSEQ_ASM_OP_CMPEQ(v, expect, "%l[cmpfail]")
tools/testing/selftests/rseq/rseq-or1k-bits.h
27
RSEQ_ASM_OP_CMPEQ(v, expect, "%l[error2]")
tools/testing/selftests/rseq/rseq-or1k-bits.h
283
int RSEQ_TEMPLATE_IDENTIFIER(rseq_cmpeqv_trystorev_storev)(intptr_t *v, intptr_t expect,
tools/testing/selftests/rseq/rseq-or1k-bits.h
29
RSEQ_ASM_OP_FINAL_STORE(v, newv, 3)
tools/testing/selftests/rseq/rseq-or1k-bits.h
298
RSEQ_ASM_OP_CMPEQ(v, expect, "%l[cmpfail]")
tools/testing/selftests/rseq/rseq-or1k-bits.h
302
RSEQ_ASM_OP_CMPEQ(v, expect, "%l[error2]")
tools/testing/selftests/rseq/rseq-or1k-bits.h
307
RSEQ_ASM_OP_FINAL_STORE_RELEASE(v, newv, 3)
tools/testing/selftests/rseq/rseq-or1k-bits.h
309
RSEQ_ASM_OP_FINAL_STORE(v, newv, 3)
tools/testing/selftests/rseq/rseq-or1k-bits.h
318
[v] "m" (*v),
tools/testing/selftests/rseq/rseq-or1k-bits.h
346
int RSEQ_TEMPLATE_IDENTIFIER(rseq_cmpeqv_trymemcpy_storev)(intptr_t *v, intptr_t expect,
tools/testing/selftests/rseq/rseq-or1k-bits.h
36
[v] "m" (*v),
tools/testing/selftests/rseq/rseq-or1k-bits.h
360
RSEQ_ASM_OP_CMPEQ(v, expect, "%l[cmpfail]")
tools/testing/selftests/rseq/rseq-or1k-bits.h
364
RSEQ_ASM_OP_CMPEQ(v, expect, "%l[error2]")
tools/testing/selftests/rseq/rseq-or1k-bits.h
369
RSEQ_ASM_OP_FINAL_STORE_RELEASE(v, newv, 3)
tools/testing/selftests/rseq/rseq-or1k-bits.h
371
RSEQ_ASM_OP_FINAL_STORE(v, newv, 3)
tools/testing/selftests/rseq/rseq-or1k-bits.h
380
[v] "m" (*v),
tools/testing/selftests/rseq/rseq-or1k-bits.h
63
int RSEQ_TEMPLATE_IDENTIFIER(rseq_cmpnev_storeoffp_load)(intptr_t *v, intptr_t expectnot,
tools/testing/selftests/rseq/rseq-or1k-bits.h
77
RSEQ_ASM_OP_CMPNE(v, expectnot, "%l[cmpfail]")
tools/testing/selftests/rseq/rseq-or1k-bits.h
81
RSEQ_ASM_OP_CMPNE(v, expectnot, "%l[error2]")
tools/testing/selftests/rseq/rseq-or1k-bits.h
83
RSEQ_ASM_OP_R_LOAD(v)
tools/testing/selftests/rseq/rseq-or1k-bits.h
86
RSEQ_ASM_OP_R_FINAL_STORE(v, 3)
tools/testing/selftests/rseq/rseq-or1k-bits.h
9
int RSEQ_TEMPLATE_IDENTIFIER(rseq_cmpeqv_storev)(intptr_t *v, intptr_t expect, intptr_t newv,
tools/testing/selftests/rseq/rseq-or1k-bits.h
93
[v] "m" (*v),
tools/testing/selftests/rseq/rseq-or1k.h
25
#define rseq_smp_store_release(p, v) \
tools/testing/selftests/rseq/rseq-or1k.h
28
RSEQ_WRITE_ONCE(*(p), v); \
tools/testing/selftests/rseq/rseq-ppc-bits.h
103
RSEQ_ASM_OP_CMPNE(v, expectnot, %l[error2])
tools/testing/selftests/rseq/rseq-ppc-bits.h
106
RSEQ_ASM_OP_R_LOAD(v)
tools/testing/selftests/rseq/rseq-ppc-bits.h
112
RSEQ_ASM_OP_R_FINAL_STORE(v, 2)
tools/testing/selftests/rseq/rseq-ppc-bits.h
120
[v] "m" (*v),
tools/testing/selftests/rseq/rseq-ppc-bits.h
15
int RSEQ_TEMPLATE_IDENTIFIER(rseq_cmpeqv_storev)(intptr_t *v, intptr_t expect, intptr_t newv, int cpu)
tools/testing/selftests/rseq/rseq-ppc-bits.h
152
int RSEQ_TEMPLATE_IDENTIFIER(rseq_addv)(intptr_t *v, intptr_t count, int cpu)
tools/testing/selftests/rseq/rseq-ppc-bits.h
171
RSEQ_ASM_OP_R_LOAD(v)
tools/testing/selftests/rseq/rseq-ppc-bits.h
175
RSEQ_ASM_OP_R_FINAL_STORE(v, 2)
tools/testing/selftests/rseq/rseq-ppc-bits.h
183
[v] "m" (*v),
tools/testing/selftests/rseq/rseq-ppc-bits.h
207
int RSEQ_TEMPLATE_IDENTIFIER(rseq_cmpeqv_cmpeqv_storev)(intptr_t *v, intptr_t expect,
tools/testing/selftests/rseq/rseq-ppc-bits.h
227
RSEQ_ASM_OP_CMPEQ(v, expect, %l[cmpfail])
tools/testing/selftests/rseq/rseq-ppc-bits.h
236
RSEQ_ASM_OP_CMPEQ(v, expect, %l[error2])
tools/testing/selftests/rseq/rseq-ppc-bits.h
241
RSEQ_ASM_OP_FINAL_STORE(newv, v, 2)
tools/testing/selftests/rseq/rseq-ppc-bits.h
252
[v] "m" (*v),
tools/testing/selftests/rseq/rseq-ppc-bits.h
292
int RSEQ_TEMPLATE_IDENTIFIER(rseq_cmpeqv_trystorev_storev)(intptr_t *v, intptr_t expect,
tools/testing/selftests/rseq/rseq-ppc-bits.h
311
RSEQ_ASM_OP_CMPEQ(v, expect, %l[cmpfail])
tools/testing/selftests/rseq/rseq-ppc-bits.h
317
RSEQ_ASM_OP_CMPEQ(v, expect, %l[error2])
tools/testing/selftests/rseq/rseq-ppc-bits.h
32
RSEQ_ASM_OP_CMPEQ(v, expect, %l[cmpfail])
tools/testing/selftests/rseq/rseq-ppc-bits.h
327
RSEQ_ASM_OP_FINAL_STORE(newv, v, 2)
tools/testing/selftests/rseq/rseq-ppc-bits.h
338
[v] "m" (*v),
tools/testing/selftests/rseq/rseq-ppc-bits.h
369
int RSEQ_TEMPLATE_IDENTIFIER(rseq_cmpeqv_trymemcpy_storev)(intptr_t *v, intptr_t expect,
tools/testing/selftests/rseq/rseq-ppc-bits.h
38
RSEQ_ASM_OP_CMPEQ(v, expect, %l[error2])
tools/testing/selftests/rseq/rseq-ppc-bits.h
392
RSEQ_ASM_OP_CMPEQ(v, expect, %l[cmpfail])
tools/testing/selftests/rseq/rseq-ppc-bits.h
398
RSEQ_ASM_OP_CMPEQ(v, expect, %l[error2])
tools/testing/selftests/rseq/rseq-ppc-bits.h
408
RSEQ_ASM_OP_FINAL_STORE(newv, v, 2)
tools/testing/selftests/rseq/rseq-ppc-bits.h
41
RSEQ_ASM_OP_FINAL_STORE(newv, v, 2)
tools/testing/selftests/rseq/rseq-ppc-bits.h
417
[v] "m" (*v),
tools/testing/selftests/rseq/rseq-ppc-bits.h
48
[v] "m" (*v),
tools/testing/selftests/rseq/rseq-ppc-bits.h
79
int RSEQ_TEMPLATE_IDENTIFIER(rseq_cmpnev_storeoffp_load)(intptr_t *v, intptr_t expectnot,
tools/testing/selftests/rseq/rseq-ppc-bits.h
97
RSEQ_ASM_OP_CMPNE(v, expectnot, %l[cmpfail])
tools/testing/selftests/rseq/rseq-ppc.h
33
#define rseq_smp_store_release(p, v) \
tools/testing/selftests/rseq/rseq-ppc.h
36
RSEQ_WRITE_ONCE(*(p), v); \
tools/testing/selftests/rseq/rseq-riscv-bits.h
119
int RSEQ_TEMPLATE_IDENTIFIER(rseq_addv)(intptr_t *v, intptr_t count, int cpu)
tools/testing/selftests/rseq/rseq-riscv-bits.h
133
RSEQ_ASM_OP_R_LOAD(v)
tools/testing/selftests/rseq/rseq-riscv-bits.h
135
RSEQ_ASM_OP_R_FINAL_STORE(v, 3)
tools/testing/selftests/rseq/rseq-riscv-bits.h
142
[v] "m" (*v),
tools/testing/selftests/rseq/rseq-riscv-bits.h
163
int RSEQ_TEMPLATE_IDENTIFIER(rseq_cmpeqv_cmpeqv_storev)(intptr_t *v, intptr_t expect,
tools/testing/selftests/rseq/rseq-riscv-bits.h
179
RSEQ_ASM_OP_CMPEQ(v, expect, "%l[cmpfail]")
tools/testing/selftests/rseq/rseq-riscv-bits.h
185
RSEQ_ASM_OP_CMPEQ(v, expect, "%l[error2]")
tools/testing/selftests/rseq/rseq-riscv-bits.h
188
RSEQ_ASM_OP_FINAL_STORE(newv, v, 3)
tools/testing/selftests/rseq/rseq-riscv-bits.h
195
[v] "m" (*v),
tools/testing/selftests/rseq/rseq-riscv-bits.h
22
RSEQ_ASM_OP_CMPEQ(v, expect, "%l[cmpfail]")
tools/testing/selftests/rseq/rseq-riscv-bits.h
26
RSEQ_ASM_OP_CMPEQ(v, expect, "%l[error2]")
tools/testing/selftests/rseq/rseq-riscv-bits.h
28
RSEQ_ASM_OP_FINAL_STORE(newv, v, 3)
tools/testing/selftests/rseq/rseq-riscv-bits.h
281
int RSEQ_TEMPLATE_IDENTIFIER(rseq_cmpeqv_trystorev_storev)(intptr_t *v, intptr_t expect,
tools/testing/selftests/rseq/rseq-riscv-bits.h
296
RSEQ_ASM_OP_CMPEQ(v, expect, "%l[cmpfail]")
tools/testing/selftests/rseq/rseq-riscv-bits.h
300
RSEQ_ASM_OP_CMPEQ(v, expect, "%l[error2]")
tools/testing/selftests/rseq/rseq-riscv-bits.h
305
RSEQ_ASM_OP_FINAL_STORE_RELEASE(newv, v, 3)
tools/testing/selftests/rseq/rseq-riscv-bits.h
307
RSEQ_ASM_OP_FINAL_STORE(newv, v, 3)
tools/testing/selftests/rseq/rseq-riscv-bits.h
316
[v] "m" (*v),
tools/testing/selftests/rseq/rseq-riscv-bits.h
344
int RSEQ_TEMPLATE_IDENTIFIER(rseq_cmpeqv_trymemcpy_storev)(intptr_t *v, intptr_t expect,
tools/testing/selftests/rseq/rseq-riscv-bits.h
35
[v] "m" (*v),
tools/testing/selftests/rseq/rseq-riscv-bits.h
358
RSEQ_ASM_OP_CMPEQ(v, expect, "%l[cmpfail]")
tools/testing/selftests/rseq/rseq-riscv-bits.h
362
RSEQ_ASM_OP_CMPEQ(v, expect, "%l[error2]")
tools/testing/selftests/rseq/rseq-riscv-bits.h
367
RSEQ_ASM_OP_FINAL_STORE_RELEASE(newv, v, 3)
tools/testing/selftests/rseq/rseq-riscv-bits.h
369
RSEQ_ASM_OP_FINAL_STORE(newv, v, 3)
tools/testing/selftests/rseq/rseq-riscv-bits.h
378
[v] "m" (*v),
tools/testing/selftests/rseq/rseq-riscv-bits.h
62
int RSEQ_TEMPLATE_IDENTIFIER(rseq_cmpnev_storeoffp_load)(intptr_t *v, intptr_t expectnot,
tools/testing/selftests/rseq/rseq-riscv-bits.h
76
RSEQ_ASM_OP_CMPNE(v, expectnot, "%l[cmpfail]")
tools/testing/selftests/rseq/rseq-riscv-bits.h
80
RSEQ_ASM_OP_CMPNE(v, expectnot, "%l[error2]")
tools/testing/selftests/rseq/rseq-riscv-bits.h
82
RSEQ_ASM_OP_R_LOAD(v)
tools/testing/selftests/rseq/rseq-riscv-bits.h
85
RSEQ_ASM_OP_R_FINAL_STORE(v, 3)
tools/testing/selftests/rseq/rseq-riscv-bits.h
9
int RSEQ_TEMPLATE_IDENTIFIER(rseq_cmpeqv_storev)(intptr_t *v, intptr_t expect, intptr_t newv, int cpu)
tools/testing/selftests/rseq/rseq-riscv-bits.h
92
[v] "m" (*v),
tools/testing/selftests/rseq/rseq-riscv.h
45
#define rseq_smp_store_release(p, v) \
tools/testing/selftests/rseq/rseq-riscv.h
48
RSEQ_WRITE_ONCE(*(p), v); \
tools/testing/selftests/rseq/rseq-s390-bits.h
115
[v] "m" (*v),
tools/testing/selftests/rseq/rseq-s390-bits.h
147
int RSEQ_TEMPLATE_IDENTIFIER(rseq_addv)(intptr_t *v, intptr_t count, int cpu)
tools/testing/selftests/rseq/rseq-s390-bits.h
175
[v] "m" (*v),
tools/testing/selftests/rseq/rseq-s390-bits.h
199
int RSEQ_TEMPLATE_IDENTIFIER(rseq_cmpeqv_cmpeqv_storev)(intptr_t *v, intptr_t expect,
tools/testing/selftests/rseq/rseq-s390-bits.h
243
[v] "m" (*v),
tools/testing/selftests/rseq/rseq-s390-bits.h
284
int RSEQ_TEMPLATE_IDENTIFIER(rseq_cmpeqv_trystorev_storev)(intptr_t *v, intptr_t expect,
tools/testing/selftests/rseq/rseq-s390-bits.h
325
[v] "m" (*v),
tools/testing/selftests/rseq/rseq-s390-bits.h
357
int RSEQ_TEMPLATE_IDENTIFIER(rseq_cmpeqv_trymemcpy_storev)(intptr_t *v, intptr_t expect,
tools/testing/selftests/rseq/rseq-s390-bits.h
41
[v] "m" (*v),
tools/testing/selftests/rseq/rseq-s390-bits.h
434
[v] "m" (*v),
tools/testing/selftests/rseq/rseq-s390-bits.h
76
int RSEQ_TEMPLATE_IDENTIFIER(rseq_cmpnev_storeoffp_load)(intptr_t *v, intptr_t expectnot,
tools/testing/selftests/rseq/rseq-s390-bits.h
9
int RSEQ_TEMPLATE_IDENTIFIER(rseq_cmpeqv_storev)(intptr_t *v, intptr_t expect, intptr_t newv, int cpu)
tools/testing/selftests/rseq/rseq-s390.h
25
#define rseq_smp_store_release(p, v) \
tools/testing/selftests/rseq/rseq-s390.h
28
RSEQ_WRITE_ONCE(*(p), v); \
tools/testing/selftests/rseq/rseq-x86-bits.h
119
[v] "m" (*v),
tools/testing/selftests/rseq/rseq-x86-bits.h
150
int RSEQ_TEMPLATE_IDENTIFIER(rseq_addv)(intptr_t *v, intptr_t count, int cpu)
tools/testing/selftests/rseq/rseq-x86-bits.h
16
int RSEQ_TEMPLATE_IDENTIFIER(rseq_cmpeqv_storev)(intptr_t *v, intptr_t expect, intptr_t newv, int cpu)
tools/testing/selftests/rseq/rseq-x86-bits.h
175
[v] "m" (*v),
tools/testing/selftests/rseq/rseq-x86-bits.h
255
int RSEQ_TEMPLATE_IDENTIFIER(rseq_cmpeqv_cmpeqv_storev)(intptr_t *v, intptr_t expect,
tools/testing/selftests/rseq/rseq-x86-bits.h
298
[v] "m" (*v),
tools/testing/selftests/rseq/rseq-x86-bits.h
337
int RSEQ_TEMPLATE_IDENTIFIER(rseq_cmpeqv_trystorev_storev)(intptr_t *v, intptr_t expect,
tools/testing/selftests/rseq/rseq-x86-bits.h
377
[v] "m" (*v),
tools/testing/selftests/rseq/rseq-x86-bits.h
407
int RSEQ_TEMPLATE_IDENTIFIER(rseq_cmpeqv_trymemcpy_storev)(intptr_t *v, intptr_t expect,
tools/testing/selftests/rseq/rseq-x86-bits.h
47
[v] "m" (*v),
tools/testing/selftests/rseq/rseq-x86-bits.h
483
[v] "m" (*v),
tools/testing/selftests/rseq/rseq-x86-bits.h
528
int RSEQ_TEMPLATE_IDENTIFIER(rseq_cmpeqv_storev)(intptr_t *v, intptr_t expect, intptr_t newv, int cpu)
tools/testing/selftests/rseq/rseq-x86-bits.h
559
[v] "m" (*v),
tools/testing/selftests/rseq/rseq-x86-bits.h
593
int RSEQ_TEMPLATE_IDENTIFIER(rseq_cmpnev_storeoffp_load)(intptr_t *v, intptr_t expectnot,
tools/testing/selftests/rseq/rseq-x86-bits.h
631
[v] "m" (*v),
tools/testing/selftests/rseq/rseq-x86-bits.h
662
int RSEQ_TEMPLATE_IDENTIFIER(rseq_addv)(intptr_t *v, intptr_t count, int cpu)
tools/testing/selftests/rseq/rseq-x86-bits.h
687
[v] "m" (*v),
tools/testing/selftests/rseq/rseq-x86-bits.h
710
int RSEQ_TEMPLATE_IDENTIFIER(rseq_cmpeqv_cmpeqv_storev)(intptr_t *v, intptr_t expect,
tools/testing/selftests/rseq/rseq-x86-bits.h
754
[v] "m" (*v),
tools/testing/selftests/rseq/rseq-x86-bits.h
793
int RSEQ_TEMPLATE_IDENTIFIER(rseq_cmpeqv_trystorev_storev)(intptr_t *v, intptr_t expect,
tools/testing/selftests/rseq/rseq-x86-bits.h
81
int RSEQ_TEMPLATE_IDENTIFIER(rseq_cmpnev_storeoffp_load)(intptr_t *v, intptr_t expectnot,
tools/testing/selftests/rseq/rseq-x86-bits.h
838
[v] "m" (*v),
tools/testing/selftests/rseq/rseq-x86-bits.h
870
int RSEQ_TEMPLATE_IDENTIFIER(rseq_cmpeqv_trymemcpy_storev)(intptr_t *v, intptr_t expect,
tools/testing/selftests/rseq/rseq-x86-bits.h
952
[v] "m" (*v),
tools/testing/selftests/rseq/rseq-x86.h
136
#define rseq_smp_store_release(p, v) \
tools/testing/selftests/rseq/rseq-x86.h
139
RSEQ_WRITE_ONCE(*p, v); \
tools/testing/selftests/rseq/rseq-x86.h
52
#define rseq_smp_store_release(p, v) \
tools/testing/selftests/rseq/rseq-x86.h
55
RSEQ_WRITE_ONCE(*(p), v); \
tools/testing/selftests/rseq/rseq.h
102
#define RSEQ_WRITE_ONCE(x, v) __extension__ ({ RSEQ_ACCESS_ONCE(x) = (v); })
tools/testing/selftests/rseq/rseq.h
249
intptr_t *v, intptr_t expect,
tools/testing/selftests/rseq/rseq.h
256
return rseq_cmpeqv_storev_relaxed_cpu_id(v, expect, newv, cpu);
tools/testing/selftests/rseq/rseq.h
258
return rseq_cmpeqv_storev_relaxed_mm_cid(v, expect, newv, cpu);
tools/testing/selftests/rseq/rseq.h
269
intptr_t *v, intptr_t expectnot, long voffp, intptr_t *load,
tools/testing/selftests/rseq/rseq.h
276
return rseq_cmpnev_storeoffp_load_relaxed_cpu_id(v, expectnot, voffp, load, cpu);
tools/testing/selftests/rseq/rseq.h
278
return rseq_cmpnev_storeoffp_load_relaxed_mm_cid(v, expectnot, voffp, load, cpu);
tools/testing/selftests/rseq/rseq.h
285
intptr_t *v, intptr_t count, int cpu)
tools/testing/selftests/rseq/rseq.h
291
return rseq_addv_relaxed_cpu_id(v, count, cpu);
tools/testing/selftests/rseq/rseq.h
293
return rseq_addv_relaxed_mm_cid(v, count, cpu);
tools/testing/selftests/rseq/rseq.h
321
intptr_t *v, intptr_t expect,
tools/testing/selftests/rseq/rseq.h
329
return rseq_cmpeqv_trystorev_storev_relaxed_cpu_id(v, expect, v2, newv2, newv, cpu);
tools/testing/selftests/rseq/rseq.h
331
return rseq_cmpeqv_trystorev_storev_relaxed_mm_cid(v, expect, v2, newv2, newv, cpu);
tools/testing/selftests/rseq/rseq.h
337
return rseq_cmpeqv_trystorev_storev_release_cpu_id(v, expect, v2, newv2, newv, cpu);
tools/testing/selftests/rseq/rseq.h
339
return rseq_cmpeqv_trystorev_storev_release_mm_cid(v, expect, v2, newv2, newv, cpu);
tools/testing/selftests/rseq/rseq.h
349
intptr_t *v, intptr_t expect,
tools/testing/selftests/rseq/rseq.h
357
return rseq_cmpeqv_cmpeqv_storev_relaxed_cpu_id(v, expect, v2, expect2, newv, cpu);
tools/testing/selftests/rseq/rseq.h
359
return rseq_cmpeqv_cmpeqv_storev_relaxed_mm_cid(v, expect, v2, expect2, newv, cpu);
tools/testing/selftests/rseq/rseq.h
366
intptr_t *v, intptr_t expect,
tools/testing/selftests/rseq/rseq.h
374
return rseq_cmpeqv_trymemcpy_storev_relaxed_cpu_id(v, expect, dst, src, len, newv, cpu);
tools/testing/selftests/rseq/rseq.h
376
return rseq_cmpeqv_trymemcpy_storev_relaxed_mm_cid(v, expect, dst, src, len, newv, cpu);
tools/testing/selftests/rseq/rseq.h
382
return rseq_cmpeqv_trymemcpy_storev_release_cpu_id(v, expect, dst, src, len, newv, cpu);
tools/testing/selftests/rseq/rseq.h
384
return rseq_cmpeqv_trymemcpy_storev_release_mm_cid(v, expect, dst, src, len, newv, cpu);
tools/testing/selftests/sched/cs_prctl_test.c
221
#define validate(v) _validate(__LINE__, v, #v)
tools/testing/selftests/watchdog/watchdog-test.c
29
const char v = 'V';
tools/testing/selftests/watchdog/watchdog-test.c
360
ret = write(fd, &v, 1);
tools/testing/selftests/watchdog/watchdog-test.c
70
int ret = write(fd, &v, 1);
tools/testing/shared/linux/rcupdate.h
10
#define RCU_INIT_POINTER(p, v) do { (p) = (v); } while (0)
tools/testing/vma/include/dup.h
85
typedef struct { unsigned long v; } freeptr_t;
tools/usb/usbip/libsrc/names.c
190
struct vendor *v;
tools/usb/usbip/libsrc/names.c
193
v = vendors[h];
tools/usb/usbip/libsrc/names.c
194
for (; v; v = v->next)
tools/usb/usbip/libsrc/names.c
195
if (v->vendorid == vendorid)
tools/usb/usbip/libsrc/names.c
197
v = my_malloc(sizeof(struct vendor) + strlen(name));
tools/usb/usbip/libsrc/names.c
198
if (!v)
tools/usb/usbip/libsrc/names.c
200
strcpy(v->name, name);
tools/usb/usbip/libsrc/names.c
201
v->vendorid = vendorid;
tools/usb/usbip/libsrc/names.c
202
v->next = vendors[h];
tools/usb/usbip/libsrc/names.c
203
vendors[h] = v;
tools/usb/usbip/libsrc/names.c
85
struct vendor *v;
tools/usb/usbip/libsrc/names.c
87
v = vendors[hashnum(vendorid)];
tools/usb/usbip/libsrc/names.c
88
for (; v; v = v->next)
tools/usb/usbip/libsrc/names.c
89
if (v->vendorid == vendorid)
tools/usb/usbip/libsrc/names.c
90
return v->name;
tools/virtio/linux/dma-mapping.h
39
#define dma_need_sync(v, a) (0)
tools/virtio/ringtest/main.c
36
unsigned long long v = 1;
tools/virtio/ringtest/main.c
40
r = write(fd, &v, sizeof v);
tools/virtio/ringtest/main.c
41
assert(r == sizeof v);
tools/virtio/ringtest/main.c
47
unsigned long long v = 1;
tools/virtio/ringtest/main.c
51
r = read(fd, &v, sizeof v);
tools/virtio/ringtest/main.c
52
assert(r == sizeof v);
tools/virtio/vhost_net_test.c
141
unsigned long long v = 1;
tools/virtio/vhost_net_test.c
144
r = write(info->kick, &v, sizeof(v));
tools/virtio/vhost_net_test.c
145
assert(r == sizeof(v));
tools/virtio/virtio_test.c
56
unsigned long long v = 1;
tools/virtio/virtio_test.c
58
r = write(info->kick, &v, sizeof v);
tools/virtio/virtio_test.c
59
assert(r == sizeof v);
